]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tg3: Add AC131 power down support
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
daf09de8
MC		 71#define DRV_MODULE_VERSION "3.102"
72#define DRV_MODULE_RELDATE "September 1, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
943 val = MAC_PHYCFG2_50610_LED_MODES;
944 break;
945 case TG3_PHY_ID_BCMAC131:
946 val = MAC_PHYCFG2_AC131_LED_MODES;
947 break;
948 case TG3_PHY_ID_RTL8211C:
949 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
950 break;
951 case TG3_PHY_ID_RTL8201E:
952 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
953 break;
954 default:
a9daf367 955 return;
fcb389df
MC		 956 }
957
958 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
959 tw32(MAC_PHYCFG2, val);
960
961 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 962 val &= ~(MAC_PHYCFG1_RGMII_INT |
963 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
964 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 965 tw32(MAC_PHYCFG1, val);
966
967 return;
968 }
969
970 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
971 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
972 MAC_PHYCFG2_FMODE_MASK_MASK |
973 MAC_PHYCFG2_GMODE_MASK_MASK |
974 MAC_PHYCFG2_ACT_MASK_MASK |
975 MAC_PHYCFG2_QUAL_MASK_MASK |
976 MAC_PHYCFG2_INBAND_ENABLE;
977
978 tw32(MAC_PHYCFG2, val);
a9daf367 979
bb85fbb6
MC		 980 val = tr32(MAC_PHYCFG1);
981 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
982 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
983 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 984 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
985 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
986 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
987 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
988 }
bb85fbb6
MC		 989 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
990 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
991 tw32(MAC_PHYCFG1, val);
a9daf367 992
a9daf367
MC		 993 val = tr32(MAC_EXT_RGMII_MODE);
994 val &= ~(MAC_RGMII_MODE_RX_INT_B |
995 MAC_RGMII_MODE_RX_QUALITY |
996 MAC_RGMII_MODE_RX_ACTIVITY |
997 MAC_RGMII_MODE_RX_ENG_DET |
998 MAC_RGMII_MODE_TX_ENABLE |
999 MAC_RGMII_MODE_TX_LOWPWR |
1000 MAC_RGMII_MODE_TX_RESET);
fcb389df 1001 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1003 val |= MAC_RGMII_MODE_RX_INT_B |
1004 MAC_RGMII_MODE_RX_QUALITY |
1005 MAC_RGMII_MODE_RX_ACTIVITY |
1006 MAC_RGMII_MODE_RX_ENG_DET;
1007 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008 val |= MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET;
1011 }
1012 tw32(MAC_EXT_RGMII_MODE, val);
1013}
1014
158d7abd
MC		 1015static void tg3_mdio_start(struct tg3 *tp)
1016{
158d7abd
MC		 1017 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018 tw32_f(MAC_MI_MODE, tp->mi_mode);
1019 udelay(80);
a9daf367 1020
882e9793
MC		 1021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1022 u32 funcnum, is_serdes;
1023
1024 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1025 if (funcnum)
1026 tp->phy_addr = 2;
1027 else
1028 tp->phy_addr = 1;
1029
1030 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1031 if (is_serdes)
1032 tp->phy_addr += 7;
1033 } else
3f0e3ad7 1034 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1035
9c61d6bc
MC		 1036 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038 tg3_mdio_config_5785(tp);
158d7abd
MC		 1039}
1040
158d7abd
MC		 1041static int tg3_mdio_init(struct tg3 *tp)
1042{
1043 int i;
1044 u32 reg;
a9daf367 1045 struct phy_device *phydev;
158d7abd
MC		 1046
1047 tg3_mdio_start(tp);
1048
1049 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1050 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1051 return 0;
1052
298cf9be
LB		 1053 tp->mdio_bus = mdiobus_alloc();
1054 if (tp->mdio_bus == NULL)
1055 return -ENOMEM;
158d7abd 1056
298cf9be
LB		 1057 tp->mdio_bus->name = "tg3 mdio bus";
1058 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1059 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1060 tp->mdio_bus->priv = tp;
1061 tp->mdio_bus->parent = &tp->pdev->dev;
1062 tp->mdio_bus->read = &tg3_mdio_read;
1063 tp->mdio_bus->write = &tg3_mdio_write;
1064 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1065 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1066 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1067
1068 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1069 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1070
1071 /* The bus registration will look for all the PHYs on the mdio bus.
1072 * Unfortunately, it does not ensure the PHY is powered up before
1073 * accessing the PHY ID registers. A chip reset is the
1074 * quickest way to bring the device back to an operational state..
1075 */
1076 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1077 tg3_bmcr_reset(tp);
1078
298cf9be 1079 i = mdiobus_register(tp->mdio_bus);
a9daf367 1080 if (i) {
158d7abd
MC		 1081 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1082 tp->dev->name, i);
9c61d6bc 1083 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1084 return i;
1085 }
158d7abd 1086
3f0e3ad7 1087 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1088
9c61d6bc
MC		 1089 if (!phydev || !phydev->drv) {
1090 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1091 mdiobus_unregister(tp->mdio_bus);
1092 mdiobus_free(tp->mdio_bus);
1093 return -ENODEV;
1094 }
1095
1096 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1097 case TG3_PHY_ID_BCM57780:
1098 phydev->interface = PHY_INTERFACE_MODE_GMII;
1099 break;
a9daf367 1100 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1101 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1102 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1103 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1104 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1105 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1106 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1107 /* fallthru */
1108 case TG3_PHY_ID_RTL8211C:
1109 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1110 break;
fcb389df 1111 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1112 case TG3_PHY_ID_BCMAC131:
1113 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1114 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1115 break;
1116 }
1117
9c61d6bc
MC		 1118 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1119
1120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1121 tg3_mdio_config_5785(tp);
a9daf367
MC		 1122
1123 return 0;
158d7abd
MC		 1124}
1125
1126static void tg3_mdio_fini(struct tg3 *tp)
1127{
1128 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1129 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1130 mdiobus_unregister(tp->mdio_bus);
1131 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1132 }
1133}
1134
4ba526ce
MC		 1135/* tp->lock is held. */
1136static inline void tg3_generate_fw_event(struct tg3 *tp)
1137{
1138 u32 val;
1139
1140 val = tr32(GRC_RX_CPU_EVENT);
1141 val |= GRC_RX_CPU_DRIVER_EVENT;
1142 tw32_f(GRC_RX_CPU_EVENT, val);
1143
1144 tp->last_event_jiffies = jiffies;
1145}
1146
1147#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1148
95e2869a
MC		 1149/* tp->lock is held. */
1150static void tg3_wait_for_event_ack(struct tg3 *tp)
1151{
1152 int i;
4ba526ce
MC		 1153 unsigned int delay_cnt;
1154 long time_remain;
1155
1156 /* If enough time has passed, no wait is necessary. */
1157 time_remain = (long)(tp->last_event_jiffies + 1 +
1158 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1159 (long)jiffies;
1160 if (time_remain < 0)
1161 return;
1162
1163 /* Check if we can shorten the wait time. */
1164 delay_cnt = jiffies_to_usecs(time_remain);
1165 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1166 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1167 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1168
4ba526ce 1169 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1170 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1171 break;
4ba526ce 1172 udelay(8);
95e2869a
MC		 1173 }
1174}
1175
1176/* tp->lock is held. */
1177static void tg3_ump_link_report(struct tg3 *tp)
1178{
1179 u32 reg;
1180 u32 val;
1181
1182 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1183 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1184 return;
1185
1186 tg3_wait_for_event_ack(tp);
1187
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1189
1190 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1191
1192 val = 0;
1193 if (!tg3_readphy(tp, MII_BMCR, &reg))
1194 val = reg << 16;
1195 if (!tg3_readphy(tp, MII_BMSR, &reg))
1196 val |= (reg & 0xffff);
1197 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1198
1199 val = 0;
1200 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1201 val = reg << 16;
1202 if (!tg3_readphy(tp, MII_LPA, &reg))
1203 val |= (reg & 0xffff);
1204 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1205
1206 val = 0;
1207 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1208 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1211 val |= (reg & 0xffff);
1212 }
1213 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1214
1215 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1216 val = reg << 16;
1217 else
1218 val = 0;
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1220
4ba526ce 1221 tg3_generate_fw_event(tp);
95e2869a
MC		 1222}
1223
1224static void tg3_link_report(struct tg3 *tp)
1225{
1226 if (!netif_carrier_ok(tp->dev)) {
1227 if (netif_msg_link(tp))
1228 printk(KERN_INFO PFX "%s: Link is down.\n",
1229 tp->dev->name);
1230 tg3_ump_link_report(tp);
1231 } else if (netif_msg_link(tp)) {
1232 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1233 tp->dev->name,
1234 (tp->link_config.active_speed == SPEED_1000 ?
1235 1000 :
1236 (tp->link_config.active_speed == SPEED_100 ?
1237 100 : 10)),
1238 (tp->link_config.active_duplex == DUPLEX_FULL ?
1239 "full" : "half"));
1240
1241 printk(KERN_INFO PFX
1242 "%s: Flow control is %s for TX and %s for RX.\n",
1243 tp->dev->name,
e18ce346 1244 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1245 "on" : "off",
e18ce346 1246 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1247 "on" : "off");
1248 tg3_ump_link_report(tp);
1249 }
1250}
1251
1252static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1253{
1254 u16 miireg;
1255
e18ce346 1256 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1257 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1258 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1259 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1260 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1261 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1262 else
1263 miireg = 0;
1264
1265 return miireg;
1266}
1267
1268static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1269{
1270 u16 miireg;
1271
e18ce346 1272 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1273 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1274 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1275 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1276 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1277 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1278 else
1279 miireg = 0;
1280
1281 return miireg;
1282}
1283
95e2869a
MC		 1284static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1285{
1286 u8 cap = 0;
1287
1288 if (lcladv & ADVERTISE_1000XPAUSE) {
1289 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1290 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1291 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1292 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1293 cap = FLOW_CTRL_RX;
95e2869a
MC		 1294 } else {
1295 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1296 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1297 }
1298 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1299 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1300 cap = FLOW_CTRL_TX;
95e2869a
MC		 1301 }
1302
1303 return cap;
1304}
1305
f51f3562 1306static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1307{
b02fd9e3 1308 u8 autoneg;
f51f3562 1309 u8 flowctrl = 0;
95e2869a
MC		 1310 u32 old_rx_mode = tp->rx_mode;
1311 u32 old_tx_mode = tp->tx_mode;
1312
b02fd9e3 1313 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1314 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1315 else
1316 autoneg = tp->link_config.autoneg;
1317
1318 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1319 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1320 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1321 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1322 else
bc02ff95 1323 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1324 } else
1325 flowctrl = tp->link_config.flowctrl;
95e2869a 1326
f51f3562 1327 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1328
e18ce346 1329 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1330 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1331 else
1332 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1333
f51f3562 1334 if (old_rx_mode != tp->rx_mode)
95e2869a 1335 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1336
e18ce346 1337 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1338 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1341
f51f3562 1342 if (old_tx_mode != tp->tx_mode)
95e2869a 1343 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1344}
1345
b02fd9e3
MC		 1346static void tg3_adjust_link(struct net_device *dev)
1347{
1348 u8 oldflowctrl, linkmesg = 0;
1349 u32 mac_mode, lcl_adv, rmt_adv;
1350 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1351 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1352
24bb4fb6 1353 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1354
1355 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1356 MAC_MODE_HALF_DUPLEX);
1357
1358 oldflowctrl = tp->link_config.active_flowctrl;
1359
1360 if (phydev->link) {
1361 lcl_adv = 0;
1362 rmt_adv = 0;
1363
1364 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1365 mac_mode |= MAC_MODE_PORT_MODE_MII;
1366 else
1367 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1368
1369 if (phydev->duplex == DUPLEX_HALF)
1370 mac_mode |= MAC_MODE_HALF_DUPLEX;
1371 else {
1372 lcl_adv = tg3_advert_flowctrl_1000T(
1373 tp->link_config.flowctrl);
1374
1375 if (phydev->pause)
1376 rmt_adv = LPA_PAUSE_CAP;
1377 if (phydev->asym_pause)
1378 rmt_adv |= LPA_PAUSE_ASYM;
1379 }
1380
1381 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1382 } else
1383 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1384
1385 if (mac_mode != tp->mac_mode) {
1386 tp->mac_mode = mac_mode;
1387 tw32_f(MAC_MODE, tp->mac_mode);
1388 udelay(40);
1389 }
1390
fcb389df
MC		 1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1392 if (phydev->speed == SPEED_10)
1393 tw32(MAC_MI_STAT,
1394 MAC_MI_STAT_10MBPS_MODE |
1395 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1396 else
1397 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1398 }
1399
b02fd9e3
MC		 1400 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1401 tw32(MAC_TX_LENGTHS,
1402 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403 (6 << TX_LENGTHS_IPG_SHIFT) |
1404 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405 else
1406 tw32(MAC_TX_LENGTHS,
1407 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1408 (6 << TX_LENGTHS_IPG_SHIFT) |
1409 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1410
1411 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1412 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1413 phydev->speed != tp->link_config.active_speed ||
1414 phydev->duplex != tp->link_config.active_duplex ||
1415 oldflowctrl != tp->link_config.active_flowctrl)
1416 linkmesg = 1;
1417
1418 tp->link_config.active_speed = phydev->speed;
1419 tp->link_config.active_duplex = phydev->duplex;
1420
24bb4fb6 1421 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1422
1423 if (linkmesg)
1424 tg3_link_report(tp);
1425}
1426
1427static int tg3_phy_init(struct tg3 *tp)
1428{
1429 struct phy_device *phydev;
1430
1431 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1432 return 0;
1433
1434 /* Bring the PHY back to a known state. */
1435 tg3_bmcr_reset(tp);
1436
3f0e3ad7 1437 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1438
1439 /* Attach the MAC to the PHY. */
fb28ad35 1440 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1441 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1442 if (IS_ERR(phydev)) {
1443 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1444 return PTR_ERR(phydev);
1445 }
1446
b02fd9e3 1447 /* Mask with MAC supported features. */
9c61d6bc
MC		 1448 switch (phydev->interface) {
1449 case PHY_INTERFACE_MODE_GMII:
1450 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1451 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1452 phydev->supported &= (PHY_GBIT_FEATURES |
1453 SUPPORTED_Pause |
1454 SUPPORTED_Asym_Pause);
1455 break;
1456 }
1457 /* fallthru */
9c61d6bc
MC		 1458 case PHY_INTERFACE_MODE_MII:
1459 phydev->supported &= (PHY_BASIC_FEATURES |
1460 SUPPORTED_Pause |
1461 SUPPORTED_Asym_Pause);
1462 break;
1463 default:
3f0e3ad7 1464 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1465 return -EINVAL;
1466 }
1467
1468 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1469
1470 phydev->advertising = phydev->supported;
1471
b02fd9e3
MC		 1472 return 0;
1473}
1474
1475static void tg3_phy_start(struct tg3 *tp)
1476{
1477 struct phy_device *phydev;
1478
1479 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1480 return;
1481
3f0e3ad7 1482 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1483
1484 if (tp->link_config.phy_is_low_power) {
1485 tp->link_config.phy_is_low_power = 0;
1486 phydev->speed = tp->link_config.orig_speed;
1487 phydev->duplex = tp->link_config.orig_duplex;
1488 phydev->autoneg = tp->link_config.orig_autoneg;
1489 phydev->advertising = tp->link_config.orig_advertising;
1490 }
1491
1492 phy_start(phydev);
1493
1494 phy_start_aneg(phydev);
1495}
1496
1497static void tg3_phy_stop(struct tg3 *tp)
1498{
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1503}
1504
1505static void tg3_phy_fini(struct tg3 *tp)
1506{
1507 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1508 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1509 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1510 }
1511}
1512
b2a5c19c
MC		 1513static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1514{
1515 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1516 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1517}
1518
7f97a4bd
MC		 1519static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1520{
1521 u32 phytest;
1522
1523 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1524 u32 phy;
1525
1526 tg3_writephy(tp, MII_TG3_FET_TEST,
1527 phytest | MII_TG3_FET_SHADOW_EN);
1528 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1531 else
1532 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1533 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1534 }
1535 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1536 }
1537}
1538
6833c043
MC		 1539static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 reg;
1542
7f97a4bd 1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1544 return;
1545
7f97a4bd
MC		 1546 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1547 tg3_phy_fet_toggle_apd(tp, enable);
1548 return;
1549 }
1550
6833c043
MC		 1551 reg = MII_TG3_MISC_SHDW_WREN |
1552 MII_TG3_MISC_SHDW_SCR5_SEL |
1553 MII_TG3_MISC_SHDW_SCR5_LPED |
1554 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1555 MII_TG3_MISC_SHDW_SCR5_SDTL |
1556 MII_TG3_MISC_SHDW_SCR5_C125OE;
1557 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1558 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1559
1560 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1561
1562
1563 reg = MII_TG3_MISC_SHDW_WREN |
1564 MII_TG3_MISC_SHDW_APD_SEL |
1565 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1566 if (enable)
1567 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1568
1569 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1570}
1571
9ef8ca99
MC		 1572static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1573{
1574 u32 phy;
1575
1576 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1577 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1578 return;
1579
7f97a4bd 1580 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1581 u32 ephy;
1582
535ef6e1
MC		 1583 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1584 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1585
1586 tg3_writephy(tp, MII_TG3_FET_TEST,
1587 ephy | MII_TG3_FET_SHADOW_EN);
1588 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1589 if (enable)
535ef6e1 1590 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1591 else
535ef6e1
MC		 1592 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1593 tg3_writephy(tp, reg, phy);
9ef8ca99 1594 }
535ef6e1 1595 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1596 }
1597 } else {
1598 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1599 MII_TG3_AUXCTL_SHDWSEL_MISC;
1600 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1601 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1602 if (enable)
1603 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1604 else
1605 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1606 phy |= MII_TG3_AUXCTL_MISC_WREN;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608 }
1609 }
1610}
1611
1da177e4
LT		 1612static void tg3_phy_set_wirespeed(struct tg3 *tp)
1613{
1614 u32 val;
1615
1616 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1617 return;
1618
1619 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1620 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1621 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1622 (val | (1 << 15) | (1 << 4)));
1623}
1624
b2a5c19c
MC		 1625static void tg3_phy_apply_otp(struct tg3 *tp)
1626{
1627 u32 otp, phy;
1628
1629 if (!tp->phy_otp)
1630 return;
1631
1632 otp = tp->phy_otp;
1633
1634 /* Enable SM_DSP clock and tx 6dB coding. */
1635 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1636 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1637 MII_TG3_AUXCTL_ACTL_TX_6DB;
1638 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1639
1640 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1641 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1642 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1643
1644 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1645 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1646 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1647
1648 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1649 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1650 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1651
1652 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1653 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1654
1655 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1656 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1657
1658 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1659 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1660 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1661
1662 /* Turn off SM_DSP clock. */
1663 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1664 MII_TG3_AUXCTL_ACTL_TX_6DB;
1665 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1666}
1667
1da177e4
LT		 1668static int tg3_wait_macro_done(struct tg3 *tp)
1669{
1670 int limit = 100;
1671
1672 while (limit--) {
1673 u32 tmp32;
1674
1675 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1676 if ((tmp32 & 0x1000) == 0)
1677 break;
1678 }
1679 }
d4675b52 1680 if (limit < 0)
1da177e4
LT		 1681 return -EBUSY;
1682
1683 return 0;
1684}
1685
1686static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1687{
1688 static const u32 test_pat[4][6] = {
1689 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1690 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1691 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1692 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1693 };
1694 int chan;
1695
1696 for (chan = 0; chan < 4; chan++) {
1697 int i;
1698
1699 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1700 (chan * 0x2000) | 0x0200);
1701 tg3_writephy(tp, 0x16, 0x0002);
1702
1703 for (i = 0; i < 6; i++)
1704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1705 test_pat[chan][i]);
1706
1707 tg3_writephy(tp, 0x16, 0x0202);
1708 if (tg3_wait_macro_done(tp)) {
1709 *resetp = 1;
1710 return -EBUSY;
1711 }
1712
1713 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1714 (chan * 0x2000) | 0x0200);
1715 tg3_writephy(tp, 0x16, 0x0082);
1716 if (tg3_wait_macro_done(tp)) {
1717 *resetp = 1;
1718 return -EBUSY;
1719 }
1720
1721 tg3_writephy(tp, 0x16, 0x0802);
1722 if (tg3_wait_macro_done(tp)) {
1723 *resetp = 1;
1724 return -EBUSY;
1725 }
1726
1727 for (i = 0; i < 6; i += 2) {
1728 u32 low, high;
1729
1730 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1731 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1732 tg3_wait_macro_done(tp)) {
1733 *resetp = 1;
1734 return -EBUSY;
1735 }
1736 low &= 0x7fff;
1737 high &= 0x000f;
1738 if (low != test_pat[chan][i] ||
1739 high != test_pat[chan][i+1]) {
1740 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1741 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1743
1744 return -EBUSY;
1745 }
1746 }
1747 }
1748
1749 return 0;
1750}
1751
1752static int tg3_phy_reset_chanpat(struct tg3 *tp)
1753{
1754 int chan;
1755
1756 for (chan = 0; chan < 4; chan++) {
1757 int i;
1758
1759 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1760 (chan * 0x2000) | 0x0200);
1761 tg3_writephy(tp, 0x16, 0x0002);
1762 for (i = 0; i < 6; i++)
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1764 tg3_writephy(tp, 0x16, 0x0202);
1765 if (tg3_wait_macro_done(tp))
1766 return -EBUSY;
1767 }
1768
1769 return 0;
1770}
1771
1772static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1773{
1774 u32 reg32, phy9_orig;
1775 int retries, do_phy_reset, err;
1776
1777 retries = 10;
1778 do_phy_reset = 1;
1779 do {
1780 if (do_phy_reset) {
1781 err = tg3_bmcr_reset(tp);
1782 if (err)
1783 return err;
1784 do_phy_reset = 0;
1785 }
1786
1787 /* Disable transmitter and interrupt. */
1788 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1789 continue;
1790
1791 reg32 |= 0x3000;
1792 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1793
1794 /* Set full-duplex, 1000 mbps. */
1795 tg3_writephy(tp, MII_BMCR,
1796 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1797
1798 /* Set to master mode. */
1799 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1800 continue;
1801
1802 tg3_writephy(tp, MII_TG3_CTRL,
1803 (MII_TG3_CTRL_AS_MASTER |
1804 MII_TG3_CTRL_ENABLE_AS_MASTER));
1805
1806 /* Enable SM_DSP_CLOCK and 6dB. */
1807 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1808
1809 /* Block the PHY control access. */
1810 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1811 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1812
1813 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1814 if (!err)
1815 break;
1816 } while (--retries);
1817
1818 err = tg3_phy_reset_chanpat(tp);
1819 if (err)
1820 return err;
1821
1822 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1823 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1824
1825 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1826 tg3_writephy(tp, 0x16, 0x0000);
1827
1828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1830 /* Set Extended packet length bit for jumbo frames */
1831 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1832 }
1833 else {
1834 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1835 }
1836
1837 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1838
1839 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1840 reg32 &= ~0x3000;
1841 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1842 } else if (!err)
1843 err = -EBUSY;
1844
1845 return err;
1846}
1847
1848/* This will reset the tigon3 PHY if there is no valid
1849 * link unless the FORCE argument is non-zero.
1850 */
1851static int tg3_phy_reset(struct tg3 *tp)
1852{
b2a5c19c 1853 u32 cpmuctrl;
1da177e4
LT		 1854 u32 phy_status;
1855 int err;
1856
60189ddf
MC		 1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1858 u32 val;
1859
1860 val = tr32(GRC_MISC_CFG);
1861 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1862 udelay(40);
1863 }
1da177e4
LT		 1864 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1865 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1866 if (err != 0)
1867 return -EBUSY;
1868
c8e1e82b
MC		 1869 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1870 netif_carrier_off(tp->dev);
1871 tg3_link_report(tp);
1872 }
1873
1da177e4
LT		 1874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1877 err = tg3_phy_reset_5703_4_5(tp);
1878 if (err)
1879 return err;
1880 goto out;
1881 }
1882
b2a5c19c
MC		 1883 cpmuctrl = 0;
1884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1885 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1886 cpmuctrl = tr32(TG3_CPMU_CTRL);
1887 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1888 tw32(TG3_CPMU_CTRL,
1889 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1890 }
1891
1da177e4
LT		 1892 err = tg3_bmcr_reset(tp);
1893 if (err)
1894 return err;
1895
b2a5c19c
MC		 1896 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1897 u32 phy;
1898
1899 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1900 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1901
1902 tw32(TG3_CPMU_CTRL, cpmuctrl);
1903 }
1904
bcb37f6c
MC		 1905 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1906 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1907 u32 val;
1908
1909 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1910 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1911 CPMU_LSPD_1000MB_MACCLK_12_5) {
1912 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1913 udelay(40);
1914 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1915 }
1916 }
1917
b2a5c19c
MC		 1918 tg3_phy_apply_otp(tp);
1919
6833c043
MC		 1920 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1921 tg3_phy_toggle_apd(tp, true);
1922 else
1923 tg3_phy_toggle_apd(tp, false);
1924
1da177e4
LT		 1925out:
1926 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1927 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1929 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1930 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1931 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1933 }
1934 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1935 tg3_writephy(tp, 0x1c, 0x8d68);
1936 tg3_writephy(tp, 0x1c, 0x8d68);
1937 }
1938 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1940 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1941 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1942 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1943 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1944 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1945 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1946 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1947 }
c424cb24
MC		 1948 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1951 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1953 tg3_writephy(tp, MII_TG3_TEST1,
1954 MII_TG3_TEST1_TRIM_EN | 0x4);
1955 } else
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
1da177e4
LT		 1959 /* Set Extended packet length bit (bit 14) on all chips that */
1960 /* support jumbo frames */
1961 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1962 /* Cannot do read-modify-write on 5401 */
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1964 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1965 u32 phy_reg;
1966
1967 /* Set bit 14 with read-modify-write to preserve other bits */
1968 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1969 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1971 }
1972
1973 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1974 * jumbo frames transmission.
1975 */
8f666b07 1976 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1977 u32 phy_reg;
1978
1979 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1980 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1981 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1982 }
1983
715116a1 1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1985 /* adjust output voltage */
535ef6e1 1986 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1987 }
1988
9ef8ca99 1989 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1990 tg3_phy_set_wirespeed(tp);
1991 return 0;
1992}
1993
1994static void tg3_frob_aux_power(struct tg3 *tp)
1995{
1996 struct tg3 *tp_peer = tp;
1997
9d26e213 1998 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1999 return;
2000
f6eb9b1f
MC		 2001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2004 struct net_device *dev_peer;
2005
2006 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2007 /* remove_one() may have been run on the peer. */
8c2dc7e1 2008 if (!dev_peer)
bc1c7567
MC		 2009 tp_peer = tp;
2010 else
2011 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2012 }
2013
1da177e4 2014 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2015 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2016 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2017 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2020 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2021 (GRC_LCLCTRL_GPIO_OE0 |
2022 GRC_LCLCTRL_GPIO_OE1 |
2023 GRC_LCLCTRL_GPIO_OE2 |
2024 GRC_LCLCTRL_GPIO_OUTPUT0 |
2025 GRC_LCLCTRL_GPIO_OUTPUT1),
2026 100);
8d519ab2
MC		 2027 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2029 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2030 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2031 GRC_LCLCTRL_GPIO_OE1 |
2032 GRC_LCLCTRL_GPIO_OE2 |
2033 GRC_LCLCTRL_GPIO_OUTPUT0 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 tp->grc_local_ctrl;
2036 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037
2038 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2039 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2040
2041 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2042 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2043 } else {
2044 u32 no_gpio2;
dc56b7d4 2045 u32 grc_local_ctrl = 0;
1da177e4
LT		 2046
2047 if (tp_peer != tp &&
2048 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2049 return;
2050
dc56b7d4
MC		 2051 /* Workaround to prevent overdrawing Amps. */
2052 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2053 ASIC_REV_5714) {
2054 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056 grc_local_ctrl, 100);
dc56b7d4
MC		 2057 }
2058
1da177e4
LT		 2059 /* On 5753 and variants, GPIO2 cannot be used. */
2060 no_gpio2 = tp->nic_sram_data_cfg &
2061 NIC_SRAM_DATA_CFG_NO_GPIO2;
2062
dc56b7d4 2063 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2064 GRC_LCLCTRL_GPIO_OE1 |
2065 GRC_LCLCTRL_GPIO_OE2 |
2066 GRC_LCLCTRL_GPIO_OUTPUT1 |
2067 GRC_LCLCTRL_GPIO_OUTPUT2;
2068 if (no_gpio2) {
2069 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2070 GRC_LCLCTRL_GPIO_OUTPUT2);
2071 }
b401e9e2
MC		 2072 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073 grc_local_ctrl, 100);
1da177e4
LT		 2074
2075 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2076
b401e9e2
MC		 2077 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078 grc_local_ctrl, 100);
1da177e4
LT		 2079
2080 if (!no_gpio2) {
2081 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083 grc_local_ctrl, 100);
1da177e4
LT		 2084 }
2085 }
2086 } else {
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2088 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2089 if (tp_peer != tp &&
2090 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2091 return;
2092
b401e9e2
MC		 2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 (GRC_LCLCTRL_GPIO_OE1 |
2095 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2096
b401e9e2
MC		 2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2099
b401e9e2
MC		 2100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101 (GRC_LCLCTRL_GPIO_OE1 |
2102 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2103 }
2104 }
2105}
2106
e8f3f6ca
MC		 2107static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2108{
2109 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2110 return 1;
2111 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2112 if (speed != SPEED_10)
2113 return 1;
2114 } else if (speed == SPEED_10)
2115 return 1;
2116
2117 return 0;
2118}
2119
1da177e4
LT		 2120static int tg3_setup_phy(struct tg3 *, int);
2121
2122#define RESET_KIND_SHUTDOWN 0
2123#define RESET_KIND_INIT 1
2124#define RESET_KIND_SUSPEND 2
2125
2126static void tg3_write_sig_post_reset(struct tg3 *, int);
2127static int tg3_halt_cpu(struct tg3 *, u32);
2128
0a459aac 2129static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2130{
ce057f01
MC		 2131 u32 val;
2132
5129724a
MC		 2133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2135 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2136 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2137
2138 sg_dig_ctrl |=
2139 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2140 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2141 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2142 }
3f7045c1 2143 return;
5129724a 2144 }
3f7045c1 2145
60189ddf 2146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2147 tg3_bmcr_reset(tp);
2148 val = tr32(GRC_MISC_CFG);
2149 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2150 udelay(40);
2151 return;
0e5f784c
MC		 2152 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2153 u32 phytest;
2154 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2155 u32 phy;
2156
2157 tg3_writephy(tp, MII_ADVERTISE, 0);
2158 tg3_writephy(tp, MII_BMCR,
2159 BMCR_ANENABLE | BMCR_ANRESTART);
2160
2161 tg3_writephy(tp, MII_TG3_FET_TEST,
2162 phytest | MII_TG3_FET_SHADOW_EN);
2163 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2164 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2165 tg3_writephy(tp,
2166 MII_TG3_FET_SHDW_AUXMODE4,
2167 phy);
2168 }
2169 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2170 }
2171 return;
0a459aac 2172 } else if (do_low_power) {
715116a1
MC		 2173 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2174 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2175
2176 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2177 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2178 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2179 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2180 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2181 }
3f7045c1 2182
15c3b696
MC		 2183 /* The PHY should not be powered down on some chips because
2184 * of bugs.
2185 */
2186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2187 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2188 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2189 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2190 return;
ce057f01 2191
bcb37f6c
MC		 2192 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2193 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2194 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2195 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2196 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2197 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2198 }
2199
15c3b696
MC		 2200 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2201}
2202
ffbcfed4
MC		 2203/* tp->lock is held. */
2204static int tg3_nvram_lock(struct tg3 *tp)
2205{
2206 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2207 int i;
2208
2209 if (tp->nvram_lock_cnt == 0) {
2210 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2211 for (i = 0; i < 8000; i++) {
2212 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2213 break;
2214 udelay(20);
2215 }
2216 if (i == 8000) {
2217 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2218 return -ENODEV;
2219 }
2220 }
2221 tp->nvram_lock_cnt++;
2222 }
2223 return 0;
2224}
2225
2226/* tp->lock is held. */
2227static void tg3_nvram_unlock(struct tg3 *tp)
2228{
2229 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2230 if (tp->nvram_lock_cnt > 0)
2231 tp->nvram_lock_cnt--;
2232 if (tp->nvram_lock_cnt == 0)
2233 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2234 }
2235}
2236
2237/* tp->lock is held. */
2238static void tg3_enable_nvram_access(struct tg3 *tp)
2239{
2240 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2241 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2242 u32 nvaccess = tr32(NVRAM_ACCESS);
2243
2244 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2245 }
2246}
2247
2248/* tp->lock is held. */
2249static void tg3_disable_nvram_access(struct tg3 *tp)
2250{
2251 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2253 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2256 }
2257}
2258
2259static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2260 u32 offset, u32 *val)
2261{
2262 u32 tmp;
2263 int i;
2264
2265 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2266 return -EINVAL;
2267
2268 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2269 EEPROM_ADDR_DEVID_MASK |
2270 EEPROM_ADDR_READ);
2271 tw32(GRC_EEPROM_ADDR,
2272 tmp |
2273 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2274 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2275 EEPROM_ADDR_ADDR_MASK) |
2276 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2277
2278 for (i = 0; i < 1000; i++) {
2279 tmp = tr32(GRC_EEPROM_ADDR);
2280
2281 if (tmp & EEPROM_ADDR_COMPLETE)
2282 break;
2283 msleep(1);
2284 }
2285 if (!(tmp & EEPROM_ADDR_COMPLETE))
2286 return -EBUSY;
2287
62cedd11
MC		 2288 tmp = tr32(GRC_EEPROM_DATA);
2289
2290 /*
2291 * The data will always be opposite the native endian
2292 * format. Perform a blind byteswap to compensate.
2293 */
2294 *val = swab32(tmp);
2295
ffbcfed4
MC		 2296 return 0;
2297}
2298
2299#define NVRAM_CMD_TIMEOUT 10000
2300
2301static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2302{
2303 int i;
2304
2305 tw32(NVRAM_CMD, nvram_cmd);
2306 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2307 udelay(10);
2308 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2309 udelay(10);
2310 break;
2311 }
2312 }
2313
2314 if (i == NVRAM_CMD_TIMEOUT)
2315 return -EBUSY;
2316
2317 return 0;
2318}
2319
2320static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2321{
2322 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2323 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2324 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2325 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2326 (tp->nvram_jedecnum == JEDEC_ATMEL))
2327
2328 addr = ((addr / tp->nvram_pagesize) <<
2329 ATMEL_AT45DB0X1B_PAGE_POS) +
2330 (addr % tp->nvram_pagesize);
2331
2332 return addr;
2333}
2334
2335static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2336{
2337 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2338 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2339 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2340 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2341 (tp->nvram_jedecnum == JEDEC_ATMEL))
2342
2343 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2344 tp->nvram_pagesize) +
2345 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2346
2347 return addr;
2348}
2349
e4f34110
MC		 2350/* NOTE: Data read in from NVRAM is byteswapped according to
2351 * the byteswapping settings for all other register accesses.
2352 * tg3 devices are BE devices, so on a BE machine, the data
2353 * returned will be exactly as it is seen in NVRAM. On a LE
2354 * machine, the 32-bit value will be byteswapped.
2355 */
ffbcfed4
MC		 2356static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2357{
2358 int ret;
2359
2360 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2361 return tg3_nvram_read_using_eeprom(tp, offset, val);
2362
2363 offset = tg3_nvram_phys_addr(tp, offset);
2364
2365 if (offset > NVRAM_ADDR_MSK)
2366 return -EINVAL;
2367
2368 ret = tg3_nvram_lock(tp);
2369 if (ret)
2370 return ret;
2371
2372 tg3_enable_nvram_access(tp);
2373
2374 tw32(NVRAM_ADDR, offset);
2375 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2376 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2377
2378 if (ret == 0)
e4f34110 2379 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2380
2381 tg3_disable_nvram_access(tp);
2382
2383 tg3_nvram_unlock(tp);
2384
2385 return ret;
2386}
2387
a9dc529d
MC		 2388/* Ensures NVRAM data is in bytestream format. */
2389static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2390{
2391 u32 v;
a9dc529d 2392 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2393 if (!res)
a9dc529d 2394 *val = cpu_to_be32(v);
ffbcfed4
MC		 2395 return res;
2396}
2397
3f007891
MC		 2398/* tp->lock is held. */
2399static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2400{
2401 u32 addr_high, addr_low;
2402 int i;
2403
2404 addr_high = ((tp->dev->dev_addr[0] << 8) |
2405 tp->dev->dev_addr[1]);
2406 addr_low = ((tp->dev->dev_addr[2] << 24) |
2407 (tp->dev->dev_addr[3] << 16) |
2408 (tp->dev->dev_addr[4] << 8) |
2409 (tp->dev->dev_addr[5] << 0));
2410 for (i = 0; i < 4; i++) {
2411 if (i == 1 && skip_mac_1)
2412 continue;
2413 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2414 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2415 }
2416
2417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2419 for (i = 0; i < 12; i++) {
2420 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2421 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2422 }
2423 }
2424
2425 addr_high = (tp->dev->dev_addr[0] +
2426 tp->dev->dev_addr[1] +
2427 tp->dev->dev_addr[2] +
2428 tp->dev->dev_addr[3] +
2429 tp->dev->dev_addr[4] +
2430 tp->dev->dev_addr[5]) &
2431 TX_BACKOFF_SEED_MASK;
2432 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2433}
2434
bc1c7567 2435static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2436{
2437 u32 misc_host_ctrl;
0a459aac 2438 bool device_should_wake, do_low_power;
1da177e4
LT		 2439
2440 /* Make sure register accesses (indirect or otherwise)
2441 * will function correctly.
2442 */
2443 pci_write_config_dword(tp->pdev,
2444 TG3PCI_MISC_HOST_CTRL,
2445 tp->misc_host_ctrl);
2446
1da177e4 2447 switch (state) {
bc1c7567 2448 case PCI_D0:
12dac075
RW		 2449 pci_enable_wake(tp->pdev, state, false);
2450 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2451
9d26e213
MC		 2452 /* Switch out of Vaux if it is a NIC */
2453 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2454 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2455
2456 return 0;
2457
bc1c7567 2458 case PCI_D1:
bc1c7567 2459 case PCI_D2:
bc1c7567 2460 case PCI_D3hot:
1da177e4
LT		 2461 break;
2462
2463 default:
12dac075
RW		 2464 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2465 tp->dev->name, state);
1da177e4 2466 return -EINVAL;
855e1111 2467 }
5e7dfd0f
MC		 2468
2469 /* Restore the CLKREQ setting. */
2470 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2471 u16 lnkctl;
2472
2473 pci_read_config_word(tp->pdev,
2474 tp->pcie_cap + PCI_EXP_LNKCTL,
2475 &lnkctl);
2476 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2477 pci_write_config_word(tp->pdev,
2478 tp->pcie_cap + PCI_EXP_LNKCTL,
2479 lnkctl);
2480 }
2481
1da177e4
LT		 2482 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2483 tw32(TG3PCI_MISC_HOST_CTRL,
2484 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2485
05ac4cb7
MC		 2486 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2487 device_may_wakeup(&tp->pdev->dev) &&
2488 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2489
dd477003 2490 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2491 do_low_power = false;
b02fd9e3
MC		 2492 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2493 !tp->link_config.phy_is_low_power) {
2494 struct phy_device *phydev;
0a459aac 2495 u32 phyid, advertising;
b02fd9e3 2496
3f0e3ad7 2497 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2498
2499 tp->link_config.phy_is_low_power = 1;
2500
2501 tp->link_config.orig_speed = phydev->speed;
2502 tp->link_config.orig_duplex = phydev->duplex;
2503 tp->link_config.orig_autoneg = phydev->autoneg;
2504 tp->link_config.orig_advertising = phydev->advertising;
2505
2506 advertising = ADVERTISED_TP |
2507 ADVERTISED_Pause |
2508 ADVERTISED_Autoneg |
2509 ADVERTISED_10baseT_Half;
2510
2511 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2512 device_should_wake) {
b02fd9e3
MC		 2513 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2514 advertising |=
2515 ADVERTISED_100baseT_Half |
2516 ADVERTISED_100baseT_Full |
2517 ADVERTISED_10baseT_Full;
2518 else
2519 advertising |= ADVERTISED_10baseT_Full;
2520 }
2521
2522 phydev->advertising = advertising;
2523
2524 phy_start_aneg(phydev);
0a459aac
MC		 2525
2526 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2527 if (phyid != TG3_PHY_ID_BCMAC131) {
2528 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2529 if (phyid == TG3_PHY_OUI_1 ||
2530 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2531 phyid == TG3_PHY_OUI_3)
2532 do_low_power = true;
2533 }
b02fd9e3 2534 }
dd477003 2535 } else {
2023276e 2536 do_low_power = true;
0a459aac 2537
dd477003
MC		 2538 if (tp->link_config.phy_is_low_power == 0) {
2539 tp->link_config.phy_is_low_power = 1;
2540 tp->link_config.orig_speed = tp->link_config.speed;
2541 tp->link_config.orig_duplex = tp->link_config.duplex;
2542 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2543 }
1da177e4 2544
dd477003
MC		 2545 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2546 tp->link_config.speed = SPEED_10;
2547 tp->link_config.duplex = DUPLEX_HALF;
2548 tp->link_config.autoneg = AUTONEG_ENABLE;
2549 tg3_setup_phy(tp, 0);
2550 }
1da177e4
LT		 2551 }
2552
b5d3772c
MC		 2553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2554 u32 val;
2555
2556 val = tr32(GRC_VCPU_EXT_CTRL);
2557 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2558 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2559 int i;
2560 u32 val;
2561
2562 for (i = 0; i < 200; i++) {
2563 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2564 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2565 break;
2566 msleep(1);
2567 }
2568 }
a85feb8c
GZ		 2569 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2570 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2571 WOL_DRV_STATE_SHUTDOWN |
2572 WOL_DRV_WOL |
2573 WOL_SET_MAGIC_PKT);
6921d201 2574
05ac4cb7 2575 if (device_should_wake) {
1da177e4
LT		 2576 u32 mac_mode;
2577
2578 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2579 if (do_low_power) {
dd477003
MC		 2580 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2581 udelay(40);
2582 }
1da177e4 2583
3f7045c1
MC		 2584 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2585 mac_mode = MAC_MODE_PORT_MODE_GMII;
2586 else
2587 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2588
e8f3f6ca
MC		 2589 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2590 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2591 ASIC_REV_5700) {
2592 u32 speed = (tp->tg3_flags &
2593 TG3_FLAG_WOL_SPEED_100MB) ?
2594 SPEED_100 : SPEED_10;
2595 if (tg3_5700_link_polarity(tp, speed))
2596 mac_mode |= MAC_MODE_LINK_POLARITY;
2597 else
2598 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2599 }
1da177e4
LT		 2600 } else {
2601 mac_mode = MAC_MODE_PORT_MODE_TBI;
2602 }
2603
cbf46853 2604 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2605 tw32(MAC_LED_CTRL, tp->led_ctrl);
2606
05ac4cb7
MC		 2607 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2608 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2609 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2610 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2611 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2612 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2613
3bda1258
MC		 2614 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2615 mac_mode |= tp->mac_mode &
2616 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2617 if (mac_mode & MAC_MODE_APE_TX_EN)
2618 mac_mode |= MAC_MODE_TDE_ENABLE;
2619 }
2620
1da177e4
LT		 2621 tw32_f(MAC_MODE, mac_mode);
2622 udelay(100);
2623
2624 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2625 udelay(10);
2626 }
2627
2628 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2629 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2631 u32 base_val;
2632
2633 base_val = tp->pci_clock_ctrl;
2634 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2635 CLOCK_CTRL_TXCLK_DISABLE);
2636
b401e9e2
MC		 2637 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2638 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2639 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2640 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2641 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2642 /* do nothing */
85e94ced 2643 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2644 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2645 u32 newbits1, newbits2;
2646
2647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2648 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2649 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2650 CLOCK_CTRL_TXCLK_DISABLE |
2651 CLOCK_CTRL_ALTCLK);
2652 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2653 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2654 newbits1 = CLOCK_CTRL_625_CORE;
2655 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2656 } else {
2657 newbits1 = CLOCK_CTRL_ALTCLK;
2658 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2659 }
2660
b401e9e2
MC		 2661 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2662 40);
1da177e4 2663
b401e9e2
MC		 2664 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2665 40);
1da177e4
LT		 2666
2667 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2668 u32 newbits3;
2669
2670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2672 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2673 CLOCK_CTRL_TXCLK_DISABLE |
2674 CLOCK_CTRL_44MHZ_CORE);
2675 } else {
2676 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2677 }
2678
b401e9e2
MC		 2679 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2680 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2681 }
2682 }
2683
05ac4cb7 2684 if (!(device_should_wake) &&
22435849 2685 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2686 tg3_power_down_phy(tp, do_low_power);
6921d201 2687
1da177e4
LT		 2688 tg3_frob_aux_power(tp);
2689
2690 /* Workaround for unstable PLL clock */
2691 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2692 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2693 u32 val = tr32(0x7d00);
2694
2695 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2696 tw32(0x7d00, val);
6921d201 2697 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2698 int err;
2699
2700 err = tg3_nvram_lock(tp);
1da177e4 2701 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2702 if (!err)
2703 tg3_nvram_unlock(tp);
6921d201 2704 }
1da177e4
LT		 2705 }
2706
bbadf503
MC		 2707 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2708
05ac4cb7 2709 if (device_should_wake)
12dac075
RW		 2710 pci_enable_wake(tp->pdev, state, true);
2711
1da177e4 2712 /* Finally, set the new power state. */
12dac075 2713 pci_set_power_state(tp->pdev, state);
1da177e4 2714
1da177e4
LT		 2715 return 0;
2716}
2717
1da177e4
LT		 2718static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2719{
2720 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2721 case MII_TG3_AUX_STAT_10HALF:
2722 *speed = SPEED_10;
2723 *duplex = DUPLEX_HALF;
2724 break;
2725
2726 case MII_TG3_AUX_STAT_10FULL:
2727 *speed = SPEED_10;
2728 *duplex = DUPLEX_FULL;
2729 break;
2730
2731 case MII_TG3_AUX_STAT_100HALF:
2732 *speed = SPEED_100;
2733 *duplex = DUPLEX_HALF;
2734 break;
2735
2736 case MII_TG3_AUX_STAT_100FULL:
2737 *speed = SPEED_100;
2738 *duplex = DUPLEX_FULL;
2739 break;
2740
2741 case MII_TG3_AUX_STAT_1000HALF:
2742 *speed = SPEED_1000;
2743 *duplex = DUPLEX_HALF;
2744 break;
2745
2746 case MII_TG3_AUX_STAT_1000FULL:
2747 *speed = SPEED_1000;
2748 *duplex = DUPLEX_FULL;
2749 break;
2750
2751 default:
7f97a4bd 2752 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2753 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2754 SPEED_10;
2755 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2756 DUPLEX_HALF;
2757 break;
2758 }
1da177e4
LT		 2759 *speed = SPEED_INVALID;
2760 *duplex = DUPLEX_INVALID;
2761 break;
855e1111 2762 }
1da177e4
LT		 2763}
2764
2765static void tg3_phy_copper_begin(struct tg3 *tp)
2766{
2767 u32 new_adv;
2768 int i;
2769
2770 if (tp->link_config.phy_is_low_power) {
2771 /* Entering low power mode. Disable gigabit and
2772 * 100baseT advertisements.
2773 */
2774 tg3_writephy(tp, MII_TG3_CTRL, 0);
2775
2776 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2777 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2778 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2779 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2780
2781 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2782 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2783 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2784 tp->link_config.advertising &=
2785 ~(ADVERTISED_1000baseT_Half |
2786 ADVERTISED_1000baseT_Full);
2787
ba4d07a8 2788 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2789 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2790 new_adv |= ADVERTISE_10HALF;
2791 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2792 new_adv |= ADVERTISE_10FULL;
2793 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2794 new_adv |= ADVERTISE_100HALF;
2795 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2796 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2797
2798 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2799
1da177e4
LT		 2800 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2801
2802 if (tp->link_config.advertising &
2803 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2804 new_adv = 0;
2805 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2806 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2807 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2808 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2809 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2810 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2811 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2812 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2813 MII_TG3_CTRL_ENABLE_AS_MASTER);
2814 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2815 } else {
2816 tg3_writephy(tp, MII_TG3_CTRL, 0);
2817 }
2818 } else {
ba4d07a8
MC		 2819 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2820 new_adv |= ADVERTISE_CSMA;
2821
1da177e4
LT		 2822 /* Asking for a specific link mode. */
2823 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2824 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2825
2826 if (tp->link_config.duplex == DUPLEX_FULL)
2827 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2828 else
2829 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2830 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2832 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2834 } else {
1da177e4
LT		 2835 if (tp->link_config.speed == SPEED_100) {
2836 if (tp->link_config.duplex == DUPLEX_FULL)
2837 new_adv |= ADVERTISE_100FULL;
2838 else
2839 new_adv |= ADVERTISE_100HALF;
2840 } else {
2841 if (tp->link_config.duplex == DUPLEX_FULL)
2842 new_adv |= ADVERTISE_10FULL;
2843 else
2844 new_adv |= ADVERTISE_10HALF;
2845 }
2846 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2847
2848 new_adv = 0;
1da177e4 2849 }
ba4d07a8
MC		 2850
2851 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2852 }
2853
2854 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2855 tp->link_config.speed != SPEED_INVALID) {
2856 u32 bmcr, orig_bmcr;
2857
2858 tp->link_config.active_speed = tp->link_config.speed;
2859 tp->link_config.active_duplex = tp->link_config.duplex;
2860
2861 bmcr = 0;
2862 switch (tp->link_config.speed) {
2863 default:
2864 case SPEED_10:
2865 break;
2866
2867 case SPEED_100:
2868 bmcr |= BMCR_SPEED100;
2869 break;
2870
2871 case SPEED_1000:
2872 bmcr |= TG3_BMCR_SPEED1000;
2873 break;
855e1111 2874 }
1da177e4
LT		 2875
2876 if (tp->link_config.duplex == DUPLEX_FULL)
2877 bmcr |= BMCR_FULLDPLX;
2878
2879 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2880 (bmcr != orig_bmcr)) {
2881 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2882 for (i = 0; i < 1500; i++) {
2883 u32 tmp;
2884
2885 udelay(10);
2886 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2887 tg3_readphy(tp, MII_BMSR, &tmp))
2888 continue;
2889 if (!(tmp & BMSR_LSTATUS)) {
2890 udelay(40);
2891 break;
2892 }
2893 }
2894 tg3_writephy(tp, MII_BMCR, bmcr);
2895 udelay(40);
2896 }
2897 } else {
2898 tg3_writephy(tp, MII_BMCR,
2899 BMCR_ANENABLE | BMCR_ANRESTART);
2900 }
2901}
2902
2903static int tg3_init_5401phy_dsp(struct tg3 *tp)
2904{
2905 int err;
2906
2907 /* Turn off tap power management. */
2908 /* Set Extended packet length bit */
2909 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2910
2911 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2912 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2913
2914 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2915 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2916
2917 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2918 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2919
2920 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2921 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2922
2923 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2924 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2925
2926 udelay(40);
2927
2928 return err;
2929}
2930
3600d918 2931static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2932{
3600d918
MC		 2933 u32 adv_reg, all_mask = 0;
2934
2935 if (mask & ADVERTISED_10baseT_Half)
2936 all_mask |= ADVERTISE_10HALF;
2937 if (mask & ADVERTISED_10baseT_Full)
2938 all_mask |= ADVERTISE_10FULL;
2939 if (mask & ADVERTISED_100baseT_Half)
2940 all_mask |= ADVERTISE_100HALF;
2941 if (mask & ADVERTISED_100baseT_Full)
2942 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2943
2944 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2945 return 0;
2946
1da177e4
LT		 2947 if ((adv_reg & all_mask) != all_mask)
2948 return 0;
2949 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2950 u32 tg3_ctrl;
2951
3600d918
MC		 2952 all_mask = 0;
2953 if (mask & ADVERTISED_1000baseT_Half)
2954 all_mask |= ADVERTISE_1000HALF;
2955 if (mask & ADVERTISED_1000baseT_Full)
2956 all_mask |= ADVERTISE_1000FULL;
2957
1da177e4
LT		 2958 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2959 return 0;
2960
1da177e4
LT		 2961 if ((tg3_ctrl & all_mask) != all_mask)
2962 return 0;
2963 }
2964 return 1;
2965}
2966
ef167e27
MC		 2967static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2968{
2969 u32 curadv, reqadv;
2970
2971 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2972 return 1;
2973
2974 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2975 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2976
2977 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2978 if (curadv != reqadv)
2979 return 0;
2980
2981 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2982 tg3_readphy(tp, MII_LPA, rmtadv);
2983 } else {
2984 /* Reprogram the advertisement register, even if it
2985 * does not affect the current link. If the link
2986 * gets renegotiated in the future, we can save an
2987 * additional renegotiation cycle by advertising
2988 * it correctly in the first place.
2989 */
2990 if (curadv != reqadv) {
2991 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2992 ADVERTISE_PAUSE_ASYM);
2993 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2994 }
2995 }
2996
2997 return 1;
2998}
2999
1da177e4
LT		 3000static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3001{
3002 int current_link_up;
3003 u32 bmsr, dummy;
ef167e27 3004 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3005 u16 current_speed;
3006 u8 current_duplex;
3007 int i, err;
3008
3009 tw32(MAC_EVENT, 0);
3010
3011 tw32_f(MAC_STATUS,
3012 (MAC_STATUS_SYNC_CHANGED |
3013 MAC_STATUS_CFG_CHANGED |
3014 MAC_STATUS_MI_COMPLETION |
3015 MAC_STATUS_LNKSTATE_CHANGED));
3016 udelay(40);
3017
8ef21428
MC		 3018 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3019 tw32_f(MAC_MI_MODE,
3020 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3021 udelay(80);
3022 }
1da177e4
LT		 3023
3024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3025
3026 /* Some third-party PHYs need to be reset on link going
3027 * down.
3028 */
3029 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3032 netif_carrier_ok(tp->dev)) {
3033 tg3_readphy(tp, MII_BMSR, &bmsr);
3034 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3035 !(bmsr & BMSR_LSTATUS))
3036 force_reset = 1;
3037 }
3038 if (force_reset)
3039 tg3_phy_reset(tp);
3040
3041 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3042 tg3_readphy(tp, MII_BMSR, &bmsr);
3043 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3044 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3045 bmsr = 0;
3046
3047 if (!(bmsr & BMSR_LSTATUS)) {
3048 err = tg3_init_5401phy_dsp(tp);
3049 if (err)
3050 return err;
3051
3052 tg3_readphy(tp, MII_BMSR, &bmsr);
3053 for (i = 0; i < 1000; i++) {
3054 udelay(10);
3055 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3056 (bmsr & BMSR_LSTATUS)) {
3057 udelay(40);
3058 break;
3059 }
3060 }
3061
3062 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3063 !(bmsr & BMSR_LSTATUS) &&
3064 tp->link_config.active_speed == SPEED_1000) {
3065 err = tg3_phy_reset(tp);
3066 if (!err)
3067 err = tg3_init_5401phy_dsp(tp);
3068 if (err)
3069 return err;
3070 }
3071 }
3072 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3073 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3074 /* 5701 {A0,B0} CRC bug workaround */
3075 tg3_writephy(tp, 0x15, 0x0a75);
3076 tg3_writephy(tp, 0x1c, 0x8c68);
3077 tg3_writephy(tp, 0x1c, 0x8d68);
3078 tg3_writephy(tp, 0x1c, 0x8c68);
3079 }
3080
3081 /* Clear pending interrupts... */
3082 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3083 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3084
3085 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3086 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3087 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3088 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3089
3090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3092 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3093 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3094 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3095 else
3096 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3097 }
3098
3099 current_link_up = 0;
3100 current_speed = SPEED_INVALID;
3101 current_duplex = DUPLEX_INVALID;
3102
3103 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3104 u32 val;
3105
3106 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3107 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3108 if (!(val & (1 << 10))) {
3109 val |= (1 << 10);
3110 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3111 goto relink;
3112 }
3113 }
3114
3115 bmsr = 0;
3116 for (i = 0; i < 100; i++) {
3117 tg3_readphy(tp, MII_BMSR, &bmsr);
3118 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3119 (bmsr & BMSR_LSTATUS))
3120 break;
3121 udelay(40);
3122 }
3123
3124 if (bmsr & BMSR_LSTATUS) {
3125 u32 aux_stat, bmcr;
3126
3127 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3128 for (i = 0; i < 2000; i++) {
3129 udelay(10);
3130 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3131 aux_stat)
3132 break;
3133 }
3134
3135 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3136 &current_speed,
3137 &current_duplex);
3138
3139 bmcr = 0;
3140 for (i = 0; i < 200; i++) {
3141 tg3_readphy(tp, MII_BMCR, &bmcr);
3142 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3143 continue;
3144 if (bmcr && bmcr != 0x7fff)
3145 break;
3146 udelay(10);
3147 }
3148
ef167e27
MC		 3149 lcl_adv = 0;
3150 rmt_adv = 0;
1da177e4 3151
ef167e27
MC		 3152 tp->link_config.active_speed = current_speed;
3153 tp->link_config.active_duplex = current_duplex;
3154
3155 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3156 if ((bmcr & BMCR_ANENABLE) &&
3157 tg3_copper_is_advertising_all(tp,
3158 tp->link_config.advertising)) {
3159 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3160 &rmt_adv))
3161 current_link_up = 1;
1da177e4
LT		 3162 }
3163 } else {
3164 if (!(bmcr & BMCR_ANENABLE) &&
3165 tp->link_config.speed == current_speed &&
ef167e27
MC		 3166 tp->link_config.duplex == current_duplex &&
3167 tp->link_config.flowctrl ==
3168 tp->link_config.active_flowctrl) {
1da177e4 3169 current_link_up = 1;
1da177e4
LT		 3170 }
3171 }
3172
ef167e27
MC		 3173 if (current_link_up == 1 &&
3174 tp->link_config.active_duplex == DUPLEX_FULL)
3175 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3176 }
3177
1da177e4 3178relink:
6921d201 3179 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3180 u32 tmp;
3181
3182 tg3_phy_copper_begin(tp);
3183
3184 tg3_readphy(tp, MII_BMSR, &tmp);
3185 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3186 (tmp & BMSR_LSTATUS))
3187 current_link_up = 1;
3188 }
3189
3190 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3191 if (current_link_up == 1) {
3192 if (tp->link_config.active_speed == SPEED_100 ||
3193 tp->link_config.active_speed == SPEED_10)
3194 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3195 else
3196 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3197 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3198 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3199 else
1da177e4
LT		 3200 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3201
3202 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3203 if (tp->link_config.active_duplex == DUPLEX_HALF)
3204 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3205
1da177e4 3206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3207 if (current_link_up == 1 &&
3208 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3209 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3210 else
3211 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3212 }
3213
3214 /* ??? Without this setting Netgear GA302T PHY does not
3215 * ??? send/receive packets...
3216 */
3217 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3218 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3219 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3220 tw32_f(MAC_MI_MODE, tp->mi_mode);
3221 udelay(80);
3222 }
3223
3224 tw32_f(MAC_MODE, tp->mac_mode);
3225 udelay(40);
3226
3227 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3228 /* Polled via timer. */
3229 tw32_f(MAC_EVENT, 0);
3230 } else {
3231 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3232 }
3233 udelay(40);
3234
3235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3236 current_link_up == 1 &&
3237 tp->link_config.active_speed == SPEED_1000 &&
3238 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3239 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3240 udelay(120);
3241 tw32_f(MAC_STATUS,
3242 (MAC_STATUS_SYNC_CHANGED |
3243 MAC_STATUS_CFG_CHANGED));
3244 udelay(40);
3245 tg3_write_mem(tp,
3246 NIC_SRAM_FIRMWARE_MBOX,
3247 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3248 }
3249
5e7dfd0f
MC		 3250 /* Prevent send BD corruption. */
3251 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3252 u16 oldlnkctl, newlnkctl;
3253
3254 pci_read_config_word(tp->pdev,
3255 tp->pcie_cap + PCI_EXP_LNKCTL,
3256 &oldlnkctl);
3257 if (tp->link_config.active_speed == SPEED_100 ||
3258 tp->link_config.active_speed == SPEED_10)
3259 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3260 else
3261 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3262 if (newlnkctl != oldlnkctl)
3263 pci_write_config_word(tp->pdev,
3264 tp->pcie_cap + PCI_EXP_LNKCTL,
3265 newlnkctl);
3266 }
3267
1da177e4
LT		 3268 if (current_link_up != netif_carrier_ok(tp->dev)) {
3269 if (current_link_up)
3270 netif_carrier_on(tp->dev);
3271 else
3272 netif_carrier_off(tp->dev);
3273 tg3_link_report(tp);
3274 }
3275
3276 return 0;
3277}
3278
3279struct tg3_fiber_aneginfo {
3280 int state;
3281#define ANEG_STATE_UNKNOWN 0
3282#define ANEG_STATE_AN_ENABLE 1
3283#define ANEG_STATE_RESTART_INIT 2
3284#define ANEG_STATE_RESTART 3
3285#define ANEG_STATE_DISABLE_LINK_OK 4
3286#define ANEG_STATE_ABILITY_DETECT_INIT 5
3287#define ANEG_STATE_ABILITY_DETECT 6
3288#define ANEG_STATE_ACK_DETECT_INIT 7
3289#define ANEG_STATE_ACK_DETECT 8
3290#define ANEG_STATE_COMPLETE_ACK_INIT 9
3291#define ANEG_STATE_COMPLETE_ACK 10
3292#define ANEG_STATE_IDLE_DETECT_INIT 11
3293#define ANEG_STATE_IDLE_DETECT 12
3294#define ANEG_STATE_LINK_OK 13
3295#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3296#define ANEG_STATE_NEXT_PAGE_WAIT 15
3297
3298 u32 flags;
3299#define MR_AN_ENABLE 0x00000001
3300#define MR_RESTART_AN 0x00000002
3301#define MR_AN_COMPLETE 0x00000004
3302#define MR_PAGE_RX 0x00000008
3303#define MR_NP_LOADED 0x00000010
3304#define MR_TOGGLE_TX 0x00000020
3305#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3306#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3307#define MR_LP_ADV_SYM_PAUSE 0x00000100
3308#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3309#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3310#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3311#define MR_LP_ADV_NEXT_PAGE 0x00001000
3312#define MR_TOGGLE_RX 0x00002000
3313#define MR_NP_RX 0x00004000
3314
3315#define MR_LINK_OK 0x80000000
3316
3317 unsigned long link_time, cur_time;
3318
3319 u32 ability_match_cfg;
3320 int ability_match_count;
3321
3322 char ability_match, idle_match, ack_match;
3323
3324 u32 txconfig, rxconfig;
3325#define ANEG_CFG_NP 0x00000080
3326#define ANEG_CFG_ACK 0x00000040
3327#define ANEG_CFG_RF2 0x00000020
3328#define ANEG_CFG_RF1 0x00000010
3329#define ANEG_CFG_PS2 0x00000001
3330#define ANEG_CFG_PS1 0x00008000
3331#define ANEG_CFG_HD 0x00004000
3332#define ANEG_CFG_FD 0x00002000
3333#define ANEG_CFG_INVAL 0x00001f06
3334
3335};
3336#define ANEG_OK 0
3337#define ANEG_DONE 1
3338#define ANEG_TIMER_ENAB 2
3339#define ANEG_FAILED -1
3340
3341#define ANEG_STATE_SETTLE_TIME 10000
3342
3343static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3344 struct tg3_fiber_aneginfo *ap)
3345{
5be73b47 3346 u16 flowctrl;
1da177e4
LT		 3347 unsigned long delta;
3348 u32 rx_cfg_reg;
3349 int ret;
3350
3351 if (ap->state == ANEG_STATE_UNKNOWN) {
3352 ap->rxconfig = 0;
3353 ap->link_time = 0;
3354 ap->cur_time = 0;
3355 ap->ability_match_cfg = 0;
3356 ap->ability_match_count = 0;
3357 ap->ability_match = 0;
3358 ap->idle_match = 0;
3359 ap->ack_match = 0;
3360 }
3361 ap->cur_time++;
3362
3363 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3364 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3365
3366 if (rx_cfg_reg != ap->ability_match_cfg) {
3367 ap->ability_match_cfg = rx_cfg_reg;
3368 ap->ability_match = 0;
3369 ap->ability_match_count = 0;
3370 } else {
3371 if (++ap->ability_match_count > 1) {
3372 ap->ability_match = 1;
3373 ap->ability_match_cfg = rx_cfg_reg;
3374 }
3375 }
3376 if (rx_cfg_reg & ANEG_CFG_ACK)
3377 ap->ack_match = 1;
3378 else
3379 ap->ack_match = 0;
3380
3381 ap->idle_match = 0;
3382 } else {
3383 ap->idle_match = 1;
3384 ap->ability_match_cfg = 0;
3385 ap->ability_match_count = 0;
3386 ap->ability_match = 0;
3387 ap->ack_match = 0;
3388
3389 rx_cfg_reg = 0;
3390 }
3391
3392 ap->rxconfig = rx_cfg_reg;
3393 ret = ANEG_OK;
3394
3395 switch(ap->state) {
3396 case ANEG_STATE_UNKNOWN:
3397 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3398 ap->state = ANEG_STATE_AN_ENABLE;
3399
3400 /* fallthru */
3401 case ANEG_STATE_AN_ENABLE:
3402 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3403 if (ap->flags & MR_AN_ENABLE) {
3404 ap->link_time = 0;
3405 ap->cur_time = 0;
3406 ap->ability_match_cfg = 0;
3407 ap->ability_match_count = 0;
3408 ap->ability_match = 0;
3409 ap->idle_match = 0;
3410 ap->ack_match = 0;
3411
3412 ap->state = ANEG_STATE_RESTART_INIT;
3413 } else {
3414 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3415 }
3416 break;
3417
3418 case ANEG_STATE_RESTART_INIT:
3419 ap->link_time = ap->cur_time;
3420 ap->flags &= ~(MR_NP_LOADED);
3421 ap->txconfig = 0;
3422 tw32(MAC_TX_AUTO_NEG, 0);
3423 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3424 tw32_f(MAC_MODE, tp->mac_mode);
3425 udelay(40);
3426
3427 ret = ANEG_TIMER_ENAB;
3428 ap->state = ANEG_STATE_RESTART;
3429
3430 /* fallthru */
3431 case ANEG_STATE_RESTART:
3432 delta = ap->cur_time - ap->link_time;
3433 if (delta > ANEG_STATE_SETTLE_TIME) {
3434 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3435 } else {
3436 ret = ANEG_TIMER_ENAB;
3437 }
3438 break;
3439
3440 case ANEG_STATE_DISABLE_LINK_OK:
3441 ret = ANEG_DONE;
3442 break;
3443
3444 case ANEG_STATE_ABILITY_DETECT_INIT:
3445 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3446 ap->txconfig = ANEG_CFG_FD;
3447 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3448 if (flowctrl & ADVERTISE_1000XPAUSE)
3449 ap->txconfig |= ANEG_CFG_PS1;
3450 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3451 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3452 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3453 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3454 tw32_f(MAC_MODE, tp->mac_mode);
3455 udelay(40);
3456
3457 ap->state = ANEG_STATE_ABILITY_DETECT;
3458 break;
3459
3460 case ANEG_STATE_ABILITY_DETECT:
3461 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3462 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3463 }
3464 break;
3465
3466 case ANEG_STATE_ACK_DETECT_INIT:
3467 ap->txconfig |= ANEG_CFG_ACK;
3468 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3469 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3470 tw32_f(MAC_MODE, tp->mac_mode);
3471 udelay(40);
3472
3473 ap->state = ANEG_STATE_ACK_DETECT;
3474
3475 /* fallthru */
3476 case ANEG_STATE_ACK_DETECT:
3477 if (ap->ack_match != 0) {
3478 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3479 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3480 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3481 } else {
3482 ap->state = ANEG_STATE_AN_ENABLE;
3483 }
3484 } else if (ap->ability_match != 0 &&
3485 ap->rxconfig == 0) {
3486 ap->state = ANEG_STATE_AN_ENABLE;
3487 }
3488 break;
3489
3490 case ANEG_STATE_COMPLETE_ACK_INIT:
3491 if (ap->rxconfig & ANEG_CFG_INVAL) {
3492 ret = ANEG_FAILED;
3493 break;
3494 }
3495 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3496 MR_LP_ADV_HALF_DUPLEX |
3497 MR_LP_ADV_SYM_PAUSE |
3498 MR_LP_ADV_ASYM_PAUSE |
3499 MR_LP_ADV_REMOTE_FAULT1 |
3500 MR_LP_ADV_REMOTE_FAULT2 |
3501 MR_LP_ADV_NEXT_PAGE |
3502 MR_TOGGLE_RX |
3503 MR_NP_RX);
3504 if (ap->rxconfig & ANEG_CFG_FD)
3505 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3506 if (ap->rxconfig & ANEG_CFG_HD)
3507 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3508 if (ap->rxconfig & ANEG_CFG_PS1)
3509 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3510 if (ap->rxconfig & ANEG_CFG_PS2)
3511 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3512 if (ap->rxconfig & ANEG_CFG_RF1)
3513 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3514 if (ap->rxconfig & ANEG_CFG_RF2)
3515 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3516 if (ap->rxconfig & ANEG_CFG_NP)
3517 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3518
3519 ap->link_time = ap->cur_time;
3520
3521 ap->flags ^= (MR_TOGGLE_TX);
3522 if (ap->rxconfig & 0x0008)
3523 ap->flags |= MR_TOGGLE_RX;
3524 if (ap->rxconfig & ANEG_CFG_NP)
3525 ap->flags |= MR_NP_RX;
3526 ap->flags |= MR_PAGE_RX;
3527
3528 ap->state = ANEG_STATE_COMPLETE_ACK;
3529 ret = ANEG_TIMER_ENAB;
3530 break;
3531
3532 case ANEG_STATE_COMPLETE_ACK:
3533 if (ap->ability_match != 0 &&
3534 ap->rxconfig == 0) {
3535 ap->state = ANEG_STATE_AN_ENABLE;
3536 break;
3537 }
3538 delta = ap->cur_time - ap->link_time;
3539 if (delta > ANEG_STATE_SETTLE_TIME) {
3540 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3541 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3542 } else {
3543 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3544 !(ap->flags & MR_NP_RX)) {
3545 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3546 } else {
3547 ret = ANEG_FAILED;
3548 }
3549 }
3550 }
3551 break;
3552
3553 case ANEG_STATE_IDLE_DETECT_INIT:
3554 ap->link_time = ap->cur_time;
3555 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3556 tw32_f(MAC_MODE, tp->mac_mode);
3557 udelay(40);
3558
3559 ap->state = ANEG_STATE_IDLE_DETECT;
3560 ret = ANEG_TIMER_ENAB;
3561 break;
3562
3563 case ANEG_STATE_IDLE_DETECT:
3564 if (ap->ability_match != 0 &&
3565 ap->rxconfig == 0) {
3566 ap->state = ANEG_STATE_AN_ENABLE;
3567 break;
3568 }
3569 delta = ap->cur_time - ap->link_time;
3570 if (delta > ANEG_STATE_SETTLE_TIME) {
3571 /* XXX another gem from the Broadcom driver :( */
3572 ap->state = ANEG_STATE_LINK_OK;
3573 }
3574 break;
3575
3576 case ANEG_STATE_LINK_OK:
3577 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3578 ret = ANEG_DONE;
3579 break;
3580
3581 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3582 /* ??? unimplemented */
3583 break;
3584
3585 case ANEG_STATE_NEXT_PAGE_WAIT:
3586 /* ??? unimplemented */
3587 break;
3588
3589 default:
3590 ret = ANEG_FAILED;
3591 break;
855e1111 3592 }
1da177e4
LT		 3593
3594 return ret;
3595}
3596
5be73b47 3597static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3598{
3599 int res = 0;
3600 struct tg3_fiber_aneginfo aninfo;
3601 int status = ANEG_FAILED;
3602 unsigned int tick;
3603 u32 tmp;
3604
3605 tw32_f(MAC_TX_AUTO_NEG, 0);
3606
3607 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3608 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3609 udelay(40);
3610
3611 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3612 udelay(40);
3613
3614 memset(&aninfo, 0, sizeof(aninfo));
3615 aninfo.flags |= MR_AN_ENABLE;
3616 aninfo.state = ANEG_STATE_UNKNOWN;
3617 aninfo.cur_time = 0;
3618 tick = 0;
3619 while (++tick < 195000) {
3620 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3621 if (status == ANEG_DONE || status == ANEG_FAILED)
3622 break;
3623
3624 udelay(1);
3625 }
3626
3627 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3628 tw32_f(MAC_MODE, tp->mac_mode);
3629 udelay(40);
3630
5be73b47
MC		 3631 *txflags = aninfo.txconfig;
3632 *rxflags = aninfo.flags;
1da177e4
LT		 3633
3634 if (status == ANEG_DONE &&
3635 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3636 MR_LP_ADV_FULL_DUPLEX)))
3637 res = 1;
3638
3639 return res;
3640}
3641
3642static void tg3_init_bcm8002(struct tg3 *tp)
3643{
3644 u32 mac_status = tr32(MAC_STATUS);
3645 int i;
3646
3647 /* Reset when initting first time or we have a link. */
3648 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3649 !(mac_status & MAC_STATUS_PCS_SYNCED))
3650 return;
3651
3652 /* Set PLL lock range. */
3653 tg3_writephy(tp, 0x16, 0x8007);
3654
3655 /* SW reset */
3656 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3657
3658 /* Wait for reset to complete. */
3659 /* XXX schedule_timeout() ... */
3660 for (i = 0; i < 500; i++)
3661 udelay(10);
3662
3663 /* Config mode; select PMA/Ch 1 regs. */
3664 tg3_writephy(tp, 0x10, 0x8411);
3665
3666 /* Enable auto-lock and comdet, select txclk for tx. */
3667 tg3_writephy(tp, 0x11, 0x0a10);
3668
3669 tg3_writephy(tp, 0x18, 0x00a0);
3670 tg3_writephy(tp, 0x16, 0x41ff);
3671
3672 /* Assert and deassert POR. */
3673 tg3_writephy(tp, 0x13, 0x0400);
3674 udelay(40);
3675 tg3_writephy(tp, 0x13, 0x0000);
3676
3677 tg3_writephy(tp, 0x11, 0x0a50);
3678 udelay(40);
3679 tg3_writephy(tp, 0x11, 0x0a10);
3680
3681 /* Wait for signal to stabilize */
3682 /* XXX schedule_timeout() ... */
3683 for (i = 0; i < 15000; i++)
3684 udelay(10);
3685
3686 /* Deselect the channel register so we can read the PHYID
3687 * later.
3688 */
3689 tg3_writephy(tp, 0x10, 0x8011);
3690}
3691
3692static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3693{
82cd3d11 3694 u16 flowctrl;
1da177e4
LT		 3695 u32 sg_dig_ctrl, sg_dig_status;
3696 u32 serdes_cfg, expected_sg_dig_ctrl;
3697 int workaround, port_a;
3698 int current_link_up;
3699
3700 serdes_cfg = 0;
3701 expected_sg_dig_ctrl = 0;
3702 workaround = 0;
3703 port_a = 1;
3704 current_link_up = 0;
3705
3706 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3707 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3708 workaround = 1;
3709 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3710 port_a = 0;
3711
3712 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3713 /* preserve bits 20-23 for voltage regulator */
3714 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3715 }
3716
3717 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3718
3719 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3720 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3721 if (workaround) {
3722 u32 val = serdes_cfg;
3723
3724 if (port_a)
3725 val |= 0xc010000;
3726 else
3727 val |= 0x4010000;
3728 tw32_f(MAC_SERDES_CFG, val);
3729 }
c98f6e3b
MC		 3730
3731 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3732 }
3733 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3734 tg3_setup_flow_control(tp, 0, 0);
3735 current_link_up = 1;
3736 }
3737 goto out;
3738 }
3739
3740 /* Want auto-negotiation. */
c98f6e3b 3741 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3742
82cd3d11
MC		 3743 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3744 if (flowctrl & ADVERTISE_1000XPAUSE)
3745 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3746 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3747 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3748
3749 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3750 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3751 tp->serdes_counter &&
3752 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3753 MAC_STATUS_RCVD_CFG)) ==
3754 MAC_STATUS_PCS_SYNCED)) {
3755 tp->serdes_counter--;
3756 current_link_up = 1;
3757 goto out;
3758 }
3759restart_autoneg:
1da177e4
LT		 3760 if (workaround)
3761 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3762 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3763 udelay(5);
3764 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3765
3d3ebe74
MC		 3766 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3767 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3768 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3769 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3770 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3771 mac_status = tr32(MAC_STATUS);
3772
c98f6e3b 3773 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3774 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3775 u32 local_adv = 0, remote_adv = 0;
3776
3777 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3778 local_adv |= ADVERTISE_1000XPAUSE;
3779 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3780 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3781
c98f6e3b 3782 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3783 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3784 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3785 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3786
3787 tg3_setup_flow_control(tp, local_adv, remote_adv);
3788 current_link_up = 1;
3d3ebe74
MC		 3789 tp->serdes_counter = 0;
3790 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3791 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3792 if (tp->serdes_counter)
3793 tp->serdes_counter--;
1da177e4
LT		 3794 else {
3795 if (workaround) {
3796 u32 val = serdes_cfg;
3797
3798 if (port_a)
3799 val |= 0xc010000;
3800 else
3801 val |= 0x4010000;
3802
3803 tw32_f(MAC_SERDES_CFG, val);
3804 }
3805
c98f6e3b 3806 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3807 udelay(40);
3808
3809 /* Link parallel detection - link is up */
3810 /* only if we have PCS_SYNC and not */
3811 /* receiving config code words */
3812 mac_status = tr32(MAC_STATUS);
3813 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3814 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3815 tg3_setup_flow_control(tp, 0, 0);
3816 current_link_up = 1;
3d3ebe74
MC		 3817 tp->tg3_flags2 |=
3818 TG3_FLG2_PARALLEL_DETECT;
3819 tp->serdes_counter =
3820 SERDES_PARALLEL_DET_TIMEOUT;
3821 } else
3822 goto restart_autoneg;
1da177e4
LT		 3823 }
3824 }
3d3ebe74
MC		 3825 } else {
3826 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3827 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3828 }
3829
3830out:
3831 return current_link_up;
3832}
3833
3834static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3835{
3836 int current_link_up = 0;
3837
5cf64b8a 3838 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3839 goto out;
1da177e4
LT		 3840
3841 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3842 u32 txflags, rxflags;
1da177e4 3843 int i;
6aa20a22 3844
5be73b47
MC		 3845 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3846 u32 local_adv = 0, remote_adv = 0;
1da177e4 3847
5be73b47
MC		 3848 if (txflags & ANEG_CFG_PS1)
3849 local_adv |= ADVERTISE_1000XPAUSE;
3850 if (txflags & ANEG_CFG_PS2)
3851 local_adv |= ADVERTISE_1000XPSE_ASYM;
3852
3853 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3854 remote_adv |= LPA_1000XPAUSE;
3855 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3856 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3857
3858 tg3_setup_flow_control(tp, local_adv, remote_adv);
3859
1da177e4
LT		 3860 current_link_up = 1;
3861 }
3862 for (i = 0; i < 30; i++) {
3863 udelay(20);
3864 tw32_f(MAC_STATUS,
3865 (MAC_STATUS_SYNC_CHANGED |
3866 MAC_STATUS_CFG_CHANGED));
3867 udelay(40);
3868 if ((tr32(MAC_STATUS) &
3869 (MAC_STATUS_SYNC_CHANGED |
3870 MAC_STATUS_CFG_CHANGED)) == 0)
3871 break;
3872 }
3873
3874 mac_status = tr32(MAC_STATUS);
3875 if (current_link_up == 0 &&
3876 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3877 !(mac_status & MAC_STATUS_RCVD_CFG))
3878 current_link_up = 1;
3879 } else {
5be73b47
MC		 3880 tg3_setup_flow_control(tp, 0, 0);
3881
1da177e4
LT		 3882 /* Forcing 1000FD link up. */
3883 current_link_up = 1;
1da177e4
LT		 3884
3885 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3886 udelay(40);
e8f3f6ca
MC		 3887
3888 tw32_f(MAC_MODE, tp->mac_mode);
3889 udelay(40);
1da177e4
LT		 3890 }
3891
3892out:
3893 return current_link_up;
3894}
3895
3896static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3897{
3898 u32 orig_pause_cfg;
3899 u16 orig_active_speed;
3900 u8 orig_active_duplex;
3901 u32 mac_status;
3902 int current_link_up;
3903 int i;
3904
8d018621 3905 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3906 orig_active_speed = tp->link_config.active_speed;
3907 orig_active_duplex = tp->link_config.active_duplex;
3908
3909 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3910 netif_carrier_ok(tp->dev) &&
3911 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3912 mac_status = tr32(MAC_STATUS);
3913 mac_status &= (MAC_STATUS_PCS_SYNCED |
3914 MAC_STATUS_SIGNAL_DET |
3915 MAC_STATUS_CFG_CHANGED |
3916 MAC_STATUS_RCVD_CFG);
3917 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3918 MAC_STATUS_SIGNAL_DET)) {
3919 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3920 MAC_STATUS_CFG_CHANGED));
3921 return 0;
3922 }
3923 }
3924
3925 tw32_f(MAC_TX_AUTO_NEG, 0);
3926
3927 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3928 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3929 tw32_f(MAC_MODE, tp->mac_mode);
3930 udelay(40);
3931
3932 if (tp->phy_id == PHY_ID_BCM8002)
3933 tg3_init_bcm8002(tp);
3934
3935 /* Enable link change event even when serdes polling. */
3936 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3937 udelay(40);
3938
3939 current_link_up = 0;
3940 mac_status = tr32(MAC_STATUS);
3941
3942 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3943 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3944 else
3945 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3946
898a56f8 3947 tp->napi[0].hw_status->status =
1da177e4 3948 (SD_STATUS_UPDATED |
898a56f8 3949 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3950
3951 for (i = 0; i < 100; i++) {
3952 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3953 MAC_STATUS_CFG_CHANGED));
3954 udelay(5);
3955 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3956 MAC_STATUS_CFG_CHANGED |
3957 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3958 break;
3959 }
3960
3961 mac_status = tr32(MAC_STATUS);
3962 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3963 current_link_up = 0;
3d3ebe74
MC		 3964 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3965 tp->serdes_counter == 0) {
1da177e4
LT		 3966 tw32_f(MAC_MODE, (tp->mac_mode |
3967 MAC_MODE_SEND_CONFIGS));
3968 udelay(1);
3969 tw32_f(MAC_MODE, tp->mac_mode);
3970 }
3971 }
3972
3973 if (current_link_up == 1) {
3974 tp->link_config.active_speed = SPEED_1000;
3975 tp->link_config.active_duplex = DUPLEX_FULL;
3976 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3977 LED_CTRL_LNKLED_OVERRIDE |
3978 LED_CTRL_1000MBPS_ON));
3979 } else {
3980 tp->link_config.active_speed = SPEED_INVALID;
3981 tp->link_config.active_duplex = DUPLEX_INVALID;
3982 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3983 LED_CTRL_LNKLED_OVERRIDE |
3984 LED_CTRL_TRAFFIC_OVERRIDE));
3985 }
3986
3987 if (current_link_up != netif_carrier_ok(tp->dev)) {
3988 if (current_link_up)
3989 netif_carrier_on(tp->dev);
3990 else
3991 netif_carrier_off(tp->dev);
3992 tg3_link_report(tp);
3993 } else {
8d018621 3994 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3995 if (orig_pause_cfg != now_pause_cfg ||
3996 orig_active_speed != tp->link_config.active_speed ||
3997 orig_active_duplex != tp->link_config.active_duplex)
3998 tg3_link_report(tp);
3999 }
4000
4001 return 0;
4002}
4003
747e8f8b
MC		 4004static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4005{
4006 int current_link_up, err = 0;
4007 u32 bmsr, bmcr;
4008 u16 current_speed;
4009 u8 current_duplex;
ef167e27 4010 u32 local_adv, remote_adv;
747e8f8b
MC		 4011
4012 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4013 tw32_f(MAC_MODE, tp->mac_mode);
4014 udelay(40);
4015
4016 tw32(MAC_EVENT, 0);
4017
4018 tw32_f(MAC_STATUS,
4019 (MAC_STATUS_SYNC_CHANGED |
4020 MAC_STATUS_CFG_CHANGED |
4021 MAC_STATUS_MI_COMPLETION |
4022 MAC_STATUS_LNKSTATE_CHANGED));
4023 udelay(40);
4024
4025 if (force_reset)
4026 tg3_phy_reset(tp);
4027
4028 current_link_up = 0;
4029 current_speed = SPEED_INVALID;
4030 current_duplex = DUPLEX_INVALID;
4031
4032 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4033 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4035 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4036 bmsr |= BMSR_LSTATUS;
4037 else
4038 bmsr &= ~BMSR_LSTATUS;
4039 }
747e8f8b
MC		 4040
4041 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4042
4043 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4044 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4045 /* do nothing, just check for link up at the end */
4046 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4047 u32 adv, new_adv;
4048
4049 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4050 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4051 ADVERTISE_1000XPAUSE |
4052 ADVERTISE_1000XPSE_ASYM |
4053 ADVERTISE_SLCT);
4054
ba4d07a8 4055 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4056
4057 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4058 new_adv |= ADVERTISE_1000XHALF;
4059 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4060 new_adv |= ADVERTISE_1000XFULL;
4061
4062 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4063 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4064 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4065 tg3_writephy(tp, MII_BMCR, bmcr);
4066
4067 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4068 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4069 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4070
4071 return err;
4072 }
4073 } else {
4074 u32 new_bmcr;
4075
4076 bmcr &= ~BMCR_SPEED1000;
4077 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4078
4079 if (tp->link_config.duplex == DUPLEX_FULL)
4080 new_bmcr |= BMCR_FULLDPLX;
4081
4082 if (new_bmcr != bmcr) {
4083 /* BMCR_SPEED1000 is a reserved bit that needs
4084 * to be set on write.
4085 */
4086 new_bmcr |= BMCR_SPEED1000;
4087
4088 /* Force a linkdown */
4089 if (netif_carrier_ok(tp->dev)) {
4090 u32 adv;
4091
4092 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4093 adv &= ~(ADVERTISE_1000XFULL |
4094 ADVERTISE_1000XHALF |
4095 ADVERTISE_SLCT);
4096 tg3_writephy(tp, MII_ADVERTISE, adv);
4097 tg3_writephy(tp, MII_BMCR, bmcr |
4098 BMCR_ANRESTART |
4099 BMCR_ANENABLE);
4100 udelay(10);
4101 netif_carrier_off(tp->dev);
4102 }
4103 tg3_writephy(tp, MII_BMCR, new_bmcr);
4104 bmcr = new_bmcr;
4105 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4106 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4107 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4108 ASIC_REV_5714) {
4109 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4110 bmsr |= BMSR_LSTATUS;
4111 else
4112 bmsr &= ~BMSR_LSTATUS;
4113 }
747e8f8b
MC		 4114 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4115 }
4116 }
4117
4118 if (bmsr & BMSR_LSTATUS) {
4119 current_speed = SPEED_1000;
4120 current_link_up = 1;
4121 if (bmcr & BMCR_FULLDPLX)
4122 current_duplex = DUPLEX_FULL;
4123 else
4124 current_duplex = DUPLEX_HALF;
4125
ef167e27
MC		 4126 local_adv = 0;
4127 remote_adv = 0;
4128
747e8f8b 4129 if (bmcr & BMCR_ANENABLE) {
ef167e27 4130 u32 common;
747e8f8b
MC		 4131
4132 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4133 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4134 common = local_adv & remote_adv;
4135 if (common & (ADVERTISE_1000XHALF |
4136 ADVERTISE_1000XFULL)) {
4137 if (common & ADVERTISE_1000XFULL)
4138 current_duplex = DUPLEX_FULL;
4139 else
4140 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4141 }
4142 else
4143 current_link_up = 0;
4144 }
4145 }
4146
ef167e27
MC		 4147 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4148 tg3_setup_flow_control(tp, local_adv, remote_adv);
4149
747e8f8b
MC		 4150 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4151 if (tp->link_config.active_duplex == DUPLEX_HALF)
4152 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4153
4154 tw32_f(MAC_MODE, tp->mac_mode);
4155 udelay(40);
4156
4157 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4158
4159 tp->link_config.active_speed = current_speed;
4160 tp->link_config.active_duplex = current_duplex;
4161
4162 if (current_link_up != netif_carrier_ok(tp->dev)) {
4163 if (current_link_up)
4164 netif_carrier_on(tp->dev);
4165 else {
4166 netif_carrier_off(tp->dev);
4167 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4168 }
4169 tg3_link_report(tp);
4170 }
4171 return err;
4172}
4173
4174static void tg3_serdes_parallel_detect(struct tg3 *tp)
4175{
3d3ebe74 4176 if (tp->serdes_counter) {
747e8f8b 4177 /* Give autoneg time to complete. */
3d3ebe74 4178 tp->serdes_counter--;
747e8f8b
MC		 4179 return;
4180 }
4181 if (!netif_carrier_ok(tp->dev) &&
4182 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4183 u32 bmcr;
4184
4185 tg3_readphy(tp, MII_BMCR, &bmcr);
4186 if (bmcr & BMCR_ANENABLE) {
4187 u32 phy1, phy2;
4188
4189 /* Select shadow register 0x1f */
4190 tg3_writephy(tp, 0x1c, 0x7c00);
4191 tg3_readphy(tp, 0x1c, &phy1);
4192
4193 /* Select expansion interrupt status register */
4194 tg3_writephy(tp, 0x17, 0x0f01);
4195 tg3_readphy(tp, 0x15, &phy2);
4196 tg3_readphy(tp, 0x15, &phy2);
4197
4198 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4199 /* We have signal detect and not receiving
4200 * config code words, link is up by parallel
4201 * detection.
4202 */
4203
4204 bmcr &= ~BMCR_ANENABLE;
4205 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4206 tg3_writephy(tp, MII_BMCR, bmcr);
4207 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4208 }
4209 }
4210 }
4211 else if (netif_carrier_ok(tp->dev) &&
4212 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4213 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4214 u32 phy2;
4215
4216 /* Select expansion interrupt status register */
4217 tg3_writephy(tp, 0x17, 0x0f01);
4218 tg3_readphy(tp, 0x15, &phy2);
4219 if (phy2 & 0x20) {
4220 u32 bmcr;
4221
4222 /* Config code words received, turn on autoneg. */
4223 tg3_readphy(tp, MII_BMCR, &bmcr);
4224 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4225
4226 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4227
4228 }
4229 }
4230}
4231
1da177e4
LT		 4232static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4233{
4234 int err;
4235
4236 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4237 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4238 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4239 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4240 } else {
4241 err = tg3_setup_copper_phy(tp, force_reset);
4242 }
4243
bcb37f6c 4244 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4245 u32 val, scale;
4246
4247 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4248 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4249 scale = 65;
4250 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4251 scale = 6;
4252 else
4253 scale = 12;
4254
4255 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4256 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4257 tw32(GRC_MISC_CFG, val);
4258 }
4259
1da177e4
LT		 4260 if (tp->link_config.active_speed == SPEED_1000 &&
4261 tp->link_config.active_duplex == DUPLEX_HALF)
4262 tw32(MAC_TX_LENGTHS,
4263 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4264 (6 << TX_LENGTHS_IPG_SHIFT) |
4265 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4266 else
4267 tw32(MAC_TX_LENGTHS,
4268 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4269 (6 << TX_LENGTHS_IPG_SHIFT) |
4270 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4271
4272 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4273 if (netif_carrier_ok(tp->dev)) {
4274 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4275 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4276 } else {
4277 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4278 }
4279 }
4280
8ed5d97e
MC		 4281 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4282 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4283 if (!netif_carrier_ok(tp->dev))
4284 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4285 tp->pwrmgmt_thresh;
4286 else
4287 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4288 tw32(PCIE_PWR_MGMT_THRESH, val);
4289 }
4290
1da177e4
LT		 4291 return err;
4292}
4293
df3e6548
MC		 4294/* This is called whenever we suspect that the system chipset is re-
4295 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4296 * is bogus tx completions. We try to recover by setting the
4297 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4298 * in the workqueue.
4299 */
4300static void tg3_tx_recover(struct tg3 *tp)
4301{
4302 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4303 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4304
4305 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4306 "mapped I/O cycles to the network device, attempting to "
4307 "recover. Please report the problem to the driver maintainer "
4308 "and include system chipset information.\n", tp->dev->name);
4309
4310 spin_lock(&tp->lock);
df3e6548 4311 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4312 spin_unlock(&tp->lock);
4313}
4314
f3f3f27e 4315static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4316{
4317 smp_mb();
f3f3f27e
MC		 4318 return tnapi->tx_pending -
4319 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4320}
4321
1da177e4
LT		 4322/* Tigon3 never reports partial packet sends. So we do not
4323 * need special logic to handle SKBs that have not had all
4324 * of their frags sent yet, like SunGEM does.
4325 */
17375d25 4326static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4327{
17375d25 4328 struct tg3 *tp = tnapi->tp;
898a56f8 4329 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4330 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4331 struct netdev_queue *txq;
4332 int index = tnapi - tp->napi;
4333
4334 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4335 index--;
4336
4337 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4338
4339 while (sw_idx != hw_idx) {
f3f3f27e 4340 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4341 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4342 int i, tx_bug = 0;
4343
4344 if (unlikely(skb == NULL)) {
4345 tg3_tx_recover(tp);
4346 return;
4347 }
1da177e4 4348
90079ce8 4349 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4350
4351 ri->skb = NULL;
4352
4353 sw_idx = NEXT_TX(sw_idx);
4354
4355 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4356 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4357 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4358 tx_bug = 1;
1da177e4
LT		 4359 sw_idx = NEXT_TX(sw_idx);
4360 }
4361
f47c11ee 4362 dev_kfree_skb(skb);
df3e6548
MC		 4363
4364 if (unlikely(tx_bug)) {
4365 tg3_tx_recover(tp);
4366 return;
4367 }
1da177e4
LT		 4368 }
4369
f3f3f27e 4370 tnapi->tx_cons = sw_idx;
1da177e4 4371
1b2a7205
MC		 4372 /* Need to make the tx_cons update visible to tg3_start_xmit()
4373 * before checking for netif_queue_stopped(). Without the
4374 * memory barrier, there is a small possibility that tg3_start_xmit()
4375 * will miss it and cause the queue to be stopped forever.
4376 */
4377 smp_mb();
4378
fe5f5787 4379 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4380 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4381 __netif_tx_lock(txq, smp_processor_id());
4382 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4383 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4384 netif_tx_wake_queue(txq);
4385 __netif_tx_unlock(txq);
51b91468 4386 }
1da177e4
LT		 4387}
4388
4389/* Returns size of skb allocated or < 0 on error.
4390 *
4391 * We only need to fill in the address because the other members
4392 * of the RX descriptor are invariant, see tg3_init_rings.
4393 *
4394 * Note the purposeful assymetry of cpu vs. chip accesses. For
4395 * posting buffers we only dirty the first cache line of the RX
4396 * descriptor (containing the address). Whereas for the RX status
4397 * buffers the cpu only reads the last cacheline of the RX descriptor
4398 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4399 */
17375d25 4400static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4401 int src_idx, u32 dest_idx_unmasked)
4402{
17375d25 4403 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4404 struct tg3_rx_buffer_desc *desc;
4405 struct ring_info *map, *src_map;
4406 struct sk_buff *skb;
4407 dma_addr_t mapping;
4408 int skb_size, dest_idx;
21f581a5 4409 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4410
4411 src_map = NULL;
4412 switch (opaque_key) {
4413 case RXD_OPAQUE_RING_STD:
4414 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4415 desc = &tpr->rx_std[dest_idx];
4416 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4417 if (src_idx >= 0)
21f581a5 4418 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4419 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4420 break;
4421
4422 case RXD_OPAQUE_RING_JUMBO:
4423 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4424 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4425 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4426 if (src_idx >= 0)
21f581a5 4427 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4428 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4429 break;
4430
4431 default:
4432 return -EINVAL;
855e1111 4433 }
1da177e4
LT		 4434
4435 /* Do not overwrite any of the map or rp information
4436 * until we are sure we can commit to a new buffer.
4437 *
4438 * Callers depend upon this behavior and assume that
4439 * we leave everything unchanged if we fail.
4440 */
287be12e 4441 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4442 if (skb == NULL)
4443 return -ENOMEM;
4444
1da177e4
LT		 4445 skb_reserve(skb, tp->rx_offset);
4446
287be12e 4447 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4448 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4449 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4450 dev_kfree_skb(skb);
4451 return -EIO;
4452 }
1da177e4
LT		 4453
4454 map->skb = skb;
4455 pci_unmap_addr_set(map, mapping, mapping);
4456
4457 if (src_map != NULL)
4458 src_map->skb = NULL;
4459
4460 desc->addr_hi = ((u64)mapping >> 32);
4461 desc->addr_lo = ((u64)mapping & 0xffffffff);
4462
4463 return skb_size;
4464}
4465
4466/* We only need to move over in the address because the other
4467 * members of the RX descriptor are invariant. See notes above
4468 * tg3_alloc_rx_skb for full details.
4469 */
17375d25 4470static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4471 int src_idx, u32 dest_idx_unmasked)
4472{
17375d25 4473 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4474 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4475 struct ring_info *src_map, *dest_map;
4476 int dest_idx;
21f581a5 4477 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4478
4479 switch (opaque_key) {
4480 case RXD_OPAQUE_RING_STD:
4481 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4482 dest_desc = &tpr->rx_std[dest_idx];
4483 dest_map = &tpr->rx_std_buffers[dest_idx];
4484 src_desc = &tpr->rx_std[src_idx];
4485 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4486 break;
4487
4488 case RXD_OPAQUE_RING_JUMBO:
4489 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4490 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4491 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4492 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4493 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4494 break;
4495
4496 default:
4497 return;
855e1111 4498 }
1da177e4
LT		 4499
4500 dest_map->skb = src_map->skb;
4501 pci_unmap_addr_set(dest_map, mapping,
4502 pci_unmap_addr(src_map, mapping));
4503 dest_desc->addr_hi = src_desc->addr_hi;
4504 dest_desc->addr_lo = src_desc->addr_lo;
4505
4506 src_map->skb = NULL;
4507}
4508
1da177e4
LT		 4509/* The RX ring scheme is composed of multiple rings which post fresh
4510 * buffers to the chip, and one special ring the chip uses to report
4511 * status back to the host.
4512 *
4513 * The special ring reports the status of received packets to the
4514 * host. The chip does not write into the original descriptor the
4515 * RX buffer was obtained from. The chip simply takes the original
4516 * descriptor as provided by the host, updates the status and length
4517 * field, then writes this into the next status ring entry.
4518 *
4519 * Each ring the host uses to post buffers to the chip is described
4520 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4521 * it is first placed into the on-chip ram. When the packet's length
4522 * is known, it walks down the TG3_BDINFO entries to select the ring.
4523 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4524 * which is within the range of the new packet's length is chosen.
4525 *
4526 * The "separate ring for rx status" scheme may sound queer, but it makes
4527 * sense from a cache coherency perspective. If only the host writes
4528 * to the buffer post rings, and only the chip writes to the rx status
4529 * rings, then cache lines never move beyond shared-modified state.
4530 * If both the host and chip were to write into the same ring, cache line
4531 * eviction could occur since both entities want it in an exclusive state.
4532 */
17375d25 4533static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4534{
17375d25 4535 struct tg3 *tp = tnapi->tp;
f92905de 4536 u32 work_mask, rx_std_posted = 0;
72334482 4537 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4538 u16 hw_idx;
1da177e4 4539 int received;
21f581a5 4540 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4541
8d9d7cfc 4542 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4543 /*
4544 * We need to order the read of hw_idx and the read of
4545 * the opaque cookie.
4546 */
4547 rmb();
1da177e4
LT		 4548 work_mask = 0;
4549 received = 0;
4550 while (sw_idx != hw_idx && budget > 0) {
72334482 4551 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4552 unsigned int len;
4553 struct sk_buff *skb;
4554 dma_addr_t dma_addr;
4555 u32 opaque_key, desc_idx, *post_ptr;
4556
4557 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4558 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4559 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4560 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4561 dma_addr = pci_unmap_addr(ri, mapping);
4562 skb = ri->skb;
4563 post_ptr = &tpr->rx_std_ptr;
f92905de 4564 rx_std_posted++;
1da177e4 4565 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4566 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4567 dma_addr = pci_unmap_addr(ri, mapping);
4568 skb = ri->skb;
4569 post_ptr = &tpr->rx_jmb_ptr;
4570 } else
1da177e4 4571 goto next_pkt_nopost;
1da177e4
LT		 4572
4573 work_mask |= opaque_key;
4574
4575 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4576 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4577 drop_it:
17375d25 4578 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4579 desc_idx, *post_ptr);
4580 drop_it_no_recycle:
4581 /* Other statistics kept track of by card. */
4582 tp->net_stats.rx_dropped++;
4583 goto next_pkt;
4584 }
4585
ad829268
MC		 4586 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4587 ETH_FCS_LEN;
1da177e4 4588
6aa20a22 4589 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4590 && tp->rx_offset == NET_IP_ALIGN
4591 /* rx_offset will likely not equal NET_IP_ALIGN
4592 * if this is a 5701 card running in PCI-X mode
4593 * [see tg3_get_invariants()]
4594 */
1da177e4
LT		 4595 ) {
4596 int skb_size;
4597
17375d25 4598 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4599 desc_idx, *post_ptr);
4600 if (skb_size < 0)
4601 goto drop_it;
4602
287be12e 4603 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4604 PCI_DMA_FROMDEVICE);
4605
4606 skb_put(skb, len);
4607 } else {
4608 struct sk_buff *copy_skb;
4609
17375d25 4610 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4611 desc_idx, *post_ptr);
4612
ad829268
MC		 4613 copy_skb = netdev_alloc_skb(tp->dev,
4614 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4615 if (copy_skb == NULL)
4616 goto drop_it_no_recycle;
4617
ad829268 4618 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4619 skb_put(copy_skb, len);
4620 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4621 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4622 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4623
4624 /* We'll reuse the original ring buffer. */
4625 skb = copy_skb;
4626 }
4627
4628 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4629 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4630 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4631 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4632 skb->ip_summed = CHECKSUM_UNNECESSARY;
4633 else
4634 skb->ip_summed = CHECKSUM_NONE;
4635
4636 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4637
4638 if (len > (tp->dev->mtu + ETH_HLEN) &&
4639 skb->protocol != htons(ETH_P_8021Q)) {
4640 dev_kfree_skb(skb);
4641 goto next_pkt;
4642 }
4643
1da177e4
LT		 4644#if TG3_VLAN_TAG_USED
4645 if (tp->vlgrp != NULL &&
4646 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4647 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4648 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4649 } else
4650#endif
17375d25 4651 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4652
1da177e4
LT		 4653 received++;
4654 budget--;
4655
4656next_pkt:
4657 (*post_ptr)++;
f92905de
MC		 4658
4659 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4660 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4661
4662 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4663 TG3_64BIT_REG_LOW, idx);
4664 work_mask &= ~RXD_OPAQUE_RING_STD;
4665 rx_std_posted = 0;
4666 }
1da177e4 4667next_pkt_nopost:
483ba50b 4668 sw_idx++;
6b31a515 4669 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4670
4671 /* Refresh hw_idx to see if there is new work */
4672 if (sw_idx == hw_idx) {
8d9d7cfc 4673 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4674 rmb();
4675 }
1da177e4
LT		 4676 }
4677
4678 /* ACK the status ring. */
72334482
MC		 4679 tnapi->rx_rcb_ptr = sw_idx;
4680 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4681
4682 /* Refill RX ring(s). */
4683 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4684 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4685 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4686 sw_idx);
4687 }
4688 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4689 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4690 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4691 sw_idx);
4692 }
4693 mmiowb();
4694
4695 return received;
4696}
4697
17375d25 4698static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4699{
17375d25 4700 struct tg3 *tp = tnapi->tp;
898a56f8 4701 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4702
1da177e4
LT		 4703 /* handle link change and other phy events */
4704 if (!(tp->tg3_flags &
4705 (TG3_FLAG_USE_LINKCHG_REG |
4706 TG3_FLAG_POLL_SERDES))) {
4707 if (sblk->status & SD_STATUS_LINK_CHG) {
4708 sblk->status = SD_STATUS_UPDATED |
4709 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4710 spin_lock(&tp->lock);
dd477003
MC		 4711 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4712 tw32_f(MAC_STATUS,
4713 (MAC_STATUS_SYNC_CHANGED |
4714 MAC_STATUS_CFG_CHANGED |
4715 MAC_STATUS_MI_COMPLETION |
4716 MAC_STATUS_LNKSTATE_CHANGED));
4717 udelay(40);
4718 } else
4719 tg3_setup_phy(tp, 0);
f47c11ee 4720 spin_unlock(&tp->lock);
1da177e4
LT		 4721 }
4722 }
4723
4724 /* run TX completion thread */
f3f3f27e 4725 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4726 tg3_tx(tnapi);
6f535763 4727 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4728 return work_done;
1da177e4
LT		 4729 }
4730
1da177e4
LT		 4731 /* run RX thread, within the bounds set by NAPI.
4732 * All RX "locking" is done by ensuring outside
bea3348e 4733 * code synchronizes with tg3->napi.poll()
1da177e4 4734 */
8d9d7cfc 4735 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4736 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4737
6f535763
DM		 4738 return work_done;
4739}
4740
4741static int tg3_poll(struct napi_struct *napi, int budget)
4742{
8ef0442f
MC		 4743 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4744 struct tg3 *tp = tnapi->tp;
6f535763 4745 int work_done = 0;
898a56f8 4746 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4747
4748 while (1) {
17375d25 4749 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4750
4751 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4752 goto tx_recovery;
4753
4754 if (unlikely(work_done >= budget))
4755 break;
4756
4fd7ab59 4757 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4758 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4759 * to tell the hw how much work has been processed,
4760 * so we must read it before checking for more work.
4761 */
898a56f8
MC		 4762 tnapi->last_tag = sblk->status_tag;
4763 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4764 rmb();
4765 } else
4766 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4767
17375d25 4768 if (likely(!tg3_has_work(tnapi))) {
288379f0 4769 napi_complete(napi);
17375d25 4770 tg3_int_reenable(tnapi);
6f535763
DM		 4771 break;
4772 }
1da177e4
LT		 4773 }
4774
bea3348e 4775 return work_done;
6f535763
DM		 4776
4777tx_recovery:
4fd7ab59 4778 /* work_done is guaranteed to be less than budget. */
288379f0 4779 napi_complete(napi);
6f535763 4780 schedule_work(&tp->reset_task);
4fd7ab59 4781 return work_done;
1da177e4
LT		 4782}
4783
f47c11ee
DM		 4784static void tg3_irq_quiesce(struct tg3 *tp)
4785{
4f125f42
MC		 4786 int i;
4787
f47c11ee
DM		 4788 BUG_ON(tp->irq_sync);
4789
4790 tp->irq_sync = 1;
4791 smp_mb();
4792
4f125f42
MC		 4793 for (i = 0; i < tp->irq_cnt; i++)
4794 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4795}
4796
4797static inline int tg3_irq_sync(struct tg3 *tp)
4798{
4799 return tp->irq_sync;
4800}
4801
4802/* Fully shutdown all tg3 driver activity elsewhere in the system.
4803 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4804 * with as well. Most of the time, this is not necessary except when
4805 * shutting down the device.
4806 */
4807static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4808{
46966545 4809 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4810 if (irq_sync)
4811 tg3_irq_quiesce(tp);
f47c11ee
DM		 4812}
4813
4814static inline void tg3_full_unlock(struct tg3 *tp)
4815{
f47c11ee
DM		 4816 spin_unlock_bh(&tp->lock);
4817}
4818
fcfa0a32
MC		 4819/* One-shot MSI handler - Chip automatically disables interrupt
4820 * after sending MSI so driver doesn't have to do it.
4821 */
7d12e780 4822static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4823{
09943a18
MC		 4824 struct tg3_napi *tnapi = dev_id;
4825 struct tg3 *tp = tnapi->tp;
fcfa0a32 4826
898a56f8 4827 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4828 if (tnapi->rx_rcb)
4829 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4830
4831 if (likely(!tg3_irq_sync(tp)))
09943a18 4832 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4833
4834 return IRQ_HANDLED;
4835}
4836
88b06bc2
MC		 4837/* MSI ISR - No need to check for interrupt sharing and no need to
4838 * flush status block and interrupt mailbox. PCI ordering rules
4839 * guarantee that MSI will arrive after the status block.
4840 */
7d12e780 4841static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4842{
09943a18
MC		 4843 struct tg3_napi *tnapi = dev_id;
4844 struct tg3 *tp = tnapi->tp;
88b06bc2 4845
898a56f8 4846 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4847 if (tnapi->rx_rcb)
4848 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4849 /*
fac9b83e 4850 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4851 * chip-internal interrupt pending events.
fac9b83e 4852 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4853 * NIC to stop sending us irqs, engaging "in-intr-handler"
4854 * event coalescing.
4855 */
4856 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4857 if (likely(!tg3_irq_sync(tp)))
09943a18 4858 napi_schedule(&tnapi->napi);
61487480 4859
88b06bc2
MC		 4860 return IRQ_RETVAL(1);
4861}
4862
7d12e780 4863static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4864{
09943a18
MC		 4865 struct tg3_napi *tnapi = dev_id;
4866 struct tg3 *tp = tnapi->tp;
898a56f8 4867 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4868 unsigned int handled = 1;
4869
1da177e4
LT		 4870 /* In INTx mode, it is possible for the interrupt to arrive at
4871 * the CPU before the status block posted prior to the interrupt.
4872 * Reading the PCI State register will confirm whether the
4873 * interrupt is ours and will flush the status block.
4874 */
d18edcb2
MC		 4875 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4876 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4877 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4878 handled = 0;
f47c11ee 4879 goto out;
fac9b83e 4880 }
d18edcb2
MC		 4881 }
4882
4883 /*
4884 * Writing any value to intr-mbox-0 clears PCI INTA# and
4885 * chip-internal interrupt pending events.
4886 * Writing non-zero to intr-mbox-0 additional tells the
4887 * NIC to stop sending us irqs, engaging "in-intr-handler"
4888 * event coalescing.
c04cb347
MC		 4889 *
4890 * Flush the mailbox to de-assert the IRQ immediately to prevent
4891 * spurious interrupts. The flush impacts performance but
4892 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4893 */
c04cb347 4894 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4895 if (tg3_irq_sync(tp))
4896 goto out;
4897 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4898 if (likely(tg3_has_work(tnapi))) {
72334482 4899 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4900 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4901 } else {
4902 /* No work, shared interrupt perhaps? re-enable
4903 * interrupts, and flush that PCI write
4904 */
4905 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4906 0x00000000);
fac9b83e 4907 }
f47c11ee 4908out:
fac9b83e
DM		 4909 return IRQ_RETVAL(handled);
4910}
4911
7d12e780 4912static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4913{
09943a18
MC		 4914 struct tg3_napi *tnapi = dev_id;
4915 struct tg3 *tp = tnapi->tp;
898a56f8 4916 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4917 unsigned int handled = 1;
4918
fac9b83e
DM		 4919 /* In INTx mode, it is possible for the interrupt to arrive at
4920 * the CPU before the status block posted prior to the interrupt.
4921 * Reading the PCI State register will confirm whether the
4922 * interrupt is ours and will flush the status block.
4923 */
898a56f8 4924 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4925 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4926 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4927 handled = 0;
f47c11ee 4928 goto out;
1da177e4 4929 }
d18edcb2
MC		 4930 }
4931
4932 /*
4933 * writing any value to intr-mbox-0 clears PCI INTA# and
4934 * chip-internal interrupt pending events.
4935 * writing non-zero to intr-mbox-0 additional tells the
4936 * NIC to stop sending us irqs, engaging "in-intr-handler"
4937 * event coalescing.
c04cb347
MC		 4938 *
4939 * Flush the mailbox to de-assert the IRQ immediately to prevent
4940 * spurious interrupts. The flush impacts performance but
4941 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4942 */
c04cb347 4943 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4944
4945 /*
4946 * In a shared interrupt configuration, sometimes other devices'
4947 * interrupts will scream. We record the current status tag here
4948 * so that the above check can report that the screaming interrupts
4949 * are unhandled. Eventually they will be silenced.
4950 */
898a56f8 4951 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4952
d18edcb2
MC		 4953 if (tg3_irq_sync(tp))
4954 goto out;
624f8e50 4955
72334482 4956 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4957
09943a18 4958 napi_schedule(&tnapi->napi);
624f8e50 4959
f47c11ee 4960out:
1da177e4
LT		 4961 return IRQ_RETVAL(handled);
4962}
4963
7938109f 4964/* ISR for interrupt test */
7d12e780 4965static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4966{
09943a18
MC		 4967 struct tg3_napi *tnapi = dev_id;
4968 struct tg3 *tp = tnapi->tp;
898a56f8 4969 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4970
f9804ddb
MC		 4971 if ((sblk->status & SD_STATUS_UPDATED) ||
4972 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4973 tg3_disable_ints(tp);
7938109f
MC		 4974 return IRQ_RETVAL(1);
4975 }
4976 return IRQ_RETVAL(0);
4977}
4978
8e7a22e3 4979static int tg3_init_hw(struct tg3 *, int);
944d980e 4980static int tg3_halt(struct tg3 *, int, int);
1da177e4 4981
b9ec6c1b
MC		 4982/* Restart hardware after configuration changes, self-test, etc.
4983 * Invoked with tp->lock held.
4984 */
4985static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4986 __releases(tp->lock)
4987 __acquires(tp->lock)
b9ec6c1b
MC		 4988{
4989 int err;
4990
4991 err = tg3_init_hw(tp, reset_phy);
4992 if (err) {
4993 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4994 "aborting.\n", tp->dev->name);
4995 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4996 tg3_full_unlock(tp);
4997 del_timer_sync(&tp->timer);
4998 tp->irq_sync = 0;
fed97810 4999 tg3_napi_enable(tp);
b9ec6c1b
MC		 5000 dev_close(tp->dev);
5001 tg3_full_lock(tp, 0);
5002 }
5003 return err;
5004}
5005
1da177e4
LT		 5006#ifdef CONFIG_NET_POLL_CONTROLLER
5007static void tg3_poll_controller(struct net_device *dev)
5008{
4f125f42 5009 int i;
88b06bc2
MC		 5010 struct tg3 *tp = netdev_priv(dev);
5011
4f125f42
MC		 5012 for (i = 0; i < tp->irq_cnt; i++)
5013 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5014}
5015#endif
5016
c4028958 5017static void tg3_reset_task(struct work_struct *work)
1da177e4 5018{
c4028958 5019 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5020 int err;
1da177e4
LT		 5021 unsigned int restart_timer;
5022
7faa006f 5023 tg3_full_lock(tp, 0);
7faa006f
MC		 5024
5025 if (!netif_running(tp->dev)) {
7faa006f
MC		 5026 tg3_full_unlock(tp);
5027 return;
5028 }
5029
5030 tg3_full_unlock(tp);
5031
b02fd9e3
MC		 5032 tg3_phy_stop(tp);
5033
1da177e4
LT		 5034 tg3_netif_stop(tp);
5035
f47c11ee 5036 tg3_full_lock(tp, 1);
1da177e4
LT		 5037
5038 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5039 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5040
df3e6548
MC		 5041 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5042 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5043 tp->write32_rx_mbox = tg3_write_flush_reg32;
5044 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5045 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5046 }
5047
944d980e 5048 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5049 err = tg3_init_hw(tp, 1);
5050 if (err)
b9ec6c1b 5051 goto out;
1da177e4
LT		 5052
5053 tg3_netif_start(tp);
5054
1da177e4
LT		 5055 if (restart_timer)
5056 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5057
b9ec6c1b 5058out:
7faa006f 5059 tg3_full_unlock(tp);
b02fd9e3
MC		 5060
5061 if (!err)
5062 tg3_phy_start(tp);
1da177e4
LT		 5063}
5064
b0408751
MC		 5065static void tg3_dump_short_state(struct tg3 *tp)
5066{
5067 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5068 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5069 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5070 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5071}
5072
1da177e4
LT		 5073static void tg3_tx_timeout(struct net_device *dev)
5074{
5075 struct tg3 *tp = netdev_priv(dev);
5076
b0408751 5077 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5078 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5079 dev->name);
b0408751
MC		 5080 tg3_dump_short_state(tp);
5081 }
1da177e4
LT		 5082
5083 schedule_work(&tp->reset_task);
5084}
5085
c58ec932
MC		 5086/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5087static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5088{
5089 u32 base = (u32) mapping & 0xffffffff;
5090
5091 return ((base > 0xffffdcc0) &&
5092 (base + len + 8 < base));
5093}
5094
72f2afb8
MC		 5095/* Test for DMA addresses > 40-bit */
5096static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5097 int len)
5098{
5099#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5100 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5101 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5102 return 0;
5103#else
5104 return 0;
5105#endif
5106}
5107
f3f3f27e 5108static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5109
72f2afb8
MC		 5110/* Workaround 4GB and 40-bit hardware DMA bugs. */
5111static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5112 u32 last_plus_one, u32 *start,
5113 u32 base_flags, u32 mss)
1da177e4 5114{
f3f3f27e 5115 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5116 struct sk_buff *new_skb;
c58ec932 5117 dma_addr_t new_addr = 0;
1da177e4 5118 u32 entry = *start;
c58ec932 5119 int i, ret = 0;
1da177e4 5120
41588ba1
MC		 5121 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5122 new_skb = skb_copy(skb, GFP_ATOMIC);
5123 else {
5124 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5125
5126 new_skb = skb_copy_expand(skb,
5127 skb_headroom(skb) + more_headroom,
5128 skb_tailroom(skb), GFP_ATOMIC);
5129 }
5130
1da177e4 5131 if (!new_skb) {
c58ec932
MC		 5132 ret = -1;
5133 } else {
5134 /* New SKB is guaranteed to be linear. */
5135 entry = *start;
90079ce8 5136 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5137 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5138
c58ec932
MC		 5139 /* Make sure new skb does not cross any 4G boundaries.
5140 * Drop the packet if it does.
5141 */
0e1406dd
MC		 5142 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5143 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5144 if (!ret)
5145 skb_dma_unmap(&tp->pdev->dev, new_skb,
5146 DMA_TO_DEVICE);
c58ec932
MC		 5147 ret = -1;
5148 dev_kfree_skb(new_skb);
5149 new_skb = NULL;
5150 } else {
f3f3f27e 5151 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5152 base_flags, 1 | (mss << 1));
5153 *start = NEXT_TX(entry);
5154 }
1da177e4
LT		 5155 }
5156
1da177e4
LT		 5157 /* Now clean up the sw ring entries. */
5158 i = 0;
5159 while (entry != last_plus_one) {
f3f3f27e
MC		 5160 if (i == 0)
5161 tnapi->tx_buffers[entry].skb = new_skb;
5162 else
5163 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5164 entry = NEXT_TX(entry);
5165 i++;
5166 }
5167
90079ce8 5168 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5169 dev_kfree_skb(skb);
5170
c58ec932 5171 return ret;
1da177e4
LT		 5172}
5173
f3f3f27e 5174static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5175 dma_addr_t mapping, int len, u32 flags,
5176 u32 mss_and_is_end)
5177{
f3f3f27e 5178 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5179 int is_end = (mss_and_is_end & 0x1);
5180 u32 mss = (mss_and_is_end >> 1);
5181 u32 vlan_tag = 0;
5182
5183 if (is_end)
5184 flags |= TXD_FLAG_END;
5185 if (flags & TXD_FLAG_VLAN) {
5186 vlan_tag = flags >> 16;
5187 flags &= 0xffff;
5188 }
5189 vlan_tag |= (mss << TXD_MSS_SHIFT);
5190
5191 txd->addr_hi = ((u64) mapping >> 32);
5192 txd->addr_lo = ((u64) mapping & 0xffffffff);
5193 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5194 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5195}
5196
5a6f3074
MC		 5197/* hard_start_xmit for devices that don't have any bugs and
5198 * support TG3_FLG2_HW_TSO_2 only.
5199 */
61357325
SH		 5200static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5201 struct net_device *dev)
5a6f3074
MC		 5202{
5203 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5204 u32 len, entry, base_flags, mss;
90079ce8
DM		 5205 struct skb_shared_info *sp;
5206 dma_addr_t mapping;
fe5f5787
MC		 5207 struct tg3_napi *tnapi;
5208 struct netdev_queue *txq;
5a6f3074 5209
fe5f5787
MC		 5210 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5211 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5212 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5213 tnapi++;
5a6f3074 5214
00b70504 5215 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5216 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5217 * interrupt. Furthermore, IRQ processing runs lockless so we have
5218 * no IRQ context deadlocks to worry about either. Rejoice!
5219 */
f3f3f27e 5220 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5221 if (!netif_tx_queue_stopped(txq)) {
5222 netif_tx_stop_queue(txq);
5a6f3074
MC		 5223
5224 /* This is a hard error, log it. */
5225 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5226 "queue awake!\n", dev->name);
5227 }
5a6f3074
MC		 5228 return NETDEV_TX_BUSY;
5229 }
5230
f3f3f27e 5231 entry = tnapi->tx_prod;
5a6f3074 5232 base_flags = 0;
5a6f3074 5233 mss = 0;
c13e3713 5234 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5235 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5236 u32 hdrlen;
5a6f3074
MC		 5237
5238 if (skb_header_cloned(skb) &&
5239 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5240 dev_kfree_skb(skb);
5241 goto out_unlock;
5242 }
5243
b0026624 5244 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5245 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5246 else {
eddc9ec5
ACM		 5247 struct iphdr *iph = ip_hdr(skb);
5248
ab6a5bb6 5249 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5250 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5251
eddc9ec5
ACM		 5252 iph->check = 0;
5253 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5254 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5255 }
5a6f3074 5256
f6eb9b1f
MC		 5257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5258 mss |= (hdrlen & 0xc) << 12;
5259 if (hdrlen & 0x10)
5260 base_flags |= 0x00000010;
5261 base_flags |= (hdrlen & 0x3e0) << 5;
5262 } else
5263 mss |= hdrlen << 9;
5264
5a6f3074
MC		 5265 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5266 TXD_FLAG_CPU_POST_DMA);
5267
aa8223c7 5268 tcp_hdr(skb)->check = 0;
5a6f3074 5269
5a6f3074 5270 }
84fa7933 5271 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5272 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5273#if TG3_VLAN_TAG_USED
5274 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5275 base_flags |= (TXD_FLAG_VLAN |
5276 (vlan_tx_tag_get(skb) << 16));
5277#endif
5278
90079ce8
DM		 5279 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5280 dev_kfree_skb(skb);
5281 goto out_unlock;
5282 }
5283
5284 sp = skb_shinfo(skb);
5285
042a53a9 5286 mapping = sp->dma_head;
5a6f3074 5287
f3f3f27e 5288 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5289
fe5f5787
MC		 5290 len = skb_headlen(skb);
5291
f6eb9b1f
MC		 5292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5293 !mss && skb->len > ETH_DATA_LEN)
5294 base_flags |= TXD_FLAG_JMB_PKT;
5295
f3f3f27e 5296 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5297 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5298
5299 entry = NEXT_TX(entry);
5300
5301 /* Now loop through additional data fragments, and queue them. */
5302 if (skb_shinfo(skb)->nr_frags > 0) {
5303 unsigned int i, last;
5304
5305 last = skb_shinfo(skb)->nr_frags - 1;
5306 for (i = 0; i <= last; i++) {
5307 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5308
5309 len = frag->size;
042a53a9 5310 mapping = sp->dma_maps[i];
f3f3f27e 5311 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5312
f3f3f27e 5313 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5314 base_flags, (i == last) | (mss << 1));
5315
5316 entry = NEXT_TX(entry);
5317 }
5318 }
5319
5320 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5321 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5322
f3f3f27e
MC		 5323 tnapi->tx_prod = entry;
5324 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5325 netif_tx_stop_queue(txq);
f3f3f27e 5326 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5327 netif_tx_wake_queue(txq);
5a6f3074
MC		 5328 }
5329
5330out_unlock:
cdd0db05 5331 mmiowb();
5a6f3074
MC		 5332
5333 return NETDEV_TX_OK;
5334}
5335
61357325
SH		 5336static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5337 struct net_device *);
52c0fd83
MC		 5338
5339/* Use GSO to workaround a rare TSO bug that may be triggered when the
5340 * TSO header is greater than 80 bytes.
5341 */
5342static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5343{
5344 struct sk_buff *segs, *nskb;
f3f3f27e 5345 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5346
5347 /* Estimate the number of fragments in the worst case */
f3f3f27e 5348 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5349 netif_stop_queue(tp->dev);
f3f3f27e 5350 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5351 return NETDEV_TX_BUSY;
5352
5353 netif_wake_queue(tp->dev);
52c0fd83
MC		 5354 }
5355
5356 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5357 if (IS_ERR(segs))
52c0fd83
MC		 5358 goto tg3_tso_bug_end;
5359
5360 do {
5361 nskb = segs;
5362 segs = segs->next;
5363 nskb->next = NULL;
5364 tg3_start_xmit_dma_bug(nskb, tp->dev);
5365 } while (segs);
5366
5367tg3_tso_bug_end:
5368 dev_kfree_skb(skb);
5369
5370 return NETDEV_TX_OK;
5371}
52c0fd83 5372
5a6f3074
MC		 5373/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5374 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5375 */
61357325
SH		 5376static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5377 struct net_device *dev)
1da177e4
LT		 5378{
5379 struct tg3 *tp = netdev_priv(dev);
1da177e4 5380 u32 len, entry, base_flags, mss;
90079ce8 5381 struct skb_shared_info *sp;
1da177e4 5382 int would_hit_hwbug;
90079ce8 5383 dma_addr_t mapping;
f3f3f27e 5384 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5385
5386 len = skb_headlen(skb);
5387
00b70504 5388 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5389 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5390 * interrupt. Furthermore, IRQ processing runs lockless so we have
5391 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5392 */
f3f3f27e 5393 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5394 if (!netif_queue_stopped(dev)) {
5395 netif_stop_queue(dev);
5396
5397 /* This is a hard error, log it. */
5398 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5399 "queue awake!\n", dev->name);
5400 }
1da177e4
LT		 5401 return NETDEV_TX_BUSY;
5402 }
5403
f3f3f27e 5404 entry = tnapi->tx_prod;
1da177e4 5405 base_flags = 0;
84fa7933 5406 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5407 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5408 mss = 0;
c13e3713 5409 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5410 struct iphdr *iph;
92c6b8d1 5411 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5412
5413 if (skb_header_cloned(skb) &&
5414 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5415 dev_kfree_skb(skb);
5416 goto out_unlock;
5417 }
5418
ab6a5bb6 5419 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5420 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5421
52c0fd83
MC		 5422 hdr_len = ip_tcp_len + tcp_opt_len;
5423 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5424 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5425 return (tg3_tso_bug(tp, skb));
5426
1da177e4
LT		 5427 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5428 TXD_FLAG_CPU_POST_DMA);
5429
eddc9ec5
ACM		 5430 iph = ip_hdr(skb);
5431 iph->check = 0;
5432 iph->tot_len = htons(mss + hdr_len);
1da177e4 5433 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5434 tcp_hdr(skb)->check = 0;
1da177e4 5435 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5436 } else
5437 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5438 iph->daddr, 0,
5439 IPPROTO_TCP,
5440 0);
1da177e4 5441
92c6b8d1
MC		 5442 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5443 mss |= hdr_len << 9;
5444 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5445 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5446 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5447 int tsflags;
5448
eddc9ec5 5449 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5450 mss |= (tsflags << 11);
5451 }
5452 } else {
eddc9ec5 5453 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5454 int tsflags;
5455
eddc9ec5 5456 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5457 base_flags |= tsflags << 12;
5458 }
5459 }
5460 }
1da177e4
LT		 5461#if TG3_VLAN_TAG_USED
5462 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5463 base_flags |= (TXD_FLAG_VLAN |
5464 (vlan_tx_tag_get(skb) << 16));
5465#endif
5466
90079ce8
DM		 5467 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5468 dev_kfree_skb(skb);
5469 goto out_unlock;
5470 }
5471
5472 sp = skb_shinfo(skb);
5473
042a53a9 5474 mapping = sp->dma_head;
1da177e4 5475
f3f3f27e 5476 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5477
5478 would_hit_hwbug = 0;
5479
92c6b8d1
MC		 5480 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5481 would_hit_hwbug = 1;
5482
0e1406dd
MC		 5483 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5484 tg3_4g_overflow_test(mapping, len))
5485 would_hit_hwbug = 1;
5486
5487 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5488 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5489 would_hit_hwbug = 1;
0e1406dd
MC		 5490
5491 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5492 would_hit_hwbug = 1;
1da177e4 5493
f3f3f27e 5494 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5495 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5496
5497 entry = NEXT_TX(entry);
5498
5499 /* Now loop through additional data fragments, and queue them. */
5500 if (skb_shinfo(skb)->nr_frags > 0) {
5501 unsigned int i, last;
5502
5503 last = skb_shinfo(skb)->nr_frags - 1;
5504 for (i = 0; i <= last; i++) {
5505 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5506
5507 len = frag->size;
042a53a9 5508 mapping = sp->dma_maps[i];
1da177e4 5509
f3f3f27e 5510 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5511
92c6b8d1
MC		 5512 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5513 len <= 8)
5514 would_hit_hwbug = 1;
5515
0e1406dd
MC		 5516 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5517 tg3_4g_overflow_test(mapping, len))
c58ec932 5518 would_hit_hwbug = 1;
1da177e4 5519
0e1406dd
MC		 5520 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5521 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5522 would_hit_hwbug = 1;
5523
1da177e4 5524 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5525 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5526 base_flags, (i == last)|(mss << 1));
5527 else
f3f3f27e 5528 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5529 base_flags, (i == last));
5530
5531 entry = NEXT_TX(entry);
5532 }
5533 }
5534
5535 if (would_hit_hwbug) {
5536 u32 last_plus_one = entry;
5537 u32 start;
1da177e4 5538
c58ec932
MC		 5539 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5540 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5541
5542 /* If the workaround fails due to memory/mapping
5543 * failure, silently drop this packet.
5544 */
72f2afb8 5545 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5546 &start, base_flags, mss))
1da177e4
LT		 5547 goto out_unlock;
5548
5549 entry = start;
5550 }
5551
5552 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5553 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5554
f3f3f27e
MC		 5555 tnapi->tx_prod = entry;
5556 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5557 netif_stop_queue(dev);
f3f3f27e 5558 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5559 netif_wake_queue(tp->dev);
5560 }
1da177e4
LT		 5561
5562out_unlock:
cdd0db05 5563 mmiowb();
1da177e4
LT		 5564
5565 return NETDEV_TX_OK;
5566}
5567
5568static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5569 int new_mtu)
5570{
5571 dev->mtu = new_mtu;
5572
ef7f5ec0 5573 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5574 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5575 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5576 ethtool_op_set_tso(dev, 0);
5577 }
5578 else
5579 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5580 } else {
a4e2b347 5581 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5582 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5583 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5584 }
1da177e4
LT		 5585}
5586
5587static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5588{
5589 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5590 int err;
1da177e4
LT		 5591
5592 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5593 return -EINVAL;
5594
5595 if (!netif_running(dev)) {
5596 /* We'll just catch it later when the
5597 * device is up'd.
5598 */
5599 tg3_set_mtu(dev, tp, new_mtu);
5600 return 0;
5601 }
5602
b02fd9e3
MC		 5603 tg3_phy_stop(tp);
5604
1da177e4 5605 tg3_netif_stop(tp);
f47c11ee
DM		 5606
5607 tg3_full_lock(tp, 1);
1da177e4 5608
944d980e 5609 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5610
5611 tg3_set_mtu(dev, tp, new_mtu);
5612
b9ec6c1b 5613 err = tg3_restart_hw(tp, 0);
1da177e4 5614
b9ec6c1b
MC		 5615 if (!err)
5616 tg3_netif_start(tp);
1da177e4 5617
f47c11ee 5618 tg3_full_unlock(tp);
1da177e4 5619
b02fd9e3
MC		 5620 if (!err)
5621 tg3_phy_start(tp);
5622
b9ec6c1b 5623 return err;
1da177e4
LT		 5624}
5625
21f581a5
MC		 5626static void tg3_rx_prodring_free(struct tg3 *tp,
5627 struct tg3_rx_prodring_set *tpr)
1da177e4 5628{
1da177e4 5629 int i;
f3f3f27e 5630 struct ring_info *rxp;
1da177e4
LT		 5631
5632 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5633 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5634
5635 if (rxp->skb == NULL)
5636 continue;
1da177e4 5637
1da177e4
LT		 5638 pci_unmap_single(tp->pdev,
5639 pci_unmap_addr(rxp, mapping),
cf7a7298 5640 tp->rx_pkt_map_sz,
1da177e4
LT		 5641 PCI_DMA_FROMDEVICE);
5642 dev_kfree_skb_any(rxp->skb);
5643 rxp->skb = NULL;
5644 }
5645
cf7a7298
MC		 5646 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5647 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5648 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5649
cf7a7298
MC		 5650 if (rxp->skb == NULL)
5651 continue;
1da177e4 5652
cf7a7298
MC		 5653 pci_unmap_single(tp->pdev,
5654 pci_unmap_addr(rxp, mapping),
5655 TG3_RX_JMB_MAP_SZ,
5656 PCI_DMA_FROMDEVICE);
5657 dev_kfree_skb_any(rxp->skb);
5658 rxp->skb = NULL;
1da177e4 5659 }
1da177e4
LT		 5660 }
5661}
5662
5663/* Initialize tx/rx rings for packet processing.
5664 *
5665 * The chip has been shut down and the driver detached from
5666 * the networking, so no interrupts or new tx packets will
5667 * end up in the driver. tp->{tx,}lock are held and thus
5668 * we may not sleep.
5669 */
21f581a5
MC		 5670static int tg3_rx_prodring_alloc(struct tg3 *tp,
5671 struct tg3_rx_prodring_set *tpr)
1da177e4 5672{
287be12e 5673 u32 i, rx_pkt_dma_sz;
17375d25 5674 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5675
1da177e4 5676 /* Zero out all descriptors. */
21f581a5 5677 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5678
287be12e 5679 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5680 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5681 tp->dev->mtu > ETH_DATA_LEN)
5682 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5683 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5684
1da177e4
LT		 5685 /* Initialize invariants of the rings, we only set this
5686 * stuff once. This works because the card does not
5687 * write into the rx buffer posting rings.
5688 */
5689 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5690 struct tg3_rx_buffer_desc *rxd;
5691
21f581a5 5692 rxd = &tpr->rx_std[i];
287be12e 5693 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5694 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5695 rxd->opaque = (RXD_OPAQUE_RING_STD |
5696 (i << RXD_OPAQUE_INDEX_SHIFT));
5697 }
5698
1da177e4
LT		 5699 /* Now allocate fresh SKBs for each rx ring. */
5700 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5701 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5702 printk(KERN_WARNING PFX
5703 "%s: Using a smaller RX standard ring, "
5704 "only %d out of %d buffers were allocated "
5705 "successfully.\n",
5706 tp->dev->name, i, tp->rx_pending);
5707 if (i == 0)
cf7a7298 5708 goto initfail;
32d8c572 5709 tp->rx_pending = i;
1da177e4 5710 break;
32d8c572 5711 }
1da177e4
LT		 5712 }
5713
cf7a7298
MC		 5714 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5715 goto done;
5716
21f581a5 5717 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5718
0f893dc6 5719 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5720 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5721 struct tg3_rx_buffer_desc *rxd;
5722
79ed5ac7 5723 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5724 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5725 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5726 RXD_FLAG_JUMBO;
5727 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5728 (i << RXD_OPAQUE_INDEX_SHIFT));
5729 }
5730
1da177e4 5731 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5732 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5733 -1, i) < 0) {
5734 printk(KERN_WARNING PFX
5735 "%s: Using a smaller RX jumbo ring, "
5736 "only %d out of %d buffers were "
5737 "allocated successfully.\n",
5738 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5739 if (i == 0)
5740 goto initfail;
32d8c572 5741 tp->rx_jumbo_pending = i;
1da177e4 5742 break;
32d8c572 5743 }
1da177e4
LT		 5744 }
5745 }
cf7a7298
MC		 5746
5747done:
32d8c572 5748 return 0;
cf7a7298
MC		 5749
5750initfail:
21f581a5 5751 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5752 return -ENOMEM;
1da177e4
LT		 5753}
5754
21f581a5
MC		 5755static void tg3_rx_prodring_fini(struct tg3 *tp,
5756 struct tg3_rx_prodring_set *tpr)
1da177e4 5757{
21f581a5
MC		 5758 kfree(tpr->rx_std_buffers);
5759 tpr->rx_std_buffers = NULL;
5760 kfree(tpr->rx_jmb_buffers);
5761 tpr->rx_jmb_buffers = NULL;
5762 if (tpr->rx_std) {
1da177e4 5763 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5764 tpr->rx_std, tpr->rx_std_mapping);
5765 tpr->rx_std = NULL;
1da177e4 5766 }
21f581a5 5767 if (tpr->rx_jmb) {
1da177e4 5768 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5769 tpr->rx_jmb, tpr->rx_jmb_mapping);
5770 tpr->rx_jmb = NULL;
1da177e4 5771 }
cf7a7298
MC		 5772}
5773
21f581a5
MC		 5774static int tg3_rx_prodring_init(struct tg3 *tp,
5775 struct tg3_rx_prodring_set *tpr)
cf7a7298 5776{
21f581a5
MC		 5777 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5778 TG3_RX_RING_SIZE, GFP_KERNEL);
5779 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5780 return -ENOMEM;
5781
21f581a5
MC		 5782 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5783 &tpr->rx_std_mapping);
5784 if (!tpr->rx_std)
cf7a7298
MC		 5785 goto err_out;
5786
5787 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5788 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5789 TG3_RX_JUMBO_RING_SIZE,
5790 GFP_KERNEL);
5791 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5792 goto err_out;
5793
21f581a5
MC		 5794 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5795 TG3_RX_JUMBO_RING_BYTES,
5796 &tpr->rx_jmb_mapping);
5797 if (!tpr->rx_jmb)
cf7a7298
MC		 5798 goto err_out;
5799 }
5800
5801 return 0;
5802
5803err_out:
21f581a5 5804 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5805 return -ENOMEM;
5806}
5807
5808/* Free up pending packets in all rx/tx rings.
5809 *
5810 * The chip has been shut down and the driver detached from
5811 * the networking, so no interrupts or new tx packets will
5812 * end up in the driver. tp->{tx,}lock is not held and we are not
5813 * in an interrupt context and thus may sleep.
5814 */
5815static void tg3_free_rings(struct tg3 *tp)
5816{
f77a6a8e 5817 int i, j;
cf7a7298 5818
f77a6a8e
MC		 5819 for (j = 0; j < tp->irq_cnt; j++) {
5820 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5821
0c1d0e2b
MC		 5822 if (!tnapi->tx_buffers)
5823 continue;
5824
f77a6a8e
MC		 5825 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5826 struct tx_ring_info *txp;
5827 struct sk_buff *skb;
cf7a7298 5828
f77a6a8e
MC		 5829 txp = &tnapi->tx_buffers[i];
5830 skb = txp->skb;
cf7a7298 5831
f77a6a8e
MC		 5832 if (skb == NULL) {
5833 i++;
5834 continue;
5835 }
cf7a7298 5836
f77a6a8e 5837 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5838
f77a6a8e 5839 txp->skb = NULL;
cf7a7298 5840
f77a6a8e
MC		 5841 i += skb_shinfo(skb)->nr_frags + 1;
5842
5843 dev_kfree_skb_any(skb);
5844 }
cf7a7298
MC		 5845 }
5846
21f581a5 5847 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5848}
5849
5850/* Initialize tx/rx rings for packet processing.
5851 *
5852 * The chip has been shut down and the driver detached from
5853 * the networking, so no interrupts or new tx packets will
5854 * end up in the driver. tp->{tx,}lock are held and thus
5855 * we may not sleep.
5856 */
5857static int tg3_init_rings(struct tg3 *tp)
5858{
f77a6a8e 5859 int i;
72334482 5860
cf7a7298
MC		 5861 /* Free up all the SKBs. */
5862 tg3_free_rings(tp);
5863
f77a6a8e
MC		 5864 for (i = 0; i < tp->irq_cnt; i++) {
5865 struct tg3_napi *tnapi = &tp->napi[i];
5866
5867 tnapi->last_tag = 0;
5868 tnapi->last_irq_tag = 0;
5869 tnapi->hw_status->status = 0;
5870 tnapi->hw_status->status_tag = 0;
5871 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5872
f77a6a8e
MC		 5873 tnapi->tx_prod = 0;
5874 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5875 if (tnapi->tx_ring)
5876 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5877
5878 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5879 if (tnapi->rx_rcb)
5880 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5881 }
72334482 5882
21f581a5 5883 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5884}
5885
5886/*
5887 * Must not be invoked with interrupt sources disabled and
5888 * the hardware shutdown down.
5889 */
5890static void tg3_free_consistent(struct tg3 *tp)
5891{
f77a6a8e 5892 int i;
898a56f8 5893
f77a6a8e
MC		 5894 for (i = 0; i < tp->irq_cnt; i++) {
5895 struct tg3_napi *tnapi = &tp->napi[i];
5896
5897 if (tnapi->tx_ring) {
5898 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5899 tnapi->tx_ring, tnapi->tx_desc_mapping);
5900 tnapi->tx_ring = NULL;
5901 }
5902
5903 kfree(tnapi->tx_buffers);
5904 tnapi->tx_buffers = NULL;
5905
5906 if (tnapi->rx_rcb) {
5907 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5908 tnapi->rx_rcb,
5909 tnapi->rx_rcb_mapping);
5910 tnapi->rx_rcb = NULL;
5911 }
5912
5913 if (tnapi->hw_status) {
5914 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5915 tnapi->hw_status,
5916 tnapi->status_mapping);
5917 tnapi->hw_status = NULL;
5918 }
1da177e4 5919 }
f77a6a8e 5920
1da177e4
LT		 5921 if (tp->hw_stats) {
5922 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5923 tp->hw_stats, tp->stats_mapping);
5924 tp->hw_stats = NULL;
5925 }
f77a6a8e 5926
21f581a5 5927 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5928}
5929
5930/*
5931 * Must not be invoked with interrupt sources disabled and
5932 * the hardware shutdown down. Can sleep.
5933 */
5934static int tg3_alloc_consistent(struct tg3 *tp)
5935{
f77a6a8e 5936 int i;
898a56f8 5937
21f581a5 5938 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5939 return -ENOMEM;
5940
f77a6a8e
MC		 5941 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5942 sizeof(struct tg3_hw_stats),
5943 &tp->stats_mapping);
5944 if (!tp->hw_stats)
1da177e4
LT		 5945 goto err_out;
5946
f77a6a8e 5947 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 5948
f77a6a8e
MC		 5949 for (i = 0; i < tp->irq_cnt; i++) {
5950 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 5951 struct tg3_hw_status *sblk;
1da177e4 5952
f77a6a8e
MC		 5953 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5954 TG3_HW_STATUS_SIZE,
5955 &tnapi->status_mapping);
5956 if (!tnapi->hw_status)
5957 goto err_out;
898a56f8 5958
f77a6a8e 5959 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 5960 sblk = tnapi->hw_status;
5961
5962 /*
5963 * When RSS is enabled, the status block format changes
5964 * slightly. The "rx_jumbo_consumer", "reserved",
5965 * and "rx_mini_consumer" members get mapped to the
5966 * other three rx return ring producer indexes.
5967 */
5968 switch (i) {
5969 default:
5970 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5971 break;
5972 case 2:
5973 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5974 break;
5975 case 3:
5976 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5977 break;
5978 case 4:
5979 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5980 break;
5981 }
72334482 5982
0c1d0e2b
MC		 5983 /*
5984 * If multivector RSS is enabled, vector 0 does not handle
5985 * rx or tx interrupts. Don't allocate any resources for it.
5986 */
5987 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5988 continue;
5989
f77a6a8e
MC		 5990 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5991 TG3_RX_RCB_RING_BYTES(tp),
5992 &tnapi->rx_rcb_mapping);
5993 if (!tnapi->rx_rcb)
5994 goto err_out;
72334482 5995
f77a6a8e 5996 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 5997
f77a6a8e
MC		 5998 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5999 TG3_TX_RING_SIZE, GFP_KERNEL);
6000 if (!tnapi->tx_buffers)
6001 goto err_out;
6002
6003 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6004 TG3_TX_RING_BYTES,
6005 &tnapi->tx_desc_mapping);
6006 if (!tnapi->tx_ring)
6007 goto err_out;
6008 }
1da177e4
LT		 6009
6010 return 0;
6011
6012err_out:
6013 tg3_free_consistent(tp);
6014 return -ENOMEM;
6015}
6016
6017#define MAX_WAIT_CNT 1000
6018
6019/* To stop a block, clear the enable bit and poll till it
6020 * clears. tp->lock is held.
6021 */
b3b7d6be 6022static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6023{
6024 unsigned int i;
6025 u32 val;
6026
6027 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6028 switch (ofs) {
6029 case RCVLSC_MODE:
6030 case DMAC_MODE:
6031 case MBFREE_MODE:
6032 case BUFMGR_MODE:
6033 case MEMARB_MODE:
6034 /* We can't enable/disable these bits of the
6035 * 5705/5750, just say success.
6036 */
6037 return 0;
6038
6039 default:
6040 break;
855e1111 6041 }
1da177e4
LT		 6042 }
6043
6044 val = tr32(ofs);
6045 val &= ~enable_bit;
6046 tw32_f(ofs, val);
6047
6048 for (i = 0; i < MAX_WAIT_CNT; i++) {
6049 udelay(100);
6050 val = tr32(ofs);
6051 if ((val & enable_bit) == 0)
6052 break;
6053 }
6054
b3b7d6be 6055 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6056 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6057 "ofs=%lx enable_bit=%x\n",
6058 ofs, enable_bit);
6059 return -ENODEV;
6060 }
6061
6062 return 0;
6063}
6064
6065/* tp->lock is held. */
b3b7d6be 6066static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6067{
6068 int i, err;
6069
6070 tg3_disable_ints(tp);
6071
6072 tp->rx_mode &= ~RX_MODE_ENABLE;
6073 tw32_f(MAC_RX_MODE, tp->rx_mode);
6074 udelay(10);
6075
b3b7d6be
DM		 6076 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6077 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6078 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6079 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6080 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6081 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6082
6083 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6084 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6085 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6086 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6087 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6088 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6089 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6090
6091 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6092 tw32_f(MAC_MODE, tp->mac_mode);
6093 udelay(40);
6094
6095 tp->tx_mode &= ~TX_MODE_ENABLE;
6096 tw32_f(MAC_TX_MODE, tp->tx_mode);
6097
6098 for (i = 0; i < MAX_WAIT_CNT; i++) {
6099 udelay(100);
6100 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6101 break;
6102 }
6103 if (i >= MAX_WAIT_CNT) {
6104 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6105 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6106 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6107 err |= -ENODEV;
1da177e4
LT		 6108 }
6109
e6de8ad1 6110 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6111 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6112 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6113
6114 tw32(FTQ_RESET, 0xffffffff);
6115 tw32(FTQ_RESET, 0x00000000);
6116
b3b7d6be
DM		 6117 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6118 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6119
f77a6a8e
MC		 6120 for (i = 0; i < tp->irq_cnt; i++) {
6121 struct tg3_napi *tnapi = &tp->napi[i];
6122 if (tnapi->hw_status)
6123 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6124 }
1da177e4
LT		 6125 if (tp->hw_stats)
6126 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6127
1da177e4
LT		 6128 return err;
6129}
6130
0d3031d9
MC		 6131static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6132{
6133 int i;
6134 u32 apedata;
6135
6136 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6137 if (apedata != APE_SEG_SIG_MAGIC)
6138 return;
6139
6140 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6141 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6142 return;
6143
6144 /* Wait for up to 1 millisecond for APE to service previous event. */
6145 for (i = 0; i < 10; i++) {
6146 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6147 return;
6148
6149 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6150
6151 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6152 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6153 event | APE_EVENT_STATUS_EVENT_PENDING);
6154
6155 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6156
6157 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6158 break;
6159
6160 udelay(100);
6161 }
6162
6163 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6164 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6165}
6166
6167static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6168{
6169 u32 event;
6170 u32 apedata;
6171
6172 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6173 return;
6174
6175 switch (kind) {
6176 case RESET_KIND_INIT:
6177 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6178 APE_HOST_SEG_SIG_MAGIC);
6179 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6180 APE_HOST_SEG_LEN_MAGIC);
6181 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6182 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6183 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6184 APE_HOST_DRIVER_ID_MAGIC);
6185 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6186 APE_HOST_BEHAV_NO_PHYLOCK);
6187
6188 event = APE_EVENT_STATUS_STATE_START;
6189 break;
6190 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6191 /* With the interface we are currently using,
6192 * APE does not track driver state. Wiping
6193 * out the HOST SEGMENT SIGNATURE forces
6194 * the APE to assume OS absent status.
6195 */
6196 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6197
0d3031d9
MC		 6198 event = APE_EVENT_STATUS_STATE_UNLOAD;
6199 break;
6200 case RESET_KIND_SUSPEND:
6201 event = APE_EVENT_STATUS_STATE_SUSPEND;
6202 break;
6203 default:
6204 return;
6205 }
6206
6207 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6208
6209 tg3_ape_send_event(tp, event);
6210}
6211
1da177e4
LT		 6212/* tp->lock is held. */
6213static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6214{
f49639e6
DM		 6215 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6216 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6217
6218 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6219 switch (kind) {
6220 case RESET_KIND_INIT:
6221 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6222 DRV_STATE_START);
6223 break;
6224
6225 case RESET_KIND_SHUTDOWN:
6226 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6227 DRV_STATE_UNLOAD);
6228 break;
6229
6230 case RESET_KIND_SUSPEND:
6231 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6232 DRV_STATE_SUSPEND);
6233 break;
6234
6235 default:
6236 break;
855e1111 6237 }
1da177e4 6238 }
0d3031d9
MC		 6239
6240 if (kind == RESET_KIND_INIT ||
6241 kind == RESET_KIND_SUSPEND)
6242 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6243}
6244
6245/* tp->lock is held. */
6246static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6247{
6248 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6249 switch (kind) {
6250 case RESET_KIND_INIT:
6251 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6252 DRV_STATE_START_DONE);
6253 break;
6254
6255 case RESET_KIND_SHUTDOWN:
6256 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6257 DRV_STATE_UNLOAD_DONE);
6258 break;
6259
6260 default:
6261 break;
855e1111 6262 }
1da177e4 6263 }
0d3031d9
MC		 6264
6265 if (kind == RESET_KIND_SHUTDOWN)
6266 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6267}
6268
6269/* tp->lock is held. */
6270static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6271{
6272 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6273 switch (kind) {
6274 case RESET_KIND_INIT:
6275 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6276 DRV_STATE_START);
6277 break;
6278
6279 case RESET_KIND_SHUTDOWN:
6280 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6281 DRV_STATE_UNLOAD);
6282 break;
6283
6284 case RESET_KIND_SUSPEND:
6285 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6286 DRV_STATE_SUSPEND);
6287 break;
6288
6289 default:
6290 break;
855e1111 6291 }
1da177e4
LT		 6292 }
6293}
6294
7a6f4369
MC		 6295static int tg3_poll_fw(struct tg3 *tp)
6296{
6297 int i;
6298 u32 val;
6299
b5d3772c 6300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6301 /* Wait up to 20ms for init done. */
6302 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6303 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6304 return 0;
0ccead18 6305 udelay(100);
b5d3772c
MC		 6306 }
6307 return -ENODEV;
6308 }
6309
7a6f4369
MC		 6310 /* Wait for firmware initialization to complete. */
6311 for (i = 0; i < 100000; i++) {
6312 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6313 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6314 break;
6315 udelay(10);
6316 }
6317
6318 /* Chip might not be fitted with firmware. Some Sun onboard
6319 * parts are configured like that. So don't signal the timeout
6320 * of the above loop as an error, but do report the lack of
6321 * running firmware once.
6322 */
6323 if (i >= 100000 &&
6324 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6325 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6326
6327 printk(KERN_INFO PFX "%s: No firmware running.\n",
6328 tp->dev->name);
6329 }
6330
6331 return 0;
6332}
6333
ee6a99b5
MC		 6334/* Save PCI command register before chip reset */
6335static void tg3_save_pci_state(struct tg3 *tp)
6336{
8a6eac90 6337 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6338}
6339
6340/* Restore PCI state after chip reset */
6341static void tg3_restore_pci_state(struct tg3 *tp)
6342{
6343 u32 val;
6344
6345 /* Re-enable indirect register accesses. */
6346 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6347 tp->misc_host_ctrl);
6348
6349 /* Set MAX PCI retry to zero. */
6350 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6351 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6352 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6353 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6354 /* Allow reads and writes to the APE register and memory space. */
6355 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6356 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6357 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6358 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6359
8a6eac90 6360 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6361
fcb389df
MC		 6362 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6363 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6364 pcie_set_readrq(tp->pdev, 4096);
6365 else {
6366 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6367 tp->pci_cacheline_sz);
6368 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6369 tp->pci_lat_timer);
6370 }
114342f2 6371 }
5f5c51e3 6372
ee6a99b5 6373 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6374 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6375 u16 pcix_cmd;
6376
6377 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6378 &pcix_cmd);
6379 pcix_cmd &= ~PCI_X_CMD_ERO;
6380 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6381 pcix_cmd);
6382 }
ee6a99b5
MC		 6383
6384 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6385
6386 /* Chip reset on 5780 will reset MSI enable bit,
6387 * so need to restore it.
6388 */
6389 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6390 u16 ctrl;
6391
6392 pci_read_config_word(tp->pdev,
6393 tp->msi_cap + PCI_MSI_FLAGS,
6394 &ctrl);
6395 pci_write_config_word(tp->pdev,
6396 tp->msi_cap + PCI_MSI_FLAGS,
6397 ctrl | PCI_MSI_FLAGS_ENABLE);
6398 val = tr32(MSGINT_MODE);
6399 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6400 }
6401 }
6402}
6403
1da177e4
LT		 6404static void tg3_stop_fw(struct tg3 *);
6405
6406/* tp->lock is held. */
6407static int tg3_chip_reset(struct tg3 *tp)
6408{
6409 u32 val;
1ee582d8 6410 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6411 int i, err;
1da177e4 6412
f49639e6
DM		 6413 tg3_nvram_lock(tp);
6414
77b483f1
MC		 6415 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6416
f49639e6
DM		 6417 /* No matching tg3_nvram_unlock() after this because
6418 * chip reset below will undo the nvram lock.
6419 */
6420 tp->nvram_lock_cnt = 0;
1da177e4 6421
ee6a99b5
MC		 6422 /* GRC_MISC_CFG core clock reset will clear the memory
6423 * enable bit in PCI register 4 and the MSI enable bit
6424 * on some chips, so we save relevant registers here.
6425 */
6426 tg3_save_pci_state(tp);
6427
d9ab5ad1 6428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6429 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6430 tw32(GRC_FASTBOOT_PC, 0);
6431
1da177e4
LT		 6432 /*
6433 * We must avoid the readl() that normally takes place.
6434 * It locks machines, causes machine checks, and other
6435 * fun things. So, temporarily disable the 5701
6436 * hardware workaround, while we do the reset.
6437 */
1ee582d8
MC		 6438 write_op = tp->write32;
6439 if (write_op == tg3_write_flush_reg32)
6440 tp->write32 = tg3_write32;
1da177e4 6441
d18edcb2
MC		 6442 /* Prevent the irq handler from reading or writing PCI registers
6443 * during chip reset when the memory enable bit in the PCI command
6444 * register may be cleared. The chip does not generate interrupt
6445 * at this time, but the irq handler may still be called due to irq
6446 * sharing or irqpoll.
6447 */
6448 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6449 for (i = 0; i < tp->irq_cnt; i++) {
6450 struct tg3_napi *tnapi = &tp->napi[i];
6451 if (tnapi->hw_status) {
6452 tnapi->hw_status->status = 0;
6453 tnapi->hw_status->status_tag = 0;
6454 }
6455 tnapi->last_tag = 0;
6456 tnapi->last_irq_tag = 0;
b8fa2f3a 6457 }
d18edcb2 6458 smp_mb();
4f125f42
MC		 6459
6460 for (i = 0; i < tp->irq_cnt; i++)
6461 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6462
255ca311
MC		 6463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6464 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6465 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6466 }
6467
1da177e4
LT		 6468 /* do the reset */
6469 val = GRC_MISC_CFG_CORECLK_RESET;
6470
6471 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6472 if (tr32(0x7e2c) == 0x60) {
6473 tw32(0x7e2c, 0x20);
6474 }
6475 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6476 tw32(GRC_MISC_CFG, (1 << 29));
6477 val |= (1 << 29);
6478 }
6479 }
6480
b5d3772c
MC		 6481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6482 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6483 tw32(GRC_VCPU_EXT_CTRL,
6484 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6485 }
6486
1da177e4
LT		 6487 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6488 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6489 tw32(GRC_MISC_CFG, val);
6490
1ee582d8
MC		 6491 /* restore 5701 hardware bug workaround write method */
6492 tp->write32 = write_op;
1da177e4
LT		 6493
6494 /* Unfortunately, we have to delay before the PCI read back.
6495 * Some 575X chips even will not respond to a PCI cfg access
6496 * when the reset command is given to the chip.
6497 *
6498 * How do these hardware designers expect things to work
6499 * properly if the PCI write is posted for a long period
6500 * of time? It is always necessary to have some method by
6501 * which a register read back can occur to push the write
6502 * out which does the reset.
6503 *
6504 * For most tg3 variants the trick below was working.
6505 * Ho hum...
6506 */
6507 udelay(120);
6508
6509 /* Flush PCI posted writes. The normal MMIO registers
6510 * are inaccessible at this time so this is the only
6511 * way to make this reliably (actually, this is no longer
6512 * the case, see above). I tried to use indirect
6513 * register read/write but this upset some 5701 variants.
6514 */
6515 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6516
6517 udelay(120);
6518
5e7dfd0f 6519 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6520 u16 val16;
6521
1da177e4
LT		 6522 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6523 int i;
6524 u32 cfg_val;
6525
6526 /* Wait for link training to complete. */
6527 for (i = 0; i < 5000; i++)
6528 udelay(100);
6529
6530 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6531 pci_write_config_dword(tp->pdev, 0xc4,
6532 cfg_val | (1 << 15));
6533 }
5e7dfd0f 6534
e7126997
MC		 6535 /* Clear the "no snoop" and "relaxed ordering" bits. */
6536 pci_read_config_word(tp->pdev,
6537 tp->pcie_cap + PCI_EXP_DEVCTL,
6538 &val16);
6539 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6540 PCI_EXP_DEVCTL_NOSNOOP_EN);
6541 /*
6542 * Older PCIe devices only support the 128 byte
6543 * MPS setting. Enforce the restriction.
5e7dfd0f 6544 */
e7126997
MC		 6545 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6546 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6547 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6548 pci_write_config_word(tp->pdev,
6549 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6550 val16);
5e7dfd0f
MC		 6551
6552 pcie_set_readrq(tp->pdev, 4096);
6553
6554 /* Clear error status */
6555 pci_write_config_word(tp->pdev,
6556 tp->pcie_cap + PCI_EXP_DEVSTA,
6557 PCI_EXP_DEVSTA_CED |
6558 PCI_EXP_DEVSTA_NFED |
6559 PCI_EXP_DEVSTA_FED |
6560 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6561 }
6562
ee6a99b5 6563 tg3_restore_pci_state(tp);
1da177e4 6564
d18edcb2
MC		 6565 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6566
ee6a99b5
MC		 6567 val = 0;
6568 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6569 val = tr32(MEMARB_MODE);
ee6a99b5 6570 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6571
6572 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6573 tg3_stop_fw(tp);
6574 tw32(0x5000, 0x400);
6575 }
6576
6577 tw32(GRC_MODE, tp->grc_mode);
6578
6579 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6580 val = tr32(0xc4);
1da177e4
LT		 6581
6582 tw32(0xc4, val | (1 << 15));
6583 }
6584
6585 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6587 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6588 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6589 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6590 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6591 }
6592
6593 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6594 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6595 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6596 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6597 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6598 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6599 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6600 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6601 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6602 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6603 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6604 } else
6605 tw32_f(MAC_MODE, 0);
6606 udelay(40);
6607
77b483f1
MC		 6608 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6609
7a6f4369
MC		 6610 err = tg3_poll_fw(tp);
6611 if (err)
6612 return err;
1da177e4 6613
0a9140cf
MC		 6614 tg3_mdio_start(tp);
6615
52cdf852
MC		 6616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6617 u8 phy_addr;
6618
6619 phy_addr = tp->phy_addr;
6620 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6621
6622 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6623 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6624 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6625 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6626 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6627 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6628 udelay(10);
6629
6630 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6631 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6632 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6633 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6634 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6635 udelay(10);
6636
6637 tp->phy_addr = phy_addr;
6638 }
6639
1da177e4 6640 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6641 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6642 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6643 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6644 val = tr32(0x7c00);
1da177e4
LT		 6645
6646 tw32(0x7c00, val | (1 << 25));
6647 }
6648
6649 /* Reprobe ASF enable state. */
6650 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6651 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6652 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6653 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6654 u32 nic_cfg;
6655
6656 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6657 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6658 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6659 tp->last_event_jiffies = jiffies;
cbf46853 6660 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6661 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6662 }
6663 }
6664
6665 return 0;
6666}
6667
6668/* tp->lock is held. */
6669static void tg3_stop_fw(struct tg3 *tp)
6670{
0d3031d9
MC		 6671 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6672 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6673 /* Wait for RX cpu to ACK the previous event. */
6674 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6675
6676 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6677
6678 tg3_generate_fw_event(tp);
1da177e4 6679
7c5026aa
MC		 6680 /* Wait for RX cpu to ACK this event. */
6681 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6682 }
6683}
6684
6685/* tp->lock is held. */
944d980e 6686static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6687{
6688 int err;
6689
6690 tg3_stop_fw(tp);
6691
944d980e 6692 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6693
b3b7d6be 6694 tg3_abort_hw(tp, silent);
1da177e4
LT		 6695 err = tg3_chip_reset(tp);
6696
daba2a63
MC		 6697 __tg3_set_mac_addr(tp, 0);
6698
944d980e
MC		 6699 tg3_write_sig_legacy(tp, kind);
6700 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6701
6702 if (err)
6703 return err;
6704
6705 return 0;
6706}
6707
1da177e4
LT		 6708#define RX_CPU_SCRATCH_BASE 0x30000
6709#define RX_CPU_SCRATCH_SIZE 0x04000
6710#define TX_CPU_SCRATCH_BASE 0x34000
6711#define TX_CPU_SCRATCH_SIZE 0x04000
6712
6713/* tp->lock is held. */
6714static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6715{
6716 int i;
6717
5d9428de
ES		 6718 BUG_ON(offset == TX_CPU_BASE &&
6719 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6720
b5d3772c
MC		 6721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6722 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6723
6724 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6725 return 0;
6726 }
1da177e4
LT		 6727 if (offset == RX_CPU_BASE) {
6728 for (i = 0; i < 10000; i++) {
6729 tw32(offset + CPU_STATE, 0xffffffff);
6730 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6731 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6732 break;
6733 }
6734
6735 tw32(offset + CPU_STATE, 0xffffffff);
6736 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6737 udelay(10);
6738 } else {
6739 for (i = 0; i < 10000; i++) {
6740 tw32(offset + CPU_STATE, 0xffffffff);
6741 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6742 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6743 break;
6744 }
6745 }
6746
6747 if (i >= 10000) {
6748 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6749 "and %s CPU\n",
6750 tp->dev->name,
6751 (offset == RX_CPU_BASE ? "RX" : "TX"));
6752 return -ENODEV;
6753 }
ec41c7df
MC		 6754
6755 /* Clear firmware's nvram arbitration. */
6756 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6757 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6758 return 0;
6759}
6760
6761struct fw_info {
077f849d
JSR		 6762 unsigned int fw_base;
6763 unsigned int fw_len;
6764 const __be32 *fw_data;
1da177e4
LT		 6765};
6766
6767/* tp->lock is held. */
6768static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6769 int cpu_scratch_size, struct fw_info *info)
6770{
ec41c7df 6771 int err, lock_err, i;
1da177e4
LT		 6772 void (*write_op)(struct tg3 *, u32, u32);
6773
6774 if (cpu_base == TX_CPU_BASE &&
6775 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6776 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6777 "TX cpu firmware on %s which is 5705.\n",
6778 tp->dev->name);
6779 return -EINVAL;
6780 }
6781
6782 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6783 write_op = tg3_write_mem;
6784 else
6785 write_op = tg3_write_indirect_reg32;
6786
1b628151
MC		 6787 /* It is possible that bootcode is still loading at this point.
6788 * Get the nvram lock first before halting the cpu.
6789 */
ec41c7df 6790 lock_err = tg3_nvram_lock(tp);
1da177e4 6791 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6792 if (!lock_err)
6793 tg3_nvram_unlock(tp);
1da177e4
LT		 6794 if (err)
6795 goto out;
6796
6797 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6798 write_op(tp, cpu_scratch_base + i, 0);
6799 tw32(cpu_base + CPU_STATE, 0xffffffff);
6800 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6801 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6802 write_op(tp, (cpu_scratch_base +
077f849d 6803 (info->fw_base & 0xffff) +
1da177e4 6804 (i * sizeof(u32))),
077f849d 6805 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6806
6807 err = 0;
6808
6809out:
1da177e4
LT		 6810 return err;
6811}
6812
6813/* tp->lock is held. */
6814static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6815{
6816 struct fw_info info;
077f849d 6817 const __be32 *fw_data;
1da177e4
LT		 6818 int err, i;
6819
077f849d
JSR		 6820 fw_data = (void *)tp->fw->data;
6821
6822 /* Firmware blob starts with version numbers, followed by
6823 start address and length. We are setting complete length.
6824 length = end_address_of_bss - start_address_of_text.
6825 Remainder is the blob to be loaded contiguously
6826 from start address. */
6827
6828 info.fw_base = be32_to_cpu(fw_data[1]);
6829 info.fw_len = tp->fw->size - 12;
6830 info.fw_data = &fw_data[3];
1da177e4
LT		 6831
6832 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6833 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6834 &info);
6835 if (err)
6836 return err;
6837
6838 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6839 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6840 &info);
6841 if (err)
6842 return err;
6843
6844 /* Now startup only the RX cpu. */
6845 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6846 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6847
6848 for (i = 0; i < 5; i++) {
077f849d 6849 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6850 break;
6851 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6852 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6853 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6854 udelay(1000);
6855 }
6856 if (i >= 5) {
6857 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6858 "to set RX CPU PC, is %08x should be %08x\n",
6859 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6860 info.fw_base);
1da177e4
LT		 6861 return -ENODEV;
6862 }
6863 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6864 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6865
6866 return 0;
6867}
6868
1da177e4 6869/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6870
6871/* tp->lock is held. */
6872static int tg3_load_tso_firmware(struct tg3 *tp)
6873{
6874 struct fw_info info;
077f849d 6875 const __be32 *fw_data;
1da177e4
LT		 6876 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6877 int err, i;
6878
6879 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6880 return 0;
6881
077f849d
JSR		 6882 fw_data = (void *)tp->fw->data;
6883
6884 /* Firmware blob starts with version numbers, followed by
6885 start address and length. We are setting complete length.
6886 length = end_address_of_bss - start_address_of_text.
6887 Remainder is the blob to be loaded contiguously
6888 from start address. */
6889
6890 info.fw_base = be32_to_cpu(fw_data[1]);
6891 cpu_scratch_size = tp->fw_len;
6892 info.fw_len = tp->fw->size - 12;
6893 info.fw_data = &fw_data[3];
6894
1da177e4 6895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6896 cpu_base = RX_CPU_BASE;
6897 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6898 } else {
1da177e4
LT		 6899 cpu_base = TX_CPU_BASE;
6900 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6901 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6902 }
6903
6904 err = tg3_load_firmware_cpu(tp, cpu_base,
6905 cpu_scratch_base, cpu_scratch_size,
6906 &info);
6907 if (err)
6908 return err;
6909
6910 /* Now startup the cpu. */
6911 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6912 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6913
6914 for (i = 0; i < 5; i++) {
077f849d 6915 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6916 break;
6917 tw32(cpu_base + CPU_STATE, 0xffffffff);
6918 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6919 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6920 udelay(1000);
6921 }
6922 if (i >= 5) {
6923 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6924 "to set CPU PC, is %08x should be %08x\n",
6925 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6926 info.fw_base);
1da177e4
LT		 6927 return -ENODEV;
6928 }
6929 tw32(cpu_base + CPU_STATE, 0xffffffff);
6930 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6931 return 0;
6932}
6933
1da177e4 6934
1da177e4
LT		 6935static int tg3_set_mac_addr(struct net_device *dev, void *p)
6936{
6937 struct tg3 *tp = netdev_priv(dev);
6938 struct sockaddr *addr = p;
986e0aeb 6939 int err = 0, skip_mac_1 = 0;
1da177e4 6940
f9804ddb
MC		 6941 if (!is_valid_ether_addr(addr->sa_data))
6942 return -EINVAL;
6943
1da177e4
LT		 6944 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6945
e75f7c90
MC		 6946 if (!netif_running(dev))
6947 return 0;
6948
58712ef9 6949 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6950 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6951
986e0aeb
MC		 6952 addr0_high = tr32(MAC_ADDR_0_HIGH);
6953 addr0_low = tr32(MAC_ADDR_0_LOW);
6954 addr1_high = tr32(MAC_ADDR_1_HIGH);
6955 addr1_low = tr32(MAC_ADDR_1_LOW);
6956
6957 /* Skip MAC addr 1 if ASF is using it. */
6958 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6959 !(addr1_high == 0 && addr1_low == 0))
6960 skip_mac_1 = 1;
58712ef9 6961 }
986e0aeb
MC		 6962 spin_lock_bh(&tp->lock);
6963 __tg3_set_mac_addr(tp, skip_mac_1);
6964 spin_unlock_bh(&tp->lock);
1da177e4 6965
b9ec6c1b 6966 return err;
1da177e4
LT		 6967}
6968
6969/* tp->lock is held. */
6970static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6971 dma_addr_t mapping, u32 maxlen_flags,
6972 u32 nic_addr)
6973{
6974 tg3_write_mem(tp,
6975 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6976 ((u64) mapping >> 32));
6977 tg3_write_mem(tp,
6978 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6979 ((u64) mapping & 0xffffffff));
6980 tg3_write_mem(tp,
6981 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6982 maxlen_flags);
6983
6984 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6985 tg3_write_mem(tp,
6986 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6987 nic_addr);
6988}
6989
6990static void __tg3_set_rx_mode(struct net_device *);
d244c892 6991static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 6992{
b6080e12
MC		 6993 int i;
6994
6995 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6996 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6997 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6998 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6999
7000 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7001 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7002 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7003 } else {
7004 tw32(HOSTCC_TXCOL_TICKS, 0);
7005 tw32(HOSTCC_TXMAX_FRAMES, 0);
7006 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7007
7008 tw32(HOSTCC_RXCOL_TICKS, 0);
7009 tw32(HOSTCC_RXMAX_FRAMES, 0);
7010 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7011 }
b6080e12 7012
15f9850d
DM		 7013 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7014 u32 val = ec->stats_block_coalesce_usecs;
7015
b6080e12
MC		 7016 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7017 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7018
15f9850d
DM		 7019 if (!netif_carrier_ok(tp->dev))
7020 val = 0;
7021
7022 tw32(HOSTCC_STAT_COAL_TICKS, val);
7023 }
b6080e12
MC		 7024
7025 for (i = 0; i < tp->irq_cnt - 1; i++) {
7026 u32 reg;
7027
7028 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7029 tw32(reg, ec->rx_coalesce_usecs);
7030 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7031 tw32(reg, ec->tx_coalesce_usecs);
7032 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7033 tw32(reg, ec->rx_max_coalesced_frames);
7034 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7035 tw32(reg, ec->tx_max_coalesced_frames);
7036 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7037 tw32(reg, ec->rx_max_coalesced_frames_irq);
7038 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7039 tw32(reg, ec->tx_max_coalesced_frames_irq);
7040 }
7041
7042 for (; i < tp->irq_max - 1; i++) {
7043 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7044 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7045 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7046 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7047 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7048 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7049 }
15f9850d 7050}
1da177e4 7051
2d31ecaf
MC		 7052/* tp->lock is held. */
7053static void tg3_rings_reset(struct tg3 *tp)
7054{
7055 int i;
f77a6a8e 7056 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7057 struct tg3_napi *tnapi = &tp->napi[0];
7058
7059 /* Disable all transmit rings but the first. */
7060 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7061 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7062 else
7063 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7064
7065 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7066 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7067 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7068 BDINFO_FLAGS_DISABLED);
7069
7070
7071 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7073 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7074 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7075 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7076 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7077 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7078 else
7079 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7080
7081 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7082 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7083 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7084 BDINFO_FLAGS_DISABLED);
7085
7086 /* Disable interrupts */
7087 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7088
7089 /* Zero mailbox registers. */
f77a6a8e
MC		 7090 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7091 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7092 tp->napi[i].tx_prod = 0;
7093 tp->napi[i].tx_cons = 0;
7094 tw32_mailbox(tp->napi[i].prodmbox, 0);
7095 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7096 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7097 }
7098 } else {
7099 tp->napi[0].tx_prod = 0;
7100 tp->napi[0].tx_cons = 0;
7101 tw32_mailbox(tp->napi[0].prodmbox, 0);
7102 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7103 }
2d31ecaf
MC		 7104
7105 /* Make sure the NIC-based send BD rings are disabled. */
7106 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7107 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7108 for (i = 0; i < 16; i++)
7109 tw32_tx_mbox(mbox + i * 8, 0);
7110 }
7111
7112 txrcb = NIC_SRAM_SEND_RCB;
7113 rxrcb = NIC_SRAM_RCV_RET_RCB;
7114
7115 /* Clear status block in ram. */
7116 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7117
7118 /* Set status block DMA address */
7119 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7120 ((u64) tnapi->status_mapping >> 32));
7121 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7122 ((u64) tnapi->status_mapping & 0xffffffff));
7123
f77a6a8e
MC		 7124 if (tnapi->tx_ring) {
7125 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7126 (TG3_TX_RING_SIZE <<
7127 BDINFO_FLAGS_MAXLEN_SHIFT),
7128 NIC_SRAM_TX_BUFFER_DESC);
7129 txrcb += TG3_BDINFO_SIZE;
7130 }
7131
7132 if (tnapi->rx_rcb) {
7133 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7134 (TG3_RX_RCB_RING_SIZE(tp) <<
7135 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7136 rxrcb += TG3_BDINFO_SIZE;
7137 }
7138
7139 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7140
f77a6a8e
MC		 7141 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7142 u64 mapping = (u64)tnapi->status_mapping;
7143 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7144 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7145
7146 /* Clear status block in ram. */
7147 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7148
7149 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7150 (TG3_TX_RING_SIZE <<
7151 BDINFO_FLAGS_MAXLEN_SHIFT),
7152 NIC_SRAM_TX_BUFFER_DESC);
7153
7154 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7155 (TG3_RX_RCB_RING_SIZE(tp) <<
7156 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7157
7158 stblk += 8;
7159 txrcb += TG3_BDINFO_SIZE;
7160 rxrcb += TG3_BDINFO_SIZE;
7161 }
2d31ecaf
MC		 7162}
7163
1da177e4 7164/* tp->lock is held. */
8e7a22e3 7165static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7166{
7167 u32 val, rdmac_mode;
7168 int i, err, limit;
21f581a5 7169 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7170
7171 tg3_disable_ints(tp);
7172
7173 tg3_stop_fw(tp);
7174
7175 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7176
7177 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7178 tg3_abort_hw(tp, 1);
1da177e4
LT		 7179 }
7180
dd477003
MC		 7181 if (reset_phy &&
7182 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7183 tg3_phy_reset(tp);
7184
1da177e4
LT		 7185 err = tg3_chip_reset(tp);
7186 if (err)
7187 return err;
7188
7189 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7190
bcb37f6c 7191 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7192 val = tr32(TG3_CPMU_CTRL);
7193 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7194 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7195
7196 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7197 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7198 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7199 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7200
7201 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7202 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7203 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7204 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7205
7206 val = tr32(TG3_CPMU_HST_ACC);
7207 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7208 val |= CPMU_HST_ACC_MACCLK_6_25;
7209 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7210 }
7211
33466d93
MC		 7212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7213 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7214 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7215 PCIE_PWR_MGMT_L1_THRESH_4MS;
7216 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7217
7218 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7219 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7220
7221 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7222
f40386c8
MC		 7223 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7224 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7225 }
7226
1da177e4
LT		 7227 /* This works around an issue with Athlon chipsets on
7228 * B3 tigon3 silicon. This bit has no effect on any
7229 * other revision. But do not set this on PCI Express
795d01c5 7230 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7231 */
795d01c5
MC		 7232 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7233 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7234 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7235 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7236 }
1da177e4
LT		 7237
7238 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7239 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7240 val = tr32(TG3PCI_PCISTATE);
7241 val |= PCISTATE_RETRY_SAME_DMA;
7242 tw32(TG3PCI_PCISTATE, val);
7243 }
7244
0d3031d9
MC		 7245 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7246 /* Allow reads and writes to the
7247 * APE register and memory space.
7248 */
7249 val = tr32(TG3PCI_PCISTATE);
7250 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7251 PCISTATE_ALLOW_APE_SHMEM_WR;
7252 tw32(TG3PCI_PCISTATE, val);
7253 }
7254
1da177e4
LT		 7255 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7256 /* Enable some hw fixes. */
7257 val = tr32(TG3PCI_MSI_DATA);
7258 val |= (1 << 26) | (1 << 28) | (1 << 29);
7259 tw32(TG3PCI_MSI_DATA, val);
7260 }
7261
7262 /* Descriptor ring init may make accesses to the
7263 * NIC SRAM area to setup the TX descriptors, so we
7264 * can only do this after the hardware has been
7265 * successfully reset.
7266 */
32d8c572
MC		 7267 err = tg3_init_rings(tp);
7268 if (err)
7269 return err;
1da177e4 7270
9936bcf6 7271 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
f6eb9b1f
MC		 7272 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7273 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
d30cdd28
MC		 7274 /* This value is determined during the probe time DMA
7275 * engine test, tg3_test_dma.
7276 */
7277 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7278 }
1da177e4
LT		 7279
7280 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7281 GRC_MODE_4X_NIC_SEND_RINGS |
7282 GRC_MODE_NO_TX_PHDR_CSUM |
7283 GRC_MODE_NO_RX_PHDR_CSUM);
7284 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7285
7286 /* Pseudo-header checksum is done by hardware logic and not
7287 * the offload processers, so make the chip do the pseudo-
7288 * header checksums on receive. For transmit it is more
7289 * convenient to do the pseudo-header checksum in software
7290 * as Linux does that on transmit for us in all cases.
7291 */
7292 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7293
7294 tw32(GRC_MODE,
7295 tp->grc_mode |
7296 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7297
7298 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7299 val = tr32(GRC_MISC_CFG);
7300 val &= ~0xff;
7301 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7302 tw32(GRC_MISC_CFG, val);
7303
7304 /* Initialize MBUF/DESC pool. */
cbf46853 7305 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7306 /* Do nothing. */
7307 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7308 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7309 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7310 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7311 else
7312 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7313 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7314 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7315 }
1da177e4
LT		 7316 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7317 int fw_len;
7318
077f849d 7319 fw_len = tp->fw_len;
1da177e4
LT		 7320 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7321 tw32(BUFMGR_MB_POOL_ADDR,
7322 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7323 tw32(BUFMGR_MB_POOL_SIZE,
7324 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7325 }
1da177e4 7326
0f893dc6 7327 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7328 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7329 tp->bufmgr_config.mbuf_read_dma_low_water);
7330 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7331 tp->bufmgr_config.mbuf_mac_rx_low_water);
7332 tw32(BUFMGR_MB_HIGH_WATER,
7333 tp->bufmgr_config.mbuf_high_water);
7334 } else {
7335 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7336 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7337 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7338 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7339 tw32(BUFMGR_MB_HIGH_WATER,
7340 tp->bufmgr_config.mbuf_high_water_jumbo);
7341 }
7342 tw32(BUFMGR_DMA_LOW_WATER,
7343 tp->bufmgr_config.dma_low_water);
7344 tw32(BUFMGR_DMA_HIGH_WATER,
7345 tp->bufmgr_config.dma_high_water);
7346
7347 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7348 for (i = 0; i < 2000; i++) {
7349 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7350 break;
7351 udelay(10);
7352 }
7353 if (i >= 2000) {
7354 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7355 tp->dev->name);
7356 return -ENODEV;
7357 }
7358
7359 /* Setup replenish threshold. */
f92905de
MC		 7360 val = tp->rx_pending / 8;
7361 if (val == 0)
7362 val = 1;
7363 else if (val > tp->rx_std_max_post)
7364 val = tp->rx_std_max_post;
b5d3772c
MC		 7365 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7366 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7367 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7368
7369 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7370 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7371 }
f92905de
MC		 7372
7373 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7374
7375 /* Initialize TG3_BDINFO's at:
7376 * RCVDBDI_STD_BD: standard eth size rx ring
7377 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7378 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7379 *
7380 * like so:
7381 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7382 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7383 * ring attribute flags
7384 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7385 *
7386 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7387 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7388 *
7389 * The size of each ring is fixed in the firmware, but the location is
7390 * configurable.
7391 */
7392 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7393 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7394 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7395 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7396 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7397 NIC_SRAM_RX_BUFFER_DESC);
7398
fdb72b38
MC		 7399 /* Disable the mini ring */
7400 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7401 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7402 BDINFO_FLAGS_DISABLED);
7403
fdb72b38
MC		 7404 /* Program the jumbo buffer descriptor ring control
7405 * blocks on those devices that have them.
7406 */
8f666b07 7407 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7408 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7409 /* Setup replenish threshold. */
7410 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7411
0f893dc6 7412 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7413 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7414 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7415 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7416 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7417 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7418 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7419 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7420 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7421 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7422 } else {
7423 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7424 BDINFO_FLAGS_DISABLED);
7425 }
7426
f6eb9b1f
MC		 7427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7428 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7429 (RX_STD_MAX_SIZE << 2);
7430 else
7431 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7432 } else
7433 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7434
7435 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7436
21f581a5 7437 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7438 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7439 tpr->rx_std_ptr);
1da177e4 7440
21f581a5
MC		 7441 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7442 tp->rx_jumbo_pending : 0;
1da177e4 7443 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7444 tpr->rx_jmb_ptr);
1da177e4 7445
f6eb9b1f
MC		 7446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7447 tw32(STD_REPLENISH_LWM, 32);
7448 tw32(JMB_REPLENISH_LWM, 16);
7449 }
7450
2d31ecaf
MC		 7451 tg3_rings_reset(tp);
7452
1da177e4 7453 /* Initialize MAC address and backoff seed. */
986e0aeb 7454 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7455
7456 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7457 tw32(MAC_RX_MTU_SIZE,
7458 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7459
7460 /* The slot time is changed by tg3_setup_phy if we
7461 * run at gigabit with half duplex.
7462 */
7463 tw32(MAC_TX_LENGTHS,
7464 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7465 (6 << TX_LENGTHS_IPG_SHIFT) |
7466 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7467
7468 /* Receive rules. */
7469 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7470 tw32(RCVLPC_CONFIG, 0x0181);
7471
7472 /* Calculate RDMAC_MODE setting early, we need it to determine
7473 * the RCVLPC_STATE_ENABLE mask.
7474 */
7475 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7476 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7477 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7478 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7479 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7480
57e6983c 7481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7483 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7484 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7485 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7486 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7487
85e94ced
MC		 7488 /* If statement applies to 5705 and 5750 PCI devices only */
7489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7490 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7491 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7492 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7494 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7495 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7496 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7497 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7498 }
7499 }
7500
85e94ced
MC		 7501 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7502 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7503
1da177e4 7504 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7505 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7506
7507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7509 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7510
7511 /* Receive/send statistics. */
1661394e
MC		 7512 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7513 val = tr32(RCVLPC_STATS_ENABLE);
7514 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7515 tw32(RCVLPC_STATS_ENABLE, val);
7516 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7517 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7518 val = tr32(RCVLPC_STATS_ENABLE);
7519 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7520 tw32(RCVLPC_STATS_ENABLE, val);
7521 } else {
7522 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7523 }
7524 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7525 tw32(SNDDATAI_STATSENAB, 0xffffff);
7526 tw32(SNDDATAI_STATSCTRL,
7527 (SNDDATAI_SCTRL_ENABLE |
7528 SNDDATAI_SCTRL_FASTUPD));
7529
7530 /* Setup host coalescing engine. */
7531 tw32(HOSTCC_MODE, 0);
7532 for (i = 0; i < 2000; i++) {
7533 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7534 break;
7535 udelay(10);
7536 }
7537
d244c892 7538 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7539
1da177e4
LT		 7540 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7541 /* Status/statistics block address. See tg3_timer,
7542 * the tg3_periodic_fetch_stats call there, and
7543 * tg3_get_stats to see how this works for 5705/5750 chips.
7544 */
1da177e4
LT		 7545 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7546 ((u64) tp->stats_mapping >> 32));
7547 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7548 ((u64) tp->stats_mapping & 0xffffffff));
7549 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7550
1da177e4 7551 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7552
7553 /* Clear statistics and status block memory areas */
7554 for (i = NIC_SRAM_STATS_BLK;
7555 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7556 i += sizeof(u32)) {
7557 tg3_write_mem(tp, i, 0);
7558 udelay(40);
7559 }
1da177e4
LT		 7560 }
7561
7562 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7563
7564 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7565 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7566 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7567 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7568
c94e3941
MC		 7569 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7570 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7571 /* reset to prevent losing 1st rx packet intermittently */
7572 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7573 udelay(10);
7574 }
7575
3bda1258
MC		 7576 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7577 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7578 else
7579 tp->mac_mode = 0;
7580 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7581 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7582 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7583 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7584 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7585 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7586 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7587 udelay(40);
7588
314fba34 7589 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7590 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7591 * register to preserve the GPIO settings for LOMs. The GPIOs,
7592 * whether used as inputs or outputs, are set by boot code after
7593 * reset.
7594 */
9d26e213 7595 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7596 u32 gpio_mask;
7597
9d26e213
MC		 7598 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7599 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7600 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7601
7602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7603 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7604 GRC_LCLCTRL_GPIO_OUTPUT3;
7605
af36e6b6
MC		 7606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7607 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7608
aaf84465 7609 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7610 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7611
7612 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7613 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7614 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7615 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7616 }
1da177e4
LT		 7617 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7618 udelay(100);
7619
baf8a94a
MC		 7620 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7621 val = tr32(MSGINT_MODE);
7622 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7623 tw32(MSGINT_MODE, val);
7624 }
7625
1da177e4
LT		 7626 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7627 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7628 udelay(40);
7629 }
7630
7631 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7632 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7633 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7634 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7635 WDMAC_MODE_LNGREAD_ENAB);
7636
85e94ced
MC		 7637 /* If statement applies to 5705 and 5750 PCI devices only */
7638 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7639 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7641 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7642 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7643 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7644 /* nothing */
7645 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7646 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7647 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7648 val |= WDMAC_MODE_RX_ACCEL;
7649 }
7650 }
7651
d9ab5ad1 7652 /* Enable host coalescing bug fix */
321d32a0 7653 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7654 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7655
788a035e
MC		 7656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7657 val |= WDMAC_MODE_BURST_ALL_DATA;
7658
1da177e4
LT		 7659 tw32_f(WDMAC_MODE, val);
7660 udelay(40);
7661
9974a356
MC		 7662 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7663 u16 pcix_cmd;
7664
7665 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7666 &pcix_cmd);
1da177e4 7667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7668 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7669 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7670 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7671 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7672 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7673 }
9974a356
MC		 7674 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7675 pcix_cmd);
1da177e4
LT		 7676 }
7677
7678 tw32_f(RDMAC_MODE, rdmac_mode);
7679 udelay(40);
7680
7681 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7682 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7683 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7684
7685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7686 tw32(SNDDATAC_MODE,
7687 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7688 else
7689 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7690
1da177e4
LT		 7691 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7692 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7693 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7694 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7695 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7696 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7697 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7698 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7699 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7700 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7701 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7702
7703 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7704 err = tg3_load_5701_a0_firmware_fix(tp);
7705 if (err)
7706 return err;
7707 }
7708
1da177e4
LT		 7709 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7710 err = tg3_load_tso_firmware(tp);
7711 if (err)
7712 return err;
7713 }
1da177e4
LT		 7714
7715 tp->tx_mode = TX_MODE_ENABLE;
7716 tw32_f(MAC_TX_MODE, tp->tx_mode);
7717 udelay(100);
7718
baf8a94a
MC		 7719 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7720 u32 reg = MAC_RSS_INDIR_TBL_0;
7721 u8 *ent = (u8 *)&val;
7722
7723 /* Setup the indirection table */
7724 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7725 int idx = i % sizeof(val);
7726
7727 ent[idx] = i % (tp->irq_cnt - 1);
7728 if (idx == sizeof(val) - 1) {
7729 tw32(reg, val);
7730 reg += 4;
7731 }
7732 }
7733
7734 /* Setup the "secret" hash key. */
7735 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7736 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7737 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7738 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7739 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7740 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7741 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7742 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7743 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7744 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7745 }
7746
1da177e4 7747 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7748 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7749 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7750
baf8a94a
MC		 7751 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7752 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7753 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7754 RX_MODE_RSS_IPV6_HASH_EN |
7755 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7756 RX_MODE_RSS_IPV4_HASH_EN |
7757 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7758
1da177e4
LT		 7759 tw32_f(MAC_RX_MODE, tp->rx_mode);
7760 udelay(10);
7761
1da177e4
LT		 7762 tw32(MAC_LED_CTRL, tp->led_ctrl);
7763
7764 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7765 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7766 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7767 udelay(10);
7768 }
7769 tw32_f(MAC_RX_MODE, tp->rx_mode);
7770 udelay(10);
7771
7772 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7773 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7774 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7775 /* Set drive transmission level to 1.2V */
7776 /* only if the signal pre-emphasis bit is not set */
7777 val = tr32(MAC_SERDES_CFG);
7778 val &= 0xfffff000;
7779 val |= 0x880;
7780 tw32(MAC_SERDES_CFG, val);
7781 }
7782 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7783 tw32(MAC_SERDES_CFG, 0x616000);
7784 }
7785
7786 /* Prevent chip from dropping frames when flow control
7787 * is enabled.
7788 */
7789 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7790
7791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7792 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7793 /* Use hardware link auto-negotiation */
7794 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7795 }
7796
d4d2c558
MC		 7797 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7798 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7799 u32 tmp;
7800
7801 tmp = tr32(SERDES_RX_CTRL);
7802 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7803 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7804 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7805 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7806 }
7807
dd477003
MC		 7808 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7809 if (tp->link_config.phy_is_low_power) {
7810 tp->link_config.phy_is_low_power = 0;
7811 tp->link_config.speed = tp->link_config.orig_speed;
7812 tp->link_config.duplex = tp->link_config.orig_duplex;
7813 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7814 }
1da177e4 7815
dd477003
MC		 7816 err = tg3_setup_phy(tp, 0);
7817 if (err)
7818 return err;
1da177e4 7819
dd477003 7820 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7821 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7822 u32 tmp;
7823
7824 /* Clear CRC stats. */
7825 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7826 tg3_writephy(tp, MII_TG3_TEST1,
7827 tmp | MII_TG3_TEST1_CRC_EN);
7828 tg3_readphy(tp, 0x14, &tmp);
7829 }
1da177e4
LT		 7830 }
7831 }
7832
7833 __tg3_set_rx_mode(tp->dev);
7834
7835 /* Initialize receive rules. */
7836 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7837 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7838 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7839 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7840
4cf78e4f 7841 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7842 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7843 limit = 8;
7844 else
7845 limit = 16;
7846 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7847 limit -= 4;
7848 switch (limit) {
7849 case 16:
7850 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7851 case 15:
7852 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7853 case 14:
7854 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7855 case 13:
7856 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7857 case 12:
7858 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7859 case 11:
7860 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7861 case 10:
7862 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7863 case 9:
7864 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7865 case 8:
7866 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7867 case 7:
7868 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7869 case 6:
7870 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7871 case 5:
7872 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7873 case 4:
7874 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7875 case 3:
7876 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7877 case 2:
7878 case 1:
7879
7880 default:
7881 break;
855e1111 7882 }
1da177e4 7883
9ce768ea
MC		 7884 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7885 /* Write our heartbeat update interval to APE. */
7886 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7887 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7888
1da177e4
LT		 7889 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7890
1da177e4
LT		 7891 return 0;
7892}
7893
7894/* Called at device open time to get the chip ready for
7895 * packet processing. Invoked with tp->lock held.
7896 */
8e7a22e3 7897static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7898{
1da177e4
LT		 7899 tg3_switch_clocks(tp);
7900
7901 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7902
2f751b67 7903 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7904}
7905
7906#define TG3_STAT_ADD32(PSTAT, REG) \
7907do { u32 __val = tr32(REG); \
7908 (PSTAT)->low += __val; \
7909 if ((PSTAT)->low < __val) \
7910 (PSTAT)->high += 1; \
7911} while (0)
7912
7913static void tg3_periodic_fetch_stats(struct tg3 *tp)
7914{
7915 struct tg3_hw_stats *sp = tp->hw_stats;
7916
7917 if (!netif_carrier_ok(tp->dev))
7918 return;
7919
7920 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7921 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7922 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7923 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7924 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7925 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7926 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7927 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7928 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7929 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7930 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7931 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7932 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7933
7934 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7935 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7936 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7937 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7938 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7939 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7940 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7941 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7942 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7943 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7944 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7945 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7946 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7947 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7948
7949 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7950 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7951 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7952}
7953
7954static void tg3_timer(unsigned long __opaque)
7955{
7956 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7957
f475f163
MC		 7958 if (tp->irq_sync)
7959 goto restart_timer;
7960
f47c11ee 7961 spin_lock(&tp->lock);
1da177e4 7962
fac9b83e
DM		 7963 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7964 /* All of this garbage is because when using non-tagged
7965 * IRQ status the mailbox/status_block protocol the chip
7966 * uses with the cpu is race prone.
7967 */
898a56f8 7968 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7969 tw32(GRC_LOCAL_CTRL,
7970 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7971 } else {
7972 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7973 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7974 }
1da177e4 7975
fac9b83e
DM		 7976 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7977 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7978 spin_unlock(&tp->lock);
fac9b83e
DM		 7979 schedule_work(&tp->reset_task);
7980 return;
7981 }
1da177e4
LT		 7982 }
7983
1da177e4
LT		 7984 /* This part only runs once per second. */
7985 if (!--tp->timer_counter) {
fac9b83e
DM		 7986 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7987 tg3_periodic_fetch_stats(tp);
7988
1da177e4
LT		 7989 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7990 u32 mac_stat;
7991 int phy_event;
7992
7993 mac_stat = tr32(MAC_STATUS);
7994
7995 phy_event = 0;
7996 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7997 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7998 phy_event = 1;
7999 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8000 phy_event = 1;
8001
8002 if (phy_event)
8003 tg3_setup_phy(tp, 0);
8004 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8005 u32 mac_stat = tr32(MAC_STATUS);
8006 int need_setup = 0;
8007
8008 if (netif_carrier_ok(tp->dev) &&
8009 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8010 need_setup = 1;
8011 }
8012 if (! netif_carrier_ok(tp->dev) &&
8013 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8014 MAC_STATUS_SIGNAL_DET))) {
8015 need_setup = 1;
8016 }
8017 if (need_setup) {
3d3ebe74
MC		 8018 if (!tp->serdes_counter) {
8019 tw32_f(MAC_MODE,
8020 (tp->mac_mode &
8021 ~MAC_MODE_PORT_MODE_MASK));
8022 udelay(40);
8023 tw32_f(MAC_MODE, tp->mac_mode);
8024 udelay(40);
8025 }
1da177e4
LT		 8026 tg3_setup_phy(tp, 0);
8027 }
747e8f8b
MC		 8028 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8029 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8030
8031 tp->timer_counter = tp->timer_multiplier;
8032 }
8033
130b8e4d
MC		 8034 /* Heartbeat is only sent once every 2 seconds.
8035 *
8036 * The heartbeat is to tell the ASF firmware that the host
8037 * driver is still alive. In the event that the OS crashes,
8038 * ASF needs to reset the hardware to free up the FIFO space
8039 * that may be filled with rx packets destined for the host.
8040 * If the FIFO is full, ASF will no longer function properly.
8041 *
8042 * Unintended resets have been reported on real time kernels
8043 * where the timer doesn't run on time. Netpoll will also have
8044 * same problem.
8045 *
8046 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8047 * to check the ring condition when the heartbeat is expiring
8048 * before doing the reset. This will prevent most unintended
8049 * resets.
8050 */
1da177e4 8051 if (!--tp->asf_counter) {
bc7959b2
MC		 8052 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8053 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8054 tg3_wait_for_event_ack(tp);
8055
bbadf503 8056 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8057 FWCMD_NICDRV_ALIVE3);
bbadf503 8058 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8059 /* 5 seconds timeout */
bbadf503 8060 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8061
8062 tg3_generate_fw_event(tp);
1da177e4
LT		 8063 }
8064 tp->asf_counter = tp->asf_multiplier;
8065 }
8066
f47c11ee 8067 spin_unlock(&tp->lock);
1da177e4 8068
f475f163 8069restart_timer:
1da177e4
LT		 8070 tp->timer.expires = jiffies + tp->timer_offset;
8071 add_timer(&tp->timer);
8072}
8073
4f125f42 8074static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8075{
7d12e780 8076 irq_handler_t fn;
fcfa0a32 8077 unsigned long flags;
4f125f42
MC		 8078 char *name;
8079 struct tg3_napi *tnapi = &tp->napi[irq_num];
8080
8081 if (tp->irq_cnt == 1)
8082 name = tp->dev->name;
8083 else {
8084 name = &tnapi->irq_lbl[0];
8085 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8086 name[IFNAMSIZ-1] = 0;
8087 }
fcfa0a32 8088
679563f4 8089 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8090 fn = tg3_msi;
8091 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8092 fn = tg3_msi_1shot;
1fb9df5d 8093 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8094 } else {
8095 fn = tg3_interrupt;
8096 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8097 fn = tg3_interrupt_tagged;
1fb9df5d 8098 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8099 }
4f125f42
MC		 8100
8101 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8102}
8103
7938109f
MC		 8104static int tg3_test_interrupt(struct tg3 *tp)
8105{
09943a18 8106 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8107 struct net_device *dev = tp->dev;
b16250e3 8108 int err, i, intr_ok = 0;
f6eb9b1f 8109 u32 val;
7938109f 8110
d4bc3927
MC		 8111 if (!netif_running(dev))
8112 return -ENODEV;
8113
7938109f
MC		 8114 tg3_disable_ints(tp);
8115
4f125f42 8116 free_irq(tnapi->irq_vec, tnapi);
7938109f 8117
f6eb9b1f
MC		 8118 /*
8119 * Turn off MSI one shot mode. Otherwise this test has no
8120 * observable way to know whether the interrupt was delivered.
8121 */
8122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8123 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8124 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8125 tw32(MSGINT_MODE, val);
8126 }
8127
4f125f42 8128 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8129 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8130 if (err)
8131 return err;
8132
898a56f8 8133 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8134 tg3_enable_ints(tp);
8135
8136 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8137 tnapi->coal_now);
7938109f
MC		 8138
8139 for (i = 0; i < 5; i++) {
b16250e3
MC		 8140 u32 int_mbox, misc_host_ctrl;
8141
898a56f8 8142 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8143 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8144
8145 if ((int_mbox != 0) ||
8146 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8147 intr_ok = 1;
7938109f 8148 break;
b16250e3
MC		 8149 }
8150
7938109f
MC		 8151 msleep(10);
8152 }
8153
8154 tg3_disable_ints(tp);
8155
4f125f42 8156 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8157
4f125f42 8158 err = tg3_request_irq(tp, 0);
7938109f
MC		 8159
8160 if (err)
8161 return err;
8162
f6eb9b1f
MC		 8163 if (intr_ok) {
8164 /* Reenable MSI one shot mode. */
8165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8166 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8167 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8168 tw32(MSGINT_MODE, val);
8169 }
7938109f 8170 return 0;
f6eb9b1f 8171 }
7938109f
MC		 8172
8173 return -EIO;
8174}
8175
8176/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8177 * successfully restored
8178 */
8179static int tg3_test_msi(struct tg3 *tp)
8180{
7938109f
MC		 8181 int err;
8182 u16 pci_cmd;
8183
8184 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8185 return 0;
8186
8187 /* Turn off SERR reporting in case MSI terminates with Master
8188 * Abort.
8189 */
8190 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8191 pci_write_config_word(tp->pdev, PCI_COMMAND,
8192 pci_cmd & ~PCI_COMMAND_SERR);
8193
8194 err = tg3_test_interrupt(tp);
8195
8196 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8197
8198 if (!err)
8199 return 0;
8200
8201 /* other failures */
8202 if (err != -EIO)
8203 return err;
8204
8205 /* MSI test failed, go back to INTx mode */
8206 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8207 "switching to INTx mode. Please report this failure to "
8208 "the PCI maintainer and include system chipset information.\n",
8209 tp->dev->name);
8210
4f125f42 8211 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8212
7938109f
MC		 8213 pci_disable_msi(tp->pdev);
8214
8215 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8216
4f125f42 8217 err = tg3_request_irq(tp, 0);
7938109f
MC		 8218 if (err)
8219 return err;
8220
8221 /* Need to reset the chip because the MSI cycle may have terminated
8222 * with Master Abort.
8223 */
f47c11ee 8224 tg3_full_lock(tp, 1);
7938109f 8225
944d980e 8226 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8227 err = tg3_init_hw(tp, 1);
7938109f 8228
f47c11ee 8229 tg3_full_unlock(tp);
7938109f
MC		 8230
8231 if (err)
4f125f42 8232 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8233
8234 return err;
8235}
8236
9e9fd12d
MC		 8237static int tg3_request_firmware(struct tg3 *tp)
8238{
8239 const __be32 *fw_data;
8240
8241 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8242 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8243 tp->dev->name, tp->fw_needed);
8244 return -ENOENT;
8245 }
8246
8247 fw_data = (void *)tp->fw->data;
8248
8249 /* Firmware blob starts with version numbers, followed by
8250 * start address and _full_ length including BSS sections
8251 * (which must be longer than the actual data, of course
8252 */
8253
8254 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8255 if (tp->fw_len < (tp->fw->size - 12)) {
8256 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8257 tp->dev->name, tp->fw_len, tp->fw_needed);
8258 release_firmware(tp->fw);
8259 tp->fw = NULL;
8260 return -EINVAL;
8261 }
8262
8263 /* We no longer need firmware; we have it. */
8264 tp->fw_needed = NULL;
8265 return 0;
8266}
8267
679563f4
MC		 8268static bool tg3_enable_msix(struct tg3 *tp)
8269{
8270 int i, rc, cpus = num_online_cpus();
8271 struct msix_entry msix_ent[tp->irq_max];
8272
8273 if (cpus == 1)
8274 /* Just fallback to the simpler MSI mode. */
8275 return false;
8276
8277 /*
8278 * We want as many rx rings enabled as there are cpus.
8279 * The first MSIX vector only deals with link interrupts, etc,
8280 * so we add one to the number of vectors we are requesting.
8281 */
8282 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8283
8284 for (i = 0; i < tp->irq_max; i++) {
8285 msix_ent[i].entry = i;
8286 msix_ent[i].vector = 0;
8287 }
8288
8289 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8290 if (rc != 0) {
8291 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8292 return false;
8293 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8294 return false;
8295 printk(KERN_NOTICE
8296 "%s: Requested %d MSI-X vectors, received %d\n",
8297 tp->dev->name, tp->irq_cnt, rc);
8298 tp->irq_cnt = rc;
8299 }
8300
baf8a94a
MC		 8301 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8302
679563f4
MC		 8303 for (i = 0; i < tp->irq_max; i++)
8304 tp->napi[i].irq_vec = msix_ent[i].vector;
8305
fe5f5787
MC		 8306 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8307
679563f4
MC		 8308 return true;
8309}
8310
07b0173c
MC		 8311static void tg3_ints_init(struct tg3 *tp)
8312{
679563f4
MC		 8313 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8314 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8315 /* All MSI supporting chips should support tagged
8316 * status. Assert that this is the case.
8317 */
679563f4
MC		 8318 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8319 "Not using MSI.\n", tp->dev->name);
8320 goto defcfg;
07b0173c 8321 }
4f125f42 8322
679563f4
MC		 8323 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8324 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8325 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8326 pci_enable_msi(tp->pdev) == 0)
8327 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8328
8329 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8330 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8331 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8332 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8333 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8334 }
8335defcfg:
8336 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8337 tp->irq_cnt = 1;
8338 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8339 tp->dev->real_num_tx_queues = 1;
679563f4 8340 }
07b0173c
MC		 8341}
8342
8343static void tg3_ints_fini(struct tg3 *tp)
8344{
679563f4
MC		 8345 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8346 pci_disable_msix(tp->pdev);
8347 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8348 pci_disable_msi(tp->pdev);
8349 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8350 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8351}
8352
1da177e4
LT		 8353static int tg3_open(struct net_device *dev)
8354{
8355 struct tg3 *tp = netdev_priv(dev);
4f125f42 8356 int i, err;
1da177e4 8357
9e9fd12d
MC		 8358 if (tp->fw_needed) {
8359 err = tg3_request_firmware(tp);
8360 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8361 if (err)
8362 return err;
8363 } else if (err) {
8364 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8365 tp->dev->name);
8366 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8367 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8368 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8369 tp->dev->name);
8370 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8371 }
8372 }
8373
c49a1561
MC		 8374 netif_carrier_off(tp->dev);
8375
bc1c7567 8376 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8377 if (err)
bc1c7567 8378 return err;
2f751b67
MC		 8379
8380 tg3_full_lock(tp, 0);
bc1c7567 8381
1da177e4
LT		 8382 tg3_disable_ints(tp);
8383 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8384
f47c11ee 8385 tg3_full_unlock(tp);
1da177e4 8386
679563f4
MC		 8387 /*
8388 * Setup interrupts first so we know how
8389 * many NAPI resources to allocate
8390 */
8391 tg3_ints_init(tp);
8392
1da177e4
LT		 8393 /* The placement of this call is tied
8394 * to the setup and use of Host TX descriptors.
8395 */
8396 err = tg3_alloc_consistent(tp);
8397 if (err)
679563f4 8398 goto err_out1;
88b06bc2 8399
fed97810 8400 tg3_napi_enable(tp);
1da177e4 8401
4f125f42
MC		 8402 for (i = 0; i < tp->irq_cnt; i++) {
8403 struct tg3_napi *tnapi = &tp->napi[i];
8404 err = tg3_request_irq(tp, i);
8405 if (err) {
8406 for (i--; i >= 0; i--)
8407 free_irq(tnapi->irq_vec, tnapi);
8408 break;
8409 }
8410 }
1da177e4 8411
07b0173c 8412 if (err)
679563f4 8413 goto err_out2;
bea3348e 8414
f47c11ee 8415 tg3_full_lock(tp, 0);
1da177e4 8416
8e7a22e3 8417 err = tg3_init_hw(tp, 1);
1da177e4 8418 if (err) {
944d980e 8419 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8420 tg3_free_rings(tp);
8421 } else {
fac9b83e
DM		 8422 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8423 tp->timer_offset = HZ;
8424 else
8425 tp->timer_offset = HZ / 10;
8426
8427 BUG_ON(tp->timer_offset > HZ);
8428 tp->timer_counter = tp->timer_multiplier =
8429 (HZ / tp->timer_offset);
8430 tp->asf_counter = tp->asf_multiplier =
28fbef78 8431 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8432
8433 init_timer(&tp->timer);
8434 tp->timer.expires = jiffies + tp->timer_offset;
8435 tp->timer.data = (unsigned long) tp;
8436 tp->timer.function = tg3_timer;
1da177e4
LT		 8437 }
8438
f47c11ee 8439 tg3_full_unlock(tp);
1da177e4 8440
07b0173c 8441 if (err)
679563f4 8442 goto err_out3;
1da177e4 8443
7938109f
MC		 8444 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8445 err = tg3_test_msi(tp);
fac9b83e 8446
7938109f 8447 if (err) {
f47c11ee 8448 tg3_full_lock(tp, 0);
944d980e 8449 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8450 tg3_free_rings(tp);
f47c11ee 8451 tg3_full_unlock(tp);
7938109f 8452
679563f4 8453 goto err_out2;
7938109f 8454 }
fcfa0a32 8455
f6eb9b1f
MC		 8456 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8457 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8458 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8459 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8460
f6eb9b1f
MC		 8461 tw32(PCIE_TRANSACTION_CFG,
8462 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8463 }
7938109f
MC		 8464 }
8465
b02fd9e3
MC		 8466 tg3_phy_start(tp);
8467
f47c11ee 8468 tg3_full_lock(tp, 0);
1da177e4 8469
7938109f
MC		 8470 add_timer(&tp->timer);
8471 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8472 tg3_enable_ints(tp);
8473
f47c11ee 8474 tg3_full_unlock(tp);
1da177e4 8475
fe5f5787 8476 netif_tx_start_all_queues(dev);
1da177e4
LT		 8477
8478 return 0;
07b0173c 8479
679563f4 8480err_out3:
4f125f42
MC		 8481 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8482 struct tg3_napi *tnapi = &tp->napi[i];
8483 free_irq(tnapi->irq_vec, tnapi);
8484 }
07b0173c 8485
679563f4 8486err_out2:
fed97810 8487 tg3_napi_disable(tp);
07b0173c 8488 tg3_free_consistent(tp);
679563f4
MC		 8489
8490err_out1:
8491 tg3_ints_fini(tp);
07b0173c 8492 return err;
1da177e4
LT		 8493}
8494
8495#if 0
8496/*static*/ void tg3_dump_state(struct tg3 *tp)
8497{
8498 u32 val32, val32_2, val32_3, val32_4, val32_5;
8499 u16 val16;
8500 int i;
898a56f8 8501 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8502
8503 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8504 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8505 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8506 val16, val32);
8507
8508 /* MAC block */
8509 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8510 tr32(MAC_MODE), tr32(MAC_STATUS));
8511 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8512 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8513 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8514 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8515 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8516 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8517
8518 /* Send data initiator control block */
8519 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8520 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8521 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8522 tr32(SNDDATAI_STATSCTRL));
8523
8524 /* Send data completion control block */
8525 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8526
8527 /* Send BD ring selector block */
8528 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8529 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8530
8531 /* Send BD initiator control block */
8532 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8533 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8534
8535 /* Send BD completion control block */
8536 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8537
8538 /* Receive list placement control block */
8539 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8540 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8541 printk(" RCVLPC_STATSCTRL[%08x]\n",
8542 tr32(RCVLPC_STATSCTRL));
8543
8544 /* Receive data and receive BD initiator control block */
8545 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8546 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8547
8548 /* Receive data completion control block */
8549 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8550 tr32(RCVDCC_MODE));
8551
8552 /* Receive BD initiator control block */
8553 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8554 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8555
8556 /* Receive BD completion control block */
8557 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8558 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8559
8560 /* Receive list selector control block */
8561 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8562 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8563
8564 /* Mbuf cluster free block */
8565 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8566 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8567
8568 /* Host coalescing control block */
8569 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8570 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8571 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8572 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8573 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8574 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8575 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8576 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8577 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8578 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8579 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8580 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8581
8582 /* Memory arbiter control block */
8583 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8584 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8585
8586 /* Buffer manager control block */
8587 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8588 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8589 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8590 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8591 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8592 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8593 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8594 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8595
8596 /* Read DMA control block */
8597 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8598 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8599
8600 /* Write DMA control block */
8601 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8602 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8603
8604 /* DMA completion block */
8605 printk("DEBUG: DMAC_MODE[%08x]\n",
8606 tr32(DMAC_MODE));
8607
8608 /* GRC block */
8609 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8610 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8611 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8612 tr32(GRC_LOCAL_CTRL));
8613
8614 /* TG3_BDINFOs */
8615 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8616 tr32(RCVDBDI_JUMBO_BD + 0x0),
8617 tr32(RCVDBDI_JUMBO_BD + 0x4),
8618 tr32(RCVDBDI_JUMBO_BD + 0x8),
8619 tr32(RCVDBDI_JUMBO_BD + 0xc));
8620 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8621 tr32(RCVDBDI_STD_BD + 0x0),
8622 tr32(RCVDBDI_STD_BD + 0x4),
8623 tr32(RCVDBDI_STD_BD + 0x8),
8624 tr32(RCVDBDI_STD_BD + 0xc));
8625 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8626 tr32(RCVDBDI_MINI_BD + 0x0),
8627 tr32(RCVDBDI_MINI_BD + 0x4),
8628 tr32(RCVDBDI_MINI_BD + 0x8),
8629 tr32(RCVDBDI_MINI_BD + 0xc));
8630
8631 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8632 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8633 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8634 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8635 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8636 val32, val32_2, val32_3, val32_4);
8637
8638 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8639 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8640 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8641 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8642 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8643 val32, val32_2, val32_3, val32_4);
8644
8645 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8646 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8647 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8648 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8649 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8650 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8651 val32, val32_2, val32_3, val32_4, val32_5);
8652
8653 /* SW status block */
898a56f8
MC		 8654 printk(KERN_DEBUG
8655 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8656 sblk->status,
8657 sblk->status_tag,
8658 sblk->rx_jumbo_consumer,
8659 sblk->rx_consumer,
8660 sblk->rx_mini_consumer,
8661 sblk->idx[0].rx_producer,
8662 sblk->idx[0].tx_consumer);
1da177e4
LT		 8663
8664 /* SW statistics block */
8665 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8666 ((u32 *)tp->hw_stats)[0],
8667 ((u32 *)tp->hw_stats)[1],
8668 ((u32 *)tp->hw_stats)[2],
8669 ((u32 *)tp->hw_stats)[3]);
8670
8671 /* Mailboxes */
8672 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8673 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8674 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8675 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8676 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8677
8678 /* NIC side send descriptors. */
8679 for (i = 0; i < 6; i++) {
8680 unsigned long txd;
8681
8682 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8683 + (i * sizeof(struct tg3_tx_buffer_desc));
8684 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8685 i,
8686 readl(txd + 0x0), readl(txd + 0x4),
8687 readl(txd + 0x8), readl(txd + 0xc));
8688 }
8689
8690 /* NIC side RX descriptors. */
8691 for (i = 0; i < 6; i++) {
8692 unsigned long rxd;
8693
8694 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8695 + (i * sizeof(struct tg3_rx_buffer_desc));
8696 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8697 i,
8698 readl(rxd + 0x0), readl(rxd + 0x4),
8699 readl(rxd + 0x8), readl(rxd + 0xc));
8700 rxd += (4 * sizeof(u32));
8701 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8702 i,
8703 readl(rxd + 0x0), readl(rxd + 0x4),
8704 readl(rxd + 0x8), readl(rxd + 0xc));
8705 }
8706
8707 for (i = 0; i < 6; i++) {
8708 unsigned long rxd;
8709
8710 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8711 + (i * sizeof(struct tg3_rx_buffer_desc));
8712 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8713 i,
8714 readl(rxd + 0x0), readl(rxd + 0x4),
8715 readl(rxd + 0x8), readl(rxd + 0xc));
8716 rxd += (4 * sizeof(u32));
8717 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8718 i,
8719 readl(rxd + 0x0), readl(rxd + 0x4),
8720 readl(rxd + 0x8), readl(rxd + 0xc));
8721 }
8722}
8723#endif
8724
8725static struct net_device_stats *tg3_get_stats(struct net_device *);
8726static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8727
8728static int tg3_close(struct net_device *dev)
8729{
4f125f42 8730 int i;
1da177e4
LT		 8731 struct tg3 *tp = netdev_priv(dev);
8732
fed97810 8733 tg3_napi_disable(tp);
28e53bdd 8734 cancel_work_sync(&tp->reset_task);
7faa006f 8735
fe5f5787 8736 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8737
8738 del_timer_sync(&tp->timer);
8739
24bb4fb6
MC		 8740 tg3_phy_stop(tp);
8741
f47c11ee 8742 tg3_full_lock(tp, 1);
1da177e4
LT		 8743#if 0
8744 tg3_dump_state(tp);
8745#endif
8746
8747 tg3_disable_ints(tp);
8748
944d980e 8749 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8750 tg3_free_rings(tp);
5cf64b8a 8751 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8752
f47c11ee 8753 tg3_full_unlock(tp);
1da177e4 8754
4f125f42
MC		 8755 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8756 struct tg3_napi *tnapi = &tp->napi[i];
8757 free_irq(tnapi->irq_vec, tnapi);
8758 }
07b0173c
MC		 8759
8760 tg3_ints_fini(tp);
1da177e4
LT		 8761
8762 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8763 sizeof(tp->net_stats_prev));
8764 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8765 sizeof(tp->estats_prev));
8766
8767 tg3_free_consistent(tp);
8768
bc1c7567
MC		 8769 tg3_set_power_state(tp, PCI_D3hot);
8770
8771 netif_carrier_off(tp->dev);
8772
1da177e4
LT		 8773 return 0;
8774}
8775
8776static inline unsigned long get_stat64(tg3_stat64_t *val)
8777{
8778 unsigned long ret;
8779
8780#if (BITS_PER_LONG == 32)
8781 ret = val->low;
8782#else
8783 ret = ((u64)val->high << 32) | ((u64)val->low);
8784#endif
8785 return ret;
8786}
8787
816f8b86
SB		 8788static inline u64 get_estat64(tg3_stat64_t *val)
8789{
8790 return ((u64)val->high << 32) | ((u64)val->low);
8791}
8792
1da177e4
LT		 8793static unsigned long calc_crc_errors(struct tg3 *tp)
8794{
8795 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8796
8797 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8798 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8800 u32 val;
8801
f47c11ee 8802 spin_lock_bh(&tp->lock);
569a5df8
MC		 8803 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8804 tg3_writephy(tp, MII_TG3_TEST1,
8805 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8806 tg3_readphy(tp, 0x14, &val);
8807 } else
8808 val = 0;
f47c11ee 8809 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8810
8811 tp->phy_crc_errors += val;
8812
8813 return tp->phy_crc_errors;
8814 }
8815
8816 return get_stat64(&hw_stats->rx_fcs_errors);
8817}
8818
8819#define ESTAT_ADD(member) \
8820 estats->member = old_estats->member + \
816f8b86 8821 get_estat64(&hw_stats->member)
1da177e4
LT		 8822
8823static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8824{
8825 struct tg3_ethtool_stats *estats = &tp->estats;
8826 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8827 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8828
8829 if (!hw_stats)
8830 return old_estats;
8831
8832 ESTAT_ADD(rx_octets);
8833 ESTAT_ADD(rx_fragments);
8834 ESTAT_ADD(rx_ucast_packets);
8835 ESTAT_ADD(rx_mcast_packets);
8836 ESTAT_ADD(rx_bcast_packets);
8837 ESTAT_ADD(rx_fcs_errors);
8838 ESTAT_ADD(rx_align_errors);
8839 ESTAT_ADD(rx_xon_pause_rcvd);
8840 ESTAT_ADD(rx_xoff_pause_rcvd);
8841 ESTAT_ADD(rx_mac_ctrl_rcvd);
8842 ESTAT_ADD(rx_xoff_entered);
8843 ESTAT_ADD(rx_frame_too_long_errors);
8844 ESTAT_ADD(rx_jabbers);
8845 ESTAT_ADD(rx_undersize_packets);
8846 ESTAT_ADD(rx_in_length_errors);
8847 ESTAT_ADD(rx_out_length_errors);
8848 ESTAT_ADD(rx_64_or_less_octet_packets);
8849 ESTAT_ADD(rx_65_to_127_octet_packets);
8850 ESTAT_ADD(rx_128_to_255_octet_packets);
8851 ESTAT_ADD(rx_256_to_511_octet_packets);
8852 ESTAT_ADD(rx_512_to_1023_octet_packets);
8853 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8854 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8855 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8856 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8857 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8858
8859 ESTAT_ADD(tx_octets);
8860 ESTAT_ADD(tx_collisions);
8861 ESTAT_ADD(tx_xon_sent);
8862 ESTAT_ADD(tx_xoff_sent);
8863 ESTAT_ADD(tx_flow_control);
8864 ESTAT_ADD(tx_mac_errors);
8865 ESTAT_ADD(tx_single_collisions);
8866 ESTAT_ADD(tx_mult_collisions);
8867 ESTAT_ADD(tx_deferred);
8868 ESTAT_ADD(tx_excessive_collisions);
8869 ESTAT_ADD(tx_late_collisions);
8870 ESTAT_ADD(tx_collide_2times);
8871 ESTAT_ADD(tx_collide_3times);
8872 ESTAT_ADD(tx_collide_4times);
8873 ESTAT_ADD(tx_collide_5times);
8874 ESTAT_ADD(tx_collide_6times);
8875 ESTAT_ADD(tx_collide_7times);
8876 ESTAT_ADD(tx_collide_8times);
8877 ESTAT_ADD(tx_collide_9times);
8878 ESTAT_ADD(tx_collide_10times);
8879 ESTAT_ADD(tx_collide_11times);
8880 ESTAT_ADD(tx_collide_12times);
8881 ESTAT_ADD(tx_collide_13times);
8882 ESTAT_ADD(tx_collide_14times);
8883 ESTAT_ADD(tx_collide_15times);
8884 ESTAT_ADD(tx_ucast_packets);
8885 ESTAT_ADD(tx_mcast_packets);
8886 ESTAT_ADD(tx_bcast_packets);
8887 ESTAT_ADD(tx_carrier_sense_errors);
8888 ESTAT_ADD(tx_discards);
8889 ESTAT_ADD(tx_errors);
8890
8891 ESTAT_ADD(dma_writeq_full);
8892 ESTAT_ADD(dma_write_prioq_full);
8893 ESTAT_ADD(rxbds_empty);
8894 ESTAT_ADD(rx_discards);
8895 ESTAT_ADD(rx_errors);
8896 ESTAT_ADD(rx_threshold_hit);
8897
8898 ESTAT_ADD(dma_readq_full);
8899 ESTAT_ADD(dma_read_prioq_full);
8900 ESTAT_ADD(tx_comp_queue_full);
8901
8902 ESTAT_ADD(ring_set_send_prod_index);
8903 ESTAT_ADD(ring_status_update);
8904 ESTAT_ADD(nic_irqs);
8905 ESTAT_ADD(nic_avoided_irqs);
8906 ESTAT_ADD(nic_tx_threshold_hit);
8907
8908 return estats;
8909}
8910
8911static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8912{
8913 struct tg3 *tp = netdev_priv(dev);
8914 struct net_device_stats *stats = &tp->net_stats;
8915 struct net_device_stats *old_stats = &tp->net_stats_prev;
8916 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8917
8918 if (!hw_stats)
8919 return old_stats;
8920
8921 stats->rx_packets = old_stats->rx_packets +
8922 get_stat64(&hw_stats->rx_ucast_packets) +
8923 get_stat64(&hw_stats->rx_mcast_packets) +
8924 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8925
1da177e4
LT		 8926 stats->tx_packets = old_stats->tx_packets +
8927 get_stat64(&hw_stats->tx_ucast_packets) +
8928 get_stat64(&hw_stats->tx_mcast_packets) +
8929 get_stat64(&hw_stats->tx_bcast_packets);
8930
8931 stats->rx_bytes = old_stats->rx_bytes +
8932 get_stat64(&hw_stats->rx_octets);
8933 stats->tx_bytes = old_stats->tx_bytes +
8934 get_stat64(&hw_stats->tx_octets);
8935
8936 stats->rx_errors = old_stats->rx_errors +
4f63b877 8937 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8938 stats->tx_errors = old_stats->tx_errors +
8939 get_stat64(&hw_stats->tx_errors) +
8940 get_stat64(&hw_stats->tx_mac_errors) +
8941 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8942 get_stat64(&hw_stats->tx_discards);
8943
8944 stats->multicast = old_stats->multicast +
8945 get_stat64(&hw_stats->rx_mcast_packets);
8946 stats->collisions = old_stats->collisions +
8947 get_stat64(&hw_stats->tx_collisions);
8948
8949 stats->rx_length_errors = old_stats->rx_length_errors +
8950 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8951 get_stat64(&hw_stats->rx_undersize_packets);
8952
8953 stats->rx_over_errors = old_stats->rx_over_errors +
8954 get_stat64(&hw_stats->rxbds_empty);
8955 stats->rx_frame_errors = old_stats->rx_frame_errors +
8956 get_stat64(&hw_stats->rx_align_errors);
8957 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8958 get_stat64(&hw_stats->tx_discards);
8959 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8960 get_stat64(&hw_stats->tx_carrier_sense_errors);
8961
8962 stats->rx_crc_errors = old_stats->rx_crc_errors +
8963 calc_crc_errors(tp);
8964
4f63b877
JL		 8965 stats->rx_missed_errors = old_stats->rx_missed_errors +
8966 get_stat64(&hw_stats->rx_discards);
8967
1da177e4
LT		 8968 return stats;
8969}
8970
8971static inline u32 calc_crc(unsigned char *buf, int len)
8972{
8973 u32 reg;
8974 u32 tmp;
8975 int j, k;
8976
8977 reg = 0xffffffff;
8978
8979 for (j = 0; j < len; j++) {
8980 reg ^= buf[j];
8981
8982 for (k = 0; k < 8; k++) {
8983 tmp = reg & 0x01;
8984
8985 reg >>= 1;
8986
8987 if (tmp) {
8988 reg ^= 0xedb88320;
8989 }
8990 }
8991 }
8992
8993 return ~reg;
8994}
8995
8996static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8997{
8998 /* accept or reject all multicast frames */
8999 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9000 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9001 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9002 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9003}
9004
9005static void __tg3_set_rx_mode(struct net_device *dev)
9006{
9007 struct tg3 *tp = netdev_priv(dev);
9008 u32 rx_mode;
9009
9010 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9011 RX_MODE_KEEP_VLAN_TAG);
9012
9013 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9014 * flag clear.
9015 */
9016#if TG3_VLAN_TAG_USED
9017 if (!tp->vlgrp &&
9018 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9019 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9020#else
9021 /* By definition, VLAN is disabled always in this
9022 * case.
9023 */
9024 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9025 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9026#endif
9027
9028 if (dev->flags & IFF_PROMISC) {
9029 /* Promiscuous mode. */
9030 rx_mode |= RX_MODE_PROMISC;
9031 } else if (dev->flags & IFF_ALLMULTI) {
9032 /* Accept all multicast. */
9033 tg3_set_multi (tp, 1);
9034 } else if (dev->mc_count < 1) {
9035 /* Reject all multicast. */
9036 tg3_set_multi (tp, 0);
9037 } else {
9038 /* Accept one or more multicast(s). */
9039 struct dev_mc_list *mclist;
9040 unsigned int i;
9041 u32 mc_filter[4] = { 0, };
9042 u32 regidx;
9043 u32 bit;
9044 u32 crc;
9045
9046 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9047 i++, mclist = mclist->next) {
9048
9049 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9050 bit = ~crc & 0x7f;
9051 regidx = (bit & 0x60) >> 5;
9052 bit &= 0x1f;
9053 mc_filter[regidx] |= (1 << bit);
9054 }
9055
9056 tw32(MAC_HASH_REG_0, mc_filter[0]);
9057 tw32(MAC_HASH_REG_1, mc_filter[1]);
9058 tw32(MAC_HASH_REG_2, mc_filter[2]);
9059 tw32(MAC_HASH_REG_3, mc_filter[3]);
9060 }
9061
9062 if (rx_mode != tp->rx_mode) {
9063 tp->rx_mode = rx_mode;
9064 tw32_f(MAC_RX_MODE, rx_mode);
9065 udelay(10);
9066 }
9067}
9068
9069static void tg3_set_rx_mode(struct net_device *dev)
9070{
9071 struct tg3 *tp = netdev_priv(dev);
9072
e75f7c90
MC		 9073 if (!netif_running(dev))
9074 return;
9075
f47c11ee 9076 tg3_full_lock(tp, 0);
1da177e4 9077 __tg3_set_rx_mode(dev);
f47c11ee 9078 tg3_full_unlock(tp);
1da177e4
LT		 9079}
9080
9081#define TG3_REGDUMP_LEN (32 * 1024)
9082
9083static int tg3_get_regs_len(struct net_device *dev)
9084{
9085 return TG3_REGDUMP_LEN;
9086}
9087
9088static void tg3_get_regs(struct net_device *dev,
9089 struct ethtool_regs *regs, void *_p)
9090{
9091 u32 *p = _p;
9092 struct tg3 *tp = netdev_priv(dev);
9093 u8 *orig_p = _p;
9094 int i;
9095
9096 regs->version = 0;
9097
9098 memset(p, 0, TG3_REGDUMP_LEN);
9099
bc1c7567
MC		 9100 if (tp->link_config.phy_is_low_power)
9101 return;
9102
f47c11ee 9103 tg3_full_lock(tp, 0);
1da177e4
LT		 9104
9105#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9106#define GET_REG32_LOOP(base,len) \
9107do { p = (u32 *)(orig_p + (base)); \
9108 for (i = 0; i < len; i += 4) \
9109 __GET_REG32((base) + i); \
9110} while (0)
9111#define GET_REG32_1(reg) \
9112do { p = (u32 *)(orig_p + (reg)); \
9113 __GET_REG32((reg)); \
9114} while (0)
9115
9116 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9117 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9118 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9119 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9120 GET_REG32_1(SNDDATAC_MODE);
9121 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9122 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9123 GET_REG32_1(SNDBDC_MODE);
9124 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9125 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9126 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9127 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9128 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9129 GET_REG32_1(RCVDCC_MODE);
9130 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9131 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9132 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9133 GET_REG32_1(MBFREE_MODE);
9134 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9135 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9136 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9137 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9138 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9139 GET_REG32_1(RX_CPU_MODE);
9140 GET_REG32_1(RX_CPU_STATE);
9141 GET_REG32_1(RX_CPU_PGMCTR);
9142 GET_REG32_1(RX_CPU_HWBKPT);
9143 GET_REG32_1(TX_CPU_MODE);
9144 GET_REG32_1(TX_CPU_STATE);
9145 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9146 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9147 GET_REG32_LOOP(FTQ_RESET, 0x120);
9148 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9149 GET_REG32_1(DMAC_MODE);
9150 GET_REG32_LOOP(GRC_MODE, 0x4c);
9151 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9152 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9153
9154#undef __GET_REG32
9155#undef GET_REG32_LOOP
9156#undef GET_REG32_1
9157
f47c11ee 9158 tg3_full_unlock(tp);
1da177e4
LT		 9159}
9160
9161static int tg3_get_eeprom_len(struct net_device *dev)
9162{
9163 struct tg3 *tp = netdev_priv(dev);
9164
9165 return tp->nvram_size;
9166}
9167
1da177e4
LT		 9168static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9169{
9170 struct tg3 *tp = netdev_priv(dev);
9171 int ret;
9172 u8 *pd;
b9fc7dc5 9173 u32 i, offset, len, b_offset, b_count;
a9dc529d 9174 __be32 val;
1da177e4 9175
df259d8c
MC		 9176 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9177 return -EINVAL;
9178
bc1c7567
MC		 9179 if (tp->link_config.phy_is_low_power)
9180 return -EAGAIN;
9181
1da177e4
LT		 9182 offset = eeprom->offset;
9183 len = eeprom->len;
9184 eeprom->len = 0;
9185
9186 eeprom->magic = TG3_EEPROM_MAGIC;
9187
9188 if (offset & 3) {
9189 /* adjustments to start on required 4 byte boundary */
9190 b_offset = offset & 3;
9191 b_count = 4 - b_offset;
9192 if (b_count > len) {
9193 /* i.e. offset=1 len=2 */
9194 b_count = len;
9195 }
a9dc529d 9196 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9197 if (ret)
9198 return ret;
1da177e4
LT		 9199 memcpy(data, ((char*)&val) + b_offset, b_count);
9200 len -= b_count;
9201 offset += b_count;
9202 eeprom->len += b_count;
9203 }
9204
9205 /* read bytes upto the last 4 byte boundary */
9206 pd = &data[eeprom->len];
9207 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9208 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9209 if (ret) {
9210 eeprom->len += i;
9211 return ret;
9212 }
1da177e4
LT		 9213 memcpy(pd + i, &val, 4);
9214 }
9215 eeprom->len += i;
9216
9217 if (len & 3) {
9218 /* read last bytes not ending on 4 byte boundary */
9219 pd = &data[eeprom->len];
9220 b_count = len & 3;
9221 b_offset = offset + len - b_count;
a9dc529d 9222 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9223 if (ret)
9224 return ret;
b9fc7dc5 9225 memcpy(pd, &val, b_count);
1da177e4
LT		 9226 eeprom->len += b_count;
9227 }
9228 return 0;
9229}
9230
6aa20a22 9231static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9232
9233static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9234{
9235 struct tg3 *tp = netdev_priv(dev);
9236 int ret;
b9fc7dc5 9237 u32 offset, len, b_offset, odd_len;
1da177e4 9238 u8 *buf;
a9dc529d 9239 __be32 start, end;
1da177e4 9240
bc1c7567
MC		 9241 if (tp->link_config.phy_is_low_power)
9242 return -EAGAIN;
9243
df259d8c
MC		 9244 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9245 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9246 return -EINVAL;
9247
9248 offset = eeprom->offset;
9249 len = eeprom->len;
9250
9251 if ((b_offset = (offset & 3))) {
9252 /* adjustments to start on required 4 byte boundary */
a9dc529d 9253 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9254 if (ret)
9255 return ret;
1da177e4
LT		 9256 len += b_offset;
9257 offset &= ~3;
1c8594b4
MC		 9258 if (len < 4)
9259 len = 4;
1da177e4
LT		 9260 }
9261
9262 odd_len = 0;
1c8594b4 9263 if (len & 3) {
1da177e4
LT		 9264 /* adjustments to end on required 4 byte boundary */
9265 odd_len = 1;
9266 len = (len + 3) & ~3;
a9dc529d 9267 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9268 if (ret)
9269 return ret;
1da177e4
LT		 9270 }
9271
9272 buf = data;
9273 if (b_offset || odd_len) {
9274 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9275 if (!buf)
1da177e4
LT		 9276 return -ENOMEM;
9277 if (b_offset)
9278 memcpy(buf, &start, 4);
9279 if (odd_len)
9280 memcpy(buf+len-4, &end, 4);
9281 memcpy(buf + b_offset, data, eeprom->len);
9282 }
9283
9284 ret = tg3_nvram_write_block(tp, offset, len, buf);
9285
9286 if (buf != data)
9287 kfree(buf);
9288
9289 return ret;
9290}
9291
9292static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9293{
b02fd9e3
MC		 9294 struct tg3 *tp = netdev_priv(dev);
9295
9296 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9297 struct phy_device *phydev;
b02fd9e3
MC		 9298 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9299 return -EAGAIN;
3f0e3ad7
MC		 9300 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9301 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9302 }
6aa20a22 9303
1da177e4
LT		 9304 cmd->supported = (SUPPORTED_Autoneg);
9305
9306 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9307 cmd->supported |= (SUPPORTED_1000baseT_Half |
9308 SUPPORTED_1000baseT_Full);
9309
ef348144 9310 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9311 cmd->supported |= (SUPPORTED_100baseT_Half |
9312 SUPPORTED_100baseT_Full |
9313 SUPPORTED_10baseT_Half |
9314 SUPPORTED_10baseT_Full |
3bebab59 9315 SUPPORTED_TP);
ef348144
KK		 9316 cmd->port = PORT_TP;
9317 } else {
1da177e4 9318 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9319 cmd->port = PORT_FIBRE;
9320 }
6aa20a22 9321
1da177e4
LT		 9322 cmd->advertising = tp->link_config.advertising;
9323 if (netif_running(dev)) {
9324 cmd->speed = tp->link_config.active_speed;
9325 cmd->duplex = tp->link_config.active_duplex;
9326 }
882e9793 9327 cmd->phy_address = tp->phy_addr;
7e5856bd 9328 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9329 cmd->autoneg = tp->link_config.autoneg;
9330 cmd->maxtxpkt = 0;
9331 cmd->maxrxpkt = 0;
9332 return 0;
9333}
6aa20a22 9334
1da177e4
LT		 9335static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9336{
9337 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9338
b02fd9e3 9339 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9340 struct phy_device *phydev;
b02fd9e3
MC		 9341 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9342 return -EAGAIN;
3f0e3ad7
MC		 9343 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9344 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9345 }
9346
7e5856bd
MC		 9347 if (cmd->autoneg != AUTONEG_ENABLE &&
9348 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9349 return -EINVAL;
7e5856bd
MC		 9350
9351 if (cmd->autoneg == AUTONEG_DISABLE &&
9352 cmd->duplex != DUPLEX_FULL &&
9353 cmd->duplex != DUPLEX_HALF)
37ff238d 9354 return -EINVAL;
1da177e4 9355
7e5856bd
MC		 9356 if (cmd->autoneg == AUTONEG_ENABLE) {
9357 u32 mask = ADVERTISED_Autoneg |
9358 ADVERTISED_Pause |
9359 ADVERTISED_Asym_Pause;
9360
9361 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9362 mask |= ADVERTISED_1000baseT_Half |
9363 ADVERTISED_1000baseT_Full;
9364
9365 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9366 mask |= ADVERTISED_100baseT_Half |
9367 ADVERTISED_100baseT_Full |
9368 ADVERTISED_10baseT_Half |
9369 ADVERTISED_10baseT_Full |
9370 ADVERTISED_TP;
9371 else
9372 mask |= ADVERTISED_FIBRE;
9373
9374 if (cmd->advertising & ~mask)
9375 return -EINVAL;
9376
9377 mask &= (ADVERTISED_1000baseT_Half |
9378 ADVERTISED_1000baseT_Full |
9379 ADVERTISED_100baseT_Half |
9380 ADVERTISED_100baseT_Full |
9381 ADVERTISED_10baseT_Half |
9382 ADVERTISED_10baseT_Full);
9383
9384 cmd->advertising &= mask;
9385 } else {
9386 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9387 if (cmd->speed != SPEED_1000)
9388 return -EINVAL;
9389
9390 if (cmd->duplex != DUPLEX_FULL)
9391 return -EINVAL;
9392 } else {
9393 if (cmd->speed != SPEED_100 &&
9394 cmd->speed != SPEED_10)
9395 return -EINVAL;
9396 }
9397 }
9398
f47c11ee 9399 tg3_full_lock(tp, 0);
1da177e4
LT		 9400
9401 tp->link_config.autoneg = cmd->autoneg;
9402 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9403 tp->link_config.advertising = (cmd->advertising |
9404 ADVERTISED_Autoneg);
1da177e4
LT		 9405 tp->link_config.speed = SPEED_INVALID;
9406 tp->link_config.duplex = DUPLEX_INVALID;
9407 } else {
9408 tp->link_config.advertising = 0;
9409 tp->link_config.speed = cmd->speed;
9410 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9411 }
6aa20a22 9412
24fcad6b
MC		 9413 tp->link_config.orig_speed = tp->link_config.speed;
9414 tp->link_config.orig_duplex = tp->link_config.duplex;
9415 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9416
1da177e4
LT		 9417 if (netif_running(dev))
9418 tg3_setup_phy(tp, 1);
9419
f47c11ee 9420 tg3_full_unlock(tp);
6aa20a22 9421
1da177e4
LT		 9422 return 0;
9423}
6aa20a22 9424
1da177e4
LT		 9425static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9426{
9427 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9428
1da177e4
LT		 9429 strcpy(info->driver, DRV_MODULE_NAME);
9430 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9431 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9432 strcpy(info->bus_info, pci_name(tp->pdev));
9433}
6aa20a22 9434
1da177e4
LT		 9435static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9436{
9437 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9438
12dac075
RW		 9439 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9440 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9441 wol->supported = WAKE_MAGIC;
9442 else
9443 wol->supported = 0;
1da177e4 9444 wol->wolopts = 0;
05ac4cb7
MC		 9445 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9446 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9447 wol->wolopts = WAKE_MAGIC;
9448 memset(&wol->sopass, 0, sizeof(wol->sopass));
9449}
6aa20a22 9450
1da177e4
LT		 9451static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9452{
9453 struct tg3 *tp = netdev_priv(dev);
12dac075 9454 struct device *dp = &tp->pdev->dev;
6aa20a22 9455
1da177e4
LT		 9456 if (wol->wolopts & ~WAKE_MAGIC)
9457 return -EINVAL;
9458 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9459 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9460 return -EINVAL;
6aa20a22 9461
f47c11ee 9462 spin_lock_bh(&tp->lock);
12dac075 9463 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9464 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9465 device_set_wakeup_enable(dp, true);
9466 } else {
1da177e4 9467 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9468 device_set_wakeup_enable(dp, false);
9469 }
f47c11ee 9470 spin_unlock_bh(&tp->lock);
6aa20a22 9471
1da177e4
LT		 9472 return 0;
9473}
6aa20a22 9474
1da177e4
LT		 9475static u32 tg3_get_msglevel(struct net_device *dev)
9476{
9477 struct tg3 *tp = netdev_priv(dev);
9478 return tp->msg_enable;
9479}
6aa20a22 9480
1da177e4
LT		 9481static void tg3_set_msglevel(struct net_device *dev, u32 value)
9482{
9483 struct tg3 *tp = netdev_priv(dev);
9484 tp->msg_enable = value;
9485}
6aa20a22 9486
1da177e4
LT		 9487static int tg3_set_tso(struct net_device *dev, u32 value)
9488{
9489 struct tg3 *tp = netdev_priv(dev);
9490
9491 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9492 if (value)
9493 return -EINVAL;
9494 return 0;
9495 }
027455ad
MC		 9496 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9497 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9498 if (value) {
b0026624 9499 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9501 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9502 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 9504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9505 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6
MC		 9506 dev->features |= NETIF_F_TSO_ECN;
9507 } else
9508 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9509 }
1da177e4
LT		 9510 return ethtool_op_set_tso(dev, value);
9511}
6aa20a22 9512
1da177e4
LT		 9513static int tg3_nway_reset(struct net_device *dev)
9514{
9515 struct tg3 *tp = netdev_priv(dev);
1da177e4 9516 int r;
6aa20a22 9517
1da177e4
LT		 9518 if (!netif_running(dev))
9519 return -EAGAIN;
9520
c94e3941
MC		 9521 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9522 return -EINVAL;
9523
b02fd9e3
MC		 9524 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9525 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9526 return -EAGAIN;
3f0e3ad7 9527 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9528 } else {
9529 u32 bmcr;
9530
9531 spin_lock_bh(&tp->lock);
9532 r = -EINVAL;
9533 tg3_readphy(tp, MII_BMCR, &bmcr);
9534 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9535 ((bmcr & BMCR_ANENABLE) ||
9536 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9537 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9538 BMCR_ANENABLE);
9539 r = 0;
9540 }
9541 spin_unlock_bh(&tp->lock);
1da177e4 9542 }
6aa20a22 9543
1da177e4
LT		 9544 return r;
9545}
6aa20a22 9546
1da177e4
LT		 9547static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9548{
9549 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9550
1da177e4
LT		 9551 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9552 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9553 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9554 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9555 else
9556 ering->rx_jumbo_max_pending = 0;
9557
9558 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9559
9560 ering->rx_pending = tp->rx_pending;
9561 ering->rx_mini_pending = 0;
4f81c32b
MC		 9562 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9563 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9564 else
9565 ering->rx_jumbo_pending = 0;
9566
f3f3f27e 9567 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9568}
6aa20a22 9569
1da177e4
LT		 9570static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9571{
9572 struct tg3 *tp = netdev_priv(dev);
646c9edd 9573 int i, irq_sync = 0, err = 0;
6aa20a22 9574
1da177e4
LT		 9575 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9576 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9577 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9578 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9579 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9580 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9581 return -EINVAL;
6aa20a22 9582
bbe832c0 9583 if (netif_running(dev)) {
b02fd9e3 9584 tg3_phy_stop(tp);
1da177e4 9585 tg3_netif_stop(tp);
bbe832c0
MC		 9586 irq_sync = 1;
9587 }
1da177e4 9588
bbe832c0 9589 tg3_full_lock(tp, irq_sync);
6aa20a22 9590
1da177e4
LT		 9591 tp->rx_pending = ering->rx_pending;
9592
9593 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9594 tp->rx_pending > 63)
9595 tp->rx_pending = 63;
9596 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9597
9598 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9599 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9600
9601 if (netif_running(dev)) {
944d980e 9602 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9603 err = tg3_restart_hw(tp, 1);
9604 if (!err)
9605 tg3_netif_start(tp);
1da177e4
LT		 9606 }
9607
f47c11ee 9608 tg3_full_unlock(tp);
6aa20a22 9609
b02fd9e3
MC		 9610 if (irq_sync && !err)
9611 tg3_phy_start(tp);
9612
b9ec6c1b 9613 return err;
1da177e4 9614}
6aa20a22 9615
1da177e4
LT		 9616static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9617{
9618 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9619
1da177e4 9620 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9621
e18ce346 9622 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9623 epause->rx_pause = 1;
9624 else
9625 epause->rx_pause = 0;
9626
e18ce346 9627 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9628 epause->tx_pause = 1;
9629 else
9630 epause->tx_pause = 0;
1da177e4 9631}
6aa20a22 9632
1da177e4
LT		 9633static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9634{
9635 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9636 int err = 0;
6aa20a22 9637
b02fd9e3
MC		 9638 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9639 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9640 return -EAGAIN;
1da177e4 9641
b02fd9e3
MC		 9642 if (epause->autoneg) {
9643 u32 newadv;
9644 struct phy_device *phydev;
f47c11ee 9645
3f0e3ad7 9646 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9647
b02fd9e3
MC		 9648 if (epause->rx_pause) {
9649 if (epause->tx_pause)
9650 newadv = ADVERTISED_Pause;
9651 else
9652 newadv = ADVERTISED_Pause |
9653 ADVERTISED_Asym_Pause;
9654 } else if (epause->tx_pause) {
9655 newadv = ADVERTISED_Asym_Pause;
9656 } else
9657 newadv = 0;
9658
9659 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9660 u32 oldadv = phydev->advertising &
9661 (ADVERTISED_Pause |
9662 ADVERTISED_Asym_Pause);
9663 if (oldadv != newadv) {
9664 phydev->advertising &=
9665 ~(ADVERTISED_Pause |
9666 ADVERTISED_Asym_Pause);
9667 phydev->advertising |= newadv;
9668 err = phy_start_aneg(phydev);
9669 }
9670 } else {
9671 tp->link_config.advertising &=
9672 ~(ADVERTISED_Pause |
9673 ADVERTISED_Asym_Pause);
9674 tp->link_config.advertising |= newadv;
9675 }
9676 } else {
9677 if (epause->rx_pause)
e18ce346 9678 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9679 else
e18ce346 9680 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9681
b02fd9e3 9682 if (epause->tx_pause)
e18ce346 9683 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9684 else
e18ce346 9685 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9686
9687 if (netif_running(dev))
9688 tg3_setup_flow_control(tp, 0, 0);
9689 }
9690 } else {
9691 int irq_sync = 0;
9692
9693 if (netif_running(dev)) {
9694 tg3_netif_stop(tp);
9695 irq_sync = 1;
9696 }
9697
9698 tg3_full_lock(tp, irq_sync);
9699
9700 if (epause->autoneg)
9701 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9702 else
9703 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9704 if (epause->rx_pause)
e18ce346 9705 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9706 else
e18ce346 9707 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9708 if (epause->tx_pause)
e18ce346 9709 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9710 else
e18ce346 9711 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9712
9713 if (netif_running(dev)) {
9714 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9715 err = tg3_restart_hw(tp, 1);
9716 if (!err)
9717 tg3_netif_start(tp);
9718 }
9719
9720 tg3_full_unlock(tp);
9721 }
6aa20a22 9722
b9ec6c1b 9723 return err;
1da177e4 9724}
6aa20a22 9725
1da177e4
LT		 9726static u32 tg3_get_rx_csum(struct net_device *dev)
9727{
9728 struct tg3 *tp = netdev_priv(dev);
9729 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9730}
6aa20a22 9731
1da177e4
LT		 9732static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9733{
9734 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9735
1da177e4
LT		 9736 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9737 if (data != 0)
9738 return -EINVAL;
9739 return 0;
9740 }
6aa20a22 9741
f47c11ee 9742 spin_lock_bh(&tp->lock);
1da177e4
LT		 9743 if (data)
9744 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9745 else
9746 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9747 spin_unlock_bh(&tp->lock);
6aa20a22 9748
1da177e4
LT		 9749 return 0;
9750}
6aa20a22 9751
1da177e4
LT		 9752static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9753{
9754 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9755
1da177e4
LT		 9756 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9757 if (data != 0)
9758 return -EINVAL;
9759 return 0;
9760 }
6aa20a22 9761
321d32a0 9762 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9763 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9764 else
9c27dbdf 9765 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9766
9767 return 0;
9768}
9769
b9f2c044 9770static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9771{
b9f2c044
JG		 9772 switch (sset) {
9773 case ETH_SS_TEST:
9774 return TG3_NUM_TEST;
9775 case ETH_SS_STATS:
9776 return TG3_NUM_STATS;
9777 default:
9778 return -EOPNOTSUPP;
9779 }
4cafd3f5
MC		 9780}
9781
1da177e4
LT		 9782static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9783{
9784 switch (stringset) {
9785 case ETH_SS_STATS:
9786 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9787 break;
4cafd3f5
MC		 9788 case ETH_SS_TEST:
9789 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9790 break;
1da177e4
LT		 9791 default:
9792 WARN_ON(1); /* we need a WARN() */
9793 break;
9794 }
9795}
9796
4009a93d
MC		 9797static int tg3_phys_id(struct net_device *dev, u32 data)
9798{
9799 struct tg3 *tp = netdev_priv(dev);
9800 int i;
9801
9802 if (!netif_running(tp->dev))
9803 return -EAGAIN;
9804
9805 if (data == 0)
759afc31 9806 data = UINT_MAX / 2;
4009a93d
MC		 9807
9808 for (i = 0; i < (data * 2); i++) {
9809 if ((i % 2) == 0)
9810 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9811 LED_CTRL_1000MBPS_ON |
9812 LED_CTRL_100MBPS_ON |
9813 LED_CTRL_10MBPS_ON |
9814 LED_CTRL_TRAFFIC_OVERRIDE |
9815 LED_CTRL_TRAFFIC_BLINK |
9816 LED_CTRL_TRAFFIC_LED);
6aa20a22 9817
4009a93d
MC		 9818 else
9819 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9820 LED_CTRL_TRAFFIC_OVERRIDE);
9821
9822 if (msleep_interruptible(500))
9823 break;
9824 }
9825 tw32(MAC_LED_CTRL, tp->led_ctrl);
9826 return 0;
9827}
9828
1da177e4
LT		 9829static void tg3_get_ethtool_stats (struct net_device *dev,
9830 struct ethtool_stats *estats, u64 *tmp_stats)
9831{
9832 struct tg3 *tp = netdev_priv(dev);
9833 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9834}
9835
566f86ad 9836#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9837#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9838#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9839#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9840#define NVRAM_SELFBOOT_HW_SIZE 0x20
9841#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9842
9843static int tg3_test_nvram(struct tg3 *tp)
9844{
b9fc7dc5 9845 u32 csum, magic;
a9dc529d 9846 __be32 *buf;
ab0049b4 9847 int i, j, k, err = 0, size;
566f86ad 9848
df259d8c
MC		 9849 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9850 return 0;
9851
e4f34110 9852 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9853 return -EIO;
9854
1b27777a
MC		 9855 if (magic == TG3_EEPROM_MAGIC)
9856 size = NVRAM_TEST_SIZE;
b16250e3 9857 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9858 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9859 TG3_EEPROM_SB_FORMAT_1) {
9860 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9861 case TG3_EEPROM_SB_REVISION_0:
9862 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9863 break;
9864 case TG3_EEPROM_SB_REVISION_2:
9865 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9866 break;
9867 case TG3_EEPROM_SB_REVISION_3:
9868 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9869 break;
9870 default:
9871 return 0;
9872 }
9873 } else
1b27777a 9874 return 0;
b16250e3
MC		 9875 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9876 size = NVRAM_SELFBOOT_HW_SIZE;
9877 else
1b27777a
MC		 9878 return -EIO;
9879
9880 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9881 if (buf == NULL)
9882 return -ENOMEM;
9883
1b27777a
MC		 9884 err = -EIO;
9885 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9886 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9887 if (err)
566f86ad 9888 break;
566f86ad 9889 }
1b27777a 9890 if (i < size)
566f86ad
MC		 9891 goto out;
9892
1b27777a 9893 /* Selfboot format */
a9dc529d 9894 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9895 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9896 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9897 u8 *buf8 = (u8 *) buf, csum8 = 0;
9898
b9fc7dc5 9899 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9900 TG3_EEPROM_SB_REVISION_2) {
9901 /* For rev 2, the csum doesn't include the MBA. */
9902 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9903 csum8 += buf8[i];
9904 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9905 csum8 += buf8[i];
9906 } else {
9907 for (i = 0; i < size; i++)
9908 csum8 += buf8[i];
9909 }
1b27777a 9910
ad96b485
AB		 9911 if (csum8 == 0) {
9912 err = 0;
9913 goto out;
9914 }
9915
9916 err = -EIO;
9917 goto out;
1b27777a 9918 }
566f86ad 9919
b9fc7dc5 9920 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9921 TG3_EEPROM_MAGIC_HW) {
9922 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9923 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9924 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9925
9926 /* Separate the parity bits and the data bytes. */
9927 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9928 if ((i == 0) || (i == 8)) {
9929 int l;
9930 u8 msk;
9931
9932 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9933 parity[k++] = buf8[i] & msk;
9934 i++;
9935 }
9936 else if (i == 16) {
9937 int l;
9938 u8 msk;
9939
9940 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9941 parity[k++] = buf8[i] & msk;
9942 i++;
9943
9944 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9945 parity[k++] = buf8[i] & msk;
9946 i++;
9947 }
9948 data[j++] = buf8[i];
9949 }
9950
9951 err = -EIO;
9952 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9953 u8 hw8 = hweight8(data[i]);
9954
9955 if ((hw8 & 0x1) && parity[i])
9956 goto out;
9957 else if (!(hw8 & 0x1) && !parity[i])
9958 goto out;
9959 }
9960 err = 0;
9961 goto out;
9962 }
9963
566f86ad
MC		 9964 /* Bootstrap checksum at offset 0x10 */
9965 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9966 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9967 goto out;
9968
9969 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9970 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9971 if (csum != be32_to_cpu(buf[0xfc/4]))
9972 goto out;
566f86ad
MC		 9973
9974 err = 0;
9975
9976out:
9977 kfree(buf);
9978 return err;
9979}
9980
ca43007a
MC		 9981#define TG3_SERDES_TIMEOUT_SEC 2
9982#define TG3_COPPER_TIMEOUT_SEC 6
9983
9984static int tg3_test_link(struct tg3 *tp)
9985{
9986 int i, max;
9987
9988 if (!netif_running(tp->dev))
9989 return -ENODEV;
9990
4c987487 9991 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9992 max = TG3_SERDES_TIMEOUT_SEC;
9993 else
9994 max = TG3_COPPER_TIMEOUT_SEC;
9995
9996 for (i = 0; i < max; i++) {
9997 if (netif_carrier_ok(tp->dev))
9998 return 0;
9999
10000 if (msleep_interruptible(1000))
10001 break;
10002 }
10003
10004 return -EIO;
10005}
10006
a71116d1 10007/* Only test the commonly used registers */
30ca3e37 10008static int tg3_test_registers(struct tg3 *tp)
a71116d1 10009{
b16250e3 10010 int i, is_5705, is_5750;
a71116d1
MC		 10011 u32 offset, read_mask, write_mask, val, save_val, read_val;
10012 static struct {
10013 u16 offset;
10014 u16 flags;
10015#define TG3_FL_5705 0x1
10016#define TG3_FL_NOT_5705 0x2
10017#define TG3_FL_NOT_5788 0x4
b16250e3 10018#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10019 u32 read_mask;
10020 u32 write_mask;
10021 } reg_tbl[] = {
10022 /* MAC Control Registers */
10023 { MAC_MODE, TG3_FL_NOT_5705,
10024 0x00000000, 0x00ef6f8c },
10025 { MAC_MODE, TG3_FL_5705,
10026 0x00000000, 0x01ef6b8c },
10027 { MAC_STATUS, TG3_FL_NOT_5705,
10028 0x03800107, 0x00000000 },
10029 { MAC_STATUS, TG3_FL_5705,
10030 0x03800100, 0x00000000 },
10031 { MAC_ADDR_0_HIGH, 0x0000,
10032 0x00000000, 0x0000ffff },
10033 { MAC_ADDR_0_LOW, 0x0000,
10034 0x00000000, 0xffffffff },
10035 { MAC_RX_MTU_SIZE, 0x0000,
10036 0x00000000, 0x0000ffff },
10037 { MAC_TX_MODE, 0x0000,
10038 0x00000000, 0x00000070 },
10039 { MAC_TX_LENGTHS, 0x0000,
10040 0x00000000, 0x00003fff },
10041 { MAC_RX_MODE, TG3_FL_NOT_5705,
10042 0x00000000, 0x000007fc },
10043 { MAC_RX_MODE, TG3_FL_5705,
10044 0x00000000, 0x000007dc },
10045 { MAC_HASH_REG_0, 0x0000,
10046 0x00000000, 0xffffffff },
10047 { MAC_HASH_REG_1, 0x0000,
10048 0x00000000, 0xffffffff },
10049 { MAC_HASH_REG_2, 0x0000,
10050 0x00000000, 0xffffffff },
10051 { MAC_HASH_REG_3, 0x0000,
10052 0x00000000, 0xffffffff },
10053
10054 /* Receive Data and Receive BD Initiator Control Registers. */
10055 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10056 0x00000000, 0xffffffff },
10057 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10058 0x00000000, 0xffffffff },
10059 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10060 0x00000000, 0x00000003 },
10061 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10062 0x00000000, 0xffffffff },
10063 { RCVDBDI_STD_BD+0, 0x0000,
10064 0x00000000, 0xffffffff },
10065 { RCVDBDI_STD_BD+4, 0x0000,
10066 0x00000000, 0xffffffff },
10067 { RCVDBDI_STD_BD+8, 0x0000,
10068 0x00000000, 0xffff0002 },
10069 { RCVDBDI_STD_BD+0xc, 0x0000,
10070 0x00000000, 0xffffffff },
6aa20a22 10071
a71116d1
MC		 10072 /* Receive BD Initiator Control Registers. */
10073 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10074 0x00000000, 0xffffffff },
10075 { RCVBDI_STD_THRESH, TG3_FL_5705,
10076 0x00000000, 0x000003ff },
10077 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10078 0x00000000, 0xffffffff },
6aa20a22 10079
a71116d1
MC		 10080 /* Host Coalescing Control Registers. */
10081 { HOSTCC_MODE, TG3_FL_NOT_5705,
10082 0x00000000, 0x00000004 },
10083 { HOSTCC_MODE, TG3_FL_5705,
10084 0x00000000, 0x000000f6 },
10085 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10086 0x00000000, 0xffffffff },
10087 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10088 0x00000000, 0x000003ff },
10089 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10090 0x00000000, 0xffffffff },
10091 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10092 0x00000000, 0x000003ff },
10093 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10094 0x00000000, 0xffffffff },
10095 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10096 0x00000000, 0x000000ff },
10097 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10098 0x00000000, 0xffffffff },
10099 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10100 0x00000000, 0x000000ff },
10101 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10102 0x00000000, 0xffffffff },
10103 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10104 0x00000000, 0xffffffff },
10105 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10106 0x00000000, 0xffffffff },
10107 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10108 0x00000000, 0x000000ff },
10109 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10110 0x00000000, 0xffffffff },
10111 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10112 0x00000000, 0x000000ff },
10113 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10114 0x00000000, 0xffffffff },
10115 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10116 0x00000000, 0xffffffff },
10117 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10118 0x00000000, 0xffffffff },
10119 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10120 0x00000000, 0xffffffff },
10121 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10122 0x00000000, 0xffffffff },
10123 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10124 0xffffffff, 0x00000000 },
10125 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10126 0xffffffff, 0x00000000 },
10127
10128 /* Buffer Manager Control Registers. */
b16250e3 10129 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10130 0x00000000, 0x007fff80 },
b16250e3 10131 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10132 0x00000000, 0x007fffff },
10133 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10134 0x00000000, 0x0000003f },
10135 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10136 0x00000000, 0x000001ff },
10137 { BUFMGR_MB_HIGH_WATER, 0x0000,
10138 0x00000000, 0x000001ff },
10139 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10140 0xffffffff, 0x00000000 },
10141 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10142 0xffffffff, 0x00000000 },
6aa20a22 10143
a71116d1
MC		 10144 /* Mailbox Registers */
10145 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10146 0x00000000, 0x000001ff },
10147 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10148 0x00000000, 0x000001ff },
10149 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10150 0x00000000, 0x000007ff },
10151 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10152 0x00000000, 0x000001ff },
10153
10154 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10155 };
10156
b16250e3
MC		 10157 is_5705 = is_5750 = 0;
10158 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10159 is_5705 = 1;
b16250e3
MC		 10160 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10161 is_5750 = 1;
10162 }
a71116d1
MC		 10163
10164 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10165 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10166 continue;
10167
10168 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10169 continue;
10170
10171 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10172 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10173 continue;
10174
b16250e3
MC		 10175 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10176 continue;
10177
a71116d1
MC		 10178 offset = (u32) reg_tbl[i].offset;
10179 read_mask = reg_tbl[i].read_mask;
10180 write_mask = reg_tbl[i].write_mask;
10181
10182 /* Save the original register content */
10183 save_val = tr32(offset);
10184
10185 /* Determine the read-only value. */
10186 read_val = save_val & read_mask;
10187
10188 /* Write zero to the register, then make sure the read-only bits
10189 * are not changed and the read/write bits are all zeros.
10190 */
10191 tw32(offset, 0);
10192
10193 val = tr32(offset);
10194
10195 /* Test the read-only and read/write bits. */
10196 if (((val & read_mask) != read_val) || (val & write_mask))
10197 goto out;
10198
10199 /* Write ones to all the bits defined by RdMask and WrMask, then
10200 * make sure the read-only bits are not changed and the
10201 * read/write bits are all ones.
10202 */
10203 tw32(offset, read_mask | write_mask);
10204
10205 val = tr32(offset);
10206
10207 /* Test the read-only bits. */
10208 if ((val & read_mask) != read_val)
10209 goto out;
10210
10211 /* Test the read/write bits. */
10212 if ((val & write_mask) != write_mask)
10213 goto out;
10214
10215 tw32(offset, save_val);
10216 }
10217
10218 return 0;
10219
10220out:
9f88f29f
MC		 10221 if (netif_msg_hw(tp))
10222 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10223 offset);
a71116d1
MC		 10224 tw32(offset, save_val);
10225 return -EIO;
10226}
10227
7942e1db
MC		 10228static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10229{
f71e1309 10230 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10231 int i;
10232 u32 j;
10233
e9edda69 10234 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10235 for (j = 0; j < len; j += 4) {
10236 u32 val;
10237
10238 tg3_write_mem(tp, offset + j, test_pattern[i]);
10239 tg3_read_mem(tp, offset + j, &val);
10240 if (val != test_pattern[i])
10241 return -EIO;
10242 }
10243 }
10244 return 0;
10245}
10246
10247static int tg3_test_memory(struct tg3 *tp)
10248{
10249 static struct mem_entry {
10250 u32 offset;
10251 u32 len;
10252 } mem_tbl_570x[] = {
38690194 10253 { 0x00000000, 0x00b50},
7942e1db
MC		 10254 { 0x00002000, 0x1c000},
10255 { 0xffffffff, 0x00000}
10256 }, mem_tbl_5705[] = {
10257 { 0x00000100, 0x0000c},
10258 { 0x00000200, 0x00008},
7942e1db
MC		 10259 { 0x00004000, 0x00800},
10260 { 0x00006000, 0x01000},
10261 { 0x00008000, 0x02000},
10262 { 0x00010000, 0x0e000},
10263 { 0xffffffff, 0x00000}
79f4d13a
MC		 10264 }, mem_tbl_5755[] = {
10265 { 0x00000200, 0x00008},
10266 { 0x00004000, 0x00800},
10267 { 0x00006000, 0x00800},
10268 { 0x00008000, 0x02000},
10269 { 0x00010000, 0x0c000},
10270 { 0xffffffff, 0x00000}
b16250e3
MC		 10271 }, mem_tbl_5906[] = {
10272 { 0x00000200, 0x00008},
10273 { 0x00004000, 0x00400},
10274 { 0x00006000, 0x00400},
10275 { 0x00008000, 0x01000},
10276 { 0x00010000, 0x01000},
10277 { 0xffffffff, 0x00000}
7942e1db
MC		 10278 };
10279 struct mem_entry *mem_tbl;
10280 int err = 0;
10281 int i;
10282
321d32a0
MC		 10283 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10284 mem_tbl = mem_tbl_5755;
10285 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10286 mem_tbl = mem_tbl_5906;
10287 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10288 mem_tbl = mem_tbl_5705;
10289 else
7942e1db
MC		 10290 mem_tbl = mem_tbl_570x;
10291
10292 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10293 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10294 mem_tbl[i].len)) != 0)
10295 break;
10296 }
6aa20a22 10297
7942e1db
MC		 10298 return err;
10299}
10300
9f40dead
MC		 10301#define TG3_MAC_LOOPBACK 0
10302#define TG3_PHY_LOOPBACK 1
10303
10304static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10305{
9f40dead 10306 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10307 u32 desc_idx, coal_now;
c76949a6
MC		 10308 struct sk_buff *skb, *rx_skb;
10309 u8 *tx_data;
10310 dma_addr_t map;
10311 int num_pkts, tx_len, rx_len, i, err;
10312 struct tg3_rx_buffer_desc *desc;
898a56f8 10313 struct tg3_napi *tnapi, *rnapi;
21f581a5 10314 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10315
0c1d0e2b
MC		 10316 if (tp->irq_cnt > 1) {
10317 tnapi = &tp->napi[1];
10318 rnapi = &tp->napi[1];
10319 } else {
10320 tnapi = &tp->napi[0];
10321 rnapi = &tp->napi[0];
10322 }
fd2ce37f 10323 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10324
9f40dead 10325 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10326 /* HW errata - mac loopback fails in some cases on 5780.
10327 * Normal traffic and PHY loopback are not affected by
10328 * errata.
10329 */
10330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10331 return 0;
10332
9f40dead 10333 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10334 MAC_MODE_PORT_INT_LPBACK;
10335 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10336 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10337 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10338 mac_mode |= MAC_MODE_PORT_MODE_MII;
10339 else
10340 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10341 tw32(MAC_MODE, mac_mode);
10342 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10343 u32 val;
10344
7f97a4bd
MC		 10345 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10346 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10347 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10348 } else
10349 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10350
9ef8ca99
MC		 10351 tg3_phy_toggle_automdix(tp, 0);
10352
3f7045c1 10353 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10354 udelay(40);
5d64ad34 10355
e8f3f6ca 10356 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10357 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10359 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10360 mac_mode |= MAC_MODE_PORT_MODE_MII;
10361 } else
10362 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10363
c94e3941
MC		 10364 /* reset to prevent losing 1st rx packet intermittently */
10365 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10366 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10367 udelay(10);
10368 tw32_f(MAC_RX_MODE, tp->rx_mode);
10369 }
e8f3f6ca
MC		 10370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10371 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10372 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10373 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10374 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10375 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10376 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10377 }
9f40dead 10378 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10379 }
10380 else
10381 return -EINVAL;
c76949a6
MC		 10382
10383 err = -EIO;
10384
c76949a6 10385 tx_len = 1514;
a20e9c62 10386 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10387 if (!skb)
10388 return -ENOMEM;
10389
c76949a6
MC		 10390 tx_data = skb_put(skb, tx_len);
10391 memcpy(tx_data, tp->dev->dev_addr, 6);
10392 memset(tx_data + 6, 0x0, 8);
10393
10394 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10395
10396 for (i = 14; i < tx_len; i++)
10397 tx_data[i] = (u8) (i & 0xff);
10398
a21771dd
MC		 10399 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10400 dev_kfree_skb(skb);
10401 return -EIO;
10402 }
c76949a6
MC		 10403
10404 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10405 rnapi->coal_now);
c76949a6
MC		 10406
10407 udelay(10);
10408
898a56f8 10409 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10410
c76949a6
MC		 10411 num_pkts = 0;
10412
a21771dd
MC		 10413 tg3_set_txd(tnapi, tnapi->tx_prod,
10414 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10415
f3f3f27e 10416 tnapi->tx_prod++;
c76949a6
MC		 10417 num_pkts++;
10418
f3f3f27e
MC		 10419 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10420 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10421
10422 udelay(10);
10423
3f7045c1
MC		 10424 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10425 for (i = 0; i < 25; i++) {
c76949a6 10426 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10427 coal_now);
c76949a6
MC		 10428
10429 udelay(10);
10430
898a56f8
MC		 10431 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10432 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10433 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10434 (rx_idx == (rx_start_idx + num_pkts)))
10435 break;
10436 }
10437
a21771dd 10438 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10439 dev_kfree_skb(skb);
10440
f3f3f27e 10441 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10442 goto out;
10443
10444 if (rx_idx != rx_start_idx + num_pkts)
10445 goto out;
10446
72334482 10447 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10448 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10449 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10450 if (opaque_key != RXD_OPAQUE_RING_STD)
10451 goto out;
10452
10453 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10454 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10455 goto out;
10456
10457 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10458 if (rx_len != tx_len)
10459 goto out;
10460
21f581a5 10461 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10462
21f581a5 10463 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10464 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10465
10466 for (i = 14; i < tx_len; i++) {
10467 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10468 goto out;
10469 }
10470 err = 0;
6aa20a22 10471
c76949a6
MC		 10472 /* tg3_free_rings will unmap and free the rx_skb */
10473out:
10474 return err;
10475}
10476
9f40dead
MC		 10477#define TG3_MAC_LOOPBACK_FAILED 1
10478#define TG3_PHY_LOOPBACK_FAILED 2
10479#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10480 TG3_PHY_LOOPBACK_FAILED)
10481
10482static int tg3_test_loopback(struct tg3 *tp)
10483{
10484 int err = 0;
9936bcf6 10485 u32 cpmuctrl = 0;
9f40dead
MC		 10486
10487 if (!netif_running(tp->dev))
10488 return TG3_LOOPBACK_FAILED;
10489
b9ec6c1b
MC		 10490 err = tg3_reset_hw(tp, 1);
10491 if (err)
10492 return TG3_LOOPBACK_FAILED;
9f40dead 10493
6833c043
MC		 10494 /* Turn off gphy autopowerdown. */
10495 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10496 tg3_phy_toggle_apd(tp, false);
10497
321d32a0 10498 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10499 int i;
10500 u32 status;
10501
10502 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10503
10504 /* Wait for up to 40 microseconds to acquire lock. */
10505 for (i = 0; i < 4; i++) {
10506 status = tr32(TG3_CPMU_MUTEX_GNT);
10507 if (status == CPMU_MUTEX_GNT_DRIVER)
10508 break;
10509 udelay(10);
10510 }
10511
10512 if (status != CPMU_MUTEX_GNT_DRIVER)
10513 return TG3_LOOPBACK_FAILED;
10514
b2a5c19c 10515 /* Turn off link-based power management. */
e875093c 10516 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10517 tw32(TG3_CPMU_CTRL,
10518 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10519 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10520 }
10521
9f40dead
MC		 10522 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10523 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10524
321d32a0 10525 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10526 tw32(TG3_CPMU_CTRL, cpmuctrl);
10527
10528 /* Release the mutex */
10529 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10530 }
10531
dd477003
MC		 10532 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10533 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10534 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10535 err |= TG3_PHY_LOOPBACK_FAILED;
10536 }
10537
6833c043
MC		 10538 /* Re-enable gphy autopowerdown. */
10539 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10540 tg3_phy_toggle_apd(tp, true);
10541
9f40dead
MC		 10542 return err;
10543}
10544
4cafd3f5
MC		 10545static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10546 u64 *data)
10547{
566f86ad
MC		 10548 struct tg3 *tp = netdev_priv(dev);
10549
bc1c7567
MC		 10550 if (tp->link_config.phy_is_low_power)
10551 tg3_set_power_state(tp, PCI_D0);
10552
566f86ad
MC		 10553 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10554
10555 if (tg3_test_nvram(tp) != 0) {
10556 etest->flags |= ETH_TEST_FL_FAILED;
10557 data[0] = 1;
10558 }
ca43007a
MC		 10559 if (tg3_test_link(tp) != 0) {
10560 etest->flags |= ETH_TEST_FL_FAILED;
10561 data[1] = 1;
10562 }
a71116d1 10563 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10564 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10565
10566 if (netif_running(dev)) {
b02fd9e3 10567 tg3_phy_stop(tp);
a71116d1 10568 tg3_netif_stop(tp);
bbe832c0
MC		 10569 irq_sync = 1;
10570 }
a71116d1 10571
bbe832c0 10572 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10573
10574 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10575 err = tg3_nvram_lock(tp);
a71116d1
MC		 10576 tg3_halt_cpu(tp, RX_CPU_BASE);
10577 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10578 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10579 if (!err)
10580 tg3_nvram_unlock(tp);
a71116d1 10581
d9ab5ad1
MC		 10582 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10583 tg3_phy_reset(tp);
10584
a71116d1
MC		 10585 if (tg3_test_registers(tp) != 0) {
10586 etest->flags |= ETH_TEST_FL_FAILED;
10587 data[2] = 1;
10588 }
7942e1db
MC		 10589 if (tg3_test_memory(tp) != 0) {
10590 etest->flags |= ETH_TEST_FL_FAILED;
10591 data[3] = 1;
10592 }
9f40dead 10593 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10594 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10595
f47c11ee
DM		 10596 tg3_full_unlock(tp);
10597
d4bc3927
MC		 10598 if (tg3_test_interrupt(tp) != 0) {
10599 etest->flags |= ETH_TEST_FL_FAILED;
10600 data[5] = 1;
10601 }
f47c11ee
DM		 10602
10603 tg3_full_lock(tp, 0);
d4bc3927 10604
a71116d1
MC		 10605 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10606 if (netif_running(dev)) {
10607 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10608 err2 = tg3_restart_hw(tp, 1);
10609 if (!err2)
b9ec6c1b 10610 tg3_netif_start(tp);
a71116d1 10611 }
f47c11ee
DM		 10612
10613 tg3_full_unlock(tp);
b02fd9e3
MC		 10614
10615 if (irq_sync && !err2)
10616 tg3_phy_start(tp);
a71116d1 10617 }
bc1c7567
MC		 10618 if (tp->link_config.phy_is_low_power)
10619 tg3_set_power_state(tp, PCI_D3hot);
10620
4cafd3f5
MC		 10621}
10622
1da177e4
LT		 10623static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10624{
10625 struct mii_ioctl_data *data = if_mii(ifr);
10626 struct tg3 *tp = netdev_priv(dev);
10627 int err;
10628
b02fd9e3 10629 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10630 struct phy_device *phydev;
b02fd9e3
MC		 10631 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10632 return -EAGAIN;
3f0e3ad7
MC		 10633 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10634 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10635 }
10636
1da177e4
LT		 10637 switch(cmd) {
10638 case SIOCGMIIPHY:
882e9793 10639 data->phy_id = tp->phy_addr;
1da177e4
LT		 10640
10641 /* fallthru */
10642 case SIOCGMIIREG: {
10643 u32 mii_regval;
10644
10645 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10646 break; /* We have no PHY */
10647
bc1c7567
MC		 10648 if (tp->link_config.phy_is_low_power)
10649 return -EAGAIN;
10650
f47c11ee 10651 spin_lock_bh(&tp->lock);
1da177e4 10652 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10653 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10654
10655 data->val_out = mii_regval;
10656
10657 return err;
10658 }
10659
10660 case SIOCSMIIREG:
10661 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10662 break; /* We have no PHY */
10663
bc1c7567
MC		 10664 if (tp->link_config.phy_is_low_power)
10665 return -EAGAIN;
10666
f47c11ee 10667 spin_lock_bh(&tp->lock);
1da177e4 10668 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10669 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10670
10671 return err;
10672
10673 default:
10674 /* do nothing */
10675 break;
10676 }
10677 return -EOPNOTSUPP;
10678}
10679
10680#if TG3_VLAN_TAG_USED
10681static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10682{
10683 struct tg3 *tp = netdev_priv(dev);
10684
844b3eed
MC		 10685 if (!netif_running(dev)) {
10686 tp->vlgrp = grp;
10687 return;
10688 }
10689
10690 tg3_netif_stop(tp);
29315e87 10691
f47c11ee 10692 tg3_full_lock(tp, 0);
1da177e4
LT		 10693
10694 tp->vlgrp = grp;
10695
10696 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10697 __tg3_set_rx_mode(dev);
10698
844b3eed 10699 tg3_netif_start(tp);
46966545
MC		 10700
10701 tg3_full_unlock(tp);
1da177e4 10702}
1da177e4
LT		 10703#endif
10704
15f9850d
DM		 10705static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10706{
10707 struct tg3 *tp = netdev_priv(dev);
10708
10709 memcpy(ec, &tp->coal, sizeof(*ec));
10710 return 0;
10711}
10712
d244c892
MC		 10713static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10714{
10715 struct tg3 *tp = netdev_priv(dev);
10716 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10717 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10718
10719 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10720 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10721 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10722 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10723 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10724 }
10725
10726 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10727 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10728 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10729 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10730 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10731 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10732 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10733 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10734 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10735 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10736 return -EINVAL;
10737
10738 /* No rx interrupts will be generated if both are zero */
10739 if ((ec->rx_coalesce_usecs == 0) &&
10740 (ec->rx_max_coalesced_frames == 0))
10741 return -EINVAL;
10742
10743 /* No tx interrupts will be generated if both are zero */
10744 if ((ec->tx_coalesce_usecs == 0) &&
10745 (ec->tx_max_coalesced_frames == 0))
10746 return -EINVAL;
10747
10748 /* Only copy relevant parameters, ignore all others. */
10749 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10750 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10751 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10752 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10753 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10754 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10755 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10756 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10757 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10758
10759 if (netif_running(dev)) {
10760 tg3_full_lock(tp, 0);
10761 __tg3_set_coalesce(tp, &tp->coal);
10762 tg3_full_unlock(tp);
10763 }
10764 return 0;
10765}
10766
7282d491 10767static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10768 .get_settings = tg3_get_settings,
10769 .set_settings = tg3_set_settings,
10770 .get_drvinfo = tg3_get_drvinfo,
10771 .get_regs_len = tg3_get_regs_len,
10772 .get_regs = tg3_get_regs,
10773 .get_wol = tg3_get_wol,
10774 .set_wol = tg3_set_wol,
10775 .get_msglevel = tg3_get_msglevel,
10776 .set_msglevel = tg3_set_msglevel,
10777 .nway_reset = tg3_nway_reset,
10778 .get_link = ethtool_op_get_link,
10779 .get_eeprom_len = tg3_get_eeprom_len,
10780 .get_eeprom = tg3_get_eeprom,
10781 .set_eeprom = tg3_set_eeprom,
10782 .get_ringparam = tg3_get_ringparam,
10783 .set_ringparam = tg3_set_ringparam,
10784 .get_pauseparam = tg3_get_pauseparam,
10785 .set_pauseparam = tg3_set_pauseparam,
10786 .get_rx_csum = tg3_get_rx_csum,
10787 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10788 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10789 .set_sg = ethtool_op_set_sg,
1da177e4 10790 .set_tso = tg3_set_tso,
4cafd3f5 10791 .self_test = tg3_self_test,
1da177e4 10792 .get_strings = tg3_get_strings,
4009a93d 10793 .phys_id = tg3_phys_id,
1da177e4 10794 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10795 .get_coalesce = tg3_get_coalesce,
d244c892 10796 .set_coalesce = tg3_set_coalesce,
b9f2c044 10797 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10798};
10799
10800static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10801{
1b27777a 10802 u32 cursize, val, magic;
1da177e4
LT		 10803
10804 tp->nvram_size = EEPROM_CHIP_SIZE;
10805
e4f34110 10806 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10807 return;
10808
b16250e3
MC		 10809 if ((magic != TG3_EEPROM_MAGIC) &&
10810 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10811 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10812 return;
10813
10814 /*
10815 * Size the chip by reading offsets at increasing powers of two.
10816 * When we encounter our validation signature, we know the addressing
10817 * has wrapped around, and thus have our chip size.
10818 */
1b27777a 10819 cursize = 0x10;
1da177e4
LT		 10820
10821 while (cursize < tp->nvram_size) {
e4f34110 10822 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10823 return;
10824
1820180b 10825 if (val == magic)
1da177e4
LT		 10826 break;
10827
10828 cursize <<= 1;
10829 }
10830
10831 tp->nvram_size = cursize;
10832}
6aa20a22 10833
1da177e4
LT		 10834static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10835{
10836 u32 val;
10837
df259d8c
MC		 10838 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10839 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10840 return;
10841
10842 /* Selfboot format */
1820180b 10843 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10844 tg3_get_eeprom_size(tp);
10845 return;
10846 }
10847
6d348f2c 10848 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10849 if (val != 0) {
6d348f2c
MC		 10850 /* This is confusing. We want to operate on the
10851 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10852 * call will read from NVRAM and byteswap the data
10853 * according to the byteswapping settings for all
10854 * other register accesses. This ensures the data we
10855 * want will always reside in the lower 16-bits.
10856 * However, the data in NVRAM is in LE format, which
10857 * means the data from the NVRAM read will always be
10858 * opposite the endianness of the CPU. The 16-bit
10859 * byteswap then brings the data to CPU endianness.
10860 */
10861 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10862 return;
10863 }
10864 }
fd1122a2 10865 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10866}
10867
10868static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10869{
10870 u32 nvcfg1;
10871
10872 nvcfg1 = tr32(NVRAM_CFG1);
10873 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10874 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10875 } else {
1da177e4
LT		 10876 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10877 tw32(NVRAM_CFG1, nvcfg1);
10878 }
10879
4c987487 10880 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10881 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10882 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10883 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10884 tp->nvram_jedecnum = JEDEC_ATMEL;
10885 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10886 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10887 break;
10888 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10889 tp->nvram_jedecnum = JEDEC_ATMEL;
10890 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10891 break;
10892 case FLASH_VENDOR_ATMEL_EEPROM:
10893 tp->nvram_jedecnum = JEDEC_ATMEL;
10894 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10895 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10896 break;
10897 case FLASH_VENDOR_ST:
10898 tp->nvram_jedecnum = JEDEC_ST;
10899 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10900 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10901 break;
10902 case FLASH_VENDOR_SAIFUN:
10903 tp->nvram_jedecnum = JEDEC_SAIFUN;
10904 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10905 break;
10906 case FLASH_VENDOR_SST_SMALL:
10907 case FLASH_VENDOR_SST_LARGE:
10908 tp->nvram_jedecnum = JEDEC_SST;
10909 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10910 break;
1da177e4 10911 }
8590a603 10912 } else {
1da177e4
LT		 10913 tp->nvram_jedecnum = JEDEC_ATMEL;
10914 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10915 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10916 }
10917}
10918
a1b950d5
MC		 10919static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10920{
10921 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10922 case FLASH_5752PAGE_SIZE_256:
10923 tp->nvram_pagesize = 256;
10924 break;
10925 case FLASH_5752PAGE_SIZE_512:
10926 tp->nvram_pagesize = 512;
10927 break;
10928 case FLASH_5752PAGE_SIZE_1K:
10929 tp->nvram_pagesize = 1024;
10930 break;
10931 case FLASH_5752PAGE_SIZE_2K:
10932 tp->nvram_pagesize = 2048;
10933 break;
10934 case FLASH_5752PAGE_SIZE_4K:
10935 tp->nvram_pagesize = 4096;
10936 break;
10937 case FLASH_5752PAGE_SIZE_264:
10938 tp->nvram_pagesize = 264;
10939 break;
10940 case FLASH_5752PAGE_SIZE_528:
10941 tp->nvram_pagesize = 528;
10942 break;
10943 }
10944}
10945
361b4ac2
MC		 10946static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10947{
10948 u32 nvcfg1;
10949
10950 nvcfg1 = tr32(NVRAM_CFG1);
10951
e6af301b
MC		 10952 /* NVRAM protection for TPM */
10953 if (nvcfg1 & (1 << 27))
10954 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10955
361b4ac2 10956 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10957 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10958 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10959 tp->nvram_jedecnum = JEDEC_ATMEL;
10960 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10961 break;
10962 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10963 tp->nvram_jedecnum = JEDEC_ATMEL;
10964 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10965 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10966 break;
10967 case FLASH_5752VENDOR_ST_M45PE10:
10968 case FLASH_5752VENDOR_ST_M45PE20:
10969 case FLASH_5752VENDOR_ST_M45PE40:
10970 tp->nvram_jedecnum = JEDEC_ST;
10971 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10972 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10973 break;
361b4ac2
MC		 10974 }
10975
10976 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 10977 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 10978 } else {
361b4ac2
MC		 10979 /* For eeprom, set pagesize to maximum eeprom size */
10980 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10981
10982 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10983 tw32(NVRAM_CFG1, nvcfg1);
10984 }
10985}
10986
d3c7b886
MC		 10987static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10988{
989a9d23 10989 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10990
10991 nvcfg1 = tr32(NVRAM_CFG1);
10992
10993 /* NVRAM protection for TPM */
989a9d23 10994 if (nvcfg1 & (1 << 27)) {
d3c7b886 10995 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10996 protect = 1;
10997 }
d3c7b886 10998
989a9d23
MC		 10999 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11000 switch (nvcfg1) {
8590a603
MC		 11001 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11002 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11003 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11004 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11005 tp->nvram_jedecnum = JEDEC_ATMEL;
11006 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11007 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11008 tp->nvram_pagesize = 264;
11009 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11010 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11011 tp->nvram_size = (protect ? 0x3e200 :
11012 TG3_NVRAM_SIZE_512KB);
11013 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11014 tp->nvram_size = (protect ? 0x1f200 :
11015 TG3_NVRAM_SIZE_256KB);
11016 else
11017 tp->nvram_size = (protect ? 0x1f200 :
11018 TG3_NVRAM_SIZE_128KB);
11019 break;
11020 case FLASH_5752VENDOR_ST_M45PE10:
11021 case FLASH_5752VENDOR_ST_M45PE20:
11022 case FLASH_5752VENDOR_ST_M45PE40:
11023 tp->nvram_jedecnum = JEDEC_ST;
11024 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11025 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11026 tp->nvram_pagesize = 256;
11027 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11028 tp->nvram_size = (protect ?
11029 TG3_NVRAM_SIZE_64KB :
11030 TG3_NVRAM_SIZE_128KB);
11031 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11032 tp->nvram_size = (protect ?
11033 TG3_NVRAM_SIZE_64KB :
11034 TG3_NVRAM_SIZE_256KB);
11035 else
11036 tp->nvram_size = (protect ?
11037 TG3_NVRAM_SIZE_128KB :
11038 TG3_NVRAM_SIZE_512KB);
11039 break;
d3c7b886
MC		 11040 }
11041}
11042
1b27777a
MC		 11043static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11044{
11045 u32 nvcfg1;
11046
11047 nvcfg1 = tr32(NVRAM_CFG1);
11048
11049 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11050 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11051 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11052 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11053 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11054 tp->nvram_jedecnum = JEDEC_ATMEL;
11055 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11056 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11057
8590a603
MC		 11058 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11059 tw32(NVRAM_CFG1, nvcfg1);
11060 break;
11061 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11062 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11063 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11064 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11065 tp->nvram_jedecnum = JEDEC_ATMEL;
11066 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11067 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11068 tp->nvram_pagesize = 264;
11069 break;
11070 case FLASH_5752VENDOR_ST_M45PE10:
11071 case FLASH_5752VENDOR_ST_M45PE20:
11072 case FLASH_5752VENDOR_ST_M45PE40:
11073 tp->nvram_jedecnum = JEDEC_ST;
11074 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11075 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11076 tp->nvram_pagesize = 256;
11077 break;
1b27777a
MC		 11078 }
11079}
11080
6b91fa02
MC		 11081static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11082{
11083 u32 nvcfg1, protect = 0;
11084
11085 nvcfg1 = tr32(NVRAM_CFG1);
11086
11087 /* NVRAM protection for TPM */
11088 if (nvcfg1 & (1 << 27)) {
11089 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11090 protect = 1;
11091 }
11092
11093 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11094 switch (nvcfg1) {
8590a603
MC		 11095 case FLASH_5761VENDOR_ATMEL_ADB021D:
11096 case FLASH_5761VENDOR_ATMEL_ADB041D:
11097 case FLASH_5761VENDOR_ATMEL_ADB081D:
11098 case FLASH_5761VENDOR_ATMEL_ADB161D:
11099 case FLASH_5761VENDOR_ATMEL_MDB021D:
11100 case FLASH_5761VENDOR_ATMEL_MDB041D:
11101 case FLASH_5761VENDOR_ATMEL_MDB081D:
11102 case FLASH_5761VENDOR_ATMEL_MDB161D:
11103 tp->nvram_jedecnum = JEDEC_ATMEL;
11104 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11105 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11106 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11107 tp->nvram_pagesize = 256;
11108 break;
11109 case FLASH_5761VENDOR_ST_A_M45PE20:
11110 case FLASH_5761VENDOR_ST_A_M45PE40:
11111 case FLASH_5761VENDOR_ST_A_M45PE80:
11112 case FLASH_5761VENDOR_ST_A_M45PE16:
11113 case FLASH_5761VENDOR_ST_M_M45PE20:
11114 case FLASH_5761VENDOR_ST_M_M45PE40:
11115 case FLASH_5761VENDOR_ST_M_M45PE80:
11116 case FLASH_5761VENDOR_ST_M_M45PE16:
11117 tp->nvram_jedecnum = JEDEC_ST;
11118 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11119 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11120 tp->nvram_pagesize = 256;
11121 break;
6b91fa02
MC		 11122 }
11123
11124 if (protect) {
11125 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11126 } else {
11127 switch (nvcfg1) {
8590a603
MC		 11128 case FLASH_5761VENDOR_ATMEL_ADB161D:
11129 case FLASH_5761VENDOR_ATMEL_MDB161D:
11130 case FLASH_5761VENDOR_ST_A_M45PE16:
11131 case FLASH_5761VENDOR_ST_M_M45PE16:
11132 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11133 break;
11134 case FLASH_5761VENDOR_ATMEL_ADB081D:
11135 case FLASH_5761VENDOR_ATMEL_MDB081D:
11136 case FLASH_5761VENDOR_ST_A_M45PE80:
11137 case FLASH_5761VENDOR_ST_M_M45PE80:
11138 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11139 break;
11140 case FLASH_5761VENDOR_ATMEL_ADB041D:
11141 case FLASH_5761VENDOR_ATMEL_MDB041D:
11142 case FLASH_5761VENDOR_ST_A_M45PE40:
11143 case FLASH_5761VENDOR_ST_M_M45PE40:
11144 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11145 break;
11146 case FLASH_5761VENDOR_ATMEL_ADB021D:
11147 case FLASH_5761VENDOR_ATMEL_MDB021D:
11148 case FLASH_5761VENDOR_ST_A_M45PE20:
11149 case FLASH_5761VENDOR_ST_M_M45PE20:
11150 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11151 break;
6b91fa02
MC		 11152 }
11153 }
11154}
11155
b5d3772c
MC		 11156static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11157{
11158 tp->nvram_jedecnum = JEDEC_ATMEL;
11159 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11160 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11161}
11162
321d32a0
MC		 11163static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11164{
11165 u32 nvcfg1;
11166
11167 nvcfg1 = tr32(NVRAM_CFG1);
11168
11169 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11170 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11171 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11172 tp->nvram_jedecnum = JEDEC_ATMEL;
11173 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11174 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11175
11176 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11177 tw32(NVRAM_CFG1, nvcfg1);
11178 return;
11179 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11180 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11181 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11182 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11183 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11184 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11185 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11186 tp->nvram_jedecnum = JEDEC_ATMEL;
11187 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11188 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11189
11190 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11191 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11192 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11193 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11194 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11195 break;
11196 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11197 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11198 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11199 break;
11200 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11201 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11202 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11203 break;
11204 }
11205 break;
11206 case FLASH_5752VENDOR_ST_M45PE10:
11207 case FLASH_5752VENDOR_ST_M45PE20:
11208 case FLASH_5752VENDOR_ST_M45PE40:
11209 tp->nvram_jedecnum = JEDEC_ST;
11210 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11211 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11212
11213 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11214 case FLASH_5752VENDOR_ST_M45PE10:
11215 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11216 break;
11217 case FLASH_5752VENDOR_ST_M45PE20:
11218 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11219 break;
11220 case FLASH_5752VENDOR_ST_M45PE40:
11221 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11222 break;
11223 }
11224 break;
11225 default:
df259d8c 11226 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11227 return;
11228 }
11229
a1b950d5
MC		 11230 tg3_nvram_get_pagesize(tp, nvcfg1);
11231 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11232 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11233}
11234
11235
11236static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11237{
11238 u32 nvcfg1;
11239
11240 nvcfg1 = tr32(NVRAM_CFG1);
11241
11242 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11243 case FLASH_5717VENDOR_ATMEL_EEPROM:
11244 case FLASH_5717VENDOR_MICRO_EEPROM:
11245 tp->nvram_jedecnum = JEDEC_ATMEL;
11246 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11247 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11248
11249 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11250 tw32(NVRAM_CFG1, nvcfg1);
11251 return;
11252 case FLASH_5717VENDOR_ATMEL_MDB011D:
11253 case FLASH_5717VENDOR_ATMEL_ADB011B:
11254 case FLASH_5717VENDOR_ATMEL_ADB011D:
11255 case FLASH_5717VENDOR_ATMEL_MDB021D:
11256 case FLASH_5717VENDOR_ATMEL_ADB021B:
11257 case FLASH_5717VENDOR_ATMEL_ADB021D:
11258 case FLASH_5717VENDOR_ATMEL_45USPT:
11259 tp->nvram_jedecnum = JEDEC_ATMEL;
11260 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11262
11263 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11264 case FLASH_5717VENDOR_ATMEL_MDB021D:
11265 case FLASH_5717VENDOR_ATMEL_ADB021B:
11266 case FLASH_5717VENDOR_ATMEL_ADB021D:
11267 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11268 break;
11269 default:
11270 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11271 break;
11272 }
321d32a0 11273 break;
a1b950d5
MC		 11274 case FLASH_5717VENDOR_ST_M_M25PE10:
11275 case FLASH_5717VENDOR_ST_A_M25PE10:
11276 case FLASH_5717VENDOR_ST_M_M45PE10:
11277 case FLASH_5717VENDOR_ST_A_M45PE10:
11278 case FLASH_5717VENDOR_ST_M_M25PE20:
11279 case FLASH_5717VENDOR_ST_A_M25PE20:
11280 case FLASH_5717VENDOR_ST_M_M45PE20:
11281 case FLASH_5717VENDOR_ST_A_M45PE20:
11282 case FLASH_5717VENDOR_ST_25USPT:
11283 case FLASH_5717VENDOR_ST_45USPT:
11284 tp->nvram_jedecnum = JEDEC_ST;
11285 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11286 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11287
11288 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11289 case FLASH_5717VENDOR_ST_M_M25PE20:
11290 case FLASH_5717VENDOR_ST_A_M25PE20:
11291 case FLASH_5717VENDOR_ST_M_M45PE20:
11292 case FLASH_5717VENDOR_ST_A_M45PE20:
11293 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11294 break;
11295 default:
11296 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11297 break;
11298 }
321d32a0 11299 break;
a1b950d5
MC		 11300 default:
11301 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11302 return;
321d32a0 11303 }
a1b950d5
MC		 11304
11305 tg3_nvram_get_pagesize(tp, nvcfg1);
11306 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11307 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11308}
11309
1da177e4
LT		 11310/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11311static void __devinit tg3_nvram_init(struct tg3 *tp)
11312{
1da177e4
LT		 11313 tw32_f(GRC_EEPROM_ADDR,
11314 (EEPROM_ADDR_FSM_RESET |
11315 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11316 EEPROM_ADDR_CLKPERD_SHIFT)));
11317
9d57f01c 11318 msleep(1);
1da177e4
LT		 11319
11320 /* Enable seeprom accesses. */
11321 tw32_f(GRC_LOCAL_CTRL,
11322 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11323 udelay(100);
11324
11325 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11326 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11327 tp->tg3_flags |= TG3_FLAG_NVRAM;
11328
ec41c7df
MC		 11329 if (tg3_nvram_lock(tp)) {
11330 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11331 "tg3_nvram_init failed.\n", tp->dev->name);
11332 return;
11333 }
e6af301b 11334 tg3_enable_nvram_access(tp);
1da177e4 11335
989a9d23
MC		 11336 tp->nvram_size = 0;
11337
361b4ac2
MC		 11338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11339 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11340 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11341 tg3_get_5755_nvram_info(tp);
d30cdd28 11342 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11345 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11346 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11347 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11348 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11349 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11350 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11351 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11352 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11353 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11354 else
11355 tg3_get_nvram_info(tp);
11356
989a9d23
MC		 11357 if (tp->nvram_size == 0)
11358 tg3_get_nvram_size(tp);
1da177e4 11359
e6af301b 11360 tg3_disable_nvram_access(tp);
381291b7 11361 tg3_nvram_unlock(tp);
1da177e4
LT		 11362
11363 } else {
11364 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11365
11366 tg3_get_eeprom_size(tp);
11367 }
11368}
11369
1da177e4
LT		 11370static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11371 u32 offset, u32 len, u8 *buf)
11372{
11373 int i, j, rc = 0;
11374 u32 val;
11375
11376 for (i = 0; i < len; i += 4) {
b9fc7dc5 11377 u32 addr;
a9dc529d 11378 __be32 data;
1da177e4
LT		 11379
11380 addr = offset + i;
11381
11382 memcpy(&data, buf + i, 4);
11383
62cedd11
MC		 11384 /*
11385 * The SEEPROM interface expects the data to always be opposite
11386 * the native endian format. We accomplish this by reversing
11387 * all the operations that would have been performed on the
11388 * data from a call to tg3_nvram_read_be32().
11389 */
11390 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11391
11392 val = tr32(GRC_EEPROM_ADDR);
11393 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11394
11395 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11396 EEPROM_ADDR_READ);
11397 tw32(GRC_EEPROM_ADDR, val |
11398 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11399 (addr & EEPROM_ADDR_ADDR_MASK) |
11400 EEPROM_ADDR_START |
11401 EEPROM_ADDR_WRITE);
6aa20a22 11402
9d57f01c 11403 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11404 val = tr32(GRC_EEPROM_ADDR);
11405
11406 if (val & EEPROM_ADDR_COMPLETE)
11407 break;
9d57f01c 11408 msleep(1);
1da177e4
LT		 11409 }
11410 if (!(val & EEPROM_ADDR_COMPLETE)) {
11411 rc = -EBUSY;
11412 break;
11413 }
11414 }
11415
11416 return rc;
11417}
11418
11419/* offset and length are dword aligned */
11420static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11421 u8 *buf)
11422{
11423 int ret = 0;
11424 u32 pagesize = tp->nvram_pagesize;
11425 u32 pagemask = pagesize - 1;
11426 u32 nvram_cmd;
11427 u8 *tmp;
11428
11429 tmp = kmalloc(pagesize, GFP_KERNEL);
11430 if (tmp == NULL)
11431 return -ENOMEM;
11432
11433 while (len) {
11434 int j;
e6af301b 11435 u32 phy_addr, page_off, size;
1da177e4
LT		 11436
11437 phy_addr = offset & ~pagemask;
6aa20a22 11438
1da177e4 11439 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11440 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11441 (__be32 *) (tmp + j));
11442 if (ret)
1da177e4
LT		 11443 break;
11444 }
11445 if (ret)
11446 break;
11447
11448 page_off = offset & pagemask;
11449 size = pagesize;
11450 if (len < size)
11451 size = len;
11452
11453 len -= size;
11454
11455 memcpy(tmp + page_off, buf, size);
11456
11457 offset = offset + (pagesize - page_off);
11458
e6af301b 11459 tg3_enable_nvram_access(tp);
1da177e4
LT		 11460
11461 /*
11462 * Before we can erase the flash page, we need
11463 * to issue a special "write enable" command.
11464 */
11465 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11466
11467 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11468 break;
11469
11470 /* Erase the target page */
11471 tw32(NVRAM_ADDR, phy_addr);
11472
11473 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11474 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11475
11476 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11477 break;
11478
11479 /* Issue another write enable to start the write. */
11480 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11481
11482 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11483 break;
11484
11485 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11486 __be32 data;
1da177e4 11487
b9fc7dc5 11488 data = *((__be32 *) (tmp + j));
a9dc529d 11489
b9fc7dc5 11490 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11491
11492 tw32(NVRAM_ADDR, phy_addr + j);
11493
11494 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11495 NVRAM_CMD_WR;
11496
11497 if (j == 0)
11498 nvram_cmd |= NVRAM_CMD_FIRST;
11499 else if (j == (pagesize - 4))
11500 nvram_cmd |= NVRAM_CMD_LAST;
11501
11502 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11503 break;
11504 }
11505 if (ret)
11506 break;
11507 }
11508
11509 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11510 tg3_nvram_exec_cmd(tp, nvram_cmd);
11511
11512 kfree(tmp);
11513
11514 return ret;
11515}
11516
11517/* offset and length are dword aligned */
11518static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11519 u8 *buf)
11520{
11521 int i, ret = 0;
11522
11523 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11524 u32 page_off, phy_addr, nvram_cmd;
11525 __be32 data;
1da177e4
LT		 11526
11527 memcpy(&data, buf + i, 4);
b9fc7dc5 11528 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11529
11530 page_off = offset % tp->nvram_pagesize;
11531
1820180b 11532 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11533
11534 tw32(NVRAM_ADDR, phy_addr);
11535
11536 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11537
11538 if ((page_off == 0) || (i == 0))
11539 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11540 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11541 nvram_cmd |= NVRAM_CMD_LAST;
11542
11543 if (i == (len - 4))
11544 nvram_cmd |= NVRAM_CMD_LAST;
11545
321d32a0
MC		 11546 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11547 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11548 (tp->nvram_jedecnum == JEDEC_ST) &&
11549 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11550
11551 if ((ret = tg3_nvram_exec_cmd(tp,
11552 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11553 NVRAM_CMD_DONE)))
11554
11555 break;
11556 }
11557 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11558 /* We always do complete word writes to eeprom. */
11559 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11560 }
11561
11562 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11563 break;
11564 }
11565 return ret;
11566}
11567
11568/* offset and length are dword aligned */
11569static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11570{
11571 int ret;
11572
1da177e4 11573 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11574 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11575 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11576 udelay(40);
11577 }
11578
11579 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11580 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11581 }
11582 else {
11583 u32 grc_mode;
11584
ec41c7df
MC		 11585 ret = tg3_nvram_lock(tp);
11586 if (ret)
11587 return ret;
1da177e4 11588
e6af301b
MC		 11589 tg3_enable_nvram_access(tp);
11590 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11591 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11592 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11593
11594 grc_mode = tr32(GRC_MODE);
11595 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11596
11597 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11598 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11599
11600 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11601 buf);
11602 }
11603 else {
11604 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11605 buf);
11606 }
11607
11608 grc_mode = tr32(GRC_MODE);
11609 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11610
e6af301b 11611 tg3_disable_nvram_access(tp);
1da177e4
LT		 11612 tg3_nvram_unlock(tp);
11613 }
11614
11615 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11616 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11617 udelay(40);
11618 }
11619
11620 return ret;
11621}
11622
11623struct subsys_tbl_ent {
11624 u16 subsys_vendor, subsys_devid;
11625 u32 phy_id;
11626};
11627
11628static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11629 /* Broadcom boards. */
11630 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11631 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11632 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11633 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11634 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11635 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11636 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11637 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11638 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11639 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11640 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11641
11642 /* 3com boards. */
11643 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11644 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11645 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11646 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11647 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11648
11649 /* DELL boards. */
11650 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11651 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11652 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11653 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11654
11655 /* Compaq boards. */
11656 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11657 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11658 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11659 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11660 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11661
11662 /* IBM boards. */
11663 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11664};
11665
11666static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11667{
11668 int i;
11669
11670 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11671 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11672 tp->pdev->subsystem_vendor) &&
11673 (subsys_id_to_phy_id[i].subsys_devid ==
11674 tp->pdev->subsystem_device))
11675 return &subsys_id_to_phy_id[i];
11676 }
11677 return NULL;
11678}
11679
7d0c41ef 11680static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11681{
1da177e4 11682 u32 val;
caf636c7
MC		 11683 u16 pmcsr;
11684
11685 /* On some early chips the SRAM cannot be accessed in D3hot state,
11686 * so need make sure we're in D0.
11687 */
11688 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11689 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11690 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11691 msleep(1);
7d0c41ef
MC		 11692
11693 /* Make sure register accesses (indirect or otherwise)
11694 * will function correctly.
11695 */
11696 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11697 tp->misc_host_ctrl);
1da177e4 11698
f49639e6
DM		 11699 /* The memory arbiter has to be enabled in order for SRAM accesses
11700 * to succeed. Normally on powerup the tg3 chip firmware will make
11701 * sure it is enabled, but other entities such as system netboot
11702 * code might disable it.
11703 */
11704 val = tr32(MEMARB_MODE);
11705 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11706
1da177e4 11707 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11708 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11709
a85feb8c
GZ		 11710 /* Assume an onboard device and WOL capable by default. */
11711 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11712
b5d3772c 11713 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11714 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11715 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11716 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11717 }
0527ba35
MC		 11718 val = tr32(VCPU_CFGSHDW);
11719 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11720 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11721 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11722 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11723 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11724 goto done;
b5d3772c
MC		 11725 }
11726
1da177e4
LT		 11727 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11728 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11729 u32 nic_cfg, led_cfg;
a9daf367 11730 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11731 int eeprom_phy_serdes = 0;
1da177e4
LT		 11732
11733 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11734 tp->nic_sram_data_cfg = nic_cfg;
11735
11736 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11737 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11738 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11739 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11740 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11741 (ver > 0) && (ver < 0x100))
11742 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11743
a9daf367
MC		 11744 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11745 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11746
1da177e4
LT		 11747 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11748 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11749 eeprom_phy_serdes = 1;
11750
11751 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11752 if (nic_phy_id != 0) {
11753 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11754 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11755
11756 eeprom_phy_id = (id1 >> 16) << 10;
11757 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11758 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11759 } else
11760 eeprom_phy_id = 0;
11761
7d0c41ef 11762 tp->phy_id = eeprom_phy_id;
747e8f8b 11763 if (eeprom_phy_serdes) {
a4e2b347 11764 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11765 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11766 else
11767 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11768 }
7d0c41ef 11769
cbf46853 11770 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11771 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11772 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11773 else
1da177e4
LT		 11774 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11775
11776 switch (led_cfg) {
11777 default:
11778 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11779 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11780 break;
11781
11782 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11783 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11784 break;
11785
11786 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11787 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11788
11789 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11790 * read on some older 5700/5701 bootcode.
11791 */
11792 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11793 ASIC_REV_5700 ||
11794 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11795 ASIC_REV_5701)
11796 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11797
1da177e4
LT		 11798 break;
11799
11800 case SHASTA_EXT_LED_SHARED:
11801 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11802 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11803 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11804 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11805 LED_CTRL_MODE_PHY_2);
11806 break;
11807
11808 case SHASTA_EXT_LED_MAC:
11809 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11810 break;
11811
11812 case SHASTA_EXT_LED_COMBO:
11813 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11814 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11815 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11816 LED_CTRL_MODE_PHY_2);
11817 break;
11818
855e1111 11819 }
1da177e4
LT		 11820
11821 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11822 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11823 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11824 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11825
b2a5c19c
MC		 11826 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11827 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11828
9d26e213 11829 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11830 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11831 if ((tp->pdev->subsystem_vendor ==
11832 PCI_VENDOR_ID_ARIMA) &&
11833 (tp->pdev->subsystem_device == 0x205a ||
11834 tp->pdev->subsystem_device == 0x2063))
11835 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11836 } else {
f49639e6 11837 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11838 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11839 }
1da177e4
LT		 11840
11841 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11842 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11843 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11844 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11845 }
b2b98d4a
MC		 11846
11847 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11848 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11849 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11850
a85feb8c
GZ		 11851 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11852 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11853 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11854
12dac075 11855 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11856 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11857 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11858
1da177e4
LT		 11859 if (cfg2 & (1 << 17))
11860 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11861
11862 /* serdes signal pre-emphasis in register 0x590 set by */
11863 /* bootcode if bit 18 is set */
11864 if (cfg2 & (1 << 18))
11865 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11866
321d32a0
MC		 11867 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11868 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11869 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11870 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11871
8ed5d97e
MC		 11872 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11873 u32 cfg3;
11874
11875 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11876 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11877 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11878 }
a9daf367
MC		 11879
11880 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11881 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11882 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11883 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11884 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11885 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11886 }
05ac4cb7
MC		 11887done:
11888 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11889 device_set_wakeup_enable(&tp->pdev->dev,
11890 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11891}
11892
b2a5c19c
MC		 11893static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11894{
11895 int i;
11896 u32 val;
11897
11898 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11899 tw32(OTP_CTRL, cmd);
11900
11901 /* Wait for up to 1 ms for command to execute. */
11902 for (i = 0; i < 100; i++) {
11903 val = tr32(OTP_STATUS);
11904 if (val & OTP_STATUS_CMD_DONE)
11905 break;
11906 udelay(10);
11907 }
11908
11909 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11910}
11911
11912/* Read the gphy configuration from the OTP region of the chip. The gphy
11913 * configuration is a 32-bit value that straddles the alignment boundary.
11914 * We do two 32-bit reads and then shift and merge the results.
11915 */
11916static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11917{
11918 u32 bhalf_otp, thalf_otp;
11919
11920 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11921
11922 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11923 return 0;
11924
11925 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11926
11927 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11928 return 0;
11929
11930 thalf_otp = tr32(OTP_READ_DATA);
11931
11932 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11933
11934 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11935 return 0;
11936
11937 bhalf_otp = tr32(OTP_READ_DATA);
11938
11939 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11940}
11941
7d0c41ef
MC		 11942static int __devinit tg3_phy_probe(struct tg3 *tp)
11943{
11944 u32 hw_phy_id_1, hw_phy_id_2;
11945 u32 hw_phy_id, hw_phy_id_masked;
11946 int err;
1da177e4 11947
b02fd9e3
MC		 11948 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11949 return tg3_phy_init(tp);
11950
1da177e4 11951 /* Reading the PHY ID register can conflict with ASF
877d0310 11952 * firmware access to the PHY hardware.
1da177e4
LT		 11953 */
11954 err = 0;
0d3031d9
MC		 11955 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11956 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11957 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11958 } else {
11959 /* Now read the physical PHY_ID from the chip and verify
11960 * that it is sane. If it doesn't look good, we fall back
11961 * to either the hard-coded table based PHY_ID and failing
11962 * that the value found in the eeprom area.
11963 */
11964 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11965 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11966
11967 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11968 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11969 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11970
11971 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11972 }
11973
11974 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11975 tp->phy_id = hw_phy_id;
11976 if (hw_phy_id_masked == PHY_ID_BCM8002)
11977 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11978 else
11979 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11980 } else {
7d0c41ef
MC		 11981 if (tp->phy_id != PHY_ID_INVALID) {
11982 /* Do nothing, phy ID already set up in
11983 * tg3_get_eeprom_hw_cfg().
11984 */
1da177e4
LT		 11985 } else {
11986 struct subsys_tbl_ent *p;
11987
11988 /* No eeprom signature? Try the hardcoded
11989 * subsys device table.
11990 */
11991 p = lookup_by_subsys(tp);
11992 if (!p)
11993 return -ENODEV;
11994
11995 tp->phy_id = p->phy_id;
11996 if (!tp->phy_id ||
11997 tp->phy_id == PHY_ID_BCM8002)
11998 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11999 }
12000 }
12001
747e8f8b 12002 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12003 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12004 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12005 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12006
12007 tg3_readphy(tp, MII_BMSR, &bmsr);
12008 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12009 (bmsr & BMSR_LSTATUS))
12010 goto skip_phy_reset;
6aa20a22 12011
1da177e4
LT		 12012 err = tg3_phy_reset(tp);
12013 if (err)
12014 return err;
12015
12016 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12017 ADVERTISE_100HALF | ADVERTISE_100FULL |
12018 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12019 tg3_ctrl = 0;
12020 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12021 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12022 MII_TG3_CTRL_ADV_1000_FULL);
12023 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12024 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12025 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12026 MII_TG3_CTRL_ENABLE_AS_MASTER);
12027 }
12028
3600d918
MC		 12029 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12030 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12031 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12032 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12033 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12034
12035 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12036 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12037
12038 tg3_writephy(tp, MII_BMCR,
12039 BMCR_ANENABLE | BMCR_ANRESTART);
12040 }
12041 tg3_phy_set_wirespeed(tp);
12042
12043 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12044 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12045 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12046 }
12047
12048skip_phy_reset:
12049 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12050 err = tg3_init_5401phy_dsp(tp);
12051 if (err)
12052 return err;
12053 }
12054
12055 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12056 err = tg3_init_5401phy_dsp(tp);
12057 }
12058
747e8f8b 12059 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12060 tp->link_config.advertising =
12061 (ADVERTISED_1000baseT_Half |
12062 ADVERTISED_1000baseT_Full |
12063 ADVERTISED_Autoneg |
12064 ADVERTISED_FIBRE);
12065 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12066 tp->link_config.advertising &=
12067 ~(ADVERTISED_1000baseT_Half |
12068 ADVERTISED_1000baseT_Full);
12069
12070 return err;
12071}
12072
12073static void __devinit tg3_read_partno(struct tg3 *tp)
12074{
6d348f2c 12075 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12076 unsigned int i;
1b27777a 12077 u32 magic;
1da177e4 12078
df259d8c
MC		 12079 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12080 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12081 goto out_not_found;
1da177e4 12082
1820180b 12083 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12084 for (i = 0; i < 256; i += 4) {
12085 u32 tmp;
1da177e4 12086
6d348f2c
MC		 12087 /* The data is in little-endian format in NVRAM.
12088 * Use the big-endian read routines to preserve
12089 * the byte order as it exists in NVRAM.
12090 */
12091 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12092 goto out_not_found;
12093
6d348f2c 12094 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12095 }
12096 } else {
12097 int vpd_cap;
12098
12099 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12100 for (i = 0; i < 256; i += 4) {
12101 u32 tmp, j = 0;
b9fc7dc5 12102 __le32 v;
1b27777a
MC		 12103 u16 tmp16;
12104
12105 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12106 i);
12107 while (j++ < 100) {
12108 pci_read_config_word(tp->pdev, vpd_cap +
12109 PCI_VPD_ADDR, &tmp16);
12110 if (tmp16 & 0x8000)
12111 break;
12112 msleep(1);
12113 }
f49639e6
DM		 12114 if (!(tmp16 & 0x8000))
12115 goto out_not_found;
12116
1b27777a
MC		 12117 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12118 &tmp);
b9fc7dc5 12119 v = cpu_to_le32(tmp);
6d348f2c 12120 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12121 }
1da177e4
LT		 12122 }
12123
12124 /* Now parse and find the part number. */
af2c6a4a 12125 for (i = 0; i < 254; ) {
1da177e4 12126 unsigned char val = vpd_data[i];
af2c6a4a 12127 unsigned int block_end;
1da177e4
LT		 12128
12129 if (val == 0x82 || val == 0x91) {
12130 i = (i + 3 +
12131 (vpd_data[i + 1] +
12132 (vpd_data[i + 2] << 8)));
12133 continue;
12134 }
12135
12136 if (val != 0x90)
12137 goto out_not_found;
12138
12139 block_end = (i + 3 +
12140 (vpd_data[i + 1] +
12141 (vpd_data[i + 2] << 8)));
12142 i += 3;
af2c6a4a
MC		 12143
12144 if (block_end > 256)
12145 goto out_not_found;
12146
12147 while (i < (block_end - 2)) {
1da177e4
LT		 12148 if (vpd_data[i + 0] == 'P' &&
12149 vpd_data[i + 1] == 'N') {
12150 int partno_len = vpd_data[i + 2];
12151
af2c6a4a
MC		 12152 i += 3;
12153 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12154 goto out_not_found;
12155
12156 memcpy(tp->board_part_number,
af2c6a4a 12157 &vpd_data[i], partno_len);
1da177e4
LT		 12158
12159 /* Success. */
12160 return;
12161 }
af2c6a4a 12162 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12163 }
12164
12165 /* Part number not found. */
12166 goto out_not_found;
12167 }
12168
12169out_not_found:
b5d3772c
MC		 12170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12171 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12172 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12173 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12174 strcpy(tp->board_part_number, "BCM57780");
12175 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12176 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12177 strcpy(tp->board_part_number, "BCM57760");
12178 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12179 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12180 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12181 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12182 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12183 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12184 else
12185 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12186}
12187
9c8a620e
MC		 12188static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12189{
12190 u32 val;
12191
e4f34110 12192 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12193 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12194 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12195 val != 0)
12196 return 0;
12197
12198 return 1;
12199}
12200
acd9c119
MC		 12201static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12202{
ff3a7cb2 12203 u32 val, offset, start, ver_offset;
acd9c119 12204 int i;
ff3a7cb2 12205 bool newver = false;
acd9c119
MC		 12206
12207 if (tg3_nvram_read(tp, 0xc, &offset) ||
12208 tg3_nvram_read(tp, 0x4, &start))
12209 return;
12210
12211 offset = tg3_nvram_logical_addr(tp, offset);
12212
ff3a7cb2 12213 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12214 return;
12215
ff3a7cb2
MC		 12216 if ((val & 0xfc000000) == 0x0c000000) {
12217 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12218 return;
12219
ff3a7cb2
MC		 12220 if (val == 0)
12221 newver = true;
12222 }
12223
12224 if (newver) {
12225 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12226 return;
12227
12228 offset = offset + ver_offset - start;
12229 for (i = 0; i < 16; i += 4) {
12230 __be32 v;
12231 if (tg3_nvram_read_be32(tp, offset + i, &v))
12232 return;
12233
12234 memcpy(tp->fw_ver + i, &v, sizeof(v));
12235 }
12236 } else {
12237 u32 major, minor;
12238
12239 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12240 return;
12241
12242 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12243 TG3_NVM_BCVER_MAJSFT;
12244 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12245 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12246 }
12247}
12248
a6f6cb1c
MC		 12249static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12250{
12251 u32 val, major, minor;
12252
12253 /* Use native endian representation */
12254 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12255 return;
12256
12257 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12258 TG3_NVM_HWSB_CFG1_MAJSFT;
12259 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12260 TG3_NVM_HWSB_CFG1_MINSFT;
12261
12262 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12263}
12264
dfe00d7d
MC		 12265static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12266{
12267 u32 offset, major, minor, build;
12268
12269 tp->fw_ver[0] = 's';
12270 tp->fw_ver[1] = 'b';
12271 tp->fw_ver[2] = '\0';
12272
12273 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12274 return;
12275
12276 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12277 case TG3_EEPROM_SB_REVISION_0:
12278 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12279 break;
12280 case TG3_EEPROM_SB_REVISION_2:
12281 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12282 break;
12283 case TG3_EEPROM_SB_REVISION_3:
12284 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12285 break;
12286 default:
12287 return;
12288 }
12289
e4f34110 12290 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12291 return;
12292
12293 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12294 TG3_EEPROM_SB_EDH_BLD_SHFT;
12295 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12296 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12297 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12298
12299 if (minor > 99 || build > 26)
12300 return;
12301
12302 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12303
12304 if (build > 0) {
12305 tp->fw_ver[8] = 'a' + build - 1;
12306 tp->fw_ver[9] = '\0';
12307 }
12308}
12309
acd9c119 12310static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12311{
12312 u32 val, offset, start;
acd9c119 12313 int i, vlen;
9c8a620e
MC		 12314
12315 for (offset = TG3_NVM_DIR_START;
12316 offset < TG3_NVM_DIR_END;
12317 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12318 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12319 return;
12320
9c8a620e
MC		 12321 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12322 break;
12323 }
12324
12325 if (offset == TG3_NVM_DIR_END)
12326 return;
12327
12328 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12329 start = 0x08000000;
e4f34110 12330 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12331 return;
12332
e4f34110 12333 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12334 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12335 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12336 return;
12337
12338 offset += val - start;
12339
acd9c119 12340 vlen = strlen(tp->fw_ver);
9c8a620e 12341
acd9c119
MC		 12342 tp->fw_ver[vlen++] = ',';
12343 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12344
12345 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12346 __be32 v;
12347 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12348 return;
12349
b9fc7dc5 12350 offset += sizeof(v);
c4e6575c 12351
acd9c119
MC		 12352 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12353 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12354 break;
c4e6575c 12355 }
9c8a620e 12356
acd9c119
MC		 12357 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12358 vlen += sizeof(v);
c4e6575c 12359 }
acd9c119
MC		 12360}
12361
7fd76445
MC		 12362static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12363{
12364 int vlen;
12365 u32 apedata;
12366
12367 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12368 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12369 return;
12370
12371 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12372 if (apedata != APE_SEG_SIG_MAGIC)
12373 return;
12374
12375 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12376 if (!(apedata & APE_FW_STATUS_READY))
12377 return;
12378
12379 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12380
12381 vlen = strlen(tp->fw_ver);
12382
12383 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12384 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12385 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12386 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12387 (apedata & APE_FW_VERSION_BLDMSK));
12388}
12389
acd9c119
MC		 12390static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12391{
12392 u32 val;
12393
df259d8c
MC		 12394 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12395 tp->fw_ver[0] = 's';
12396 tp->fw_ver[1] = 'b';
12397 tp->fw_ver[2] = '\0';
12398
12399 return;
12400 }
12401
acd9c119
MC		 12402 if (tg3_nvram_read(tp, 0, &val))
12403 return;
12404
12405 if (val == TG3_EEPROM_MAGIC)
12406 tg3_read_bc_ver(tp);
12407 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12408 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12409 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12410 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12411 else
12412 return;
12413
12414 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12415 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12416 return;
12417
12418 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12419
12420 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12421}
12422
7544b097
MC		 12423static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12424
1da177e4
LT		 12425static int __devinit tg3_get_invariants(struct tg3 *tp)
12426{
12427 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12428 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12429 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12430 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12431 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12432 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12433 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12434 { },
12435 };
12436 u32 misc_ctrl_reg;
1da177e4
LT		 12437 u32 pci_state_reg, grc_misc_cfg;
12438 u32 val;
12439 u16 pci_cmd;
5e7dfd0f 12440 int err;
1da177e4 12441
1da177e4
LT		 12442 /* Force memory write invalidate off. If we leave it on,
12443 * then on 5700_BX chips we have to enable a workaround.
12444 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12445 * to match the cacheline size. The Broadcom driver have this
12446 * workaround but turns MWI off all the times so never uses
12447 * it. This seems to suggest that the workaround is insufficient.
12448 */
12449 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12450 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12451 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12452
12453 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12454 * has the register indirect write enable bit set before
12455 * we try to access any of the MMIO registers. It is also
12456 * critical that the PCI-X hw workaround situation is decided
12457 * before that as well.
12458 */
12459 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12460 &misc_ctrl_reg);
12461
12462 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12463 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12465 u32 prod_id_asic_rev;
12466
f6eb9b1f
MC		 12467 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12468 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12469 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12470 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12471 pci_read_config_dword(tp->pdev,
12472 TG3PCI_GEN2_PRODID_ASICREV,
12473 &prod_id_asic_rev);
12474 else
12475 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12476 &prod_id_asic_rev);
12477
321d32a0 12478 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12479 }
1da177e4 12480
ff645bec
MC		 12481 /* Wrong chip ID in 5752 A0. This code can be removed later
12482 * as A0 is not in production.
12483 */
12484 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12485 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12486
6892914f
MC		 12487 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12488 * we need to disable memory and use config. cycles
12489 * only to access all registers. The 5702/03 chips
12490 * can mistakenly decode the special cycles from the
12491 * ICH chipsets as memory write cycles, causing corruption
12492 * of register and memory space. Only certain ICH bridges
12493 * will drive special cycles with non-zero data during the
12494 * address phase which can fall within the 5703's address
12495 * range. This is not an ICH bug as the PCI spec allows
12496 * non-zero address during special cycles. However, only
12497 * these ICH bridges are known to drive non-zero addresses
12498 * during special cycles.
12499 *
12500 * Since special cycles do not cross PCI bridges, we only
12501 * enable this workaround if the 5703 is on the secondary
12502 * bus of these ICH bridges.
12503 */
12504 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12505 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12506 static struct tg3_dev_id {
12507 u32 vendor;
12508 u32 device;
12509 u32 rev;
12510 } ich_chipsets[] = {
12511 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12512 PCI_ANY_ID },
12513 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12514 PCI_ANY_ID },
12515 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12516 0xa },
12517 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12518 PCI_ANY_ID },
12519 { },
12520 };
12521 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12522 struct pci_dev *bridge = NULL;
12523
12524 while (pci_id->vendor != 0) {
12525 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12526 bridge);
12527 if (!bridge) {
12528 pci_id++;
12529 continue;
12530 }
12531 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12532 if (bridge->revision > pci_id->rev)
6892914f
MC		 12533 continue;
12534 }
12535 if (bridge->subordinate &&
12536 (bridge->subordinate->number ==
12537 tp->pdev->bus->number)) {
12538
12539 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12540 pci_dev_put(bridge);
12541 break;
12542 }
12543 }
12544 }
12545
41588ba1
MC		 12546 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12547 static struct tg3_dev_id {
12548 u32 vendor;
12549 u32 device;
12550 } bridge_chipsets[] = {
12551 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12552 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12553 { },
12554 };
12555 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12556 struct pci_dev *bridge = NULL;
12557
12558 while (pci_id->vendor != 0) {
12559 bridge = pci_get_device(pci_id->vendor,
12560 pci_id->device,
12561 bridge);
12562 if (!bridge) {
12563 pci_id++;
12564 continue;
12565 }
12566 if (bridge->subordinate &&
12567 (bridge->subordinate->number <=
12568 tp->pdev->bus->number) &&
12569 (bridge->subordinate->subordinate >=
12570 tp->pdev->bus->number)) {
12571 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12572 pci_dev_put(bridge);
12573 break;
12574 }
12575 }
12576 }
12577
4a29cc2e
MC		 12578 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12579 * DMA addresses > 40-bit. This bridge may have other additional
12580 * 57xx devices behind it in some 4-port NIC designs for example.
12581 * Any tg3 device found behind the bridge will also need the 40-bit
12582 * DMA workaround.
12583 */
a4e2b347
MC		 12584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12585 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12586 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12587 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12588 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12589 }
4a29cc2e
MC		 12590 else {
12591 struct pci_dev *bridge = NULL;
12592
12593 do {
12594 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12595 PCI_DEVICE_ID_SERVERWORKS_EPB,
12596 bridge);
12597 if (bridge && bridge->subordinate &&
12598 (bridge->subordinate->number <=
12599 tp->pdev->bus->number) &&
12600 (bridge->subordinate->subordinate >=
12601 tp->pdev->bus->number)) {
12602 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12603 pci_dev_put(bridge);
12604 break;
12605 }
12606 } while (bridge);
12607 }
4cf78e4f 12608
1da177e4
LT		 12609 /* Initialize misc host control in PCI block. */
12610 tp->misc_host_ctrl |= (misc_ctrl_reg &
12611 MISC_HOST_CTRL_CHIPREV);
12612 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12613 tp->misc_host_ctrl);
12614
f6eb9b1f
MC		 12615 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12618 tp->pdev_peer = tg3_find_peer(tp);
12619
321d32a0
MC		 12620 /* Intentionally exclude ASIC_REV_5906 */
12621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12624 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12626 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12628 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12629
12630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12633 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12634 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12635 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12636
1b440c56
JL		 12637 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12638 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12639 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12640
027455ad
MC		 12641 /* 5700 B0 chips do not support checksumming correctly due
12642 * to hardware bugs.
12643 */
12644 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12645 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12646 else {
12647 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12648 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12649 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12650 tp->dev->features |= NETIF_F_IPV6_CSUM;
12651 }
12652
5a6f3074 12653 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12654 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12655 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12656 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12657 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12658 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12659 tp->pdev_peer == tp->pdev))
12660 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12661
321d32a0 12662 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12663 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12664 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12665 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12666 } else {
7f62ad5d 12667 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12668 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12669 ASIC_REV_5750 &&
12670 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12671 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12672 }
5a6f3074 12673 }
1da177e4 12674
4f125f42
MC		 12675 tp->irq_max = 1;
12676
f6eb9b1f
MC		 12677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12678 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12679 tp->irq_max = TG3_IRQ_MAX_VECS;
12680 }
0e1406dd
MC		 12681
12682 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
92c6b8d1
MC		 12683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12684 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12685 else {
12686 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12687 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12688 }
0e1406dd 12689 }
f6eb9b1f 12690
f51f3562 12691 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12692 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12694 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12695
52f4490c
MC		 12696 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12697 &pci_state_reg);
12698
5e7dfd0f
MC		 12699 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12700 if (tp->pcie_cap != 0) {
12701 u16 lnkctl;
12702
1da177e4 12703 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12704
12705 pcie_set_readrq(tp->pdev, 4096);
12706
5e7dfd0f
MC		 12707 pci_read_config_word(tp->pdev,
12708 tp->pcie_cap + PCI_EXP_LNKCTL,
12709 &lnkctl);
12710 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12711 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12712 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12713 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12714 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12715 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12716 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12717 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12718 }
52f4490c 12719 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12720 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12721 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12722 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12723 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12724 if (!tp->pcix_cap) {
12725 printk(KERN_ERR PFX "Cannot find PCI-X "
12726 "capability, aborting.\n");
12727 return -EIO;
12728 }
12729
12730 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12731 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12732 }
1da177e4 12733
399de50b
MC		 12734 /* If we have an AMD 762 or VIA K8T800 chipset, write
12735 * reordering to the mailbox registers done by the host
12736 * controller can cause major troubles. We read back from
12737 * every mailbox register write to force the writes to be
12738 * posted to the chip in order.
12739 */
12740 if (pci_dev_present(write_reorder_chipsets) &&
12741 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12742 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12743
69fc4053
MC		 12744 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12745 &tp->pci_cacheline_sz);
12746 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12747 &tp->pci_lat_timer);
1da177e4
LT		 12748 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12749 tp->pci_lat_timer < 64) {
12750 tp->pci_lat_timer = 64;
69fc4053
MC		 12751 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12752 tp->pci_lat_timer);
1da177e4
LT		 12753 }
12754
52f4490c
MC		 12755 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12756 /* 5700 BX chips need to have their TX producer index
12757 * mailboxes written twice to workaround a bug.
12758 */
12759 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12760
52f4490c 12761 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12762 *
12763 * The workaround is to use indirect register accesses
12764 * for all chip writes not to mailbox registers.
12765 */
52f4490c 12766 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12767 u32 pm_reg;
1da177e4
LT		 12768
12769 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12770
12771 /* The chip can have it's power management PCI config
12772 * space registers clobbered due to this bug.
12773 * So explicitly force the chip into D0 here.
12774 */
9974a356
MC		 12775 pci_read_config_dword(tp->pdev,
12776 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12777 &pm_reg);
12778 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12779 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12780 pci_write_config_dword(tp->pdev,
12781 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12782 pm_reg);
12783
12784 /* Also, force SERR#/PERR# in PCI command. */
12785 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12786 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12787 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12788 }
12789 }
12790
1da177e4
LT		 12791 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12792 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12793 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12794 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12795
12796 /* Chip-specific fixup from Broadcom driver */
12797 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12798 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12799 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12800 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12801 }
12802
1ee582d8 12803 /* Default fast path register access methods */
20094930 12804 tp->read32 = tg3_read32;
1ee582d8 12805 tp->write32 = tg3_write32;
09ee929c 12806 tp->read32_mbox = tg3_read32;
20094930 12807 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12808 tp->write32_tx_mbox = tg3_write32;
12809 tp->write32_rx_mbox = tg3_write32;
12810
12811 /* Various workaround register access methods */
12812 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12813 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12814 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12815 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12816 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12817 /*
12818 * Back to back register writes can cause problems on these
12819 * chips, the workaround is to read back all reg writes
12820 * except those to mailbox regs.
12821 *
12822 * See tg3_write_indirect_reg32().
12823 */
1ee582d8 12824 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12825 }
12826
1ee582d8
MC		 12827 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12828 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12829 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12830 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12831 tp->write32_rx_mbox = tg3_write_flush_reg32;
12832 }
20094930 12833
6892914f
MC		 12834 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12835 tp->read32 = tg3_read_indirect_reg32;
12836 tp->write32 = tg3_write_indirect_reg32;
12837 tp->read32_mbox = tg3_read_indirect_mbox;
12838 tp->write32_mbox = tg3_write_indirect_mbox;
12839 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12840 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12841
12842 iounmap(tp->regs);
22abe310 12843 tp->regs = NULL;
6892914f
MC		 12844
12845 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12846 pci_cmd &= ~PCI_COMMAND_MEMORY;
12847 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12848 }
b5d3772c
MC		 12849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12850 tp->read32_mbox = tg3_read32_mbox_5906;
12851 tp->write32_mbox = tg3_write32_mbox_5906;
12852 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12853 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12854 }
6892914f 12855
bbadf503
MC		 12856 if (tp->write32 == tg3_write_indirect_reg32 ||
12857 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12858 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12860 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12861
7d0c41ef 12862 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12863 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12864 * determined before calling tg3_set_power_state() so that
12865 * we know whether or not to switch out of Vaux power.
12866 * When the flag is set, it means that GPIO1 is used for eeprom
12867 * write protect and also implies that it is a LOM where GPIOs
12868 * are not used to switch power.
6aa20a22 12869 */
7d0c41ef
MC		 12870 tg3_get_eeprom_hw_cfg(tp);
12871
0d3031d9
MC		 12872 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12873 /* Allow reads and writes to the
12874 * APE register and memory space.
12875 */
12876 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12877 PCISTATE_ALLOW_APE_SHMEM_WR;
12878 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12879 pci_state_reg);
12880 }
12881
9936bcf6 12882 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12887 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12888
314fba34
MC		 12889 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12890 * GPIO1 driven high will bring 5700's external PHY out of reset.
12891 * It is also used as eeprom write protect on LOMs.
12892 */
12893 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12894 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12895 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12896 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12897 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12898 /* Unused GPIO3 must be driven as output on 5752 because there
12899 * are no pull-up resistors on unused GPIO pins.
12900 */
12901 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12902 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12903
321d32a0
MC		 12904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12906 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12907
8d519ab2
MC		 12908 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12909 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12910 /* Turn off the debug UART. */
12911 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12912 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12913 /* Keep VMain power. */
12914 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12915 GRC_LCLCTRL_GPIO_OUTPUT0;
12916 }
12917
1da177e4 12918 /* Force the chip into D0. */
bc1c7567 12919 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12920 if (err) {
12921 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12922 pci_name(tp->pdev));
12923 return err;
12924 }
12925
1da177e4
LT		 12926 /* Derive initial jumbo mode from MTU assigned in
12927 * ether_setup() via the alloc_etherdev() call
12928 */
0f893dc6 12929 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12930 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12931 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12932
12933 /* Determine WakeOnLan speed to use. */
12934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12935 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12936 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12937 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12938 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12939 } else {
12940 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12941 }
12942
7f97a4bd
MC		 12943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12944 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12945
1da177e4
LT		 12946 /* A few boards don't want Ethernet@WireSpeed phy feature */
12947 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12948 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12949 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12950 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12951 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12952 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12953 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12954
12955 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12956 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12957 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12958 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12959 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12960
321d32a0 12961 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12962 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 12963 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 12964 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12965 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 12966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12970 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12971 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12972 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12973 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12974 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12975 } else
c424cb24
MC		 12976 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12977 }
1da177e4 12978
b2a5c19c
MC		 12979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12980 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12981 tp->phy_otp = tg3_read_otp_phycfg(tp);
12982 if (tp->phy_otp == 0)
12983 tp->phy_otp = TG3_OTP_DEFAULT;
12984 }
12985
f51f3562 12986 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12987 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12988 else
12989 tp->mi_mode = MAC_MI_MODE_BASE;
12990
1da177e4 12991 tp->coalesce_mode = 0;
1da177e4
LT		 12992 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12993 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12994 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12995
321d32a0
MC		 12996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12998 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12999
158d7abd
MC		 13000 err = tg3_mdio_init(tp);
13001 if (err)
13002 return err;
1da177e4
LT		 13003
13004 /* Initialize data/descriptor byte/word swapping. */
13005 val = tr32(GRC_MODE);
13006 val &= GRC_MODE_HOST_STACKUP;
13007 tw32(GRC_MODE, val | tp->grc_mode);
13008
13009 tg3_switch_clocks(tp);
13010
13011 /* Clear this out for sanity. */
13012 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13013
13014 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13015 &pci_state_reg);
13016 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13017 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13018 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13019
13020 if (chiprevid == CHIPREV_ID_5701_A0 ||
13021 chiprevid == CHIPREV_ID_5701_B0 ||
13022 chiprevid == CHIPREV_ID_5701_B2 ||
13023 chiprevid == CHIPREV_ID_5701_B5) {
13024 void __iomem *sram_base;
13025
13026 /* Write some dummy words into the SRAM status block
13027 * area, see if it reads back correctly. If the return
13028 * value is bad, force enable the PCIX workaround.
13029 */
13030 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13031
13032 writel(0x00000000, sram_base);
13033 writel(0x00000000, sram_base + 4);
13034 writel(0xffffffff, sram_base + 4);
13035 if (readl(sram_base) != 0x00000000)
13036 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13037 }
13038 }
13039
13040 udelay(50);
13041 tg3_nvram_init(tp);
13042
13043 grc_misc_cfg = tr32(GRC_MISC_CFG);
13044 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13045
1da177e4
LT		 13046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13047 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13048 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13049 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13050
fac9b83e
DM		 13051 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13052 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13053 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13054 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13055 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13056 HOSTCC_MODE_CLRTICK_TXBD);
13057
13058 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13059 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13060 tp->misc_host_ctrl);
13061 }
13062
3bda1258
MC		 13063 /* Preserve the APE MAC_MODE bits */
13064 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13065 tp->mac_mode = tr32(MAC_MODE) |
13066 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13067 else
13068 tp->mac_mode = TG3_DEF_MAC_MODE;
13069
1da177e4
LT		 13070 /* these are limited to 10/100 only */
13071 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13072 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13073 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13074 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13075 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13076 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13077 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13078 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13079 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13080 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13081 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13082 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13083 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13084 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13085
13086 err = tg3_phy_probe(tp);
13087 if (err) {
13088 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13089 pci_name(tp->pdev), err);
13090 /* ... but do not return immediately ... */
b02fd9e3 13091 tg3_mdio_fini(tp);
1da177e4
LT		 13092 }
13093
13094 tg3_read_partno(tp);
c4e6575c 13095 tg3_read_fw_ver(tp);
1da177e4
LT		 13096
13097 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13098 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13099 } else {
13100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13101 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13102 else
13103 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13104 }
13105
13106 /* 5700 {AX,BX} chips have a broken status block link
13107 * change bit implementation, so we must use the
13108 * status register in those cases.
13109 */
13110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13111 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13112 else
13113 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13114
13115 /* The led_ctrl is set during tg3_phy_probe, here we might
13116 * have to force the link status polling mechanism based
13117 * upon subsystem IDs.
13118 */
13119 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13121 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13122 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13123 TG3_FLAG_USE_LINKCHG_REG);
13124 }
13125
13126 /* For all SERDES we poll the MAC status register. */
13127 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13128 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13129 else
13130 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13131
ad829268 13132 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13134 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13135 tp->rx_offset = 0;
13136
f92905de
MC		 13137 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13138
13139 /* Increment the rx prod index on the rx std ring by at most
13140 * 8 for these chips to workaround hw errata.
13141 */
13142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13145 tp->rx_std_max_post = 8;
13146
8ed5d97e
MC		 13147 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13148 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13149 PCIE_PWR_MGMT_L1_THRESH_MSK;
13150
1da177e4
LT		 13151 return err;
13152}
13153
49b6e95f 13154#ifdef CONFIG_SPARC
1da177e4
LT		 13155static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13156{
13157 struct net_device *dev = tp->dev;
13158 struct pci_dev *pdev = tp->pdev;
49b6e95f 13159 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13160 const unsigned char *addr;
49b6e95f
DM		 13161 int len;
13162
13163 addr = of_get_property(dp, "local-mac-address", &len);
13164 if (addr && len == 6) {
13165 memcpy(dev->dev_addr, addr, 6);
13166 memcpy(dev->perm_addr, dev->dev_addr, 6);
13167 return 0;
1da177e4
LT		 13168 }
13169 return -ENODEV;
13170}
13171
13172static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13173{
13174 struct net_device *dev = tp->dev;
13175
13176 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13177 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13178 return 0;
13179}
13180#endif
13181
13182static int __devinit tg3_get_device_address(struct tg3 *tp)
13183{
13184 struct net_device *dev = tp->dev;
13185 u32 hi, lo, mac_offset;
008652b3 13186 int addr_ok = 0;
1da177e4 13187
49b6e95f 13188#ifdef CONFIG_SPARC
1da177e4
LT		 13189 if (!tg3_get_macaddr_sparc(tp))
13190 return 0;
13191#endif
13192
13193 mac_offset = 0x7c;
f49639e6 13194 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13195 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13196 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13197 mac_offset = 0xcc;
13198 if (tg3_nvram_lock(tp))
13199 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13200 else
13201 tg3_nvram_unlock(tp);
a1b950d5
MC		 13202 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13203 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13204 mac_offset = 0xcc;
13205 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13206 mac_offset = 0x10;
1da177e4
LT		 13207
13208 /* First try to get it from MAC address mailbox. */
13209 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13210 if ((hi >> 16) == 0x484b) {
13211 dev->dev_addr[0] = (hi >> 8) & 0xff;
13212 dev->dev_addr[1] = (hi >> 0) & 0xff;
13213
13214 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13215 dev->dev_addr[2] = (lo >> 24) & 0xff;
13216 dev->dev_addr[3] = (lo >> 16) & 0xff;
13217 dev->dev_addr[4] = (lo >> 8) & 0xff;
13218 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13219
008652b3
MC		 13220 /* Some old bootcode may report a 0 MAC address in SRAM */
13221 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13222 }
13223 if (!addr_ok) {
13224 /* Next, try NVRAM. */
df259d8c
MC		 13225 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13226 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13227 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13228 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13229 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13230 }
13231 /* Finally just fetch it out of the MAC control regs. */
13232 else {
13233 hi = tr32(MAC_ADDR_0_HIGH);
13234 lo = tr32(MAC_ADDR_0_LOW);
13235
13236 dev->dev_addr[5] = lo & 0xff;
13237 dev->dev_addr[4] = (lo >> 8) & 0xff;
13238 dev->dev_addr[3] = (lo >> 16) & 0xff;
13239 dev->dev_addr[2] = (lo >> 24) & 0xff;
13240 dev->dev_addr[1] = hi & 0xff;
13241 dev->dev_addr[0] = (hi >> 8) & 0xff;
13242 }
1da177e4
LT		 13243 }
13244
13245 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13246#ifdef CONFIG_SPARC
1da177e4
LT		 13247 if (!tg3_get_default_macaddr_sparc(tp))
13248 return 0;
13249#endif
13250 return -EINVAL;
13251 }
2ff43697 13252 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13253 return 0;
13254}
13255
59e6b434
DM		 13256#define BOUNDARY_SINGLE_CACHELINE 1
13257#define BOUNDARY_MULTI_CACHELINE 2
13258
13259static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13260{
13261 int cacheline_size;
13262 u8 byte;
13263 int goal;
13264
13265 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13266 if (byte == 0)
13267 cacheline_size = 1024;
13268 else
13269 cacheline_size = (int) byte * 4;
13270
13271 /* On 5703 and later chips, the boundary bits have no
13272 * effect.
13273 */
13274 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13275 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13276 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13277 goto out;
13278
13279#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13280 goal = BOUNDARY_MULTI_CACHELINE;
13281#else
13282#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13283 goal = BOUNDARY_SINGLE_CACHELINE;
13284#else
13285 goal = 0;
13286#endif
13287#endif
13288
13289 if (!goal)
13290 goto out;
13291
13292 /* PCI controllers on most RISC systems tend to disconnect
13293 * when a device tries to burst across a cache-line boundary.
13294 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13295 *
13296 * Unfortunately, for PCI-E there are only limited
13297 * write-side controls for this, and thus for reads
13298 * we will still get the disconnects. We'll also waste
13299 * these PCI cycles for both read and write for chips
13300 * other than 5700 and 5701 which do not implement the
13301 * boundary bits.
13302 */
13303 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13304 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13305 switch (cacheline_size) {
13306 case 16:
13307 case 32:
13308 case 64:
13309 case 128:
13310 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13311 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13312 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13313 } else {
13314 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13315 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13316 }
13317 break;
13318
13319 case 256:
13320 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13321 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13322 break;
13323
13324 default:
13325 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13326 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13327 break;
855e1111 13328 }
59e6b434
DM		 13329 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13330 switch (cacheline_size) {
13331 case 16:
13332 case 32:
13333 case 64:
13334 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13335 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13336 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13337 break;
13338 }
13339 /* fallthrough */
13340 case 128:
13341 default:
13342 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13343 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13344 break;
855e1111 13345 }
59e6b434
DM		 13346 } else {
13347 switch (cacheline_size) {
13348 case 16:
13349 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13350 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13351 DMA_RWCTRL_WRITE_BNDRY_16);
13352 break;
13353 }
13354 /* fallthrough */
13355 case 32:
13356 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13357 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13358 DMA_RWCTRL_WRITE_BNDRY_32);
13359 break;
13360 }
13361 /* fallthrough */
13362 case 64:
13363 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13364 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13365 DMA_RWCTRL_WRITE_BNDRY_64);
13366 break;
13367 }
13368 /* fallthrough */
13369 case 128:
13370 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13371 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13372 DMA_RWCTRL_WRITE_BNDRY_128);
13373 break;
13374 }
13375 /* fallthrough */
13376 case 256:
13377 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13378 DMA_RWCTRL_WRITE_BNDRY_256);
13379 break;
13380 case 512:
13381 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13382 DMA_RWCTRL_WRITE_BNDRY_512);
13383 break;
13384 case 1024:
13385 default:
13386 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13387 DMA_RWCTRL_WRITE_BNDRY_1024);
13388 break;
855e1111 13389 }
59e6b434
DM		 13390 }
13391
13392out:
13393 return val;
13394}
13395
1da177e4
LT		 13396static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13397{
13398 struct tg3_internal_buffer_desc test_desc;
13399 u32 sram_dma_descs;
13400 int i, ret;
13401
13402 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13403
13404 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13405 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13406 tw32(RDMAC_STATUS, 0);
13407 tw32(WDMAC_STATUS, 0);
13408
13409 tw32(BUFMGR_MODE, 0);
13410 tw32(FTQ_RESET, 0);
13411
13412 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13413 test_desc.addr_lo = buf_dma & 0xffffffff;
13414 test_desc.nic_mbuf = 0x00002100;
13415 test_desc.len = size;
13416
13417 /*
13418 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13419 * the *second* time the tg3 driver was getting loaded after an
13420 * initial scan.
13421 *
13422 * Broadcom tells me:
13423 * ...the DMA engine is connected to the GRC block and a DMA
13424 * reset may affect the GRC block in some unpredictable way...
13425 * The behavior of resets to individual blocks has not been tested.
13426 *
13427 * Broadcom noted the GRC reset will also reset all sub-components.
13428 */
13429 if (to_device) {
13430 test_desc.cqid_sqid = (13 << 8) | 2;
13431
13432 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13433 udelay(40);
13434 } else {
13435 test_desc.cqid_sqid = (16 << 8) | 7;
13436
13437 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13438 udelay(40);
13439 }
13440 test_desc.flags = 0x00000005;
13441
13442 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13443 u32 val;
13444
13445 val = *(((u32 *)&test_desc) + i);
13446 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13447 sram_dma_descs + (i * sizeof(u32)));
13448 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13449 }
13450 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13451
13452 if (to_device) {
13453 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13454 } else {
13455 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13456 }
13457
13458 ret = -ENODEV;
13459 for (i = 0; i < 40; i++) {
13460 u32 val;
13461
13462 if (to_device)
13463 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13464 else
13465 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13466 if ((val & 0xffff) == sram_dma_descs) {
13467 ret = 0;
13468 break;
13469 }
13470
13471 udelay(100);
13472 }
13473
13474 return ret;
13475}
13476
ded7340d 13477#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13478
13479static int __devinit tg3_test_dma(struct tg3 *tp)
13480{
13481 dma_addr_t buf_dma;
59e6b434 13482 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13483 int ret;
13484
13485 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13486 if (!buf) {
13487 ret = -ENOMEM;
13488 goto out_nofree;
13489 }
13490
13491 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13492 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13493
59e6b434 13494 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13495
13496 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13497 /* DMA read watermark not used on PCIE */
13498 tp->dma_rwctrl |= 0x00180000;
13499 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13502 tp->dma_rwctrl |= 0x003f0000;
13503 else
13504 tp->dma_rwctrl |= 0x003f000f;
13505 } else {
13506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13507 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13508 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13509 u32 read_water = 0x7;
1da177e4 13510
4a29cc2e
MC		 13511 /* If the 5704 is behind the EPB bridge, we can
13512 * do the less restrictive ONE_DMA workaround for
13513 * better performance.
13514 */
13515 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13517 tp->dma_rwctrl |= 0x8000;
13518 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13519 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13520
49afdeb6
MC		 13521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13522 read_water = 4;
59e6b434 13523 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13524 tp->dma_rwctrl |=
13525 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13526 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13527 (1 << 23);
4cf78e4f
MC		 13528 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13529 /* 5780 always in PCIX mode */
13530 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13531 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13532 /* 5714 always in PCIX mode */
13533 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13534 } else {
13535 tp->dma_rwctrl |= 0x001b000f;
13536 }
13537 }
13538
13539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13540 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13541 tp->dma_rwctrl &= 0xfffffff0;
13542
13543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13544 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13545 /* Remove this if it causes problems for some boards. */
13546 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13547
13548 /* On 5700/5701 chips, we need to set this bit.
13549 * Otherwise the chip will issue cacheline transactions
13550 * to streamable DMA memory with not all the byte
13551 * enables turned on. This is an error on several
13552 * RISC PCI controllers, in particular sparc64.
13553 *
13554 * On 5703/5704 chips, this bit has been reassigned
13555 * a different meaning. In particular, it is used
13556 * on those chips to enable a PCI-X workaround.
13557 */
13558 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13559 }
13560
13561 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13562
13563#if 0
13564 /* Unneeded, already done by tg3_get_invariants. */
13565 tg3_switch_clocks(tp);
13566#endif
13567
13568 ret = 0;
13569 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13570 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13571 goto out;
13572
59e6b434
DM		 13573 /* It is best to perform DMA test with maximum write burst size
13574 * to expose the 5700/5701 write DMA bug.
13575 */
13576 saved_dma_rwctrl = tp->dma_rwctrl;
13577 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13578 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13579
1da177e4
LT		 13580 while (1) {
13581 u32 *p = buf, i;
13582
13583 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13584 p[i] = i;
13585
13586 /* Send the buffer to the chip. */
13587 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13588 if (ret) {
13589 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13590 break;
13591 }
13592
13593#if 0
13594 /* validate data reached card RAM correctly. */
13595 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13596 u32 val;
13597 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13598 if (le32_to_cpu(val) != p[i]) {
13599 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13600 /* ret = -ENODEV here? */
13601 }
13602 p[i] = 0;
13603 }
13604#endif
13605 /* Now read it back. */
13606 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13607 if (ret) {
13608 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13609
13610 break;
13611 }
13612
13613 /* Verify it. */
13614 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13615 if (p[i] == i)
13616 continue;
13617
59e6b434
DM		 13618 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13619 DMA_RWCTRL_WRITE_BNDRY_16) {
13620 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13621 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13622 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13623 break;
13624 } else {
13625 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13626 ret = -ENODEV;
13627 goto out;
13628 }
13629 }
13630
13631 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13632 /* Success. */
13633 ret = 0;
13634 break;
13635 }
13636 }
59e6b434
DM		 13637 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13638 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13639 static struct pci_device_id dma_wait_state_chipsets[] = {
13640 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13641 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13642 { },
13643 };
13644
59e6b434 13645 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13646 * now look for chipsets that are known to expose the
13647 * DMA bug without failing the test.
59e6b434 13648 */
6d1cfbab
MC		 13649 if (pci_dev_present(dma_wait_state_chipsets)) {
13650 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13651 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13652 }
13653 else
13654 /* Safe to use the calculated DMA boundary. */
13655 tp->dma_rwctrl = saved_dma_rwctrl;
13656
59e6b434
DM		 13657 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13658 }
1da177e4
LT		 13659
13660out:
13661 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13662out_nofree:
13663 return ret;
13664}
13665
13666static void __devinit tg3_init_link_config(struct tg3 *tp)
13667{
13668 tp->link_config.advertising =
13669 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13670 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13671 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13672 ADVERTISED_Autoneg | ADVERTISED_MII);
13673 tp->link_config.speed = SPEED_INVALID;
13674 tp->link_config.duplex = DUPLEX_INVALID;
13675 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13676 tp->link_config.active_speed = SPEED_INVALID;
13677 tp->link_config.active_duplex = DUPLEX_INVALID;
13678 tp->link_config.phy_is_low_power = 0;
13679 tp->link_config.orig_speed = SPEED_INVALID;
13680 tp->link_config.orig_duplex = DUPLEX_INVALID;
13681 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13682}
13683
13684static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13685{
f6eb9b1f
MC		 13686 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13687 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13688 tp->bufmgr_config.mbuf_read_dma_low_water =
13689 DEFAULT_MB_RDMA_LOW_WATER_5705;
13690 tp->bufmgr_config.mbuf_mac_rx_low_water =
13691 DEFAULT_MB_MACRX_LOW_WATER_5705;
13692 tp->bufmgr_config.mbuf_high_water =
13693 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13695 tp->bufmgr_config.mbuf_mac_rx_low_water =
13696 DEFAULT_MB_MACRX_LOW_WATER_5906;
13697 tp->bufmgr_config.mbuf_high_water =
13698 DEFAULT_MB_HIGH_WATER_5906;
13699 }
fdfec172
MC		 13700
13701 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13702 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13703 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13704 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13705 tp->bufmgr_config.mbuf_high_water_jumbo =
13706 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13707 } else {
13708 tp->bufmgr_config.mbuf_read_dma_low_water =
13709 DEFAULT_MB_RDMA_LOW_WATER;
13710 tp->bufmgr_config.mbuf_mac_rx_low_water =
13711 DEFAULT_MB_MACRX_LOW_WATER;
13712 tp->bufmgr_config.mbuf_high_water =
13713 DEFAULT_MB_HIGH_WATER;
13714
13715 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13716 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13717 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13718 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13719 tp->bufmgr_config.mbuf_high_water_jumbo =
13720 DEFAULT_MB_HIGH_WATER_JUMBO;
13721 }
1da177e4
LT		 13722
13723 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13724 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13725}
13726
13727static char * __devinit tg3_phy_string(struct tg3 *tp)
13728{
13729 switch (tp->phy_id & PHY_ID_MASK) {
13730 case PHY_ID_BCM5400: return "5400";
13731 case PHY_ID_BCM5401: return "5401";
13732 case PHY_ID_BCM5411: return "5411";
13733 case PHY_ID_BCM5701: return "5701";
13734 case PHY_ID_BCM5703: return "5703";
13735 case PHY_ID_BCM5704: return "5704";
13736 case PHY_ID_BCM5705: return "5705";
13737 case PHY_ID_BCM5750: return "5750";
85e94ced 13738 case PHY_ID_BCM5752: return "5752";
a4e2b347 13739 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13740 case PHY_ID_BCM5780: return "5780";
af36e6b6 13741 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13742 case PHY_ID_BCM5787: return "5787";
d30cdd28 13743 case PHY_ID_BCM5784: return "5784";
126a3368 13744 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13745 case PHY_ID_BCM5906: return "5906";
9936bcf6 13746 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13747 case PHY_ID_BCM8002: return "8002/serdes";
13748 case 0: return "serdes";
13749 default: return "unknown";
855e1111 13750 }
1da177e4
LT		 13751}
13752
f9804ddb
MC		 13753static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13754{
13755 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13756 strcpy(str, "PCI Express");
13757 return str;
13758 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13759 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13760
13761 strcpy(str, "PCIX:");
13762
13763 if ((clock_ctrl == 7) ||
13764 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13765 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13766 strcat(str, "133MHz");
13767 else if (clock_ctrl == 0)
13768 strcat(str, "33MHz");
13769 else if (clock_ctrl == 2)
13770 strcat(str, "50MHz");
13771 else if (clock_ctrl == 4)
13772 strcat(str, "66MHz");
13773 else if (clock_ctrl == 6)
13774 strcat(str, "100MHz");
f9804ddb
MC		 13775 } else {
13776 strcpy(str, "PCI:");
13777 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13778 strcat(str, "66MHz");
13779 else
13780 strcat(str, "33MHz");
13781 }
13782 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13783 strcat(str, ":32-bit");
13784 else
13785 strcat(str, ":64-bit");
13786 return str;
13787}
13788
8c2dc7e1 13789static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13790{
13791 struct pci_dev *peer;
13792 unsigned int func, devnr = tp->pdev->devfn & ~7;
13793
13794 for (func = 0; func < 8; func++) {
13795 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13796 if (peer && peer != tp->pdev)
13797 break;
13798 pci_dev_put(peer);
13799 }
16fe9d74
MC		 13800 /* 5704 can be configured in single-port mode, set peer to
13801 * tp->pdev in that case.
13802 */
13803 if (!peer) {
13804 peer = tp->pdev;
13805 return peer;
13806 }
1da177e4
LT		 13807
13808 /*
13809 * We don't need to keep the refcount elevated; there's no way
13810 * to remove one half of this device without removing the other
13811 */
13812 pci_dev_put(peer);
13813
13814 return peer;
13815}
13816
15f9850d
DM		 13817static void __devinit tg3_init_coal(struct tg3 *tp)
13818{
13819 struct ethtool_coalesce *ec = &tp->coal;
13820
13821 memset(ec, 0, sizeof(*ec));
13822 ec->cmd = ETHTOOL_GCOALESCE;
13823 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13824 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13825 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13826 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13827 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13828 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13829 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13830 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13831 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13832
13833 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13834 HOSTCC_MODE_CLRTICK_TXBD)) {
13835 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13836 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13837 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13838 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13839 }
d244c892
MC		 13840
13841 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13842 ec->rx_coalesce_usecs_irq = 0;
13843 ec->tx_coalesce_usecs_irq = 0;
13844 ec->stats_block_coalesce_usecs = 0;
13845 }
15f9850d
DM		 13846}
13847
7c7d64b8
SH		 13848static const struct net_device_ops tg3_netdev_ops = {
13849 .ndo_open = tg3_open,
13850 .ndo_stop = tg3_close,
00829823
SH		 13851 .ndo_start_xmit = tg3_start_xmit,
13852 .ndo_get_stats = tg3_get_stats,
13853 .ndo_validate_addr = eth_validate_addr,
13854 .ndo_set_multicast_list = tg3_set_rx_mode,
13855 .ndo_set_mac_address = tg3_set_mac_addr,
13856 .ndo_do_ioctl = tg3_ioctl,
13857 .ndo_tx_timeout = tg3_tx_timeout,
13858 .ndo_change_mtu = tg3_change_mtu,
13859#if TG3_VLAN_TAG_USED
13860 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13861#endif
13862#ifdef CONFIG_NET_POLL_CONTROLLER
13863 .ndo_poll_controller = tg3_poll_controller,
13864#endif
13865};
13866
13867static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13868 .ndo_open = tg3_open,
13869 .ndo_stop = tg3_close,
13870 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13871 .ndo_get_stats = tg3_get_stats,
13872 .ndo_validate_addr = eth_validate_addr,
13873 .ndo_set_multicast_list = tg3_set_rx_mode,
13874 .ndo_set_mac_address = tg3_set_mac_addr,
13875 .ndo_do_ioctl = tg3_ioctl,
13876 .ndo_tx_timeout = tg3_tx_timeout,
13877 .ndo_change_mtu = tg3_change_mtu,
13878#if TG3_VLAN_TAG_USED
13879 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13880#endif
13881#ifdef CONFIG_NET_POLL_CONTROLLER
13882 .ndo_poll_controller = tg3_poll_controller,
13883#endif
13884};
13885
1da177e4
LT		 13886static int __devinit tg3_init_one(struct pci_dev *pdev,
13887 const struct pci_device_id *ent)
13888{
13889 static int tg3_version_printed = 0;
1da177e4
LT		 13890 struct net_device *dev;
13891 struct tg3 *tp;
646c9edd
MC		 13892 int i, err, pm_cap;
13893 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13894 char str[40];
72f2afb8 13895 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13896
13897 if (tg3_version_printed++ == 0)
13898 printk(KERN_INFO "%s", version);
13899
13900 err = pci_enable_device(pdev);
13901 if (err) {
13902 printk(KERN_ERR PFX "Cannot enable PCI device, "
13903 "aborting.\n");
13904 return err;
13905 }
13906
1da177e4
LT		 13907 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13908 if (err) {
13909 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13910 "aborting.\n");
13911 goto err_out_disable_pdev;
13912 }
13913
13914 pci_set_master(pdev);
13915
13916 /* Find power-management capability. */
13917 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13918 if (pm_cap == 0) {
13919 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13920 "aborting.\n");
13921 err = -EIO;
13922 goto err_out_free_res;
13923 }
13924
fe5f5787 13925 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 13926 if (!dev) {
13927 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13928 err = -ENOMEM;
13929 goto err_out_free_res;
13930 }
13931
1da177e4
LT		 13932 SET_NETDEV_DEV(dev, &pdev->dev);
13933
1da177e4
LT		 13934#if TG3_VLAN_TAG_USED
13935 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13936#endif
13937
13938 tp = netdev_priv(dev);
13939 tp->pdev = pdev;
13940 tp->dev = dev;
13941 tp->pm_cap = pm_cap;
1da177e4
LT		 13942 tp->rx_mode = TG3_DEF_RX_MODE;
13943 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13944
1da177e4
LT		 13945 if (tg3_debug > 0)
13946 tp->msg_enable = tg3_debug;
13947 else
13948 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13949
13950 /* The word/byte swap controls here control register access byte
13951 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13952 * setting below.
13953 */
13954 tp->misc_host_ctrl =
13955 MISC_HOST_CTRL_MASK_PCI_INT |
13956 MISC_HOST_CTRL_WORD_SWAP |
13957 MISC_HOST_CTRL_INDIR_ACCESS |
13958 MISC_HOST_CTRL_PCISTATE_RW;
13959
13960 /* The NONFRM (non-frame) byte/word swap controls take effect
13961 * on descriptor entries, anything which isn't packet data.
13962 *
13963 * The StrongARM chips on the board (one for tx, one for rx)
13964 * are running in big-endian mode.
13965 */
13966 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13967 GRC_MODE_WSWAP_NONFRM_DATA);
13968#ifdef __BIG_ENDIAN
13969 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13970#endif
13971 spin_lock_init(&tp->lock);
1da177e4 13972 spin_lock_init(&tp->indirect_lock);
c4028958 13973 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13974
d5fe488a 13975 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13976 if (!tp->regs) {
1da177e4
LT		 13977 printk(KERN_ERR PFX "Cannot map device registers, "
13978 "aborting.\n");
13979 err = -ENOMEM;
13980 goto err_out_free_dev;
13981 }
13982
13983 tg3_init_link_config(tp);
13984
1da177e4
LT		 13985 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13986 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13987
646c9edd
MC		 13988 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13989 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13990 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13991 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13992 struct tg3_napi *tnapi = &tp->napi[i];
13993
13994 tnapi->tp = tp;
13995 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13996
13997 tnapi->int_mbox = intmbx;
13998 if (i < 4)
13999 intmbx += 0x8;
14000 else
14001 intmbx += 0x4;
14002
14003 tnapi->consmbox = rcvmbx;
14004 tnapi->prodmbox = sndmbx;
14005
14006 if (i)
14007 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14008 else
14009 tnapi->coal_now = HOSTCC_MODE_NOW;
14010
14011 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14012 break;
14013
14014 /*
14015 * If we support MSIX, we'll be using RSS. If we're using
14016 * RSS, the first vector only handles link interrupts and the
14017 * remaining vectors handle rx and tx interrupts. Reuse the
14018 * mailbox values for the next iteration. The values we setup
14019 * above are still useful for the single vectored mode.
14020 */
14021 if (!i)
14022 continue;
14023
14024 rcvmbx += 0x8;
14025
14026 if (sndmbx & 0x4)
14027 sndmbx -= 0x4;
14028 else
14029 sndmbx += 0xc;
14030 }
14031
8ef0442f 14032 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 14033 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14034 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14035 dev->irq = pdev->irq;
1da177e4
LT		 14036
14037 err = tg3_get_invariants(tp);
14038 if (err) {
14039 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14040 "aborting.\n");
14041 goto err_out_iounmap;
14042 }
14043
92c6b8d1 14044 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
00829823
SH		 14045 dev->netdev_ops = &tg3_netdev_ops;
14046 else
14047 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14048
14049
4a29cc2e
MC		 14050 /* The EPB bridge inside 5714, 5715, and 5780 and any
14051 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14052 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14053 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14054 * do DMA address check in tg3_start_xmit().
14055 */
4a29cc2e 14056 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14057 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14058 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14059 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14060#ifdef CONFIG_HIGHMEM
6a35528a 14061 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14062#endif
4a29cc2e 14063 } else
6a35528a 14064 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14065
14066 /* Configure DMA attributes. */
284901a9 14067 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14068 err = pci_set_dma_mask(pdev, dma_mask);
14069 if (!err) {
14070 dev->features |= NETIF_F_HIGHDMA;
14071 err = pci_set_consistent_dma_mask(pdev,
14072 persist_dma_mask);
14073 if (err < 0) {
14074 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14075 "DMA for consistent allocations\n");
14076 goto err_out_iounmap;
14077 }
14078 }
14079 }
284901a9
YH		 14080 if (err || dma_mask == DMA_BIT_MASK(32)) {
14081 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14082 if (err) {
14083 printk(KERN_ERR PFX "No usable DMA configuration, "
14084 "aborting.\n");
14085 goto err_out_iounmap;
14086 }
14087 }
14088
fdfec172 14089 tg3_init_bufmgr_config(tp);
1da177e4 14090
077f849d 14091 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 14092 tp->fw_needed = FIRMWARE_TG3;
077f849d 14093
1da177e4
LT		 14094 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14095 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14096 }
14097 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14099 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 14100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 14101 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14102 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14103 } else {
7f62ad5d 14104 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 14105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 14106 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 14107 else
9e9fd12d 14108 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 14109 }
1da177e4 14110
4e3a7aaa
MC		 14111 /* TSO is on by default on chips that support hardware TSO.
14112 * Firmware TSO on older chips gives lower performance, so it
14113 * is off by default, but can be enabled using ethtool.
14114 */
b0026624 14115 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 14116 if (dev->features & NETIF_F_IP_CSUM)
14117 dev->features |= NETIF_F_TSO;
14118 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14119 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 14120 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 14121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14122 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14123 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 14125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6 14127 dev->features |= NETIF_F_TSO_ECN;
b0026624 14128 }
1da177e4 14129
1da177e4
LT		 14130
14131 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14132 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14133 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14134 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14135 tp->rx_pending = 63;
14136 }
14137
1da177e4
LT		 14138 err = tg3_get_device_address(tp);
14139 if (err) {
14140 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14141 "aborting.\n");
077f849d 14142 goto err_out_fw;
1da177e4
LT		 14143 }
14144
c88864df 14145 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14146 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14147 if (!tp->aperegs) {
c88864df
MC		 14148 printk(KERN_ERR PFX "Cannot map APE registers, "
14149 "aborting.\n");
14150 err = -ENOMEM;
077f849d 14151 goto err_out_fw;
c88864df
MC		 14152 }
14153
14154 tg3_ape_lock_init(tp);
7fd76445
MC		 14155
14156 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14157 tg3_read_dash_ver(tp);
c88864df
MC		 14158 }
14159
1da177e4
LT		 14160 /*
14161 * Reset chip in case UNDI or EFI driver did not shutdown
14162 * DMA self test will enable WDMAC and we'll see (spurious)
14163 * pending DMA on the PCI bus at that point.
14164 */
14165 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14166 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14167 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14168 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14169 }
14170
14171 err = tg3_test_dma(tp);
14172 if (err) {
14173 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14174 goto err_out_apeunmap;
1da177e4
LT		 14175 }
14176
1da177e4
LT		 14177 /* flow control autonegotiation is default behavior */
14178 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14179 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14180
15f9850d
DM		 14181 tg3_init_coal(tp);
14182
c49a1561
MC		 14183 pci_set_drvdata(pdev, dev);
14184
1da177e4
LT		 14185 err = register_netdev(dev);
14186 if (err) {
14187 printk(KERN_ERR PFX "Cannot register net device, "
14188 "aborting.\n");
0d3031d9 14189 goto err_out_apeunmap;
1da177e4
LT		 14190 }
14191
df59c940 14192 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14193 dev->name,
14194 tp->board_part_number,
14195 tp->pci_chip_rev_id,
f9804ddb 14196 tg3_bus_string(tp, str),
e174961c 14197 dev->dev_addr);
1da177e4 14198
3f0e3ad7
MC		 14199 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14200 struct phy_device *phydev;
14201 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14202 printk(KERN_INFO
14203 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14204 tp->dev->name, phydev->drv->name,
14205 dev_name(&phydev->dev));
14206 } else
df59c940
MC		 14207 printk(KERN_INFO
14208 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14209 tp->dev->name, tg3_phy_string(tp),
14210 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14211 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14212 "10/100/1000Base-T")),
14213 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14214
14215 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14216 dev->name,
14217 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14218 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14219 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14220 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14221 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14222 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14223 dev->name, tp->dma_rwctrl,
284901a9 14224 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14225 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14226
14227 return 0;
14228
0d3031d9
MC		 14229err_out_apeunmap:
14230 if (tp->aperegs) {
14231 iounmap(tp->aperegs);
14232 tp->aperegs = NULL;
14233 }
14234
077f849d
JSR		 14235err_out_fw:
14236 if (tp->fw)
14237 release_firmware(tp->fw);
14238
1da177e4 14239err_out_iounmap:
6892914f
MC		 14240 if (tp->regs) {
14241 iounmap(tp->regs);
22abe310 14242 tp->regs = NULL;
6892914f 14243 }
1da177e4
LT		 14244
14245err_out_free_dev:
14246 free_netdev(dev);
14247
14248err_out_free_res:
14249 pci_release_regions(pdev);
14250
14251err_out_disable_pdev:
14252 pci_disable_device(pdev);
14253 pci_set_drvdata(pdev, NULL);
14254 return err;
14255}
14256
14257static void __devexit tg3_remove_one(struct pci_dev *pdev)
14258{
14259 struct net_device *dev = pci_get_drvdata(pdev);
14260
14261 if (dev) {
14262 struct tg3 *tp = netdev_priv(dev);
14263
077f849d
JSR		 14264 if (tp->fw)
14265 release_firmware(tp->fw);
14266
7faa006f 14267 flush_scheduled_work();
158d7abd 14268
b02fd9e3
MC		 14269 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14270 tg3_phy_fini(tp);
158d7abd 14271 tg3_mdio_fini(tp);
b02fd9e3 14272 }
158d7abd 14273
1da177e4 14274 unregister_netdev(dev);
0d3031d9
MC		 14275 if (tp->aperegs) {
14276 iounmap(tp->aperegs);
14277 tp->aperegs = NULL;
14278 }
6892914f
MC		 14279 if (tp->regs) {
14280 iounmap(tp->regs);
22abe310 14281 tp->regs = NULL;
6892914f 14282 }
1da177e4
LT		 14283 free_netdev(dev);
14284 pci_release_regions(pdev);
14285 pci_disable_device(pdev);
14286 pci_set_drvdata(pdev, NULL);
14287 }
14288}
14289
14290static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14291{
14292 struct net_device *dev = pci_get_drvdata(pdev);
14293 struct tg3 *tp = netdev_priv(dev);
12dac075 14294 pci_power_t target_state;
1da177e4
LT		 14295 int err;
14296
3e0c95fd
MC		 14297 /* PCI register 4 needs to be saved whether netif_running() or not.
14298 * MSI address and data need to be saved if using MSI and
14299 * netif_running().
14300 */
14301 pci_save_state(pdev);
14302
1da177e4
LT		 14303 if (!netif_running(dev))
14304 return 0;
14305
7faa006f 14306 flush_scheduled_work();
b02fd9e3 14307 tg3_phy_stop(tp);
1da177e4
LT		 14308 tg3_netif_stop(tp);
14309
14310 del_timer_sync(&tp->timer);
14311
f47c11ee 14312 tg3_full_lock(tp, 1);
1da177e4 14313 tg3_disable_ints(tp);
f47c11ee 14314 tg3_full_unlock(tp);
1da177e4
LT		 14315
14316 netif_device_detach(dev);
14317
f47c11ee 14318 tg3_full_lock(tp, 0);
944d980e 14319 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14320 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14321 tg3_full_unlock(tp);
1da177e4 14322
12dac075
RW		 14323 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14324
14325 err = tg3_set_power_state(tp, target_state);
1da177e4 14326 if (err) {
b02fd9e3
MC		 14327 int err2;
14328
f47c11ee 14329 tg3_full_lock(tp, 0);
1da177e4 14330
6a9eba15 14331 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14332 err2 = tg3_restart_hw(tp, 1);
14333 if (err2)
b9ec6c1b 14334 goto out;
1da177e4
LT		 14335
14336 tp->timer.expires = jiffies + tp->timer_offset;
14337 add_timer(&tp->timer);
14338
14339 netif_device_attach(dev);
14340 tg3_netif_start(tp);
14341
b9ec6c1b 14342out:
f47c11ee 14343 tg3_full_unlock(tp);
b02fd9e3
MC		 14344
14345 if (!err2)
14346 tg3_phy_start(tp);
1da177e4
LT		 14347 }
14348
14349 return err;
14350}
14351
14352static int tg3_resume(struct pci_dev *pdev)
14353{
14354 struct net_device *dev = pci_get_drvdata(pdev);
14355 struct tg3 *tp = netdev_priv(dev);
14356 int err;
14357
3e0c95fd
MC		 14358 pci_restore_state(tp->pdev);
14359
1da177e4
LT		 14360 if (!netif_running(dev))
14361 return 0;
14362
bc1c7567 14363 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14364 if (err)
14365 return err;
14366
14367 netif_device_attach(dev);
14368
f47c11ee 14369 tg3_full_lock(tp, 0);
1da177e4 14370
6a9eba15 14371 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14372 err = tg3_restart_hw(tp, 1);
14373 if (err)
14374 goto out;
1da177e4
LT		 14375
14376 tp->timer.expires = jiffies + tp->timer_offset;
14377 add_timer(&tp->timer);
14378
1da177e4
LT		 14379 tg3_netif_start(tp);
14380
b9ec6c1b 14381out:
f47c11ee 14382 tg3_full_unlock(tp);
1da177e4 14383
b02fd9e3
MC		 14384 if (!err)
14385 tg3_phy_start(tp);
14386
b9ec6c1b 14387 return err;
1da177e4
LT		 14388}
14389
14390static struct pci_driver tg3_driver = {
14391 .name = DRV_MODULE_NAME,
14392 .id_table = tg3_pci_tbl,
14393 .probe = tg3_init_one,
14394 .remove = __devexit_p(tg3_remove_one),
14395 .suspend = tg3_suspend,
14396 .resume = tg3_resume
14397};
14398
14399static int __init tg3_init(void)
14400{
29917620 14401 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14402}
14403
14404static void __exit tg3_cleanup(void)
14405{
14406 pci_unregister_driver(&tg3_driver);
14407}
14408
14409module_init(tg3_init);
14410module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree