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tg3: Disable CLKREQ in L2
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
ba5b0bfa 7 * Copyright (C) 2005-2010 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
7ae554e5
MC		 70#define DRV_MODULE_VERSION "3.109"
71#define DRV_MODULE_RELDATE "April 2, 2010"
1da177e4
LT		 72
73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0
75#define TG3_DEF_TX_MODE 0
76#define TG3_DEF_MSG_ENABLE \
77 (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86/* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
88 */
89#define TG3_TX_TIMEOUT (5 * HZ)
90
91/* hardware minimum and maximum for a single frame's data payload */
92#define TG3_MIN_MTU 60
93#define TG3_MAX_MTU(tp) \
8f666b07 94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 95
96/* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
99 */
100#define TG3_RX_RING_SIZE 512
101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
c6cdf436 104#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
79ed5ac7
MC		 121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
1da177e4 123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 124 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
1da177e4
LT		 127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
287be12e
MC		 129#define TG3_DMA_BYTE_ENAB 64
130
131#define TG3_RX_STD_DMA_SZ 1536
132#define TG3_RX_JMB_DMA_SZ 9046
133
134#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135
136#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 138
2b2cdb65
MC		 139#define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
141
142#define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144
c6cdf436
MC		 145#define TG3_RSS_MIN_NUM_MSIX_VECS 2
146
1da177e4 147/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 148#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 149
ad829268
MC		 150#define TG3_RAW_IP_ALIGN 2
151
1da177e4
LT		 152/* number of ETHTOOL_GSTATS u64's */
153#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
154
4cafd3f5
MC		 155#define TG3_NUM_TEST 6
156
c6cdf436
MC		 157#define TG3_FW_UPDATE_TIMEOUT_SEC 5
158
077f849d
JSR		 159#define FIRMWARE_TG3 "tigon/tg3.bin"
160#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
161#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
162
1da177e4 163static char version[] __devinitdata =
05dbe005 164 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 165
166MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
167MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
168MODULE_LICENSE("GPL");
169MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 170MODULE_FIRMWARE(FIRMWARE_TG3);
171MODULE_FIRMWARE(FIRMWARE_TG3TSO);
172MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
173
1da177e4
LT		 174static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
175module_param(tg3_debug, int, 0);
176MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
177
a3aa1884 178static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
b0f75221
MC		 248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
13185217
HK		 254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
259 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
260 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
261 {}
1da177e4
LT		 262};
263
264MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
265
50da859d 266static const struct {
1da177e4
LT		 267 const char string[ETH_GSTRING_LEN];
268} ethtool_stats_keys[TG3_NUM_STATS] = {
269 { "rx_octets" },
270 { "rx_fragments" },
271 { "rx_ucast_packets" },
272 { "rx_mcast_packets" },
273 { "rx_bcast_packets" },
274 { "rx_fcs_errors" },
275 { "rx_align_errors" },
276 { "rx_xon_pause_rcvd" },
277 { "rx_xoff_pause_rcvd" },
278 { "rx_mac_ctrl_rcvd" },
279 { "rx_xoff_entered" },
280 { "rx_frame_too_long_errors" },
281 { "rx_jabbers" },
282 { "rx_undersize_packets" },
283 { "rx_in_length_errors" },
284 { "rx_out_length_errors" },
285 { "rx_64_or_less_octet_packets" },
286 { "rx_65_to_127_octet_packets" },
287 { "rx_128_to_255_octet_packets" },
288 { "rx_256_to_511_octet_packets" },
289 { "rx_512_to_1023_octet_packets" },
290 { "rx_1024_to_1522_octet_packets" },
291 { "rx_1523_to_2047_octet_packets" },
292 { "rx_2048_to_4095_octet_packets" },
293 { "rx_4096_to_8191_octet_packets" },
294 { "rx_8192_to_9022_octet_packets" },
295
296 { "tx_octets" },
297 { "tx_collisions" },
298
299 { "tx_xon_sent" },
300 { "tx_xoff_sent" },
301 { "tx_flow_control" },
302 { "tx_mac_errors" },
303 { "tx_single_collisions" },
304 { "tx_mult_collisions" },
305 { "tx_deferred" },
306 { "tx_excessive_collisions" },
307 { "tx_late_collisions" },
308 { "tx_collide_2times" },
309 { "tx_collide_3times" },
310 { "tx_collide_4times" },
311 { "tx_collide_5times" },
312 { "tx_collide_6times" },
313 { "tx_collide_7times" },
314 { "tx_collide_8times" },
315 { "tx_collide_9times" },
316 { "tx_collide_10times" },
317 { "tx_collide_11times" },
318 { "tx_collide_12times" },
319 { "tx_collide_13times" },
320 { "tx_collide_14times" },
321 { "tx_collide_15times" },
322 { "tx_ucast_packets" },
323 { "tx_mcast_packets" },
324 { "tx_bcast_packets" },
325 { "tx_carrier_sense_errors" },
326 { "tx_discards" },
327 { "tx_errors" },
328
329 { "dma_writeq_full" },
330 { "dma_write_prioq_full" },
331 { "rxbds_empty" },
332 { "rx_discards" },
333 { "rx_errors" },
334 { "rx_threshold_hit" },
335
336 { "dma_readq_full" },
337 { "dma_read_prioq_full" },
338 { "tx_comp_queue_full" },
339
340 { "ring_set_send_prod_index" },
341 { "ring_status_update" },
342 { "nic_irqs" },
343 { "nic_avoided_irqs" },
344 { "nic_tx_threshold_hit" }
345};
346
50da859d 347static const struct {
4cafd3f5
MC		 348 const char string[ETH_GSTRING_LEN];
349} ethtool_test_keys[TG3_NUM_TEST] = {
350 { "nvram test (online) " },
351 { "link test (online) " },
352 { "register test (offline)" },
353 { "memory test (offline)" },
354 { "loopback test (offline)" },
355 { "interrupt test (offline)" },
356};
357
b401e9e2
MC		 358static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
359{
360 writel(val, tp->regs + off);
361}
362
363static u32 tg3_read32(struct tg3 *tp, u32 off)
364{
6aa20a22 365 return (readl(tp->regs + off));
b401e9e2
MC		 366}
367
0d3031d9
MC		 368static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
369{
370 writel(val, tp->aperegs + off);
371}
372
373static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
374{
375 return (readl(tp->aperegs + off));
376}
377
1da177e4
LT		 378static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
379{
6892914f
MC		 380 unsigned long flags;
381
382 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 383 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 385 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 386}
387
388static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
389{
390 writel(val, tp->regs + off);
391 readl(tp->regs + off);
1da177e4
LT		 392}
393
6892914f 394static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 395{
6892914f
MC		 396 unsigned long flags;
397 u32 val;
398
399 spin_lock_irqsave(&tp->indirect_lock, flags);
400 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
401 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
403 return val;
404}
405
406static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
407{
408 unsigned long flags;
409
410 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
411 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
412 TG3_64BIT_REG_LOW, val);
413 return;
414 }
66711e66 415 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 416 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
417 TG3_64BIT_REG_LOW, val);
418 return;
1da177e4 419 }
6892914f
MC		 420
421 spin_lock_irqsave(&tp->indirect_lock, flags);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
424 spin_unlock_irqrestore(&tp->indirect_lock, flags);
425
426 /* In indirect mode when disabling interrupts, we also need
427 * to clear the interrupt bit in the GRC local ctrl register.
428 */
429 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
430 (val == 0x1)) {
431 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
432 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
433 }
434}
435
436static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
437{
438 unsigned long flags;
439 u32 val;
440
441 spin_lock_irqsave(&tp->indirect_lock, flags);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
443 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
444 spin_unlock_irqrestore(&tp->indirect_lock, flags);
445 return val;
446}
447
b401e9e2
MC		 448/* usec_wait specifies the wait time in usec when writing to certain registers
449 * where it is unsafe to read back the register without some delay.
450 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
451 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
452 */
453static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 454{
b401e9e2
MC		 455 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
456 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
457 /* Non-posted methods */
458 tp->write32(tp, off, val);
459 else {
460 /* Posted method */
461 tg3_write32(tp, off, val);
462 if (usec_wait)
463 udelay(usec_wait);
464 tp->read32(tp, off);
465 }
466 /* Wait again after the read for the posted method to guarantee that
467 * the wait time is met.
468 */
469 if (usec_wait)
470 udelay(usec_wait);
1da177e4
LT		 471}
472
09ee929c
MC		 473static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
474{
475 tp->write32_mbox(tp, off, val);
6892914f
MC		 476 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
477 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478 tp->read32_mbox(tp, off);
09ee929c
MC		 479}
480
20094930 481static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 482{
483 void __iomem *mbox = tp->regs + off;
484 writel(val, mbox);
485 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
486 writel(val, mbox);
487 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
488 readl(mbox);
489}
490
b5d3772c
MC		 491static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
492{
493 return (readl(tp->regs + off + GRCMBOX_BASE));
494}
495
496static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
497{
498 writel(val, tp->regs + off + GRCMBOX_BASE);
499}
500
c6cdf436 501#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 502#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 503#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
504#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
505#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 506
c6cdf436
MC		 507#define tw32(reg, val) tp->write32(tp, reg, val)
508#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
509#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
510#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 511
512static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
513{
6892914f
MC		 514 unsigned long flags;
515
b5d3772c
MC		 516 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
517 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
518 return;
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 530
bbadf503
MC		 531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 535}
536
1da177e4
LT		 537static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
538{
6892914f
MC		 539 unsigned long flags;
540
b5d3772c
MC		 541 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
542 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
543 *val = 0;
544 return;
545 }
546
6892914f 547 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 548 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
549 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
550 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 551
bbadf503
MC		 552 /* Always leave this as zero. */
553 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 } else {
555 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
556 *val = tr32(TG3PCI_MEM_WIN_DATA);
557
558 /* Always leave this as zero. */
559 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
560 }
6892914f 561 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 562}
563
0d3031d9
MC		 564static void tg3_ape_lock_init(struct tg3 *tp)
565{
566 int i;
567
568 /* Make sure the driver hasn't any stale locks. */
569 for (i = 0; i < 8; i++)
570 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
571 APE_LOCK_GRANT_DRIVER);
572}
573
574static int tg3_ape_lock(struct tg3 *tp, int locknum)
575{
576 int i, off;
577 int ret = 0;
578 u32 status;
579
580 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
581 return 0;
582
583 switch (locknum) {
33f401ae
MC		 584 case TG3_APE_LOCK_GRC:
585 case TG3_APE_LOCK_MEM:
586 break;
587 default:
588 return -EINVAL;
0d3031d9
MC		 589 }
590
591 off = 4 * locknum;
592
593 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
594
595 /* Wait for up to 1 millisecond to acquire lock. */
596 for (i = 0; i < 100; i++) {
597 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
598 if (status == APE_LOCK_GRANT_DRIVER)
599 break;
600 udelay(10);
601 }
602
603 if (status != APE_LOCK_GRANT_DRIVER) {
604 /* Revoke the lock request. */
605 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
606 APE_LOCK_GRANT_DRIVER);
607
608 ret = -EBUSY;
609 }
610
611 return ret;
612}
613
614static void tg3_ape_unlock(struct tg3 *tp, int locknum)
615{
616 int off;
617
618 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
619 return;
620
621 switch (locknum) {
33f401ae
MC		 622 case TG3_APE_LOCK_GRC:
623 case TG3_APE_LOCK_MEM:
624 break;
625 default:
626 return;
0d3031d9
MC		 627 }
628
629 off = 4 * locknum;
630 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
631}
632
1da177e4
LT		 633static void tg3_disable_ints(struct tg3 *tp)
634{
89aeb3bc
MC		 635 int i;
636
1da177e4
LT		 637 tw32(TG3PCI_MISC_HOST_CTRL,
638 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 639 for (i = 0; i < tp->irq_max; i++)
640 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 641}
642
1da177e4
LT		 643static void tg3_enable_ints(struct tg3 *tp)
644{
89aeb3bc 645 int i;
89aeb3bc 646
bbe832c0
MC		 647 tp->irq_sync = 0;
648 wmb();
649
1da177e4
LT		 650 tw32(TG3PCI_MISC_HOST_CTRL,
651 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 652
f89f38b8 653 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 654 for (i = 0; i < tp->irq_cnt; i++) {
655 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 656
898a56f8 657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 658 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
659 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 660
f89f38b8 661 tp->coal_now |= tnapi->coal_now;
89aeb3bc 662 }
f19af9c2
MC		 663
664 /* Force an initial interrupt */
665 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
666 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
667 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
668 else
f89f38b8
MC		 669 tw32(HOSTCC_MODE, tp->coal_now);
670
671 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 672}
673
17375d25 674static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 675{
17375d25 676 struct tg3 *tp = tnapi->tp;
898a56f8 677 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 678 unsigned int work_exists = 0;
679
680 /* check for phy events */
681 if (!(tp->tg3_flags &
682 (TG3_FLAG_USE_LINKCHG_REG |
683 TG3_FLAG_POLL_SERDES))) {
684 if (sblk->status & SD_STATUS_LINK_CHG)
685 work_exists = 1;
686 }
687 /* check for RX/TX work to do */
f3f3f27e 688 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 689 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 690 work_exists = 1;
691
692 return work_exists;
693}
694
17375d25 695/* tg3_int_reenable
04237ddd
MC		 696 * similar to tg3_enable_ints, but it accurately determines whether there
697 * is new work pending and can return without flushing the PIO write
6aa20a22 698 * which reenables interrupts
1da177e4 699 */
17375d25 700static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 701{
17375d25
MC		 702 struct tg3 *tp = tnapi->tp;
703
898a56f8 704 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 705 mmiowb();
706
fac9b83e
DM		 707 /* When doing tagged status, this work check is unnecessary.
708 * The last_tag we write above tells the chip which piece of
709 * work we've completed.
710 */
711 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 712 tg3_has_work(tnapi))
04237ddd 713 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 714 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 715}
716
fed97810
MC		 717static void tg3_napi_disable(struct tg3 *tp)
718{
719 int i;
720
721 for (i = tp->irq_cnt - 1; i >= 0; i--)
722 napi_disable(&tp->napi[i].napi);
723}
724
725static void tg3_napi_enable(struct tg3 *tp)
726{
727 int i;
728
729 for (i = 0; i < tp->irq_cnt; i++)
730 napi_enable(&tp->napi[i].napi);
731}
732
1da177e4
LT		 733static inline void tg3_netif_stop(struct tg3 *tp)
734{
bbe832c0 735 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 736 tg3_napi_disable(tp);
1da177e4
LT		 737 netif_tx_disable(tp->dev);
738}
739
740static inline void tg3_netif_start(struct tg3 *tp)
741{
fe5f5787
MC		 742 /* NOTE: unconditional netif_tx_wake_all_queues is only
743 * appropriate so long as all callers are assured to
744 * have free tx slots (such as after tg3_init_hw)
1da177e4 745 */
fe5f5787
MC		 746 netif_tx_wake_all_queues(tp->dev);
747
fed97810
MC		 748 tg3_napi_enable(tp);
749 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 750 tg3_enable_ints(tp);
1da177e4
LT		 751}
752
753static void tg3_switch_clocks(struct tg3 *tp)
754{
f6eb9b1f 755 u32 clock_ctrl;
1da177e4
LT		 756 u32 orig_clock_ctrl;
757
795d01c5
MC		 758 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
759 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 760 return;
761
f6eb9b1f
MC		 762 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
763
1da177e4
LT		 764 orig_clock_ctrl = clock_ctrl;
765 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
766 CLOCK_CTRL_CLKRUN_OENABLE |
767 0x1f);
768 tp->pci_clock_ctrl = clock_ctrl;
769
770 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
771 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 772 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 774 }
775 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 776 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777 clock_ctrl |
778 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
779 40);
780 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781 clock_ctrl | (CLOCK_CTRL_ALTCLK),
782 40);
1da177e4 783 }
b401e9e2 784 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 785}
786
787#define PHY_BUSY_LOOPS 5000
788
789static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
790{
791 u32 frame_val;
792 unsigned int loops;
793 int ret;
794
795 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
796 tw32_f(MAC_MI_MODE,
797 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
798 udelay(80);
799 }
800
801 *val = 0x0;
802
882e9793 803 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 804 MI_COM_PHY_ADDR_MASK);
805 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
806 MI_COM_REG_ADDR_MASK);
807 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 808
1da177e4
LT		 809 tw32_f(MAC_MI_COM, frame_val);
810
811 loops = PHY_BUSY_LOOPS;
812 while (loops != 0) {
813 udelay(10);
814 frame_val = tr32(MAC_MI_COM);
815
816 if ((frame_val & MI_COM_BUSY) == 0) {
817 udelay(5);
818 frame_val = tr32(MAC_MI_COM);
819 break;
820 }
821 loops -= 1;
822 }
823
824 ret = -EBUSY;
825 if (loops != 0) {
826 *val = frame_val & MI_COM_DATA_MASK;
827 ret = 0;
828 }
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE, tp->mi_mode);
832 udelay(80);
833 }
834
835 return ret;
836}
837
838static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
839{
840 u32 frame_val;
841 unsigned int loops;
842 int ret;
843
7f97a4bd 844 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 845 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
846 return 0;
847
1da177e4
LT		 848 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
849 tw32_f(MAC_MI_MODE,
850 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
851 udelay(80);
852 }
853
882e9793 854 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 855 MI_COM_PHY_ADDR_MASK);
856 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
857 MI_COM_REG_ADDR_MASK);
858 frame_val |= (val & MI_COM_DATA_MASK);
859 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 860
1da177e4
LT		 861 tw32_f(MAC_MI_COM, frame_val);
862
863 loops = PHY_BUSY_LOOPS;
864 while (loops != 0) {
865 udelay(10);
866 frame_val = tr32(MAC_MI_COM);
867 if ((frame_val & MI_COM_BUSY) == 0) {
868 udelay(5);
869 frame_val = tr32(MAC_MI_COM);
870 break;
871 }
872 loops -= 1;
873 }
874
875 ret = -EBUSY;
876 if (loops != 0)
877 ret = 0;
878
879 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
880 tw32_f(MAC_MI_MODE, tp->mi_mode);
881 udelay(80);
882 }
883
884 return ret;
885}
886
95e2869a
MC		 887static int tg3_bmcr_reset(struct tg3 *tp)
888{
889 u32 phy_control;
890 int limit, err;
891
892 /* OK, reset it, and poll the BMCR_RESET bit until it
893 * clears or we time out.
894 */
895 phy_control = BMCR_RESET;
896 err = tg3_writephy(tp, MII_BMCR, phy_control);
897 if (err != 0)
898 return -EBUSY;
899
900 limit = 5000;
901 while (limit--) {
902 err = tg3_readphy(tp, MII_BMCR, &phy_control);
903 if (err != 0)
904 return -EBUSY;
905
906 if ((phy_control & BMCR_RESET) == 0) {
907 udelay(40);
908 break;
909 }
910 udelay(10);
911 }
d4675b52 912 if (limit < 0)
95e2869a
MC		 913 return -EBUSY;
914
915 return 0;
916}
917
158d7abd
MC		 918static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
919{
3d16543d 920 struct tg3 *tp = bp->priv;
158d7abd
MC		 921 u32 val;
922
24bb4fb6 923 spin_lock_bh(&tp->lock);
158d7abd
MC		 924
925 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 926 val = -EIO;
927
928 spin_unlock_bh(&tp->lock);
158d7abd
MC		 929
930 return val;
931}
932
933static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
934{
3d16543d 935 struct tg3 *tp = bp->priv;
24bb4fb6 936 u32 ret = 0;
158d7abd 937
24bb4fb6 938 spin_lock_bh(&tp->lock);
158d7abd
MC		 939
940 if (tg3_writephy(tp, reg, val))
24bb4fb6 941 ret = -EIO;
158d7abd 942
24bb4fb6
MC		 943 spin_unlock_bh(&tp->lock);
944
945 return ret;
158d7abd
MC		 946}
947
948static int tg3_mdio_reset(struct mii_bus *bp)
949{
950 return 0;
951}
952
9c61d6bc 953static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 954{
955 u32 val;
fcb389df 956 struct phy_device *phydev;
a9daf367 957
3f0e3ad7 958 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 959 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 960 case PHY_ID_BCM50610:
961 case PHY_ID_BCM50610M:
fcb389df
MC		 962 val = MAC_PHYCFG2_50610_LED_MODES;
963 break;
6a443a0f 964 case PHY_ID_BCMAC131:
fcb389df
MC		 965 val = MAC_PHYCFG2_AC131_LED_MODES;
966 break;
6a443a0f 967 case PHY_ID_RTL8211C:
fcb389df
MC		 968 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
969 break;
6a443a0f 970 case PHY_ID_RTL8201E:
fcb389df
MC		 971 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
972 break;
973 default:
a9daf367 974 return;
fcb389df
MC		 975 }
976
977 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
978 tw32(MAC_PHYCFG2, val);
979
980 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 981 val &= ~(MAC_PHYCFG1_RGMII_INT |
982 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
983 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 984 tw32(MAC_PHYCFG1, val);
985
986 return;
987 }
988
14417063 989 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
fcb389df
MC		 990 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
991 MAC_PHYCFG2_FMODE_MASK_MASK |
992 MAC_PHYCFG2_GMODE_MASK_MASK |
993 MAC_PHYCFG2_ACT_MASK_MASK |
994 MAC_PHYCFG2_QUAL_MASK_MASK |
995 MAC_PHYCFG2_INBAND_ENABLE;
996
997 tw32(MAC_PHYCFG2, val);
a9daf367 998
bb85fbb6
MC		 999 val = tr32(MAC_PHYCFG1);
1000 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1001 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
14417063 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1005 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1006 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1007 }
bb85fbb6
MC		 1008 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1009 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1010 tw32(MAC_PHYCFG1, val);
a9daf367 1011
a9daf367
MC		 1012 val = tr32(MAC_EXT_RGMII_MODE);
1013 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET |
1017 MAC_RGMII_MODE_TX_ENABLE |
1018 MAC_RGMII_MODE_TX_LOWPWR |
1019 MAC_RGMII_MODE_TX_RESET);
14417063 1020 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1021 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1022 val |= MAC_RGMII_MODE_RX_INT_B |
1023 MAC_RGMII_MODE_RX_QUALITY |
1024 MAC_RGMII_MODE_RX_ACTIVITY |
1025 MAC_RGMII_MODE_RX_ENG_DET;
1026 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1027 val |= MAC_RGMII_MODE_TX_ENABLE |
1028 MAC_RGMII_MODE_TX_LOWPWR |
1029 MAC_RGMII_MODE_TX_RESET;
1030 }
1031 tw32(MAC_EXT_RGMII_MODE, val);
1032}
1033
158d7abd
MC		 1034static void tg3_mdio_start(struct tg3 *tp)
1035{
158d7abd
MC		 1036 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1038 udelay(80);
a9daf367 1039
9ea4818d
MC		 1040 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1042 tg3_mdio_config_5785(tp);
1043}
1044
1045static int tg3_mdio_init(struct tg3 *tp)
1046{
1047 int i;
1048 u32 reg;
1049 struct phy_device *phydev;
1050
882e9793
MC		 1051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1052 u32 funcnum, is_serdes;
1053
1054 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1055 if (funcnum)
1056 tp->phy_addr = 2;
1057 else
1058 tp->phy_addr = 1;
1059
d1ec96af
MC		 1060 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1061 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1062 else
1063 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1064 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1065 if (is_serdes)
1066 tp->phy_addr += 7;
1067 } else
3f0e3ad7 1068 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1069
158d7abd
MC		 1070 tg3_mdio_start(tp);
1071
1072 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1073 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1074 return 0;
1075
298cf9be
LB		 1076 tp->mdio_bus = mdiobus_alloc();
1077 if (tp->mdio_bus == NULL)
1078 return -ENOMEM;
158d7abd 1079
298cf9be
LB		 1080 tp->mdio_bus->name = "tg3 mdio bus";
1081 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1082 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1083 tp->mdio_bus->priv = tp;
1084 tp->mdio_bus->parent = &tp->pdev->dev;
1085 tp->mdio_bus->read = &tg3_mdio_read;
1086 tp->mdio_bus->write = &tg3_mdio_write;
1087 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1088 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1089 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1090
1091 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1092 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1093
1094 /* The bus registration will look for all the PHYs on the mdio bus.
1095 * Unfortunately, it does not ensure the PHY is powered up before
1096 * accessing the PHY ID registers. A chip reset is the
1097 * quickest way to bring the device back to an operational state..
1098 */
1099 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1100 tg3_bmcr_reset(tp);
1101
298cf9be 1102 i = mdiobus_register(tp->mdio_bus);
a9daf367 1103 if (i) {
ab96b241 1104 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1105 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1106 return i;
1107 }
158d7abd 1108
3f0e3ad7 1109 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1110
9c61d6bc 1111 if (!phydev || !phydev->drv) {
ab96b241 1112 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1113 mdiobus_unregister(tp->mdio_bus);
1114 mdiobus_free(tp->mdio_bus);
1115 return -ENODEV;
1116 }
1117
1118 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1119 case PHY_ID_BCM57780:
321d32a0 1120 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1121 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1122 break;
6a443a0f
MC		 1123 case PHY_ID_BCM50610:
1124 case PHY_ID_BCM50610M:
32e5a8d6 1125 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1126 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1127 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1128 PHY_BRCM_AUTO_PWRDWN_ENABLE;
14417063 1129 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
a9daf367
MC		 1130 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1132 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1133 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1134 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1135 /* fallthru */
6a443a0f 1136 case PHY_ID_RTL8211C:
fcb389df 1137 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1138 break;
6a443a0f
MC		 1139 case PHY_ID_RTL8201E:
1140 case PHY_ID_BCMAC131:
a9daf367 1141 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1142 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1143 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1144 break;
1145 }
1146
9c61d6bc
MC		 1147 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1148
1149 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1150 tg3_mdio_config_5785(tp);
a9daf367
MC		 1151
1152 return 0;
158d7abd
MC		 1153}
1154
1155static void tg3_mdio_fini(struct tg3 *tp)
1156{
1157 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1158 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1159 mdiobus_unregister(tp->mdio_bus);
1160 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1161 }
1162}
1163
4ba526ce
MC		 1164/* tp->lock is held. */
1165static inline void tg3_generate_fw_event(struct tg3 *tp)
1166{
1167 u32 val;
1168
1169 val = tr32(GRC_RX_CPU_EVENT);
1170 val |= GRC_RX_CPU_DRIVER_EVENT;
1171 tw32_f(GRC_RX_CPU_EVENT, val);
1172
1173 tp->last_event_jiffies = jiffies;
1174}
1175
1176#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1177
95e2869a
MC		 1178/* tp->lock is held. */
1179static void tg3_wait_for_event_ack(struct tg3 *tp)
1180{
1181 int i;
4ba526ce
MC		 1182 unsigned int delay_cnt;
1183 long time_remain;
1184
1185 /* If enough time has passed, no wait is necessary. */
1186 time_remain = (long)(tp->last_event_jiffies + 1 +
1187 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1188 (long)jiffies;
1189 if (time_remain < 0)
1190 return;
1191
1192 /* Check if we can shorten the wait time. */
1193 delay_cnt = jiffies_to_usecs(time_remain);
1194 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1195 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1196 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1197
4ba526ce 1198 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1199 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1200 break;
4ba526ce 1201 udelay(8);
95e2869a
MC		 1202 }
1203}
1204
1205/* tp->lock is held. */
1206static void tg3_ump_link_report(struct tg3 *tp)
1207{
1208 u32 reg;
1209 u32 val;
1210
1211 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1212 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1213 return;
1214
1215 tg3_wait_for_event_ack(tp);
1216
1217 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1218
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1220
1221 val = 0;
1222 if (!tg3_readphy(tp, MII_BMCR, &reg))
1223 val = reg << 16;
1224 if (!tg3_readphy(tp, MII_BMSR, &reg))
1225 val |= (reg & 0xffff);
1226 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1227
1228 val = 0;
1229 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1230 val = reg << 16;
1231 if (!tg3_readphy(tp, MII_LPA, &reg))
1232 val |= (reg & 0xffff);
1233 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1234
1235 val = 0;
1236 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1237 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1238 val = reg << 16;
1239 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1240 val |= (reg & 0xffff);
1241 }
1242 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1243
1244 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1245 val = reg << 16;
1246 else
1247 val = 0;
1248 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1249
4ba526ce 1250 tg3_generate_fw_event(tp);
95e2869a
MC		 1251}
1252
1253static void tg3_link_report(struct tg3 *tp)
1254{
1255 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1256 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1257 tg3_ump_link_report(tp);
1258 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1259 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1260 (tp->link_config.active_speed == SPEED_1000 ?
1261 1000 :
1262 (tp->link_config.active_speed == SPEED_100 ?
1263 100 : 10)),
1264 (tp->link_config.active_duplex == DUPLEX_FULL ?
1265 "full" : "half"));
1266
1267 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1268 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1269 "on" : "off",
1270 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1271 "on" : "off");
95e2869a
MC		 1272 tg3_ump_link_report(tp);
1273 }
1274}
1275
1276static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1277{
1278 u16 miireg;
1279
e18ce346 1280 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1281 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1282 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1283 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1284 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1285 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1286 else
1287 miireg = 0;
1288
1289 return miireg;
1290}
1291
1292static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1293{
1294 u16 miireg;
1295
e18ce346 1296 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1297 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1298 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1299 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1300 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1301 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1302 else
1303 miireg = 0;
1304
1305 return miireg;
1306}
1307
95e2869a
MC		 1308static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1309{
1310 u8 cap = 0;
1311
1312 if (lcladv & ADVERTISE_1000XPAUSE) {
1313 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1314 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1315 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1316 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1317 cap = FLOW_CTRL_RX;
95e2869a
MC		 1318 } else {
1319 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1320 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1321 }
1322 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1323 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1324 cap = FLOW_CTRL_TX;
95e2869a
MC		 1325 }
1326
1327 return cap;
1328}
1329
f51f3562 1330static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1331{
b02fd9e3 1332 u8 autoneg;
f51f3562 1333 u8 flowctrl = 0;
95e2869a
MC		 1334 u32 old_rx_mode = tp->rx_mode;
1335 u32 old_tx_mode = tp->tx_mode;
1336
b02fd9e3 1337 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1338 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1339 else
1340 autoneg = tp->link_config.autoneg;
1341
1342 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1343 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1344 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1345 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1346 else
bc02ff95 1347 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1348 } else
1349 flowctrl = tp->link_config.flowctrl;
95e2869a 1350
f51f3562 1351 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1352
e18ce346 1353 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1354 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1355 else
1356 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1357
f51f3562 1358 if (old_rx_mode != tp->rx_mode)
95e2869a 1359 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1360
e18ce346 1361 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1362 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1363 else
1364 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1365
f51f3562 1366 if (old_tx_mode != tp->tx_mode)
95e2869a 1367 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1368}
1369
b02fd9e3
MC		 1370static void tg3_adjust_link(struct net_device *dev)
1371{
1372 u8 oldflowctrl, linkmesg = 0;
1373 u32 mac_mode, lcl_adv, rmt_adv;
1374 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1375 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1376
24bb4fb6 1377 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1378
1379 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1380 MAC_MODE_HALF_DUPLEX);
1381
1382 oldflowctrl = tp->link_config.active_flowctrl;
1383
1384 if (phydev->link) {
1385 lcl_adv = 0;
1386 rmt_adv = 0;
1387
1388 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1389 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1390 else if (phydev->speed == SPEED_1000 ||
1391 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1392 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1393 else
1394 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1395
1396 if (phydev->duplex == DUPLEX_HALF)
1397 mac_mode |= MAC_MODE_HALF_DUPLEX;
1398 else {
1399 lcl_adv = tg3_advert_flowctrl_1000T(
1400 tp->link_config.flowctrl);
1401
1402 if (phydev->pause)
1403 rmt_adv = LPA_PAUSE_CAP;
1404 if (phydev->asym_pause)
1405 rmt_adv |= LPA_PAUSE_ASYM;
1406 }
1407
1408 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1409 } else
1410 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1411
1412 if (mac_mode != tp->mac_mode) {
1413 tp->mac_mode = mac_mode;
1414 tw32_f(MAC_MODE, tp->mac_mode);
1415 udelay(40);
1416 }
1417
fcb389df
MC		 1418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1419 if (phydev->speed == SPEED_10)
1420 tw32(MAC_MI_STAT,
1421 MAC_MI_STAT_10MBPS_MODE |
1422 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1423 else
1424 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1425 }
1426
b02fd9e3
MC		 1427 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1428 tw32(MAC_TX_LENGTHS,
1429 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1430 (6 << TX_LENGTHS_IPG_SHIFT) |
1431 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1432 else
1433 tw32(MAC_TX_LENGTHS,
1434 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1435 (6 << TX_LENGTHS_IPG_SHIFT) |
1436 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1437
1438 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1439 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1440 phydev->speed != tp->link_config.active_speed ||
1441 phydev->duplex != tp->link_config.active_duplex ||
1442 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 1443 linkmesg = 1;
b02fd9e3
MC		 1444
1445 tp->link_config.active_speed = phydev->speed;
1446 tp->link_config.active_duplex = phydev->duplex;
1447
24bb4fb6 1448 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1449
1450 if (linkmesg)
1451 tg3_link_report(tp);
1452}
1453
1454static int tg3_phy_init(struct tg3 *tp)
1455{
1456 struct phy_device *phydev;
1457
1458 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1459 return 0;
1460
1461 /* Bring the PHY back to a known state. */
1462 tg3_bmcr_reset(tp);
1463
3f0e3ad7 1464 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1465
1466 /* Attach the MAC to the PHY. */
fb28ad35 1467 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1468 phydev->dev_flags, phydev->interface);
b02fd9e3 1469 if (IS_ERR(phydev)) {
ab96b241 1470 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 1471 return PTR_ERR(phydev);
1472 }
1473
b02fd9e3 1474 /* Mask with MAC supported features. */
9c61d6bc
MC		 1475 switch (phydev->interface) {
1476 case PHY_INTERFACE_MODE_GMII:
1477 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1478 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1479 phydev->supported &= (PHY_GBIT_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 }
1484 /* fallthru */
9c61d6bc
MC		 1485 case PHY_INTERFACE_MODE_MII:
1486 phydev->supported &= (PHY_BASIC_FEATURES |
1487 SUPPORTED_Pause |
1488 SUPPORTED_Asym_Pause);
1489 break;
1490 default:
3f0e3ad7 1491 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1492 return -EINVAL;
1493 }
1494
1495 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1496
1497 phydev->advertising = phydev->supported;
1498
b02fd9e3
MC		 1499 return 0;
1500}
1501
1502static void tg3_phy_start(struct tg3 *tp)
1503{
1504 struct phy_device *phydev;
1505
1506 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1507 return;
1508
3f0e3ad7 1509 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1510
1511 if (tp->link_config.phy_is_low_power) {
1512 tp->link_config.phy_is_low_power = 0;
1513 phydev->speed = tp->link_config.orig_speed;
1514 phydev->duplex = tp->link_config.orig_duplex;
1515 phydev->autoneg = tp->link_config.orig_autoneg;
1516 phydev->advertising = tp->link_config.orig_advertising;
1517 }
1518
1519 phy_start(phydev);
1520
1521 phy_start_aneg(phydev);
1522}
1523
1524static void tg3_phy_stop(struct tg3 *tp)
1525{
1526 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1527 return;
1528
3f0e3ad7 1529 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1530}
1531
1532static void tg3_phy_fini(struct tg3 *tp)
1533{
1534 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1535 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1536 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1537 }
1538}
1539
b2a5c19c
MC		 1540static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1541{
1542 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1543 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1544}
1545
7f97a4bd
MC		 1546static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1547{
1548 u32 phytest;
1549
1550 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1551 u32 phy;
1552
1553 tg3_writephy(tp, MII_TG3_FET_TEST,
1554 phytest | MII_TG3_FET_SHADOW_EN);
1555 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1556 if (enable)
1557 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1558 else
1559 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1560 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1561 }
1562 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1563 }
1564}
1565
6833c043
MC		 1566static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1567{
1568 u32 reg;
1569
ecf1410b
MC		 1570 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1571 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1572 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1573 return;
1574
7f97a4bd
MC		 1575 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1576 tg3_phy_fet_toggle_apd(tp, enable);
1577 return;
1578 }
1579
6833c043
MC		 1580 reg = MII_TG3_MISC_SHDW_WREN |
1581 MII_TG3_MISC_SHDW_SCR5_SEL |
1582 MII_TG3_MISC_SHDW_SCR5_LPED |
1583 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1584 MII_TG3_MISC_SHDW_SCR5_SDTL |
1585 MII_TG3_MISC_SHDW_SCR5_C125OE;
1586 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1587 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1588
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590
1591
1592 reg = MII_TG3_MISC_SHDW_WREN |
1593 MII_TG3_MISC_SHDW_APD_SEL |
1594 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1595 if (enable)
1596 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1597
1598 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1599}
1600
9ef8ca99
MC		 1601static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1602{
1603 u32 phy;
1604
1605 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1606 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1607 return;
1608
7f97a4bd 1609 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1610 u32 ephy;
1611
535ef6e1
MC		 1612 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1613 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1614
1615 tg3_writephy(tp, MII_TG3_FET_TEST,
1616 ephy | MII_TG3_FET_SHADOW_EN);
1617 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1618 if (enable)
535ef6e1 1619 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1620 else
535ef6e1
MC		 1621 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1622 tg3_writephy(tp, reg, phy);
9ef8ca99 1623 }
535ef6e1 1624 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1625 }
1626 } else {
1627 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1628 MII_TG3_AUXCTL_SHDWSEL_MISC;
1629 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1630 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1631 if (enable)
1632 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1633 else
1634 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1635 phy |= MII_TG3_AUXCTL_MISC_WREN;
1636 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1637 }
1638 }
1639}
1640
1da177e4
LT		 1641static void tg3_phy_set_wirespeed(struct tg3 *tp)
1642{
1643 u32 val;
1644
1645 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1646 return;
1647
1648 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1649 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1650 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1651 (val | (1 << 15) | (1 << 4)));
1652}
1653
b2a5c19c
MC		 1654static void tg3_phy_apply_otp(struct tg3 *tp)
1655{
1656 u32 otp, phy;
1657
1658 if (!tp->phy_otp)
1659 return;
1660
1661 otp = tp->phy_otp;
1662
1663 /* Enable SM_DSP clock and tx 6dB coding. */
1664 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1665 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1666 MII_TG3_AUXCTL_ACTL_TX_6DB;
1667 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1668
1669 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1670 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1671 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1672
1673 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1674 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1675 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1676
1677 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1678 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1680
1681 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1683
1684 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1685 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1686
1687 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1688 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1690
1691 /* Turn off SM_DSP clock. */
1692 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1693 MII_TG3_AUXCTL_ACTL_TX_6DB;
1694 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1695}
1696
1da177e4
LT		 1697static int tg3_wait_macro_done(struct tg3 *tp)
1698{
1699 int limit = 100;
1700
1701 while (limit--) {
1702 u32 tmp32;
1703
1704 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1705 if ((tmp32 & 0x1000) == 0)
1706 break;
1707 }
1708 }
d4675b52 1709 if (limit < 0)
1da177e4
LT		 1710 return -EBUSY;
1711
1712 return 0;
1713}
1714
1715static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1716{
1717 static const u32 test_pat[4][6] = {
1718 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1719 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1720 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1721 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1722 };
1723 int chan;
1724
1725 for (chan = 0; chan < 4; chan++) {
1726 int i;
1727
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731
1732 for (i = 0; i < 6; i++)
1733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1734 test_pat[chan][i]);
1735
1736 tg3_writephy(tp, 0x16, 0x0202);
1737 if (tg3_wait_macro_done(tp)) {
1738 *resetp = 1;
1739 return -EBUSY;
1740 }
1741
1742 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1743 (chan * 0x2000) | 0x0200);
1744 tg3_writephy(tp, 0x16, 0x0082);
1745 if (tg3_wait_macro_done(tp)) {
1746 *resetp = 1;
1747 return -EBUSY;
1748 }
1749
1750 tg3_writephy(tp, 0x16, 0x0802);
1751 if (tg3_wait_macro_done(tp)) {
1752 *resetp = 1;
1753 return -EBUSY;
1754 }
1755
1756 for (i = 0; i < 6; i += 2) {
1757 u32 low, high;
1758
1759 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1760 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1761 tg3_wait_macro_done(tp)) {
1762 *resetp = 1;
1763 return -EBUSY;
1764 }
1765 low &= 0x7fff;
1766 high &= 0x000f;
1767 if (low != test_pat[chan][i] ||
1768 high != test_pat[chan][i+1]) {
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1770 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1771 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1772
1773 return -EBUSY;
1774 }
1775 }
1776 }
1777
1778 return 0;
1779}
1780
1781static int tg3_phy_reset_chanpat(struct tg3 *tp)
1782{
1783 int chan;
1784
1785 for (chan = 0; chan < 4; chan++) {
1786 int i;
1787
1788 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1789 (chan * 0x2000) | 0x0200);
1790 tg3_writephy(tp, 0x16, 0x0002);
1791 for (i = 0; i < 6; i++)
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1793 tg3_writephy(tp, 0x16, 0x0202);
1794 if (tg3_wait_macro_done(tp))
1795 return -EBUSY;
1796 }
1797
1798 return 0;
1799}
1800
1801static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1802{
1803 u32 reg32, phy9_orig;
1804 int retries, do_phy_reset, err;
1805
1806 retries = 10;
1807 do_phy_reset = 1;
1808 do {
1809 if (do_phy_reset) {
1810 err = tg3_bmcr_reset(tp);
1811 if (err)
1812 return err;
1813 do_phy_reset = 0;
1814 }
1815
1816 /* Disable transmitter and interrupt. */
1817 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1818 continue;
1819
1820 reg32 |= 0x3000;
1821 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1822
1823 /* Set full-duplex, 1000 mbps. */
1824 tg3_writephy(tp, MII_BMCR,
1825 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1826
1827 /* Set to master mode. */
1828 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1829 continue;
1830
1831 tg3_writephy(tp, MII_TG3_CTRL,
1832 (MII_TG3_CTRL_AS_MASTER |
1833 MII_TG3_CTRL_ENABLE_AS_MASTER));
1834
1835 /* Enable SM_DSP_CLOCK and 6dB. */
1836 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1837
1838 /* Block the PHY control access. */
1839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1841
1842 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1843 if (!err)
1844 break;
1845 } while (--retries);
1846
1847 err = tg3_phy_reset_chanpat(tp);
1848 if (err)
1849 return err;
1850
1851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1852 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1853
1854 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1855 tg3_writephy(tp, 0x16, 0x0000);
1856
1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1859 /* Set Extended packet length bit for jumbo frames */
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
859a5887 1861 } else {
1da177e4
LT		 1862 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1863 }
1864
1865 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1866
1867 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1868 reg32 &= ~0x3000;
1869 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1870 } else if (!err)
1871 err = -EBUSY;
1872
1873 return err;
1874}
1875
1876/* This will reset the tigon3 PHY if there is no valid
1877 * link unless the FORCE argument is non-zero.
1878 */
1879static int tg3_phy_reset(struct tg3 *tp)
1880{
b2a5c19c 1881 u32 cpmuctrl;
1da177e4
LT		 1882 u32 phy_status;
1883 int err;
1884
60189ddf
MC		 1885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1886 u32 val;
1887
1888 val = tr32(GRC_MISC_CFG);
1889 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1890 udelay(40);
1891 }
1da177e4
LT		 1892 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1893 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1894 if (err != 0)
1895 return -EBUSY;
1896
c8e1e82b
MC		 1897 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1898 netif_carrier_off(tp->dev);
1899 tg3_link_report(tp);
1900 }
1901
1da177e4
LT		 1902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1905 err = tg3_phy_reset_5703_4_5(tp);
1906 if (err)
1907 return err;
1908 goto out;
1909 }
1910
b2a5c19c
MC		 1911 cpmuctrl = 0;
1912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1913 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1914 cpmuctrl = tr32(TG3_CPMU_CTRL);
1915 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1916 tw32(TG3_CPMU_CTRL,
1917 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1918 }
1919
1da177e4
LT		 1920 err = tg3_bmcr_reset(tp);
1921 if (err)
1922 return err;
1923
b2a5c19c
MC		 1924 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1925 u32 phy;
1926
1927 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1928 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1929
1930 tw32(TG3_CPMU_CTRL, cpmuctrl);
1931 }
1932
bcb37f6c
MC		 1933 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1934 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1935 u32 val;
1936
1937 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1938 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1939 CPMU_LSPD_1000MB_MACCLK_12_5) {
1940 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1941 udelay(40);
1942 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1943 }
1944 }
1945
ecf1410b
MC		 1946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1947 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1948 return 0;
1949
b2a5c19c
MC		 1950 tg3_phy_apply_otp(tp);
1951
6833c043
MC		 1952 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1953 tg3_phy_toggle_apd(tp, true);
1954 else
1955 tg3_phy_toggle_apd(tp, false);
1956
1da177e4
LT		 1957out:
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1965 }
1966 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1967 tg3_writephy(tp, 0x1c, 0x8d68);
1968 tg3_writephy(tp, 0x1c, 0x8d68);
1969 }
1970 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1975 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1977 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1978 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
859a5887 1979 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
c424cb24
MC		 1980 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1982 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1983 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1984 tg3_writephy(tp, MII_TG3_TEST1,
1985 MII_TG3_TEST1_TRIM_EN | 0x4);
1986 } else
1987 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1988 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1989 }
1da177e4
LT		 1990 /* Set Extended packet length bit (bit 14) on all chips that */
1991 /* support jumbo frames */
79eb6904 1992 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 1993 /* Cannot do read-modify-write on 5401 */
1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1995 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1996 u32 phy_reg;
1997
1998 /* Set bit 14 with read-modify-write to preserve other bits */
1999 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2000 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2001 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2002 }
2003
2004 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2005 * jumbo frames transmission.
2006 */
8f666b07 2007 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2008 u32 phy_reg;
2009
2010 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
c6cdf436
MC		 2011 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2012 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2013 }
2014
715116a1 2015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2016 /* adjust output voltage */
535ef6e1 2017 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2018 }
2019
9ef8ca99 2020 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2021 tg3_phy_set_wirespeed(tp);
2022 return 0;
2023}
2024
2025static void tg3_frob_aux_power(struct tg3 *tp)
2026{
2027 struct tg3 *tp_peer = tp;
2028
334355aa
MC		 2029 /* The GPIOs do something completely different on 57765. */
2030 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2032 return;
2033
f6eb9b1f
MC		 2034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2037 struct net_device *dev_peer;
2038
2039 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2040 /* remove_one() may have been run on the peer. */
8c2dc7e1 2041 if (!dev_peer)
bc1c7567
MC		 2042 tp_peer = tp;
2043 else
2044 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2045 }
2046
1da177e4 2047 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2048 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2049 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2050 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2053 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2054 (GRC_LCLCTRL_GPIO_OE0 |
2055 GRC_LCLCTRL_GPIO_OE1 |
2056 GRC_LCLCTRL_GPIO_OE2 |
2057 GRC_LCLCTRL_GPIO_OUTPUT0 |
2058 GRC_LCLCTRL_GPIO_OUTPUT1),
2059 100);
8d519ab2
MC		 2060 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2061 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2062 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2063 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2064 GRC_LCLCTRL_GPIO_OE1 |
2065 GRC_LCLCTRL_GPIO_OE2 |
2066 GRC_LCLCTRL_GPIO_OUTPUT0 |
2067 GRC_LCLCTRL_GPIO_OUTPUT1 |
2068 tp->grc_local_ctrl;
2069 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2070
2071 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2072 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2073
2074 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2075 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2076 } else {
2077 u32 no_gpio2;
dc56b7d4 2078 u32 grc_local_ctrl = 0;
1da177e4
LT		 2079
2080 if (tp_peer != tp &&
2081 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2082 return;
2083
dc56b7d4
MC		 2084 /* Workaround to prevent overdrawing Amps. */
2085 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2086 ASIC_REV_5714) {
2087 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2088 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089 grc_local_ctrl, 100);
dc56b7d4
MC		 2090 }
2091
1da177e4
LT		 2092 /* On 5753 and variants, GPIO2 cannot be used. */
2093 no_gpio2 = tp->nic_sram_data_cfg &
2094 NIC_SRAM_DATA_CFG_NO_GPIO2;
2095
dc56b7d4 2096 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2097 GRC_LCLCTRL_GPIO_OE1 |
2098 GRC_LCLCTRL_GPIO_OE2 |
2099 GRC_LCLCTRL_GPIO_OUTPUT1 |
2100 GRC_LCLCTRL_GPIO_OUTPUT2;
2101 if (no_gpio2) {
2102 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2103 GRC_LCLCTRL_GPIO_OUTPUT2);
2104 }
b401e9e2
MC		 2105 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2106 grc_local_ctrl, 100);
1da177e4
LT		 2107
2108 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2109
b401e9e2
MC		 2110 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111 grc_local_ctrl, 100);
1da177e4
LT		 2112
2113 if (!no_gpio2) {
2114 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116 grc_local_ctrl, 100);
1da177e4
LT		 2117 }
2118 }
2119 } else {
2120 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2121 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2122 if (tp_peer != tp &&
2123 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2124 return;
2125
b401e9e2
MC		 2126 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127 (GRC_LCLCTRL_GPIO_OE1 |
2128 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2129
b401e9e2
MC		 2130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2132
b401e9e2
MC		 2133 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2134 (GRC_LCLCTRL_GPIO_OE1 |
2135 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2136 }
2137 }
2138}
2139
e8f3f6ca
MC		 2140static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2141{
2142 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2143 return 1;
79eb6904 2144 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 2145 if (speed != SPEED_10)
2146 return 1;
2147 } else if (speed == SPEED_10)
2148 return 1;
2149
2150 return 0;
2151}
2152
1da177e4
LT		 2153static int tg3_setup_phy(struct tg3 *, int);
2154
2155#define RESET_KIND_SHUTDOWN 0
2156#define RESET_KIND_INIT 1
2157#define RESET_KIND_SUSPEND 2
2158
2159static void tg3_write_sig_post_reset(struct tg3 *, int);
2160static int tg3_halt_cpu(struct tg3 *, u32);
2161
0a459aac 2162static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2163{
ce057f01
MC		 2164 u32 val;
2165
5129724a
MC		 2166 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2168 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2169 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2170
2171 sg_dig_ctrl |=
2172 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2173 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2174 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2175 }
3f7045c1 2176 return;
5129724a 2177 }
3f7045c1 2178
60189ddf 2179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2180 tg3_bmcr_reset(tp);
2181 val = tr32(GRC_MISC_CFG);
2182 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2183 udelay(40);
2184 return;
0e5f784c
MC		 2185 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2186 u32 phytest;
2187 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2188 u32 phy;
2189
2190 tg3_writephy(tp, MII_ADVERTISE, 0);
2191 tg3_writephy(tp, MII_BMCR,
2192 BMCR_ANENABLE | BMCR_ANRESTART);
2193
2194 tg3_writephy(tp, MII_TG3_FET_TEST,
2195 phytest | MII_TG3_FET_SHADOW_EN);
2196 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2197 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2198 tg3_writephy(tp,
2199 MII_TG3_FET_SHDW_AUXMODE4,
2200 phy);
2201 }
2202 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2203 }
2204 return;
0a459aac 2205 } else if (do_low_power) {
715116a1
MC		 2206 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2207 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2208
2209 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2210 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2211 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2212 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2213 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2214 }
3f7045c1 2215
15c3b696
MC		 2216 /* The PHY should not be powered down on some chips because
2217 * of bugs.
2218 */
2219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2222 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2223 return;
ce057f01 2224
bcb37f6c
MC		 2225 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2226 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2227 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2228 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2229 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2230 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2231 }
2232
15c3b696
MC		 2233 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2234}
2235
ffbcfed4
MC		 2236/* tp->lock is held. */
2237static int tg3_nvram_lock(struct tg3 *tp)
2238{
2239 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2240 int i;
2241
2242 if (tp->nvram_lock_cnt == 0) {
2243 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2244 for (i = 0; i < 8000; i++) {
2245 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2246 break;
2247 udelay(20);
2248 }
2249 if (i == 8000) {
2250 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2251 return -ENODEV;
2252 }
2253 }
2254 tp->nvram_lock_cnt++;
2255 }
2256 return 0;
2257}
2258
2259/* tp->lock is held. */
2260static void tg3_nvram_unlock(struct tg3 *tp)
2261{
2262 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2263 if (tp->nvram_lock_cnt > 0)
2264 tp->nvram_lock_cnt--;
2265 if (tp->nvram_lock_cnt == 0)
2266 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2267 }
2268}
2269
2270/* tp->lock is held. */
2271static void tg3_enable_nvram_access(struct tg3 *tp)
2272{
2273 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2274 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2275 u32 nvaccess = tr32(NVRAM_ACCESS);
2276
2277 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2278 }
2279}
2280
2281/* tp->lock is held. */
2282static void tg3_disable_nvram_access(struct tg3 *tp)
2283{
2284 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2285 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2286 u32 nvaccess = tr32(NVRAM_ACCESS);
2287
2288 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2289 }
2290}
2291
2292static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2293 u32 offset, u32 *val)
2294{
2295 u32 tmp;
2296 int i;
2297
2298 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2299 return -EINVAL;
2300
2301 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2302 EEPROM_ADDR_DEVID_MASK |
2303 EEPROM_ADDR_READ);
2304 tw32(GRC_EEPROM_ADDR,
2305 tmp |
2306 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2307 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2308 EEPROM_ADDR_ADDR_MASK) |
2309 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2310
2311 for (i = 0; i < 1000; i++) {
2312 tmp = tr32(GRC_EEPROM_ADDR);
2313
2314 if (tmp & EEPROM_ADDR_COMPLETE)
2315 break;
2316 msleep(1);
2317 }
2318 if (!(tmp & EEPROM_ADDR_COMPLETE))
2319 return -EBUSY;
2320
62cedd11
MC		 2321 tmp = tr32(GRC_EEPROM_DATA);
2322
2323 /*
2324 * The data will always be opposite the native endian
2325 * format. Perform a blind byteswap to compensate.
2326 */
2327 *val = swab32(tmp);
2328
ffbcfed4
MC		 2329 return 0;
2330}
2331
2332#define NVRAM_CMD_TIMEOUT 10000
2333
2334static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2335{
2336 int i;
2337
2338 tw32(NVRAM_CMD, nvram_cmd);
2339 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2340 udelay(10);
2341 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2342 udelay(10);
2343 break;
2344 }
2345 }
2346
2347 if (i == NVRAM_CMD_TIMEOUT)
2348 return -EBUSY;
2349
2350 return 0;
2351}
2352
2353static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2354{
2355 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2356 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2357 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2358 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2359 (tp->nvram_jedecnum == JEDEC_ATMEL))
2360
2361 addr = ((addr / tp->nvram_pagesize) <<
2362 ATMEL_AT45DB0X1B_PAGE_POS) +
2363 (addr % tp->nvram_pagesize);
2364
2365 return addr;
2366}
2367
2368static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2369{
2370 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2371 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2372 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2373 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2374 (tp->nvram_jedecnum == JEDEC_ATMEL))
2375
2376 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2377 tp->nvram_pagesize) +
2378 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2379
2380 return addr;
2381}
2382
e4f34110
MC		 2383/* NOTE: Data read in from NVRAM is byteswapped according to
2384 * the byteswapping settings for all other register accesses.
2385 * tg3 devices are BE devices, so on a BE machine, the data
2386 * returned will be exactly as it is seen in NVRAM. On a LE
2387 * machine, the 32-bit value will be byteswapped.
2388 */
ffbcfed4
MC		 2389static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2390{
2391 int ret;
2392
2393 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2394 return tg3_nvram_read_using_eeprom(tp, offset, val);
2395
2396 offset = tg3_nvram_phys_addr(tp, offset);
2397
2398 if (offset > NVRAM_ADDR_MSK)
2399 return -EINVAL;
2400
2401 ret = tg3_nvram_lock(tp);
2402 if (ret)
2403 return ret;
2404
2405 tg3_enable_nvram_access(tp);
2406
2407 tw32(NVRAM_ADDR, offset);
2408 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2409 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2410
2411 if (ret == 0)
e4f34110 2412 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2413
2414 tg3_disable_nvram_access(tp);
2415
2416 tg3_nvram_unlock(tp);
2417
2418 return ret;
2419}
2420
a9dc529d
MC		 2421/* Ensures NVRAM data is in bytestream format. */
2422static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2423{
2424 u32 v;
a9dc529d 2425 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2426 if (!res)
a9dc529d 2427 *val = cpu_to_be32(v);
ffbcfed4
MC		 2428 return res;
2429}
2430
3f007891
MC		 2431/* tp->lock is held. */
2432static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2433{
2434 u32 addr_high, addr_low;
2435 int i;
2436
2437 addr_high = ((tp->dev->dev_addr[0] << 8) |
2438 tp->dev->dev_addr[1]);
2439 addr_low = ((tp->dev->dev_addr[2] << 24) |
2440 (tp->dev->dev_addr[3] << 16) |
2441 (tp->dev->dev_addr[4] << 8) |
2442 (tp->dev->dev_addr[5] << 0));
2443 for (i = 0; i < 4; i++) {
2444 if (i == 1 && skip_mac_1)
2445 continue;
2446 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2447 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2448 }
2449
2450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2452 for (i = 0; i < 12; i++) {
2453 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2454 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2455 }
2456 }
2457
2458 addr_high = (tp->dev->dev_addr[0] +
2459 tp->dev->dev_addr[1] +
2460 tp->dev->dev_addr[2] +
2461 tp->dev->dev_addr[3] +
2462 tp->dev->dev_addr[4] +
2463 tp->dev->dev_addr[5]) &
2464 TX_BACKOFF_SEED_MASK;
2465 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2466}
2467
bc1c7567 2468static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2469{
2470 u32 misc_host_ctrl;
0a459aac 2471 bool device_should_wake, do_low_power;
1da177e4
LT		 2472
2473 /* Make sure register accesses (indirect or otherwise)
2474 * will function correctly.
2475 */
2476 pci_write_config_dword(tp->pdev,
2477 TG3PCI_MISC_HOST_CTRL,
2478 tp->misc_host_ctrl);
2479
1da177e4 2480 switch (state) {
bc1c7567 2481 case PCI_D0:
12dac075
RW		 2482 pci_enable_wake(tp->pdev, state, false);
2483 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2484
9d26e213
MC		 2485 /* Switch out of Vaux if it is a NIC */
2486 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2487 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2488
2489 return 0;
2490
bc1c7567 2491 case PCI_D1:
bc1c7567 2492 case PCI_D2:
bc1c7567 2493 case PCI_D3hot:
1da177e4
LT		 2494 break;
2495
2496 default:
05dbe005
JP		 2497 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2498 state);
1da177e4 2499 return -EINVAL;
855e1111 2500 }
5e7dfd0f
MC		 2501
2502 /* Restore the CLKREQ setting. */
2503 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2504 u16 lnkctl;
2505
2506 pci_read_config_word(tp->pdev,
2507 tp->pcie_cap + PCI_EXP_LNKCTL,
2508 &lnkctl);
2509 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2510 pci_write_config_word(tp->pdev,
2511 tp->pcie_cap + PCI_EXP_LNKCTL,
2512 lnkctl);
2513 }
2514
1da177e4
LT		 2515 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2516 tw32(TG3PCI_MISC_HOST_CTRL,
2517 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2518
05ac4cb7
MC		 2519 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2520 device_may_wakeup(&tp->pdev->dev) &&
2521 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2522
dd477003 2523 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2524 do_low_power = false;
b02fd9e3
MC		 2525 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2526 !tp->link_config.phy_is_low_power) {
2527 struct phy_device *phydev;
0a459aac 2528 u32 phyid, advertising;
b02fd9e3 2529
3f0e3ad7 2530 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2531
2532 tp->link_config.phy_is_low_power = 1;
2533
2534 tp->link_config.orig_speed = phydev->speed;
2535 tp->link_config.orig_duplex = phydev->duplex;
2536 tp->link_config.orig_autoneg = phydev->autoneg;
2537 tp->link_config.orig_advertising = phydev->advertising;
2538
2539 advertising = ADVERTISED_TP |
2540 ADVERTISED_Pause |
2541 ADVERTISED_Autoneg |
2542 ADVERTISED_10baseT_Half;
2543
2544 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2545 device_should_wake) {
b02fd9e3
MC		 2546 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2547 advertising |=
2548 ADVERTISED_100baseT_Half |
2549 ADVERTISED_100baseT_Full |
2550 ADVERTISED_10baseT_Full;
2551 else
2552 advertising |= ADVERTISED_10baseT_Full;
2553 }
2554
2555 phydev->advertising = advertising;
2556
2557 phy_start_aneg(phydev);
0a459aac
MC		 2558
2559 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 2560 if (phyid != PHY_ID_BCMAC131) {
2561 phyid &= PHY_BCM_OUI_MASK;
2562 if (phyid == PHY_BCM_OUI_1 ||
2563 phyid == PHY_BCM_OUI_2 ||
2564 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 2565 do_low_power = true;
2566 }
b02fd9e3 2567 }
dd477003 2568 } else {
2023276e 2569 do_low_power = true;
0a459aac 2570
dd477003
MC		 2571 if (tp->link_config.phy_is_low_power == 0) {
2572 tp->link_config.phy_is_low_power = 1;
2573 tp->link_config.orig_speed = tp->link_config.speed;
2574 tp->link_config.orig_duplex = tp->link_config.duplex;
2575 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2576 }
1da177e4 2577
dd477003
MC		 2578 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2579 tp->link_config.speed = SPEED_10;
2580 tp->link_config.duplex = DUPLEX_HALF;
2581 tp->link_config.autoneg = AUTONEG_ENABLE;
2582 tg3_setup_phy(tp, 0);
2583 }
1da177e4
LT		 2584 }
2585
b5d3772c
MC		 2586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2587 u32 val;
2588
2589 val = tr32(GRC_VCPU_EXT_CTRL);
2590 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2591 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2592 int i;
2593 u32 val;
2594
2595 for (i = 0; i < 200; i++) {
2596 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2597 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2598 break;
2599 msleep(1);
2600 }
2601 }
a85feb8c
GZ		 2602 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2603 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2604 WOL_DRV_STATE_SHUTDOWN |
2605 WOL_DRV_WOL |
2606 WOL_SET_MAGIC_PKT);
6921d201 2607
05ac4cb7 2608 if (device_should_wake) {
1da177e4
LT		 2609 u32 mac_mode;
2610
2611 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2612 if (do_low_power) {
dd477003
MC		 2613 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2614 udelay(40);
2615 }
1da177e4 2616
3f7045c1
MC		 2617 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2618 mac_mode = MAC_MODE_PORT_MODE_GMII;
2619 else
2620 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2621
e8f3f6ca
MC		 2622 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2623 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2624 ASIC_REV_5700) {
2625 u32 speed = (tp->tg3_flags &
2626 TG3_FLAG_WOL_SPEED_100MB) ?
2627 SPEED_100 : SPEED_10;
2628 if (tg3_5700_link_polarity(tp, speed))
2629 mac_mode |= MAC_MODE_LINK_POLARITY;
2630 else
2631 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2632 }
1da177e4
LT		 2633 } else {
2634 mac_mode = MAC_MODE_PORT_MODE_TBI;
2635 }
2636
cbf46853 2637 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2638 tw32(MAC_LED_CTRL, tp->led_ctrl);
2639
05ac4cb7
MC		 2640 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2641 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2642 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2643 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2644 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2645 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2646
3bda1258
MC		 2647 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2648 mac_mode |= tp->mac_mode &
2649 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2650 if (mac_mode & MAC_MODE_APE_TX_EN)
2651 mac_mode |= MAC_MODE_TDE_ENABLE;
2652 }
2653
1da177e4
LT		 2654 tw32_f(MAC_MODE, mac_mode);
2655 udelay(100);
2656
2657 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2658 udelay(10);
2659 }
2660
2661 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2662 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2663 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2664 u32 base_val;
2665
2666 base_val = tp->pci_clock_ctrl;
2667 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2668 CLOCK_CTRL_TXCLK_DISABLE);
2669
b401e9e2
MC		 2670 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2671 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2672 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2673 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2674 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2675 /* do nothing */
85e94ced 2676 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2677 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2678 u32 newbits1, newbits2;
2679
2680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2682 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2683 CLOCK_CTRL_TXCLK_DISABLE |
2684 CLOCK_CTRL_ALTCLK);
2685 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2686 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2687 newbits1 = CLOCK_CTRL_625_CORE;
2688 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2689 } else {
2690 newbits1 = CLOCK_CTRL_ALTCLK;
2691 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2692 }
2693
b401e9e2
MC		 2694 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2695 40);
1da177e4 2696
b401e9e2
MC		 2697 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2698 40);
1da177e4
LT		 2699
2700 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2701 u32 newbits3;
2702
2703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2705 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2706 CLOCK_CTRL_TXCLK_DISABLE |
2707 CLOCK_CTRL_44MHZ_CORE);
2708 } else {
2709 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2710 }
2711
b401e9e2
MC		 2712 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2713 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2714 }
2715 }
2716
05ac4cb7 2717 if (!(device_should_wake) &&
22435849 2718 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2719 tg3_power_down_phy(tp, do_low_power);
6921d201 2720
1da177e4
LT		 2721 tg3_frob_aux_power(tp);
2722
2723 /* Workaround for unstable PLL clock */
2724 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2725 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2726 u32 val = tr32(0x7d00);
2727
2728 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2729 tw32(0x7d00, val);
6921d201 2730 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2731 int err;
2732
2733 err = tg3_nvram_lock(tp);
1da177e4 2734 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2735 if (!err)
2736 tg3_nvram_unlock(tp);
6921d201 2737 }
1da177e4
LT		 2738 }
2739
bbadf503
MC		 2740 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2741
05ac4cb7 2742 if (device_should_wake)
12dac075
RW		 2743 pci_enable_wake(tp->pdev, state, true);
2744
1da177e4 2745 /* Finally, set the new power state. */
12dac075 2746 pci_set_power_state(tp->pdev, state);
1da177e4 2747
1da177e4
LT		 2748 return 0;
2749}
2750
1da177e4
LT		 2751static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2752{
2753 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2754 case MII_TG3_AUX_STAT_10HALF:
2755 *speed = SPEED_10;
2756 *duplex = DUPLEX_HALF;
2757 break;
2758
2759 case MII_TG3_AUX_STAT_10FULL:
2760 *speed = SPEED_10;
2761 *duplex = DUPLEX_FULL;
2762 break;
2763
2764 case MII_TG3_AUX_STAT_100HALF:
2765 *speed = SPEED_100;
2766 *duplex = DUPLEX_HALF;
2767 break;
2768
2769 case MII_TG3_AUX_STAT_100FULL:
2770 *speed = SPEED_100;
2771 *duplex = DUPLEX_FULL;
2772 break;
2773
2774 case MII_TG3_AUX_STAT_1000HALF:
2775 *speed = SPEED_1000;
2776 *duplex = DUPLEX_HALF;
2777 break;
2778
2779 case MII_TG3_AUX_STAT_1000FULL:
2780 *speed = SPEED_1000;
2781 *duplex = DUPLEX_FULL;
2782 break;
2783
2784 default:
7f97a4bd 2785 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2786 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2787 SPEED_10;
2788 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2789 DUPLEX_HALF;
2790 break;
2791 }
1da177e4
LT		 2792 *speed = SPEED_INVALID;
2793 *duplex = DUPLEX_INVALID;
2794 break;
855e1111 2795 }
1da177e4
LT		 2796}
2797
2798static void tg3_phy_copper_begin(struct tg3 *tp)
2799{
2800 u32 new_adv;
2801 int i;
2802
2803 if (tp->link_config.phy_is_low_power) {
2804 /* Entering low power mode. Disable gigabit and
2805 * 100baseT advertisements.
2806 */
2807 tg3_writephy(tp, MII_TG3_CTRL, 0);
2808
2809 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2810 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2811 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2812 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2813
2814 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2815 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2816 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2817 tp->link_config.advertising &=
2818 ~(ADVERTISED_1000baseT_Half |
2819 ADVERTISED_1000baseT_Full);
2820
ba4d07a8 2821 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2822 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2823 new_adv |= ADVERTISE_10HALF;
2824 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2825 new_adv |= ADVERTISE_10FULL;
2826 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2827 new_adv |= ADVERTISE_100HALF;
2828 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2829 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2830
2831 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2832
1da177e4
LT		 2833 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2834
2835 if (tp->link_config.advertising &
2836 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2837 new_adv = 0;
2838 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2839 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2840 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2841 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2842 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2843 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2844 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2845 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2846 MII_TG3_CTRL_ENABLE_AS_MASTER);
2847 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2848 } else {
2849 tg3_writephy(tp, MII_TG3_CTRL, 0);
2850 }
2851 } else {
ba4d07a8
MC		 2852 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2853 new_adv |= ADVERTISE_CSMA;
2854
1da177e4
LT		 2855 /* Asking for a specific link mode. */
2856 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2857 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2858
2859 if (tp->link_config.duplex == DUPLEX_FULL)
2860 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2861 else
2862 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2863 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2864 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2865 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2866 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2867 } else {
1da177e4
LT		 2868 if (tp->link_config.speed == SPEED_100) {
2869 if (tp->link_config.duplex == DUPLEX_FULL)
2870 new_adv |= ADVERTISE_100FULL;
2871 else
2872 new_adv |= ADVERTISE_100HALF;
2873 } else {
2874 if (tp->link_config.duplex == DUPLEX_FULL)
2875 new_adv |= ADVERTISE_10FULL;
2876 else
2877 new_adv |= ADVERTISE_10HALF;
2878 }
2879 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2880
2881 new_adv = 0;
1da177e4 2882 }
ba4d07a8
MC		 2883
2884 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2885 }
2886
2887 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2888 tp->link_config.speed != SPEED_INVALID) {
2889 u32 bmcr, orig_bmcr;
2890
2891 tp->link_config.active_speed = tp->link_config.speed;
2892 tp->link_config.active_duplex = tp->link_config.duplex;
2893
2894 bmcr = 0;
2895 switch (tp->link_config.speed) {
2896 default:
2897 case SPEED_10:
2898 break;
2899
2900 case SPEED_100:
2901 bmcr |= BMCR_SPEED100;
2902 break;
2903
2904 case SPEED_1000:
2905 bmcr |= TG3_BMCR_SPEED1000;
2906 break;
855e1111 2907 }
1da177e4
LT		 2908
2909 if (tp->link_config.duplex == DUPLEX_FULL)
2910 bmcr |= BMCR_FULLDPLX;
2911
2912 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2913 (bmcr != orig_bmcr)) {
2914 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2915 for (i = 0; i < 1500; i++) {
2916 u32 tmp;
2917
2918 udelay(10);
2919 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2920 tg3_readphy(tp, MII_BMSR, &tmp))
2921 continue;
2922 if (!(tmp & BMSR_LSTATUS)) {
2923 udelay(40);
2924 break;
2925 }
2926 }
2927 tg3_writephy(tp, MII_BMCR, bmcr);
2928 udelay(40);
2929 }
2930 } else {
2931 tg3_writephy(tp, MII_BMCR,
2932 BMCR_ANENABLE | BMCR_ANRESTART);
2933 }
2934}
2935
2936static int tg3_init_5401phy_dsp(struct tg3 *tp)
2937{
2938 int err;
2939
2940 /* Turn off tap power management. */
2941 /* Set Extended packet length bit */
2942 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2943
2944 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2945 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2946
2947 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2948 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2949
2950 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2951 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2952
2953 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2954 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2955
2956 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2957 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2958
2959 udelay(40);
2960
2961 return err;
2962}
2963
3600d918 2964static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2965{
3600d918
MC		 2966 u32 adv_reg, all_mask = 0;
2967
2968 if (mask & ADVERTISED_10baseT_Half)
2969 all_mask |= ADVERTISE_10HALF;
2970 if (mask & ADVERTISED_10baseT_Full)
2971 all_mask |= ADVERTISE_10FULL;
2972 if (mask & ADVERTISED_100baseT_Half)
2973 all_mask |= ADVERTISE_100HALF;
2974 if (mask & ADVERTISED_100baseT_Full)
2975 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2976
2977 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2978 return 0;
2979
1da177e4
LT		 2980 if ((adv_reg & all_mask) != all_mask)
2981 return 0;
2982 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2983 u32 tg3_ctrl;
2984
3600d918
MC		 2985 all_mask = 0;
2986 if (mask & ADVERTISED_1000baseT_Half)
2987 all_mask |= ADVERTISE_1000HALF;
2988 if (mask & ADVERTISED_1000baseT_Full)
2989 all_mask |= ADVERTISE_1000FULL;
2990
1da177e4
LT		 2991 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2992 return 0;
2993
1da177e4
LT		 2994 if ((tg3_ctrl & all_mask) != all_mask)
2995 return 0;
2996 }
2997 return 1;
2998}
2999
ef167e27
MC		 3000static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3001{
3002 u32 curadv, reqadv;
3003
3004 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3005 return 1;
3006
3007 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3008 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3009
3010 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3011 if (curadv != reqadv)
3012 return 0;
3013
3014 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3015 tg3_readphy(tp, MII_LPA, rmtadv);
3016 } else {
3017 /* Reprogram the advertisement register, even if it
3018 * does not affect the current link. If the link
3019 * gets renegotiated in the future, we can save an
3020 * additional renegotiation cycle by advertising
3021 * it correctly in the first place.
3022 */
3023 if (curadv != reqadv) {
3024 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3025 ADVERTISE_PAUSE_ASYM);
3026 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3027 }
3028 }
3029
3030 return 1;
3031}
3032
1da177e4
LT		 3033static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3034{
3035 int current_link_up;
3036 u32 bmsr, dummy;
ef167e27 3037 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3038 u16 current_speed;
3039 u8 current_duplex;
3040 int i, err;
3041
3042 tw32(MAC_EVENT, 0);
3043
3044 tw32_f(MAC_STATUS,
3045 (MAC_STATUS_SYNC_CHANGED |
3046 MAC_STATUS_CFG_CHANGED |
3047 MAC_STATUS_MI_COMPLETION |
3048 MAC_STATUS_LNKSTATE_CHANGED));
3049 udelay(40);
3050
8ef21428
MC		 3051 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3052 tw32_f(MAC_MI_MODE,
3053 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3054 udelay(80);
3055 }
1da177e4
LT		 3056
3057 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3058
3059 /* Some third-party PHYs need to be reset on link going
3060 * down.
3061 */
3062 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3065 netif_carrier_ok(tp->dev)) {
3066 tg3_readphy(tp, MII_BMSR, &bmsr);
3067 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068 !(bmsr & BMSR_LSTATUS))
3069 force_reset = 1;
3070 }
3071 if (force_reset)
3072 tg3_phy_reset(tp);
3073
79eb6904 3074 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 3075 tg3_readphy(tp, MII_BMSR, &bmsr);
3076 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3077 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3078 bmsr = 0;
3079
3080 if (!(bmsr & BMSR_LSTATUS)) {
3081 err = tg3_init_5401phy_dsp(tp);
3082 if (err)
3083 return err;
3084
3085 tg3_readphy(tp, MII_BMSR, &bmsr);
3086 for (i = 0; i < 1000; i++) {
3087 udelay(10);
3088 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3089 (bmsr & BMSR_LSTATUS)) {
3090 udelay(40);
3091 break;
3092 }
3093 }
3094
79eb6904
MC		 3095 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3096 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 3097 !(bmsr & BMSR_LSTATUS) &&
3098 tp->link_config.active_speed == SPEED_1000) {
3099 err = tg3_phy_reset(tp);
3100 if (!err)
3101 err = tg3_init_5401phy_dsp(tp);
3102 if (err)
3103 return err;
3104 }
3105 }
3106 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3107 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3108 /* 5701 {A0,B0} CRC bug workaround */
3109 tg3_writephy(tp, 0x15, 0x0a75);
3110 tg3_writephy(tp, 0x1c, 0x8c68);
3111 tg3_writephy(tp, 0x1c, 0x8d68);
3112 tg3_writephy(tp, 0x1c, 0x8c68);
3113 }
3114
3115 /* Clear pending interrupts... */
3116 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3117 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3118
3119 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3120 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3121 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3122 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3123
3124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3126 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3127 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3128 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3129 else
3130 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3131 }
3132
3133 current_link_up = 0;
3134 current_speed = SPEED_INVALID;
3135 current_duplex = DUPLEX_INVALID;
3136
3137 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3138 u32 val;
3139
3140 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3141 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3142 if (!(val & (1 << 10))) {
3143 val |= (1 << 10);
3144 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3145 goto relink;
3146 }
3147 }
3148
3149 bmsr = 0;
3150 for (i = 0; i < 100; i++) {
3151 tg3_readphy(tp, MII_BMSR, &bmsr);
3152 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3153 (bmsr & BMSR_LSTATUS))
3154 break;
3155 udelay(40);
3156 }
3157
3158 if (bmsr & BMSR_LSTATUS) {
3159 u32 aux_stat, bmcr;
3160
3161 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3162 for (i = 0; i < 2000; i++) {
3163 udelay(10);
3164 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3165 aux_stat)
3166 break;
3167 }
3168
3169 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3170 &current_speed,
3171 &current_duplex);
3172
3173 bmcr = 0;
3174 for (i = 0; i < 200; i++) {
3175 tg3_readphy(tp, MII_BMCR, &bmcr);
3176 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3177 continue;
3178 if (bmcr && bmcr != 0x7fff)
3179 break;
3180 udelay(10);
3181 }
3182
ef167e27
MC		 3183 lcl_adv = 0;
3184 rmt_adv = 0;
1da177e4 3185
ef167e27
MC		 3186 tp->link_config.active_speed = current_speed;
3187 tp->link_config.active_duplex = current_duplex;
3188
3189 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3190 if ((bmcr & BMCR_ANENABLE) &&
3191 tg3_copper_is_advertising_all(tp,
3192 tp->link_config.advertising)) {
3193 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3194 &rmt_adv))
3195 current_link_up = 1;
1da177e4
LT		 3196 }
3197 } else {
3198 if (!(bmcr & BMCR_ANENABLE) &&
3199 tp->link_config.speed == current_speed &&
ef167e27
MC		 3200 tp->link_config.duplex == current_duplex &&
3201 tp->link_config.flowctrl ==
3202 tp->link_config.active_flowctrl) {
1da177e4 3203 current_link_up = 1;
1da177e4
LT		 3204 }
3205 }
3206
ef167e27
MC		 3207 if (current_link_up == 1 &&
3208 tp->link_config.active_duplex == DUPLEX_FULL)
3209 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3210 }
3211
1da177e4 3212relink:
6921d201 3213 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3214 u32 tmp;
3215
3216 tg3_phy_copper_begin(tp);
3217
3218 tg3_readphy(tp, MII_BMSR, &tmp);
3219 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3220 (tmp & BMSR_LSTATUS))
3221 current_link_up = 1;
3222 }
3223
3224 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3225 if (current_link_up == 1) {
3226 if (tp->link_config.active_speed == SPEED_100 ||
3227 tp->link_config.active_speed == SPEED_10)
3228 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3229 else
3230 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3231 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3232 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3233 else
1da177e4
LT		 3234 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3235
3236 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3237 if (tp->link_config.active_duplex == DUPLEX_HALF)
3238 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3239
1da177e4 3240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3241 if (current_link_up == 1 &&
3242 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3243 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3244 else
3245 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3246 }
3247
3248 /* ??? Without this setting Netgear GA302T PHY does not
3249 * ??? send/receive packets...
3250 */
79eb6904 3251 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1da177e4
LT		 3252 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3253 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3254 tw32_f(MAC_MI_MODE, tp->mi_mode);
3255 udelay(80);
3256 }
3257
3258 tw32_f(MAC_MODE, tp->mac_mode);
3259 udelay(40);
3260
3261 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3262 /* Polled via timer. */
3263 tw32_f(MAC_EVENT, 0);
3264 } else {
3265 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3266 }
3267 udelay(40);
3268
3269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3270 current_link_up == 1 &&
3271 tp->link_config.active_speed == SPEED_1000 &&
3272 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3273 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3274 udelay(120);
3275 tw32_f(MAC_STATUS,
3276 (MAC_STATUS_SYNC_CHANGED |
3277 MAC_STATUS_CFG_CHANGED));
3278 udelay(40);
3279 tg3_write_mem(tp,
3280 NIC_SRAM_FIRMWARE_MBOX,
3281 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3282 }
3283
5e7dfd0f
MC		 3284 /* Prevent send BD corruption. */
3285 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3286 u16 oldlnkctl, newlnkctl;
3287
3288 pci_read_config_word(tp->pdev,
3289 tp->pcie_cap + PCI_EXP_LNKCTL,
3290 &oldlnkctl);
3291 if (tp->link_config.active_speed == SPEED_100 ||
3292 tp->link_config.active_speed == SPEED_10)
3293 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3294 else
3295 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3296 if (newlnkctl != oldlnkctl)
3297 pci_write_config_word(tp->pdev,
3298 tp->pcie_cap + PCI_EXP_LNKCTL,
3299 newlnkctl);
3300 }
3301
1da177e4
LT		 3302 if (current_link_up != netif_carrier_ok(tp->dev)) {
3303 if (current_link_up)
3304 netif_carrier_on(tp->dev);
3305 else
3306 netif_carrier_off(tp->dev);
3307 tg3_link_report(tp);
3308 }
3309
3310 return 0;
3311}
3312
3313struct tg3_fiber_aneginfo {
3314 int state;
3315#define ANEG_STATE_UNKNOWN 0
3316#define ANEG_STATE_AN_ENABLE 1
3317#define ANEG_STATE_RESTART_INIT 2
3318#define ANEG_STATE_RESTART 3
3319#define ANEG_STATE_DISABLE_LINK_OK 4
3320#define ANEG_STATE_ABILITY_DETECT_INIT 5
3321#define ANEG_STATE_ABILITY_DETECT 6
3322#define ANEG_STATE_ACK_DETECT_INIT 7
3323#define ANEG_STATE_ACK_DETECT 8
3324#define ANEG_STATE_COMPLETE_ACK_INIT 9
3325#define ANEG_STATE_COMPLETE_ACK 10
3326#define ANEG_STATE_IDLE_DETECT_INIT 11
3327#define ANEG_STATE_IDLE_DETECT 12
3328#define ANEG_STATE_LINK_OK 13
3329#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3330#define ANEG_STATE_NEXT_PAGE_WAIT 15
3331
3332 u32 flags;
3333#define MR_AN_ENABLE 0x00000001
3334#define MR_RESTART_AN 0x00000002
3335#define MR_AN_COMPLETE 0x00000004
3336#define MR_PAGE_RX 0x00000008
3337#define MR_NP_LOADED 0x00000010
3338#define MR_TOGGLE_TX 0x00000020
3339#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3340#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3341#define MR_LP_ADV_SYM_PAUSE 0x00000100
3342#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3343#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3344#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3345#define MR_LP_ADV_NEXT_PAGE 0x00001000
3346#define MR_TOGGLE_RX 0x00002000
3347#define MR_NP_RX 0x00004000
3348
3349#define MR_LINK_OK 0x80000000
3350
3351 unsigned long link_time, cur_time;
3352
3353 u32 ability_match_cfg;
3354 int ability_match_count;
3355
3356 char ability_match, idle_match, ack_match;
3357
3358 u32 txconfig, rxconfig;
3359#define ANEG_CFG_NP 0x00000080
3360#define ANEG_CFG_ACK 0x00000040
3361#define ANEG_CFG_RF2 0x00000020
3362#define ANEG_CFG_RF1 0x00000010
3363#define ANEG_CFG_PS2 0x00000001
3364#define ANEG_CFG_PS1 0x00008000
3365#define ANEG_CFG_HD 0x00004000
3366#define ANEG_CFG_FD 0x00002000
3367#define ANEG_CFG_INVAL 0x00001f06
3368
3369};
3370#define ANEG_OK 0
3371#define ANEG_DONE 1
3372#define ANEG_TIMER_ENAB 2
3373#define ANEG_FAILED -1
3374
3375#define ANEG_STATE_SETTLE_TIME 10000
3376
3377static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3378 struct tg3_fiber_aneginfo *ap)
3379{
5be73b47 3380 u16 flowctrl;
1da177e4
LT		 3381 unsigned long delta;
3382 u32 rx_cfg_reg;
3383 int ret;
3384
3385 if (ap->state == ANEG_STATE_UNKNOWN) {
3386 ap->rxconfig = 0;
3387 ap->link_time = 0;
3388 ap->cur_time = 0;
3389 ap->ability_match_cfg = 0;
3390 ap->ability_match_count = 0;
3391 ap->ability_match = 0;
3392 ap->idle_match = 0;
3393 ap->ack_match = 0;
3394 }
3395 ap->cur_time++;
3396
3397 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3398 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3399
3400 if (rx_cfg_reg != ap->ability_match_cfg) {
3401 ap->ability_match_cfg = rx_cfg_reg;
3402 ap->ability_match = 0;
3403 ap->ability_match_count = 0;
3404 } else {
3405 if (++ap->ability_match_count > 1) {
3406 ap->ability_match = 1;
3407 ap->ability_match_cfg = rx_cfg_reg;
3408 }
3409 }
3410 if (rx_cfg_reg & ANEG_CFG_ACK)
3411 ap->ack_match = 1;
3412 else
3413 ap->ack_match = 0;
3414
3415 ap->idle_match = 0;
3416 } else {
3417 ap->idle_match = 1;
3418 ap->ability_match_cfg = 0;
3419 ap->ability_match_count = 0;
3420 ap->ability_match = 0;
3421 ap->ack_match = 0;
3422
3423 rx_cfg_reg = 0;
3424 }
3425
3426 ap->rxconfig = rx_cfg_reg;
3427 ret = ANEG_OK;
3428
33f401ae 3429 switch (ap->state) {
1da177e4
LT		 3430 case ANEG_STATE_UNKNOWN:
3431 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3432 ap->state = ANEG_STATE_AN_ENABLE;
3433
3434 /* fallthru */
3435 case ANEG_STATE_AN_ENABLE:
3436 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3437 if (ap->flags & MR_AN_ENABLE) {
3438 ap->link_time = 0;
3439 ap->cur_time = 0;
3440 ap->ability_match_cfg = 0;
3441 ap->ability_match_count = 0;
3442 ap->ability_match = 0;
3443 ap->idle_match = 0;
3444 ap->ack_match = 0;
3445
3446 ap->state = ANEG_STATE_RESTART_INIT;
3447 } else {
3448 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3449 }
3450 break;
3451
3452 case ANEG_STATE_RESTART_INIT:
3453 ap->link_time = ap->cur_time;
3454 ap->flags &= ~(MR_NP_LOADED);
3455 ap->txconfig = 0;
3456 tw32(MAC_TX_AUTO_NEG, 0);
3457 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3458 tw32_f(MAC_MODE, tp->mac_mode);
3459 udelay(40);
3460
3461 ret = ANEG_TIMER_ENAB;
3462 ap->state = ANEG_STATE_RESTART;
3463
3464 /* fallthru */
3465 case ANEG_STATE_RESTART:
3466 delta = ap->cur_time - ap->link_time;
859a5887 3467 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 3468 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 3469 else
1da177e4 3470 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 3471 break;
3472
3473 case ANEG_STATE_DISABLE_LINK_OK:
3474 ret = ANEG_DONE;
3475 break;
3476
3477 case ANEG_STATE_ABILITY_DETECT_INIT:
3478 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3479 ap->txconfig = ANEG_CFG_FD;
3480 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3481 if (flowctrl & ADVERTISE_1000XPAUSE)
3482 ap->txconfig |= ANEG_CFG_PS1;
3483 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3484 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3485 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487 tw32_f(MAC_MODE, tp->mac_mode);
3488 udelay(40);
3489
3490 ap->state = ANEG_STATE_ABILITY_DETECT;
3491 break;
3492
3493 case ANEG_STATE_ABILITY_DETECT:
859a5887 3494 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 3495 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 3496 break;
3497
3498 case ANEG_STATE_ACK_DETECT_INIT:
3499 ap->txconfig |= ANEG_CFG_ACK;
3500 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3501 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3502 tw32_f(MAC_MODE, tp->mac_mode);
3503 udelay(40);
3504
3505 ap->state = ANEG_STATE_ACK_DETECT;
3506
3507 /* fallthru */
3508 case ANEG_STATE_ACK_DETECT:
3509 if (ap->ack_match != 0) {
3510 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3511 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3512 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3513 } else {
3514 ap->state = ANEG_STATE_AN_ENABLE;
3515 }
3516 } else if (ap->ability_match != 0 &&
3517 ap->rxconfig == 0) {
3518 ap->state = ANEG_STATE_AN_ENABLE;
3519 }
3520 break;
3521
3522 case ANEG_STATE_COMPLETE_ACK_INIT:
3523 if (ap->rxconfig & ANEG_CFG_INVAL) {
3524 ret = ANEG_FAILED;
3525 break;
3526 }
3527 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3528 MR_LP_ADV_HALF_DUPLEX |
3529 MR_LP_ADV_SYM_PAUSE |
3530 MR_LP_ADV_ASYM_PAUSE |
3531 MR_LP_ADV_REMOTE_FAULT1 |
3532 MR_LP_ADV_REMOTE_FAULT2 |
3533 MR_LP_ADV_NEXT_PAGE |
3534 MR_TOGGLE_RX |
3535 MR_NP_RX);
3536 if (ap->rxconfig & ANEG_CFG_FD)
3537 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3538 if (ap->rxconfig & ANEG_CFG_HD)
3539 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3540 if (ap->rxconfig & ANEG_CFG_PS1)
3541 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3542 if (ap->rxconfig & ANEG_CFG_PS2)
3543 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3544 if (ap->rxconfig & ANEG_CFG_RF1)
3545 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3546 if (ap->rxconfig & ANEG_CFG_RF2)
3547 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3548 if (ap->rxconfig & ANEG_CFG_NP)
3549 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3550
3551 ap->link_time = ap->cur_time;
3552
3553 ap->flags ^= (MR_TOGGLE_TX);
3554 if (ap->rxconfig & 0x0008)
3555 ap->flags |= MR_TOGGLE_RX;
3556 if (ap->rxconfig & ANEG_CFG_NP)
3557 ap->flags |= MR_NP_RX;
3558 ap->flags |= MR_PAGE_RX;
3559
3560 ap->state = ANEG_STATE_COMPLETE_ACK;
3561 ret = ANEG_TIMER_ENAB;
3562 break;
3563
3564 case ANEG_STATE_COMPLETE_ACK:
3565 if (ap->ability_match != 0 &&
3566 ap->rxconfig == 0) {
3567 ap->state = ANEG_STATE_AN_ENABLE;
3568 break;
3569 }
3570 delta = ap->cur_time - ap->link_time;
3571 if (delta > ANEG_STATE_SETTLE_TIME) {
3572 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3573 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3574 } else {
3575 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3576 !(ap->flags & MR_NP_RX)) {
3577 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3578 } else {
3579 ret = ANEG_FAILED;
3580 }
3581 }
3582 }
3583 break;
3584
3585 case ANEG_STATE_IDLE_DETECT_INIT:
3586 ap->link_time = ap->cur_time;
3587 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3588 tw32_f(MAC_MODE, tp->mac_mode);
3589 udelay(40);
3590
3591 ap->state = ANEG_STATE_IDLE_DETECT;
3592 ret = ANEG_TIMER_ENAB;
3593 break;
3594
3595 case ANEG_STATE_IDLE_DETECT:
3596 if (ap->ability_match != 0 &&
3597 ap->rxconfig == 0) {
3598 ap->state = ANEG_STATE_AN_ENABLE;
3599 break;
3600 }
3601 delta = ap->cur_time - ap->link_time;
3602 if (delta > ANEG_STATE_SETTLE_TIME) {
3603 /* XXX another gem from the Broadcom driver :( */
3604 ap->state = ANEG_STATE_LINK_OK;
3605 }
3606 break;
3607
3608 case ANEG_STATE_LINK_OK:
3609 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3610 ret = ANEG_DONE;
3611 break;
3612
3613 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3614 /* ??? unimplemented */
3615 break;
3616
3617 case ANEG_STATE_NEXT_PAGE_WAIT:
3618 /* ??? unimplemented */
3619 break;
3620
3621 default:
3622 ret = ANEG_FAILED;
3623 break;
855e1111 3624 }
1da177e4
LT		 3625
3626 return ret;
3627}
3628
5be73b47 3629static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3630{
3631 int res = 0;
3632 struct tg3_fiber_aneginfo aninfo;
3633 int status = ANEG_FAILED;
3634 unsigned int tick;
3635 u32 tmp;
3636
3637 tw32_f(MAC_TX_AUTO_NEG, 0);
3638
3639 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3640 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3641 udelay(40);
3642
3643 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3644 udelay(40);
3645
3646 memset(&aninfo, 0, sizeof(aninfo));
3647 aninfo.flags |= MR_AN_ENABLE;
3648 aninfo.state = ANEG_STATE_UNKNOWN;
3649 aninfo.cur_time = 0;
3650 tick = 0;
3651 while (++tick < 195000) {
3652 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3653 if (status == ANEG_DONE || status == ANEG_FAILED)
3654 break;
3655
3656 udelay(1);
3657 }
3658
3659 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3660 tw32_f(MAC_MODE, tp->mac_mode);
3661 udelay(40);
3662
5be73b47
MC		 3663 *txflags = aninfo.txconfig;
3664 *rxflags = aninfo.flags;
1da177e4
LT		 3665
3666 if (status == ANEG_DONE &&
3667 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3668 MR_LP_ADV_FULL_DUPLEX)))
3669 res = 1;
3670
3671 return res;
3672}
3673
3674static void tg3_init_bcm8002(struct tg3 *tp)
3675{
3676 u32 mac_status = tr32(MAC_STATUS);
3677 int i;
3678
3679 /* Reset when initting first time or we have a link. */
3680 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3681 !(mac_status & MAC_STATUS_PCS_SYNCED))
3682 return;
3683
3684 /* Set PLL lock range. */
3685 tg3_writephy(tp, 0x16, 0x8007);
3686
3687 /* SW reset */
3688 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3689
3690 /* Wait for reset to complete. */
3691 /* XXX schedule_timeout() ... */
3692 for (i = 0; i < 500; i++)
3693 udelay(10);
3694
3695 /* Config mode; select PMA/Ch 1 regs. */
3696 tg3_writephy(tp, 0x10, 0x8411);
3697
3698 /* Enable auto-lock and comdet, select txclk for tx. */
3699 tg3_writephy(tp, 0x11, 0x0a10);
3700
3701 tg3_writephy(tp, 0x18, 0x00a0);
3702 tg3_writephy(tp, 0x16, 0x41ff);
3703
3704 /* Assert and deassert POR. */
3705 tg3_writephy(tp, 0x13, 0x0400);
3706 udelay(40);
3707 tg3_writephy(tp, 0x13, 0x0000);
3708
3709 tg3_writephy(tp, 0x11, 0x0a50);
3710 udelay(40);
3711 tg3_writephy(tp, 0x11, 0x0a10);
3712
3713 /* Wait for signal to stabilize */
3714 /* XXX schedule_timeout() ... */
3715 for (i = 0; i < 15000; i++)
3716 udelay(10);
3717
3718 /* Deselect the channel register so we can read the PHYID
3719 * later.
3720 */
3721 tg3_writephy(tp, 0x10, 0x8011);
3722}
3723
3724static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3725{
82cd3d11 3726 u16 flowctrl;
1da177e4
LT		 3727 u32 sg_dig_ctrl, sg_dig_status;
3728 u32 serdes_cfg, expected_sg_dig_ctrl;
3729 int workaround, port_a;
3730 int current_link_up;
3731
3732 serdes_cfg = 0;
3733 expected_sg_dig_ctrl = 0;
3734 workaround = 0;
3735 port_a = 1;
3736 current_link_up = 0;
3737
3738 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3739 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3740 workaround = 1;
3741 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3742 port_a = 0;
3743
3744 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3745 /* preserve bits 20-23 for voltage regulator */
3746 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3747 }
3748
3749 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3750
3751 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3752 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3753 if (workaround) {
3754 u32 val = serdes_cfg;
3755
3756 if (port_a)
3757 val |= 0xc010000;
3758 else
3759 val |= 0x4010000;
3760 tw32_f(MAC_SERDES_CFG, val);
3761 }
c98f6e3b
MC		 3762
3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3764 }
3765 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3766 tg3_setup_flow_control(tp, 0, 0);
3767 current_link_up = 1;
3768 }
3769 goto out;
3770 }
3771
3772 /* Want auto-negotiation. */
c98f6e3b 3773 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3774
82cd3d11
MC		 3775 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3776 if (flowctrl & ADVERTISE_1000XPAUSE)
3777 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3778 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3779 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3780
3781 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3782 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3783 tp->serdes_counter &&
3784 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3785 MAC_STATUS_RCVD_CFG)) ==
3786 MAC_STATUS_PCS_SYNCED)) {
3787 tp->serdes_counter--;
3788 current_link_up = 1;
3789 goto out;
3790 }
3791restart_autoneg:
1da177e4
LT		 3792 if (workaround)
3793 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3794 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3795 udelay(5);
3796 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3797
3d3ebe74
MC		 3798 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3799 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3800 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3801 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3802 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3803 mac_status = tr32(MAC_STATUS);
3804
c98f6e3b 3805 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3806 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3807 u32 local_adv = 0, remote_adv = 0;
3808
3809 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3810 local_adv |= ADVERTISE_1000XPAUSE;
3811 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3812 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3813
c98f6e3b 3814 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3815 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3816 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3817 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3818
3819 tg3_setup_flow_control(tp, local_adv, remote_adv);
3820 current_link_up = 1;
3d3ebe74
MC		 3821 tp->serdes_counter = 0;
3822 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3823 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3824 if (tp->serdes_counter)
3825 tp->serdes_counter--;
1da177e4
LT		 3826 else {
3827 if (workaround) {
3828 u32 val = serdes_cfg;
3829
3830 if (port_a)
3831 val |= 0xc010000;
3832 else
3833 val |= 0x4010000;
3834
3835 tw32_f(MAC_SERDES_CFG, val);
3836 }
3837
c98f6e3b 3838 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3839 udelay(40);
3840
3841 /* Link parallel detection - link is up */
3842 /* only if we have PCS_SYNC and not */
3843 /* receiving config code words */
3844 mac_status = tr32(MAC_STATUS);
3845 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3846 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3847 tg3_setup_flow_control(tp, 0, 0);
3848 current_link_up = 1;
3d3ebe74
MC		 3849 tp->tg3_flags2 |=
3850 TG3_FLG2_PARALLEL_DETECT;
3851 tp->serdes_counter =
3852 SERDES_PARALLEL_DET_TIMEOUT;
3853 } else
3854 goto restart_autoneg;
1da177e4
LT		 3855 }
3856 }
3d3ebe74
MC		 3857 } else {
3858 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3859 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3860 }
3861
3862out:
3863 return current_link_up;
3864}
3865
3866static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3867{
3868 int current_link_up = 0;
3869
5cf64b8a 3870 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3871 goto out;
1da177e4
LT		 3872
3873 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3874 u32 txflags, rxflags;
1da177e4 3875 int i;
6aa20a22 3876
5be73b47
MC		 3877 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3878 u32 local_adv = 0, remote_adv = 0;
1da177e4 3879
5be73b47
MC		 3880 if (txflags & ANEG_CFG_PS1)
3881 local_adv |= ADVERTISE_1000XPAUSE;
3882 if (txflags & ANEG_CFG_PS2)
3883 local_adv |= ADVERTISE_1000XPSE_ASYM;
3884
3885 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3886 remote_adv |= LPA_1000XPAUSE;
3887 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3888 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3889
3890 tg3_setup_flow_control(tp, local_adv, remote_adv);
3891
1da177e4
LT		 3892 current_link_up = 1;
3893 }
3894 for (i = 0; i < 30; i++) {
3895 udelay(20);
3896 tw32_f(MAC_STATUS,
3897 (MAC_STATUS_SYNC_CHANGED |
3898 MAC_STATUS_CFG_CHANGED));
3899 udelay(40);
3900 if ((tr32(MAC_STATUS) &
3901 (MAC_STATUS_SYNC_CHANGED |
3902 MAC_STATUS_CFG_CHANGED)) == 0)
3903 break;
3904 }
3905
3906 mac_status = tr32(MAC_STATUS);
3907 if (current_link_up == 0 &&
3908 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3909 !(mac_status & MAC_STATUS_RCVD_CFG))
3910 current_link_up = 1;
3911 } else {
5be73b47
MC		 3912 tg3_setup_flow_control(tp, 0, 0);
3913
1da177e4
LT		 3914 /* Forcing 1000FD link up. */
3915 current_link_up = 1;
1da177e4
LT		 3916
3917 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3918 udelay(40);
e8f3f6ca
MC		 3919
3920 tw32_f(MAC_MODE, tp->mac_mode);
3921 udelay(40);
1da177e4
LT		 3922 }
3923
3924out:
3925 return current_link_up;
3926}
3927
3928static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3929{
3930 u32 orig_pause_cfg;
3931 u16 orig_active_speed;
3932 u8 orig_active_duplex;
3933 u32 mac_status;
3934 int current_link_up;
3935 int i;
3936
8d018621 3937 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3938 orig_active_speed = tp->link_config.active_speed;
3939 orig_active_duplex = tp->link_config.active_duplex;
3940
3941 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3942 netif_carrier_ok(tp->dev) &&
3943 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3944 mac_status = tr32(MAC_STATUS);
3945 mac_status &= (MAC_STATUS_PCS_SYNCED |
3946 MAC_STATUS_SIGNAL_DET |
3947 MAC_STATUS_CFG_CHANGED |
3948 MAC_STATUS_RCVD_CFG);
3949 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3950 MAC_STATUS_SIGNAL_DET)) {
3951 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3952 MAC_STATUS_CFG_CHANGED));
3953 return 0;
3954 }
3955 }
3956
3957 tw32_f(MAC_TX_AUTO_NEG, 0);
3958
3959 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3960 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3961 tw32_f(MAC_MODE, tp->mac_mode);
3962 udelay(40);
3963
79eb6904 3964 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 3965 tg3_init_bcm8002(tp);
3966
3967 /* Enable link change event even when serdes polling. */
3968 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3969 udelay(40);
3970
3971 current_link_up = 0;
3972 mac_status = tr32(MAC_STATUS);
3973
3974 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3975 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3976 else
3977 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3978
898a56f8 3979 tp->napi[0].hw_status->status =
1da177e4 3980 (SD_STATUS_UPDATED |
898a56f8 3981 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3982
3983 for (i = 0; i < 100; i++) {
3984 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3985 MAC_STATUS_CFG_CHANGED));
3986 udelay(5);
3987 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3988 MAC_STATUS_CFG_CHANGED |
3989 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3990 break;
3991 }
3992
3993 mac_status = tr32(MAC_STATUS);
3994 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3995 current_link_up = 0;
3d3ebe74
MC		 3996 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3997 tp->serdes_counter == 0) {
1da177e4
LT		 3998 tw32_f(MAC_MODE, (tp->mac_mode |
3999 MAC_MODE_SEND_CONFIGS));
4000 udelay(1);
4001 tw32_f(MAC_MODE, tp->mac_mode);
4002 }
4003 }
4004
4005 if (current_link_up == 1) {
4006 tp->link_config.active_speed = SPEED_1000;
4007 tp->link_config.active_duplex = DUPLEX_FULL;
4008 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4009 LED_CTRL_LNKLED_OVERRIDE |
4010 LED_CTRL_1000MBPS_ON));
4011 } else {
4012 tp->link_config.active_speed = SPEED_INVALID;
4013 tp->link_config.active_duplex = DUPLEX_INVALID;
4014 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4015 LED_CTRL_LNKLED_OVERRIDE |
4016 LED_CTRL_TRAFFIC_OVERRIDE));
4017 }
4018
4019 if (current_link_up != netif_carrier_ok(tp->dev)) {
4020 if (current_link_up)
4021 netif_carrier_on(tp->dev);
4022 else
4023 netif_carrier_off(tp->dev);
4024 tg3_link_report(tp);
4025 } else {
8d018621 4026 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4027 if (orig_pause_cfg != now_pause_cfg ||
4028 orig_active_speed != tp->link_config.active_speed ||
4029 orig_active_duplex != tp->link_config.active_duplex)
4030 tg3_link_report(tp);
4031 }
4032
4033 return 0;
4034}
4035
747e8f8b
MC		 4036static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4037{
4038 int current_link_up, err = 0;
4039 u32 bmsr, bmcr;
4040 u16 current_speed;
4041 u8 current_duplex;
ef167e27 4042 u32 local_adv, remote_adv;
747e8f8b
MC		 4043
4044 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4045 tw32_f(MAC_MODE, tp->mac_mode);
4046 udelay(40);
4047
4048 tw32(MAC_EVENT, 0);
4049
4050 tw32_f(MAC_STATUS,
4051 (MAC_STATUS_SYNC_CHANGED |
4052 MAC_STATUS_CFG_CHANGED |
4053 MAC_STATUS_MI_COMPLETION |
4054 MAC_STATUS_LNKSTATE_CHANGED));
4055 udelay(40);
4056
4057 if (force_reset)
4058 tg3_phy_reset(tp);
4059
4060 current_link_up = 0;
4061 current_speed = SPEED_INVALID;
4062 current_duplex = DUPLEX_INVALID;
4063
4064 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4065 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4067 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4068 bmsr |= BMSR_LSTATUS;
4069 else
4070 bmsr &= ~BMSR_LSTATUS;
4071 }
747e8f8b
MC		 4072
4073 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4074
4075 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4076 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4077 /* do nothing, just check for link up at the end */
4078 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4079 u32 adv, new_adv;
4080
4081 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4082 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4083 ADVERTISE_1000XPAUSE |
4084 ADVERTISE_1000XPSE_ASYM |
4085 ADVERTISE_SLCT);
4086
ba4d07a8 4087 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4088
4089 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4090 new_adv |= ADVERTISE_1000XHALF;
4091 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4092 new_adv |= ADVERTISE_1000XFULL;
4093
4094 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4095 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4096 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4097 tg3_writephy(tp, MII_BMCR, bmcr);
4098
4099 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4100 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4101 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4102
4103 return err;
4104 }
4105 } else {
4106 u32 new_bmcr;
4107
4108 bmcr &= ~BMCR_SPEED1000;
4109 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4110
4111 if (tp->link_config.duplex == DUPLEX_FULL)
4112 new_bmcr |= BMCR_FULLDPLX;
4113
4114 if (new_bmcr != bmcr) {
4115 /* BMCR_SPEED1000 is a reserved bit that needs
4116 * to be set on write.
4117 */
4118 new_bmcr |= BMCR_SPEED1000;
4119
4120 /* Force a linkdown */
4121 if (netif_carrier_ok(tp->dev)) {
4122 u32 adv;
4123
4124 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4125 adv &= ~(ADVERTISE_1000XFULL |
4126 ADVERTISE_1000XHALF |
4127 ADVERTISE_SLCT);
4128 tg3_writephy(tp, MII_ADVERTISE, adv);
4129 tg3_writephy(tp, MII_BMCR, bmcr |
4130 BMCR_ANRESTART |
4131 BMCR_ANENABLE);
4132 udelay(10);
4133 netif_carrier_off(tp->dev);
4134 }
4135 tg3_writephy(tp, MII_BMCR, new_bmcr);
4136 bmcr = new_bmcr;
4137 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4138 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4139 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4140 ASIC_REV_5714) {
4141 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4142 bmsr |= BMSR_LSTATUS;
4143 else
4144 bmsr &= ~BMSR_LSTATUS;
4145 }
747e8f8b
MC		 4146 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4147 }
4148 }
4149
4150 if (bmsr & BMSR_LSTATUS) {
4151 current_speed = SPEED_1000;
4152 current_link_up = 1;
4153 if (bmcr & BMCR_FULLDPLX)
4154 current_duplex = DUPLEX_FULL;
4155 else
4156 current_duplex = DUPLEX_HALF;
4157
ef167e27
MC		 4158 local_adv = 0;
4159 remote_adv = 0;
4160
747e8f8b 4161 if (bmcr & BMCR_ANENABLE) {
ef167e27 4162 u32 common;
747e8f8b
MC		 4163
4164 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4165 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4166 common = local_adv & remote_adv;
4167 if (common & (ADVERTISE_1000XHALF |
4168 ADVERTISE_1000XFULL)) {
4169 if (common & ADVERTISE_1000XFULL)
4170 current_duplex = DUPLEX_FULL;
4171 else
4172 current_duplex = DUPLEX_HALF;
859a5887 4173 } else {
747e8f8b 4174 current_link_up = 0;
859a5887 4175 }
747e8f8b
MC		 4176 }
4177 }
4178
ef167e27
MC		 4179 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4180 tg3_setup_flow_control(tp, local_adv, remote_adv);
4181
747e8f8b
MC		 4182 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4183 if (tp->link_config.active_duplex == DUPLEX_HALF)
4184 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4185
4186 tw32_f(MAC_MODE, tp->mac_mode);
4187 udelay(40);
4188
4189 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4190
4191 tp->link_config.active_speed = current_speed;
4192 tp->link_config.active_duplex = current_duplex;
4193
4194 if (current_link_up != netif_carrier_ok(tp->dev)) {
4195 if (current_link_up)
4196 netif_carrier_on(tp->dev);
4197 else {
4198 netif_carrier_off(tp->dev);
4199 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4200 }
4201 tg3_link_report(tp);
4202 }
4203 return err;
4204}
4205
4206static void tg3_serdes_parallel_detect(struct tg3 *tp)
4207{
3d3ebe74 4208 if (tp->serdes_counter) {
747e8f8b 4209 /* Give autoneg time to complete. */
3d3ebe74 4210 tp->serdes_counter--;
747e8f8b
MC		 4211 return;
4212 }
c6cdf436 4213
747e8f8b
MC		 4214 if (!netif_carrier_ok(tp->dev) &&
4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4216 u32 bmcr;
4217
4218 tg3_readphy(tp, MII_BMCR, &bmcr);
4219 if (bmcr & BMCR_ANENABLE) {
4220 u32 phy1, phy2;
4221
4222 /* Select shadow register 0x1f */
4223 tg3_writephy(tp, 0x1c, 0x7c00);
4224 tg3_readphy(tp, 0x1c, &phy1);
4225
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp, 0x17, 0x0f01);
4228 tg3_readphy(tp, 0x15, &phy2);
4229 tg3_readphy(tp, 0x15, &phy2);
4230
4231 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4232 /* We have signal detect and not receiving
4233 * config code words, link is up by parallel
4234 * detection.
4235 */
4236
4237 bmcr &= ~BMCR_ANENABLE;
4238 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4239 tg3_writephy(tp, MII_BMCR, bmcr);
4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4241 }
4242 }
859a5887
MC		 4243 } else if (netif_carrier_ok(tp->dev) &&
4244 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4245 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4246 u32 phy2;
4247
4248 /* Select expansion interrupt status register */
4249 tg3_writephy(tp, 0x17, 0x0f01);
4250 tg3_readphy(tp, 0x15, &phy2);
4251 if (phy2 & 0x20) {
4252 u32 bmcr;
4253
4254 /* Config code words received, turn on autoneg. */
4255 tg3_readphy(tp, MII_BMCR, &bmcr);
4256 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4257
4258 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4259
4260 }
4261 }
4262}
4263
1da177e4
LT		 4264static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4265{
4266 int err;
4267
859a5887 4268 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1da177e4 4269 err = tg3_setup_fiber_phy(tp, force_reset);
859a5887 4270 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
747e8f8b 4271 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 4272 else
1da177e4 4273 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 4274
bcb37f6c 4275 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4276 u32 val, scale;
4277
4278 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4279 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4280 scale = 65;
4281 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4282 scale = 6;
4283 else
4284 scale = 12;
4285
4286 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4287 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4288 tw32(GRC_MISC_CFG, val);
4289 }
4290
1da177e4
LT		 4291 if (tp->link_config.active_speed == SPEED_1000 &&
4292 tp->link_config.active_duplex == DUPLEX_HALF)
4293 tw32(MAC_TX_LENGTHS,
4294 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4295 (6 << TX_LENGTHS_IPG_SHIFT) |
4296 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4297 else
4298 tw32(MAC_TX_LENGTHS,
4299 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4300 (6 << TX_LENGTHS_IPG_SHIFT) |
4301 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4302
4303 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4304 if (netif_carrier_ok(tp->dev)) {
4305 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4306 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4307 } else {
4308 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4309 }
4310 }
4311
8ed5d97e
MC		 4312 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4313 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4314 if (!netif_carrier_ok(tp->dev))
4315 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4316 tp->pwrmgmt_thresh;
4317 else
4318 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4319 tw32(PCIE_PWR_MGMT_THRESH, val);
4320 }
4321
1da177e4
LT		 4322 return err;
4323}
4324
df3e6548
MC		 4325/* This is called whenever we suspect that the system chipset is re-
4326 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4327 * is bogus tx completions. We try to recover by setting the
4328 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4329 * in the workqueue.
4330 */
4331static void tg3_tx_recover(struct tg3 *tp)
4332{
4333 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4334 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4335
5129c3a3
MC		 4336 netdev_warn(tp->dev,
4337 "The system may be re-ordering memory-mapped I/O "
4338 "cycles to the network device, attempting to recover. "
4339 "Please report the problem to the driver maintainer "
4340 "and include system chipset information.\n");
df3e6548
MC		 4341
4342 spin_lock(&tp->lock);
df3e6548 4343 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4344 spin_unlock(&tp->lock);
4345}
4346
f3f3f27e 4347static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4348{
4349 smp_mb();
f3f3f27e
MC		 4350 return tnapi->tx_pending -
4351 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4352}
4353
1da177e4
LT		 4354/* Tigon3 never reports partial packet sends. So we do not
4355 * need special logic to handle SKBs that have not had all
4356 * of their frags sent yet, like SunGEM does.
4357 */
17375d25 4358static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4359{
17375d25 4360 struct tg3 *tp = tnapi->tp;
898a56f8 4361 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4362 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4363 struct netdev_queue *txq;
4364 int index = tnapi - tp->napi;
4365
19cfaecc 4366 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4367 index--;
4368
4369 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4370
4371 while (sw_idx != hw_idx) {
f4188d8a 4372 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4373 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4374 int i, tx_bug = 0;
4375
4376 if (unlikely(skb == NULL)) {
4377 tg3_tx_recover(tp);
4378 return;
4379 }
1da177e4 4380
f4188d8a
AD		 4381 pci_unmap_single(tp->pdev,
4382 pci_unmap_addr(ri, mapping),
4383 skb_headlen(skb),
4384 PCI_DMA_TODEVICE);
1da177e4
LT		 4385
4386 ri->skb = NULL;
4387
4388 sw_idx = NEXT_TX(sw_idx);
4389
4390 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4391 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4392 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4393 tx_bug = 1;
f4188d8a
AD		 4394
4395 pci_unmap_page(tp->pdev,
4396 pci_unmap_addr(ri, mapping),
4397 skb_shinfo(skb)->frags[i].size,
4398 PCI_DMA_TODEVICE);
1da177e4
LT		 4399 sw_idx = NEXT_TX(sw_idx);
4400 }
4401
f47c11ee 4402 dev_kfree_skb(skb);
df3e6548
MC		 4403
4404 if (unlikely(tx_bug)) {
4405 tg3_tx_recover(tp);
4406 return;
4407 }
1da177e4
LT		 4408 }
4409
f3f3f27e 4410 tnapi->tx_cons = sw_idx;
1da177e4 4411
1b2a7205
MC		 4412 /* Need to make the tx_cons update visible to tg3_start_xmit()
4413 * before checking for netif_queue_stopped(). Without the
4414 * memory barrier, there is a small possibility that tg3_start_xmit()
4415 * will miss it and cause the queue to be stopped forever.
4416 */
4417 smp_mb();
4418
fe5f5787 4419 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4420 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4421 __netif_tx_lock(txq, smp_processor_id());
4422 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4423 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4424 netif_tx_wake_queue(txq);
4425 __netif_tx_unlock(txq);
51b91468 4426 }
1da177e4
LT		 4427}
4428
2b2cdb65
MC		 4429static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4430{
4431 if (!ri->skb)
4432 return;
4433
4434 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4435 map_sz, PCI_DMA_FROMDEVICE);
4436 dev_kfree_skb_any(ri->skb);
4437 ri->skb = NULL;
4438}
4439
1da177e4
LT		 4440/* Returns size of skb allocated or < 0 on error.
4441 *
4442 * We only need to fill in the address because the other members
4443 * of the RX descriptor are invariant, see tg3_init_rings.
4444 *
4445 * Note the purposeful assymetry of cpu vs. chip accesses. For
4446 * posting buffers we only dirty the first cache line of the RX
4447 * descriptor (containing the address). Whereas for the RX status
4448 * buffers the cpu only reads the last cacheline of the RX descriptor
4449 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4450 */
86b21e59 4451static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4452 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4453{
4454 struct tg3_rx_buffer_desc *desc;
4455 struct ring_info *map, *src_map;
4456 struct sk_buff *skb;
4457 dma_addr_t mapping;
4458 int skb_size, dest_idx;
4459
4460 src_map = NULL;
4461 switch (opaque_key) {
4462 case RXD_OPAQUE_RING_STD:
4463 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4464 desc = &tpr->rx_std[dest_idx];
4465 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4466 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4467 break;
4468
4469 case RXD_OPAQUE_RING_JUMBO:
4470 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4471 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4472 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4473 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4474 break;
4475
4476 default:
4477 return -EINVAL;
855e1111 4478 }
1da177e4
LT		 4479
4480 /* Do not overwrite any of the map or rp information
4481 * until we are sure we can commit to a new buffer.
4482 *
4483 * Callers depend upon this behavior and assume that
4484 * we leave everything unchanged if we fail.
4485 */
287be12e 4486 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4487 if (skb == NULL)
4488 return -ENOMEM;
4489
1da177e4
LT		 4490 skb_reserve(skb, tp->rx_offset);
4491
287be12e 4492 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4493 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4494 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4495 dev_kfree_skb(skb);
4496 return -EIO;
4497 }
1da177e4
LT		 4498
4499 map->skb = skb;
4500 pci_unmap_addr_set(map, mapping, mapping);
4501
1da177e4
LT		 4502 desc->addr_hi = ((u64)mapping >> 32);
4503 desc->addr_lo = ((u64)mapping & 0xffffffff);
4504
4505 return skb_size;
4506}
4507
4508/* We only need to move over in the address because the other
4509 * members of the RX descriptor are invariant. See notes above
4510 * tg3_alloc_rx_skb for full details.
4511 */
a3896167
MC		 4512static void tg3_recycle_rx(struct tg3_napi *tnapi,
4513 struct tg3_rx_prodring_set *dpr,
4514 u32 opaque_key, int src_idx,
4515 u32 dest_idx_unmasked)
1da177e4 4516{
17375d25 4517 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4518 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4519 struct ring_info *src_map, *dest_map;
a3896167 4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
c6cdf436 4521 int dest_idx;
1da177e4
LT		 4522
4523 switch (opaque_key) {
4524 case RXD_OPAQUE_RING_STD:
4525 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4526 dest_desc = &dpr->rx_std[dest_idx];
4527 dest_map = &dpr->rx_std_buffers[dest_idx];
4528 src_desc = &spr->rx_std[src_idx];
4529 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4530 break;
4531
4532 case RXD_OPAQUE_RING_JUMBO:
4533 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4534 dest_desc = &dpr->rx_jmb[dest_idx].std;
4535 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4536 src_desc = &spr->rx_jmb[src_idx].std;
4537 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4538 break;
4539
4540 default:
4541 return;
855e1111 4542 }
1da177e4
LT		 4543
4544 dest_map->skb = src_map->skb;
4545 pci_unmap_addr_set(dest_map, mapping,
4546 pci_unmap_addr(src_map, mapping));
4547 dest_desc->addr_hi = src_desc->addr_hi;
4548 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 4549
4550 /* Ensure that the update to the skb happens after the physical
4551 * addresses have been transferred to the new BD location.
4552 */
4553 smp_wmb();
4554
1da177e4
LT		 4555 src_map->skb = NULL;
4556}
4557
1da177e4
LT		 4558/* The RX ring scheme is composed of multiple rings which post fresh
4559 * buffers to the chip, and one special ring the chip uses to report
4560 * status back to the host.
4561 *
4562 * The special ring reports the status of received packets to the
4563 * host. The chip does not write into the original descriptor the
4564 * RX buffer was obtained from. The chip simply takes the original
4565 * descriptor as provided by the host, updates the status and length
4566 * field, then writes this into the next status ring entry.
4567 *
4568 * Each ring the host uses to post buffers to the chip is described
4569 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4570 * it is first placed into the on-chip ram. When the packet's length
4571 * is known, it walks down the TG3_BDINFO entries to select the ring.
4572 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4573 * which is within the range of the new packet's length is chosen.
4574 *
4575 * The "separate ring for rx status" scheme may sound queer, but it makes
4576 * sense from a cache coherency perspective. If only the host writes
4577 * to the buffer post rings, and only the chip writes to the rx status
4578 * rings, then cache lines never move beyond shared-modified state.
4579 * If both the host and chip were to write into the same ring, cache line
4580 * eviction could occur since both entities want it in an exclusive state.
4581 */
17375d25 4582static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4583{
17375d25 4584 struct tg3 *tp = tnapi->tp;
f92905de 4585 u32 work_mask, rx_std_posted = 0;
4361935a 4586 u32 std_prod_idx, jmb_prod_idx;
72334482 4587 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4588 u16 hw_idx;
1da177e4 4589 int received;
b196c7e4 4590 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4591
8d9d7cfc 4592 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4593 /*
4594 * We need to order the read of hw_idx and the read of
4595 * the opaque cookie.
4596 */
4597 rmb();
1da177e4
LT		 4598 work_mask = 0;
4599 received = 0;
4361935a
MC		 4600 std_prod_idx = tpr->rx_std_prod_idx;
4601 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4602 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4603 struct ring_info *ri;
72334482 4604 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4605 unsigned int len;
4606 struct sk_buff *skb;
4607 dma_addr_t dma_addr;
4608 u32 opaque_key, desc_idx, *post_ptr;
4609
4610 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4611 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4612 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4613 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4614 dma_addr = pci_unmap_addr(ri, mapping);
4615 skb = ri->skb;
4361935a 4616 post_ptr = &std_prod_idx;
f92905de 4617 rx_std_posted++;
1da177e4 4618 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4619 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4620 dma_addr = pci_unmap_addr(ri, mapping);
4621 skb = ri->skb;
4361935a 4622 post_ptr = &jmb_prod_idx;
21f581a5 4623 } else
1da177e4 4624 goto next_pkt_nopost;
1da177e4
LT		 4625
4626 work_mask |= opaque_key;
4627
4628 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4629 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4630 drop_it:
a3896167 4631 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4632 desc_idx, *post_ptr);
4633 drop_it_no_recycle:
4634 /* Other statistics kept track of by card. */
4635 tp->net_stats.rx_dropped++;
4636 goto next_pkt;
4637 }
4638
ad829268
MC		 4639 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4640 ETH_FCS_LEN;
1da177e4 4641
8e95a202
JP		 4642 if (len > RX_COPY_THRESHOLD &&
4643 tp->rx_offset == NET_IP_ALIGN) {
4644 /* rx_offset will likely not equal NET_IP_ALIGN
4645 * if this is a 5701 card running in PCI-X mode
4646 * [see tg3_get_invariants()]
4647 */
1da177e4
LT		 4648 int skb_size;
4649
86b21e59 4650 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4651 *post_ptr);
1da177e4
LT		 4652 if (skb_size < 0)
4653 goto drop_it;
4654
287be12e 4655 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4656 PCI_DMA_FROMDEVICE);
4657
61e800cf
MC		 4658 /* Ensure that the update to the skb happens
4659 * after the usage of the old DMA mapping.
4660 */
4661 smp_wmb();
4662
4663 ri->skb = NULL;
4664
1da177e4
LT		 4665 skb_put(skb, len);
4666 } else {
4667 struct sk_buff *copy_skb;
4668
a3896167 4669 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4670 desc_idx, *post_ptr);
4671
ad829268
MC		 4672 copy_skb = netdev_alloc_skb(tp->dev,
4673 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4674 if (copy_skb == NULL)
4675 goto drop_it_no_recycle;
4676
ad829268 4677 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4678 skb_put(copy_skb, len);
4679 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4680 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4681 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4682
4683 /* We'll reuse the original ring buffer. */
4684 skb = copy_skb;
4685 }
4686
4687 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4688 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4689 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4690 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4691 skb->ip_summed = CHECKSUM_UNNECESSARY;
4692 else
4693 skb->ip_summed = CHECKSUM_NONE;
4694
4695 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4696
4697 if (len > (tp->dev->mtu + ETH_HLEN) &&
4698 skb->protocol != htons(ETH_P_8021Q)) {
4699 dev_kfree_skb(skb);
4700 goto next_pkt;
4701 }
4702
1da177e4
LT		 4703#if TG3_VLAN_TAG_USED
4704 if (tp->vlgrp != NULL &&
4705 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4706 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4707 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4708 } else
4709#endif
17375d25 4710 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4711
1da177e4
LT		 4712 received++;
4713 budget--;
4714
4715next_pkt:
4716 (*post_ptr)++;
f92905de
MC		 4717
4718 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4719 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721 tpr->rx_std_prod_idx);
f92905de
MC		 4722 work_mask &= ~RXD_OPAQUE_RING_STD;
4723 rx_std_posted = 0;
4724 }
1da177e4 4725next_pkt_nopost:
483ba50b 4726 sw_idx++;
6b31a515 4727 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4728
4729 /* Refresh hw_idx to see if there is new work */
4730 if (sw_idx == hw_idx) {
8d9d7cfc 4731 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4732 rmb();
4733 }
1da177e4
LT		 4734 }
4735
4736 /* ACK the status ring. */
72334482
MC		 4737 tnapi->rx_rcb_ptr = sw_idx;
4738 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4739
4740 /* Refill RX ring(s). */
e4af1af9 4741 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
b196c7e4
MC		 4742 if (work_mask & RXD_OPAQUE_RING_STD) {
4743 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4744 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4745 tpr->rx_std_prod_idx);
4746 }
4747 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4748 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4749 TG3_RX_JUMBO_RING_SIZE;
4750 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4751 tpr->rx_jmb_prod_idx);
4752 }
4753 mmiowb();
4754 } else if (work_mask) {
4755 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4756 * updated before the producer indices can be updated.
4757 */
4758 smp_wmb();
4759
4361935a 4760 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4761 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4 4762
e4af1af9
MC		 4763 if (tnapi != &tp->napi[1])
4764 napi_schedule(&tp->napi[1].napi);
1da177e4 4765 }
1da177e4
LT		 4766
4767 return received;
4768}
4769
35f2d7d0 4770static void tg3_poll_link(struct tg3 *tp)
1da177e4 4771{
1da177e4
LT		 4772 /* handle link change and other phy events */
4773 if (!(tp->tg3_flags &
4774 (TG3_FLAG_USE_LINKCHG_REG |
4775 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4776 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4777
1da177e4
LT		 4778 if (sblk->status & SD_STATUS_LINK_CHG) {
4779 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4780 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4781 spin_lock(&tp->lock);
dd477003
MC		 4782 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4783 tw32_f(MAC_STATUS,
4784 (MAC_STATUS_SYNC_CHANGED |
4785 MAC_STATUS_CFG_CHANGED |
4786 MAC_STATUS_MI_COMPLETION |
4787 MAC_STATUS_LNKSTATE_CHANGED));
4788 udelay(40);
4789 } else
4790 tg3_setup_phy(tp, 0);
f47c11ee 4791 spin_unlock(&tp->lock);
1da177e4
LT		 4792 }
4793 }
35f2d7d0
MC		 4794}
4795
f89f38b8
MC		 4796static int tg3_rx_prodring_xfer(struct tg3 *tp,
4797 struct tg3_rx_prodring_set *dpr,
4798 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 4799{
4800 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 4801 int i, err = 0;
b196c7e4
MC		 4802
4803 while (1) {
4804 src_prod_idx = spr->rx_std_prod_idx;
4805
4806 /* Make sure updates to the rx_std_buffers[] entries and the
4807 * standard producer index are seen in the correct order.
4808 */
4809 smp_rmb();
4810
4811 if (spr->rx_std_cons_idx == src_prod_idx)
4812 break;
4813
4814 if (spr->rx_std_cons_idx < src_prod_idx)
4815 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4816 else
4817 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4818
4819 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4820
4821 si = spr->rx_std_cons_idx;
4822 di = dpr->rx_std_prod_idx;
4823
e92967bf
MC		 4824 for (i = di; i < di + cpycnt; i++) {
4825 if (dpr->rx_std_buffers[i].skb) {
4826 cpycnt = i - di;
f89f38b8 4827 err = -ENOSPC;
e92967bf
MC		 4828 break;
4829 }
4830 }
4831
4832 if (!cpycnt)
4833 break;
4834
4835 /* Ensure that updates to the rx_std_buffers ring and the
4836 * shadowed hardware producer ring from tg3_recycle_skb() are
4837 * ordered correctly WRT the skb check above.
4838 */
4839 smp_rmb();
4840
b196c7e4
MC		 4841 memcpy(&dpr->rx_std_buffers[di],
4842 &spr->rx_std_buffers[si],
4843 cpycnt * sizeof(struct ring_info));
4844
4845 for (i = 0; i < cpycnt; i++, di++, si++) {
4846 struct tg3_rx_buffer_desc *sbd, *dbd;
4847 sbd = &spr->rx_std[si];
4848 dbd = &dpr->rx_std[di];
4849 dbd->addr_hi = sbd->addr_hi;
4850 dbd->addr_lo = sbd->addr_lo;
4851 }
4852
4853 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4854 TG3_RX_RING_SIZE;
4855 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4856 TG3_RX_RING_SIZE;
4857 }
4858
4859 while (1) {
4860 src_prod_idx = spr->rx_jmb_prod_idx;
4861
4862 /* Make sure updates to the rx_jmb_buffers[] entries and
4863 * the jumbo producer index are seen in the correct order.
4864 */
4865 smp_rmb();
4866
4867 if (spr->rx_jmb_cons_idx == src_prod_idx)
4868 break;
4869
4870 if (spr->rx_jmb_cons_idx < src_prod_idx)
4871 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4872 else
4873 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4874
4875 cpycnt = min(cpycnt,
4876 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4877
4878 si = spr->rx_jmb_cons_idx;
4879 di = dpr->rx_jmb_prod_idx;
4880
e92967bf
MC		 4881 for (i = di; i < di + cpycnt; i++) {
4882 if (dpr->rx_jmb_buffers[i].skb) {
4883 cpycnt = i - di;
f89f38b8 4884 err = -ENOSPC;
e92967bf
MC		 4885 break;
4886 }
4887 }
4888
4889 if (!cpycnt)
4890 break;
4891
4892 /* Ensure that updates to the rx_jmb_buffers ring and the
4893 * shadowed hardware producer ring from tg3_recycle_skb() are
4894 * ordered correctly WRT the skb check above.
4895 */
4896 smp_rmb();
4897
b196c7e4
MC		 4898 memcpy(&dpr->rx_jmb_buffers[di],
4899 &spr->rx_jmb_buffers[si],
4900 cpycnt * sizeof(struct ring_info));
4901
4902 for (i = 0; i < cpycnt; i++, di++, si++) {
4903 struct tg3_rx_buffer_desc *sbd, *dbd;
4904 sbd = &spr->rx_jmb[si].std;
4905 dbd = &dpr->rx_jmb[di].std;
4906 dbd->addr_hi = sbd->addr_hi;
4907 dbd->addr_lo = sbd->addr_lo;
4908 }
4909
4910 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4911 TG3_RX_JUMBO_RING_SIZE;
4912 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4913 TG3_RX_JUMBO_RING_SIZE;
4914 }
f89f38b8
MC		 4915
4916 return err;
b196c7e4
MC		 4917}
4918
35f2d7d0
MC		 4919static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4920{
4921 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4922
4923 /* run TX completion thread */
f3f3f27e 4924 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4925 tg3_tx(tnapi);
6f535763 4926 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4927 return work_done;
1da177e4
LT		 4928 }
4929
1da177e4
LT		 4930 /* run RX thread, within the bounds set by NAPI.
4931 * All RX "locking" is done by ensuring outside
bea3348e 4932 * code synchronizes with tg3->napi.poll()
1da177e4 4933 */
8d9d7cfc 4934 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4935 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4936
b196c7e4 4937 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
e4af1af9 4938 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
f89f38b8 4939 int i, err = 0;
e4af1af9
MC		 4940 u32 std_prod_idx = dpr->rx_std_prod_idx;
4941 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 4942
e4af1af9 4943 for (i = 1; i < tp->irq_cnt; i++)
f89f38b8
MC		 4944 err |= tg3_rx_prodring_xfer(tp, dpr,
4945 tp->napi[i].prodring);
b196c7e4
MC		 4946
4947 wmb();
4948
e4af1af9
MC		 4949 if (std_prod_idx != dpr->rx_std_prod_idx)
4950 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4951 dpr->rx_std_prod_idx);
b196c7e4 4952
e4af1af9
MC		 4953 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4954 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4955 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 4956
4957 mmiowb();
f89f38b8
MC		 4958
4959 if (err)
4960 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 4961 }
4962
6f535763
DM		 4963 return work_done;
4964}
4965
35f2d7d0
MC		 4966static int tg3_poll_msix(struct napi_struct *napi, int budget)
4967{
4968 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4969 struct tg3 *tp = tnapi->tp;
4970 int work_done = 0;
4971 struct tg3_hw_status *sblk = tnapi->hw_status;
4972
4973 while (1) {
4974 work_done = tg3_poll_work(tnapi, work_done, budget);
4975
4976 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4977 goto tx_recovery;
4978
4979 if (unlikely(work_done >= budget))
4980 break;
4981
c6cdf436 4982 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 4983 * to tell the hw how much work has been processed,
4984 * so we must read it before checking for more work.
4985 */
4986 tnapi->last_tag = sblk->status_tag;
4987 tnapi->last_irq_tag = tnapi->last_tag;
4988 rmb();
4989
4990 /* check for RX/TX work to do */
6d40db7b
MC		 4991 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4992 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
35f2d7d0
MC		 4993 napi_complete(napi);
4994 /* Reenable interrupts. */
4995 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4996 mmiowb();
4997 break;
4998 }
4999 }
5000
5001 return work_done;
5002
5003tx_recovery:
5004 /* work_done is guaranteed to be less than budget. */
5005 napi_complete(napi);
5006 schedule_work(&tp->reset_task);
5007 return work_done;
5008}
5009
6f535763
DM		 5010static int tg3_poll(struct napi_struct *napi, int budget)
5011{
8ef0442f
MC		 5012 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5013 struct tg3 *tp = tnapi->tp;
6f535763 5014 int work_done = 0;
898a56f8 5015 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 5016
5017 while (1) {
35f2d7d0
MC		 5018 tg3_poll_link(tp);
5019
17375d25 5020 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 5021
5022 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023 goto tx_recovery;
5024
5025 if (unlikely(work_done >= budget))
5026 break;
5027
4fd7ab59 5028 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 5029 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 5030 * to tell the hw how much work has been processed,
5031 * so we must read it before checking for more work.
5032 */
898a56f8
MC		 5033 tnapi->last_tag = sblk->status_tag;
5034 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 5035 rmb();
5036 } else
5037 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 5038
17375d25 5039 if (likely(!tg3_has_work(tnapi))) {
288379f0 5040 napi_complete(napi);
17375d25 5041 tg3_int_reenable(tnapi);
6f535763
DM		 5042 break;
5043 }
1da177e4
LT		 5044 }
5045
bea3348e 5046 return work_done;
6f535763
DM		 5047
5048tx_recovery:
4fd7ab59 5049 /* work_done is guaranteed to be less than budget. */
288379f0 5050 napi_complete(napi);
6f535763 5051 schedule_work(&tp->reset_task);
4fd7ab59 5052 return work_done;
1da177e4
LT		 5053}
5054
f47c11ee
DM		 5055static void tg3_irq_quiesce(struct tg3 *tp)
5056{
4f125f42
MC		 5057 int i;
5058
f47c11ee
DM		 5059 BUG_ON(tp->irq_sync);
5060
5061 tp->irq_sync = 1;
5062 smp_mb();
5063
4f125f42
MC		 5064 for (i = 0; i < tp->irq_cnt; i++)
5065 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5066}
5067
5068static inline int tg3_irq_sync(struct tg3 *tp)
5069{
5070 return tp->irq_sync;
5071}
5072
5073/* Fully shutdown all tg3 driver activity elsewhere in the system.
5074 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5075 * with as well. Most of the time, this is not necessary except when
5076 * shutting down the device.
5077 */
5078static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5079{
46966545 5080 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5081 if (irq_sync)
5082 tg3_irq_quiesce(tp);
f47c11ee
DM		 5083}
5084
5085static inline void tg3_full_unlock(struct tg3 *tp)
5086{
f47c11ee
DM		 5087 spin_unlock_bh(&tp->lock);
5088}
5089
fcfa0a32
MC		 5090/* One-shot MSI handler - Chip automatically disables interrupt
5091 * after sending MSI so driver doesn't have to do it.
5092 */
7d12e780 5093static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5094{
09943a18
MC		 5095 struct tg3_napi *tnapi = dev_id;
5096 struct tg3 *tp = tnapi->tp;
fcfa0a32 5097
898a56f8 5098 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5099 if (tnapi->rx_rcb)
5100 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5101
5102 if (likely(!tg3_irq_sync(tp)))
09943a18 5103 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5104
5105 return IRQ_HANDLED;
5106}
5107
88b06bc2
MC		 5108/* MSI ISR - No need to check for interrupt sharing and no need to
5109 * flush status block and interrupt mailbox. PCI ordering rules
5110 * guarantee that MSI will arrive after the status block.
5111 */
7d12e780 5112static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5113{
09943a18
MC		 5114 struct tg3_napi *tnapi = dev_id;
5115 struct tg3 *tp = tnapi->tp;
88b06bc2 5116
898a56f8 5117 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5118 if (tnapi->rx_rcb)
5119 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5120 /*
fac9b83e 5121 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5122 * chip-internal interrupt pending events.
fac9b83e 5123 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5124 * NIC to stop sending us irqs, engaging "in-intr-handler"
5125 * event coalescing.
5126 */
5127 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5128 if (likely(!tg3_irq_sync(tp)))
09943a18 5129 napi_schedule(&tnapi->napi);
61487480 5130
88b06bc2
MC		 5131 return IRQ_RETVAL(1);
5132}
5133
7d12e780 5134static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5135{
09943a18
MC		 5136 struct tg3_napi *tnapi = dev_id;
5137 struct tg3 *tp = tnapi->tp;
898a56f8 5138 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5139 unsigned int handled = 1;
5140
1da177e4
LT		 5141 /* In INTx mode, it is possible for the interrupt to arrive at
5142 * the CPU before the status block posted prior to the interrupt.
5143 * Reading the PCI State register will confirm whether the
5144 * interrupt is ours and will flush the status block.
5145 */
d18edcb2
MC		 5146 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5147 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5148 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5149 handled = 0;
f47c11ee 5150 goto out;
fac9b83e 5151 }
d18edcb2
MC		 5152 }
5153
5154 /*
5155 * Writing any value to intr-mbox-0 clears PCI INTA# and
5156 * chip-internal interrupt pending events.
5157 * Writing non-zero to intr-mbox-0 additional tells the
5158 * NIC to stop sending us irqs, engaging "in-intr-handler"
5159 * event coalescing.
c04cb347
MC		 5160 *
5161 * Flush the mailbox to de-assert the IRQ immediately to prevent
5162 * spurious interrupts. The flush impacts performance but
5163 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5164 */
c04cb347 5165 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5166 if (tg3_irq_sync(tp))
5167 goto out;
5168 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5169 if (likely(tg3_has_work(tnapi))) {
72334482 5170 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5171 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5172 } else {
5173 /* No work, shared interrupt perhaps? re-enable
5174 * interrupts, and flush that PCI write
5175 */
5176 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5177 0x00000000);
fac9b83e 5178 }
f47c11ee 5179out:
fac9b83e
DM		 5180 return IRQ_RETVAL(handled);
5181}
5182
7d12e780 5183static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5184{
09943a18
MC		 5185 struct tg3_napi *tnapi = dev_id;
5186 struct tg3 *tp = tnapi->tp;
898a56f8 5187 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5188 unsigned int handled = 1;
5189
fac9b83e
DM		 5190 /* In INTx mode, it is possible for the interrupt to arrive at
5191 * the CPU before the status block posted prior to the interrupt.
5192 * Reading the PCI State register will confirm whether the
5193 * interrupt is ours and will flush the status block.
5194 */
898a56f8 5195 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5196 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5197 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5198 handled = 0;
f47c11ee 5199 goto out;
1da177e4 5200 }
d18edcb2
MC		 5201 }
5202
5203 /*
5204 * writing any value to intr-mbox-0 clears PCI INTA# and
5205 * chip-internal interrupt pending events.
5206 * writing non-zero to intr-mbox-0 additional tells the
5207 * NIC to stop sending us irqs, engaging "in-intr-handler"
5208 * event coalescing.
c04cb347
MC		 5209 *
5210 * Flush the mailbox to de-assert the IRQ immediately to prevent
5211 * spurious interrupts. The flush impacts performance but
5212 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5213 */
c04cb347 5214 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5215
5216 /*
5217 * In a shared interrupt configuration, sometimes other devices'
5218 * interrupts will scream. We record the current status tag here
5219 * so that the above check can report that the screaming interrupts
5220 * are unhandled. Eventually they will be silenced.
5221 */
898a56f8 5222 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5223
d18edcb2
MC		 5224 if (tg3_irq_sync(tp))
5225 goto out;
624f8e50 5226
72334482 5227 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5228
09943a18 5229 napi_schedule(&tnapi->napi);
624f8e50 5230
f47c11ee 5231out:
1da177e4
LT		 5232 return IRQ_RETVAL(handled);
5233}
5234
7938109f 5235/* ISR for interrupt test */
7d12e780 5236static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5237{
09943a18
MC		 5238 struct tg3_napi *tnapi = dev_id;
5239 struct tg3 *tp = tnapi->tp;
898a56f8 5240 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5241
f9804ddb
MC		 5242 if ((sblk->status & SD_STATUS_UPDATED) ||
5243 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5244 tg3_disable_ints(tp);
7938109f
MC		 5245 return IRQ_RETVAL(1);
5246 }
5247 return IRQ_RETVAL(0);
5248}
5249
8e7a22e3 5250static int tg3_init_hw(struct tg3 *, int);
944d980e 5251static int tg3_halt(struct tg3 *, int, int);
1da177e4 5252
b9ec6c1b
MC		 5253/* Restart hardware after configuration changes, self-test, etc.
5254 * Invoked with tp->lock held.
5255 */
5256static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5257 __releases(tp->lock)
5258 __acquires(tp->lock)
b9ec6c1b
MC		 5259{
5260 int err;
5261
5262 err = tg3_init_hw(tp, reset_phy);
5263 if (err) {
5129c3a3
MC		 5264 netdev_err(tp->dev,
5265 "Failed to re-initialize device, aborting\n");
b9ec6c1b
MC		 5266 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5267 tg3_full_unlock(tp);
5268 del_timer_sync(&tp->timer);
5269 tp->irq_sync = 0;
fed97810 5270 tg3_napi_enable(tp);
b9ec6c1b
MC		 5271 dev_close(tp->dev);
5272 tg3_full_lock(tp, 0);
5273 }
5274 return err;
5275}
5276
1da177e4
LT		 5277#ifdef CONFIG_NET_POLL_CONTROLLER
5278static void tg3_poll_controller(struct net_device *dev)
5279{
4f125f42 5280 int i;
88b06bc2
MC		 5281 struct tg3 *tp = netdev_priv(dev);
5282
4f125f42 5283 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 5284 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 5285}
5286#endif
5287
c4028958 5288static void tg3_reset_task(struct work_struct *work)
1da177e4 5289{
c4028958 5290 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5291 int err;
1da177e4
LT		 5292 unsigned int restart_timer;
5293
7faa006f 5294 tg3_full_lock(tp, 0);
7faa006f
MC		 5295
5296 if (!netif_running(tp->dev)) {
7faa006f
MC		 5297 tg3_full_unlock(tp);
5298 return;
5299 }
5300
5301 tg3_full_unlock(tp);
5302
b02fd9e3
MC		 5303 tg3_phy_stop(tp);
5304
1da177e4
LT		 5305 tg3_netif_stop(tp);
5306
f47c11ee 5307 tg3_full_lock(tp, 1);
1da177e4
LT		 5308
5309 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5310 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5311
df3e6548
MC		 5312 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5313 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5314 tp->write32_rx_mbox = tg3_write_flush_reg32;
5315 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5316 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5317 }
5318
944d980e 5319 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5320 err = tg3_init_hw(tp, 1);
5321 if (err)
b9ec6c1b 5322 goto out;
1da177e4
LT		 5323
5324 tg3_netif_start(tp);
5325
1da177e4
LT		 5326 if (restart_timer)
5327 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5328
b9ec6c1b 5329out:
7faa006f 5330 tg3_full_unlock(tp);
b02fd9e3
MC		 5331
5332 if (!err)
5333 tg3_phy_start(tp);
1da177e4
LT		 5334}
5335
b0408751
MC		 5336static void tg3_dump_short_state(struct tg3 *tp)
5337{
05dbe005
JP		 5338 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5339 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5340 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5341 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
b0408751
MC		 5342}
5343
1da177e4
LT		 5344static void tg3_tx_timeout(struct net_device *dev)
5345{
5346 struct tg3 *tp = netdev_priv(dev);
5347
b0408751 5348 if (netif_msg_tx_err(tp)) {
05dbe005 5349 netdev_err(dev, "transmit timed out, resetting\n");
b0408751
MC		 5350 tg3_dump_short_state(tp);
5351 }
1da177e4
LT		 5352
5353 schedule_work(&tp->reset_task);
5354}
5355
c58ec932
MC		 5356/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5357static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5358{
5359 u32 base = (u32) mapping & 0xffffffff;
5360
5361 return ((base > 0xffffdcc0) &&
5362 (base + len + 8 < base));
5363}
5364
72f2afb8
MC		 5365/* Test for DMA addresses > 40-bit */
5366static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5367 int len)
5368{
5369#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5370 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5371 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5372 return 0;
5373#else
5374 return 0;
5375#endif
5376}
5377
f3f3f27e 5378static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5379
72f2afb8 5380/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5381static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5382 struct sk_buff *skb, u32 last_plus_one,
5383 u32 *start, u32 base_flags, u32 mss)
1da177e4 5384{
24f4efd4 5385 struct tg3 *tp = tnapi->tp;
41588ba1 5386 struct sk_buff *new_skb;
c58ec932 5387 dma_addr_t new_addr = 0;
1da177e4 5388 u32 entry = *start;
c58ec932 5389 int i, ret = 0;
1da177e4 5390
41588ba1
MC		 5391 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5392 new_skb = skb_copy(skb, GFP_ATOMIC);
5393 else {
5394 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5395
5396 new_skb = skb_copy_expand(skb,
5397 skb_headroom(skb) + more_headroom,
5398 skb_tailroom(skb), GFP_ATOMIC);
5399 }
5400
1da177e4 5401 if (!new_skb) {
c58ec932
MC		 5402 ret = -1;
5403 } else {
5404 /* New SKB is guaranteed to be linear. */
5405 entry = *start;
f4188d8a
AD		 5406 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5407 PCI_DMA_TODEVICE);
5408 /* Make sure the mapping succeeded */
5409 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5410 ret = -1;
5411 dev_kfree_skb(new_skb);
5412 new_skb = NULL;
90079ce8 5413
c58ec932
MC		 5414 /* Make sure new skb does not cross any 4G boundaries.
5415 * Drop the packet if it does.
5416 */
f4188d8a
AD		 5417 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5418 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5419 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5420 PCI_DMA_TODEVICE);
c58ec932
MC		 5421 ret = -1;
5422 dev_kfree_skb(new_skb);
5423 new_skb = NULL;
5424 } else {
f3f3f27e 5425 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5426 base_flags, 1 | (mss << 1));
5427 *start = NEXT_TX(entry);
5428 }
1da177e4
LT		 5429 }
5430
1da177e4
LT		 5431 /* Now clean up the sw ring entries. */
5432 i = 0;
5433 while (entry != last_plus_one) {
f4188d8a
AD		 5434 int len;
5435
f3f3f27e 5436 if (i == 0)
f4188d8a 5437 len = skb_headlen(skb);
f3f3f27e 5438 else
f4188d8a
AD		 5439 len = skb_shinfo(skb)->frags[i-1].size;
5440
5441 pci_unmap_single(tp->pdev,
5442 pci_unmap_addr(&tnapi->tx_buffers[entry],
5443 mapping),
5444 len, PCI_DMA_TODEVICE);
5445 if (i == 0) {
5446 tnapi->tx_buffers[entry].skb = new_skb;
5447 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5448 new_addr);
5449 } else {
f3f3f27e 5450 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5451 }
1da177e4
LT		 5452 entry = NEXT_TX(entry);
5453 i++;
5454 }
5455
5456 dev_kfree_skb(skb);
5457
c58ec932 5458 return ret;
1da177e4
LT		 5459}
5460
f3f3f27e 5461static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5462 dma_addr_t mapping, int len, u32 flags,
5463 u32 mss_and_is_end)
5464{
f3f3f27e 5465 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5466 int is_end = (mss_and_is_end & 0x1);
5467 u32 mss = (mss_and_is_end >> 1);
5468 u32 vlan_tag = 0;
5469
5470 if (is_end)
5471 flags |= TXD_FLAG_END;
5472 if (flags & TXD_FLAG_VLAN) {
5473 vlan_tag = flags >> 16;
5474 flags &= 0xffff;
5475 }
5476 vlan_tag |= (mss << TXD_MSS_SHIFT);
5477
5478 txd->addr_hi = ((u64) mapping >> 32);
5479 txd->addr_lo = ((u64) mapping & 0xffffffff);
5480 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5481 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5482}
5483
5a6f3074 5484/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5485 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5486 */
61357325
SH		 5487static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5488 struct net_device *dev)
5a6f3074
MC		 5489{
5490 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5491 u32 len, entry, base_flags, mss;
90079ce8 5492 dma_addr_t mapping;
fe5f5787
MC		 5493 struct tg3_napi *tnapi;
5494 struct netdev_queue *txq;
f4188d8a
AD		 5495 unsigned int i, last;
5496
fe5f5787
MC		 5497 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5498 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5499 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5500 tnapi++;
5a6f3074 5501
00b70504 5502 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5503 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5504 * interrupt. Furthermore, IRQ processing runs lockless so we have
5505 * no IRQ context deadlocks to worry about either. Rejoice!
5506 */
f3f3f27e 5507 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5508 if (!netif_tx_queue_stopped(txq)) {
5509 netif_tx_stop_queue(txq);
5a6f3074
MC		 5510
5511 /* This is a hard error, log it. */
5129c3a3
MC		 5512 netdev_err(dev,
5513 "BUG! Tx Ring full when queue awake!\n");
5a6f3074 5514 }
5a6f3074
MC		 5515 return NETDEV_TX_BUSY;
5516 }
5517
f3f3f27e 5518 entry = tnapi->tx_prod;
5a6f3074 5519 base_flags = 0;
5a6f3074 5520 mss = 0;
c13e3713 5521 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5522 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5523 u32 hdrlen;
5a6f3074
MC		 5524
5525 if (skb_header_cloned(skb) &&
5526 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5527 dev_kfree_skb(skb);
5528 goto out_unlock;
5529 }
5530
b0026624 5531 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5532 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5533 else {
eddc9ec5
ACM		 5534 struct iphdr *iph = ip_hdr(skb);
5535
ab6a5bb6 5536 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5537 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5538
eddc9ec5
ACM		 5539 iph->check = 0;
5540 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5541 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5542 }
5a6f3074 5543
e849cdc3 5544 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5545 mss |= (hdrlen & 0xc) << 12;
5546 if (hdrlen & 0x10)
5547 base_flags |= 0x00000010;
5548 base_flags |= (hdrlen & 0x3e0) << 5;
5549 } else
5550 mss |= hdrlen << 9;
5551
5a6f3074
MC		 5552 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5553 TXD_FLAG_CPU_POST_DMA);
5554
aa8223c7 5555 tcp_hdr(skb)->check = 0;
5a6f3074 5556
859a5887 5557 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5a6f3074 5558 base_flags |= TXD_FLAG_TCPUDP_CSUM;
859a5887
MC		 5559 }
5560
5a6f3074
MC		 5561#if TG3_VLAN_TAG_USED
5562 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5563 base_flags |= (TXD_FLAG_VLAN |
5564 (vlan_tx_tag_get(skb) << 16));
5565#endif
5566
f4188d8a
AD		 5567 len = skb_headlen(skb);
5568
5569 /* Queue skb data, a.k.a. the main skb fragment. */
5570 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5571 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5572 dev_kfree_skb(skb);
5573 goto out_unlock;
5574 }
5575
f3f3f27e 5576 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5577 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5578
b703df6f 5579 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5580 !mss && skb->len > ETH_DATA_LEN)
5581 base_flags |= TXD_FLAG_JMB_PKT;
5582
f3f3f27e 5583 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5584 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5585
5586 entry = NEXT_TX(entry);
5587
5588 /* Now loop through additional data fragments, and queue them. */
5589 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5590 last = skb_shinfo(skb)->nr_frags - 1;
5591 for (i = 0; i <= last; i++) {
5592 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5593
5594 len = frag->size;
f4188d8a
AD		 5595 mapping = pci_map_page(tp->pdev,
5596 frag->page,
5597 frag->page_offset,
5598 len, PCI_DMA_TODEVICE);
5599 if (pci_dma_mapping_error(tp->pdev, mapping))
5600 goto dma_error;
5601
f3f3f27e 5602 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5603 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5604 mapping);
5a6f3074 5605
f3f3f27e 5606 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5607 base_flags, (i == last) | (mss << 1));
5608
5609 entry = NEXT_TX(entry);
5610 }
5611 }
5612
5613 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5614 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5615
f3f3f27e
MC		 5616 tnapi->tx_prod = entry;
5617 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5618 netif_tx_stop_queue(txq);
f3f3f27e 5619 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5620 netif_tx_wake_queue(txq);
5a6f3074
MC		 5621 }
5622
5623out_unlock:
cdd0db05 5624 mmiowb();
5a6f3074
MC		 5625
5626 return NETDEV_TX_OK;
f4188d8a
AD		 5627
5628dma_error:
5629 last = i;
5630 entry = tnapi->tx_prod;
5631 tnapi->tx_buffers[entry].skb = NULL;
5632 pci_unmap_single(tp->pdev,
5633 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5634 skb_headlen(skb),
5635 PCI_DMA_TODEVICE);
5636 for (i = 0; i <= last; i++) {
5637 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5638 entry = NEXT_TX(entry);
5639
5640 pci_unmap_page(tp->pdev,
5641 pci_unmap_addr(&tnapi->tx_buffers[entry],
5642 mapping),
5643 frag->size, PCI_DMA_TODEVICE);
5644 }
5645
5646 dev_kfree_skb(skb);
5647 return NETDEV_TX_OK;
5a6f3074
MC		 5648}
5649
61357325
SH		 5650static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5651 struct net_device *);
52c0fd83
MC		 5652
5653/* Use GSO to workaround a rare TSO bug that may be triggered when the
5654 * TSO header is greater than 80 bytes.
5655 */
5656static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5657{
5658 struct sk_buff *segs, *nskb;
f3f3f27e 5659 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5660
5661 /* Estimate the number of fragments in the worst case */
f3f3f27e 5662 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5663 netif_stop_queue(tp->dev);
f3f3f27e 5664 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5665 return NETDEV_TX_BUSY;
5666
5667 netif_wake_queue(tp->dev);
52c0fd83
MC		 5668 }
5669
5670 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5671 if (IS_ERR(segs))
52c0fd83
MC		 5672 goto tg3_tso_bug_end;
5673
5674 do {
5675 nskb = segs;
5676 segs = segs->next;
5677 nskb->next = NULL;
5678 tg3_start_xmit_dma_bug(nskb, tp->dev);
5679 } while (segs);
5680
5681tg3_tso_bug_end:
5682 dev_kfree_skb(skb);
5683
5684 return NETDEV_TX_OK;
5685}
52c0fd83 5686
5a6f3074
MC		 5687/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5688 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5689 */
61357325
SH		 5690static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5691 struct net_device *dev)
1da177e4
LT		 5692{
5693 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5694 u32 len, entry, base_flags, mss;
5695 int would_hit_hwbug;
90079ce8 5696 dma_addr_t mapping;
24f4efd4
MC		 5697 struct tg3_napi *tnapi;
5698 struct netdev_queue *txq;
f4188d8a
AD		 5699 unsigned int i, last;
5700
24f4efd4
MC		 5701 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5702 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5703 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5704 tnapi++;
1da177e4 5705
00b70504 5706 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5707 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5708 * interrupt. Furthermore, IRQ processing runs lockless so we have
5709 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5710 */
f3f3f27e 5711 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5712 if (!netif_tx_queue_stopped(txq)) {
5713 netif_tx_stop_queue(txq);
1f064a87
SH		 5714
5715 /* This is a hard error, log it. */
5129c3a3
MC		 5716 netdev_err(dev,
5717 "BUG! Tx Ring full when queue awake!\n");
1f064a87 5718 }
1da177e4
LT		 5719 return NETDEV_TX_BUSY;
5720 }
5721
f3f3f27e 5722 entry = tnapi->tx_prod;
1da177e4 5723 base_flags = 0;
84fa7933 5724 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5725 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5726
c13e3713 5727 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5728 struct iphdr *iph;
92c6b8d1 5729 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5730
5731 if (skb_header_cloned(skb) &&
5732 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5733 dev_kfree_skb(skb);
5734 goto out_unlock;
5735 }
5736
ab6a5bb6 5737 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5738 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5739
52c0fd83
MC		 5740 hdr_len = ip_tcp_len + tcp_opt_len;
5741 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5742 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5743 return (tg3_tso_bug(tp, skb));
5744
1da177e4
LT		 5745 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5746 TXD_FLAG_CPU_POST_DMA);
5747
eddc9ec5
ACM		 5748 iph = ip_hdr(skb);
5749 iph->check = 0;
5750 iph->tot_len = htons(mss + hdr_len);
1da177e4 5751 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5752 tcp_hdr(skb)->check = 0;
1da177e4 5753 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5754 } else
5755 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5756 iph->daddr, 0,
5757 IPPROTO_TCP,
5758 0);
1da177e4 5759
615774fe
MC		 5760 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5761 mss |= (hdr_len & 0xc) << 12;
5762 if (hdr_len & 0x10)
5763 base_flags |= 0x00000010;
5764 base_flags |= (hdr_len & 0x3e0) << 5;
5765 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5766 mss |= hdr_len << 9;
5767 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5768 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5769 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5770 int tsflags;
5771
eddc9ec5 5772 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5773 mss |= (tsflags << 11);
5774 }
5775 } else {
eddc9ec5 5776 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5777 int tsflags;
5778
eddc9ec5 5779 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5780 base_flags |= tsflags << 12;
5781 }
5782 }
5783 }
1da177e4
LT		 5784#if TG3_VLAN_TAG_USED
5785 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5786 base_flags |= (TXD_FLAG_VLAN |
5787 (vlan_tx_tag_get(skb) << 16));
5788#endif
5789
b703df6f 5790 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5791 !mss && skb->len > ETH_DATA_LEN)
5792 base_flags |= TXD_FLAG_JMB_PKT;
5793
f4188d8a
AD		 5794 len = skb_headlen(skb);
5795
5796 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5797 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5798 dev_kfree_skb(skb);
5799 goto out_unlock;
5800 }
5801
f3f3f27e 5802 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5803 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5804
5805 would_hit_hwbug = 0;
5806
92c6b8d1
MC		 5807 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5808 would_hit_hwbug = 1;
5809
0e1406dd
MC		 5810 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5811 tg3_4g_overflow_test(mapping, len))
5812 would_hit_hwbug = 1;
5813
5814 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5815 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5816 would_hit_hwbug = 1;
0e1406dd
MC		 5817
5818 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5819 would_hit_hwbug = 1;
1da177e4 5820
f3f3f27e 5821 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5822 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5823
5824 entry = NEXT_TX(entry);
5825
5826 /* Now loop through additional data fragments, and queue them. */
5827 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5828 last = skb_shinfo(skb)->nr_frags - 1;
5829 for (i = 0; i <= last; i++) {
5830 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5831
5832 len = frag->size;
f4188d8a
AD		 5833 mapping = pci_map_page(tp->pdev,
5834 frag->page,
5835 frag->page_offset,
5836 len, PCI_DMA_TODEVICE);
1da177e4 5837
f3f3f27e 5838 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5839 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5840 mapping);
5841 if (pci_dma_mapping_error(tp->pdev, mapping))
5842 goto dma_error;
1da177e4 5843
92c6b8d1
MC		 5844 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5845 len <= 8)
5846 would_hit_hwbug = 1;
5847
0e1406dd
MC		 5848 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5849 tg3_4g_overflow_test(mapping, len))
c58ec932 5850 would_hit_hwbug = 1;
1da177e4 5851
0e1406dd
MC		 5852 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5853 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5854 would_hit_hwbug = 1;
5855
1da177e4 5856 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5857 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5858 base_flags, (i == last)|(mss << 1));
5859 else
f3f3f27e 5860 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5861 base_flags, (i == last));
5862
5863 entry = NEXT_TX(entry);
5864 }
5865 }
5866
5867 if (would_hit_hwbug) {
5868 u32 last_plus_one = entry;
5869 u32 start;
1da177e4 5870
c58ec932
MC		 5871 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5872 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5873
5874 /* If the workaround fails due to memory/mapping
5875 * failure, silently drop this packet.
5876 */
24f4efd4 5877 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5878 &start, base_flags, mss))
1da177e4
LT		 5879 goto out_unlock;
5880
5881 entry = start;
5882 }
5883
5884 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5885 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5886
f3f3f27e
MC		 5887 tnapi->tx_prod = entry;
5888 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5889 netif_tx_stop_queue(txq);
f3f3f27e 5890 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5891 netif_tx_wake_queue(txq);
51b91468 5892 }
1da177e4
LT		 5893
5894out_unlock:
cdd0db05 5895 mmiowb();
1da177e4
LT		 5896
5897 return NETDEV_TX_OK;
f4188d8a
AD		 5898
5899dma_error:
5900 last = i;
5901 entry = tnapi->tx_prod;
5902 tnapi->tx_buffers[entry].skb = NULL;
5903 pci_unmap_single(tp->pdev,
5904 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5905 skb_headlen(skb),
5906 PCI_DMA_TODEVICE);
5907 for (i = 0; i <= last; i++) {
5908 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5909 entry = NEXT_TX(entry);
5910
5911 pci_unmap_page(tp->pdev,
5912 pci_unmap_addr(&tnapi->tx_buffers[entry],
5913 mapping),
5914 frag->size, PCI_DMA_TODEVICE);
5915 }
5916
5917 dev_kfree_skb(skb);
5918 return NETDEV_TX_OK;
1da177e4
LT		 5919}
5920
5921static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5922 int new_mtu)
5923{
5924 dev->mtu = new_mtu;
5925
ef7f5ec0 5926 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5927 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5928 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5929 ethtool_op_set_tso(dev, 0);
859a5887 5930 } else {
ef7f5ec0 5931 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
859a5887 5932 }
ef7f5ec0 5933 } else {
a4e2b347 5934 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5935 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5936 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5937 }
1da177e4
LT		 5938}
5939
5940static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5941{
5942 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5943 int err;
1da177e4
LT		 5944
5945 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5946 return -EINVAL;
5947
5948 if (!netif_running(dev)) {
5949 /* We'll just catch it later when the
5950 * device is up'd.
5951 */
5952 tg3_set_mtu(dev, tp, new_mtu);
5953 return 0;
5954 }
5955
b02fd9e3
MC		 5956 tg3_phy_stop(tp);
5957
1da177e4 5958 tg3_netif_stop(tp);
f47c11ee
DM		 5959
5960 tg3_full_lock(tp, 1);
1da177e4 5961
944d980e 5962 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5963
5964 tg3_set_mtu(dev, tp, new_mtu);
5965
b9ec6c1b 5966 err = tg3_restart_hw(tp, 0);
1da177e4 5967
b9ec6c1b
MC		 5968 if (!err)
5969 tg3_netif_start(tp);
1da177e4 5970
f47c11ee 5971 tg3_full_unlock(tp);
1da177e4 5972
b02fd9e3
MC		 5973 if (!err)
5974 tg3_phy_start(tp);
5975
b9ec6c1b 5976 return err;
1da177e4
LT		 5977}
5978
21f581a5
MC		 5979static void tg3_rx_prodring_free(struct tg3 *tp,
5980 struct tg3_rx_prodring_set *tpr)
1da177e4 5981{
1da177e4
LT		 5982 int i;
5983
b196c7e4
MC		 5984 if (tpr != &tp->prodring[0]) {
5985 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5986 i = (i + 1) % TG3_RX_RING_SIZE)
5987 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5988 tp->rx_pkt_map_sz);
5989
5990 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5991 for (i = tpr->rx_jmb_cons_idx;
5992 i != tpr->rx_jmb_prod_idx;
5993 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5994 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5995 TG3_RX_JMB_MAP_SZ);
5996 }
5997 }
5998
2b2cdb65 5999 return;
b196c7e4 6000 }
1da177e4 6001
2b2cdb65
MC		 6002 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6003 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6004 tp->rx_pkt_map_sz);
1da177e4 6005
cf7a7298 6006 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 6007 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6008 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6009 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 6010 }
6011}
6012
c6cdf436 6013/* Initialize rx rings for packet processing.
1da177e4
LT		 6014 *
6015 * The chip has been shut down and the driver detached from
6016 * the networking, so no interrupts or new tx packets will
6017 * end up in the driver. tp->{tx,}lock are held and thus
6018 * we may not sleep.
6019 */
21f581a5
MC		 6020static int tg3_rx_prodring_alloc(struct tg3 *tp,
6021 struct tg3_rx_prodring_set *tpr)
1da177e4 6022{
287be12e 6023 u32 i, rx_pkt_dma_sz;
1da177e4 6024
b196c7e4
MC		 6025 tpr->rx_std_cons_idx = 0;
6026 tpr->rx_std_prod_idx = 0;
6027 tpr->rx_jmb_cons_idx = 0;
6028 tpr->rx_jmb_prod_idx = 0;
6029
2b2cdb65
MC		 6030 if (tpr != &tp->prodring[0]) {
6031 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6032 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6033 memset(&tpr->rx_jmb_buffers[0], 0,
6034 TG3_RX_JMB_BUFF_RING_SIZE);
6035 goto done;
6036 }
6037
1da177e4 6038 /* Zero out all descriptors. */
21f581a5 6039 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 6040
287be12e 6041 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 6042 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 6043 tp->dev->mtu > ETH_DATA_LEN)
6044 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6045 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 6046
1da177e4
LT		 6047 /* Initialize invariants of the rings, we only set this
6048 * stuff once. This works because the card does not
6049 * write into the rx buffer posting rings.
6050 */
6051 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6052 struct tg3_rx_buffer_desc *rxd;
6053
21f581a5 6054 rxd = &tpr->rx_std[i];
287be12e 6055 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6056 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6057 rxd->opaque = (RXD_OPAQUE_RING_STD |
6058 (i << RXD_OPAQUE_INDEX_SHIFT));
6059 }
6060
1da177e4
LT		 6061 /* Now allocate fresh SKBs for each rx ring. */
6062 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6063 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
5129c3a3
MC		 6064 netdev_warn(tp->dev,
6065 "Using a smaller RX standard ring. Only "
6066 "%d out of %d buffers were allocated "
6067 "successfully\n", i, tp->rx_pending);
32d8c572 6068 if (i == 0)
cf7a7298 6069 goto initfail;
32d8c572 6070 tp->rx_pending = i;
1da177e4 6071 break;
32d8c572 6072 }
1da177e4
LT		 6073 }
6074
cf7a7298
MC		 6075 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6076 goto done;
6077
21f581a5 6078 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6079
0d86df80
MC		 6080 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6081 goto done;
cf7a7298 6082
0d86df80
MC		 6083 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6084 struct tg3_rx_buffer_desc *rxd;
6085
6086 rxd = &tpr->rx_jmb[i].std;
6087 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6088 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6089 RXD_FLAG_JUMBO;
6090 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6091 (i << RXD_OPAQUE_INDEX_SHIFT));
6092 }
6093
6094 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6095 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
5129c3a3
MC		 6096 netdev_warn(tp->dev,
6097 "Using a smaller RX jumbo ring. Only %d "
6098 "out of %d buffers were allocated "
6099 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 6100 if (i == 0)
6101 goto initfail;
6102 tp->rx_jumbo_pending = i;
6103 break;
1da177e4
LT		 6104 }
6105 }
cf7a7298
MC		 6106
6107done:
32d8c572 6108 return 0;
cf7a7298
MC		 6109
6110initfail:
21f581a5 6111 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6112 return -ENOMEM;
1da177e4
LT		 6113}
6114
21f581a5
MC		 6115static void tg3_rx_prodring_fini(struct tg3 *tp,
6116 struct tg3_rx_prodring_set *tpr)
1da177e4 6117{
21f581a5
MC		 6118 kfree(tpr->rx_std_buffers);
6119 tpr->rx_std_buffers = NULL;
6120 kfree(tpr->rx_jmb_buffers);
6121 tpr->rx_jmb_buffers = NULL;
6122 if (tpr->rx_std) {
1da177e4 6123 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6124 tpr->rx_std, tpr->rx_std_mapping);
6125 tpr->rx_std = NULL;
1da177e4 6126 }
21f581a5 6127 if (tpr->rx_jmb) {
1da177e4 6128 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6129 tpr->rx_jmb, tpr->rx_jmb_mapping);
6130 tpr->rx_jmb = NULL;
1da177e4 6131 }
cf7a7298
MC		 6132}
6133
21f581a5
MC		 6134static int tg3_rx_prodring_init(struct tg3 *tp,
6135 struct tg3_rx_prodring_set *tpr)
cf7a7298 6136{
2b2cdb65 6137 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6138 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6139 return -ENOMEM;
6140
21f581a5
MC		 6141 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6142 &tpr->rx_std_mapping);
6143 if (!tpr->rx_std)
cf7a7298
MC		 6144 goto err_out;
6145
6146 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6147 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6148 GFP_KERNEL);
6149 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6150 goto err_out;
6151
21f581a5
MC		 6152 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6153 TG3_RX_JUMBO_RING_BYTES,
6154 &tpr->rx_jmb_mapping);
6155 if (!tpr->rx_jmb)
cf7a7298
MC		 6156 goto err_out;
6157 }
6158
6159 return 0;
6160
6161err_out:
21f581a5 6162 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6163 return -ENOMEM;
6164}
6165
6166/* Free up pending packets in all rx/tx rings.
6167 *
6168 * The chip has been shut down and the driver detached from
6169 * the networking, so no interrupts or new tx packets will
6170 * end up in the driver. tp->{tx,}lock is not held and we are not
6171 * in an interrupt context and thus may sleep.
6172 */
6173static void tg3_free_rings(struct tg3 *tp)
6174{
f77a6a8e 6175 int i, j;
cf7a7298 6176
f77a6a8e
MC		 6177 for (j = 0; j < tp->irq_cnt; j++) {
6178 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6179
0c1d0e2b
MC		 6180 if (!tnapi->tx_buffers)
6181 continue;
6182
f77a6a8e 6183 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6184 struct ring_info *txp;
f77a6a8e 6185 struct sk_buff *skb;
f4188d8a 6186 unsigned int k;
cf7a7298 6187
f77a6a8e
MC		 6188 txp = &tnapi->tx_buffers[i];
6189 skb = txp->skb;
cf7a7298 6190
f77a6a8e
MC		 6191 if (skb == NULL) {
6192 i++;
6193 continue;
6194 }
cf7a7298 6195
f4188d8a
AD		 6196 pci_unmap_single(tp->pdev,
6197 pci_unmap_addr(txp, mapping),
6198 skb_headlen(skb),
6199 PCI_DMA_TODEVICE);
f77a6a8e 6200 txp->skb = NULL;
cf7a7298 6201
f4188d8a
AD		 6202 i++;
6203
6204 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6205 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6206 pci_unmap_page(tp->pdev,
6207 pci_unmap_addr(txp, mapping),
6208 skb_shinfo(skb)->frags[k].size,
6209 PCI_DMA_TODEVICE);
6210 i++;
6211 }
f77a6a8e
MC		 6212
6213 dev_kfree_skb_any(skb);
6214 }
cf7a7298 6215
e4af1af9 6216 tg3_rx_prodring_free(tp, &tp->prodring[j]);
2b2cdb65 6217 }
cf7a7298
MC		 6218}
6219
6220/* Initialize tx/rx rings for packet processing.
6221 *
6222 * The chip has been shut down and the driver detached from
6223 * the networking, so no interrupts or new tx packets will
6224 * end up in the driver. tp->{tx,}lock are held and thus
6225 * we may not sleep.
6226 */
6227static int tg3_init_rings(struct tg3 *tp)
6228{
f77a6a8e 6229 int i;
72334482 6230
cf7a7298
MC		 6231 /* Free up all the SKBs. */
6232 tg3_free_rings(tp);
6233
f77a6a8e
MC		 6234 for (i = 0; i < tp->irq_cnt; i++) {
6235 struct tg3_napi *tnapi = &tp->napi[i];
6236
6237 tnapi->last_tag = 0;
6238 tnapi->last_irq_tag = 0;
6239 tnapi->hw_status->status = 0;
6240 tnapi->hw_status->status_tag = 0;
6241 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6242
f77a6a8e
MC		 6243 tnapi->tx_prod = 0;
6244 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6245 if (tnapi->tx_ring)
6246 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6247
6248 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6249 if (tnapi->rx_rcb)
6250 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 6251
e4af1af9
MC		 6252 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6253 tg3_free_rings(tp);
2b2cdb65 6254 return -ENOMEM;
e4af1af9 6255 }
f77a6a8e 6256 }
72334482 6257
2b2cdb65 6258 return 0;
cf7a7298
MC		 6259}
6260
6261/*
6262 * Must not be invoked with interrupt sources disabled and
6263 * the hardware shutdown down.
6264 */
6265static void tg3_free_consistent(struct tg3 *tp)
6266{
f77a6a8e 6267 int i;
898a56f8 6268
f77a6a8e
MC		 6269 for (i = 0; i < tp->irq_cnt; i++) {
6270 struct tg3_napi *tnapi = &tp->napi[i];
6271
6272 if (tnapi->tx_ring) {
6273 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6274 tnapi->tx_ring, tnapi->tx_desc_mapping);
6275 tnapi->tx_ring = NULL;
6276 }
6277
6278 kfree(tnapi->tx_buffers);
6279 tnapi->tx_buffers = NULL;
6280
6281 if (tnapi->rx_rcb) {
6282 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6283 tnapi->rx_rcb,
6284 tnapi->rx_rcb_mapping);
6285 tnapi->rx_rcb = NULL;
6286 }
6287
6288 if (tnapi->hw_status) {
6289 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6290 tnapi->hw_status,
6291 tnapi->status_mapping);
6292 tnapi->hw_status = NULL;
6293 }
1da177e4 6294 }
f77a6a8e 6295
1da177e4
LT		 6296 if (tp->hw_stats) {
6297 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6298 tp->hw_stats, tp->stats_mapping);
6299 tp->hw_stats = NULL;
6300 }
f77a6a8e 6301
e4af1af9 6302 for (i = 0; i < tp->irq_cnt; i++)
2b2cdb65 6303 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6304}
6305
6306/*
6307 * Must not be invoked with interrupt sources disabled and
6308 * the hardware shutdown down. Can sleep.
6309 */
6310static int tg3_alloc_consistent(struct tg3 *tp)
6311{
f77a6a8e 6312 int i;
898a56f8 6313
e4af1af9 6314 for (i = 0; i < tp->irq_cnt; i++) {
2b2cdb65
MC		 6315 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6316 goto err_out;
6317 }
1da177e4 6318
f77a6a8e
MC		 6319 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6320 sizeof(struct tg3_hw_stats),
6321 &tp->stats_mapping);
6322 if (!tp->hw_stats)
1da177e4
LT		 6323 goto err_out;
6324
f77a6a8e 6325 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6326
f77a6a8e
MC		 6327 for (i = 0; i < tp->irq_cnt; i++) {
6328 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6329 struct tg3_hw_status *sblk;
1da177e4 6330
f77a6a8e
MC		 6331 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6332 TG3_HW_STATUS_SIZE,
6333 &tnapi->status_mapping);
6334 if (!tnapi->hw_status)
6335 goto err_out;
898a56f8 6336
f77a6a8e 6337 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6338 sblk = tnapi->hw_status;
6339
19cfaecc
MC		 6340 /* If multivector TSS is enabled, vector 0 does not handle
6341 * tx interrupts. Don't allocate any resources for it.
6342 */
6343 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6344 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6345 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6346 TG3_TX_RING_SIZE,
6347 GFP_KERNEL);
6348 if (!tnapi->tx_buffers)
6349 goto err_out;
6350
6351 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6352 TG3_TX_RING_BYTES,
6353 &tnapi->tx_desc_mapping);
6354 if (!tnapi->tx_ring)
6355 goto err_out;
6356 }
6357
8d9d7cfc
MC		 6358 /*
6359 * When RSS is enabled, the status block format changes
6360 * slightly. The "rx_jumbo_consumer", "reserved",
6361 * and "rx_mini_consumer" members get mapped to the
6362 * other three rx return ring producer indexes.
6363 */
6364 switch (i) {
6365 default:
6366 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6367 break;
6368 case 2:
6369 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6370 break;
6371 case 3:
6372 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6373 break;
6374 case 4:
6375 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6376 break;
6377 }
72334482 6378
e4af1af9 6379 tnapi->prodring = &tp->prodring[i];
b196c7e4 6380
0c1d0e2b
MC		 6381 /*
6382 * If multivector RSS is enabled, vector 0 does not handle
6383 * rx or tx interrupts. Don't allocate any resources for it.
6384 */
6385 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6386 continue;
6387
f77a6a8e
MC		 6388 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6389 TG3_RX_RCB_RING_BYTES(tp),
6390 &tnapi->rx_rcb_mapping);
6391 if (!tnapi->rx_rcb)
6392 goto err_out;
72334482 6393
f77a6a8e 6394 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6395 }
1da177e4
LT		 6396
6397 return 0;
6398
6399err_out:
6400 tg3_free_consistent(tp);
6401 return -ENOMEM;
6402}
6403
6404#define MAX_WAIT_CNT 1000
6405
6406/* To stop a block, clear the enable bit and poll till it
6407 * clears. tp->lock is held.
6408 */
b3b7d6be 6409static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6410{
6411 unsigned int i;
6412 u32 val;
6413
6414 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6415 switch (ofs) {
6416 case RCVLSC_MODE:
6417 case DMAC_MODE:
6418 case MBFREE_MODE:
6419 case BUFMGR_MODE:
6420 case MEMARB_MODE:
6421 /* We can't enable/disable these bits of the
6422 * 5705/5750, just say success.
6423 */
6424 return 0;
6425
6426 default:
6427 break;
855e1111 6428 }
1da177e4
LT		 6429 }
6430
6431 val = tr32(ofs);
6432 val &= ~enable_bit;
6433 tw32_f(ofs, val);
6434
6435 for (i = 0; i < MAX_WAIT_CNT; i++) {
6436 udelay(100);
6437 val = tr32(ofs);
6438 if ((val & enable_bit) == 0)
6439 break;
6440 }
6441
b3b7d6be 6442 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 6443 dev_err(&tp->pdev->dev,
6444 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6445 ofs, enable_bit);
1da177e4
LT		 6446 return -ENODEV;
6447 }
6448
6449 return 0;
6450}
6451
6452/* tp->lock is held. */
b3b7d6be 6453static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6454{
6455 int i, err;
6456
6457 tg3_disable_ints(tp);
6458
6459 tp->rx_mode &= ~RX_MODE_ENABLE;
6460 tw32_f(MAC_RX_MODE, tp->rx_mode);
6461 udelay(10);
6462
b3b7d6be
DM		 6463 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6464 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6465 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6466 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6467 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6468 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6469
6470 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6471 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6472 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6473 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6474 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6475 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6476 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6477
6478 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6479 tw32_f(MAC_MODE, tp->mac_mode);
6480 udelay(40);
6481
6482 tp->tx_mode &= ~TX_MODE_ENABLE;
6483 tw32_f(MAC_TX_MODE, tp->tx_mode);
6484
6485 for (i = 0; i < MAX_WAIT_CNT; i++) {
6486 udelay(100);
6487 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6488 break;
6489 }
6490 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 6491 dev_err(&tp->pdev->dev,
6492 "%s timed out, TX_MODE_ENABLE will not clear "
6493 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 6494 err |= -ENODEV;
1da177e4
LT		 6495 }
6496
e6de8ad1 6497 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6498 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6499 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6500
6501 tw32(FTQ_RESET, 0xffffffff);
6502 tw32(FTQ_RESET, 0x00000000);
6503
b3b7d6be
DM		 6504 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6505 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6506
f77a6a8e
MC		 6507 for (i = 0; i < tp->irq_cnt; i++) {
6508 struct tg3_napi *tnapi = &tp->napi[i];
6509 if (tnapi->hw_status)
6510 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6511 }
1da177e4
LT		 6512 if (tp->hw_stats)
6513 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6514
1da177e4
LT		 6515 return err;
6516}
6517
0d3031d9
MC		 6518static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6519{
6520 int i;
6521 u32 apedata;
6522
6523 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6524 if (apedata != APE_SEG_SIG_MAGIC)
6525 return;
6526
6527 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6528 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6529 return;
6530
6531 /* Wait for up to 1 millisecond for APE to service previous event. */
6532 for (i = 0; i < 10; i++) {
6533 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6534 return;
6535
6536 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6537
6538 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6539 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6540 event | APE_EVENT_STATUS_EVENT_PENDING);
6541
6542 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6543
6544 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6545 break;
6546
6547 udelay(100);
6548 }
6549
6550 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6551 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6552}
6553
6554static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6555{
6556 u32 event;
6557 u32 apedata;
6558
6559 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6560 return;
6561
6562 switch (kind) {
33f401ae
MC		 6563 case RESET_KIND_INIT:
6564 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6565 APE_HOST_SEG_SIG_MAGIC);
6566 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6567 APE_HOST_SEG_LEN_MAGIC);
6568 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6569 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6570 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6571 APE_HOST_DRIVER_ID_MAGIC);
6572 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6573 APE_HOST_BEHAV_NO_PHYLOCK);
6574
6575 event = APE_EVENT_STATUS_STATE_START;
6576 break;
6577 case RESET_KIND_SHUTDOWN:
6578 /* With the interface we are currently using,
6579 * APE does not track driver state. Wiping
6580 * out the HOST SEGMENT SIGNATURE forces
6581 * the APE to assume OS absent status.
6582 */
6583 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
b2aee154 6584
33f401ae
MC		 6585 event = APE_EVENT_STATUS_STATE_UNLOAD;
6586 break;
6587 case RESET_KIND_SUSPEND:
6588 event = APE_EVENT_STATUS_STATE_SUSPEND;
6589 break;
6590 default:
6591 return;
0d3031d9
MC		 6592 }
6593
6594 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6595
6596 tg3_ape_send_event(tp, event);
6597}
6598
1da177e4
LT		 6599/* tp->lock is held. */
6600static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6601{
f49639e6
DM		 6602 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6603 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6604
6605 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6606 switch (kind) {
6607 case RESET_KIND_INIT:
6608 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6609 DRV_STATE_START);
6610 break;
6611
6612 case RESET_KIND_SHUTDOWN:
6613 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6614 DRV_STATE_UNLOAD);
6615 break;
6616
6617 case RESET_KIND_SUSPEND:
6618 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6619 DRV_STATE_SUSPEND);
6620 break;
6621
6622 default:
6623 break;
855e1111 6624 }
1da177e4 6625 }
0d3031d9
MC		 6626
6627 if (kind == RESET_KIND_INIT ||
6628 kind == RESET_KIND_SUSPEND)
6629 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6630}
6631
6632/* tp->lock is held. */
6633static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6634{
6635 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6636 switch (kind) {
6637 case RESET_KIND_INIT:
6638 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6639 DRV_STATE_START_DONE);
6640 break;
6641
6642 case RESET_KIND_SHUTDOWN:
6643 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6644 DRV_STATE_UNLOAD_DONE);
6645 break;
6646
6647 default:
6648 break;
855e1111 6649 }
1da177e4 6650 }
0d3031d9
MC		 6651
6652 if (kind == RESET_KIND_SHUTDOWN)
6653 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6654}
6655
6656/* tp->lock is held. */
6657static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6658{
6659 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6660 switch (kind) {
6661 case RESET_KIND_INIT:
6662 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6663 DRV_STATE_START);
6664 break;
6665
6666 case RESET_KIND_SHUTDOWN:
6667 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6668 DRV_STATE_UNLOAD);
6669 break;
6670
6671 case RESET_KIND_SUSPEND:
6672 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6673 DRV_STATE_SUSPEND);
6674 break;
6675
6676 default:
6677 break;
855e1111 6678 }
1da177e4
LT		 6679 }
6680}
6681
7a6f4369
MC		 6682static int tg3_poll_fw(struct tg3 *tp)
6683{
6684 int i;
6685 u32 val;
6686
b5d3772c 6687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6688 /* Wait up to 20ms for init done. */
6689 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6690 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6691 return 0;
0ccead18 6692 udelay(100);
b5d3772c
MC		 6693 }
6694 return -ENODEV;
6695 }
6696
7a6f4369
MC		 6697 /* Wait for firmware initialization to complete. */
6698 for (i = 0; i < 100000; i++) {
6699 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6700 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6701 break;
6702 udelay(10);
6703 }
6704
6705 /* Chip might not be fitted with firmware. Some Sun onboard
6706 * parts are configured like that. So don't signal the timeout
6707 * of the above loop as an error, but do report the lack of
6708 * running firmware once.
6709 */
6710 if (i >= 100000 &&
6711 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6712 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6713
05dbe005 6714 netdev_info(tp->dev, "No firmware running\n");
7a6f4369
MC		 6715 }
6716
6b10c165
MC		 6717 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6718 /* The 57765 A0 needs a little more
6719 * time to do some important work.
6720 */
6721 mdelay(10);
6722 }
6723
7a6f4369
MC		 6724 return 0;
6725}
6726
ee6a99b5
MC		 6727/* Save PCI command register before chip reset */
6728static void tg3_save_pci_state(struct tg3 *tp)
6729{
8a6eac90 6730 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6731}
6732
6733/* Restore PCI state after chip reset */
6734static void tg3_restore_pci_state(struct tg3 *tp)
6735{
6736 u32 val;
6737
6738 /* Re-enable indirect register accesses. */
6739 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6740 tp->misc_host_ctrl);
6741
6742 /* Set MAX PCI retry to zero. */
6743 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6744 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6745 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6746 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6747 /* Allow reads and writes to the APE register and memory space. */
6748 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6749 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6750 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6751 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6752
8a6eac90 6753 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6754
fcb389df
MC		 6755 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6756 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6757 pcie_set_readrq(tp->pdev, 4096);
6758 else {
6759 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6760 tp->pci_cacheline_sz);
6761 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6762 tp->pci_lat_timer);
6763 }
114342f2 6764 }
5f5c51e3 6765
ee6a99b5 6766 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6767 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6768 u16 pcix_cmd;
6769
6770 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6771 &pcix_cmd);
6772 pcix_cmd &= ~PCI_X_CMD_ERO;
6773 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6774 pcix_cmd);
6775 }
ee6a99b5
MC		 6776
6777 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6778
6779 /* Chip reset on 5780 will reset MSI enable bit,
6780 * so need to restore it.
6781 */
6782 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6783 u16 ctrl;
6784
6785 pci_read_config_word(tp->pdev,
6786 tp->msi_cap + PCI_MSI_FLAGS,
6787 &ctrl);
6788 pci_write_config_word(tp->pdev,
6789 tp->msi_cap + PCI_MSI_FLAGS,
6790 ctrl | PCI_MSI_FLAGS_ENABLE);
6791 val = tr32(MSGINT_MODE);
6792 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6793 }
6794 }
6795}
6796
1da177e4
LT		 6797static void tg3_stop_fw(struct tg3 *);
6798
6799/* tp->lock is held. */
6800static int tg3_chip_reset(struct tg3 *tp)
6801{
6802 u32 val;
1ee582d8 6803 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6804 int i, err;
1da177e4 6805
f49639e6
DM		 6806 tg3_nvram_lock(tp);
6807
77b483f1
MC		 6808 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6809
f49639e6
DM		 6810 /* No matching tg3_nvram_unlock() after this because
6811 * chip reset below will undo the nvram lock.
6812 */
6813 tp->nvram_lock_cnt = 0;
1da177e4 6814
ee6a99b5
MC		 6815 /* GRC_MISC_CFG core clock reset will clear the memory
6816 * enable bit in PCI register 4 and the MSI enable bit
6817 * on some chips, so we save relevant registers here.
6818 */
6819 tg3_save_pci_state(tp);
6820
d9ab5ad1 6821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6822 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6823 tw32(GRC_FASTBOOT_PC, 0);
6824
1da177e4
LT		 6825 /*
6826 * We must avoid the readl() that normally takes place.
6827 * It locks machines, causes machine checks, and other
6828 * fun things. So, temporarily disable the 5701
6829 * hardware workaround, while we do the reset.
6830 */
1ee582d8
MC		 6831 write_op = tp->write32;
6832 if (write_op == tg3_write_flush_reg32)
6833 tp->write32 = tg3_write32;
1da177e4 6834
d18edcb2
MC		 6835 /* Prevent the irq handler from reading or writing PCI registers
6836 * during chip reset when the memory enable bit in the PCI command
6837 * register may be cleared. The chip does not generate interrupt
6838 * at this time, but the irq handler may still be called due to irq
6839 * sharing or irqpoll.
6840 */
6841 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6842 for (i = 0; i < tp->irq_cnt; i++) {
6843 struct tg3_napi *tnapi = &tp->napi[i];
6844 if (tnapi->hw_status) {
6845 tnapi->hw_status->status = 0;
6846 tnapi->hw_status->status_tag = 0;
6847 }
6848 tnapi->last_tag = 0;
6849 tnapi->last_irq_tag = 0;
b8fa2f3a 6850 }
d18edcb2 6851 smp_mb();
4f125f42
MC		 6852
6853 for (i = 0; i < tp->irq_cnt; i++)
6854 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6855
255ca311
MC		 6856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6857 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6858 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6859 }
6860
1da177e4
LT		 6861 /* do the reset */
6862 val = GRC_MISC_CFG_CORECLK_RESET;
6863
6864 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6865 if (tr32(0x7e2c) == 0x60) {
6866 tw32(0x7e2c, 0x20);
6867 }
6868 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6869 tw32(GRC_MISC_CFG, (1 << 29));
6870 val |= (1 << 29);
6871 }
6872 }
6873
b5d3772c
MC		 6874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6875 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6876 tw32(GRC_VCPU_EXT_CTRL,
6877 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6878 }
6879
1da177e4
LT		 6880 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6881 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6882 tw32(GRC_MISC_CFG, val);
6883
1ee582d8
MC		 6884 /* restore 5701 hardware bug workaround write method */
6885 tp->write32 = write_op;
1da177e4
LT		 6886
6887 /* Unfortunately, we have to delay before the PCI read back.
6888 * Some 575X chips even will not respond to a PCI cfg access
6889 * when the reset command is given to the chip.
6890 *
6891 * How do these hardware designers expect things to work
6892 * properly if the PCI write is posted for a long period
6893 * of time? It is always necessary to have some method by
6894 * which a register read back can occur to push the write
6895 * out which does the reset.
6896 *
6897 * For most tg3 variants the trick below was working.
6898 * Ho hum...
6899 */
6900 udelay(120);
6901
6902 /* Flush PCI posted writes. The normal MMIO registers
6903 * are inaccessible at this time so this is the only
6904 * way to make this reliably (actually, this is no longer
6905 * the case, see above). I tried to use indirect
6906 * register read/write but this upset some 5701 variants.
6907 */
6908 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6909
6910 udelay(120);
6911
5e7dfd0f 6912 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6913 u16 val16;
6914
1da177e4
LT		 6915 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6916 int i;
6917 u32 cfg_val;
6918
6919 /* Wait for link training to complete. */
6920 for (i = 0; i < 5000; i++)
6921 udelay(100);
6922
6923 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6924 pci_write_config_dword(tp->pdev, 0xc4,
6925 cfg_val | (1 << 15));
6926 }
5e7dfd0f 6927
e7126997
MC		 6928 /* Clear the "no snoop" and "relaxed ordering" bits. */
6929 pci_read_config_word(tp->pdev,
6930 tp->pcie_cap + PCI_EXP_DEVCTL,
6931 &val16);
6932 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6933 PCI_EXP_DEVCTL_NOSNOOP_EN);
6934 /*
6935 * Older PCIe devices only support the 128 byte
6936 * MPS setting. Enforce the restriction.
5e7dfd0f 6937 */
e7126997
MC		 6938 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6939 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6940 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6941 pci_write_config_word(tp->pdev,
6942 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6943 val16);
5e7dfd0f
MC		 6944
6945 pcie_set_readrq(tp->pdev, 4096);
6946
6947 /* Clear error status */
6948 pci_write_config_word(tp->pdev,
6949 tp->pcie_cap + PCI_EXP_DEVSTA,
6950 PCI_EXP_DEVSTA_CED |
6951 PCI_EXP_DEVSTA_NFED |
6952 PCI_EXP_DEVSTA_FED |
6953 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6954 }
6955
ee6a99b5 6956 tg3_restore_pci_state(tp);
1da177e4 6957
d18edcb2
MC		 6958 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6959
ee6a99b5
MC		 6960 val = 0;
6961 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6962 val = tr32(MEMARB_MODE);
ee6a99b5 6963 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6964
6965 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6966 tg3_stop_fw(tp);
6967 tw32(0x5000, 0x400);
6968 }
6969
6970 tw32(GRC_MODE, tp->grc_mode);
6971
6972 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6973 val = tr32(0xc4);
1da177e4
LT		 6974
6975 tw32(0xc4, val | (1 << 15));
6976 }
6977
6978 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6980 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6981 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6982 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6983 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6984 }
6985
6986 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6987 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6988 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6989 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6990 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6991 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6992 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6993 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6994 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6995 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6996 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6997 } else
6998 tw32_f(MAC_MODE, 0);
6999 udelay(40);
7000
77b483f1
MC		 7001 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7002
7a6f4369
MC		 7003 err = tg3_poll_fw(tp);
7004 if (err)
7005 return err;
1da177e4 7006
0a9140cf
MC		 7007 tg3_mdio_start(tp);
7008
52cdf852
MC		 7009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7010 u8 phy_addr;
7011
7012 phy_addr = tp->phy_addr;
7013 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7014
7015 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7016 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7017 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7018 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7019 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7020 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7021 udelay(10);
7022
7023 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7024 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7025 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7026 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7027 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7028 udelay(10);
7029
7030 tp->phy_addr = phy_addr;
7031 }
7032
1da177e4 7033 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 7034 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7035 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 7036 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7037 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 7038 val = tr32(0x7c00);
1da177e4
LT		 7039
7040 tw32(0x7c00, val | (1 << 25));
7041 }
7042
7043 /* Reprobe ASF enable state. */
7044 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7045 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7046 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7047 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7048 u32 nic_cfg;
7049
7050 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7051 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7052 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 7053 tp->last_event_jiffies = jiffies;
cbf46853 7054 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7055 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7056 }
7057 }
7058
7059 return 0;
7060}
7061
7062/* tp->lock is held. */
7063static void tg3_stop_fw(struct tg3 *tp)
7064{
0d3031d9
MC		 7065 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7066 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7067 /* Wait for RX cpu to ACK the previous event. */
7068 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7069
7070 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7071
7072 tg3_generate_fw_event(tp);
1da177e4 7073
7c5026aa
MC		 7074 /* Wait for RX cpu to ACK this event. */
7075 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7076 }
7077}
7078
7079/* tp->lock is held. */
944d980e 7080static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7081{
7082 int err;
7083
7084 tg3_stop_fw(tp);
7085
944d980e 7086 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7087
b3b7d6be 7088 tg3_abort_hw(tp, silent);
1da177e4
LT		 7089 err = tg3_chip_reset(tp);
7090
daba2a63
MC		 7091 __tg3_set_mac_addr(tp, 0);
7092
944d980e
MC		 7093 tg3_write_sig_legacy(tp, kind);
7094 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7095
7096 if (err)
7097 return err;
7098
7099 return 0;
7100}
7101
1da177e4
LT		 7102#define RX_CPU_SCRATCH_BASE 0x30000
7103#define RX_CPU_SCRATCH_SIZE 0x04000
7104#define TX_CPU_SCRATCH_BASE 0x34000
7105#define TX_CPU_SCRATCH_SIZE 0x04000
7106
7107/* tp->lock is held. */
7108static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7109{
7110 int i;
7111
5d9428de
ES		 7112 BUG_ON(offset == TX_CPU_BASE &&
7113 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7114
b5d3772c
MC		 7115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7116 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7117
7118 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7119 return 0;
7120 }
1da177e4
LT		 7121 if (offset == RX_CPU_BASE) {
7122 for (i = 0; i < 10000; i++) {
7123 tw32(offset + CPU_STATE, 0xffffffff);
7124 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7125 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7126 break;
7127 }
7128
7129 tw32(offset + CPU_STATE, 0xffffffff);
7130 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7131 udelay(10);
7132 } else {
7133 for (i = 0; i < 10000; i++) {
7134 tw32(offset + CPU_STATE, 0xffffffff);
7135 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7136 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7137 break;
7138 }
7139 }
7140
7141 if (i >= 10000) {
05dbe005
JP		 7142 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7143 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
1da177e4
LT		 7144 return -ENODEV;
7145 }
ec41c7df
MC		 7146
7147 /* Clear firmware's nvram arbitration. */
7148 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7149 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7150 return 0;
7151}
7152
7153struct fw_info {
077f849d
JSR		 7154 unsigned int fw_base;
7155 unsigned int fw_len;
7156 const __be32 *fw_data;
1da177e4
LT		 7157};
7158
7159/* tp->lock is held. */
7160static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7161 int cpu_scratch_size, struct fw_info *info)
7162{
ec41c7df 7163 int err, lock_err, i;
1da177e4
LT		 7164 void (*write_op)(struct tg3 *, u32, u32);
7165
7166 if (cpu_base == TX_CPU_BASE &&
7167 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5129c3a3
MC		 7168 netdev_err(tp->dev,
7169 "%s: Trying to load TX cpu firmware which is 5705\n",
05dbe005 7170 __func__);
1da177e4
LT		 7171 return -EINVAL;
7172 }
7173
7174 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7175 write_op = tg3_write_mem;
7176 else
7177 write_op = tg3_write_indirect_reg32;
7178
1b628151
MC		 7179 /* It is possible that bootcode is still loading at this point.
7180 * Get the nvram lock first before halting the cpu.
7181 */
ec41c7df 7182 lock_err = tg3_nvram_lock(tp);
1da177e4 7183 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7184 if (!lock_err)
7185 tg3_nvram_unlock(tp);
1da177e4
LT		 7186 if (err)
7187 goto out;
7188
7189 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7190 write_op(tp, cpu_scratch_base + i, 0);
7191 tw32(cpu_base + CPU_STATE, 0xffffffff);
7192 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7193 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7194 write_op(tp, (cpu_scratch_base +
077f849d 7195 (info->fw_base & 0xffff) +
1da177e4 7196 (i * sizeof(u32))),
077f849d 7197 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7198
7199 err = 0;
7200
7201out:
1da177e4
LT		 7202 return err;
7203}
7204
7205/* tp->lock is held. */
7206static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7207{
7208 struct fw_info info;
077f849d 7209 const __be32 *fw_data;
1da177e4
LT		 7210 int err, i;
7211
077f849d
JSR		 7212 fw_data = (void *)tp->fw->data;
7213
7214 /* Firmware blob starts with version numbers, followed by
7215 start address and length. We are setting complete length.
7216 length = end_address_of_bss - start_address_of_text.
7217 Remainder is the blob to be loaded contiguously
7218 from start address. */
7219
7220 info.fw_base = be32_to_cpu(fw_data[1]);
7221 info.fw_len = tp->fw->size - 12;
7222 info.fw_data = &fw_data[3];
1da177e4
LT		 7223
7224 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7225 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7226 &info);
7227 if (err)
7228 return err;
7229
7230 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7231 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7232 &info);
7233 if (err)
7234 return err;
7235
7236 /* Now startup only the RX cpu. */
7237 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7238 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7239
7240 for (i = 0; i < 5; i++) {
077f849d 7241 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7242 break;
7243 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7244 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7245 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7246 udelay(1000);
7247 }
7248 if (i >= 5) {
5129c3a3
MC		 7249 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7250 "should be %08x\n", __func__,
05dbe005 7251 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
1da177e4
LT		 7252 return -ENODEV;
7253 }
7254 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7255 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7256
7257 return 0;
7258}
7259
1da177e4 7260/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7261
7262/* tp->lock is held. */
7263static int tg3_load_tso_firmware(struct tg3 *tp)
7264{
7265 struct fw_info info;
077f849d 7266 const __be32 *fw_data;
1da177e4
LT		 7267 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7268 int err, i;
7269
7270 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7271 return 0;
7272
077f849d
JSR		 7273 fw_data = (void *)tp->fw->data;
7274
7275 /* Firmware blob starts with version numbers, followed by
7276 start address and length. We are setting complete length.
7277 length = end_address_of_bss - start_address_of_text.
7278 Remainder is the blob to be loaded contiguously
7279 from start address. */
7280
7281 info.fw_base = be32_to_cpu(fw_data[1]);
7282 cpu_scratch_size = tp->fw_len;
7283 info.fw_len = tp->fw->size - 12;
7284 info.fw_data = &fw_data[3];
7285
1da177e4 7286 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7287 cpu_base = RX_CPU_BASE;
7288 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7289 } else {
1da177e4
LT		 7290 cpu_base = TX_CPU_BASE;
7291 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7292 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7293 }
7294
7295 err = tg3_load_firmware_cpu(tp, cpu_base,
7296 cpu_scratch_base, cpu_scratch_size,
7297 &info);
7298 if (err)
7299 return err;
7300
7301 /* Now startup the cpu. */
7302 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7303 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7304
7305 for (i = 0; i < 5; i++) {
077f849d 7306 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7307 break;
7308 tw32(cpu_base + CPU_STATE, 0xffffffff);
7309 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7310 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7311 udelay(1000);
7312 }
7313 if (i >= 5) {
5129c3a3
MC		 7314 netdev_err(tp->dev,
7315 "%s fails to set CPU PC, is %08x should be %08x\n",
05dbe005 7316 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
1da177e4
LT		 7317 return -ENODEV;
7318 }
7319 tw32(cpu_base + CPU_STATE, 0xffffffff);
7320 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7321 return 0;
7322}
7323
1da177e4 7324
1da177e4
LT		 7325static int tg3_set_mac_addr(struct net_device *dev, void *p)
7326{
7327 struct tg3 *tp = netdev_priv(dev);
7328 struct sockaddr *addr = p;
986e0aeb 7329 int err = 0, skip_mac_1 = 0;
1da177e4 7330
f9804ddb
MC		 7331 if (!is_valid_ether_addr(addr->sa_data))
7332 return -EINVAL;
7333
1da177e4
LT		 7334 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7335
e75f7c90
MC		 7336 if (!netif_running(dev))
7337 return 0;
7338
58712ef9 7339 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7340 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7341
986e0aeb
MC		 7342 addr0_high = tr32(MAC_ADDR_0_HIGH);
7343 addr0_low = tr32(MAC_ADDR_0_LOW);
7344 addr1_high = tr32(MAC_ADDR_1_HIGH);
7345 addr1_low = tr32(MAC_ADDR_1_LOW);
7346
7347 /* Skip MAC addr 1 if ASF is using it. */
7348 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7349 !(addr1_high == 0 && addr1_low == 0))
7350 skip_mac_1 = 1;
58712ef9 7351 }
986e0aeb
MC		 7352 spin_lock_bh(&tp->lock);
7353 __tg3_set_mac_addr(tp, skip_mac_1);
7354 spin_unlock_bh(&tp->lock);
1da177e4 7355
b9ec6c1b 7356 return err;
1da177e4
LT		 7357}
7358
7359/* tp->lock is held. */
7360static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7361 dma_addr_t mapping, u32 maxlen_flags,
7362 u32 nic_addr)
7363{
7364 tg3_write_mem(tp,
7365 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7366 ((u64) mapping >> 32));
7367 tg3_write_mem(tp,
7368 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7369 ((u64) mapping & 0xffffffff));
7370 tg3_write_mem(tp,
7371 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7372 maxlen_flags);
7373
7374 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7375 tg3_write_mem(tp,
7376 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7377 nic_addr);
7378}
7379
7380static void __tg3_set_rx_mode(struct net_device *);
d244c892 7381static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7382{
b6080e12
MC		 7383 int i;
7384
19cfaecc 7385 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7386 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7387 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7388 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7389 } else {
7390 tw32(HOSTCC_TXCOL_TICKS, 0);
7391 tw32(HOSTCC_TXMAX_FRAMES, 0);
7392 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7393 }
b6080e12 7394
19cfaecc
MC		 7395 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7396 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7397 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7398 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7399 } else {
b6080e12
MC		 7400 tw32(HOSTCC_RXCOL_TICKS, 0);
7401 tw32(HOSTCC_RXMAX_FRAMES, 0);
7402 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7403 }
b6080e12 7404
15f9850d
DM		 7405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7406 u32 val = ec->stats_block_coalesce_usecs;
7407
b6080e12
MC		 7408 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7409 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7410
15f9850d
DM		 7411 if (!netif_carrier_ok(tp->dev))
7412 val = 0;
7413
7414 tw32(HOSTCC_STAT_COAL_TICKS, val);
7415 }
b6080e12
MC		 7416
7417 for (i = 0; i < tp->irq_cnt - 1; i++) {
7418 u32 reg;
7419
7420 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7421 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7422 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7423 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7424 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7425 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7426
7427 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7428 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7429 tw32(reg, ec->tx_coalesce_usecs);
7430 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7431 tw32(reg, ec->tx_max_coalesced_frames);
7432 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7433 tw32(reg, ec->tx_max_coalesced_frames_irq);
7434 }
b6080e12
MC		 7435 }
7436
7437 for (; i < tp->irq_max - 1; i++) {
7438 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7439 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7440 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7441
7442 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7443 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7444 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7445 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7446 }
b6080e12 7447 }
15f9850d 7448}
1da177e4 7449
2d31ecaf
MC		 7450/* tp->lock is held. */
7451static void tg3_rings_reset(struct tg3 *tp)
7452{
7453 int i;
f77a6a8e 7454 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7455 struct tg3_napi *tnapi = &tp->napi[0];
7456
7457 /* Disable all transmit rings but the first. */
7458 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7459 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7460 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7461 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7462 else
7463 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7464
7465 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7466 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7467 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7468 BDINFO_FLAGS_DISABLED);
7469
7470
7471 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7473 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7474 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7475 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7476 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7478 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7479 else
7480 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7481
7482 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7483 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7484 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7485 BDINFO_FLAGS_DISABLED);
7486
7487 /* Disable interrupts */
7488 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7489
7490 /* Zero mailbox registers. */
f77a6a8e
MC		 7491 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7492 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7493 tp->napi[i].tx_prod = 0;
7494 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7495 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7496 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7497 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7498 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7499 }
c2353a32
MC		 7500 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7501 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7502 } else {
7503 tp->napi[0].tx_prod = 0;
7504 tp->napi[0].tx_cons = 0;
7505 tw32_mailbox(tp->napi[0].prodmbox, 0);
7506 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7507 }
2d31ecaf
MC		 7508
7509 /* Make sure the NIC-based send BD rings are disabled. */
7510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7511 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7512 for (i = 0; i < 16; i++)
7513 tw32_tx_mbox(mbox + i * 8, 0);
7514 }
7515
7516 txrcb = NIC_SRAM_SEND_RCB;
7517 rxrcb = NIC_SRAM_RCV_RET_RCB;
7518
7519 /* Clear status block in ram. */
7520 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7521
7522 /* Set status block DMA address */
7523 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7524 ((u64) tnapi->status_mapping >> 32));
7525 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7526 ((u64) tnapi->status_mapping & 0xffffffff));
7527
f77a6a8e
MC		 7528 if (tnapi->tx_ring) {
7529 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7530 (TG3_TX_RING_SIZE <<
7531 BDINFO_FLAGS_MAXLEN_SHIFT),
7532 NIC_SRAM_TX_BUFFER_DESC);
7533 txrcb += TG3_BDINFO_SIZE;
7534 }
7535
7536 if (tnapi->rx_rcb) {
7537 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7538 (TG3_RX_RCB_RING_SIZE(tp) <<
7539 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7540 rxrcb += TG3_BDINFO_SIZE;
7541 }
7542
7543 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7544
f77a6a8e
MC		 7545 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7546 u64 mapping = (u64)tnapi->status_mapping;
7547 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7548 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7549
7550 /* Clear status block in ram. */
7551 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7552
19cfaecc
MC		 7553 if (tnapi->tx_ring) {
7554 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7555 (TG3_TX_RING_SIZE <<
7556 BDINFO_FLAGS_MAXLEN_SHIFT),
7557 NIC_SRAM_TX_BUFFER_DESC);
7558 txrcb += TG3_BDINFO_SIZE;
7559 }
f77a6a8e
MC		 7560
7561 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7562 (TG3_RX_RCB_RING_SIZE(tp) <<
7563 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7564
7565 stblk += 8;
f77a6a8e
MC		 7566 rxrcb += TG3_BDINFO_SIZE;
7567 }
2d31ecaf
MC		 7568}
7569
1da177e4 7570/* tp->lock is held. */
8e7a22e3 7571static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7572{
7573 u32 val, rdmac_mode;
7574 int i, err, limit;
21f581a5 7575 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7576
7577 tg3_disable_ints(tp);
7578
7579 tg3_stop_fw(tp);
7580
7581 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7582
859a5887 7583 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
e6de8ad1 7584 tg3_abort_hw(tp, 1);
1da177e4 7585
603f1173 7586 if (reset_phy)
d4d2c558
MC		 7587 tg3_phy_reset(tp);
7588
1da177e4
LT		 7589 err = tg3_chip_reset(tp);
7590 if (err)
7591 return err;
7592
7593 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7594
bcb37f6c 7595 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7596 val = tr32(TG3_CPMU_CTRL);
7597 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7598 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7599
7600 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7601 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7602 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7603 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7604
7605 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7606 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7607 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7608 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7609
7610 val = tr32(TG3_CPMU_HST_ACC);
7611 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7612 val |= CPMU_HST_ACC_MACCLK_6_25;
7613 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7614 }
7615
33466d93
MC		 7616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7617 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7618 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7619 PCIE_PWR_MGMT_L1_THRESH_4MS;
7620 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7621
7622 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7623 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7624
7625 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7626
f40386c8
MC		 7627 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7628 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7629 }
7630
614b0590
MC		 7631 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7632 u32 grc_mode = tr32(GRC_MODE);
7633
7634 /* Access the lower 1K of PL PCIE block registers. */
7635 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7636 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7637
7638 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7639 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7640 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7641
7642 tw32(GRC_MODE, grc_mode);
7643 }
7644
cea46462
MC		 7645 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7646 u32 grc_mode = tr32(GRC_MODE);
7647
7648 /* Access the lower 1K of PL PCIE block registers. */
7649 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7650 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7651
7652 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7653 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7654 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7655
7656 tw32(GRC_MODE, grc_mode);
7657 }
7658
1da177e4
LT		 7659 /* This works around an issue with Athlon chipsets on
7660 * B3 tigon3 silicon. This bit has no effect on any
7661 * other revision. But do not set this on PCI Express
795d01c5 7662 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7663 */
795d01c5
MC		 7664 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7665 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7666 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7667 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7668 }
1da177e4
LT		 7669
7670 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7671 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7672 val = tr32(TG3PCI_PCISTATE);
7673 val |= PCISTATE_RETRY_SAME_DMA;
7674 tw32(TG3PCI_PCISTATE, val);
7675 }
7676
0d3031d9
MC		 7677 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7678 /* Allow reads and writes to the
7679 * APE register and memory space.
7680 */
7681 val = tr32(TG3PCI_PCISTATE);
7682 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7683 PCISTATE_ALLOW_APE_SHMEM_WR;
7684 tw32(TG3PCI_PCISTATE, val);
7685 }
7686
1da177e4
LT		 7687 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7688 /* Enable some hw fixes. */
7689 val = tr32(TG3PCI_MSI_DATA);
7690 val |= (1 << 26) | (1 << 28) | (1 << 29);
7691 tw32(TG3PCI_MSI_DATA, val);
7692 }
7693
7694 /* Descriptor ring init may make accesses to the
7695 * NIC SRAM area to setup the TX descriptors, so we
7696 * can only do this after the hardware has been
7697 * successfully reset.
7698 */
32d8c572
MC		 7699 err = tg3_init_rings(tp);
7700 if (err)
7701 return err;
1da177e4 7702
b703df6f
MC		 7703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7705 val = tr32(TG3PCI_DMA_RW_CTRL) &
7706 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7707 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7708 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7709 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7710 /* This value is determined during the probe time DMA
7711 * engine test, tg3_test_dma.
7712 */
7713 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7714 }
1da177e4
LT		 7715
7716 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7717 GRC_MODE_4X_NIC_SEND_RINGS |
7718 GRC_MODE_NO_TX_PHDR_CSUM |
7719 GRC_MODE_NO_RX_PHDR_CSUM);
7720 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7721
7722 /* Pseudo-header checksum is done by hardware logic and not
7723 * the offload processers, so make the chip do the pseudo-
7724 * header checksums on receive. For transmit it is more
7725 * convenient to do the pseudo-header checksum in software
7726 * as Linux does that on transmit for us in all cases.
7727 */
7728 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7729
7730 tw32(GRC_MODE,
7731 tp->grc_mode |
7732 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7733
7734 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7735 val = tr32(GRC_MISC_CFG);
7736 val &= ~0xff;
7737 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7738 tw32(GRC_MISC_CFG, val);
7739
7740 /* Initialize MBUF/DESC pool. */
cbf46853 7741 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7742 /* Do nothing. */
7743 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7744 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7746 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7747 else
7748 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7749 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7750 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
859a5887 7751 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
1da177e4
LT		 7752 int fw_len;
7753
077f849d 7754 fw_len = tp->fw_len;
1da177e4
LT		 7755 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7756 tw32(BUFMGR_MB_POOL_ADDR,
7757 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7758 tw32(BUFMGR_MB_POOL_SIZE,
7759 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7760 }
1da177e4 7761
0f893dc6 7762 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7763 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7764 tp->bufmgr_config.mbuf_read_dma_low_water);
7765 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7766 tp->bufmgr_config.mbuf_mac_rx_low_water);
7767 tw32(BUFMGR_MB_HIGH_WATER,
7768 tp->bufmgr_config.mbuf_high_water);
7769 } else {
7770 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7771 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7772 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7773 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7774 tw32(BUFMGR_MB_HIGH_WATER,
7775 tp->bufmgr_config.mbuf_high_water_jumbo);
7776 }
7777 tw32(BUFMGR_DMA_LOW_WATER,
7778 tp->bufmgr_config.dma_low_water);
7779 tw32(BUFMGR_DMA_HIGH_WATER,
7780 tp->bufmgr_config.dma_high_water);
7781
7782 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7783 for (i = 0; i < 2000; i++) {
7784 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7785 break;
7786 udelay(10);
7787 }
7788 if (i >= 2000) {
05dbe005 7789 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 7790 return -ENODEV;
7791 }
7792
7793 /* Setup replenish threshold. */
f92905de
MC		 7794 val = tp->rx_pending / 8;
7795 if (val == 0)
7796 val = 1;
7797 else if (val > tp->rx_std_max_post)
7798 val = tp->rx_std_max_post;
b5d3772c
MC		 7799 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7800 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7801 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7802
7803 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7804 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7805 }
f92905de
MC		 7806
7807 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7808
7809 /* Initialize TG3_BDINFO's at:
7810 * RCVDBDI_STD_BD: standard eth size rx ring
7811 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7812 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7813 *
7814 * like so:
7815 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7816 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7817 * ring attribute flags
7818 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7819 *
7820 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7821 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7822 *
7823 * The size of each ring is fixed in the firmware, but the location is
7824 * configurable.
7825 */
7826 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7827 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7828 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7829 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7830 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7831 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7832 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7833
fdb72b38
MC		 7834 /* Disable the mini ring */
7835 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7836 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7837 BDINFO_FLAGS_DISABLED);
7838
fdb72b38
MC		 7839 /* Program the jumbo buffer descriptor ring control
7840 * blocks on those devices that have them.
7841 */
8f666b07 7842 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7843 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7844 /* Setup replenish threshold. */
7845 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7846
0f893dc6 7847 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7848 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7849 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7850 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7851 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7852 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7853 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7854 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7855 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7856 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7857 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7858 } else {
7859 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7860 BDINFO_FLAGS_DISABLED);
7861 }
7862
b703df6f
MC		 7863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7865 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7866 (RX_STD_MAX_SIZE << 2);
7867 else
7868 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7869 } else
7870 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7871
7872 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7873
411da640 7874 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7875 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7876
411da640 7877 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7878 tp->rx_jumbo_pending : 0;
66711e66 7879 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7880
b703df6f
MC		 7881 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7883 tw32(STD_REPLENISH_LWM, 32);
7884 tw32(JMB_REPLENISH_LWM, 16);
7885 }
7886
2d31ecaf
MC		 7887 tg3_rings_reset(tp);
7888
1da177e4 7889 /* Initialize MAC address and backoff seed. */
986e0aeb 7890 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7891
7892 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7893 tw32(MAC_RX_MTU_SIZE,
7894 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7895
7896 /* The slot time is changed by tg3_setup_phy if we
7897 * run at gigabit with half duplex.
7898 */
7899 tw32(MAC_TX_LENGTHS,
7900 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7901 (6 << TX_LENGTHS_IPG_SHIFT) |
7902 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7903
7904 /* Receive rules. */
7905 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7906 tw32(RCVLPC_CONFIG, 0x0181);
7907
7908 /* Calculate RDMAC_MODE setting early, we need it to determine
7909 * the RCVLPC_STATE_ENABLE mask.
7910 */
7911 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7912 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7913 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7914 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7915 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7916
0339e4e3
MC		 7917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7918 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7919
57e6983c 7920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7923 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7924 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7925 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7926
85e94ced
MC		 7927 /* If statement applies to 5705 and 5750 PCI devices only */
7928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7929 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7930 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7931 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7933 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7934 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7935 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7936 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7937 }
7938 }
7939
85e94ced
MC		 7940 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7941 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7942
1da177e4 7943 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7944 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7945
e849cdc3
MC		 7946 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7949 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7950
7951 /* Receive/send statistics. */
1661394e
MC		 7952 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7953 val = tr32(RCVLPC_STATS_ENABLE);
7954 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7955 tw32(RCVLPC_STATS_ENABLE, val);
7956 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7957 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7958 val = tr32(RCVLPC_STATS_ENABLE);
7959 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7960 tw32(RCVLPC_STATS_ENABLE, val);
7961 } else {
7962 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7963 }
7964 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7965 tw32(SNDDATAI_STATSENAB, 0xffffff);
7966 tw32(SNDDATAI_STATSCTRL,
7967 (SNDDATAI_SCTRL_ENABLE |
7968 SNDDATAI_SCTRL_FASTUPD));
7969
7970 /* Setup host coalescing engine. */
7971 tw32(HOSTCC_MODE, 0);
7972 for (i = 0; i < 2000; i++) {
7973 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7974 break;
7975 udelay(10);
7976 }
7977
d244c892 7978 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7979
1da177e4
LT		 7980 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7981 /* Status/statistics block address. See tg3_timer,
7982 * the tg3_periodic_fetch_stats call there, and
7983 * tg3_get_stats to see how this works for 5705/5750 chips.
7984 */
1da177e4
LT		 7985 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7986 ((u64) tp->stats_mapping >> 32));
7987 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7988 ((u64) tp->stats_mapping & 0xffffffff));
7989 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7990
1da177e4 7991 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7992
7993 /* Clear statistics and status block memory areas */
7994 for (i = NIC_SRAM_STATS_BLK;
7995 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7996 i += sizeof(u32)) {
7997 tg3_write_mem(tp, i, 0);
7998 udelay(40);
7999 }
1da177e4
LT		 8000 }
8001
8002 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8003
8004 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8005 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8006 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8007 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8008
c94e3941
MC		 8009 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8010 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8011 /* reset to prevent losing 1st rx packet intermittently */
8012 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8013 udelay(10);
8014 }
8015
3bda1258
MC		 8016 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8017 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8018 else
8019 tp->mac_mode = 0;
8020 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 8021 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 8022 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8023 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8024 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8025 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 8026 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8027 udelay(40);
8028
314fba34 8029 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 8030 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 8031 * register to preserve the GPIO settings for LOMs. The GPIOs,
8032 * whether used as inputs or outputs, are set by boot code after
8033 * reset.
8034 */
9d26e213 8035 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 8036 u32 gpio_mask;
8037
9d26e213
MC		 8038 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8039 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8040 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 8041
8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8043 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8044 GRC_LCLCTRL_GPIO_OUTPUT3;
8045
af36e6b6
MC		 8046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8047 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8048
aaf84465 8049 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 8050 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8051
8052 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 8053 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8054 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8055 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 8056 }
1da177e4
LT		 8057 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8058 udelay(100);
8059
baf8a94a
MC		 8060 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8061 val = tr32(MSGINT_MODE);
8062 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8063 tw32(MSGINT_MODE, val);
8064 }
8065
1da177e4
LT		 8066 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8067 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8068 udelay(40);
8069 }
8070
8071 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8072 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8073 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8074 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8075 WDMAC_MODE_LNGREAD_ENAB);
8076
85e94ced
MC		 8077 /* If statement applies to 5705 and 5750 PCI devices only */
8078 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8079 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8081 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8082 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8083 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8084 /* nothing */
8085 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8086 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8087 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8088 val |= WDMAC_MODE_RX_ACCEL;
8089 }
8090 }
8091
d9ab5ad1 8092 /* Enable host coalescing bug fix */
321d32a0 8093 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8094 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8095
788a035e
MC		 8096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8097 val |= WDMAC_MODE_BURST_ALL_DATA;
8098
1da177e4
LT		 8099 tw32_f(WDMAC_MODE, val);
8100 udelay(40);
8101
9974a356
MC		 8102 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8103 u16 pcix_cmd;
8104
8105 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8106 &pcix_cmd);
1da177e4 8107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8108 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8109 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8110 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8111 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8112 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8113 }
9974a356
MC		 8114 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8115 pcix_cmd);
1da177e4
LT		 8116 }
8117
8118 tw32_f(RDMAC_MODE, rdmac_mode);
8119 udelay(40);
8120
8121 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8122 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8123 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8124
8125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8126 tw32(SNDDATAC_MODE,
8127 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8128 else
8129 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8130
1da177e4
LT		 8131 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8132 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8133 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8134 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8135 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8136 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8137 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8138 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8139 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8140 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8141 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8142
8143 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8144 err = tg3_load_5701_a0_firmware_fix(tp);
8145 if (err)
8146 return err;
8147 }
8148
1da177e4
LT		 8149 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8150 err = tg3_load_tso_firmware(tp);
8151 if (err)
8152 return err;
8153 }
1da177e4
LT		 8154
8155 tp->tx_mode = TX_MODE_ENABLE;
8156 tw32_f(MAC_TX_MODE, tp->tx_mode);
8157 udelay(100);
8158
baf8a94a
MC		 8159 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8160 u32 reg = MAC_RSS_INDIR_TBL_0;
8161 u8 *ent = (u8 *)&val;
8162
8163 /* Setup the indirection table */
8164 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8165 int idx = i % sizeof(val);
8166
8167 ent[idx] = i % (tp->irq_cnt - 1);
8168 if (idx == sizeof(val) - 1) {
8169 tw32(reg, val);
8170 reg += 4;
8171 }
8172 }
8173
8174 /* Setup the "secret" hash key. */
8175 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8176 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8177 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8178 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8179 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8180 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8181 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8182 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8183 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8184 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8185 }
8186
1da177e4 8187 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8188 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8189 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8190
baf8a94a
MC		 8191 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8192 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8193 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8194 RX_MODE_RSS_IPV6_HASH_EN |
8195 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8196 RX_MODE_RSS_IPV4_HASH_EN |
8197 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8198
1da177e4
LT		 8199 tw32_f(MAC_RX_MODE, tp->rx_mode);
8200 udelay(10);
8201
1da177e4
LT		 8202 tw32(MAC_LED_CTRL, tp->led_ctrl);
8203
8204 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8205 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8206 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8207 udelay(10);
8208 }
8209 tw32_f(MAC_RX_MODE, tp->rx_mode);
8210 udelay(10);
8211
8212 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8213 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8214 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8215 /* Set drive transmission level to 1.2V */
8216 /* only if the signal pre-emphasis bit is not set */
8217 val = tr32(MAC_SERDES_CFG);
8218 val &= 0xfffff000;
8219 val |= 0x880;
8220 tw32(MAC_SERDES_CFG, val);
8221 }
8222 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8223 tw32(MAC_SERDES_CFG, 0x616000);
8224 }
8225
8226 /* Prevent chip from dropping frames when flow control
8227 * is enabled.
8228 */
666bc831
MC		 8229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8230 val = 1;
8231 else
8232 val = 2;
8233 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8234
8235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8236 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8237 /* Use hardware link auto-negotiation */
8238 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8239 }
8240
d4d2c558
MC		 8241 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8242 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8243 u32 tmp;
8244
8245 tmp = tr32(SERDES_RX_CTRL);
8246 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8247 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8248 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8249 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8250 }
8251
dd477003
MC		 8252 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8253 if (tp->link_config.phy_is_low_power) {
8254 tp->link_config.phy_is_low_power = 0;
8255 tp->link_config.speed = tp->link_config.orig_speed;
8256 tp->link_config.duplex = tp->link_config.orig_duplex;
8257 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8258 }
1da177e4 8259
dd477003
MC		 8260 err = tg3_setup_phy(tp, 0);
8261 if (err)
8262 return err;
1da177e4 8263
dd477003 8264 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8265 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8266 u32 tmp;
8267
8268 /* Clear CRC stats. */
8269 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8270 tg3_writephy(tp, MII_TG3_TEST1,
8271 tmp | MII_TG3_TEST1_CRC_EN);
8272 tg3_readphy(tp, 0x14, &tmp);
8273 }
1da177e4
LT		 8274 }
8275 }
8276
8277 __tg3_set_rx_mode(tp->dev);
8278
8279 /* Initialize receive rules. */
8280 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8281 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8282 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8283 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8284
4cf78e4f 8285 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8286 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8287 limit = 8;
8288 else
8289 limit = 16;
8290 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8291 limit -= 4;
8292 switch (limit) {
8293 case 16:
8294 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8295 case 15:
8296 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8297 case 14:
8298 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8299 case 13:
8300 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8301 case 12:
8302 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8303 case 11:
8304 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8305 case 10:
8306 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8307 case 9:
8308 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8309 case 8:
8310 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8311 case 7:
8312 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8313 case 6:
8314 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8315 case 5:
8316 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8317 case 4:
8318 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8319 case 3:
8320 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8321 case 2:
8322 case 1:
8323
8324 default:
8325 break;
855e1111 8326 }
1da177e4 8327
9ce768ea
MC		 8328 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8329 /* Write our heartbeat update interval to APE. */
8330 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8331 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8332
1da177e4
LT		 8333 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8334
1da177e4
LT		 8335 return 0;
8336}
8337
8338/* Called at device open time to get the chip ready for
8339 * packet processing. Invoked with tp->lock held.
8340 */
8e7a22e3 8341static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8342{
1da177e4
LT		 8343 tg3_switch_clocks(tp);
8344
8345 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8346
2f751b67 8347 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8348}
8349
8350#define TG3_STAT_ADD32(PSTAT, REG) \
8351do { u32 __val = tr32(REG); \
8352 (PSTAT)->low += __val; \
8353 if ((PSTAT)->low < __val) \
8354 (PSTAT)->high += 1; \
8355} while (0)
8356
8357static void tg3_periodic_fetch_stats(struct tg3 *tp)
8358{
8359 struct tg3_hw_stats *sp = tp->hw_stats;
8360
8361 if (!netif_carrier_ok(tp->dev))
8362 return;
8363
8364 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8365 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8366 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8367 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8368 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8369 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8370 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8371 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8372 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8373 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8374 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8375 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8376 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8377
8378 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8379 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8380 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8381 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8382 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8383 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8384 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8385 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8386 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8387 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8388 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8389 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8390 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8391 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8392
8393 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8394 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8395 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8396}
8397
8398static void tg3_timer(unsigned long __opaque)
8399{
8400 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8401
f475f163
MC		 8402 if (tp->irq_sync)
8403 goto restart_timer;
8404
f47c11ee 8405 spin_lock(&tp->lock);
1da177e4 8406
fac9b83e
DM		 8407 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8408 /* All of this garbage is because when using non-tagged
8409 * IRQ status the mailbox/status_block protocol the chip
8410 * uses with the cpu is race prone.
8411 */
898a56f8 8412 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8413 tw32(GRC_LOCAL_CTRL,
8414 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8415 } else {
8416 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8417 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8418 }
1da177e4 8419
fac9b83e
DM		 8420 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8421 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8422 spin_unlock(&tp->lock);
fac9b83e
DM		 8423 schedule_work(&tp->reset_task);
8424 return;
8425 }
1da177e4
LT		 8426 }
8427
1da177e4
LT		 8428 /* This part only runs once per second. */
8429 if (!--tp->timer_counter) {
fac9b83e
DM		 8430 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8431 tg3_periodic_fetch_stats(tp);
8432
1da177e4
LT		 8433 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8434 u32 mac_stat;
8435 int phy_event;
8436
8437 mac_stat = tr32(MAC_STATUS);
8438
8439 phy_event = 0;
8440 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8441 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8442 phy_event = 1;
8443 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8444 phy_event = 1;
8445
8446 if (phy_event)
8447 tg3_setup_phy(tp, 0);
8448 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8449 u32 mac_stat = tr32(MAC_STATUS);
8450 int need_setup = 0;
8451
8452 if (netif_carrier_ok(tp->dev) &&
8453 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8454 need_setup = 1;
8455 }
8456 if (! netif_carrier_ok(tp->dev) &&
8457 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8458 MAC_STATUS_SIGNAL_DET))) {
8459 need_setup = 1;
8460 }
8461 if (need_setup) {
3d3ebe74
MC		 8462 if (!tp->serdes_counter) {
8463 tw32_f(MAC_MODE,
8464 (tp->mac_mode &
8465 ~MAC_MODE_PORT_MODE_MASK));
8466 udelay(40);
8467 tw32_f(MAC_MODE, tp->mac_mode);
8468 udelay(40);
8469 }
1da177e4
LT		 8470 tg3_setup_phy(tp, 0);
8471 }
747e8f8b
MC		 8472 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8473 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8474
8475 tp->timer_counter = tp->timer_multiplier;
8476 }
8477
130b8e4d
MC		 8478 /* Heartbeat is only sent once every 2 seconds.
8479 *
8480 * The heartbeat is to tell the ASF firmware that the host
8481 * driver is still alive. In the event that the OS crashes,
8482 * ASF needs to reset the hardware to free up the FIFO space
8483 * that may be filled with rx packets destined for the host.
8484 * If the FIFO is full, ASF will no longer function properly.
8485 *
8486 * Unintended resets have been reported on real time kernels
8487 * where the timer doesn't run on time. Netpoll will also have
8488 * same problem.
8489 *
8490 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8491 * to check the ring condition when the heartbeat is expiring
8492 * before doing the reset. This will prevent most unintended
8493 * resets.
8494 */
1da177e4 8495 if (!--tp->asf_counter) {
bc7959b2
MC		 8496 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8497 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8498 tg3_wait_for_event_ack(tp);
8499
bbadf503 8500 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8501 FWCMD_NICDRV_ALIVE3);
bbadf503 8502 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 8503 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8504 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 8505
8506 tg3_generate_fw_event(tp);
1da177e4
LT		 8507 }
8508 tp->asf_counter = tp->asf_multiplier;
8509 }
8510
f47c11ee 8511 spin_unlock(&tp->lock);
1da177e4 8512
f475f163 8513restart_timer:
1da177e4
LT		 8514 tp->timer.expires = jiffies + tp->timer_offset;
8515 add_timer(&tp->timer);
8516}
8517
4f125f42 8518static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8519{
7d12e780 8520 irq_handler_t fn;
fcfa0a32 8521 unsigned long flags;
4f125f42
MC		 8522 char *name;
8523 struct tg3_napi *tnapi = &tp->napi[irq_num];
8524
8525 if (tp->irq_cnt == 1)
8526 name = tp->dev->name;
8527 else {
8528 name = &tnapi->irq_lbl[0];
8529 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8530 name[IFNAMSIZ-1] = 0;
8531 }
fcfa0a32 8532
679563f4 8533 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8534 fn = tg3_msi;
8535 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8536 fn = tg3_msi_1shot;
1fb9df5d 8537 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8538 } else {
8539 fn = tg3_interrupt;
8540 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8541 fn = tg3_interrupt_tagged;
1fb9df5d 8542 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8543 }
4f125f42
MC		 8544
8545 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8546}
8547
7938109f
MC		 8548static int tg3_test_interrupt(struct tg3 *tp)
8549{
09943a18 8550 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8551 struct net_device *dev = tp->dev;
b16250e3 8552 int err, i, intr_ok = 0;
f6eb9b1f 8553 u32 val;
7938109f 8554
d4bc3927
MC		 8555 if (!netif_running(dev))
8556 return -ENODEV;
8557
7938109f
MC		 8558 tg3_disable_ints(tp);
8559
4f125f42 8560 free_irq(tnapi->irq_vec, tnapi);
7938109f 8561
f6eb9b1f
MC		 8562 /*
8563 * Turn off MSI one shot mode. Otherwise this test has no
8564 * observable way to know whether the interrupt was delivered.
8565 */
b703df6f
MC		 8566 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8568 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8569 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8570 tw32(MSGINT_MODE, val);
8571 }
8572
4f125f42 8573 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8574 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8575 if (err)
8576 return err;
8577
898a56f8 8578 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8579 tg3_enable_ints(tp);
8580
8581 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8582 tnapi->coal_now);
7938109f
MC		 8583
8584 for (i = 0; i < 5; i++) {
b16250e3
MC		 8585 u32 int_mbox, misc_host_ctrl;
8586
898a56f8 8587 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8588 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8589
8590 if ((int_mbox != 0) ||
8591 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8592 intr_ok = 1;
7938109f 8593 break;
b16250e3
MC		 8594 }
8595
7938109f
MC		 8596 msleep(10);
8597 }
8598
8599 tg3_disable_ints(tp);
8600
4f125f42 8601 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8602
4f125f42 8603 err = tg3_request_irq(tp, 0);
7938109f
MC		 8604
8605 if (err)
8606 return err;
8607
f6eb9b1f
MC		 8608 if (intr_ok) {
8609 /* Reenable MSI one shot mode. */
b703df6f
MC		 8610 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8612 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8613 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8614 tw32(MSGINT_MODE, val);
8615 }
7938109f 8616 return 0;
f6eb9b1f 8617 }
7938109f
MC		 8618
8619 return -EIO;
8620}
8621
8622/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8623 * successfully restored
8624 */
8625static int tg3_test_msi(struct tg3 *tp)
8626{
7938109f
MC		 8627 int err;
8628 u16 pci_cmd;
8629
8630 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8631 return 0;
8632
8633 /* Turn off SERR reporting in case MSI terminates with Master
8634 * Abort.
8635 */
8636 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8637 pci_write_config_word(tp->pdev, PCI_COMMAND,
8638 pci_cmd & ~PCI_COMMAND_SERR);
8639
8640 err = tg3_test_interrupt(tp);
8641
8642 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8643
8644 if (!err)
8645 return 0;
8646
8647 /* other failures */
8648 if (err != -EIO)
8649 return err;
8650
8651 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 8652 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8653 "to INTx mode. Please report this failure to the PCI "
8654 "maintainer and include system chipset information\n");
7938109f 8655
4f125f42 8656 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8657
7938109f
MC		 8658 pci_disable_msi(tp->pdev);
8659
8660 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8661
4f125f42 8662 err = tg3_request_irq(tp, 0);
7938109f
MC		 8663 if (err)
8664 return err;
8665
8666 /* Need to reset the chip because the MSI cycle may have terminated
8667 * with Master Abort.
8668 */
f47c11ee 8669 tg3_full_lock(tp, 1);
7938109f 8670
944d980e 8671 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8672 err = tg3_init_hw(tp, 1);
7938109f 8673
f47c11ee 8674 tg3_full_unlock(tp);
7938109f
MC		 8675
8676 if (err)
4f125f42 8677 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8678
8679 return err;
8680}
8681
9e9fd12d
MC		 8682static int tg3_request_firmware(struct tg3 *tp)
8683{
8684 const __be32 *fw_data;
8685
8686 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 8687 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8688 tp->fw_needed);
9e9fd12d
MC		 8689 return -ENOENT;
8690 }
8691
8692 fw_data = (void *)tp->fw->data;
8693
8694 /* Firmware blob starts with version numbers, followed by
8695 * start address and _full_ length including BSS sections
8696 * (which must be longer than the actual data, of course
8697 */
8698
8699 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8700 if (tp->fw_len < (tp->fw->size - 12)) {
05dbe005
JP		 8701 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8702 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 8703 release_firmware(tp->fw);
8704 tp->fw = NULL;
8705 return -EINVAL;
8706 }
8707
8708 /* We no longer need firmware; we have it. */
8709 tp->fw_needed = NULL;
8710 return 0;
8711}
8712
679563f4
MC		 8713static bool tg3_enable_msix(struct tg3 *tp)
8714{
8715 int i, rc, cpus = num_online_cpus();
8716 struct msix_entry msix_ent[tp->irq_max];
8717
8718 if (cpus == 1)
8719 /* Just fallback to the simpler MSI mode. */
8720 return false;
8721
8722 /*
8723 * We want as many rx rings enabled as there are cpus.
8724 * The first MSIX vector only deals with link interrupts, etc,
8725 * so we add one to the number of vectors we are requesting.
8726 */
8727 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8728
8729 for (i = 0; i < tp->irq_max; i++) {
8730 msix_ent[i].entry = i;
8731 msix_ent[i].vector = 0;
8732 }
8733
8734 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8735 if (rc != 0) {
8736 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8737 return false;
8738 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8739 return false;
05dbe005
JP		 8740 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8741 tp->irq_cnt, rc);
679563f4
MC		 8742 tp->irq_cnt = rc;
8743 }
8744
baf8a94a
MC		 8745 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8746
679563f4
MC		 8747 for (i = 0; i < tp->irq_max; i++)
8748 tp->napi[i].irq_vec = msix_ent[i].vector;
8749
19cfaecc
MC		 8750 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8751 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8752 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8753 } else
8754 tp->dev->real_num_tx_queues = 1;
fe5f5787 8755
679563f4
MC		 8756 return true;
8757}
8758
07b0173c
MC		 8759static void tg3_ints_init(struct tg3 *tp)
8760{
679563f4
MC		 8761 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8762 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8763 /* All MSI supporting chips should support tagged
8764 * status. Assert that this is the case.
8765 */
5129c3a3
MC		 8766 netdev_warn(tp->dev,
8767 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 8768 goto defcfg;
07b0173c 8769 }
4f125f42 8770
679563f4
MC		 8771 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8772 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8773 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8774 pci_enable_msi(tp->pdev) == 0)
8775 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8776
8777 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8778 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8779 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8780 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8781 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8782 }
8783defcfg:
8784 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8785 tp->irq_cnt = 1;
8786 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8787 tp->dev->real_num_tx_queues = 1;
679563f4 8788 }
07b0173c
MC		 8789}
8790
8791static void tg3_ints_fini(struct tg3 *tp)
8792{
679563f4
MC		 8793 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8794 pci_disable_msix(tp->pdev);
8795 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8796 pci_disable_msi(tp->pdev);
8797 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8798 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8799}
8800
1da177e4
LT		 8801static int tg3_open(struct net_device *dev)
8802{
8803 struct tg3 *tp = netdev_priv(dev);
4f125f42 8804 int i, err;
1da177e4 8805
9e9fd12d
MC		 8806 if (tp->fw_needed) {
8807 err = tg3_request_firmware(tp);
8808 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8809 if (err)
8810 return err;
8811 } else if (err) {
05dbe005 8812 netdev_warn(tp->dev, "TSO capability disabled\n");
9e9fd12d
MC		 8813 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8814 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
05dbe005 8815 netdev_notice(tp->dev, "TSO capability restored\n");
9e9fd12d
MC		 8816 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8817 }
8818 }
8819
c49a1561
MC		 8820 netif_carrier_off(tp->dev);
8821
bc1c7567 8822 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8823 if (err)
bc1c7567 8824 return err;
2f751b67
MC		 8825
8826 tg3_full_lock(tp, 0);
bc1c7567 8827
1da177e4
LT		 8828 tg3_disable_ints(tp);
8829 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8830
f47c11ee 8831 tg3_full_unlock(tp);
1da177e4 8832
679563f4
MC		 8833 /*
8834 * Setup interrupts first so we know how
8835 * many NAPI resources to allocate
8836 */
8837 tg3_ints_init(tp);
8838
1da177e4
LT		 8839 /* The placement of this call is tied
8840 * to the setup and use of Host TX descriptors.
8841 */
8842 err = tg3_alloc_consistent(tp);
8843 if (err)
679563f4 8844 goto err_out1;
88b06bc2 8845
fed97810 8846 tg3_napi_enable(tp);
1da177e4 8847
4f125f42
MC		 8848 for (i = 0; i < tp->irq_cnt; i++) {
8849 struct tg3_napi *tnapi = &tp->napi[i];
8850 err = tg3_request_irq(tp, i);
8851 if (err) {
8852 for (i--; i >= 0; i--)
8853 free_irq(tnapi->irq_vec, tnapi);
8854 break;
8855 }
8856 }
1da177e4 8857
07b0173c 8858 if (err)
679563f4 8859 goto err_out2;
bea3348e 8860
f47c11ee 8861 tg3_full_lock(tp, 0);
1da177e4 8862
8e7a22e3 8863 err = tg3_init_hw(tp, 1);
1da177e4 8864 if (err) {
944d980e 8865 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8866 tg3_free_rings(tp);
8867 } else {
fac9b83e
DM		 8868 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8869 tp->timer_offset = HZ;
8870 else
8871 tp->timer_offset = HZ / 10;
8872
8873 BUG_ON(tp->timer_offset > HZ);
8874 tp->timer_counter = tp->timer_multiplier =
8875 (HZ / tp->timer_offset);
8876 tp->asf_counter = tp->asf_multiplier =
28fbef78 8877 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8878
8879 init_timer(&tp->timer);
8880 tp->timer.expires = jiffies + tp->timer_offset;
8881 tp->timer.data = (unsigned long) tp;
8882 tp->timer.function = tg3_timer;
1da177e4
LT		 8883 }
8884
f47c11ee 8885 tg3_full_unlock(tp);
1da177e4 8886
07b0173c 8887 if (err)
679563f4 8888 goto err_out3;
1da177e4 8889
7938109f
MC		 8890 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8891 err = tg3_test_msi(tp);
fac9b83e 8892
7938109f 8893 if (err) {
f47c11ee 8894 tg3_full_lock(tp, 0);
944d980e 8895 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8896 tg3_free_rings(tp);
f47c11ee 8897 tg3_full_unlock(tp);
7938109f 8898
679563f4 8899 goto err_out2;
7938109f 8900 }
fcfa0a32 8901
f6eb9b1f 8902 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8903 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8904 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8905 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8906 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8907
f6eb9b1f
MC		 8908 tw32(PCIE_TRANSACTION_CFG,
8909 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8910 }
7938109f
MC		 8911 }
8912
b02fd9e3
MC		 8913 tg3_phy_start(tp);
8914
f47c11ee 8915 tg3_full_lock(tp, 0);
1da177e4 8916
7938109f
MC		 8917 add_timer(&tp->timer);
8918 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8919 tg3_enable_ints(tp);
8920
f47c11ee 8921 tg3_full_unlock(tp);
1da177e4 8922
fe5f5787 8923 netif_tx_start_all_queues(dev);
1da177e4
LT		 8924
8925 return 0;
07b0173c 8926
679563f4 8927err_out3:
4f125f42
MC		 8928 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8929 struct tg3_napi *tnapi = &tp->napi[i];
8930 free_irq(tnapi->irq_vec, tnapi);
8931 }
07b0173c 8932
679563f4 8933err_out2:
fed97810 8934 tg3_napi_disable(tp);
07b0173c 8935 tg3_free_consistent(tp);
679563f4
MC		 8936
8937err_out1:
8938 tg3_ints_fini(tp);
07b0173c 8939 return err;
1da177e4
LT		 8940}
8941
1da177e4
LT		 8942static struct net_device_stats *tg3_get_stats(struct net_device *);
8943static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8944
8945static int tg3_close(struct net_device *dev)
8946{
4f125f42 8947 int i;
1da177e4
LT		 8948 struct tg3 *tp = netdev_priv(dev);
8949
fed97810 8950 tg3_napi_disable(tp);
28e53bdd 8951 cancel_work_sync(&tp->reset_task);
7faa006f 8952
fe5f5787 8953 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8954
8955 del_timer_sync(&tp->timer);
8956
24bb4fb6
MC		 8957 tg3_phy_stop(tp);
8958
f47c11ee 8959 tg3_full_lock(tp, 1);
1da177e4
LT		 8960
8961 tg3_disable_ints(tp);
8962
944d980e 8963 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8964 tg3_free_rings(tp);
5cf64b8a 8965 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8966
f47c11ee 8967 tg3_full_unlock(tp);
1da177e4 8968
4f125f42
MC		 8969 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8970 struct tg3_napi *tnapi = &tp->napi[i];
8971 free_irq(tnapi->irq_vec, tnapi);
8972 }
07b0173c
MC		 8973
8974 tg3_ints_fini(tp);
1da177e4
LT		 8975
8976 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8977 sizeof(tp->net_stats_prev));
8978 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8979 sizeof(tp->estats_prev));
8980
8981 tg3_free_consistent(tp);
8982
bc1c7567
MC		 8983 tg3_set_power_state(tp, PCI_D3hot);
8984
8985 netif_carrier_off(tp->dev);
8986
1da177e4
LT		 8987 return 0;
8988}
8989
8990static inline unsigned long get_stat64(tg3_stat64_t *val)
8991{
8992 unsigned long ret;
8993
8994#if (BITS_PER_LONG == 32)
8995 ret = val->low;
8996#else
8997 ret = ((u64)val->high << 32) | ((u64)val->low);
8998#endif
8999 return ret;
9000}
9001
816f8b86
SB		 9002static inline u64 get_estat64(tg3_stat64_t *val)
9003{
9004 return ((u64)val->high << 32) | ((u64)val->low);
9005}
9006
1da177e4
LT		 9007static unsigned long calc_crc_errors(struct tg3 *tp)
9008{
9009 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9010
9011 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9012 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9014 u32 val;
9015
f47c11ee 9016 spin_lock_bh(&tp->lock);
569a5df8
MC		 9017 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9018 tg3_writephy(tp, MII_TG3_TEST1,
9019 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9020 tg3_readphy(tp, 0x14, &val);
9021 } else
9022 val = 0;
f47c11ee 9023 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9024
9025 tp->phy_crc_errors += val;
9026
9027 return tp->phy_crc_errors;
9028 }
9029
9030 return get_stat64(&hw_stats->rx_fcs_errors);
9031}
9032
9033#define ESTAT_ADD(member) \
9034 estats->member = old_estats->member + \
816f8b86 9035 get_estat64(&hw_stats->member)
1da177e4
LT		 9036
9037static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9038{
9039 struct tg3_ethtool_stats *estats = &tp->estats;
9040 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9041 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9042
9043 if (!hw_stats)
9044 return old_estats;
9045
9046 ESTAT_ADD(rx_octets);
9047 ESTAT_ADD(rx_fragments);
9048 ESTAT_ADD(rx_ucast_packets);
9049 ESTAT_ADD(rx_mcast_packets);
9050 ESTAT_ADD(rx_bcast_packets);
9051 ESTAT_ADD(rx_fcs_errors);
9052 ESTAT_ADD(rx_align_errors);
9053 ESTAT_ADD(rx_xon_pause_rcvd);
9054 ESTAT_ADD(rx_xoff_pause_rcvd);
9055 ESTAT_ADD(rx_mac_ctrl_rcvd);
9056 ESTAT_ADD(rx_xoff_entered);
9057 ESTAT_ADD(rx_frame_too_long_errors);
9058 ESTAT_ADD(rx_jabbers);
9059 ESTAT_ADD(rx_undersize_packets);
9060 ESTAT_ADD(rx_in_length_errors);
9061 ESTAT_ADD(rx_out_length_errors);
9062 ESTAT_ADD(rx_64_or_less_octet_packets);
9063 ESTAT_ADD(rx_65_to_127_octet_packets);
9064 ESTAT_ADD(rx_128_to_255_octet_packets);
9065 ESTAT_ADD(rx_256_to_511_octet_packets);
9066 ESTAT_ADD(rx_512_to_1023_octet_packets);
9067 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9068 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9069 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9070 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9071 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9072
9073 ESTAT_ADD(tx_octets);
9074 ESTAT_ADD(tx_collisions);
9075 ESTAT_ADD(tx_xon_sent);
9076 ESTAT_ADD(tx_xoff_sent);
9077 ESTAT_ADD(tx_flow_control);
9078 ESTAT_ADD(tx_mac_errors);
9079 ESTAT_ADD(tx_single_collisions);
9080 ESTAT_ADD(tx_mult_collisions);
9081 ESTAT_ADD(tx_deferred);
9082 ESTAT_ADD(tx_excessive_collisions);
9083 ESTAT_ADD(tx_late_collisions);
9084 ESTAT_ADD(tx_collide_2times);
9085 ESTAT_ADD(tx_collide_3times);
9086 ESTAT_ADD(tx_collide_4times);
9087 ESTAT_ADD(tx_collide_5times);
9088 ESTAT_ADD(tx_collide_6times);
9089 ESTAT_ADD(tx_collide_7times);
9090 ESTAT_ADD(tx_collide_8times);
9091 ESTAT_ADD(tx_collide_9times);
9092 ESTAT_ADD(tx_collide_10times);
9093 ESTAT_ADD(tx_collide_11times);
9094 ESTAT_ADD(tx_collide_12times);
9095 ESTAT_ADD(tx_collide_13times);
9096 ESTAT_ADD(tx_collide_14times);
9097 ESTAT_ADD(tx_collide_15times);
9098 ESTAT_ADD(tx_ucast_packets);
9099 ESTAT_ADD(tx_mcast_packets);
9100 ESTAT_ADD(tx_bcast_packets);
9101 ESTAT_ADD(tx_carrier_sense_errors);
9102 ESTAT_ADD(tx_discards);
9103 ESTAT_ADD(tx_errors);
9104
9105 ESTAT_ADD(dma_writeq_full);
9106 ESTAT_ADD(dma_write_prioq_full);
9107 ESTAT_ADD(rxbds_empty);
9108 ESTAT_ADD(rx_discards);
9109 ESTAT_ADD(rx_errors);
9110 ESTAT_ADD(rx_threshold_hit);
9111
9112 ESTAT_ADD(dma_readq_full);
9113 ESTAT_ADD(dma_read_prioq_full);
9114 ESTAT_ADD(tx_comp_queue_full);
9115
9116 ESTAT_ADD(ring_set_send_prod_index);
9117 ESTAT_ADD(ring_status_update);
9118 ESTAT_ADD(nic_irqs);
9119 ESTAT_ADD(nic_avoided_irqs);
9120 ESTAT_ADD(nic_tx_threshold_hit);
9121
9122 return estats;
9123}
9124
9125static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9126{
9127 struct tg3 *tp = netdev_priv(dev);
9128 struct net_device_stats *stats = &tp->net_stats;
9129 struct net_device_stats *old_stats = &tp->net_stats_prev;
9130 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9131
9132 if (!hw_stats)
9133 return old_stats;
9134
9135 stats->rx_packets = old_stats->rx_packets +
9136 get_stat64(&hw_stats->rx_ucast_packets) +
9137 get_stat64(&hw_stats->rx_mcast_packets) +
9138 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9139
1da177e4
LT		 9140 stats->tx_packets = old_stats->tx_packets +
9141 get_stat64(&hw_stats->tx_ucast_packets) +
9142 get_stat64(&hw_stats->tx_mcast_packets) +
9143 get_stat64(&hw_stats->tx_bcast_packets);
9144
9145 stats->rx_bytes = old_stats->rx_bytes +
9146 get_stat64(&hw_stats->rx_octets);
9147 stats->tx_bytes = old_stats->tx_bytes +
9148 get_stat64(&hw_stats->tx_octets);
9149
9150 stats->rx_errors = old_stats->rx_errors +
4f63b877 9151 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9152 stats->tx_errors = old_stats->tx_errors +
9153 get_stat64(&hw_stats->tx_errors) +
9154 get_stat64(&hw_stats->tx_mac_errors) +
9155 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9156 get_stat64(&hw_stats->tx_discards);
9157
9158 stats->multicast = old_stats->multicast +
9159 get_stat64(&hw_stats->rx_mcast_packets);
9160 stats->collisions = old_stats->collisions +
9161 get_stat64(&hw_stats->tx_collisions);
9162
9163 stats->rx_length_errors = old_stats->rx_length_errors +
9164 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9165 get_stat64(&hw_stats->rx_undersize_packets);
9166
9167 stats->rx_over_errors = old_stats->rx_over_errors +
9168 get_stat64(&hw_stats->rxbds_empty);
9169 stats->rx_frame_errors = old_stats->rx_frame_errors +
9170 get_stat64(&hw_stats->rx_align_errors);
9171 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9172 get_stat64(&hw_stats->tx_discards);
9173 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9174 get_stat64(&hw_stats->tx_carrier_sense_errors);
9175
9176 stats->rx_crc_errors = old_stats->rx_crc_errors +
9177 calc_crc_errors(tp);
9178
4f63b877
JL		 9179 stats->rx_missed_errors = old_stats->rx_missed_errors +
9180 get_stat64(&hw_stats->rx_discards);
9181
1da177e4
LT		 9182 return stats;
9183}
9184
9185static inline u32 calc_crc(unsigned char *buf, int len)
9186{
9187 u32 reg;
9188 u32 tmp;
9189 int j, k;
9190
9191 reg = 0xffffffff;
9192
9193 for (j = 0; j < len; j++) {
9194 reg ^= buf[j];
9195
9196 for (k = 0; k < 8; k++) {
9197 tmp = reg & 0x01;
9198
9199 reg >>= 1;
9200
859a5887 9201 if (tmp)
1da177e4 9202 reg ^= 0xedb88320;
1da177e4
LT		 9203 }
9204 }
9205
9206 return ~reg;
9207}
9208
9209static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9210{
9211 /* accept or reject all multicast frames */
9212 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9213 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9214 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9215 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9216}
9217
9218static void __tg3_set_rx_mode(struct net_device *dev)
9219{
9220 struct tg3 *tp = netdev_priv(dev);
9221 u32 rx_mode;
9222
9223 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9224 RX_MODE_KEEP_VLAN_TAG);
9225
9226 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9227 * flag clear.
9228 */
9229#if TG3_VLAN_TAG_USED
9230 if (!tp->vlgrp &&
9231 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9232 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9233#else
9234 /* By definition, VLAN is disabled always in this
9235 * case.
9236 */
9237 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9238 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9239#endif
9240
9241 if (dev->flags & IFF_PROMISC) {
9242 /* Promiscuous mode. */
9243 rx_mode |= RX_MODE_PROMISC;
9244 } else if (dev->flags & IFF_ALLMULTI) {
9245 /* Accept all multicast. */
9246 tg3_set_multi (tp, 1);
4cd24eaf 9247 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 9248 /* Reject all multicast. */
9249 tg3_set_multi (tp, 0);
9250 } else {
9251 /* Accept one or more multicast(s). */
22bedad3 9252 struct netdev_hw_addr *ha;
1da177e4
LT		 9253 u32 mc_filter[4] = { 0, };
9254 u32 regidx;
9255 u32 bit;
9256 u32 crc;
9257
22bedad3
JP		 9258 netdev_for_each_mc_addr(ha, dev) {
9259 crc = calc_crc(ha->addr, ETH_ALEN);
1da177e4
LT		 9260 bit = ~crc & 0x7f;
9261 regidx = (bit & 0x60) >> 5;
9262 bit &= 0x1f;
9263 mc_filter[regidx] |= (1 << bit);
9264 }
9265
9266 tw32(MAC_HASH_REG_0, mc_filter[0]);
9267 tw32(MAC_HASH_REG_1, mc_filter[1]);
9268 tw32(MAC_HASH_REG_2, mc_filter[2]);
9269 tw32(MAC_HASH_REG_3, mc_filter[3]);
9270 }
9271
9272 if (rx_mode != tp->rx_mode) {
9273 tp->rx_mode = rx_mode;
9274 tw32_f(MAC_RX_MODE, rx_mode);
9275 udelay(10);
9276 }
9277}
9278
9279static void tg3_set_rx_mode(struct net_device *dev)
9280{
9281 struct tg3 *tp = netdev_priv(dev);
9282
e75f7c90
MC		 9283 if (!netif_running(dev))
9284 return;
9285
f47c11ee 9286 tg3_full_lock(tp, 0);
1da177e4 9287 __tg3_set_rx_mode(dev);
f47c11ee 9288 tg3_full_unlock(tp);
1da177e4
LT		 9289}
9290
9291#define TG3_REGDUMP_LEN (32 * 1024)
9292
9293static int tg3_get_regs_len(struct net_device *dev)
9294{
9295 return TG3_REGDUMP_LEN;
9296}
9297
9298static void tg3_get_regs(struct net_device *dev,
9299 struct ethtool_regs *regs, void *_p)
9300{
9301 u32 *p = _p;
9302 struct tg3 *tp = netdev_priv(dev);
9303 u8 *orig_p = _p;
9304 int i;
9305
9306 regs->version = 0;
9307
9308 memset(p, 0, TG3_REGDUMP_LEN);
9309
bc1c7567
MC		 9310 if (tp->link_config.phy_is_low_power)
9311 return;
9312
f47c11ee 9313 tg3_full_lock(tp, 0);
1da177e4
LT		 9314
9315#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9316#define GET_REG32_LOOP(base,len) \
9317do { p = (u32 *)(orig_p + (base)); \
9318 for (i = 0; i < len; i += 4) \
9319 __GET_REG32((base) + i); \
9320} while (0)
9321#define GET_REG32_1(reg) \
9322do { p = (u32 *)(orig_p + (reg)); \
9323 __GET_REG32((reg)); \
9324} while (0)
9325
9326 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9327 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9328 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9329 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9330 GET_REG32_1(SNDDATAC_MODE);
9331 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9332 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9333 GET_REG32_1(SNDBDC_MODE);
9334 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9335 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9336 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9337 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9338 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9339 GET_REG32_1(RCVDCC_MODE);
9340 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9341 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9342 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9343 GET_REG32_1(MBFREE_MODE);
9344 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9345 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9346 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9347 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9348 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9349 GET_REG32_1(RX_CPU_MODE);
9350 GET_REG32_1(RX_CPU_STATE);
9351 GET_REG32_1(RX_CPU_PGMCTR);
9352 GET_REG32_1(RX_CPU_HWBKPT);
9353 GET_REG32_1(TX_CPU_MODE);
9354 GET_REG32_1(TX_CPU_STATE);
9355 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9356 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9357 GET_REG32_LOOP(FTQ_RESET, 0x120);
9358 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9359 GET_REG32_1(DMAC_MODE);
9360 GET_REG32_LOOP(GRC_MODE, 0x4c);
9361 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9362 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9363
9364#undef __GET_REG32
9365#undef GET_REG32_LOOP
9366#undef GET_REG32_1
9367
f47c11ee 9368 tg3_full_unlock(tp);
1da177e4
LT		 9369}
9370
9371static int tg3_get_eeprom_len(struct net_device *dev)
9372{
9373 struct tg3 *tp = netdev_priv(dev);
9374
9375 return tp->nvram_size;
9376}
9377
1da177e4
LT		 9378static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9379{
9380 struct tg3 *tp = netdev_priv(dev);
9381 int ret;
9382 u8 *pd;
b9fc7dc5 9383 u32 i, offset, len, b_offset, b_count;
a9dc529d 9384 __be32 val;
1da177e4 9385
df259d8c
MC		 9386 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9387 return -EINVAL;
9388
bc1c7567
MC		 9389 if (tp->link_config.phy_is_low_power)
9390 return -EAGAIN;
9391
1da177e4
LT		 9392 offset = eeprom->offset;
9393 len = eeprom->len;
9394 eeprom->len = 0;
9395
9396 eeprom->magic = TG3_EEPROM_MAGIC;
9397
9398 if (offset & 3) {
9399 /* adjustments to start on required 4 byte boundary */
9400 b_offset = offset & 3;
9401 b_count = 4 - b_offset;
9402 if (b_count > len) {
9403 /* i.e. offset=1 len=2 */
9404 b_count = len;
9405 }
a9dc529d 9406 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9407 if (ret)
9408 return ret;
1da177e4
LT		 9409 memcpy(data, ((char*)&val) + b_offset, b_count);
9410 len -= b_count;
9411 offset += b_count;
c6cdf436 9412 eeprom->len += b_count;
1da177e4
LT		 9413 }
9414
9415 /* read bytes upto the last 4 byte boundary */
9416 pd = &data[eeprom->len];
9417 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9418 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9419 if (ret) {
9420 eeprom->len += i;
9421 return ret;
9422 }
1da177e4
LT		 9423 memcpy(pd + i, &val, 4);
9424 }
9425 eeprom->len += i;
9426
9427 if (len & 3) {
9428 /* read last bytes not ending on 4 byte boundary */
9429 pd = &data[eeprom->len];
9430 b_count = len & 3;
9431 b_offset = offset + len - b_count;
a9dc529d 9432 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9433 if (ret)
9434 return ret;
b9fc7dc5 9435 memcpy(pd, &val, b_count);
1da177e4
LT		 9436 eeprom->len += b_count;
9437 }
9438 return 0;
9439}
9440
6aa20a22 9441static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9442
9443static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9444{
9445 struct tg3 *tp = netdev_priv(dev);
9446 int ret;
b9fc7dc5 9447 u32 offset, len, b_offset, odd_len;
1da177e4 9448 u8 *buf;
a9dc529d 9449 __be32 start, end;
1da177e4 9450
bc1c7567
MC		 9451 if (tp->link_config.phy_is_low_power)
9452 return -EAGAIN;
9453
df259d8c
MC		 9454 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9455 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9456 return -EINVAL;
9457
9458 offset = eeprom->offset;
9459 len = eeprom->len;
9460
9461 if ((b_offset = (offset & 3))) {
9462 /* adjustments to start on required 4 byte boundary */
a9dc529d 9463 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9464 if (ret)
9465 return ret;
1da177e4
LT		 9466 len += b_offset;
9467 offset &= ~3;
1c8594b4
MC		 9468 if (len < 4)
9469 len = 4;
1da177e4
LT		 9470 }
9471
9472 odd_len = 0;
1c8594b4 9473 if (len & 3) {
1da177e4
LT		 9474 /* adjustments to end on required 4 byte boundary */
9475 odd_len = 1;
9476 len = (len + 3) & ~3;
a9dc529d 9477 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9478 if (ret)
9479 return ret;
1da177e4
LT		 9480 }
9481
9482 buf = data;
9483 if (b_offset || odd_len) {
9484 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9485 if (!buf)
1da177e4
LT		 9486 return -ENOMEM;
9487 if (b_offset)
9488 memcpy(buf, &start, 4);
9489 if (odd_len)
9490 memcpy(buf+len-4, &end, 4);
9491 memcpy(buf + b_offset, data, eeprom->len);
9492 }
9493
9494 ret = tg3_nvram_write_block(tp, offset, len, buf);
9495
9496 if (buf != data)
9497 kfree(buf);
9498
9499 return ret;
9500}
9501
9502static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9503{
b02fd9e3
MC		 9504 struct tg3 *tp = netdev_priv(dev);
9505
9506 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9507 struct phy_device *phydev;
b02fd9e3
MC		 9508 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9509 return -EAGAIN;
3f0e3ad7
MC		 9510 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9511 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9512 }
6aa20a22 9513
1da177e4
LT		 9514 cmd->supported = (SUPPORTED_Autoneg);
9515
9516 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9517 cmd->supported |= (SUPPORTED_1000baseT_Half |
9518 SUPPORTED_1000baseT_Full);
9519
ef348144 9520 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9521 cmd->supported |= (SUPPORTED_100baseT_Half |
9522 SUPPORTED_100baseT_Full |
9523 SUPPORTED_10baseT_Half |
9524 SUPPORTED_10baseT_Full |
3bebab59 9525 SUPPORTED_TP);
ef348144
KK		 9526 cmd->port = PORT_TP;
9527 } else {
1da177e4 9528 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9529 cmd->port = PORT_FIBRE;
9530 }
6aa20a22 9531
1da177e4
LT		 9532 cmd->advertising = tp->link_config.advertising;
9533 if (netif_running(dev)) {
9534 cmd->speed = tp->link_config.active_speed;
9535 cmd->duplex = tp->link_config.active_duplex;
9536 }
882e9793 9537 cmd->phy_address = tp->phy_addr;
7e5856bd 9538 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9539 cmd->autoneg = tp->link_config.autoneg;
9540 cmd->maxtxpkt = 0;
9541 cmd->maxrxpkt = 0;
9542 return 0;
9543}
6aa20a22 9544
1da177e4
LT		 9545static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9546{
9547 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9548
b02fd9e3 9549 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9550 struct phy_device *phydev;
b02fd9e3
MC		 9551 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9552 return -EAGAIN;
3f0e3ad7
MC		 9553 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9554 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9555 }
9556
7e5856bd
MC		 9557 if (cmd->autoneg != AUTONEG_ENABLE &&
9558 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9559 return -EINVAL;
7e5856bd
MC		 9560
9561 if (cmd->autoneg == AUTONEG_DISABLE &&
9562 cmd->duplex != DUPLEX_FULL &&
9563 cmd->duplex != DUPLEX_HALF)
37ff238d 9564 return -EINVAL;
1da177e4 9565
7e5856bd
MC		 9566 if (cmd->autoneg == AUTONEG_ENABLE) {
9567 u32 mask = ADVERTISED_Autoneg |
9568 ADVERTISED_Pause |
9569 ADVERTISED_Asym_Pause;
9570
3f07d129 9571 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7e5856bd
MC		 9572 mask |= ADVERTISED_1000baseT_Half |
9573 ADVERTISED_1000baseT_Full;
9574
9575 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9576 mask |= ADVERTISED_100baseT_Half |
9577 ADVERTISED_100baseT_Full |
9578 ADVERTISED_10baseT_Half |
9579 ADVERTISED_10baseT_Full |
9580 ADVERTISED_TP;
9581 else
9582 mask |= ADVERTISED_FIBRE;
9583
9584 if (cmd->advertising & ~mask)
9585 return -EINVAL;
9586
9587 mask &= (ADVERTISED_1000baseT_Half |
9588 ADVERTISED_1000baseT_Full |
9589 ADVERTISED_100baseT_Half |
9590 ADVERTISED_100baseT_Full |
9591 ADVERTISED_10baseT_Half |
9592 ADVERTISED_10baseT_Full);
9593
9594 cmd->advertising &= mask;
9595 } else {
9596 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9597 if (cmd->speed != SPEED_1000)
9598 return -EINVAL;
9599
9600 if (cmd->duplex != DUPLEX_FULL)
9601 return -EINVAL;
9602 } else {
9603 if (cmd->speed != SPEED_100 &&
9604 cmd->speed != SPEED_10)
9605 return -EINVAL;
9606 }
9607 }
9608
f47c11ee 9609 tg3_full_lock(tp, 0);
1da177e4
LT		 9610
9611 tp->link_config.autoneg = cmd->autoneg;
9612 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9613 tp->link_config.advertising = (cmd->advertising |
9614 ADVERTISED_Autoneg);
1da177e4
LT		 9615 tp->link_config.speed = SPEED_INVALID;
9616 tp->link_config.duplex = DUPLEX_INVALID;
9617 } else {
9618 tp->link_config.advertising = 0;
9619 tp->link_config.speed = cmd->speed;
9620 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9621 }
6aa20a22 9622
24fcad6b
MC		 9623 tp->link_config.orig_speed = tp->link_config.speed;
9624 tp->link_config.orig_duplex = tp->link_config.duplex;
9625 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9626
1da177e4
LT		 9627 if (netif_running(dev))
9628 tg3_setup_phy(tp, 1);
9629
f47c11ee 9630 tg3_full_unlock(tp);
6aa20a22 9631
1da177e4
LT		 9632 return 0;
9633}
6aa20a22 9634
1da177e4
LT		 9635static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9636{
9637 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9638
1da177e4
LT		 9639 strcpy(info->driver, DRV_MODULE_NAME);
9640 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9641 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9642 strcpy(info->bus_info, pci_name(tp->pdev));
9643}
6aa20a22 9644
1da177e4
LT		 9645static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9646{
9647 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9648
12dac075
RW		 9649 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9650 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9651 wol->supported = WAKE_MAGIC;
9652 else
9653 wol->supported = 0;
1da177e4 9654 wol->wolopts = 0;
05ac4cb7
MC		 9655 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9656 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9657 wol->wolopts = WAKE_MAGIC;
9658 memset(&wol->sopass, 0, sizeof(wol->sopass));
9659}
6aa20a22 9660
1da177e4
LT		 9661static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9662{
9663 struct tg3 *tp = netdev_priv(dev);
12dac075 9664 struct device *dp = &tp->pdev->dev;
6aa20a22 9665
1da177e4
LT		 9666 if (wol->wolopts & ~WAKE_MAGIC)
9667 return -EINVAL;
9668 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9669 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9670 return -EINVAL;
6aa20a22 9671
f47c11ee 9672 spin_lock_bh(&tp->lock);
12dac075 9673 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9674 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9675 device_set_wakeup_enable(dp, true);
9676 } else {
1da177e4 9677 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9678 device_set_wakeup_enable(dp, false);
9679 }
f47c11ee 9680 spin_unlock_bh(&tp->lock);
6aa20a22 9681
1da177e4
LT		 9682 return 0;
9683}
6aa20a22 9684
1da177e4
LT		 9685static u32 tg3_get_msglevel(struct net_device *dev)
9686{
9687 struct tg3 *tp = netdev_priv(dev);
9688 return tp->msg_enable;
9689}
6aa20a22 9690
1da177e4
LT		 9691static void tg3_set_msglevel(struct net_device *dev, u32 value)
9692{
9693 struct tg3 *tp = netdev_priv(dev);
9694 tp->msg_enable = value;
9695}
6aa20a22 9696
1da177e4
LT		 9697static int tg3_set_tso(struct net_device *dev, u32 value)
9698{
9699 struct tg3 *tp = netdev_priv(dev);
9700
9701 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9702 if (value)
9703 return -EINVAL;
9704 return 0;
9705 }
027455ad 9706 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9707 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9708 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9709 if (value) {
b0026624 9710 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9711 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9712 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9713 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9714 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9717 dev->features |= NETIF_F_TSO_ECN;
9718 } else
9719 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9720 }
1da177e4
LT		 9721 return ethtool_op_set_tso(dev, value);
9722}
6aa20a22 9723
1da177e4
LT		 9724static int tg3_nway_reset(struct net_device *dev)
9725{
9726 struct tg3 *tp = netdev_priv(dev);
1da177e4 9727 int r;
6aa20a22 9728
1da177e4
LT		 9729 if (!netif_running(dev))
9730 return -EAGAIN;
9731
c94e3941
MC		 9732 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9733 return -EINVAL;
9734
b02fd9e3
MC		 9735 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9736 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9737 return -EAGAIN;
3f0e3ad7 9738 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9739 } else {
9740 u32 bmcr;
9741
9742 spin_lock_bh(&tp->lock);
9743 r = -EINVAL;
9744 tg3_readphy(tp, MII_BMCR, &bmcr);
9745 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9746 ((bmcr & BMCR_ANENABLE) ||
9747 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9748 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9749 BMCR_ANENABLE);
9750 r = 0;
9751 }
9752 spin_unlock_bh(&tp->lock);
1da177e4 9753 }
6aa20a22 9754
1da177e4
LT		 9755 return r;
9756}
6aa20a22 9757
1da177e4
LT		 9758static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9759{
9760 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9761
1da177e4
LT		 9762 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9763 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9764 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9765 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9766 else
9767 ering->rx_jumbo_max_pending = 0;
9768
9769 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9770
9771 ering->rx_pending = tp->rx_pending;
9772 ering->rx_mini_pending = 0;
4f81c32b
MC		 9773 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9774 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9775 else
9776 ering->rx_jumbo_pending = 0;
9777
f3f3f27e 9778 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9779}
6aa20a22 9780
1da177e4
LT		 9781static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9782{
9783 struct tg3 *tp = netdev_priv(dev);
646c9edd 9784 int i, irq_sync = 0, err = 0;
6aa20a22 9785
1da177e4
LT		 9786 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9787 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9788 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9789 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9790 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9791 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9792 return -EINVAL;
6aa20a22 9793
bbe832c0 9794 if (netif_running(dev)) {
b02fd9e3 9795 tg3_phy_stop(tp);
1da177e4 9796 tg3_netif_stop(tp);
bbe832c0
MC		 9797 irq_sync = 1;
9798 }
1da177e4 9799
bbe832c0 9800 tg3_full_lock(tp, irq_sync);
6aa20a22 9801
1da177e4
LT		 9802 tp->rx_pending = ering->rx_pending;
9803
9804 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9805 tp->rx_pending > 63)
9806 tp->rx_pending = 63;
9807 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9808
9809 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9810 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9811
9812 if (netif_running(dev)) {
944d980e 9813 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9814 err = tg3_restart_hw(tp, 1);
9815 if (!err)
9816 tg3_netif_start(tp);
1da177e4
LT		 9817 }
9818
f47c11ee 9819 tg3_full_unlock(tp);
6aa20a22 9820
b02fd9e3
MC		 9821 if (irq_sync && !err)
9822 tg3_phy_start(tp);
9823
b9ec6c1b 9824 return err;
1da177e4 9825}
6aa20a22 9826
1da177e4
LT		 9827static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9828{
9829 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9830
1da177e4 9831 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9832
e18ce346 9833 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9834 epause->rx_pause = 1;
9835 else
9836 epause->rx_pause = 0;
9837
e18ce346 9838 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9839 epause->tx_pause = 1;
9840 else
9841 epause->tx_pause = 0;
1da177e4 9842}
6aa20a22 9843
1da177e4
LT		 9844static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9845{
9846 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9847 int err = 0;
6aa20a22 9848
b02fd9e3 9849 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2712168f
MC		 9850 u32 newadv;
9851 struct phy_device *phydev;
1da177e4 9852
2712168f 9853 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 9854
2712168f
MC		 9855 if (!(phydev->supported & SUPPORTED_Pause) ||
9856 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9857 ((epause->rx_pause && !epause->tx_pause) ||
9858 (!epause->rx_pause && epause->tx_pause))))
9859 return -EINVAL;
1da177e4 9860
2712168f
MC		 9861 tp->link_config.flowctrl = 0;
9862 if (epause->rx_pause) {
9863 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9864
9865 if (epause->tx_pause) {
9866 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9867 newadv = ADVERTISED_Pause;
b02fd9e3 9868 } else
2712168f
MC		 9869 newadv = ADVERTISED_Pause |
9870 ADVERTISED_Asym_Pause;
9871 } else if (epause->tx_pause) {
9872 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9873 newadv = ADVERTISED_Asym_Pause;
9874 } else
9875 newadv = 0;
9876
9877 if (epause->autoneg)
9878 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9879 else
9880 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9881
9882 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9883 u32 oldadv = phydev->advertising &
9884 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9885 if (oldadv != newadv) {
9886 phydev->advertising &=
9887 ~(ADVERTISED_Pause |
9888 ADVERTISED_Asym_Pause);
9889 phydev->advertising |= newadv;
9890 if (phydev->autoneg) {
9891 /*
9892 * Always renegotiate the link to
9893 * inform our link partner of our
9894 * flow control settings, even if the
9895 * flow control is forced. Let
9896 * tg3_adjust_link() do the final
9897 * flow control setup.
9898 */
9899 return phy_start_aneg(phydev);
b02fd9e3 9900 }
b02fd9e3 9901 }
b02fd9e3 9902
2712168f 9903 if (!epause->autoneg)
b02fd9e3 9904 tg3_setup_flow_control(tp, 0, 0);
2712168f
MC		 9905 } else {
9906 tp->link_config.orig_advertising &=
9907 ~(ADVERTISED_Pause |
9908 ADVERTISED_Asym_Pause);
9909 tp->link_config.orig_advertising |= newadv;
b02fd9e3
MC		 9910 }
9911 } else {
9912 int irq_sync = 0;
9913
9914 if (netif_running(dev)) {
9915 tg3_netif_stop(tp);
9916 irq_sync = 1;
9917 }
9918
9919 tg3_full_lock(tp, irq_sync);
9920
9921 if (epause->autoneg)
9922 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9923 else
9924 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9925 if (epause->rx_pause)
e18ce346 9926 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9927 else
e18ce346 9928 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9929 if (epause->tx_pause)
e18ce346 9930 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9931 else
e18ce346 9932 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9933
9934 if (netif_running(dev)) {
9935 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9936 err = tg3_restart_hw(tp, 1);
9937 if (!err)
9938 tg3_netif_start(tp);
9939 }
9940
9941 tg3_full_unlock(tp);
9942 }
6aa20a22 9943
b9ec6c1b 9944 return err;
1da177e4 9945}
6aa20a22 9946
1da177e4
LT		 9947static u32 tg3_get_rx_csum(struct net_device *dev)
9948{
9949 struct tg3 *tp = netdev_priv(dev);
9950 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9951}
6aa20a22 9952
1da177e4
LT		 9953static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9954{
9955 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9956
1da177e4
LT		 9957 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9958 if (data != 0)
9959 return -EINVAL;
c6cdf436
MC		 9960 return 0;
9961 }
6aa20a22 9962
f47c11ee 9963 spin_lock_bh(&tp->lock);
1da177e4
LT		 9964 if (data)
9965 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9966 else
9967 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9968 spin_unlock_bh(&tp->lock);
6aa20a22 9969
1da177e4
LT		 9970 return 0;
9971}
6aa20a22 9972
1da177e4
LT		 9973static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9974{
9975 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9976
1da177e4
LT		 9977 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9978 if (data != 0)
9979 return -EINVAL;
c6cdf436
MC		 9980 return 0;
9981 }
6aa20a22 9982
321d32a0 9983 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9984 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9985 else
9c27dbdf 9986 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9987
9988 return 0;
9989}
9990
b9f2c044 9991static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9992{
b9f2c044
JG		 9993 switch (sset) {
9994 case ETH_SS_TEST:
9995 return TG3_NUM_TEST;
9996 case ETH_SS_STATS:
9997 return TG3_NUM_STATS;
9998 default:
9999 return -EOPNOTSUPP;
10000 }
4cafd3f5
MC		 10001}
10002
1da177e4
LT		 10003static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10004{
10005 switch (stringset) {
10006 case ETH_SS_STATS:
10007 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10008 break;
4cafd3f5
MC		 10009 case ETH_SS_TEST:
10010 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10011 break;
1da177e4
LT		 10012 default:
10013 WARN_ON(1); /* we need a WARN() */
10014 break;
10015 }
10016}
10017
4009a93d
MC		 10018static int tg3_phys_id(struct net_device *dev, u32 data)
10019{
10020 struct tg3 *tp = netdev_priv(dev);
10021 int i;
10022
10023 if (!netif_running(tp->dev))
10024 return -EAGAIN;
10025
10026 if (data == 0)
759afc31 10027 data = UINT_MAX / 2;
4009a93d
MC		 10028
10029 for (i = 0; i < (data * 2); i++) {
10030 if ((i % 2) == 0)
10031 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10032 LED_CTRL_1000MBPS_ON |
10033 LED_CTRL_100MBPS_ON |
10034 LED_CTRL_10MBPS_ON |
10035 LED_CTRL_TRAFFIC_OVERRIDE |
10036 LED_CTRL_TRAFFIC_BLINK |
10037 LED_CTRL_TRAFFIC_LED);
6aa20a22 10038
4009a93d
MC		 10039 else
10040 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10041 LED_CTRL_TRAFFIC_OVERRIDE);
10042
10043 if (msleep_interruptible(500))
10044 break;
10045 }
10046 tw32(MAC_LED_CTRL, tp->led_ctrl);
10047 return 0;
10048}
10049
1da177e4
LT		 10050static void tg3_get_ethtool_stats (struct net_device *dev,
10051 struct ethtool_stats *estats, u64 *tmp_stats)
10052{
10053 struct tg3 *tp = netdev_priv(dev);
10054 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10055}
10056
566f86ad 10057#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10058#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10059#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10060#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10061#define NVRAM_SELFBOOT_HW_SIZE 0x20
10062#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10063
10064static int tg3_test_nvram(struct tg3 *tp)
10065{
b9fc7dc5 10066 u32 csum, magic;
a9dc529d 10067 __be32 *buf;
ab0049b4 10068 int i, j, k, err = 0, size;
566f86ad 10069
df259d8c
MC		 10070 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10071 return 0;
10072
e4f34110 10073 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10074 return -EIO;
10075
1b27777a
MC		 10076 if (magic == TG3_EEPROM_MAGIC)
10077 size = NVRAM_TEST_SIZE;
b16250e3 10078 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10079 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10080 TG3_EEPROM_SB_FORMAT_1) {
10081 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10082 case TG3_EEPROM_SB_REVISION_0:
10083 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10084 break;
10085 case TG3_EEPROM_SB_REVISION_2:
10086 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10087 break;
10088 case TG3_EEPROM_SB_REVISION_3:
10089 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10090 break;
10091 default:
10092 return 0;
10093 }
10094 } else
1b27777a 10095 return 0;
b16250e3
MC		 10096 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10097 size = NVRAM_SELFBOOT_HW_SIZE;
10098 else
1b27777a
MC		 10099 return -EIO;
10100
10101 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10102 if (buf == NULL)
10103 return -ENOMEM;
10104
1b27777a
MC		 10105 err = -EIO;
10106 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10107 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10108 if (err)
566f86ad 10109 break;
566f86ad 10110 }
1b27777a 10111 if (i < size)
566f86ad
MC		 10112 goto out;
10113
1b27777a 10114 /* Selfboot format */
a9dc529d 10115 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10116 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10117 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10118 u8 *buf8 = (u8 *) buf, csum8 = 0;
10119
b9fc7dc5 10120 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10121 TG3_EEPROM_SB_REVISION_2) {
10122 /* For rev 2, the csum doesn't include the MBA. */
10123 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10124 csum8 += buf8[i];
10125 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10126 csum8 += buf8[i];
10127 } else {
10128 for (i = 0; i < size; i++)
10129 csum8 += buf8[i];
10130 }
1b27777a 10131
ad96b485
AB		 10132 if (csum8 == 0) {
10133 err = 0;
10134 goto out;
10135 }
10136
10137 err = -EIO;
10138 goto out;
1b27777a 10139 }
566f86ad 10140
b9fc7dc5 10141 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10142 TG3_EEPROM_MAGIC_HW) {
10143 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10144 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10145 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10146
10147 /* Separate the parity bits and the data bytes. */
10148 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10149 if ((i == 0) || (i == 8)) {
10150 int l;
10151 u8 msk;
10152
10153 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10154 parity[k++] = buf8[i] & msk;
10155 i++;
859a5887 10156 } else if (i == 16) {
b16250e3
MC		 10157 int l;
10158 u8 msk;
10159
10160 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10161 parity[k++] = buf8[i] & msk;
10162 i++;
10163
10164 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10165 parity[k++] = buf8[i] & msk;
10166 i++;
10167 }
10168 data[j++] = buf8[i];
10169 }
10170
10171 err = -EIO;
10172 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10173 u8 hw8 = hweight8(data[i]);
10174
10175 if ((hw8 & 0x1) && parity[i])
10176 goto out;
10177 else if (!(hw8 & 0x1) && !parity[i])
10178 goto out;
10179 }
10180 err = 0;
10181 goto out;
10182 }
10183
566f86ad
MC		 10184 /* Bootstrap checksum at offset 0x10 */
10185 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10186 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10187 goto out;
10188
10189 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10190 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10191 if (csum != be32_to_cpu(buf[0xfc/4]))
10192 goto out;
566f86ad
MC		 10193
10194 err = 0;
10195
10196out:
10197 kfree(buf);
10198 return err;
10199}
10200
ca43007a
MC		 10201#define TG3_SERDES_TIMEOUT_SEC 2
10202#define TG3_COPPER_TIMEOUT_SEC 6
10203
10204static int tg3_test_link(struct tg3 *tp)
10205{
10206 int i, max;
10207
10208 if (!netif_running(tp->dev))
10209 return -ENODEV;
10210
4c987487 10211 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10212 max = TG3_SERDES_TIMEOUT_SEC;
10213 else
10214 max = TG3_COPPER_TIMEOUT_SEC;
10215
10216 for (i = 0; i < max; i++) {
10217 if (netif_carrier_ok(tp->dev))
10218 return 0;
10219
10220 if (msleep_interruptible(1000))
10221 break;
10222 }
10223
10224 return -EIO;
10225}
10226
a71116d1 10227/* Only test the commonly used registers */
30ca3e37 10228static int tg3_test_registers(struct tg3 *tp)
a71116d1 10229{
b16250e3 10230 int i, is_5705, is_5750;
a71116d1
MC		 10231 u32 offset, read_mask, write_mask, val, save_val, read_val;
10232 static struct {
10233 u16 offset;
10234 u16 flags;
10235#define TG3_FL_5705 0x1
10236#define TG3_FL_NOT_5705 0x2
10237#define TG3_FL_NOT_5788 0x4
b16250e3 10238#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10239 u32 read_mask;
10240 u32 write_mask;
10241 } reg_tbl[] = {
10242 /* MAC Control Registers */
10243 { MAC_MODE, TG3_FL_NOT_5705,
10244 0x00000000, 0x00ef6f8c },
10245 { MAC_MODE, TG3_FL_5705,
10246 0x00000000, 0x01ef6b8c },
10247 { MAC_STATUS, TG3_FL_NOT_5705,
10248 0x03800107, 0x00000000 },
10249 { MAC_STATUS, TG3_FL_5705,
10250 0x03800100, 0x00000000 },
10251 { MAC_ADDR_0_HIGH, 0x0000,
10252 0x00000000, 0x0000ffff },
10253 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 10254 0x00000000, 0xffffffff },
a71116d1
MC		 10255 { MAC_RX_MTU_SIZE, 0x0000,
10256 0x00000000, 0x0000ffff },
10257 { MAC_TX_MODE, 0x0000,
10258 0x00000000, 0x00000070 },
10259 { MAC_TX_LENGTHS, 0x0000,
10260 0x00000000, 0x00003fff },
10261 { MAC_RX_MODE, TG3_FL_NOT_5705,
10262 0x00000000, 0x000007fc },
10263 { MAC_RX_MODE, TG3_FL_5705,
10264 0x00000000, 0x000007dc },
10265 { MAC_HASH_REG_0, 0x0000,
10266 0x00000000, 0xffffffff },
10267 { MAC_HASH_REG_1, 0x0000,
10268 0x00000000, 0xffffffff },
10269 { MAC_HASH_REG_2, 0x0000,
10270 0x00000000, 0xffffffff },
10271 { MAC_HASH_REG_3, 0x0000,
10272 0x00000000, 0xffffffff },
10273
10274 /* Receive Data and Receive BD Initiator Control Registers. */
10275 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10276 0x00000000, 0xffffffff },
10277 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10278 0x00000000, 0xffffffff },
10279 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10280 0x00000000, 0x00000003 },
10281 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10282 0x00000000, 0xffffffff },
10283 { RCVDBDI_STD_BD+0, 0x0000,
10284 0x00000000, 0xffffffff },
10285 { RCVDBDI_STD_BD+4, 0x0000,
10286 0x00000000, 0xffffffff },
10287 { RCVDBDI_STD_BD+8, 0x0000,
10288 0x00000000, 0xffff0002 },
10289 { RCVDBDI_STD_BD+0xc, 0x0000,
10290 0x00000000, 0xffffffff },
6aa20a22 10291
a71116d1
MC		 10292 /* Receive BD Initiator Control Registers. */
10293 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10294 0x00000000, 0xffffffff },
10295 { RCVBDI_STD_THRESH, TG3_FL_5705,
10296 0x00000000, 0x000003ff },
10297 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10298 0x00000000, 0xffffffff },
6aa20a22 10299
a71116d1
MC		 10300 /* Host Coalescing Control Registers. */
10301 { HOSTCC_MODE, TG3_FL_NOT_5705,
10302 0x00000000, 0x00000004 },
10303 { HOSTCC_MODE, TG3_FL_5705,
10304 0x00000000, 0x000000f6 },
10305 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10306 0x00000000, 0xffffffff },
10307 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10308 0x00000000, 0x000003ff },
10309 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10310 0x00000000, 0xffffffff },
10311 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10312 0x00000000, 0x000003ff },
10313 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10314 0x00000000, 0xffffffff },
10315 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10316 0x00000000, 0x000000ff },
10317 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10318 0x00000000, 0xffffffff },
10319 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10320 0x00000000, 0x000000ff },
10321 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10322 0x00000000, 0xffffffff },
10323 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10324 0x00000000, 0xffffffff },
10325 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10326 0x00000000, 0xffffffff },
10327 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10328 0x00000000, 0x000000ff },
10329 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10330 0x00000000, 0xffffffff },
10331 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10332 0x00000000, 0x000000ff },
10333 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10334 0x00000000, 0xffffffff },
10335 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10336 0x00000000, 0xffffffff },
10337 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10338 0x00000000, 0xffffffff },
10339 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10340 0x00000000, 0xffffffff },
10341 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10342 0x00000000, 0xffffffff },
10343 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10344 0xffffffff, 0x00000000 },
10345 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10346 0xffffffff, 0x00000000 },
10347
10348 /* Buffer Manager Control Registers. */
b16250e3 10349 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10350 0x00000000, 0x007fff80 },
b16250e3 10351 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10352 0x00000000, 0x007fffff },
10353 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10354 0x00000000, 0x0000003f },
10355 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10356 0x00000000, 0x000001ff },
10357 { BUFMGR_MB_HIGH_WATER, 0x0000,
10358 0x00000000, 0x000001ff },
10359 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10360 0xffffffff, 0x00000000 },
10361 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10362 0xffffffff, 0x00000000 },
6aa20a22 10363
a71116d1
MC		 10364 /* Mailbox Registers */
10365 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10366 0x00000000, 0x000001ff },
10367 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10368 0x00000000, 0x000001ff },
10369 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10370 0x00000000, 0x000007ff },
10371 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10372 0x00000000, 0x000001ff },
10373
10374 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10375 };
10376
b16250e3
MC		 10377 is_5705 = is_5750 = 0;
10378 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10379 is_5705 = 1;
b16250e3
MC		 10380 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10381 is_5750 = 1;
10382 }
a71116d1
MC		 10383
10384 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10385 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10386 continue;
10387
10388 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10389 continue;
10390
10391 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10392 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10393 continue;
10394
b16250e3
MC		 10395 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10396 continue;
10397
a71116d1
MC		 10398 offset = (u32) reg_tbl[i].offset;
10399 read_mask = reg_tbl[i].read_mask;
10400 write_mask = reg_tbl[i].write_mask;
10401
10402 /* Save the original register content */
10403 save_val = tr32(offset);
10404
10405 /* Determine the read-only value. */
10406 read_val = save_val & read_mask;
10407
10408 /* Write zero to the register, then make sure the read-only bits
10409 * are not changed and the read/write bits are all zeros.
10410 */
10411 tw32(offset, 0);
10412
10413 val = tr32(offset);
10414
10415 /* Test the read-only and read/write bits. */
10416 if (((val & read_mask) != read_val) || (val & write_mask))
10417 goto out;
10418
10419 /* Write ones to all the bits defined by RdMask and WrMask, then
10420 * make sure the read-only bits are not changed and the
10421 * read/write bits are all ones.
10422 */
10423 tw32(offset, read_mask | write_mask);
10424
10425 val = tr32(offset);
10426
10427 /* Test the read-only bits. */
10428 if ((val & read_mask) != read_val)
10429 goto out;
10430
10431 /* Test the read/write bits. */
10432 if ((val & write_mask) != write_mask)
10433 goto out;
10434
10435 tw32(offset, save_val);
10436 }
10437
10438 return 0;
10439
10440out:
9f88f29f 10441 if (netif_msg_hw(tp))
2445e461
MC		 10442 netdev_err(tp->dev,
10443 "Register test failed at offset %x\n", offset);
a71116d1
MC		 10444 tw32(offset, save_val);
10445 return -EIO;
10446}
10447
7942e1db
MC		 10448static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10449{
f71e1309 10450 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10451 int i;
10452 u32 j;
10453
e9edda69 10454 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10455 for (j = 0; j < len; j += 4) {
10456 u32 val;
10457
10458 tg3_write_mem(tp, offset + j, test_pattern[i]);
10459 tg3_read_mem(tp, offset + j, &val);
10460 if (val != test_pattern[i])
10461 return -EIO;
10462 }
10463 }
10464 return 0;
10465}
10466
10467static int tg3_test_memory(struct tg3 *tp)
10468{
10469 static struct mem_entry {
10470 u32 offset;
10471 u32 len;
10472 } mem_tbl_570x[] = {
38690194 10473 { 0x00000000, 0x00b50},
7942e1db
MC		 10474 { 0x00002000, 0x1c000},
10475 { 0xffffffff, 0x00000}
10476 }, mem_tbl_5705[] = {
10477 { 0x00000100, 0x0000c},
10478 { 0x00000200, 0x00008},
7942e1db
MC		 10479 { 0x00004000, 0x00800},
10480 { 0x00006000, 0x01000},
10481 { 0x00008000, 0x02000},
10482 { 0x00010000, 0x0e000},
10483 { 0xffffffff, 0x00000}
79f4d13a
MC		 10484 }, mem_tbl_5755[] = {
10485 { 0x00000200, 0x00008},
10486 { 0x00004000, 0x00800},
10487 { 0x00006000, 0x00800},
10488 { 0x00008000, 0x02000},
10489 { 0x00010000, 0x0c000},
10490 { 0xffffffff, 0x00000}
b16250e3
MC		 10491 }, mem_tbl_5906[] = {
10492 { 0x00000200, 0x00008},
10493 { 0x00004000, 0x00400},
10494 { 0x00006000, 0x00400},
10495 { 0x00008000, 0x01000},
10496 { 0x00010000, 0x01000},
10497 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10498 }, mem_tbl_5717[] = {
10499 { 0x00000200, 0x00008},
10500 { 0x00010000, 0x0a000},
10501 { 0x00020000, 0x13c00},
10502 { 0xffffffff, 0x00000}
10503 }, mem_tbl_57765[] = {
10504 { 0x00000200, 0x00008},
10505 { 0x00004000, 0x00800},
10506 { 0x00006000, 0x09800},
10507 { 0x00010000, 0x0a000},
10508 { 0xffffffff, 0x00000}
7942e1db
MC		 10509 };
10510 struct mem_entry *mem_tbl;
10511 int err = 0;
10512 int i;
10513
8b5a6c42
MC		 10514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10515 mem_tbl = mem_tbl_5717;
10516 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10517 mem_tbl = mem_tbl_57765;
10518 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10519 mem_tbl = mem_tbl_5755;
10520 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10521 mem_tbl = mem_tbl_5906;
10522 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10523 mem_tbl = mem_tbl_5705;
10524 else
7942e1db
MC		 10525 mem_tbl = mem_tbl_570x;
10526
10527 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10528 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10529 mem_tbl[i].len)) != 0)
10530 break;
10531 }
6aa20a22 10532
7942e1db
MC		 10533 return err;
10534}
10535
9f40dead
MC		 10536#define TG3_MAC_LOOPBACK 0
10537#define TG3_PHY_LOOPBACK 1
10538
10539static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10540{
9f40dead 10541 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10542 u32 desc_idx, coal_now;
c76949a6
MC		 10543 struct sk_buff *skb, *rx_skb;
10544 u8 *tx_data;
10545 dma_addr_t map;
10546 int num_pkts, tx_len, rx_len, i, err;
10547 struct tg3_rx_buffer_desc *desc;
898a56f8 10548 struct tg3_napi *tnapi, *rnapi;
21f581a5 10549 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10550
c8873405
MC		 10551 tnapi = &tp->napi[0];
10552 rnapi = &tp->napi[0];
0c1d0e2b 10553 if (tp->irq_cnt > 1) {
0c1d0e2b 10554 rnapi = &tp->napi[1];
c8873405
MC		 10555 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10556 tnapi = &tp->napi[1];
0c1d0e2b 10557 }
fd2ce37f 10558 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10559
9f40dead 10560 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10561 /* HW errata - mac loopback fails in some cases on 5780.
10562 * Normal traffic and PHY loopback are not affected by
10563 * errata.
10564 */
10565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10566 return 0;
10567
9f40dead 10568 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10569 MAC_MODE_PORT_INT_LPBACK;
10570 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10571 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10572 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10573 mac_mode |= MAC_MODE_PORT_MODE_MII;
10574 else
10575 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10576 tw32(MAC_MODE, mac_mode);
10577 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10578 u32 val;
10579
7f97a4bd
MC		 10580 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10581 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10582 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10583 } else
10584 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10585
9ef8ca99
MC		 10586 tg3_phy_toggle_automdix(tp, 0);
10587
3f7045c1 10588 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10589 udelay(40);
5d64ad34 10590
e8f3f6ca 10591 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd 10592 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1061b7c5
MC		 10593 tg3_writephy(tp, MII_TG3_FET_PTEST,
10594 MII_TG3_FET_PTEST_FRC_TX_LINK |
10595 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10596 /* The write needs to be flushed for the AC131 */
10597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10598 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
5d64ad34
MC		 10599 mac_mode |= MAC_MODE_PORT_MODE_MII;
10600 } else
10601 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10602
c94e3941
MC		 10603 /* reset to prevent losing 1st rx packet intermittently */
10604 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10605 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10606 udelay(10);
10607 tw32_f(MAC_RX_MODE, tp->rx_mode);
10608 }
e8f3f6ca 10609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
79eb6904
MC		 10610 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10611 if (masked_phy_id == TG3_PHY_ID_BCM5401)
e8f3f6ca 10612 mac_mode &= ~MAC_MODE_LINK_POLARITY;
79eb6904 10613 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
e8f3f6ca 10614 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10615 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10616 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10617 }
9f40dead 10618 tw32(MAC_MODE, mac_mode);
859a5887 10619 } else {
9f40dead 10620 return -EINVAL;
859a5887 10621 }
c76949a6
MC		 10622
10623 err = -EIO;
10624
c76949a6 10625 tx_len = 1514;
a20e9c62 10626 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10627 if (!skb)
10628 return -ENOMEM;
10629
c76949a6
MC		 10630 tx_data = skb_put(skb, tx_len);
10631 memcpy(tx_data, tp->dev->dev_addr, 6);
10632 memset(tx_data + 6, 0x0, 8);
10633
10634 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10635
10636 for (i = 14; i < tx_len; i++)
10637 tx_data[i] = (u8) (i & 0xff);
10638
f4188d8a
AD		 10639 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10640 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10641 dev_kfree_skb(skb);
10642 return -EIO;
10643 }
c76949a6
MC		 10644
10645 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10646 rnapi->coal_now);
c76949a6
MC		 10647
10648 udelay(10);
10649
898a56f8 10650 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10651
c76949a6
MC		 10652 num_pkts = 0;
10653
f4188d8a 10654 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10655
f3f3f27e 10656 tnapi->tx_prod++;
c76949a6
MC		 10657 num_pkts++;
10658
f3f3f27e
MC		 10659 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10660 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10661
10662 udelay(10);
10663
303fc921
MC		 10664 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10665 for (i = 0; i < 35; i++) {
c76949a6 10666 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10667 coal_now);
c76949a6
MC		 10668
10669 udelay(10);
10670
898a56f8
MC		 10671 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10672 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10673 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10674 (rx_idx == (rx_start_idx + num_pkts)))
10675 break;
10676 }
10677
f4188d8a 10678 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10679 dev_kfree_skb(skb);
10680
f3f3f27e 10681 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10682 goto out;
10683
10684 if (rx_idx != rx_start_idx + num_pkts)
10685 goto out;
10686
72334482 10687 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10688 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10689 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10690 if (opaque_key != RXD_OPAQUE_RING_STD)
10691 goto out;
10692
10693 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10694 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10695 goto out;
10696
10697 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10698 if (rx_len != tx_len)
10699 goto out;
10700
21f581a5 10701 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10702
21f581a5 10703 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10704 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10705
10706 for (i = 14; i < tx_len; i++) {
10707 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10708 goto out;
10709 }
10710 err = 0;
6aa20a22 10711
c76949a6
MC		 10712 /* tg3_free_rings will unmap and free the rx_skb */
10713out:
10714 return err;
10715}
10716
9f40dead
MC		 10717#define TG3_MAC_LOOPBACK_FAILED 1
10718#define TG3_PHY_LOOPBACK_FAILED 2
10719#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10720 TG3_PHY_LOOPBACK_FAILED)
10721
10722static int tg3_test_loopback(struct tg3 *tp)
10723{
10724 int err = 0;
9936bcf6 10725 u32 cpmuctrl = 0;
9f40dead
MC		 10726
10727 if (!netif_running(tp->dev))
10728 return TG3_LOOPBACK_FAILED;
10729
b9ec6c1b
MC		 10730 err = tg3_reset_hw(tp, 1);
10731 if (err)
10732 return TG3_LOOPBACK_FAILED;
9f40dead 10733
6833c043
MC		 10734 /* Turn off gphy autopowerdown. */
10735 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10736 tg3_phy_toggle_apd(tp, false);
10737
321d32a0 10738 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10739 int i;
10740 u32 status;
10741
10742 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10743
10744 /* Wait for up to 40 microseconds to acquire lock. */
10745 for (i = 0; i < 4; i++) {
10746 status = tr32(TG3_CPMU_MUTEX_GNT);
10747 if (status == CPMU_MUTEX_GNT_DRIVER)
10748 break;
10749 udelay(10);
10750 }
10751
10752 if (status != CPMU_MUTEX_GNT_DRIVER)
10753 return TG3_LOOPBACK_FAILED;
10754
b2a5c19c 10755 /* Turn off link-based power management. */
e875093c 10756 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10757 tw32(TG3_CPMU_CTRL,
10758 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10759 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10760 }
10761
9f40dead
MC		 10762 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10763 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10764
321d32a0 10765 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10766 tw32(TG3_CPMU_CTRL, cpmuctrl);
10767
10768 /* Release the mutex */
10769 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10770 }
10771
dd477003
MC		 10772 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10773 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10774 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10775 err |= TG3_PHY_LOOPBACK_FAILED;
10776 }
10777
6833c043
MC		 10778 /* Re-enable gphy autopowerdown. */
10779 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10780 tg3_phy_toggle_apd(tp, true);
10781
9f40dead
MC		 10782 return err;
10783}
10784
4cafd3f5
MC		 10785static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10786 u64 *data)
10787{
566f86ad
MC		 10788 struct tg3 *tp = netdev_priv(dev);
10789
bc1c7567
MC		 10790 if (tp->link_config.phy_is_low_power)
10791 tg3_set_power_state(tp, PCI_D0);
10792
566f86ad
MC		 10793 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10794
10795 if (tg3_test_nvram(tp) != 0) {
10796 etest->flags |= ETH_TEST_FL_FAILED;
10797 data[0] = 1;
10798 }
ca43007a
MC		 10799 if (tg3_test_link(tp) != 0) {
10800 etest->flags |= ETH_TEST_FL_FAILED;
10801 data[1] = 1;
10802 }
a71116d1 10803 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10804 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10805
10806 if (netif_running(dev)) {
b02fd9e3 10807 tg3_phy_stop(tp);
a71116d1 10808 tg3_netif_stop(tp);
bbe832c0
MC		 10809 irq_sync = 1;
10810 }
a71116d1 10811
bbe832c0 10812 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10813
10814 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10815 err = tg3_nvram_lock(tp);
a71116d1
MC		 10816 tg3_halt_cpu(tp, RX_CPU_BASE);
10817 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10818 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10819 if (!err)
10820 tg3_nvram_unlock(tp);
a71116d1 10821
d9ab5ad1
MC		 10822 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10823 tg3_phy_reset(tp);
10824
a71116d1
MC		 10825 if (tg3_test_registers(tp) != 0) {
10826 etest->flags |= ETH_TEST_FL_FAILED;
10827 data[2] = 1;
10828 }
7942e1db
MC		 10829 if (tg3_test_memory(tp) != 0) {
10830 etest->flags |= ETH_TEST_FL_FAILED;
10831 data[3] = 1;
10832 }
9f40dead 10833 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10834 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10835
f47c11ee
DM		 10836 tg3_full_unlock(tp);
10837
d4bc3927
MC		 10838 if (tg3_test_interrupt(tp) != 0) {
10839 etest->flags |= ETH_TEST_FL_FAILED;
10840 data[5] = 1;
10841 }
f47c11ee
DM		 10842
10843 tg3_full_lock(tp, 0);
d4bc3927 10844
a71116d1
MC		 10845 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10846 if (netif_running(dev)) {
10847 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10848 err2 = tg3_restart_hw(tp, 1);
10849 if (!err2)
b9ec6c1b 10850 tg3_netif_start(tp);
a71116d1 10851 }
f47c11ee
DM		 10852
10853 tg3_full_unlock(tp);
b02fd9e3
MC		 10854
10855 if (irq_sync && !err2)
10856 tg3_phy_start(tp);
a71116d1 10857 }
bc1c7567
MC		 10858 if (tp->link_config.phy_is_low_power)
10859 tg3_set_power_state(tp, PCI_D3hot);
10860
4cafd3f5
MC		 10861}
10862
1da177e4
LT		 10863static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10864{
10865 struct mii_ioctl_data *data = if_mii(ifr);
10866 struct tg3 *tp = netdev_priv(dev);
10867 int err;
10868
b02fd9e3 10869 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10870 struct phy_device *phydev;
b02fd9e3
MC		 10871 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10872 return -EAGAIN;
3f0e3ad7
MC		 10873 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10874 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10875 }
10876
33f401ae 10877 switch (cmd) {
1da177e4 10878 case SIOCGMIIPHY:
882e9793 10879 data->phy_id = tp->phy_addr;
1da177e4
LT		 10880
10881 /* fallthru */
10882 case SIOCGMIIREG: {
10883 u32 mii_regval;
10884
10885 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10886 break; /* We have no PHY */
10887
bc1c7567
MC		 10888 if (tp->link_config.phy_is_low_power)
10889 return -EAGAIN;
10890
f47c11ee 10891 spin_lock_bh(&tp->lock);
1da177e4 10892 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10893 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10894
10895 data->val_out = mii_regval;
10896
10897 return err;
10898 }
10899
10900 case SIOCSMIIREG:
10901 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10902 break; /* We have no PHY */
10903
bc1c7567
MC		 10904 if (tp->link_config.phy_is_low_power)
10905 return -EAGAIN;
10906
f47c11ee 10907 spin_lock_bh(&tp->lock);
1da177e4 10908 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10909 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10910
10911 return err;
10912
10913 default:
10914 /* do nothing */
10915 break;
10916 }
10917 return -EOPNOTSUPP;
10918}
10919
10920#if TG3_VLAN_TAG_USED
10921static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10922{
10923 struct tg3 *tp = netdev_priv(dev);
10924
844b3eed
MC		 10925 if (!netif_running(dev)) {
10926 tp->vlgrp = grp;
10927 return;
10928 }
10929
10930 tg3_netif_stop(tp);
29315e87 10931
f47c11ee 10932 tg3_full_lock(tp, 0);
1da177e4
LT		 10933
10934 tp->vlgrp = grp;
10935
10936 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10937 __tg3_set_rx_mode(dev);
10938
844b3eed 10939 tg3_netif_start(tp);
46966545
MC		 10940
10941 tg3_full_unlock(tp);
1da177e4 10942}
1da177e4
LT		 10943#endif
10944
15f9850d
DM		 10945static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10946{
10947 struct tg3 *tp = netdev_priv(dev);
10948
10949 memcpy(ec, &tp->coal, sizeof(*ec));
10950 return 0;
10951}
10952
d244c892
MC		 10953static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10954{
10955 struct tg3 *tp = netdev_priv(dev);
10956 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10957 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10958
10959 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10960 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10961 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10962 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10963 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10964 }
10965
10966 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10967 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10968 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10969 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10970 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10971 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10972 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10973 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10974 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10975 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10976 return -EINVAL;
10977
10978 /* No rx interrupts will be generated if both are zero */
10979 if ((ec->rx_coalesce_usecs == 0) &&
10980 (ec->rx_max_coalesced_frames == 0))
10981 return -EINVAL;
10982
10983 /* No tx interrupts will be generated if both are zero */
10984 if ((ec->tx_coalesce_usecs == 0) &&
10985 (ec->tx_max_coalesced_frames == 0))
10986 return -EINVAL;
10987
10988 /* Only copy relevant parameters, ignore all others. */
10989 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10990 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10991 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10992 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10993 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10994 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10995 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10996 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10997 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10998
10999 if (netif_running(dev)) {
11000 tg3_full_lock(tp, 0);
11001 __tg3_set_coalesce(tp, &tp->coal);
11002 tg3_full_unlock(tp);
11003 }
11004 return 0;
11005}
11006
7282d491 11007static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11008 .get_settings = tg3_get_settings,
11009 .set_settings = tg3_set_settings,
11010 .get_drvinfo = tg3_get_drvinfo,
11011 .get_regs_len = tg3_get_regs_len,
11012 .get_regs = tg3_get_regs,
11013 .get_wol = tg3_get_wol,
11014 .set_wol = tg3_set_wol,
11015 .get_msglevel = tg3_get_msglevel,
11016 .set_msglevel = tg3_set_msglevel,
11017 .nway_reset = tg3_nway_reset,
11018 .get_link = ethtool_op_get_link,
11019 .get_eeprom_len = tg3_get_eeprom_len,
11020 .get_eeprom = tg3_get_eeprom,
11021 .set_eeprom = tg3_set_eeprom,
11022 .get_ringparam = tg3_get_ringparam,
11023 .set_ringparam = tg3_set_ringparam,
11024 .get_pauseparam = tg3_get_pauseparam,
11025 .set_pauseparam = tg3_set_pauseparam,
11026 .get_rx_csum = tg3_get_rx_csum,
11027 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11028 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11029 .set_sg = ethtool_op_set_sg,
1da177e4 11030 .set_tso = tg3_set_tso,
4cafd3f5 11031 .self_test = tg3_self_test,
1da177e4 11032 .get_strings = tg3_get_strings,
4009a93d 11033 .phys_id = tg3_phys_id,
1da177e4 11034 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11035 .get_coalesce = tg3_get_coalesce,
d244c892 11036 .set_coalesce = tg3_set_coalesce,
b9f2c044 11037 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11038};
11039
11040static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11041{
1b27777a 11042 u32 cursize, val, magic;
1da177e4
LT		 11043
11044 tp->nvram_size = EEPROM_CHIP_SIZE;
11045
e4f34110 11046 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11047 return;
11048
b16250e3
MC		 11049 if ((magic != TG3_EEPROM_MAGIC) &&
11050 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11051 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11052 return;
11053
11054 /*
11055 * Size the chip by reading offsets at increasing powers of two.
11056 * When we encounter our validation signature, we know the addressing
11057 * has wrapped around, and thus have our chip size.
11058 */
1b27777a 11059 cursize = 0x10;
1da177e4
LT		 11060
11061 while (cursize < tp->nvram_size) {
e4f34110 11062 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11063 return;
11064
1820180b 11065 if (val == magic)
1da177e4
LT		 11066 break;
11067
11068 cursize <<= 1;
11069 }
11070
11071 tp->nvram_size = cursize;
11072}
6aa20a22 11073
1da177e4
LT		 11074static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11075{
11076 u32 val;
11077
df259d8c
MC		 11078 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11079 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11080 return;
11081
11082 /* Selfboot format */
1820180b 11083 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11084 tg3_get_eeprom_size(tp);
11085 return;
11086 }
11087
6d348f2c 11088 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11089 if (val != 0) {
6d348f2c
MC		 11090 /* This is confusing. We want to operate on the
11091 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11092 * call will read from NVRAM and byteswap the data
11093 * according to the byteswapping settings for all
11094 * other register accesses. This ensures the data we
11095 * want will always reside in the lower 16-bits.
11096 * However, the data in NVRAM is in LE format, which
11097 * means the data from the NVRAM read will always be
11098 * opposite the endianness of the CPU. The 16-bit
11099 * byteswap then brings the data to CPU endianness.
11100 */
11101 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11102 return;
11103 }
11104 }
fd1122a2 11105 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11106}
11107
11108static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11109{
11110 u32 nvcfg1;
11111
11112 nvcfg1 = tr32(NVRAM_CFG1);
11113 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11114 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11115 } else {
1da177e4
LT		 11116 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11117 tw32(NVRAM_CFG1, nvcfg1);
11118 }
11119
4c987487 11120 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11121 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11122 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11123 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11124 tp->nvram_jedecnum = JEDEC_ATMEL;
11125 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11126 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11127 break;
11128 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11129 tp->nvram_jedecnum = JEDEC_ATMEL;
11130 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11131 break;
11132 case FLASH_VENDOR_ATMEL_EEPROM:
11133 tp->nvram_jedecnum = JEDEC_ATMEL;
11134 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11135 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11136 break;
11137 case FLASH_VENDOR_ST:
11138 tp->nvram_jedecnum = JEDEC_ST;
11139 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11140 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11141 break;
11142 case FLASH_VENDOR_SAIFUN:
11143 tp->nvram_jedecnum = JEDEC_SAIFUN;
11144 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11145 break;
11146 case FLASH_VENDOR_SST_SMALL:
11147 case FLASH_VENDOR_SST_LARGE:
11148 tp->nvram_jedecnum = JEDEC_SST;
11149 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11150 break;
1da177e4 11151 }
8590a603 11152 } else {
1da177e4
LT		 11153 tp->nvram_jedecnum = JEDEC_ATMEL;
11154 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11155 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11156 }
11157}
11158
a1b950d5
MC		 11159static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11160{
11161 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11162 case FLASH_5752PAGE_SIZE_256:
11163 tp->nvram_pagesize = 256;
11164 break;
11165 case FLASH_5752PAGE_SIZE_512:
11166 tp->nvram_pagesize = 512;
11167 break;
11168 case FLASH_5752PAGE_SIZE_1K:
11169 tp->nvram_pagesize = 1024;
11170 break;
11171 case FLASH_5752PAGE_SIZE_2K:
11172 tp->nvram_pagesize = 2048;
11173 break;
11174 case FLASH_5752PAGE_SIZE_4K:
11175 tp->nvram_pagesize = 4096;
11176 break;
11177 case FLASH_5752PAGE_SIZE_264:
11178 tp->nvram_pagesize = 264;
11179 break;
11180 case FLASH_5752PAGE_SIZE_528:
11181 tp->nvram_pagesize = 528;
11182 break;
11183 }
11184}
11185
361b4ac2
MC		 11186static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11187{
11188 u32 nvcfg1;
11189
11190 nvcfg1 = tr32(NVRAM_CFG1);
11191
e6af301b
MC		 11192 /* NVRAM protection for TPM */
11193 if (nvcfg1 & (1 << 27))
f66a29b0 11194 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11195
361b4ac2 11196 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11197 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11198 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11199 tp->nvram_jedecnum = JEDEC_ATMEL;
11200 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11201 break;
11202 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11203 tp->nvram_jedecnum = JEDEC_ATMEL;
11204 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11205 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11206 break;
11207 case FLASH_5752VENDOR_ST_M45PE10:
11208 case FLASH_5752VENDOR_ST_M45PE20:
11209 case FLASH_5752VENDOR_ST_M45PE40:
11210 tp->nvram_jedecnum = JEDEC_ST;
11211 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11212 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11213 break;
361b4ac2
MC		 11214 }
11215
11216 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11217 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11218 } else {
361b4ac2
MC		 11219 /* For eeprom, set pagesize to maximum eeprom size */
11220 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11221
11222 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11223 tw32(NVRAM_CFG1, nvcfg1);
11224 }
11225}
11226
d3c7b886
MC		 11227static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11228{
989a9d23 11229 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11230
11231 nvcfg1 = tr32(NVRAM_CFG1);
11232
11233 /* NVRAM protection for TPM */
989a9d23 11234 if (nvcfg1 & (1 << 27)) {
f66a29b0 11235 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11236 protect = 1;
11237 }
d3c7b886 11238
989a9d23
MC		 11239 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11240 switch (nvcfg1) {
8590a603
MC		 11241 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11242 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11243 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11244 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11245 tp->nvram_jedecnum = JEDEC_ATMEL;
11246 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11247 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11248 tp->nvram_pagesize = 264;
11249 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11250 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11251 tp->nvram_size = (protect ? 0x3e200 :
11252 TG3_NVRAM_SIZE_512KB);
11253 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11254 tp->nvram_size = (protect ? 0x1f200 :
11255 TG3_NVRAM_SIZE_256KB);
11256 else
11257 tp->nvram_size = (protect ? 0x1f200 :
11258 TG3_NVRAM_SIZE_128KB);
11259 break;
11260 case FLASH_5752VENDOR_ST_M45PE10:
11261 case FLASH_5752VENDOR_ST_M45PE20:
11262 case FLASH_5752VENDOR_ST_M45PE40:
11263 tp->nvram_jedecnum = JEDEC_ST;
11264 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11266 tp->nvram_pagesize = 256;
11267 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11268 tp->nvram_size = (protect ?
11269 TG3_NVRAM_SIZE_64KB :
11270 TG3_NVRAM_SIZE_128KB);
11271 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11272 tp->nvram_size = (protect ?
11273 TG3_NVRAM_SIZE_64KB :
11274 TG3_NVRAM_SIZE_256KB);
11275 else
11276 tp->nvram_size = (protect ?
11277 TG3_NVRAM_SIZE_128KB :
11278 TG3_NVRAM_SIZE_512KB);
11279 break;
d3c7b886
MC		 11280 }
11281}
11282
1b27777a
MC		 11283static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11284{
11285 u32 nvcfg1;
11286
11287 nvcfg1 = tr32(NVRAM_CFG1);
11288
11289 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11290 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11291 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11292 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11293 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11294 tp->nvram_jedecnum = JEDEC_ATMEL;
11295 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11296 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11297
8590a603
MC		 11298 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11299 tw32(NVRAM_CFG1, nvcfg1);
11300 break;
11301 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11302 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11303 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11304 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11305 tp->nvram_jedecnum = JEDEC_ATMEL;
11306 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11307 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11308 tp->nvram_pagesize = 264;
11309 break;
11310 case FLASH_5752VENDOR_ST_M45PE10:
11311 case FLASH_5752VENDOR_ST_M45PE20:
11312 case FLASH_5752VENDOR_ST_M45PE40:
11313 tp->nvram_jedecnum = JEDEC_ST;
11314 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11315 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11316 tp->nvram_pagesize = 256;
11317 break;
1b27777a
MC		 11318 }
11319}
11320
6b91fa02
MC		 11321static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11322{
11323 u32 nvcfg1, protect = 0;
11324
11325 nvcfg1 = tr32(NVRAM_CFG1);
11326
11327 /* NVRAM protection for TPM */
11328 if (nvcfg1 & (1 << 27)) {
f66a29b0 11329 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11330 protect = 1;
11331 }
11332
11333 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11334 switch (nvcfg1) {
8590a603
MC		 11335 case FLASH_5761VENDOR_ATMEL_ADB021D:
11336 case FLASH_5761VENDOR_ATMEL_ADB041D:
11337 case FLASH_5761VENDOR_ATMEL_ADB081D:
11338 case FLASH_5761VENDOR_ATMEL_ADB161D:
11339 case FLASH_5761VENDOR_ATMEL_MDB021D:
11340 case FLASH_5761VENDOR_ATMEL_MDB041D:
11341 case FLASH_5761VENDOR_ATMEL_MDB081D:
11342 case FLASH_5761VENDOR_ATMEL_MDB161D:
11343 tp->nvram_jedecnum = JEDEC_ATMEL;
11344 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11345 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11346 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11347 tp->nvram_pagesize = 256;
11348 break;
11349 case FLASH_5761VENDOR_ST_A_M45PE20:
11350 case FLASH_5761VENDOR_ST_A_M45PE40:
11351 case FLASH_5761VENDOR_ST_A_M45PE80:
11352 case FLASH_5761VENDOR_ST_A_M45PE16:
11353 case FLASH_5761VENDOR_ST_M_M45PE20:
11354 case FLASH_5761VENDOR_ST_M_M45PE40:
11355 case FLASH_5761VENDOR_ST_M_M45PE80:
11356 case FLASH_5761VENDOR_ST_M_M45PE16:
11357 tp->nvram_jedecnum = JEDEC_ST;
11358 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11359 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11360 tp->nvram_pagesize = 256;
11361 break;
6b91fa02
MC		 11362 }
11363
11364 if (protect) {
11365 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11366 } else {
11367 switch (nvcfg1) {
8590a603
MC		 11368 case FLASH_5761VENDOR_ATMEL_ADB161D:
11369 case FLASH_5761VENDOR_ATMEL_MDB161D:
11370 case FLASH_5761VENDOR_ST_A_M45PE16:
11371 case FLASH_5761VENDOR_ST_M_M45PE16:
11372 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11373 break;
11374 case FLASH_5761VENDOR_ATMEL_ADB081D:
11375 case FLASH_5761VENDOR_ATMEL_MDB081D:
11376 case FLASH_5761VENDOR_ST_A_M45PE80:
11377 case FLASH_5761VENDOR_ST_M_M45PE80:
11378 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11379 break;
11380 case FLASH_5761VENDOR_ATMEL_ADB041D:
11381 case FLASH_5761VENDOR_ATMEL_MDB041D:
11382 case FLASH_5761VENDOR_ST_A_M45PE40:
11383 case FLASH_5761VENDOR_ST_M_M45PE40:
11384 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11385 break;
11386 case FLASH_5761VENDOR_ATMEL_ADB021D:
11387 case FLASH_5761VENDOR_ATMEL_MDB021D:
11388 case FLASH_5761VENDOR_ST_A_M45PE20:
11389 case FLASH_5761VENDOR_ST_M_M45PE20:
11390 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11391 break;
6b91fa02
MC		 11392 }
11393 }
11394}
11395
b5d3772c
MC		 11396static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11397{
11398 tp->nvram_jedecnum = JEDEC_ATMEL;
11399 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11400 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11401}
11402
321d32a0
MC		 11403static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11404{
11405 u32 nvcfg1;
11406
11407 nvcfg1 = tr32(NVRAM_CFG1);
11408
11409 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11410 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11411 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11412 tp->nvram_jedecnum = JEDEC_ATMEL;
11413 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11414 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11415
11416 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11417 tw32(NVRAM_CFG1, nvcfg1);
11418 return;
11419 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11420 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11421 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11422 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11423 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11424 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11425 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11426 tp->nvram_jedecnum = JEDEC_ATMEL;
11427 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11428 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11429
11430 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11431 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11432 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11433 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11434 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11435 break;
11436 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11437 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11438 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11439 break;
11440 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11441 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11442 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11443 break;
11444 }
11445 break;
11446 case FLASH_5752VENDOR_ST_M45PE10:
11447 case FLASH_5752VENDOR_ST_M45PE20:
11448 case FLASH_5752VENDOR_ST_M45PE40:
11449 tp->nvram_jedecnum = JEDEC_ST;
11450 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11451 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11452
11453 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11454 case FLASH_5752VENDOR_ST_M45PE10:
11455 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11456 break;
11457 case FLASH_5752VENDOR_ST_M45PE20:
11458 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11459 break;
11460 case FLASH_5752VENDOR_ST_M45PE40:
11461 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11462 break;
11463 }
11464 break;
11465 default:
df259d8c 11466 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11467 return;
11468 }
11469
a1b950d5
MC		 11470 tg3_nvram_get_pagesize(tp, nvcfg1);
11471 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11472 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11473}
11474
11475
11476static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11477{
11478 u32 nvcfg1;
11479
11480 nvcfg1 = tr32(NVRAM_CFG1);
11481
11482 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11483 case FLASH_5717VENDOR_ATMEL_EEPROM:
11484 case FLASH_5717VENDOR_MICRO_EEPROM:
11485 tp->nvram_jedecnum = JEDEC_ATMEL;
11486 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11487 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11488
11489 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11490 tw32(NVRAM_CFG1, nvcfg1);
11491 return;
11492 case FLASH_5717VENDOR_ATMEL_MDB011D:
11493 case FLASH_5717VENDOR_ATMEL_ADB011B:
11494 case FLASH_5717VENDOR_ATMEL_ADB011D:
11495 case FLASH_5717VENDOR_ATMEL_MDB021D:
11496 case FLASH_5717VENDOR_ATMEL_ADB021B:
11497 case FLASH_5717VENDOR_ATMEL_ADB021D:
11498 case FLASH_5717VENDOR_ATMEL_45USPT:
11499 tp->nvram_jedecnum = JEDEC_ATMEL;
11500 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11501 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11502
11503 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11504 case FLASH_5717VENDOR_ATMEL_MDB021D:
11505 case FLASH_5717VENDOR_ATMEL_ADB021B:
11506 case FLASH_5717VENDOR_ATMEL_ADB021D:
11507 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11508 break;
11509 default:
11510 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11511 break;
11512 }
321d32a0 11513 break;
a1b950d5
MC		 11514 case FLASH_5717VENDOR_ST_M_M25PE10:
11515 case FLASH_5717VENDOR_ST_A_M25PE10:
11516 case FLASH_5717VENDOR_ST_M_M45PE10:
11517 case FLASH_5717VENDOR_ST_A_M45PE10:
11518 case FLASH_5717VENDOR_ST_M_M25PE20:
11519 case FLASH_5717VENDOR_ST_A_M25PE20:
11520 case FLASH_5717VENDOR_ST_M_M45PE20:
11521 case FLASH_5717VENDOR_ST_A_M45PE20:
11522 case FLASH_5717VENDOR_ST_25USPT:
11523 case FLASH_5717VENDOR_ST_45USPT:
11524 tp->nvram_jedecnum = JEDEC_ST;
11525 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11526 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11527
11528 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11529 case FLASH_5717VENDOR_ST_M_M25PE20:
11530 case FLASH_5717VENDOR_ST_A_M25PE20:
11531 case FLASH_5717VENDOR_ST_M_M45PE20:
11532 case FLASH_5717VENDOR_ST_A_M45PE20:
11533 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11534 break;
11535 default:
11536 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11537 break;
11538 }
321d32a0 11539 break;
a1b950d5
MC		 11540 default:
11541 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11542 return;
321d32a0 11543 }
a1b950d5
MC		 11544
11545 tg3_nvram_get_pagesize(tp, nvcfg1);
11546 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11547 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11548}
11549
1da177e4
LT		 11550/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11551static void __devinit tg3_nvram_init(struct tg3 *tp)
11552{
1da177e4
LT		 11553 tw32_f(GRC_EEPROM_ADDR,
11554 (EEPROM_ADDR_FSM_RESET |
11555 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11556 EEPROM_ADDR_CLKPERD_SHIFT)));
11557
9d57f01c 11558 msleep(1);
1da177e4
LT		 11559
11560 /* Enable seeprom accesses. */
11561 tw32_f(GRC_LOCAL_CTRL,
11562 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11563 udelay(100);
11564
11565 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11566 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11567 tp->tg3_flags |= TG3_FLAG_NVRAM;
11568
ec41c7df 11569 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 11570 netdev_warn(tp->dev,
11571 "Cannot get nvram lock, %s failed\n",
05dbe005 11572 __func__);
ec41c7df
MC		 11573 return;
11574 }
e6af301b 11575 tg3_enable_nvram_access(tp);
1da177e4 11576
989a9d23
MC		 11577 tp->nvram_size = 0;
11578
361b4ac2
MC		 11579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11580 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11581 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11582 tg3_get_5755_nvram_info(tp);
d30cdd28 11583 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11584 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11585 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11586 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11587 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11588 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11589 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11590 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11591 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11592 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11593 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11594 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11595 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11596 else
11597 tg3_get_nvram_info(tp);
11598
989a9d23
MC		 11599 if (tp->nvram_size == 0)
11600 tg3_get_nvram_size(tp);
1da177e4 11601
e6af301b 11602 tg3_disable_nvram_access(tp);
381291b7 11603 tg3_nvram_unlock(tp);
1da177e4
LT		 11604
11605 } else {
11606 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11607
11608 tg3_get_eeprom_size(tp);
11609 }
11610}
11611
1da177e4
LT		 11612static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11613 u32 offset, u32 len, u8 *buf)
11614{
11615 int i, j, rc = 0;
11616 u32 val;
11617
11618 for (i = 0; i < len; i += 4) {
b9fc7dc5 11619 u32 addr;
a9dc529d 11620 __be32 data;
1da177e4
LT		 11621
11622 addr = offset + i;
11623
11624 memcpy(&data, buf + i, 4);
11625
62cedd11
MC		 11626 /*
11627 * The SEEPROM interface expects the data to always be opposite
11628 * the native endian format. We accomplish this by reversing
11629 * all the operations that would have been performed on the
11630 * data from a call to tg3_nvram_read_be32().
11631 */
11632 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11633
11634 val = tr32(GRC_EEPROM_ADDR);
11635 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11636
11637 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11638 EEPROM_ADDR_READ);
11639 tw32(GRC_EEPROM_ADDR, val |
11640 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11641 (addr & EEPROM_ADDR_ADDR_MASK) |
11642 EEPROM_ADDR_START |
11643 EEPROM_ADDR_WRITE);
6aa20a22 11644
9d57f01c 11645 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11646 val = tr32(GRC_EEPROM_ADDR);
11647
11648 if (val & EEPROM_ADDR_COMPLETE)
11649 break;
9d57f01c 11650 msleep(1);
1da177e4
LT		 11651 }
11652 if (!(val & EEPROM_ADDR_COMPLETE)) {
11653 rc = -EBUSY;
11654 break;
11655 }
11656 }
11657
11658 return rc;
11659}
11660
11661/* offset and length are dword aligned */
11662static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11663 u8 *buf)
11664{
11665 int ret = 0;
11666 u32 pagesize = tp->nvram_pagesize;
11667 u32 pagemask = pagesize - 1;
11668 u32 nvram_cmd;
11669 u8 *tmp;
11670
11671 tmp = kmalloc(pagesize, GFP_KERNEL);
11672 if (tmp == NULL)
11673 return -ENOMEM;
11674
11675 while (len) {
11676 int j;
e6af301b 11677 u32 phy_addr, page_off, size;
1da177e4
LT		 11678
11679 phy_addr = offset & ~pagemask;
6aa20a22 11680
1da177e4 11681 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11682 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11683 (__be32 *) (tmp + j));
11684 if (ret)
1da177e4
LT		 11685 break;
11686 }
11687 if (ret)
11688 break;
11689
c6cdf436 11690 page_off = offset & pagemask;
1da177e4
LT		 11691 size = pagesize;
11692 if (len < size)
11693 size = len;
11694
11695 len -= size;
11696
11697 memcpy(tmp + page_off, buf, size);
11698
11699 offset = offset + (pagesize - page_off);
11700
e6af301b 11701 tg3_enable_nvram_access(tp);
1da177e4
LT		 11702
11703 /*
11704 * Before we can erase the flash page, we need
11705 * to issue a special "write enable" command.
11706 */
11707 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11708
11709 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11710 break;
11711
11712 /* Erase the target page */
11713 tw32(NVRAM_ADDR, phy_addr);
11714
11715 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11716 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11717
c6cdf436 11718 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
1da177e4
LT		 11719 break;
11720
11721 /* Issue another write enable to start the write. */
11722 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11723
11724 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11725 break;
11726
11727 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11728 __be32 data;
1da177e4 11729
b9fc7dc5 11730 data = *((__be32 *) (tmp + j));
a9dc529d 11731
b9fc7dc5 11732 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11733
11734 tw32(NVRAM_ADDR, phy_addr + j);
11735
11736 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11737 NVRAM_CMD_WR;
11738
11739 if (j == 0)
11740 nvram_cmd |= NVRAM_CMD_FIRST;
11741 else if (j == (pagesize - 4))
11742 nvram_cmd |= NVRAM_CMD_LAST;
11743
11744 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11745 break;
11746 }
11747 if (ret)
11748 break;
11749 }
11750
11751 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11752 tg3_nvram_exec_cmd(tp, nvram_cmd);
11753
11754 kfree(tmp);
11755
11756 return ret;
11757}
11758
11759/* offset and length are dword aligned */
11760static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11761 u8 *buf)
11762{
11763 int i, ret = 0;
11764
11765 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11766 u32 page_off, phy_addr, nvram_cmd;
11767 __be32 data;
1da177e4
LT		 11768
11769 memcpy(&data, buf + i, 4);
b9fc7dc5 11770 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4 11771
c6cdf436 11772 page_off = offset % tp->nvram_pagesize;
1da177e4 11773
1820180b 11774 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11775
11776 tw32(NVRAM_ADDR, phy_addr);
11777
11778 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11779
c6cdf436 11780 if (page_off == 0 || i == 0)
1da177e4 11781 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11782 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11783 nvram_cmd |= NVRAM_CMD_LAST;
11784
11785 if (i == (len - 4))
11786 nvram_cmd |= NVRAM_CMD_LAST;
11787
321d32a0
MC		 11788 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11789 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11790 (tp->nvram_jedecnum == JEDEC_ST) &&
11791 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11792
11793 if ((ret = tg3_nvram_exec_cmd(tp,
11794 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11795 NVRAM_CMD_DONE)))
11796
11797 break;
11798 }
11799 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11800 /* We always do complete word writes to eeprom. */
11801 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11802 }
11803
11804 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11805 break;
11806 }
11807 return ret;
11808}
11809
11810/* offset and length are dword aligned */
11811static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11812{
11813 int ret;
11814
1da177e4 11815 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11816 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11817 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11818 udelay(40);
11819 }
11820
11821 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11822 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
859a5887 11823 } else {
1da177e4
LT		 11824 u32 grc_mode;
11825
ec41c7df
MC		 11826 ret = tg3_nvram_lock(tp);
11827 if (ret)
11828 return ret;
1da177e4 11829
e6af301b
MC		 11830 tg3_enable_nvram_access(tp);
11831 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11832 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11833 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11834
11835 grc_mode = tr32(GRC_MODE);
11836 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11837
11838 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11839 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11840
11841 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11842 buf);
859a5887 11843 } else {
1da177e4
LT		 11844 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11845 buf);
11846 }
11847
11848 grc_mode = tr32(GRC_MODE);
11849 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11850
e6af301b 11851 tg3_disable_nvram_access(tp);
1da177e4
LT		 11852 tg3_nvram_unlock(tp);
11853 }
11854
11855 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11856 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11857 udelay(40);
11858 }
11859
11860 return ret;
11861}
11862
11863struct subsys_tbl_ent {
11864 u16 subsys_vendor, subsys_devid;
11865 u32 phy_id;
11866};
11867
24daf2b0 11868static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
1da177e4 11869 /* Broadcom boards. */
24daf2b0 11870 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11871 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 11872 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11873 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 11874 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11875 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 11876 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11877 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11878 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11879 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 11880 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11881 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 11882 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11883 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11884 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11885 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 11886 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11887 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 11888 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11889 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 11890 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 11891 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 11892
11893 /* 3com boards. */
24daf2b0 11894 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11895 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 11896 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11897 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 11898 { TG3PCI_SUBVENDOR_ID_3COM,
11899 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11900 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11901 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 11902 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 11903 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 11904
11905 /* DELL boards. */
24daf2b0 11906 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11907 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 11908 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11909 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 11910 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11911 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 11912 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 11913 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 11914
11915 /* Compaq boards. */
24daf2b0 11916 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11917 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 11918 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11919 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 11920 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11921 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11922 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11923 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 11924 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 11925 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 11926
11927 /* IBM boards. */
24daf2b0
MC		 11928 { TG3PCI_SUBVENDOR_ID_IBM,
11929 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 11930};
11931
24daf2b0 11932static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 11933{
11934 int i;
11935
11936 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11937 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11938 tp->pdev->subsystem_vendor) &&
11939 (subsys_id_to_phy_id[i].subsys_devid ==
11940 tp->pdev->subsystem_device))
11941 return &subsys_id_to_phy_id[i];
11942 }
11943 return NULL;
11944}
11945
7d0c41ef 11946static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11947{
1da177e4 11948 u32 val;
caf636c7
MC		 11949 u16 pmcsr;
11950
11951 /* On some early chips the SRAM cannot be accessed in D3hot state,
11952 * so need make sure we're in D0.
11953 */
11954 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11955 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11956 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11957 msleep(1);
7d0c41ef
MC		 11958
11959 /* Make sure register accesses (indirect or otherwise)
11960 * will function correctly.
11961 */
11962 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11963 tp->misc_host_ctrl);
1da177e4 11964
f49639e6
DM		 11965 /* The memory arbiter has to be enabled in order for SRAM accesses
11966 * to succeed. Normally on powerup the tg3 chip firmware will make
11967 * sure it is enabled, but other entities such as system netboot
11968 * code might disable it.
11969 */
11970 val = tr32(MEMARB_MODE);
11971 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11972
79eb6904 11973 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 11974 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11975
a85feb8c
GZ		 11976 /* Assume an onboard device and WOL capable by default. */
11977 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11978
b5d3772c 11979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11980 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11981 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11982 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11983 }
0527ba35
MC		 11984 val = tr32(VCPU_CFGSHDW);
11985 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11986 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11987 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11988 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11989 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11990 goto done;
b5d3772c
MC		 11991 }
11992
1da177e4
LT		 11993 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11994 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11995 u32 nic_cfg, led_cfg;
a9daf367 11996 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11997 int eeprom_phy_serdes = 0;
1da177e4
LT		 11998
11999 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12000 tp->nic_sram_data_cfg = nic_cfg;
12001
12002 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12003 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12004 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12005 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12006 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12007 (ver > 0) && (ver < 0x100))
12008 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12009
a9daf367
MC		 12010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12011 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12012
1da177e4
LT		 12013 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12014 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12015 eeprom_phy_serdes = 1;
12016
12017 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12018 if (nic_phy_id != 0) {
12019 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12020 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12021
12022 eeprom_phy_id = (id1 >> 16) << 10;
12023 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12024 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12025 } else
12026 eeprom_phy_id = 0;
12027
7d0c41ef 12028 tp->phy_id = eeprom_phy_id;
747e8f8b 12029 if (eeprom_phy_serdes) {
d1ec96af
MC		 12030 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12032 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12033 else
12034 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12035 }
7d0c41ef 12036
cbf46853 12037 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12038 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12039 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12040 else
1da177e4
LT		 12041 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12042
12043 switch (led_cfg) {
12044 default:
12045 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12046 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12047 break;
12048
12049 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12050 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12051 break;
12052
12053 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12054 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12055
12056 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12057 * read on some older 5700/5701 bootcode.
12058 */
12059 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12060 ASIC_REV_5700 ||
12061 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12062 ASIC_REV_5701)
12063 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12064
1da177e4
LT		 12065 break;
12066
12067 case SHASTA_EXT_LED_SHARED:
12068 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12069 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12070 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12071 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12072 LED_CTRL_MODE_PHY_2);
12073 break;
12074
12075 case SHASTA_EXT_LED_MAC:
12076 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12077 break;
12078
12079 case SHASTA_EXT_LED_COMBO:
12080 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12081 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12082 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12083 LED_CTRL_MODE_PHY_2);
12084 break;
12085
855e1111 12086 }
1da177e4
LT		 12087
12088 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12090 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12091 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12092
b2a5c19c
MC		 12093 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12094 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12095
9d26e213 12096 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12097 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12098 if ((tp->pdev->subsystem_vendor ==
12099 PCI_VENDOR_ID_ARIMA) &&
12100 (tp->pdev->subsystem_device == 0x205a ||
12101 tp->pdev->subsystem_device == 0x2063))
12102 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12103 } else {
f49639e6 12104 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12105 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12106 }
1da177e4
LT		 12107
12108 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12109 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12110 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12111 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12112 }
b2b98d4a
MC		 12113
12114 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12115 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12116 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12117
a85feb8c
GZ		 12118 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12119 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12120 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12121
12dac075 12122 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12123 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12124 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12125
1da177e4
LT		 12126 if (cfg2 & (1 << 17))
12127 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12128
12129 /* serdes signal pre-emphasis in register 0x590 set by */
12130 /* bootcode if bit 18 is set */
12131 if (cfg2 & (1 << 18))
12132 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12133
321d32a0
MC		 12134 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12135 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12136 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12137 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12138
8ed5d97e
MC		 12139 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12140 u32 cfg3;
12141
12142 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12143 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12144 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12145 }
a9daf367 12146
14417063
MC		 12147 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12148 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
a9daf367
MC		 12149 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12150 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12151 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12152 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12153 }
05ac4cb7
MC		 12154done:
12155 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12156 device_set_wakeup_enable(&tp->pdev->dev,
12157 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12158}
12159
b2a5c19c
MC		 12160static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12161{
12162 int i;
12163 u32 val;
12164
12165 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12166 tw32(OTP_CTRL, cmd);
12167
12168 /* Wait for up to 1 ms for command to execute. */
12169 for (i = 0; i < 100; i++) {
12170 val = tr32(OTP_STATUS);
12171 if (val & OTP_STATUS_CMD_DONE)
12172 break;
12173 udelay(10);
12174 }
12175
12176 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12177}
12178
12179/* Read the gphy configuration from the OTP region of the chip. The gphy
12180 * configuration is a 32-bit value that straddles the alignment boundary.
12181 * We do two 32-bit reads and then shift and merge the results.
12182 */
12183static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12184{
12185 u32 bhalf_otp, thalf_otp;
12186
12187 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12188
12189 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12190 return 0;
12191
12192 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12193
12194 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12195 return 0;
12196
12197 thalf_otp = tr32(OTP_READ_DATA);
12198
12199 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12200
12201 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12202 return 0;
12203
12204 bhalf_otp = tr32(OTP_READ_DATA);
12205
12206 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12207}
12208
7d0c41ef
MC		 12209static int __devinit tg3_phy_probe(struct tg3 *tp)
12210{
12211 u32 hw_phy_id_1, hw_phy_id_2;
12212 u32 hw_phy_id, hw_phy_id_masked;
12213 int err;
1da177e4 12214
b02fd9e3
MC		 12215 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12216 return tg3_phy_init(tp);
12217
1da177e4 12218 /* Reading the PHY ID register can conflict with ASF
877d0310 12219 * firmware access to the PHY hardware.
1da177e4
LT		 12220 */
12221 err = 0;
0d3031d9
MC		 12222 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12223 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
79eb6904 12224 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 12225 } else {
12226 /* Now read the physical PHY_ID from the chip and verify
12227 * that it is sane. If it doesn't look good, we fall back
12228 * to either the hard-coded table based PHY_ID and failing
12229 * that the value found in the eeprom area.
12230 */
12231 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12232 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12233
12234 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12235 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12236 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12237
79eb6904 12238 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 12239 }
12240
79eb6904 12241 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 12242 tp->phy_id = hw_phy_id;
79eb6904 12243 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
1da177e4 12244 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12245 else
12246 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12247 } else {
79eb6904 12248 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 12249 /* Do nothing, phy ID already set up in
12250 * tg3_get_eeprom_hw_cfg().
12251 */
1da177e4
LT		 12252 } else {
12253 struct subsys_tbl_ent *p;
12254
12255 /* No eeprom signature? Try the hardcoded
12256 * subsys device table.
12257 */
24daf2b0 12258 p = tg3_lookup_by_subsys(tp);
1da177e4
LT		 12259 if (!p)
12260 return -ENODEV;
12261
12262 tp->phy_id = p->phy_id;
12263 if (!tp->phy_id ||
79eb6904 12264 tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 12265 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12266 }
12267 }
12268
747e8f8b 12269 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12270 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12271 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12272 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12273
12274 tg3_readphy(tp, MII_BMSR, &bmsr);
12275 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12276 (bmsr & BMSR_LSTATUS))
12277 goto skip_phy_reset;
6aa20a22 12278
1da177e4
LT		 12279 err = tg3_phy_reset(tp);
12280 if (err)
12281 return err;
12282
12283 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12284 ADVERTISE_100HALF | ADVERTISE_100FULL |
12285 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12286 tg3_ctrl = 0;
12287 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12288 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12289 MII_TG3_CTRL_ADV_1000_FULL);
12290 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12291 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12292 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12293 MII_TG3_CTRL_ENABLE_AS_MASTER);
12294 }
12295
3600d918
MC		 12296 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12297 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12298 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12299 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12300 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12301
12302 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12303 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12304
12305 tg3_writephy(tp, MII_BMCR,
12306 BMCR_ANENABLE | BMCR_ANRESTART);
12307 }
12308 tg3_phy_set_wirespeed(tp);
12309
12310 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12311 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12312 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12313 }
12314
12315skip_phy_reset:
79eb6904 12316 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 12317 err = tg3_init_5401phy_dsp(tp);
12318 if (err)
12319 return err;
1da177e4 12320
1da177e4
LT		 12321 err = tg3_init_5401phy_dsp(tp);
12322 }
12323
747e8f8b 12324 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12325 tp->link_config.advertising =
12326 (ADVERTISED_1000baseT_Half |
12327 ADVERTISED_1000baseT_Full |
12328 ADVERTISED_Autoneg |
12329 ADVERTISED_FIBRE);
12330 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12331 tp->link_config.advertising &=
12332 ~(ADVERTISED_1000baseT_Half |
12333 ADVERTISED_1000baseT_Full);
12334
12335 return err;
12336}
12337
184b8904 12338static void __devinit tg3_read_vpd(struct tg3 *tp)
1da177e4 12339{
184b8904 12340 u8 vpd_data[TG3_NVM_VPD_LEN];
4181b2c8 12341 unsigned int block_end, rosize, len;
184b8904 12342 int j, i = 0;
1b27777a 12343 u32 magic;
1da177e4 12344
df259d8c
MC		 12345 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12346 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12347 goto out_not_found;
1da177e4 12348
1820180b 12349 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12350 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12351 u32 tmp;
1da177e4 12352
6d348f2c
MC		 12353 /* The data is in little-endian format in NVRAM.
12354 * Use the big-endian read routines to preserve
12355 * the byte order as it exists in NVRAM.
12356 */
141518c9 12357 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12358 goto out_not_found;
12359
6d348f2c 12360 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12361 }
12362 } else {
94c982bd 12363 ssize_t cnt;
4181b2c8 12364 unsigned int pos = 0;
94c982bd
MC		 12365
12366 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12367 cnt = pci_read_vpd(tp->pdev, pos,
12368 TG3_NVM_VPD_LEN - pos,
12369 &vpd_data[pos]);
12370 if (cnt == -ETIMEDOUT || -EINTR)
12371 cnt = 0;
12372 else if (cnt < 0)
f49639e6 12373 goto out_not_found;
1b27777a 12374 }
94c982bd
MC		 12375 if (pos != TG3_NVM_VPD_LEN)
12376 goto out_not_found;
1da177e4
LT		 12377 }
12378
4181b2c8
MC		 12379 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12380 PCI_VPD_LRDT_RO_DATA);
12381 if (i < 0)
12382 goto out_not_found;
1da177e4 12383
4181b2c8
MC		 12384 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12385 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12386 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 12387
4181b2c8
MC		 12388 if (block_end > TG3_NVM_VPD_LEN)
12389 goto out_not_found;
af2c6a4a 12390
184b8904
MC		 12391 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12392 PCI_VPD_RO_KEYWORD_MFR_ID);
12393 if (j > 0) {
12394 len = pci_vpd_info_field_size(&vpd_data[j]);
12395
12396 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12397 if (j + len > block_end || len != 4 ||
12398 memcmp(&vpd_data[j], "1028", 4))
12399 goto partno;
12400
12401 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12402 PCI_VPD_RO_KEYWORD_VENDOR0);
12403 if (j < 0)
12404 goto partno;
12405
12406 len = pci_vpd_info_field_size(&vpd_data[j]);
12407
12408 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12409 if (j + len > block_end)
12410 goto partno;
12411
12412 memcpy(tp->fw_ver, &vpd_data[j], len);
12413 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12414 }
12415
12416partno:
4181b2c8
MC		 12417 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12418 PCI_VPD_RO_KEYWORD_PARTNO);
12419 if (i < 0)
12420 goto out_not_found;
af2c6a4a 12421
4181b2c8 12422 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 12423
4181b2c8
MC		 12424 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12425 if (len > TG3_BPN_SIZE ||
12426 (len + i) > TG3_NVM_VPD_LEN)
12427 goto out_not_found;
1da177e4 12428
4181b2c8 12429 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 12430
4181b2c8 12431 return;
1da177e4
LT		 12432
12433out_not_found:
b5d3772c
MC		 12434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12435 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12436 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12437 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12438 strcpy(tp->board_part_number, "BCM57780");
12439 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12440 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12441 strcpy(tp->board_part_number, "BCM57760");
12442 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12443 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12444 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12445 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12446 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12447 strcpy(tp->board_part_number, "BCM57788");
b474eca7
MC		 12448 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12449 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12450 strcpy(tp->board_part_number, "BCM57761");
12451 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12452 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
b703df6f 12453 strcpy(tp->board_part_number, "BCM57765");
b474eca7
MC		 12454 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12455 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12456 strcpy(tp->board_part_number, "BCM57781");
12457 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12458 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12459 strcpy(tp->board_part_number, "BCM57785");
12460 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12461 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12462 strcpy(tp->board_part_number, "BCM57791");
12463 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12464 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12465 strcpy(tp->board_part_number, "BCM57795");
b5d3772c
MC		 12466 else
12467 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12468}
12469
9c8a620e
MC		 12470static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12471{
12472 u32 val;
12473
e4f34110 12474 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12475 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12476 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12477 val != 0)
12478 return 0;
12479
12480 return 1;
12481}
12482
acd9c119
MC		 12483static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12484{
ff3a7cb2 12485 u32 val, offset, start, ver_offset;
75f9936e 12486 int i, dst_off;
ff3a7cb2 12487 bool newver = false;
acd9c119
MC		 12488
12489 if (tg3_nvram_read(tp, 0xc, &offset) ||
12490 tg3_nvram_read(tp, 0x4, &start))
12491 return;
12492
12493 offset = tg3_nvram_logical_addr(tp, offset);
12494
ff3a7cb2 12495 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12496 return;
12497
ff3a7cb2
MC		 12498 if ((val & 0xfc000000) == 0x0c000000) {
12499 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12500 return;
12501
ff3a7cb2
MC		 12502 if (val == 0)
12503 newver = true;
12504 }
12505
75f9936e
MC		 12506 dst_off = strlen(tp->fw_ver);
12507
ff3a7cb2 12508 if (newver) {
75f9936e
MC		 12509 if (TG3_VER_SIZE - dst_off < 16 ||
12510 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 12511 return;
12512
12513 offset = offset + ver_offset - start;
12514 for (i = 0; i < 16; i += 4) {
12515 __be32 v;
12516 if (tg3_nvram_read_be32(tp, offset + i, &v))
12517 return;
12518
75f9936e 12519 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 12520 }
12521 } else {
12522 u32 major, minor;
12523
12524 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12525 return;
12526
12527 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12528 TG3_NVM_BCVER_MAJSFT;
12529 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 12530 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12531 "v%d.%02d", major, minor);
acd9c119
MC		 12532 }
12533}
12534
a6f6cb1c
MC		 12535static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12536{
12537 u32 val, major, minor;
12538
12539 /* Use native endian representation */
12540 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12541 return;
12542
12543 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12544 TG3_NVM_HWSB_CFG1_MAJSFT;
12545 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12546 TG3_NVM_HWSB_CFG1_MINSFT;
12547
12548 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12549}
12550
dfe00d7d
MC		 12551static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12552{
12553 u32 offset, major, minor, build;
12554
75f9936e 12555 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 12556
12557 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12558 return;
12559
12560 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12561 case TG3_EEPROM_SB_REVISION_0:
12562 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12563 break;
12564 case TG3_EEPROM_SB_REVISION_2:
12565 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12566 break;
12567 case TG3_EEPROM_SB_REVISION_3:
12568 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12569 break;
a4153d40
MC		 12570 case TG3_EEPROM_SB_REVISION_4:
12571 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12572 break;
12573 case TG3_EEPROM_SB_REVISION_5:
12574 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12575 break;
dfe00d7d
MC		 12576 default:
12577 return;
12578 }
12579
e4f34110 12580 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12581 return;
12582
12583 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12584 TG3_EEPROM_SB_EDH_BLD_SHFT;
12585 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12586 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12587 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12588
12589 if (minor > 99 || build > 26)
12590 return;
12591
75f9936e
MC		 12592 offset = strlen(tp->fw_ver);
12593 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12594 " v%d.%02d", major, minor);
dfe00d7d
MC		 12595
12596 if (build > 0) {
75f9936e
MC		 12597 offset = strlen(tp->fw_ver);
12598 if (offset < TG3_VER_SIZE - 1)
12599 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 12600 }
12601}
12602
acd9c119 12603static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12604{
12605 u32 val, offset, start;
acd9c119 12606 int i, vlen;
9c8a620e
MC		 12607
12608 for (offset = TG3_NVM_DIR_START;
12609 offset < TG3_NVM_DIR_END;
12610 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12611 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12612 return;
12613
9c8a620e
MC		 12614 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12615 break;
12616 }
12617
12618 if (offset == TG3_NVM_DIR_END)
12619 return;
12620
12621 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12622 start = 0x08000000;
e4f34110 12623 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12624 return;
12625
e4f34110 12626 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12627 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12628 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12629 return;
12630
12631 offset += val - start;
12632
acd9c119 12633 vlen = strlen(tp->fw_ver);
9c8a620e 12634
acd9c119
MC		 12635 tp->fw_ver[vlen++] = ',';
12636 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12637
12638 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12639 __be32 v;
12640 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12641 return;
12642
b9fc7dc5 12643 offset += sizeof(v);
c4e6575c 12644
acd9c119
MC		 12645 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12646 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12647 break;
c4e6575c 12648 }
9c8a620e 12649
acd9c119
MC		 12650 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12651 vlen += sizeof(v);
c4e6575c 12652 }
acd9c119
MC		 12653}
12654
7fd76445
MC		 12655static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12656{
12657 int vlen;
12658 u32 apedata;
12659
12660 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12661 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12662 return;
12663
12664 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12665 if (apedata != APE_SEG_SIG_MAGIC)
12666 return;
12667
12668 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12669 if (!(apedata & APE_FW_STATUS_READY))
12670 return;
12671
12672 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12673
12674 vlen = strlen(tp->fw_ver);
12675
12676 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12677 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12678 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12679 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12680 (apedata & APE_FW_VERSION_BLDMSK));
12681}
12682
acd9c119
MC		 12683static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12684{
12685 u32 val;
75f9936e 12686 bool vpd_vers = false;
acd9c119 12687
75f9936e
MC		 12688 if (tp->fw_ver[0] != 0)
12689 vpd_vers = true;
df259d8c 12690
75f9936e
MC		 12691 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12692 strcat(tp->fw_ver, "sb");
df259d8c
MC		 12693 return;
12694 }
12695
acd9c119
MC		 12696 if (tg3_nvram_read(tp, 0, &val))
12697 return;
12698
12699 if (val == TG3_EEPROM_MAGIC)
12700 tg3_read_bc_ver(tp);
12701 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12702 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12703 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12704 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12705 else
12706 return;
12707
12708 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
75f9936e
MC		 12709 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12710 goto done;
acd9c119
MC		 12711
12712 tg3_read_mgmtfw_ver(tp);
9c8a620e 12713
75f9936e 12714done:
9c8a620e 12715 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12716}
12717
7544b097
MC		 12718static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12719
1da177e4
LT		 12720static int __devinit tg3_get_invariants(struct tg3 *tp)
12721{
12722 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4 12723 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
c6cdf436 12724 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004 12725 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
c6cdf436 12726 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12727 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12728 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12729 { },
12730 };
12731 u32 misc_ctrl_reg;
1da177e4
LT		 12732 u32 pci_state_reg, grc_misc_cfg;
12733 u32 val;
12734 u16 pci_cmd;
5e7dfd0f 12735 int err;
1da177e4 12736
1da177e4
LT		 12737 /* Force memory write invalidate off. If we leave it on,
12738 * then on 5700_BX chips we have to enable a workaround.
12739 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12740 * to match the cacheline size. The Broadcom driver have this
12741 * workaround but turns MWI off all the times so never uses
12742 * it. This seems to suggest that the workaround is insufficient.
12743 */
12744 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12745 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12746 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12747
12748 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12749 * has the register indirect write enable bit set before
12750 * we try to access any of the MMIO registers. It is also
12751 * critical that the PCI-X hw workaround situation is decided
12752 * before that as well.
12753 */
12754 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12755 &misc_ctrl_reg);
12756
12757 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12758 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12760 u32 prod_id_asic_rev;
12761
5001e2f6
MC		 12762 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12764 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12765 pci_read_config_dword(tp->pdev,
12766 TG3PCI_GEN2_PRODID_ASICREV,
12767 &prod_id_asic_rev);
b703df6f
MC		 12768 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12769 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12770 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12771 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12772 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12773 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12774 pci_read_config_dword(tp->pdev,
12775 TG3PCI_GEN15_PRODID_ASICREV,
12776 &prod_id_asic_rev);
f6eb9b1f
MC		 12777 else
12778 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12779 &prod_id_asic_rev);
12780
321d32a0 12781 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12782 }
1da177e4 12783
ff645bec
MC		 12784 /* Wrong chip ID in 5752 A0. This code can be removed later
12785 * as A0 is not in production.
12786 */
12787 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12788 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12789
6892914f
MC		 12790 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12791 * we need to disable memory and use config. cycles
12792 * only to access all registers. The 5702/03 chips
12793 * can mistakenly decode the special cycles from the
12794 * ICH chipsets as memory write cycles, causing corruption
12795 * of register and memory space. Only certain ICH bridges
12796 * will drive special cycles with non-zero data during the
12797 * address phase which can fall within the 5703's address
12798 * range. This is not an ICH bug as the PCI spec allows
12799 * non-zero address during special cycles. However, only
12800 * these ICH bridges are known to drive non-zero addresses
12801 * during special cycles.
12802 *
12803 * Since special cycles do not cross PCI bridges, we only
12804 * enable this workaround if the 5703 is on the secondary
12805 * bus of these ICH bridges.
12806 */
12807 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12808 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12809 static struct tg3_dev_id {
12810 u32 vendor;
12811 u32 device;
12812 u32 rev;
12813 } ich_chipsets[] = {
12814 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12815 PCI_ANY_ID },
12816 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12817 PCI_ANY_ID },
12818 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12819 0xa },
12820 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12821 PCI_ANY_ID },
12822 { },
12823 };
12824 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12825 struct pci_dev *bridge = NULL;
12826
12827 while (pci_id->vendor != 0) {
12828 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12829 bridge);
12830 if (!bridge) {
12831 pci_id++;
12832 continue;
12833 }
12834 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12835 if (bridge->revision > pci_id->rev)
6892914f
MC		 12836 continue;
12837 }
12838 if (bridge->subordinate &&
12839 (bridge->subordinate->number ==
12840 tp->pdev->bus->number)) {
12841
12842 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12843 pci_dev_put(bridge);
12844 break;
12845 }
12846 }
12847 }
12848
41588ba1
MC		 12849 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12850 static struct tg3_dev_id {
12851 u32 vendor;
12852 u32 device;
12853 } bridge_chipsets[] = {
12854 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12855 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12856 { },
12857 };
12858 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12859 struct pci_dev *bridge = NULL;
12860
12861 while (pci_id->vendor != 0) {
12862 bridge = pci_get_device(pci_id->vendor,
12863 pci_id->device,
12864 bridge);
12865 if (!bridge) {
12866 pci_id++;
12867 continue;
12868 }
12869 if (bridge->subordinate &&
12870 (bridge->subordinate->number <=
12871 tp->pdev->bus->number) &&
12872 (bridge->subordinate->subordinate >=
12873 tp->pdev->bus->number)) {
12874 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12875 pci_dev_put(bridge);
12876 break;
12877 }
12878 }
12879 }
12880
4a29cc2e
MC		 12881 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12882 * DMA addresses > 40-bit. This bridge may have other additional
12883 * 57xx devices behind it in some 4-port NIC designs for example.
12884 * Any tg3 device found behind the bridge will also need the 40-bit
12885 * DMA workaround.
12886 */
a4e2b347
MC		 12887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12889 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12890 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12891 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
859a5887 12892 } else {
4a29cc2e
MC		 12893 struct pci_dev *bridge = NULL;
12894
12895 do {
12896 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12897 PCI_DEVICE_ID_SERVERWORKS_EPB,
12898 bridge);
12899 if (bridge && bridge->subordinate &&
12900 (bridge->subordinate->number <=
12901 tp->pdev->bus->number) &&
12902 (bridge->subordinate->subordinate >=
12903 tp->pdev->bus->number)) {
12904 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12905 pci_dev_put(bridge);
12906 break;
12907 }
12908 } while (bridge);
12909 }
4cf78e4f 12910
1da177e4
LT		 12911 /* Initialize misc host control in PCI block. */
12912 tp->misc_host_ctrl |= (misc_ctrl_reg &
12913 MISC_HOST_CTRL_CHIPREV);
12914 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12915 tp->misc_host_ctrl);
12916
f6eb9b1f
MC		 12917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12918 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12920 tp->pdev_peer = tg3_find_peer(tp);
12921
321d32a0
MC		 12922 /* Intentionally exclude ASIC_REV_5906 */
12923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 12928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 12929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 12931 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12932
12933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12936 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12937 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12938 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12939
1b440c56
JL		 12940 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12941 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12942 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12943
027455ad
MC		 12944 /* 5700 B0 chips do not support checksumming correctly due
12945 * to hardware bugs.
12946 */
12947 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12948 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12949 else {
12950 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12951 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12952 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12953 tp->dev->features |= NETIF_F_IPV6_CSUM;
12954 }
12955
507399f1 12956 /* Determine TSO capabilities */
b703df6f
MC		 12957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 12959 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12960 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12961 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 12962 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12963 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12964 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12966 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12967 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12968 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12969 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12970 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12971 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12972 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12973 tp->fw_needed = FIRMWARE_TG3TSO5;
12974 else
12975 tp->fw_needed = FIRMWARE_TG3TSO;
12976 }
12977
12978 tp->irq_max = 1;
12979
5a6f3074 12980 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12981 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12982 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12983 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12984 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12985 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12986 tp->pdev_peer == tp->pdev))
12987 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12988
321d32a0 12989 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 12991 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12992 }
4f125f42 12993
b703df6f
MC		 12994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 12996 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12997 tp->irq_max = TG3_IRQ_MAX_VECS;
12998 }
f6eb9b1f 12999 }
0e1406dd 13000
615774fe
MC		 13001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13003 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13004 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13005 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13006 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13007 }
f6eb9b1f 13008
b703df6f
MC		 13009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13011 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13012
f51f3562 13013 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
c6cdf436
MC		 13014 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13015 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13016 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13017
52f4490c
MC		 13018 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13019 &pci_state_reg);
13020
5e7dfd0f
MC		 13021 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13022 if (tp->pcie_cap != 0) {
13023 u16 lnkctl;
13024
1da177e4 13025 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13026
13027 pcie_set_readrq(tp->pdev, 4096);
13028
5e7dfd0f
MC		 13029 pci_read_config_word(tp->pdev,
13030 tp->pcie_cap + PCI_EXP_LNKCTL,
13031 &lnkctl);
13032 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13034 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13037 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13038 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13039 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13040 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13041 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13042 }
52f4490c 13043 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13044 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13045 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13046 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13047 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13048 if (!tp->pcix_cap) {
2445e461
MC		 13049 dev_err(&tp->pdev->dev,
13050 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 13051 return -EIO;
13052 }
13053
13054 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13055 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13056 }
1da177e4 13057
399de50b
MC		 13058 /* If we have an AMD 762 or VIA K8T800 chipset, write
13059 * reordering to the mailbox registers done by the host
13060 * controller can cause major troubles. We read back from
13061 * every mailbox register write to force the writes to be
13062 * posted to the chip in order.
13063 */
13064 if (pci_dev_present(write_reorder_chipsets) &&
13065 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13066 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13067
69fc4053
MC		 13068 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13069 &tp->pci_cacheline_sz);
13070 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13071 &tp->pci_lat_timer);
1da177e4
LT		 13072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13073 tp->pci_lat_timer < 64) {
13074 tp->pci_lat_timer = 64;
69fc4053
MC		 13075 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13076 tp->pci_lat_timer);
1da177e4
LT		 13077 }
13078
52f4490c
MC		 13079 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13080 /* 5700 BX chips need to have their TX producer index
13081 * mailboxes written twice to workaround a bug.
13082 */
13083 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13084
52f4490c 13085 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13086 *
13087 * The workaround is to use indirect register accesses
13088 * for all chip writes not to mailbox registers.
13089 */
52f4490c 13090 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13091 u32 pm_reg;
1da177e4
LT		 13092
13093 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13094
13095 /* The chip can have it's power management PCI config
13096 * space registers clobbered due to this bug.
13097 * So explicitly force the chip into D0 here.
13098 */
9974a356
MC		 13099 pci_read_config_dword(tp->pdev,
13100 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13101 &pm_reg);
13102 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13103 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13104 pci_write_config_dword(tp->pdev,
13105 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13106 pm_reg);
13107
13108 /* Also, force SERR#/PERR# in PCI command. */
13109 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13110 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13111 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13112 }
13113 }
13114
1da177e4
LT		 13115 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13116 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13117 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13118 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13119
13120 /* Chip-specific fixup from Broadcom driver */
13121 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13122 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13123 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13124 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13125 }
13126
1ee582d8 13127 /* Default fast path register access methods */
20094930 13128 tp->read32 = tg3_read32;
1ee582d8 13129 tp->write32 = tg3_write32;
09ee929c 13130 tp->read32_mbox = tg3_read32;
20094930 13131 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13132 tp->write32_tx_mbox = tg3_write32;
13133 tp->write32_rx_mbox = tg3_write32;
13134
13135 /* Various workaround register access methods */
13136 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13137 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13138 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13139 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13140 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13141 /*
13142 * Back to back register writes can cause problems on these
13143 * chips, the workaround is to read back all reg writes
13144 * except those to mailbox regs.
13145 *
13146 * See tg3_write_indirect_reg32().
13147 */
1ee582d8 13148 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13149 }
13150
1ee582d8
MC		 13151 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13152 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13153 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13154 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13155 tp->write32_rx_mbox = tg3_write_flush_reg32;
13156 }
20094930 13157
6892914f
MC		 13158 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13159 tp->read32 = tg3_read_indirect_reg32;
13160 tp->write32 = tg3_write_indirect_reg32;
13161 tp->read32_mbox = tg3_read_indirect_mbox;
13162 tp->write32_mbox = tg3_write_indirect_mbox;
13163 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13164 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13165
13166 iounmap(tp->regs);
22abe310 13167 tp->regs = NULL;
6892914f
MC		 13168
13169 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13170 pci_cmd &= ~PCI_COMMAND_MEMORY;
13171 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13172 }
b5d3772c
MC		 13173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13174 tp->read32_mbox = tg3_read32_mbox_5906;
13175 tp->write32_mbox = tg3_write32_mbox_5906;
13176 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13177 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13178 }
6892914f 13179
bbadf503
MC		 13180 if (tp->write32 == tg3_write_indirect_reg32 ||
13181 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13182 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13183 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13184 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13185
7d0c41ef 13186 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13187 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13188 * determined before calling tg3_set_power_state() so that
13189 * we know whether or not to switch out of Vaux power.
13190 * When the flag is set, it means that GPIO1 is used for eeprom
13191 * write protect and also implies that it is a LOM where GPIOs
13192 * are not used to switch power.
6aa20a22 13193 */
7d0c41ef
MC		 13194 tg3_get_eeprom_hw_cfg(tp);
13195
0d3031d9
MC		 13196 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13197 /* Allow reads and writes to the
13198 * APE register and memory space.
13199 */
13200 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13201 PCISTATE_ALLOW_APE_SHMEM_WR;
13202 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13203 pci_state_reg);
13204 }
13205
9936bcf6 13206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13208 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13212 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13213
314fba34
MC		 13214 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13215 * GPIO1 driven high will bring 5700's external PHY out of reset.
13216 * It is also used as eeprom write protect on LOMs.
13217 */
13218 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13219 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13220 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13221 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13222 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13223 /* Unused GPIO3 must be driven as output on 5752 because there
13224 * are no pull-up resistors on unused GPIO pins.
13225 */
13226 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13227 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13228
321d32a0 13229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13232 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13233
8d519ab2
MC		 13234 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13235 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13236 /* Turn off the debug UART. */
13237 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13238 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13239 /* Keep VMain power. */
13240 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13241 GRC_LCLCTRL_GPIO_OUTPUT0;
13242 }
13243
1da177e4 13244 /* Force the chip into D0. */
bc1c7567 13245 err = tg3_set_power_state(tp, PCI_D0);
1da177e4 13246 if (err) {
2445e461 13247 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
1da177e4
LT		 13248 return err;
13249 }
13250
1da177e4
LT		 13251 /* Derive initial jumbo mode from MTU assigned in
13252 * ether_setup() via the alloc_etherdev() call
13253 */
0f893dc6 13254 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13255 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13256 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13257
13258 /* Determine WakeOnLan speed to use. */
13259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13260 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13261 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13262 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13263 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13264 } else {
13265 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13266 }
13267
7f97a4bd
MC		 13268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13269 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13270
1da177e4
LT		 13271 /* A few boards don't want Ethernet@WireSpeed phy feature */
13272 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13273 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13274 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13275 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13276 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13277 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13278 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13279
13280 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13281 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13282 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13283 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13284 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13285
321d32a0 13286 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13287 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13288 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13289 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13290 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13291 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13294 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13295 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13296 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13297 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13298 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13299 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13300 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13301 } else
c424cb24
MC		 13302 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13303 }
1da177e4 13304
b2a5c19c
MC		 13305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13306 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13307 tp->phy_otp = tg3_read_otp_phycfg(tp);
13308 if (tp->phy_otp == 0)
13309 tp->phy_otp = TG3_OTP_DEFAULT;
13310 }
13311
f51f3562 13312 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13313 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13314 else
13315 tp->mi_mode = MAC_MI_MODE_BASE;
13316
1da177e4 13317 tp->coalesce_mode = 0;
1da177e4
LT		 13318 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13319 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13320 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13321
321d32a0
MC		 13322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13324 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13325
158d7abd
MC		 13326 err = tg3_mdio_init(tp);
13327 if (err)
13328 return err;
1da177e4 13329
55dffe79
MC		 13330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13331 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13332 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13333 return -ENOTSUPP;
13334
1da177e4
LT		 13335 /* Initialize data/descriptor byte/word swapping. */
13336 val = tr32(GRC_MODE);
13337 val &= GRC_MODE_HOST_STACKUP;
13338 tw32(GRC_MODE, val | tp->grc_mode);
13339
13340 tg3_switch_clocks(tp);
13341
13342 /* Clear this out for sanity. */
13343 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13344
13345 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13346 &pci_state_reg);
13347 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13348 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13349 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13350
13351 if (chiprevid == CHIPREV_ID_5701_A0 ||
13352 chiprevid == CHIPREV_ID_5701_B0 ||
13353 chiprevid == CHIPREV_ID_5701_B2 ||
13354 chiprevid == CHIPREV_ID_5701_B5) {
13355 void __iomem *sram_base;
13356
13357 /* Write some dummy words into the SRAM status block
13358 * area, see if it reads back correctly. If the return
13359 * value is bad, force enable the PCIX workaround.
13360 */
13361 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13362
13363 writel(0x00000000, sram_base);
13364 writel(0x00000000, sram_base + 4);
13365 writel(0xffffffff, sram_base + 4);
13366 if (readl(sram_base) != 0x00000000)
13367 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13368 }
13369 }
13370
13371 udelay(50);
13372 tg3_nvram_init(tp);
13373
13374 grc_misc_cfg = tr32(GRC_MISC_CFG);
13375 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13376
1da177e4
LT		 13377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13378 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13379 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13380 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13381
fac9b83e
DM		 13382 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13383 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13384 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13385 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13386 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13387 HOSTCC_MODE_CLRTICK_TXBD);
13388
13389 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13390 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13391 tp->misc_host_ctrl);
13392 }
13393
3bda1258
MC		 13394 /* Preserve the APE MAC_MODE bits */
13395 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13396 tp->mac_mode = tr32(MAC_MODE) |
13397 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13398 else
13399 tp->mac_mode = TG3_DEF_MAC_MODE;
13400
1da177e4
LT		 13401 /* these are limited to 10/100 only */
13402 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13403 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13404 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13405 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13406 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13407 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13408 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13409 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13410 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13411 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13412 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13413 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
d1101142
MC		 13414 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13415 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
7f97a4bd 13416 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13417 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13418
13419 err = tg3_phy_probe(tp);
13420 if (err) {
2445e461 13421 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 13422 /* ... but do not return immediately ... */
b02fd9e3 13423 tg3_mdio_fini(tp);
1da177e4
LT		 13424 }
13425
184b8904 13426 tg3_read_vpd(tp);
c4e6575c 13427 tg3_read_fw_ver(tp);
1da177e4
LT		 13428
13429 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13430 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13431 } else {
13432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13433 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13434 else
13435 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13436 }
13437
13438 /* 5700 {AX,BX} chips have a broken status block link
13439 * change bit implementation, so we must use the
13440 * status register in those cases.
13441 */
13442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13443 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13444 else
13445 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13446
13447 /* The led_ctrl is set during tg3_phy_probe, here we might
13448 * have to force the link status polling mechanism based
13449 * upon subsystem IDs.
13450 */
13451 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13452 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13453 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13454 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13455 TG3_FLAG_USE_LINKCHG_REG);
13456 }
13457
13458 /* For all SERDES we poll the MAC status register. */
13459 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13460 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13461 else
13462 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13463
ad829268 13464 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13466 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13467 tp->rx_offset = 0;
13468
f92905de
MC		 13469 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13470
13471 /* Increment the rx prod index on the rx std ring by at most
13472 * 8 for these chips to workaround hw errata.
13473 */
13474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13477 tp->rx_std_max_post = 8;
13478
8ed5d97e
MC		 13479 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13480 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13481 PCIE_PWR_MGMT_L1_THRESH_MSK;
13482
1da177e4
LT		 13483 return err;
13484}
13485
49b6e95f 13486#ifdef CONFIG_SPARC
1da177e4
LT		 13487static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13488{
13489 struct net_device *dev = tp->dev;
13490 struct pci_dev *pdev = tp->pdev;
49b6e95f 13491 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13492 const unsigned char *addr;
49b6e95f
DM		 13493 int len;
13494
13495 addr = of_get_property(dp, "local-mac-address", &len);
13496 if (addr && len == 6) {
13497 memcpy(dev->dev_addr, addr, 6);
13498 memcpy(dev->perm_addr, dev->dev_addr, 6);
13499 return 0;
1da177e4
LT		 13500 }
13501 return -ENODEV;
13502}
13503
13504static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13505{
13506 struct net_device *dev = tp->dev;
13507
13508 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13509 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13510 return 0;
13511}
13512#endif
13513
13514static int __devinit tg3_get_device_address(struct tg3 *tp)
13515{
13516 struct net_device *dev = tp->dev;
13517 u32 hi, lo, mac_offset;
008652b3 13518 int addr_ok = 0;
1da177e4 13519
49b6e95f 13520#ifdef CONFIG_SPARC
1da177e4
LT		 13521 if (!tg3_get_macaddr_sparc(tp))
13522 return 0;
13523#endif
13524
13525 mac_offset = 0x7c;
f49639e6 13526 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13527 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13528 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13529 mac_offset = 0xcc;
13530 if (tg3_nvram_lock(tp))
13531 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13532 else
13533 tg3_nvram_unlock(tp);
a1b950d5
MC		 13534 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13535 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13536 mac_offset = 0xcc;
13537 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13538 mac_offset = 0x10;
1da177e4
LT		 13539
13540 /* First try to get it from MAC address mailbox. */
13541 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13542 if ((hi >> 16) == 0x484b) {
13543 dev->dev_addr[0] = (hi >> 8) & 0xff;
13544 dev->dev_addr[1] = (hi >> 0) & 0xff;
13545
13546 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13547 dev->dev_addr[2] = (lo >> 24) & 0xff;
13548 dev->dev_addr[3] = (lo >> 16) & 0xff;
13549 dev->dev_addr[4] = (lo >> 8) & 0xff;
13550 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13551
008652b3
MC		 13552 /* Some old bootcode may report a 0 MAC address in SRAM */
13553 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13554 }
13555 if (!addr_ok) {
13556 /* Next, try NVRAM. */
df259d8c
MC		 13557 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13558 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13559 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13560 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13561 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13562 }
13563 /* Finally just fetch it out of the MAC control regs. */
13564 else {
13565 hi = tr32(MAC_ADDR_0_HIGH);
13566 lo = tr32(MAC_ADDR_0_LOW);
13567
13568 dev->dev_addr[5] = lo & 0xff;
13569 dev->dev_addr[4] = (lo >> 8) & 0xff;
13570 dev->dev_addr[3] = (lo >> 16) & 0xff;
13571 dev->dev_addr[2] = (lo >> 24) & 0xff;
13572 dev->dev_addr[1] = hi & 0xff;
13573 dev->dev_addr[0] = (hi >> 8) & 0xff;
13574 }
1da177e4
LT		 13575 }
13576
13577 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13578#ifdef CONFIG_SPARC
1da177e4
LT		 13579 if (!tg3_get_default_macaddr_sparc(tp))
13580 return 0;
13581#endif
13582 return -EINVAL;
13583 }
2ff43697 13584 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13585 return 0;
13586}
13587
59e6b434
DM		 13588#define BOUNDARY_SINGLE_CACHELINE 1
13589#define BOUNDARY_MULTI_CACHELINE 2
13590
13591static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13592{
13593 int cacheline_size;
13594 u8 byte;
13595 int goal;
13596
13597 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13598 if (byte == 0)
13599 cacheline_size = 1024;
13600 else
13601 cacheline_size = (int) byte * 4;
13602
13603 /* On 5703 and later chips, the boundary bits have no
13604 * effect.
13605 */
13606 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13607 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13608 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13609 goto out;
13610
13611#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13612 goal = BOUNDARY_MULTI_CACHELINE;
13613#else
13614#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13615 goal = BOUNDARY_SINGLE_CACHELINE;
13616#else
13617 goal = 0;
13618#endif
13619#endif
13620
b703df6f
MC		 13621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13623 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13624 goto out;
13625 }
13626
59e6b434
DM		 13627 if (!goal)
13628 goto out;
13629
13630 /* PCI controllers on most RISC systems tend to disconnect
13631 * when a device tries to burst across a cache-line boundary.
13632 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13633 *
13634 * Unfortunately, for PCI-E there are only limited
13635 * write-side controls for this, and thus for reads
13636 * we will still get the disconnects. We'll also waste
13637 * these PCI cycles for both read and write for chips
13638 * other than 5700 and 5701 which do not implement the
13639 * boundary bits.
13640 */
13641 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13642 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13643 switch (cacheline_size) {
13644 case 16:
13645 case 32:
13646 case 64:
13647 case 128:
13648 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13649 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13650 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13651 } else {
13652 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13653 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13654 }
13655 break;
13656
13657 case 256:
13658 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13659 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13660 break;
13661
13662 default:
13663 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13664 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13665 break;
855e1111 13666 }
59e6b434
DM		 13667 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13668 switch (cacheline_size) {
13669 case 16:
13670 case 32:
13671 case 64:
13672 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13673 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13674 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13675 break;
13676 }
13677 /* fallthrough */
13678 case 128:
13679 default:
13680 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13681 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13682 break;
855e1111 13683 }
59e6b434
DM		 13684 } else {
13685 switch (cacheline_size) {
13686 case 16:
13687 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13688 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13689 DMA_RWCTRL_WRITE_BNDRY_16);
13690 break;
13691 }
13692 /* fallthrough */
13693 case 32:
13694 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13695 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13696 DMA_RWCTRL_WRITE_BNDRY_32);
13697 break;
13698 }
13699 /* fallthrough */
13700 case 64:
13701 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13702 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13703 DMA_RWCTRL_WRITE_BNDRY_64);
13704 break;
13705 }
13706 /* fallthrough */
13707 case 128:
13708 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13709 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13710 DMA_RWCTRL_WRITE_BNDRY_128);
13711 break;
13712 }
13713 /* fallthrough */
13714 case 256:
13715 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13716 DMA_RWCTRL_WRITE_BNDRY_256);
13717 break;
13718 case 512:
13719 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13720 DMA_RWCTRL_WRITE_BNDRY_512);
13721 break;
13722 case 1024:
13723 default:
13724 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13725 DMA_RWCTRL_WRITE_BNDRY_1024);
13726 break;
855e1111 13727 }
59e6b434
DM		 13728 }
13729
13730out:
13731 return val;
13732}
13733
1da177e4
LT		 13734static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13735{
13736 struct tg3_internal_buffer_desc test_desc;
13737 u32 sram_dma_descs;
13738 int i, ret;
13739
13740 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13741
13742 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13743 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13744 tw32(RDMAC_STATUS, 0);
13745 tw32(WDMAC_STATUS, 0);
13746
13747 tw32(BUFMGR_MODE, 0);
13748 tw32(FTQ_RESET, 0);
13749
13750 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13751 test_desc.addr_lo = buf_dma & 0xffffffff;
13752 test_desc.nic_mbuf = 0x00002100;
13753 test_desc.len = size;
13754
13755 /*
13756 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13757 * the *second* time the tg3 driver was getting loaded after an
13758 * initial scan.
13759 *
13760 * Broadcom tells me:
13761 * ...the DMA engine is connected to the GRC block and a DMA
13762 * reset may affect the GRC block in some unpredictable way...
13763 * The behavior of resets to individual blocks has not been tested.
13764 *
13765 * Broadcom noted the GRC reset will also reset all sub-components.
13766 */
13767 if (to_device) {
13768 test_desc.cqid_sqid = (13 << 8) | 2;
13769
13770 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13771 udelay(40);
13772 } else {
13773 test_desc.cqid_sqid = (16 << 8) | 7;
13774
13775 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13776 udelay(40);
13777 }
13778 test_desc.flags = 0x00000005;
13779
13780 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13781 u32 val;
13782
13783 val = *(((u32 *)&test_desc) + i);
13784 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13785 sram_dma_descs + (i * sizeof(u32)));
13786 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13787 }
13788 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13789
859a5887 13790 if (to_device)
1da177e4 13791 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 13792 else
1da177e4 13793 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 13794
13795 ret = -ENODEV;
13796 for (i = 0; i < 40; i++) {
13797 u32 val;
13798
13799 if (to_device)
13800 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13801 else
13802 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13803 if ((val & 0xffff) == sram_dma_descs) {
13804 ret = 0;
13805 break;
13806 }
13807
13808 udelay(100);
13809 }
13810
13811 return ret;
13812}
13813
ded7340d 13814#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13815
13816static int __devinit tg3_test_dma(struct tg3 *tp)
13817{
13818 dma_addr_t buf_dma;
59e6b434 13819 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13820 int ret = 0;
1da177e4
LT		 13821
13822 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13823 if (!buf) {
13824 ret = -ENOMEM;
13825 goto out_nofree;
13826 }
13827
13828 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13829 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13830
59e6b434 13831 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13832
b703df6f
MC		 13833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13835 goto out;
13836
1da177e4
LT		 13837 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13838 /* DMA read watermark not used on PCIE */
13839 tp->dma_rwctrl |= 0x00180000;
13840 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13843 tp->dma_rwctrl |= 0x003f0000;
13844 else
13845 tp->dma_rwctrl |= 0x003f000f;
13846 } else {
13847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13849 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13850 u32 read_water = 0x7;
1da177e4 13851
4a29cc2e
MC		 13852 /* If the 5704 is behind the EPB bridge, we can
13853 * do the less restrictive ONE_DMA workaround for
13854 * better performance.
13855 */
13856 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13858 tp->dma_rwctrl |= 0x8000;
13859 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13860 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13861
49afdeb6
MC		 13862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13863 read_water = 4;
59e6b434 13864 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13865 tp->dma_rwctrl |=
13866 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13867 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13868 (1 << 23);
4cf78e4f
MC		 13869 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13870 /* 5780 always in PCIX mode */
13871 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13872 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13873 /* 5714 always in PCIX mode */
13874 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13875 } else {
13876 tp->dma_rwctrl |= 0x001b000f;
13877 }
13878 }
13879
13880 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13882 tp->dma_rwctrl &= 0xfffffff0;
13883
13884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13886 /* Remove this if it causes problems for some boards. */
13887 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13888
13889 /* On 5700/5701 chips, we need to set this bit.
13890 * Otherwise the chip will issue cacheline transactions
13891 * to streamable DMA memory with not all the byte
13892 * enables turned on. This is an error on several
13893 * RISC PCI controllers, in particular sparc64.
13894 *
13895 * On 5703/5704 chips, this bit has been reassigned
13896 * a different meaning. In particular, it is used
13897 * on those chips to enable a PCI-X workaround.
13898 */
13899 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13900 }
13901
13902 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13903
13904#if 0
13905 /* Unneeded, already done by tg3_get_invariants. */
13906 tg3_switch_clocks(tp);
13907#endif
13908
1da177e4
LT		 13909 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13910 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13911 goto out;
13912
59e6b434
DM		 13913 /* It is best to perform DMA test with maximum write burst size
13914 * to expose the 5700/5701 write DMA bug.
13915 */
13916 saved_dma_rwctrl = tp->dma_rwctrl;
13917 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13918 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13919
1da177e4
LT		 13920 while (1) {
13921 u32 *p = buf, i;
13922
13923 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13924 p[i] = i;
13925
13926 /* Send the buffer to the chip. */
13927 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13928 if (ret) {
2445e461
MC		 13929 dev_err(&tp->pdev->dev,
13930 "%s: Buffer write failed. err = %d\n",
13931 __func__, ret);
1da177e4
LT		 13932 break;
13933 }
13934
13935#if 0
13936 /* validate data reached card RAM correctly. */
13937 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13938 u32 val;
13939 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13940 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 13941 dev_err(&tp->pdev->dev,
13942 "%s: Buffer corrupted on device! "
13943 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 13944 /* ret = -ENODEV here? */
13945 }
13946 p[i] = 0;
13947 }
13948#endif
13949 /* Now read it back. */
13950 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13951 if (ret) {
5129c3a3
MC		 13952 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
13953 "err = %d\n", __func__, ret);
1da177e4
LT		 13954 break;
13955 }
13956
13957 /* Verify it. */
13958 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13959 if (p[i] == i)
13960 continue;
13961
59e6b434
DM		 13962 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13963 DMA_RWCTRL_WRITE_BNDRY_16) {
13964 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13965 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13966 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13967 break;
13968 } else {
2445e461
MC		 13969 dev_err(&tp->pdev->dev,
13970 "%s: Buffer corrupted on read back! "
13971 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 13972 ret = -ENODEV;
13973 goto out;
13974 }
13975 }
13976
13977 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13978 /* Success. */
13979 ret = 0;
13980 break;
13981 }
13982 }
59e6b434
DM		 13983 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13984 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13985 static struct pci_device_id dma_wait_state_chipsets[] = {
13986 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13987 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13988 { },
13989 };
13990
59e6b434 13991 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13992 * now look for chipsets that are known to expose the
13993 * DMA bug without failing the test.
59e6b434 13994 */
6d1cfbab
MC		 13995 if (pci_dev_present(dma_wait_state_chipsets)) {
13996 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13997 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 13998 } else {
6d1cfbab
MC		 13999 /* Safe to use the calculated DMA boundary. */
14000 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 14001 }
6d1cfbab 14002
59e6b434
DM		 14003 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14004 }
1da177e4
LT		 14005
14006out:
14007 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14008out_nofree:
14009 return ret;
14010}
14011
14012static void __devinit tg3_init_link_config(struct tg3 *tp)
14013{
14014 tp->link_config.advertising =
14015 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14016 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14017 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14018 ADVERTISED_Autoneg | ADVERTISED_MII);
14019 tp->link_config.speed = SPEED_INVALID;
14020 tp->link_config.duplex = DUPLEX_INVALID;
14021 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14022 tp->link_config.active_speed = SPEED_INVALID;
14023 tp->link_config.active_duplex = DUPLEX_INVALID;
14024 tp->link_config.phy_is_low_power = 0;
14025 tp->link_config.orig_speed = SPEED_INVALID;
14026 tp->link_config.orig_duplex = DUPLEX_INVALID;
14027 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14028}
14029
14030static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14031{
666bc831
MC		 14032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14034 tp->bufmgr_config.mbuf_read_dma_low_water =
14035 DEFAULT_MB_RDMA_LOW_WATER_5705;
14036 tp->bufmgr_config.mbuf_mac_rx_low_water =
14037 DEFAULT_MB_MACRX_LOW_WATER_57765;
14038 tp->bufmgr_config.mbuf_high_water =
14039 DEFAULT_MB_HIGH_WATER_57765;
14040
14041 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14042 DEFAULT_MB_RDMA_LOW_WATER_5705;
14043 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14044 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14045 tp->bufmgr_config.mbuf_high_water_jumbo =
14046 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14047 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14048 tp->bufmgr_config.mbuf_read_dma_low_water =
14049 DEFAULT_MB_RDMA_LOW_WATER_5705;
14050 tp->bufmgr_config.mbuf_mac_rx_low_water =
14051 DEFAULT_MB_MACRX_LOW_WATER_5705;
14052 tp->bufmgr_config.mbuf_high_water =
14053 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14055 tp->bufmgr_config.mbuf_mac_rx_low_water =
14056 DEFAULT_MB_MACRX_LOW_WATER_5906;
14057 tp->bufmgr_config.mbuf_high_water =
14058 DEFAULT_MB_HIGH_WATER_5906;
14059 }
fdfec172
MC		 14060
14061 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14062 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14063 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14064 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14065 tp->bufmgr_config.mbuf_high_water_jumbo =
14066 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14067 } else {
14068 tp->bufmgr_config.mbuf_read_dma_low_water =
14069 DEFAULT_MB_RDMA_LOW_WATER;
14070 tp->bufmgr_config.mbuf_mac_rx_low_water =
14071 DEFAULT_MB_MACRX_LOW_WATER;
14072 tp->bufmgr_config.mbuf_high_water =
14073 DEFAULT_MB_HIGH_WATER;
14074
14075 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14076 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14077 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14078 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14079 tp->bufmgr_config.mbuf_high_water_jumbo =
14080 DEFAULT_MB_HIGH_WATER_JUMBO;
14081 }
1da177e4
LT		 14082
14083 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14084 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14085}
14086
14087static char * __devinit tg3_phy_string(struct tg3 *tp)
14088{
79eb6904
MC		 14089 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14090 case TG3_PHY_ID_BCM5400: return "5400";
14091 case TG3_PHY_ID_BCM5401: return "5401";
14092 case TG3_PHY_ID_BCM5411: return "5411";
14093 case TG3_PHY_ID_BCM5701: return "5701";
14094 case TG3_PHY_ID_BCM5703: return "5703";
14095 case TG3_PHY_ID_BCM5704: return "5704";
14096 case TG3_PHY_ID_BCM5705: return "5705";
14097 case TG3_PHY_ID_BCM5750: return "5750";
14098 case TG3_PHY_ID_BCM5752: return "5752";
14099 case TG3_PHY_ID_BCM5714: return "5714";
14100 case TG3_PHY_ID_BCM5780: return "5780";
14101 case TG3_PHY_ID_BCM5755: return "5755";
14102 case TG3_PHY_ID_BCM5787: return "5787";
14103 case TG3_PHY_ID_BCM5784: return "5784";
14104 case TG3_PHY_ID_BCM5756: return "5722/5756";
14105 case TG3_PHY_ID_BCM5906: return "5906";
14106 case TG3_PHY_ID_BCM5761: return "5761";
14107 case TG3_PHY_ID_BCM5718C: return "5718C";
14108 case TG3_PHY_ID_BCM5718S: return "5718S";
14109 case TG3_PHY_ID_BCM57765: return "57765";
14110 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 14111 case 0: return "serdes";
14112 default: return "unknown";
855e1111 14113 }
1da177e4
LT		 14114}
14115
f9804ddb
MC		 14116static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14117{
14118 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14119 strcpy(str, "PCI Express");
14120 return str;
14121 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14122 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14123
14124 strcpy(str, "PCIX:");
14125
14126 if ((clock_ctrl == 7) ||
14127 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14128 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14129 strcat(str, "133MHz");
14130 else if (clock_ctrl == 0)
14131 strcat(str, "33MHz");
14132 else if (clock_ctrl == 2)
14133 strcat(str, "50MHz");
14134 else if (clock_ctrl == 4)
14135 strcat(str, "66MHz");
14136 else if (clock_ctrl == 6)
14137 strcat(str, "100MHz");
f9804ddb
MC		 14138 } else {
14139 strcpy(str, "PCI:");
14140 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14141 strcat(str, "66MHz");
14142 else
14143 strcat(str, "33MHz");
14144 }
14145 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14146 strcat(str, ":32-bit");
14147 else
14148 strcat(str, ":64-bit");
14149 return str;
14150}
14151
8c2dc7e1 14152static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14153{
14154 struct pci_dev *peer;
14155 unsigned int func, devnr = tp->pdev->devfn & ~7;
14156
14157 for (func = 0; func < 8; func++) {
14158 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14159 if (peer && peer != tp->pdev)
14160 break;
14161 pci_dev_put(peer);
14162 }
16fe9d74
MC		 14163 /* 5704 can be configured in single-port mode, set peer to
14164 * tp->pdev in that case.
14165 */
14166 if (!peer) {
14167 peer = tp->pdev;
14168 return peer;
14169 }
1da177e4
LT		 14170
14171 /*
14172 * We don't need to keep the refcount elevated; there's no way
14173 * to remove one half of this device without removing the other
14174 */
14175 pci_dev_put(peer);
14176
14177 return peer;
14178}
14179
15f9850d
DM		 14180static void __devinit tg3_init_coal(struct tg3 *tp)
14181{
14182 struct ethtool_coalesce *ec = &tp->coal;
14183
14184 memset(ec, 0, sizeof(*ec));
14185 ec->cmd = ETHTOOL_GCOALESCE;
14186 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14187 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14188 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14189 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14190 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14191 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14192 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14193 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14194 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14195
14196 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14197 HOSTCC_MODE_CLRTICK_TXBD)) {
14198 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14199 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14200 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14201 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14202 }
d244c892
MC		 14203
14204 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14205 ec->rx_coalesce_usecs_irq = 0;
14206 ec->tx_coalesce_usecs_irq = 0;
14207 ec->stats_block_coalesce_usecs = 0;
14208 }
15f9850d
DM		 14209}
14210
7c7d64b8
SH		 14211static const struct net_device_ops tg3_netdev_ops = {
14212 .ndo_open = tg3_open,
14213 .ndo_stop = tg3_close,
00829823
SH		 14214 .ndo_start_xmit = tg3_start_xmit,
14215 .ndo_get_stats = tg3_get_stats,
14216 .ndo_validate_addr = eth_validate_addr,
14217 .ndo_set_multicast_list = tg3_set_rx_mode,
14218 .ndo_set_mac_address = tg3_set_mac_addr,
14219 .ndo_do_ioctl = tg3_ioctl,
14220 .ndo_tx_timeout = tg3_tx_timeout,
14221 .ndo_change_mtu = tg3_change_mtu,
14222#if TG3_VLAN_TAG_USED
14223 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14224#endif
14225#ifdef CONFIG_NET_POLL_CONTROLLER
14226 .ndo_poll_controller = tg3_poll_controller,
14227#endif
14228};
14229
14230static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14231 .ndo_open = tg3_open,
14232 .ndo_stop = tg3_close,
14233 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14234 .ndo_get_stats = tg3_get_stats,
14235 .ndo_validate_addr = eth_validate_addr,
14236 .ndo_set_multicast_list = tg3_set_rx_mode,
14237 .ndo_set_mac_address = tg3_set_mac_addr,
14238 .ndo_do_ioctl = tg3_ioctl,
14239 .ndo_tx_timeout = tg3_tx_timeout,
14240 .ndo_change_mtu = tg3_change_mtu,
14241#if TG3_VLAN_TAG_USED
14242 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14243#endif
14244#ifdef CONFIG_NET_POLL_CONTROLLER
14245 .ndo_poll_controller = tg3_poll_controller,
14246#endif
14247};
14248
1da177e4
LT		 14249static int __devinit tg3_init_one(struct pci_dev *pdev,
14250 const struct pci_device_id *ent)
14251{
1da177e4
LT		 14252 struct net_device *dev;
14253 struct tg3 *tp;
646c9edd
MC		 14254 int i, err, pm_cap;
14255 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14256 char str[40];
72f2afb8 14257 u64 dma_mask, persist_dma_mask;
1da177e4 14258
05dbe005 14259 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 14260
14261 err = pci_enable_device(pdev);
14262 if (err) {
2445e461 14263 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 14264 return err;
14265 }
14266
1da177e4
LT		 14267 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14268 if (err) {
2445e461 14269 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 14270 goto err_out_disable_pdev;
14271 }
14272
14273 pci_set_master(pdev);
14274
14275 /* Find power-management capability. */
14276 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14277 if (pm_cap == 0) {
2445e461
MC		 14278 dev_err(&pdev->dev,
14279 "Cannot find Power Management capability, aborting\n");
1da177e4
LT		 14280 err = -EIO;
14281 goto err_out_free_res;
14282 }
14283
fe5f5787 14284 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 14285 if (!dev) {
2445e461 14286 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4
LT		 14287 err = -ENOMEM;
14288 goto err_out_free_res;
14289 }
14290
1da177e4
LT		 14291 SET_NETDEV_DEV(dev, &pdev->dev);
14292
1da177e4
LT		 14293#if TG3_VLAN_TAG_USED
14294 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14295#endif
14296
14297 tp = netdev_priv(dev);
14298 tp->pdev = pdev;
14299 tp->dev = dev;
14300 tp->pm_cap = pm_cap;
1da177e4
LT		 14301 tp->rx_mode = TG3_DEF_RX_MODE;
14302 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14303
1da177e4
LT		 14304 if (tg3_debug > 0)
14305 tp->msg_enable = tg3_debug;
14306 else
14307 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14308
14309 /* The word/byte swap controls here control register access byte
14310 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14311 * setting below.
14312 */
14313 tp->misc_host_ctrl =
14314 MISC_HOST_CTRL_MASK_PCI_INT |
14315 MISC_HOST_CTRL_WORD_SWAP |
14316 MISC_HOST_CTRL_INDIR_ACCESS |
14317 MISC_HOST_CTRL_PCISTATE_RW;
14318
14319 /* The NONFRM (non-frame) byte/word swap controls take effect
14320 * on descriptor entries, anything which isn't packet data.
14321 *
14322 * The StrongARM chips on the board (one for tx, one for rx)
14323 * are running in big-endian mode.
14324 */
14325 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14326 GRC_MODE_WSWAP_NONFRM_DATA);
14327#ifdef __BIG_ENDIAN
14328 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14329#endif
14330 spin_lock_init(&tp->lock);
1da177e4 14331 spin_lock_init(&tp->indirect_lock);
c4028958 14332 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14333
d5fe488a 14334 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14335 if (!tp->regs) {
ab96b241 14336 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 14337 err = -ENOMEM;
14338 goto err_out_free_dev;
14339 }
14340
14341 tg3_init_link_config(tp);
14342
1da177e4
LT		 14343 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14344 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14345
1da177e4 14346 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14347 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14348 dev->irq = pdev->irq;
1da177e4
LT		 14349
14350 err = tg3_get_invariants(tp);
14351 if (err) {
ab96b241
MC		 14352 dev_err(&pdev->dev,
14353 "Problem fetching invariants of chip, aborting\n");
1da177e4
LT		 14354 goto err_out_iounmap;
14355 }
14356
615774fe
MC		 14357 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14358 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14359 dev->netdev_ops = &tg3_netdev_ops;
14360 else
14361 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14362
14363
4a29cc2e
MC		 14364 /* The EPB bridge inside 5714, 5715, and 5780 and any
14365 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14366 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14367 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14368 * do DMA address check in tg3_start_xmit().
14369 */
4a29cc2e 14370 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14371 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14372 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14373 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14374#ifdef CONFIG_HIGHMEM
6a35528a 14375 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14376#endif
4a29cc2e 14377 } else
6a35528a 14378 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14379
14380 /* Configure DMA attributes. */
284901a9 14381 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14382 err = pci_set_dma_mask(pdev, dma_mask);
14383 if (!err) {
14384 dev->features |= NETIF_F_HIGHDMA;
14385 err = pci_set_consistent_dma_mask(pdev,
14386 persist_dma_mask);
14387 if (err < 0) {
ab96b241
MC		 14388 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14389 "DMA for consistent allocations\n");
72f2afb8
MC		 14390 goto err_out_iounmap;
14391 }
14392 }
14393 }
284901a9
YH		 14394 if (err || dma_mask == DMA_BIT_MASK(32)) {
14395 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 14396 if (err) {
ab96b241
MC		 14397 dev_err(&pdev->dev,
14398 "No usable DMA configuration, aborting\n");
72f2afb8
MC		 14399 goto err_out_iounmap;
14400 }
14401 }
14402
fdfec172 14403 tg3_init_bufmgr_config(tp);
1da177e4 14404
507399f1
MC		 14405 /* Selectively allow TSO based on operating conditions */
14406 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14407 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14408 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14409 else {
14410 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14411 tp->fw_needed = NULL;
1da177e4 14412 }
507399f1
MC		 14413
14414 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14415 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14416
4e3a7aaa
MC		 14417 /* TSO is on by default on chips that support hardware TSO.
14418 * Firmware TSO on older chips gives lower performance, so it
14419 * is off by default, but can be enabled using ethtool.
14420 */
e849cdc3
MC		 14421 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14422 (dev->features & NETIF_F_IP_CSUM))
14423 dev->features |= NETIF_F_TSO;
14424
14425 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14426 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14427 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14428 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14429 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14431 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14432 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14434 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14435 dev->features |= NETIF_F_TSO_ECN;
b0026624 14436 }
1da177e4 14437
1da177e4
LT		 14438 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14439 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14440 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14441 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14442 tp->rx_pending = 63;
14443 }
14444
1da177e4
LT		 14445 err = tg3_get_device_address(tp);
14446 if (err) {
ab96b241
MC		 14447 dev_err(&pdev->dev,
14448 "Could not obtain valid ethernet address, aborting\n");
026a6c21 14449 goto err_out_iounmap;
1da177e4
LT		 14450 }
14451
c88864df 14452 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14453 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14454 if (!tp->aperegs) {
ab96b241
MC		 14455 dev_err(&pdev->dev,
14456 "Cannot map APE registers, aborting\n");
c88864df 14457 err = -ENOMEM;
026a6c21 14458 goto err_out_iounmap;
c88864df
MC		 14459 }
14460
14461 tg3_ape_lock_init(tp);
7fd76445
MC		 14462
14463 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14464 tg3_read_dash_ver(tp);
c88864df
MC		 14465 }
14466
1da177e4
LT		 14467 /*
14468 * Reset chip in case UNDI or EFI driver did not shutdown
14469 * DMA self test will enable WDMAC and we'll see (spurious)
14470 * pending DMA on the PCI bus at that point.
14471 */
14472 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14473 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14474 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14475 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14476 }
14477
14478 err = tg3_test_dma(tp);
14479 if (err) {
ab96b241 14480 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 14481 goto err_out_apeunmap;
1da177e4
LT		 14482 }
14483
1da177e4
LT		 14484 /* flow control autonegotiation is default behavior */
14485 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14486 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14487
78f90dcf
MC		 14488 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14489 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14490 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14491 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14492 struct tg3_napi *tnapi = &tp->napi[i];
14493
14494 tnapi->tp = tp;
14495 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14496
14497 tnapi->int_mbox = intmbx;
14498 if (i < 4)
14499 intmbx += 0x8;
14500 else
14501 intmbx += 0x4;
14502
14503 tnapi->consmbox = rcvmbx;
14504 tnapi->prodmbox = sndmbx;
14505
14506 if (i) {
14507 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14508 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14509 } else {
14510 tnapi->coal_now = HOSTCC_MODE_NOW;
14511 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14512 }
14513
14514 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14515 break;
14516
14517 /*
14518 * If we support MSIX, we'll be using RSS. If we're using
14519 * RSS, the first vector only handles link interrupts and the
14520 * remaining vectors handle rx and tx interrupts. Reuse the
14521 * mailbox values for the next iteration. The values we setup
14522 * above are still useful for the single vectored mode.
14523 */
14524 if (!i)
14525 continue;
14526
14527 rcvmbx += 0x8;
14528
14529 if (sndmbx & 0x4)
14530 sndmbx -= 0x4;
14531 else
14532 sndmbx += 0xc;
14533 }
14534
15f9850d
DM		 14535 tg3_init_coal(tp);
14536
c49a1561
MC		 14537 pci_set_drvdata(pdev, dev);
14538
1da177e4
LT		 14539 err = register_netdev(dev);
14540 if (err) {
ab96b241 14541 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 14542 goto err_out_apeunmap;
1da177e4
LT		 14543 }
14544
05dbe005
JP		 14545 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14546 tp->board_part_number,
14547 tp->pci_chip_rev_id,
14548 tg3_bus_string(tp, str),
14549 dev->dev_addr);
1da177e4 14550
3f0e3ad7
MC		 14551 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14552 struct phy_device *phydev;
14553 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 14554 netdev_info(dev,
14555 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 14556 phydev->drv->name, dev_name(&phydev->dev));
3f0e3ad7 14557 } else
5129c3a3
MC		 14558 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14559 "(WireSpeed[%d])\n", tg3_phy_string(tp),
05dbe005
JP		 14560 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14561 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14562 "10/100/1000Base-T")),
14563 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14564
14565 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14566 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14567 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14568 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14569 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14570 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14571 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14572 tp->dma_rwctrl,
14573 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14574 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4
LT		 14575
14576 return 0;
14577
0d3031d9
MC		 14578err_out_apeunmap:
14579 if (tp->aperegs) {
14580 iounmap(tp->aperegs);
14581 tp->aperegs = NULL;
14582 }
14583
1da177e4 14584err_out_iounmap:
6892914f
MC		 14585 if (tp->regs) {
14586 iounmap(tp->regs);
22abe310 14587 tp->regs = NULL;
6892914f 14588 }
1da177e4
LT		 14589
14590err_out_free_dev:
14591 free_netdev(dev);
14592
14593err_out_free_res:
14594 pci_release_regions(pdev);
14595
14596err_out_disable_pdev:
14597 pci_disable_device(pdev);
14598 pci_set_drvdata(pdev, NULL);
14599 return err;
14600}
14601
14602static void __devexit tg3_remove_one(struct pci_dev *pdev)
14603{
14604 struct net_device *dev = pci_get_drvdata(pdev);
14605
14606 if (dev) {
14607 struct tg3 *tp = netdev_priv(dev);
14608
077f849d
JSR		 14609 if (tp->fw)
14610 release_firmware(tp->fw);
14611
7faa006f 14612 flush_scheduled_work();
158d7abd 14613
b02fd9e3
MC		 14614 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14615 tg3_phy_fini(tp);
158d7abd 14616 tg3_mdio_fini(tp);
b02fd9e3 14617 }
158d7abd 14618
1da177e4 14619 unregister_netdev(dev);
0d3031d9
MC		 14620 if (tp->aperegs) {
14621 iounmap(tp->aperegs);
14622 tp->aperegs = NULL;
14623 }
6892914f
MC		 14624 if (tp->regs) {
14625 iounmap(tp->regs);
22abe310 14626 tp->regs = NULL;
6892914f 14627 }
1da177e4
LT		 14628 free_netdev(dev);
14629 pci_release_regions(pdev);
14630 pci_disable_device(pdev);
14631 pci_set_drvdata(pdev, NULL);
14632 }
14633}
14634
14635static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14636{
14637 struct net_device *dev = pci_get_drvdata(pdev);
14638 struct tg3 *tp = netdev_priv(dev);
12dac075 14639 pci_power_t target_state;
1da177e4
LT		 14640 int err;
14641
3e0c95fd
MC		 14642 /* PCI register 4 needs to be saved whether netif_running() or not.
14643 * MSI address and data need to be saved if using MSI and
14644 * netif_running().
14645 */
14646 pci_save_state(pdev);
14647
1da177e4
LT		 14648 if (!netif_running(dev))
14649 return 0;
14650
7faa006f 14651 flush_scheduled_work();
b02fd9e3 14652 tg3_phy_stop(tp);
1da177e4
LT		 14653 tg3_netif_stop(tp);
14654
14655 del_timer_sync(&tp->timer);
14656
f47c11ee 14657 tg3_full_lock(tp, 1);
1da177e4 14658 tg3_disable_ints(tp);
f47c11ee 14659 tg3_full_unlock(tp);
1da177e4
LT		 14660
14661 netif_device_detach(dev);
14662
f47c11ee 14663 tg3_full_lock(tp, 0);
944d980e 14664 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14665 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14666 tg3_full_unlock(tp);
1da177e4 14667
12dac075
RW		 14668 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14669
14670 err = tg3_set_power_state(tp, target_state);
1da177e4 14671 if (err) {
b02fd9e3
MC		 14672 int err2;
14673
f47c11ee 14674 tg3_full_lock(tp, 0);
1da177e4 14675
6a9eba15 14676 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14677 err2 = tg3_restart_hw(tp, 1);
14678 if (err2)
b9ec6c1b 14679 goto out;
1da177e4
LT		 14680
14681 tp->timer.expires = jiffies + tp->timer_offset;
14682 add_timer(&tp->timer);
14683
14684 netif_device_attach(dev);
14685 tg3_netif_start(tp);
14686
b9ec6c1b 14687out:
f47c11ee 14688 tg3_full_unlock(tp);
b02fd9e3
MC		 14689
14690 if (!err2)
14691 tg3_phy_start(tp);
1da177e4
LT		 14692 }
14693
14694 return err;
14695}
14696
14697static int tg3_resume(struct pci_dev *pdev)
14698{
14699 struct net_device *dev = pci_get_drvdata(pdev);
14700 struct tg3 *tp = netdev_priv(dev);
14701 int err;
14702
3e0c95fd
MC		 14703 pci_restore_state(tp->pdev);
14704
1da177e4
LT		 14705 if (!netif_running(dev))
14706 return 0;
14707
bc1c7567 14708 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14709 if (err)
14710 return err;
14711
14712 netif_device_attach(dev);
14713
f47c11ee 14714 tg3_full_lock(tp, 0);
1da177e4 14715
6a9eba15 14716 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14717 err = tg3_restart_hw(tp, 1);
14718 if (err)
14719 goto out;
1da177e4
LT		 14720
14721 tp->timer.expires = jiffies + tp->timer_offset;
14722 add_timer(&tp->timer);
14723
1da177e4
LT		 14724 tg3_netif_start(tp);
14725
b9ec6c1b 14726out:
f47c11ee 14727 tg3_full_unlock(tp);
1da177e4 14728
b02fd9e3
MC		 14729 if (!err)
14730 tg3_phy_start(tp);
14731
b9ec6c1b 14732 return err;
1da177e4
LT		 14733}
14734
14735static struct pci_driver tg3_driver = {
14736 .name = DRV_MODULE_NAME,
14737 .id_table = tg3_pci_tbl,
14738 .probe = tg3_init_one,
14739 .remove = __devexit_p(tg3_remove_one),
14740 .suspend = tg3_suspend,
14741 .resume = tg3_resume
14742};
14743
14744static int __init tg3_init(void)
14745{
29917620 14746 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14747}
14748
14749static void __exit tg3_cleanup(void)
14750{
14751 pci_unregister_driver(&tg3_driver);
14752}
14753
14754module_init(tg3_init);
14755module_exit(tg3_cleanup);
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