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tg3: rename rx_[std|jmb]_ptr
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
123b43e9
MC		 71#define DRV_MODULE_VERSION "3.103"
72#define DRV_MODULE_RELDATE "November 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
c73430d0 943 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
a9daf367 956 return;
fcb389df
MC		 957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
a9daf367 980
bb85fbb6
MC		 981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
bb85fbb6
MC		 990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
a9daf367 993
a9daf367
MC		 994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
fcb389df 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014}
1015
158d7abd
MC		 1016static void tg3_mdio_start(struct tg3 *tp)
1017{
158d7abd
MC		 1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
a9daf367 1021
882e9793
MC		 1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
3f0e3ad7 1035 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1036
9c61d6bc
MC		 1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
158d7abd
MC		 1040}
1041
158d7abd
MC		 1042static int tg3_mdio_init(struct tg3 *tp)
1043{
1044 int i;
1045 u32 reg;
a9daf367 1046 struct phy_device *phydev;
158d7abd
MC		 1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
298cf9be
LB		 1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
158d7abd 1057
298cf9be
LB		 1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1070 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
298cf9be 1080 i = mdiobus_register(tp->mdio_bus);
a9daf367 1081 if (i) {
158d7abd
MC		 1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
9c61d6bc 1084 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1085 return i;
1086 }
158d7abd 1087
3f0e3ad7 1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1089
9c61d6bc
MC		 1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1100 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1101 break;
a9daf367 1102 case TG3_PHY_ID_BCM50610:
c73430d0 1103 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1104 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1105 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1106 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1107 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1108 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1114 /* fallthru */
1115 case TG3_PHY_ID_RTL8211C:
1116 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1117 break;
fcb389df 1118 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1119 case TG3_PHY_ID_BCMAC131:
1120 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1121 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1122 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1123 break;
1124 }
1125
9c61d6bc
MC		 1126 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129 tg3_mdio_config_5785(tp);
a9daf367
MC		 1130
1131 return 0;
158d7abd
MC		 1132}
1133
1134static void tg3_mdio_fini(struct tg3 *tp)
1135{
1136 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1138 mdiobus_unregister(tp->mdio_bus);
1139 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1140 }
1141}
1142
4ba526ce
MC		 1143/* tp->lock is held. */
1144static inline void tg3_generate_fw_event(struct tg3 *tp)
1145{
1146 u32 val;
1147
1148 val = tr32(GRC_RX_CPU_EVENT);
1149 val |= GRC_RX_CPU_DRIVER_EVENT;
1150 tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152 tp->last_event_jiffies = jiffies;
1153}
1154
1155#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
95e2869a
MC		 1157/* tp->lock is held. */
1158static void tg3_wait_for_event_ack(struct tg3 *tp)
1159{
1160 int i;
4ba526ce
MC		 1161 unsigned int delay_cnt;
1162 long time_remain;
1163
1164 /* If enough time has passed, no wait is necessary. */
1165 time_remain = (long)(tp->last_event_jiffies + 1 +
1166 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167 (long)jiffies;
1168 if (time_remain < 0)
1169 return;
1170
1171 /* Check if we can shorten the wait time. */
1172 delay_cnt = jiffies_to_usecs(time_remain);
1173 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1176
4ba526ce 1177 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1178 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179 break;
4ba526ce 1180 udelay(8);
95e2869a
MC		 1181 }
1182}
1183
1184/* tp->lock is held. */
1185static void tg3_ump_link_report(struct tg3 *tp)
1186{
1187 u32 reg;
1188 u32 val;
1189
1190 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1192 return;
1193
1194 tg3_wait_for_event_ack(tp);
1195
1196 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200 val = 0;
1201 if (!tg3_readphy(tp, MII_BMCR, &reg))
1202 val = reg << 16;
1203 if (!tg3_readphy(tp, MII_BMSR, &reg))
1204 val |= (reg & 0xffff);
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207 val = 0;
1208 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_LPA, &reg))
1211 val |= (reg & 0xffff);
1212 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214 val = 0;
1215 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217 val = reg << 16;
1218 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219 val |= (reg & 0xffff);
1220 }
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224 val = reg << 16;
1225 else
1226 val = 0;
1227 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
4ba526ce 1229 tg3_generate_fw_event(tp);
95e2869a
MC		 1230}
1231
1232static void tg3_link_report(struct tg3 *tp)
1233{
1234 if (!netif_carrier_ok(tp->dev)) {
1235 if (netif_msg_link(tp))
1236 printk(KERN_INFO PFX "%s: Link is down.\n",
1237 tp->dev->name);
1238 tg3_ump_link_report(tp);
1239 } else if (netif_msg_link(tp)) {
1240 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241 tp->dev->name,
1242 (tp->link_config.active_speed == SPEED_1000 ?
1243 1000 :
1244 (tp->link_config.active_speed == SPEED_100 ?
1245 100 : 10)),
1246 (tp->link_config.active_duplex == DUPLEX_FULL ?
1247 "full" : "half"));
1248
1249 printk(KERN_INFO PFX
1250 "%s: Flow control is %s for TX and %s for RX.\n",
1251 tp->dev->name,
e18ce346 1252 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1253 "on" : "off",
e18ce346 1254 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1255 "on" : "off");
1256 tg3_ump_link_report(tp);
1257 }
1258}
1259
1260static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261{
1262 u16 miireg;
1263
e18ce346 1264 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1265 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1266 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1267 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1268 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1269 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270 else
1271 miireg = 0;
1272
1273 return miireg;
1274}
1275
1276static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277{
1278 u16 miireg;
1279
e18ce346 1280 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1281 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1282 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1283 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1284 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1285 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286 else
1287 miireg = 0;
1288
1289 return miireg;
1290}
1291
95e2869a
MC		 1292static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293{
1294 u8 cap = 0;
1295
1296 if (lcladv & ADVERTISE_1000XPAUSE) {
1297 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1299 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1300 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1301 cap = FLOW_CTRL_RX;
95e2869a
MC		 1302 } else {
1303 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1304 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1305 }
1306 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1308 cap = FLOW_CTRL_TX;
95e2869a
MC		 1309 }
1310
1311 return cap;
1312}
1313
f51f3562 1314static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1315{
b02fd9e3 1316 u8 autoneg;
f51f3562 1317 u8 flowctrl = 0;
95e2869a
MC		 1318 u32 old_rx_mode = tp->rx_mode;
1319 u32 old_tx_mode = tp->tx_mode;
1320
b02fd9e3 1321 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1322 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1323 else
1324 autoneg = tp->link_config.autoneg;
1325
1326 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1327 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1329 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1330 else
bc02ff95 1331 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1332 } else
1333 flowctrl = tp->link_config.flowctrl;
95e2869a 1334
f51f3562 1335 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1336
e18ce346 1337 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1338 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
f51f3562 1342 if (old_rx_mode != tp->rx_mode)
95e2869a 1343 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1344
e18ce346 1345 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1346 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347 else
1348 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
f51f3562 1350 if (old_tx_mode != tp->tx_mode)
95e2869a 1351 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1352}
1353
b02fd9e3
MC		 1354static void tg3_adjust_link(struct net_device *dev)
1355{
1356 u8 oldflowctrl, linkmesg = 0;
1357 u32 mac_mode, lcl_adv, rmt_adv;
1358 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1359 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1360
24bb4fb6 1361 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1362
1363 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364 MAC_MODE_HALF_DUPLEX);
1365
1366 oldflowctrl = tp->link_config.active_flowctrl;
1367
1368 if (phydev->link) {
1369 lcl_adv = 0;
1370 rmt_adv = 0;
1371
1372 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1374 else if (phydev->speed == SPEED_1000 ||
1375 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1376 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1377 else
1378 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1379
1380 if (phydev->duplex == DUPLEX_HALF)
1381 mac_mode |= MAC_MODE_HALF_DUPLEX;
1382 else {
1383 lcl_adv = tg3_advert_flowctrl_1000T(
1384 tp->link_config.flowctrl);
1385
1386 if (phydev->pause)
1387 rmt_adv = LPA_PAUSE_CAP;
1388 if (phydev->asym_pause)
1389 rmt_adv |= LPA_PAUSE_ASYM;
1390 }
1391
1392 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393 } else
1394 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396 if (mac_mode != tp->mac_mode) {
1397 tp->mac_mode = mac_mode;
1398 tw32_f(MAC_MODE, tp->mac_mode);
1399 udelay(40);
1400 }
1401
fcb389df
MC		 1402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403 if (phydev->speed == SPEED_10)
1404 tw32(MAC_MI_STAT,
1405 MAC_MI_STAT_10MBPS_MODE |
1406 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407 else
1408 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409 }
1410
b02fd9e3
MC		 1411 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412 tw32(MAC_TX_LENGTHS,
1413 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414 (6 << TX_LENGTHS_IPG_SHIFT) |
1415 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416 else
1417 tw32(MAC_TX_LENGTHS,
1418 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419 (6 << TX_LENGTHS_IPG_SHIFT) |
1420 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424 phydev->speed != tp->link_config.active_speed ||
1425 phydev->duplex != tp->link_config.active_duplex ||
1426 oldflowctrl != tp->link_config.active_flowctrl)
1427 linkmesg = 1;
1428
1429 tp->link_config.active_speed = phydev->speed;
1430 tp->link_config.active_duplex = phydev->duplex;
1431
24bb4fb6 1432 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1433
1434 if (linkmesg)
1435 tg3_link_report(tp);
1436}
1437
1438static int tg3_phy_init(struct tg3 *tp)
1439{
1440 struct phy_device *phydev;
1441
1442 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443 return 0;
1444
1445 /* Bring the PHY back to a known state. */
1446 tg3_bmcr_reset(tp);
1447
3f0e3ad7 1448 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1449
1450 /* Attach the MAC to the PHY. */
fb28ad35 1451 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1452 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1453 if (IS_ERR(phydev)) {
1454 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455 return PTR_ERR(phydev);
1456 }
1457
b02fd9e3 1458 /* Mask with MAC supported features. */
9c61d6bc
MC		 1459 switch (phydev->interface) {
1460 case PHY_INTERFACE_MODE_GMII:
1461 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1462 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463 phydev->supported &= (PHY_GBIT_FEATURES |
1464 SUPPORTED_Pause |
1465 SUPPORTED_Asym_Pause);
1466 break;
1467 }
1468 /* fallthru */
9c61d6bc
MC		 1469 case PHY_INTERFACE_MODE_MII:
1470 phydev->supported &= (PHY_BASIC_FEATURES |
1471 SUPPORTED_Pause |
1472 SUPPORTED_Asym_Pause);
1473 break;
1474 default:
3f0e3ad7 1475 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1476 return -EINVAL;
1477 }
1478
1479 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1480
1481 phydev->advertising = phydev->supported;
1482
b02fd9e3
MC		 1483 return 0;
1484}
1485
1486static void tg3_phy_start(struct tg3 *tp)
1487{
1488 struct phy_device *phydev;
1489
1490 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491 return;
1492
3f0e3ad7 1493 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1494
1495 if (tp->link_config.phy_is_low_power) {
1496 tp->link_config.phy_is_low_power = 0;
1497 phydev->speed = tp->link_config.orig_speed;
1498 phydev->duplex = tp->link_config.orig_duplex;
1499 phydev->autoneg = tp->link_config.orig_autoneg;
1500 phydev->advertising = tp->link_config.orig_advertising;
1501 }
1502
1503 phy_start(phydev);
1504
1505 phy_start_aneg(phydev);
1506}
1507
1508static void tg3_phy_stop(struct tg3 *tp)
1509{
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511 return;
1512
3f0e3ad7 1513 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1514}
1515
1516static void tg3_phy_fini(struct tg3 *tp)
1517{
1518 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1519 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1520 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521 }
1522}
1523
b2a5c19c
MC		 1524static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525{
1526 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528}
1529
7f97a4bd
MC		 1530static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531{
1532 u32 phytest;
1533
1534 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535 u32 phy;
1536
1537 tg3_writephy(tp, MII_TG3_FET_TEST,
1538 phytest | MII_TG3_FET_SHADOW_EN);
1539 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540 if (enable)
1541 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542 else
1543 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545 }
1546 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547 }
1548}
1549
6833c043
MC		 1550static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551{
1552 u32 reg;
1553
7f97a4bd 1554 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1555 return;
1556
7f97a4bd
MC		 1557 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558 tg3_phy_fet_toggle_apd(tp, enable);
1559 return;
1560 }
1561
6833c043
MC		 1562 reg = MII_TG3_MISC_SHDW_WREN |
1563 MII_TG3_MISC_SHDW_SCR5_SEL |
1564 MII_TG3_MISC_SHDW_SCR5_LPED |
1565 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566 MII_TG3_MISC_SHDW_SCR5_SDTL |
1567 MII_TG3_MISC_SHDW_SCR5_C125OE;
1568 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574 reg = MII_TG3_MISC_SHDW_WREN |
1575 MII_TG3_MISC_SHDW_APD_SEL |
1576 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577 if (enable)
1578 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581}
1582
9ef8ca99
MC		 1583static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584{
1585 u32 phy;
1586
1587 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589 return;
1590
7f97a4bd 1591 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1592 u32 ephy;
1593
535ef6e1
MC		 1594 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597 tg3_writephy(tp, MII_TG3_FET_TEST,
1598 ephy | MII_TG3_FET_SHADOW_EN);
1599 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1600 if (enable)
535ef6e1 1601 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1602 else
535ef6e1
MC		 1603 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604 tg3_writephy(tp, reg, phy);
9ef8ca99 1605 }
535ef6e1 1606 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1607 }
1608 } else {
1609 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610 MII_TG3_AUXCTL_SHDWSEL_MISC;
1611 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613 if (enable)
1614 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615 else
1616 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617 phy |= MII_TG3_AUXCTL_MISC_WREN;
1618 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619 }
1620 }
1621}
1622
1da177e4
LT		 1623static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624{
1625 u32 val;
1626
1627 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628 return;
1629
1630 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633 (val | (1 << 15) | (1 << 4)));
1634}
1635
b2a5c19c
MC		 1636static void tg3_phy_apply_otp(struct tg3 *tp)
1637{
1638 u32 otp, phy;
1639
1640 if (!tp->phy_otp)
1641 return;
1642
1643 otp = tp->phy_otp;
1644
1645 /* Enable SM_DSP clock and tx 6dB coding. */
1646 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648 MII_TG3_AUXCTL_ACTL_TX_6DB;
1649 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673 /* Turn off SM_DSP clock. */
1674 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675 MII_TG3_AUXCTL_ACTL_TX_6DB;
1676 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677}
1678
1da177e4
LT		 1679static int tg3_wait_macro_done(struct tg3 *tp)
1680{
1681 int limit = 100;
1682
1683 while (limit--) {
1684 u32 tmp32;
1685
1686 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687 if ((tmp32 & 0x1000) == 0)
1688 break;
1689 }
1690 }
d4675b52 1691 if (limit < 0)
1da177e4
LT		 1692 return -EBUSY;
1693
1694 return 0;
1695}
1696
1697static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698{
1699 static const u32 test_pat[4][6] = {
1700 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704 };
1705 int chan;
1706
1707 for (chan = 0; chan < 4; chan++) {
1708 int i;
1709
1710 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711 (chan * 0x2000) | 0x0200);
1712 tg3_writephy(tp, 0x16, 0x0002);
1713
1714 for (i = 0; i < 6; i++)
1715 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716 test_pat[chan][i]);
1717
1718 tg3_writephy(tp, 0x16, 0x0202);
1719 if (tg3_wait_macro_done(tp)) {
1720 *resetp = 1;
1721 return -EBUSY;
1722 }
1723
1724 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725 (chan * 0x2000) | 0x0200);
1726 tg3_writephy(tp, 0x16, 0x0082);
1727 if (tg3_wait_macro_done(tp)) {
1728 *resetp = 1;
1729 return -EBUSY;
1730 }
1731
1732 tg3_writephy(tp, 0x16, 0x0802);
1733 if (tg3_wait_macro_done(tp)) {
1734 *resetp = 1;
1735 return -EBUSY;
1736 }
1737
1738 for (i = 0; i < 6; i += 2) {
1739 u32 low, high;
1740
1741 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743 tg3_wait_macro_done(tp)) {
1744 *resetp = 1;
1745 return -EBUSY;
1746 }
1747 low &= 0x7fff;
1748 high &= 0x000f;
1749 if (low != test_pat[chan][i] ||
1750 high != test_pat[chan][i+1]) {
1751 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755 return -EBUSY;
1756 }
1757 }
1758 }
1759
1760 return 0;
1761}
1762
1763static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764{
1765 int chan;
1766
1767 for (chan = 0; chan < 4; chan++) {
1768 int i;
1769
1770 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771 (chan * 0x2000) | 0x0200);
1772 tg3_writephy(tp, 0x16, 0x0002);
1773 for (i = 0; i < 6; i++)
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775 tg3_writephy(tp, 0x16, 0x0202);
1776 if (tg3_wait_macro_done(tp))
1777 return -EBUSY;
1778 }
1779
1780 return 0;
1781}
1782
1783static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784{
1785 u32 reg32, phy9_orig;
1786 int retries, do_phy_reset, err;
1787
1788 retries = 10;
1789 do_phy_reset = 1;
1790 do {
1791 if (do_phy_reset) {
1792 err = tg3_bmcr_reset(tp);
1793 if (err)
1794 return err;
1795 do_phy_reset = 0;
1796 }
1797
1798 /* Disable transmitter and interrupt. */
1799 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800 continue;
1801
1802 reg32 |= 0x3000;
1803 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805 /* Set full-duplex, 1000 mbps. */
1806 tg3_writephy(tp, MII_BMCR,
1807 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809 /* Set to master mode. */
1810 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811 continue;
1812
1813 tg3_writephy(tp, MII_TG3_CTRL,
1814 (MII_TG3_CTRL_AS_MASTER |
1815 MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817 /* Enable SM_DSP_CLOCK and 6dB. */
1818 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820 /* Block the PHY control access. */
1821 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825 if (!err)
1826 break;
1827 } while (--retries);
1828
1829 err = tg3_phy_reset_chanpat(tp);
1830 if (err)
1831 return err;
1832
1833 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837 tg3_writephy(tp, 0x16, 0x0000);
1838
1839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841 /* Set Extended packet length bit for jumbo frames */
1842 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843 }
1844 else {
1845 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846 }
1847
1848 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851 reg32 &= ~0x3000;
1852 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853 } else if (!err)
1854 err = -EBUSY;
1855
1856 return err;
1857}
1858
1859/* This will reset the tigon3 PHY if there is no valid
1860 * link unless the FORCE argument is non-zero.
1861 */
1862static int tg3_phy_reset(struct tg3 *tp)
1863{
b2a5c19c 1864 u32 cpmuctrl;
1da177e4
LT		 1865 u32 phy_status;
1866 int err;
1867
60189ddf
MC		 1868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869 u32 val;
1870
1871 val = tr32(GRC_MISC_CFG);
1872 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873 udelay(40);
1874 }
1da177e4
LT		 1875 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1876 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877 if (err != 0)
1878 return -EBUSY;
1879
c8e1e82b
MC		 1880 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881 netif_carrier_off(tp->dev);
1882 tg3_link_report(tp);
1883 }
1884
1da177e4
LT		 1885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888 err = tg3_phy_reset_5703_4_5(tp);
1889 if (err)
1890 return err;
1891 goto out;
1892 }
1893
b2a5c19c
MC		 1894 cpmuctrl = 0;
1895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899 tw32(TG3_CPMU_CTRL,
1900 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901 }
1902
1da177e4
LT		 1903 err = tg3_bmcr_reset(tp);
1904 if (err)
1905 return err;
1906
b2a5c19c
MC		 1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908 u32 phy;
1909
1910 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914 }
1915
bcb37f6c
MC		 1916 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1918 u32 val;
1919
1920 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922 CPMU_LSPD_1000MB_MACCLK_12_5) {
1923 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924 udelay(40);
1925 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926 }
1927 }
1928
b2a5c19c
MC		 1929 tg3_phy_apply_otp(tp);
1930
6833c043
MC		 1931 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932 tg3_phy_toggle_apd(tp, true);
1933 else
1934 tg3_phy_toggle_apd(tp, false);
1935
1da177e4
LT		 1936out:
1937 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944 }
1945 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946 tg3_writephy(tp, 0x1c, 0x8d68);
1947 tg3_writephy(tp, 0x1c, 0x8d68);
1948 }
1949 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
c424cb24
MC		 1959 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1962 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964 tg3_writephy(tp, MII_TG3_TEST1,
1965 MII_TG3_TEST1_TRIM_EN | 0x4);
1966 } else
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969 }
1da177e4
LT		 1970 /* Set Extended packet length bit (bit 14) on all chips that */
1971 /* support jumbo frames */
1972 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973 /* Cannot do read-modify-write on 5401 */
1974 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1975 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1976 u32 phy_reg;
1977
1978 /* Set bit 14 with read-modify-write to preserve other bits */
1979 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982 }
1983
1984 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985 * jumbo frames transmission.
1986 */
8f666b07 1987 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1988 u32 phy_reg;
1989
1990 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993 }
1994
715116a1 1995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1996 /* adjust output voltage */
535ef6e1 1997 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1998 }
1999
9ef8ca99 2000 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2001 tg3_phy_set_wirespeed(tp);
2002 return 0;
2003}
2004
2005static void tg3_frob_aux_power(struct tg3 *tp)
2006{
2007 struct tg3 *tp_peer = tp;
2008
9d26e213 2009 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2010 return;
2011
f6eb9b1f
MC		 2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2015 struct net_device *dev_peer;
2016
2017 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2018 /* remove_one() may have been run on the peer. */
8c2dc7e1 2019 if (!dev_peer)
bc1c7567
MC		 2020 tp_peer = tp;
2021 else
2022 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2023 }
2024
1da177e4 2025 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2026 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2031 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032 (GRC_LCLCTRL_GPIO_OE0 |
2033 GRC_LCLCTRL_GPIO_OE1 |
2034 GRC_LCLCTRL_GPIO_OE2 |
2035 GRC_LCLCTRL_GPIO_OUTPUT0 |
2036 GRC_LCLCTRL_GPIO_OUTPUT1),
2037 100);
8d519ab2
MC		 2038 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2040 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1 |
2046 tp->grc_local_ctrl;
2047 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2054 } else {
2055 u32 no_gpio2;
dc56b7d4 2056 u32 grc_local_ctrl = 0;
1da177e4
LT		 2057
2058 if (tp_peer != tp &&
2059 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060 return;
2061
dc56b7d4
MC		 2062 /* Workaround to prevent overdrawing Amps. */
2063 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064 ASIC_REV_5714) {
2065 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 grc_local_ctrl, 100);
dc56b7d4
MC		 2068 }
2069
1da177e4
LT		 2070 /* On 5753 and variants, GPIO2 cannot be used. */
2071 no_gpio2 = tp->nic_sram_data_cfg &
2072 NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
dc56b7d4 2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2075 GRC_LCLCTRL_GPIO_OE1 |
2076 GRC_LCLCTRL_GPIO_OE2 |
2077 GRC_LCLCTRL_GPIO_OUTPUT1 |
2078 GRC_LCLCTRL_GPIO_OUTPUT2;
2079 if (no_gpio2) {
2080 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081 GRC_LCLCTRL_GPIO_OUTPUT2);
2082 }
b401e9e2
MC		 2083 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084 grc_local_ctrl, 100);
1da177e4
LT		 2085
2086 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
b401e9e2
MC		 2088 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089 grc_local_ctrl, 100);
1da177e4
LT		 2090
2091 if (!no_gpio2) {
2092 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 grc_local_ctrl, 100);
1da177e4
LT		 2095 }
2096 }
2097 } else {
2098 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100 if (tp_peer != tp &&
2101 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102 return;
2103
b401e9e2
MC		 2104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105 (GRC_LCLCTRL_GPIO_OE1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2107
b401e9e2
MC		 2108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2110
b401e9e2
MC		 2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 (GRC_LCLCTRL_GPIO_OE1 |
2113 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2114 }
2115 }
2116}
2117
e8f3f6ca
MC		 2118static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119{
2120 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121 return 1;
2122 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123 if (speed != SPEED_10)
2124 return 1;
2125 } else if (speed == SPEED_10)
2126 return 1;
2127
2128 return 0;
2129}
2130
1da177e4
LT		 2131static int tg3_setup_phy(struct tg3 *, int);
2132
2133#define RESET_KIND_SHUTDOWN 0
2134#define RESET_KIND_INIT 1
2135#define RESET_KIND_SUSPEND 2
2136
2137static void tg3_write_sig_post_reset(struct tg3 *, int);
2138static int tg3_halt_cpu(struct tg3 *, u32);
2139
0a459aac 2140static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2141{
ce057f01
MC		 2142 u32 val;
2143
5129724a
MC		 2144 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149 sg_dig_ctrl |=
2150 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153 }
3f7045c1 2154 return;
5129724a 2155 }
3f7045c1 2156
60189ddf 2157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2158 tg3_bmcr_reset(tp);
2159 val = tr32(GRC_MISC_CFG);
2160 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161 udelay(40);
2162 return;
0e5f784c
MC		 2163 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164 u32 phytest;
2165 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166 u32 phy;
2167
2168 tg3_writephy(tp, MII_ADVERTISE, 0);
2169 tg3_writephy(tp, MII_BMCR,
2170 BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172 tg3_writephy(tp, MII_TG3_FET_TEST,
2173 phytest | MII_TG3_FET_SHADOW_EN);
2174 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176 tg3_writephy(tp,
2177 MII_TG3_FET_SHDW_AUXMODE4,
2178 phy);
2179 }
2180 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181 }
2182 return;
0a459aac 2183 } else if (do_low_power) {
715116a1
MC		 2184 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2186
2187 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2192 }
3f7045c1 2193
15c3b696
MC		 2194 /* The PHY should not be powered down on some chips because
2195 * of bugs.
2196 */
2197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201 return;
ce057f01 2202
bcb37f6c
MC		 2203 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2205 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209 }
2210
15c3b696
MC		 2211 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212}
2213
ffbcfed4
MC		 2214/* tp->lock is held. */
2215static int tg3_nvram_lock(struct tg3 *tp)
2216{
2217 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218 int i;
2219
2220 if (tp->nvram_lock_cnt == 0) {
2221 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222 for (i = 0; i < 8000; i++) {
2223 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224 break;
2225 udelay(20);
2226 }
2227 if (i == 8000) {
2228 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229 return -ENODEV;
2230 }
2231 }
2232 tp->nvram_lock_cnt++;
2233 }
2234 return 0;
2235}
2236
2237/* tp->lock is held. */
2238static void tg3_nvram_unlock(struct tg3 *tp)
2239{
2240 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241 if (tp->nvram_lock_cnt > 0)
2242 tp->nvram_lock_cnt--;
2243 if (tp->nvram_lock_cnt == 0)
2244 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245 }
2246}
2247
2248/* tp->lock is held. */
2249static void tg3_enable_nvram_access(struct tg3 *tp)
2250{
2251 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2252 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2253 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256 }
2257}
2258
2259/* tp->lock is held. */
2260static void tg3_disable_nvram_access(struct tg3 *tp)
2261{
2262 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2263 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2264 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267 }
2268}
2269
2270static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271 u32 offset, u32 *val)
2272{
2273 u32 tmp;
2274 int i;
2275
2276 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277 return -EINVAL;
2278
2279 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280 EEPROM_ADDR_DEVID_MASK |
2281 EEPROM_ADDR_READ);
2282 tw32(GRC_EEPROM_ADDR,
2283 tmp |
2284 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286 EEPROM_ADDR_ADDR_MASK) |
2287 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289 for (i = 0; i < 1000; i++) {
2290 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292 if (tmp & EEPROM_ADDR_COMPLETE)
2293 break;
2294 msleep(1);
2295 }
2296 if (!(tmp & EEPROM_ADDR_COMPLETE))
2297 return -EBUSY;
2298
62cedd11
MC		 2299 tmp = tr32(GRC_EEPROM_DATA);
2300
2301 /*
2302 * The data will always be opposite the native endian
2303 * format. Perform a blind byteswap to compensate.
2304 */
2305 *val = swab32(tmp);
2306
ffbcfed4
MC		 2307 return 0;
2308}
2309
2310#define NVRAM_CMD_TIMEOUT 10000
2311
2312static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313{
2314 int i;
2315
2316 tw32(NVRAM_CMD, nvram_cmd);
2317 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318 udelay(10);
2319 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320 udelay(10);
2321 break;
2322 }
2323 }
2324
2325 if (i == NVRAM_CMD_TIMEOUT)
2326 return -EBUSY;
2327
2328 return 0;
2329}
2330
2331static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332{
2333 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337 (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339 addr = ((addr / tp->nvram_pagesize) <<
2340 ATMEL_AT45DB0X1B_PAGE_POS) +
2341 (addr % tp->nvram_pagesize);
2342
2343 return addr;
2344}
2345
2346static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347{
2348 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352 (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355 tp->nvram_pagesize) +
2356 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358 return addr;
2359}
2360
e4f34110
MC		 2361/* NOTE: Data read in from NVRAM is byteswapped according to
2362 * the byteswapping settings for all other register accesses.
2363 * tg3 devices are BE devices, so on a BE machine, the data
2364 * returned will be exactly as it is seen in NVRAM. On a LE
2365 * machine, the 32-bit value will be byteswapped.
2366 */
ffbcfed4
MC		 2367static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368{
2369 int ret;
2370
2371 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374 offset = tg3_nvram_phys_addr(tp, offset);
2375
2376 if (offset > NVRAM_ADDR_MSK)
2377 return -EINVAL;
2378
2379 ret = tg3_nvram_lock(tp);
2380 if (ret)
2381 return ret;
2382
2383 tg3_enable_nvram_access(tp);
2384
2385 tw32(NVRAM_ADDR, offset);
2386 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389 if (ret == 0)
e4f34110 2390 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2391
2392 tg3_disable_nvram_access(tp);
2393
2394 tg3_nvram_unlock(tp);
2395
2396 return ret;
2397}
2398
a9dc529d
MC		 2399/* Ensures NVRAM data is in bytestream format. */
2400static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2401{
2402 u32 v;
a9dc529d 2403 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2404 if (!res)
a9dc529d 2405 *val = cpu_to_be32(v);
ffbcfed4
MC		 2406 return res;
2407}
2408
3f007891
MC		 2409/* tp->lock is held. */
2410static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411{
2412 u32 addr_high, addr_low;
2413 int i;
2414
2415 addr_high = ((tp->dev->dev_addr[0] << 8) |
2416 tp->dev->dev_addr[1]);
2417 addr_low = ((tp->dev->dev_addr[2] << 24) |
2418 (tp->dev->dev_addr[3] << 16) |
2419 (tp->dev->dev_addr[4] << 8) |
2420 (tp->dev->dev_addr[5] << 0));
2421 for (i = 0; i < 4; i++) {
2422 if (i == 1 && skip_mac_1)
2423 continue;
2424 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426 }
2427
2428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430 for (i = 0; i < 12; i++) {
2431 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433 }
2434 }
2435
2436 addr_high = (tp->dev->dev_addr[0] +
2437 tp->dev->dev_addr[1] +
2438 tp->dev->dev_addr[2] +
2439 tp->dev->dev_addr[3] +
2440 tp->dev->dev_addr[4] +
2441 tp->dev->dev_addr[5]) &
2442 TX_BACKOFF_SEED_MASK;
2443 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444}
2445
bc1c7567 2446static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2447{
2448 u32 misc_host_ctrl;
0a459aac 2449 bool device_should_wake, do_low_power;
1da177e4
LT		 2450
2451 /* Make sure register accesses (indirect or otherwise)
2452 * will function correctly.
2453 */
2454 pci_write_config_dword(tp->pdev,
2455 TG3PCI_MISC_HOST_CTRL,
2456 tp->misc_host_ctrl);
2457
1da177e4 2458 switch (state) {
bc1c7567 2459 case PCI_D0:
12dac075
RW		 2460 pci_enable_wake(tp->pdev, state, false);
2461 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2462
9d26e213
MC		 2463 /* Switch out of Vaux if it is a NIC */
2464 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2465 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2466
2467 return 0;
2468
bc1c7567 2469 case PCI_D1:
bc1c7567 2470 case PCI_D2:
bc1c7567 2471 case PCI_D3hot:
1da177e4
LT		 2472 break;
2473
2474 default:
12dac075
RW		 2475 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476 tp->dev->name, state);
1da177e4 2477 return -EINVAL;
855e1111 2478 }
5e7dfd0f
MC		 2479
2480 /* Restore the CLKREQ setting. */
2481 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482 u16 lnkctl;
2483
2484 pci_read_config_word(tp->pdev,
2485 tp->pcie_cap + PCI_EXP_LNKCTL,
2486 &lnkctl);
2487 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488 pci_write_config_word(tp->pdev,
2489 tp->pcie_cap + PCI_EXP_LNKCTL,
2490 lnkctl);
2491 }
2492
1da177e4
LT		 2493 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494 tw32(TG3PCI_MISC_HOST_CTRL,
2495 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
05ac4cb7
MC		 2497 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498 device_may_wakeup(&tp->pdev->dev) &&
2499 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
dd477003 2501 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2502 do_low_power = false;
b02fd9e3
MC		 2503 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504 !tp->link_config.phy_is_low_power) {
2505 struct phy_device *phydev;
0a459aac 2506 u32 phyid, advertising;
b02fd9e3 2507
3f0e3ad7 2508 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2509
2510 tp->link_config.phy_is_low_power = 1;
2511
2512 tp->link_config.orig_speed = phydev->speed;
2513 tp->link_config.orig_duplex = phydev->duplex;
2514 tp->link_config.orig_autoneg = phydev->autoneg;
2515 tp->link_config.orig_advertising = phydev->advertising;
2516
2517 advertising = ADVERTISED_TP |
2518 ADVERTISED_Pause |
2519 ADVERTISED_Autoneg |
2520 ADVERTISED_10baseT_Half;
2521
2522 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2523 device_should_wake) {
b02fd9e3
MC		 2524 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525 advertising |=
2526 ADVERTISED_100baseT_Half |
2527 ADVERTISED_100baseT_Full |
2528 ADVERTISED_10baseT_Full;
2529 else
2530 advertising |= ADVERTISED_10baseT_Full;
2531 }
2532
2533 phydev->advertising = advertising;
2534
2535 phy_start_aneg(phydev);
0a459aac
MC		 2536
2537 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538 if (phyid != TG3_PHY_ID_BCMAC131) {
2539 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2540 if (phyid == TG3_PHY_OUI_1 ||
2541 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2542 phyid == TG3_PHY_OUI_3)
2543 do_low_power = true;
2544 }
b02fd9e3 2545 }
dd477003 2546 } else {
2023276e 2547 do_low_power = true;
0a459aac 2548
dd477003
MC		 2549 if (tp->link_config.phy_is_low_power == 0) {
2550 tp->link_config.phy_is_low_power = 1;
2551 tp->link_config.orig_speed = tp->link_config.speed;
2552 tp->link_config.orig_duplex = tp->link_config.duplex;
2553 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554 }
1da177e4 2555
dd477003
MC		 2556 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557 tp->link_config.speed = SPEED_10;
2558 tp->link_config.duplex = DUPLEX_HALF;
2559 tp->link_config.autoneg = AUTONEG_ENABLE;
2560 tg3_setup_phy(tp, 0);
2561 }
1da177e4
LT		 2562 }
2563
b5d3772c
MC		 2564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565 u32 val;
2566
2567 val = tr32(GRC_VCPU_EXT_CTRL);
2568 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2570 int i;
2571 u32 val;
2572
2573 for (i = 0; i < 200; i++) {
2574 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576 break;
2577 msleep(1);
2578 }
2579 }
a85feb8c
GZ		 2580 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582 WOL_DRV_STATE_SHUTDOWN |
2583 WOL_DRV_WOL |
2584 WOL_SET_MAGIC_PKT);
6921d201 2585
05ac4cb7 2586 if (device_should_wake) {
1da177e4
LT		 2587 u32 mac_mode;
2588
2589 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2590 if (do_low_power) {
dd477003
MC		 2591 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592 udelay(40);
2593 }
1da177e4 2594
3f7045c1
MC		 2595 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597 else
2598 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2599
e8f3f6ca
MC		 2600 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602 ASIC_REV_5700) {
2603 u32 speed = (tp->tg3_flags &
2604 TG3_FLAG_WOL_SPEED_100MB) ?
2605 SPEED_100 : SPEED_10;
2606 if (tg3_5700_link_polarity(tp, speed))
2607 mac_mode |= MAC_MODE_LINK_POLARITY;
2608 else
2609 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610 }
1da177e4
LT		 2611 } else {
2612 mac_mode = MAC_MODE_PORT_MODE_TBI;
2613 }
2614
cbf46853 2615 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2616 tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
05ac4cb7
MC		 2618 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2624
3bda1258
MC		 2625 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626 mac_mode |= tp->mac_mode &
2627 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628 if (mac_mode & MAC_MODE_APE_TX_EN)
2629 mac_mode |= MAC_MODE_TDE_ENABLE;
2630 }
2631
1da177e4
LT		 2632 tw32_f(MAC_MODE, mac_mode);
2633 udelay(100);
2634
2635 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636 udelay(10);
2637 }
2638
2639 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642 u32 base_val;
2643
2644 base_val = tp->pci_clock_ctrl;
2645 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646 CLOCK_CTRL_TXCLK_DISABLE);
2647
b401e9e2
MC		 2648 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2650 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2651 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2652 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2653 /* do nothing */
85e94ced 2654 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2655 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656 u32 newbits1, newbits2;
2657
2658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661 CLOCK_CTRL_TXCLK_DISABLE |
2662 CLOCK_CTRL_ALTCLK);
2663 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665 newbits1 = CLOCK_CTRL_625_CORE;
2666 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667 } else {
2668 newbits1 = CLOCK_CTRL_ALTCLK;
2669 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670 }
2671
b401e9e2
MC		 2672 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673 40);
1da177e4 2674
b401e9e2
MC		 2675 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676 40);
1da177e4
LT		 2677
2678 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679 u32 newbits3;
2680
2681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684 CLOCK_CTRL_TXCLK_DISABLE |
2685 CLOCK_CTRL_44MHZ_CORE);
2686 } else {
2687 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688 }
2689
b401e9e2
MC		 2690 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2692 }
2693 }
2694
05ac4cb7 2695 if (!(device_should_wake) &&
22435849 2696 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2697 tg3_power_down_phy(tp, do_low_power);
6921d201 2698
1da177e4
LT		 2699 tg3_frob_aux_power(tp);
2700
2701 /* Workaround for unstable PLL clock */
2702 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704 u32 val = tr32(0x7d00);
2705
2706 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707 tw32(0x7d00, val);
6921d201 2708 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2709 int err;
2710
2711 err = tg3_nvram_lock(tp);
1da177e4 2712 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2713 if (!err)
2714 tg3_nvram_unlock(tp);
6921d201 2715 }
1da177e4
LT		 2716 }
2717
bbadf503
MC		 2718 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
05ac4cb7 2720 if (device_should_wake)
12dac075
RW		 2721 pci_enable_wake(tp->pdev, state, true);
2722
1da177e4 2723 /* Finally, set the new power state. */
12dac075 2724 pci_set_power_state(tp->pdev, state);
1da177e4 2725
1da177e4
LT		 2726 return 0;
2727}
2728
1da177e4
LT		 2729static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730{
2731 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732 case MII_TG3_AUX_STAT_10HALF:
2733 *speed = SPEED_10;
2734 *duplex = DUPLEX_HALF;
2735 break;
2736
2737 case MII_TG3_AUX_STAT_10FULL:
2738 *speed = SPEED_10;
2739 *duplex = DUPLEX_FULL;
2740 break;
2741
2742 case MII_TG3_AUX_STAT_100HALF:
2743 *speed = SPEED_100;
2744 *duplex = DUPLEX_HALF;
2745 break;
2746
2747 case MII_TG3_AUX_STAT_100FULL:
2748 *speed = SPEED_100;
2749 *duplex = DUPLEX_FULL;
2750 break;
2751
2752 case MII_TG3_AUX_STAT_1000HALF:
2753 *speed = SPEED_1000;
2754 *duplex = DUPLEX_HALF;
2755 break;
2756
2757 case MII_TG3_AUX_STAT_1000FULL:
2758 *speed = SPEED_1000;
2759 *duplex = DUPLEX_FULL;
2760 break;
2761
2762 default:
7f97a4bd 2763 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2764 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765 SPEED_10;
2766 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767 DUPLEX_HALF;
2768 break;
2769 }
1da177e4
LT		 2770 *speed = SPEED_INVALID;
2771 *duplex = DUPLEX_INVALID;
2772 break;
855e1111 2773 }
1da177e4
LT		 2774}
2775
2776static void tg3_phy_copper_begin(struct tg3 *tp)
2777{
2778 u32 new_adv;
2779 int i;
2780
2781 if (tp->link_config.phy_is_low_power) {
2782 /* Entering low power mode. Disable gigabit and
2783 * 100baseT advertisements.
2784 */
2785 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2794 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795 tp->link_config.advertising &=
2796 ~(ADVERTISED_1000baseT_Half |
2797 ADVERTISED_1000baseT_Full);
2798
ba4d07a8 2799 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2800 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801 new_adv |= ADVERTISE_10HALF;
2802 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803 new_adv |= ADVERTISE_10FULL;
2804 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805 new_adv |= ADVERTISE_100HALF;
2806 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2808
2809 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
1da177e4
LT		 2811 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813 if (tp->link_config.advertising &
2814 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815 new_adv = 0;
2816 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824 MII_TG3_CTRL_ENABLE_AS_MASTER);
2825 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826 } else {
2827 tg3_writephy(tp, MII_TG3_CTRL, 0);
2828 }
2829 } else {
ba4d07a8
MC		 2830 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831 new_adv |= ADVERTISE_CSMA;
2832
1da177e4
LT		 2833 /* Asking for a specific link mode. */
2834 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2835 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837 if (tp->link_config.duplex == DUPLEX_FULL)
2838 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839 else
2840 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2845 } else {
1da177e4
LT		 2846 if (tp->link_config.speed == SPEED_100) {
2847 if (tp->link_config.duplex == DUPLEX_FULL)
2848 new_adv |= ADVERTISE_100FULL;
2849 else
2850 new_adv |= ADVERTISE_100HALF;
2851 } else {
2852 if (tp->link_config.duplex == DUPLEX_FULL)
2853 new_adv |= ADVERTISE_10FULL;
2854 else
2855 new_adv |= ADVERTISE_10HALF;
2856 }
2857 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2858
2859 new_adv = 0;
1da177e4 2860 }
ba4d07a8
MC		 2861
2862 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2863 }
2864
2865 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866 tp->link_config.speed != SPEED_INVALID) {
2867 u32 bmcr, orig_bmcr;
2868
2869 tp->link_config.active_speed = tp->link_config.speed;
2870 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872 bmcr = 0;
2873 switch (tp->link_config.speed) {
2874 default:
2875 case SPEED_10:
2876 break;
2877
2878 case SPEED_100:
2879 bmcr |= BMCR_SPEED100;
2880 break;
2881
2882 case SPEED_1000:
2883 bmcr |= TG3_BMCR_SPEED1000;
2884 break;
855e1111 2885 }
1da177e4
LT		 2886
2887 if (tp->link_config.duplex == DUPLEX_FULL)
2888 bmcr |= BMCR_FULLDPLX;
2889
2890 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891 (bmcr != orig_bmcr)) {
2892 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893 for (i = 0; i < 1500; i++) {
2894 u32 tmp;
2895
2896 udelay(10);
2897 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898 tg3_readphy(tp, MII_BMSR, &tmp))
2899 continue;
2900 if (!(tmp & BMSR_LSTATUS)) {
2901 udelay(40);
2902 break;
2903 }
2904 }
2905 tg3_writephy(tp, MII_BMCR, bmcr);
2906 udelay(40);
2907 }
2908 } else {
2909 tg3_writephy(tp, MII_BMCR,
2910 BMCR_ANENABLE | BMCR_ANRESTART);
2911 }
2912}
2913
2914static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915{
2916 int err;
2917
2918 /* Turn off tap power management. */
2919 /* Set Extended packet length bit */
2920 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937 udelay(40);
2938
2939 return err;
2940}
2941
3600d918 2942static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2943{
3600d918
MC		 2944 u32 adv_reg, all_mask = 0;
2945
2946 if (mask & ADVERTISED_10baseT_Half)
2947 all_mask |= ADVERTISE_10HALF;
2948 if (mask & ADVERTISED_10baseT_Full)
2949 all_mask |= ADVERTISE_10FULL;
2950 if (mask & ADVERTISED_100baseT_Half)
2951 all_mask |= ADVERTISE_100HALF;
2952 if (mask & ADVERTISED_100baseT_Full)
2953 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2954
2955 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956 return 0;
2957
1da177e4
LT		 2958 if ((adv_reg & all_mask) != all_mask)
2959 return 0;
2960 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961 u32 tg3_ctrl;
2962
3600d918
MC		 2963 all_mask = 0;
2964 if (mask & ADVERTISED_1000baseT_Half)
2965 all_mask |= ADVERTISE_1000HALF;
2966 if (mask & ADVERTISED_1000baseT_Full)
2967 all_mask |= ADVERTISE_1000FULL;
2968
1da177e4
LT		 2969 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970 return 0;
2971
1da177e4
LT		 2972 if ((tg3_ctrl & all_mask) != all_mask)
2973 return 0;
2974 }
2975 return 1;
2976}
2977
ef167e27
MC		 2978static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979{
2980 u32 curadv, reqadv;
2981
2982 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983 return 1;
2984
2985 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989 if (curadv != reqadv)
2990 return 0;
2991
2992 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993 tg3_readphy(tp, MII_LPA, rmtadv);
2994 } else {
2995 /* Reprogram the advertisement register, even if it
2996 * does not affect the current link. If the link
2997 * gets renegotiated in the future, we can save an
2998 * additional renegotiation cycle by advertising
2999 * it correctly in the first place.
3000 */
3001 if (curadv != reqadv) {
3002 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003 ADVERTISE_PAUSE_ASYM);
3004 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005 }
3006 }
3007
3008 return 1;
3009}
3010
1da177e4
LT		 3011static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012{
3013 int current_link_up;
3014 u32 bmsr, dummy;
ef167e27 3015 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3016 u16 current_speed;
3017 u8 current_duplex;
3018 int i, err;
3019
3020 tw32(MAC_EVENT, 0);
3021
3022 tw32_f(MAC_STATUS,
3023 (MAC_STATUS_SYNC_CHANGED |
3024 MAC_STATUS_CFG_CHANGED |
3025 MAC_STATUS_MI_COMPLETION |
3026 MAC_STATUS_LNKSTATE_CHANGED));
3027 udelay(40);
3028
8ef21428
MC		 3029 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030 tw32_f(MAC_MI_MODE,
3031 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032 udelay(80);
3033 }
1da177e4
LT		 3034
3035 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037 /* Some third-party PHYs need to be reset on link going
3038 * down.
3039 */
3040 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043 netif_carrier_ok(tp->dev)) {
3044 tg3_readphy(tp, MII_BMSR, &bmsr);
3045 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046 !(bmsr & BMSR_LSTATUS))
3047 force_reset = 1;
3048 }
3049 if (force_reset)
3050 tg3_phy_reset(tp);
3051
3052 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056 bmsr = 0;
3057
3058 if (!(bmsr & BMSR_LSTATUS)) {
3059 err = tg3_init_5401phy_dsp(tp);
3060 if (err)
3061 return err;
3062
3063 tg3_readphy(tp, MII_BMSR, &bmsr);
3064 for (i = 0; i < 1000; i++) {
3065 udelay(10);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS)) {
3068 udelay(40);
3069 break;
3070 }
3071 }
3072
3073 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074 !(bmsr & BMSR_LSTATUS) &&
3075 tp->link_config.active_speed == SPEED_1000) {
3076 err = tg3_phy_reset(tp);
3077 if (!err)
3078 err = tg3_init_5401phy_dsp(tp);
3079 if (err)
3080 return err;
3081 }
3082 }
3083 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085 /* 5701 {A0,B0} CRC bug workaround */
3086 tg3_writephy(tp, 0x15, 0x0a75);
3087 tg3_writephy(tp, 0x1c, 0x8c68);
3088 tg3_writephy(tp, 0x1c, 0x8d68);
3089 tg3_writephy(tp, 0x1c, 0x8c68);
3090 }
3091
3092 /* Clear pending interrupts... */
3093 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3098 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3099 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106 else
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108 }
3109
3110 current_link_up = 0;
3111 current_speed = SPEED_INVALID;
3112 current_duplex = DUPLEX_INVALID;
3113
3114 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115 u32 val;
3116
3117 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119 if (!(val & (1 << 10))) {
3120 val |= (1 << 10);
3121 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122 goto relink;
3123 }
3124 }
3125
3126 bmsr = 0;
3127 for (i = 0; i < 100; i++) {
3128 tg3_readphy(tp, MII_BMSR, &bmsr);
3129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130 (bmsr & BMSR_LSTATUS))
3131 break;
3132 udelay(40);
3133 }
3134
3135 if (bmsr & BMSR_LSTATUS) {
3136 u32 aux_stat, bmcr;
3137
3138 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139 for (i = 0; i < 2000; i++) {
3140 udelay(10);
3141 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142 aux_stat)
3143 break;
3144 }
3145
3146 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147 &current_speed,
3148 &current_duplex);
3149
3150 bmcr = 0;
3151 for (i = 0; i < 200; i++) {
3152 tg3_readphy(tp, MII_BMCR, &bmcr);
3153 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154 continue;
3155 if (bmcr && bmcr != 0x7fff)
3156 break;
3157 udelay(10);
3158 }
3159
ef167e27
MC		 3160 lcl_adv = 0;
3161 rmt_adv = 0;
1da177e4 3162
ef167e27
MC		 3163 tp->link_config.active_speed = current_speed;
3164 tp->link_config.active_duplex = current_duplex;
3165
3166 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167 if ((bmcr & BMCR_ANENABLE) &&
3168 tg3_copper_is_advertising_all(tp,
3169 tp->link_config.advertising)) {
3170 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171 &rmt_adv))
3172 current_link_up = 1;
1da177e4
LT		 3173 }
3174 } else {
3175 if (!(bmcr & BMCR_ANENABLE) &&
3176 tp->link_config.speed == current_speed &&
ef167e27
MC		 3177 tp->link_config.duplex == current_duplex &&
3178 tp->link_config.flowctrl ==
3179 tp->link_config.active_flowctrl) {
1da177e4 3180 current_link_up = 1;
1da177e4
LT		 3181 }
3182 }
3183
ef167e27
MC		 3184 if (current_link_up == 1 &&
3185 tp->link_config.active_duplex == DUPLEX_FULL)
3186 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3187 }
3188
1da177e4 3189relink:
6921d201 3190 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3191 u32 tmp;
3192
3193 tg3_phy_copper_begin(tp);
3194
3195 tg3_readphy(tp, MII_BMSR, &tmp);
3196 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197 (tmp & BMSR_LSTATUS))
3198 current_link_up = 1;
3199 }
3200
3201 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202 if (current_link_up == 1) {
3203 if (tp->link_config.active_speed == SPEED_100 ||
3204 tp->link_config.active_speed == SPEED_10)
3205 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206 else
3207 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3208 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210 else
1da177e4
LT		 3211 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214 if (tp->link_config.active_duplex == DUPLEX_HALF)
3215 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
1da177e4 3217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3218 if (current_link_up == 1 &&
3219 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3220 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3221 else
3222 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3223 }
3224
3225 /* ??? Without this setting Netgear GA302T PHY does not
3226 * ??? send/receive packets...
3227 */
3228 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232 udelay(80);
3233 }
3234
3235 tw32_f(MAC_MODE, tp->mac_mode);
3236 udelay(40);
3237
3238 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239 /* Polled via timer. */
3240 tw32_f(MAC_EVENT, 0);
3241 } else {
3242 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243 }
3244 udelay(40);
3245
3246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247 current_link_up == 1 &&
3248 tp->link_config.active_speed == SPEED_1000 &&
3249 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251 udelay(120);
3252 tw32_f(MAC_STATUS,
3253 (MAC_STATUS_SYNC_CHANGED |
3254 MAC_STATUS_CFG_CHANGED));
3255 udelay(40);
3256 tg3_write_mem(tp,
3257 NIC_SRAM_FIRMWARE_MBOX,
3258 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259 }
3260
5e7dfd0f
MC		 3261 /* Prevent send BD corruption. */
3262 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263 u16 oldlnkctl, newlnkctl;
3264
3265 pci_read_config_word(tp->pdev,
3266 tp->pcie_cap + PCI_EXP_LNKCTL,
3267 &oldlnkctl);
3268 if (tp->link_config.active_speed == SPEED_100 ||
3269 tp->link_config.active_speed == SPEED_10)
3270 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271 else
3272 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273 if (newlnkctl != oldlnkctl)
3274 pci_write_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3276 newlnkctl);
3277 }
3278
1da177e4
LT		 3279 if (current_link_up != netif_carrier_ok(tp->dev)) {
3280 if (current_link_up)
3281 netif_carrier_on(tp->dev);
3282 else
3283 netif_carrier_off(tp->dev);
3284 tg3_link_report(tp);
3285 }
3286
3287 return 0;
3288}
3289
3290struct tg3_fiber_aneginfo {
3291 int state;
3292#define ANEG_STATE_UNKNOWN 0
3293#define ANEG_STATE_AN_ENABLE 1
3294#define ANEG_STATE_RESTART_INIT 2
3295#define ANEG_STATE_RESTART 3
3296#define ANEG_STATE_DISABLE_LINK_OK 4
3297#define ANEG_STATE_ABILITY_DETECT_INIT 5
3298#define ANEG_STATE_ABILITY_DETECT 6
3299#define ANEG_STATE_ACK_DETECT_INIT 7
3300#define ANEG_STATE_ACK_DETECT 8
3301#define ANEG_STATE_COMPLETE_ACK_INIT 9
3302#define ANEG_STATE_COMPLETE_ACK 10
3303#define ANEG_STATE_IDLE_DETECT_INIT 11
3304#define ANEG_STATE_IDLE_DETECT 12
3305#define ANEG_STATE_LINK_OK 13
3306#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3307#define ANEG_STATE_NEXT_PAGE_WAIT 15
3308
3309 u32 flags;
3310#define MR_AN_ENABLE 0x00000001
3311#define MR_RESTART_AN 0x00000002
3312#define MR_AN_COMPLETE 0x00000004
3313#define MR_PAGE_RX 0x00000008
3314#define MR_NP_LOADED 0x00000010
3315#define MR_TOGGLE_TX 0x00000020
3316#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3317#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3318#define MR_LP_ADV_SYM_PAUSE 0x00000100
3319#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3320#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322#define MR_LP_ADV_NEXT_PAGE 0x00001000
3323#define MR_TOGGLE_RX 0x00002000
3324#define MR_NP_RX 0x00004000
3325
3326#define MR_LINK_OK 0x80000000
3327
3328 unsigned long link_time, cur_time;
3329
3330 u32 ability_match_cfg;
3331 int ability_match_count;
3332
3333 char ability_match, idle_match, ack_match;
3334
3335 u32 txconfig, rxconfig;
3336#define ANEG_CFG_NP 0x00000080
3337#define ANEG_CFG_ACK 0x00000040
3338#define ANEG_CFG_RF2 0x00000020
3339#define ANEG_CFG_RF1 0x00000010
3340#define ANEG_CFG_PS2 0x00000001
3341#define ANEG_CFG_PS1 0x00008000
3342#define ANEG_CFG_HD 0x00004000
3343#define ANEG_CFG_FD 0x00002000
3344#define ANEG_CFG_INVAL 0x00001f06
3345
3346};
3347#define ANEG_OK 0
3348#define ANEG_DONE 1
3349#define ANEG_TIMER_ENAB 2
3350#define ANEG_FAILED -1
3351
3352#define ANEG_STATE_SETTLE_TIME 10000
3353
3354static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355 struct tg3_fiber_aneginfo *ap)
3356{
5be73b47 3357 u16 flowctrl;
1da177e4
LT		 3358 unsigned long delta;
3359 u32 rx_cfg_reg;
3360 int ret;
3361
3362 if (ap->state == ANEG_STATE_UNKNOWN) {
3363 ap->rxconfig = 0;
3364 ap->link_time = 0;
3365 ap->cur_time = 0;
3366 ap->ability_match_cfg = 0;
3367 ap->ability_match_count = 0;
3368 ap->ability_match = 0;
3369 ap->idle_match = 0;
3370 ap->ack_match = 0;
3371 }
3372 ap->cur_time++;
3373
3374 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377 if (rx_cfg_reg != ap->ability_match_cfg) {
3378 ap->ability_match_cfg = rx_cfg_reg;
3379 ap->ability_match = 0;
3380 ap->ability_match_count = 0;
3381 } else {
3382 if (++ap->ability_match_count > 1) {
3383 ap->ability_match = 1;
3384 ap->ability_match_cfg = rx_cfg_reg;
3385 }
3386 }
3387 if (rx_cfg_reg & ANEG_CFG_ACK)
3388 ap->ack_match = 1;
3389 else
3390 ap->ack_match = 0;
3391
3392 ap->idle_match = 0;
3393 } else {
3394 ap->idle_match = 1;
3395 ap->ability_match_cfg = 0;
3396 ap->ability_match_count = 0;
3397 ap->ability_match = 0;
3398 ap->ack_match = 0;
3399
3400 rx_cfg_reg = 0;
3401 }
3402
3403 ap->rxconfig = rx_cfg_reg;
3404 ret = ANEG_OK;
3405
3406 switch(ap->state) {
3407 case ANEG_STATE_UNKNOWN:
3408 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409 ap->state = ANEG_STATE_AN_ENABLE;
3410
3411 /* fallthru */
3412 case ANEG_STATE_AN_ENABLE:
3413 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414 if (ap->flags & MR_AN_ENABLE) {
3415 ap->link_time = 0;
3416 ap->cur_time = 0;
3417 ap->ability_match_cfg = 0;
3418 ap->ability_match_count = 0;
3419 ap->ability_match = 0;
3420 ap->idle_match = 0;
3421 ap->ack_match = 0;
3422
3423 ap->state = ANEG_STATE_RESTART_INIT;
3424 } else {
3425 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426 }
3427 break;
3428
3429 case ANEG_STATE_RESTART_INIT:
3430 ap->link_time = ap->cur_time;
3431 ap->flags &= ~(MR_NP_LOADED);
3432 ap->txconfig = 0;
3433 tw32(MAC_TX_AUTO_NEG, 0);
3434 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435 tw32_f(MAC_MODE, tp->mac_mode);
3436 udelay(40);
3437
3438 ret = ANEG_TIMER_ENAB;
3439 ap->state = ANEG_STATE_RESTART;
3440
3441 /* fallthru */
3442 case ANEG_STATE_RESTART:
3443 delta = ap->cur_time - ap->link_time;
3444 if (delta > ANEG_STATE_SETTLE_TIME) {
3445 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446 } else {
3447 ret = ANEG_TIMER_ENAB;
3448 }
3449 break;
3450
3451 case ANEG_STATE_DISABLE_LINK_OK:
3452 ret = ANEG_DONE;
3453 break;
3454
3455 case ANEG_STATE_ABILITY_DETECT_INIT:
3456 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3457 ap->txconfig = ANEG_CFG_FD;
3458 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459 if (flowctrl & ADVERTISE_1000XPAUSE)
3460 ap->txconfig |= ANEG_CFG_PS1;
3461 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3463 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465 tw32_f(MAC_MODE, tp->mac_mode);
3466 udelay(40);
3467
3468 ap->state = ANEG_STATE_ABILITY_DETECT;
3469 break;
3470
3471 case ANEG_STATE_ABILITY_DETECT:
3472 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474 }
3475 break;
3476
3477 case ANEG_STATE_ACK_DETECT_INIT:
3478 ap->txconfig |= ANEG_CFG_ACK;
3479 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481 tw32_f(MAC_MODE, tp->mac_mode);
3482 udelay(40);
3483
3484 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486 /* fallthru */
3487 case ANEG_STATE_ACK_DETECT:
3488 if (ap->ack_match != 0) {
3489 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492 } else {
3493 ap->state = ANEG_STATE_AN_ENABLE;
3494 }
3495 } else if (ap->ability_match != 0 &&
3496 ap->rxconfig == 0) {
3497 ap->state = ANEG_STATE_AN_ENABLE;
3498 }
3499 break;
3500
3501 case ANEG_STATE_COMPLETE_ACK_INIT:
3502 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503 ret = ANEG_FAILED;
3504 break;
3505 }
3506 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507 MR_LP_ADV_HALF_DUPLEX |
3508 MR_LP_ADV_SYM_PAUSE |
3509 MR_LP_ADV_ASYM_PAUSE |
3510 MR_LP_ADV_REMOTE_FAULT1 |
3511 MR_LP_ADV_REMOTE_FAULT2 |
3512 MR_LP_ADV_NEXT_PAGE |
3513 MR_TOGGLE_RX |
3514 MR_NP_RX);
3515 if (ap->rxconfig & ANEG_CFG_FD)
3516 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517 if (ap->rxconfig & ANEG_CFG_HD)
3518 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519 if (ap->rxconfig & ANEG_CFG_PS1)
3520 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521 if (ap->rxconfig & ANEG_CFG_PS2)
3522 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523 if (ap->rxconfig & ANEG_CFG_RF1)
3524 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525 if (ap->rxconfig & ANEG_CFG_RF2)
3526 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527 if (ap->rxconfig & ANEG_CFG_NP)
3528 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530 ap->link_time = ap->cur_time;
3531
3532 ap->flags ^= (MR_TOGGLE_TX);
3533 if (ap->rxconfig & 0x0008)
3534 ap->flags |= MR_TOGGLE_RX;
3535 if (ap->rxconfig & ANEG_CFG_NP)
3536 ap->flags |= MR_NP_RX;
3537 ap->flags |= MR_PAGE_RX;
3538
3539 ap->state = ANEG_STATE_COMPLETE_ACK;
3540 ret = ANEG_TIMER_ENAB;
3541 break;
3542
3543 case ANEG_STATE_COMPLETE_ACK:
3544 if (ap->ability_match != 0 &&
3545 ap->rxconfig == 0) {
3546 ap->state = ANEG_STATE_AN_ENABLE;
3547 break;
3548 }
3549 delta = ap->cur_time - ap->link_time;
3550 if (delta > ANEG_STATE_SETTLE_TIME) {
3551 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553 } else {
3554 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555 !(ap->flags & MR_NP_RX)) {
3556 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557 } else {
3558 ret = ANEG_FAILED;
3559 }
3560 }
3561 }
3562 break;
3563
3564 case ANEG_STATE_IDLE_DETECT_INIT:
3565 ap->link_time = ap->cur_time;
3566 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567 tw32_f(MAC_MODE, tp->mac_mode);
3568 udelay(40);
3569
3570 ap->state = ANEG_STATE_IDLE_DETECT;
3571 ret = ANEG_TIMER_ENAB;
3572 break;
3573
3574 case ANEG_STATE_IDLE_DETECT:
3575 if (ap->ability_match != 0 &&
3576 ap->rxconfig == 0) {
3577 ap->state = ANEG_STATE_AN_ENABLE;
3578 break;
3579 }
3580 delta = ap->cur_time - ap->link_time;
3581 if (delta > ANEG_STATE_SETTLE_TIME) {
3582 /* XXX another gem from the Broadcom driver :( */
3583 ap->state = ANEG_STATE_LINK_OK;
3584 }
3585 break;
3586
3587 case ANEG_STATE_LINK_OK:
3588 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589 ret = ANEG_DONE;
3590 break;
3591
3592 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593 /* ??? unimplemented */
3594 break;
3595
3596 case ANEG_STATE_NEXT_PAGE_WAIT:
3597 /* ??? unimplemented */
3598 break;
3599
3600 default:
3601 ret = ANEG_FAILED;
3602 break;
855e1111 3603 }
1da177e4
LT		 3604
3605 return ret;
3606}
3607
5be73b47 3608static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3609{
3610 int res = 0;
3611 struct tg3_fiber_aneginfo aninfo;
3612 int status = ANEG_FAILED;
3613 unsigned int tick;
3614 u32 tmp;
3615
3616 tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620 udelay(40);
3621
3622 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623 udelay(40);
3624
3625 memset(&aninfo, 0, sizeof(aninfo));
3626 aninfo.flags |= MR_AN_ENABLE;
3627 aninfo.state = ANEG_STATE_UNKNOWN;
3628 aninfo.cur_time = 0;
3629 tick = 0;
3630 while (++tick < 195000) {
3631 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632 if (status == ANEG_DONE || status == ANEG_FAILED)
3633 break;
3634
3635 udelay(1);
3636 }
3637
3638 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639 tw32_f(MAC_MODE, tp->mac_mode);
3640 udelay(40);
3641
5be73b47
MC		 3642 *txflags = aninfo.txconfig;
3643 *rxflags = aninfo.flags;
1da177e4
LT		 3644
3645 if (status == ANEG_DONE &&
3646 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647 MR_LP_ADV_FULL_DUPLEX)))
3648 res = 1;
3649
3650 return res;
3651}
3652
3653static void tg3_init_bcm8002(struct tg3 *tp)
3654{
3655 u32 mac_status = tr32(MAC_STATUS);
3656 int i;
3657
3658 /* Reset when initting first time or we have a link. */
3659 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660 !(mac_status & MAC_STATUS_PCS_SYNCED))
3661 return;
3662
3663 /* Set PLL lock range. */
3664 tg3_writephy(tp, 0x16, 0x8007);
3665
3666 /* SW reset */
3667 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669 /* Wait for reset to complete. */
3670 /* XXX schedule_timeout() ... */
3671 for (i = 0; i < 500; i++)
3672 udelay(10);
3673
3674 /* Config mode; select PMA/Ch 1 regs. */
3675 tg3_writephy(tp, 0x10, 0x8411);
3676
3677 /* Enable auto-lock and comdet, select txclk for tx. */
3678 tg3_writephy(tp, 0x11, 0x0a10);
3679
3680 tg3_writephy(tp, 0x18, 0x00a0);
3681 tg3_writephy(tp, 0x16, 0x41ff);
3682
3683 /* Assert and deassert POR. */
3684 tg3_writephy(tp, 0x13, 0x0400);
3685 udelay(40);
3686 tg3_writephy(tp, 0x13, 0x0000);
3687
3688 tg3_writephy(tp, 0x11, 0x0a50);
3689 udelay(40);
3690 tg3_writephy(tp, 0x11, 0x0a10);
3691
3692 /* Wait for signal to stabilize */
3693 /* XXX schedule_timeout() ... */
3694 for (i = 0; i < 15000; i++)
3695 udelay(10);
3696
3697 /* Deselect the channel register so we can read the PHYID
3698 * later.
3699 */
3700 tg3_writephy(tp, 0x10, 0x8011);
3701}
3702
3703static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704{
82cd3d11 3705 u16 flowctrl;
1da177e4
LT		 3706 u32 sg_dig_ctrl, sg_dig_status;
3707 u32 serdes_cfg, expected_sg_dig_ctrl;
3708 int workaround, port_a;
3709 int current_link_up;
3710
3711 serdes_cfg = 0;
3712 expected_sg_dig_ctrl = 0;
3713 workaround = 0;
3714 port_a = 1;
3715 current_link_up = 0;
3716
3717 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719 workaround = 1;
3720 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721 port_a = 0;
3722
3723 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724 /* preserve bits 20-23 for voltage regulator */
3725 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726 }
3727
3728 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3731 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3732 if (workaround) {
3733 u32 val = serdes_cfg;
3734
3735 if (port_a)
3736 val |= 0xc010000;
3737 else
3738 val |= 0x4010000;
3739 tw32_f(MAC_SERDES_CFG, val);
3740 }
c98f6e3b
MC		 3741
3742 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3743 }
3744 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745 tg3_setup_flow_control(tp, 0, 0);
3746 current_link_up = 1;
3747 }
3748 goto out;
3749 }
3750
3751 /* Want auto-negotiation. */
c98f6e3b 3752 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3753
82cd3d11
MC		 3754 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755 if (flowctrl & ADVERTISE_1000XPAUSE)
3756 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3759
3760 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3761 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762 tp->serdes_counter &&
3763 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764 MAC_STATUS_RCVD_CFG)) ==
3765 MAC_STATUS_PCS_SYNCED)) {
3766 tp->serdes_counter--;
3767 current_link_up = 1;
3768 goto out;
3769 }
3770restart_autoneg:
1da177e4
LT		 3771 if (workaround)
3772 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3773 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3774 udelay(5);
3775 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3d3ebe74
MC		 3777 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3779 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3781 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3782 mac_status = tr32(MAC_STATUS);
3783
c98f6e3b 3784 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3785 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3786 u32 local_adv = 0, remote_adv = 0;
3787
3788 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789 local_adv |= ADVERTISE_1000XPAUSE;
3790 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3792
c98f6e3b 3793 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3794 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3795 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3796 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3797
3798 tg3_setup_flow_control(tp, local_adv, remote_adv);
3799 current_link_up = 1;
3d3ebe74
MC		 3800 tp->serdes_counter = 0;
3801 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3802 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3803 if (tp->serdes_counter)
3804 tp->serdes_counter--;
1da177e4
LT		 3805 else {
3806 if (workaround) {
3807 u32 val = serdes_cfg;
3808
3809 if (port_a)
3810 val |= 0xc010000;
3811 else
3812 val |= 0x4010000;
3813
3814 tw32_f(MAC_SERDES_CFG, val);
3815 }
3816
c98f6e3b 3817 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3818 udelay(40);
3819
3820 /* Link parallel detection - link is up */
3821 /* only if we have PCS_SYNC and not */
3822 /* receiving config code words */
3823 mac_status = tr32(MAC_STATUS);
3824 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826 tg3_setup_flow_control(tp, 0, 0);
3827 current_link_up = 1;
3d3ebe74
MC		 3828 tp->tg3_flags2 |=
3829 TG3_FLG2_PARALLEL_DETECT;
3830 tp->serdes_counter =
3831 SERDES_PARALLEL_DET_TIMEOUT;
3832 } else
3833 goto restart_autoneg;
1da177e4
LT		 3834 }
3835 }
3d3ebe74
MC		 3836 } else {
3837 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3839 }
3840
3841out:
3842 return current_link_up;
3843}
3844
3845static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846{
3847 int current_link_up = 0;
3848
5cf64b8a 3849 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3850 goto out;
1da177e4
LT		 3851
3852 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3853 u32 txflags, rxflags;
1da177e4 3854 int i;
6aa20a22 3855
5be73b47
MC		 3856 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857 u32 local_adv = 0, remote_adv = 0;
1da177e4 3858
5be73b47
MC		 3859 if (txflags & ANEG_CFG_PS1)
3860 local_adv |= ADVERTISE_1000XPAUSE;
3861 if (txflags & ANEG_CFG_PS2)
3862 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865 remote_adv |= LPA_1000XPAUSE;
3866 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3868
3869 tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
1da177e4
LT		 3871 current_link_up = 1;
3872 }
3873 for (i = 0; i < 30; i++) {
3874 udelay(20);
3875 tw32_f(MAC_STATUS,
3876 (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 udelay(40);
3879 if ((tr32(MAC_STATUS) &
3880 (MAC_STATUS_SYNC_CHANGED |
3881 MAC_STATUS_CFG_CHANGED)) == 0)
3882 break;
3883 }
3884
3885 mac_status = tr32(MAC_STATUS);
3886 if (current_link_up == 0 &&
3887 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888 !(mac_status & MAC_STATUS_RCVD_CFG))
3889 current_link_up = 1;
3890 } else {
5be73b47
MC		 3891 tg3_setup_flow_control(tp, 0, 0);
3892
1da177e4
LT		 3893 /* Forcing 1000FD link up. */
3894 current_link_up = 1;
1da177e4
LT		 3895
3896 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897 udelay(40);
e8f3f6ca
MC		 3898
3899 tw32_f(MAC_MODE, tp->mac_mode);
3900 udelay(40);
1da177e4
LT		 3901 }
3902
3903out:
3904 return current_link_up;
3905}
3906
3907static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908{
3909 u32 orig_pause_cfg;
3910 u16 orig_active_speed;
3911 u8 orig_active_duplex;
3912 u32 mac_status;
3913 int current_link_up;
3914 int i;
3915
8d018621 3916 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3917 orig_active_speed = tp->link_config.active_speed;
3918 orig_active_duplex = tp->link_config.active_duplex;
3919
3920 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921 netif_carrier_ok(tp->dev) &&
3922 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923 mac_status = tr32(MAC_STATUS);
3924 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925 MAC_STATUS_SIGNAL_DET |
3926 MAC_STATUS_CFG_CHANGED |
3927 MAC_STATUS_RCVD_CFG);
3928 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929 MAC_STATUS_SIGNAL_DET)) {
3930 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931 MAC_STATUS_CFG_CHANGED));
3932 return 0;
3933 }
3934 }
3935
3936 tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940 tw32_f(MAC_MODE, tp->mac_mode);
3941 udelay(40);
3942
3943 if (tp->phy_id == PHY_ID_BCM8002)
3944 tg3_init_bcm8002(tp);
3945
3946 /* Enable link change event even when serdes polling. */
3947 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948 udelay(40);
3949
3950 current_link_up = 0;
3951 mac_status = tr32(MAC_STATUS);
3952
3953 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955 else
3956 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
898a56f8 3958 tp->napi[0].hw_status->status =
1da177e4 3959 (SD_STATUS_UPDATED |
898a56f8 3960 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3961
3962 for (i = 0; i < 100; i++) {
3963 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964 MAC_STATUS_CFG_CHANGED));
3965 udelay(5);
3966 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3967 MAC_STATUS_CFG_CHANGED |
3968 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3969 break;
3970 }
3971
3972 mac_status = tr32(MAC_STATUS);
3973 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974 current_link_up = 0;
3d3ebe74
MC		 3975 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976 tp->serdes_counter == 0) {
1da177e4
LT		 3977 tw32_f(MAC_MODE, (tp->mac_mode |
3978 MAC_MODE_SEND_CONFIGS));
3979 udelay(1);
3980 tw32_f(MAC_MODE, tp->mac_mode);
3981 }
3982 }
3983
3984 if (current_link_up == 1) {
3985 tp->link_config.active_speed = SPEED_1000;
3986 tp->link_config.active_duplex = DUPLEX_FULL;
3987 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988 LED_CTRL_LNKLED_OVERRIDE |
3989 LED_CTRL_1000MBPS_ON));
3990 } else {
3991 tp->link_config.active_speed = SPEED_INVALID;
3992 tp->link_config.active_duplex = DUPLEX_INVALID;
3993 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994 LED_CTRL_LNKLED_OVERRIDE |
3995 LED_CTRL_TRAFFIC_OVERRIDE));
3996 }
3997
3998 if (current_link_up != netif_carrier_ok(tp->dev)) {
3999 if (current_link_up)
4000 netif_carrier_on(tp->dev);
4001 else
4002 netif_carrier_off(tp->dev);
4003 tg3_link_report(tp);
4004 } else {
8d018621 4005 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4006 if (orig_pause_cfg != now_pause_cfg ||
4007 orig_active_speed != tp->link_config.active_speed ||
4008 orig_active_duplex != tp->link_config.active_duplex)
4009 tg3_link_report(tp);
4010 }
4011
4012 return 0;
4013}
4014
747e8f8b
MC		 4015static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016{
4017 int current_link_up, err = 0;
4018 u32 bmsr, bmcr;
4019 u16 current_speed;
4020 u8 current_duplex;
ef167e27 4021 u32 local_adv, remote_adv;
747e8f8b
MC		 4022
4023 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024 tw32_f(MAC_MODE, tp->mac_mode);
4025 udelay(40);
4026
4027 tw32(MAC_EVENT, 0);
4028
4029 tw32_f(MAC_STATUS,
4030 (MAC_STATUS_SYNC_CHANGED |
4031 MAC_STATUS_CFG_CHANGED |
4032 MAC_STATUS_MI_COMPLETION |
4033 MAC_STATUS_LNKSTATE_CHANGED));
4034 udelay(40);
4035
4036 if (force_reset)
4037 tg3_phy_reset(tp);
4038
4039 current_link_up = 0;
4040 current_speed = SPEED_INVALID;
4041 current_duplex = DUPLEX_INVALID;
4042
4043 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047 bmsr |= BMSR_LSTATUS;
4048 else
4049 bmsr &= ~BMSR_LSTATUS;
4050 }
747e8f8b
MC		 4051
4052 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4055 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4056 /* do nothing, just check for link up at the end */
4057 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058 u32 adv, new_adv;
4059
4060 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062 ADVERTISE_1000XPAUSE |
4063 ADVERTISE_1000XPSE_ASYM |
4064 ADVERTISE_SLCT);
4065
ba4d07a8 4066 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4067
4068 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069 new_adv |= ADVERTISE_1000XHALF;
4070 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071 new_adv |= ADVERTISE_1000XFULL;
4072
4073 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076 tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4079 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4080 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082 return err;
4083 }
4084 } else {
4085 u32 new_bmcr;
4086
4087 bmcr &= ~BMCR_SPEED1000;
4088 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090 if (tp->link_config.duplex == DUPLEX_FULL)
4091 new_bmcr |= BMCR_FULLDPLX;
4092
4093 if (new_bmcr != bmcr) {
4094 /* BMCR_SPEED1000 is a reserved bit that needs
4095 * to be set on write.
4096 */
4097 new_bmcr |= BMCR_SPEED1000;
4098
4099 /* Force a linkdown */
4100 if (netif_carrier_ok(tp->dev)) {
4101 u32 adv;
4102
4103 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104 adv &= ~(ADVERTISE_1000XFULL |
4105 ADVERTISE_1000XHALF |
4106 ADVERTISE_SLCT);
4107 tg3_writephy(tp, MII_ADVERTISE, adv);
4108 tg3_writephy(tp, MII_BMCR, bmcr |
4109 BMCR_ANRESTART |
4110 BMCR_ANENABLE);
4111 udelay(10);
4112 netif_carrier_off(tp->dev);
4113 }
4114 tg3_writephy(tp, MII_BMCR, new_bmcr);
4115 bmcr = new_bmcr;
4116 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4118 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119 ASIC_REV_5714) {
4120 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121 bmsr |= BMSR_LSTATUS;
4122 else
4123 bmsr &= ~BMSR_LSTATUS;
4124 }
747e8f8b
MC		 4125 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126 }
4127 }
4128
4129 if (bmsr & BMSR_LSTATUS) {
4130 current_speed = SPEED_1000;
4131 current_link_up = 1;
4132 if (bmcr & BMCR_FULLDPLX)
4133 current_duplex = DUPLEX_FULL;
4134 else
4135 current_duplex = DUPLEX_HALF;
4136
ef167e27
MC		 4137 local_adv = 0;
4138 remote_adv = 0;
4139
747e8f8b 4140 if (bmcr & BMCR_ANENABLE) {
ef167e27 4141 u32 common;
747e8f8b
MC		 4142
4143 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145 common = local_adv & remote_adv;
4146 if (common & (ADVERTISE_1000XHALF |
4147 ADVERTISE_1000XFULL)) {
4148 if (common & ADVERTISE_1000XFULL)
4149 current_duplex = DUPLEX_FULL;
4150 else
4151 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4152 }
4153 else
4154 current_link_up = 0;
4155 }
4156 }
4157
ef167e27
MC		 4158 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
747e8f8b
MC		 4161 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162 if (tp->link_config.active_duplex == DUPLEX_HALF)
4163 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165 tw32_f(MAC_MODE, tp->mac_mode);
4166 udelay(40);
4167
4168 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170 tp->link_config.active_speed = current_speed;
4171 tp->link_config.active_duplex = current_duplex;
4172
4173 if (current_link_up != netif_carrier_ok(tp->dev)) {
4174 if (current_link_up)
4175 netif_carrier_on(tp->dev);
4176 else {
4177 netif_carrier_off(tp->dev);
4178 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179 }
4180 tg3_link_report(tp);
4181 }
4182 return err;
4183}
4184
4185static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186{
3d3ebe74 4187 if (tp->serdes_counter) {
747e8f8b 4188 /* Give autoneg time to complete. */
3d3ebe74 4189 tp->serdes_counter--;
747e8f8b
MC		 4190 return;
4191 }
4192 if (!netif_carrier_ok(tp->dev) &&
4193 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194 u32 bmcr;
4195
4196 tg3_readphy(tp, MII_BMCR, &bmcr);
4197 if (bmcr & BMCR_ANENABLE) {
4198 u32 phy1, phy2;
4199
4200 /* Select shadow register 0x1f */
4201 tg3_writephy(tp, 0x1c, 0x7c00);
4202 tg3_readphy(tp, 0x1c, &phy1);
4203
4204 /* Select expansion interrupt status register */
4205 tg3_writephy(tp, 0x17, 0x0f01);
4206 tg3_readphy(tp, 0x15, &phy2);
4207 tg3_readphy(tp, 0x15, &phy2);
4208
4209 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210 /* We have signal detect and not receiving
4211 * config code words, link is up by parallel
4212 * detection.
4213 */
4214
4215 bmcr &= ~BMCR_ANENABLE;
4216 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217 tg3_writephy(tp, MII_BMCR, bmcr);
4218 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219 }
4220 }
4221 }
4222 else if (netif_carrier_ok(tp->dev) &&
4223 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225 u32 phy2;
4226
4227 /* Select expansion interrupt status register */
4228 tg3_writephy(tp, 0x17, 0x0f01);
4229 tg3_readphy(tp, 0x15, &phy2);
4230 if (phy2 & 0x20) {
4231 u32 bmcr;
4232
4233 /* Config code words received, turn on autoneg. */
4234 tg3_readphy(tp, MII_BMCR, &bmcr);
4235 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239 }
4240 }
4241}
4242
1da177e4
LT		 4243static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244{
4245 int err;
4246
4247 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4249 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4251 } else {
4252 err = tg3_setup_copper_phy(tp, force_reset);
4253 }
4254
bcb37f6c 4255 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4256 u32 val, scale;
4257
4258 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260 scale = 65;
4261 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262 scale = 6;
4263 else
4264 scale = 12;
4265
4266 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268 tw32(GRC_MISC_CFG, val);
4269 }
4270
1da177e4
LT		 4271 if (tp->link_config.active_speed == SPEED_1000 &&
4272 tp->link_config.active_duplex == DUPLEX_HALF)
4273 tw32(MAC_TX_LENGTHS,
4274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275 (6 << TX_LENGTHS_IPG_SHIFT) |
4276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277 else
4278 tw32(MAC_TX_LENGTHS,
4279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280 (6 << TX_LENGTHS_IPG_SHIFT) |
4281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284 if (netif_carrier_ok(tp->dev)) {
4285 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4286 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4287 } else {
4288 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289 }
4290 }
4291
8ed5d97e
MC		 4292 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294 if (!netif_carrier_ok(tp->dev))
4295 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296 tp->pwrmgmt_thresh;
4297 else
4298 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299 tw32(PCIE_PWR_MGMT_THRESH, val);
4300 }
4301
1da177e4
LT		 4302 return err;
4303}
4304
df3e6548
MC		 4305/* This is called whenever we suspect that the system chipset is re-
4306 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307 * is bogus tx completions. We try to recover by setting the
4308 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309 * in the workqueue.
4310 */
4311static void tg3_tx_recover(struct tg3 *tp)
4312{
4313 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317 "mapped I/O cycles to the network device, attempting to "
4318 "recover. Please report the problem to the driver maintainer "
4319 "and include system chipset information.\n", tp->dev->name);
4320
4321 spin_lock(&tp->lock);
df3e6548 4322 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4323 spin_unlock(&tp->lock);
4324}
4325
f3f3f27e 4326static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4327{
4328 smp_mb();
f3f3f27e
MC		 4329 return tnapi->tx_pending -
4330 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4331}
4332
1da177e4
LT		 4333/* Tigon3 never reports partial packet sends. So we do not
4334 * need special logic to handle SKBs that have not had all
4335 * of their frags sent yet, like SunGEM does.
4336 */
17375d25 4337static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4338{
17375d25 4339 struct tg3 *tp = tnapi->tp;
898a56f8 4340 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4341 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4342 struct netdev_queue *txq;
4343 int index = tnapi - tp->napi;
4344
4345 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346 index--;
4347
4348 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4349
4350 while (sw_idx != hw_idx) {
f3f3f27e 4351 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4352 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4353 int i, tx_bug = 0;
4354
4355 if (unlikely(skb == NULL)) {
4356 tg3_tx_recover(tp);
4357 return;
4358 }
1da177e4 4359
90079ce8 4360 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4361
4362 ri->skb = NULL;
4363
4364 sw_idx = NEXT_TX(sw_idx);
4365
4366 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4367 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4368 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369 tx_bug = 1;
1da177e4
LT		 4370 sw_idx = NEXT_TX(sw_idx);
4371 }
4372
f47c11ee 4373 dev_kfree_skb(skb);
df3e6548
MC		 4374
4375 if (unlikely(tx_bug)) {
4376 tg3_tx_recover(tp);
4377 return;
4378 }
1da177e4
LT		 4379 }
4380
f3f3f27e 4381 tnapi->tx_cons = sw_idx;
1da177e4 4382
1b2a7205
MC		 4383 /* Need to make the tx_cons update visible to tg3_start_xmit()
4384 * before checking for netif_queue_stopped(). Without the
4385 * memory barrier, there is a small possibility that tg3_start_xmit()
4386 * will miss it and cause the queue to be stopped forever.
4387 */
4388 smp_mb();
4389
fe5f5787 4390 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4392 __netif_tx_lock(txq, smp_processor_id());
4393 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4394 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4395 netif_tx_wake_queue(txq);
4396 __netif_tx_unlock(txq);
51b91468 4397 }
1da177e4
LT		 4398}
4399
4400/* Returns size of skb allocated or < 0 on error.
4401 *
4402 * We only need to fill in the address because the other members
4403 * of the RX descriptor are invariant, see tg3_init_rings.
4404 *
4405 * Note the purposeful assymetry of cpu vs. chip accesses. For
4406 * posting buffers we only dirty the first cache line of the RX
4407 * descriptor (containing the address). Whereas for the RX status
4408 * buffers the cpu only reads the last cacheline of the RX descriptor
4409 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410 */
86b21e59 4411static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4412 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4413{
4414 struct tg3_rx_buffer_desc *desc;
4415 struct ring_info *map, *src_map;
4416 struct sk_buff *skb;
4417 dma_addr_t mapping;
4418 int skb_size, dest_idx;
4419
4420 src_map = NULL;
4421 switch (opaque_key) {
4422 case RXD_OPAQUE_RING_STD:
4423 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4424 desc = &tpr->rx_std[dest_idx];
4425 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4426 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4427 break;
4428
4429 case RXD_OPAQUE_RING_JUMBO:
4430 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4431 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4432 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4433 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4434 break;
4435
4436 default:
4437 return -EINVAL;
855e1111 4438 }
1da177e4
LT		 4439
4440 /* Do not overwrite any of the map or rp information
4441 * until we are sure we can commit to a new buffer.
4442 *
4443 * Callers depend upon this behavior and assume that
4444 * we leave everything unchanged if we fail.
4445 */
287be12e 4446 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4447 if (skb == NULL)
4448 return -ENOMEM;
4449
1da177e4
LT		 4450 skb_reserve(skb, tp->rx_offset);
4451
287be12e 4452 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4453 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4454 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4455 dev_kfree_skb(skb);
4456 return -EIO;
4457 }
1da177e4
LT		 4458
4459 map->skb = skb;
4460 pci_unmap_addr_set(map, mapping, mapping);
4461
1da177e4
LT		 4462 desc->addr_hi = ((u64)mapping >> 32);
4463 desc->addr_lo = ((u64)mapping & 0xffffffff);
4464
4465 return skb_size;
4466}
4467
4468/* We only need to move over in the address because the other
4469 * members of the RX descriptor are invariant. See notes above
4470 * tg3_alloc_rx_skb for full details.
4471 */
a3896167
MC		 4472static void tg3_recycle_rx(struct tg3_napi *tnapi,
4473 struct tg3_rx_prodring_set *dpr,
4474 u32 opaque_key, int src_idx,
4475 u32 dest_idx_unmasked)
1da177e4 4476{
17375d25 4477 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4478 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4479 struct ring_info *src_map, *dest_map;
4480 int dest_idx;
a3896167 4481 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4482
4483 switch (opaque_key) {
4484 case RXD_OPAQUE_RING_STD:
4485 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4486 dest_desc = &dpr->rx_std[dest_idx];
4487 dest_map = &dpr->rx_std_buffers[dest_idx];
4488 src_desc = &spr->rx_std[src_idx];
4489 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4490 break;
4491
4492 case RXD_OPAQUE_RING_JUMBO:
4493 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4494 dest_desc = &dpr->rx_jmb[dest_idx].std;
4495 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4496 src_desc = &spr->rx_jmb[src_idx].std;
4497 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4498 break;
4499
4500 default:
4501 return;
855e1111 4502 }
1da177e4
LT		 4503
4504 dest_map->skb = src_map->skb;
4505 pci_unmap_addr_set(dest_map, mapping,
4506 pci_unmap_addr(src_map, mapping));
4507 dest_desc->addr_hi = src_desc->addr_hi;
4508 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4509 src_map->skb = NULL;
4510}
4511
1da177e4
LT		 4512/* The RX ring scheme is composed of multiple rings which post fresh
4513 * buffers to the chip, and one special ring the chip uses to report
4514 * status back to the host.
4515 *
4516 * The special ring reports the status of received packets to the
4517 * host. The chip does not write into the original descriptor the
4518 * RX buffer was obtained from. The chip simply takes the original
4519 * descriptor as provided by the host, updates the status and length
4520 * field, then writes this into the next status ring entry.
4521 *
4522 * Each ring the host uses to post buffers to the chip is described
4523 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4524 * it is first placed into the on-chip ram. When the packet's length
4525 * is known, it walks down the TG3_BDINFO entries to select the ring.
4526 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4527 * which is within the range of the new packet's length is chosen.
4528 *
4529 * The "separate ring for rx status" scheme may sound queer, but it makes
4530 * sense from a cache coherency perspective. If only the host writes
4531 * to the buffer post rings, and only the chip writes to the rx status
4532 * rings, then cache lines never move beyond shared-modified state.
4533 * If both the host and chip were to write into the same ring, cache line
4534 * eviction could occur since both entities want it in an exclusive state.
4535 */
17375d25 4536static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4537{
17375d25 4538 struct tg3 *tp = tnapi->tp;
f92905de 4539 u32 work_mask, rx_std_posted = 0;
72334482 4540 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4541 u16 hw_idx;
1da177e4 4542 int received;
21f581a5 4543 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4544
8d9d7cfc 4545 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4546 /*
4547 * We need to order the read of hw_idx and the read of
4548 * the opaque cookie.
4549 */
4550 rmb();
1da177e4
LT		 4551 work_mask = 0;
4552 received = 0;
4553 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4554 struct ring_info *ri;
72334482 4555 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4556 unsigned int len;
4557 struct sk_buff *skb;
4558 dma_addr_t dma_addr;
4559 u32 opaque_key, desc_idx, *post_ptr;
4560
4561 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4562 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4563 if (opaque_key == RXD_OPAQUE_RING_STD) {
afc081f8 4564 ri = &tpr->rx_std_buffers[desc_idx];
21f581a5
MC		 4565 dma_addr = pci_unmap_addr(ri, mapping);
4566 skb = ri->skb;
411da640 4567 post_ptr = &tpr->rx_std_prod_idx;
f92905de 4568 rx_std_posted++;
1da177e4 4569 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
afc081f8 4570 ri = &tpr->rx_jmb_buffers[desc_idx];
21f581a5
MC		 4571 dma_addr = pci_unmap_addr(ri, mapping);
4572 skb = ri->skb;
411da640 4573 post_ptr = &tpr->rx_jmb_prod_idx;
21f581a5 4574 } else
1da177e4 4575 goto next_pkt_nopost;
1da177e4
LT		 4576
4577 work_mask |= opaque_key;
4578
4579 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4580 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4581 drop_it:
a3896167 4582 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4583 desc_idx, *post_ptr);
4584 drop_it_no_recycle:
4585 /* Other statistics kept track of by card. */
4586 tp->net_stats.rx_dropped++;
4587 goto next_pkt;
4588 }
4589
ad829268
MC		 4590 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4591 ETH_FCS_LEN;
1da177e4 4592
6aa20a22 4593 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4594 && tp->rx_offset == NET_IP_ALIGN
4595 /* rx_offset will likely not equal NET_IP_ALIGN
4596 * if this is a 5701 card running in PCI-X mode
4597 * [see tg3_get_invariants()]
4598 */
1da177e4
LT		 4599 ) {
4600 int skb_size;
4601
86b21e59 4602 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4603 *post_ptr);
1da177e4
LT		 4604 if (skb_size < 0)
4605 goto drop_it;
4606
afc081f8
MC		 4607 ri->skb = NULL;
4608
287be12e 4609 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4610 PCI_DMA_FROMDEVICE);
4611
4612 skb_put(skb, len);
4613 } else {
4614 struct sk_buff *copy_skb;
4615
a3896167 4616 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4617 desc_idx, *post_ptr);
4618
ad829268
MC		 4619 copy_skb = netdev_alloc_skb(tp->dev,
4620 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4621 if (copy_skb == NULL)
4622 goto drop_it_no_recycle;
4623
ad829268 4624 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4625 skb_put(copy_skb, len);
4626 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4627 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4628 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4629
4630 /* We'll reuse the original ring buffer. */
4631 skb = copy_skb;
4632 }
4633
4634 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4635 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4636 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4637 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4638 skb->ip_summed = CHECKSUM_UNNECESSARY;
4639 else
4640 skb->ip_summed = CHECKSUM_NONE;
4641
4642 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4643
4644 if (len > (tp->dev->mtu + ETH_HLEN) &&
4645 skb->protocol != htons(ETH_P_8021Q)) {
4646 dev_kfree_skb(skb);
4647 goto next_pkt;
4648 }
4649
1da177e4
LT		 4650#if TG3_VLAN_TAG_USED
4651 if (tp->vlgrp != NULL &&
4652 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4653 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4654 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4655 } else
4656#endif
17375d25 4657 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4658
1da177e4
LT		 4659 received++;
4660 budget--;
4661
4662next_pkt:
4663 (*post_ptr)++;
f92905de
MC		 4664
4665 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4666 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4667
4668 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4669 TG3_64BIT_REG_LOW, idx);
4670 work_mask &= ~RXD_OPAQUE_RING_STD;
4671 rx_std_posted = 0;
4672 }
1da177e4 4673next_pkt_nopost:
483ba50b 4674 sw_idx++;
6b31a515 4675 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4676
4677 /* Refresh hw_idx to see if there is new work */
4678 if (sw_idx == hw_idx) {
8d9d7cfc 4679 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4680 rmb();
4681 }
1da177e4
LT		 4682 }
4683
4684 /* ACK the status ring. */
72334482
MC		 4685 tnapi->rx_rcb_ptr = sw_idx;
4686 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4687
4688 /* Refill RX ring(s). */
4689 if (work_mask & RXD_OPAQUE_RING_STD) {
411da640 4690 sw_idx = tpr->rx_std_prod_idx % TG3_RX_RING_SIZE;
1da177e4
LT		 4691 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4692 sw_idx);
4693 }
4694 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
411da640 4695 sw_idx = tpr->rx_jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4696 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4697 sw_idx);
4698 }
4699 mmiowb();
4700
4701 return received;
4702}
4703
35f2d7d0 4704static void tg3_poll_link(struct tg3 *tp)
1da177e4 4705{
1da177e4
LT		 4706 /* handle link change and other phy events */
4707 if (!(tp->tg3_flags &
4708 (TG3_FLAG_USE_LINKCHG_REG |
4709 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4710 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4711
1da177e4
LT		 4712 if (sblk->status & SD_STATUS_LINK_CHG) {
4713 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4714 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4715 spin_lock(&tp->lock);
dd477003
MC		 4716 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4717 tw32_f(MAC_STATUS,
4718 (MAC_STATUS_SYNC_CHANGED |
4719 MAC_STATUS_CFG_CHANGED |
4720 MAC_STATUS_MI_COMPLETION |
4721 MAC_STATUS_LNKSTATE_CHANGED));
4722 udelay(40);
4723 } else
4724 tg3_setup_phy(tp, 0);
f47c11ee 4725 spin_unlock(&tp->lock);
1da177e4
LT		 4726 }
4727 }
35f2d7d0
MC		 4728}
4729
4730static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4731{
4732 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4733
4734 /* run TX completion thread */
f3f3f27e 4735 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4736 tg3_tx(tnapi);
6f535763 4737 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4738 return work_done;
1da177e4
LT		 4739 }
4740
1da177e4
LT		 4741 /* run RX thread, within the bounds set by NAPI.
4742 * All RX "locking" is done by ensuring outside
bea3348e 4743 * code synchronizes with tg3->napi.poll()
1da177e4 4744 */
8d9d7cfc 4745 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4746 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4747
6f535763
DM		 4748 return work_done;
4749}
4750
35f2d7d0
MC		 4751static int tg3_poll_msix(struct napi_struct *napi, int budget)
4752{
4753 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4754 struct tg3 *tp = tnapi->tp;
4755 int work_done = 0;
4756 struct tg3_hw_status *sblk = tnapi->hw_status;
4757
4758 while (1) {
4759 work_done = tg3_poll_work(tnapi, work_done, budget);
4760
4761 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4762 goto tx_recovery;
4763
4764 if (unlikely(work_done >= budget))
4765 break;
4766
4767 /* tp->last_tag is used in tg3_restart_ints() below
4768 * to tell the hw how much work has been processed,
4769 * so we must read it before checking for more work.
4770 */
4771 tnapi->last_tag = sblk->status_tag;
4772 tnapi->last_irq_tag = tnapi->last_tag;
4773 rmb();
4774
4775 /* check for RX/TX work to do */
4776 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4777 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4778 napi_complete(napi);
4779 /* Reenable interrupts. */
4780 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4781 mmiowb();
4782 break;
4783 }
4784 }
4785
4786 return work_done;
4787
4788tx_recovery:
4789 /* work_done is guaranteed to be less than budget. */
4790 napi_complete(napi);
4791 schedule_work(&tp->reset_task);
4792 return work_done;
4793}
4794
6f535763
DM		 4795static int tg3_poll(struct napi_struct *napi, int budget)
4796{
8ef0442f
MC		 4797 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4798 struct tg3 *tp = tnapi->tp;
6f535763 4799 int work_done = 0;
898a56f8 4800 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4801
4802 while (1) {
35f2d7d0
MC		 4803 tg3_poll_link(tp);
4804
17375d25 4805 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4806
4807 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4808 goto tx_recovery;
4809
4810 if (unlikely(work_done >= budget))
4811 break;
4812
4fd7ab59 4813 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4814 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4815 * to tell the hw how much work has been processed,
4816 * so we must read it before checking for more work.
4817 */
898a56f8
MC		 4818 tnapi->last_tag = sblk->status_tag;
4819 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4820 rmb();
4821 } else
4822 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4823
17375d25 4824 if (likely(!tg3_has_work(tnapi))) {
288379f0 4825 napi_complete(napi);
17375d25 4826 tg3_int_reenable(tnapi);
6f535763
DM		 4827 break;
4828 }
1da177e4
LT		 4829 }
4830
bea3348e 4831 return work_done;
6f535763
DM		 4832
4833tx_recovery:
4fd7ab59 4834 /* work_done is guaranteed to be less than budget. */
288379f0 4835 napi_complete(napi);
6f535763 4836 schedule_work(&tp->reset_task);
4fd7ab59 4837 return work_done;
1da177e4
LT		 4838}
4839
f47c11ee
DM		 4840static void tg3_irq_quiesce(struct tg3 *tp)
4841{
4f125f42
MC		 4842 int i;
4843
f47c11ee
DM		 4844 BUG_ON(tp->irq_sync);
4845
4846 tp->irq_sync = 1;
4847 smp_mb();
4848
4f125f42
MC		 4849 for (i = 0; i < tp->irq_cnt; i++)
4850 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4851}
4852
4853static inline int tg3_irq_sync(struct tg3 *tp)
4854{
4855 return tp->irq_sync;
4856}
4857
4858/* Fully shutdown all tg3 driver activity elsewhere in the system.
4859 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4860 * with as well. Most of the time, this is not necessary except when
4861 * shutting down the device.
4862 */
4863static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4864{
46966545 4865 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4866 if (irq_sync)
4867 tg3_irq_quiesce(tp);
f47c11ee
DM		 4868}
4869
4870static inline void tg3_full_unlock(struct tg3 *tp)
4871{
f47c11ee
DM		 4872 spin_unlock_bh(&tp->lock);
4873}
4874
fcfa0a32
MC		 4875/* One-shot MSI handler - Chip automatically disables interrupt
4876 * after sending MSI so driver doesn't have to do it.
4877 */
7d12e780 4878static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4879{
09943a18
MC		 4880 struct tg3_napi *tnapi = dev_id;
4881 struct tg3 *tp = tnapi->tp;
fcfa0a32 4882
898a56f8 4883 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4884 if (tnapi->rx_rcb)
4885 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4886
4887 if (likely(!tg3_irq_sync(tp)))
09943a18 4888 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4889
4890 return IRQ_HANDLED;
4891}
4892
88b06bc2
MC		 4893/* MSI ISR - No need to check for interrupt sharing and no need to
4894 * flush status block and interrupt mailbox. PCI ordering rules
4895 * guarantee that MSI will arrive after the status block.
4896 */
7d12e780 4897static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4898{
09943a18
MC		 4899 struct tg3_napi *tnapi = dev_id;
4900 struct tg3 *tp = tnapi->tp;
88b06bc2 4901
898a56f8 4902 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4903 if (tnapi->rx_rcb)
4904 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4905 /*
fac9b83e 4906 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4907 * chip-internal interrupt pending events.
fac9b83e 4908 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4909 * NIC to stop sending us irqs, engaging "in-intr-handler"
4910 * event coalescing.
4911 */
4912 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4913 if (likely(!tg3_irq_sync(tp)))
09943a18 4914 napi_schedule(&tnapi->napi);
61487480 4915
88b06bc2
MC		 4916 return IRQ_RETVAL(1);
4917}
4918
7d12e780 4919static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4920{
09943a18
MC		 4921 struct tg3_napi *tnapi = dev_id;
4922 struct tg3 *tp = tnapi->tp;
898a56f8 4923 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4924 unsigned int handled = 1;
4925
1da177e4
LT		 4926 /* In INTx mode, it is possible for the interrupt to arrive at
4927 * the CPU before the status block posted prior to the interrupt.
4928 * Reading the PCI State register will confirm whether the
4929 * interrupt is ours and will flush the status block.
4930 */
d18edcb2
MC		 4931 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4932 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4933 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4934 handled = 0;
f47c11ee 4935 goto out;
fac9b83e 4936 }
d18edcb2
MC		 4937 }
4938
4939 /*
4940 * Writing any value to intr-mbox-0 clears PCI INTA# and
4941 * chip-internal interrupt pending events.
4942 * Writing non-zero to intr-mbox-0 additional tells the
4943 * NIC to stop sending us irqs, engaging "in-intr-handler"
4944 * event coalescing.
c04cb347
MC		 4945 *
4946 * Flush the mailbox to de-assert the IRQ immediately to prevent
4947 * spurious interrupts. The flush impacts performance but
4948 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4949 */
c04cb347 4950 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4951 if (tg3_irq_sync(tp))
4952 goto out;
4953 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4954 if (likely(tg3_has_work(tnapi))) {
72334482 4955 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4956 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4957 } else {
4958 /* No work, shared interrupt perhaps? re-enable
4959 * interrupts, and flush that PCI write
4960 */
4961 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4962 0x00000000);
fac9b83e 4963 }
f47c11ee 4964out:
fac9b83e
DM		 4965 return IRQ_RETVAL(handled);
4966}
4967
7d12e780 4968static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4969{
09943a18
MC		 4970 struct tg3_napi *tnapi = dev_id;
4971 struct tg3 *tp = tnapi->tp;
898a56f8 4972 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4973 unsigned int handled = 1;
4974
fac9b83e
DM		 4975 /* In INTx mode, it is possible for the interrupt to arrive at
4976 * the CPU before the status block posted prior to the interrupt.
4977 * Reading the PCI State register will confirm whether the
4978 * interrupt is ours and will flush the status block.
4979 */
898a56f8 4980 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4981 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4982 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4983 handled = 0;
f47c11ee 4984 goto out;
1da177e4 4985 }
d18edcb2
MC		 4986 }
4987
4988 /*
4989 * writing any value to intr-mbox-0 clears PCI INTA# and
4990 * chip-internal interrupt pending events.
4991 * writing non-zero to intr-mbox-0 additional tells the
4992 * NIC to stop sending us irqs, engaging "in-intr-handler"
4993 * event coalescing.
c04cb347
MC		 4994 *
4995 * Flush the mailbox to de-assert the IRQ immediately to prevent
4996 * spurious interrupts. The flush impacts performance but
4997 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4998 */
c04cb347 4999 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5000
5001 /*
5002 * In a shared interrupt configuration, sometimes other devices'
5003 * interrupts will scream. We record the current status tag here
5004 * so that the above check can report that the screaming interrupts
5005 * are unhandled. Eventually they will be silenced.
5006 */
898a56f8 5007 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5008
d18edcb2
MC		 5009 if (tg3_irq_sync(tp))
5010 goto out;
624f8e50 5011
72334482 5012 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5013
09943a18 5014 napi_schedule(&tnapi->napi);
624f8e50 5015
f47c11ee 5016out:
1da177e4
LT		 5017 return IRQ_RETVAL(handled);
5018}
5019
7938109f 5020/* ISR for interrupt test */
7d12e780 5021static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5022{
09943a18
MC		 5023 struct tg3_napi *tnapi = dev_id;
5024 struct tg3 *tp = tnapi->tp;
898a56f8 5025 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5026
f9804ddb
MC		 5027 if ((sblk->status & SD_STATUS_UPDATED) ||
5028 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5029 tg3_disable_ints(tp);
7938109f
MC		 5030 return IRQ_RETVAL(1);
5031 }
5032 return IRQ_RETVAL(0);
5033}
5034
8e7a22e3 5035static int tg3_init_hw(struct tg3 *, int);
944d980e 5036static int tg3_halt(struct tg3 *, int, int);
1da177e4 5037
b9ec6c1b
MC		 5038/* Restart hardware after configuration changes, self-test, etc.
5039 * Invoked with tp->lock held.
5040 */
5041static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5042 __releases(tp->lock)
5043 __acquires(tp->lock)
b9ec6c1b
MC		 5044{
5045 int err;
5046
5047 err = tg3_init_hw(tp, reset_phy);
5048 if (err) {
5049 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5050 "aborting.\n", tp->dev->name);
5051 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5052 tg3_full_unlock(tp);
5053 del_timer_sync(&tp->timer);
5054 tp->irq_sync = 0;
fed97810 5055 tg3_napi_enable(tp);
b9ec6c1b
MC		 5056 dev_close(tp->dev);
5057 tg3_full_lock(tp, 0);
5058 }
5059 return err;
5060}
5061
1da177e4
LT		 5062#ifdef CONFIG_NET_POLL_CONTROLLER
5063static void tg3_poll_controller(struct net_device *dev)
5064{
4f125f42 5065 int i;
88b06bc2
MC		 5066 struct tg3 *tp = netdev_priv(dev);
5067
4f125f42
MC		 5068 for (i = 0; i < tp->irq_cnt; i++)
5069 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5070}
5071#endif
5072
c4028958 5073static void tg3_reset_task(struct work_struct *work)
1da177e4 5074{
c4028958 5075 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5076 int err;
1da177e4
LT		 5077 unsigned int restart_timer;
5078
7faa006f 5079 tg3_full_lock(tp, 0);
7faa006f
MC		 5080
5081 if (!netif_running(tp->dev)) {
7faa006f
MC		 5082 tg3_full_unlock(tp);
5083 return;
5084 }
5085
5086 tg3_full_unlock(tp);
5087
b02fd9e3
MC		 5088 tg3_phy_stop(tp);
5089
1da177e4
LT		 5090 tg3_netif_stop(tp);
5091
f47c11ee 5092 tg3_full_lock(tp, 1);
1da177e4
LT		 5093
5094 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5095 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5096
df3e6548
MC		 5097 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5098 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5099 tp->write32_rx_mbox = tg3_write_flush_reg32;
5100 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5101 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5102 }
5103
944d980e 5104 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5105 err = tg3_init_hw(tp, 1);
5106 if (err)
b9ec6c1b 5107 goto out;
1da177e4
LT		 5108
5109 tg3_netif_start(tp);
5110
1da177e4
LT		 5111 if (restart_timer)
5112 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5113
b9ec6c1b 5114out:
7faa006f 5115 tg3_full_unlock(tp);
b02fd9e3
MC		 5116
5117 if (!err)
5118 tg3_phy_start(tp);
1da177e4
LT		 5119}
5120
b0408751
MC		 5121static void tg3_dump_short_state(struct tg3 *tp)
5122{
5123 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5124 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5125 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5126 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5127}
5128
1da177e4
LT		 5129static void tg3_tx_timeout(struct net_device *dev)
5130{
5131 struct tg3 *tp = netdev_priv(dev);
5132
b0408751 5133 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5134 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5135 dev->name);
b0408751
MC		 5136 tg3_dump_short_state(tp);
5137 }
1da177e4
LT		 5138
5139 schedule_work(&tp->reset_task);
5140}
5141
c58ec932
MC		 5142/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5143static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5144{
5145 u32 base = (u32) mapping & 0xffffffff;
5146
5147 return ((base > 0xffffdcc0) &&
5148 (base + len + 8 < base));
5149}
5150
72f2afb8
MC		 5151/* Test for DMA addresses > 40-bit */
5152static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5153 int len)
5154{
5155#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5156 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5157 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5158 return 0;
5159#else
5160 return 0;
5161#endif
5162}
5163
f3f3f27e 5164static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5165
72f2afb8 5166/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5167static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5168 struct sk_buff *skb, u32 last_plus_one,
5169 u32 *start, u32 base_flags, u32 mss)
1da177e4 5170{
24f4efd4 5171 struct tg3 *tp = tnapi->tp;
41588ba1 5172 struct sk_buff *new_skb;
c58ec932 5173 dma_addr_t new_addr = 0;
1da177e4 5174 u32 entry = *start;
c58ec932 5175 int i, ret = 0;
1da177e4 5176
41588ba1
MC		 5177 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5178 new_skb = skb_copy(skb, GFP_ATOMIC);
5179 else {
5180 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5181
5182 new_skb = skb_copy_expand(skb,
5183 skb_headroom(skb) + more_headroom,
5184 skb_tailroom(skb), GFP_ATOMIC);
5185 }
5186
1da177e4 5187 if (!new_skb) {
c58ec932
MC		 5188 ret = -1;
5189 } else {
5190 /* New SKB is guaranteed to be linear. */
5191 entry = *start;
90079ce8 5192 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5193 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5194
c58ec932
MC		 5195 /* Make sure new skb does not cross any 4G boundaries.
5196 * Drop the packet if it does.
5197 */
0e1406dd
MC		 5198 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5199 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5200 if (!ret)
5201 skb_dma_unmap(&tp->pdev->dev, new_skb,
5202 DMA_TO_DEVICE);
c58ec932
MC		 5203 ret = -1;
5204 dev_kfree_skb(new_skb);
5205 new_skb = NULL;
5206 } else {
f3f3f27e 5207 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5208 base_flags, 1 | (mss << 1));
5209 *start = NEXT_TX(entry);
5210 }
1da177e4
LT		 5211 }
5212
1da177e4
LT		 5213 /* Now clean up the sw ring entries. */
5214 i = 0;
5215 while (entry != last_plus_one) {
f3f3f27e
MC		 5216 if (i == 0)
5217 tnapi->tx_buffers[entry].skb = new_skb;
5218 else
5219 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5220 entry = NEXT_TX(entry);
5221 i++;
5222 }
5223
90079ce8 5224 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5225 dev_kfree_skb(skb);
5226
c58ec932 5227 return ret;
1da177e4
LT		 5228}
5229
f3f3f27e 5230static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5231 dma_addr_t mapping, int len, u32 flags,
5232 u32 mss_and_is_end)
5233{
f3f3f27e 5234 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5235 int is_end = (mss_and_is_end & 0x1);
5236 u32 mss = (mss_and_is_end >> 1);
5237 u32 vlan_tag = 0;
5238
5239 if (is_end)
5240 flags |= TXD_FLAG_END;
5241 if (flags & TXD_FLAG_VLAN) {
5242 vlan_tag = flags >> 16;
5243 flags &= 0xffff;
5244 }
5245 vlan_tag |= (mss << TXD_MSS_SHIFT);
5246
5247 txd->addr_hi = ((u64) mapping >> 32);
5248 txd->addr_lo = ((u64) mapping & 0xffffffff);
5249 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5250 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5251}
5252
5a6f3074 5253/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5254 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5255 */
61357325
SH		 5256static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5257 struct net_device *dev)
5a6f3074
MC		 5258{
5259 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5260 u32 len, entry, base_flags, mss;
90079ce8
DM		 5261 struct skb_shared_info *sp;
5262 dma_addr_t mapping;
fe5f5787
MC		 5263 struct tg3_napi *tnapi;
5264 struct netdev_queue *txq;
5a6f3074 5265
fe5f5787
MC		 5266 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5267 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5268 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5269 tnapi++;
5a6f3074 5270
00b70504 5271 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5272 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5273 * interrupt. Furthermore, IRQ processing runs lockless so we have
5274 * no IRQ context deadlocks to worry about either. Rejoice!
5275 */
f3f3f27e 5276 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5277 if (!netif_tx_queue_stopped(txq)) {
5278 netif_tx_stop_queue(txq);
5a6f3074
MC		 5279
5280 /* This is a hard error, log it. */
5281 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5282 "queue awake!\n", dev->name);
5283 }
5a6f3074
MC		 5284 return NETDEV_TX_BUSY;
5285 }
5286
f3f3f27e 5287 entry = tnapi->tx_prod;
5a6f3074 5288 base_flags = 0;
5a6f3074 5289 mss = 0;
c13e3713 5290 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5291 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5292 u32 hdrlen;
5a6f3074
MC		 5293
5294 if (skb_header_cloned(skb) &&
5295 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5296 dev_kfree_skb(skb);
5297 goto out_unlock;
5298 }
5299
b0026624 5300 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5301 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5302 else {
eddc9ec5
ACM		 5303 struct iphdr *iph = ip_hdr(skb);
5304
ab6a5bb6 5305 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5306 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5307
eddc9ec5
ACM		 5308 iph->check = 0;
5309 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5310 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5311 }
5a6f3074 5312
e849cdc3 5313 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5314 mss |= (hdrlen & 0xc) << 12;
5315 if (hdrlen & 0x10)
5316 base_flags |= 0x00000010;
5317 base_flags |= (hdrlen & 0x3e0) << 5;
5318 } else
5319 mss |= hdrlen << 9;
5320
5a6f3074
MC		 5321 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5322 TXD_FLAG_CPU_POST_DMA);
5323
aa8223c7 5324 tcp_hdr(skb)->check = 0;
5a6f3074 5325
5a6f3074 5326 }
84fa7933 5327 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5328 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5329#if TG3_VLAN_TAG_USED
5330 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5331 base_flags |= (TXD_FLAG_VLAN |
5332 (vlan_tx_tag_get(skb) << 16));
5333#endif
5334
90079ce8
DM		 5335 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5336 dev_kfree_skb(skb);
5337 goto out_unlock;
5338 }
5339
5340 sp = skb_shinfo(skb);
5341
042a53a9 5342 mapping = sp->dma_head;
5a6f3074 5343
f3f3f27e 5344 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5345
fe5f5787
MC		 5346 len = skb_headlen(skb);
5347
f6eb9b1f
MC		 5348 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5349 !mss && skb->len > ETH_DATA_LEN)
5350 base_flags |= TXD_FLAG_JMB_PKT;
5351
f3f3f27e 5352 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5353 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5354
5355 entry = NEXT_TX(entry);
5356
5357 /* Now loop through additional data fragments, and queue them. */
5358 if (skb_shinfo(skb)->nr_frags > 0) {
5359 unsigned int i, last;
5360
5361 last = skb_shinfo(skb)->nr_frags - 1;
5362 for (i = 0; i <= last; i++) {
5363 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5364
5365 len = frag->size;
042a53a9 5366 mapping = sp->dma_maps[i];
f3f3f27e 5367 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5368
f3f3f27e 5369 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5370 base_flags, (i == last) | (mss << 1));
5371
5372 entry = NEXT_TX(entry);
5373 }
5374 }
5375
5376 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5377 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5378
f3f3f27e
MC		 5379 tnapi->tx_prod = entry;
5380 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5381 netif_tx_stop_queue(txq);
f3f3f27e 5382 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5383 netif_tx_wake_queue(txq);
5a6f3074
MC		 5384 }
5385
5386out_unlock:
cdd0db05 5387 mmiowb();
5a6f3074
MC		 5388
5389 return NETDEV_TX_OK;
5390}
5391
61357325
SH		 5392static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5393 struct net_device *);
52c0fd83
MC		 5394
5395/* Use GSO to workaround a rare TSO bug that may be triggered when the
5396 * TSO header is greater than 80 bytes.
5397 */
5398static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5399{
5400 struct sk_buff *segs, *nskb;
f3f3f27e 5401 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5402
5403 /* Estimate the number of fragments in the worst case */
f3f3f27e 5404 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5405 netif_stop_queue(tp->dev);
f3f3f27e 5406 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5407 return NETDEV_TX_BUSY;
5408
5409 netif_wake_queue(tp->dev);
52c0fd83
MC		 5410 }
5411
5412 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5413 if (IS_ERR(segs))
52c0fd83
MC		 5414 goto tg3_tso_bug_end;
5415
5416 do {
5417 nskb = segs;
5418 segs = segs->next;
5419 nskb->next = NULL;
5420 tg3_start_xmit_dma_bug(nskb, tp->dev);
5421 } while (segs);
5422
5423tg3_tso_bug_end:
5424 dev_kfree_skb(skb);
5425
5426 return NETDEV_TX_OK;
5427}
52c0fd83 5428
5a6f3074
MC		 5429/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5430 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5431 */
61357325
SH		 5432static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5433 struct net_device *dev)
1da177e4
LT		 5434{
5435 struct tg3 *tp = netdev_priv(dev);
1da177e4 5436 u32 len, entry, base_flags, mss;
90079ce8 5437 struct skb_shared_info *sp;
1da177e4 5438 int would_hit_hwbug;
90079ce8 5439 dma_addr_t mapping;
24f4efd4
MC		 5440 struct tg3_napi *tnapi;
5441 struct netdev_queue *txq;
1da177e4 5442
24f4efd4
MC		 5443 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5444 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5445 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5446 tnapi++;
1da177e4 5447
00b70504 5448 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5449 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5450 * interrupt. Furthermore, IRQ processing runs lockless so we have
5451 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5452 */
f3f3f27e 5453 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5454 if (!netif_tx_queue_stopped(txq)) {
5455 netif_tx_stop_queue(txq);
1f064a87
SH		 5456
5457 /* This is a hard error, log it. */
5458 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5459 "queue awake!\n", dev->name);
5460 }
1da177e4
LT		 5461 return NETDEV_TX_BUSY;
5462 }
5463
f3f3f27e 5464 entry = tnapi->tx_prod;
1da177e4 5465 base_flags = 0;
84fa7933 5466 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5467 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5468
c13e3713 5469 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5470 struct iphdr *iph;
92c6b8d1 5471 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5472
5473 if (skb_header_cloned(skb) &&
5474 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5475 dev_kfree_skb(skb);
5476 goto out_unlock;
5477 }
5478
ab6a5bb6 5479 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5480 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5481
52c0fd83
MC		 5482 hdr_len = ip_tcp_len + tcp_opt_len;
5483 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5484 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5485 return (tg3_tso_bug(tp, skb));
5486
1da177e4
LT		 5487 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5488 TXD_FLAG_CPU_POST_DMA);
5489
eddc9ec5
ACM		 5490 iph = ip_hdr(skb);
5491 iph->check = 0;
5492 iph->tot_len = htons(mss + hdr_len);
1da177e4 5493 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5494 tcp_hdr(skb)->check = 0;
1da177e4 5495 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5496 } else
5497 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5498 iph->daddr, 0,
5499 IPPROTO_TCP,
5500 0);
1da177e4 5501
615774fe
MC		 5502 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5503 mss |= (hdr_len & 0xc) << 12;
5504 if (hdr_len & 0x10)
5505 base_flags |= 0x00000010;
5506 base_flags |= (hdr_len & 0x3e0) << 5;
5507 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5508 mss |= hdr_len << 9;
5509 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5511 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5512 int tsflags;
5513
eddc9ec5 5514 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5515 mss |= (tsflags << 11);
5516 }
5517 } else {
eddc9ec5 5518 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5519 int tsflags;
5520
eddc9ec5 5521 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5522 base_flags |= tsflags << 12;
5523 }
5524 }
5525 }
1da177e4
LT		 5526#if TG3_VLAN_TAG_USED
5527 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5528 base_flags |= (TXD_FLAG_VLAN |
5529 (vlan_tx_tag_get(skb) << 16));
5530#endif
5531
615774fe
MC		 5532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5533 !mss && skb->len > ETH_DATA_LEN)
5534 base_flags |= TXD_FLAG_JMB_PKT;
5535
90079ce8
DM		 5536 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5537 dev_kfree_skb(skb);
5538 goto out_unlock;
5539 }
5540
5541 sp = skb_shinfo(skb);
5542
042a53a9 5543 mapping = sp->dma_head;
1da177e4 5544
f3f3f27e 5545 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5546
5547 would_hit_hwbug = 0;
5548
24f4efd4
MC		 5549 len = skb_headlen(skb);
5550
92c6b8d1
MC		 5551 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5552 would_hit_hwbug = 1;
5553
0e1406dd
MC		 5554 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5555 tg3_4g_overflow_test(mapping, len))
5556 would_hit_hwbug = 1;
5557
5558 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5559 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5560 would_hit_hwbug = 1;
0e1406dd
MC		 5561
5562 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5563 would_hit_hwbug = 1;
1da177e4 5564
f3f3f27e 5565 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5566 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5567
5568 entry = NEXT_TX(entry);
5569
5570 /* Now loop through additional data fragments, and queue them. */
5571 if (skb_shinfo(skb)->nr_frags > 0) {
5572 unsigned int i, last;
5573
5574 last = skb_shinfo(skb)->nr_frags - 1;
5575 for (i = 0; i <= last; i++) {
5576 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5577
5578 len = frag->size;
042a53a9 5579 mapping = sp->dma_maps[i];
1da177e4 5580
f3f3f27e 5581 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5582
92c6b8d1
MC		 5583 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5584 len <= 8)
5585 would_hit_hwbug = 1;
5586
0e1406dd
MC		 5587 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5588 tg3_4g_overflow_test(mapping, len))
c58ec932 5589 would_hit_hwbug = 1;
1da177e4 5590
0e1406dd
MC		 5591 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5592 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5593 would_hit_hwbug = 1;
5594
1da177e4 5595 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5596 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5597 base_flags, (i == last)|(mss << 1));
5598 else
f3f3f27e 5599 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5600 base_flags, (i == last));
5601
5602 entry = NEXT_TX(entry);
5603 }
5604 }
5605
5606 if (would_hit_hwbug) {
5607 u32 last_plus_one = entry;
5608 u32 start;
1da177e4 5609
c58ec932
MC		 5610 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5611 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5612
5613 /* If the workaround fails due to memory/mapping
5614 * failure, silently drop this packet.
5615 */
24f4efd4 5616 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5617 &start, base_flags, mss))
1da177e4
LT		 5618 goto out_unlock;
5619
5620 entry = start;
5621 }
5622
5623 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5624 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5625
f3f3f27e
MC		 5626 tnapi->tx_prod = entry;
5627 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5628 netif_tx_stop_queue(txq);
f3f3f27e 5629 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5630 netif_tx_wake_queue(txq);
51b91468 5631 }
1da177e4
LT		 5632
5633out_unlock:
cdd0db05 5634 mmiowb();
1da177e4
LT		 5635
5636 return NETDEV_TX_OK;
5637}
5638
5639static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5640 int new_mtu)
5641{
5642 dev->mtu = new_mtu;
5643
ef7f5ec0 5644 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5645 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5646 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5647 ethtool_op_set_tso(dev, 0);
5648 }
5649 else
5650 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5651 } else {
a4e2b347 5652 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5653 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5654 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5655 }
1da177e4
LT		 5656}
5657
5658static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5659{
5660 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5661 int err;
1da177e4
LT		 5662
5663 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5664 return -EINVAL;
5665
5666 if (!netif_running(dev)) {
5667 /* We'll just catch it later when the
5668 * device is up'd.
5669 */
5670 tg3_set_mtu(dev, tp, new_mtu);
5671 return 0;
5672 }
5673
b02fd9e3
MC		 5674 tg3_phy_stop(tp);
5675
1da177e4 5676 tg3_netif_stop(tp);
f47c11ee
DM		 5677
5678 tg3_full_lock(tp, 1);
1da177e4 5679
944d980e 5680 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5681
5682 tg3_set_mtu(dev, tp, new_mtu);
5683
b9ec6c1b 5684 err = tg3_restart_hw(tp, 0);
1da177e4 5685
b9ec6c1b
MC		 5686 if (!err)
5687 tg3_netif_start(tp);
1da177e4 5688
f47c11ee 5689 tg3_full_unlock(tp);
1da177e4 5690
b02fd9e3
MC		 5691 if (!err)
5692 tg3_phy_start(tp);
5693
b9ec6c1b 5694 return err;
1da177e4
LT		 5695}
5696
21f581a5
MC		 5697static void tg3_rx_prodring_free(struct tg3 *tp,
5698 struct tg3_rx_prodring_set *tpr)
1da177e4 5699{
1da177e4 5700 int i;
f3f3f27e 5701 struct ring_info *rxp;
1da177e4
LT		 5702
5703 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5704 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5705
5706 if (rxp->skb == NULL)
5707 continue;
1da177e4 5708
1da177e4
LT		 5709 pci_unmap_single(tp->pdev,
5710 pci_unmap_addr(rxp, mapping),
cf7a7298 5711 tp->rx_pkt_map_sz,
1da177e4
LT		 5712 PCI_DMA_FROMDEVICE);
5713 dev_kfree_skb_any(rxp->skb);
5714 rxp->skb = NULL;
5715 }
5716
cf7a7298
MC		 5717 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5718 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5719 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5720
cf7a7298
MC		 5721 if (rxp->skb == NULL)
5722 continue;
1da177e4 5723
cf7a7298
MC		 5724 pci_unmap_single(tp->pdev,
5725 pci_unmap_addr(rxp, mapping),
5726 TG3_RX_JMB_MAP_SZ,
5727 PCI_DMA_FROMDEVICE);
5728 dev_kfree_skb_any(rxp->skb);
5729 rxp->skb = NULL;
1da177e4 5730 }
1da177e4
LT		 5731 }
5732}
5733
5734/* Initialize tx/rx rings for packet processing.
5735 *
5736 * The chip has been shut down and the driver detached from
5737 * the networking, so no interrupts or new tx packets will
5738 * end up in the driver. tp->{tx,}lock are held and thus
5739 * we may not sleep.
5740 */
21f581a5
MC		 5741static int tg3_rx_prodring_alloc(struct tg3 *tp,
5742 struct tg3_rx_prodring_set *tpr)
1da177e4 5743{
287be12e 5744 u32 i, rx_pkt_dma_sz;
1da177e4 5745
1da177e4 5746 /* Zero out all descriptors. */
21f581a5 5747 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5748
287be12e 5749 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5750 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5751 tp->dev->mtu > ETH_DATA_LEN)
5752 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5753 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5754
1da177e4
LT		 5755 /* Initialize invariants of the rings, we only set this
5756 * stuff once. This works because the card does not
5757 * write into the rx buffer posting rings.
5758 */
5759 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5760 struct tg3_rx_buffer_desc *rxd;
5761
21f581a5 5762 rxd = &tpr->rx_std[i];
287be12e 5763 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5764 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5765 rxd->opaque = (RXD_OPAQUE_RING_STD |
5766 (i << RXD_OPAQUE_INDEX_SHIFT));
5767 }
5768
1da177e4
LT		 5769 /* Now allocate fresh SKBs for each rx ring. */
5770 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 5771 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 5772 printk(KERN_WARNING PFX
5773 "%s: Using a smaller RX standard ring, "
5774 "only %d out of %d buffers were allocated "
5775 "successfully.\n",
5776 tp->dev->name, i, tp->rx_pending);
5777 if (i == 0)
cf7a7298 5778 goto initfail;
32d8c572 5779 tp->rx_pending = i;
1da177e4 5780 break;
32d8c572 5781 }
1da177e4
LT		 5782 }
5783
cf7a7298
MC		 5784 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5785 goto done;
5786
21f581a5 5787 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5788
0f893dc6 5789 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5790 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5791 struct tg3_rx_buffer_desc *rxd;
5792
79ed5ac7 5793 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5794 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5795 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5796 RXD_FLAG_JUMBO;
5797 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5798 (i << RXD_OPAQUE_INDEX_SHIFT));
5799 }
5800
1da177e4 5801 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 5802 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 5803 i) < 0) {
32d8c572
MC		 5804 printk(KERN_WARNING PFX
5805 "%s: Using a smaller RX jumbo ring, "
5806 "only %d out of %d buffers were "
5807 "allocated successfully.\n",
5808 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5809 if (i == 0)
5810 goto initfail;
32d8c572 5811 tp->rx_jumbo_pending = i;
1da177e4 5812 break;
32d8c572 5813 }
1da177e4
LT		 5814 }
5815 }
cf7a7298
MC		 5816
5817done:
32d8c572 5818 return 0;
cf7a7298
MC		 5819
5820initfail:
21f581a5 5821 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5822 return -ENOMEM;
1da177e4
LT		 5823}
5824
21f581a5
MC		 5825static void tg3_rx_prodring_fini(struct tg3 *tp,
5826 struct tg3_rx_prodring_set *tpr)
1da177e4 5827{
21f581a5
MC		 5828 kfree(tpr->rx_std_buffers);
5829 tpr->rx_std_buffers = NULL;
5830 kfree(tpr->rx_jmb_buffers);
5831 tpr->rx_jmb_buffers = NULL;
5832 if (tpr->rx_std) {
1da177e4 5833 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5834 tpr->rx_std, tpr->rx_std_mapping);
5835 tpr->rx_std = NULL;
1da177e4 5836 }
21f581a5 5837 if (tpr->rx_jmb) {
1da177e4 5838 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5839 tpr->rx_jmb, tpr->rx_jmb_mapping);
5840 tpr->rx_jmb = NULL;
1da177e4 5841 }
cf7a7298
MC		 5842}
5843
21f581a5
MC		 5844static int tg3_rx_prodring_init(struct tg3 *tp,
5845 struct tg3_rx_prodring_set *tpr)
cf7a7298 5846{
21f581a5
MC		 5847 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5848 TG3_RX_RING_SIZE, GFP_KERNEL);
5849 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5850 return -ENOMEM;
5851
21f581a5
MC		 5852 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5853 &tpr->rx_std_mapping);
5854 if (!tpr->rx_std)
cf7a7298
MC		 5855 goto err_out;
5856
5857 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5858 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5859 TG3_RX_JUMBO_RING_SIZE,
5860 GFP_KERNEL);
5861 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5862 goto err_out;
5863
21f581a5
MC		 5864 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5865 TG3_RX_JUMBO_RING_BYTES,
5866 &tpr->rx_jmb_mapping);
5867 if (!tpr->rx_jmb)
cf7a7298
MC		 5868 goto err_out;
5869 }
5870
5871 return 0;
5872
5873err_out:
21f581a5 5874 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5875 return -ENOMEM;
5876}
5877
5878/* Free up pending packets in all rx/tx rings.
5879 *
5880 * The chip has been shut down and the driver detached from
5881 * the networking, so no interrupts or new tx packets will
5882 * end up in the driver. tp->{tx,}lock is not held and we are not
5883 * in an interrupt context and thus may sleep.
5884 */
5885static void tg3_free_rings(struct tg3 *tp)
5886{
f77a6a8e 5887 int i, j;
cf7a7298 5888
f77a6a8e
MC		 5889 for (j = 0; j < tp->irq_cnt; j++) {
5890 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5891
0c1d0e2b
MC		 5892 if (!tnapi->tx_buffers)
5893 continue;
5894
f77a6a8e
MC		 5895 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5896 struct tx_ring_info *txp;
5897 struct sk_buff *skb;
cf7a7298 5898
f77a6a8e
MC		 5899 txp = &tnapi->tx_buffers[i];
5900 skb = txp->skb;
cf7a7298 5901
f77a6a8e
MC		 5902 if (skb == NULL) {
5903 i++;
5904 continue;
5905 }
cf7a7298 5906
f77a6a8e 5907 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5908
f77a6a8e 5909 txp->skb = NULL;
cf7a7298 5910
f77a6a8e
MC		 5911 i += skb_shinfo(skb)->nr_frags + 1;
5912
5913 dev_kfree_skb_any(skb);
5914 }
cf7a7298
MC		 5915 }
5916
21f581a5 5917 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5918}
5919
5920/* Initialize tx/rx rings for packet processing.
5921 *
5922 * The chip has been shut down and the driver detached from
5923 * the networking, so no interrupts or new tx packets will
5924 * end up in the driver. tp->{tx,}lock are held and thus
5925 * we may not sleep.
5926 */
5927static int tg3_init_rings(struct tg3 *tp)
5928{
f77a6a8e 5929 int i;
72334482 5930
cf7a7298
MC		 5931 /* Free up all the SKBs. */
5932 tg3_free_rings(tp);
5933
f77a6a8e
MC		 5934 for (i = 0; i < tp->irq_cnt; i++) {
5935 struct tg3_napi *tnapi = &tp->napi[i];
5936
5937 tnapi->last_tag = 0;
5938 tnapi->last_irq_tag = 0;
5939 tnapi->hw_status->status = 0;
5940 tnapi->hw_status->status_tag = 0;
5941 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5942
f77a6a8e
MC		 5943 tnapi->tx_prod = 0;
5944 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5945 if (tnapi->tx_ring)
5946 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5947
5948 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5949 if (tnapi->rx_rcb)
5950 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5951 }
72334482 5952
21f581a5 5953 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5954}
5955
5956/*
5957 * Must not be invoked with interrupt sources disabled and
5958 * the hardware shutdown down.
5959 */
5960static void tg3_free_consistent(struct tg3 *tp)
5961{
f77a6a8e 5962 int i;
898a56f8 5963
f77a6a8e
MC		 5964 for (i = 0; i < tp->irq_cnt; i++) {
5965 struct tg3_napi *tnapi = &tp->napi[i];
5966
5967 if (tnapi->tx_ring) {
5968 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5969 tnapi->tx_ring, tnapi->tx_desc_mapping);
5970 tnapi->tx_ring = NULL;
5971 }
5972
5973 kfree(tnapi->tx_buffers);
5974 tnapi->tx_buffers = NULL;
5975
5976 if (tnapi->rx_rcb) {
5977 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5978 tnapi->rx_rcb,
5979 tnapi->rx_rcb_mapping);
5980 tnapi->rx_rcb = NULL;
5981 }
5982
5983 if (tnapi->hw_status) {
5984 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5985 tnapi->hw_status,
5986 tnapi->status_mapping);
5987 tnapi->hw_status = NULL;
5988 }
1da177e4 5989 }
f77a6a8e 5990
1da177e4
LT		 5991 if (tp->hw_stats) {
5992 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5993 tp->hw_stats, tp->stats_mapping);
5994 tp->hw_stats = NULL;
5995 }
f77a6a8e 5996
21f581a5 5997 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5998}
5999
6000/*
6001 * Must not be invoked with interrupt sources disabled and
6002 * the hardware shutdown down. Can sleep.
6003 */
6004static int tg3_alloc_consistent(struct tg3 *tp)
6005{
f77a6a8e 6006 int i;
898a56f8 6007
21f581a5 6008 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 6009 return -ENOMEM;
6010
f77a6a8e
MC		 6011 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6012 sizeof(struct tg3_hw_stats),
6013 &tp->stats_mapping);
6014 if (!tp->hw_stats)
1da177e4
LT		 6015 goto err_out;
6016
f77a6a8e 6017 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6018
f77a6a8e
MC		 6019 for (i = 0; i < tp->irq_cnt; i++) {
6020 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6021 struct tg3_hw_status *sblk;
1da177e4 6022
f77a6a8e
MC		 6023 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6024 TG3_HW_STATUS_SIZE,
6025 &tnapi->status_mapping);
6026 if (!tnapi->hw_status)
6027 goto err_out;
898a56f8 6028
f77a6a8e 6029 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6030 sblk = tnapi->hw_status;
6031
6032 /*
6033 * When RSS is enabled, the status block format changes
6034 * slightly. The "rx_jumbo_consumer", "reserved",
6035 * and "rx_mini_consumer" members get mapped to the
6036 * other three rx return ring producer indexes.
6037 */
6038 switch (i) {
6039 default:
6040 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6041 break;
6042 case 2:
6043 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6044 break;
6045 case 3:
6046 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6047 break;
6048 case 4:
6049 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6050 break;
6051 }
72334482 6052
0c1d0e2b
MC		 6053 /*
6054 * If multivector RSS is enabled, vector 0 does not handle
6055 * rx or tx interrupts. Don't allocate any resources for it.
6056 */
6057 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6058 continue;
6059
f77a6a8e
MC		 6060 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6061 TG3_RX_RCB_RING_BYTES(tp),
6062 &tnapi->rx_rcb_mapping);
6063 if (!tnapi->rx_rcb)
6064 goto err_out;
72334482 6065
f77a6a8e 6066 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6067
f77a6a8e
MC		 6068 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6069 TG3_TX_RING_SIZE, GFP_KERNEL);
6070 if (!tnapi->tx_buffers)
6071 goto err_out;
6072
6073 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6074 TG3_TX_RING_BYTES,
6075 &tnapi->tx_desc_mapping);
6076 if (!tnapi->tx_ring)
6077 goto err_out;
6078 }
1da177e4
LT		 6079
6080 return 0;
6081
6082err_out:
6083 tg3_free_consistent(tp);
6084 return -ENOMEM;
6085}
6086
6087#define MAX_WAIT_CNT 1000
6088
6089/* To stop a block, clear the enable bit and poll till it
6090 * clears. tp->lock is held.
6091 */
b3b7d6be 6092static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6093{
6094 unsigned int i;
6095 u32 val;
6096
6097 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6098 switch (ofs) {
6099 case RCVLSC_MODE:
6100 case DMAC_MODE:
6101 case MBFREE_MODE:
6102 case BUFMGR_MODE:
6103 case MEMARB_MODE:
6104 /* We can't enable/disable these bits of the
6105 * 5705/5750, just say success.
6106 */
6107 return 0;
6108
6109 default:
6110 break;
855e1111 6111 }
1da177e4
LT		 6112 }
6113
6114 val = tr32(ofs);
6115 val &= ~enable_bit;
6116 tw32_f(ofs, val);
6117
6118 for (i = 0; i < MAX_WAIT_CNT; i++) {
6119 udelay(100);
6120 val = tr32(ofs);
6121 if ((val & enable_bit) == 0)
6122 break;
6123 }
6124
b3b7d6be 6125 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6126 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6127 "ofs=%lx enable_bit=%x\n",
6128 ofs, enable_bit);
6129 return -ENODEV;
6130 }
6131
6132 return 0;
6133}
6134
6135/* tp->lock is held. */
b3b7d6be 6136static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6137{
6138 int i, err;
6139
6140 tg3_disable_ints(tp);
6141
6142 tp->rx_mode &= ~RX_MODE_ENABLE;
6143 tw32_f(MAC_RX_MODE, tp->rx_mode);
6144 udelay(10);
6145
b3b7d6be
DM		 6146 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6147 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6148 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6149 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6150 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6151 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6152
6153 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6154 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6155 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6156 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6157 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6158 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6159 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6160
6161 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6162 tw32_f(MAC_MODE, tp->mac_mode);
6163 udelay(40);
6164
6165 tp->tx_mode &= ~TX_MODE_ENABLE;
6166 tw32_f(MAC_TX_MODE, tp->tx_mode);
6167
6168 for (i = 0; i < MAX_WAIT_CNT; i++) {
6169 udelay(100);
6170 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6171 break;
6172 }
6173 if (i >= MAX_WAIT_CNT) {
6174 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6175 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6176 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6177 err |= -ENODEV;
1da177e4
LT		 6178 }
6179
e6de8ad1 6180 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6181 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6182 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6183
6184 tw32(FTQ_RESET, 0xffffffff);
6185 tw32(FTQ_RESET, 0x00000000);
6186
b3b7d6be
DM		 6187 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6188 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6189
f77a6a8e
MC		 6190 for (i = 0; i < tp->irq_cnt; i++) {
6191 struct tg3_napi *tnapi = &tp->napi[i];
6192 if (tnapi->hw_status)
6193 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6194 }
1da177e4
LT		 6195 if (tp->hw_stats)
6196 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6197
1da177e4
LT		 6198 return err;
6199}
6200
0d3031d9
MC		 6201static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6202{
6203 int i;
6204 u32 apedata;
6205
6206 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6207 if (apedata != APE_SEG_SIG_MAGIC)
6208 return;
6209
6210 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6211 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6212 return;
6213
6214 /* Wait for up to 1 millisecond for APE to service previous event. */
6215 for (i = 0; i < 10; i++) {
6216 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6217 return;
6218
6219 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6220
6221 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6222 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6223 event | APE_EVENT_STATUS_EVENT_PENDING);
6224
6225 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6226
6227 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6228 break;
6229
6230 udelay(100);
6231 }
6232
6233 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6234 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6235}
6236
6237static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6238{
6239 u32 event;
6240 u32 apedata;
6241
6242 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6243 return;
6244
6245 switch (kind) {
6246 case RESET_KIND_INIT:
6247 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6248 APE_HOST_SEG_SIG_MAGIC);
6249 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6250 APE_HOST_SEG_LEN_MAGIC);
6251 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6252 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6253 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6254 APE_HOST_DRIVER_ID_MAGIC);
6255 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6256 APE_HOST_BEHAV_NO_PHYLOCK);
6257
6258 event = APE_EVENT_STATUS_STATE_START;
6259 break;
6260 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6261 /* With the interface we are currently using,
6262 * APE does not track driver state. Wiping
6263 * out the HOST SEGMENT SIGNATURE forces
6264 * the APE to assume OS absent status.
6265 */
6266 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6267
0d3031d9
MC		 6268 event = APE_EVENT_STATUS_STATE_UNLOAD;
6269 break;
6270 case RESET_KIND_SUSPEND:
6271 event = APE_EVENT_STATUS_STATE_SUSPEND;
6272 break;
6273 default:
6274 return;
6275 }
6276
6277 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6278
6279 tg3_ape_send_event(tp, event);
6280}
6281
1da177e4
LT		 6282/* tp->lock is held. */
6283static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6284{
f49639e6
DM		 6285 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6286 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6287
6288 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6289 switch (kind) {
6290 case RESET_KIND_INIT:
6291 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6292 DRV_STATE_START);
6293 break;
6294
6295 case RESET_KIND_SHUTDOWN:
6296 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6297 DRV_STATE_UNLOAD);
6298 break;
6299
6300 case RESET_KIND_SUSPEND:
6301 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6302 DRV_STATE_SUSPEND);
6303 break;
6304
6305 default:
6306 break;
855e1111 6307 }
1da177e4 6308 }
0d3031d9
MC		 6309
6310 if (kind == RESET_KIND_INIT ||
6311 kind == RESET_KIND_SUSPEND)
6312 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6313}
6314
6315/* tp->lock is held. */
6316static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6317{
6318 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6319 switch (kind) {
6320 case RESET_KIND_INIT:
6321 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6322 DRV_STATE_START_DONE);
6323 break;
6324
6325 case RESET_KIND_SHUTDOWN:
6326 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6327 DRV_STATE_UNLOAD_DONE);
6328 break;
6329
6330 default:
6331 break;
855e1111 6332 }
1da177e4 6333 }
0d3031d9
MC		 6334
6335 if (kind == RESET_KIND_SHUTDOWN)
6336 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6337}
6338
6339/* tp->lock is held. */
6340static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6341{
6342 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6343 switch (kind) {
6344 case RESET_KIND_INIT:
6345 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6346 DRV_STATE_START);
6347 break;
6348
6349 case RESET_KIND_SHUTDOWN:
6350 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6351 DRV_STATE_UNLOAD);
6352 break;
6353
6354 case RESET_KIND_SUSPEND:
6355 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6356 DRV_STATE_SUSPEND);
6357 break;
6358
6359 default:
6360 break;
855e1111 6361 }
1da177e4
LT		 6362 }
6363}
6364
7a6f4369
MC		 6365static int tg3_poll_fw(struct tg3 *tp)
6366{
6367 int i;
6368 u32 val;
6369
b5d3772c 6370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6371 /* Wait up to 20ms for init done. */
6372 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6373 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6374 return 0;
0ccead18 6375 udelay(100);
b5d3772c
MC		 6376 }
6377 return -ENODEV;
6378 }
6379
7a6f4369
MC		 6380 /* Wait for firmware initialization to complete. */
6381 for (i = 0; i < 100000; i++) {
6382 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6383 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6384 break;
6385 udelay(10);
6386 }
6387
6388 /* Chip might not be fitted with firmware. Some Sun onboard
6389 * parts are configured like that. So don't signal the timeout
6390 * of the above loop as an error, but do report the lack of
6391 * running firmware once.
6392 */
6393 if (i >= 100000 &&
6394 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6395 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6396
6397 printk(KERN_INFO PFX "%s: No firmware running.\n",
6398 tp->dev->name);
6399 }
6400
6401 return 0;
6402}
6403
ee6a99b5
MC		 6404/* Save PCI command register before chip reset */
6405static void tg3_save_pci_state(struct tg3 *tp)
6406{
8a6eac90 6407 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6408}
6409
6410/* Restore PCI state after chip reset */
6411static void tg3_restore_pci_state(struct tg3 *tp)
6412{
6413 u32 val;
6414
6415 /* Re-enable indirect register accesses. */
6416 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6417 tp->misc_host_ctrl);
6418
6419 /* Set MAX PCI retry to zero. */
6420 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6421 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6422 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6423 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6424 /* Allow reads and writes to the APE register and memory space. */
6425 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6426 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6427 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6428 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6429
8a6eac90 6430 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6431
fcb389df
MC		 6432 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6433 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6434 pcie_set_readrq(tp->pdev, 4096);
6435 else {
6436 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6437 tp->pci_cacheline_sz);
6438 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6439 tp->pci_lat_timer);
6440 }
114342f2 6441 }
5f5c51e3 6442
ee6a99b5 6443 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6444 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6445 u16 pcix_cmd;
6446
6447 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6448 &pcix_cmd);
6449 pcix_cmd &= ~PCI_X_CMD_ERO;
6450 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6451 pcix_cmd);
6452 }
ee6a99b5
MC		 6453
6454 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6455
6456 /* Chip reset on 5780 will reset MSI enable bit,
6457 * so need to restore it.
6458 */
6459 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6460 u16 ctrl;
6461
6462 pci_read_config_word(tp->pdev,
6463 tp->msi_cap + PCI_MSI_FLAGS,
6464 &ctrl);
6465 pci_write_config_word(tp->pdev,
6466 tp->msi_cap + PCI_MSI_FLAGS,
6467 ctrl | PCI_MSI_FLAGS_ENABLE);
6468 val = tr32(MSGINT_MODE);
6469 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6470 }
6471 }
6472}
6473
1da177e4
LT		 6474static void tg3_stop_fw(struct tg3 *);
6475
6476/* tp->lock is held. */
6477static int tg3_chip_reset(struct tg3 *tp)
6478{
6479 u32 val;
1ee582d8 6480 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6481 int i, err;
1da177e4 6482
f49639e6
DM		 6483 tg3_nvram_lock(tp);
6484
77b483f1
MC		 6485 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6486
f49639e6
DM		 6487 /* No matching tg3_nvram_unlock() after this because
6488 * chip reset below will undo the nvram lock.
6489 */
6490 tp->nvram_lock_cnt = 0;
1da177e4 6491
ee6a99b5
MC		 6492 /* GRC_MISC_CFG core clock reset will clear the memory
6493 * enable bit in PCI register 4 and the MSI enable bit
6494 * on some chips, so we save relevant registers here.
6495 */
6496 tg3_save_pci_state(tp);
6497
d9ab5ad1 6498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6499 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6500 tw32(GRC_FASTBOOT_PC, 0);
6501
1da177e4
LT		 6502 /*
6503 * We must avoid the readl() that normally takes place.
6504 * It locks machines, causes machine checks, and other
6505 * fun things. So, temporarily disable the 5701
6506 * hardware workaround, while we do the reset.
6507 */
1ee582d8
MC		 6508 write_op = tp->write32;
6509 if (write_op == tg3_write_flush_reg32)
6510 tp->write32 = tg3_write32;
1da177e4 6511
d18edcb2
MC		 6512 /* Prevent the irq handler from reading or writing PCI registers
6513 * during chip reset when the memory enable bit in the PCI command
6514 * register may be cleared. The chip does not generate interrupt
6515 * at this time, but the irq handler may still be called due to irq
6516 * sharing or irqpoll.
6517 */
6518 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6519 for (i = 0; i < tp->irq_cnt; i++) {
6520 struct tg3_napi *tnapi = &tp->napi[i];
6521 if (tnapi->hw_status) {
6522 tnapi->hw_status->status = 0;
6523 tnapi->hw_status->status_tag = 0;
6524 }
6525 tnapi->last_tag = 0;
6526 tnapi->last_irq_tag = 0;
b8fa2f3a 6527 }
d18edcb2 6528 smp_mb();
4f125f42
MC		 6529
6530 for (i = 0; i < tp->irq_cnt; i++)
6531 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6532
255ca311
MC		 6533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6534 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6535 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6536 }
6537
1da177e4
LT		 6538 /* do the reset */
6539 val = GRC_MISC_CFG_CORECLK_RESET;
6540
6541 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6542 if (tr32(0x7e2c) == 0x60) {
6543 tw32(0x7e2c, 0x20);
6544 }
6545 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6546 tw32(GRC_MISC_CFG, (1 << 29));
6547 val |= (1 << 29);
6548 }
6549 }
6550
b5d3772c
MC		 6551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6552 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6553 tw32(GRC_VCPU_EXT_CTRL,
6554 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6555 }
6556
1da177e4
LT		 6557 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6558 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6559 tw32(GRC_MISC_CFG, val);
6560
1ee582d8
MC		 6561 /* restore 5701 hardware bug workaround write method */
6562 tp->write32 = write_op;
1da177e4
LT		 6563
6564 /* Unfortunately, we have to delay before the PCI read back.
6565 * Some 575X chips even will not respond to a PCI cfg access
6566 * when the reset command is given to the chip.
6567 *
6568 * How do these hardware designers expect things to work
6569 * properly if the PCI write is posted for a long period
6570 * of time? It is always necessary to have some method by
6571 * which a register read back can occur to push the write
6572 * out which does the reset.
6573 *
6574 * For most tg3 variants the trick below was working.
6575 * Ho hum...
6576 */
6577 udelay(120);
6578
6579 /* Flush PCI posted writes. The normal MMIO registers
6580 * are inaccessible at this time so this is the only
6581 * way to make this reliably (actually, this is no longer
6582 * the case, see above). I tried to use indirect
6583 * register read/write but this upset some 5701 variants.
6584 */
6585 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6586
6587 udelay(120);
6588
5e7dfd0f 6589 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6590 u16 val16;
6591
1da177e4
LT		 6592 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6593 int i;
6594 u32 cfg_val;
6595
6596 /* Wait for link training to complete. */
6597 for (i = 0; i < 5000; i++)
6598 udelay(100);
6599
6600 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6601 pci_write_config_dword(tp->pdev, 0xc4,
6602 cfg_val | (1 << 15));
6603 }
5e7dfd0f 6604
e7126997
MC		 6605 /* Clear the "no snoop" and "relaxed ordering" bits. */
6606 pci_read_config_word(tp->pdev,
6607 tp->pcie_cap + PCI_EXP_DEVCTL,
6608 &val16);
6609 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6610 PCI_EXP_DEVCTL_NOSNOOP_EN);
6611 /*
6612 * Older PCIe devices only support the 128 byte
6613 * MPS setting. Enforce the restriction.
5e7dfd0f 6614 */
e7126997
MC		 6615 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6616 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6617 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6618 pci_write_config_word(tp->pdev,
6619 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6620 val16);
5e7dfd0f
MC		 6621
6622 pcie_set_readrq(tp->pdev, 4096);
6623
6624 /* Clear error status */
6625 pci_write_config_word(tp->pdev,
6626 tp->pcie_cap + PCI_EXP_DEVSTA,
6627 PCI_EXP_DEVSTA_CED |
6628 PCI_EXP_DEVSTA_NFED |
6629 PCI_EXP_DEVSTA_FED |
6630 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6631 }
6632
ee6a99b5 6633 tg3_restore_pci_state(tp);
1da177e4 6634
d18edcb2
MC		 6635 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6636
ee6a99b5
MC		 6637 val = 0;
6638 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6639 val = tr32(MEMARB_MODE);
ee6a99b5 6640 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6641
6642 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6643 tg3_stop_fw(tp);
6644 tw32(0x5000, 0x400);
6645 }
6646
6647 tw32(GRC_MODE, tp->grc_mode);
6648
6649 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6650 val = tr32(0xc4);
1da177e4
LT		 6651
6652 tw32(0xc4, val | (1 << 15));
6653 }
6654
6655 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6657 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6658 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6659 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6660 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6661 }
6662
6663 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6664 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6665 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6666 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6667 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6668 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6669 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6670 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6671 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6672 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6673 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6674 } else
6675 tw32_f(MAC_MODE, 0);
6676 udelay(40);
6677
77b483f1
MC		 6678 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6679
7a6f4369
MC		 6680 err = tg3_poll_fw(tp);
6681 if (err)
6682 return err;
1da177e4 6683
0a9140cf
MC		 6684 tg3_mdio_start(tp);
6685
52cdf852
MC		 6686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6687 u8 phy_addr;
6688
6689 phy_addr = tp->phy_addr;
6690 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6691
6692 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6693 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6694 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6695 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6696 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6697 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6698 udelay(10);
6699
6700 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6701 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6702 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6703 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6704 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6705 udelay(10);
6706
6707 tp->phy_addr = phy_addr;
6708 }
6709
1da177e4 6710 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6711 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6712 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6713 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6714 val = tr32(0x7c00);
1da177e4
LT		 6715
6716 tw32(0x7c00, val | (1 << 25));
6717 }
6718
6719 /* Reprobe ASF enable state. */
6720 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6721 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6722 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6723 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6724 u32 nic_cfg;
6725
6726 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6727 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6728 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6729 tp->last_event_jiffies = jiffies;
cbf46853 6730 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6731 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6732 }
6733 }
6734
6735 return 0;
6736}
6737
6738/* tp->lock is held. */
6739static void tg3_stop_fw(struct tg3 *tp)
6740{
0d3031d9
MC		 6741 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6742 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6743 /* Wait for RX cpu to ACK the previous event. */
6744 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6745
6746 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6747
6748 tg3_generate_fw_event(tp);
1da177e4 6749
7c5026aa
MC		 6750 /* Wait for RX cpu to ACK this event. */
6751 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6752 }
6753}
6754
6755/* tp->lock is held. */
944d980e 6756static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6757{
6758 int err;
6759
6760 tg3_stop_fw(tp);
6761
944d980e 6762 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6763
b3b7d6be 6764 tg3_abort_hw(tp, silent);
1da177e4
LT		 6765 err = tg3_chip_reset(tp);
6766
daba2a63
MC		 6767 __tg3_set_mac_addr(tp, 0);
6768
944d980e
MC		 6769 tg3_write_sig_legacy(tp, kind);
6770 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6771
6772 if (err)
6773 return err;
6774
6775 return 0;
6776}
6777
1da177e4
LT		 6778#define RX_CPU_SCRATCH_BASE 0x30000
6779#define RX_CPU_SCRATCH_SIZE 0x04000
6780#define TX_CPU_SCRATCH_BASE 0x34000
6781#define TX_CPU_SCRATCH_SIZE 0x04000
6782
6783/* tp->lock is held. */
6784static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6785{
6786 int i;
6787
5d9428de
ES		 6788 BUG_ON(offset == TX_CPU_BASE &&
6789 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6790
b5d3772c
MC		 6791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6792 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6793
6794 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6795 return 0;
6796 }
1da177e4
LT		 6797 if (offset == RX_CPU_BASE) {
6798 for (i = 0; i < 10000; i++) {
6799 tw32(offset + CPU_STATE, 0xffffffff);
6800 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6801 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6802 break;
6803 }
6804
6805 tw32(offset + CPU_STATE, 0xffffffff);
6806 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6807 udelay(10);
6808 } else {
6809 for (i = 0; i < 10000; i++) {
6810 tw32(offset + CPU_STATE, 0xffffffff);
6811 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6812 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6813 break;
6814 }
6815 }
6816
6817 if (i >= 10000) {
6818 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6819 "and %s CPU\n",
6820 tp->dev->name,
6821 (offset == RX_CPU_BASE ? "RX" : "TX"));
6822 return -ENODEV;
6823 }
ec41c7df
MC		 6824
6825 /* Clear firmware's nvram arbitration. */
6826 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6827 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6828 return 0;
6829}
6830
6831struct fw_info {
077f849d
JSR		 6832 unsigned int fw_base;
6833 unsigned int fw_len;
6834 const __be32 *fw_data;
1da177e4
LT		 6835};
6836
6837/* tp->lock is held. */
6838static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6839 int cpu_scratch_size, struct fw_info *info)
6840{
ec41c7df 6841 int err, lock_err, i;
1da177e4
LT		 6842 void (*write_op)(struct tg3 *, u32, u32);
6843
6844 if (cpu_base == TX_CPU_BASE &&
6845 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6846 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6847 "TX cpu firmware on %s which is 5705.\n",
6848 tp->dev->name);
6849 return -EINVAL;
6850 }
6851
6852 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6853 write_op = tg3_write_mem;
6854 else
6855 write_op = tg3_write_indirect_reg32;
6856
1b628151
MC		 6857 /* It is possible that bootcode is still loading at this point.
6858 * Get the nvram lock first before halting the cpu.
6859 */
ec41c7df 6860 lock_err = tg3_nvram_lock(tp);
1da177e4 6861 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6862 if (!lock_err)
6863 tg3_nvram_unlock(tp);
1da177e4
LT		 6864 if (err)
6865 goto out;
6866
6867 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6868 write_op(tp, cpu_scratch_base + i, 0);
6869 tw32(cpu_base + CPU_STATE, 0xffffffff);
6870 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6871 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6872 write_op(tp, (cpu_scratch_base +
077f849d 6873 (info->fw_base & 0xffff) +
1da177e4 6874 (i * sizeof(u32))),
077f849d 6875 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6876
6877 err = 0;
6878
6879out:
1da177e4
LT		 6880 return err;
6881}
6882
6883/* tp->lock is held. */
6884static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6885{
6886 struct fw_info info;
077f849d 6887 const __be32 *fw_data;
1da177e4
LT		 6888 int err, i;
6889
077f849d
JSR		 6890 fw_data = (void *)tp->fw->data;
6891
6892 /* Firmware blob starts with version numbers, followed by
6893 start address and length. We are setting complete length.
6894 length = end_address_of_bss - start_address_of_text.
6895 Remainder is the blob to be loaded contiguously
6896 from start address. */
6897
6898 info.fw_base = be32_to_cpu(fw_data[1]);
6899 info.fw_len = tp->fw->size - 12;
6900 info.fw_data = &fw_data[3];
1da177e4
LT		 6901
6902 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6903 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6904 &info);
6905 if (err)
6906 return err;
6907
6908 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6909 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6910 &info);
6911 if (err)
6912 return err;
6913
6914 /* Now startup only the RX cpu. */
6915 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6916 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6917
6918 for (i = 0; i < 5; i++) {
077f849d 6919 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6920 break;
6921 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6922 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6923 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6924 udelay(1000);
6925 }
6926 if (i >= 5) {
6927 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6928 "to set RX CPU PC, is %08x should be %08x\n",
6929 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6930 info.fw_base);
1da177e4
LT		 6931 return -ENODEV;
6932 }
6933 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6934 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6935
6936 return 0;
6937}
6938
1da177e4 6939/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6940
6941/* tp->lock is held. */
6942static int tg3_load_tso_firmware(struct tg3 *tp)
6943{
6944 struct fw_info info;
077f849d 6945 const __be32 *fw_data;
1da177e4
LT		 6946 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6947 int err, i;
6948
6949 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6950 return 0;
6951
077f849d
JSR		 6952 fw_data = (void *)tp->fw->data;
6953
6954 /* Firmware blob starts with version numbers, followed by
6955 start address and length. We are setting complete length.
6956 length = end_address_of_bss - start_address_of_text.
6957 Remainder is the blob to be loaded contiguously
6958 from start address. */
6959
6960 info.fw_base = be32_to_cpu(fw_data[1]);
6961 cpu_scratch_size = tp->fw_len;
6962 info.fw_len = tp->fw->size - 12;
6963 info.fw_data = &fw_data[3];
6964
1da177e4 6965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6966 cpu_base = RX_CPU_BASE;
6967 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6968 } else {
1da177e4
LT		 6969 cpu_base = TX_CPU_BASE;
6970 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6971 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6972 }
6973
6974 err = tg3_load_firmware_cpu(tp, cpu_base,
6975 cpu_scratch_base, cpu_scratch_size,
6976 &info);
6977 if (err)
6978 return err;
6979
6980 /* Now startup the cpu. */
6981 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6982 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6983
6984 for (i = 0; i < 5; i++) {
077f849d 6985 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6986 break;
6987 tw32(cpu_base + CPU_STATE, 0xffffffff);
6988 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6989 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6990 udelay(1000);
6991 }
6992 if (i >= 5) {
6993 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6994 "to set CPU PC, is %08x should be %08x\n",
6995 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6996 info.fw_base);
1da177e4
LT		 6997 return -ENODEV;
6998 }
6999 tw32(cpu_base + CPU_STATE, 0xffffffff);
7000 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7001 return 0;
7002}
7003
1da177e4 7004
1da177e4
LT		 7005static int tg3_set_mac_addr(struct net_device *dev, void *p)
7006{
7007 struct tg3 *tp = netdev_priv(dev);
7008 struct sockaddr *addr = p;
986e0aeb 7009 int err = 0, skip_mac_1 = 0;
1da177e4 7010
f9804ddb
MC		 7011 if (!is_valid_ether_addr(addr->sa_data))
7012 return -EINVAL;
7013
1da177e4
LT		 7014 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7015
e75f7c90
MC		 7016 if (!netif_running(dev))
7017 return 0;
7018
58712ef9 7019 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7020 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7021
986e0aeb
MC		 7022 addr0_high = tr32(MAC_ADDR_0_HIGH);
7023 addr0_low = tr32(MAC_ADDR_0_LOW);
7024 addr1_high = tr32(MAC_ADDR_1_HIGH);
7025 addr1_low = tr32(MAC_ADDR_1_LOW);
7026
7027 /* Skip MAC addr 1 if ASF is using it. */
7028 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7029 !(addr1_high == 0 && addr1_low == 0))
7030 skip_mac_1 = 1;
58712ef9 7031 }
986e0aeb
MC		 7032 spin_lock_bh(&tp->lock);
7033 __tg3_set_mac_addr(tp, skip_mac_1);
7034 spin_unlock_bh(&tp->lock);
1da177e4 7035
b9ec6c1b 7036 return err;
1da177e4
LT		 7037}
7038
7039/* tp->lock is held. */
7040static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7041 dma_addr_t mapping, u32 maxlen_flags,
7042 u32 nic_addr)
7043{
7044 tg3_write_mem(tp,
7045 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7046 ((u64) mapping >> 32));
7047 tg3_write_mem(tp,
7048 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7049 ((u64) mapping & 0xffffffff));
7050 tg3_write_mem(tp,
7051 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7052 maxlen_flags);
7053
7054 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7055 tg3_write_mem(tp,
7056 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7057 nic_addr);
7058}
7059
7060static void __tg3_set_rx_mode(struct net_device *);
d244c892 7061static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7062{
b6080e12
MC		 7063 int i;
7064
7065 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7066 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7067 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7068 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7069
7070 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7071 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7072 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7073 } else {
7074 tw32(HOSTCC_TXCOL_TICKS, 0);
7075 tw32(HOSTCC_TXMAX_FRAMES, 0);
7076 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7077
7078 tw32(HOSTCC_RXCOL_TICKS, 0);
7079 tw32(HOSTCC_RXMAX_FRAMES, 0);
7080 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7081 }
b6080e12 7082
15f9850d
DM		 7083 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7084 u32 val = ec->stats_block_coalesce_usecs;
7085
b6080e12
MC		 7086 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7087 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7088
15f9850d
DM		 7089 if (!netif_carrier_ok(tp->dev))
7090 val = 0;
7091
7092 tw32(HOSTCC_STAT_COAL_TICKS, val);
7093 }
b6080e12
MC		 7094
7095 for (i = 0; i < tp->irq_cnt - 1; i++) {
7096 u32 reg;
7097
7098 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7099 tw32(reg, ec->rx_coalesce_usecs);
7100 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7101 tw32(reg, ec->tx_coalesce_usecs);
7102 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7103 tw32(reg, ec->rx_max_coalesced_frames);
7104 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7105 tw32(reg, ec->tx_max_coalesced_frames);
7106 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7107 tw32(reg, ec->rx_max_coalesced_frames_irq);
7108 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7109 tw32(reg, ec->tx_max_coalesced_frames_irq);
7110 }
7111
7112 for (; i < tp->irq_max - 1; i++) {
7113 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7114 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7115 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7116 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7117 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7118 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7119 }
15f9850d 7120}
1da177e4 7121
2d31ecaf
MC		 7122/* tp->lock is held. */
7123static void tg3_rings_reset(struct tg3 *tp)
7124{
7125 int i;
f77a6a8e 7126 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7127 struct tg3_napi *tnapi = &tp->napi[0];
7128
7129 /* Disable all transmit rings but the first. */
7130 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7131 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7132 else
7133 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7134
7135 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7136 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7137 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7138 BDINFO_FLAGS_DISABLED);
7139
7140
7141 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7143 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7144 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7145 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7146 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7147 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7148 else
7149 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7150
7151 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7152 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7153 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7154 BDINFO_FLAGS_DISABLED);
7155
7156 /* Disable interrupts */
7157 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7158
7159 /* Zero mailbox registers. */
f77a6a8e
MC		 7160 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7161 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7162 tp->napi[i].tx_prod = 0;
7163 tp->napi[i].tx_cons = 0;
7164 tw32_mailbox(tp->napi[i].prodmbox, 0);
7165 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7166 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7167 }
7168 } else {
7169 tp->napi[0].tx_prod = 0;
7170 tp->napi[0].tx_cons = 0;
7171 tw32_mailbox(tp->napi[0].prodmbox, 0);
7172 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7173 }
2d31ecaf
MC		 7174
7175 /* Make sure the NIC-based send BD rings are disabled. */
7176 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7177 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7178 for (i = 0; i < 16; i++)
7179 tw32_tx_mbox(mbox + i * 8, 0);
7180 }
7181
7182 txrcb = NIC_SRAM_SEND_RCB;
7183 rxrcb = NIC_SRAM_RCV_RET_RCB;
7184
7185 /* Clear status block in ram. */
7186 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7187
7188 /* Set status block DMA address */
7189 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7190 ((u64) tnapi->status_mapping >> 32));
7191 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7192 ((u64) tnapi->status_mapping & 0xffffffff));
7193
f77a6a8e
MC		 7194 if (tnapi->tx_ring) {
7195 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7196 (TG3_TX_RING_SIZE <<
7197 BDINFO_FLAGS_MAXLEN_SHIFT),
7198 NIC_SRAM_TX_BUFFER_DESC);
7199 txrcb += TG3_BDINFO_SIZE;
7200 }
7201
7202 if (tnapi->rx_rcb) {
7203 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7204 (TG3_RX_RCB_RING_SIZE(tp) <<
7205 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7206 rxrcb += TG3_BDINFO_SIZE;
7207 }
7208
7209 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7210
f77a6a8e
MC		 7211 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7212 u64 mapping = (u64)tnapi->status_mapping;
7213 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7214 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7215
7216 /* Clear status block in ram. */
7217 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7218
7219 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7220 (TG3_TX_RING_SIZE <<
7221 BDINFO_FLAGS_MAXLEN_SHIFT),
7222 NIC_SRAM_TX_BUFFER_DESC);
7223
7224 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7225 (TG3_RX_RCB_RING_SIZE(tp) <<
7226 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7227
7228 stblk += 8;
7229 txrcb += TG3_BDINFO_SIZE;
7230 rxrcb += TG3_BDINFO_SIZE;
7231 }
2d31ecaf
MC		 7232}
7233
1da177e4 7234/* tp->lock is held. */
8e7a22e3 7235static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7236{
7237 u32 val, rdmac_mode;
7238 int i, err, limit;
21f581a5 7239 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7240
7241 tg3_disable_ints(tp);
7242
7243 tg3_stop_fw(tp);
7244
7245 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7246
7247 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7248 tg3_abort_hw(tp, 1);
1da177e4
LT		 7249 }
7250
dd477003
MC		 7251 if (reset_phy &&
7252 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7253 tg3_phy_reset(tp);
7254
1da177e4
LT		 7255 err = tg3_chip_reset(tp);
7256 if (err)
7257 return err;
7258
7259 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7260
bcb37f6c 7261 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7262 val = tr32(TG3_CPMU_CTRL);
7263 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7264 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7265
7266 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7267 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7268 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7269 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7270
7271 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7272 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7273 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7274 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7275
7276 val = tr32(TG3_CPMU_HST_ACC);
7277 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7278 val |= CPMU_HST_ACC_MACCLK_6_25;
7279 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7280 }
7281
33466d93
MC		 7282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7283 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7284 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7285 PCIE_PWR_MGMT_L1_THRESH_4MS;
7286 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7287
7288 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7289 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7290
7291 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7292
f40386c8
MC		 7293 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7294 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7295 }
7296
1da177e4
LT		 7297 /* This works around an issue with Athlon chipsets on
7298 * B3 tigon3 silicon. This bit has no effect on any
7299 * other revision. But do not set this on PCI Express
795d01c5 7300 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7301 */
795d01c5
MC		 7302 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7303 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7304 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7305 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7306 }
1da177e4
LT		 7307
7308 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7309 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7310 val = tr32(TG3PCI_PCISTATE);
7311 val |= PCISTATE_RETRY_SAME_DMA;
7312 tw32(TG3PCI_PCISTATE, val);
7313 }
7314
0d3031d9
MC		 7315 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7316 /* Allow reads and writes to the
7317 * APE register and memory space.
7318 */
7319 val = tr32(TG3PCI_PCISTATE);
7320 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7321 PCISTATE_ALLOW_APE_SHMEM_WR;
7322 tw32(TG3PCI_PCISTATE, val);
7323 }
7324
1da177e4
LT		 7325 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7326 /* Enable some hw fixes. */
7327 val = tr32(TG3PCI_MSI_DATA);
7328 val |= (1 << 26) | (1 << 28) | (1 << 29);
7329 tw32(TG3PCI_MSI_DATA, val);
7330 }
7331
7332 /* Descriptor ring init may make accesses to the
7333 * NIC SRAM area to setup the TX descriptors, so we
7334 * can only do this after the hardware has been
7335 * successfully reset.
7336 */
32d8c572
MC		 7337 err = tg3_init_rings(tp);
7338 if (err)
7339 return err;
1da177e4 7340
cbf9ca6c
MC		 7341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7342 val = tr32(TG3PCI_DMA_RW_CTRL) &
7343 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7344 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7345 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7346 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7347 /* This value is determined during the probe time DMA
7348 * engine test, tg3_test_dma.
7349 */
7350 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7351 }
1da177e4
LT		 7352
7353 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7354 GRC_MODE_4X_NIC_SEND_RINGS |
7355 GRC_MODE_NO_TX_PHDR_CSUM |
7356 GRC_MODE_NO_RX_PHDR_CSUM);
7357 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7358
7359 /* Pseudo-header checksum is done by hardware logic and not
7360 * the offload processers, so make the chip do the pseudo-
7361 * header checksums on receive. For transmit it is more
7362 * convenient to do the pseudo-header checksum in software
7363 * as Linux does that on transmit for us in all cases.
7364 */
7365 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7366
7367 tw32(GRC_MODE,
7368 tp->grc_mode |
7369 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7370
7371 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7372 val = tr32(GRC_MISC_CFG);
7373 val &= ~0xff;
7374 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7375 tw32(GRC_MISC_CFG, val);
7376
7377 /* Initialize MBUF/DESC pool. */
cbf46853 7378 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7379 /* Do nothing. */
7380 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7381 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7383 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7384 else
7385 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7386 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7387 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7388 }
1da177e4
LT		 7389 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7390 int fw_len;
7391
077f849d 7392 fw_len = tp->fw_len;
1da177e4
LT		 7393 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7394 tw32(BUFMGR_MB_POOL_ADDR,
7395 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7396 tw32(BUFMGR_MB_POOL_SIZE,
7397 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7398 }
1da177e4 7399
0f893dc6 7400 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7401 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7402 tp->bufmgr_config.mbuf_read_dma_low_water);
7403 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7404 tp->bufmgr_config.mbuf_mac_rx_low_water);
7405 tw32(BUFMGR_MB_HIGH_WATER,
7406 tp->bufmgr_config.mbuf_high_water);
7407 } else {
7408 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7409 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7410 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7411 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7412 tw32(BUFMGR_MB_HIGH_WATER,
7413 tp->bufmgr_config.mbuf_high_water_jumbo);
7414 }
7415 tw32(BUFMGR_DMA_LOW_WATER,
7416 tp->bufmgr_config.dma_low_water);
7417 tw32(BUFMGR_DMA_HIGH_WATER,
7418 tp->bufmgr_config.dma_high_water);
7419
7420 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7421 for (i = 0; i < 2000; i++) {
7422 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7423 break;
7424 udelay(10);
7425 }
7426 if (i >= 2000) {
7427 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7428 tp->dev->name);
7429 return -ENODEV;
7430 }
7431
7432 /* Setup replenish threshold. */
f92905de
MC		 7433 val = tp->rx_pending / 8;
7434 if (val == 0)
7435 val = 1;
7436 else if (val > tp->rx_std_max_post)
7437 val = tp->rx_std_max_post;
b5d3772c
MC		 7438 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7439 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7440 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7441
7442 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7443 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7444 }
f92905de
MC		 7445
7446 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7447
7448 /* Initialize TG3_BDINFO's at:
7449 * RCVDBDI_STD_BD: standard eth size rx ring
7450 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7451 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7452 *
7453 * like so:
7454 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7455 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7456 * ring attribute flags
7457 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7458 *
7459 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7460 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7461 *
7462 * The size of each ring is fixed in the firmware, but the location is
7463 * configurable.
7464 */
7465 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7466 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7467 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7468 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7469 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7470 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7471 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7472
fdb72b38
MC		 7473 /* Disable the mini ring */
7474 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7475 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7476 BDINFO_FLAGS_DISABLED);
7477
fdb72b38
MC		 7478 /* Program the jumbo buffer descriptor ring control
7479 * blocks on those devices that have them.
7480 */
8f666b07 7481 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7482 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7483 /* Setup replenish threshold. */
7484 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7485
0f893dc6 7486 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7487 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7488 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7489 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7490 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7491 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7492 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7493 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7494 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7495 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7496 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7497 } else {
7498 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7499 BDINFO_FLAGS_DISABLED);
7500 }
7501
f6eb9b1f
MC		 7502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7503 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7504 (RX_STD_MAX_SIZE << 2);
7505 else
7506 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7507 } else
7508 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7509
7510 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7511
411da640 7512 tpr->rx_std_prod_idx = tp->rx_pending;
1da177e4 7513 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
411da640 7514 tpr->rx_std_prod_idx);
1da177e4 7515
411da640 7516 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7517 tp->rx_jumbo_pending : 0;
1da177e4 7518 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
411da640 7519 tpr->rx_jmb_prod_idx);
1da177e4 7520
f6eb9b1f
MC		 7521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7522 tw32(STD_REPLENISH_LWM, 32);
7523 tw32(JMB_REPLENISH_LWM, 16);
7524 }
7525
2d31ecaf
MC		 7526 tg3_rings_reset(tp);
7527
1da177e4 7528 /* Initialize MAC address and backoff seed. */
986e0aeb 7529 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7530
7531 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7532 tw32(MAC_RX_MTU_SIZE,
7533 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7534
7535 /* The slot time is changed by tg3_setup_phy if we
7536 * run at gigabit with half duplex.
7537 */
7538 tw32(MAC_TX_LENGTHS,
7539 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7540 (6 << TX_LENGTHS_IPG_SHIFT) |
7541 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7542
7543 /* Receive rules. */
7544 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7545 tw32(RCVLPC_CONFIG, 0x0181);
7546
7547 /* Calculate RDMAC_MODE setting early, we need it to determine
7548 * the RCVLPC_STATE_ENABLE mask.
7549 */
7550 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7551 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7552 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7553 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7554 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7555
57e6983c 7556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7559 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7560 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7561 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7562
85e94ced
MC		 7563 /* If statement applies to 5705 and 5750 PCI devices only */
7564 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7565 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7566 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7567 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7569 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7570 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7571 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7572 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7573 }
7574 }
7575
85e94ced
MC		 7576 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7577 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7578
1da177e4 7579 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7580 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7581
e849cdc3
MC		 7582 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7583 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7584 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7585 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7586
7587 /* Receive/send statistics. */
1661394e
MC		 7588 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7589 val = tr32(RCVLPC_STATS_ENABLE);
7590 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7591 tw32(RCVLPC_STATS_ENABLE, val);
7592 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7593 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7594 val = tr32(RCVLPC_STATS_ENABLE);
7595 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7596 tw32(RCVLPC_STATS_ENABLE, val);
7597 } else {
7598 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7599 }
7600 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7601 tw32(SNDDATAI_STATSENAB, 0xffffff);
7602 tw32(SNDDATAI_STATSCTRL,
7603 (SNDDATAI_SCTRL_ENABLE |
7604 SNDDATAI_SCTRL_FASTUPD));
7605
7606 /* Setup host coalescing engine. */
7607 tw32(HOSTCC_MODE, 0);
7608 for (i = 0; i < 2000; i++) {
7609 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7610 break;
7611 udelay(10);
7612 }
7613
d244c892 7614 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7615
1da177e4
LT		 7616 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7617 /* Status/statistics block address. See tg3_timer,
7618 * the tg3_periodic_fetch_stats call there, and
7619 * tg3_get_stats to see how this works for 5705/5750 chips.
7620 */
1da177e4
LT		 7621 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7622 ((u64) tp->stats_mapping >> 32));
7623 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7624 ((u64) tp->stats_mapping & 0xffffffff));
7625 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7626
1da177e4 7627 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7628
7629 /* Clear statistics and status block memory areas */
7630 for (i = NIC_SRAM_STATS_BLK;
7631 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7632 i += sizeof(u32)) {
7633 tg3_write_mem(tp, i, 0);
7634 udelay(40);
7635 }
1da177e4
LT		 7636 }
7637
7638 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7639
7640 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7641 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7642 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7643 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7644
c94e3941
MC		 7645 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7646 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7647 /* reset to prevent losing 1st rx packet intermittently */
7648 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7649 udelay(10);
7650 }
7651
3bda1258
MC		 7652 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7653 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7654 else
7655 tp->mac_mode = 0;
7656 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7657 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7658 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7659 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7660 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7661 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7662 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7663 udelay(40);
7664
314fba34 7665 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7666 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7667 * register to preserve the GPIO settings for LOMs. The GPIOs,
7668 * whether used as inputs or outputs, are set by boot code after
7669 * reset.
7670 */
9d26e213 7671 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7672 u32 gpio_mask;
7673
9d26e213
MC		 7674 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7675 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7676 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7677
7678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7679 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7680 GRC_LCLCTRL_GPIO_OUTPUT3;
7681
af36e6b6
MC		 7682 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7683 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7684
aaf84465 7685 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7686 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7687
7688 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7689 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7690 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7691 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7692 }
1da177e4
LT		 7693 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7694 udelay(100);
7695
baf8a94a
MC		 7696 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7697 val = tr32(MSGINT_MODE);
7698 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7699 tw32(MSGINT_MODE, val);
7700 }
7701
1da177e4
LT		 7702 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7703 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7704 udelay(40);
7705 }
7706
7707 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7708 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7709 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7710 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7711 WDMAC_MODE_LNGREAD_ENAB);
7712
85e94ced
MC		 7713 /* If statement applies to 5705 and 5750 PCI devices only */
7714 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7715 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7717 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7718 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7719 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7720 /* nothing */
7721 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7722 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7723 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7724 val |= WDMAC_MODE_RX_ACCEL;
7725 }
7726 }
7727
d9ab5ad1 7728 /* Enable host coalescing bug fix */
321d32a0 7729 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7730 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7731
788a035e
MC		 7732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7733 val |= WDMAC_MODE_BURST_ALL_DATA;
7734
1da177e4
LT		 7735 tw32_f(WDMAC_MODE, val);
7736 udelay(40);
7737
9974a356
MC		 7738 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7739 u16 pcix_cmd;
7740
7741 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7742 &pcix_cmd);
1da177e4 7743 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7744 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7745 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7746 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7747 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7748 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7749 }
9974a356
MC		 7750 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7751 pcix_cmd);
1da177e4
LT		 7752 }
7753
7754 tw32_f(RDMAC_MODE, rdmac_mode);
7755 udelay(40);
7756
7757 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7758 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7759 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7760
7761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7762 tw32(SNDDATAC_MODE,
7763 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7764 else
7765 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7766
1da177e4
LT		 7767 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7768 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7769 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7770 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7771 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7772 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7773 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7774 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7775 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7776 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7777 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7778
7779 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7780 err = tg3_load_5701_a0_firmware_fix(tp);
7781 if (err)
7782 return err;
7783 }
7784
1da177e4
LT		 7785 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7786 err = tg3_load_tso_firmware(tp);
7787 if (err)
7788 return err;
7789 }
1da177e4
LT		 7790
7791 tp->tx_mode = TX_MODE_ENABLE;
7792 tw32_f(MAC_TX_MODE, tp->tx_mode);
7793 udelay(100);
7794
baf8a94a
MC		 7795 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7796 u32 reg = MAC_RSS_INDIR_TBL_0;
7797 u8 *ent = (u8 *)&val;
7798
7799 /* Setup the indirection table */
7800 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7801 int idx = i % sizeof(val);
7802
7803 ent[idx] = i % (tp->irq_cnt - 1);
7804 if (idx == sizeof(val) - 1) {
7805 tw32(reg, val);
7806 reg += 4;
7807 }
7808 }
7809
7810 /* Setup the "secret" hash key. */
7811 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7812 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7813 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7814 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7815 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7816 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7817 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7818 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7819 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7820 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7821 }
7822
1da177e4 7823 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7824 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7825 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7826
baf8a94a
MC		 7827 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7828 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7829 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7830 RX_MODE_RSS_IPV6_HASH_EN |
7831 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7832 RX_MODE_RSS_IPV4_HASH_EN |
7833 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7834
1da177e4
LT		 7835 tw32_f(MAC_RX_MODE, tp->rx_mode);
7836 udelay(10);
7837
1da177e4
LT		 7838 tw32(MAC_LED_CTRL, tp->led_ctrl);
7839
7840 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7841 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7842 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7843 udelay(10);
7844 }
7845 tw32_f(MAC_RX_MODE, tp->rx_mode);
7846 udelay(10);
7847
7848 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7849 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7850 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7851 /* Set drive transmission level to 1.2V */
7852 /* only if the signal pre-emphasis bit is not set */
7853 val = tr32(MAC_SERDES_CFG);
7854 val &= 0xfffff000;
7855 val |= 0x880;
7856 tw32(MAC_SERDES_CFG, val);
7857 }
7858 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7859 tw32(MAC_SERDES_CFG, 0x616000);
7860 }
7861
7862 /* Prevent chip from dropping frames when flow control
7863 * is enabled.
7864 */
7865 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7866
7867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7868 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7869 /* Use hardware link auto-negotiation */
7870 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7871 }
7872
d4d2c558
MC		 7873 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7874 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7875 u32 tmp;
7876
7877 tmp = tr32(SERDES_RX_CTRL);
7878 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7879 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7880 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7881 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7882 }
7883
dd477003
MC		 7884 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7885 if (tp->link_config.phy_is_low_power) {
7886 tp->link_config.phy_is_low_power = 0;
7887 tp->link_config.speed = tp->link_config.orig_speed;
7888 tp->link_config.duplex = tp->link_config.orig_duplex;
7889 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7890 }
1da177e4 7891
dd477003
MC		 7892 err = tg3_setup_phy(tp, 0);
7893 if (err)
7894 return err;
1da177e4 7895
dd477003 7896 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7897 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7898 u32 tmp;
7899
7900 /* Clear CRC stats. */
7901 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7902 tg3_writephy(tp, MII_TG3_TEST1,
7903 tmp | MII_TG3_TEST1_CRC_EN);
7904 tg3_readphy(tp, 0x14, &tmp);
7905 }
1da177e4
LT		 7906 }
7907 }
7908
7909 __tg3_set_rx_mode(tp->dev);
7910
7911 /* Initialize receive rules. */
7912 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7913 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7914 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7915 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7916
4cf78e4f 7917 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7918 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7919 limit = 8;
7920 else
7921 limit = 16;
7922 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7923 limit -= 4;
7924 switch (limit) {
7925 case 16:
7926 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7927 case 15:
7928 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7929 case 14:
7930 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7931 case 13:
7932 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7933 case 12:
7934 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7935 case 11:
7936 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7937 case 10:
7938 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7939 case 9:
7940 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7941 case 8:
7942 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7943 case 7:
7944 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7945 case 6:
7946 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7947 case 5:
7948 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7949 case 4:
7950 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7951 case 3:
7952 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7953 case 2:
7954 case 1:
7955
7956 default:
7957 break;
855e1111 7958 }
1da177e4 7959
9ce768ea
MC		 7960 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7961 /* Write our heartbeat update interval to APE. */
7962 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7963 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7964
1da177e4
LT		 7965 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7966
1da177e4
LT		 7967 return 0;
7968}
7969
7970/* Called at device open time to get the chip ready for
7971 * packet processing. Invoked with tp->lock held.
7972 */
8e7a22e3 7973static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7974{
1da177e4
LT		 7975 tg3_switch_clocks(tp);
7976
7977 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7978
2f751b67 7979 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7980}
7981
7982#define TG3_STAT_ADD32(PSTAT, REG) \
7983do { u32 __val = tr32(REG); \
7984 (PSTAT)->low += __val; \
7985 if ((PSTAT)->low < __val) \
7986 (PSTAT)->high += 1; \
7987} while (0)
7988
7989static void tg3_periodic_fetch_stats(struct tg3 *tp)
7990{
7991 struct tg3_hw_stats *sp = tp->hw_stats;
7992
7993 if (!netif_carrier_ok(tp->dev))
7994 return;
7995
7996 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7997 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7998 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7999 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8000 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8001 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8002 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8003 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8004 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8005 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8006 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8007 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8008 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8009
8010 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8011 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8012 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8013 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8014 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8015 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8016 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8017 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8018 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8019 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8020 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8021 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8022 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8023 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8024
8025 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8026 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8027 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8028}
8029
8030static void tg3_timer(unsigned long __opaque)
8031{
8032 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8033
f475f163
MC		 8034 if (tp->irq_sync)
8035 goto restart_timer;
8036
f47c11ee 8037 spin_lock(&tp->lock);
1da177e4 8038
fac9b83e
DM		 8039 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8040 /* All of this garbage is because when using non-tagged
8041 * IRQ status the mailbox/status_block protocol the chip
8042 * uses with the cpu is race prone.
8043 */
898a56f8 8044 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8045 tw32(GRC_LOCAL_CTRL,
8046 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8047 } else {
8048 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8049 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8050 }
1da177e4 8051
fac9b83e
DM		 8052 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8053 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8054 spin_unlock(&tp->lock);
fac9b83e
DM		 8055 schedule_work(&tp->reset_task);
8056 return;
8057 }
1da177e4
LT		 8058 }
8059
1da177e4
LT		 8060 /* This part only runs once per second. */
8061 if (!--tp->timer_counter) {
fac9b83e
DM		 8062 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8063 tg3_periodic_fetch_stats(tp);
8064
1da177e4
LT		 8065 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8066 u32 mac_stat;
8067 int phy_event;
8068
8069 mac_stat = tr32(MAC_STATUS);
8070
8071 phy_event = 0;
8072 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8073 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8074 phy_event = 1;
8075 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8076 phy_event = 1;
8077
8078 if (phy_event)
8079 tg3_setup_phy(tp, 0);
8080 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8081 u32 mac_stat = tr32(MAC_STATUS);
8082 int need_setup = 0;
8083
8084 if (netif_carrier_ok(tp->dev) &&
8085 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8086 need_setup = 1;
8087 }
8088 if (! netif_carrier_ok(tp->dev) &&
8089 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8090 MAC_STATUS_SIGNAL_DET))) {
8091 need_setup = 1;
8092 }
8093 if (need_setup) {
3d3ebe74
MC		 8094 if (!tp->serdes_counter) {
8095 tw32_f(MAC_MODE,
8096 (tp->mac_mode &
8097 ~MAC_MODE_PORT_MODE_MASK));
8098 udelay(40);
8099 tw32_f(MAC_MODE, tp->mac_mode);
8100 udelay(40);
8101 }
1da177e4
LT		 8102 tg3_setup_phy(tp, 0);
8103 }
747e8f8b
MC		 8104 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8105 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8106
8107 tp->timer_counter = tp->timer_multiplier;
8108 }
8109
130b8e4d
MC		 8110 /* Heartbeat is only sent once every 2 seconds.
8111 *
8112 * The heartbeat is to tell the ASF firmware that the host
8113 * driver is still alive. In the event that the OS crashes,
8114 * ASF needs to reset the hardware to free up the FIFO space
8115 * that may be filled with rx packets destined for the host.
8116 * If the FIFO is full, ASF will no longer function properly.
8117 *
8118 * Unintended resets have been reported on real time kernels
8119 * where the timer doesn't run on time. Netpoll will also have
8120 * same problem.
8121 *
8122 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8123 * to check the ring condition when the heartbeat is expiring
8124 * before doing the reset. This will prevent most unintended
8125 * resets.
8126 */
1da177e4 8127 if (!--tp->asf_counter) {
bc7959b2
MC		 8128 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8129 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8130 tg3_wait_for_event_ack(tp);
8131
bbadf503 8132 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8133 FWCMD_NICDRV_ALIVE3);
bbadf503 8134 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8135 /* 5 seconds timeout */
bbadf503 8136 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8137
8138 tg3_generate_fw_event(tp);
1da177e4
LT		 8139 }
8140 tp->asf_counter = tp->asf_multiplier;
8141 }
8142
f47c11ee 8143 spin_unlock(&tp->lock);
1da177e4 8144
f475f163 8145restart_timer:
1da177e4
LT		 8146 tp->timer.expires = jiffies + tp->timer_offset;
8147 add_timer(&tp->timer);
8148}
8149
4f125f42 8150static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8151{
7d12e780 8152 irq_handler_t fn;
fcfa0a32 8153 unsigned long flags;
4f125f42
MC		 8154 char *name;
8155 struct tg3_napi *tnapi = &tp->napi[irq_num];
8156
8157 if (tp->irq_cnt == 1)
8158 name = tp->dev->name;
8159 else {
8160 name = &tnapi->irq_lbl[0];
8161 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8162 name[IFNAMSIZ-1] = 0;
8163 }
fcfa0a32 8164
679563f4 8165 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8166 fn = tg3_msi;
8167 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8168 fn = tg3_msi_1shot;
1fb9df5d 8169 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8170 } else {
8171 fn = tg3_interrupt;
8172 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8173 fn = tg3_interrupt_tagged;
1fb9df5d 8174 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8175 }
4f125f42
MC		 8176
8177 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8178}
8179
7938109f
MC		 8180static int tg3_test_interrupt(struct tg3 *tp)
8181{
09943a18 8182 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8183 struct net_device *dev = tp->dev;
b16250e3 8184 int err, i, intr_ok = 0;
f6eb9b1f 8185 u32 val;
7938109f 8186
d4bc3927
MC		 8187 if (!netif_running(dev))
8188 return -ENODEV;
8189
7938109f
MC		 8190 tg3_disable_ints(tp);
8191
4f125f42 8192 free_irq(tnapi->irq_vec, tnapi);
7938109f 8193
f6eb9b1f
MC		 8194 /*
8195 * Turn off MSI one shot mode. Otherwise this test has no
8196 * observable way to know whether the interrupt was delivered.
8197 */
8198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8199 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8200 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8201 tw32(MSGINT_MODE, val);
8202 }
8203
4f125f42 8204 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8205 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8206 if (err)
8207 return err;
8208
898a56f8 8209 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8210 tg3_enable_ints(tp);
8211
8212 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8213 tnapi->coal_now);
7938109f
MC		 8214
8215 for (i = 0; i < 5; i++) {
b16250e3
MC		 8216 u32 int_mbox, misc_host_ctrl;
8217
898a56f8 8218 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8219 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8220
8221 if ((int_mbox != 0) ||
8222 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8223 intr_ok = 1;
7938109f 8224 break;
b16250e3
MC		 8225 }
8226
7938109f
MC		 8227 msleep(10);
8228 }
8229
8230 tg3_disable_ints(tp);
8231
4f125f42 8232 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8233
4f125f42 8234 err = tg3_request_irq(tp, 0);
7938109f
MC		 8235
8236 if (err)
8237 return err;
8238
f6eb9b1f
MC		 8239 if (intr_ok) {
8240 /* Reenable MSI one shot mode. */
8241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8242 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8243 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8244 tw32(MSGINT_MODE, val);
8245 }
7938109f 8246 return 0;
f6eb9b1f 8247 }
7938109f
MC		 8248
8249 return -EIO;
8250}
8251
8252/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8253 * successfully restored
8254 */
8255static int tg3_test_msi(struct tg3 *tp)
8256{
7938109f
MC		 8257 int err;
8258 u16 pci_cmd;
8259
8260 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8261 return 0;
8262
8263 /* Turn off SERR reporting in case MSI terminates with Master
8264 * Abort.
8265 */
8266 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8267 pci_write_config_word(tp->pdev, PCI_COMMAND,
8268 pci_cmd & ~PCI_COMMAND_SERR);
8269
8270 err = tg3_test_interrupt(tp);
8271
8272 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8273
8274 if (!err)
8275 return 0;
8276
8277 /* other failures */
8278 if (err != -EIO)
8279 return err;
8280
8281 /* MSI test failed, go back to INTx mode */
8282 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8283 "switching to INTx mode. Please report this failure to "
8284 "the PCI maintainer and include system chipset information.\n",
8285 tp->dev->name);
8286
4f125f42 8287 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8288
7938109f
MC		 8289 pci_disable_msi(tp->pdev);
8290
8291 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8292
4f125f42 8293 err = tg3_request_irq(tp, 0);
7938109f
MC		 8294 if (err)
8295 return err;
8296
8297 /* Need to reset the chip because the MSI cycle may have terminated
8298 * with Master Abort.
8299 */
f47c11ee 8300 tg3_full_lock(tp, 1);
7938109f 8301
944d980e 8302 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8303 err = tg3_init_hw(tp, 1);
7938109f 8304
f47c11ee 8305 tg3_full_unlock(tp);
7938109f
MC		 8306
8307 if (err)
4f125f42 8308 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8309
8310 return err;
8311}
8312
9e9fd12d
MC		 8313static int tg3_request_firmware(struct tg3 *tp)
8314{
8315 const __be32 *fw_data;
8316
8317 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8318 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8319 tp->dev->name, tp->fw_needed);
8320 return -ENOENT;
8321 }
8322
8323 fw_data = (void *)tp->fw->data;
8324
8325 /* Firmware blob starts with version numbers, followed by
8326 * start address and _full_ length including BSS sections
8327 * (which must be longer than the actual data, of course
8328 */
8329
8330 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8331 if (tp->fw_len < (tp->fw->size - 12)) {
8332 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8333 tp->dev->name, tp->fw_len, tp->fw_needed);
8334 release_firmware(tp->fw);
8335 tp->fw = NULL;
8336 return -EINVAL;
8337 }
8338
8339 /* We no longer need firmware; we have it. */
8340 tp->fw_needed = NULL;
8341 return 0;
8342}
8343
679563f4
MC		 8344static bool tg3_enable_msix(struct tg3 *tp)
8345{
8346 int i, rc, cpus = num_online_cpus();
8347 struct msix_entry msix_ent[tp->irq_max];
8348
8349 if (cpus == 1)
8350 /* Just fallback to the simpler MSI mode. */
8351 return false;
8352
8353 /*
8354 * We want as many rx rings enabled as there are cpus.
8355 * The first MSIX vector only deals with link interrupts, etc,
8356 * so we add one to the number of vectors we are requesting.
8357 */
8358 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8359
8360 for (i = 0; i < tp->irq_max; i++) {
8361 msix_ent[i].entry = i;
8362 msix_ent[i].vector = 0;
8363 }
8364
8365 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8366 if (rc != 0) {
8367 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8368 return false;
8369 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8370 return false;
8371 printk(KERN_NOTICE
8372 "%s: Requested %d MSI-X vectors, received %d\n",
8373 tp->dev->name, tp->irq_cnt, rc);
8374 tp->irq_cnt = rc;
8375 }
8376
baf8a94a
MC		 8377 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8378
679563f4
MC		 8379 for (i = 0; i < tp->irq_max; i++)
8380 tp->napi[i].irq_vec = msix_ent[i].vector;
8381
fe5f5787
MC		 8382 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8383
679563f4
MC		 8384 return true;
8385}
8386
07b0173c
MC		 8387static void tg3_ints_init(struct tg3 *tp)
8388{
679563f4
MC		 8389 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8390 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8391 /* All MSI supporting chips should support tagged
8392 * status. Assert that this is the case.
8393 */
679563f4
MC		 8394 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8395 "Not using MSI.\n", tp->dev->name);
8396 goto defcfg;
07b0173c 8397 }
4f125f42 8398
679563f4
MC		 8399 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8400 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8401 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8402 pci_enable_msi(tp->pdev) == 0)
8403 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8404
8405 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8406 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8407 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8408 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8409 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8410 }
8411defcfg:
8412 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8413 tp->irq_cnt = 1;
8414 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8415 tp->dev->real_num_tx_queues = 1;
679563f4 8416 }
07b0173c
MC		 8417}
8418
8419static void tg3_ints_fini(struct tg3 *tp)
8420{
679563f4
MC		 8421 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8422 pci_disable_msix(tp->pdev);
8423 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8424 pci_disable_msi(tp->pdev);
8425 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8426 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8427}
8428
1da177e4
LT		 8429static int tg3_open(struct net_device *dev)
8430{
8431 struct tg3 *tp = netdev_priv(dev);
4f125f42 8432 int i, err;
1da177e4 8433
9e9fd12d
MC		 8434 if (tp->fw_needed) {
8435 err = tg3_request_firmware(tp);
8436 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8437 if (err)
8438 return err;
8439 } else if (err) {
8440 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8441 tp->dev->name);
8442 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8443 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8444 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8445 tp->dev->name);
8446 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8447 }
8448 }
8449
c49a1561
MC		 8450 netif_carrier_off(tp->dev);
8451
bc1c7567 8452 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8453 if (err)
bc1c7567 8454 return err;
2f751b67
MC		 8455
8456 tg3_full_lock(tp, 0);
bc1c7567 8457
1da177e4
LT		 8458 tg3_disable_ints(tp);
8459 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8460
f47c11ee 8461 tg3_full_unlock(tp);
1da177e4 8462
679563f4
MC		 8463 /*
8464 * Setup interrupts first so we know how
8465 * many NAPI resources to allocate
8466 */
8467 tg3_ints_init(tp);
8468
1da177e4
LT		 8469 /* The placement of this call is tied
8470 * to the setup and use of Host TX descriptors.
8471 */
8472 err = tg3_alloc_consistent(tp);
8473 if (err)
679563f4 8474 goto err_out1;
88b06bc2 8475
fed97810 8476 tg3_napi_enable(tp);
1da177e4 8477
4f125f42
MC		 8478 for (i = 0; i < tp->irq_cnt; i++) {
8479 struct tg3_napi *tnapi = &tp->napi[i];
8480 err = tg3_request_irq(tp, i);
8481 if (err) {
8482 for (i--; i >= 0; i--)
8483 free_irq(tnapi->irq_vec, tnapi);
8484 break;
8485 }
8486 }
1da177e4 8487
07b0173c 8488 if (err)
679563f4 8489 goto err_out2;
bea3348e 8490
f47c11ee 8491 tg3_full_lock(tp, 0);
1da177e4 8492
8e7a22e3 8493 err = tg3_init_hw(tp, 1);
1da177e4 8494 if (err) {
944d980e 8495 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8496 tg3_free_rings(tp);
8497 } else {
fac9b83e
DM		 8498 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8499 tp->timer_offset = HZ;
8500 else
8501 tp->timer_offset = HZ / 10;
8502
8503 BUG_ON(tp->timer_offset > HZ);
8504 tp->timer_counter = tp->timer_multiplier =
8505 (HZ / tp->timer_offset);
8506 tp->asf_counter = tp->asf_multiplier =
28fbef78 8507 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8508
8509 init_timer(&tp->timer);
8510 tp->timer.expires = jiffies + tp->timer_offset;
8511 tp->timer.data = (unsigned long) tp;
8512 tp->timer.function = tg3_timer;
1da177e4
LT		 8513 }
8514
f47c11ee 8515 tg3_full_unlock(tp);
1da177e4 8516
07b0173c 8517 if (err)
679563f4 8518 goto err_out3;
1da177e4 8519
7938109f
MC		 8520 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8521 err = tg3_test_msi(tp);
fac9b83e 8522
7938109f 8523 if (err) {
f47c11ee 8524 tg3_full_lock(tp, 0);
944d980e 8525 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8526 tg3_free_rings(tp);
f47c11ee 8527 tg3_full_unlock(tp);
7938109f 8528
679563f4 8529 goto err_out2;
7938109f 8530 }
fcfa0a32 8531
f6eb9b1f
MC		 8532 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8533 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8534 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8535 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8536
f6eb9b1f
MC		 8537 tw32(PCIE_TRANSACTION_CFG,
8538 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8539 }
7938109f
MC		 8540 }
8541
b02fd9e3
MC		 8542 tg3_phy_start(tp);
8543
f47c11ee 8544 tg3_full_lock(tp, 0);
1da177e4 8545
7938109f
MC		 8546 add_timer(&tp->timer);
8547 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8548 tg3_enable_ints(tp);
8549
f47c11ee 8550 tg3_full_unlock(tp);
1da177e4 8551
fe5f5787 8552 netif_tx_start_all_queues(dev);
1da177e4
LT		 8553
8554 return 0;
07b0173c 8555
679563f4 8556err_out3:
4f125f42
MC		 8557 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8558 struct tg3_napi *tnapi = &tp->napi[i];
8559 free_irq(tnapi->irq_vec, tnapi);
8560 }
07b0173c 8561
679563f4 8562err_out2:
fed97810 8563 tg3_napi_disable(tp);
07b0173c 8564 tg3_free_consistent(tp);
679563f4
MC		 8565
8566err_out1:
8567 tg3_ints_fini(tp);
07b0173c 8568 return err;
1da177e4
LT		 8569}
8570
8571#if 0
8572/*static*/ void tg3_dump_state(struct tg3 *tp)
8573{
8574 u32 val32, val32_2, val32_3, val32_4, val32_5;
8575 u16 val16;
8576 int i;
898a56f8 8577 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8578
8579 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8580 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8581 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8582 val16, val32);
8583
8584 /* MAC block */
8585 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8586 tr32(MAC_MODE), tr32(MAC_STATUS));
8587 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8588 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8589 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8590 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8591 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8592 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8593
8594 /* Send data initiator control block */
8595 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8596 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8597 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8598 tr32(SNDDATAI_STATSCTRL));
8599
8600 /* Send data completion control block */
8601 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8602
8603 /* Send BD ring selector block */
8604 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8605 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8606
8607 /* Send BD initiator control block */
8608 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8609 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8610
8611 /* Send BD completion control block */
8612 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8613
8614 /* Receive list placement control block */
8615 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8616 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8617 printk(" RCVLPC_STATSCTRL[%08x]\n",
8618 tr32(RCVLPC_STATSCTRL));
8619
8620 /* Receive data and receive BD initiator control block */
8621 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8622 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8623
8624 /* Receive data completion control block */
8625 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8626 tr32(RCVDCC_MODE));
8627
8628 /* Receive BD initiator control block */
8629 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8630 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8631
8632 /* Receive BD completion control block */
8633 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8634 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8635
8636 /* Receive list selector control block */
8637 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8638 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8639
8640 /* Mbuf cluster free block */
8641 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8642 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8643
8644 /* Host coalescing control block */
8645 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8646 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8647 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8648 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8649 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8650 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8651 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8652 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8653 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8654 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8655 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8656 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8657
8658 /* Memory arbiter control block */
8659 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8660 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8661
8662 /* Buffer manager control block */
8663 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8664 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8665 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8666 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8667 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8668 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8669 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8670 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8671
8672 /* Read DMA control block */
8673 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8674 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8675
8676 /* Write DMA control block */
8677 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8678 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8679
8680 /* DMA completion block */
8681 printk("DEBUG: DMAC_MODE[%08x]\n",
8682 tr32(DMAC_MODE));
8683
8684 /* GRC block */
8685 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8686 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8687 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8688 tr32(GRC_LOCAL_CTRL));
8689
8690 /* TG3_BDINFOs */
8691 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8692 tr32(RCVDBDI_JUMBO_BD + 0x0),
8693 tr32(RCVDBDI_JUMBO_BD + 0x4),
8694 tr32(RCVDBDI_JUMBO_BD + 0x8),
8695 tr32(RCVDBDI_JUMBO_BD + 0xc));
8696 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8697 tr32(RCVDBDI_STD_BD + 0x0),
8698 tr32(RCVDBDI_STD_BD + 0x4),
8699 tr32(RCVDBDI_STD_BD + 0x8),
8700 tr32(RCVDBDI_STD_BD + 0xc));
8701 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8702 tr32(RCVDBDI_MINI_BD + 0x0),
8703 tr32(RCVDBDI_MINI_BD + 0x4),
8704 tr32(RCVDBDI_MINI_BD + 0x8),
8705 tr32(RCVDBDI_MINI_BD + 0xc));
8706
8707 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8708 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8709 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8710 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8711 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8712 val32, val32_2, val32_3, val32_4);
8713
8714 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8715 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8716 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8717 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8718 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8719 val32, val32_2, val32_3, val32_4);
8720
8721 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8722 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8723 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8724 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8725 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8726 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8727 val32, val32_2, val32_3, val32_4, val32_5);
8728
8729 /* SW status block */
898a56f8
MC		 8730 printk(KERN_DEBUG
8731 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8732 sblk->status,
8733 sblk->status_tag,
8734 sblk->rx_jumbo_consumer,
8735 sblk->rx_consumer,
8736 sblk->rx_mini_consumer,
8737 sblk->idx[0].rx_producer,
8738 sblk->idx[0].tx_consumer);
1da177e4
LT		 8739
8740 /* SW statistics block */
8741 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8742 ((u32 *)tp->hw_stats)[0],
8743 ((u32 *)tp->hw_stats)[1],
8744 ((u32 *)tp->hw_stats)[2],
8745 ((u32 *)tp->hw_stats)[3]);
8746
8747 /* Mailboxes */
8748 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8749 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8750 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8751 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8752 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8753
8754 /* NIC side send descriptors. */
8755 for (i = 0; i < 6; i++) {
8756 unsigned long txd;
8757
8758 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8759 + (i * sizeof(struct tg3_tx_buffer_desc));
8760 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8761 i,
8762 readl(txd + 0x0), readl(txd + 0x4),
8763 readl(txd + 0x8), readl(txd + 0xc));
8764 }
8765
8766 /* NIC side RX descriptors. */
8767 for (i = 0; i < 6; i++) {
8768 unsigned long rxd;
8769
8770 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8771 + (i * sizeof(struct tg3_rx_buffer_desc));
8772 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8773 i,
8774 readl(rxd + 0x0), readl(rxd + 0x4),
8775 readl(rxd + 0x8), readl(rxd + 0xc));
8776 rxd += (4 * sizeof(u32));
8777 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8778 i,
8779 readl(rxd + 0x0), readl(rxd + 0x4),
8780 readl(rxd + 0x8), readl(rxd + 0xc));
8781 }
8782
8783 for (i = 0; i < 6; i++) {
8784 unsigned long rxd;
8785
8786 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8787 + (i * sizeof(struct tg3_rx_buffer_desc));
8788 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8789 i,
8790 readl(rxd + 0x0), readl(rxd + 0x4),
8791 readl(rxd + 0x8), readl(rxd + 0xc));
8792 rxd += (4 * sizeof(u32));
8793 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8794 i,
8795 readl(rxd + 0x0), readl(rxd + 0x4),
8796 readl(rxd + 0x8), readl(rxd + 0xc));
8797 }
8798}
8799#endif
8800
8801static struct net_device_stats *tg3_get_stats(struct net_device *);
8802static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8803
8804static int tg3_close(struct net_device *dev)
8805{
4f125f42 8806 int i;
1da177e4
LT		 8807 struct tg3 *tp = netdev_priv(dev);
8808
fed97810 8809 tg3_napi_disable(tp);
28e53bdd 8810 cancel_work_sync(&tp->reset_task);
7faa006f 8811
fe5f5787 8812 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8813
8814 del_timer_sync(&tp->timer);
8815
24bb4fb6
MC		 8816 tg3_phy_stop(tp);
8817
f47c11ee 8818 tg3_full_lock(tp, 1);
1da177e4
LT		 8819#if 0
8820 tg3_dump_state(tp);
8821#endif
8822
8823 tg3_disable_ints(tp);
8824
944d980e 8825 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8826 tg3_free_rings(tp);
5cf64b8a 8827 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8828
f47c11ee 8829 tg3_full_unlock(tp);
1da177e4 8830
4f125f42
MC		 8831 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8832 struct tg3_napi *tnapi = &tp->napi[i];
8833 free_irq(tnapi->irq_vec, tnapi);
8834 }
07b0173c
MC		 8835
8836 tg3_ints_fini(tp);
1da177e4
LT		 8837
8838 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8839 sizeof(tp->net_stats_prev));
8840 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8841 sizeof(tp->estats_prev));
8842
8843 tg3_free_consistent(tp);
8844
bc1c7567
MC		 8845 tg3_set_power_state(tp, PCI_D3hot);
8846
8847 netif_carrier_off(tp->dev);
8848
1da177e4
LT		 8849 return 0;
8850}
8851
8852static inline unsigned long get_stat64(tg3_stat64_t *val)
8853{
8854 unsigned long ret;
8855
8856#if (BITS_PER_LONG == 32)
8857 ret = val->low;
8858#else
8859 ret = ((u64)val->high << 32) | ((u64)val->low);
8860#endif
8861 return ret;
8862}
8863
816f8b86
SB		 8864static inline u64 get_estat64(tg3_stat64_t *val)
8865{
8866 return ((u64)val->high << 32) | ((u64)val->low);
8867}
8868
1da177e4
LT		 8869static unsigned long calc_crc_errors(struct tg3 *tp)
8870{
8871 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8872
8873 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8874 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8876 u32 val;
8877
f47c11ee 8878 spin_lock_bh(&tp->lock);
569a5df8
MC		 8879 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8880 tg3_writephy(tp, MII_TG3_TEST1,
8881 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8882 tg3_readphy(tp, 0x14, &val);
8883 } else
8884 val = 0;
f47c11ee 8885 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8886
8887 tp->phy_crc_errors += val;
8888
8889 return tp->phy_crc_errors;
8890 }
8891
8892 return get_stat64(&hw_stats->rx_fcs_errors);
8893}
8894
8895#define ESTAT_ADD(member) \
8896 estats->member = old_estats->member + \
816f8b86 8897 get_estat64(&hw_stats->member)
1da177e4
LT		 8898
8899static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8900{
8901 struct tg3_ethtool_stats *estats = &tp->estats;
8902 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8903 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8904
8905 if (!hw_stats)
8906 return old_estats;
8907
8908 ESTAT_ADD(rx_octets);
8909 ESTAT_ADD(rx_fragments);
8910 ESTAT_ADD(rx_ucast_packets);
8911 ESTAT_ADD(rx_mcast_packets);
8912 ESTAT_ADD(rx_bcast_packets);
8913 ESTAT_ADD(rx_fcs_errors);
8914 ESTAT_ADD(rx_align_errors);
8915 ESTAT_ADD(rx_xon_pause_rcvd);
8916 ESTAT_ADD(rx_xoff_pause_rcvd);
8917 ESTAT_ADD(rx_mac_ctrl_rcvd);
8918 ESTAT_ADD(rx_xoff_entered);
8919 ESTAT_ADD(rx_frame_too_long_errors);
8920 ESTAT_ADD(rx_jabbers);
8921 ESTAT_ADD(rx_undersize_packets);
8922 ESTAT_ADD(rx_in_length_errors);
8923 ESTAT_ADD(rx_out_length_errors);
8924 ESTAT_ADD(rx_64_or_less_octet_packets);
8925 ESTAT_ADD(rx_65_to_127_octet_packets);
8926 ESTAT_ADD(rx_128_to_255_octet_packets);
8927 ESTAT_ADD(rx_256_to_511_octet_packets);
8928 ESTAT_ADD(rx_512_to_1023_octet_packets);
8929 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8930 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8931 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8932 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8933 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8934
8935 ESTAT_ADD(tx_octets);
8936 ESTAT_ADD(tx_collisions);
8937 ESTAT_ADD(tx_xon_sent);
8938 ESTAT_ADD(tx_xoff_sent);
8939 ESTAT_ADD(tx_flow_control);
8940 ESTAT_ADD(tx_mac_errors);
8941 ESTAT_ADD(tx_single_collisions);
8942 ESTAT_ADD(tx_mult_collisions);
8943 ESTAT_ADD(tx_deferred);
8944 ESTAT_ADD(tx_excessive_collisions);
8945 ESTAT_ADD(tx_late_collisions);
8946 ESTAT_ADD(tx_collide_2times);
8947 ESTAT_ADD(tx_collide_3times);
8948 ESTAT_ADD(tx_collide_4times);
8949 ESTAT_ADD(tx_collide_5times);
8950 ESTAT_ADD(tx_collide_6times);
8951 ESTAT_ADD(tx_collide_7times);
8952 ESTAT_ADD(tx_collide_8times);
8953 ESTAT_ADD(tx_collide_9times);
8954 ESTAT_ADD(tx_collide_10times);
8955 ESTAT_ADD(tx_collide_11times);
8956 ESTAT_ADD(tx_collide_12times);
8957 ESTAT_ADD(tx_collide_13times);
8958 ESTAT_ADD(tx_collide_14times);
8959 ESTAT_ADD(tx_collide_15times);
8960 ESTAT_ADD(tx_ucast_packets);
8961 ESTAT_ADD(tx_mcast_packets);
8962 ESTAT_ADD(tx_bcast_packets);
8963 ESTAT_ADD(tx_carrier_sense_errors);
8964 ESTAT_ADD(tx_discards);
8965 ESTAT_ADD(tx_errors);
8966
8967 ESTAT_ADD(dma_writeq_full);
8968 ESTAT_ADD(dma_write_prioq_full);
8969 ESTAT_ADD(rxbds_empty);
8970 ESTAT_ADD(rx_discards);
8971 ESTAT_ADD(rx_errors);
8972 ESTAT_ADD(rx_threshold_hit);
8973
8974 ESTAT_ADD(dma_readq_full);
8975 ESTAT_ADD(dma_read_prioq_full);
8976 ESTAT_ADD(tx_comp_queue_full);
8977
8978 ESTAT_ADD(ring_set_send_prod_index);
8979 ESTAT_ADD(ring_status_update);
8980 ESTAT_ADD(nic_irqs);
8981 ESTAT_ADD(nic_avoided_irqs);
8982 ESTAT_ADD(nic_tx_threshold_hit);
8983
8984 return estats;
8985}
8986
8987static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8988{
8989 struct tg3 *tp = netdev_priv(dev);
8990 struct net_device_stats *stats = &tp->net_stats;
8991 struct net_device_stats *old_stats = &tp->net_stats_prev;
8992 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8993
8994 if (!hw_stats)
8995 return old_stats;
8996
8997 stats->rx_packets = old_stats->rx_packets +
8998 get_stat64(&hw_stats->rx_ucast_packets) +
8999 get_stat64(&hw_stats->rx_mcast_packets) +
9000 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9001
1da177e4
LT		 9002 stats->tx_packets = old_stats->tx_packets +
9003 get_stat64(&hw_stats->tx_ucast_packets) +
9004 get_stat64(&hw_stats->tx_mcast_packets) +
9005 get_stat64(&hw_stats->tx_bcast_packets);
9006
9007 stats->rx_bytes = old_stats->rx_bytes +
9008 get_stat64(&hw_stats->rx_octets);
9009 stats->tx_bytes = old_stats->tx_bytes +
9010 get_stat64(&hw_stats->tx_octets);
9011
9012 stats->rx_errors = old_stats->rx_errors +
4f63b877 9013 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9014 stats->tx_errors = old_stats->tx_errors +
9015 get_stat64(&hw_stats->tx_errors) +
9016 get_stat64(&hw_stats->tx_mac_errors) +
9017 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9018 get_stat64(&hw_stats->tx_discards);
9019
9020 stats->multicast = old_stats->multicast +
9021 get_stat64(&hw_stats->rx_mcast_packets);
9022 stats->collisions = old_stats->collisions +
9023 get_stat64(&hw_stats->tx_collisions);
9024
9025 stats->rx_length_errors = old_stats->rx_length_errors +
9026 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9027 get_stat64(&hw_stats->rx_undersize_packets);
9028
9029 stats->rx_over_errors = old_stats->rx_over_errors +
9030 get_stat64(&hw_stats->rxbds_empty);
9031 stats->rx_frame_errors = old_stats->rx_frame_errors +
9032 get_stat64(&hw_stats->rx_align_errors);
9033 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9034 get_stat64(&hw_stats->tx_discards);
9035 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9036 get_stat64(&hw_stats->tx_carrier_sense_errors);
9037
9038 stats->rx_crc_errors = old_stats->rx_crc_errors +
9039 calc_crc_errors(tp);
9040
4f63b877
JL		 9041 stats->rx_missed_errors = old_stats->rx_missed_errors +
9042 get_stat64(&hw_stats->rx_discards);
9043
1da177e4
LT		 9044 return stats;
9045}
9046
9047static inline u32 calc_crc(unsigned char *buf, int len)
9048{
9049 u32 reg;
9050 u32 tmp;
9051 int j, k;
9052
9053 reg = 0xffffffff;
9054
9055 for (j = 0; j < len; j++) {
9056 reg ^= buf[j];
9057
9058 for (k = 0; k < 8; k++) {
9059 tmp = reg & 0x01;
9060
9061 reg >>= 1;
9062
9063 if (tmp) {
9064 reg ^= 0xedb88320;
9065 }
9066 }
9067 }
9068
9069 return ~reg;
9070}
9071
9072static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9073{
9074 /* accept or reject all multicast frames */
9075 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9076 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9077 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9078 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9079}
9080
9081static void __tg3_set_rx_mode(struct net_device *dev)
9082{
9083 struct tg3 *tp = netdev_priv(dev);
9084 u32 rx_mode;
9085
9086 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9087 RX_MODE_KEEP_VLAN_TAG);
9088
9089 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9090 * flag clear.
9091 */
9092#if TG3_VLAN_TAG_USED
9093 if (!tp->vlgrp &&
9094 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9095 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9096#else
9097 /* By definition, VLAN is disabled always in this
9098 * case.
9099 */
9100 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9101 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9102#endif
9103
9104 if (dev->flags & IFF_PROMISC) {
9105 /* Promiscuous mode. */
9106 rx_mode |= RX_MODE_PROMISC;
9107 } else if (dev->flags & IFF_ALLMULTI) {
9108 /* Accept all multicast. */
9109 tg3_set_multi (tp, 1);
9110 } else if (dev->mc_count < 1) {
9111 /* Reject all multicast. */
9112 tg3_set_multi (tp, 0);
9113 } else {
9114 /* Accept one or more multicast(s). */
9115 struct dev_mc_list *mclist;
9116 unsigned int i;
9117 u32 mc_filter[4] = { 0, };
9118 u32 regidx;
9119 u32 bit;
9120 u32 crc;
9121
9122 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9123 i++, mclist = mclist->next) {
9124
9125 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9126 bit = ~crc & 0x7f;
9127 regidx = (bit & 0x60) >> 5;
9128 bit &= 0x1f;
9129 mc_filter[regidx] |= (1 << bit);
9130 }
9131
9132 tw32(MAC_HASH_REG_0, mc_filter[0]);
9133 tw32(MAC_HASH_REG_1, mc_filter[1]);
9134 tw32(MAC_HASH_REG_2, mc_filter[2]);
9135 tw32(MAC_HASH_REG_3, mc_filter[3]);
9136 }
9137
9138 if (rx_mode != tp->rx_mode) {
9139 tp->rx_mode = rx_mode;
9140 tw32_f(MAC_RX_MODE, rx_mode);
9141 udelay(10);
9142 }
9143}
9144
9145static void tg3_set_rx_mode(struct net_device *dev)
9146{
9147 struct tg3 *tp = netdev_priv(dev);
9148
e75f7c90
MC		 9149 if (!netif_running(dev))
9150 return;
9151
f47c11ee 9152 tg3_full_lock(tp, 0);
1da177e4 9153 __tg3_set_rx_mode(dev);
f47c11ee 9154 tg3_full_unlock(tp);
1da177e4
LT		 9155}
9156
9157#define TG3_REGDUMP_LEN (32 * 1024)
9158
9159static int tg3_get_regs_len(struct net_device *dev)
9160{
9161 return TG3_REGDUMP_LEN;
9162}
9163
9164static void tg3_get_regs(struct net_device *dev,
9165 struct ethtool_regs *regs, void *_p)
9166{
9167 u32 *p = _p;
9168 struct tg3 *tp = netdev_priv(dev);
9169 u8 *orig_p = _p;
9170 int i;
9171
9172 regs->version = 0;
9173
9174 memset(p, 0, TG3_REGDUMP_LEN);
9175
bc1c7567
MC		 9176 if (tp->link_config.phy_is_low_power)
9177 return;
9178
f47c11ee 9179 tg3_full_lock(tp, 0);
1da177e4
LT		 9180
9181#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9182#define GET_REG32_LOOP(base,len) \
9183do { p = (u32 *)(orig_p + (base)); \
9184 for (i = 0; i < len; i += 4) \
9185 __GET_REG32((base) + i); \
9186} while (0)
9187#define GET_REG32_1(reg) \
9188do { p = (u32 *)(orig_p + (reg)); \
9189 __GET_REG32((reg)); \
9190} while (0)
9191
9192 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9193 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9194 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9195 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9196 GET_REG32_1(SNDDATAC_MODE);
9197 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9198 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9199 GET_REG32_1(SNDBDC_MODE);
9200 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9201 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9202 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9203 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9204 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9205 GET_REG32_1(RCVDCC_MODE);
9206 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9207 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9208 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9209 GET_REG32_1(MBFREE_MODE);
9210 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9211 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9212 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9213 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9214 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9215 GET_REG32_1(RX_CPU_MODE);
9216 GET_REG32_1(RX_CPU_STATE);
9217 GET_REG32_1(RX_CPU_PGMCTR);
9218 GET_REG32_1(RX_CPU_HWBKPT);
9219 GET_REG32_1(TX_CPU_MODE);
9220 GET_REG32_1(TX_CPU_STATE);
9221 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9222 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9223 GET_REG32_LOOP(FTQ_RESET, 0x120);
9224 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9225 GET_REG32_1(DMAC_MODE);
9226 GET_REG32_LOOP(GRC_MODE, 0x4c);
9227 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9228 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9229
9230#undef __GET_REG32
9231#undef GET_REG32_LOOP
9232#undef GET_REG32_1
9233
f47c11ee 9234 tg3_full_unlock(tp);
1da177e4
LT		 9235}
9236
9237static int tg3_get_eeprom_len(struct net_device *dev)
9238{
9239 struct tg3 *tp = netdev_priv(dev);
9240
9241 return tp->nvram_size;
9242}
9243
1da177e4
LT		 9244static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9245{
9246 struct tg3 *tp = netdev_priv(dev);
9247 int ret;
9248 u8 *pd;
b9fc7dc5 9249 u32 i, offset, len, b_offset, b_count;
a9dc529d 9250 __be32 val;
1da177e4 9251
df259d8c
MC		 9252 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9253 return -EINVAL;
9254
bc1c7567
MC		 9255 if (tp->link_config.phy_is_low_power)
9256 return -EAGAIN;
9257
1da177e4
LT		 9258 offset = eeprom->offset;
9259 len = eeprom->len;
9260 eeprom->len = 0;
9261
9262 eeprom->magic = TG3_EEPROM_MAGIC;
9263
9264 if (offset & 3) {
9265 /* adjustments to start on required 4 byte boundary */
9266 b_offset = offset & 3;
9267 b_count = 4 - b_offset;
9268 if (b_count > len) {
9269 /* i.e. offset=1 len=2 */
9270 b_count = len;
9271 }
a9dc529d 9272 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9273 if (ret)
9274 return ret;
1da177e4
LT		 9275 memcpy(data, ((char*)&val) + b_offset, b_count);
9276 len -= b_count;
9277 offset += b_count;
9278 eeprom->len += b_count;
9279 }
9280
9281 /* read bytes upto the last 4 byte boundary */
9282 pd = &data[eeprom->len];
9283 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9284 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9285 if (ret) {
9286 eeprom->len += i;
9287 return ret;
9288 }
1da177e4
LT		 9289 memcpy(pd + i, &val, 4);
9290 }
9291 eeprom->len += i;
9292
9293 if (len & 3) {
9294 /* read last bytes not ending on 4 byte boundary */
9295 pd = &data[eeprom->len];
9296 b_count = len & 3;
9297 b_offset = offset + len - b_count;
a9dc529d 9298 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9299 if (ret)
9300 return ret;
b9fc7dc5 9301 memcpy(pd, &val, b_count);
1da177e4
LT		 9302 eeprom->len += b_count;
9303 }
9304 return 0;
9305}
9306
6aa20a22 9307static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9308
9309static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9310{
9311 struct tg3 *tp = netdev_priv(dev);
9312 int ret;
b9fc7dc5 9313 u32 offset, len, b_offset, odd_len;
1da177e4 9314 u8 *buf;
a9dc529d 9315 __be32 start, end;
1da177e4 9316
bc1c7567
MC		 9317 if (tp->link_config.phy_is_low_power)
9318 return -EAGAIN;
9319
df259d8c
MC		 9320 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9321 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9322 return -EINVAL;
9323
9324 offset = eeprom->offset;
9325 len = eeprom->len;
9326
9327 if ((b_offset = (offset & 3))) {
9328 /* adjustments to start on required 4 byte boundary */
a9dc529d 9329 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9330 if (ret)
9331 return ret;
1da177e4
LT		 9332 len += b_offset;
9333 offset &= ~3;
1c8594b4
MC		 9334 if (len < 4)
9335 len = 4;
1da177e4
LT		 9336 }
9337
9338 odd_len = 0;
1c8594b4 9339 if (len & 3) {
1da177e4
LT		 9340 /* adjustments to end on required 4 byte boundary */
9341 odd_len = 1;
9342 len = (len + 3) & ~3;
a9dc529d 9343 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9344 if (ret)
9345 return ret;
1da177e4
LT		 9346 }
9347
9348 buf = data;
9349 if (b_offset || odd_len) {
9350 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9351 if (!buf)
1da177e4
LT		 9352 return -ENOMEM;
9353 if (b_offset)
9354 memcpy(buf, &start, 4);
9355 if (odd_len)
9356 memcpy(buf+len-4, &end, 4);
9357 memcpy(buf + b_offset, data, eeprom->len);
9358 }
9359
9360 ret = tg3_nvram_write_block(tp, offset, len, buf);
9361
9362 if (buf != data)
9363 kfree(buf);
9364
9365 return ret;
9366}
9367
9368static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9369{
b02fd9e3
MC		 9370 struct tg3 *tp = netdev_priv(dev);
9371
9372 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9373 struct phy_device *phydev;
b02fd9e3
MC		 9374 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9375 return -EAGAIN;
3f0e3ad7
MC		 9376 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9377 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9378 }
6aa20a22 9379
1da177e4
LT		 9380 cmd->supported = (SUPPORTED_Autoneg);
9381
9382 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9383 cmd->supported |= (SUPPORTED_1000baseT_Half |
9384 SUPPORTED_1000baseT_Full);
9385
ef348144 9386 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9387 cmd->supported |= (SUPPORTED_100baseT_Half |
9388 SUPPORTED_100baseT_Full |
9389 SUPPORTED_10baseT_Half |
9390 SUPPORTED_10baseT_Full |
3bebab59 9391 SUPPORTED_TP);
ef348144
KK		 9392 cmd->port = PORT_TP;
9393 } else {
1da177e4 9394 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9395 cmd->port = PORT_FIBRE;
9396 }
6aa20a22 9397
1da177e4
LT		 9398 cmd->advertising = tp->link_config.advertising;
9399 if (netif_running(dev)) {
9400 cmd->speed = tp->link_config.active_speed;
9401 cmd->duplex = tp->link_config.active_duplex;
9402 }
882e9793 9403 cmd->phy_address = tp->phy_addr;
7e5856bd 9404 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9405 cmd->autoneg = tp->link_config.autoneg;
9406 cmd->maxtxpkt = 0;
9407 cmd->maxrxpkt = 0;
9408 return 0;
9409}
6aa20a22 9410
1da177e4
LT		 9411static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9412{
9413 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9414
b02fd9e3 9415 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9416 struct phy_device *phydev;
b02fd9e3
MC		 9417 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9418 return -EAGAIN;
3f0e3ad7
MC		 9419 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9420 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9421 }
9422
7e5856bd
MC		 9423 if (cmd->autoneg != AUTONEG_ENABLE &&
9424 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9425 return -EINVAL;
7e5856bd
MC		 9426
9427 if (cmd->autoneg == AUTONEG_DISABLE &&
9428 cmd->duplex != DUPLEX_FULL &&
9429 cmd->duplex != DUPLEX_HALF)
37ff238d 9430 return -EINVAL;
1da177e4 9431
7e5856bd
MC		 9432 if (cmd->autoneg == AUTONEG_ENABLE) {
9433 u32 mask = ADVERTISED_Autoneg |
9434 ADVERTISED_Pause |
9435 ADVERTISED_Asym_Pause;
9436
9437 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9438 mask |= ADVERTISED_1000baseT_Half |
9439 ADVERTISED_1000baseT_Full;
9440
9441 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9442 mask |= ADVERTISED_100baseT_Half |
9443 ADVERTISED_100baseT_Full |
9444 ADVERTISED_10baseT_Half |
9445 ADVERTISED_10baseT_Full |
9446 ADVERTISED_TP;
9447 else
9448 mask |= ADVERTISED_FIBRE;
9449
9450 if (cmd->advertising & ~mask)
9451 return -EINVAL;
9452
9453 mask &= (ADVERTISED_1000baseT_Half |
9454 ADVERTISED_1000baseT_Full |
9455 ADVERTISED_100baseT_Half |
9456 ADVERTISED_100baseT_Full |
9457 ADVERTISED_10baseT_Half |
9458 ADVERTISED_10baseT_Full);
9459
9460 cmd->advertising &= mask;
9461 } else {
9462 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9463 if (cmd->speed != SPEED_1000)
9464 return -EINVAL;
9465
9466 if (cmd->duplex != DUPLEX_FULL)
9467 return -EINVAL;
9468 } else {
9469 if (cmd->speed != SPEED_100 &&
9470 cmd->speed != SPEED_10)
9471 return -EINVAL;
9472 }
9473 }
9474
f47c11ee 9475 tg3_full_lock(tp, 0);
1da177e4
LT		 9476
9477 tp->link_config.autoneg = cmd->autoneg;
9478 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9479 tp->link_config.advertising = (cmd->advertising |
9480 ADVERTISED_Autoneg);
1da177e4
LT		 9481 tp->link_config.speed = SPEED_INVALID;
9482 tp->link_config.duplex = DUPLEX_INVALID;
9483 } else {
9484 tp->link_config.advertising = 0;
9485 tp->link_config.speed = cmd->speed;
9486 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9487 }
6aa20a22 9488
24fcad6b
MC		 9489 tp->link_config.orig_speed = tp->link_config.speed;
9490 tp->link_config.orig_duplex = tp->link_config.duplex;
9491 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9492
1da177e4
LT		 9493 if (netif_running(dev))
9494 tg3_setup_phy(tp, 1);
9495
f47c11ee 9496 tg3_full_unlock(tp);
6aa20a22 9497
1da177e4
LT		 9498 return 0;
9499}
6aa20a22 9500
1da177e4
LT		 9501static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9502{
9503 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9504
1da177e4
LT		 9505 strcpy(info->driver, DRV_MODULE_NAME);
9506 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9507 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9508 strcpy(info->bus_info, pci_name(tp->pdev));
9509}
6aa20a22 9510
1da177e4
LT		 9511static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9512{
9513 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9514
12dac075
RW		 9515 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9516 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9517 wol->supported = WAKE_MAGIC;
9518 else
9519 wol->supported = 0;
1da177e4 9520 wol->wolopts = 0;
05ac4cb7
MC		 9521 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9522 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9523 wol->wolopts = WAKE_MAGIC;
9524 memset(&wol->sopass, 0, sizeof(wol->sopass));
9525}
6aa20a22 9526
1da177e4
LT		 9527static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9528{
9529 struct tg3 *tp = netdev_priv(dev);
12dac075 9530 struct device *dp = &tp->pdev->dev;
6aa20a22 9531
1da177e4
LT		 9532 if (wol->wolopts & ~WAKE_MAGIC)
9533 return -EINVAL;
9534 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9535 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9536 return -EINVAL;
6aa20a22 9537
f47c11ee 9538 spin_lock_bh(&tp->lock);
12dac075 9539 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9540 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9541 device_set_wakeup_enable(dp, true);
9542 } else {
1da177e4 9543 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9544 device_set_wakeup_enable(dp, false);
9545 }
f47c11ee 9546 spin_unlock_bh(&tp->lock);
6aa20a22 9547
1da177e4
LT		 9548 return 0;
9549}
6aa20a22 9550
1da177e4
LT		 9551static u32 tg3_get_msglevel(struct net_device *dev)
9552{
9553 struct tg3 *tp = netdev_priv(dev);
9554 return tp->msg_enable;
9555}
6aa20a22 9556
1da177e4
LT		 9557static void tg3_set_msglevel(struct net_device *dev, u32 value)
9558{
9559 struct tg3 *tp = netdev_priv(dev);
9560 tp->msg_enable = value;
9561}
6aa20a22 9562
1da177e4
LT		 9563static int tg3_set_tso(struct net_device *dev, u32 value)
9564{
9565 struct tg3 *tp = netdev_priv(dev);
9566
9567 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9568 if (value)
9569 return -EINVAL;
9570 return 0;
9571 }
027455ad 9572 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9573 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9574 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9575 if (value) {
b0026624 9576 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9577 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9579 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9580 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9581 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9582 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9583 dev->features |= NETIF_F_TSO_ECN;
9584 } else
9585 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9586 }
1da177e4
LT		 9587 return ethtool_op_set_tso(dev, value);
9588}
6aa20a22 9589
1da177e4
LT		 9590static int tg3_nway_reset(struct net_device *dev)
9591{
9592 struct tg3 *tp = netdev_priv(dev);
1da177e4 9593 int r;
6aa20a22 9594
1da177e4
LT		 9595 if (!netif_running(dev))
9596 return -EAGAIN;
9597
c94e3941
MC		 9598 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9599 return -EINVAL;
9600
b02fd9e3
MC		 9601 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9602 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9603 return -EAGAIN;
3f0e3ad7 9604 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9605 } else {
9606 u32 bmcr;
9607
9608 spin_lock_bh(&tp->lock);
9609 r = -EINVAL;
9610 tg3_readphy(tp, MII_BMCR, &bmcr);
9611 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9612 ((bmcr & BMCR_ANENABLE) ||
9613 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9614 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9615 BMCR_ANENABLE);
9616 r = 0;
9617 }
9618 spin_unlock_bh(&tp->lock);
1da177e4 9619 }
6aa20a22 9620
1da177e4
LT		 9621 return r;
9622}
6aa20a22 9623
1da177e4
LT		 9624static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9625{
9626 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9627
1da177e4
LT		 9628 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9629 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9630 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9631 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9632 else
9633 ering->rx_jumbo_max_pending = 0;
9634
9635 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9636
9637 ering->rx_pending = tp->rx_pending;
9638 ering->rx_mini_pending = 0;
4f81c32b
MC		 9639 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9640 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9641 else
9642 ering->rx_jumbo_pending = 0;
9643
f3f3f27e 9644 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9645}
6aa20a22 9646
1da177e4
LT		 9647static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9648{
9649 struct tg3 *tp = netdev_priv(dev);
646c9edd 9650 int i, irq_sync = 0, err = 0;
6aa20a22 9651
1da177e4
LT		 9652 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9653 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9654 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9655 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9656 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9657 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9658 return -EINVAL;
6aa20a22 9659
bbe832c0 9660 if (netif_running(dev)) {
b02fd9e3 9661 tg3_phy_stop(tp);
1da177e4 9662 tg3_netif_stop(tp);
bbe832c0
MC		 9663 irq_sync = 1;
9664 }
1da177e4 9665
bbe832c0 9666 tg3_full_lock(tp, irq_sync);
6aa20a22 9667
1da177e4
LT		 9668 tp->rx_pending = ering->rx_pending;
9669
9670 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9671 tp->rx_pending > 63)
9672 tp->rx_pending = 63;
9673 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9674
9675 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9676 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9677
9678 if (netif_running(dev)) {
944d980e 9679 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9680 err = tg3_restart_hw(tp, 1);
9681 if (!err)
9682 tg3_netif_start(tp);
1da177e4
LT		 9683 }
9684
f47c11ee 9685 tg3_full_unlock(tp);
6aa20a22 9686
b02fd9e3
MC		 9687 if (irq_sync && !err)
9688 tg3_phy_start(tp);
9689
b9ec6c1b 9690 return err;
1da177e4 9691}
6aa20a22 9692
1da177e4
LT		 9693static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9694{
9695 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9696
1da177e4 9697 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9698
e18ce346 9699 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9700 epause->rx_pause = 1;
9701 else
9702 epause->rx_pause = 0;
9703
e18ce346 9704 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9705 epause->tx_pause = 1;
9706 else
9707 epause->tx_pause = 0;
1da177e4 9708}
6aa20a22 9709
1da177e4
LT		 9710static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9711{
9712 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9713 int err = 0;
6aa20a22 9714
b02fd9e3
MC		 9715 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9716 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9717 return -EAGAIN;
1da177e4 9718
b02fd9e3
MC		 9719 if (epause->autoneg) {
9720 u32 newadv;
9721 struct phy_device *phydev;
f47c11ee 9722
3f0e3ad7 9723 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9724
b02fd9e3
MC		 9725 if (epause->rx_pause) {
9726 if (epause->tx_pause)
9727 newadv = ADVERTISED_Pause;
9728 else
9729 newadv = ADVERTISED_Pause |
9730 ADVERTISED_Asym_Pause;
9731 } else if (epause->tx_pause) {
9732 newadv = ADVERTISED_Asym_Pause;
9733 } else
9734 newadv = 0;
9735
9736 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9737 u32 oldadv = phydev->advertising &
9738 (ADVERTISED_Pause |
9739 ADVERTISED_Asym_Pause);
9740 if (oldadv != newadv) {
9741 phydev->advertising &=
9742 ~(ADVERTISED_Pause |
9743 ADVERTISED_Asym_Pause);
9744 phydev->advertising |= newadv;
9745 err = phy_start_aneg(phydev);
9746 }
9747 } else {
9748 tp->link_config.advertising &=
9749 ~(ADVERTISED_Pause |
9750 ADVERTISED_Asym_Pause);
9751 tp->link_config.advertising |= newadv;
9752 }
9753 } else {
9754 if (epause->rx_pause)
e18ce346 9755 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9756 else
e18ce346 9757 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9758
b02fd9e3 9759 if (epause->tx_pause)
e18ce346 9760 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9761 else
e18ce346 9762 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9763
9764 if (netif_running(dev))
9765 tg3_setup_flow_control(tp, 0, 0);
9766 }
9767 } else {
9768 int irq_sync = 0;
9769
9770 if (netif_running(dev)) {
9771 tg3_netif_stop(tp);
9772 irq_sync = 1;
9773 }
9774
9775 tg3_full_lock(tp, irq_sync);
9776
9777 if (epause->autoneg)
9778 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9779 else
9780 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9781 if (epause->rx_pause)
e18ce346 9782 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9783 else
e18ce346 9784 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9785 if (epause->tx_pause)
e18ce346 9786 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9787 else
e18ce346 9788 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9789
9790 if (netif_running(dev)) {
9791 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9792 err = tg3_restart_hw(tp, 1);
9793 if (!err)
9794 tg3_netif_start(tp);
9795 }
9796
9797 tg3_full_unlock(tp);
9798 }
6aa20a22 9799
b9ec6c1b 9800 return err;
1da177e4 9801}
6aa20a22 9802
1da177e4
LT		 9803static u32 tg3_get_rx_csum(struct net_device *dev)
9804{
9805 struct tg3 *tp = netdev_priv(dev);
9806 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9807}
6aa20a22 9808
1da177e4
LT		 9809static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9810{
9811 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9812
1da177e4
LT		 9813 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9814 if (data != 0)
9815 return -EINVAL;
9816 return 0;
9817 }
6aa20a22 9818
f47c11ee 9819 spin_lock_bh(&tp->lock);
1da177e4
LT		 9820 if (data)
9821 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9822 else
9823 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9824 spin_unlock_bh(&tp->lock);
6aa20a22 9825
1da177e4
LT		 9826 return 0;
9827}
6aa20a22 9828
1da177e4
LT		 9829static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9830{
9831 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9832
1da177e4
LT		 9833 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9834 if (data != 0)
9835 return -EINVAL;
9836 return 0;
9837 }
6aa20a22 9838
321d32a0 9839 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9840 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9841 else
9c27dbdf 9842 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9843
9844 return 0;
9845}
9846
b9f2c044 9847static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9848{
b9f2c044
JG		 9849 switch (sset) {
9850 case ETH_SS_TEST:
9851 return TG3_NUM_TEST;
9852 case ETH_SS_STATS:
9853 return TG3_NUM_STATS;
9854 default:
9855 return -EOPNOTSUPP;
9856 }
4cafd3f5
MC		 9857}
9858
1da177e4
LT		 9859static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9860{
9861 switch (stringset) {
9862 case ETH_SS_STATS:
9863 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9864 break;
4cafd3f5
MC		 9865 case ETH_SS_TEST:
9866 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9867 break;
1da177e4
LT		 9868 default:
9869 WARN_ON(1); /* we need a WARN() */
9870 break;
9871 }
9872}
9873
4009a93d
MC		 9874static int tg3_phys_id(struct net_device *dev, u32 data)
9875{
9876 struct tg3 *tp = netdev_priv(dev);
9877 int i;
9878
9879 if (!netif_running(tp->dev))
9880 return -EAGAIN;
9881
9882 if (data == 0)
759afc31 9883 data = UINT_MAX / 2;
4009a93d
MC		 9884
9885 for (i = 0; i < (data * 2); i++) {
9886 if ((i % 2) == 0)
9887 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9888 LED_CTRL_1000MBPS_ON |
9889 LED_CTRL_100MBPS_ON |
9890 LED_CTRL_10MBPS_ON |
9891 LED_CTRL_TRAFFIC_OVERRIDE |
9892 LED_CTRL_TRAFFIC_BLINK |
9893 LED_CTRL_TRAFFIC_LED);
6aa20a22 9894
4009a93d
MC		 9895 else
9896 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9897 LED_CTRL_TRAFFIC_OVERRIDE);
9898
9899 if (msleep_interruptible(500))
9900 break;
9901 }
9902 tw32(MAC_LED_CTRL, tp->led_ctrl);
9903 return 0;
9904}
9905
1da177e4
LT		 9906static void tg3_get_ethtool_stats (struct net_device *dev,
9907 struct ethtool_stats *estats, u64 *tmp_stats)
9908{
9909 struct tg3 *tp = netdev_priv(dev);
9910 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9911}
9912
566f86ad 9913#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9914#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9915#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9916#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9917#define NVRAM_SELFBOOT_HW_SIZE 0x20
9918#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9919
9920static int tg3_test_nvram(struct tg3 *tp)
9921{
b9fc7dc5 9922 u32 csum, magic;
a9dc529d 9923 __be32 *buf;
ab0049b4 9924 int i, j, k, err = 0, size;
566f86ad 9925
df259d8c
MC		 9926 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9927 return 0;
9928
e4f34110 9929 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9930 return -EIO;
9931
1b27777a
MC		 9932 if (magic == TG3_EEPROM_MAGIC)
9933 size = NVRAM_TEST_SIZE;
b16250e3 9934 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9935 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9936 TG3_EEPROM_SB_FORMAT_1) {
9937 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9938 case TG3_EEPROM_SB_REVISION_0:
9939 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9940 break;
9941 case TG3_EEPROM_SB_REVISION_2:
9942 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9943 break;
9944 case TG3_EEPROM_SB_REVISION_3:
9945 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9946 break;
9947 default:
9948 return 0;
9949 }
9950 } else
1b27777a 9951 return 0;
b16250e3
MC		 9952 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9953 size = NVRAM_SELFBOOT_HW_SIZE;
9954 else
1b27777a
MC		 9955 return -EIO;
9956
9957 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9958 if (buf == NULL)
9959 return -ENOMEM;
9960
1b27777a
MC		 9961 err = -EIO;
9962 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9963 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9964 if (err)
566f86ad 9965 break;
566f86ad 9966 }
1b27777a 9967 if (i < size)
566f86ad
MC		 9968 goto out;
9969
1b27777a 9970 /* Selfboot format */
a9dc529d 9971 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9972 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9973 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9974 u8 *buf8 = (u8 *) buf, csum8 = 0;
9975
b9fc7dc5 9976 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9977 TG3_EEPROM_SB_REVISION_2) {
9978 /* For rev 2, the csum doesn't include the MBA. */
9979 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9980 csum8 += buf8[i];
9981 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9982 csum8 += buf8[i];
9983 } else {
9984 for (i = 0; i < size; i++)
9985 csum8 += buf8[i];
9986 }
1b27777a 9987
ad96b485
AB		 9988 if (csum8 == 0) {
9989 err = 0;
9990 goto out;
9991 }
9992
9993 err = -EIO;
9994 goto out;
1b27777a 9995 }
566f86ad 9996
b9fc7dc5 9997 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9998 TG3_EEPROM_MAGIC_HW) {
9999 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10000 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10001 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10002
10003 /* Separate the parity bits and the data bytes. */
10004 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10005 if ((i == 0) || (i == 8)) {
10006 int l;
10007 u8 msk;
10008
10009 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10010 parity[k++] = buf8[i] & msk;
10011 i++;
10012 }
10013 else if (i == 16) {
10014 int l;
10015 u8 msk;
10016
10017 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10018 parity[k++] = buf8[i] & msk;
10019 i++;
10020
10021 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10022 parity[k++] = buf8[i] & msk;
10023 i++;
10024 }
10025 data[j++] = buf8[i];
10026 }
10027
10028 err = -EIO;
10029 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10030 u8 hw8 = hweight8(data[i]);
10031
10032 if ((hw8 & 0x1) && parity[i])
10033 goto out;
10034 else if (!(hw8 & 0x1) && !parity[i])
10035 goto out;
10036 }
10037 err = 0;
10038 goto out;
10039 }
10040
566f86ad
MC		 10041 /* Bootstrap checksum at offset 0x10 */
10042 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10043 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10044 goto out;
10045
10046 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10047 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10048 if (csum != be32_to_cpu(buf[0xfc/4]))
10049 goto out;
566f86ad
MC		 10050
10051 err = 0;
10052
10053out:
10054 kfree(buf);
10055 return err;
10056}
10057
ca43007a
MC		 10058#define TG3_SERDES_TIMEOUT_SEC 2
10059#define TG3_COPPER_TIMEOUT_SEC 6
10060
10061static int tg3_test_link(struct tg3 *tp)
10062{
10063 int i, max;
10064
10065 if (!netif_running(tp->dev))
10066 return -ENODEV;
10067
4c987487 10068 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10069 max = TG3_SERDES_TIMEOUT_SEC;
10070 else
10071 max = TG3_COPPER_TIMEOUT_SEC;
10072
10073 for (i = 0; i < max; i++) {
10074 if (netif_carrier_ok(tp->dev))
10075 return 0;
10076
10077 if (msleep_interruptible(1000))
10078 break;
10079 }
10080
10081 return -EIO;
10082}
10083
a71116d1 10084/* Only test the commonly used registers */
30ca3e37 10085static int tg3_test_registers(struct tg3 *tp)
a71116d1 10086{
b16250e3 10087 int i, is_5705, is_5750;
a71116d1
MC		 10088 u32 offset, read_mask, write_mask, val, save_val, read_val;
10089 static struct {
10090 u16 offset;
10091 u16 flags;
10092#define TG3_FL_5705 0x1
10093#define TG3_FL_NOT_5705 0x2
10094#define TG3_FL_NOT_5788 0x4
b16250e3 10095#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10096 u32 read_mask;
10097 u32 write_mask;
10098 } reg_tbl[] = {
10099 /* MAC Control Registers */
10100 { MAC_MODE, TG3_FL_NOT_5705,
10101 0x00000000, 0x00ef6f8c },
10102 { MAC_MODE, TG3_FL_5705,
10103 0x00000000, 0x01ef6b8c },
10104 { MAC_STATUS, TG3_FL_NOT_5705,
10105 0x03800107, 0x00000000 },
10106 { MAC_STATUS, TG3_FL_5705,
10107 0x03800100, 0x00000000 },
10108 { MAC_ADDR_0_HIGH, 0x0000,
10109 0x00000000, 0x0000ffff },
10110 { MAC_ADDR_0_LOW, 0x0000,
10111 0x00000000, 0xffffffff },
10112 { MAC_RX_MTU_SIZE, 0x0000,
10113 0x00000000, 0x0000ffff },
10114 { MAC_TX_MODE, 0x0000,
10115 0x00000000, 0x00000070 },
10116 { MAC_TX_LENGTHS, 0x0000,
10117 0x00000000, 0x00003fff },
10118 { MAC_RX_MODE, TG3_FL_NOT_5705,
10119 0x00000000, 0x000007fc },
10120 { MAC_RX_MODE, TG3_FL_5705,
10121 0x00000000, 0x000007dc },
10122 { MAC_HASH_REG_0, 0x0000,
10123 0x00000000, 0xffffffff },
10124 { MAC_HASH_REG_1, 0x0000,
10125 0x00000000, 0xffffffff },
10126 { MAC_HASH_REG_2, 0x0000,
10127 0x00000000, 0xffffffff },
10128 { MAC_HASH_REG_3, 0x0000,
10129 0x00000000, 0xffffffff },
10130
10131 /* Receive Data and Receive BD Initiator Control Registers. */
10132 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10133 0x00000000, 0xffffffff },
10134 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10135 0x00000000, 0xffffffff },
10136 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10137 0x00000000, 0x00000003 },
10138 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10139 0x00000000, 0xffffffff },
10140 { RCVDBDI_STD_BD+0, 0x0000,
10141 0x00000000, 0xffffffff },
10142 { RCVDBDI_STD_BD+4, 0x0000,
10143 0x00000000, 0xffffffff },
10144 { RCVDBDI_STD_BD+8, 0x0000,
10145 0x00000000, 0xffff0002 },
10146 { RCVDBDI_STD_BD+0xc, 0x0000,
10147 0x00000000, 0xffffffff },
6aa20a22 10148
a71116d1
MC		 10149 /* Receive BD Initiator Control Registers. */
10150 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10151 0x00000000, 0xffffffff },
10152 { RCVBDI_STD_THRESH, TG3_FL_5705,
10153 0x00000000, 0x000003ff },
10154 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10155 0x00000000, 0xffffffff },
6aa20a22 10156
a71116d1
MC		 10157 /* Host Coalescing Control Registers. */
10158 { HOSTCC_MODE, TG3_FL_NOT_5705,
10159 0x00000000, 0x00000004 },
10160 { HOSTCC_MODE, TG3_FL_5705,
10161 0x00000000, 0x000000f6 },
10162 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10163 0x00000000, 0xffffffff },
10164 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10165 0x00000000, 0x000003ff },
10166 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10167 0x00000000, 0xffffffff },
10168 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10169 0x00000000, 0x000003ff },
10170 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10171 0x00000000, 0xffffffff },
10172 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10173 0x00000000, 0x000000ff },
10174 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10175 0x00000000, 0xffffffff },
10176 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10177 0x00000000, 0x000000ff },
10178 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10179 0x00000000, 0xffffffff },
10180 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10181 0x00000000, 0xffffffff },
10182 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10183 0x00000000, 0xffffffff },
10184 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10185 0x00000000, 0x000000ff },
10186 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10187 0x00000000, 0xffffffff },
10188 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10189 0x00000000, 0x000000ff },
10190 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10191 0x00000000, 0xffffffff },
10192 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10193 0x00000000, 0xffffffff },
10194 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10195 0x00000000, 0xffffffff },
10196 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10197 0x00000000, 0xffffffff },
10198 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10199 0x00000000, 0xffffffff },
10200 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10201 0xffffffff, 0x00000000 },
10202 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10203 0xffffffff, 0x00000000 },
10204
10205 /* Buffer Manager Control Registers. */
b16250e3 10206 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10207 0x00000000, 0x007fff80 },
b16250e3 10208 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10209 0x00000000, 0x007fffff },
10210 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10211 0x00000000, 0x0000003f },
10212 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10213 0x00000000, 0x000001ff },
10214 { BUFMGR_MB_HIGH_WATER, 0x0000,
10215 0x00000000, 0x000001ff },
10216 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10217 0xffffffff, 0x00000000 },
10218 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10219 0xffffffff, 0x00000000 },
6aa20a22 10220
a71116d1
MC		 10221 /* Mailbox Registers */
10222 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10223 0x00000000, 0x000001ff },
10224 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10225 0x00000000, 0x000001ff },
10226 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10227 0x00000000, 0x000007ff },
10228 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10229 0x00000000, 0x000001ff },
10230
10231 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10232 };
10233
b16250e3
MC		 10234 is_5705 = is_5750 = 0;
10235 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10236 is_5705 = 1;
b16250e3
MC		 10237 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10238 is_5750 = 1;
10239 }
a71116d1
MC		 10240
10241 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10242 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10243 continue;
10244
10245 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10246 continue;
10247
10248 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10249 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10250 continue;
10251
b16250e3
MC		 10252 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10253 continue;
10254
a71116d1
MC		 10255 offset = (u32) reg_tbl[i].offset;
10256 read_mask = reg_tbl[i].read_mask;
10257 write_mask = reg_tbl[i].write_mask;
10258
10259 /* Save the original register content */
10260 save_val = tr32(offset);
10261
10262 /* Determine the read-only value. */
10263 read_val = save_val & read_mask;
10264
10265 /* Write zero to the register, then make sure the read-only bits
10266 * are not changed and the read/write bits are all zeros.
10267 */
10268 tw32(offset, 0);
10269
10270 val = tr32(offset);
10271
10272 /* Test the read-only and read/write bits. */
10273 if (((val & read_mask) != read_val) || (val & write_mask))
10274 goto out;
10275
10276 /* Write ones to all the bits defined by RdMask and WrMask, then
10277 * make sure the read-only bits are not changed and the
10278 * read/write bits are all ones.
10279 */
10280 tw32(offset, read_mask | write_mask);
10281
10282 val = tr32(offset);
10283
10284 /* Test the read-only bits. */
10285 if ((val & read_mask) != read_val)
10286 goto out;
10287
10288 /* Test the read/write bits. */
10289 if ((val & write_mask) != write_mask)
10290 goto out;
10291
10292 tw32(offset, save_val);
10293 }
10294
10295 return 0;
10296
10297out:
9f88f29f
MC		 10298 if (netif_msg_hw(tp))
10299 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10300 offset);
a71116d1
MC		 10301 tw32(offset, save_val);
10302 return -EIO;
10303}
10304
7942e1db
MC		 10305static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10306{
f71e1309 10307 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10308 int i;
10309 u32 j;
10310
e9edda69 10311 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10312 for (j = 0; j < len; j += 4) {
10313 u32 val;
10314
10315 tg3_write_mem(tp, offset + j, test_pattern[i]);
10316 tg3_read_mem(tp, offset + j, &val);
10317 if (val != test_pattern[i])
10318 return -EIO;
10319 }
10320 }
10321 return 0;
10322}
10323
10324static int tg3_test_memory(struct tg3 *tp)
10325{
10326 static struct mem_entry {
10327 u32 offset;
10328 u32 len;
10329 } mem_tbl_570x[] = {
38690194 10330 { 0x00000000, 0x00b50},
7942e1db
MC		 10331 { 0x00002000, 0x1c000},
10332 { 0xffffffff, 0x00000}
10333 }, mem_tbl_5705[] = {
10334 { 0x00000100, 0x0000c},
10335 { 0x00000200, 0x00008},
7942e1db
MC		 10336 { 0x00004000, 0x00800},
10337 { 0x00006000, 0x01000},
10338 { 0x00008000, 0x02000},
10339 { 0x00010000, 0x0e000},
10340 { 0xffffffff, 0x00000}
79f4d13a
MC		 10341 }, mem_tbl_5755[] = {
10342 { 0x00000200, 0x00008},
10343 { 0x00004000, 0x00800},
10344 { 0x00006000, 0x00800},
10345 { 0x00008000, 0x02000},
10346 { 0x00010000, 0x0c000},
10347 { 0xffffffff, 0x00000}
b16250e3
MC		 10348 }, mem_tbl_5906[] = {
10349 { 0x00000200, 0x00008},
10350 { 0x00004000, 0x00400},
10351 { 0x00006000, 0x00400},
10352 { 0x00008000, 0x01000},
10353 { 0x00010000, 0x01000},
10354 { 0xffffffff, 0x00000}
7942e1db
MC		 10355 };
10356 struct mem_entry *mem_tbl;
10357 int err = 0;
10358 int i;
10359
321d32a0
MC		 10360 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10361 mem_tbl = mem_tbl_5755;
10362 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10363 mem_tbl = mem_tbl_5906;
10364 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10365 mem_tbl = mem_tbl_5705;
10366 else
7942e1db
MC		 10367 mem_tbl = mem_tbl_570x;
10368
10369 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10370 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10371 mem_tbl[i].len)) != 0)
10372 break;
10373 }
6aa20a22 10374
7942e1db
MC		 10375 return err;
10376}
10377
9f40dead
MC		 10378#define TG3_MAC_LOOPBACK 0
10379#define TG3_PHY_LOOPBACK 1
10380
10381static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10382{
9f40dead 10383 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10384 u32 desc_idx, coal_now;
c76949a6
MC		 10385 struct sk_buff *skb, *rx_skb;
10386 u8 *tx_data;
10387 dma_addr_t map;
10388 int num_pkts, tx_len, rx_len, i, err;
10389 struct tg3_rx_buffer_desc *desc;
898a56f8 10390 struct tg3_napi *tnapi, *rnapi;
21f581a5 10391 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10392
0c1d0e2b
MC		 10393 if (tp->irq_cnt > 1) {
10394 tnapi = &tp->napi[1];
10395 rnapi = &tp->napi[1];
10396 } else {
10397 tnapi = &tp->napi[0];
10398 rnapi = &tp->napi[0];
10399 }
fd2ce37f 10400 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10401
9f40dead 10402 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10403 /* HW errata - mac loopback fails in some cases on 5780.
10404 * Normal traffic and PHY loopback are not affected by
10405 * errata.
10406 */
10407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10408 return 0;
10409
9f40dead 10410 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10411 MAC_MODE_PORT_INT_LPBACK;
10412 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10413 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10414 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10415 mac_mode |= MAC_MODE_PORT_MODE_MII;
10416 else
10417 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10418 tw32(MAC_MODE, mac_mode);
10419 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10420 u32 val;
10421
7f97a4bd
MC		 10422 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10423 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10424 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10425 } else
10426 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10427
9ef8ca99
MC		 10428 tg3_phy_toggle_automdix(tp, 0);
10429
3f7045c1 10430 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10431 udelay(40);
5d64ad34 10432
e8f3f6ca 10433 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10434 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10436 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10437 mac_mode |= MAC_MODE_PORT_MODE_MII;
10438 } else
10439 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10440
c94e3941
MC		 10441 /* reset to prevent losing 1st rx packet intermittently */
10442 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10443 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10444 udelay(10);
10445 tw32_f(MAC_RX_MODE, tp->rx_mode);
10446 }
e8f3f6ca
MC		 10447 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10448 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10449 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10450 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10451 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10452 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10453 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10454 }
9f40dead 10455 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10456 }
10457 else
10458 return -EINVAL;
c76949a6
MC		 10459
10460 err = -EIO;
10461
c76949a6 10462 tx_len = 1514;
a20e9c62 10463 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10464 if (!skb)
10465 return -ENOMEM;
10466
c76949a6
MC		 10467 tx_data = skb_put(skb, tx_len);
10468 memcpy(tx_data, tp->dev->dev_addr, 6);
10469 memset(tx_data + 6, 0x0, 8);
10470
10471 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10472
10473 for (i = 14; i < tx_len; i++)
10474 tx_data[i] = (u8) (i & 0xff);
10475
a21771dd
MC		 10476 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10477 dev_kfree_skb(skb);
10478 return -EIO;
10479 }
c76949a6
MC		 10480
10481 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10482 rnapi->coal_now);
c76949a6
MC		 10483
10484 udelay(10);
10485
898a56f8 10486 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10487
c76949a6
MC		 10488 num_pkts = 0;
10489
a21771dd
MC		 10490 tg3_set_txd(tnapi, tnapi->tx_prod,
10491 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10492
f3f3f27e 10493 tnapi->tx_prod++;
c76949a6
MC		 10494 num_pkts++;
10495
f3f3f27e
MC		 10496 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10497 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10498
10499 udelay(10);
10500
303fc921
MC		 10501 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10502 for (i = 0; i < 35; i++) {
c76949a6 10503 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10504 coal_now);
c76949a6
MC		 10505
10506 udelay(10);
10507
898a56f8
MC		 10508 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10509 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10510 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10511 (rx_idx == (rx_start_idx + num_pkts)))
10512 break;
10513 }
10514
a21771dd 10515 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10516 dev_kfree_skb(skb);
10517
f3f3f27e 10518 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10519 goto out;
10520
10521 if (rx_idx != rx_start_idx + num_pkts)
10522 goto out;
10523
72334482 10524 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10525 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10526 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10527 if (opaque_key != RXD_OPAQUE_RING_STD)
10528 goto out;
10529
10530 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10531 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10532 goto out;
10533
10534 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10535 if (rx_len != tx_len)
10536 goto out;
10537
21f581a5 10538 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10539
21f581a5 10540 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10541 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10542
10543 for (i = 14; i < tx_len; i++) {
10544 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10545 goto out;
10546 }
10547 err = 0;
6aa20a22 10548
c76949a6
MC		 10549 /* tg3_free_rings will unmap and free the rx_skb */
10550out:
10551 return err;
10552}
10553
9f40dead
MC		 10554#define TG3_MAC_LOOPBACK_FAILED 1
10555#define TG3_PHY_LOOPBACK_FAILED 2
10556#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10557 TG3_PHY_LOOPBACK_FAILED)
10558
10559static int tg3_test_loopback(struct tg3 *tp)
10560{
10561 int err = 0;
9936bcf6 10562 u32 cpmuctrl = 0;
9f40dead
MC		 10563
10564 if (!netif_running(tp->dev))
10565 return TG3_LOOPBACK_FAILED;
10566
b9ec6c1b
MC		 10567 err = tg3_reset_hw(tp, 1);
10568 if (err)
10569 return TG3_LOOPBACK_FAILED;
9f40dead 10570
6833c043
MC		 10571 /* Turn off gphy autopowerdown. */
10572 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10573 tg3_phy_toggle_apd(tp, false);
10574
321d32a0 10575 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10576 int i;
10577 u32 status;
10578
10579 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10580
10581 /* Wait for up to 40 microseconds to acquire lock. */
10582 for (i = 0; i < 4; i++) {
10583 status = tr32(TG3_CPMU_MUTEX_GNT);
10584 if (status == CPMU_MUTEX_GNT_DRIVER)
10585 break;
10586 udelay(10);
10587 }
10588
10589 if (status != CPMU_MUTEX_GNT_DRIVER)
10590 return TG3_LOOPBACK_FAILED;
10591
b2a5c19c 10592 /* Turn off link-based power management. */
e875093c 10593 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10594 tw32(TG3_CPMU_CTRL,
10595 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10596 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10597 }
10598
9f40dead
MC		 10599 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10600 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10601
321d32a0 10602 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10603 tw32(TG3_CPMU_CTRL, cpmuctrl);
10604
10605 /* Release the mutex */
10606 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10607 }
10608
dd477003
MC		 10609 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10610 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10611 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10612 err |= TG3_PHY_LOOPBACK_FAILED;
10613 }
10614
6833c043
MC		 10615 /* Re-enable gphy autopowerdown. */
10616 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10617 tg3_phy_toggle_apd(tp, true);
10618
9f40dead
MC		 10619 return err;
10620}
10621
4cafd3f5
MC		 10622static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10623 u64 *data)
10624{
566f86ad
MC		 10625 struct tg3 *tp = netdev_priv(dev);
10626
bc1c7567
MC		 10627 if (tp->link_config.phy_is_low_power)
10628 tg3_set_power_state(tp, PCI_D0);
10629
566f86ad
MC		 10630 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10631
10632 if (tg3_test_nvram(tp) != 0) {
10633 etest->flags |= ETH_TEST_FL_FAILED;
10634 data[0] = 1;
10635 }
ca43007a
MC		 10636 if (tg3_test_link(tp) != 0) {
10637 etest->flags |= ETH_TEST_FL_FAILED;
10638 data[1] = 1;
10639 }
a71116d1 10640 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10641 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10642
10643 if (netif_running(dev)) {
b02fd9e3 10644 tg3_phy_stop(tp);
a71116d1 10645 tg3_netif_stop(tp);
bbe832c0
MC		 10646 irq_sync = 1;
10647 }
a71116d1 10648
bbe832c0 10649 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10650
10651 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10652 err = tg3_nvram_lock(tp);
a71116d1
MC		 10653 tg3_halt_cpu(tp, RX_CPU_BASE);
10654 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10655 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10656 if (!err)
10657 tg3_nvram_unlock(tp);
a71116d1 10658
d9ab5ad1
MC		 10659 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10660 tg3_phy_reset(tp);
10661
a71116d1
MC		 10662 if (tg3_test_registers(tp) != 0) {
10663 etest->flags |= ETH_TEST_FL_FAILED;
10664 data[2] = 1;
10665 }
7942e1db
MC		 10666 if (tg3_test_memory(tp) != 0) {
10667 etest->flags |= ETH_TEST_FL_FAILED;
10668 data[3] = 1;
10669 }
9f40dead 10670 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10671 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10672
f47c11ee
DM		 10673 tg3_full_unlock(tp);
10674
d4bc3927
MC		 10675 if (tg3_test_interrupt(tp) != 0) {
10676 etest->flags |= ETH_TEST_FL_FAILED;
10677 data[5] = 1;
10678 }
f47c11ee
DM		 10679
10680 tg3_full_lock(tp, 0);
d4bc3927 10681
a71116d1
MC		 10682 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10683 if (netif_running(dev)) {
10684 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10685 err2 = tg3_restart_hw(tp, 1);
10686 if (!err2)
b9ec6c1b 10687 tg3_netif_start(tp);
a71116d1 10688 }
f47c11ee
DM		 10689
10690 tg3_full_unlock(tp);
b02fd9e3
MC		 10691
10692 if (irq_sync && !err2)
10693 tg3_phy_start(tp);
a71116d1 10694 }
bc1c7567
MC		 10695 if (tp->link_config.phy_is_low_power)
10696 tg3_set_power_state(tp, PCI_D3hot);
10697
4cafd3f5
MC		 10698}
10699
1da177e4
LT		 10700static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10701{
10702 struct mii_ioctl_data *data = if_mii(ifr);
10703 struct tg3 *tp = netdev_priv(dev);
10704 int err;
10705
b02fd9e3 10706 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10707 struct phy_device *phydev;
b02fd9e3
MC		 10708 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10709 return -EAGAIN;
3f0e3ad7
MC		 10710 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10711 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10712 }
10713
1da177e4
LT		 10714 switch(cmd) {
10715 case SIOCGMIIPHY:
882e9793 10716 data->phy_id = tp->phy_addr;
1da177e4
LT		 10717
10718 /* fallthru */
10719 case SIOCGMIIREG: {
10720 u32 mii_regval;
10721
10722 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10723 break; /* We have no PHY */
10724
bc1c7567
MC		 10725 if (tp->link_config.phy_is_low_power)
10726 return -EAGAIN;
10727
f47c11ee 10728 spin_lock_bh(&tp->lock);
1da177e4 10729 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10730 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10731
10732 data->val_out = mii_regval;
10733
10734 return err;
10735 }
10736
10737 case SIOCSMIIREG:
10738 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10739 break; /* We have no PHY */
10740
bc1c7567
MC		 10741 if (tp->link_config.phy_is_low_power)
10742 return -EAGAIN;
10743
f47c11ee 10744 spin_lock_bh(&tp->lock);
1da177e4 10745 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10746 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10747
10748 return err;
10749
10750 default:
10751 /* do nothing */
10752 break;
10753 }
10754 return -EOPNOTSUPP;
10755}
10756
10757#if TG3_VLAN_TAG_USED
10758static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10759{
10760 struct tg3 *tp = netdev_priv(dev);
10761
844b3eed
MC		 10762 if (!netif_running(dev)) {
10763 tp->vlgrp = grp;
10764 return;
10765 }
10766
10767 tg3_netif_stop(tp);
29315e87 10768
f47c11ee 10769 tg3_full_lock(tp, 0);
1da177e4
LT		 10770
10771 tp->vlgrp = grp;
10772
10773 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10774 __tg3_set_rx_mode(dev);
10775
844b3eed 10776 tg3_netif_start(tp);
46966545
MC		 10777
10778 tg3_full_unlock(tp);
1da177e4 10779}
1da177e4
LT		 10780#endif
10781
15f9850d
DM		 10782static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10783{
10784 struct tg3 *tp = netdev_priv(dev);
10785
10786 memcpy(ec, &tp->coal, sizeof(*ec));
10787 return 0;
10788}
10789
d244c892
MC		 10790static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10791{
10792 struct tg3 *tp = netdev_priv(dev);
10793 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10794 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10795
10796 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10797 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10798 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10799 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10800 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10801 }
10802
10803 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10804 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10805 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10806 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10807 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10808 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10809 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10810 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10811 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10812 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10813 return -EINVAL;
10814
10815 /* No rx interrupts will be generated if both are zero */
10816 if ((ec->rx_coalesce_usecs == 0) &&
10817 (ec->rx_max_coalesced_frames == 0))
10818 return -EINVAL;
10819
10820 /* No tx interrupts will be generated if both are zero */
10821 if ((ec->tx_coalesce_usecs == 0) &&
10822 (ec->tx_max_coalesced_frames == 0))
10823 return -EINVAL;
10824
10825 /* Only copy relevant parameters, ignore all others. */
10826 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10827 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10828 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10829 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10830 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10831 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10832 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10833 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10834 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10835
10836 if (netif_running(dev)) {
10837 tg3_full_lock(tp, 0);
10838 __tg3_set_coalesce(tp, &tp->coal);
10839 tg3_full_unlock(tp);
10840 }
10841 return 0;
10842}
10843
7282d491 10844static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10845 .get_settings = tg3_get_settings,
10846 .set_settings = tg3_set_settings,
10847 .get_drvinfo = tg3_get_drvinfo,
10848 .get_regs_len = tg3_get_regs_len,
10849 .get_regs = tg3_get_regs,
10850 .get_wol = tg3_get_wol,
10851 .set_wol = tg3_set_wol,
10852 .get_msglevel = tg3_get_msglevel,
10853 .set_msglevel = tg3_set_msglevel,
10854 .nway_reset = tg3_nway_reset,
10855 .get_link = ethtool_op_get_link,
10856 .get_eeprom_len = tg3_get_eeprom_len,
10857 .get_eeprom = tg3_get_eeprom,
10858 .set_eeprom = tg3_set_eeprom,
10859 .get_ringparam = tg3_get_ringparam,
10860 .set_ringparam = tg3_set_ringparam,
10861 .get_pauseparam = tg3_get_pauseparam,
10862 .set_pauseparam = tg3_set_pauseparam,
10863 .get_rx_csum = tg3_get_rx_csum,
10864 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10865 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10866 .set_sg = ethtool_op_set_sg,
1da177e4 10867 .set_tso = tg3_set_tso,
4cafd3f5 10868 .self_test = tg3_self_test,
1da177e4 10869 .get_strings = tg3_get_strings,
4009a93d 10870 .phys_id = tg3_phys_id,
1da177e4 10871 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10872 .get_coalesce = tg3_get_coalesce,
d244c892 10873 .set_coalesce = tg3_set_coalesce,
b9f2c044 10874 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10875};
10876
10877static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10878{
1b27777a 10879 u32 cursize, val, magic;
1da177e4
LT		 10880
10881 tp->nvram_size = EEPROM_CHIP_SIZE;
10882
e4f34110 10883 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10884 return;
10885
b16250e3
MC		 10886 if ((magic != TG3_EEPROM_MAGIC) &&
10887 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10888 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10889 return;
10890
10891 /*
10892 * Size the chip by reading offsets at increasing powers of two.
10893 * When we encounter our validation signature, we know the addressing
10894 * has wrapped around, and thus have our chip size.
10895 */
1b27777a 10896 cursize = 0x10;
1da177e4
LT		 10897
10898 while (cursize < tp->nvram_size) {
e4f34110 10899 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10900 return;
10901
1820180b 10902 if (val == magic)
1da177e4
LT		 10903 break;
10904
10905 cursize <<= 1;
10906 }
10907
10908 tp->nvram_size = cursize;
10909}
6aa20a22 10910
1da177e4
LT		 10911static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10912{
10913 u32 val;
10914
df259d8c
MC		 10915 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10916 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10917 return;
10918
10919 /* Selfboot format */
1820180b 10920 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10921 tg3_get_eeprom_size(tp);
10922 return;
10923 }
10924
6d348f2c 10925 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10926 if (val != 0) {
6d348f2c
MC		 10927 /* This is confusing. We want to operate on the
10928 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10929 * call will read from NVRAM and byteswap the data
10930 * according to the byteswapping settings for all
10931 * other register accesses. This ensures the data we
10932 * want will always reside in the lower 16-bits.
10933 * However, the data in NVRAM is in LE format, which
10934 * means the data from the NVRAM read will always be
10935 * opposite the endianness of the CPU. The 16-bit
10936 * byteswap then brings the data to CPU endianness.
10937 */
10938 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10939 return;
10940 }
10941 }
fd1122a2 10942 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10943}
10944
10945static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10946{
10947 u32 nvcfg1;
10948
10949 nvcfg1 = tr32(NVRAM_CFG1);
10950 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10951 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10952 } else {
1da177e4
LT		 10953 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10954 tw32(NVRAM_CFG1, nvcfg1);
10955 }
10956
4c987487 10957 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10958 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10959 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10960 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10961 tp->nvram_jedecnum = JEDEC_ATMEL;
10962 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10963 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10964 break;
10965 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10966 tp->nvram_jedecnum = JEDEC_ATMEL;
10967 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10968 break;
10969 case FLASH_VENDOR_ATMEL_EEPROM:
10970 tp->nvram_jedecnum = JEDEC_ATMEL;
10971 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10972 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10973 break;
10974 case FLASH_VENDOR_ST:
10975 tp->nvram_jedecnum = JEDEC_ST;
10976 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10977 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10978 break;
10979 case FLASH_VENDOR_SAIFUN:
10980 tp->nvram_jedecnum = JEDEC_SAIFUN;
10981 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10982 break;
10983 case FLASH_VENDOR_SST_SMALL:
10984 case FLASH_VENDOR_SST_LARGE:
10985 tp->nvram_jedecnum = JEDEC_SST;
10986 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10987 break;
1da177e4 10988 }
8590a603 10989 } else {
1da177e4
LT		 10990 tp->nvram_jedecnum = JEDEC_ATMEL;
10991 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10992 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10993 }
10994}
10995
a1b950d5
MC		 10996static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10997{
10998 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10999 case FLASH_5752PAGE_SIZE_256:
11000 tp->nvram_pagesize = 256;
11001 break;
11002 case FLASH_5752PAGE_SIZE_512:
11003 tp->nvram_pagesize = 512;
11004 break;
11005 case FLASH_5752PAGE_SIZE_1K:
11006 tp->nvram_pagesize = 1024;
11007 break;
11008 case FLASH_5752PAGE_SIZE_2K:
11009 tp->nvram_pagesize = 2048;
11010 break;
11011 case FLASH_5752PAGE_SIZE_4K:
11012 tp->nvram_pagesize = 4096;
11013 break;
11014 case FLASH_5752PAGE_SIZE_264:
11015 tp->nvram_pagesize = 264;
11016 break;
11017 case FLASH_5752PAGE_SIZE_528:
11018 tp->nvram_pagesize = 528;
11019 break;
11020 }
11021}
11022
361b4ac2
MC		 11023static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11024{
11025 u32 nvcfg1;
11026
11027 nvcfg1 = tr32(NVRAM_CFG1);
11028
e6af301b
MC		 11029 /* NVRAM protection for TPM */
11030 if (nvcfg1 & (1 << 27))
f66a29b0 11031 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11032
361b4ac2 11033 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11034 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11035 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11036 tp->nvram_jedecnum = JEDEC_ATMEL;
11037 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11038 break;
11039 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11040 tp->nvram_jedecnum = JEDEC_ATMEL;
11041 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11042 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11043 break;
11044 case FLASH_5752VENDOR_ST_M45PE10:
11045 case FLASH_5752VENDOR_ST_M45PE20:
11046 case FLASH_5752VENDOR_ST_M45PE40:
11047 tp->nvram_jedecnum = JEDEC_ST;
11048 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11049 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11050 break;
361b4ac2
MC		 11051 }
11052
11053 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11054 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11055 } else {
361b4ac2
MC		 11056 /* For eeprom, set pagesize to maximum eeprom size */
11057 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11058
11059 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11060 tw32(NVRAM_CFG1, nvcfg1);
11061 }
11062}
11063
d3c7b886
MC		 11064static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11065{
989a9d23 11066 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11067
11068 nvcfg1 = tr32(NVRAM_CFG1);
11069
11070 /* NVRAM protection for TPM */
989a9d23 11071 if (nvcfg1 & (1 << 27)) {
f66a29b0 11072 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11073 protect = 1;
11074 }
d3c7b886 11075
989a9d23
MC		 11076 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11077 switch (nvcfg1) {
8590a603
MC		 11078 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11079 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11080 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11081 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11082 tp->nvram_jedecnum = JEDEC_ATMEL;
11083 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11084 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11085 tp->nvram_pagesize = 264;
11086 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11087 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11088 tp->nvram_size = (protect ? 0x3e200 :
11089 TG3_NVRAM_SIZE_512KB);
11090 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11091 tp->nvram_size = (protect ? 0x1f200 :
11092 TG3_NVRAM_SIZE_256KB);
11093 else
11094 tp->nvram_size = (protect ? 0x1f200 :
11095 TG3_NVRAM_SIZE_128KB);
11096 break;
11097 case FLASH_5752VENDOR_ST_M45PE10:
11098 case FLASH_5752VENDOR_ST_M45PE20:
11099 case FLASH_5752VENDOR_ST_M45PE40:
11100 tp->nvram_jedecnum = JEDEC_ST;
11101 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11102 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11103 tp->nvram_pagesize = 256;
11104 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11105 tp->nvram_size = (protect ?
11106 TG3_NVRAM_SIZE_64KB :
11107 TG3_NVRAM_SIZE_128KB);
11108 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11109 tp->nvram_size = (protect ?
11110 TG3_NVRAM_SIZE_64KB :
11111 TG3_NVRAM_SIZE_256KB);
11112 else
11113 tp->nvram_size = (protect ?
11114 TG3_NVRAM_SIZE_128KB :
11115 TG3_NVRAM_SIZE_512KB);
11116 break;
d3c7b886
MC		 11117 }
11118}
11119
1b27777a
MC		 11120static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11121{
11122 u32 nvcfg1;
11123
11124 nvcfg1 = tr32(NVRAM_CFG1);
11125
11126 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11127 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11128 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11129 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11130 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11131 tp->nvram_jedecnum = JEDEC_ATMEL;
11132 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11133 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11134
8590a603
MC		 11135 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11136 tw32(NVRAM_CFG1, nvcfg1);
11137 break;
11138 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11139 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11140 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11141 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11142 tp->nvram_jedecnum = JEDEC_ATMEL;
11143 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11144 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11145 tp->nvram_pagesize = 264;
11146 break;
11147 case FLASH_5752VENDOR_ST_M45PE10:
11148 case FLASH_5752VENDOR_ST_M45PE20:
11149 case FLASH_5752VENDOR_ST_M45PE40:
11150 tp->nvram_jedecnum = JEDEC_ST;
11151 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11152 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11153 tp->nvram_pagesize = 256;
11154 break;
1b27777a
MC		 11155 }
11156}
11157
6b91fa02
MC		 11158static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11159{
11160 u32 nvcfg1, protect = 0;
11161
11162 nvcfg1 = tr32(NVRAM_CFG1);
11163
11164 /* NVRAM protection for TPM */
11165 if (nvcfg1 & (1 << 27)) {
f66a29b0 11166 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11167 protect = 1;
11168 }
11169
11170 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11171 switch (nvcfg1) {
8590a603
MC		 11172 case FLASH_5761VENDOR_ATMEL_ADB021D:
11173 case FLASH_5761VENDOR_ATMEL_ADB041D:
11174 case FLASH_5761VENDOR_ATMEL_ADB081D:
11175 case FLASH_5761VENDOR_ATMEL_ADB161D:
11176 case FLASH_5761VENDOR_ATMEL_MDB021D:
11177 case FLASH_5761VENDOR_ATMEL_MDB041D:
11178 case FLASH_5761VENDOR_ATMEL_MDB081D:
11179 case FLASH_5761VENDOR_ATMEL_MDB161D:
11180 tp->nvram_jedecnum = JEDEC_ATMEL;
11181 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11182 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11183 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11184 tp->nvram_pagesize = 256;
11185 break;
11186 case FLASH_5761VENDOR_ST_A_M45PE20:
11187 case FLASH_5761VENDOR_ST_A_M45PE40:
11188 case FLASH_5761VENDOR_ST_A_M45PE80:
11189 case FLASH_5761VENDOR_ST_A_M45PE16:
11190 case FLASH_5761VENDOR_ST_M_M45PE20:
11191 case FLASH_5761VENDOR_ST_M_M45PE40:
11192 case FLASH_5761VENDOR_ST_M_M45PE80:
11193 case FLASH_5761VENDOR_ST_M_M45PE16:
11194 tp->nvram_jedecnum = JEDEC_ST;
11195 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11196 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11197 tp->nvram_pagesize = 256;
11198 break;
6b91fa02
MC		 11199 }
11200
11201 if (protect) {
11202 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11203 } else {
11204 switch (nvcfg1) {
8590a603
MC		 11205 case FLASH_5761VENDOR_ATMEL_ADB161D:
11206 case FLASH_5761VENDOR_ATMEL_MDB161D:
11207 case FLASH_5761VENDOR_ST_A_M45PE16:
11208 case FLASH_5761VENDOR_ST_M_M45PE16:
11209 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11210 break;
11211 case FLASH_5761VENDOR_ATMEL_ADB081D:
11212 case FLASH_5761VENDOR_ATMEL_MDB081D:
11213 case FLASH_5761VENDOR_ST_A_M45PE80:
11214 case FLASH_5761VENDOR_ST_M_M45PE80:
11215 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11216 break;
11217 case FLASH_5761VENDOR_ATMEL_ADB041D:
11218 case FLASH_5761VENDOR_ATMEL_MDB041D:
11219 case FLASH_5761VENDOR_ST_A_M45PE40:
11220 case FLASH_5761VENDOR_ST_M_M45PE40:
11221 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11222 break;
11223 case FLASH_5761VENDOR_ATMEL_ADB021D:
11224 case FLASH_5761VENDOR_ATMEL_MDB021D:
11225 case FLASH_5761VENDOR_ST_A_M45PE20:
11226 case FLASH_5761VENDOR_ST_M_M45PE20:
11227 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11228 break;
6b91fa02
MC		 11229 }
11230 }
11231}
11232
b5d3772c
MC		 11233static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11234{
11235 tp->nvram_jedecnum = JEDEC_ATMEL;
11236 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11237 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11238}
11239
321d32a0
MC		 11240static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11241{
11242 u32 nvcfg1;
11243
11244 nvcfg1 = tr32(NVRAM_CFG1);
11245
11246 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11247 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11248 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11249 tp->nvram_jedecnum = JEDEC_ATMEL;
11250 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11251 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11252
11253 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11254 tw32(NVRAM_CFG1, nvcfg1);
11255 return;
11256 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11257 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11258 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11259 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11260 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11261 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11262 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11263 tp->nvram_jedecnum = JEDEC_ATMEL;
11264 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11266
11267 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11268 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11269 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11270 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11271 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11272 break;
11273 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11274 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11275 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11276 break;
11277 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11278 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11279 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11280 break;
11281 }
11282 break;
11283 case FLASH_5752VENDOR_ST_M45PE10:
11284 case FLASH_5752VENDOR_ST_M45PE20:
11285 case FLASH_5752VENDOR_ST_M45PE40:
11286 tp->nvram_jedecnum = JEDEC_ST;
11287 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11288 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11289
11290 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11291 case FLASH_5752VENDOR_ST_M45PE10:
11292 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11293 break;
11294 case FLASH_5752VENDOR_ST_M45PE20:
11295 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11296 break;
11297 case FLASH_5752VENDOR_ST_M45PE40:
11298 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11299 break;
11300 }
11301 break;
11302 default:
df259d8c 11303 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11304 return;
11305 }
11306
a1b950d5
MC		 11307 tg3_nvram_get_pagesize(tp, nvcfg1);
11308 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11309 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11310}
11311
11312
11313static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11314{
11315 u32 nvcfg1;
11316
11317 nvcfg1 = tr32(NVRAM_CFG1);
11318
11319 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11320 case FLASH_5717VENDOR_ATMEL_EEPROM:
11321 case FLASH_5717VENDOR_MICRO_EEPROM:
11322 tp->nvram_jedecnum = JEDEC_ATMEL;
11323 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11324 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11325
11326 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11327 tw32(NVRAM_CFG1, nvcfg1);
11328 return;
11329 case FLASH_5717VENDOR_ATMEL_MDB011D:
11330 case FLASH_5717VENDOR_ATMEL_ADB011B:
11331 case FLASH_5717VENDOR_ATMEL_ADB011D:
11332 case FLASH_5717VENDOR_ATMEL_MDB021D:
11333 case FLASH_5717VENDOR_ATMEL_ADB021B:
11334 case FLASH_5717VENDOR_ATMEL_ADB021D:
11335 case FLASH_5717VENDOR_ATMEL_45USPT:
11336 tp->nvram_jedecnum = JEDEC_ATMEL;
11337 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11338 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11339
11340 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11341 case FLASH_5717VENDOR_ATMEL_MDB021D:
11342 case FLASH_5717VENDOR_ATMEL_ADB021B:
11343 case FLASH_5717VENDOR_ATMEL_ADB021D:
11344 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11345 break;
11346 default:
11347 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11348 break;
11349 }
321d32a0 11350 break;
a1b950d5
MC		 11351 case FLASH_5717VENDOR_ST_M_M25PE10:
11352 case FLASH_5717VENDOR_ST_A_M25PE10:
11353 case FLASH_5717VENDOR_ST_M_M45PE10:
11354 case FLASH_5717VENDOR_ST_A_M45PE10:
11355 case FLASH_5717VENDOR_ST_M_M25PE20:
11356 case FLASH_5717VENDOR_ST_A_M25PE20:
11357 case FLASH_5717VENDOR_ST_M_M45PE20:
11358 case FLASH_5717VENDOR_ST_A_M45PE20:
11359 case FLASH_5717VENDOR_ST_25USPT:
11360 case FLASH_5717VENDOR_ST_45USPT:
11361 tp->nvram_jedecnum = JEDEC_ST;
11362 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11363 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11364
11365 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11366 case FLASH_5717VENDOR_ST_M_M25PE20:
11367 case FLASH_5717VENDOR_ST_A_M25PE20:
11368 case FLASH_5717VENDOR_ST_M_M45PE20:
11369 case FLASH_5717VENDOR_ST_A_M45PE20:
11370 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11371 break;
11372 default:
11373 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11374 break;
11375 }
321d32a0 11376 break;
a1b950d5
MC		 11377 default:
11378 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11379 return;
321d32a0 11380 }
a1b950d5
MC		 11381
11382 tg3_nvram_get_pagesize(tp, nvcfg1);
11383 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11384 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11385}
11386
1da177e4
LT		 11387/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11388static void __devinit tg3_nvram_init(struct tg3 *tp)
11389{
1da177e4
LT		 11390 tw32_f(GRC_EEPROM_ADDR,
11391 (EEPROM_ADDR_FSM_RESET |
11392 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11393 EEPROM_ADDR_CLKPERD_SHIFT)));
11394
9d57f01c 11395 msleep(1);
1da177e4
LT		 11396
11397 /* Enable seeprom accesses. */
11398 tw32_f(GRC_LOCAL_CTRL,
11399 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11400 udelay(100);
11401
11402 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11403 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11404 tp->tg3_flags |= TG3_FLAG_NVRAM;
11405
ec41c7df
MC		 11406 if (tg3_nvram_lock(tp)) {
11407 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11408 "tg3_nvram_init failed.\n", tp->dev->name);
11409 return;
11410 }
e6af301b 11411 tg3_enable_nvram_access(tp);
1da177e4 11412
989a9d23
MC		 11413 tp->nvram_size = 0;
11414
361b4ac2
MC		 11415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11416 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11417 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11418 tg3_get_5755_nvram_info(tp);
d30cdd28 11419 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11420 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11422 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11423 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11424 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11425 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11426 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11427 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11428 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11429 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11430 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11431 else
11432 tg3_get_nvram_info(tp);
11433
989a9d23
MC		 11434 if (tp->nvram_size == 0)
11435 tg3_get_nvram_size(tp);
1da177e4 11436
e6af301b 11437 tg3_disable_nvram_access(tp);
381291b7 11438 tg3_nvram_unlock(tp);
1da177e4
LT		 11439
11440 } else {
11441 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11442
11443 tg3_get_eeprom_size(tp);
11444 }
11445}
11446
1da177e4
LT		 11447static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11448 u32 offset, u32 len, u8 *buf)
11449{
11450 int i, j, rc = 0;
11451 u32 val;
11452
11453 for (i = 0; i < len; i += 4) {
b9fc7dc5 11454 u32 addr;
a9dc529d 11455 __be32 data;
1da177e4
LT		 11456
11457 addr = offset + i;
11458
11459 memcpy(&data, buf + i, 4);
11460
62cedd11
MC		 11461 /*
11462 * The SEEPROM interface expects the data to always be opposite
11463 * the native endian format. We accomplish this by reversing
11464 * all the operations that would have been performed on the
11465 * data from a call to tg3_nvram_read_be32().
11466 */
11467 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11468
11469 val = tr32(GRC_EEPROM_ADDR);
11470 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11471
11472 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11473 EEPROM_ADDR_READ);
11474 tw32(GRC_EEPROM_ADDR, val |
11475 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11476 (addr & EEPROM_ADDR_ADDR_MASK) |
11477 EEPROM_ADDR_START |
11478 EEPROM_ADDR_WRITE);
6aa20a22 11479
9d57f01c 11480 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11481 val = tr32(GRC_EEPROM_ADDR);
11482
11483 if (val & EEPROM_ADDR_COMPLETE)
11484 break;
9d57f01c 11485 msleep(1);
1da177e4
LT		 11486 }
11487 if (!(val & EEPROM_ADDR_COMPLETE)) {
11488 rc = -EBUSY;
11489 break;
11490 }
11491 }
11492
11493 return rc;
11494}
11495
11496/* offset and length are dword aligned */
11497static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11498 u8 *buf)
11499{
11500 int ret = 0;
11501 u32 pagesize = tp->nvram_pagesize;
11502 u32 pagemask = pagesize - 1;
11503 u32 nvram_cmd;
11504 u8 *tmp;
11505
11506 tmp = kmalloc(pagesize, GFP_KERNEL);
11507 if (tmp == NULL)
11508 return -ENOMEM;
11509
11510 while (len) {
11511 int j;
e6af301b 11512 u32 phy_addr, page_off, size;
1da177e4
LT		 11513
11514 phy_addr = offset & ~pagemask;
6aa20a22 11515
1da177e4 11516 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11517 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11518 (__be32 *) (tmp + j));
11519 if (ret)
1da177e4
LT		 11520 break;
11521 }
11522 if (ret)
11523 break;
11524
11525 page_off = offset & pagemask;
11526 size = pagesize;
11527 if (len < size)
11528 size = len;
11529
11530 len -= size;
11531
11532 memcpy(tmp + page_off, buf, size);
11533
11534 offset = offset + (pagesize - page_off);
11535
e6af301b 11536 tg3_enable_nvram_access(tp);
1da177e4
LT		 11537
11538 /*
11539 * Before we can erase the flash page, we need
11540 * to issue a special "write enable" command.
11541 */
11542 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11543
11544 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11545 break;
11546
11547 /* Erase the target page */
11548 tw32(NVRAM_ADDR, phy_addr);
11549
11550 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11551 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11552
11553 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11554 break;
11555
11556 /* Issue another write enable to start the write. */
11557 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11558
11559 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11560 break;
11561
11562 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11563 __be32 data;
1da177e4 11564
b9fc7dc5 11565 data = *((__be32 *) (tmp + j));
a9dc529d 11566
b9fc7dc5 11567 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11568
11569 tw32(NVRAM_ADDR, phy_addr + j);
11570
11571 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11572 NVRAM_CMD_WR;
11573
11574 if (j == 0)
11575 nvram_cmd |= NVRAM_CMD_FIRST;
11576 else if (j == (pagesize - 4))
11577 nvram_cmd |= NVRAM_CMD_LAST;
11578
11579 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11580 break;
11581 }
11582 if (ret)
11583 break;
11584 }
11585
11586 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11587 tg3_nvram_exec_cmd(tp, nvram_cmd);
11588
11589 kfree(tmp);
11590
11591 return ret;
11592}
11593
11594/* offset and length are dword aligned */
11595static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11596 u8 *buf)
11597{
11598 int i, ret = 0;
11599
11600 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11601 u32 page_off, phy_addr, nvram_cmd;
11602 __be32 data;
1da177e4
LT		 11603
11604 memcpy(&data, buf + i, 4);
b9fc7dc5 11605 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11606
11607 page_off = offset % tp->nvram_pagesize;
11608
1820180b 11609 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11610
11611 tw32(NVRAM_ADDR, phy_addr);
11612
11613 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11614
11615 if ((page_off == 0) || (i == 0))
11616 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11617 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11618 nvram_cmd |= NVRAM_CMD_LAST;
11619
11620 if (i == (len - 4))
11621 nvram_cmd |= NVRAM_CMD_LAST;
11622
321d32a0
MC		 11623 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11624 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11625 (tp->nvram_jedecnum == JEDEC_ST) &&
11626 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11627
11628 if ((ret = tg3_nvram_exec_cmd(tp,
11629 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11630 NVRAM_CMD_DONE)))
11631
11632 break;
11633 }
11634 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11635 /* We always do complete word writes to eeprom. */
11636 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11637 }
11638
11639 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11640 break;
11641 }
11642 return ret;
11643}
11644
11645/* offset and length are dword aligned */
11646static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11647{
11648 int ret;
11649
1da177e4 11650 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11651 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11652 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11653 udelay(40);
11654 }
11655
11656 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11657 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11658 }
11659 else {
11660 u32 grc_mode;
11661
ec41c7df
MC		 11662 ret = tg3_nvram_lock(tp);
11663 if (ret)
11664 return ret;
1da177e4 11665
e6af301b
MC		 11666 tg3_enable_nvram_access(tp);
11667 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11668 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11669 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11670
11671 grc_mode = tr32(GRC_MODE);
11672 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11673
11674 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11675 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11676
11677 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11678 buf);
11679 }
11680 else {
11681 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11682 buf);
11683 }
11684
11685 grc_mode = tr32(GRC_MODE);
11686 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11687
e6af301b 11688 tg3_disable_nvram_access(tp);
1da177e4
LT		 11689 tg3_nvram_unlock(tp);
11690 }
11691
11692 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11693 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11694 udelay(40);
11695 }
11696
11697 return ret;
11698}
11699
11700struct subsys_tbl_ent {
11701 u16 subsys_vendor, subsys_devid;
11702 u32 phy_id;
11703};
11704
11705static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11706 /* Broadcom boards. */
11707 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11708 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11709 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11710 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11711 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11712 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11713 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11714 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11715 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11716 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11717 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11718
11719 /* 3com boards. */
11720 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11721 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11722 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11723 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11724 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11725
11726 /* DELL boards. */
11727 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11728 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11729 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11730 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11731
11732 /* Compaq boards. */
11733 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11734 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11735 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11736 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11737 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11738
11739 /* IBM boards. */
11740 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11741};
11742
11743static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11744{
11745 int i;
11746
11747 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11748 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11749 tp->pdev->subsystem_vendor) &&
11750 (subsys_id_to_phy_id[i].subsys_devid ==
11751 tp->pdev->subsystem_device))
11752 return &subsys_id_to_phy_id[i];
11753 }
11754 return NULL;
11755}
11756
7d0c41ef 11757static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11758{
1da177e4 11759 u32 val;
caf636c7
MC		 11760 u16 pmcsr;
11761
11762 /* On some early chips the SRAM cannot be accessed in D3hot state,
11763 * so need make sure we're in D0.
11764 */
11765 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11766 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11767 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11768 msleep(1);
7d0c41ef
MC		 11769
11770 /* Make sure register accesses (indirect or otherwise)
11771 * will function correctly.
11772 */
11773 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11774 tp->misc_host_ctrl);
1da177e4 11775
f49639e6
DM		 11776 /* The memory arbiter has to be enabled in order for SRAM accesses
11777 * to succeed. Normally on powerup the tg3 chip firmware will make
11778 * sure it is enabled, but other entities such as system netboot
11779 * code might disable it.
11780 */
11781 val = tr32(MEMARB_MODE);
11782 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11783
1da177e4 11784 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11785 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11786
a85feb8c
GZ		 11787 /* Assume an onboard device and WOL capable by default. */
11788 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11789
b5d3772c 11790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11791 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11792 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11793 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11794 }
0527ba35
MC		 11795 val = tr32(VCPU_CFGSHDW);
11796 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11797 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11798 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11799 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11800 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11801 goto done;
b5d3772c
MC		 11802 }
11803
1da177e4
LT		 11804 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11805 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11806 u32 nic_cfg, led_cfg;
a9daf367 11807 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11808 int eeprom_phy_serdes = 0;
1da177e4
LT		 11809
11810 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11811 tp->nic_sram_data_cfg = nic_cfg;
11812
11813 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11814 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11815 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11816 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11817 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11818 (ver > 0) && (ver < 0x100))
11819 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11820
a9daf367
MC		 11821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11822 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11823
1da177e4
LT		 11824 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11825 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11826 eeprom_phy_serdes = 1;
11827
11828 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11829 if (nic_phy_id != 0) {
11830 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11831 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11832
11833 eeprom_phy_id = (id1 >> 16) << 10;
11834 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11835 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11836 } else
11837 eeprom_phy_id = 0;
11838
7d0c41ef 11839 tp->phy_id = eeprom_phy_id;
747e8f8b 11840 if (eeprom_phy_serdes) {
a4e2b347 11841 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11842 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11843 else
11844 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11845 }
7d0c41ef 11846
cbf46853 11847 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11848 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11849 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11850 else
1da177e4
LT		 11851 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11852
11853 switch (led_cfg) {
11854 default:
11855 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11856 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11857 break;
11858
11859 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11860 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11861 break;
11862
11863 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11864 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11865
11866 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11867 * read on some older 5700/5701 bootcode.
11868 */
11869 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11870 ASIC_REV_5700 ||
11871 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11872 ASIC_REV_5701)
11873 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11874
1da177e4
LT		 11875 break;
11876
11877 case SHASTA_EXT_LED_SHARED:
11878 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11879 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11880 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11881 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11882 LED_CTRL_MODE_PHY_2);
11883 break;
11884
11885 case SHASTA_EXT_LED_MAC:
11886 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11887 break;
11888
11889 case SHASTA_EXT_LED_COMBO:
11890 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11891 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11892 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11893 LED_CTRL_MODE_PHY_2);
11894 break;
11895
855e1111 11896 }
1da177e4
LT		 11897
11898 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11900 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11901 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11902
b2a5c19c
MC		 11903 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11904 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11905
9d26e213 11906 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11907 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11908 if ((tp->pdev->subsystem_vendor ==
11909 PCI_VENDOR_ID_ARIMA) &&
11910 (tp->pdev->subsystem_device == 0x205a ||
11911 tp->pdev->subsystem_device == 0x2063))
11912 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11913 } else {
f49639e6 11914 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11915 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11916 }
1da177e4
LT		 11917
11918 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11919 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11920 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11921 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11922 }
b2b98d4a
MC		 11923
11924 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11925 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11926 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11927
a85feb8c
GZ		 11928 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11929 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11930 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11931
12dac075 11932 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11933 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11934 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11935
1da177e4
LT		 11936 if (cfg2 & (1 << 17))
11937 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11938
11939 /* serdes signal pre-emphasis in register 0x590 set by */
11940 /* bootcode if bit 18 is set */
11941 if (cfg2 & (1 << 18))
11942 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11943
321d32a0
MC		 11944 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11945 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11946 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11947 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11948
8ed5d97e
MC		 11949 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11950 u32 cfg3;
11951
11952 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11953 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11954 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11955 }
a9daf367
MC		 11956
11957 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11958 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11959 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11960 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11961 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11962 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11963 }
05ac4cb7
MC		 11964done:
11965 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11966 device_set_wakeup_enable(&tp->pdev->dev,
11967 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11968}
11969
b2a5c19c
MC		 11970static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11971{
11972 int i;
11973 u32 val;
11974
11975 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11976 tw32(OTP_CTRL, cmd);
11977
11978 /* Wait for up to 1 ms for command to execute. */
11979 for (i = 0; i < 100; i++) {
11980 val = tr32(OTP_STATUS);
11981 if (val & OTP_STATUS_CMD_DONE)
11982 break;
11983 udelay(10);
11984 }
11985
11986 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11987}
11988
11989/* Read the gphy configuration from the OTP region of the chip. The gphy
11990 * configuration is a 32-bit value that straddles the alignment boundary.
11991 * We do two 32-bit reads and then shift and merge the results.
11992 */
11993static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11994{
11995 u32 bhalf_otp, thalf_otp;
11996
11997 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11998
11999 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12000 return 0;
12001
12002 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12003
12004 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12005 return 0;
12006
12007 thalf_otp = tr32(OTP_READ_DATA);
12008
12009 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12010
12011 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12012 return 0;
12013
12014 bhalf_otp = tr32(OTP_READ_DATA);
12015
12016 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12017}
12018
7d0c41ef
MC		 12019static int __devinit tg3_phy_probe(struct tg3 *tp)
12020{
12021 u32 hw_phy_id_1, hw_phy_id_2;
12022 u32 hw_phy_id, hw_phy_id_masked;
12023 int err;
1da177e4 12024
b02fd9e3
MC		 12025 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12026 return tg3_phy_init(tp);
12027
1da177e4 12028 /* Reading the PHY ID register can conflict with ASF
877d0310 12029 * firmware access to the PHY hardware.
1da177e4
LT		 12030 */
12031 err = 0;
0d3031d9
MC		 12032 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12033 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12034 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12035 } else {
12036 /* Now read the physical PHY_ID from the chip and verify
12037 * that it is sane. If it doesn't look good, we fall back
12038 * to either the hard-coded table based PHY_ID and failing
12039 * that the value found in the eeprom area.
12040 */
12041 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12042 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12043
12044 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12045 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12046 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12047
12048 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12049 }
12050
12051 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12052 tp->phy_id = hw_phy_id;
12053 if (hw_phy_id_masked == PHY_ID_BCM8002)
12054 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12055 else
12056 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12057 } else {
7d0c41ef
MC		 12058 if (tp->phy_id != PHY_ID_INVALID) {
12059 /* Do nothing, phy ID already set up in
12060 * tg3_get_eeprom_hw_cfg().
12061 */
1da177e4
LT		 12062 } else {
12063 struct subsys_tbl_ent *p;
12064
12065 /* No eeprom signature? Try the hardcoded
12066 * subsys device table.
12067 */
12068 p = lookup_by_subsys(tp);
12069 if (!p)
12070 return -ENODEV;
12071
12072 tp->phy_id = p->phy_id;
12073 if (!tp->phy_id ||
12074 tp->phy_id == PHY_ID_BCM8002)
12075 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12076 }
12077 }
12078
747e8f8b 12079 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12080 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12081 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12082 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12083
12084 tg3_readphy(tp, MII_BMSR, &bmsr);
12085 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12086 (bmsr & BMSR_LSTATUS))
12087 goto skip_phy_reset;
6aa20a22 12088
1da177e4
LT		 12089 err = tg3_phy_reset(tp);
12090 if (err)
12091 return err;
12092
12093 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12094 ADVERTISE_100HALF | ADVERTISE_100FULL |
12095 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12096 tg3_ctrl = 0;
12097 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12098 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12099 MII_TG3_CTRL_ADV_1000_FULL);
12100 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12101 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12102 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12103 MII_TG3_CTRL_ENABLE_AS_MASTER);
12104 }
12105
3600d918
MC		 12106 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12107 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12108 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12109 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12110 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12111
12112 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12113 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12114
12115 tg3_writephy(tp, MII_BMCR,
12116 BMCR_ANENABLE | BMCR_ANRESTART);
12117 }
12118 tg3_phy_set_wirespeed(tp);
12119
12120 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12121 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12122 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12123 }
12124
12125skip_phy_reset:
12126 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12127 err = tg3_init_5401phy_dsp(tp);
12128 if (err)
12129 return err;
12130 }
12131
12132 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12133 err = tg3_init_5401phy_dsp(tp);
12134 }
12135
747e8f8b 12136 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12137 tp->link_config.advertising =
12138 (ADVERTISED_1000baseT_Half |
12139 ADVERTISED_1000baseT_Full |
12140 ADVERTISED_Autoneg |
12141 ADVERTISED_FIBRE);
12142 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12143 tp->link_config.advertising &=
12144 ~(ADVERTISED_1000baseT_Half |
12145 ADVERTISED_1000baseT_Full);
12146
12147 return err;
12148}
12149
12150static void __devinit tg3_read_partno(struct tg3 *tp)
12151{
6d348f2c 12152 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12153 unsigned int i;
1b27777a 12154 u32 magic;
1da177e4 12155
df259d8c
MC		 12156 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12157 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12158 goto out_not_found;
1da177e4 12159
1820180b 12160 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12161 for (i = 0; i < 256; i += 4) {
12162 u32 tmp;
1da177e4 12163
6d348f2c
MC		 12164 /* The data is in little-endian format in NVRAM.
12165 * Use the big-endian read routines to preserve
12166 * the byte order as it exists in NVRAM.
12167 */
12168 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12169 goto out_not_found;
12170
6d348f2c 12171 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12172 }
12173 } else {
12174 int vpd_cap;
12175
12176 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12177 for (i = 0; i < 256; i += 4) {
12178 u32 tmp, j = 0;
b9fc7dc5 12179 __le32 v;
1b27777a
MC		 12180 u16 tmp16;
12181
12182 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12183 i);
12184 while (j++ < 100) {
12185 pci_read_config_word(tp->pdev, vpd_cap +
12186 PCI_VPD_ADDR, &tmp16);
12187 if (tmp16 & 0x8000)
12188 break;
12189 msleep(1);
12190 }
f49639e6
DM		 12191 if (!(tmp16 & 0x8000))
12192 goto out_not_found;
12193
1b27777a
MC		 12194 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12195 &tmp);
b9fc7dc5 12196 v = cpu_to_le32(tmp);
6d348f2c 12197 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12198 }
1da177e4
LT		 12199 }
12200
12201 /* Now parse and find the part number. */
af2c6a4a 12202 for (i = 0; i < 254; ) {
1da177e4 12203 unsigned char val = vpd_data[i];
af2c6a4a 12204 unsigned int block_end;
1da177e4
LT		 12205
12206 if (val == 0x82 || val == 0x91) {
12207 i = (i + 3 +
12208 (vpd_data[i + 1] +
12209 (vpd_data[i + 2] << 8)));
12210 continue;
12211 }
12212
12213 if (val != 0x90)
12214 goto out_not_found;
12215
12216 block_end = (i + 3 +
12217 (vpd_data[i + 1] +
12218 (vpd_data[i + 2] << 8)));
12219 i += 3;
af2c6a4a
MC		 12220
12221 if (block_end > 256)
12222 goto out_not_found;
12223
12224 while (i < (block_end - 2)) {
1da177e4
LT		 12225 if (vpd_data[i + 0] == 'P' &&
12226 vpd_data[i + 1] == 'N') {
12227 int partno_len = vpd_data[i + 2];
12228
af2c6a4a
MC		 12229 i += 3;
12230 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12231 goto out_not_found;
12232
12233 memcpy(tp->board_part_number,
af2c6a4a 12234 &vpd_data[i], partno_len);
1da177e4
LT		 12235
12236 /* Success. */
12237 return;
12238 }
af2c6a4a 12239 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12240 }
12241
12242 /* Part number not found. */
12243 goto out_not_found;
12244 }
12245
12246out_not_found:
b5d3772c
MC		 12247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12248 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12249 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12250 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12251 strcpy(tp->board_part_number, "BCM57780");
12252 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12253 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12254 strcpy(tp->board_part_number, "BCM57760");
12255 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12256 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12257 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12258 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12259 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12260 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12261 else
12262 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12263}
12264
9c8a620e
MC		 12265static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12266{
12267 u32 val;
12268
e4f34110 12269 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12270 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12271 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12272 val != 0)
12273 return 0;
12274
12275 return 1;
12276}
12277
acd9c119
MC		 12278static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12279{
ff3a7cb2 12280 u32 val, offset, start, ver_offset;
acd9c119 12281 int i;
ff3a7cb2 12282 bool newver = false;
acd9c119
MC		 12283
12284 if (tg3_nvram_read(tp, 0xc, &offset) ||
12285 tg3_nvram_read(tp, 0x4, &start))
12286 return;
12287
12288 offset = tg3_nvram_logical_addr(tp, offset);
12289
ff3a7cb2 12290 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12291 return;
12292
ff3a7cb2
MC		 12293 if ((val & 0xfc000000) == 0x0c000000) {
12294 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12295 return;
12296
ff3a7cb2
MC		 12297 if (val == 0)
12298 newver = true;
12299 }
12300
12301 if (newver) {
12302 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12303 return;
12304
12305 offset = offset + ver_offset - start;
12306 for (i = 0; i < 16; i += 4) {
12307 __be32 v;
12308 if (tg3_nvram_read_be32(tp, offset + i, &v))
12309 return;
12310
12311 memcpy(tp->fw_ver + i, &v, sizeof(v));
12312 }
12313 } else {
12314 u32 major, minor;
12315
12316 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12317 return;
12318
12319 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12320 TG3_NVM_BCVER_MAJSFT;
12321 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12322 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12323 }
12324}
12325
a6f6cb1c
MC		 12326static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12327{
12328 u32 val, major, minor;
12329
12330 /* Use native endian representation */
12331 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12332 return;
12333
12334 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12335 TG3_NVM_HWSB_CFG1_MAJSFT;
12336 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12337 TG3_NVM_HWSB_CFG1_MINSFT;
12338
12339 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12340}
12341
dfe00d7d
MC		 12342static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12343{
12344 u32 offset, major, minor, build;
12345
12346 tp->fw_ver[0] = 's';
12347 tp->fw_ver[1] = 'b';
12348 tp->fw_ver[2] = '\0';
12349
12350 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12351 return;
12352
12353 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12354 case TG3_EEPROM_SB_REVISION_0:
12355 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12356 break;
12357 case TG3_EEPROM_SB_REVISION_2:
12358 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12359 break;
12360 case TG3_EEPROM_SB_REVISION_3:
12361 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12362 break;
12363 default:
12364 return;
12365 }
12366
e4f34110 12367 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12368 return;
12369
12370 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12371 TG3_EEPROM_SB_EDH_BLD_SHFT;
12372 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12373 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12374 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12375
12376 if (minor > 99 || build > 26)
12377 return;
12378
12379 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12380
12381 if (build > 0) {
12382 tp->fw_ver[8] = 'a' + build - 1;
12383 tp->fw_ver[9] = '\0';
12384 }
12385}
12386
acd9c119 12387static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12388{
12389 u32 val, offset, start;
acd9c119 12390 int i, vlen;
9c8a620e
MC		 12391
12392 for (offset = TG3_NVM_DIR_START;
12393 offset < TG3_NVM_DIR_END;
12394 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12395 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12396 return;
12397
9c8a620e
MC		 12398 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12399 break;
12400 }
12401
12402 if (offset == TG3_NVM_DIR_END)
12403 return;
12404
12405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12406 start = 0x08000000;
e4f34110 12407 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12408 return;
12409
e4f34110 12410 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12411 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12412 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12413 return;
12414
12415 offset += val - start;
12416
acd9c119 12417 vlen = strlen(tp->fw_ver);
9c8a620e 12418
acd9c119
MC		 12419 tp->fw_ver[vlen++] = ',';
12420 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12421
12422 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12423 __be32 v;
12424 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12425 return;
12426
b9fc7dc5 12427 offset += sizeof(v);
c4e6575c 12428
acd9c119
MC		 12429 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12430 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12431 break;
c4e6575c 12432 }
9c8a620e 12433
acd9c119
MC		 12434 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12435 vlen += sizeof(v);
c4e6575c 12436 }
acd9c119
MC		 12437}
12438
7fd76445
MC		 12439static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12440{
12441 int vlen;
12442 u32 apedata;
12443
12444 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12445 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12446 return;
12447
12448 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12449 if (apedata != APE_SEG_SIG_MAGIC)
12450 return;
12451
12452 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12453 if (!(apedata & APE_FW_STATUS_READY))
12454 return;
12455
12456 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12457
12458 vlen = strlen(tp->fw_ver);
12459
12460 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12461 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12462 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12463 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12464 (apedata & APE_FW_VERSION_BLDMSK));
12465}
12466
acd9c119
MC		 12467static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12468{
12469 u32 val;
12470
df259d8c
MC		 12471 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12472 tp->fw_ver[0] = 's';
12473 tp->fw_ver[1] = 'b';
12474 tp->fw_ver[2] = '\0';
12475
12476 return;
12477 }
12478
acd9c119
MC		 12479 if (tg3_nvram_read(tp, 0, &val))
12480 return;
12481
12482 if (val == TG3_EEPROM_MAGIC)
12483 tg3_read_bc_ver(tp);
12484 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12485 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12486 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12487 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12488 else
12489 return;
12490
12491 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12492 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12493 return;
12494
12495 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12496
12497 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12498}
12499
7544b097
MC		 12500static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12501
1da177e4
LT		 12502static int __devinit tg3_get_invariants(struct tg3 *tp)
12503{
12504 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12505 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12506 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12507 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12508 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12509 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12510 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12511 { },
12512 };
12513 u32 misc_ctrl_reg;
1da177e4
LT		 12514 u32 pci_state_reg, grc_misc_cfg;
12515 u32 val;
12516 u16 pci_cmd;
5e7dfd0f 12517 int err;
1da177e4 12518
1da177e4
LT		 12519 /* Force memory write invalidate off. If we leave it on,
12520 * then on 5700_BX chips we have to enable a workaround.
12521 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12522 * to match the cacheline size. The Broadcom driver have this
12523 * workaround but turns MWI off all the times so never uses
12524 * it. This seems to suggest that the workaround is insufficient.
12525 */
12526 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12527 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12528 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12529
12530 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12531 * has the register indirect write enable bit set before
12532 * we try to access any of the MMIO registers. It is also
12533 * critical that the PCI-X hw workaround situation is decided
12534 * before that as well.
12535 */
12536 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12537 &misc_ctrl_reg);
12538
12539 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12540 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12542 u32 prod_id_asic_rev;
12543
f6eb9b1f
MC		 12544 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12545 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12546 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12547 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12548 pci_read_config_dword(tp->pdev,
12549 TG3PCI_GEN2_PRODID_ASICREV,
12550 &prod_id_asic_rev);
12551 else
12552 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12553 &prod_id_asic_rev);
12554
321d32a0 12555 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12556 }
1da177e4 12557
ff645bec
MC		 12558 /* Wrong chip ID in 5752 A0. This code can be removed later
12559 * as A0 is not in production.
12560 */
12561 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12562 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12563
6892914f
MC		 12564 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12565 * we need to disable memory and use config. cycles
12566 * only to access all registers. The 5702/03 chips
12567 * can mistakenly decode the special cycles from the
12568 * ICH chipsets as memory write cycles, causing corruption
12569 * of register and memory space. Only certain ICH bridges
12570 * will drive special cycles with non-zero data during the
12571 * address phase which can fall within the 5703's address
12572 * range. This is not an ICH bug as the PCI spec allows
12573 * non-zero address during special cycles. However, only
12574 * these ICH bridges are known to drive non-zero addresses
12575 * during special cycles.
12576 *
12577 * Since special cycles do not cross PCI bridges, we only
12578 * enable this workaround if the 5703 is on the secondary
12579 * bus of these ICH bridges.
12580 */
12581 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12582 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12583 static struct tg3_dev_id {
12584 u32 vendor;
12585 u32 device;
12586 u32 rev;
12587 } ich_chipsets[] = {
12588 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12589 PCI_ANY_ID },
12590 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12591 PCI_ANY_ID },
12592 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12593 0xa },
12594 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12595 PCI_ANY_ID },
12596 { },
12597 };
12598 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12599 struct pci_dev *bridge = NULL;
12600
12601 while (pci_id->vendor != 0) {
12602 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12603 bridge);
12604 if (!bridge) {
12605 pci_id++;
12606 continue;
12607 }
12608 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12609 if (bridge->revision > pci_id->rev)
6892914f
MC		 12610 continue;
12611 }
12612 if (bridge->subordinate &&
12613 (bridge->subordinate->number ==
12614 tp->pdev->bus->number)) {
12615
12616 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12617 pci_dev_put(bridge);
12618 break;
12619 }
12620 }
12621 }
12622
41588ba1
MC		 12623 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12624 static struct tg3_dev_id {
12625 u32 vendor;
12626 u32 device;
12627 } bridge_chipsets[] = {
12628 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12629 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12630 { },
12631 };
12632 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12633 struct pci_dev *bridge = NULL;
12634
12635 while (pci_id->vendor != 0) {
12636 bridge = pci_get_device(pci_id->vendor,
12637 pci_id->device,
12638 bridge);
12639 if (!bridge) {
12640 pci_id++;
12641 continue;
12642 }
12643 if (bridge->subordinate &&
12644 (bridge->subordinate->number <=
12645 tp->pdev->bus->number) &&
12646 (bridge->subordinate->subordinate >=
12647 tp->pdev->bus->number)) {
12648 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12649 pci_dev_put(bridge);
12650 break;
12651 }
12652 }
12653 }
12654
4a29cc2e
MC		 12655 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12656 * DMA addresses > 40-bit. This bridge may have other additional
12657 * 57xx devices behind it in some 4-port NIC designs for example.
12658 * Any tg3 device found behind the bridge will also need the 40-bit
12659 * DMA workaround.
12660 */
a4e2b347
MC		 12661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12663 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12664 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12665 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12666 }
4a29cc2e
MC		 12667 else {
12668 struct pci_dev *bridge = NULL;
12669
12670 do {
12671 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12672 PCI_DEVICE_ID_SERVERWORKS_EPB,
12673 bridge);
12674 if (bridge && bridge->subordinate &&
12675 (bridge->subordinate->number <=
12676 tp->pdev->bus->number) &&
12677 (bridge->subordinate->subordinate >=
12678 tp->pdev->bus->number)) {
12679 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12680 pci_dev_put(bridge);
12681 break;
12682 }
12683 } while (bridge);
12684 }
4cf78e4f 12685
1da177e4
LT		 12686 /* Initialize misc host control in PCI block. */
12687 tp->misc_host_ctrl |= (misc_ctrl_reg &
12688 MISC_HOST_CTRL_CHIPREV);
12689 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12690 tp->misc_host_ctrl);
12691
f6eb9b1f
MC		 12692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12694 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12695 tp->pdev_peer = tg3_find_peer(tp);
12696
321d32a0
MC		 12697 /* Intentionally exclude ASIC_REV_5906 */
12698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12705 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12706
12707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12710 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12711 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12712 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12713
1b440c56
JL		 12714 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12715 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12716 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12717
027455ad
MC		 12718 /* 5700 B0 chips do not support checksumming correctly due
12719 * to hardware bugs.
12720 */
12721 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12722 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12723 else {
12724 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12725 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12726 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12727 tp->dev->features |= NETIF_F_IPV6_CSUM;
12728 }
12729
507399f1 12730 /* Determine TSO capabilities */
e849cdc3
MC		 12731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12732 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12733 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12734 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 12735 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12736 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12737 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12739 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12740 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12741 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12742 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12743 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12744 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12746 tp->fw_needed = FIRMWARE_TG3TSO5;
12747 else
12748 tp->fw_needed = FIRMWARE_TG3TSO;
12749 }
12750
12751 tp->irq_max = 1;
12752
5a6f3074 12753 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12754 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12755 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12756 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12757 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12758 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12759 tp->pdev_peer == tp->pdev))
12760 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12761
321d32a0 12762 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12763 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 12764 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12765 }
4f125f42 12766
507399f1
MC		 12767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12768 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12769 tp->irq_max = TG3_IRQ_MAX_VECS;
12770 }
f6eb9b1f 12771 }
0e1406dd 12772
615774fe
MC		 12773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12774 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12775 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12776 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12777 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12778 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 12779 }
f6eb9b1f 12780
f51f3562 12781 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12782 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12783 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12784 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12785
52f4490c
MC		 12786 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12787 &pci_state_reg);
12788
5e7dfd0f
MC		 12789 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12790 if (tp->pcie_cap != 0) {
12791 u16 lnkctl;
12792
1da177e4 12793 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12794
12795 pcie_set_readrq(tp->pdev, 4096);
12796
5e7dfd0f
MC		 12797 pci_read_config_word(tp->pdev,
12798 tp->pcie_cap + PCI_EXP_LNKCTL,
12799 &lnkctl);
12800 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12802 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12805 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12806 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12807 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12808 }
52f4490c 12809 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12810 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12811 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12812 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12813 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12814 if (!tp->pcix_cap) {
12815 printk(KERN_ERR PFX "Cannot find PCI-X "
12816 "capability, aborting.\n");
12817 return -EIO;
12818 }
12819
12820 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12821 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12822 }
1da177e4 12823
399de50b
MC		 12824 /* If we have an AMD 762 or VIA K8T800 chipset, write
12825 * reordering to the mailbox registers done by the host
12826 * controller can cause major troubles. We read back from
12827 * every mailbox register write to force the writes to be
12828 * posted to the chip in order.
12829 */
12830 if (pci_dev_present(write_reorder_chipsets) &&
12831 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12832 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12833
69fc4053
MC		 12834 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12835 &tp->pci_cacheline_sz);
12836 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12837 &tp->pci_lat_timer);
1da177e4
LT		 12838 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12839 tp->pci_lat_timer < 64) {
12840 tp->pci_lat_timer = 64;
69fc4053
MC		 12841 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12842 tp->pci_lat_timer);
1da177e4
LT		 12843 }
12844
52f4490c
MC		 12845 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12846 /* 5700 BX chips need to have their TX producer index
12847 * mailboxes written twice to workaround a bug.
12848 */
12849 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12850
52f4490c 12851 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12852 *
12853 * The workaround is to use indirect register accesses
12854 * for all chip writes not to mailbox registers.
12855 */
52f4490c 12856 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12857 u32 pm_reg;
1da177e4
LT		 12858
12859 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12860
12861 /* The chip can have it's power management PCI config
12862 * space registers clobbered due to this bug.
12863 * So explicitly force the chip into D0 here.
12864 */
9974a356
MC		 12865 pci_read_config_dword(tp->pdev,
12866 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12867 &pm_reg);
12868 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12869 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12870 pci_write_config_dword(tp->pdev,
12871 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12872 pm_reg);
12873
12874 /* Also, force SERR#/PERR# in PCI command. */
12875 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12876 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12877 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12878 }
12879 }
12880
1da177e4
LT		 12881 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12882 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12883 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12884 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12885
12886 /* Chip-specific fixup from Broadcom driver */
12887 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12888 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12889 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12890 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12891 }
12892
1ee582d8 12893 /* Default fast path register access methods */
20094930 12894 tp->read32 = tg3_read32;
1ee582d8 12895 tp->write32 = tg3_write32;
09ee929c 12896 tp->read32_mbox = tg3_read32;
20094930 12897 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12898 tp->write32_tx_mbox = tg3_write32;
12899 tp->write32_rx_mbox = tg3_write32;
12900
12901 /* Various workaround register access methods */
12902 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12903 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12904 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12905 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12906 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12907 /*
12908 * Back to back register writes can cause problems on these
12909 * chips, the workaround is to read back all reg writes
12910 * except those to mailbox regs.
12911 *
12912 * See tg3_write_indirect_reg32().
12913 */
1ee582d8 12914 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12915 }
12916
1ee582d8
MC		 12917 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12918 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12919 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12920 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12921 tp->write32_rx_mbox = tg3_write_flush_reg32;
12922 }
20094930 12923
6892914f
MC		 12924 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12925 tp->read32 = tg3_read_indirect_reg32;
12926 tp->write32 = tg3_write_indirect_reg32;
12927 tp->read32_mbox = tg3_read_indirect_mbox;
12928 tp->write32_mbox = tg3_write_indirect_mbox;
12929 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12930 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12931
12932 iounmap(tp->regs);
22abe310 12933 tp->regs = NULL;
6892914f
MC		 12934
12935 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12936 pci_cmd &= ~PCI_COMMAND_MEMORY;
12937 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12938 }
b5d3772c
MC		 12939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12940 tp->read32_mbox = tg3_read32_mbox_5906;
12941 tp->write32_mbox = tg3_write32_mbox_5906;
12942 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12943 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12944 }
6892914f 12945
bbadf503
MC		 12946 if (tp->write32 == tg3_write_indirect_reg32 ||
12947 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12948 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12950 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12951
7d0c41ef 12952 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12953 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12954 * determined before calling tg3_set_power_state() so that
12955 * we know whether or not to switch out of Vaux power.
12956 * When the flag is set, it means that GPIO1 is used for eeprom
12957 * write protect and also implies that it is a LOM where GPIOs
12958 * are not used to switch power.
6aa20a22 12959 */
7d0c41ef
MC		 12960 tg3_get_eeprom_hw_cfg(tp);
12961
0d3031d9
MC		 12962 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12963 /* Allow reads and writes to the
12964 * APE register and memory space.
12965 */
12966 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12967 PCISTATE_ALLOW_APE_SHMEM_WR;
12968 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12969 pci_state_reg);
12970 }
12971
9936bcf6 12972 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12977 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12978
314fba34
MC		 12979 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12980 * GPIO1 driven high will bring 5700's external PHY out of reset.
12981 * It is also used as eeprom write protect on LOMs.
12982 */
12983 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12984 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12985 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12986 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12987 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12988 /* Unused GPIO3 must be driven as output on 5752 because there
12989 * are no pull-up resistors on unused GPIO pins.
12990 */
12991 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12992 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12993
321d32a0
MC		 12994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12996 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12997
8d519ab2
MC		 12998 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12999 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13000 /* Turn off the debug UART. */
13001 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13002 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13003 /* Keep VMain power. */
13004 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13005 GRC_LCLCTRL_GPIO_OUTPUT0;
13006 }
13007
1da177e4 13008 /* Force the chip into D0. */
bc1c7567 13009 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13010 if (err) {
13011 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13012 pci_name(tp->pdev));
13013 return err;
13014 }
13015
1da177e4
LT		 13016 /* Derive initial jumbo mode from MTU assigned in
13017 * ether_setup() via the alloc_etherdev() call
13018 */
0f893dc6 13019 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13020 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13021 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13022
13023 /* Determine WakeOnLan speed to use. */
13024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13025 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13026 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13027 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13028 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13029 } else {
13030 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13031 }
13032
7f97a4bd
MC		 13033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13034 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13035
1da177e4
LT		 13036 /* A few boards don't want Ethernet@WireSpeed phy feature */
13037 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13038 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13039 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13040 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13041 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13042 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13043 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13044
13045 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13046 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13047 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13048 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13049 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13050
321d32a0 13051 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13052 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13053 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 13054 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13055 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 13056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13060 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13061 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13062 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13063 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13064 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13065 } else
c424cb24
MC		 13066 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13067 }
1da177e4 13068
b2a5c19c
MC		 13069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13070 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13071 tp->phy_otp = tg3_read_otp_phycfg(tp);
13072 if (tp->phy_otp == 0)
13073 tp->phy_otp = TG3_OTP_DEFAULT;
13074 }
13075
f51f3562 13076 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13077 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13078 else
13079 tp->mi_mode = MAC_MI_MODE_BASE;
13080
1da177e4 13081 tp->coalesce_mode = 0;
1da177e4
LT		 13082 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13083 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13084 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13085
321d32a0
MC		 13086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13088 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13089
158d7abd
MC		 13090 err = tg3_mdio_init(tp);
13091 if (err)
13092 return err;
1da177e4
LT		 13093
13094 /* Initialize data/descriptor byte/word swapping. */
13095 val = tr32(GRC_MODE);
13096 val &= GRC_MODE_HOST_STACKUP;
13097 tw32(GRC_MODE, val | tp->grc_mode);
13098
13099 tg3_switch_clocks(tp);
13100
13101 /* Clear this out for sanity. */
13102 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13103
13104 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13105 &pci_state_reg);
13106 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13107 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13108 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13109
13110 if (chiprevid == CHIPREV_ID_5701_A0 ||
13111 chiprevid == CHIPREV_ID_5701_B0 ||
13112 chiprevid == CHIPREV_ID_5701_B2 ||
13113 chiprevid == CHIPREV_ID_5701_B5) {
13114 void __iomem *sram_base;
13115
13116 /* Write some dummy words into the SRAM status block
13117 * area, see if it reads back correctly. If the return
13118 * value is bad, force enable the PCIX workaround.
13119 */
13120 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13121
13122 writel(0x00000000, sram_base);
13123 writel(0x00000000, sram_base + 4);
13124 writel(0xffffffff, sram_base + 4);
13125 if (readl(sram_base) != 0x00000000)
13126 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13127 }
13128 }
13129
13130 udelay(50);
13131 tg3_nvram_init(tp);
13132
13133 grc_misc_cfg = tr32(GRC_MISC_CFG);
13134 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13135
1da177e4
LT		 13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13137 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13138 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13139 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13140
fac9b83e
DM		 13141 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13142 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13143 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13144 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13145 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13146 HOSTCC_MODE_CLRTICK_TXBD);
13147
13148 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13149 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13150 tp->misc_host_ctrl);
13151 }
13152
3bda1258
MC		 13153 /* Preserve the APE MAC_MODE bits */
13154 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13155 tp->mac_mode = tr32(MAC_MODE) |
13156 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13157 else
13158 tp->mac_mode = TG3_DEF_MAC_MODE;
13159
1da177e4
LT		 13160 /* these are limited to 10/100 only */
13161 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13162 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13163 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13164 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13165 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13166 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13167 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13168 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13169 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13170 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13171 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13172 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13173 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13174 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13175
13176 err = tg3_phy_probe(tp);
13177 if (err) {
13178 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13179 pci_name(tp->pdev), err);
13180 /* ... but do not return immediately ... */
b02fd9e3 13181 tg3_mdio_fini(tp);
1da177e4
LT		 13182 }
13183
13184 tg3_read_partno(tp);
c4e6575c 13185 tg3_read_fw_ver(tp);
1da177e4
LT		 13186
13187 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13188 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13189 } else {
13190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13191 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13192 else
13193 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13194 }
13195
13196 /* 5700 {AX,BX} chips have a broken status block link
13197 * change bit implementation, so we must use the
13198 * status register in those cases.
13199 */
13200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13201 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13202 else
13203 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13204
13205 /* The led_ctrl is set during tg3_phy_probe, here we might
13206 * have to force the link status polling mechanism based
13207 * upon subsystem IDs.
13208 */
13209 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13211 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13212 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13213 TG3_FLAG_USE_LINKCHG_REG);
13214 }
13215
13216 /* For all SERDES we poll the MAC status register. */
13217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13218 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13219 else
13220 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13221
ad829268 13222 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13224 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13225 tp->rx_offset = 0;
13226
f92905de
MC		 13227 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13228
13229 /* Increment the rx prod index on the rx std ring by at most
13230 * 8 for these chips to workaround hw errata.
13231 */
13232 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13233 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13234 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13235 tp->rx_std_max_post = 8;
13236
8ed5d97e
MC		 13237 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13238 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13239 PCIE_PWR_MGMT_L1_THRESH_MSK;
13240
1da177e4
LT		 13241 return err;
13242}
13243
49b6e95f 13244#ifdef CONFIG_SPARC
1da177e4
LT		 13245static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13246{
13247 struct net_device *dev = tp->dev;
13248 struct pci_dev *pdev = tp->pdev;
49b6e95f 13249 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13250 const unsigned char *addr;
49b6e95f
DM		 13251 int len;
13252
13253 addr = of_get_property(dp, "local-mac-address", &len);
13254 if (addr && len == 6) {
13255 memcpy(dev->dev_addr, addr, 6);
13256 memcpy(dev->perm_addr, dev->dev_addr, 6);
13257 return 0;
1da177e4
LT		 13258 }
13259 return -ENODEV;
13260}
13261
13262static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13263{
13264 struct net_device *dev = tp->dev;
13265
13266 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13267 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13268 return 0;
13269}
13270#endif
13271
13272static int __devinit tg3_get_device_address(struct tg3 *tp)
13273{
13274 struct net_device *dev = tp->dev;
13275 u32 hi, lo, mac_offset;
008652b3 13276 int addr_ok = 0;
1da177e4 13277
49b6e95f 13278#ifdef CONFIG_SPARC
1da177e4
LT		 13279 if (!tg3_get_macaddr_sparc(tp))
13280 return 0;
13281#endif
13282
13283 mac_offset = 0x7c;
f49639e6 13284 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13285 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13286 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13287 mac_offset = 0xcc;
13288 if (tg3_nvram_lock(tp))
13289 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13290 else
13291 tg3_nvram_unlock(tp);
a1b950d5
MC		 13292 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13293 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13294 mac_offset = 0xcc;
13295 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13296 mac_offset = 0x10;
1da177e4
LT		 13297
13298 /* First try to get it from MAC address mailbox. */
13299 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13300 if ((hi >> 16) == 0x484b) {
13301 dev->dev_addr[0] = (hi >> 8) & 0xff;
13302 dev->dev_addr[1] = (hi >> 0) & 0xff;
13303
13304 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13305 dev->dev_addr[2] = (lo >> 24) & 0xff;
13306 dev->dev_addr[3] = (lo >> 16) & 0xff;
13307 dev->dev_addr[4] = (lo >> 8) & 0xff;
13308 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13309
008652b3
MC		 13310 /* Some old bootcode may report a 0 MAC address in SRAM */
13311 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13312 }
13313 if (!addr_ok) {
13314 /* Next, try NVRAM. */
df259d8c
MC		 13315 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13316 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13317 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13318 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13319 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13320 }
13321 /* Finally just fetch it out of the MAC control regs. */
13322 else {
13323 hi = tr32(MAC_ADDR_0_HIGH);
13324 lo = tr32(MAC_ADDR_0_LOW);
13325
13326 dev->dev_addr[5] = lo & 0xff;
13327 dev->dev_addr[4] = (lo >> 8) & 0xff;
13328 dev->dev_addr[3] = (lo >> 16) & 0xff;
13329 dev->dev_addr[2] = (lo >> 24) & 0xff;
13330 dev->dev_addr[1] = hi & 0xff;
13331 dev->dev_addr[0] = (hi >> 8) & 0xff;
13332 }
1da177e4
LT		 13333 }
13334
13335 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13336#ifdef CONFIG_SPARC
1da177e4
LT		 13337 if (!tg3_get_default_macaddr_sparc(tp))
13338 return 0;
13339#endif
13340 return -EINVAL;
13341 }
2ff43697 13342 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13343 return 0;
13344}
13345
59e6b434
DM		 13346#define BOUNDARY_SINGLE_CACHELINE 1
13347#define BOUNDARY_MULTI_CACHELINE 2
13348
13349static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13350{
13351 int cacheline_size;
13352 u8 byte;
13353 int goal;
13354
13355 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13356 if (byte == 0)
13357 cacheline_size = 1024;
13358 else
13359 cacheline_size = (int) byte * 4;
13360
13361 /* On 5703 and later chips, the boundary bits have no
13362 * effect.
13363 */
13364 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13365 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13366 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13367 goto out;
13368
13369#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13370 goal = BOUNDARY_MULTI_CACHELINE;
13371#else
13372#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13373 goal = BOUNDARY_SINGLE_CACHELINE;
13374#else
13375 goal = 0;
13376#endif
13377#endif
13378
cbf9ca6c
MC		 13379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13380 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13381 goto out;
13382 }
13383
59e6b434
DM		 13384 if (!goal)
13385 goto out;
13386
13387 /* PCI controllers on most RISC systems tend to disconnect
13388 * when a device tries to burst across a cache-line boundary.
13389 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13390 *
13391 * Unfortunately, for PCI-E there are only limited
13392 * write-side controls for this, and thus for reads
13393 * we will still get the disconnects. We'll also waste
13394 * these PCI cycles for both read and write for chips
13395 * other than 5700 and 5701 which do not implement the
13396 * boundary bits.
13397 */
13398 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13399 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13400 switch (cacheline_size) {
13401 case 16:
13402 case 32:
13403 case 64:
13404 case 128:
13405 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13406 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13407 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13408 } else {
13409 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13410 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13411 }
13412 break;
13413
13414 case 256:
13415 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13416 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13417 break;
13418
13419 default:
13420 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13421 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13422 break;
855e1111 13423 }
59e6b434
DM		 13424 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13425 switch (cacheline_size) {
13426 case 16:
13427 case 32:
13428 case 64:
13429 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13430 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13431 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13432 break;
13433 }
13434 /* fallthrough */
13435 case 128:
13436 default:
13437 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13438 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13439 break;
855e1111 13440 }
59e6b434
DM		 13441 } else {
13442 switch (cacheline_size) {
13443 case 16:
13444 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13445 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13446 DMA_RWCTRL_WRITE_BNDRY_16);
13447 break;
13448 }
13449 /* fallthrough */
13450 case 32:
13451 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13452 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13453 DMA_RWCTRL_WRITE_BNDRY_32);
13454 break;
13455 }
13456 /* fallthrough */
13457 case 64:
13458 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13459 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13460 DMA_RWCTRL_WRITE_BNDRY_64);
13461 break;
13462 }
13463 /* fallthrough */
13464 case 128:
13465 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13466 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13467 DMA_RWCTRL_WRITE_BNDRY_128);
13468 break;
13469 }
13470 /* fallthrough */
13471 case 256:
13472 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13473 DMA_RWCTRL_WRITE_BNDRY_256);
13474 break;
13475 case 512:
13476 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13477 DMA_RWCTRL_WRITE_BNDRY_512);
13478 break;
13479 case 1024:
13480 default:
13481 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13482 DMA_RWCTRL_WRITE_BNDRY_1024);
13483 break;
855e1111 13484 }
59e6b434
DM		 13485 }
13486
13487out:
13488 return val;
13489}
13490
1da177e4
LT		 13491static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13492{
13493 struct tg3_internal_buffer_desc test_desc;
13494 u32 sram_dma_descs;
13495 int i, ret;
13496
13497 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13498
13499 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13500 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13501 tw32(RDMAC_STATUS, 0);
13502 tw32(WDMAC_STATUS, 0);
13503
13504 tw32(BUFMGR_MODE, 0);
13505 tw32(FTQ_RESET, 0);
13506
13507 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13508 test_desc.addr_lo = buf_dma & 0xffffffff;
13509 test_desc.nic_mbuf = 0x00002100;
13510 test_desc.len = size;
13511
13512 /*
13513 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13514 * the *second* time the tg3 driver was getting loaded after an
13515 * initial scan.
13516 *
13517 * Broadcom tells me:
13518 * ...the DMA engine is connected to the GRC block and a DMA
13519 * reset may affect the GRC block in some unpredictable way...
13520 * The behavior of resets to individual blocks has not been tested.
13521 *
13522 * Broadcom noted the GRC reset will also reset all sub-components.
13523 */
13524 if (to_device) {
13525 test_desc.cqid_sqid = (13 << 8) | 2;
13526
13527 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13528 udelay(40);
13529 } else {
13530 test_desc.cqid_sqid = (16 << 8) | 7;
13531
13532 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13533 udelay(40);
13534 }
13535 test_desc.flags = 0x00000005;
13536
13537 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13538 u32 val;
13539
13540 val = *(((u32 *)&test_desc) + i);
13541 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13542 sram_dma_descs + (i * sizeof(u32)));
13543 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13544 }
13545 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13546
13547 if (to_device) {
13548 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13549 } else {
13550 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13551 }
13552
13553 ret = -ENODEV;
13554 for (i = 0; i < 40; i++) {
13555 u32 val;
13556
13557 if (to_device)
13558 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13559 else
13560 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13561 if ((val & 0xffff) == sram_dma_descs) {
13562 ret = 0;
13563 break;
13564 }
13565
13566 udelay(100);
13567 }
13568
13569 return ret;
13570}
13571
ded7340d 13572#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13573
13574static int __devinit tg3_test_dma(struct tg3 *tp)
13575{
13576 dma_addr_t buf_dma;
59e6b434 13577 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13578 int ret = 0;
1da177e4
LT		 13579
13580 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13581 if (!buf) {
13582 ret = -ENOMEM;
13583 goto out_nofree;
13584 }
13585
13586 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13587 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13588
59e6b434 13589 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13590
cbf9ca6c
MC		 13591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13592 goto out;
13593
1da177e4
LT		 13594 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13595 /* DMA read watermark not used on PCIE */
13596 tp->dma_rwctrl |= 0x00180000;
13597 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13598 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13599 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13600 tp->dma_rwctrl |= 0x003f0000;
13601 else
13602 tp->dma_rwctrl |= 0x003f000f;
13603 } else {
13604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13605 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13606 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13607 u32 read_water = 0x7;
1da177e4 13608
4a29cc2e
MC		 13609 /* If the 5704 is behind the EPB bridge, we can
13610 * do the less restrictive ONE_DMA workaround for
13611 * better performance.
13612 */
13613 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13614 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13615 tp->dma_rwctrl |= 0x8000;
13616 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13617 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13618
49afdeb6
MC		 13619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13620 read_water = 4;
59e6b434 13621 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13622 tp->dma_rwctrl |=
13623 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13624 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13625 (1 << 23);
4cf78e4f
MC		 13626 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13627 /* 5780 always in PCIX mode */
13628 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13629 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13630 /* 5714 always in PCIX mode */
13631 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13632 } else {
13633 tp->dma_rwctrl |= 0x001b000f;
13634 }
13635 }
13636
13637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13639 tp->dma_rwctrl &= 0xfffffff0;
13640
13641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13643 /* Remove this if it causes problems for some boards. */
13644 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13645
13646 /* On 5700/5701 chips, we need to set this bit.
13647 * Otherwise the chip will issue cacheline transactions
13648 * to streamable DMA memory with not all the byte
13649 * enables turned on. This is an error on several
13650 * RISC PCI controllers, in particular sparc64.
13651 *
13652 * On 5703/5704 chips, this bit has been reassigned
13653 * a different meaning. In particular, it is used
13654 * on those chips to enable a PCI-X workaround.
13655 */
13656 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13657 }
13658
13659 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13660
13661#if 0
13662 /* Unneeded, already done by tg3_get_invariants. */
13663 tg3_switch_clocks(tp);
13664#endif
13665
1da177e4
LT		 13666 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13667 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13668 goto out;
13669
59e6b434
DM		 13670 /* It is best to perform DMA test with maximum write burst size
13671 * to expose the 5700/5701 write DMA bug.
13672 */
13673 saved_dma_rwctrl = tp->dma_rwctrl;
13674 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13675 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13676
1da177e4
LT		 13677 while (1) {
13678 u32 *p = buf, i;
13679
13680 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13681 p[i] = i;
13682
13683 /* Send the buffer to the chip. */
13684 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13685 if (ret) {
13686 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13687 break;
13688 }
13689
13690#if 0
13691 /* validate data reached card RAM correctly. */
13692 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13693 u32 val;
13694 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13695 if (le32_to_cpu(val) != p[i]) {
13696 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13697 /* ret = -ENODEV here? */
13698 }
13699 p[i] = 0;
13700 }
13701#endif
13702 /* Now read it back. */
13703 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13704 if (ret) {
13705 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13706
13707 break;
13708 }
13709
13710 /* Verify it. */
13711 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13712 if (p[i] == i)
13713 continue;
13714
59e6b434
DM		 13715 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13716 DMA_RWCTRL_WRITE_BNDRY_16) {
13717 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13718 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13719 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13720 break;
13721 } else {
13722 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13723 ret = -ENODEV;
13724 goto out;
13725 }
13726 }
13727
13728 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13729 /* Success. */
13730 ret = 0;
13731 break;
13732 }
13733 }
59e6b434
DM		 13734 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13735 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13736 static struct pci_device_id dma_wait_state_chipsets[] = {
13737 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13738 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13739 { },
13740 };
13741
59e6b434 13742 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13743 * now look for chipsets that are known to expose the
13744 * DMA bug without failing the test.
59e6b434 13745 */
6d1cfbab
MC		 13746 if (pci_dev_present(dma_wait_state_chipsets)) {
13747 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13748 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13749 }
13750 else
13751 /* Safe to use the calculated DMA boundary. */
13752 tp->dma_rwctrl = saved_dma_rwctrl;
13753
59e6b434
DM		 13754 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13755 }
1da177e4
LT		 13756
13757out:
13758 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13759out_nofree:
13760 return ret;
13761}
13762
13763static void __devinit tg3_init_link_config(struct tg3 *tp)
13764{
13765 tp->link_config.advertising =
13766 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13767 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13768 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13769 ADVERTISED_Autoneg | ADVERTISED_MII);
13770 tp->link_config.speed = SPEED_INVALID;
13771 tp->link_config.duplex = DUPLEX_INVALID;
13772 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13773 tp->link_config.active_speed = SPEED_INVALID;
13774 tp->link_config.active_duplex = DUPLEX_INVALID;
13775 tp->link_config.phy_is_low_power = 0;
13776 tp->link_config.orig_speed = SPEED_INVALID;
13777 tp->link_config.orig_duplex = DUPLEX_INVALID;
13778 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13779}
13780
13781static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13782{
f6eb9b1f
MC		 13783 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13784 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13785 tp->bufmgr_config.mbuf_read_dma_low_water =
13786 DEFAULT_MB_RDMA_LOW_WATER_5705;
13787 tp->bufmgr_config.mbuf_mac_rx_low_water =
13788 DEFAULT_MB_MACRX_LOW_WATER_5705;
13789 tp->bufmgr_config.mbuf_high_water =
13790 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13792 tp->bufmgr_config.mbuf_mac_rx_low_water =
13793 DEFAULT_MB_MACRX_LOW_WATER_5906;
13794 tp->bufmgr_config.mbuf_high_water =
13795 DEFAULT_MB_HIGH_WATER_5906;
13796 }
fdfec172
MC		 13797
13798 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13799 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13800 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13801 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13802 tp->bufmgr_config.mbuf_high_water_jumbo =
13803 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13804 } else {
13805 tp->bufmgr_config.mbuf_read_dma_low_water =
13806 DEFAULT_MB_RDMA_LOW_WATER;
13807 tp->bufmgr_config.mbuf_mac_rx_low_water =
13808 DEFAULT_MB_MACRX_LOW_WATER;
13809 tp->bufmgr_config.mbuf_high_water =
13810 DEFAULT_MB_HIGH_WATER;
13811
13812 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13813 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13814 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13815 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13816 tp->bufmgr_config.mbuf_high_water_jumbo =
13817 DEFAULT_MB_HIGH_WATER_JUMBO;
13818 }
1da177e4
LT		 13819
13820 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13821 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13822}
13823
13824static char * __devinit tg3_phy_string(struct tg3 *tp)
13825{
13826 switch (tp->phy_id & PHY_ID_MASK) {
13827 case PHY_ID_BCM5400: return "5400";
13828 case PHY_ID_BCM5401: return "5401";
13829 case PHY_ID_BCM5411: return "5411";
13830 case PHY_ID_BCM5701: return "5701";
13831 case PHY_ID_BCM5703: return "5703";
13832 case PHY_ID_BCM5704: return "5704";
13833 case PHY_ID_BCM5705: return "5705";
13834 case PHY_ID_BCM5750: return "5750";
85e94ced 13835 case PHY_ID_BCM5752: return "5752";
a4e2b347 13836 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13837 case PHY_ID_BCM5780: return "5780";
af36e6b6 13838 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13839 case PHY_ID_BCM5787: return "5787";
d30cdd28 13840 case PHY_ID_BCM5784: return "5784";
126a3368 13841 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13842 case PHY_ID_BCM5906: return "5906";
9936bcf6 13843 case PHY_ID_BCM5761: return "5761";
c2060fe1 13844 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 13845 case PHY_ID_BCM8002: return "8002/serdes";
13846 case 0: return "serdes";
13847 default: return "unknown";
855e1111 13848 }
1da177e4
LT		 13849}
13850
f9804ddb
MC		 13851static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13852{
13853 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13854 strcpy(str, "PCI Express");
13855 return str;
13856 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13857 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13858
13859 strcpy(str, "PCIX:");
13860
13861 if ((clock_ctrl == 7) ||
13862 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13863 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13864 strcat(str, "133MHz");
13865 else if (clock_ctrl == 0)
13866 strcat(str, "33MHz");
13867 else if (clock_ctrl == 2)
13868 strcat(str, "50MHz");
13869 else if (clock_ctrl == 4)
13870 strcat(str, "66MHz");
13871 else if (clock_ctrl == 6)
13872 strcat(str, "100MHz");
f9804ddb
MC		 13873 } else {
13874 strcpy(str, "PCI:");
13875 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13876 strcat(str, "66MHz");
13877 else
13878 strcat(str, "33MHz");
13879 }
13880 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13881 strcat(str, ":32-bit");
13882 else
13883 strcat(str, ":64-bit");
13884 return str;
13885}
13886
8c2dc7e1 13887static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13888{
13889 struct pci_dev *peer;
13890 unsigned int func, devnr = tp->pdev->devfn & ~7;
13891
13892 for (func = 0; func < 8; func++) {
13893 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13894 if (peer && peer != tp->pdev)
13895 break;
13896 pci_dev_put(peer);
13897 }
16fe9d74
MC		 13898 /* 5704 can be configured in single-port mode, set peer to
13899 * tp->pdev in that case.
13900 */
13901 if (!peer) {
13902 peer = tp->pdev;
13903 return peer;
13904 }
1da177e4
LT		 13905
13906 /*
13907 * We don't need to keep the refcount elevated; there's no way
13908 * to remove one half of this device without removing the other
13909 */
13910 pci_dev_put(peer);
13911
13912 return peer;
13913}
13914
15f9850d
DM		 13915static void __devinit tg3_init_coal(struct tg3 *tp)
13916{
13917 struct ethtool_coalesce *ec = &tp->coal;
13918
13919 memset(ec, 0, sizeof(*ec));
13920 ec->cmd = ETHTOOL_GCOALESCE;
13921 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13922 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13923 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13924 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13925 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13926 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13927 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13928 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13929 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13930
13931 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13932 HOSTCC_MODE_CLRTICK_TXBD)) {
13933 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13934 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13935 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13936 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13937 }
d244c892
MC		 13938
13939 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13940 ec->rx_coalesce_usecs_irq = 0;
13941 ec->tx_coalesce_usecs_irq = 0;
13942 ec->stats_block_coalesce_usecs = 0;
13943 }
15f9850d
DM		 13944}
13945
7c7d64b8
SH		 13946static const struct net_device_ops tg3_netdev_ops = {
13947 .ndo_open = tg3_open,
13948 .ndo_stop = tg3_close,
00829823
SH		 13949 .ndo_start_xmit = tg3_start_xmit,
13950 .ndo_get_stats = tg3_get_stats,
13951 .ndo_validate_addr = eth_validate_addr,
13952 .ndo_set_multicast_list = tg3_set_rx_mode,
13953 .ndo_set_mac_address = tg3_set_mac_addr,
13954 .ndo_do_ioctl = tg3_ioctl,
13955 .ndo_tx_timeout = tg3_tx_timeout,
13956 .ndo_change_mtu = tg3_change_mtu,
13957#if TG3_VLAN_TAG_USED
13958 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13959#endif
13960#ifdef CONFIG_NET_POLL_CONTROLLER
13961 .ndo_poll_controller = tg3_poll_controller,
13962#endif
13963};
13964
13965static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13966 .ndo_open = tg3_open,
13967 .ndo_stop = tg3_close,
13968 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13969 .ndo_get_stats = tg3_get_stats,
13970 .ndo_validate_addr = eth_validate_addr,
13971 .ndo_set_multicast_list = tg3_set_rx_mode,
13972 .ndo_set_mac_address = tg3_set_mac_addr,
13973 .ndo_do_ioctl = tg3_ioctl,
13974 .ndo_tx_timeout = tg3_tx_timeout,
13975 .ndo_change_mtu = tg3_change_mtu,
13976#if TG3_VLAN_TAG_USED
13977 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13978#endif
13979#ifdef CONFIG_NET_POLL_CONTROLLER
13980 .ndo_poll_controller = tg3_poll_controller,
13981#endif
13982};
13983
1da177e4
LT		 13984static int __devinit tg3_init_one(struct pci_dev *pdev,
13985 const struct pci_device_id *ent)
13986{
13987 static int tg3_version_printed = 0;
1da177e4
LT		 13988 struct net_device *dev;
13989 struct tg3 *tp;
646c9edd
MC		 13990 int i, err, pm_cap;
13991 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13992 char str[40];
72f2afb8 13993 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13994
13995 if (tg3_version_printed++ == 0)
13996 printk(KERN_INFO "%s", version);
13997
13998 err = pci_enable_device(pdev);
13999 if (err) {
14000 printk(KERN_ERR PFX "Cannot enable PCI device, "
14001 "aborting.\n");
14002 return err;
14003 }
14004
1da177e4
LT		 14005 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14006 if (err) {
14007 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14008 "aborting.\n");
14009 goto err_out_disable_pdev;
14010 }
14011
14012 pci_set_master(pdev);
14013
14014 /* Find power-management capability. */
14015 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14016 if (pm_cap == 0) {
14017 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14018 "aborting.\n");
14019 err = -EIO;
14020 goto err_out_free_res;
14021 }
14022
fe5f5787 14023 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14024 if (!dev) {
14025 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14026 err = -ENOMEM;
14027 goto err_out_free_res;
14028 }
14029
1da177e4
LT		 14030 SET_NETDEV_DEV(dev, &pdev->dev);
14031
1da177e4
LT		 14032#if TG3_VLAN_TAG_USED
14033 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14034#endif
14035
14036 tp = netdev_priv(dev);
14037 tp->pdev = pdev;
14038 tp->dev = dev;
14039 tp->pm_cap = pm_cap;
1da177e4
LT		 14040 tp->rx_mode = TG3_DEF_RX_MODE;
14041 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14042
1da177e4
LT		 14043 if (tg3_debug > 0)
14044 tp->msg_enable = tg3_debug;
14045 else
14046 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14047
14048 /* The word/byte swap controls here control register access byte
14049 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14050 * setting below.
14051 */
14052 tp->misc_host_ctrl =
14053 MISC_HOST_CTRL_MASK_PCI_INT |
14054 MISC_HOST_CTRL_WORD_SWAP |
14055 MISC_HOST_CTRL_INDIR_ACCESS |
14056 MISC_HOST_CTRL_PCISTATE_RW;
14057
14058 /* The NONFRM (non-frame) byte/word swap controls take effect
14059 * on descriptor entries, anything which isn't packet data.
14060 *
14061 * The StrongARM chips on the board (one for tx, one for rx)
14062 * are running in big-endian mode.
14063 */
14064 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14065 GRC_MODE_WSWAP_NONFRM_DATA);
14066#ifdef __BIG_ENDIAN
14067 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14068#endif
14069 spin_lock_init(&tp->lock);
1da177e4 14070 spin_lock_init(&tp->indirect_lock);
c4028958 14071 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14072
d5fe488a 14073 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14074 if (!tp->regs) {
1da177e4
LT		 14075 printk(KERN_ERR PFX "Cannot map device registers, "
14076 "aborting.\n");
14077 err = -ENOMEM;
14078 goto err_out_free_dev;
14079 }
14080
14081 tg3_init_link_config(tp);
14082
1da177e4
LT		 14083 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14084 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14085
1da177e4 14086 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14087 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14088 dev->irq = pdev->irq;
1da177e4
LT		 14089
14090 err = tg3_get_invariants(tp);
14091 if (err) {
14092 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14093 "aborting.\n");
14094 goto err_out_iounmap;
14095 }
14096
615774fe
MC		 14097 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14098 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14099 dev->netdev_ops = &tg3_netdev_ops;
14100 else
14101 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14102
14103
4a29cc2e
MC		 14104 /* The EPB bridge inside 5714, 5715, and 5780 and any
14105 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14106 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14107 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14108 * do DMA address check in tg3_start_xmit().
14109 */
4a29cc2e 14110 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14111 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14112 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14113 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14114#ifdef CONFIG_HIGHMEM
6a35528a 14115 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14116#endif
4a29cc2e 14117 } else
6a35528a 14118 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14119
14120 /* Configure DMA attributes. */
284901a9 14121 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14122 err = pci_set_dma_mask(pdev, dma_mask);
14123 if (!err) {
14124 dev->features |= NETIF_F_HIGHDMA;
14125 err = pci_set_consistent_dma_mask(pdev,
14126 persist_dma_mask);
14127 if (err < 0) {
14128 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14129 "DMA for consistent allocations\n");
14130 goto err_out_iounmap;
14131 }
14132 }
14133 }
284901a9
YH		 14134 if (err || dma_mask == DMA_BIT_MASK(32)) {
14135 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14136 if (err) {
14137 printk(KERN_ERR PFX "No usable DMA configuration, "
14138 "aborting.\n");
14139 goto err_out_iounmap;
14140 }
14141 }
14142
fdfec172 14143 tg3_init_bufmgr_config(tp);
1da177e4 14144
507399f1
MC		 14145 /* Selectively allow TSO based on operating conditions */
14146 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14147 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14148 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14149 else {
14150 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14151 tp->fw_needed = NULL;
1da177e4 14152 }
507399f1
MC		 14153
14154 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14155 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14156
4e3a7aaa
MC		 14157 /* TSO is on by default on chips that support hardware TSO.
14158 * Firmware TSO on older chips gives lower performance, so it
14159 * is off by default, but can be enabled using ethtool.
14160 */
e849cdc3
MC		 14161 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14162 (dev->features & NETIF_F_IP_CSUM))
14163 dev->features |= NETIF_F_TSO;
14164
14165 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14166 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14167 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14168 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14169 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14171 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14172 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14174 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14175 dev->features |= NETIF_F_TSO_ECN;
b0026624 14176 }
1da177e4 14177
1da177e4
LT		 14178 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14179 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14180 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14181 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14182 tp->rx_pending = 63;
14183 }
14184
1da177e4
LT		 14185 err = tg3_get_device_address(tp);
14186 if (err) {
14187 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14188 "aborting.\n");
077f849d 14189 goto err_out_fw;
1da177e4
LT		 14190 }
14191
c88864df 14192 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14193 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14194 if (!tp->aperegs) {
c88864df
MC		 14195 printk(KERN_ERR PFX "Cannot map APE registers, "
14196 "aborting.\n");
14197 err = -ENOMEM;
077f849d 14198 goto err_out_fw;
c88864df
MC		 14199 }
14200
14201 tg3_ape_lock_init(tp);
7fd76445
MC		 14202
14203 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14204 tg3_read_dash_ver(tp);
c88864df
MC		 14205 }
14206
1da177e4
LT		 14207 /*
14208 * Reset chip in case UNDI or EFI driver did not shutdown
14209 * DMA self test will enable WDMAC and we'll see (spurious)
14210 * pending DMA on the PCI bus at that point.
14211 */
14212 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14213 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14214 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14215 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14216 }
14217
14218 err = tg3_test_dma(tp);
14219 if (err) {
14220 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14221 goto err_out_apeunmap;
1da177e4
LT		 14222 }
14223
1da177e4
LT		 14224 /* flow control autonegotiation is default behavior */
14225 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14226 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14227
78f90dcf
MC		 14228 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14229 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14230 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14231 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14232 struct tg3_napi *tnapi = &tp->napi[i];
14233
14234 tnapi->tp = tp;
14235 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14236
14237 tnapi->int_mbox = intmbx;
14238 if (i < 4)
14239 intmbx += 0x8;
14240 else
14241 intmbx += 0x4;
14242
14243 tnapi->consmbox = rcvmbx;
14244 tnapi->prodmbox = sndmbx;
14245
14246 if (i) {
14247 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14248 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14249 } else {
14250 tnapi->coal_now = HOSTCC_MODE_NOW;
14251 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14252 }
14253
14254 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14255 break;
14256
14257 /*
14258 * If we support MSIX, we'll be using RSS. If we're using
14259 * RSS, the first vector only handles link interrupts and the
14260 * remaining vectors handle rx and tx interrupts. Reuse the
14261 * mailbox values for the next iteration. The values we setup
14262 * above are still useful for the single vectored mode.
14263 */
14264 if (!i)
14265 continue;
14266
14267 rcvmbx += 0x8;
14268
14269 if (sndmbx & 0x4)
14270 sndmbx -= 0x4;
14271 else
14272 sndmbx += 0xc;
14273 }
14274
15f9850d
DM		 14275 tg3_init_coal(tp);
14276
c49a1561
MC		 14277 pci_set_drvdata(pdev, dev);
14278
1da177e4
LT		 14279 err = register_netdev(dev);
14280 if (err) {
14281 printk(KERN_ERR PFX "Cannot register net device, "
14282 "aborting.\n");
0d3031d9 14283 goto err_out_apeunmap;
1da177e4
LT		 14284 }
14285
df59c940 14286 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14287 dev->name,
14288 tp->board_part_number,
14289 tp->pci_chip_rev_id,
f9804ddb 14290 tg3_bus_string(tp, str),
e174961c 14291 dev->dev_addr);
1da177e4 14292
3f0e3ad7
MC		 14293 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14294 struct phy_device *phydev;
14295 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14296 printk(KERN_INFO
14297 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14298 tp->dev->name, phydev->drv->name,
14299 dev_name(&phydev->dev));
14300 } else
df59c940
MC		 14301 printk(KERN_INFO
14302 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14303 tp->dev->name, tg3_phy_string(tp),
14304 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14305 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14306 "10/100/1000Base-T")),
14307 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14308
14309 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14310 dev->name,
14311 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14312 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14313 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14314 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14315 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14316 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14317 dev->name, tp->dma_rwctrl,
284901a9 14318 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14319 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14320
14321 return 0;
14322
0d3031d9
MC		 14323err_out_apeunmap:
14324 if (tp->aperegs) {
14325 iounmap(tp->aperegs);
14326 tp->aperegs = NULL;
14327 }
14328
077f849d
JSR		 14329err_out_fw:
14330 if (tp->fw)
14331 release_firmware(tp->fw);
14332
1da177e4 14333err_out_iounmap:
6892914f
MC		 14334 if (tp->regs) {
14335 iounmap(tp->regs);
22abe310 14336 tp->regs = NULL;
6892914f 14337 }
1da177e4
LT		 14338
14339err_out_free_dev:
14340 free_netdev(dev);
14341
14342err_out_free_res:
14343 pci_release_regions(pdev);
14344
14345err_out_disable_pdev:
14346 pci_disable_device(pdev);
14347 pci_set_drvdata(pdev, NULL);
14348 return err;
14349}
14350
14351static void __devexit tg3_remove_one(struct pci_dev *pdev)
14352{
14353 struct net_device *dev = pci_get_drvdata(pdev);
14354
14355 if (dev) {
14356 struct tg3 *tp = netdev_priv(dev);
14357
077f849d
JSR		 14358 if (tp->fw)
14359 release_firmware(tp->fw);
14360
7faa006f 14361 flush_scheduled_work();
158d7abd 14362
b02fd9e3
MC		 14363 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14364 tg3_phy_fini(tp);
158d7abd 14365 tg3_mdio_fini(tp);
b02fd9e3 14366 }
158d7abd 14367
1da177e4 14368 unregister_netdev(dev);
0d3031d9
MC		 14369 if (tp->aperegs) {
14370 iounmap(tp->aperegs);
14371 tp->aperegs = NULL;
14372 }
6892914f
MC		 14373 if (tp->regs) {
14374 iounmap(tp->regs);
22abe310 14375 tp->regs = NULL;
6892914f 14376 }
1da177e4
LT		 14377 free_netdev(dev);
14378 pci_release_regions(pdev);
14379 pci_disable_device(pdev);
14380 pci_set_drvdata(pdev, NULL);
14381 }
14382}
14383
14384static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14385{
14386 struct net_device *dev = pci_get_drvdata(pdev);
14387 struct tg3 *tp = netdev_priv(dev);
12dac075 14388 pci_power_t target_state;
1da177e4
LT		 14389 int err;
14390
3e0c95fd
MC		 14391 /* PCI register 4 needs to be saved whether netif_running() or not.
14392 * MSI address and data need to be saved if using MSI and
14393 * netif_running().
14394 */
14395 pci_save_state(pdev);
14396
1da177e4
LT		 14397 if (!netif_running(dev))
14398 return 0;
14399
7faa006f 14400 flush_scheduled_work();
b02fd9e3 14401 tg3_phy_stop(tp);
1da177e4
LT		 14402 tg3_netif_stop(tp);
14403
14404 del_timer_sync(&tp->timer);
14405
f47c11ee 14406 tg3_full_lock(tp, 1);
1da177e4 14407 tg3_disable_ints(tp);
f47c11ee 14408 tg3_full_unlock(tp);
1da177e4
LT		 14409
14410 netif_device_detach(dev);
14411
f47c11ee 14412 tg3_full_lock(tp, 0);
944d980e 14413 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14414 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14415 tg3_full_unlock(tp);
1da177e4 14416
12dac075
RW		 14417 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14418
14419 err = tg3_set_power_state(tp, target_state);
1da177e4 14420 if (err) {
b02fd9e3
MC		 14421 int err2;
14422
f47c11ee 14423 tg3_full_lock(tp, 0);
1da177e4 14424
6a9eba15 14425 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14426 err2 = tg3_restart_hw(tp, 1);
14427 if (err2)
b9ec6c1b 14428 goto out;
1da177e4
LT		 14429
14430 tp->timer.expires = jiffies + tp->timer_offset;
14431 add_timer(&tp->timer);
14432
14433 netif_device_attach(dev);
14434 tg3_netif_start(tp);
14435
b9ec6c1b 14436out:
f47c11ee 14437 tg3_full_unlock(tp);
b02fd9e3
MC		 14438
14439 if (!err2)
14440 tg3_phy_start(tp);
1da177e4
LT		 14441 }
14442
14443 return err;
14444}
14445
14446static int tg3_resume(struct pci_dev *pdev)
14447{
14448 struct net_device *dev = pci_get_drvdata(pdev);
14449 struct tg3 *tp = netdev_priv(dev);
14450 int err;
14451
3e0c95fd
MC		 14452 pci_restore_state(tp->pdev);
14453
1da177e4
LT		 14454 if (!netif_running(dev))
14455 return 0;
14456
bc1c7567 14457 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14458 if (err)
14459 return err;
14460
14461 netif_device_attach(dev);
14462
f47c11ee 14463 tg3_full_lock(tp, 0);
1da177e4 14464
6a9eba15 14465 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14466 err = tg3_restart_hw(tp, 1);
14467 if (err)
14468 goto out;
1da177e4
LT		 14469
14470 tp->timer.expires = jiffies + tp->timer_offset;
14471 add_timer(&tp->timer);
14472
1da177e4
LT		 14473 tg3_netif_start(tp);
14474
b9ec6c1b 14475out:
f47c11ee 14476 tg3_full_unlock(tp);
1da177e4 14477
b02fd9e3
MC		 14478 if (!err)
14479 tg3_phy_start(tp);
14480
b9ec6c1b 14481 return err;
1da177e4
LT		 14482}
14483
14484static struct pci_driver tg3_driver = {
14485 .name = DRV_MODULE_NAME,
14486 .id_table = tg3_pci_tbl,
14487 .probe = tg3_init_one,
14488 .remove = __devexit_p(tg3_remove_one),
14489 .suspend = tg3_suspend,
14490 .resume = tg3_resume
14491};
14492
14493static int __init tg3_init(void)
14494{
29917620 14495 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14496}
14497
14498static void __exit tg3_cleanup(void)
14499{
14500 pci_unregister_driver(&tg3_driver);
14501}
14502
14503module_init(tg3_init);
14504module_exit(tg3_cleanup);
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