]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/tg3.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tg3: Disable 5717 serdes and B0 support
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
cceea982
MC		 71#define DRV_MODULE_VERSION "3.105"
72#define DRV_MODULE_RELDATE "December 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
13185217
HK		 247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254 {}
1da177e4
LT		 255};
256
257MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
50da859d 259static const struct {
1da177e4
LT		 260 const char string[ETH_GSTRING_LEN];
261} ethtool_stats_keys[TG3_NUM_STATS] = {
262 { "rx_octets" },
263 { "rx_fragments" },
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
267 { "rx_fcs_errors" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
274 { "rx_jabbers" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
288
289 { "tx_octets" },
290 { "tx_collisions" },
291
292 { "tx_xon_sent" },
293 { "tx_xoff_sent" },
294 { "tx_flow_control" },
295 { "tx_mac_errors" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
298 { "tx_deferred" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
319 { "tx_discards" },
320 { "tx_errors" },
321
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
324 { "rxbds_empty" },
325 { "rx_discards" },
326 { "rx_errors" },
327 { "rx_threshold_hit" },
328
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
332
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
335 { "nic_irqs" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
338};
339
50da859d 340static const struct {
4cafd3f5
MC		 341 const char string[ETH_GSTRING_LEN];
342} ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
349};
350
b401e9e2
MC		 351static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354}
355
356static u32 tg3_read32(struct tg3 *tp, u32 off)
357{
6aa20a22 358 return (readl(tp->regs + off));
b401e9e2
MC		 359}
360
0d3031d9
MC		 361static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->aperegs + off);
364}
365
366static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367{
368 return (readl(tp->aperegs + off));
369}
370
1da177e4
LT		 371static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372{
6892914f
MC		 373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 379}
380
381static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382{
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
1da177e4
LT		 385}
386
6892914f 387static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 388{
6892914f
MC		 389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
399static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
66711e66 408 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
1da177e4 412 }
6892914f
MC		 413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427}
428
429static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430{
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439}
440
b401e9e2
MC		 441/* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 447{
b401e9e2
MC		 448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
1da177e4
LT		 464}
465
09ee929c
MC		 466static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467{
468 tp->write32_mbox(tp, off, val);
6892914f
MC		 469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
09ee929c
MC		 472}
473
20094930 474static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 475{
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482}
483
b5d3772c
MC		 484static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485{
486 return (readl(tp->regs + off + GRCMBOX_BASE));
487}
488
489static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off + GRCMBOX_BASE);
492}
493
20094930 494#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 495#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 496#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 498#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 499
500#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 501#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 503#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 504
505static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506{
6892914f
MC		 507 unsigned long flags;
508
b5d3772c
MC		 509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511 return;
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 528}
529
1da177e4
LT		 530static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536 *val = 0;
537 return;
538 }
539
6892914f 540 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 544
bbadf503
MC		 545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 } else {
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 }
6892914f 554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 555}
556
0d3031d9
MC		 557static void tg3_ape_lock_init(struct tg3 *tp)
558{
559 int i;
560
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
565}
566
567static int tg3_ape_lock(struct tg3 *tp, int locknum)
568{
569 int i, off;
570 int ret = 0;
571 u32 status;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return 0;
575
576 switch (locknum) {
77b483f1 577 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 off = 4 * locknum;
585
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
592 break;
593 udelay(10);
594 }
595
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
600
601 ret = -EBUSY;
602 }
603
604 return ret;
605}
606
607static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608{
609 int off;
610
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612 return;
613
614 switch (locknum) {
77b483f1 615 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 616 case TG3_APE_LOCK_MEM:
617 break;
618 default:
619 return;
620 }
621
622 off = 4 * locknum;
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624}
625
1da177e4
LT		 626static void tg3_disable_ints(struct tg3 *tp)
627{
89aeb3bc
MC		 628 int i;
629
1da177e4
LT		 630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 634}
635
1da177e4
LT		 636static void tg3_enable_ints(struct tg3 *tp)
637{
89aeb3bc
MC		 638 int i;
639 u32 coal_now = 0;
640
bbe832c0
MC		 641 tp->irq_sync = 0;
642 wmb();
643
1da177e4
LT		 644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 646
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 652
89aeb3bc
MC		 653 coal_now |= tnapi->coal_now;
654 }
f19af9c2
MC		 655
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660 else
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 663}
664
17375d25 665static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 666{
17375d25 667 struct tg3 *tp = tnapi->tp;
898a56f8 668 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 669 unsigned int work_exists = 0;
670
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
676 work_exists = 1;
677 }
678 /* check for RX/TX work to do */
f3f3f27e 679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 681 work_exists = 1;
682
683 return work_exists;
684}
685
17375d25 686/* tg3_int_reenable
04237ddd
MC		 687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
6aa20a22 689 * which reenables interrupts
1da177e4 690 */
17375d25 691static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 692{
17375d25
MC		 693 struct tg3 *tp = tnapi->tp;
694
898a56f8 695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 696 mmiowb();
697
fac9b83e
DM		 698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
701 */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 703 tg3_has_work(tnapi))
04237ddd 704 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 706}
707
fed97810
MC		 708static void tg3_napi_disable(struct tg3 *tp)
709{
710 int i;
711
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
714}
715
716static void tg3_napi_enable(struct tg3 *tp)
717{
718 int i;
719
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
722}
723
1da177e4
LT		 724static inline void tg3_netif_stop(struct tg3 *tp)
725{
bbe832c0 726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 727 tg3_napi_disable(tp);
1da177e4
LT		 728 netif_tx_disable(tp->dev);
729}
730
731static inline void tg3_netif_start(struct tg3 *tp)
732{
fe5f5787
MC		 733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
1da177e4 736 */
fe5f5787
MC		 737 netif_tx_wake_all_queues(tp->dev);
738
fed97810
MC		 739 tg3_napi_enable(tp);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 741 tg3_enable_ints(tp);
1da177e4
LT		 742}
743
744static void tg3_switch_clocks(struct tg3 *tp)
745{
f6eb9b1f 746 u32 clock_ctrl;
1da177e4
LT		 747 u32 orig_clock_ctrl;
748
795d01c5
MC		 749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 751 return;
752
f6eb9b1f
MC		 753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
1da177e4
LT		 755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
758 0x1f);
759 tp->pci_clock_ctrl = clock_ctrl;
760
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 765 }
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl |
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770 40);
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
773 40);
1da177e4 774 }
b401e9e2 775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 776}
777
778#define PHY_BUSY_LOOPS 5000
779
780static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781{
782 u32 frame_val;
783 unsigned int loops;
784 int ret;
785
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787 tw32_f(MAC_MI_MODE,
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789 udelay(80);
790 }
791
792 *val = 0x0;
793
882e9793 794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 799
1da177e4
LT		 800 tw32_f(MAC_MI_COM, frame_val);
801
802 loops = PHY_BUSY_LOOPS;
803 while (loops != 0) {
804 udelay(10);
805 frame_val = tr32(MAC_MI_COM);
806
807 if ((frame_val & MI_COM_BUSY) == 0) {
808 udelay(5);
809 frame_val = tr32(MAC_MI_COM);
810 break;
811 }
812 loops -= 1;
813 }
814
815 ret = -EBUSY;
816 if (loops != 0) {
817 *val = frame_val & MI_COM_DATA_MASK;
818 ret = 0;
819 }
820
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
823 udelay(80);
824 }
825
826 return ret;
827}
828
829static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830{
831 u32 frame_val;
832 unsigned int loops;
833 int ret;
834
7f97a4bd 835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837 return 0;
838
1da177e4
LT		 839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840 tw32_f(MAC_MI_MODE,
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842 udelay(80);
843 }
844
882e9793 845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 851
1da177e4
LT		 852 tw32_f(MAC_MI_COM, frame_val);
853
854 loops = PHY_BUSY_LOOPS;
855 while (loops != 0) {
856 udelay(10);
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
859 udelay(5);
860 frame_val = tr32(MAC_MI_COM);
861 break;
862 }
863 loops -= 1;
864 }
865
866 ret = -EBUSY;
867 if (loops != 0)
868 ret = 0;
869
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
872 udelay(80);
873 }
874
875 return ret;
876}
877
95e2869a
MC		 878static int tg3_bmcr_reset(struct tg3 *tp)
879{
880 u32 phy_control;
881 int limit, err;
882
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
885 */
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
888 if (err != 0)
889 return -EBUSY;
890
891 limit = 5000;
892 while (limit--) {
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 if ((phy_control & BMCR_RESET) == 0) {
898 udelay(40);
899 break;
900 }
901 udelay(10);
902 }
d4675b52 903 if (limit < 0)
95e2869a
MC		 904 return -EBUSY;
905
906 return 0;
907}
908
158d7abd
MC		 909static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910{
3d16543d 911 struct tg3 *tp = bp->priv;
158d7abd
MC		 912 u32 val;
913
24bb4fb6 914 spin_lock_bh(&tp->lock);
158d7abd
MC		 915
916 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 917 val = -EIO;
918
919 spin_unlock_bh(&tp->lock);
158d7abd
MC		 920
921 return val;
922}
923
924static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925{
3d16543d 926 struct tg3 *tp = bp->priv;
24bb4fb6 927 u32 ret = 0;
158d7abd 928
24bb4fb6 929 spin_lock_bh(&tp->lock);
158d7abd
MC		 930
931 if (tg3_writephy(tp, reg, val))
24bb4fb6 932 ret = -EIO;
158d7abd 933
24bb4fb6
MC		 934 spin_unlock_bh(&tp->lock);
935
936 return ret;
158d7abd
MC		 937}
938
939static int tg3_mdio_reset(struct mii_bus *bp)
940{
941 return 0;
942}
943
9c61d6bc 944static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 945{
946 u32 val;
fcb389df 947 struct phy_device *phydev;
a9daf367 948
3f0e3ad7 949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
c73430d0 952 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 953 val = MAC_PHYCFG2_50610_LED_MODES;
954 break;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960 break;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963 break;
964 default:
a9daf367 965 return;
fcb389df
MC		 966 }
967
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
970
971 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 975 tw32(MAC_PHYCFG1, val);
976
977 return;
978 }
979
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
987
988 tw32(MAC_PHYCFG2, val);
a9daf367 989
bb85fbb6
MC		 990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998 }
bb85fbb6
MC		 999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
a9daf367 1002
a9daf367
MC		 1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
fcb389df 1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1021 }
1022 tw32(MAC_EXT_RGMII_MODE, val);
1023}
1024
158d7abd
MC		 1025static void tg3_mdio_start(struct tg3 *tp)
1026{
158d7abd
MC		 1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1029 udelay(80);
a9daf367 1030
882e9793
MC		 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1033
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035 if (funcnum)
1036 tp->phy_addr = 2;
1037 else
1038 tp->phy_addr = 1;
1039
d1ec96af
MC		 1040 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1041 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1042 else
1043 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1044 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1045 if (is_serdes)
1046 tp->phy_addr += 7;
1047 } else
3f0e3ad7 1048 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1049
9c61d6bc
MC		 1050 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1052 tg3_mdio_config_5785(tp);
158d7abd
MC		 1053}
1054
158d7abd
MC		 1055static int tg3_mdio_init(struct tg3 *tp)
1056{
1057 int i;
1058 u32 reg;
a9daf367 1059 struct phy_device *phydev;
158d7abd
MC		 1060
1061 tg3_mdio_start(tp);
1062
1063 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1064 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1065 return 0;
1066
298cf9be
LB		 1067 tp->mdio_bus = mdiobus_alloc();
1068 if (tp->mdio_bus == NULL)
1069 return -ENOMEM;
158d7abd 1070
298cf9be
LB		 1071 tp->mdio_bus->name = "tg3 mdio bus";
1072 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1073 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1074 tp->mdio_bus->priv = tp;
1075 tp->mdio_bus->parent = &tp->pdev->dev;
1076 tp->mdio_bus->read = &tg3_mdio_read;
1077 tp->mdio_bus->write = &tg3_mdio_write;
1078 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1079 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1080 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1081
1082 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1083 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1084
1085 /* The bus registration will look for all the PHYs on the mdio bus.
1086 * Unfortunately, it does not ensure the PHY is powered up before
1087 * accessing the PHY ID registers. A chip reset is the
1088 * quickest way to bring the device back to an operational state..
1089 */
1090 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1091 tg3_bmcr_reset(tp);
1092
298cf9be 1093 i = mdiobus_register(tp->mdio_bus);
a9daf367 1094 if (i) {
158d7abd
MC		 1095 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1096 tp->dev->name, i);
9c61d6bc 1097 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1098 return i;
1099 }
158d7abd 1100
3f0e3ad7 1101 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1102
9c61d6bc
MC		 1103 if (!phydev || !phydev->drv) {
1104 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1105 mdiobus_unregister(tp->mdio_bus);
1106 mdiobus_free(tp->mdio_bus);
1107 return -ENODEV;
1108 }
1109
1110 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1111 case TG3_PHY_ID_BCM57780:
1112 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1113 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1114 break;
a9daf367 1115 case TG3_PHY_ID_BCM50610:
c73430d0 1116 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1117 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1118 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1119 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1120 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1122 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1123 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1124 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1125 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1126 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1127 /* fallthru */
1128 case TG3_PHY_ID_RTL8211C:
1129 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1130 break;
fcb389df 1131 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1132 case TG3_PHY_ID_BCMAC131:
1133 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1134 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1135 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1136 break;
1137 }
1138
9c61d6bc
MC		 1139 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1140
1141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1142 tg3_mdio_config_5785(tp);
a9daf367
MC		 1143
1144 return 0;
158d7abd
MC		 1145}
1146
1147static void tg3_mdio_fini(struct tg3 *tp)
1148{
1149 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1150 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1151 mdiobus_unregister(tp->mdio_bus);
1152 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1153 }
1154}
1155
4ba526ce
MC		 1156/* tp->lock is held. */
1157static inline void tg3_generate_fw_event(struct tg3 *tp)
1158{
1159 u32 val;
1160
1161 val = tr32(GRC_RX_CPU_EVENT);
1162 val |= GRC_RX_CPU_DRIVER_EVENT;
1163 tw32_f(GRC_RX_CPU_EVENT, val);
1164
1165 tp->last_event_jiffies = jiffies;
1166}
1167
1168#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1169
95e2869a
MC		 1170/* tp->lock is held. */
1171static void tg3_wait_for_event_ack(struct tg3 *tp)
1172{
1173 int i;
4ba526ce
MC		 1174 unsigned int delay_cnt;
1175 long time_remain;
1176
1177 /* If enough time has passed, no wait is necessary. */
1178 time_remain = (long)(tp->last_event_jiffies + 1 +
1179 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1180 (long)jiffies;
1181 if (time_remain < 0)
1182 return;
1183
1184 /* Check if we can shorten the wait time. */
1185 delay_cnt = jiffies_to_usecs(time_remain);
1186 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1187 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1188 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1189
4ba526ce 1190 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1191 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1192 break;
4ba526ce 1193 udelay(8);
95e2869a
MC		 1194 }
1195}
1196
1197/* tp->lock is held. */
1198static void tg3_ump_link_report(struct tg3 *tp)
1199{
1200 u32 reg;
1201 u32 val;
1202
1203 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1204 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1205 return;
1206
1207 tg3_wait_for_event_ack(tp);
1208
1209 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1210
1211 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1212
1213 val = 0;
1214 if (!tg3_readphy(tp, MII_BMCR, &reg))
1215 val = reg << 16;
1216 if (!tg3_readphy(tp, MII_BMSR, &reg))
1217 val |= (reg & 0xffff);
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1219
1220 val = 0;
1221 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1222 val = reg << 16;
1223 if (!tg3_readphy(tp, MII_LPA, &reg))
1224 val |= (reg & 0xffff);
1225 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1226
1227 val = 0;
1228 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1229 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1230 val = reg << 16;
1231 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1232 val |= (reg & 0xffff);
1233 }
1234 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1235
1236 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1237 val = reg << 16;
1238 else
1239 val = 0;
1240 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1241
4ba526ce 1242 tg3_generate_fw_event(tp);
95e2869a
MC		 1243}
1244
1245static void tg3_link_report(struct tg3 *tp)
1246{
1247 if (!netif_carrier_ok(tp->dev)) {
1248 if (netif_msg_link(tp))
1249 printk(KERN_INFO PFX "%s: Link is down.\n",
1250 tp->dev->name);
1251 tg3_ump_link_report(tp);
1252 } else if (netif_msg_link(tp)) {
1253 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1254 tp->dev->name,
1255 (tp->link_config.active_speed == SPEED_1000 ?
1256 1000 :
1257 (tp->link_config.active_speed == SPEED_100 ?
1258 100 : 10)),
1259 (tp->link_config.active_duplex == DUPLEX_FULL ?
1260 "full" : "half"));
1261
1262 printk(KERN_INFO PFX
1263 "%s: Flow control is %s for TX and %s for RX.\n",
1264 tp->dev->name,
e18ce346 1265 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1266 "on" : "off",
e18ce346 1267 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1268 "on" : "off");
1269 tg3_ump_link_report(tp);
1270 }
1271}
1272
1273static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1274{
1275 u16 miireg;
1276
e18ce346 1277 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1278 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1279 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1280 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1281 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1282 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1283 else
1284 miireg = 0;
1285
1286 return miireg;
1287}
1288
1289static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1290{
1291 u16 miireg;
1292
e18ce346 1293 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1294 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1295 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1296 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1297 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1298 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1299 else
1300 miireg = 0;
1301
1302 return miireg;
1303}
1304
95e2869a
MC		 1305static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1306{
1307 u8 cap = 0;
1308
1309 if (lcladv & ADVERTISE_1000XPAUSE) {
1310 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1311 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1312 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1313 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1314 cap = FLOW_CTRL_RX;
95e2869a
MC		 1315 } else {
1316 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1317 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1318 }
1319 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1320 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1321 cap = FLOW_CTRL_TX;
95e2869a
MC		 1322 }
1323
1324 return cap;
1325}
1326
f51f3562 1327static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1328{
b02fd9e3 1329 u8 autoneg;
f51f3562 1330 u8 flowctrl = 0;
95e2869a
MC		 1331 u32 old_rx_mode = tp->rx_mode;
1332 u32 old_tx_mode = tp->tx_mode;
1333
b02fd9e3 1334 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1335 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1336 else
1337 autoneg = tp->link_config.autoneg;
1338
1339 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1340 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1341 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1342 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1343 else
bc02ff95 1344 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1345 } else
1346 flowctrl = tp->link_config.flowctrl;
95e2869a 1347
f51f3562 1348 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1349
e18ce346 1350 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1351 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1352 else
1353 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1354
f51f3562 1355 if (old_rx_mode != tp->rx_mode)
95e2869a 1356 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1357
e18ce346 1358 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1359 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1360 else
1361 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1362
f51f3562 1363 if (old_tx_mode != tp->tx_mode)
95e2869a 1364 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1365}
1366
b02fd9e3
MC		 1367static void tg3_adjust_link(struct net_device *dev)
1368{
1369 u8 oldflowctrl, linkmesg = 0;
1370 u32 mac_mode, lcl_adv, rmt_adv;
1371 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1372 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1373
24bb4fb6 1374 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1375
1376 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1377 MAC_MODE_HALF_DUPLEX);
1378
1379 oldflowctrl = tp->link_config.active_flowctrl;
1380
1381 if (phydev->link) {
1382 lcl_adv = 0;
1383 rmt_adv = 0;
1384
1385 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1386 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1387 else if (phydev->speed == SPEED_1000 ||
1388 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1389 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1390 else
1391 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1392
1393 if (phydev->duplex == DUPLEX_HALF)
1394 mac_mode |= MAC_MODE_HALF_DUPLEX;
1395 else {
1396 lcl_adv = tg3_advert_flowctrl_1000T(
1397 tp->link_config.flowctrl);
1398
1399 if (phydev->pause)
1400 rmt_adv = LPA_PAUSE_CAP;
1401 if (phydev->asym_pause)
1402 rmt_adv |= LPA_PAUSE_ASYM;
1403 }
1404
1405 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1406 } else
1407 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1408
1409 if (mac_mode != tp->mac_mode) {
1410 tp->mac_mode = mac_mode;
1411 tw32_f(MAC_MODE, tp->mac_mode);
1412 udelay(40);
1413 }
1414
fcb389df
MC		 1415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1416 if (phydev->speed == SPEED_10)
1417 tw32(MAC_MI_STAT,
1418 MAC_MI_STAT_10MBPS_MODE |
1419 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420 else
1421 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422 }
1423
b02fd9e3
MC		 1424 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1425 tw32(MAC_TX_LENGTHS,
1426 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1427 (6 << TX_LENGTHS_IPG_SHIFT) |
1428 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1429 else
1430 tw32(MAC_TX_LENGTHS,
1431 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1432 (6 << TX_LENGTHS_IPG_SHIFT) |
1433 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1434
1435 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1436 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1437 phydev->speed != tp->link_config.active_speed ||
1438 phydev->duplex != tp->link_config.active_duplex ||
1439 oldflowctrl != tp->link_config.active_flowctrl)
1440 linkmesg = 1;
1441
1442 tp->link_config.active_speed = phydev->speed;
1443 tp->link_config.active_duplex = phydev->duplex;
1444
24bb4fb6 1445 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1446
1447 if (linkmesg)
1448 tg3_link_report(tp);
1449}
1450
1451static int tg3_phy_init(struct tg3 *tp)
1452{
1453 struct phy_device *phydev;
1454
1455 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1456 return 0;
1457
1458 /* Bring the PHY back to a known state. */
1459 tg3_bmcr_reset(tp);
1460
3f0e3ad7 1461 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1462
1463 /* Attach the MAC to the PHY. */
fb28ad35 1464 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1465 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1466 if (IS_ERR(phydev)) {
1467 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1468 return PTR_ERR(phydev);
1469 }
1470
b02fd9e3 1471 /* Mask with MAC supported features. */
9c61d6bc
MC		 1472 switch (phydev->interface) {
1473 case PHY_INTERFACE_MODE_GMII:
1474 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1475 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1476 phydev->supported &= (PHY_GBIT_FEATURES |
1477 SUPPORTED_Pause |
1478 SUPPORTED_Asym_Pause);
1479 break;
1480 }
1481 /* fallthru */
9c61d6bc
MC		 1482 case PHY_INTERFACE_MODE_MII:
1483 phydev->supported &= (PHY_BASIC_FEATURES |
1484 SUPPORTED_Pause |
1485 SUPPORTED_Asym_Pause);
1486 break;
1487 default:
3f0e3ad7 1488 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1489 return -EINVAL;
1490 }
1491
1492 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1493
1494 phydev->advertising = phydev->supported;
1495
b02fd9e3
MC		 1496 return 0;
1497}
1498
1499static void tg3_phy_start(struct tg3 *tp)
1500{
1501 struct phy_device *phydev;
1502
1503 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1504 return;
1505
3f0e3ad7 1506 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1507
1508 if (tp->link_config.phy_is_low_power) {
1509 tp->link_config.phy_is_low_power = 0;
1510 phydev->speed = tp->link_config.orig_speed;
1511 phydev->duplex = tp->link_config.orig_duplex;
1512 phydev->autoneg = tp->link_config.orig_autoneg;
1513 phydev->advertising = tp->link_config.orig_advertising;
1514 }
1515
1516 phy_start(phydev);
1517
1518 phy_start_aneg(phydev);
1519}
1520
1521static void tg3_phy_stop(struct tg3 *tp)
1522{
1523 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1524 return;
1525
3f0e3ad7 1526 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1527}
1528
1529static void tg3_phy_fini(struct tg3 *tp)
1530{
1531 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1532 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1533 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1534 }
1535}
1536
b2a5c19c
MC		 1537static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1538{
1539 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1540 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1541}
1542
7f97a4bd
MC		 1543static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1544{
1545 u32 phytest;
1546
1547 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1548 u32 phy;
1549
1550 tg3_writephy(tp, MII_TG3_FET_TEST,
1551 phytest | MII_TG3_FET_SHADOW_EN);
1552 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1553 if (enable)
1554 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1555 else
1556 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1557 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1558 }
1559 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1560 }
1561}
1562
6833c043
MC		 1563static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1564{
1565 u32 reg;
1566
7f97a4bd 1567 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1568 return;
1569
7f97a4bd
MC		 1570 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1571 tg3_phy_fet_toggle_apd(tp, enable);
1572 return;
1573 }
1574
6833c043
MC		 1575 reg = MII_TG3_MISC_SHDW_WREN |
1576 MII_TG3_MISC_SHDW_SCR5_SEL |
1577 MII_TG3_MISC_SHDW_SCR5_LPED |
1578 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1579 MII_TG3_MISC_SHDW_SCR5_SDTL |
1580 MII_TG3_MISC_SHDW_SCR5_C125OE;
1581 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1582 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1583
1584 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1585
1586
1587 reg = MII_TG3_MISC_SHDW_WREN |
1588 MII_TG3_MISC_SHDW_APD_SEL |
1589 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1590 if (enable)
1591 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1592
1593 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594}
1595
9ef8ca99
MC		 1596static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1597{
1598 u32 phy;
1599
1600 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1601 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1602 return;
1603
7f97a4bd 1604 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1605 u32 ephy;
1606
535ef6e1
MC		 1607 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1608 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1609
1610 tg3_writephy(tp, MII_TG3_FET_TEST,
1611 ephy | MII_TG3_FET_SHADOW_EN);
1612 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1613 if (enable)
535ef6e1 1614 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1615 else
535ef6e1
MC		 1616 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1617 tg3_writephy(tp, reg, phy);
9ef8ca99 1618 }
535ef6e1 1619 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1620 }
1621 } else {
1622 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1623 MII_TG3_AUXCTL_SHDWSEL_MISC;
1624 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1625 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1626 if (enable)
1627 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1628 else
1629 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1630 phy |= MII_TG3_AUXCTL_MISC_WREN;
1631 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1632 }
1633 }
1634}
1635
1da177e4
LT		 1636static void tg3_phy_set_wirespeed(struct tg3 *tp)
1637{
1638 u32 val;
1639
1640 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1641 return;
1642
1643 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1644 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1645 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1646 (val | (1 << 15) | (1 << 4)));
1647}
1648
b2a5c19c
MC		 1649static void tg3_phy_apply_otp(struct tg3 *tp)
1650{
1651 u32 otp, phy;
1652
1653 if (!tp->phy_otp)
1654 return;
1655
1656 otp = tp->phy_otp;
1657
1658 /* Enable SM_DSP clock and tx 6dB coding. */
1659 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1660 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1661 MII_TG3_AUXCTL_ACTL_TX_6DB;
1662 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1663
1664 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1665 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1666 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1667
1668 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1669 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1670 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1671
1672 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1673 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1674 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1675
1676 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1677 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1678
1679 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1680 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1681
1682 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1683 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1684 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1685
1686 /* Turn off SM_DSP clock. */
1687 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1688 MII_TG3_AUXCTL_ACTL_TX_6DB;
1689 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1690}
1691
1da177e4
LT		 1692static int tg3_wait_macro_done(struct tg3 *tp)
1693{
1694 int limit = 100;
1695
1696 while (limit--) {
1697 u32 tmp32;
1698
1699 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1700 if ((tmp32 & 0x1000) == 0)
1701 break;
1702 }
1703 }
d4675b52 1704 if (limit < 0)
1da177e4
LT		 1705 return -EBUSY;
1706
1707 return 0;
1708}
1709
1710static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1711{
1712 static const u32 test_pat[4][6] = {
1713 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1714 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1715 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1716 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1717 };
1718 int chan;
1719
1720 for (chan = 0; chan < 4; chan++) {
1721 int i;
1722
1723 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1724 (chan * 0x2000) | 0x0200);
1725 tg3_writephy(tp, 0x16, 0x0002);
1726
1727 for (i = 0; i < 6; i++)
1728 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1729 test_pat[chan][i]);
1730
1731 tg3_writephy(tp, 0x16, 0x0202);
1732 if (tg3_wait_macro_done(tp)) {
1733 *resetp = 1;
1734 return -EBUSY;
1735 }
1736
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1738 (chan * 0x2000) | 0x0200);
1739 tg3_writephy(tp, 0x16, 0x0082);
1740 if (tg3_wait_macro_done(tp)) {
1741 *resetp = 1;
1742 return -EBUSY;
1743 }
1744
1745 tg3_writephy(tp, 0x16, 0x0802);
1746 if (tg3_wait_macro_done(tp)) {
1747 *resetp = 1;
1748 return -EBUSY;
1749 }
1750
1751 for (i = 0; i < 6; i += 2) {
1752 u32 low, high;
1753
1754 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1755 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1756 tg3_wait_macro_done(tp)) {
1757 *resetp = 1;
1758 return -EBUSY;
1759 }
1760 low &= 0x7fff;
1761 high &= 0x000f;
1762 if (low != test_pat[chan][i] ||
1763 high != test_pat[chan][i+1]) {
1764 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1765 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1766 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1767
1768 return -EBUSY;
1769 }
1770 }
1771 }
1772
1773 return 0;
1774}
1775
1776static int tg3_phy_reset_chanpat(struct tg3 *tp)
1777{
1778 int chan;
1779
1780 for (chan = 0; chan < 4; chan++) {
1781 int i;
1782
1783 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784 (chan * 0x2000) | 0x0200);
1785 tg3_writephy(tp, 0x16, 0x0002);
1786 for (i = 0; i < 6; i++)
1787 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1788 tg3_writephy(tp, 0x16, 0x0202);
1789 if (tg3_wait_macro_done(tp))
1790 return -EBUSY;
1791 }
1792
1793 return 0;
1794}
1795
1796static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1797{
1798 u32 reg32, phy9_orig;
1799 int retries, do_phy_reset, err;
1800
1801 retries = 10;
1802 do_phy_reset = 1;
1803 do {
1804 if (do_phy_reset) {
1805 err = tg3_bmcr_reset(tp);
1806 if (err)
1807 return err;
1808 do_phy_reset = 0;
1809 }
1810
1811 /* Disable transmitter and interrupt. */
1812 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1813 continue;
1814
1815 reg32 |= 0x3000;
1816 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1817
1818 /* Set full-duplex, 1000 mbps. */
1819 tg3_writephy(tp, MII_BMCR,
1820 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1821
1822 /* Set to master mode. */
1823 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1824 continue;
1825
1826 tg3_writephy(tp, MII_TG3_CTRL,
1827 (MII_TG3_CTRL_AS_MASTER |
1828 MII_TG3_CTRL_ENABLE_AS_MASTER));
1829
1830 /* Enable SM_DSP_CLOCK and 6dB. */
1831 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1832
1833 /* Block the PHY control access. */
1834 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1835 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1836
1837 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1838 if (!err)
1839 break;
1840 } while (--retries);
1841
1842 err = tg3_phy_reset_chanpat(tp);
1843 if (err)
1844 return err;
1845
1846 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1847 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1848
1849 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1850 tg3_writephy(tp, 0x16, 0x0000);
1851
1852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1853 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1854 /* Set Extended packet length bit for jumbo frames */
1855 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1856 }
1857 else {
1858 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1859 }
1860
1861 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1862
1863 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1864 reg32 &= ~0x3000;
1865 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1866 } else if (!err)
1867 err = -EBUSY;
1868
1869 return err;
1870}
1871
1872/* This will reset the tigon3 PHY if there is no valid
1873 * link unless the FORCE argument is non-zero.
1874 */
1875static int tg3_phy_reset(struct tg3 *tp)
1876{
b2a5c19c 1877 u32 cpmuctrl;
1da177e4
LT		 1878 u32 phy_status;
1879 int err;
1880
60189ddf
MC		 1881 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1882 u32 val;
1883
1884 val = tr32(GRC_MISC_CFG);
1885 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1886 udelay(40);
1887 }
1da177e4
LT		 1888 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1889 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1890 if (err != 0)
1891 return -EBUSY;
1892
c8e1e82b
MC		 1893 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1894 netif_carrier_off(tp->dev);
1895 tg3_link_report(tp);
1896 }
1897
1da177e4
LT		 1898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1900 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1901 err = tg3_phy_reset_5703_4_5(tp);
1902 if (err)
1903 return err;
1904 goto out;
1905 }
1906
b2a5c19c
MC		 1907 cpmuctrl = 0;
1908 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1909 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1910 cpmuctrl = tr32(TG3_CPMU_CTRL);
1911 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1912 tw32(TG3_CPMU_CTRL,
1913 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1914 }
1915
1da177e4
LT		 1916 err = tg3_bmcr_reset(tp);
1917 if (err)
1918 return err;
1919
b2a5c19c
MC		 1920 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1921 u32 phy;
1922
1923 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1924 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1925
1926 tw32(TG3_CPMU_CTRL, cpmuctrl);
1927 }
1928
bcb37f6c
MC		 1929 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1930 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1931 u32 val;
1932
1933 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1934 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1935 CPMU_LSPD_1000MB_MACCLK_12_5) {
1936 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1937 udelay(40);
1938 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1939 }
1940 }
1941
b2a5c19c
MC		 1942 tg3_phy_apply_otp(tp);
1943
6833c043
MC		 1944 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1945 tg3_phy_toggle_apd(tp, true);
1946 else
1947 tg3_phy_toggle_apd(tp, false);
1948
1da177e4
LT		 1949out:
1950 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1951 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1952 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1953 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1955 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1956 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1957 }
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1959 tg3_writephy(tp, 0x1c, 0x8d68);
1960 tg3_writephy(tp, 0x1c, 0x8d68);
1961 }
1962 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1966 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1968 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1969 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1971 }
c424cb24
MC		 1972 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1973 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1975 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1977 tg3_writephy(tp, MII_TG3_TEST1,
1978 MII_TG3_TEST1_TRIM_EN | 0x4);
1979 } else
1980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1981 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1982 }
1da177e4
LT		 1983 /* Set Extended packet length bit (bit 14) on all chips that */
1984 /* support jumbo frames */
1985 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1986 /* Cannot do read-modify-write on 5401 */
1987 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1988 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1989 u32 phy_reg;
1990
1991 /* Set bit 14 with read-modify-write to preserve other bits */
1992 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1993 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1995 }
1996
1997 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1998 * jumbo frames transmission.
1999 */
8f666b07 2000 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2001 u32 phy_reg;
2002
2003 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2004 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2005 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2006 }
2007
715116a1 2008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2009 /* adjust output voltage */
535ef6e1 2010 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2011 }
2012
9ef8ca99 2013 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2014 tg3_phy_set_wirespeed(tp);
2015 return 0;
2016}
2017
2018static void tg3_frob_aux_power(struct tg3 *tp)
2019{
2020 struct tg3 *tp_peer = tp;
2021
9d26e213 2022 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2023 return;
2024
f6eb9b1f
MC		 2025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2028 struct net_device *dev_peer;
2029
2030 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2031 /* remove_one() may have been run on the peer. */
8c2dc7e1 2032 if (!dev_peer)
bc1c7567
MC		 2033 tp_peer = tp;
2034 else
2035 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2036 }
2037
1da177e4 2038 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2039 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2040 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2041 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2043 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2044 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2045 (GRC_LCLCTRL_GPIO_OE0 |
2046 GRC_LCLCTRL_GPIO_OE1 |
2047 GRC_LCLCTRL_GPIO_OE2 |
2048 GRC_LCLCTRL_GPIO_OUTPUT0 |
2049 GRC_LCLCTRL_GPIO_OUTPUT1),
2050 100);
8d519ab2
MC		 2051 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2052 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2053 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2054 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2055 GRC_LCLCTRL_GPIO_OE1 |
2056 GRC_LCLCTRL_GPIO_OE2 |
2057 GRC_LCLCTRL_GPIO_OUTPUT0 |
2058 GRC_LCLCTRL_GPIO_OUTPUT1 |
2059 tp->grc_local_ctrl;
2060 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061
2062 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2063 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2064
2065 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2066 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2067 } else {
2068 u32 no_gpio2;
dc56b7d4 2069 u32 grc_local_ctrl = 0;
1da177e4
LT		 2070
2071 if (tp_peer != tp &&
2072 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2073 return;
2074
dc56b7d4
MC		 2075 /* Workaround to prevent overdrawing Amps. */
2076 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2077 ASIC_REV_5714) {
2078 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2079 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2080 grc_local_ctrl, 100);
dc56b7d4
MC		 2081 }
2082
1da177e4
LT		 2083 /* On 5753 and variants, GPIO2 cannot be used. */
2084 no_gpio2 = tp->nic_sram_data_cfg &
2085 NIC_SRAM_DATA_CFG_NO_GPIO2;
2086
dc56b7d4 2087 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2088 GRC_LCLCTRL_GPIO_OE1 |
2089 GRC_LCLCTRL_GPIO_OE2 |
2090 GRC_LCLCTRL_GPIO_OUTPUT1 |
2091 GRC_LCLCTRL_GPIO_OUTPUT2;
2092 if (no_gpio2) {
2093 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2094 GRC_LCLCTRL_GPIO_OUTPUT2);
2095 }
b401e9e2
MC		 2096 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2097 grc_local_ctrl, 100);
1da177e4
LT		 2098
2099 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2100
b401e9e2
MC		 2101 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2102 grc_local_ctrl, 100);
1da177e4
LT		 2103
2104 if (!no_gpio2) {
2105 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2106 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107 grc_local_ctrl, 100);
1da177e4
LT		 2108 }
2109 }
2110 } else {
2111 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2112 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2113 if (tp_peer != tp &&
2114 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2115 return;
2116
b401e9e2
MC		 2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 (GRC_LCLCTRL_GPIO_OE1 |
2119 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2120
b401e9e2
MC		 2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2123
b401e9e2
MC		 2124 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125 (GRC_LCLCTRL_GPIO_OE1 |
2126 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2127 }
2128 }
2129}
2130
e8f3f6ca
MC		 2131static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2132{
2133 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2134 return 1;
2135 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2136 if (speed != SPEED_10)
2137 return 1;
2138 } else if (speed == SPEED_10)
2139 return 1;
2140
2141 return 0;
2142}
2143
1da177e4
LT		 2144static int tg3_setup_phy(struct tg3 *, int);
2145
2146#define RESET_KIND_SHUTDOWN 0
2147#define RESET_KIND_INIT 1
2148#define RESET_KIND_SUSPEND 2
2149
2150static void tg3_write_sig_post_reset(struct tg3 *, int);
2151static int tg3_halt_cpu(struct tg3 *, u32);
2152
0a459aac 2153static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2154{
ce057f01
MC		 2155 u32 val;
2156
5129724a
MC		 2157 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2159 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2160 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2161
2162 sg_dig_ctrl |=
2163 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2164 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2165 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2166 }
3f7045c1 2167 return;
5129724a 2168 }
3f7045c1 2169
60189ddf 2170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2171 tg3_bmcr_reset(tp);
2172 val = tr32(GRC_MISC_CFG);
2173 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2174 udelay(40);
2175 return;
0e5f784c
MC		 2176 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2177 u32 phytest;
2178 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2179 u32 phy;
2180
2181 tg3_writephy(tp, MII_ADVERTISE, 0);
2182 tg3_writephy(tp, MII_BMCR,
2183 BMCR_ANENABLE | BMCR_ANRESTART);
2184
2185 tg3_writephy(tp, MII_TG3_FET_TEST,
2186 phytest | MII_TG3_FET_SHADOW_EN);
2187 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2188 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2189 tg3_writephy(tp,
2190 MII_TG3_FET_SHDW_AUXMODE4,
2191 phy);
2192 }
2193 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2194 }
2195 return;
0a459aac 2196 } else if (do_low_power) {
715116a1
MC		 2197 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2198 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2199
2200 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2201 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2202 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2203 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2204 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2205 }
3f7045c1 2206
15c3b696
MC		 2207 /* The PHY should not be powered down on some chips because
2208 * of bugs.
2209 */
2210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2212 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2213 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2214 return;
ce057f01 2215
bcb37f6c
MC		 2216 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2217 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2218 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2219 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2220 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2221 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2222 }
2223
15c3b696
MC		 2224 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2225}
2226
ffbcfed4
MC		 2227/* tp->lock is held. */
2228static int tg3_nvram_lock(struct tg3 *tp)
2229{
2230 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2231 int i;
2232
2233 if (tp->nvram_lock_cnt == 0) {
2234 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2235 for (i = 0; i < 8000; i++) {
2236 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2237 break;
2238 udelay(20);
2239 }
2240 if (i == 8000) {
2241 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2242 return -ENODEV;
2243 }
2244 }
2245 tp->nvram_lock_cnt++;
2246 }
2247 return 0;
2248}
2249
2250/* tp->lock is held. */
2251static void tg3_nvram_unlock(struct tg3 *tp)
2252{
2253 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2254 if (tp->nvram_lock_cnt > 0)
2255 tp->nvram_lock_cnt--;
2256 if (tp->nvram_lock_cnt == 0)
2257 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2258 }
2259}
2260
2261/* tp->lock is held. */
2262static void tg3_enable_nvram_access(struct tg3 *tp)
2263{
2264 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2265 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2266 u32 nvaccess = tr32(NVRAM_ACCESS);
2267
2268 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2269 }
2270}
2271
2272/* tp->lock is held. */
2273static void tg3_disable_nvram_access(struct tg3 *tp)
2274{
2275 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2276 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2277 u32 nvaccess = tr32(NVRAM_ACCESS);
2278
2279 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2280 }
2281}
2282
2283static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2284 u32 offset, u32 *val)
2285{
2286 u32 tmp;
2287 int i;
2288
2289 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2290 return -EINVAL;
2291
2292 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2293 EEPROM_ADDR_DEVID_MASK |
2294 EEPROM_ADDR_READ);
2295 tw32(GRC_EEPROM_ADDR,
2296 tmp |
2297 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2298 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2299 EEPROM_ADDR_ADDR_MASK) |
2300 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2301
2302 for (i = 0; i < 1000; i++) {
2303 tmp = tr32(GRC_EEPROM_ADDR);
2304
2305 if (tmp & EEPROM_ADDR_COMPLETE)
2306 break;
2307 msleep(1);
2308 }
2309 if (!(tmp & EEPROM_ADDR_COMPLETE))
2310 return -EBUSY;
2311
62cedd11
MC		 2312 tmp = tr32(GRC_EEPROM_DATA);
2313
2314 /*
2315 * The data will always be opposite the native endian
2316 * format. Perform a blind byteswap to compensate.
2317 */
2318 *val = swab32(tmp);
2319
ffbcfed4
MC		 2320 return 0;
2321}
2322
2323#define NVRAM_CMD_TIMEOUT 10000
2324
2325static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2326{
2327 int i;
2328
2329 tw32(NVRAM_CMD, nvram_cmd);
2330 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2331 udelay(10);
2332 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2333 udelay(10);
2334 break;
2335 }
2336 }
2337
2338 if (i == NVRAM_CMD_TIMEOUT)
2339 return -EBUSY;
2340
2341 return 0;
2342}
2343
2344static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2345{
2346 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2347 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2348 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2349 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2350 (tp->nvram_jedecnum == JEDEC_ATMEL))
2351
2352 addr = ((addr / tp->nvram_pagesize) <<
2353 ATMEL_AT45DB0X1B_PAGE_POS) +
2354 (addr % tp->nvram_pagesize);
2355
2356 return addr;
2357}
2358
2359static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2360{
2361 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365 (tp->nvram_jedecnum == JEDEC_ATMEL))
2366
2367 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2368 tp->nvram_pagesize) +
2369 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2370
2371 return addr;
2372}
2373
e4f34110
MC		 2374/* NOTE: Data read in from NVRAM is byteswapped according to
2375 * the byteswapping settings for all other register accesses.
2376 * tg3 devices are BE devices, so on a BE machine, the data
2377 * returned will be exactly as it is seen in NVRAM. On a LE
2378 * machine, the 32-bit value will be byteswapped.
2379 */
ffbcfed4
MC		 2380static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2381{
2382 int ret;
2383
2384 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2385 return tg3_nvram_read_using_eeprom(tp, offset, val);
2386
2387 offset = tg3_nvram_phys_addr(tp, offset);
2388
2389 if (offset > NVRAM_ADDR_MSK)
2390 return -EINVAL;
2391
2392 ret = tg3_nvram_lock(tp);
2393 if (ret)
2394 return ret;
2395
2396 tg3_enable_nvram_access(tp);
2397
2398 tw32(NVRAM_ADDR, offset);
2399 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2400 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2401
2402 if (ret == 0)
e4f34110 2403 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2404
2405 tg3_disable_nvram_access(tp);
2406
2407 tg3_nvram_unlock(tp);
2408
2409 return ret;
2410}
2411
a9dc529d
MC		 2412/* Ensures NVRAM data is in bytestream format. */
2413static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2414{
2415 u32 v;
a9dc529d 2416 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2417 if (!res)
a9dc529d 2418 *val = cpu_to_be32(v);
ffbcfed4
MC		 2419 return res;
2420}
2421
3f007891
MC		 2422/* tp->lock is held. */
2423static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2424{
2425 u32 addr_high, addr_low;
2426 int i;
2427
2428 addr_high = ((tp->dev->dev_addr[0] << 8) |
2429 tp->dev->dev_addr[1]);
2430 addr_low = ((tp->dev->dev_addr[2] << 24) |
2431 (tp->dev->dev_addr[3] << 16) |
2432 (tp->dev->dev_addr[4] << 8) |
2433 (tp->dev->dev_addr[5] << 0));
2434 for (i = 0; i < 4; i++) {
2435 if (i == 1 && skip_mac_1)
2436 continue;
2437 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2438 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2439 }
2440
2441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2443 for (i = 0; i < 12; i++) {
2444 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2445 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2446 }
2447 }
2448
2449 addr_high = (tp->dev->dev_addr[0] +
2450 tp->dev->dev_addr[1] +
2451 tp->dev->dev_addr[2] +
2452 tp->dev->dev_addr[3] +
2453 tp->dev->dev_addr[4] +
2454 tp->dev->dev_addr[5]) &
2455 TX_BACKOFF_SEED_MASK;
2456 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2457}
2458
bc1c7567 2459static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2460{
2461 u32 misc_host_ctrl;
0a459aac 2462 bool device_should_wake, do_low_power;
1da177e4
LT		 2463
2464 /* Make sure register accesses (indirect or otherwise)
2465 * will function correctly.
2466 */
2467 pci_write_config_dword(tp->pdev,
2468 TG3PCI_MISC_HOST_CTRL,
2469 tp->misc_host_ctrl);
2470
1da177e4 2471 switch (state) {
bc1c7567 2472 case PCI_D0:
12dac075
RW		 2473 pci_enable_wake(tp->pdev, state, false);
2474 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2475
9d26e213
MC		 2476 /* Switch out of Vaux if it is a NIC */
2477 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2478 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2479
2480 return 0;
2481
bc1c7567 2482 case PCI_D1:
bc1c7567 2483 case PCI_D2:
bc1c7567 2484 case PCI_D3hot:
1da177e4
LT		 2485 break;
2486
2487 default:
12dac075
RW		 2488 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2489 tp->dev->name, state);
1da177e4 2490 return -EINVAL;
855e1111 2491 }
5e7dfd0f
MC		 2492
2493 /* Restore the CLKREQ setting. */
2494 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2495 u16 lnkctl;
2496
2497 pci_read_config_word(tp->pdev,
2498 tp->pcie_cap + PCI_EXP_LNKCTL,
2499 &lnkctl);
2500 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2501 pci_write_config_word(tp->pdev,
2502 tp->pcie_cap + PCI_EXP_LNKCTL,
2503 lnkctl);
2504 }
2505
1da177e4
LT		 2506 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2507 tw32(TG3PCI_MISC_HOST_CTRL,
2508 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2509
05ac4cb7
MC		 2510 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2511 device_may_wakeup(&tp->pdev->dev) &&
2512 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2513
dd477003 2514 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2515 do_low_power = false;
b02fd9e3
MC		 2516 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2517 !tp->link_config.phy_is_low_power) {
2518 struct phy_device *phydev;
0a459aac 2519 u32 phyid, advertising;
b02fd9e3 2520
3f0e3ad7 2521 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2522
2523 tp->link_config.phy_is_low_power = 1;
2524
2525 tp->link_config.orig_speed = phydev->speed;
2526 tp->link_config.orig_duplex = phydev->duplex;
2527 tp->link_config.orig_autoneg = phydev->autoneg;
2528 tp->link_config.orig_advertising = phydev->advertising;
2529
2530 advertising = ADVERTISED_TP |
2531 ADVERTISED_Pause |
2532 ADVERTISED_Autoneg |
2533 ADVERTISED_10baseT_Half;
2534
2535 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2536 device_should_wake) {
b02fd9e3
MC		 2537 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2538 advertising |=
2539 ADVERTISED_100baseT_Half |
2540 ADVERTISED_100baseT_Full |
2541 ADVERTISED_10baseT_Full;
2542 else
2543 advertising |= ADVERTISED_10baseT_Full;
2544 }
2545
2546 phydev->advertising = advertising;
2547
2548 phy_start_aneg(phydev);
0a459aac
MC		 2549
2550 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2551 if (phyid != TG3_PHY_ID_BCMAC131) {
2552 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2553 if (phyid == TG3_PHY_OUI_1 ||
2554 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2555 phyid == TG3_PHY_OUI_3)
2556 do_low_power = true;
2557 }
b02fd9e3 2558 }
dd477003 2559 } else {
2023276e 2560 do_low_power = true;
0a459aac 2561
dd477003
MC		 2562 if (tp->link_config.phy_is_low_power == 0) {
2563 tp->link_config.phy_is_low_power = 1;
2564 tp->link_config.orig_speed = tp->link_config.speed;
2565 tp->link_config.orig_duplex = tp->link_config.duplex;
2566 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2567 }
1da177e4 2568
dd477003
MC		 2569 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2570 tp->link_config.speed = SPEED_10;
2571 tp->link_config.duplex = DUPLEX_HALF;
2572 tp->link_config.autoneg = AUTONEG_ENABLE;
2573 tg3_setup_phy(tp, 0);
2574 }
1da177e4
LT		 2575 }
2576
b5d3772c
MC		 2577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2578 u32 val;
2579
2580 val = tr32(GRC_VCPU_EXT_CTRL);
2581 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2582 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2583 int i;
2584 u32 val;
2585
2586 for (i = 0; i < 200; i++) {
2587 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2588 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2589 break;
2590 msleep(1);
2591 }
2592 }
a85feb8c
GZ		 2593 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2594 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2595 WOL_DRV_STATE_SHUTDOWN |
2596 WOL_DRV_WOL |
2597 WOL_SET_MAGIC_PKT);
6921d201 2598
05ac4cb7 2599 if (device_should_wake) {
1da177e4
LT		 2600 u32 mac_mode;
2601
2602 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2603 if (do_low_power) {
dd477003
MC		 2604 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2605 udelay(40);
2606 }
1da177e4 2607
3f7045c1
MC		 2608 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2609 mac_mode = MAC_MODE_PORT_MODE_GMII;
2610 else
2611 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2612
e8f3f6ca
MC		 2613 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2614 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2615 ASIC_REV_5700) {
2616 u32 speed = (tp->tg3_flags &
2617 TG3_FLAG_WOL_SPEED_100MB) ?
2618 SPEED_100 : SPEED_10;
2619 if (tg3_5700_link_polarity(tp, speed))
2620 mac_mode |= MAC_MODE_LINK_POLARITY;
2621 else
2622 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2623 }
1da177e4
LT		 2624 } else {
2625 mac_mode = MAC_MODE_PORT_MODE_TBI;
2626 }
2627
cbf46853 2628 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2629 tw32(MAC_LED_CTRL, tp->led_ctrl);
2630
05ac4cb7
MC		 2631 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2632 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2633 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2634 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2635 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2636 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2637
3bda1258
MC		 2638 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2639 mac_mode |= tp->mac_mode &
2640 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2641 if (mac_mode & MAC_MODE_APE_TX_EN)
2642 mac_mode |= MAC_MODE_TDE_ENABLE;
2643 }
2644
1da177e4
LT		 2645 tw32_f(MAC_MODE, mac_mode);
2646 udelay(100);
2647
2648 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2649 udelay(10);
2650 }
2651
2652 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2653 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2655 u32 base_val;
2656
2657 base_val = tp->pci_clock_ctrl;
2658 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2659 CLOCK_CTRL_TXCLK_DISABLE);
2660
b401e9e2
MC		 2661 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2662 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2663 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2664 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2665 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2666 /* do nothing */
85e94ced 2667 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2668 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2669 u32 newbits1, newbits2;
2670
2671 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2673 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2674 CLOCK_CTRL_TXCLK_DISABLE |
2675 CLOCK_CTRL_ALTCLK);
2676 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2677 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2678 newbits1 = CLOCK_CTRL_625_CORE;
2679 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2680 } else {
2681 newbits1 = CLOCK_CTRL_ALTCLK;
2682 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2683 }
2684
b401e9e2
MC		 2685 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2686 40);
1da177e4 2687
b401e9e2
MC		 2688 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2689 40);
1da177e4
LT		 2690
2691 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2692 u32 newbits3;
2693
2694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2696 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2697 CLOCK_CTRL_TXCLK_DISABLE |
2698 CLOCK_CTRL_44MHZ_CORE);
2699 } else {
2700 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2701 }
2702
b401e9e2
MC		 2703 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2704 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2705 }
2706 }
2707
05ac4cb7 2708 if (!(device_should_wake) &&
22435849 2709 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2710 tg3_power_down_phy(tp, do_low_power);
6921d201 2711
1da177e4
LT		 2712 tg3_frob_aux_power(tp);
2713
2714 /* Workaround for unstable PLL clock */
2715 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2716 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2717 u32 val = tr32(0x7d00);
2718
2719 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2720 tw32(0x7d00, val);
6921d201 2721 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2722 int err;
2723
2724 err = tg3_nvram_lock(tp);
1da177e4 2725 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2726 if (!err)
2727 tg3_nvram_unlock(tp);
6921d201 2728 }
1da177e4
LT		 2729 }
2730
bbadf503
MC		 2731 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2732
05ac4cb7 2733 if (device_should_wake)
12dac075
RW		 2734 pci_enable_wake(tp->pdev, state, true);
2735
1da177e4 2736 /* Finally, set the new power state. */
12dac075 2737 pci_set_power_state(tp->pdev, state);
1da177e4 2738
1da177e4
LT		 2739 return 0;
2740}
2741
1da177e4
LT		 2742static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2743{
2744 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2745 case MII_TG3_AUX_STAT_10HALF:
2746 *speed = SPEED_10;
2747 *duplex = DUPLEX_HALF;
2748 break;
2749
2750 case MII_TG3_AUX_STAT_10FULL:
2751 *speed = SPEED_10;
2752 *duplex = DUPLEX_FULL;
2753 break;
2754
2755 case MII_TG3_AUX_STAT_100HALF:
2756 *speed = SPEED_100;
2757 *duplex = DUPLEX_HALF;
2758 break;
2759
2760 case MII_TG3_AUX_STAT_100FULL:
2761 *speed = SPEED_100;
2762 *duplex = DUPLEX_FULL;
2763 break;
2764
2765 case MII_TG3_AUX_STAT_1000HALF:
2766 *speed = SPEED_1000;
2767 *duplex = DUPLEX_HALF;
2768 break;
2769
2770 case MII_TG3_AUX_STAT_1000FULL:
2771 *speed = SPEED_1000;
2772 *duplex = DUPLEX_FULL;
2773 break;
2774
2775 default:
7f97a4bd 2776 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2777 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2778 SPEED_10;
2779 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2780 DUPLEX_HALF;
2781 break;
2782 }
1da177e4
LT		 2783 *speed = SPEED_INVALID;
2784 *duplex = DUPLEX_INVALID;
2785 break;
855e1111 2786 }
1da177e4
LT		 2787}
2788
2789static void tg3_phy_copper_begin(struct tg3 *tp)
2790{
2791 u32 new_adv;
2792 int i;
2793
2794 if (tp->link_config.phy_is_low_power) {
2795 /* Entering low power mode. Disable gigabit and
2796 * 100baseT advertisements.
2797 */
2798 tg3_writephy(tp, MII_TG3_CTRL, 0);
2799
2800 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2801 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2802 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2803 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2804
2805 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2806 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2807 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2808 tp->link_config.advertising &=
2809 ~(ADVERTISED_1000baseT_Half |
2810 ADVERTISED_1000baseT_Full);
2811
ba4d07a8 2812 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2813 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2814 new_adv |= ADVERTISE_10HALF;
2815 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2816 new_adv |= ADVERTISE_10FULL;
2817 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2818 new_adv |= ADVERTISE_100HALF;
2819 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2820 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2821
2822 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2823
1da177e4
LT		 2824 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2825
2826 if (tp->link_config.advertising &
2827 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2828 new_adv = 0;
2829 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2830 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2831 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2832 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2833 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2834 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2835 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2836 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2837 MII_TG3_CTRL_ENABLE_AS_MASTER);
2838 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2839 } else {
2840 tg3_writephy(tp, MII_TG3_CTRL, 0);
2841 }
2842 } else {
ba4d07a8
MC		 2843 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2844 new_adv |= ADVERTISE_CSMA;
2845
1da177e4
LT		 2846 /* Asking for a specific link mode. */
2847 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2848 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2849
2850 if (tp->link_config.duplex == DUPLEX_FULL)
2851 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2852 else
2853 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2854 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2855 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2856 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2857 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2858 } else {
1da177e4
LT		 2859 if (tp->link_config.speed == SPEED_100) {
2860 if (tp->link_config.duplex == DUPLEX_FULL)
2861 new_adv |= ADVERTISE_100FULL;
2862 else
2863 new_adv |= ADVERTISE_100HALF;
2864 } else {
2865 if (tp->link_config.duplex == DUPLEX_FULL)
2866 new_adv |= ADVERTISE_10FULL;
2867 else
2868 new_adv |= ADVERTISE_10HALF;
2869 }
2870 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2871
2872 new_adv = 0;
1da177e4 2873 }
ba4d07a8
MC		 2874
2875 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2876 }
2877
2878 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2879 tp->link_config.speed != SPEED_INVALID) {
2880 u32 bmcr, orig_bmcr;
2881
2882 tp->link_config.active_speed = tp->link_config.speed;
2883 tp->link_config.active_duplex = tp->link_config.duplex;
2884
2885 bmcr = 0;
2886 switch (tp->link_config.speed) {
2887 default:
2888 case SPEED_10:
2889 break;
2890
2891 case SPEED_100:
2892 bmcr |= BMCR_SPEED100;
2893 break;
2894
2895 case SPEED_1000:
2896 bmcr |= TG3_BMCR_SPEED1000;
2897 break;
855e1111 2898 }
1da177e4
LT		 2899
2900 if (tp->link_config.duplex == DUPLEX_FULL)
2901 bmcr |= BMCR_FULLDPLX;
2902
2903 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2904 (bmcr != orig_bmcr)) {
2905 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2906 for (i = 0; i < 1500; i++) {
2907 u32 tmp;
2908
2909 udelay(10);
2910 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2911 tg3_readphy(tp, MII_BMSR, &tmp))
2912 continue;
2913 if (!(tmp & BMSR_LSTATUS)) {
2914 udelay(40);
2915 break;
2916 }
2917 }
2918 tg3_writephy(tp, MII_BMCR, bmcr);
2919 udelay(40);
2920 }
2921 } else {
2922 tg3_writephy(tp, MII_BMCR,
2923 BMCR_ANENABLE | BMCR_ANRESTART);
2924 }
2925}
2926
2927static int tg3_init_5401phy_dsp(struct tg3 *tp)
2928{
2929 int err;
2930
2931 /* Turn off tap power management. */
2932 /* Set Extended packet length bit */
2933 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2934
2935 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2936 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2937
2938 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2939 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2940
2941 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2942 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2943
2944 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2945 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2946
2947 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2948 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2949
2950 udelay(40);
2951
2952 return err;
2953}
2954
3600d918 2955static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2956{
3600d918
MC		 2957 u32 adv_reg, all_mask = 0;
2958
2959 if (mask & ADVERTISED_10baseT_Half)
2960 all_mask |= ADVERTISE_10HALF;
2961 if (mask & ADVERTISED_10baseT_Full)
2962 all_mask |= ADVERTISE_10FULL;
2963 if (mask & ADVERTISED_100baseT_Half)
2964 all_mask |= ADVERTISE_100HALF;
2965 if (mask & ADVERTISED_100baseT_Full)
2966 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2967
2968 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2969 return 0;
2970
1da177e4
LT		 2971 if ((adv_reg & all_mask) != all_mask)
2972 return 0;
2973 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2974 u32 tg3_ctrl;
2975
3600d918
MC		 2976 all_mask = 0;
2977 if (mask & ADVERTISED_1000baseT_Half)
2978 all_mask |= ADVERTISE_1000HALF;
2979 if (mask & ADVERTISED_1000baseT_Full)
2980 all_mask |= ADVERTISE_1000FULL;
2981
1da177e4
LT		 2982 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2983 return 0;
2984
1da177e4
LT		 2985 if ((tg3_ctrl & all_mask) != all_mask)
2986 return 0;
2987 }
2988 return 1;
2989}
2990
ef167e27
MC		 2991static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2992{
2993 u32 curadv, reqadv;
2994
2995 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2996 return 1;
2997
2998 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2999 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3000
3001 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3002 if (curadv != reqadv)
3003 return 0;
3004
3005 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3006 tg3_readphy(tp, MII_LPA, rmtadv);
3007 } else {
3008 /* Reprogram the advertisement register, even if it
3009 * does not affect the current link. If the link
3010 * gets renegotiated in the future, we can save an
3011 * additional renegotiation cycle by advertising
3012 * it correctly in the first place.
3013 */
3014 if (curadv != reqadv) {
3015 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3016 ADVERTISE_PAUSE_ASYM);
3017 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3018 }
3019 }
3020
3021 return 1;
3022}
3023
1da177e4
LT		 3024static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3025{
3026 int current_link_up;
3027 u32 bmsr, dummy;
ef167e27 3028 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3029 u16 current_speed;
3030 u8 current_duplex;
3031 int i, err;
3032
3033 tw32(MAC_EVENT, 0);
3034
3035 tw32_f(MAC_STATUS,
3036 (MAC_STATUS_SYNC_CHANGED |
3037 MAC_STATUS_CFG_CHANGED |
3038 MAC_STATUS_MI_COMPLETION |
3039 MAC_STATUS_LNKSTATE_CHANGED));
3040 udelay(40);
3041
8ef21428
MC		 3042 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3043 tw32_f(MAC_MI_MODE,
3044 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3045 udelay(80);
3046 }
1da177e4
LT		 3047
3048 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3049
3050 /* Some third-party PHYs need to be reset on link going
3051 * down.
3052 */
3053 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3056 netif_carrier_ok(tp->dev)) {
3057 tg3_readphy(tp, MII_BMSR, &bmsr);
3058 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3059 !(bmsr & BMSR_LSTATUS))
3060 force_reset = 1;
3061 }
3062 if (force_reset)
3063 tg3_phy_reset(tp);
3064
3065 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3066 tg3_readphy(tp, MII_BMSR, &bmsr);
3067 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3068 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3069 bmsr = 0;
3070
3071 if (!(bmsr & BMSR_LSTATUS)) {
3072 err = tg3_init_5401phy_dsp(tp);
3073 if (err)
3074 return err;
3075
3076 tg3_readphy(tp, MII_BMSR, &bmsr);
3077 for (i = 0; i < 1000; i++) {
3078 udelay(10);
3079 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3080 (bmsr & BMSR_LSTATUS)) {
3081 udelay(40);
3082 break;
3083 }
3084 }
3085
3086 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3087 !(bmsr & BMSR_LSTATUS) &&
3088 tp->link_config.active_speed == SPEED_1000) {
3089 err = tg3_phy_reset(tp);
3090 if (!err)
3091 err = tg3_init_5401phy_dsp(tp);
3092 if (err)
3093 return err;
3094 }
3095 }
3096 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3097 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3098 /* 5701 {A0,B0} CRC bug workaround */
3099 tg3_writephy(tp, 0x15, 0x0a75);
3100 tg3_writephy(tp, 0x1c, 0x8c68);
3101 tg3_writephy(tp, 0x1c, 0x8d68);
3102 tg3_writephy(tp, 0x1c, 0x8c68);
3103 }
3104
3105 /* Clear pending interrupts... */
3106 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3107 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3108
3109 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3110 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3111 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3112 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3113
3114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3116 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3117 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3118 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3119 else
3120 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3121 }
3122
3123 current_link_up = 0;
3124 current_speed = SPEED_INVALID;
3125 current_duplex = DUPLEX_INVALID;
3126
3127 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3128 u32 val;
3129
3130 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3131 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3132 if (!(val & (1 << 10))) {
3133 val |= (1 << 10);
3134 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3135 goto relink;
3136 }
3137 }
3138
3139 bmsr = 0;
3140 for (i = 0; i < 100; i++) {
3141 tg3_readphy(tp, MII_BMSR, &bmsr);
3142 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3143 (bmsr & BMSR_LSTATUS))
3144 break;
3145 udelay(40);
3146 }
3147
3148 if (bmsr & BMSR_LSTATUS) {
3149 u32 aux_stat, bmcr;
3150
3151 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3152 for (i = 0; i < 2000; i++) {
3153 udelay(10);
3154 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3155 aux_stat)
3156 break;
3157 }
3158
3159 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3160 &current_speed,
3161 &current_duplex);
3162
3163 bmcr = 0;
3164 for (i = 0; i < 200; i++) {
3165 tg3_readphy(tp, MII_BMCR, &bmcr);
3166 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3167 continue;
3168 if (bmcr && bmcr != 0x7fff)
3169 break;
3170 udelay(10);
3171 }
3172
ef167e27
MC		 3173 lcl_adv = 0;
3174 rmt_adv = 0;
1da177e4 3175
ef167e27
MC		 3176 tp->link_config.active_speed = current_speed;
3177 tp->link_config.active_duplex = current_duplex;
3178
3179 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3180 if ((bmcr & BMCR_ANENABLE) &&
3181 tg3_copper_is_advertising_all(tp,
3182 tp->link_config.advertising)) {
3183 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3184 &rmt_adv))
3185 current_link_up = 1;
1da177e4
LT		 3186 }
3187 } else {
3188 if (!(bmcr & BMCR_ANENABLE) &&
3189 tp->link_config.speed == current_speed &&
ef167e27
MC		 3190 tp->link_config.duplex == current_duplex &&
3191 tp->link_config.flowctrl ==
3192 tp->link_config.active_flowctrl) {
1da177e4 3193 current_link_up = 1;
1da177e4
LT		 3194 }
3195 }
3196
ef167e27
MC		 3197 if (current_link_up == 1 &&
3198 tp->link_config.active_duplex == DUPLEX_FULL)
3199 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3200 }
3201
1da177e4 3202relink:
6921d201 3203 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3204 u32 tmp;
3205
3206 tg3_phy_copper_begin(tp);
3207
3208 tg3_readphy(tp, MII_BMSR, &tmp);
3209 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3210 (tmp & BMSR_LSTATUS))
3211 current_link_up = 1;
3212 }
3213
3214 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3215 if (current_link_up == 1) {
3216 if (tp->link_config.active_speed == SPEED_100 ||
3217 tp->link_config.active_speed == SPEED_10)
3218 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219 else
3220 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3221 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3222 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3223 else
1da177e4
LT		 3224 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3225
3226 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3227 if (tp->link_config.active_duplex == DUPLEX_HALF)
3228 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3229
1da177e4 3230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3231 if (current_link_up == 1 &&
3232 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3233 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3234 else
3235 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3236 }
3237
3238 /* ??? Without this setting Netgear GA302T PHY does not
3239 * ??? send/receive packets...
3240 */
3241 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3242 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3243 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3244 tw32_f(MAC_MI_MODE, tp->mi_mode);
3245 udelay(80);
3246 }
3247
3248 tw32_f(MAC_MODE, tp->mac_mode);
3249 udelay(40);
3250
3251 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3252 /* Polled via timer. */
3253 tw32_f(MAC_EVENT, 0);
3254 } else {
3255 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3256 }
3257 udelay(40);
3258
3259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3260 current_link_up == 1 &&
3261 tp->link_config.active_speed == SPEED_1000 &&
3262 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3263 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3264 udelay(120);
3265 tw32_f(MAC_STATUS,
3266 (MAC_STATUS_SYNC_CHANGED |
3267 MAC_STATUS_CFG_CHANGED));
3268 udelay(40);
3269 tg3_write_mem(tp,
3270 NIC_SRAM_FIRMWARE_MBOX,
3271 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3272 }
3273
5e7dfd0f
MC		 3274 /* Prevent send BD corruption. */
3275 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3276 u16 oldlnkctl, newlnkctl;
3277
3278 pci_read_config_word(tp->pdev,
3279 tp->pcie_cap + PCI_EXP_LNKCTL,
3280 &oldlnkctl);
3281 if (tp->link_config.active_speed == SPEED_100 ||
3282 tp->link_config.active_speed == SPEED_10)
3283 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3284 else
3285 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3286 if (newlnkctl != oldlnkctl)
3287 pci_write_config_word(tp->pdev,
3288 tp->pcie_cap + PCI_EXP_LNKCTL,
3289 newlnkctl);
3290 }
3291
1da177e4
LT		 3292 if (current_link_up != netif_carrier_ok(tp->dev)) {
3293 if (current_link_up)
3294 netif_carrier_on(tp->dev);
3295 else
3296 netif_carrier_off(tp->dev);
3297 tg3_link_report(tp);
3298 }
3299
3300 return 0;
3301}
3302
3303struct tg3_fiber_aneginfo {
3304 int state;
3305#define ANEG_STATE_UNKNOWN 0
3306#define ANEG_STATE_AN_ENABLE 1
3307#define ANEG_STATE_RESTART_INIT 2
3308#define ANEG_STATE_RESTART 3
3309#define ANEG_STATE_DISABLE_LINK_OK 4
3310#define ANEG_STATE_ABILITY_DETECT_INIT 5
3311#define ANEG_STATE_ABILITY_DETECT 6
3312#define ANEG_STATE_ACK_DETECT_INIT 7
3313#define ANEG_STATE_ACK_DETECT 8
3314#define ANEG_STATE_COMPLETE_ACK_INIT 9
3315#define ANEG_STATE_COMPLETE_ACK 10
3316#define ANEG_STATE_IDLE_DETECT_INIT 11
3317#define ANEG_STATE_IDLE_DETECT 12
3318#define ANEG_STATE_LINK_OK 13
3319#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3320#define ANEG_STATE_NEXT_PAGE_WAIT 15
3321
3322 u32 flags;
3323#define MR_AN_ENABLE 0x00000001
3324#define MR_RESTART_AN 0x00000002
3325#define MR_AN_COMPLETE 0x00000004
3326#define MR_PAGE_RX 0x00000008
3327#define MR_NP_LOADED 0x00000010
3328#define MR_TOGGLE_TX 0x00000020
3329#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3330#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3331#define MR_LP_ADV_SYM_PAUSE 0x00000100
3332#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3333#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3334#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3335#define MR_LP_ADV_NEXT_PAGE 0x00001000
3336#define MR_TOGGLE_RX 0x00002000
3337#define MR_NP_RX 0x00004000
3338
3339#define MR_LINK_OK 0x80000000
3340
3341 unsigned long link_time, cur_time;
3342
3343 u32 ability_match_cfg;
3344 int ability_match_count;
3345
3346 char ability_match, idle_match, ack_match;
3347
3348 u32 txconfig, rxconfig;
3349#define ANEG_CFG_NP 0x00000080
3350#define ANEG_CFG_ACK 0x00000040
3351#define ANEG_CFG_RF2 0x00000020
3352#define ANEG_CFG_RF1 0x00000010
3353#define ANEG_CFG_PS2 0x00000001
3354#define ANEG_CFG_PS1 0x00008000
3355#define ANEG_CFG_HD 0x00004000
3356#define ANEG_CFG_FD 0x00002000
3357#define ANEG_CFG_INVAL 0x00001f06
3358
3359};
3360#define ANEG_OK 0
3361#define ANEG_DONE 1
3362#define ANEG_TIMER_ENAB 2
3363#define ANEG_FAILED -1
3364
3365#define ANEG_STATE_SETTLE_TIME 10000
3366
3367static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3368 struct tg3_fiber_aneginfo *ap)
3369{
5be73b47 3370 u16 flowctrl;
1da177e4
LT		 3371 unsigned long delta;
3372 u32 rx_cfg_reg;
3373 int ret;
3374
3375 if (ap->state == ANEG_STATE_UNKNOWN) {
3376 ap->rxconfig = 0;
3377 ap->link_time = 0;
3378 ap->cur_time = 0;
3379 ap->ability_match_cfg = 0;
3380 ap->ability_match_count = 0;
3381 ap->ability_match = 0;
3382 ap->idle_match = 0;
3383 ap->ack_match = 0;
3384 }
3385 ap->cur_time++;
3386
3387 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3388 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3389
3390 if (rx_cfg_reg != ap->ability_match_cfg) {
3391 ap->ability_match_cfg = rx_cfg_reg;
3392 ap->ability_match = 0;
3393 ap->ability_match_count = 0;
3394 } else {
3395 if (++ap->ability_match_count > 1) {
3396 ap->ability_match = 1;
3397 ap->ability_match_cfg = rx_cfg_reg;
3398 }
3399 }
3400 if (rx_cfg_reg & ANEG_CFG_ACK)
3401 ap->ack_match = 1;
3402 else
3403 ap->ack_match = 0;
3404
3405 ap->idle_match = 0;
3406 } else {
3407 ap->idle_match = 1;
3408 ap->ability_match_cfg = 0;
3409 ap->ability_match_count = 0;
3410 ap->ability_match = 0;
3411 ap->ack_match = 0;
3412
3413 rx_cfg_reg = 0;
3414 }
3415
3416 ap->rxconfig = rx_cfg_reg;
3417 ret = ANEG_OK;
3418
3419 switch(ap->state) {
3420 case ANEG_STATE_UNKNOWN:
3421 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3422 ap->state = ANEG_STATE_AN_ENABLE;
3423
3424 /* fallthru */
3425 case ANEG_STATE_AN_ENABLE:
3426 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3427 if (ap->flags & MR_AN_ENABLE) {
3428 ap->link_time = 0;
3429 ap->cur_time = 0;
3430 ap->ability_match_cfg = 0;
3431 ap->ability_match_count = 0;
3432 ap->ability_match = 0;
3433 ap->idle_match = 0;
3434 ap->ack_match = 0;
3435
3436 ap->state = ANEG_STATE_RESTART_INIT;
3437 } else {
3438 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3439 }
3440 break;
3441
3442 case ANEG_STATE_RESTART_INIT:
3443 ap->link_time = ap->cur_time;
3444 ap->flags &= ~(MR_NP_LOADED);
3445 ap->txconfig = 0;
3446 tw32(MAC_TX_AUTO_NEG, 0);
3447 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3448 tw32_f(MAC_MODE, tp->mac_mode);
3449 udelay(40);
3450
3451 ret = ANEG_TIMER_ENAB;
3452 ap->state = ANEG_STATE_RESTART;
3453
3454 /* fallthru */
3455 case ANEG_STATE_RESTART:
3456 delta = ap->cur_time - ap->link_time;
3457 if (delta > ANEG_STATE_SETTLE_TIME) {
3458 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3459 } else {
3460 ret = ANEG_TIMER_ENAB;
3461 }
3462 break;
3463
3464 case ANEG_STATE_DISABLE_LINK_OK:
3465 ret = ANEG_DONE;
3466 break;
3467
3468 case ANEG_STATE_ABILITY_DETECT_INIT:
3469 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3470 ap->txconfig = ANEG_CFG_FD;
3471 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3472 if (flowctrl & ADVERTISE_1000XPAUSE)
3473 ap->txconfig |= ANEG_CFG_PS1;
3474 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3475 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3476 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3477 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3478 tw32_f(MAC_MODE, tp->mac_mode);
3479 udelay(40);
3480
3481 ap->state = ANEG_STATE_ABILITY_DETECT;
3482 break;
3483
3484 case ANEG_STATE_ABILITY_DETECT:
3485 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3486 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3487 }
3488 break;
3489
3490 case ANEG_STATE_ACK_DETECT_INIT:
3491 ap->txconfig |= ANEG_CFG_ACK;
3492 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3493 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3494 tw32_f(MAC_MODE, tp->mac_mode);
3495 udelay(40);
3496
3497 ap->state = ANEG_STATE_ACK_DETECT;
3498
3499 /* fallthru */
3500 case ANEG_STATE_ACK_DETECT:
3501 if (ap->ack_match != 0) {
3502 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3503 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3504 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3505 } else {
3506 ap->state = ANEG_STATE_AN_ENABLE;
3507 }
3508 } else if (ap->ability_match != 0 &&
3509 ap->rxconfig == 0) {
3510 ap->state = ANEG_STATE_AN_ENABLE;
3511 }
3512 break;
3513
3514 case ANEG_STATE_COMPLETE_ACK_INIT:
3515 if (ap->rxconfig & ANEG_CFG_INVAL) {
3516 ret = ANEG_FAILED;
3517 break;
3518 }
3519 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3520 MR_LP_ADV_HALF_DUPLEX |
3521 MR_LP_ADV_SYM_PAUSE |
3522 MR_LP_ADV_ASYM_PAUSE |
3523 MR_LP_ADV_REMOTE_FAULT1 |
3524 MR_LP_ADV_REMOTE_FAULT2 |
3525 MR_LP_ADV_NEXT_PAGE |
3526 MR_TOGGLE_RX |
3527 MR_NP_RX);
3528 if (ap->rxconfig & ANEG_CFG_FD)
3529 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3530 if (ap->rxconfig & ANEG_CFG_HD)
3531 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3532 if (ap->rxconfig & ANEG_CFG_PS1)
3533 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3534 if (ap->rxconfig & ANEG_CFG_PS2)
3535 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3536 if (ap->rxconfig & ANEG_CFG_RF1)
3537 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3538 if (ap->rxconfig & ANEG_CFG_RF2)
3539 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3540 if (ap->rxconfig & ANEG_CFG_NP)
3541 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3542
3543 ap->link_time = ap->cur_time;
3544
3545 ap->flags ^= (MR_TOGGLE_TX);
3546 if (ap->rxconfig & 0x0008)
3547 ap->flags |= MR_TOGGLE_RX;
3548 if (ap->rxconfig & ANEG_CFG_NP)
3549 ap->flags |= MR_NP_RX;
3550 ap->flags |= MR_PAGE_RX;
3551
3552 ap->state = ANEG_STATE_COMPLETE_ACK;
3553 ret = ANEG_TIMER_ENAB;
3554 break;
3555
3556 case ANEG_STATE_COMPLETE_ACK:
3557 if (ap->ability_match != 0 &&
3558 ap->rxconfig == 0) {
3559 ap->state = ANEG_STATE_AN_ENABLE;
3560 break;
3561 }
3562 delta = ap->cur_time - ap->link_time;
3563 if (delta > ANEG_STATE_SETTLE_TIME) {
3564 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3565 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566 } else {
3567 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3568 !(ap->flags & MR_NP_RX)) {
3569 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3570 } else {
3571 ret = ANEG_FAILED;
3572 }
3573 }
3574 }
3575 break;
3576
3577 case ANEG_STATE_IDLE_DETECT_INIT:
3578 ap->link_time = ap->cur_time;
3579 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3580 tw32_f(MAC_MODE, tp->mac_mode);
3581 udelay(40);
3582
3583 ap->state = ANEG_STATE_IDLE_DETECT;
3584 ret = ANEG_TIMER_ENAB;
3585 break;
3586
3587 case ANEG_STATE_IDLE_DETECT:
3588 if (ap->ability_match != 0 &&
3589 ap->rxconfig == 0) {
3590 ap->state = ANEG_STATE_AN_ENABLE;
3591 break;
3592 }
3593 delta = ap->cur_time - ap->link_time;
3594 if (delta > ANEG_STATE_SETTLE_TIME) {
3595 /* XXX another gem from the Broadcom driver :( */
3596 ap->state = ANEG_STATE_LINK_OK;
3597 }
3598 break;
3599
3600 case ANEG_STATE_LINK_OK:
3601 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3602 ret = ANEG_DONE;
3603 break;
3604
3605 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3606 /* ??? unimplemented */
3607 break;
3608
3609 case ANEG_STATE_NEXT_PAGE_WAIT:
3610 /* ??? unimplemented */
3611 break;
3612
3613 default:
3614 ret = ANEG_FAILED;
3615 break;
855e1111 3616 }
1da177e4
LT		 3617
3618 return ret;
3619}
3620
5be73b47 3621static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3622{
3623 int res = 0;
3624 struct tg3_fiber_aneginfo aninfo;
3625 int status = ANEG_FAILED;
3626 unsigned int tick;
3627 u32 tmp;
3628
3629 tw32_f(MAC_TX_AUTO_NEG, 0);
3630
3631 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3632 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3633 udelay(40);
3634
3635 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3636 udelay(40);
3637
3638 memset(&aninfo, 0, sizeof(aninfo));
3639 aninfo.flags |= MR_AN_ENABLE;
3640 aninfo.state = ANEG_STATE_UNKNOWN;
3641 aninfo.cur_time = 0;
3642 tick = 0;
3643 while (++tick < 195000) {
3644 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3645 if (status == ANEG_DONE || status == ANEG_FAILED)
3646 break;
3647
3648 udelay(1);
3649 }
3650
3651 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3652 tw32_f(MAC_MODE, tp->mac_mode);
3653 udelay(40);
3654
5be73b47
MC		 3655 *txflags = aninfo.txconfig;
3656 *rxflags = aninfo.flags;
1da177e4
LT		 3657
3658 if (status == ANEG_DONE &&
3659 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3660 MR_LP_ADV_FULL_DUPLEX)))
3661 res = 1;
3662
3663 return res;
3664}
3665
3666static void tg3_init_bcm8002(struct tg3 *tp)
3667{
3668 u32 mac_status = tr32(MAC_STATUS);
3669 int i;
3670
3671 /* Reset when initting first time or we have a link. */
3672 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3673 !(mac_status & MAC_STATUS_PCS_SYNCED))
3674 return;
3675
3676 /* Set PLL lock range. */
3677 tg3_writephy(tp, 0x16, 0x8007);
3678
3679 /* SW reset */
3680 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3681
3682 /* Wait for reset to complete. */
3683 /* XXX schedule_timeout() ... */
3684 for (i = 0; i < 500; i++)
3685 udelay(10);
3686
3687 /* Config mode; select PMA/Ch 1 regs. */
3688 tg3_writephy(tp, 0x10, 0x8411);
3689
3690 /* Enable auto-lock and comdet, select txclk for tx. */
3691 tg3_writephy(tp, 0x11, 0x0a10);
3692
3693 tg3_writephy(tp, 0x18, 0x00a0);
3694 tg3_writephy(tp, 0x16, 0x41ff);
3695
3696 /* Assert and deassert POR. */
3697 tg3_writephy(tp, 0x13, 0x0400);
3698 udelay(40);
3699 tg3_writephy(tp, 0x13, 0x0000);
3700
3701 tg3_writephy(tp, 0x11, 0x0a50);
3702 udelay(40);
3703 tg3_writephy(tp, 0x11, 0x0a10);
3704
3705 /* Wait for signal to stabilize */
3706 /* XXX schedule_timeout() ... */
3707 for (i = 0; i < 15000; i++)
3708 udelay(10);
3709
3710 /* Deselect the channel register so we can read the PHYID
3711 * later.
3712 */
3713 tg3_writephy(tp, 0x10, 0x8011);
3714}
3715
3716static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3717{
82cd3d11 3718 u16 flowctrl;
1da177e4
LT		 3719 u32 sg_dig_ctrl, sg_dig_status;
3720 u32 serdes_cfg, expected_sg_dig_ctrl;
3721 int workaround, port_a;
3722 int current_link_up;
3723
3724 serdes_cfg = 0;
3725 expected_sg_dig_ctrl = 0;
3726 workaround = 0;
3727 port_a = 1;
3728 current_link_up = 0;
3729
3730 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3731 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3732 workaround = 1;
3733 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3734 port_a = 0;
3735
3736 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3737 /* preserve bits 20-23 for voltage regulator */
3738 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3739 }
3740
3741 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3742
3743 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3744 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3745 if (workaround) {
3746 u32 val = serdes_cfg;
3747
3748 if (port_a)
3749 val |= 0xc010000;
3750 else
3751 val |= 0x4010000;
3752 tw32_f(MAC_SERDES_CFG, val);
3753 }
c98f6e3b
MC		 3754
3755 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3756 }
3757 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3758 tg3_setup_flow_control(tp, 0, 0);
3759 current_link_up = 1;
3760 }
3761 goto out;
3762 }
3763
3764 /* Want auto-negotiation. */
c98f6e3b 3765 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3766
82cd3d11
MC		 3767 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3768 if (flowctrl & ADVERTISE_1000XPAUSE)
3769 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3770 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3771 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3772
3773 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3774 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3775 tp->serdes_counter &&
3776 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3777 MAC_STATUS_RCVD_CFG)) ==
3778 MAC_STATUS_PCS_SYNCED)) {
3779 tp->serdes_counter--;
3780 current_link_up = 1;
3781 goto out;
3782 }
3783restart_autoneg:
1da177e4
LT		 3784 if (workaround)
3785 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3786 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3787 udelay(5);
3788 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3789
3d3ebe74
MC		 3790 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3791 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3792 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3793 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3794 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3795 mac_status = tr32(MAC_STATUS);
3796
c98f6e3b 3797 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3798 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3799 u32 local_adv = 0, remote_adv = 0;
3800
3801 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3802 local_adv |= ADVERTISE_1000XPAUSE;
3803 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3804 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3805
c98f6e3b 3806 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3807 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3808 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3809 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3810
3811 tg3_setup_flow_control(tp, local_adv, remote_adv);
3812 current_link_up = 1;
3d3ebe74
MC		 3813 tp->serdes_counter = 0;
3814 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3815 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3816 if (tp->serdes_counter)
3817 tp->serdes_counter--;
1da177e4
LT		 3818 else {
3819 if (workaround) {
3820 u32 val = serdes_cfg;
3821
3822 if (port_a)
3823 val |= 0xc010000;
3824 else
3825 val |= 0x4010000;
3826
3827 tw32_f(MAC_SERDES_CFG, val);
3828 }
3829
c98f6e3b 3830 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3831 udelay(40);
3832
3833 /* Link parallel detection - link is up */
3834 /* only if we have PCS_SYNC and not */
3835 /* receiving config code words */
3836 mac_status = tr32(MAC_STATUS);
3837 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3838 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3839 tg3_setup_flow_control(tp, 0, 0);
3840 current_link_up = 1;
3d3ebe74
MC		 3841 tp->tg3_flags2 |=
3842 TG3_FLG2_PARALLEL_DETECT;
3843 tp->serdes_counter =
3844 SERDES_PARALLEL_DET_TIMEOUT;
3845 } else
3846 goto restart_autoneg;
1da177e4
LT		 3847 }
3848 }
3d3ebe74
MC		 3849 } else {
3850 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3851 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3852 }
3853
3854out:
3855 return current_link_up;
3856}
3857
3858static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3859{
3860 int current_link_up = 0;
3861
5cf64b8a 3862 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3863 goto out;
1da177e4
LT		 3864
3865 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3866 u32 txflags, rxflags;
1da177e4 3867 int i;
6aa20a22 3868
5be73b47
MC		 3869 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3870 u32 local_adv = 0, remote_adv = 0;
1da177e4 3871
5be73b47
MC		 3872 if (txflags & ANEG_CFG_PS1)
3873 local_adv |= ADVERTISE_1000XPAUSE;
3874 if (txflags & ANEG_CFG_PS2)
3875 local_adv |= ADVERTISE_1000XPSE_ASYM;
3876
3877 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3878 remote_adv |= LPA_1000XPAUSE;
3879 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3880 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3881
3882 tg3_setup_flow_control(tp, local_adv, remote_adv);
3883
1da177e4
LT		 3884 current_link_up = 1;
3885 }
3886 for (i = 0; i < 30; i++) {
3887 udelay(20);
3888 tw32_f(MAC_STATUS,
3889 (MAC_STATUS_SYNC_CHANGED |
3890 MAC_STATUS_CFG_CHANGED));
3891 udelay(40);
3892 if ((tr32(MAC_STATUS) &
3893 (MAC_STATUS_SYNC_CHANGED |
3894 MAC_STATUS_CFG_CHANGED)) == 0)
3895 break;
3896 }
3897
3898 mac_status = tr32(MAC_STATUS);
3899 if (current_link_up == 0 &&
3900 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3901 !(mac_status & MAC_STATUS_RCVD_CFG))
3902 current_link_up = 1;
3903 } else {
5be73b47
MC		 3904 tg3_setup_flow_control(tp, 0, 0);
3905
1da177e4
LT		 3906 /* Forcing 1000FD link up. */
3907 current_link_up = 1;
1da177e4
LT		 3908
3909 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3910 udelay(40);
e8f3f6ca
MC		 3911
3912 tw32_f(MAC_MODE, tp->mac_mode);
3913 udelay(40);
1da177e4
LT		 3914 }
3915
3916out:
3917 return current_link_up;
3918}
3919
3920static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3921{
3922 u32 orig_pause_cfg;
3923 u16 orig_active_speed;
3924 u8 orig_active_duplex;
3925 u32 mac_status;
3926 int current_link_up;
3927 int i;
3928
8d018621 3929 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3930 orig_active_speed = tp->link_config.active_speed;
3931 orig_active_duplex = tp->link_config.active_duplex;
3932
3933 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3934 netif_carrier_ok(tp->dev) &&
3935 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3936 mac_status = tr32(MAC_STATUS);
3937 mac_status &= (MAC_STATUS_PCS_SYNCED |
3938 MAC_STATUS_SIGNAL_DET |
3939 MAC_STATUS_CFG_CHANGED |
3940 MAC_STATUS_RCVD_CFG);
3941 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3942 MAC_STATUS_SIGNAL_DET)) {
3943 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3944 MAC_STATUS_CFG_CHANGED));
3945 return 0;
3946 }
3947 }
3948
3949 tw32_f(MAC_TX_AUTO_NEG, 0);
3950
3951 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3952 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3953 tw32_f(MAC_MODE, tp->mac_mode);
3954 udelay(40);
3955
3956 if (tp->phy_id == PHY_ID_BCM8002)
3957 tg3_init_bcm8002(tp);
3958
3959 /* Enable link change event even when serdes polling. */
3960 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3961 udelay(40);
3962
3963 current_link_up = 0;
3964 mac_status = tr32(MAC_STATUS);
3965
3966 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3967 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3968 else
3969 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3970
898a56f8 3971 tp->napi[0].hw_status->status =
1da177e4 3972 (SD_STATUS_UPDATED |
898a56f8 3973 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3974
3975 for (i = 0; i < 100; i++) {
3976 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3977 MAC_STATUS_CFG_CHANGED));
3978 udelay(5);
3979 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3980 MAC_STATUS_CFG_CHANGED |
3981 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3982 break;
3983 }
3984
3985 mac_status = tr32(MAC_STATUS);
3986 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3987 current_link_up = 0;
3d3ebe74
MC		 3988 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3989 tp->serdes_counter == 0) {
1da177e4
LT		 3990 tw32_f(MAC_MODE, (tp->mac_mode |
3991 MAC_MODE_SEND_CONFIGS));
3992 udelay(1);
3993 tw32_f(MAC_MODE, tp->mac_mode);
3994 }
3995 }
3996
3997 if (current_link_up == 1) {
3998 tp->link_config.active_speed = SPEED_1000;
3999 tp->link_config.active_duplex = DUPLEX_FULL;
4000 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4001 LED_CTRL_LNKLED_OVERRIDE |
4002 LED_CTRL_1000MBPS_ON));
4003 } else {
4004 tp->link_config.active_speed = SPEED_INVALID;
4005 tp->link_config.active_duplex = DUPLEX_INVALID;
4006 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4007 LED_CTRL_LNKLED_OVERRIDE |
4008 LED_CTRL_TRAFFIC_OVERRIDE));
4009 }
4010
4011 if (current_link_up != netif_carrier_ok(tp->dev)) {
4012 if (current_link_up)
4013 netif_carrier_on(tp->dev);
4014 else
4015 netif_carrier_off(tp->dev);
4016 tg3_link_report(tp);
4017 } else {
8d018621 4018 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4019 if (orig_pause_cfg != now_pause_cfg ||
4020 orig_active_speed != tp->link_config.active_speed ||
4021 orig_active_duplex != tp->link_config.active_duplex)
4022 tg3_link_report(tp);
4023 }
4024
4025 return 0;
4026}
4027
747e8f8b
MC		 4028static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4029{
4030 int current_link_up, err = 0;
4031 u32 bmsr, bmcr;
4032 u16 current_speed;
4033 u8 current_duplex;
ef167e27 4034 u32 local_adv, remote_adv;
747e8f8b
MC		 4035
4036 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4037 tw32_f(MAC_MODE, tp->mac_mode);
4038 udelay(40);
4039
4040 tw32(MAC_EVENT, 0);
4041
4042 tw32_f(MAC_STATUS,
4043 (MAC_STATUS_SYNC_CHANGED |
4044 MAC_STATUS_CFG_CHANGED |
4045 MAC_STATUS_MI_COMPLETION |
4046 MAC_STATUS_LNKSTATE_CHANGED));
4047 udelay(40);
4048
4049 if (force_reset)
4050 tg3_phy_reset(tp);
4051
4052 current_link_up = 0;
4053 current_speed = SPEED_INVALID;
4054 current_duplex = DUPLEX_INVALID;
4055
4056 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4057 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4059 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4060 bmsr |= BMSR_LSTATUS;
4061 else
4062 bmsr &= ~BMSR_LSTATUS;
4063 }
747e8f8b
MC		 4064
4065 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4066
4067 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4068 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4069 /* do nothing, just check for link up at the end */
4070 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4071 u32 adv, new_adv;
4072
4073 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4074 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4075 ADVERTISE_1000XPAUSE |
4076 ADVERTISE_1000XPSE_ASYM |
4077 ADVERTISE_SLCT);
4078
ba4d07a8 4079 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4080
4081 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4082 new_adv |= ADVERTISE_1000XHALF;
4083 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4084 new_adv |= ADVERTISE_1000XFULL;
4085
4086 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4087 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4088 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4089 tg3_writephy(tp, MII_BMCR, bmcr);
4090
4091 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4092 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4093 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4094
4095 return err;
4096 }
4097 } else {
4098 u32 new_bmcr;
4099
4100 bmcr &= ~BMCR_SPEED1000;
4101 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4102
4103 if (tp->link_config.duplex == DUPLEX_FULL)
4104 new_bmcr |= BMCR_FULLDPLX;
4105
4106 if (new_bmcr != bmcr) {
4107 /* BMCR_SPEED1000 is a reserved bit that needs
4108 * to be set on write.
4109 */
4110 new_bmcr |= BMCR_SPEED1000;
4111
4112 /* Force a linkdown */
4113 if (netif_carrier_ok(tp->dev)) {
4114 u32 adv;
4115
4116 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4117 adv &= ~(ADVERTISE_1000XFULL |
4118 ADVERTISE_1000XHALF |
4119 ADVERTISE_SLCT);
4120 tg3_writephy(tp, MII_ADVERTISE, adv);
4121 tg3_writephy(tp, MII_BMCR, bmcr |
4122 BMCR_ANRESTART |
4123 BMCR_ANENABLE);
4124 udelay(10);
4125 netif_carrier_off(tp->dev);
4126 }
4127 tg3_writephy(tp, MII_BMCR, new_bmcr);
4128 bmcr = new_bmcr;
4129 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4130 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4131 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4132 ASIC_REV_5714) {
4133 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4134 bmsr |= BMSR_LSTATUS;
4135 else
4136 bmsr &= ~BMSR_LSTATUS;
4137 }
747e8f8b
MC		 4138 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4139 }
4140 }
4141
4142 if (bmsr & BMSR_LSTATUS) {
4143 current_speed = SPEED_1000;
4144 current_link_up = 1;
4145 if (bmcr & BMCR_FULLDPLX)
4146 current_duplex = DUPLEX_FULL;
4147 else
4148 current_duplex = DUPLEX_HALF;
4149
ef167e27
MC		 4150 local_adv = 0;
4151 remote_adv = 0;
4152
747e8f8b 4153 if (bmcr & BMCR_ANENABLE) {
ef167e27 4154 u32 common;
747e8f8b
MC		 4155
4156 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4157 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4158 common = local_adv & remote_adv;
4159 if (common & (ADVERTISE_1000XHALF |
4160 ADVERTISE_1000XFULL)) {
4161 if (common & ADVERTISE_1000XFULL)
4162 current_duplex = DUPLEX_FULL;
4163 else
4164 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4165 }
4166 else
4167 current_link_up = 0;
4168 }
4169 }
4170
ef167e27
MC		 4171 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4172 tg3_setup_flow_control(tp, local_adv, remote_adv);
4173
747e8f8b
MC		 4174 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4175 if (tp->link_config.active_duplex == DUPLEX_HALF)
4176 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4177
4178 tw32_f(MAC_MODE, tp->mac_mode);
4179 udelay(40);
4180
4181 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4182
4183 tp->link_config.active_speed = current_speed;
4184 tp->link_config.active_duplex = current_duplex;
4185
4186 if (current_link_up != netif_carrier_ok(tp->dev)) {
4187 if (current_link_up)
4188 netif_carrier_on(tp->dev);
4189 else {
4190 netif_carrier_off(tp->dev);
4191 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4192 }
4193 tg3_link_report(tp);
4194 }
4195 return err;
4196}
4197
4198static void tg3_serdes_parallel_detect(struct tg3 *tp)
4199{
3d3ebe74 4200 if (tp->serdes_counter) {
747e8f8b 4201 /* Give autoneg time to complete. */
3d3ebe74 4202 tp->serdes_counter--;
747e8f8b
MC		 4203 return;
4204 }
4205 if (!netif_carrier_ok(tp->dev) &&
4206 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4207 u32 bmcr;
4208
4209 tg3_readphy(tp, MII_BMCR, &bmcr);
4210 if (bmcr & BMCR_ANENABLE) {
4211 u32 phy1, phy2;
4212
4213 /* Select shadow register 0x1f */
4214 tg3_writephy(tp, 0x1c, 0x7c00);
4215 tg3_readphy(tp, 0x1c, &phy1);
4216
4217 /* Select expansion interrupt status register */
4218 tg3_writephy(tp, 0x17, 0x0f01);
4219 tg3_readphy(tp, 0x15, &phy2);
4220 tg3_readphy(tp, 0x15, &phy2);
4221
4222 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4223 /* We have signal detect and not receiving
4224 * config code words, link is up by parallel
4225 * detection.
4226 */
4227
4228 bmcr &= ~BMCR_ANENABLE;
4229 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4230 tg3_writephy(tp, MII_BMCR, bmcr);
4231 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4232 }
4233 }
4234 }
4235 else if (netif_carrier_ok(tp->dev) &&
4236 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4237 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4238 u32 phy2;
4239
4240 /* Select expansion interrupt status register */
4241 tg3_writephy(tp, 0x17, 0x0f01);
4242 tg3_readphy(tp, 0x15, &phy2);
4243 if (phy2 & 0x20) {
4244 u32 bmcr;
4245
4246 /* Config code words received, turn on autoneg. */
4247 tg3_readphy(tp, MII_BMCR, &bmcr);
4248 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4249
4250 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4251
4252 }
4253 }
4254}
4255
1da177e4
LT		 4256static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4257{
4258 int err;
4259
4260 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4261 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4262 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4263 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4264 } else {
4265 err = tg3_setup_copper_phy(tp, force_reset);
4266 }
4267
bcb37f6c 4268 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4269 u32 val, scale;
4270
4271 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4272 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4273 scale = 65;
4274 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4275 scale = 6;
4276 else
4277 scale = 12;
4278
4279 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4280 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4281 tw32(GRC_MISC_CFG, val);
4282 }
4283
1da177e4
LT		 4284 if (tp->link_config.active_speed == SPEED_1000 &&
4285 tp->link_config.active_duplex == DUPLEX_HALF)
4286 tw32(MAC_TX_LENGTHS,
4287 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4288 (6 << TX_LENGTHS_IPG_SHIFT) |
4289 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4290 else
4291 tw32(MAC_TX_LENGTHS,
4292 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4293 (6 << TX_LENGTHS_IPG_SHIFT) |
4294 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4295
4296 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4297 if (netif_carrier_ok(tp->dev)) {
4298 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4299 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4300 } else {
4301 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4302 }
4303 }
4304
8ed5d97e
MC		 4305 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4306 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4307 if (!netif_carrier_ok(tp->dev))
4308 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4309 tp->pwrmgmt_thresh;
4310 else
4311 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4312 tw32(PCIE_PWR_MGMT_THRESH, val);
4313 }
4314
1da177e4
LT		 4315 return err;
4316}
4317
df3e6548
MC		 4318/* This is called whenever we suspect that the system chipset is re-
4319 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4320 * is bogus tx completions. We try to recover by setting the
4321 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4322 * in the workqueue.
4323 */
4324static void tg3_tx_recover(struct tg3 *tp)
4325{
4326 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4327 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4328
4329 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4330 "mapped I/O cycles to the network device, attempting to "
4331 "recover. Please report the problem to the driver maintainer "
4332 "and include system chipset information.\n", tp->dev->name);
4333
4334 spin_lock(&tp->lock);
df3e6548 4335 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4336 spin_unlock(&tp->lock);
4337}
4338
f3f3f27e 4339static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4340{
4341 smp_mb();
f3f3f27e
MC		 4342 return tnapi->tx_pending -
4343 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4344}
4345
1da177e4
LT		 4346/* Tigon3 never reports partial packet sends. So we do not
4347 * need special logic to handle SKBs that have not had all
4348 * of their frags sent yet, like SunGEM does.
4349 */
17375d25 4350static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4351{
17375d25 4352 struct tg3 *tp = tnapi->tp;
898a56f8 4353 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4354 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4355 struct netdev_queue *txq;
4356 int index = tnapi - tp->napi;
4357
19cfaecc 4358 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4359 index--;
4360
4361 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4362
4363 while (sw_idx != hw_idx) {
f4188d8a 4364 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4365 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4366 int i, tx_bug = 0;
4367
4368 if (unlikely(skb == NULL)) {
4369 tg3_tx_recover(tp);
4370 return;
4371 }
1da177e4 4372
f4188d8a
AD		 4373 pci_unmap_single(tp->pdev,
4374 pci_unmap_addr(ri, mapping),
4375 skb_headlen(skb),
4376 PCI_DMA_TODEVICE);
1da177e4
LT		 4377
4378 ri->skb = NULL;
4379
4380 sw_idx = NEXT_TX(sw_idx);
4381
4382 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4383 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4384 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4385 tx_bug = 1;
f4188d8a
AD		 4386
4387 pci_unmap_page(tp->pdev,
4388 pci_unmap_addr(ri, mapping),
4389 skb_shinfo(skb)->frags[i].size,
4390 PCI_DMA_TODEVICE);
1da177e4
LT		 4391 sw_idx = NEXT_TX(sw_idx);
4392 }
4393
f47c11ee 4394 dev_kfree_skb(skb);
df3e6548
MC		 4395
4396 if (unlikely(tx_bug)) {
4397 tg3_tx_recover(tp);
4398 return;
4399 }
1da177e4
LT		 4400 }
4401
f3f3f27e 4402 tnapi->tx_cons = sw_idx;
1da177e4 4403
1b2a7205
MC		 4404 /* Need to make the tx_cons update visible to tg3_start_xmit()
4405 * before checking for netif_queue_stopped(). Without the
4406 * memory barrier, there is a small possibility that tg3_start_xmit()
4407 * will miss it and cause the queue to be stopped forever.
4408 */
4409 smp_mb();
4410
fe5f5787 4411 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4412 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4413 __netif_tx_lock(txq, smp_processor_id());
4414 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4415 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4416 netif_tx_wake_queue(txq);
4417 __netif_tx_unlock(txq);
51b91468 4418 }
1da177e4
LT		 4419}
4420
2b2cdb65
MC		 4421static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4422{
4423 if (!ri->skb)
4424 return;
4425
4426 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4427 map_sz, PCI_DMA_FROMDEVICE);
4428 dev_kfree_skb_any(ri->skb);
4429 ri->skb = NULL;
4430}
4431
1da177e4
LT		 4432/* Returns size of skb allocated or < 0 on error.
4433 *
4434 * We only need to fill in the address because the other members
4435 * of the RX descriptor are invariant, see tg3_init_rings.
4436 *
4437 * Note the purposeful assymetry of cpu vs. chip accesses. For
4438 * posting buffers we only dirty the first cache line of the RX
4439 * descriptor (containing the address). Whereas for the RX status
4440 * buffers the cpu only reads the last cacheline of the RX descriptor
4441 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4442 */
86b21e59 4443static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4444 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4445{
4446 struct tg3_rx_buffer_desc *desc;
4447 struct ring_info *map, *src_map;
4448 struct sk_buff *skb;
4449 dma_addr_t mapping;
4450 int skb_size, dest_idx;
4451
4452 src_map = NULL;
4453 switch (opaque_key) {
4454 case RXD_OPAQUE_RING_STD:
4455 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4456 desc = &tpr->rx_std[dest_idx];
4457 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4458 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4459 break;
4460
4461 case RXD_OPAQUE_RING_JUMBO:
4462 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4463 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4464 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4465 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4466 break;
4467
4468 default:
4469 return -EINVAL;
855e1111 4470 }
1da177e4
LT		 4471
4472 /* Do not overwrite any of the map or rp information
4473 * until we are sure we can commit to a new buffer.
4474 *
4475 * Callers depend upon this behavior and assume that
4476 * we leave everything unchanged if we fail.
4477 */
287be12e 4478 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4479 if (skb == NULL)
4480 return -ENOMEM;
4481
1da177e4
LT		 4482 skb_reserve(skb, tp->rx_offset);
4483
287be12e 4484 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4485 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4486 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4487 dev_kfree_skb(skb);
4488 return -EIO;
4489 }
1da177e4
LT		 4490
4491 map->skb = skb;
4492 pci_unmap_addr_set(map, mapping, mapping);
4493
1da177e4
LT		 4494 desc->addr_hi = ((u64)mapping >> 32);
4495 desc->addr_lo = ((u64)mapping & 0xffffffff);
4496
4497 return skb_size;
4498}
4499
4500/* We only need to move over in the address because the other
4501 * members of the RX descriptor are invariant. See notes above
4502 * tg3_alloc_rx_skb for full details.
4503 */
a3896167
MC		 4504static void tg3_recycle_rx(struct tg3_napi *tnapi,
4505 struct tg3_rx_prodring_set *dpr,
4506 u32 opaque_key, int src_idx,
4507 u32 dest_idx_unmasked)
1da177e4 4508{
17375d25 4509 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4510 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4511 struct ring_info *src_map, *dest_map;
4512 int dest_idx;
a3896167 4513 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4514
4515 switch (opaque_key) {
4516 case RXD_OPAQUE_RING_STD:
4517 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4518 dest_desc = &dpr->rx_std[dest_idx];
4519 dest_map = &dpr->rx_std_buffers[dest_idx];
4520 src_desc = &spr->rx_std[src_idx];
4521 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4522 break;
4523
4524 case RXD_OPAQUE_RING_JUMBO:
4525 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4526 dest_desc = &dpr->rx_jmb[dest_idx].std;
4527 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4528 src_desc = &spr->rx_jmb[src_idx].std;
4529 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4530 break;
4531
4532 default:
4533 return;
855e1111 4534 }
1da177e4
LT		 4535
4536 dest_map->skb = src_map->skb;
4537 pci_unmap_addr_set(dest_map, mapping,
4538 pci_unmap_addr(src_map, mapping));
4539 dest_desc->addr_hi = src_desc->addr_hi;
4540 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4541 src_map->skb = NULL;
4542}
4543
1da177e4
LT		 4544/* The RX ring scheme is composed of multiple rings which post fresh
4545 * buffers to the chip, and one special ring the chip uses to report
4546 * status back to the host.
4547 *
4548 * The special ring reports the status of received packets to the
4549 * host. The chip does not write into the original descriptor the
4550 * RX buffer was obtained from. The chip simply takes the original
4551 * descriptor as provided by the host, updates the status and length
4552 * field, then writes this into the next status ring entry.
4553 *
4554 * Each ring the host uses to post buffers to the chip is described
4555 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4556 * it is first placed into the on-chip ram. When the packet's length
4557 * is known, it walks down the TG3_BDINFO entries to select the ring.
4558 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4559 * which is within the range of the new packet's length is chosen.
4560 *
4561 * The "separate ring for rx status" scheme may sound queer, but it makes
4562 * sense from a cache coherency perspective. If only the host writes
4563 * to the buffer post rings, and only the chip writes to the rx status
4564 * rings, then cache lines never move beyond shared-modified state.
4565 * If both the host and chip were to write into the same ring, cache line
4566 * eviction could occur since both entities want it in an exclusive state.
4567 */
17375d25 4568static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4569{
17375d25 4570 struct tg3 *tp = tnapi->tp;
f92905de 4571 u32 work_mask, rx_std_posted = 0;
4361935a 4572 u32 std_prod_idx, jmb_prod_idx;
72334482 4573 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4574 u16 hw_idx;
1da177e4 4575 int received;
b196c7e4 4576 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4577
8d9d7cfc 4578 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4579 /*
4580 * We need to order the read of hw_idx and the read of
4581 * the opaque cookie.
4582 */
4583 rmb();
1da177e4
LT		 4584 work_mask = 0;
4585 received = 0;
4361935a
MC		 4586 std_prod_idx = tpr->rx_std_prod_idx;
4587 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4588 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4589 struct ring_info *ri;
72334482 4590 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4591 unsigned int len;
4592 struct sk_buff *skb;
4593 dma_addr_t dma_addr;
4594 u32 opaque_key, desc_idx, *post_ptr;
4595
4596 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4597 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4598 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4599 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4600 dma_addr = pci_unmap_addr(ri, mapping);
4601 skb = ri->skb;
4361935a 4602 post_ptr = &std_prod_idx;
f92905de 4603 rx_std_posted++;
1da177e4 4604 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4605 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4606 dma_addr = pci_unmap_addr(ri, mapping);
4607 skb = ri->skb;
4361935a 4608 post_ptr = &jmb_prod_idx;
21f581a5 4609 } else
1da177e4 4610 goto next_pkt_nopost;
1da177e4
LT		 4611
4612 work_mask |= opaque_key;
4613
4614 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4615 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4616 drop_it:
a3896167 4617 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4618 desc_idx, *post_ptr);
4619 drop_it_no_recycle:
4620 /* Other statistics kept track of by card. */
4621 tp->net_stats.rx_dropped++;
4622 goto next_pkt;
4623 }
4624
ad829268
MC		 4625 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4626 ETH_FCS_LEN;
1da177e4 4627
8e95a202
JP		 4628 if (len > RX_COPY_THRESHOLD &&
4629 tp->rx_offset == NET_IP_ALIGN) {
4630 /* rx_offset will likely not equal NET_IP_ALIGN
4631 * if this is a 5701 card running in PCI-X mode
4632 * [see tg3_get_invariants()]
4633 */
1da177e4
LT		 4634 int skb_size;
4635
86b21e59 4636 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4637 *post_ptr);
1da177e4
LT		 4638 if (skb_size < 0)
4639 goto drop_it;
4640
afc081f8
MC		 4641 ri->skb = NULL;
4642
287be12e 4643 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4644 PCI_DMA_FROMDEVICE);
4645
4646 skb_put(skb, len);
4647 } else {
4648 struct sk_buff *copy_skb;
4649
a3896167 4650 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4651 desc_idx, *post_ptr);
4652
ad829268
MC		 4653 copy_skb = netdev_alloc_skb(tp->dev,
4654 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4655 if (copy_skb == NULL)
4656 goto drop_it_no_recycle;
4657
ad829268 4658 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4659 skb_put(copy_skb, len);
4660 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4661 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4662 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4663
4664 /* We'll reuse the original ring buffer. */
4665 skb = copy_skb;
4666 }
4667
4668 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4669 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4670 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4671 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4672 skb->ip_summed = CHECKSUM_UNNECESSARY;
4673 else
4674 skb->ip_summed = CHECKSUM_NONE;
4675
4676 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4677
4678 if (len > (tp->dev->mtu + ETH_HLEN) &&
4679 skb->protocol != htons(ETH_P_8021Q)) {
4680 dev_kfree_skb(skb);
4681 goto next_pkt;
4682 }
4683
1da177e4
LT		 4684#if TG3_VLAN_TAG_USED
4685 if (tp->vlgrp != NULL &&
4686 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4687 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4688 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4689 } else
4690#endif
17375d25 4691 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4692
1da177e4
LT		 4693 received++;
4694 budget--;
4695
4696next_pkt:
4697 (*post_ptr)++;
f92905de
MC		 4698
4699 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4700 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4701 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4702 tpr->rx_std_prod_idx);
f92905de
MC		 4703 work_mask &= ~RXD_OPAQUE_RING_STD;
4704 rx_std_posted = 0;
4705 }
1da177e4 4706next_pkt_nopost:
483ba50b 4707 sw_idx++;
6b31a515 4708 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4709
4710 /* Refresh hw_idx to see if there is new work */
4711 if (sw_idx == hw_idx) {
8d9d7cfc 4712 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4713 rmb();
4714 }
1da177e4
LT		 4715 }
4716
4717 /* ACK the status ring. */
72334482
MC		 4718 tnapi->rx_rcb_ptr = sw_idx;
4719 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4720
4721 /* Refill RX ring(s). */
b196c7e4
MC		 4722 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4723 if (work_mask & RXD_OPAQUE_RING_STD) {
4724 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4725 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4726 tpr->rx_std_prod_idx);
4727 }
4728 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4729 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4730 TG3_RX_JUMBO_RING_SIZE;
4731 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4732 tpr->rx_jmb_prod_idx);
4733 }
4734 mmiowb();
4735 } else if (work_mask) {
4736 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4737 * updated before the producer indices can be updated.
4738 */
4739 smp_wmb();
4740
4361935a 4741 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4742 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4
MC		 4743
4744 napi_schedule(&tp->napi[1].napi);
1da177e4 4745 }
1da177e4
LT		 4746
4747 return received;
4748}
4749
35f2d7d0 4750static void tg3_poll_link(struct tg3 *tp)
1da177e4 4751{
1da177e4
LT		 4752 /* handle link change and other phy events */
4753 if (!(tp->tg3_flags &
4754 (TG3_FLAG_USE_LINKCHG_REG |
4755 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4756 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4757
1da177e4
LT		 4758 if (sblk->status & SD_STATUS_LINK_CHG) {
4759 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4760 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4761 spin_lock(&tp->lock);
dd477003
MC		 4762 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4763 tw32_f(MAC_STATUS,
4764 (MAC_STATUS_SYNC_CHANGED |
4765 MAC_STATUS_CFG_CHANGED |
4766 MAC_STATUS_MI_COMPLETION |
4767 MAC_STATUS_LNKSTATE_CHANGED));
4768 udelay(40);
4769 } else
4770 tg3_setup_phy(tp, 0);
f47c11ee 4771 spin_unlock(&tp->lock);
1da177e4
LT		 4772 }
4773 }
35f2d7d0
MC		 4774}
4775
b196c7e4
MC		 4776static void tg3_rx_prodring_xfer(struct tg3 *tp,
4777 struct tg3_rx_prodring_set *dpr,
4778 struct tg3_rx_prodring_set *spr)
4779{
4780 u32 si, di, cpycnt, src_prod_idx;
4781 int i;
4782
4783 while (1) {
4784 src_prod_idx = spr->rx_std_prod_idx;
4785
4786 /* Make sure updates to the rx_std_buffers[] entries and the
4787 * standard producer index are seen in the correct order.
4788 */
4789 smp_rmb();
4790
4791 if (spr->rx_std_cons_idx == src_prod_idx)
4792 break;
4793
4794 if (spr->rx_std_cons_idx < src_prod_idx)
4795 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4796 else
4797 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4798
4799 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4800
4801 si = spr->rx_std_cons_idx;
4802 di = dpr->rx_std_prod_idx;
4803
4804 memcpy(&dpr->rx_std_buffers[di],
4805 &spr->rx_std_buffers[si],
4806 cpycnt * sizeof(struct ring_info));
4807
4808 for (i = 0; i < cpycnt; i++, di++, si++) {
4809 struct tg3_rx_buffer_desc *sbd, *dbd;
4810 sbd = &spr->rx_std[si];
4811 dbd = &dpr->rx_std[di];
4812 dbd->addr_hi = sbd->addr_hi;
4813 dbd->addr_lo = sbd->addr_lo;
4814 }
4815
4816 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4817 TG3_RX_RING_SIZE;
4818 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4819 TG3_RX_RING_SIZE;
4820 }
4821
4822 while (1) {
4823 src_prod_idx = spr->rx_jmb_prod_idx;
4824
4825 /* Make sure updates to the rx_jmb_buffers[] entries and
4826 * the jumbo producer index are seen in the correct order.
4827 */
4828 smp_rmb();
4829
4830 if (spr->rx_jmb_cons_idx == src_prod_idx)
4831 break;
4832
4833 if (spr->rx_jmb_cons_idx < src_prod_idx)
4834 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4835 else
4836 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4837
4838 cpycnt = min(cpycnt,
4839 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4840
4841 si = spr->rx_jmb_cons_idx;
4842 di = dpr->rx_jmb_prod_idx;
4843
4844 memcpy(&dpr->rx_jmb_buffers[di],
4845 &spr->rx_jmb_buffers[si],
4846 cpycnt * sizeof(struct ring_info));
4847
4848 for (i = 0; i < cpycnt; i++, di++, si++) {
4849 struct tg3_rx_buffer_desc *sbd, *dbd;
4850 sbd = &spr->rx_jmb[si].std;
4851 dbd = &dpr->rx_jmb[di].std;
4852 dbd->addr_hi = sbd->addr_hi;
4853 dbd->addr_lo = sbd->addr_lo;
4854 }
4855
4856 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4857 TG3_RX_JUMBO_RING_SIZE;
4858 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4859 TG3_RX_JUMBO_RING_SIZE;
4860 }
4861}
4862
35f2d7d0
MC		 4863static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4864{
4865 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4866
4867 /* run TX completion thread */
f3f3f27e 4868 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4869 tg3_tx(tnapi);
6f535763 4870 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4871 return work_done;
1da177e4
LT		 4872 }
4873
1da177e4
LT		 4874 /* run RX thread, within the bounds set by NAPI.
4875 * All RX "locking" is done by ensuring outside
bea3348e 4876 * code synchronizes with tg3->napi.poll()
1da177e4 4877 */
8d9d7cfc 4878 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4879 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4880
b196c7e4
MC		 4881 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4882 int i;
4883 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4884 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4885
4886 for (i = 2; i < tp->irq_cnt; i++)
4887 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4888 tp->napi[i].prodring);
4889
4890 wmb();
4891
4892 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4893 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4894 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4895 }
4896
4897 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4898 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4899 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4900 }
4901
4902 mmiowb();
4903 }
4904
6f535763
DM		 4905 return work_done;
4906}
4907
35f2d7d0
MC		 4908static int tg3_poll_msix(struct napi_struct *napi, int budget)
4909{
4910 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4911 struct tg3 *tp = tnapi->tp;
4912 int work_done = 0;
4913 struct tg3_hw_status *sblk = tnapi->hw_status;
4914
4915 while (1) {
4916 work_done = tg3_poll_work(tnapi, work_done, budget);
4917
4918 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4919 goto tx_recovery;
4920
4921 if (unlikely(work_done >= budget))
4922 break;
4923
4924 /* tp->last_tag is used in tg3_restart_ints() below
4925 * to tell the hw how much work has been processed,
4926 * so we must read it before checking for more work.
4927 */
4928 tnapi->last_tag = sblk->status_tag;
4929 tnapi->last_irq_tag = tnapi->last_tag;
4930 rmb();
4931
4932 /* check for RX/TX work to do */
4933 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4934 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4935 napi_complete(napi);
4936 /* Reenable interrupts. */
4937 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4938 mmiowb();
4939 break;
4940 }
4941 }
4942
4943 return work_done;
4944
4945tx_recovery:
4946 /* work_done is guaranteed to be less than budget. */
4947 napi_complete(napi);
4948 schedule_work(&tp->reset_task);
4949 return work_done;
4950}
4951
6f535763
DM		 4952static int tg3_poll(struct napi_struct *napi, int budget)
4953{
8ef0442f
MC		 4954 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4955 struct tg3 *tp = tnapi->tp;
6f535763 4956 int work_done = 0;
898a56f8 4957 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4958
4959 while (1) {
35f2d7d0
MC		 4960 tg3_poll_link(tp);
4961
17375d25 4962 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4963
4964 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4965 goto tx_recovery;
4966
4967 if (unlikely(work_done >= budget))
4968 break;
4969
4fd7ab59 4970 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4971 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4972 * to tell the hw how much work has been processed,
4973 * so we must read it before checking for more work.
4974 */
898a56f8
MC		 4975 tnapi->last_tag = sblk->status_tag;
4976 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4977 rmb();
4978 } else
4979 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4980
17375d25 4981 if (likely(!tg3_has_work(tnapi))) {
288379f0 4982 napi_complete(napi);
17375d25 4983 tg3_int_reenable(tnapi);
6f535763
DM		 4984 break;
4985 }
1da177e4
LT		 4986 }
4987
bea3348e 4988 return work_done;
6f535763
DM		 4989
4990tx_recovery:
4fd7ab59 4991 /* work_done is guaranteed to be less than budget. */
288379f0 4992 napi_complete(napi);
6f535763 4993 schedule_work(&tp->reset_task);
4fd7ab59 4994 return work_done;
1da177e4
LT		 4995}
4996
f47c11ee
DM		 4997static void tg3_irq_quiesce(struct tg3 *tp)
4998{
4f125f42
MC		 4999 int i;
5000
f47c11ee
DM		 5001 BUG_ON(tp->irq_sync);
5002
5003 tp->irq_sync = 1;
5004 smp_mb();
5005
4f125f42
MC		 5006 for (i = 0; i < tp->irq_cnt; i++)
5007 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5008}
5009
5010static inline int tg3_irq_sync(struct tg3 *tp)
5011{
5012 return tp->irq_sync;
5013}
5014
5015/* Fully shutdown all tg3 driver activity elsewhere in the system.
5016 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5017 * with as well. Most of the time, this is not necessary except when
5018 * shutting down the device.
5019 */
5020static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5021{
46966545 5022 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5023 if (irq_sync)
5024 tg3_irq_quiesce(tp);
f47c11ee
DM		 5025}
5026
5027static inline void tg3_full_unlock(struct tg3 *tp)
5028{
f47c11ee
DM		 5029 spin_unlock_bh(&tp->lock);
5030}
5031
fcfa0a32
MC		 5032/* One-shot MSI handler - Chip automatically disables interrupt
5033 * after sending MSI so driver doesn't have to do it.
5034 */
7d12e780 5035static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5036{
09943a18
MC		 5037 struct tg3_napi *tnapi = dev_id;
5038 struct tg3 *tp = tnapi->tp;
fcfa0a32 5039
898a56f8 5040 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5041 if (tnapi->rx_rcb)
5042 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5043
5044 if (likely(!tg3_irq_sync(tp)))
09943a18 5045 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5046
5047 return IRQ_HANDLED;
5048}
5049
88b06bc2
MC		 5050/* MSI ISR - No need to check for interrupt sharing and no need to
5051 * flush status block and interrupt mailbox. PCI ordering rules
5052 * guarantee that MSI will arrive after the status block.
5053 */
7d12e780 5054static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5055{
09943a18
MC		 5056 struct tg3_napi *tnapi = dev_id;
5057 struct tg3 *tp = tnapi->tp;
88b06bc2 5058
898a56f8 5059 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5060 if (tnapi->rx_rcb)
5061 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5062 /*
fac9b83e 5063 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5064 * chip-internal interrupt pending events.
fac9b83e 5065 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5066 * NIC to stop sending us irqs, engaging "in-intr-handler"
5067 * event coalescing.
5068 */
5069 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5070 if (likely(!tg3_irq_sync(tp)))
09943a18 5071 napi_schedule(&tnapi->napi);
61487480 5072
88b06bc2
MC		 5073 return IRQ_RETVAL(1);
5074}
5075
7d12e780 5076static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5077{
09943a18
MC		 5078 struct tg3_napi *tnapi = dev_id;
5079 struct tg3 *tp = tnapi->tp;
898a56f8 5080 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5081 unsigned int handled = 1;
5082
1da177e4
LT		 5083 /* In INTx mode, it is possible for the interrupt to arrive at
5084 * the CPU before the status block posted prior to the interrupt.
5085 * Reading the PCI State register will confirm whether the
5086 * interrupt is ours and will flush the status block.
5087 */
d18edcb2
MC		 5088 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5089 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5090 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5091 handled = 0;
f47c11ee 5092 goto out;
fac9b83e 5093 }
d18edcb2
MC		 5094 }
5095
5096 /*
5097 * Writing any value to intr-mbox-0 clears PCI INTA# and
5098 * chip-internal interrupt pending events.
5099 * Writing non-zero to intr-mbox-0 additional tells the
5100 * NIC to stop sending us irqs, engaging "in-intr-handler"
5101 * event coalescing.
c04cb347
MC		 5102 *
5103 * Flush the mailbox to de-assert the IRQ immediately to prevent
5104 * spurious interrupts. The flush impacts performance but
5105 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5106 */
c04cb347 5107 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5108 if (tg3_irq_sync(tp))
5109 goto out;
5110 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5111 if (likely(tg3_has_work(tnapi))) {
72334482 5112 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5113 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5114 } else {
5115 /* No work, shared interrupt perhaps? re-enable
5116 * interrupts, and flush that PCI write
5117 */
5118 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5119 0x00000000);
fac9b83e 5120 }
f47c11ee 5121out:
fac9b83e
DM		 5122 return IRQ_RETVAL(handled);
5123}
5124
7d12e780 5125static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5126{
09943a18
MC		 5127 struct tg3_napi *tnapi = dev_id;
5128 struct tg3 *tp = tnapi->tp;
898a56f8 5129 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5130 unsigned int handled = 1;
5131
fac9b83e
DM		 5132 /* In INTx mode, it is possible for the interrupt to arrive at
5133 * the CPU before the status block posted prior to the interrupt.
5134 * Reading the PCI State register will confirm whether the
5135 * interrupt is ours and will flush the status block.
5136 */
898a56f8 5137 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5138 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5139 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5140 handled = 0;
f47c11ee 5141 goto out;
1da177e4 5142 }
d18edcb2
MC		 5143 }
5144
5145 /*
5146 * writing any value to intr-mbox-0 clears PCI INTA# and
5147 * chip-internal interrupt pending events.
5148 * writing non-zero to intr-mbox-0 additional tells the
5149 * NIC to stop sending us irqs, engaging "in-intr-handler"
5150 * event coalescing.
c04cb347
MC		 5151 *
5152 * Flush the mailbox to de-assert the IRQ immediately to prevent
5153 * spurious interrupts. The flush impacts performance but
5154 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5155 */
c04cb347 5156 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5157
5158 /*
5159 * In a shared interrupt configuration, sometimes other devices'
5160 * interrupts will scream. We record the current status tag here
5161 * so that the above check can report that the screaming interrupts
5162 * are unhandled. Eventually they will be silenced.
5163 */
898a56f8 5164 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5165
d18edcb2
MC		 5166 if (tg3_irq_sync(tp))
5167 goto out;
624f8e50 5168
72334482 5169 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5170
09943a18 5171 napi_schedule(&tnapi->napi);
624f8e50 5172
f47c11ee 5173out:
1da177e4
LT		 5174 return IRQ_RETVAL(handled);
5175}
5176
7938109f 5177/* ISR for interrupt test */
7d12e780 5178static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5179{
09943a18
MC		 5180 struct tg3_napi *tnapi = dev_id;
5181 struct tg3 *tp = tnapi->tp;
898a56f8 5182 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5183
f9804ddb
MC		 5184 if ((sblk->status & SD_STATUS_UPDATED) ||
5185 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5186 tg3_disable_ints(tp);
7938109f
MC		 5187 return IRQ_RETVAL(1);
5188 }
5189 return IRQ_RETVAL(0);
5190}
5191
8e7a22e3 5192static int tg3_init_hw(struct tg3 *, int);
944d980e 5193static int tg3_halt(struct tg3 *, int, int);
1da177e4 5194
b9ec6c1b
MC		 5195/* Restart hardware after configuration changes, self-test, etc.
5196 * Invoked with tp->lock held.
5197 */
5198static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5199 __releases(tp->lock)
5200 __acquires(tp->lock)
b9ec6c1b
MC		 5201{
5202 int err;
5203
5204 err = tg3_init_hw(tp, reset_phy);
5205 if (err) {
5206 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5207 "aborting.\n", tp->dev->name);
5208 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5209 tg3_full_unlock(tp);
5210 del_timer_sync(&tp->timer);
5211 tp->irq_sync = 0;
fed97810 5212 tg3_napi_enable(tp);
b9ec6c1b
MC		 5213 dev_close(tp->dev);
5214 tg3_full_lock(tp, 0);
5215 }
5216 return err;
5217}
5218
1da177e4
LT		 5219#ifdef CONFIG_NET_POLL_CONTROLLER
5220static void tg3_poll_controller(struct net_device *dev)
5221{
4f125f42 5222 int i;
88b06bc2
MC		 5223 struct tg3 *tp = netdev_priv(dev);
5224
4f125f42
MC		 5225 for (i = 0; i < tp->irq_cnt; i++)
5226 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5227}
5228#endif
5229
c4028958 5230static void tg3_reset_task(struct work_struct *work)
1da177e4 5231{
c4028958 5232 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5233 int err;
1da177e4
LT		 5234 unsigned int restart_timer;
5235
7faa006f 5236 tg3_full_lock(tp, 0);
7faa006f
MC		 5237
5238 if (!netif_running(tp->dev)) {
7faa006f
MC		 5239 tg3_full_unlock(tp);
5240 return;
5241 }
5242
5243 tg3_full_unlock(tp);
5244
b02fd9e3
MC		 5245 tg3_phy_stop(tp);
5246
1da177e4
LT		 5247 tg3_netif_stop(tp);
5248
f47c11ee 5249 tg3_full_lock(tp, 1);
1da177e4
LT		 5250
5251 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5252 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5253
df3e6548
MC		 5254 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5255 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5256 tp->write32_rx_mbox = tg3_write_flush_reg32;
5257 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5258 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5259 }
5260
944d980e 5261 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5262 err = tg3_init_hw(tp, 1);
5263 if (err)
b9ec6c1b 5264 goto out;
1da177e4
LT		 5265
5266 tg3_netif_start(tp);
5267
1da177e4
LT		 5268 if (restart_timer)
5269 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5270
b9ec6c1b 5271out:
7faa006f 5272 tg3_full_unlock(tp);
b02fd9e3
MC		 5273
5274 if (!err)
5275 tg3_phy_start(tp);
1da177e4
LT		 5276}
5277
b0408751
MC		 5278static void tg3_dump_short_state(struct tg3 *tp)
5279{
5280 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5281 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5282 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5283 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5284}
5285
1da177e4
LT		 5286static void tg3_tx_timeout(struct net_device *dev)
5287{
5288 struct tg3 *tp = netdev_priv(dev);
5289
b0408751 5290 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5291 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5292 dev->name);
b0408751
MC		 5293 tg3_dump_short_state(tp);
5294 }
1da177e4
LT		 5295
5296 schedule_work(&tp->reset_task);
5297}
5298
c58ec932
MC		 5299/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5300static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5301{
5302 u32 base = (u32) mapping & 0xffffffff;
5303
5304 return ((base > 0xffffdcc0) &&
5305 (base + len + 8 < base));
5306}
5307
72f2afb8
MC		 5308/* Test for DMA addresses > 40-bit */
5309static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5310 int len)
5311{
5312#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5313 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5314 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5315 return 0;
5316#else
5317 return 0;
5318#endif
5319}
5320
f3f3f27e 5321static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5322
72f2afb8 5323/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5324static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5325 struct sk_buff *skb, u32 last_plus_one,
5326 u32 *start, u32 base_flags, u32 mss)
1da177e4 5327{
24f4efd4 5328 struct tg3 *tp = tnapi->tp;
41588ba1 5329 struct sk_buff *new_skb;
c58ec932 5330 dma_addr_t new_addr = 0;
1da177e4 5331 u32 entry = *start;
c58ec932 5332 int i, ret = 0;
1da177e4 5333
41588ba1
MC		 5334 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5335 new_skb = skb_copy(skb, GFP_ATOMIC);
5336 else {
5337 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5338
5339 new_skb = skb_copy_expand(skb,
5340 skb_headroom(skb) + more_headroom,
5341 skb_tailroom(skb), GFP_ATOMIC);
5342 }
5343
1da177e4 5344 if (!new_skb) {
c58ec932
MC		 5345 ret = -1;
5346 } else {
5347 /* New SKB is guaranteed to be linear. */
5348 entry = *start;
f4188d8a
AD		 5349 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5350 PCI_DMA_TODEVICE);
5351 /* Make sure the mapping succeeded */
5352 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5353 ret = -1;
5354 dev_kfree_skb(new_skb);
5355 new_skb = NULL;
90079ce8 5356
c58ec932
MC		 5357 /* Make sure new skb does not cross any 4G boundaries.
5358 * Drop the packet if it does.
5359 */
f4188d8a
AD		 5360 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5361 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5362 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5363 PCI_DMA_TODEVICE);
c58ec932
MC		 5364 ret = -1;
5365 dev_kfree_skb(new_skb);
5366 new_skb = NULL;
5367 } else {
f3f3f27e 5368 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5369 base_flags, 1 | (mss << 1));
5370 *start = NEXT_TX(entry);
5371 }
1da177e4
LT		 5372 }
5373
1da177e4
LT		 5374 /* Now clean up the sw ring entries. */
5375 i = 0;
5376 while (entry != last_plus_one) {
f4188d8a
AD		 5377 int len;
5378
f3f3f27e 5379 if (i == 0)
f4188d8a 5380 len = skb_headlen(skb);
f3f3f27e 5381 else
f4188d8a
AD		 5382 len = skb_shinfo(skb)->frags[i-1].size;
5383
5384 pci_unmap_single(tp->pdev,
5385 pci_unmap_addr(&tnapi->tx_buffers[entry],
5386 mapping),
5387 len, PCI_DMA_TODEVICE);
5388 if (i == 0) {
5389 tnapi->tx_buffers[entry].skb = new_skb;
5390 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5391 new_addr);
5392 } else {
f3f3f27e 5393 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5394 }
1da177e4
LT		 5395 entry = NEXT_TX(entry);
5396 i++;
5397 }
5398
5399 dev_kfree_skb(skb);
5400
c58ec932 5401 return ret;
1da177e4
LT		 5402}
5403
f3f3f27e 5404static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5405 dma_addr_t mapping, int len, u32 flags,
5406 u32 mss_and_is_end)
5407{
f3f3f27e 5408 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5409 int is_end = (mss_and_is_end & 0x1);
5410 u32 mss = (mss_and_is_end >> 1);
5411 u32 vlan_tag = 0;
5412
5413 if (is_end)
5414 flags |= TXD_FLAG_END;
5415 if (flags & TXD_FLAG_VLAN) {
5416 vlan_tag = flags >> 16;
5417 flags &= 0xffff;
5418 }
5419 vlan_tag |= (mss << TXD_MSS_SHIFT);
5420
5421 txd->addr_hi = ((u64) mapping >> 32);
5422 txd->addr_lo = ((u64) mapping & 0xffffffff);
5423 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5424 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5425}
5426
5a6f3074 5427/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5428 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5429 */
61357325
SH		 5430static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5431 struct net_device *dev)
5a6f3074
MC		 5432{
5433 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5434 u32 len, entry, base_flags, mss;
90079ce8 5435 dma_addr_t mapping;
fe5f5787
MC		 5436 struct tg3_napi *tnapi;
5437 struct netdev_queue *txq;
f4188d8a
AD		 5438 unsigned int i, last;
5439
5a6f3074 5440
fe5f5787
MC		 5441 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5442 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5444 tnapi++;
5a6f3074 5445
00b70504 5446 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5447 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5448 * interrupt. Furthermore, IRQ processing runs lockless so we have
5449 * no IRQ context deadlocks to worry about either. Rejoice!
5450 */
f3f3f27e 5451 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5452 if (!netif_tx_queue_stopped(txq)) {
5453 netif_tx_stop_queue(txq);
5a6f3074
MC		 5454
5455 /* This is a hard error, log it. */
5456 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5457 "queue awake!\n", dev->name);
5458 }
5a6f3074
MC		 5459 return NETDEV_TX_BUSY;
5460 }
5461
f3f3f27e 5462 entry = tnapi->tx_prod;
5a6f3074 5463 base_flags = 0;
5a6f3074 5464 mss = 0;
c13e3713 5465 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5466 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5467 u32 hdrlen;
5a6f3074
MC		 5468
5469 if (skb_header_cloned(skb) &&
5470 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5471 dev_kfree_skb(skb);
5472 goto out_unlock;
5473 }
5474
b0026624 5475 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5476 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5477 else {
eddc9ec5
ACM		 5478 struct iphdr *iph = ip_hdr(skb);
5479
ab6a5bb6 5480 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5481 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5482
eddc9ec5
ACM		 5483 iph->check = 0;
5484 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5485 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5486 }
5a6f3074 5487
e849cdc3 5488 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5489 mss |= (hdrlen & 0xc) << 12;
5490 if (hdrlen & 0x10)
5491 base_flags |= 0x00000010;
5492 base_flags |= (hdrlen & 0x3e0) << 5;
5493 } else
5494 mss |= hdrlen << 9;
5495
5a6f3074
MC		 5496 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5497 TXD_FLAG_CPU_POST_DMA);
5498
aa8223c7 5499 tcp_hdr(skb)->check = 0;
5a6f3074 5500
5a6f3074 5501 }
84fa7933 5502 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5503 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5504#if TG3_VLAN_TAG_USED
5505 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5506 base_flags |= (TXD_FLAG_VLAN |
5507 (vlan_tx_tag_get(skb) << 16));
5508#endif
5509
f4188d8a
AD		 5510 len = skb_headlen(skb);
5511
5512 /* Queue skb data, a.k.a. the main skb fragment. */
5513 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5514 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5515 dev_kfree_skb(skb);
5516 goto out_unlock;
5517 }
5518
f3f3f27e 5519 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5520 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5521
b703df6f 5522 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5523 !mss && skb->len > ETH_DATA_LEN)
5524 base_flags |= TXD_FLAG_JMB_PKT;
5525
f3f3f27e 5526 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5527 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5528
5529 entry = NEXT_TX(entry);
5530
5531 /* Now loop through additional data fragments, and queue them. */
5532 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5533 last = skb_shinfo(skb)->nr_frags - 1;
5534 for (i = 0; i <= last; i++) {
5535 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5536
5537 len = frag->size;
f4188d8a
AD		 5538 mapping = pci_map_page(tp->pdev,
5539 frag->page,
5540 frag->page_offset,
5541 len, PCI_DMA_TODEVICE);
5542 if (pci_dma_mapping_error(tp->pdev, mapping))
5543 goto dma_error;
5544
f3f3f27e 5545 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5546 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5547 mapping);
5a6f3074 5548
f3f3f27e 5549 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5550 base_flags, (i == last) | (mss << 1));
5551
5552 entry = NEXT_TX(entry);
5553 }
5554 }
5555
5556 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5557 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5558
f3f3f27e
MC		 5559 tnapi->tx_prod = entry;
5560 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5561 netif_tx_stop_queue(txq);
f3f3f27e 5562 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5563 netif_tx_wake_queue(txq);
5a6f3074
MC		 5564 }
5565
5566out_unlock:
cdd0db05 5567 mmiowb();
5a6f3074
MC		 5568
5569 return NETDEV_TX_OK;
f4188d8a
AD		 5570
5571dma_error:
5572 last = i;
5573 entry = tnapi->tx_prod;
5574 tnapi->tx_buffers[entry].skb = NULL;
5575 pci_unmap_single(tp->pdev,
5576 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5577 skb_headlen(skb),
5578 PCI_DMA_TODEVICE);
5579 for (i = 0; i <= last; i++) {
5580 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5581 entry = NEXT_TX(entry);
5582
5583 pci_unmap_page(tp->pdev,
5584 pci_unmap_addr(&tnapi->tx_buffers[entry],
5585 mapping),
5586 frag->size, PCI_DMA_TODEVICE);
5587 }
5588
5589 dev_kfree_skb(skb);
5590 return NETDEV_TX_OK;
5a6f3074
MC		 5591}
5592
61357325
SH		 5593static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5594 struct net_device *);
52c0fd83
MC		 5595
5596/* Use GSO to workaround a rare TSO bug that may be triggered when the
5597 * TSO header is greater than 80 bytes.
5598 */
5599static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5600{
5601 struct sk_buff *segs, *nskb;
f3f3f27e 5602 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5603
5604 /* Estimate the number of fragments in the worst case */
f3f3f27e 5605 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5606 netif_stop_queue(tp->dev);
f3f3f27e 5607 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5608 return NETDEV_TX_BUSY;
5609
5610 netif_wake_queue(tp->dev);
52c0fd83
MC		 5611 }
5612
5613 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5614 if (IS_ERR(segs))
52c0fd83
MC		 5615 goto tg3_tso_bug_end;
5616
5617 do {
5618 nskb = segs;
5619 segs = segs->next;
5620 nskb->next = NULL;
5621 tg3_start_xmit_dma_bug(nskb, tp->dev);
5622 } while (segs);
5623
5624tg3_tso_bug_end:
5625 dev_kfree_skb(skb);
5626
5627 return NETDEV_TX_OK;
5628}
52c0fd83 5629
5a6f3074
MC		 5630/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5631 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5632 */
61357325
SH		 5633static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5634 struct net_device *dev)
1da177e4
LT		 5635{
5636 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5637 u32 len, entry, base_flags, mss;
5638 int would_hit_hwbug;
90079ce8 5639 dma_addr_t mapping;
24f4efd4
MC		 5640 struct tg3_napi *tnapi;
5641 struct netdev_queue *txq;
f4188d8a
AD		 5642 unsigned int i, last;
5643
1da177e4 5644
24f4efd4
MC		 5645 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5646 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5647 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5648 tnapi++;
1da177e4 5649
00b70504 5650 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5651 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5652 * interrupt. Furthermore, IRQ processing runs lockless so we have
5653 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5654 */
f3f3f27e 5655 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5656 if (!netif_tx_queue_stopped(txq)) {
5657 netif_tx_stop_queue(txq);
1f064a87
SH		 5658
5659 /* This is a hard error, log it. */
5660 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5661 "queue awake!\n", dev->name);
5662 }
1da177e4
LT		 5663 return NETDEV_TX_BUSY;
5664 }
5665
f3f3f27e 5666 entry = tnapi->tx_prod;
1da177e4 5667 base_flags = 0;
84fa7933 5668 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5669 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5670
c13e3713 5671 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5672 struct iphdr *iph;
92c6b8d1 5673 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5674
5675 if (skb_header_cloned(skb) &&
5676 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5677 dev_kfree_skb(skb);
5678 goto out_unlock;
5679 }
5680
ab6a5bb6 5681 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5682 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5683
52c0fd83
MC		 5684 hdr_len = ip_tcp_len + tcp_opt_len;
5685 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5686 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5687 return (tg3_tso_bug(tp, skb));
5688
1da177e4
LT		 5689 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5690 TXD_FLAG_CPU_POST_DMA);
5691
eddc9ec5
ACM		 5692 iph = ip_hdr(skb);
5693 iph->check = 0;
5694 iph->tot_len = htons(mss + hdr_len);
1da177e4 5695 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5696 tcp_hdr(skb)->check = 0;
1da177e4 5697 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5698 } else
5699 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5700 iph->daddr, 0,
5701 IPPROTO_TCP,
5702 0);
1da177e4 5703
615774fe
MC		 5704 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5705 mss |= (hdr_len & 0xc) << 12;
5706 if (hdr_len & 0x10)
5707 base_flags |= 0x00000010;
5708 base_flags |= (hdr_len & 0x3e0) << 5;
5709 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5710 mss |= hdr_len << 9;
5711 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5712 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5713 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5714 int tsflags;
5715
eddc9ec5 5716 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5717 mss |= (tsflags << 11);
5718 }
5719 } else {
eddc9ec5 5720 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5721 int tsflags;
5722
eddc9ec5 5723 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5724 base_flags |= tsflags << 12;
5725 }
5726 }
5727 }
1da177e4
LT		 5728#if TG3_VLAN_TAG_USED
5729 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5730 base_flags |= (TXD_FLAG_VLAN |
5731 (vlan_tx_tag_get(skb) << 16));
5732#endif
5733
b703df6f 5734 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5735 !mss && skb->len > ETH_DATA_LEN)
5736 base_flags |= TXD_FLAG_JMB_PKT;
5737
f4188d8a
AD		 5738 len = skb_headlen(skb);
5739
5740 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5741 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5742 dev_kfree_skb(skb);
5743 goto out_unlock;
5744 }
5745
f3f3f27e 5746 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5747 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5748
5749 would_hit_hwbug = 0;
5750
92c6b8d1
MC		 5751 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5752 would_hit_hwbug = 1;
5753
0e1406dd
MC		 5754 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5755 tg3_4g_overflow_test(mapping, len))
5756 would_hit_hwbug = 1;
5757
5758 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5759 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5760 would_hit_hwbug = 1;
0e1406dd
MC		 5761
5762 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5763 would_hit_hwbug = 1;
1da177e4 5764
f3f3f27e 5765 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5766 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5767
5768 entry = NEXT_TX(entry);
5769
5770 /* Now loop through additional data fragments, and queue them. */
5771 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5772 last = skb_shinfo(skb)->nr_frags - 1;
5773 for (i = 0; i <= last; i++) {
5774 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5775
5776 len = frag->size;
f4188d8a
AD		 5777 mapping = pci_map_page(tp->pdev,
5778 frag->page,
5779 frag->page_offset,
5780 len, PCI_DMA_TODEVICE);
1da177e4 5781
f3f3f27e 5782 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5783 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5784 mapping);
5785 if (pci_dma_mapping_error(tp->pdev, mapping))
5786 goto dma_error;
1da177e4 5787
92c6b8d1
MC		 5788 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5789 len <= 8)
5790 would_hit_hwbug = 1;
5791
0e1406dd
MC		 5792 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5793 tg3_4g_overflow_test(mapping, len))
c58ec932 5794 would_hit_hwbug = 1;
1da177e4 5795
0e1406dd
MC		 5796 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5797 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5798 would_hit_hwbug = 1;
5799
1da177e4 5800 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5801 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5802 base_flags, (i == last)|(mss << 1));
5803 else
f3f3f27e 5804 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5805 base_flags, (i == last));
5806
5807 entry = NEXT_TX(entry);
5808 }
5809 }
5810
5811 if (would_hit_hwbug) {
5812 u32 last_plus_one = entry;
5813 u32 start;
1da177e4 5814
c58ec932
MC		 5815 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5816 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5817
5818 /* If the workaround fails due to memory/mapping
5819 * failure, silently drop this packet.
5820 */
24f4efd4 5821 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5822 &start, base_flags, mss))
1da177e4
LT		 5823 goto out_unlock;
5824
5825 entry = start;
5826 }
5827
5828 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5829 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5830
f3f3f27e
MC		 5831 tnapi->tx_prod = entry;
5832 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5833 netif_tx_stop_queue(txq);
f3f3f27e 5834 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5835 netif_tx_wake_queue(txq);
51b91468 5836 }
1da177e4
LT		 5837
5838out_unlock:
cdd0db05 5839 mmiowb();
1da177e4
LT		 5840
5841 return NETDEV_TX_OK;
f4188d8a
AD		 5842
5843dma_error:
5844 last = i;
5845 entry = tnapi->tx_prod;
5846 tnapi->tx_buffers[entry].skb = NULL;
5847 pci_unmap_single(tp->pdev,
5848 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5849 skb_headlen(skb),
5850 PCI_DMA_TODEVICE);
5851 for (i = 0; i <= last; i++) {
5852 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5853 entry = NEXT_TX(entry);
5854
5855 pci_unmap_page(tp->pdev,
5856 pci_unmap_addr(&tnapi->tx_buffers[entry],
5857 mapping),
5858 frag->size, PCI_DMA_TODEVICE);
5859 }
5860
5861 dev_kfree_skb(skb);
5862 return NETDEV_TX_OK;
1da177e4
LT		 5863}
5864
5865static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5866 int new_mtu)
5867{
5868 dev->mtu = new_mtu;
5869
ef7f5ec0 5870 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5871 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5872 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5873 ethtool_op_set_tso(dev, 0);
5874 }
5875 else
5876 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5877 } else {
a4e2b347 5878 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5879 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5880 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5881 }
1da177e4
LT		 5882}
5883
5884static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5885{
5886 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5887 int err;
1da177e4
LT		 5888
5889 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5890 return -EINVAL;
5891
5892 if (!netif_running(dev)) {
5893 /* We'll just catch it later when the
5894 * device is up'd.
5895 */
5896 tg3_set_mtu(dev, tp, new_mtu);
5897 return 0;
5898 }
5899
b02fd9e3
MC		 5900 tg3_phy_stop(tp);
5901
1da177e4 5902 tg3_netif_stop(tp);
f47c11ee
DM		 5903
5904 tg3_full_lock(tp, 1);
1da177e4 5905
944d980e 5906 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5907
5908 tg3_set_mtu(dev, tp, new_mtu);
5909
b9ec6c1b 5910 err = tg3_restart_hw(tp, 0);
1da177e4 5911
b9ec6c1b
MC		 5912 if (!err)
5913 tg3_netif_start(tp);
1da177e4 5914
f47c11ee 5915 tg3_full_unlock(tp);
1da177e4 5916
b02fd9e3
MC		 5917 if (!err)
5918 tg3_phy_start(tp);
5919
b9ec6c1b 5920 return err;
1da177e4
LT		 5921}
5922
21f581a5
MC		 5923static void tg3_rx_prodring_free(struct tg3 *tp,
5924 struct tg3_rx_prodring_set *tpr)
1da177e4 5925{
1da177e4
LT		 5926 int i;
5927
b196c7e4
MC		 5928 if (tpr != &tp->prodring[0]) {
5929 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5930 i = (i + 1) % TG3_RX_RING_SIZE)
5931 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5932 tp->rx_pkt_map_sz);
5933
5934 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5935 for (i = tpr->rx_jmb_cons_idx;
5936 i != tpr->rx_jmb_prod_idx;
5937 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5938 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5939 TG3_RX_JMB_MAP_SZ);
5940 }
5941 }
5942
2b2cdb65 5943 return;
b196c7e4 5944 }
1da177e4 5945
2b2cdb65
MC		 5946 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5947 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5948 tp->rx_pkt_map_sz);
1da177e4 5949
cf7a7298 5950 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5951 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5952 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5953 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5954 }
5955}
5956
5957/* Initialize tx/rx rings for packet processing.
5958 *
5959 * The chip has been shut down and the driver detached from
5960 * the networking, so no interrupts or new tx packets will
5961 * end up in the driver. tp->{tx,}lock are held and thus
5962 * we may not sleep.
5963 */
21f581a5
MC		 5964static int tg3_rx_prodring_alloc(struct tg3 *tp,
5965 struct tg3_rx_prodring_set *tpr)
1da177e4 5966{
287be12e 5967 u32 i, rx_pkt_dma_sz;
1da177e4 5968
b196c7e4
MC		 5969 tpr->rx_std_cons_idx = 0;
5970 tpr->rx_std_prod_idx = 0;
5971 tpr->rx_jmb_cons_idx = 0;
5972 tpr->rx_jmb_prod_idx = 0;
5973
2b2cdb65
MC		 5974 if (tpr != &tp->prodring[0]) {
5975 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5976 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5977 memset(&tpr->rx_jmb_buffers[0], 0,
5978 TG3_RX_JMB_BUFF_RING_SIZE);
5979 goto done;
5980 }
5981
1da177e4 5982 /* Zero out all descriptors. */
21f581a5 5983 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5984
287be12e 5985 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5986 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5987 tp->dev->mtu > ETH_DATA_LEN)
5988 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5989 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5990
1da177e4
LT		 5991 /* Initialize invariants of the rings, we only set this
5992 * stuff once. This works because the card does not
5993 * write into the rx buffer posting rings.
5994 */
5995 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5996 struct tg3_rx_buffer_desc *rxd;
5997
21f581a5 5998 rxd = &tpr->rx_std[i];
287be12e 5999 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6000 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6001 rxd->opaque = (RXD_OPAQUE_RING_STD |
6002 (i << RXD_OPAQUE_INDEX_SHIFT));
6003 }
6004
1da177e4
LT		 6005 /* Now allocate fresh SKBs for each rx ring. */
6006 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6007 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6008 printk(KERN_WARNING PFX
6009 "%s: Using a smaller RX standard ring, "
6010 "only %d out of %d buffers were allocated "
6011 "successfully.\n",
6012 tp->dev->name, i, tp->rx_pending);
6013 if (i == 0)
cf7a7298 6014 goto initfail;
32d8c572 6015 tp->rx_pending = i;
1da177e4 6016 break;
32d8c572 6017 }
1da177e4
LT		 6018 }
6019
cf7a7298
MC		 6020 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6021 goto done;
6022
21f581a5 6023 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6024
0f893dc6 6025 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6026 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6027 struct tg3_rx_buffer_desc *rxd;
6028
79ed5ac7 6029 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6030 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6031 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6032 RXD_FLAG_JUMBO;
6033 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6034 (i << RXD_OPAQUE_INDEX_SHIFT));
6035 }
6036
1da177e4 6037 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6038 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6039 i) < 0) {
32d8c572
MC		 6040 printk(KERN_WARNING PFX
6041 "%s: Using a smaller RX jumbo ring, "
6042 "only %d out of %d buffers were "
6043 "allocated successfully.\n",
6044 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6045 if (i == 0)
6046 goto initfail;
32d8c572 6047 tp->rx_jumbo_pending = i;
1da177e4 6048 break;
32d8c572 6049 }
1da177e4
LT		 6050 }
6051 }
cf7a7298
MC		 6052
6053done:
32d8c572 6054 return 0;
cf7a7298
MC		 6055
6056initfail:
21f581a5 6057 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6058 return -ENOMEM;
1da177e4
LT		 6059}
6060
21f581a5
MC		 6061static void tg3_rx_prodring_fini(struct tg3 *tp,
6062 struct tg3_rx_prodring_set *tpr)
1da177e4 6063{
21f581a5
MC		 6064 kfree(tpr->rx_std_buffers);
6065 tpr->rx_std_buffers = NULL;
6066 kfree(tpr->rx_jmb_buffers);
6067 tpr->rx_jmb_buffers = NULL;
6068 if (tpr->rx_std) {
1da177e4 6069 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6070 tpr->rx_std, tpr->rx_std_mapping);
6071 tpr->rx_std = NULL;
1da177e4 6072 }
21f581a5 6073 if (tpr->rx_jmb) {
1da177e4 6074 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6075 tpr->rx_jmb, tpr->rx_jmb_mapping);
6076 tpr->rx_jmb = NULL;
1da177e4 6077 }
cf7a7298
MC		 6078}
6079
21f581a5
MC		 6080static int tg3_rx_prodring_init(struct tg3 *tp,
6081 struct tg3_rx_prodring_set *tpr)
cf7a7298 6082{
2b2cdb65 6083 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6084 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6085 return -ENOMEM;
6086
21f581a5
MC		 6087 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6088 &tpr->rx_std_mapping);
6089 if (!tpr->rx_std)
cf7a7298
MC		 6090 goto err_out;
6091
6092 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6093 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6094 GFP_KERNEL);
6095 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6096 goto err_out;
6097
21f581a5
MC		 6098 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6099 TG3_RX_JUMBO_RING_BYTES,
6100 &tpr->rx_jmb_mapping);
6101 if (!tpr->rx_jmb)
cf7a7298
MC		 6102 goto err_out;
6103 }
6104
6105 return 0;
6106
6107err_out:
21f581a5 6108 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6109 return -ENOMEM;
6110}
6111
6112/* Free up pending packets in all rx/tx rings.
6113 *
6114 * The chip has been shut down and the driver detached from
6115 * the networking, so no interrupts or new tx packets will
6116 * end up in the driver. tp->{tx,}lock is not held and we are not
6117 * in an interrupt context and thus may sleep.
6118 */
6119static void tg3_free_rings(struct tg3 *tp)
6120{
f77a6a8e 6121 int i, j;
cf7a7298 6122
f77a6a8e
MC		 6123 for (j = 0; j < tp->irq_cnt; j++) {
6124 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6125
0c1d0e2b
MC		 6126 if (!tnapi->tx_buffers)
6127 continue;
6128
f77a6a8e 6129 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6130 struct ring_info *txp;
f77a6a8e 6131 struct sk_buff *skb;
f4188d8a 6132 unsigned int k;
cf7a7298 6133
f77a6a8e
MC		 6134 txp = &tnapi->tx_buffers[i];
6135 skb = txp->skb;
cf7a7298 6136
f77a6a8e
MC		 6137 if (skb == NULL) {
6138 i++;
6139 continue;
6140 }
cf7a7298 6141
f4188d8a
AD		 6142 pci_unmap_single(tp->pdev,
6143 pci_unmap_addr(txp, mapping),
6144 skb_headlen(skb),
6145 PCI_DMA_TODEVICE);
f77a6a8e 6146 txp->skb = NULL;
cf7a7298 6147
f4188d8a
AD		 6148 i++;
6149
6150 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6151 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6152 pci_unmap_page(tp->pdev,
6153 pci_unmap_addr(txp, mapping),
6154 skb_shinfo(skb)->frags[k].size,
6155 PCI_DMA_TODEVICE);
6156 i++;
6157 }
f77a6a8e
MC		 6158
6159 dev_kfree_skb_any(skb);
6160 }
cf7a7298 6161
2b2cdb65
MC		 6162 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6163 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6164 }
cf7a7298
MC		 6165}
6166
6167/* Initialize tx/rx rings for packet processing.
6168 *
6169 * The chip has been shut down and the driver detached from
6170 * the networking, so no interrupts or new tx packets will
6171 * end up in the driver. tp->{tx,}lock are held and thus
6172 * we may not sleep.
6173 */
6174static int tg3_init_rings(struct tg3 *tp)
6175{
f77a6a8e 6176 int i;
72334482 6177
cf7a7298
MC		 6178 /* Free up all the SKBs. */
6179 tg3_free_rings(tp);
6180
f77a6a8e
MC		 6181 for (i = 0; i < tp->irq_cnt; i++) {
6182 struct tg3_napi *tnapi = &tp->napi[i];
6183
6184 tnapi->last_tag = 0;
6185 tnapi->last_irq_tag = 0;
6186 tnapi->hw_status->status = 0;
6187 tnapi->hw_status->status_tag = 0;
6188 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6189
f77a6a8e
MC		 6190 tnapi->tx_prod = 0;
6191 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6192 if (tnapi->tx_ring)
6193 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6194
6195 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6196 if (tnapi->rx_rcb)
6197 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 6198
6199 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6200 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6201 return -ENOMEM;
f77a6a8e 6202 }
72334482 6203
2b2cdb65 6204 return 0;
cf7a7298
MC		 6205}
6206
6207/*
6208 * Must not be invoked with interrupt sources disabled and
6209 * the hardware shutdown down.
6210 */
6211static void tg3_free_consistent(struct tg3 *tp)
6212{
f77a6a8e 6213 int i;
898a56f8 6214
f77a6a8e
MC		 6215 for (i = 0; i < tp->irq_cnt; i++) {
6216 struct tg3_napi *tnapi = &tp->napi[i];
6217
6218 if (tnapi->tx_ring) {
6219 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6220 tnapi->tx_ring, tnapi->tx_desc_mapping);
6221 tnapi->tx_ring = NULL;
6222 }
6223
6224 kfree(tnapi->tx_buffers);
6225 tnapi->tx_buffers = NULL;
6226
6227 if (tnapi->rx_rcb) {
6228 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6229 tnapi->rx_rcb,
6230 tnapi->rx_rcb_mapping);
6231 tnapi->rx_rcb = NULL;
6232 }
6233
6234 if (tnapi->hw_status) {
6235 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6236 tnapi->hw_status,
6237 tnapi->status_mapping);
6238 tnapi->hw_status = NULL;
6239 }
1da177e4 6240 }
f77a6a8e 6241
1da177e4
LT		 6242 if (tp->hw_stats) {
6243 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6244 tp->hw_stats, tp->stats_mapping);
6245 tp->hw_stats = NULL;
6246 }
f77a6a8e 6247
2b2cdb65
MC		 6248 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6249 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6250}
6251
6252/*
6253 * Must not be invoked with interrupt sources disabled and
6254 * the hardware shutdown down. Can sleep.
6255 */
6256static int tg3_alloc_consistent(struct tg3 *tp)
6257{
f77a6a8e 6258 int i;
898a56f8 6259
2b2cdb65
MC		 6260 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6261 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6262 goto err_out;
6263 }
1da177e4 6264
f77a6a8e
MC		 6265 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6266 sizeof(struct tg3_hw_stats),
6267 &tp->stats_mapping);
6268 if (!tp->hw_stats)
1da177e4
LT		 6269 goto err_out;
6270
f77a6a8e 6271 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6272
f77a6a8e
MC		 6273 for (i = 0; i < tp->irq_cnt; i++) {
6274 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6275 struct tg3_hw_status *sblk;
1da177e4 6276
f77a6a8e
MC		 6277 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6278 TG3_HW_STATUS_SIZE,
6279 &tnapi->status_mapping);
6280 if (!tnapi->hw_status)
6281 goto err_out;
898a56f8 6282
f77a6a8e 6283 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6284 sblk = tnapi->hw_status;
6285
19cfaecc
MC		 6286 /* If multivector TSS is enabled, vector 0 does not handle
6287 * tx interrupts. Don't allocate any resources for it.
6288 */
6289 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6290 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6291 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6292 TG3_TX_RING_SIZE,
6293 GFP_KERNEL);
6294 if (!tnapi->tx_buffers)
6295 goto err_out;
6296
6297 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6298 TG3_TX_RING_BYTES,
6299 &tnapi->tx_desc_mapping);
6300 if (!tnapi->tx_ring)
6301 goto err_out;
6302 }
6303
8d9d7cfc
MC		 6304 /*
6305 * When RSS is enabled, the status block format changes
6306 * slightly. The "rx_jumbo_consumer", "reserved",
6307 * and "rx_mini_consumer" members get mapped to the
6308 * other three rx return ring producer indexes.
6309 */
6310 switch (i) {
6311 default:
6312 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6313 break;
6314 case 2:
6315 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6316 break;
6317 case 3:
6318 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6319 break;
6320 case 4:
6321 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6322 break;
6323 }
72334482 6324
b196c7e4
MC		 6325 if (tp->irq_cnt == 1)
6326 tnapi->prodring = &tp->prodring[0];
6327 else if (i)
6328 tnapi->prodring = &tp->prodring[i - 1];
6329
0c1d0e2b
MC		 6330 /*
6331 * If multivector RSS is enabled, vector 0 does not handle
6332 * rx or tx interrupts. Don't allocate any resources for it.
6333 */
6334 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6335 continue;
6336
f77a6a8e
MC		 6337 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6338 TG3_RX_RCB_RING_BYTES(tp),
6339 &tnapi->rx_rcb_mapping);
6340 if (!tnapi->rx_rcb)
6341 goto err_out;
72334482 6342
f77a6a8e 6343 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6344 }
1da177e4
LT		 6345
6346 return 0;
6347
6348err_out:
6349 tg3_free_consistent(tp);
6350 return -ENOMEM;
6351}
6352
6353#define MAX_WAIT_CNT 1000
6354
6355/* To stop a block, clear the enable bit and poll till it
6356 * clears. tp->lock is held.
6357 */
b3b7d6be 6358static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6359{
6360 unsigned int i;
6361 u32 val;
6362
6363 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6364 switch (ofs) {
6365 case RCVLSC_MODE:
6366 case DMAC_MODE:
6367 case MBFREE_MODE:
6368 case BUFMGR_MODE:
6369 case MEMARB_MODE:
6370 /* We can't enable/disable these bits of the
6371 * 5705/5750, just say success.
6372 */
6373 return 0;
6374
6375 default:
6376 break;
855e1111 6377 }
1da177e4
LT		 6378 }
6379
6380 val = tr32(ofs);
6381 val &= ~enable_bit;
6382 tw32_f(ofs, val);
6383
6384 for (i = 0; i < MAX_WAIT_CNT; i++) {
6385 udelay(100);
6386 val = tr32(ofs);
6387 if ((val & enable_bit) == 0)
6388 break;
6389 }
6390
b3b7d6be 6391 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6392 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6393 "ofs=%lx enable_bit=%x\n",
6394 ofs, enable_bit);
6395 return -ENODEV;
6396 }
6397
6398 return 0;
6399}
6400
6401/* tp->lock is held. */
b3b7d6be 6402static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6403{
6404 int i, err;
6405
6406 tg3_disable_ints(tp);
6407
6408 tp->rx_mode &= ~RX_MODE_ENABLE;
6409 tw32_f(MAC_RX_MODE, tp->rx_mode);
6410 udelay(10);
6411
b3b7d6be
DM		 6412 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6413 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6414 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6415 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6416 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6417 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6418
6419 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6420 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6421 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6422 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6423 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6424 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6425 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6426
6427 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6428 tw32_f(MAC_MODE, tp->mac_mode);
6429 udelay(40);
6430
6431 tp->tx_mode &= ~TX_MODE_ENABLE;
6432 tw32_f(MAC_TX_MODE, tp->tx_mode);
6433
6434 for (i = 0; i < MAX_WAIT_CNT; i++) {
6435 udelay(100);
6436 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6437 break;
6438 }
6439 if (i >= MAX_WAIT_CNT) {
6440 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6441 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6442 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6443 err |= -ENODEV;
1da177e4
LT		 6444 }
6445
e6de8ad1 6446 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6447 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6448 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6449
6450 tw32(FTQ_RESET, 0xffffffff);
6451 tw32(FTQ_RESET, 0x00000000);
6452
b3b7d6be
DM		 6453 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6454 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6455
f77a6a8e
MC		 6456 for (i = 0; i < tp->irq_cnt; i++) {
6457 struct tg3_napi *tnapi = &tp->napi[i];
6458 if (tnapi->hw_status)
6459 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6460 }
1da177e4
LT		 6461 if (tp->hw_stats)
6462 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6463
1da177e4
LT		 6464 return err;
6465}
6466
0d3031d9
MC		 6467static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6468{
6469 int i;
6470 u32 apedata;
6471
6472 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6473 if (apedata != APE_SEG_SIG_MAGIC)
6474 return;
6475
6476 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6477 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6478 return;
6479
6480 /* Wait for up to 1 millisecond for APE to service previous event. */
6481 for (i = 0; i < 10; i++) {
6482 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6483 return;
6484
6485 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6486
6487 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6488 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6489 event | APE_EVENT_STATUS_EVENT_PENDING);
6490
6491 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6492
6493 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6494 break;
6495
6496 udelay(100);
6497 }
6498
6499 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6500 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6501}
6502
6503static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6504{
6505 u32 event;
6506 u32 apedata;
6507
6508 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6509 return;
6510
6511 switch (kind) {
6512 case RESET_KIND_INIT:
6513 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6514 APE_HOST_SEG_SIG_MAGIC);
6515 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6516 APE_HOST_SEG_LEN_MAGIC);
6517 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6518 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6519 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6520 APE_HOST_DRIVER_ID_MAGIC);
6521 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6522 APE_HOST_BEHAV_NO_PHYLOCK);
6523
6524 event = APE_EVENT_STATUS_STATE_START;
6525 break;
6526 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6527 /* With the interface we are currently using,
6528 * APE does not track driver state. Wiping
6529 * out the HOST SEGMENT SIGNATURE forces
6530 * the APE to assume OS absent status.
6531 */
6532 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6533
0d3031d9
MC		 6534 event = APE_EVENT_STATUS_STATE_UNLOAD;
6535 break;
6536 case RESET_KIND_SUSPEND:
6537 event = APE_EVENT_STATUS_STATE_SUSPEND;
6538 break;
6539 default:
6540 return;
6541 }
6542
6543 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6544
6545 tg3_ape_send_event(tp, event);
6546}
6547
1da177e4
LT		 6548/* tp->lock is held. */
6549static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6550{
f49639e6
DM		 6551 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6552 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6553
6554 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6555 switch (kind) {
6556 case RESET_KIND_INIT:
6557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6558 DRV_STATE_START);
6559 break;
6560
6561 case RESET_KIND_SHUTDOWN:
6562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6563 DRV_STATE_UNLOAD);
6564 break;
6565
6566 case RESET_KIND_SUSPEND:
6567 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6568 DRV_STATE_SUSPEND);
6569 break;
6570
6571 default:
6572 break;
855e1111 6573 }
1da177e4 6574 }
0d3031d9
MC		 6575
6576 if (kind == RESET_KIND_INIT ||
6577 kind == RESET_KIND_SUSPEND)
6578 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6579}
6580
6581/* tp->lock is held. */
6582static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6583{
6584 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6585 switch (kind) {
6586 case RESET_KIND_INIT:
6587 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6588 DRV_STATE_START_DONE);
6589 break;
6590
6591 case RESET_KIND_SHUTDOWN:
6592 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6593 DRV_STATE_UNLOAD_DONE);
6594 break;
6595
6596 default:
6597 break;
855e1111 6598 }
1da177e4 6599 }
0d3031d9
MC		 6600
6601 if (kind == RESET_KIND_SHUTDOWN)
6602 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6603}
6604
6605/* tp->lock is held. */
6606static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6607{
6608 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6609 switch (kind) {
6610 case RESET_KIND_INIT:
6611 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612 DRV_STATE_START);
6613 break;
6614
6615 case RESET_KIND_SHUTDOWN:
6616 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6617 DRV_STATE_UNLOAD);
6618 break;
6619
6620 case RESET_KIND_SUSPEND:
6621 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6622 DRV_STATE_SUSPEND);
6623 break;
6624
6625 default:
6626 break;
855e1111 6627 }
1da177e4
LT		 6628 }
6629}
6630
7a6f4369
MC		 6631static int tg3_poll_fw(struct tg3 *tp)
6632{
6633 int i;
6634 u32 val;
6635
b5d3772c 6636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6637 /* Wait up to 20ms for init done. */
6638 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6639 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6640 return 0;
0ccead18 6641 udelay(100);
b5d3772c
MC		 6642 }
6643 return -ENODEV;
6644 }
6645
7a6f4369
MC		 6646 /* Wait for firmware initialization to complete. */
6647 for (i = 0; i < 100000; i++) {
6648 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6649 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6650 break;
6651 udelay(10);
6652 }
6653
6654 /* Chip might not be fitted with firmware. Some Sun onboard
6655 * parts are configured like that. So don't signal the timeout
6656 * of the above loop as an error, but do report the lack of
6657 * running firmware once.
6658 */
6659 if (i >= 100000 &&
6660 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6661 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6662
6663 printk(KERN_INFO PFX "%s: No firmware running.\n",
6664 tp->dev->name);
6665 }
6666
6667 return 0;
6668}
6669
ee6a99b5
MC		 6670/* Save PCI command register before chip reset */
6671static void tg3_save_pci_state(struct tg3 *tp)
6672{
8a6eac90 6673 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6674}
6675
6676/* Restore PCI state after chip reset */
6677static void tg3_restore_pci_state(struct tg3 *tp)
6678{
6679 u32 val;
6680
6681 /* Re-enable indirect register accesses. */
6682 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6683 tp->misc_host_ctrl);
6684
6685 /* Set MAX PCI retry to zero. */
6686 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6687 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6688 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6689 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6690 /* Allow reads and writes to the APE register and memory space. */
6691 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6692 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6693 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6694 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6695
8a6eac90 6696 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6697
fcb389df
MC		 6698 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6699 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6700 pcie_set_readrq(tp->pdev, 4096);
6701 else {
6702 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6703 tp->pci_cacheline_sz);
6704 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6705 tp->pci_lat_timer);
6706 }
114342f2 6707 }
5f5c51e3 6708
ee6a99b5 6709 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6710 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6711 u16 pcix_cmd;
6712
6713 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6714 &pcix_cmd);
6715 pcix_cmd &= ~PCI_X_CMD_ERO;
6716 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6717 pcix_cmd);
6718 }
ee6a99b5
MC		 6719
6720 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6721
6722 /* Chip reset on 5780 will reset MSI enable bit,
6723 * so need to restore it.
6724 */
6725 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6726 u16 ctrl;
6727
6728 pci_read_config_word(tp->pdev,
6729 tp->msi_cap + PCI_MSI_FLAGS,
6730 &ctrl);
6731 pci_write_config_word(tp->pdev,
6732 tp->msi_cap + PCI_MSI_FLAGS,
6733 ctrl | PCI_MSI_FLAGS_ENABLE);
6734 val = tr32(MSGINT_MODE);
6735 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6736 }
6737 }
6738}
6739
1da177e4
LT		 6740static void tg3_stop_fw(struct tg3 *);
6741
6742/* tp->lock is held. */
6743static int tg3_chip_reset(struct tg3 *tp)
6744{
6745 u32 val;
1ee582d8 6746 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6747 int i, err;
1da177e4 6748
f49639e6
DM		 6749 tg3_nvram_lock(tp);
6750
77b483f1
MC		 6751 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6752
f49639e6
DM		 6753 /* No matching tg3_nvram_unlock() after this because
6754 * chip reset below will undo the nvram lock.
6755 */
6756 tp->nvram_lock_cnt = 0;
1da177e4 6757
ee6a99b5
MC		 6758 /* GRC_MISC_CFG core clock reset will clear the memory
6759 * enable bit in PCI register 4 and the MSI enable bit
6760 * on some chips, so we save relevant registers here.
6761 */
6762 tg3_save_pci_state(tp);
6763
d9ab5ad1 6764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6765 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6766 tw32(GRC_FASTBOOT_PC, 0);
6767
1da177e4
LT		 6768 /*
6769 * We must avoid the readl() that normally takes place.
6770 * It locks machines, causes machine checks, and other
6771 * fun things. So, temporarily disable the 5701
6772 * hardware workaround, while we do the reset.
6773 */
1ee582d8
MC		 6774 write_op = tp->write32;
6775 if (write_op == tg3_write_flush_reg32)
6776 tp->write32 = tg3_write32;
1da177e4 6777
d18edcb2
MC		 6778 /* Prevent the irq handler from reading or writing PCI registers
6779 * during chip reset when the memory enable bit in the PCI command
6780 * register may be cleared. The chip does not generate interrupt
6781 * at this time, but the irq handler may still be called due to irq
6782 * sharing or irqpoll.
6783 */
6784 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6785 for (i = 0; i < tp->irq_cnt; i++) {
6786 struct tg3_napi *tnapi = &tp->napi[i];
6787 if (tnapi->hw_status) {
6788 tnapi->hw_status->status = 0;
6789 tnapi->hw_status->status_tag = 0;
6790 }
6791 tnapi->last_tag = 0;
6792 tnapi->last_irq_tag = 0;
b8fa2f3a 6793 }
d18edcb2 6794 smp_mb();
4f125f42
MC		 6795
6796 for (i = 0; i < tp->irq_cnt; i++)
6797 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6798
255ca311
MC		 6799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6800 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6801 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6802 }
6803
1da177e4
LT		 6804 /* do the reset */
6805 val = GRC_MISC_CFG_CORECLK_RESET;
6806
6807 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6808 if (tr32(0x7e2c) == 0x60) {
6809 tw32(0x7e2c, 0x20);
6810 }
6811 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6812 tw32(GRC_MISC_CFG, (1 << 29));
6813 val |= (1 << 29);
6814 }
6815 }
6816
b5d3772c
MC		 6817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6818 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6819 tw32(GRC_VCPU_EXT_CTRL,
6820 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6821 }
6822
1da177e4
LT		 6823 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6824 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6825 tw32(GRC_MISC_CFG, val);
6826
1ee582d8
MC		 6827 /* restore 5701 hardware bug workaround write method */
6828 tp->write32 = write_op;
1da177e4
LT		 6829
6830 /* Unfortunately, we have to delay before the PCI read back.
6831 * Some 575X chips even will not respond to a PCI cfg access
6832 * when the reset command is given to the chip.
6833 *
6834 * How do these hardware designers expect things to work
6835 * properly if the PCI write is posted for a long period
6836 * of time? It is always necessary to have some method by
6837 * which a register read back can occur to push the write
6838 * out which does the reset.
6839 *
6840 * For most tg3 variants the trick below was working.
6841 * Ho hum...
6842 */
6843 udelay(120);
6844
6845 /* Flush PCI posted writes. The normal MMIO registers
6846 * are inaccessible at this time so this is the only
6847 * way to make this reliably (actually, this is no longer
6848 * the case, see above). I tried to use indirect
6849 * register read/write but this upset some 5701 variants.
6850 */
6851 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6852
6853 udelay(120);
6854
5e7dfd0f 6855 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6856 u16 val16;
6857
1da177e4
LT		 6858 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6859 int i;
6860 u32 cfg_val;
6861
6862 /* Wait for link training to complete. */
6863 for (i = 0; i < 5000; i++)
6864 udelay(100);
6865
6866 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6867 pci_write_config_dword(tp->pdev, 0xc4,
6868 cfg_val | (1 << 15));
6869 }
5e7dfd0f 6870
e7126997
MC		 6871 /* Clear the "no snoop" and "relaxed ordering" bits. */
6872 pci_read_config_word(tp->pdev,
6873 tp->pcie_cap + PCI_EXP_DEVCTL,
6874 &val16);
6875 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6876 PCI_EXP_DEVCTL_NOSNOOP_EN);
6877 /*
6878 * Older PCIe devices only support the 128 byte
6879 * MPS setting. Enforce the restriction.
5e7dfd0f 6880 */
e7126997
MC		 6881 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6882 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6883 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6884 pci_write_config_word(tp->pdev,
6885 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6886 val16);
5e7dfd0f
MC		 6887
6888 pcie_set_readrq(tp->pdev, 4096);
6889
6890 /* Clear error status */
6891 pci_write_config_word(tp->pdev,
6892 tp->pcie_cap + PCI_EXP_DEVSTA,
6893 PCI_EXP_DEVSTA_CED |
6894 PCI_EXP_DEVSTA_NFED |
6895 PCI_EXP_DEVSTA_FED |
6896 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6897 }
6898
ee6a99b5 6899 tg3_restore_pci_state(tp);
1da177e4 6900
d18edcb2
MC		 6901 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6902
ee6a99b5
MC		 6903 val = 0;
6904 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6905 val = tr32(MEMARB_MODE);
ee6a99b5 6906 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6907
6908 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6909 tg3_stop_fw(tp);
6910 tw32(0x5000, 0x400);
6911 }
6912
6913 tw32(GRC_MODE, tp->grc_mode);
6914
6915 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6916 val = tr32(0xc4);
1da177e4
LT		 6917
6918 tw32(0xc4, val | (1 << 15));
6919 }
6920
6921 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6923 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6924 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6925 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6926 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6927 }
6928
6929 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6930 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6931 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6932 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6933 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6934 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6935 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6936 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6937 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6938 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6939 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6940 } else
6941 tw32_f(MAC_MODE, 0);
6942 udelay(40);
6943
77b483f1
MC		 6944 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6945
7a6f4369
MC		 6946 err = tg3_poll_fw(tp);
6947 if (err)
6948 return err;
1da177e4 6949
0a9140cf
MC		 6950 tg3_mdio_start(tp);
6951
52cdf852
MC		 6952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6953 u8 phy_addr;
6954
6955 phy_addr = tp->phy_addr;
6956 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6957
6958 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6959 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6960 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6961 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6962 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6963 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6964 udelay(10);
6965
6966 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6967 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6968 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6969 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6970 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6971 udelay(10);
6972
6973 tp->phy_addr = phy_addr;
6974 }
6975
1da177e4 6976 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6977 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6978 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 6979 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6980 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 6981 val = tr32(0x7c00);
1da177e4
LT		 6982
6983 tw32(0x7c00, val | (1 << 25));
6984 }
6985
6986 /* Reprobe ASF enable state. */
6987 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6988 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6989 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6990 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6991 u32 nic_cfg;
6992
6993 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6994 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6995 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6996 tp->last_event_jiffies = jiffies;
cbf46853 6997 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6998 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6999 }
7000 }
7001
7002 return 0;
7003}
7004
7005/* tp->lock is held. */
7006static void tg3_stop_fw(struct tg3 *tp)
7007{
0d3031d9
MC		 7008 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7009 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7010 /* Wait for RX cpu to ACK the previous event. */
7011 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7012
7013 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7014
7015 tg3_generate_fw_event(tp);
1da177e4 7016
7c5026aa
MC		 7017 /* Wait for RX cpu to ACK this event. */
7018 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7019 }
7020}
7021
7022/* tp->lock is held. */
944d980e 7023static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7024{
7025 int err;
7026
7027 tg3_stop_fw(tp);
7028
944d980e 7029 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7030
b3b7d6be 7031 tg3_abort_hw(tp, silent);
1da177e4
LT		 7032 err = tg3_chip_reset(tp);
7033
daba2a63
MC		 7034 __tg3_set_mac_addr(tp, 0);
7035
944d980e
MC		 7036 tg3_write_sig_legacy(tp, kind);
7037 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7038
7039 if (err)
7040 return err;
7041
7042 return 0;
7043}
7044
1da177e4
LT		 7045#define RX_CPU_SCRATCH_BASE 0x30000
7046#define RX_CPU_SCRATCH_SIZE 0x04000
7047#define TX_CPU_SCRATCH_BASE 0x34000
7048#define TX_CPU_SCRATCH_SIZE 0x04000
7049
7050/* tp->lock is held. */
7051static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7052{
7053 int i;
7054
5d9428de
ES		 7055 BUG_ON(offset == TX_CPU_BASE &&
7056 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7057
b5d3772c
MC		 7058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7059 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7060
7061 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7062 return 0;
7063 }
1da177e4
LT		 7064 if (offset == RX_CPU_BASE) {
7065 for (i = 0; i < 10000; i++) {
7066 tw32(offset + CPU_STATE, 0xffffffff);
7067 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7068 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7069 break;
7070 }
7071
7072 tw32(offset + CPU_STATE, 0xffffffff);
7073 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7074 udelay(10);
7075 } else {
7076 for (i = 0; i < 10000; i++) {
7077 tw32(offset + CPU_STATE, 0xffffffff);
7078 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7079 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7080 break;
7081 }
7082 }
7083
7084 if (i >= 10000) {
7085 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7086 "and %s CPU\n",
7087 tp->dev->name,
7088 (offset == RX_CPU_BASE ? "RX" : "TX"));
7089 return -ENODEV;
7090 }
ec41c7df
MC		 7091
7092 /* Clear firmware's nvram arbitration. */
7093 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7094 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7095 return 0;
7096}
7097
7098struct fw_info {
077f849d
JSR		 7099 unsigned int fw_base;
7100 unsigned int fw_len;
7101 const __be32 *fw_data;
1da177e4
LT		 7102};
7103
7104/* tp->lock is held. */
7105static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7106 int cpu_scratch_size, struct fw_info *info)
7107{
ec41c7df 7108 int err, lock_err, i;
1da177e4
LT		 7109 void (*write_op)(struct tg3 *, u32, u32);
7110
7111 if (cpu_base == TX_CPU_BASE &&
7112 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7113 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7114 "TX cpu firmware on %s which is 5705.\n",
7115 tp->dev->name);
7116 return -EINVAL;
7117 }
7118
7119 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7120 write_op = tg3_write_mem;
7121 else
7122 write_op = tg3_write_indirect_reg32;
7123
1b628151
MC		 7124 /* It is possible that bootcode is still loading at this point.
7125 * Get the nvram lock first before halting the cpu.
7126 */
ec41c7df 7127 lock_err = tg3_nvram_lock(tp);
1da177e4 7128 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7129 if (!lock_err)
7130 tg3_nvram_unlock(tp);
1da177e4
LT		 7131 if (err)
7132 goto out;
7133
7134 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7135 write_op(tp, cpu_scratch_base + i, 0);
7136 tw32(cpu_base + CPU_STATE, 0xffffffff);
7137 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7138 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7139 write_op(tp, (cpu_scratch_base +
077f849d 7140 (info->fw_base & 0xffff) +
1da177e4 7141 (i * sizeof(u32))),
077f849d 7142 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7143
7144 err = 0;
7145
7146out:
1da177e4
LT		 7147 return err;
7148}
7149
7150/* tp->lock is held. */
7151static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7152{
7153 struct fw_info info;
077f849d 7154 const __be32 *fw_data;
1da177e4
LT		 7155 int err, i;
7156
077f849d
JSR		 7157 fw_data = (void *)tp->fw->data;
7158
7159 /* Firmware blob starts with version numbers, followed by
7160 start address and length. We are setting complete length.
7161 length = end_address_of_bss - start_address_of_text.
7162 Remainder is the blob to be loaded contiguously
7163 from start address. */
7164
7165 info.fw_base = be32_to_cpu(fw_data[1]);
7166 info.fw_len = tp->fw->size - 12;
7167 info.fw_data = &fw_data[3];
1da177e4
LT		 7168
7169 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7170 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7171 &info);
7172 if (err)
7173 return err;
7174
7175 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7176 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7177 &info);
7178 if (err)
7179 return err;
7180
7181 /* Now startup only the RX cpu. */
7182 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7183 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7184
7185 for (i = 0; i < 5; i++) {
077f849d 7186 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7187 break;
7188 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7189 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7190 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7191 udelay(1000);
7192 }
7193 if (i >= 5) {
7194 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7195 "to set RX CPU PC, is %08x should be %08x\n",
7196 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7197 info.fw_base);
1da177e4
LT		 7198 return -ENODEV;
7199 }
7200 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7201 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7202
7203 return 0;
7204}
7205
1da177e4 7206/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7207
7208/* tp->lock is held. */
7209static int tg3_load_tso_firmware(struct tg3 *tp)
7210{
7211 struct fw_info info;
077f849d 7212 const __be32 *fw_data;
1da177e4
LT		 7213 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7214 int err, i;
7215
7216 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7217 return 0;
7218
077f849d
JSR		 7219 fw_data = (void *)tp->fw->data;
7220
7221 /* Firmware blob starts with version numbers, followed by
7222 start address and length. We are setting complete length.
7223 length = end_address_of_bss - start_address_of_text.
7224 Remainder is the blob to be loaded contiguously
7225 from start address. */
7226
7227 info.fw_base = be32_to_cpu(fw_data[1]);
7228 cpu_scratch_size = tp->fw_len;
7229 info.fw_len = tp->fw->size - 12;
7230 info.fw_data = &fw_data[3];
7231
1da177e4 7232 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7233 cpu_base = RX_CPU_BASE;
7234 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7235 } else {
1da177e4
LT		 7236 cpu_base = TX_CPU_BASE;
7237 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7238 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7239 }
7240
7241 err = tg3_load_firmware_cpu(tp, cpu_base,
7242 cpu_scratch_base, cpu_scratch_size,
7243 &info);
7244 if (err)
7245 return err;
7246
7247 /* Now startup the cpu. */
7248 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7249 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7250
7251 for (i = 0; i < 5; i++) {
077f849d 7252 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7253 break;
7254 tw32(cpu_base + CPU_STATE, 0xffffffff);
7255 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7256 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7257 udelay(1000);
7258 }
7259 if (i >= 5) {
7260 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7261 "to set CPU PC, is %08x should be %08x\n",
7262 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7263 info.fw_base);
1da177e4
LT		 7264 return -ENODEV;
7265 }
7266 tw32(cpu_base + CPU_STATE, 0xffffffff);
7267 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7268 return 0;
7269}
7270
1da177e4 7271
1da177e4
LT		 7272static int tg3_set_mac_addr(struct net_device *dev, void *p)
7273{
7274 struct tg3 *tp = netdev_priv(dev);
7275 struct sockaddr *addr = p;
986e0aeb 7276 int err = 0, skip_mac_1 = 0;
1da177e4 7277
f9804ddb
MC		 7278 if (!is_valid_ether_addr(addr->sa_data))
7279 return -EINVAL;
7280
1da177e4
LT		 7281 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7282
e75f7c90
MC		 7283 if (!netif_running(dev))
7284 return 0;
7285
58712ef9 7286 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7287 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7288
986e0aeb
MC		 7289 addr0_high = tr32(MAC_ADDR_0_HIGH);
7290 addr0_low = tr32(MAC_ADDR_0_LOW);
7291 addr1_high = tr32(MAC_ADDR_1_HIGH);
7292 addr1_low = tr32(MAC_ADDR_1_LOW);
7293
7294 /* Skip MAC addr 1 if ASF is using it. */
7295 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7296 !(addr1_high == 0 && addr1_low == 0))
7297 skip_mac_1 = 1;
58712ef9 7298 }
986e0aeb
MC		 7299 spin_lock_bh(&tp->lock);
7300 __tg3_set_mac_addr(tp, skip_mac_1);
7301 spin_unlock_bh(&tp->lock);
1da177e4 7302
b9ec6c1b 7303 return err;
1da177e4
LT		 7304}
7305
7306/* tp->lock is held. */
7307static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7308 dma_addr_t mapping, u32 maxlen_flags,
7309 u32 nic_addr)
7310{
7311 tg3_write_mem(tp,
7312 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7313 ((u64) mapping >> 32));
7314 tg3_write_mem(tp,
7315 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7316 ((u64) mapping & 0xffffffff));
7317 tg3_write_mem(tp,
7318 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7319 maxlen_flags);
7320
7321 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7322 tg3_write_mem(tp,
7323 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7324 nic_addr);
7325}
7326
7327static void __tg3_set_rx_mode(struct net_device *);
d244c892 7328static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7329{
b6080e12
MC		 7330 int i;
7331
19cfaecc 7332 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7333 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7334 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7335 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7336 } else {
7337 tw32(HOSTCC_TXCOL_TICKS, 0);
7338 tw32(HOSTCC_TXMAX_FRAMES, 0);
7339 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7340 }
b6080e12 7341
19cfaecc
MC		 7342 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7343 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7344 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7345 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7346 } else {
b6080e12
MC		 7347 tw32(HOSTCC_RXCOL_TICKS, 0);
7348 tw32(HOSTCC_RXMAX_FRAMES, 0);
7349 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7350 }
b6080e12 7351
15f9850d
DM		 7352 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7353 u32 val = ec->stats_block_coalesce_usecs;
7354
b6080e12
MC		 7355 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7356 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7357
15f9850d
DM		 7358 if (!netif_carrier_ok(tp->dev))
7359 val = 0;
7360
7361 tw32(HOSTCC_STAT_COAL_TICKS, val);
7362 }
b6080e12
MC		 7363
7364 for (i = 0; i < tp->irq_cnt - 1; i++) {
7365 u32 reg;
7366
7367 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7368 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7369 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7370 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7371 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7372 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7373
7374 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7375 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7376 tw32(reg, ec->tx_coalesce_usecs);
7377 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7378 tw32(reg, ec->tx_max_coalesced_frames);
7379 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7380 tw32(reg, ec->tx_max_coalesced_frames_irq);
7381 }
b6080e12
MC		 7382 }
7383
7384 for (; i < tp->irq_max - 1; i++) {
7385 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7386 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7387 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7388
7389 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7390 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7391 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7392 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7393 }
b6080e12 7394 }
15f9850d 7395}
1da177e4 7396
2d31ecaf
MC		 7397/* tp->lock is held. */
7398static void tg3_rings_reset(struct tg3 *tp)
7399{
7400 int i;
f77a6a8e 7401 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7402 struct tg3_napi *tnapi = &tp->napi[0];
7403
7404 /* Disable all transmit rings but the first. */
7405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7406 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7407 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7408 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7409 else
7410 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7411
7412 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7413 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7414 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7415 BDINFO_FLAGS_DISABLED);
7416
7417
7418 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7420 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7421 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7422 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7423 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7425 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7426 else
7427 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7428
7429 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7430 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7431 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7432 BDINFO_FLAGS_DISABLED);
7433
7434 /* Disable interrupts */
7435 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7436
7437 /* Zero mailbox registers. */
f77a6a8e
MC		 7438 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7439 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7440 tp->napi[i].tx_prod = 0;
7441 tp->napi[i].tx_cons = 0;
7442 tw32_mailbox(tp->napi[i].prodmbox, 0);
7443 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7444 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7445 }
7446 } else {
7447 tp->napi[0].tx_prod = 0;
7448 tp->napi[0].tx_cons = 0;
7449 tw32_mailbox(tp->napi[0].prodmbox, 0);
7450 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7451 }
2d31ecaf
MC		 7452
7453 /* Make sure the NIC-based send BD rings are disabled. */
7454 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7455 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7456 for (i = 0; i < 16; i++)
7457 tw32_tx_mbox(mbox + i * 8, 0);
7458 }
7459
7460 txrcb = NIC_SRAM_SEND_RCB;
7461 rxrcb = NIC_SRAM_RCV_RET_RCB;
7462
7463 /* Clear status block in ram. */
7464 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7465
7466 /* Set status block DMA address */
7467 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7468 ((u64) tnapi->status_mapping >> 32));
7469 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7470 ((u64) tnapi->status_mapping & 0xffffffff));
7471
f77a6a8e
MC		 7472 if (tnapi->tx_ring) {
7473 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7474 (TG3_TX_RING_SIZE <<
7475 BDINFO_FLAGS_MAXLEN_SHIFT),
7476 NIC_SRAM_TX_BUFFER_DESC);
7477 txrcb += TG3_BDINFO_SIZE;
7478 }
7479
7480 if (tnapi->rx_rcb) {
7481 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7482 (TG3_RX_RCB_RING_SIZE(tp) <<
7483 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7484 rxrcb += TG3_BDINFO_SIZE;
7485 }
7486
7487 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7488
f77a6a8e
MC		 7489 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7490 u64 mapping = (u64)tnapi->status_mapping;
7491 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7492 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7493
7494 /* Clear status block in ram. */
7495 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7496
19cfaecc
MC		 7497 if (tnapi->tx_ring) {
7498 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7499 (TG3_TX_RING_SIZE <<
7500 BDINFO_FLAGS_MAXLEN_SHIFT),
7501 NIC_SRAM_TX_BUFFER_DESC);
7502 txrcb += TG3_BDINFO_SIZE;
7503 }
f77a6a8e
MC		 7504
7505 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7506 (TG3_RX_RCB_RING_SIZE(tp) <<
7507 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7508
7509 stblk += 8;
f77a6a8e
MC		 7510 rxrcb += TG3_BDINFO_SIZE;
7511 }
2d31ecaf
MC		 7512}
7513
1da177e4 7514/* tp->lock is held. */
8e7a22e3 7515static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7516{
7517 u32 val, rdmac_mode;
7518 int i, err, limit;
21f581a5 7519 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7520
7521 tg3_disable_ints(tp);
7522
7523 tg3_stop_fw(tp);
7524
7525 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7526
7527 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7528 tg3_abort_hw(tp, 1);
1da177e4
LT		 7529 }
7530
dd477003
MC		 7531 if (reset_phy &&
7532 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7533 tg3_phy_reset(tp);
7534
1da177e4
LT		 7535 err = tg3_chip_reset(tp);
7536 if (err)
7537 return err;
7538
7539 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7540
bcb37f6c 7541 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7542 val = tr32(TG3_CPMU_CTRL);
7543 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7544 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7545
7546 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7547 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7548 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7549 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7550
7551 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7552 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7553 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7554 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7555
7556 val = tr32(TG3_CPMU_HST_ACC);
7557 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7558 val |= CPMU_HST_ACC_MACCLK_6_25;
7559 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7560 }
7561
33466d93
MC		 7562 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7563 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7564 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7565 PCIE_PWR_MGMT_L1_THRESH_4MS;
7566 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7567
7568 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7569 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7570
7571 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7572
f40386c8
MC		 7573 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7574 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7575 }
7576
1da177e4
LT		 7577 /* This works around an issue with Athlon chipsets on
7578 * B3 tigon3 silicon. This bit has no effect on any
7579 * other revision. But do not set this on PCI Express
795d01c5 7580 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7581 */
795d01c5
MC		 7582 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7583 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7584 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7585 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7586 }
1da177e4
LT		 7587
7588 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7589 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7590 val = tr32(TG3PCI_PCISTATE);
7591 val |= PCISTATE_RETRY_SAME_DMA;
7592 tw32(TG3PCI_PCISTATE, val);
7593 }
7594
0d3031d9
MC		 7595 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7596 /* Allow reads and writes to the
7597 * APE register and memory space.
7598 */
7599 val = tr32(TG3PCI_PCISTATE);
7600 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7601 PCISTATE_ALLOW_APE_SHMEM_WR;
7602 tw32(TG3PCI_PCISTATE, val);
7603 }
7604
1da177e4
LT		 7605 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7606 /* Enable some hw fixes. */
7607 val = tr32(TG3PCI_MSI_DATA);
7608 val |= (1 << 26) | (1 << 28) | (1 << 29);
7609 tw32(TG3PCI_MSI_DATA, val);
7610 }
7611
7612 /* Descriptor ring init may make accesses to the
7613 * NIC SRAM area to setup the TX descriptors, so we
7614 * can only do this after the hardware has been
7615 * successfully reset.
7616 */
32d8c572
MC		 7617 err = tg3_init_rings(tp);
7618 if (err)
7619 return err;
1da177e4 7620
b703df6f
MC		 7621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7623 val = tr32(TG3PCI_DMA_RW_CTRL) &
7624 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7625 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7626 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7627 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7628 /* This value is determined during the probe time DMA
7629 * engine test, tg3_test_dma.
7630 */
7631 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7632 }
1da177e4
LT		 7633
7634 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7635 GRC_MODE_4X_NIC_SEND_RINGS |
7636 GRC_MODE_NO_TX_PHDR_CSUM |
7637 GRC_MODE_NO_RX_PHDR_CSUM);
7638 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7639
7640 /* Pseudo-header checksum is done by hardware logic and not
7641 * the offload processers, so make the chip do the pseudo-
7642 * header checksums on receive. For transmit it is more
7643 * convenient to do the pseudo-header checksum in software
7644 * as Linux does that on transmit for us in all cases.
7645 */
7646 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7647
7648 tw32(GRC_MODE,
7649 tp->grc_mode |
7650 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7651
7652 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7653 val = tr32(GRC_MISC_CFG);
7654 val &= ~0xff;
7655 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7656 tw32(GRC_MISC_CFG, val);
7657
7658 /* Initialize MBUF/DESC pool. */
cbf46853 7659 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7660 /* Do nothing. */
7661 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7662 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7664 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7665 else
7666 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7667 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7668 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7669 }
1da177e4
LT		 7670 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7671 int fw_len;
7672
077f849d 7673 fw_len = tp->fw_len;
1da177e4
LT		 7674 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7675 tw32(BUFMGR_MB_POOL_ADDR,
7676 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7677 tw32(BUFMGR_MB_POOL_SIZE,
7678 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7679 }
1da177e4 7680
0f893dc6 7681 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7682 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7683 tp->bufmgr_config.mbuf_read_dma_low_water);
7684 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7685 tp->bufmgr_config.mbuf_mac_rx_low_water);
7686 tw32(BUFMGR_MB_HIGH_WATER,
7687 tp->bufmgr_config.mbuf_high_water);
7688 } else {
7689 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7690 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7691 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7692 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7693 tw32(BUFMGR_MB_HIGH_WATER,
7694 tp->bufmgr_config.mbuf_high_water_jumbo);
7695 }
7696 tw32(BUFMGR_DMA_LOW_WATER,
7697 tp->bufmgr_config.dma_low_water);
7698 tw32(BUFMGR_DMA_HIGH_WATER,
7699 tp->bufmgr_config.dma_high_water);
7700
7701 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7702 for (i = 0; i < 2000; i++) {
7703 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7704 break;
7705 udelay(10);
7706 }
7707 if (i >= 2000) {
7708 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7709 tp->dev->name);
7710 return -ENODEV;
7711 }
7712
7713 /* Setup replenish threshold. */
f92905de
MC		 7714 val = tp->rx_pending / 8;
7715 if (val == 0)
7716 val = 1;
7717 else if (val > tp->rx_std_max_post)
7718 val = tp->rx_std_max_post;
b5d3772c
MC		 7719 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7720 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7721 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7722
7723 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7724 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7725 }
f92905de
MC		 7726
7727 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7728
7729 /* Initialize TG3_BDINFO's at:
7730 * RCVDBDI_STD_BD: standard eth size rx ring
7731 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7732 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7733 *
7734 * like so:
7735 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7736 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7737 * ring attribute flags
7738 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7739 *
7740 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7741 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7742 *
7743 * The size of each ring is fixed in the firmware, but the location is
7744 * configurable.
7745 */
7746 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7747 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7748 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7749 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7750 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7751 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7752 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7753
fdb72b38
MC		 7754 /* Disable the mini ring */
7755 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7756 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7757 BDINFO_FLAGS_DISABLED);
7758
fdb72b38
MC		 7759 /* Program the jumbo buffer descriptor ring control
7760 * blocks on those devices that have them.
7761 */
8f666b07 7762 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7763 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7764 /* Setup replenish threshold. */
7765 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7766
0f893dc6 7767 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7768 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7769 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7770 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7771 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7772 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7773 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7774 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7775 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7776 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7777 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7778 } else {
7779 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7780 BDINFO_FLAGS_DISABLED);
7781 }
7782
b703df6f
MC		 7783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7784 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7785 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7786 (RX_STD_MAX_SIZE << 2);
7787 else
7788 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7789 } else
7790 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7791
7792 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7793
411da640 7794 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7795 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7796
411da640 7797 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7798 tp->rx_jumbo_pending : 0;
66711e66 7799 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7800
b703df6f
MC		 7801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7803 tw32(STD_REPLENISH_LWM, 32);
7804 tw32(JMB_REPLENISH_LWM, 16);
7805 }
7806
2d31ecaf
MC		 7807 tg3_rings_reset(tp);
7808
1da177e4 7809 /* Initialize MAC address and backoff seed. */
986e0aeb 7810 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7811
7812 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7813 tw32(MAC_RX_MTU_SIZE,
7814 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7815
7816 /* The slot time is changed by tg3_setup_phy if we
7817 * run at gigabit with half duplex.
7818 */
7819 tw32(MAC_TX_LENGTHS,
7820 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7821 (6 << TX_LENGTHS_IPG_SHIFT) |
7822 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7823
7824 /* Receive rules. */
7825 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7826 tw32(RCVLPC_CONFIG, 0x0181);
7827
7828 /* Calculate RDMAC_MODE setting early, we need it to determine
7829 * the RCVLPC_STATE_ENABLE mask.
7830 */
7831 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7832 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7833 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7834 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7835 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7836
57e6983c 7837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7840 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7841 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7842 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7843
85e94ced
MC		 7844 /* If statement applies to 5705 and 5750 PCI devices only */
7845 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7846 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7847 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7848 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7850 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7851 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7852 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7853 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7854 }
7855 }
7856
85e94ced
MC		 7857 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7858 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7859
1da177e4 7860 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7861 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7862
e849cdc3
MC		 7863 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7866 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7867
7868 /* Receive/send statistics. */
1661394e
MC		 7869 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7870 val = tr32(RCVLPC_STATS_ENABLE);
7871 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7872 tw32(RCVLPC_STATS_ENABLE, val);
7873 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7874 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7875 val = tr32(RCVLPC_STATS_ENABLE);
7876 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7877 tw32(RCVLPC_STATS_ENABLE, val);
7878 } else {
7879 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7880 }
7881 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7882 tw32(SNDDATAI_STATSENAB, 0xffffff);
7883 tw32(SNDDATAI_STATSCTRL,
7884 (SNDDATAI_SCTRL_ENABLE |
7885 SNDDATAI_SCTRL_FASTUPD));
7886
7887 /* Setup host coalescing engine. */
7888 tw32(HOSTCC_MODE, 0);
7889 for (i = 0; i < 2000; i++) {
7890 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7891 break;
7892 udelay(10);
7893 }
7894
d244c892 7895 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7896
1da177e4
LT		 7897 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7898 /* Status/statistics block address. See tg3_timer,
7899 * the tg3_periodic_fetch_stats call there, and
7900 * tg3_get_stats to see how this works for 5705/5750 chips.
7901 */
1da177e4
LT		 7902 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7903 ((u64) tp->stats_mapping >> 32));
7904 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7905 ((u64) tp->stats_mapping & 0xffffffff));
7906 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7907
1da177e4 7908 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7909
7910 /* Clear statistics and status block memory areas */
7911 for (i = NIC_SRAM_STATS_BLK;
7912 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7913 i += sizeof(u32)) {
7914 tg3_write_mem(tp, i, 0);
7915 udelay(40);
7916 }
1da177e4
LT		 7917 }
7918
7919 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7920
7921 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7922 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7923 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7924 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7925
c94e3941
MC		 7926 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7927 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7928 /* reset to prevent losing 1st rx packet intermittently */
7929 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7930 udelay(10);
7931 }
7932
3bda1258
MC		 7933 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7934 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7935 else
7936 tp->mac_mode = 0;
7937 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7938 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7939 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7940 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7941 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7942 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7943 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7944 udelay(40);
7945
314fba34 7946 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7947 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7948 * register to preserve the GPIO settings for LOMs. The GPIOs,
7949 * whether used as inputs or outputs, are set by boot code after
7950 * reset.
7951 */
9d26e213 7952 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7953 u32 gpio_mask;
7954
9d26e213
MC		 7955 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7956 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7957 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7958
7959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7960 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7961 GRC_LCLCTRL_GPIO_OUTPUT3;
7962
af36e6b6
MC		 7963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7964 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7965
aaf84465 7966 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7967 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7968
7969 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7970 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7971 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7972 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7973 }
1da177e4
LT		 7974 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7975 udelay(100);
7976
baf8a94a
MC		 7977 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7978 val = tr32(MSGINT_MODE);
7979 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7980 tw32(MSGINT_MODE, val);
7981 }
7982
1da177e4
LT		 7983 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7984 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7985 udelay(40);
7986 }
7987
7988 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7989 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7990 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7991 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7992 WDMAC_MODE_LNGREAD_ENAB);
7993
85e94ced
MC		 7994 /* If statement applies to 5705 and 5750 PCI devices only */
7995 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7996 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7998 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7999 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8000 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8001 /* nothing */
8002 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8003 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8004 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8005 val |= WDMAC_MODE_RX_ACCEL;
8006 }
8007 }
8008
d9ab5ad1 8009 /* Enable host coalescing bug fix */
321d32a0 8010 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8011 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8012
788a035e
MC		 8013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8014 val |= WDMAC_MODE_BURST_ALL_DATA;
8015
1da177e4
LT		 8016 tw32_f(WDMAC_MODE, val);
8017 udelay(40);
8018
9974a356
MC		 8019 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8020 u16 pcix_cmd;
8021
8022 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8023 &pcix_cmd);
1da177e4 8024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8025 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8026 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8027 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8028 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8029 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8030 }
9974a356
MC		 8031 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8032 pcix_cmd);
1da177e4
LT		 8033 }
8034
8035 tw32_f(RDMAC_MODE, rdmac_mode);
8036 udelay(40);
8037
8038 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8039 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8040 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8041
8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8043 tw32(SNDDATAC_MODE,
8044 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8045 else
8046 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8047
1da177e4
LT		 8048 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8049 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8050 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8051 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8052 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8053 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8054 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8055 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8056 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8057 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8058 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8059
8060 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8061 err = tg3_load_5701_a0_firmware_fix(tp);
8062 if (err)
8063 return err;
8064 }
8065
1da177e4
LT		 8066 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8067 err = tg3_load_tso_firmware(tp);
8068 if (err)
8069 return err;
8070 }
1da177e4
LT		 8071
8072 tp->tx_mode = TX_MODE_ENABLE;
8073 tw32_f(MAC_TX_MODE, tp->tx_mode);
8074 udelay(100);
8075
baf8a94a
MC		 8076 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8077 u32 reg = MAC_RSS_INDIR_TBL_0;
8078 u8 *ent = (u8 *)&val;
8079
8080 /* Setup the indirection table */
8081 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8082 int idx = i % sizeof(val);
8083
8084 ent[idx] = i % (tp->irq_cnt - 1);
8085 if (idx == sizeof(val) - 1) {
8086 tw32(reg, val);
8087 reg += 4;
8088 }
8089 }
8090
8091 /* Setup the "secret" hash key. */
8092 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8093 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8094 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8095 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8096 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8097 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8098 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8099 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8100 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8101 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8102 }
8103
1da177e4 8104 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8105 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8106 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8107
baf8a94a
MC		 8108 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8109 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8110 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8111 RX_MODE_RSS_IPV6_HASH_EN |
8112 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8113 RX_MODE_RSS_IPV4_HASH_EN |
8114 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8115
1da177e4
LT		 8116 tw32_f(MAC_RX_MODE, tp->rx_mode);
8117 udelay(10);
8118
1da177e4
LT		 8119 tw32(MAC_LED_CTRL, tp->led_ctrl);
8120
8121 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8122 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8123 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8124 udelay(10);
8125 }
8126 tw32_f(MAC_RX_MODE, tp->rx_mode);
8127 udelay(10);
8128
8129 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8130 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8131 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8132 /* Set drive transmission level to 1.2V */
8133 /* only if the signal pre-emphasis bit is not set */
8134 val = tr32(MAC_SERDES_CFG);
8135 val &= 0xfffff000;
8136 val |= 0x880;
8137 tw32(MAC_SERDES_CFG, val);
8138 }
8139 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8140 tw32(MAC_SERDES_CFG, 0x616000);
8141 }
8142
8143 /* Prevent chip from dropping frames when flow control
8144 * is enabled.
8145 */
8146 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8147
8148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8149 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8150 /* Use hardware link auto-negotiation */
8151 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8152 }
8153
d4d2c558
MC		 8154 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8155 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8156 u32 tmp;
8157
8158 tmp = tr32(SERDES_RX_CTRL);
8159 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8160 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8161 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8162 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8163 }
8164
dd477003
MC		 8165 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8166 if (tp->link_config.phy_is_low_power) {
8167 tp->link_config.phy_is_low_power = 0;
8168 tp->link_config.speed = tp->link_config.orig_speed;
8169 tp->link_config.duplex = tp->link_config.orig_duplex;
8170 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8171 }
1da177e4 8172
dd477003
MC		 8173 err = tg3_setup_phy(tp, 0);
8174 if (err)
8175 return err;
1da177e4 8176
dd477003 8177 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8178 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8179 u32 tmp;
8180
8181 /* Clear CRC stats. */
8182 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8183 tg3_writephy(tp, MII_TG3_TEST1,
8184 tmp | MII_TG3_TEST1_CRC_EN);
8185 tg3_readphy(tp, 0x14, &tmp);
8186 }
1da177e4
LT		 8187 }
8188 }
8189
8190 __tg3_set_rx_mode(tp->dev);
8191
8192 /* Initialize receive rules. */
8193 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8194 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8195 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8196 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8197
4cf78e4f 8198 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8199 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8200 limit = 8;
8201 else
8202 limit = 16;
8203 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8204 limit -= 4;
8205 switch (limit) {
8206 case 16:
8207 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8208 case 15:
8209 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8210 case 14:
8211 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8212 case 13:
8213 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8214 case 12:
8215 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8216 case 11:
8217 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8218 case 10:
8219 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8220 case 9:
8221 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8222 case 8:
8223 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8224 case 7:
8225 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8226 case 6:
8227 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8228 case 5:
8229 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8230 case 4:
8231 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8232 case 3:
8233 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8234 case 2:
8235 case 1:
8236
8237 default:
8238 break;
855e1111 8239 }
1da177e4 8240
9ce768ea
MC		 8241 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8242 /* Write our heartbeat update interval to APE. */
8243 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8244 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8245
1da177e4
LT		 8246 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8247
1da177e4
LT		 8248 return 0;
8249}
8250
8251/* Called at device open time to get the chip ready for
8252 * packet processing. Invoked with tp->lock held.
8253 */
8e7a22e3 8254static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8255{
1da177e4
LT		 8256 tg3_switch_clocks(tp);
8257
8258 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8259
2f751b67 8260 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8261}
8262
8263#define TG3_STAT_ADD32(PSTAT, REG) \
8264do { u32 __val = tr32(REG); \
8265 (PSTAT)->low += __val; \
8266 if ((PSTAT)->low < __val) \
8267 (PSTAT)->high += 1; \
8268} while (0)
8269
8270static void tg3_periodic_fetch_stats(struct tg3 *tp)
8271{
8272 struct tg3_hw_stats *sp = tp->hw_stats;
8273
8274 if (!netif_carrier_ok(tp->dev))
8275 return;
8276
8277 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8278 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8279 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8280 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8281 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8282 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8283 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8284 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8285 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8286 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8287 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8288 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8289 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8290
8291 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8292 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8293 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8294 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8295 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8296 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8297 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8298 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8299 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8300 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8301 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8302 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8303 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8304 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8305
8306 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8307 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8308 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8309}
8310
8311static void tg3_timer(unsigned long __opaque)
8312{
8313 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8314
f475f163
MC		 8315 if (tp->irq_sync)
8316 goto restart_timer;
8317
f47c11ee 8318 spin_lock(&tp->lock);
1da177e4 8319
fac9b83e
DM		 8320 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8321 /* All of this garbage is because when using non-tagged
8322 * IRQ status the mailbox/status_block protocol the chip
8323 * uses with the cpu is race prone.
8324 */
898a56f8 8325 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8326 tw32(GRC_LOCAL_CTRL,
8327 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8328 } else {
8329 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8330 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8331 }
1da177e4 8332
fac9b83e
DM		 8333 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8334 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8335 spin_unlock(&tp->lock);
fac9b83e
DM		 8336 schedule_work(&tp->reset_task);
8337 return;
8338 }
1da177e4
LT		 8339 }
8340
1da177e4
LT		 8341 /* This part only runs once per second. */
8342 if (!--tp->timer_counter) {
fac9b83e
DM		 8343 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8344 tg3_periodic_fetch_stats(tp);
8345
1da177e4
LT		 8346 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8347 u32 mac_stat;
8348 int phy_event;
8349
8350 mac_stat = tr32(MAC_STATUS);
8351
8352 phy_event = 0;
8353 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8354 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8355 phy_event = 1;
8356 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8357 phy_event = 1;
8358
8359 if (phy_event)
8360 tg3_setup_phy(tp, 0);
8361 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8362 u32 mac_stat = tr32(MAC_STATUS);
8363 int need_setup = 0;
8364
8365 if (netif_carrier_ok(tp->dev) &&
8366 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8367 need_setup = 1;
8368 }
8369 if (! netif_carrier_ok(tp->dev) &&
8370 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8371 MAC_STATUS_SIGNAL_DET))) {
8372 need_setup = 1;
8373 }
8374 if (need_setup) {
3d3ebe74
MC		 8375 if (!tp->serdes_counter) {
8376 tw32_f(MAC_MODE,
8377 (tp->mac_mode &
8378 ~MAC_MODE_PORT_MODE_MASK));
8379 udelay(40);
8380 tw32_f(MAC_MODE, tp->mac_mode);
8381 udelay(40);
8382 }
1da177e4
LT		 8383 tg3_setup_phy(tp, 0);
8384 }
747e8f8b
MC		 8385 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8386 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8387
8388 tp->timer_counter = tp->timer_multiplier;
8389 }
8390
130b8e4d
MC		 8391 /* Heartbeat is only sent once every 2 seconds.
8392 *
8393 * The heartbeat is to tell the ASF firmware that the host
8394 * driver is still alive. In the event that the OS crashes,
8395 * ASF needs to reset the hardware to free up the FIFO space
8396 * that may be filled with rx packets destined for the host.
8397 * If the FIFO is full, ASF will no longer function properly.
8398 *
8399 * Unintended resets have been reported on real time kernels
8400 * where the timer doesn't run on time. Netpoll will also have
8401 * same problem.
8402 *
8403 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8404 * to check the ring condition when the heartbeat is expiring
8405 * before doing the reset. This will prevent most unintended
8406 * resets.
8407 */
1da177e4 8408 if (!--tp->asf_counter) {
bc7959b2
MC		 8409 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8410 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8411 tg3_wait_for_event_ack(tp);
8412
bbadf503 8413 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8414 FWCMD_NICDRV_ALIVE3);
bbadf503 8415 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8416 /* 5 seconds timeout */
bbadf503 8417 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8418
8419 tg3_generate_fw_event(tp);
1da177e4
LT		 8420 }
8421 tp->asf_counter = tp->asf_multiplier;
8422 }
8423
f47c11ee 8424 spin_unlock(&tp->lock);
1da177e4 8425
f475f163 8426restart_timer:
1da177e4
LT		 8427 tp->timer.expires = jiffies + tp->timer_offset;
8428 add_timer(&tp->timer);
8429}
8430
4f125f42 8431static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8432{
7d12e780 8433 irq_handler_t fn;
fcfa0a32 8434 unsigned long flags;
4f125f42
MC		 8435 char *name;
8436 struct tg3_napi *tnapi = &tp->napi[irq_num];
8437
8438 if (tp->irq_cnt == 1)
8439 name = tp->dev->name;
8440 else {
8441 name = &tnapi->irq_lbl[0];
8442 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8443 name[IFNAMSIZ-1] = 0;
8444 }
fcfa0a32 8445
679563f4 8446 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8447 fn = tg3_msi;
8448 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8449 fn = tg3_msi_1shot;
1fb9df5d 8450 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8451 } else {
8452 fn = tg3_interrupt;
8453 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8454 fn = tg3_interrupt_tagged;
1fb9df5d 8455 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8456 }
4f125f42
MC		 8457
8458 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8459}
8460
7938109f
MC		 8461static int tg3_test_interrupt(struct tg3 *tp)
8462{
09943a18 8463 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8464 struct net_device *dev = tp->dev;
b16250e3 8465 int err, i, intr_ok = 0;
f6eb9b1f 8466 u32 val;
7938109f 8467
d4bc3927
MC		 8468 if (!netif_running(dev))
8469 return -ENODEV;
8470
7938109f
MC		 8471 tg3_disable_ints(tp);
8472
4f125f42 8473 free_irq(tnapi->irq_vec, tnapi);
7938109f 8474
f6eb9b1f
MC		 8475 /*
8476 * Turn off MSI one shot mode. Otherwise this test has no
8477 * observable way to know whether the interrupt was delivered.
8478 */
b703df6f
MC		 8479 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8480 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8481 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8482 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8483 tw32(MSGINT_MODE, val);
8484 }
8485
4f125f42 8486 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8487 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8488 if (err)
8489 return err;
8490
898a56f8 8491 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8492 tg3_enable_ints(tp);
8493
8494 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8495 tnapi->coal_now);
7938109f
MC		 8496
8497 for (i = 0; i < 5; i++) {
b16250e3
MC		 8498 u32 int_mbox, misc_host_ctrl;
8499
898a56f8 8500 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8501 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8502
8503 if ((int_mbox != 0) ||
8504 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8505 intr_ok = 1;
7938109f 8506 break;
b16250e3
MC		 8507 }
8508
7938109f
MC		 8509 msleep(10);
8510 }
8511
8512 tg3_disable_ints(tp);
8513
4f125f42 8514 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8515
4f125f42 8516 err = tg3_request_irq(tp, 0);
7938109f
MC		 8517
8518 if (err)
8519 return err;
8520
f6eb9b1f
MC		 8521 if (intr_ok) {
8522 /* Reenable MSI one shot mode. */
b703df6f
MC		 8523 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8525 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8526 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8527 tw32(MSGINT_MODE, val);
8528 }
7938109f 8529 return 0;
f6eb9b1f 8530 }
7938109f
MC		 8531
8532 return -EIO;
8533}
8534
8535/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8536 * successfully restored
8537 */
8538static int tg3_test_msi(struct tg3 *tp)
8539{
7938109f
MC		 8540 int err;
8541 u16 pci_cmd;
8542
8543 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8544 return 0;
8545
8546 /* Turn off SERR reporting in case MSI terminates with Master
8547 * Abort.
8548 */
8549 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8550 pci_write_config_word(tp->pdev, PCI_COMMAND,
8551 pci_cmd & ~PCI_COMMAND_SERR);
8552
8553 err = tg3_test_interrupt(tp);
8554
8555 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8556
8557 if (!err)
8558 return 0;
8559
8560 /* other failures */
8561 if (err != -EIO)
8562 return err;
8563
8564 /* MSI test failed, go back to INTx mode */
8565 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8566 "switching to INTx mode. Please report this failure to "
8567 "the PCI maintainer and include system chipset information.\n",
8568 tp->dev->name);
8569
4f125f42 8570 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8571
7938109f
MC		 8572 pci_disable_msi(tp->pdev);
8573
8574 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8575
4f125f42 8576 err = tg3_request_irq(tp, 0);
7938109f
MC		 8577 if (err)
8578 return err;
8579
8580 /* Need to reset the chip because the MSI cycle may have terminated
8581 * with Master Abort.
8582 */
f47c11ee 8583 tg3_full_lock(tp, 1);
7938109f 8584
944d980e 8585 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8586 err = tg3_init_hw(tp, 1);
7938109f 8587
f47c11ee 8588 tg3_full_unlock(tp);
7938109f
MC		 8589
8590 if (err)
4f125f42 8591 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8592
8593 return err;
8594}
8595
9e9fd12d
MC		 8596static int tg3_request_firmware(struct tg3 *tp)
8597{
8598 const __be32 *fw_data;
8599
8600 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8601 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8602 tp->dev->name, tp->fw_needed);
8603 return -ENOENT;
8604 }
8605
8606 fw_data = (void *)tp->fw->data;
8607
8608 /* Firmware blob starts with version numbers, followed by
8609 * start address and _full_ length including BSS sections
8610 * (which must be longer than the actual data, of course
8611 */
8612
8613 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8614 if (tp->fw_len < (tp->fw->size - 12)) {
8615 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8616 tp->dev->name, tp->fw_len, tp->fw_needed);
8617 release_firmware(tp->fw);
8618 tp->fw = NULL;
8619 return -EINVAL;
8620 }
8621
8622 /* We no longer need firmware; we have it. */
8623 tp->fw_needed = NULL;
8624 return 0;
8625}
8626
679563f4
MC		 8627static bool tg3_enable_msix(struct tg3 *tp)
8628{
8629 int i, rc, cpus = num_online_cpus();
8630 struct msix_entry msix_ent[tp->irq_max];
8631
8632 if (cpus == 1)
8633 /* Just fallback to the simpler MSI mode. */
8634 return false;
8635
8636 /*
8637 * We want as many rx rings enabled as there are cpus.
8638 * The first MSIX vector only deals with link interrupts, etc,
8639 * so we add one to the number of vectors we are requesting.
8640 */
8641 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8642
8643 for (i = 0; i < tp->irq_max; i++) {
8644 msix_ent[i].entry = i;
8645 msix_ent[i].vector = 0;
8646 }
8647
8648 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8649 if (rc != 0) {
8650 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8651 return false;
8652 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8653 return false;
8654 printk(KERN_NOTICE
8655 "%s: Requested %d MSI-X vectors, received %d\n",
8656 tp->dev->name, tp->irq_cnt, rc);
8657 tp->irq_cnt = rc;
8658 }
8659
baf8a94a
MC		 8660 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8661
679563f4
MC		 8662 for (i = 0; i < tp->irq_max; i++)
8663 tp->napi[i].irq_vec = msix_ent[i].vector;
8664
19cfaecc
MC		 8665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8666 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8667 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8668 } else
8669 tp->dev->real_num_tx_queues = 1;
fe5f5787 8670
679563f4
MC		 8671 return true;
8672}
8673
07b0173c
MC		 8674static void tg3_ints_init(struct tg3 *tp)
8675{
679563f4
MC		 8676 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8677 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8678 /* All MSI supporting chips should support tagged
8679 * status. Assert that this is the case.
8680 */
679563f4
MC		 8681 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8682 "Not using MSI.\n", tp->dev->name);
8683 goto defcfg;
07b0173c 8684 }
4f125f42 8685
679563f4
MC		 8686 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8687 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8688 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8689 pci_enable_msi(tp->pdev) == 0)
8690 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8691
8692 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8693 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8694 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8695 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8696 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8697 }
8698defcfg:
8699 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8700 tp->irq_cnt = 1;
8701 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8702 tp->dev->real_num_tx_queues = 1;
679563f4 8703 }
07b0173c
MC		 8704}
8705
8706static void tg3_ints_fini(struct tg3 *tp)
8707{
679563f4
MC		 8708 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8709 pci_disable_msix(tp->pdev);
8710 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8711 pci_disable_msi(tp->pdev);
8712 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8713 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8714}
8715
1da177e4
LT		 8716static int tg3_open(struct net_device *dev)
8717{
8718 struct tg3 *tp = netdev_priv(dev);
4f125f42 8719 int i, err;
1da177e4 8720
9e9fd12d
MC		 8721 if (tp->fw_needed) {
8722 err = tg3_request_firmware(tp);
8723 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8724 if (err)
8725 return err;
8726 } else if (err) {
8727 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8728 tp->dev->name);
8729 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8730 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8731 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8732 tp->dev->name);
8733 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8734 }
8735 }
8736
c49a1561
MC		 8737 netif_carrier_off(tp->dev);
8738
bc1c7567 8739 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8740 if (err)
bc1c7567 8741 return err;
2f751b67
MC		 8742
8743 tg3_full_lock(tp, 0);
bc1c7567 8744
1da177e4
LT		 8745 tg3_disable_ints(tp);
8746 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8747
f47c11ee 8748 tg3_full_unlock(tp);
1da177e4 8749
679563f4
MC		 8750 /*
8751 * Setup interrupts first so we know how
8752 * many NAPI resources to allocate
8753 */
8754 tg3_ints_init(tp);
8755
1da177e4
LT		 8756 /* The placement of this call is tied
8757 * to the setup and use of Host TX descriptors.
8758 */
8759 err = tg3_alloc_consistent(tp);
8760 if (err)
679563f4 8761 goto err_out1;
88b06bc2 8762
fed97810 8763 tg3_napi_enable(tp);
1da177e4 8764
4f125f42
MC		 8765 for (i = 0; i < tp->irq_cnt; i++) {
8766 struct tg3_napi *tnapi = &tp->napi[i];
8767 err = tg3_request_irq(tp, i);
8768 if (err) {
8769 for (i--; i >= 0; i--)
8770 free_irq(tnapi->irq_vec, tnapi);
8771 break;
8772 }
8773 }
1da177e4 8774
07b0173c 8775 if (err)
679563f4 8776 goto err_out2;
bea3348e 8777
f47c11ee 8778 tg3_full_lock(tp, 0);
1da177e4 8779
8e7a22e3 8780 err = tg3_init_hw(tp, 1);
1da177e4 8781 if (err) {
944d980e 8782 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8783 tg3_free_rings(tp);
8784 } else {
fac9b83e
DM		 8785 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8786 tp->timer_offset = HZ;
8787 else
8788 tp->timer_offset = HZ / 10;
8789
8790 BUG_ON(tp->timer_offset > HZ);
8791 tp->timer_counter = tp->timer_multiplier =
8792 (HZ / tp->timer_offset);
8793 tp->asf_counter = tp->asf_multiplier =
28fbef78 8794 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8795
8796 init_timer(&tp->timer);
8797 tp->timer.expires = jiffies + tp->timer_offset;
8798 tp->timer.data = (unsigned long) tp;
8799 tp->timer.function = tg3_timer;
1da177e4
LT		 8800 }
8801
f47c11ee 8802 tg3_full_unlock(tp);
1da177e4 8803
07b0173c 8804 if (err)
679563f4 8805 goto err_out3;
1da177e4 8806
7938109f
MC		 8807 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8808 err = tg3_test_msi(tp);
fac9b83e 8809
7938109f 8810 if (err) {
f47c11ee 8811 tg3_full_lock(tp, 0);
944d980e 8812 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8813 tg3_free_rings(tp);
f47c11ee 8814 tg3_full_unlock(tp);
7938109f 8815
679563f4 8816 goto err_out2;
7938109f 8817 }
fcfa0a32 8818
f6eb9b1f 8819 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8820 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8821 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8822 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8823 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8824
f6eb9b1f
MC		 8825 tw32(PCIE_TRANSACTION_CFG,
8826 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8827 }
7938109f
MC		 8828 }
8829
b02fd9e3
MC		 8830 tg3_phy_start(tp);
8831
f47c11ee 8832 tg3_full_lock(tp, 0);
1da177e4 8833
7938109f
MC		 8834 add_timer(&tp->timer);
8835 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8836 tg3_enable_ints(tp);
8837
f47c11ee 8838 tg3_full_unlock(tp);
1da177e4 8839
fe5f5787 8840 netif_tx_start_all_queues(dev);
1da177e4
LT		 8841
8842 return 0;
07b0173c 8843
679563f4 8844err_out3:
4f125f42
MC		 8845 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8846 struct tg3_napi *tnapi = &tp->napi[i];
8847 free_irq(tnapi->irq_vec, tnapi);
8848 }
07b0173c 8849
679563f4 8850err_out2:
fed97810 8851 tg3_napi_disable(tp);
07b0173c 8852 tg3_free_consistent(tp);
679563f4
MC		 8853
8854err_out1:
8855 tg3_ints_fini(tp);
07b0173c 8856 return err;
1da177e4
LT		 8857}
8858
8859#if 0
8860/*static*/ void tg3_dump_state(struct tg3 *tp)
8861{
8862 u32 val32, val32_2, val32_3, val32_4, val32_5;
8863 u16 val16;
8864 int i;
898a56f8 8865 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8866
8867 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8868 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8869 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8870 val16, val32);
8871
8872 /* MAC block */
8873 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8874 tr32(MAC_MODE), tr32(MAC_STATUS));
8875 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8876 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8877 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8878 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8879 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8880 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8881
8882 /* Send data initiator control block */
8883 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8884 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8885 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8886 tr32(SNDDATAI_STATSCTRL));
8887
8888 /* Send data completion control block */
8889 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8890
8891 /* Send BD ring selector block */
8892 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8893 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8894
8895 /* Send BD initiator control block */
8896 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8897 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8898
8899 /* Send BD completion control block */
8900 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8901
8902 /* Receive list placement control block */
8903 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8904 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8905 printk(" RCVLPC_STATSCTRL[%08x]\n",
8906 tr32(RCVLPC_STATSCTRL));
8907
8908 /* Receive data and receive BD initiator control block */
8909 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8910 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8911
8912 /* Receive data completion control block */
8913 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8914 tr32(RCVDCC_MODE));
8915
8916 /* Receive BD initiator control block */
8917 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8918 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8919
8920 /* Receive BD completion control block */
8921 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8922 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8923
8924 /* Receive list selector control block */
8925 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8926 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8927
8928 /* Mbuf cluster free block */
8929 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8930 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8931
8932 /* Host coalescing control block */
8933 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8934 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8935 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8936 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8937 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8938 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8939 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8940 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8941 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8942 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8943 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8944 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8945
8946 /* Memory arbiter control block */
8947 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8948 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8949
8950 /* Buffer manager control block */
8951 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8952 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8953 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8954 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8955 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8956 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8957 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8958 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8959
8960 /* Read DMA control block */
8961 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8962 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8963
8964 /* Write DMA control block */
8965 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8966 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8967
8968 /* DMA completion block */
8969 printk("DEBUG: DMAC_MODE[%08x]\n",
8970 tr32(DMAC_MODE));
8971
8972 /* GRC block */
8973 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8974 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8975 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8976 tr32(GRC_LOCAL_CTRL));
8977
8978 /* TG3_BDINFOs */
8979 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8980 tr32(RCVDBDI_JUMBO_BD + 0x0),
8981 tr32(RCVDBDI_JUMBO_BD + 0x4),
8982 tr32(RCVDBDI_JUMBO_BD + 0x8),
8983 tr32(RCVDBDI_JUMBO_BD + 0xc));
8984 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8985 tr32(RCVDBDI_STD_BD + 0x0),
8986 tr32(RCVDBDI_STD_BD + 0x4),
8987 tr32(RCVDBDI_STD_BD + 0x8),
8988 tr32(RCVDBDI_STD_BD + 0xc));
8989 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8990 tr32(RCVDBDI_MINI_BD + 0x0),
8991 tr32(RCVDBDI_MINI_BD + 0x4),
8992 tr32(RCVDBDI_MINI_BD + 0x8),
8993 tr32(RCVDBDI_MINI_BD + 0xc));
8994
8995 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8996 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8997 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8998 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8999 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9000 val32, val32_2, val32_3, val32_4);
9001
9002 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9003 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9004 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9005 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9006 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9007 val32, val32_2, val32_3, val32_4);
9008
9009 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9010 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9011 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9012 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9013 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9014 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9015 val32, val32_2, val32_3, val32_4, val32_5);
9016
9017 /* SW status block */
898a56f8
MC		 9018 printk(KERN_DEBUG
9019 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9020 sblk->status,
9021 sblk->status_tag,
9022 sblk->rx_jumbo_consumer,
9023 sblk->rx_consumer,
9024 sblk->rx_mini_consumer,
9025 sblk->idx[0].rx_producer,
9026 sblk->idx[0].tx_consumer);
1da177e4
LT		 9027
9028 /* SW statistics block */
9029 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9030 ((u32 *)tp->hw_stats)[0],
9031 ((u32 *)tp->hw_stats)[1],
9032 ((u32 *)tp->hw_stats)[2],
9033 ((u32 *)tp->hw_stats)[3]);
9034
9035 /* Mailboxes */
9036 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9037 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9038 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9039 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9040 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9041
9042 /* NIC side send descriptors. */
9043 for (i = 0; i < 6; i++) {
9044 unsigned long txd;
9045
9046 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9047 + (i * sizeof(struct tg3_tx_buffer_desc));
9048 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9049 i,
9050 readl(txd + 0x0), readl(txd + 0x4),
9051 readl(txd + 0x8), readl(txd + 0xc));
9052 }
9053
9054 /* NIC side RX descriptors. */
9055 for (i = 0; i < 6; i++) {
9056 unsigned long rxd;
9057
9058 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9059 + (i * sizeof(struct tg3_rx_buffer_desc));
9060 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9061 i,
9062 readl(rxd + 0x0), readl(rxd + 0x4),
9063 readl(rxd + 0x8), readl(rxd + 0xc));
9064 rxd += (4 * sizeof(u32));
9065 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9066 i,
9067 readl(rxd + 0x0), readl(rxd + 0x4),
9068 readl(rxd + 0x8), readl(rxd + 0xc));
9069 }
9070
9071 for (i = 0; i < 6; i++) {
9072 unsigned long rxd;
9073
9074 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9075 + (i * sizeof(struct tg3_rx_buffer_desc));
9076 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9077 i,
9078 readl(rxd + 0x0), readl(rxd + 0x4),
9079 readl(rxd + 0x8), readl(rxd + 0xc));
9080 rxd += (4 * sizeof(u32));
9081 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9082 i,
9083 readl(rxd + 0x0), readl(rxd + 0x4),
9084 readl(rxd + 0x8), readl(rxd + 0xc));
9085 }
9086}
9087#endif
9088
9089static struct net_device_stats *tg3_get_stats(struct net_device *);
9090static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9091
9092static int tg3_close(struct net_device *dev)
9093{
4f125f42 9094 int i;
1da177e4
LT		 9095 struct tg3 *tp = netdev_priv(dev);
9096
fed97810 9097 tg3_napi_disable(tp);
28e53bdd 9098 cancel_work_sync(&tp->reset_task);
7faa006f 9099
fe5f5787 9100 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9101
9102 del_timer_sync(&tp->timer);
9103
24bb4fb6
MC		 9104 tg3_phy_stop(tp);
9105
f47c11ee 9106 tg3_full_lock(tp, 1);
1da177e4
LT		 9107#if 0
9108 tg3_dump_state(tp);
9109#endif
9110
9111 tg3_disable_ints(tp);
9112
944d980e 9113 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9114 tg3_free_rings(tp);
5cf64b8a 9115 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9116
f47c11ee 9117 tg3_full_unlock(tp);
1da177e4 9118
4f125f42
MC		 9119 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9120 struct tg3_napi *tnapi = &tp->napi[i];
9121 free_irq(tnapi->irq_vec, tnapi);
9122 }
07b0173c
MC		 9123
9124 tg3_ints_fini(tp);
1da177e4
LT		 9125
9126 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9127 sizeof(tp->net_stats_prev));
9128 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9129 sizeof(tp->estats_prev));
9130
9131 tg3_free_consistent(tp);
9132
bc1c7567
MC		 9133 tg3_set_power_state(tp, PCI_D3hot);
9134
9135 netif_carrier_off(tp->dev);
9136
1da177e4
LT		 9137 return 0;
9138}
9139
9140static inline unsigned long get_stat64(tg3_stat64_t *val)
9141{
9142 unsigned long ret;
9143
9144#if (BITS_PER_LONG == 32)
9145 ret = val->low;
9146#else
9147 ret = ((u64)val->high << 32) | ((u64)val->low);
9148#endif
9149 return ret;
9150}
9151
816f8b86
SB		 9152static inline u64 get_estat64(tg3_stat64_t *val)
9153{
9154 return ((u64)val->high << 32) | ((u64)val->low);
9155}
9156
1da177e4
LT		 9157static unsigned long calc_crc_errors(struct tg3 *tp)
9158{
9159 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9160
9161 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9162 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9164 u32 val;
9165
f47c11ee 9166 spin_lock_bh(&tp->lock);
569a5df8
MC		 9167 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9168 tg3_writephy(tp, MII_TG3_TEST1,
9169 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9170 tg3_readphy(tp, 0x14, &val);
9171 } else
9172 val = 0;
f47c11ee 9173 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9174
9175 tp->phy_crc_errors += val;
9176
9177 return tp->phy_crc_errors;
9178 }
9179
9180 return get_stat64(&hw_stats->rx_fcs_errors);
9181}
9182
9183#define ESTAT_ADD(member) \
9184 estats->member = old_estats->member + \
816f8b86 9185 get_estat64(&hw_stats->member)
1da177e4
LT		 9186
9187static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9188{
9189 struct tg3_ethtool_stats *estats = &tp->estats;
9190 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9191 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9192
9193 if (!hw_stats)
9194 return old_estats;
9195
9196 ESTAT_ADD(rx_octets);
9197 ESTAT_ADD(rx_fragments);
9198 ESTAT_ADD(rx_ucast_packets);
9199 ESTAT_ADD(rx_mcast_packets);
9200 ESTAT_ADD(rx_bcast_packets);
9201 ESTAT_ADD(rx_fcs_errors);
9202 ESTAT_ADD(rx_align_errors);
9203 ESTAT_ADD(rx_xon_pause_rcvd);
9204 ESTAT_ADD(rx_xoff_pause_rcvd);
9205 ESTAT_ADD(rx_mac_ctrl_rcvd);
9206 ESTAT_ADD(rx_xoff_entered);
9207 ESTAT_ADD(rx_frame_too_long_errors);
9208 ESTAT_ADD(rx_jabbers);
9209 ESTAT_ADD(rx_undersize_packets);
9210 ESTAT_ADD(rx_in_length_errors);
9211 ESTAT_ADD(rx_out_length_errors);
9212 ESTAT_ADD(rx_64_or_less_octet_packets);
9213 ESTAT_ADD(rx_65_to_127_octet_packets);
9214 ESTAT_ADD(rx_128_to_255_octet_packets);
9215 ESTAT_ADD(rx_256_to_511_octet_packets);
9216 ESTAT_ADD(rx_512_to_1023_octet_packets);
9217 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9218 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9219 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9220 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9221 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9222
9223 ESTAT_ADD(tx_octets);
9224 ESTAT_ADD(tx_collisions);
9225 ESTAT_ADD(tx_xon_sent);
9226 ESTAT_ADD(tx_xoff_sent);
9227 ESTAT_ADD(tx_flow_control);
9228 ESTAT_ADD(tx_mac_errors);
9229 ESTAT_ADD(tx_single_collisions);
9230 ESTAT_ADD(tx_mult_collisions);
9231 ESTAT_ADD(tx_deferred);
9232 ESTAT_ADD(tx_excessive_collisions);
9233 ESTAT_ADD(tx_late_collisions);
9234 ESTAT_ADD(tx_collide_2times);
9235 ESTAT_ADD(tx_collide_3times);
9236 ESTAT_ADD(tx_collide_4times);
9237 ESTAT_ADD(tx_collide_5times);
9238 ESTAT_ADD(tx_collide_6times);
9239 ESTAT_ADD(tx_collide_7times);
9240 ESTAT_ADD(tx_collide_8times);
9241 ESTAT_ADD(tx_collide_9times);
9242 ESTAT_ADD(tx_collide_10times);
9243 ESTAT_ADD(tx_collide_11times);
9244 ESTAT_ADD(tx_collide_12times);
9245 ESTAT_ADD(tx_collide_13times);
9246 ESTAT_ADD(tx_collide_14times);
9247 ESTAT_ADD(tx_collide_15times);
9248 ESTAT_ADD(tx_ucast_packets);
9249 ESTAT_ADD(tx_mcast_packets);
9250 ESTAT_ADD(tx_bcast_packets);
9251 ESTAT_ADD(tx_carrier_sense_errors);
9252 ESTAT_ADD(tx_discards);
9253 ESTAT_ADD(tx_errors);
9254
9255 ESTAT_ADD(dma_writeq_full);
9256 ESTAT_ADD(dma_write_prioq_full);
9257 ESTAT_ADD(rxbds_empty);
9258 ESTAT_ADD(rx_discards);
9259 ESTAT_ADD(rx_errors);
9260 ESTAT_ADD(rx_threshold_hit);
9261
9262 ESTAT_ADD(dma_readq_full);
9263 ESTAT_ADD(dma_read_prioq_full);
9264 ESTAT_ADD(tx_comp_queue_full);
9265
9266 ESTAT_ADD(ring_set_send_prod_index);
9267 ESTAT_ADD(ring_status_update);
9268 ESTAT_ADD(nic_irqs);
9269 ESTAT_ADD(nic_avoided_irqs);
9270 ESTAT_ADD(nic_tx_threshold_hit);
9271
9272 return estats;
9273}
9274
9275static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9276{
9277 struct tg3 *tp = netdev_priv(dev);
9278 struct net_device_stats *stats = &tp->net_stats;
9279 struct net_device_stats *old_stats = &tp->net_stats_prev;
9280 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9281
9282 if (!hw_stats)
9283 return old_stats;
9284
9285 stats->rx_packets = old_stats->rx_packets +
9286 get_stat64(&hw_stats->rx_ucast_packets) +
9287 get_stat64(&hw_stats->rx_mcast_packets) +
9288 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9289
1da177e4
LT		 9290 stats->tx_packets = old_stats->tx_packets +
9291 get_stat64(&hw_stats->tx_ucast_packets) +
9292 get_stat64(&hw_stats->tx_mcast_packets) +
9293 get_stat64(&hw_stats->tx_bcast_packets);
9294
9295 stats->rx_bytes = old_stats->rx_bytes +
9296 get_stat64(&hw_stats->rx_octets);
9297 stats->tx_bytes = old_stats->tx_bytes +
9298 get_stat64(&hw_stats->tx_octets);
9299
9300 stats->rx_errors = old_stats->rx_errors +
4f63b877 9301 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9302 stats->tx_errors = old_stats->tx_errors +
9303 get_stat64(&hw_stats->tx_errors) +
9304 get_stat64(&hw_stats->tx_mac_errors) +
9305 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9306 get_stat64(&hw_stats->tx_discards);
9307
9308 stats->multicast = old_stats->multicast +
9309 get_stat64(&hw_stats->rx_mcast_packets);
9310 stats->collisions = old_stats->collisions +
9311 get_stat64(&hw_stats->tx_collisions);
9312
9313 stats->rx_length_errors = old_stats->rx_length_errors +
9314 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9315 get_stat64(&hw_stats->rx_undersize_packets);
9316
9317 stats->rx_over_errors = old_stats->rx_over_errors +
9318 get_stat64(&hw_stats->rxbds_empty);
9319 stats->rx_frame_errors = old_stats->rx_frame_errors +
9320 get_stat64(&hw_stats->rx_align_errors);
9321 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9322 get_stat64(&hw_stats->tx_discards);
9323 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9324 get_stat64(&hw_stats->tx_carrier_sense_errors);
9325
9326 stats->rx_crc_errors = old_stats->rx_crc_errors +
9327 calc_crc_errors(tp);
9328
4f63b877
JL		 9329 stats->rx_missed_errors = old_stats->rx_missed_errors +
9330 get_stat64(&hw_stats->rx_discards);
9331
1da177e4
LT		 9332 return stats;
9333}
9334
9335static inline u32 calc_crc(unsigned char *buf, int len)
9336{
9337 u32 reg;
9338 u32 tmp;
9339 int j, k;
9340
9341 reg = 0xffffffff;
9342
9343 for (j = 0; j < len; j++) {
9344 reg ^= buf[j];
9345
9346 for (k = 0; k < 8; k++) {
9347 tmp = reg & 0x01;
9348
9349 reg >>= 1;
9350
9351 if (tmp) {
9352 reg ^= 0xedb88320;
9353 }
9354 }
9355 }
9356
9357 return ~reg;
9358}
9359
9360static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9361{
9362 /* accept or reject all multicast frames */
9363 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9364 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9365 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9366 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9367}
9368
9369static void __tg3_set_rx_mode(struct net_device *dev)
9370{
9371 struct tg3 *tp = netdev_priv(dev);
9372 u32 rx_mode;
9373
9374 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9375 RX_MODE_KEEP_VLAN_TAG);
9376
9377 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9378 * flag clear.
9379 */
9380#if TG3_VLAN_TAG_USED
9381 if (!tp->vlgrp &&
9382 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9383 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9384#else
9385 /* By definition, VLAN is disabled always in this
9386 * case.
9387 */
9388 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9389 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9390#endif
9391
9392 if (dev->flags & IFF_PROMISC) {
9393 /* Promiscuous mode. */
9394 rx_mode |= RX_MODE_PROMISC;
9395 } else if (dev->flags & IFF_ALLMULTI) {
9396 /* Accept all multicast. */
9397 tg3_set_multi (tp, 1);
9398 } else if (dev->mc_count < 1) {
9399 /* Reject all multicast. */
9400 tg3_set_multi (tp, 0);
9401 } else {
9402 /* Accept one or more multicast(s). */
9403 struct dev_mc_list *mclist;
9404 unsigned int i;
9405 u32 mc_filter[4] = { 0, };
9406 u32 regidx;
9407 u32 bit;
9408 u32 crc;
9409
9410 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9411 i++, mclist = mclist->next) {
9412
9413 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9414 bit = ~crc & 0x7f;
9415 regidx = (bit & 0x60) >> 5;
9416 bit &= 0x1f;
9417 mc_filter[regidx] |= (1 << bit);
9418 }
9419
9420 tw32(MAC_HASH_REG_0, mc_filter[0]);
9421 tw32(MAC_HASH_REG_1, mc_filter[1]);
9422 tw32(MAC_HASH_REG_2, mc_filter[2]);
9423 tw32(MAC_HASH_REG_3, mc_filter[3]);
9424 }
9425
9426 if (rx_mode != tp->rx_mode) {
9427 tp->rx_mode = rx_mode;
9428 tw32_f(MAC_RX_MODE, rx_mode);
9429 udelay(10);
9430 }
9431}
9432
9433static void tg3_set_rx_mode(struct net_device *dev)
9434{
9435 struct tg3 *tp = netdev_priv(dev);
9436
e75f7c90
MC		 9437 if (!netif_running(dev))
9438 return;
9439
f47c11ee 9440 tg3_full_lock(tp, 0);
1da177e4 9441 __tg3_set_rx_mode(dev);
f47c11ee 9442 tg3_full_unlock(tp);
1da177e4
LT		 9443}
9444
9445#define TG3_REGDUMP_LEN (32 * 1024)
9446
9447static int tg3_get_regs_len(struct net_device *dev)
9448{
9449 return TG3_REGDUMP_LEN;
9450}
9451
9452static void tg3_get_regs(struct net_device *dev,
9453 struct ethtool_regs *regs, void *_p)
9454{
9455 u32 *p = _p;
9456 struct tg3 *tp = netdev_priv(dev);
9457 u8 *orig_p = _p;
9458 int i;
9459
9460 regs->version = 0;
9461
9462 memset(p, 0, TG3_REGDUMP_LEN);
9463
bc1c7567
MC		 9464 if (tp->link_config.phy_is_low_power)
9465 return;
9466
f47c11ee 9467 tg3_full_lock(tp, 0);
1da177e4
LT		 9468
9469#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9470#define GET_REG32_LOOP(base,len) \
9471do { p = (u32 *)(orig_p + (base)); \
9472 for (i = 0; i < len; i += 4) \
9473 __GET_REG32((base) + i); \
9474} while (0)
9475#define GET_REG32_1(reg) \
9476do { p = (u32 *)(orig_p + (reg)); \
9477 __GET_REG32((reg)); \
9478} while (0)
9479
9480 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9481 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9482 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9483 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9484 GET_REG32_1(SNDDATAC_MODE);
9485 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9486 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9487 GET_REG32_1(SNDBDC_MODE);
9488 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9489 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9490 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9491 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9492 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9493 GET_REG32_1(RCVDCC_MODE);
9494 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9495 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9496 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9497 GET_REG32_1(MBFREE_MODE);
9498 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9499 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9500 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9501 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9502 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9503 GET_REG32_1(RX_CPU_MODE);
9504 GET_REG32_1(RX_CPU_STATE);
9505 GET_REG32_1(RX_CPU_PGMCTR);
9506 GET_REG32_1(RX_CPU_HWBKPT);
9507 GET_REG32_1(TX_CPU_MODE);
9508 GET_REG32_1(TX_CPU_STATE);
9509 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9510 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9511 GET_REG32_LOOP(FTQ_RESET, 0x120);
9512 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9513 GET_REG32_1(DMAC_MODE);
9514 GET_REG32_LOOP(GRC_MODE, 0x4c);
9515 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9516 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9517
9518#undef __GET_REG32
9519#undef GET_REG32_LOOP
9520#undef GET_REG32_1
9521
f47c11ee 9522 tg3_full_unlock(tp);
1da177e4
LT		 9523}
9524
9525static int tg3_get_eeprom_len(struct net_device *dev)
9526{
9527 struct tg3 *tp = netdev_priv(dev);
9528
9529 return tp->nvram_size;
9530}
9531
1da177e4
LT		 9532static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9533{
9534 struct tg3 *tp = netdev_priv(dev);
9535 int ret;
9536 u8 *pd;
b9fc7dc5 9537 u32 i, offset, len, b_offset, b_count;
a9dc529d 9538 __be32 val;
1da177e4 9539
df259d8c
MC		 9540 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9541 return -EINVAL;
9542
bc1c7567
MC		 9543 if (tp->link_config.phy_is_low_power)
9544 return -EAGAIN;
9545
1da177e4
LT		 9546 offset = eeprom->offset;
9547 len = eeprom->len;
9548 eeprom->len = 0;
9549
9550 eeprom->magic = TG3_EEPROM_MAGIC;
9551
9552 if (offset & 3) {
9553 /* adjustments to start on required 4 byte boundary */
9554 b_offset = offset & 3;
9555 b_count = 4 - b_offset;
9556 if (b_count > len) {
9557 /* i.e. offset=1 len=2 */
9558 b_count = len;
9559 }
a9dc529d 9560 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9561 if (ret)
9562 return ret;
1da177e4
LT		 9563 memcpy(data, ((char*)&val) + b_offset, b_count);
9564 len -= b_count;
9565 offset += b_count;
9566 eeprom->len += b_count;
9567 }
9568
9569 /* read bytes upto the last 4 byte boundary */
9570 pd = &data[eeprom->len];
9571 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9572 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9573 if (ret) {
9574 eeprom->len += i;
9575 return ret;
9576 }
1da177e4
LT		 9577 memcpy(pd + i, &val, 4);
9578 }
9579 eeprom->len += i;
9580
9581 if (len & 3) {
9582 /* read last bytes not ending on 4 byte boundary */
9583 pd = &data[eeprom->len];
9584 b_count = len & 3;
9585 b_offset = offset + len - b_count;
a9dc529d 9586 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9587 if (ret)
9588 return ret;
b9fc7dc5 9589 memcpy(pd, &val, b_count);
1da177e4
LT		 9590 eeprom->len += b_count;
9591 }
9592 return 0;
9593}
9594
6aa20a22 9595static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9596
9597static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9598{
9599 struct tg3 *tp = netdev_priv(dev);
9600 int ret;
b9fc7dc5 9601 u32 offset, len, b_offset, odd_len;
1da177e4 9602 u8 *buf;
a9dc529d 9603 __be32 start, end;
1da177e4 9604
bc1c7567
MC		 9605 if (tp->link_config.phy_is_low_power)
9606 return -EAGAIN;
9607
df259d8c
MC		 9608 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9609 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9610 return -EINVAL;
9611
9612 offset = eeprom->offset;
9613 len = eeprom->len;
9614
9615 if ((b_offset = (offset & 3))) {
9616 /* adjustments to start on required 4 byte boundary */
a9dc529d 9617 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9618 if (ret)
9619 return ret;
1da177e4
LT		 9620 len += b_offset;
9621 offset &= ~3;
1c8594b4
MC		 9622 if (len < 4)
9623 len = 4;
1da177e4
LT		 9624 }
9625
9626 odd_len = 0;
1c8594b4 9627 if (len & 3) {
1da177e4
LT		 9628 /* adjustments to end on required 4 byte boundary */
9629 odd_len = 1;
9630 len = (len + 3) & ~3;
a9dc529d 9631 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9632 if (ret)
9633 return ret;
1da177e4
LT		 9634 }
9635
9636 buf = data;
9637 if (b_offset || odd_len) {
9638 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9639 if (!buf)
1da177e4
LT		 9640 return -ENOMEM;
9641 if (b_offset)
9642 memcpy(buf, &start, 4);
9643 if (odd_len)
9644 memcpy(buf+len-4, &end, 4);
9645 memcpy(buf + b_offset, data, eeprom->len);
9646 }
9647
9648 ret = tg3_nvram_write_block(tp, offset, len, buf);
9649
9650 if (buf != data)
9651 kfree(buf);
9652
9653 return ret;
9654}
9655
9656static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9657{
b02fd9e3
MC		 9658 struct tg3 *tp = netdev_priv(dev);
9659
9660 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9661 struct phy_device *phydev;
b02fd9e3
MC		 9662 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9663 return -EAGAIN;
3f0e3ad7
MC		 9664 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9665 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9666 }
6aa20a22 9667
1da177e4
LT		 9668 cmd->supported = (SUPPORTED_Autoneg);
9669
9670 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9671 cmd->supported |= (SUPPORTED_1000baseT_Half |
9672 SUPPORTED_1000baseT_Full);
9673
ef348144 9674 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9675 cmd->supported |= (SUPPORTED_100baseT_Half |
9676 SUPPORTED_100baseT_Full |
9677 SUPPORTED_10baseT_Half |
9678 SUPPORTED_10baseT_Full |
3bebab59 9679 SUPPORTED_TP);
ef348144
KK		 9680 cmd->port = PORT_TP;
9681 } else {
1da177e4 9682 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9683 cmd->port = PORT_FIBRE;
9684 }
6aa20a22 9685
1da177e4
LT		 9686 cmd->advertising = tp->link_config.advertising;
9687 if (netif_running(dev)) {
9688 cmd->speed = tp->link_config.active_speed;
9689 cmd->duplex = tp->link_config.active_duplex;
9690 }
882e9793 9691 cmd->phy_address = tp->phy_addr;
7e5856bd 9692 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9693 cmd->autoneg = tp->link_config.autoneg;
9694 cmd->maxtxpkt = 0;
9695 cmd->maxrxpkt = 0;
9696 return 0;
9697}
6aa20a22 9698
1da177e4
LT		 9699static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9700{
9701 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9702
b02fd9e3 9703 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9704 struct phy_device *phydev;
b02fd9e3
MC		 9705 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9706 return -EAGAIN;
3f0e3ad7
MC		 9707 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9708 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9709 }
9710
7e5856bd
MC		 9711 if (cmd->autoneg != AUTONEG_ENABLE &&
9712 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9713 return -EINVAL;
7e5856bd
MC		 9714
9715 if (cmd->autoneg == AUTONEG_DISABLE &&
9716 cmd->duplex != DUPLEX_FULL &&
9717 cmd->duplex != DUPLEX_HALF)
37ff238d 9718 return -EINVAL;
1da177e4 9719
7e5856bd
MC		 9720 if (cmd->autoneg == AUTONEG_ENABLE) {
9721 u32 mask = ADVERTISED_Autoneg |
9722 ADVERTISED_Pause |
9723 ADVERTISED_Asym_Pause;
9724
9725 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9726 mask |= ADVERTISED_1000baseT_Half |
9727 ADVERTISED_1000baseT_Full;
9728
9729 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9730 mask |= ADVERTISED_100baseT_Half |
9731 ADVERTISED_100baseT_Full |
9732 ADVERTISED_10baseT_Half |
9733 ADVERTISED_10baseT_Full |
9734 ADVERTISED_TP;
9735 else
9736 mask |= ADVERTISED_FIBRE;
9737
9738 if (cmd->advertising & ~mask)
9739 return -EINVAL;
9740
9741 mask &= (ADVERTISED_1000baseT_Half |
9742 ADVERTISED_1000baseT_Full |
9743 ADVERTISED_100baseT_Half |
9744 ADVERTISED_100baseT_Full |
9745 ADVERTISED_10baseT_Half |
9746 ADVERTISED_10baseT_Full);
9747
9748 cmd->advertising &= mask;
9749 } else {
9750 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9751 if (cmd->speed != SPEED_1000)
9752 return -EINVAL;
9753
9754 if (cmd->duplex != DUPLEX_FULL)
9755 return -EINVAL;
9756 } else {
9757 if (cmd->speed != SPEED_100 &&
9758 cmd->speed != SPEED_10)
9759 return -EINVAL;
9760 }
9761 }
9762
f47c11ee 9763 tg3_full_lock(tp, 0);
1da177e4
LT		 9764
9765 tp->link_config.autoneg = cmd->autoneg;
9766 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9767 tp->link_config.advertising = (cmd->advertising |
9768 ADVERTISED_Autoneg);
1da177e4
LT		 9769 tp->link_config.speed = SPEED_INVALID;
9770 tp->link_config.duplex = DUPLEX_INVALID;
9771 } else {
9772 tp->link_config.advertising = 0;
9773 tp->link_config.speed = cmd->speed;
9774 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9775 }
6aa20a22 9776
24fcad6b
MC		 9777 tp->link_config.orig_speed = tp->link_config.speed;
9778 tp->link_config.orig_duplex = tp->link_config.duplex;
9779 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9780
1da177e4
LT		 9781 if (netif_running(dev))
9782 tg3_setup_phy(tp, 1);
9783
f47c11ee 9784 tg3_full_unlock(tp);
6aa20a22 9785
1da177e4
LT		 9786 return 0;
9787}
6aa20a22 9788
1da177e4
LT		 9789static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9790{
9791 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9792
1da177e4
LT		 9793 strcpy(info->driver, DRV_MODULE_NAME);
9794 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9795 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9796 strcpy(info->bus_info, pci_name(tp->pdev));
9797}
6aa20a22 9798
1da177e4
LT		 9799static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9800{
9801 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9802
12dac075
RW		 9803 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9804 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9805 wol->supported = WAKE_MAGIC;
9806 else
9807 wol->supported = 0;
1da177e4 9808 wol->wolopts = 0;
05ac4cb7
MC		 9809 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9810 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9811 wol->wolopts = WAKE_MAGIC;
9812 memset(&wol->sopass, 0, sizeof(wol->sopass));
9813}
6aa20a22 9814
1da177e4
LT		 9815static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9816{
9817 struct tg3 *tp = netdev_priv(dev);
12dac075 9818 struct device *dp = &tp->pdev->dev;
6aa20a22 9819
1da177e4
LT		 9820 if (wol->wolopts & ~WAKE_MAGIC)
9821 return -EINVAL;
9822 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9823 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9824 return -EINVAL;
6aa20a22 9825
f47c11ee 9826 spin_lock_bh(&tp->lock);
12dac075 9827 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9828 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9829 device_set_wakeup_enable(dp, true);
9830 } else {
1da177e4 9831 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9832 device_set_wakeup_enable(dp, false);
9833 }
f47c11ee 9834 spin_unlock_bh(&tp->lock);
6aa20a22 9835
1da177e4
LT		 9836 return 0;
9837}
6aa20a22 9838
1da177e4
LT		 9839static u32 tg3_get_msglevel(struct net_device *dev)
9840{
9841 struct tg3 *tp = netdev_priv(dev);
9842 return tp->msg_enable;
9843}
6aa20a22 9844
1da177e4
LT		 9845static void tg3_set_msglevel(struct net_device *dev, u32 value)
9846{
9847 struct tg3 *tp = netdev_priv(dev);
9848 tp->msg_enable = value;
9849}
6aa20a22 9850
1da177e4
LT		 9851static int tg3_set_tso(struct net_device *dev, u32 value)
9852{
9853 struct tg3 *tp = netdev_priv(dev);
9854
9855 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9856 if (value)
9857 return -EINVAL;
9858 return 0;
9859 }
027455ad 9860 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9861 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9862 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9863 if (value) {
b0026624 9864 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9865 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9867 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9868 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9871 dev->features |= NETIF_F_TSO_ECN;
9872 } else
9873 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9874 }
1da177e4
LT		 9875 return ethtool_op_set_tso(dev, value);
9876}
6aa20a22 9877
1da177e4
LT		 9878static int tg3_nway_reset(struct net_device *dev)
9879{
9880 struct tg3 *tp = netdev_priv(dev);
1da177e4 9881 int r;
6aa20a22 9882
1da177e4
LT		 9883 if (!netif_running(dev))
9884 return -EAGAIN;
9885
c94e3941
MC		 9886 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9887 return -EINVAL;
9888
b02fd9e3
MC		 9889 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9890 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9891 return -EAGAIN;
3f0e3ad7 9892 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9893 } else {
9894 u32 bmcr;
9895
9896 spin_lock_bh(&tp->lock);
9897 r = -EINVAL;
9898 tg3_readphy(tp, MII_BMCR, &bmcr);
9899 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9900 ((bmcr & BMCR_ANENABLE) ||
9901 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9902 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9903 BMCR_ANENABLE);
9904 r = 0;
9905 }
9906 spin_unlock_bh(&tp->lock);
1da177e4 9907 }
6aa20a22 9908
1da177e4
LT		 9909 return r;
9910}
6aa20a22 9911
1da177e4
LT		 9912static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9913{
9914 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9915
1da177e4
LT		 9916 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9917 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9918 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9919 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9920 else
9921 ering->rx_jumbo_max_pending = 0;
9922
9923 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9924
9925 ering->rx_pending = tp->rx_pending;
9926 ering->rx_mini_pending = 0;
4f81c32b
MC		 9927 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9928 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9929 else
9930 ering->rx_jumbo_pending = 0;
9931
f3f3f27e 9932 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9933}
6aa20a22 9934
1da177e4
LT		 9935static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9936{
9937 struct tg3 *tp = netdev_priv(dev);
646c9edd 9938 int i, irq_sync = 0, err = 0;
6aa20a22 9939
1da177e4
LT		 9940 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9941 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9942 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9943 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9944 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9945 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9946 return -EINVAL;
6aa20a22 9947
bbe832c0 9948 if (netif_running(dev)) {
b02fd9e3 9949 tg3_phy_stop(tp);
1da177e4 9950 tg3_netif_stop(tp);
bbe832c0
MC		 9951 irq_sync = 1;
9952 }
1da177e4 9953
bbe832c0 9954 tg3_full_lock(tp, irq_sync);
6aa20a22 9955
1da177e4
LT		 9956 tp->rx_pending = ering->rx_pending;
9957
9958 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9959 tp->rx_pending > 63)
9960 tp->rx_pending = 63;
9961 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9962
9963 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9964 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9965
9966 if (netif_running(dev)) {
944d980e 9967 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9968 err = tg3_restart_hw(tp, 1);
9969 if (!err)
9970 tg3_netif_start(tp);
1da177e4
LT		 9971 }
9972
f47c11ee 9973 tg3_full_unlock(tp);
6aa20a22 9974
b02fd9e3
MC		 9975 if (irq_sync && !err)
9976 tg3_phy_start(tp);
9977
b9ec6c1b 9978 return err;
1da177e4 9979}
6aa20a22 9980
1da177e4
LT		 9981static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9982{
9983 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9984
1da177e4 9985 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9986
e18ce346 9987 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9988 epause->rx_pause = 1;
9989 else
9990 epause->rx_pause = 0;
9991
e18ce346 9992 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9993 epause->tx_pause = 1;
9994 else
9995 epause->tx_pause = 0;
1da177e4 9996}
6aa20a22 9997
1da177e4
LT		 9998static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9999{
10000 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10001 int err = 0;
6aa20a22 10002
b02fd9e3
MC		 10003 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10004 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10005 return -EAGAIN;
1da177e4 10006
b02fd9e3
MC		 10007 if (epause->autoneg) {
10008 u32 newadv;
10009 struct phy_device *phydev;
f47c11ee 10010
3f0e3ad7 10011 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 10012
b02fd9e3
MC		 10013 if (epause->rx_pause) {
10014 if (epause->tx_pause)
10015 newadv = ADVERTISED_Pause;
10016 else
10017 newadv = ADVERTISED_Pause |
10018 ADVERTISED_Asym_Pause;
10019 } else if (epause->tx_pause) {
10020 newadv = ADVERTISED_Asym_Pause;
10021 } else
10022 newadv = 0;
10023
10024 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10025 u32 oldadv = phydev->advertising &
10026 (ADVERTISED_Pause |
10027 ADVERTISED_Asym_Pause);
10028 if (oldadv != newadv) {
10029 phydev->advertising &=
10030 ~(ADVERTISED_Pause |
10031 ADVERTISED_Asym_Pause);
10032 phydev->advertising |= newadv;
10033 err = phy_start_aneg(phydev);
10034 }
10035 } else {
10036 tp->link_config.advertising &=
10037 ~(ADVERTISED_Pause |
10038 ADVERTISED_Asym_Pause);
10039 tp->link_config.advertising |= newadv;
10040 }
10041 } else {
10042 if (epause->rx_pause)
e18ce346 10043 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10044 else
e18ce346 10045 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10046
b02fd9e3 10047 if (epause->tx_pause)
e18ce346 10048 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10049 else
e18ce346 10050 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10051
10052 if (netif_running(dev))
10053 tg3_setup_flow_control(tp, 0, 0);
10054 }
10055 } else {
10056 int irq_sync = 0;
10057
10058 if (netif_running(dev)) {
10059 tg3_netif_stop(tp);
10060 irq_sync = 1;
10061 }
10062
10063 tg3_full_lock(tp, irq_sync);
10064
10065 if (epause->autoneg)
10066 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10067 else
10068 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10069 if (epause->rx_pause)
e18ce346 10070 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10071 else
e18ce346 10072 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10073 if (epause->tx_pause)
e18ce346 10074 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10075 else
e18ce346 10076 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10077
10078 if (netif_running(dev)) {
10079 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10080 err = tg3_restart_hw(tp, 1);
10081 if (!err)
10082 tg3_netif_start(tp);
10083 }
10084
10085 tg3_full_unlock(tp);
10086 }
6aa20a22 10087
b9ec6c1b 10088 return err;
1da177e4 10089}
6aa20a22 10090
1da177e4
LT		 10091static u32 tg3_get_rx_csum(struct net_device *dev)
10092{
10093 struct tg3 *tp = netdev_priv(dev);
10094 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10095}
6aa20a22 10096
1da177e4
LT		 10097static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10098{
10099 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10100
1da177e4
LT		 10101 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10102 if (data != 0)
10103 return -EINVAL;
10104 return 0;
10105 }
6aa20a22 10106
f47c11ee 10107 spin_lock_bh(&tp->lock);
1da177e4
LT		 10108 if (data)
10109 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10110 else
10111 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10112 spin_unlock_bh(&tp->lock);
6aa20a22 10113
1da177e4
LT		 10114 return 0;
10115}
6aa20a22 10116
1da177e4
LT		 10117static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10118{
10119 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10120
1da177e4
LT		 10121 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10122 if (data != 0)
10123 return -EINVAL;
10124 return 0;
10125 }
6aa20a22 10126
321d32a0 10127 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10128 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10129 else
9c27dbdf 10130 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10131
10132 return 0;
10133}
10134
b9f2c044 10135static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10136{
b9f2c044
JG		 10137 switch (sset) {
10138 case ETH_SS_TEST:
10139 return TG3_NUM_TEST;
10140 case ETH_SS_STATS:
10141 return TG3_NUM_STATS;
10142 default:
10143 return -EOPNOTSUPP;
10144 }
4cafd3f5
MC		 10145}
10146
1da177e4
LT		 10147static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10148{
10149 switch (stringset) {
10150 case ETH_SS_STATS:
10151 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10152 break;
4cafd3f5
MC		 10153 case ETH_SS_TEST:
10154 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10155 break;
1da177e4
LT		 10156 default:
10157 WARN_ON(1); /* we need a WARN() */
10158 break;
10159 }
10160}
10161
4009a93d
MC		 10162static int tg3_phys_id(struct net_device *dev, u32 data)
10163{
10164 struct tg3 *tp = netdev_priv(dev);
10165 int i;
10166
10167 if (!netif_running(tp->dev))
10168 return -EAGAIN;
10169
10170 if (data == 0)
759afc31 10171 data = UINT_MAX / 2;
4009a93d
MC		 10172
10173 for (i = 0; i < (data * 2); i++) {
10174 if ((i % 2) == 0)
10175 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10176 LED_CTRL_1000MBPS_ON |
10177 LED_CTRL_100MBPS_ON |
10178 LED_CTRL_10MBPS_ON |
10179 LED_CTRL_TRAFFIC_OVERRIDE |
10180 LED_CTRL_TRAFFIC_BLINK |
10181 LED_CTRL_TRAFFIC_LED);
6aa20a22 10182
4009a93d
MC		 10183 else
10184 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10185 LED_CTRL_TRAFFIC_OVERRIDE);
10186
10187 if (msleep_interruptible(500))
10188 break;
10189 }
10190 tw32(MAC_LED_CTRL, tp->led_ctrl);
10191 return 0;
10192}
10193
1da177e4
LT		 10194static void tg3_get_ethtool_stats (struct net_device *dev,
10195 struct ethtool_stats *estats, u64 *tmp_stats)
10196{
10197 struct tg3 *tp = netdev_priv(dev);
10198 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10199}
10200
566f86ad 10201#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10202#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10203#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10204#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10205#define NVRAM_SELFBOOT_HW_SIZE 0x20
10206#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10207
10208static int tg3_test_nvram(struct tg3 *tp)
10209{
b9fc7dc5 10210 u32 csum, magic;
a9dc529d 10211 __be32 *buf;
ab0049b4 10212 int i, j, k, err = 0, size;
566f86ad 10213
df259d8c
MC		 10214 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10215 return 0;
10216
e4f34110 10217 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10218 return -EIO;
10219
1b27777a
MC		 10220 if (magic == TG3_EEPROM_MAGIC)
10221 size = NVRAM_TEST_SIZE;
b16250e3 10222 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10223 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10224 TG3_EEPROM_SB_FORMAT_1) {
10225 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10226 case TG3_EEPROM_SB_REVISION_0:
10227 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10228 break;
10229 case TG3_EEPROM_SB_REVISION_2:
10230 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10231 break;
10232 case TG3_EEPROM_SB_REVISION_3:
10233 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10234 break;
10235 default:
10236 return 0;
10237 }
10238 } else
1b27777a 10239 return 0;
b16250e3
MC		 10240 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10241 size = NVRAM_SELFBOOT_HW_SIZE;
10242 else
1b27777a
MC		 10243 return -EIO;
10244
10245 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10246 if (buf == NULL)
10247 return -ENOMEM;
10248
1b27777a
MC		 10249 err = -EIO;
10250 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10251 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10252 if (err)
566f86ad 10253 break;
566f86ad 10254 }
1b27777a 10255 if (i < size)
566f86ad
MC		 10256 goto out;
10257
1b27777a 10258 /* Selfboot format */
a9dc529d 10259 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10260 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10261 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10262 u8 *buf8 = (u8 *) buf, csum8 = 0;
10263
b9fc7dc5 10264 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10265 TG3_EEPROM_SB_REVISION_2) {
10266 /* For rev 2, the csum doesn't include the MBA. */
10267 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10268 csum8 += buf8[i];
10269 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10270 csum8 += buf8[i];
10271 } else {
10272 for (i = 0; i < size; i++)
10273 csum8 += buf8[i];
10274 }
1b27777a 10275
ad96b485
AB		 10276 if (csum8 == 0) {
10277 err = 0;
10278 goto out;
10279 }
10280
10281 err = -EIO;
10282 goto out;
1b27777a 10283 }
566f86ad 10284
b9fc7dc5 10285 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10286 TG3_EEPROM_MAGIC_HW) {
10287 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10288 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10289 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10290
10291 /* Separate the parity bits and the data bytes. */
10292 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10293 if ((i == 0) || (i == 8)) {
10294 int l;
10295 u8 msk;
10296
10297 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10298 parity[k++] = buf8[i] & msk;
10299 i++;
10300 }
10301 else if (i == 16) {
10302 int l;
10303 u8 msk;
10304
10305 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10306 parity[k++] = buf8[i] & msk;
10307 i++;
10308
10309 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10310 parity[k++] = buf8[i] & msk;
10311 i++;
10312 }
10313 data[j++] = buf8[i];
10314 }
10315
10316 err = -EIO;
10317 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10318 u8 hw8 = hweight8(data[i]);
10319
10320 if ((hw8 & 0x1) && parity[i])
10321 goto out;
10322 else if (!(hw8 & 0x1) && !parity[i])
10323 goto out;
10324 }
10325 err = 0;
10326 goto out;
10327 }
10328
566f86ad
MC		 10329 /* Bootstrap checksum at offset 0x10 */
10330 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10331 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10332 goto out;
10333
10334 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10335 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10336 if (csum != be32_to_cpu(buf[0xfc/4]))
10337 goto out;
566f86ad
MC		 10338
10339 err = 0;
10340
10341out:
10342 kfree(buf);
10343 return err;
10344}
10345
ca43007a
MC		 10346#define TG3_SERDES_TIMEOUT_SEC 2
10347#define TG3_COPPER_TIMEOUT_SEC 6
10348
10349static int tg3_test_link(struct tg3 *tp)
10350{
10351 int i, max;
10352
10353 if (!netif_running(tp->dev))
10354 return -ENODEV;
10355
4c987487 10356 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10357 max = TG3_SERDES_TIMEOUT_SEC;
10358 else
10359 max = TG3_COPPER_TIMEOUT_SEC;
10360
10361 for (i = 0; i < max; i++) {
10362 if (netif_carrier_ok(tp->dev))
10363 return 0;
10364
10365 if (msleep_interruptible(1000))
10366 break;
10367 }
10368
10369 return -EIO;
10370}
10371
a71116d1 10372/* Only test the commonly used registers */
30ca3e37 10373static int tg3_test_registers(struct tg3 *tp)
a71116d1 10374{
b16250e3 10375 int i, is_5705, is_5750;
a71116d1
MC		 10376 u32 offset, read_mask, write_mask, val, save_val, read_val;
10377 static struct {
10378 u16 offset;
10379 u16 flags;
10380#define TG3_FL_5705 0x1
10381#define TG3_FL_NOT_5705 0x2
10382#define TG3_FL_NOT_5788 0x4
b16250e3 10383#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10384 u32 read_mask;
10385 u32 write_mask;
10386 } reg_tbl[] = {
10387 /* MAC Control Registers */
10388 { MAC_MODE, TG3_FL_NOT_5705,
10389 0x00000000, 0x00ef6f8c },
10390 { MAC_MODE, TG3_FL_5705,
10391 0x00000000, 0x01ef6b8c },
10392 { MAC_STATUS, TG3_FL_NOT_5705,
10393 0x03800107, 0x00000000 },
10394 { MAC_STATUS, TG3_FL_5705,
10395 0x03800100, 0x00000000 },
10396 { MAC_ADDR_0_HIGH, 0x0000,
10397 0x00000000, 0x0000ffff },
10398 { MAC_ADDR_0_LOW, 0x0000,
10399 0x00000000, 0xffffffff },
10400 { MAC_RX_MTU_SIZE, 0x0000,
10401 0x00000000, 0x0000ffff },
10402 { MAC_TX_MODE, 0x0000,
10403 0x00000000, 0x00000070 },
10404 { MAC_TX_LENGTHS, 0x0000,
10405 0x00000000, 0x00003fff },
10406 { MAC_RX_MODE, TG3_FL_NOT_5705,
10407 0x00000000, 0x000007fc },
10408 { MAC_RX_MODE, TG3_FL_5705,
10409 0x00000000, 0x000007dc },
10410 { MAC_HASH_REG_0, 0x0000,
10411 0x00000000, 0xffffffff },
10412 { MAC_HASH_REG_1, 0x0000,
10413 0x00000000, 0xffffffff },
10414 { MAC_HASH_REG_2, 0x0000,
10415 0x00000000, 0xffffffff },
10416 { MAC_HASH_REG_3, 0x0000,
10417 0x00000000, 0xffffffff },
10418
10419 /* Receive Data and Receive BD Initiator Control Registers. */
10420 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10421 0x00000000, 0xffffffff },
10422 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10423 0x00000000, 0xffffffff },
10424 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10425 0x00000000, 0x00000003 },
10426 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10427 0x00000000, 0xffffffff },
10428 { RCVDBDI_STD_BD+0, 0x0000,
10429 0x00000000, 0xffffffff },
10430 { RCVDBDI_STD_BD+4, 0x0000,
10431 0x00000000, 0xffffffff },
10432 { RCVDBDI_STD_BD+8, 0x0000,
10433 0x00000000, 0xffff0002 },
10434 { RCVDBDI_STD_BD+0xc, 0x0000,
10435 0x00000000, 0xffffffff },
6aa20a22 10436
a71116d1
MC		 10437 /* Receive BD Initiator Control Registers. */
10438 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10439 0x00000000, 0xffffffff },
10440 { RCVBDI_STD_THRESH, TG3_FL_5705,
10441 0x00000000, 0x000003ff },
10442 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10443 0x00000000, 0xffffffff },
6aa20a22 10444
a71116d1
MC		 10445 /* Host Coalescing Control Registers. */
10446 { HOSTCC_MODE, TG3_FL_NOT_5705,
10447 0x00000000, 0x00000004 },
10448 { HOSTCC_MODE, TG3_FL_5705,
10449 0x00000000, 0x000000f6 },
10450 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10451 0x00000000, 0xffffffff },
10452 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10453 0x00000000, 0x000003ff },
10454 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10455 0x00000000, 0xffffffff },
10456 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10457 0x00000000, 0x000003ff },
10458 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10459 0x00000000, 0xffffffff },
10460 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10461 0x00000000, 0x000000ff },
10462 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10463 0x00000000, 0xffffffff },
10464 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10465 0x00000000, 0x000000ff },
10466 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10467 0x00000000, 0xffffffff },
10468 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10469 0x00000000, 0xffffffff },
10470 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10471 0x00000000, 0xffffffff },
10472 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10473 0x00000000, 0x000000ff },
10474 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10475 0x00000000, 0xffffffff },
10476 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10477 0x00000000, 0x000000ff },
10478 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10479 0x00000000, 0xffffffff },
10480 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10481 0x00000000, 0xffffffff },
10482 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10483 0x00000000, 0xffffffff },
10484 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10485 0x00000000, 0xffffffff },
10486 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10487 0x00000000, 0xffffffff },
10488 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10489 0xffffffff, 0x00000000 },
10490 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10491 0xffffffff, 0x00000000 },
10492
10493 /* Buffer Manager Control Registers. */
b16250e3 10494 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10495 0x00000000, 0x007fff80 },
b16250e3 10496 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10497 0x00000000, 0x007fffff },
10498 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10499 0x00000000, 0x0000003f },
10500 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10501 0x00000000, 0x000001ff },
10502 { BUFMGR_MB_HIGH_WATER, 0x0000,
10503 0x00000000, 0x000001ff },
10504 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10505 0xffffffff, 0x00000000 },
10506 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10507 0xffffffff, 0x00000000 },
6aa20a22 10508
a71116d1
MC		 10509 /* Mailbox Registers */
10510 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10511 0x00000000, 0x000001ff },
10512 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10513 0x00000000, 0x000001ff },
10514 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10515 0x00000000, 0x000007ff },
10516 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10517 0x00000000, 0x000001ff },
10518
10519 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10520 };
10521
b16250e3
MC		 10522 is_5705 = is_5750 = 0;
10523 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10524 is_5705 = 1;
b16250e3
MC		 10525 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10526 is_5750 = 1;
10527 }
a71116d1
MC		 10528
10529 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10530 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10531 continue;
10532
10533 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10534 continue;
10535
10536 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10537 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10538 continue;
10539
b16250e3
MC		 10540 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10541 continue;
10542
a71116d1
MC		 10543 offset = (u32) reg_tbl[i].offset;
10544 read_mask = reg_tbl[i].read_mask;
10545 write_mask = reg_tbl[i].write_mask;
10546
10547 /* Save the original register content */
10548 save_val = tr32(offset);
10549
10550 /* Determine the read-only value. */
10551 read_val = save_val & read_mask;
10552
10553 /* Write zero to the register, then make sure the read-only bits
10554 * are not changed and the read/write bits are all zeros.
10555 */
10556 tw32(offset, 0);
10557
10558 val = tr32(offset);
10559
10560 /* Test the read-only and read/write bits. */
10561 if (((val & read_mask) != read_val) || (val & write_mask))
10562 goto out;
10563
10564 /* Write ones to all the bits defined by RdMask and WrMask, then
10565 * make sure the read-only bits are not changed and the
10566 * read/write bits are all ones.
10567 */
10568 tw32(offset, read_mask | write_mask);
10569
10570 val = tr32(offset);
10571
10572 /* Test the read-only bits. */
10573 if ((val & read_mask) != read_val)
10574 goto out;
10575
10576 /* Test the read/write bits. */
10577 if ((val & write_mask) != write_mask)
10578 goto out;
10579
10580 tw32(offset, save_val);
10581 }
10582
10583 return 0;
10584
10585out:
9f88f29f
MC		 10586 if (netif_msg_hw(tp))
10587 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10588 offset);
a71116d1
MC		 10589 tw32(offset, save_val);
10590 return -EIO;
10591}
10592
7942e1db
MC		 10593static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10594{
f71e1309 10595 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10596 int i;
10597 u32 j;
10598
e9edda69 10599 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10600 for (j = 0; j < len; j += 4) {
10601 u32 val;
10602
10603 tg3_write_mem(tp, offset + j, test_pattern[i]);
10604 tg3_read_mem(tp, offset + j, &val);
10605 if (val != test_pattern[i])
10606 return -EIO;
10607 }
10608 }
10609 return 0;
10610}
10611
10612static int tg3_test_memory(struct tg3 *tp)
10613{
10614 static struct mem_entry {
10615 u32 offset;
10616 u32 len;
10617 } mem_tbl_570x[] = {
38690194 10618 { 0x00000000, 0x00b50},
7942e1db
MC		 10619 { 0x00002000, 0x1c000},
10620 { 0xffffffff, 0x00000}
10621 }, mem_tbl_5705[] = {
10622 { 0x00000100, 0x0000c},
10623 { 0x00000200, 0x00008},
7942e1db
MC		 10624 { 0x00004000, 0x00800},
10625 { 0x00006000, 0x01000},
10626 { 0x00008000, 0x02000},
10627 { 0x00010000, 0x0e000},
10628 { 0xffffffff, 0x00000}
79f4d13a
MC		 10629 }, mem_tbl_5755[] = {
10630 { 0x00000200, 0x00008},
10631 { 0x00004000, 0x00800},
10632 { 0x00006000, 0x00800},
10633 { 0x00008000, 0x02000},
10634 { 0x00010000, 0x0c000},
10635 { 0xffffffff, 0x00000}
b16250e3
MC		 10636 }, mem_tbl_5906[] = {
10637 { 0x00000200, 0x00008},
10638 { 0x00004000, 0x00400},
10639 { 0x00006000, 0x00400},
10640 { 0x00008000, 0x01000},
10641 { 0x00010000, 0x01000},
10642 { 0xffffffff, 0x00000}
7942e1db
MC		 10643 };
10644 struct mem_entry *mem_tbl;
10645 int err = 0;
10646 int i;
10647
321d32a0
MC		 10648 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10649 mem_tbl = mem_tbl_5755;
10650 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10651 mem_tbl = mem_tbl_5906;
10652 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10653 mem_tbl = mem_tbl_5705;
10654 else
7942e1db
MC		 10655 mem_tbl = mem_tbl_570x;
10656
10657 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10658 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10659 mem_tbl[i].len)) != 0)
10660 break;
10661 }
6aa20a22 10662
7942e1db
MC		 10663 return err;
10664}
10665
9f40dead
MC		 10666#define TG3_MAC_LOOPBACK 0
10667#define TG3_PHY_LOOPBACK 1
10668
10669static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10670{
9f40dead 10671 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10672 u32 desc_idx, coal_now;
c76949a6
MC		 10673 struct sk_buff *skb, *rx_skb;
10674 u8 *tx_data;
10675 dma_addr_t map;
10676 int num_pkts, tx_len, rx_len, i, err;
10677 struct tg3_rx_buffer_desc *desc;
898a56f8 10678 struct tg3_napi *tnapi, *rnapi;
21f581a5 10679 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10680
0c1d0e2b
MC		 10681 if (tp->irq_cnt > 1) {
10682 tnapi = &tp->napi[1];
10683 rnapi = &tp->napi[1];
10684 } else {
10685 tnapi = &tp->napi[0];
10686 rnapi = &tp->napi[0];
10687 }
fd2ce37f 10688 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10689
9f40dead 10690 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10691 /* HW errata - mac loopback fails in some cases on 5780.
10692 * Normal traffic and PHY loopback are not affected by
10693 * errata.
10694 */
10695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10696 return 0;
10697
9f40dead 10698 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10699 MAC_MODE_PORT_INT_LPBACK;
10700 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10701 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10702 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10703 mac_mode |= MAC_MODE_PORT_MODE_MII;
10704 else
10705 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10706 tw32(MAC_MODE, mac_mode);
10707 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10708 u32 val;
10709
7f97a4bd
MC		 10710 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10711 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10712 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10713 } else
10714 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10715
9ef8ca99
MC		 10716 tg3_phy_toggle_automdix(tp, 0);
10717
3f7045c1 10718 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10719 udelay(40);
5d64ad34 10720
e8f3f6ca 10721 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10722 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10724 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10725 mac_mode |= MAC_MODE_PORT_MODE_MII;
10726 } else
10727 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10728
c94e3941
MC		 10729 /* reset to prevent losing 1st rx packet intermittently */
10730 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10731 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10732 udelay(10);
10733 tw32_f(MAC_RX_MODE, tp->rx_mode);
10734 }
e8f3f6ca
MC		 10735 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10736 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10737 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10738 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10739 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10740 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10741 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10742 }
9f40dead 10743 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10744 }
10745 else
10746 return -EINVAL;
c76949a6
MC		 10747
10748 err = -EIO;
10749
c76949a6 10750 tx_len = 1514;
a20e9c62 10751 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10752 if (!skb)
10753 return -ENOMEM;
10754
c76949a6
MC		 10755 tx_data = skb_put(skb, tx_len);
10756 memcpy(tx_data, tp->dev->dev_addr, 6);
10757 memset(tx_data + 6, 0x0, 8);
10758
10759 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10760
10761 for (i = 14; i < tx_len; i++)
10762 tx_data[i] = (u8) (i & 0xff);
10763
f4188d8a
AD		 10764 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10765 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10766 dev_kfree_skb(skb);
10767 return -EIO;
10768 }
c76949a6
MC		 10769
10770 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10771 rnapi->coal_now);
c76949a6
MC		 10772
10773 udelay(10);
10774
898a56f8 10775 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10776
c76949a6
MC		 10777 num_pkts = 0;
10778
f4188d8a 10779 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10780
f3f3f27e 10781 tnapi->tx_prod++;
c76949a6
MC		 10782 num_pkts++;
10783
f3f3f27e
MC		 10784 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10785 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10786
10787 udelay(10);
10788
303fc921
MC		 10789 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10790 for (i = 0; i < 35; i++) {
c76949a6 10791 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10792 coal_now);
c76949a6
MC		 10793
10794 udelay(10);
10795
898a56f8
MC		 10796 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10797 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10798 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10799 (rx_idx == (rx_start_idx + num_pkts)))
10800 break;
10801 }
10802
f4188d8a 10803 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10804 dev_kfree_skb(skb);
10805
f3f3f27e 10806 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10807 goto out;
10808
10809 if (rx_idx != rx_start_idx + num_pkts)
10810 goto out;
10811
72334482 10812 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10813 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10814 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10815 if (opaque_key != RXD_OPAQUE_RING_STD)
10816 goto out;
10817
10818 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10819 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10820 goto out;
10821
10822 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10823 if (rx_len != tx_len)
10824 goto out;
10825
21f581a5 10826 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10827
21f581a5 10828 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10829 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10830
10831 for (i = 14; i < tx_len; i++) {
10832 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10833 goto out;
10834 }
10835 err = 0;
6aa20a22 10836
c76949a6
MC		 10837 /* tg3_free_rings will unmap and free the rx_skb */
10838out:
10839 return err;
10840}
10841
9f40dead
MC		 10842#define TG3_MAC_LOOPBACK_FAILED 1
10843#define TG3_PHY_LOOPBACK_FAILED 2
10844#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10845 TG3_PHY_LOOPBACK_FAILED)
10846
10847static int tg3_test_loopback(struct tg3 *tp)
10848{
10849 int err = 0;
9936bcf6 10850 u32 cpmuctrl = 0;
9f40dead
MC		 10851
10852 if (!netif_running(tp->dev))
10853 return TG3_LOOPBACK_FAILED;
10854
b9ec6c1b
MC		 10855 err = tg3_reset_hw(tp, 1);
10856 if (err)
10857 return TG3_LOOPBACK_FAILED;
9f40dead 10858
6833c043
MC		 10859 /* Turn off gphy autopowerdown. */
10860 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10861 tg3_phy_toggle_apd(tp, false);
10862
321d32a0 10863 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10864 int i;
10865 u32 status;
10866
10867 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10868
10869 /* Wait for up to 40 microseconds to acquire lock. */
10870 for (i = 0; i < 4; i++) {
10871 status = tr32(TG3_CPMU_MUTEX_GNT);
10872 if (status == CPMU_MUTEX_GNT_DRIVER)
10873 break;
10874 udelay(10);
10875 }
10876
10877 if (status != CPMU_MUTEX_GNT_DRIVER)
10878 return TG3_LOOPBACK_FAILED;
10879
b2a5c19c 10880 /* Turn off link-based power management. */
e875093c 10881 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10882 tw32(TG3_CPMU_CTRL,
10883 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10884 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10885 }
10886
9f40dead
MC		 10887 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10888 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10889
321d32a0 10890 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10891 tw32(TG3_CPMU_CTRL, cpmuctrl);
10892
10893 /* Release the mutex */
10894 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10895 }
10896
dd477003
MC		 10897 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10898 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10899 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10900 err |= TG3_PHY_LOOPBACK_FAILED;
10901 }
10902
6833c043
MC		 10903 /* Re-enable gphy autopowerdown. */
10904 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10905 tg3_phy_toggle_apd(tp, true);
10906
9f40dead
MC		 10907 return err;
10908}
10909
4cafd3f5
MC		 10910static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10911 u64 *data)
10912{
566f86ad
MC		 10913 struct tg3 *tp = netdev_priv(dev);
10914
bc1c7567
MC		 10915 if (tp->link_config.phy_is_low_power)
10916 tg3_set_power_state(tp, PCI_D0);
10917
566f86ad
MC		 10918 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10919
10920 if (tg3_test_nvram(tp) != 0) {
10921 etest->flags |= ETH_TEST_FL_FAILED;
10922 data[0] = 1;
10923 }
ca43007a
MC		 10924 if (tg3_test_link(tp) != 0) {
10925 etest->flags |= ETH_TEST_FL_FAILED;
10926 data[1] = 1;
10927 }
a71116d1 10928 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10929 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10930
10931 if (netif_running(dev)) {
b02fd9e3 10932 tg3_phy_stop(tp);
a71116d1 10933 tg3_netif_stop(tp);
bbe832c0
MC		 10934 irq_sync = 1;
10935 }
a71116d1 10936
bbe832c0 10937 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10938
10939 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10940 err = tg3_nvram_lock(tp);
a71116d1
MC		 10941 tg3_halt_cpu(tp, RX_CPU_BASE);
10942 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10943 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10944 if (!err)
10945 tg3_nvram_unlock(tp);
a71116d1 10946
d9ab5ad1
MC		 10947 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10948 tg3_phy_reset(tp);
10949
a71116d1
MC		 10950 if (tg3_test_registers(tp) != 0) {
10951 etest->flags |= ETH_TEST_FL_FAILED;
10952 data[2] = 1;
10953 }
7942e1db
MC		 10954 if (tg3_test_memory(tp) != 0) {
10955 etest->flags |= ETH_TEST_FL_FAILED;
10956 data[3] = 1;
10957 }
9f40dead 10958 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10959 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10960
f47c11ee
DM		 10961 tg3_full_unlock(tp);
10962
d4bc3927
MC		 10963 if (tg3_test_interrupt(tp) != 0) {
10964 etest->flags |= ETH_TEST_FL_FAILED;
10965 data[5] = 1;
10966 }
f47c11ee
DM		 10967
10968 tg3_full_lock(tp, 0);
d4bc3927 10969
a71116d1
MC		 10970 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10971 if (netif_running(dev)) {
10972 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10973 err2 = tg3_restart_hw(tp, 1);
10974 if (!err2)
b9ec6c1b 10975 tg3_netif_start(tp);
a71116d1 10976 }
f47c11ee
DM		 10977
10978 tg3_full_unlock(tp);
b02fd9e3
MC		 10979
10980 if (irq_sync && !err2)
10981 tg3_phy_start(tp);
a71116d1 10982 }
bc1c7567
MC		 10983 if (tp->link_config.phy_is_low_power)
10984 tg3_set_power_state(tp, PCI_D3hot);
10985
4cafd3f5
MC		 10986}
10987
1da177e4
LT		 10988static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10989{
10990 struct mii_ioctl_data *data = if_mii(ifr);
10991 struct tg3 *tp = netdev_priv(dev);
10992 int err;
10993
b02fd9e3 10994 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10995 struct phy_device *phydev;
b02fd9e3
MC		 10996 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10997 return -EAGAIN;
3f0e3ad7
MC		 10998 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10999 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11000 }
11001
1da177e4
LT		 11002 switch(cmd) {
11003 case SIOCGMIIPHY:
882e9793 11004 data->phy_id = tp->phy_addr;
1da177e4
LT		 11005
11006 /* fallthru */
11007 case SIOCGMIIREG: {
11008 u32 mii_regval;
11009
11010 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11011 break; /* We have no PHY */
11012
bc1c7567
MC		 11013 if (tp->link_config.phy_is_low_power)
11014 return -EAGAIN;
11015
f47c11ee 11016 spin_lock_bh(&tp->lock);
1da177e4 11017 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11018 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11019
11020 data->val_out = mii_regval;
11021
11022 return err;
11023 }
11024
11025 case SIOCSMIIREG:
11026 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11027 break; /* We have no PHY */
11028
bc1c7567
MC		 11029 if (tp->link_config.phy_is_low_power)
11030 return -EAGAIN;
11031
f47c11ee 11032 spin_lock_bh(&tp->lock);
1da177e4 11033 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11034 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11035
11036 return err;
11037
11038 default:
11039 /* do nothing */
11040 break;
11041 }
11042 return -EOPNOTSUPP;
11043}
11044
11045#if TG3_VLAN_TAG_USED
11046static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11047{
11048 struct tg3 *tp = netdev_priv(dev);
11049
844b3eed
MC		 11050 if (!netif_running(dev)) {
11051 tp->vlgrp = grp;
11052 return;
11053 }
11054
11055 tg3_netif_stop(tp);
29315e87 11056
f47c11ee 11057 tg3_full_lock(tp, 0);
1da177e4
LT		 11058
11059 tp->vlgrp = grp;
11060
11061 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11062 __tg3_set_rx_mode(dev);
11063
844b3eed 11064 tg3_netif_start(tp);
46966545
MC		 11065
11066 tg3_full_unlock(tp);
1da177e4 11067}
1da177e4
LT		 11068#endif
11069
15f9850d
DM		 11070static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11071{
11072 struct tg3 *tp = netdev_priv(dev);
11073
11074 memcpy(ec, &tp->coal, sizeof(*ec));
11075 return 0;
11076}
11077
d244c892
MC		 11078static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11079{
11080 struct tg3 *tp = netdev_priv(dev);
11081 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11082 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11083
11084 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11085 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11086 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11087 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11088 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11089 }
11090
11091 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11092 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11093 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11094 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11095 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11096 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11097 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11098 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11099 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11100 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11101 return -EINVAL;
11102
11103 /* No rx interrupts will be generated if both are zero */
11104 if ((ec->rx_coalesce_usecs == 0) &&
11105 (ec->rx_max_coalesced_frames == 0))
11106 return -EINVAL;
11107
11108 /* No tx interrupts will be generated if both are zero */
11109 if ((ec->tx_coalesce_usecs == 0) &&
11110 (ec->tx_max_coalesced_frames == 0))
11111 return -EINVAL;
11112
11113 /* Only copy relevant parameters, ignore all others. */
11114 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11115 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11116 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11117 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11118 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11119 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11120 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11121 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11122 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11123
11124 if (netif_running(dev)) {
11125 tg3_full_lock(tp, 0);
11126 __tg3_set_coalesce(tp, &tp->coal);
11127 tg3_full_unlock(tp);
11128 }
11129 return 0;
11130}
11131
7282d491 11132static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11133 .get_settings = tg3_get_settings,
11134 .set_settings = tg3_set_settings,
11135 .get_drvinfo = tg3_get_drvinfo,
11136 .get_regs_len = tg3_get_regs_len,
11137 .get_regs = tg3_get_regs,
11138 .get_wol = tg3_get_wol,
11139 .set_wol = tg3_set_wol,
11140 .get_msglevel = tg3_get_msglevel,
11141 .set_msglevel = tg3_set_msglevel,
11142 .nway_reset = tg3_nway_reset,
11143 .get_link = ethtool_op_get_link,
11144 .get_eeprom_len = tg3_get_eeprom_len,
11145 .get_eeprom = tg3_get_eeprom,
11146 .set_eeprom = tg3_set_eeprom,
11147 .get_ringparam = tg3_get_ringparam,
11148 .set_ringparam = tg3_set_ringparam,
11149 .get_pauseparam = tg3_get_pauseparam,
11150 .set_pauseparam = tg3_set_pauseparam,
11151 .get_rx_csum = tg3_get_rx_csum,
11152 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11153 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11154 .set_sg = ethtool_op_set_sg,
1da177e4 11155 .set_tso = tg3_set_tso,
4cafd3f5 11156 .self_test = tg3_self_test,
1da177e4 11157 .get_strings = tg3_get_strings,
4009a93d 11158 .phys_id = tg3_phys_id,
1da177e4 11159 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11160 .get_coalesce = tg3_get_coalesce,
d244c892 11161 .set_coalesce = tg3_set_coalesce,
b9f2c044 11162 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11163};
11164
11165static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11166{
1b27777a 11167 u32 cursize, val, magic;
1da177e4
LT		 11168
11169 tp->nvram_size = EEPROM_CHIP_SIZE;
11170
e4f34110 11171 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11172 return;
11173
b16250e3
MC		 11174 if ((magic != TG3_EEPROM_MAGIC) &&
11175 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11176 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11177 return;
11178
11179 /*
11180 * Size the chip by reading offsets at increasing powers of two.
11181 * When we encounter our validation signature, we know the addressing
11182 * has wrapped around, and thus have our chip size.
11183 */
1b27777a 11184 cursize = 0x10;
1da177e4
LT		 11185
11186 while (cursize < tp->nvram_size) {
e4f34110 11187 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11188 return;
11189
1820180b 11190 if (val == magic)
1da177e4
LT		 11191 break;
11192
11193 cursize <<= 1;
11194 }
11195
11196 tp->nvram_size = cursize;
11197}
6aa20a22 11198
1da177e4
LT		 11199static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11200{
11201 u32 val;
11202
df259d8c
MC		 11203 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11204 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11205 return;
11206
11207 /* Selfboot format */
1820180b 11208 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11209 tg3_get_eeprom_size(tp);
11210 return;
11211 }
11212
6d348f2c 11213 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11214 if (val != 0) {
6d348f2c
MC		 11215 /* This is confusing. We want to operate on the
11216 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11217 * call will read from NVRAM and byteswap the data
11218 * according to the byteswapping settings for all
11219 * other register accesses. This ensures the data we
11220 * want will always reside in the lower 16-bits.
11221 * However, the data in NVRAM is in LE format, which
11222 * means the data from the NVRAM read will always be
11223 * opposite the endianness of the CPU. The 16-bit
11224 * byteswap then brings the data to CPU endianness.
11225 */
11226 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11227 return;
11228 }
11229 }
fd1122a2 11230 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11231}
11232
11233static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11234{
11235 u32 nvcfg1;
11236
11237 nvcfg1 = tr32(NVRAM_CFG1);
11238 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11239 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11240 } else {
1da177e4
LT		 11241 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11242 tw32(NVRAM_CFG1, nvcfg1);
11243 }
11244
4c987487 11245 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11246 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11247 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11248 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11249 tp->nvram_jedecnum = JEDEC_ATMEL;
11250 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11251 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11252 break;
11253 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11254 tp->nvram_jedecnum = JEDEC_ATMEL;
11255 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11256 break;
11257 case FLASH_VENDOR_ATMEL_EEPROM:
11258 tp->nvram_jedecnum = JEDEC_ATMEL;
11259 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11260 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261 break;
11262 case FLASH_VENDOR_ST:
11263 tp->nvram_jedecnum = JEDEC_ST;
11264 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11265 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266 break;
11267 case FLASH_VENDOR_SAIFUN:
11268 tp->nvram_jedecnum = JEDEC_SAIFUN;
11269 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11270 break;
11271 case FLASH_VENDOR_SST_SMALL:
11272 case FLASH_VENDOR_SST_LARGE:
11273 tp->nvram_jedecnum = JEDEC_SST;
11274 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11275 break;
1da177e4 11276 }
8590a603 11277 } else {
1da177e4
LT		 11278 tp->nvram_jedecnum = JEDEC_ATMEL;
11279 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11280 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11281 }
11282}
11283
a1b950d5
MC		 11284static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11285{
11286 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11287 case FLASH_5752PAGE_SIZE_256:
11288 tp->nvram_pagesize = 256;
11289 break;
11290 case FLASH_5752PAGE_SIZE_512:
11291 tp->nvram_pagesize = 512;
11292 break;
11293 case FLASH_5752PAGE_SIZE_1K:
11294 tp->nvram_pagesize = 1024;
11295 break;
11296 case FLASH_5752PAGE_SIZE_2K:
11297 tp->nvram_pagesize = 2048;
11298 break;
11299 case FLASH_5752PAGE_SIZE_4K:
11300 tp->nvram_pagesize = 4096;
11301 break;
11302 case FLASH_5752PAGE_SIZE_264:
11303 tp->nvram_pagesize = 264;
11304 break;
11305 case FLASH_5752PAGE_SIZE_528:
11306 tp->nvram_pagesize = 528;
11307 break;
11308 }
11309}
11310
361b4ac2
MC		 11311static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11312{
11313 u32 nvcfg1;
11314
11315 nvcfg1 = tr32(NVRAM_CFG1);
11316
e6af301b
MC		 11317 /* NVRAM protection for TPM */
11318 if (nvcfg1 & (1 << 27))
f66a29b0 11319 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11320
361b4ac2 11321 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11322 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11323 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11324 tp->nvram_jedecnum = JEDEC_ATMEL;
11325 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11326 break;
11327 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11328 tp->nvram_jedecnum = JEDEC_ATMEL;
11329 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11330 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11331 break;
11332 case FLASH_5752VENDOR_ST_M45PE10:
11333 case FLASH_5752VENDOR_ST_M45PE20:
11334 case FLASH_5752VENDOR_ST_M45PE40:
11335 tp->nvram_jedecnum = JEDEC_ST;
11336 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11337 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11338 break;
361b4ac2
MC		 11339 }
11340
11341 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11342 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11343 } else {
361b4ac2
MC		 11344 /* For eeprom, set pagesize to maximum eeprom size */
11345 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11346
11347 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11348 tw32(NVRAM_CFG1, nvcfg1);
11349 }
11350}
11351
d3c7b886
MC		 11352static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11353{
989a9d23 11354 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11355
11356 nvcfg1 = tr32(NVRAM_CFG1);
11357
11358 /* NVRAM protection for TPM */
989a9d23 11359 if (nvcfg1 & (1 << 27)) {
f66a29b0 11360 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11361 protect = 1;
11362 }
d3c7b886 11363
989a9d23
MC		 11364 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11365 switch (nvcfg1) {
8590a603
MC		 11366 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11367 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11368 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11369 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11370 tp->nvram_jedecnum = JEDEC_ATMEL;
11371 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11372 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11373 tp->nvram_pagesize = 264;
11374 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11375 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11376 tp->nvram_size = (protect ? 0x3e200 :
11377 TG3_NVRAM_SIZE_512KB);
11378 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11379 tp->nvram_size = (protect ? 0x1f200 :
11380 TG3_NVRAM_SIZE_256KB);
11381 else
11382 tp->nvram_size = (protect ? 0x1f200 :
11383 TG3_NVRAM_SIZE_128KB);
11384 break;
11385 case FLASH_5752VENDOR_ST_M45PE10:
11386 case FLASH_5752VENDOR_ST_M45PE20:
11387 case FLASH_5752VENDOR_ST_M45PE40:
11388 tp->nvram_jedecnum = JEDEC_ST;
11389 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11390 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11391 tp->nvram_pagesize = 256;
11392 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11393 tp->nvram_size = (protect ?
11394 TG3_NVRAM_SIZE_64KB :
11395 TG3_NVRAM_SIZE_128KB);
11396 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11397 tp->nvram_size = (protect ?
11398 TG3_NVRAM_SIZE_64KB :
11399 TG3_NVRAM_SIZE_256KB);
11400 else
11401 tp->nvram_size = (protect ?
11402 TG3_NVRAM_SIZE_128KB :
11403 TG3_NVRAM_SIZE_512KB);
11404 break;
d3c7b886
MC		 11405 }
11406}
11407
1b27777a
MC		 11408static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11409{
11410 u32 nvcfg1;
11411
11412 nvcfg1 = tr32(NVRAM_CFG1);
11413
11414 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11415 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11416 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11417 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11418 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11419 tp->nvram_jedecnum = JEDEC_ATMEL;
11420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11421 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11422
8590a603
MC		 11423 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11424 tw32(NVRAM_CFG1, nvcfg1);
11425 break;
11426 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11427 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11428 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11429 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11430 tp->nvram_jedecnum = JEDEC_ATMEL;
11431 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11432 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11433 tp->nvram_pagesize = 264;
11434 break;
11435 case FLASH_5752VENDOR_ST_M45PE10:
11436 case FLASH_5752VENDOR_ST_M45PE20:
11437 case FLASH_5752VENDOR_ST_M45PE40:
11438 tp->nvram_jedecnum = JEDEC_ST;
11439 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11440 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11441 tp->nvram_pagesize = 256;
11442 break;
1b27777a
MC		 11443 }
11444}
11445
6b91fa02
MC		 11446static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11447{
11448 u32 nvcfg1, protect = 0;
11449
11450 nvcfg1 = tr32(NVRAM_CFG1);
11451
11452 /* NVRAM protection for TPM */
11453 if (nvcfg1 & (1 << 27)) {
f66a29b0 11454 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11455 protect = 1;
11456 }
11457
11458 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11459 switch (nvcfg1) {
8590a603
MC		 11460 case FLASH_5761VENDOR_ATMEL_ADB021D:
11461 case FLASH_5761VENDOR_ATMEL_ADB041D:
11462 case FLASH_5761VENDOR_ATMEL_ADB081D:
11463 case FLASH_5761VENDOR_ATMEL_ADB161D:
11464 case FLASH_5761VENDOR_ATMEL_MDB021D:
11465 case FLASH_5761VENDOR_ATMEL_MDB041D:
11466 case FLASH_5761VENDOR_ATMEL_MDB081D:
11467 case FLASH_5761VENDOR_ATMEL_MDB161D:
11468 tp->nvram_jedecnum = JEDEC_ATMEL;
11469 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11470 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11471 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11472 tp->nvram_pagesize = 256;
11473 break;
11474 case FLASH_5761VENDOR_ST_A_M45PE20:
11475 case FLASH_5761VENDOR_ST_A_M45PE40:
11476 case FLASH_5761VENDOR_ST_A_M45PE80:
11477 case FLASH_5761VENDOR_ST_A_M45PE16:
11478 case FLASH_5761VENDOR_ST_M_M45PE20:
11479 case FLASH_5761VENDOR_ST_M_M45PE40:
11480 case FLASH_5761VENDOR_ST_M_M45PE80:
11481 case FLASH_5761VENDOR_ST_M_M45PE16:
11482 tp->nvram_jedecnum = JEDEC_ST;
11483 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11484 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11485 tp->nvram_pagesize = 256;
11486 break;
6b91fa02
MC		 11487 }
11488
11489 if (protect) {
11490 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11491 } else {
11492 switch (nvcfg1) {
8590a603
MC		 11493 case FLASH_5761VENDOR_ATMEL_ADB161D:
11494 case FLASH_5761VENDOR_ATMEL_MDB161D:
11495 case FLASH_5761VENDOR_ST_A_M45PE16:
11496 case FLASH_5761VENDOR_ST_M_M45PE16:
11497 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11498 break;
11499 case FLASH_5761VENDOR_ATMEL_ADB081D:
11500 case FLASH_5761VENDOR_ATMEL_MDB081D:
11501 case FLASH_5761VENDOR_ST_A_M45PE80:
11502 case FLASH_5761VENDOR_ST_M_M45PE80:
11503 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11504 break;
11505 case FLASH_5761VENDOR_ATMEL_ADB041D:
11506 case FLASH_5761VENDOR_ATMEL_MDB041D:
11507 case FLASH_5761VENDOR_ST_A_M45PE40:
11508 case FLASH_5761VENDOR_ST_M_M45PE40:
11509 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11510 break;
11511 case FLASH_5761VENDOR_ATMEL_ADB021D:
11512 case FLASH_5761VENDOR_ATMEL_MDB021D:
11513 case FLASH_5761VENDOR_ST_A_M45PE20:
11514 case FLASH_5761VENDOR_ST_M_M45PE20:
11515 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11516 break;
6b91fa02
MC		 11517 }
11518 }
11519}
11520
b5d3772c
MC		 11521static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11522{
11523 tp->nvram_jedecnum = JEDEC_ATMEL;
11524 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11525 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11526}
11527
321d32a0
MC		 11528static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11529{
11530 u32 nvcfg1;
11531
11532 nvcfg1 = tr32(NVRAM_CFG1);
11533
11534 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11535 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11536 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11537 tp->nvram_jedecnum = JEDEC_ATMEL;
11538 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11539 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11540
11541 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11542 tw32(NVRAM_CFG1, nvcfg1);
11543 return;
11544 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11545 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11546 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11547 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11548 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11549 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11550 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11551 tp->nvram_jedecnum = JEDEC_ATMEL;
11552 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11553 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11554
11555 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11556 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11557 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11558 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11559 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11560 break;
11561 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11562 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11563 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11564 break;
11565 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11566 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11567 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11568 break;
11569 }
11570 break;
11571 case FLASH_5752VENDOR_ST_M45PE10:
11572 case FLASH_5752VENDOR_ST_M45PE20:
11573 case FLASH_5752VENDOR_ST_M45PE40:
11574 tp->nvram_jedecnum = JEDEC_ST;
11575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11576 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11577
11578 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11579 case FLASH_5752VENDOR_ST_M45PE10:
11580 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11581 break;
11582 case FLASH_5752VENDOR_ST_M45PE20:
11583 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11584 break;
11585 case FLASH_5752VENDOR_ST_M45PE40:
11586 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11587 break;
11588 }
11589 break;
11590 default:
df259d8c 11591 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11592 return;
11593 }
11594
a1b950d5
MC		 11595 tg3_nvram_get_pagesize(tp, nvcfg1);
11596 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11597 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11598}
11599
11600
11601static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11602{
11603 u32 nvcfg1;
11604
11605 nvcfg1 = tr32(NVRAM_CFG1);
11606
11607 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11608 case FLASH_5717VENDOR_ATMEL_EEPROM:
11609 case FLASH_5717VENDOR_MICRO_EEPROM:
11610 tp->nvram_jedecnum = JEDEC_ATMEL;
11611 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11612 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11613
11614 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11615 tw32(NVRAM_CFG1, nvcfg1);
11616 return;
11617 case FLASH_5717VENDOR_ATMEL_MDB011D:
11618 case FLASH_5717VENDOR_ATMEL_ADB011B:
11619 case FLASH_5717VENDOR_ATMEL_ADB011D:
11620 case FLASH_5717VENDOR_ATMEL_MDB021D:
11621 case FLASH_5717VENDOR_ATMEL_ADB021B:
11622 case FLASH_5717VENDOR_ATMEL_ADB021D:
11623 case FLASH_5717VENDOR_ATMEL_45USPT:
11624 tp->nvram_jedecnum = JEDEC_ATMEL;
11625 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11626 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11627
11628 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11629 case FLASH_5717VENDOR_ATMEL_MDB021D:
11630 case FLASH_5717VENDOR_ATMEL_ADB021B:
11631 case FLASH_5717VENDOR_ATMEL_ADB021D:
11632 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11633 break;
11634 default:
11635 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11636 break;
11637 }
321d32a0 11638 break;
a1b950d5
MC		 11639 case FLASH_5717VENDOR_ST_M_M25PE10:
11640 case FLASH_5717VENDOR_ST_A_M25PE10:
11641 case FLASH_5717VENDOR_ST_M_M45PE10:
11642 case FLASH_5717VENDOR_ST_A_M45PE10:
11643 case FLASH_5717VENDOR_ST_M_M25PE20:
11644 case FLASH_5717VENDOR_ST_A_M25PE20:
11645 case FLASH_5717VENDOR_ST_M_M45PE20:
11646 case FLASH_5717VENDOR_ST_A_M45PE20:
11647 case FLASH_5717VENDOR_ST_25USPT:
11648 case FLASH_5717VENDOR_ST_45USPT:
11649 tp->nvram_jedecnum = JEDEC_ST;
11650 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11651 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11652
11653 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11654 case FLASH_5717VENDOR_ST_M_M25PE20:
11655 case FLASH_5717VENDOR_ST_A_M25PE20:
11656 case FLASH_5717VENDOR_ST_M_M45PE20:
11657 case FLASH_5717VENDOR_ST_A_M45PE20:
11658 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11659 break;
11660 default:
11661 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11662 break;
11663 }
321d32a0 11664 break;
a1b950d5
MC		 11665 default:
11666 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11667 return;
321d32a0 11668 }
a1b950d5
MC		 11669
11670 tg3_nvram_get_pagesize(tp, nvcfg1);
11671 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11672 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11673}
11674
1da177e4
LT		 11675/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11676static void __devinit tg3_nvram_init(struct tg3 *tp)
11677{
1da177e4
LT		 11678 tw32_f(GRC_EEPROM_ADDR,
11679 (EEPROM_ADDR_FSM_RESET |
11680 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11681 EEPROM_ADDR_CLKPERD_SHIFT)));
11682
9d57f01c 11683 msleep(1);
1da177e4
LT		 11684
11685 /* Enable seeprom accesses. */
11686 tw32_f(GRC_LOCAL_CTRL,
11687 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11688 udelay(100);
11689
11690 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11691 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11692 tp->tg3_flags |= TG3_FLAG_NVRAM;
11693
ec41c7df
MC		 11694 if (tg3_nvram_lock(tp)) {
11695 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11696 "tg3_nvram_init failed.\n", tp->dev->name);
11697 return;
11698 }
e6af301b 11699 tg3_enable_nvram_access(tp);
1da177e4 11700
989a9d23
MC		 11701 tp->nvram_size = 0;
11702
361b4ac2
MC		 11703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11704 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11705 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11706 tg3_get_5755_nvram_info(tp);
d30cdd28 11707 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11710 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11711 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11712 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11713 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11714 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11715 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11717 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11718 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11719 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11720 else
11721 tg3_get_nvram_info(tp);
11722
989a9d23
MC		 11723 if (tp->nvram_size == 0)
11724 tg3_get_nvram_size(tp);
1da177e4 11725
e6af301b 11726 tg3_disable_nvram_access(tp);
381291b7 11727 tg3_nvram_unlock(tp);
1da177e4
LT		 11728
11729 } else {
11730 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11731
11732 tg3_get_eeprom_size(tp);
11733 }
11734}
11735
1da177e4
LT		 11736static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11737 u32 offset, u32 len, u8 *buf)
11738{
11739 int i, j, rc = 0;
11740 u32 val;
11741
11742 for (i = 0; i < len; i += 4) {
b9fc7dc5 11743 u32 addr;
a9dc529d 11744 __be32 data;
1da177e4
LT		 11745
11746 addr = offset + i;
11747
11748 memcpy(&data, buf + i, 4);
11749
62cedd11
MC		 11750 /*
11751 * The SEEPROM interface expects the data to always be opposite
11752 * the native endian format. We accomplish this by reversing
11753 * all the operations that would have been performed on the
11754 * data from a call to tg3_nvram_read_be32().
11755 */
11756 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11757
11758 val = tr32(GRC_EEPROM_ADDR);
11759 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11760
11761 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11762 EEPROM_ADDR_READ);
11763 tw32(GRC_EEPROM_ADDR, val |
11764 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11765 (addr & EEPROM_ADDR_ADDR_MASK) |
11766 EEPROM_ADDR_START |
11767 EEPROM_ADDR_WRITE);
6aa20a22 11768
9d57f01c 11769 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11770 val = tr32(GRC_EEPROM_ADDR);
11771
11772 if (val & EEPROM_ADDR_COMPLETE)
11773 break;
9d57f01c 11774 msleep(1);
1da177e4
LT		 11775 }
11776 if (!(val & EEPROM_ADDR_COMPLETE)) {
11777 rc = -EBUSY;
11778 break;
11779 }
11780 }
11781
11782 return rc;
11783}
11784
11785/* offset and length are dword aligned */
11786static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11787 u8 *buf)
11788{
11789 int ret = 0;
11790 u32 pagesize = tp->nvram_pagesize;
11791 u32 pagemask = pagesize - 1;
11792 u32 nvram_cmd;
11793 u8 *tmp;
11794
11795 tmp = kmalloc(pagesize, GFP_KERNEL);
11796 if (tmp == NULL)
11797 return -ENOMEM;
11798
11799 while (len) {
11800 int j;
e6af301b 11801 u32 phy_addr, page_off, size;
1da177e4
LT		 11802
11803 phy_addr = offset & ~pagemask;
6aa20a22 11804
1da177e4 11805 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11806 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11807 (__be32 *) (tmp + j));
11808 if (ret)
1da177e4
LT		 11809 break;
11810 }
11811 if (ret)
11812 break;
11813
11814 page_off = offset & pagemask;
11815 size = pagesize;
11816 if (len < size)
11817 size = len;
11818
11819 len -= size;
11820
11821 memcpy(tmp + page_off, buf, size);
11822
11823 offset = offset + (pagesize - page_off);
11824
e6af301b 11825 tg3_enable_nvram_access(tp);
1da177e4
LT		 11826
11827 /*
11828 * Before we can erase the flash page, we need
11829 * to issue a special "write enable" command.
11830 */
11831 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11832
11833 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11834 break;
11835
11836 /* Erase the target page */
11837 tw32(NVRAM_ADDR, phy_addr);
11838
11839 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11840 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11841
11842 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11843 break;
11844
11845 /* Issue another write enable to start the write. */
11846 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11847
11848 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11849 break;
11850
11851 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11852 __be32 data;
1da177e4 11853
b9fc7dc5 11854 data = *((__be32 *) (tmp + j));
a9dc529d 11855
b9fc7dc5 11856 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11857
11858 tw32(NVRAM_ADDR, phy_addr + j);
11859
11860 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11861 NVRAM_CMD_WR;
11862
11863 if (j == 0)
11864 nvram_cmd |= NVRAM_CMD_FIRST;
11865 else if (j == (pagesize - 4))
11866 nvram_cmd |= NVRAM_CMD_LAST;
11867
11868 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11869 break;
11870 }
11871 if (ret)
11872 break;
11873 }
11874
11875 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11876 tg3_nvram_exec_cmd(tp, nvram_cmd);
11877
11878 kfree(tmp);
11879
11880 return ret;
11881}
11882
11883/* offset and length are dword aligned */
11884static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11885 u8 *buf)
11886{
11887 int i, ret = 0;
11888
11889 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11890 u32 page_off, phy_addr, nvram_cmd;
11891 __be32 data;
1da177e4
LT		 11892
11893 memcpy(&data, buf + i, 4);
b9fc7dc5 11894 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11895
11896 page_off = offset % tp->nvram_pagesize;
11897
1820180b 11898 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11899
11900 tw32(NVRAM_ADDR, phy_addr);
11901
11902 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11903
11904 if ((page_off == 0) || (i == 0))
11905 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11906 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11907 nvram_cmd |= NVRAM_CMD_LAST;
11908
11909 if (i == (len - 4))
11910 nvram_cmd |= NVRAM_CMD_LAST;
11911
321d32a0
MC		 11912 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11913 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11914 (tp->nvram_jedecnum == JEDEC_ST) &&
11915 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11916
11917 if ((ret = tg3_nvram_exec_cmd(tp,
11918 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11919 NVRAM_CMD_DONE)))
11920
11921 break;
11922 }
11923 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11924 /* We always do complete word writes to eeprom. */
11925 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11926 }
11927
11928 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11929 break;
11930 }
11931 return ret;
11932}
11933
11934/* offset and length are dword aligned */
11935static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11936{
11937 int ret;
11938
1da177e4 11939 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11940 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11941 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11942 udelay(40);
11943 }
11944
11945 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11946 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11947 }
11948 else {
11949 u32 grc_mode;
11950
ec41c7df
MC		 11951 ret = tg3_nvram_lock(tp);
11952 if (ret)
11953 return ret;
1da177e4 11954
e6af301b
MC		 11955 tg3_enable_nvram_access(tp);
11956 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11957 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11958 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11959
11960 grc_mode = tr32(GRC_MODE);
11961 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11962
11963 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11964 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11965
11966 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11967 buf);
11968 }
11969 else {
11970 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11971 buf);
11972 }
11973
11974 grc_mode = tr32(GRC_MODE);
11975 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11976
e6af301b 11977 tg3_disable_nvram_access(tp);
1da177e4
LT		 11978 tg3_nvram_unlock(tp);
11979 }
11980
11981 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11982 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11983 udelay(40);
11984 }
11985
11986 return ret;
11987}
11988
11989struct subsys_tbl_ent {
11990 u16 subsys_vendor, subsys_devid;
11991 u32 phy_id;
11992};
11993
11994static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11995 /* Broadcom boards. */
11996 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11997 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11998 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11999 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12000 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12001 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12002 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12003 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12004 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12005 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12006 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12007
12008 /* 3com boards. */
12009 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12010 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12011 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12012 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12013 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12014
12015 /* DELL boards. */
12016 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12017 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12018 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12019 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12020
12021 /* Compaq boards. */
12022 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12023 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12024 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12025 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12026 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12027
12028 /* IBM boards. */
12029 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12030};
12031
12032static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12033{
12034 int i;
12035
12036 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12037 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12038 tp->pdev->subsystem_vendor) &&
12039 (subsys_id_to_phy_id[i].subsys_devid ==
12040 tp->pdev->subsystem_device))
12041 return &subsys_id_to_phy_id[i];
12042 }
12043 return NULL;
12044}
12045
7d0c41ef 12046static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12047{
1da177e4 12048 u32 val;
caf636c7
MC		 12049 u16 pmcsr;
12050
12051 /* On some early chips the SRAM cannot be accessed in D3hot state,
12052 * so need make sure we're in D0.
12053 */
12054 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12055 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12056 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12057 msleep(1);
7d0c41ef
MC		 12058
12059 /* Make sure register accesses (indirect or otherwise)
12060 * will function correctly.
12061 */
12062 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12063 tp->misc_host_ctrl);
1da177e4 12064
f49639e6
DM		 12065 /* The memory arbiter has to be enabled in order for SRAM accesses
12066 * to succeed. Normally on powerup the tg3 chip firmware will make
12067 * sure it is enabled, but other entities such as system netboot
12068 * code might disable it.
12069 */
12070 val = tr32(MEMARB_MODE);
12071 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12072
1da177e4 12073 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12074 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12075
a85feb8c
GZ		 12076 /* Assume an onboard device and WOL capable by default. */
12077 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12078
b5d3772c 12079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12080 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12081 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12082 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12083 }
0527ba35
MC		 12084 val = tr32(VCPU_CFGSHDW);
12085 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12086 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12087 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12088 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12089 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12090 goto done;
b5d3772c
MC		 12091 }
12092
1da177e4
LT		 12093 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12094 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12095 u32 nic_cfg, led_cfg;
a9daf367 12096 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12097 int eeprom_phy_serdes = 0;
1da177e4
LT		 12098
12099 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12100 tp->nic_sram_data_cfg = nic_cfg;
12101
12102 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12103 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12104 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12105 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12106 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12107 (ver > 0) && (ver < 0x100))
12108 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12109
a9daf367
MC		 12110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12111 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12112
1da177e4
LT		 12113 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12114 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12115 eeprom_phy_serdes = 1;
12116
12117 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12118 if (nic_phy_id != 0) {
12119 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12120 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12121
12122 eeprom_phy_id = (id1 >> 16) << 10;
12123 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12124 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12125 } else
12126 eeprom_phy_id = 0;
12127
7d0c41ef 12128 tp->phy_id = eeprom_phy_id;
747e8f8b 12129 if (eeprom_phy_serdes) {
d1ec96af
MC		 12130 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12132 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12133 else
12134 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12135 }
7d0c41ef 12136
cbf46853 12137 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12138 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12139 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12140 else
1da177e4
LT		 12141 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12142
12143 switch (led_cfg) {
12144 default:
12145 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12146 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12147 break;
12148
12149 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12150 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12151 break;
12152
12153 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12154 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12155
12156 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12157 * read on some older 5700/5701 bootcode.
12158 */
12159 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12160 ASIC_REV_5700 ||
12161 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12162 ASIC_REV_5701)
12163 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12164
1da177e4
LT		 12165 break;
12166
12167 case SHASTA_EXT_LED_SHARED:
12168 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12169 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12170 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12171 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12172 LED_CTRL_MODE_PHY_2);
12173 break;
12174
12175 case SHASTA_EXT_LED_MAC:
12176 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12177 break;
12178
12179 case SHASTA_EXT_LED_COMBO:
12180 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12181 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12182 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12183 LED_CTRL_MODE_PHY_2);
12184 break;
12185
855e1111 12186 }
1da177e4
LT		 12187
12188 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12190 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12191 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12192
b2a5c19c
MC		 12193 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12194 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12195
9d26e213 12196 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12197 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12198 if ((tp->pdev->subsystem_vendor ==
12199 PCI_VENDOR_ID_ARIMA) &&
12200 (tp->pdev->subsystem_device == 0x205a ||
12201 tp->pdev->subsystem_device == 0x2063))
12202 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12203 } else {
f49639e6 12204 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12205 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12206 }
1da177e4
LT		 12207
12208 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12209 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12210 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12211 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12212 }
b2b98d4a
MC		 12213
12214 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12215 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12216 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12217
a85feb8c
GZ		 12218 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12219 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12220 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12221
12dac075 12222 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12223 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12224 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12225
1da177e4
LT		 12226 if (cfg2 & (1 << 17))
12227 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12228
12229 /* serdes signal pre-emphasis in register 0x590 set by */
12230 /* bootcode if bit 18 is set */
12231 if (cfg2 & (1 << 18))
12232 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12233
321d32a0
MC		 12234 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12235 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12236 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12237 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12238
8ed5d97e
MC		 12239 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12240 u32 cfg3;
12241
12242 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12243 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12244 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12245 }
a9daf367
MC		 12246
12247 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12248 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12249 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12250 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12251 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12252 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12253 }
05ac4cb7
MC		 12254done:
12255 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12256 device_set_wakeup_enable(&tp->pdev->dev,
12257 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12258}
12259
b2a5c19c
MC		 12260static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12261{
12262 int i;
12263 u32 val;
12264
12265 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12266 tw32(OTP_CTRL, cmd);
12267
12268 /* Wait for up to 1 ms for command to execute. */
12269 for (i = 0; i < 100; i++) {
12270 val = tr32(OTP_STATUS);
12271 if (val & OTP_STATUS_CMD_DONE)
12272 break;
12273 udelay(10);
12274 }
12275
12276 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12277}
12278
12279/* Read the gphy configuration from the OTP region of the chip. The gphy
12280 * configuration is a 32-bit value that straddles the alignment boundary.
12281 * We do two 32-bit reads and then shift and merge the results.
12282 */
12283static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12284{
12285 u32 bhalf_otp, thalf_otp;
12286
12287 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12288
12289 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12290 return 0;
12291
12292 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12293
12294 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12295 return 0;
12296
12297 thalf_otp = tr32(OTP_READ_DATA);
12298
12299 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12300
12301 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12302 return 0;
12303
12304 bhalf_otp = tr32(OTP_READ_DATA);
12305
12306 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12307}
12308
7d0c41ef
MC		 12309static int __devinit tg3_phy_probe(struct tg3 *tp)
12310{
12311 u32 hw_phy_id_1, hw_phy_id_2;
12312 u32 hw_phy_id, hw_phy_id_masked;
12313 int err;
1da177e4 12314
b02fd9e3
MC		 12315 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12316 return tg3_phy_init(tp);
12317
1da177e4 12318 /* Reading the PHY ID register can conflict with ASF
877d0310 12319 * firmware access to the PHY hardware.
1da177e4
LT		 12320 */
12321 err = 0;
0d3031d9
MC		 12322 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12323 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12324 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12325 } else {
12326 /* Now read the physical PHY_ID from the chip and verify
12327 * that it is sane. If it doesn't look good, we fall back
12328 * to either the hard-coded table based PHY_ID and failing
12329 * that the value found in the eeprom area.
12330 */
12331 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12332 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12333
12334 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12335 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12336 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12337
12338 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12339 }
12340
12341 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12342 tp->phy_id = hw_phy_id;
12343 if (hw_phy_id_masked == PHY_ID_BCM8002)
12344 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12345 else
12346 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12347 } else {
7d0c41ef
MC		 12348 if (tp->phy_id != PHY_ID_INVALID) {
12349 /* Do nothing, phy ID already set up in
12350 * tg3_get_eeprom_hw_cfg().
12351 */
1da177e4
LT		 12352 } else {
12353 struct subsys_tbl_ent *p;
12354
12355 /* No eeprom signature? Try the hardcoded
12356 * subsys device table.
12357 */
12358 p = lookup_by_subsys(tp);
12359 if (!p)
12360 return -ENODEV;
12361
12362 tp->phy_id = p->phy_id;
12363 if (!tp->phy_id ||
12364 tp->phy_id == PHY_ID_BCM8002)
12365 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12366 }
12367 }
12368
747e8f8b 12369 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12370 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12371 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12372 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12373
12374 tg3_readphy(tp, MII_BMSR, &bmsr);
12375 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12376 (bmsr & BMSR_LSTATUS))
12377 goto skip_phy_reset;
6aa20a22 12378
1da177e4
LT		 12379 err = tg3_phy_reset(tp);
12380 if (err)
12381 return err;
12382
12383 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12384 ADVERTISE_100HALF | ADVERTISE_100FULL |
12385 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12386 tg3_ctrl = 0;
12387 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12388 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12389 MII_TG3_CTRL_ADV_1000_FULL);
12390 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12391 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12392 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12393 MII_TG3_CTRL_ENABLE_AS_MASTER);
12394 }
12395
3600d918
MC		 12396 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12397 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12398 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12399 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12400 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12401
12402 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12403 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12404
12405 tg3_writephy(tp, MII_BMCR,
12406 BMCR_ANENABLE | BMCR_ANRESTART);
12407 }
12408 tg3_phy_set_wirespeed(tp);
12409
12410 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12411 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12412 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12413 }
12414
12415skip_phy_reset:
12416 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12417 err = tg3_init_5401phy_dsp(tp);
12418 if (err)
12419 return err;
12420 }
12421
12422 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12423 err = tg3_init_5401phy_dsp(tp);
12424 }
12425
747e8f8b 12426 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12427 tp->link_config.advertising =
12428 (ADVERTISED_1000baseT_Half |
12429 ADVERTISED_1000baseT_Full |
12430 ADVERTISED_Autoneg |
12431 ADVERTISED_FIBRE);
12432 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12433 tp->link_config.advertising &=
12434 ~(ADVERTISED_1000baseT_Half |
12435 ADVERTISED_1000baseT_Full);
12436
12437 return err;
12438}
12439
12440static void __devinit tg3_read_partno(struct tg3 *tp)
12441{
141518c9 12442 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12443 unsigned int i;
1b27777a 12444 u32 magic;
1da177e4 12445
df259d8c
MC		 12446 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12447 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12448 goto out_not_found;
1da177e4 12449
1820180b 12450 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12451 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12452 u32 tmp;
1da177e4 12453
6d348f2c
MC		 12454 /* The data is in little-endian format in NVRAM.
12455 * Use the big-endian read routines to preserve
12456 * the byte order as it exists in NVRAM.
12457 */
141518c9 12458 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12459 goto out_not_found;
12460
6d348f2c 12461 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12462 }
12463 } else {
94c982bd
MC		 12464 ssize_t cnt;
12465 unsigned int pos = 0, i = 0;
12466
12467 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12468 cnt = pci_read_vpd(tp->pdev, pos,
12469 TG3_NVM_VPD_LEN - pos,
12470 &vpd_data[pos]);
12471 if (cnt == -ETIMEDOUT || -EINTR)
12472 cnt = 0;
12473 else if (cnt < 0)
f49639e6 12474 goto out_not_found;
1b27777a 12475 }
94c982bd
MC		 12476 if (pos != TG3_NVM_VPD_LEN)
12477 goto out_not_found;
1da177e4
LT		 12478 }
12479
12480 /* Now parse and find the part number. */
141518c9 12481 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12482 unsigned char val = vpd_data[i];
af2c6a4a 12483 unsigned int block_end;
1da177e4
LT		 12484
12485 if (val == 0x82 || val == 0x91) {
12486 i = (i + 3 +
12487 (vpd_data[i + 1] +
12488 (vpd_data[i + 2] << 8)));
12489 continue;
12490 }
12491
12492 if (val != 0x90)
12493 goto out_not_found;
12494
12495 block_end = (i + 3 +
12496 (vpd_data[i + 1] +
12497 (vpd_data[i + 2] << 8)));
12498 i += 3;
af2c6a4a 12499
141518c9 12500 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12501 goto out_not_found;
12502
12503 while (i < (block_end - 2)) {
1da177e4
LT		 12504 if (vpd_data[i + 0] == 'P' &&
12505 vpd_data[i + 1] == 'N') {
12506 int partno_len = vpd_data[i + 2];
12507
af2c6a4a 12508 i += 3;
141518c9
MC		 12509 if (partno_len > TG3_BPN_SIZE ||
12510 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12511 goto out_not_found;
12512
12513 memcpy(tp->board_part_number,
af2c6a4a 12514 &vpd_data[i], partno_len);
1da177e4
LT		 12515
12516 /* Success. */
12517 return;
12518 }
af2c6a4a 12519 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12520 }
12521
12522 /* Part number not found. */
12523 goto out_not_found;
12524 }
12525
12526out_not_found:
b5d3772c
MC		 12527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12528 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12529 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12530 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12531 strcpy(tp->board_part_number, "BCM57780");
12532 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12533 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12534 strcpy(tp->board_part_number, "BCM57760");
12535 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12536 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12537 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12538 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12539 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12540 strcpy(tp->board_part_number, "BCM57788");
b703df6f
MC		 12541 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12542 strcpy(tp->board_part_number, "BCM57765");
b5d3772c
MC		 12543 else
12544 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12545}
12546
9c8a620e
MC		 12547static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12548{
12549 u32 val;
12550
e4f34110 12551 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12552 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12553 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12554 val != 0)
12555 return 0;
12556
12557 return 1;
12558}
12559
acd9c119
MC		 12560static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12561{
ff3a7cb2 12562 u32 val, offset, start, ver_offset;
acd9c119 12563 int i;
ff3a7cb2 12564 bool newver = false;
acd9c119
MC		 12565
12566 if (tg3_nvram_read(tp, 0xc, &offset) ||
12567 tg3_nvram_read(tp, 0x4, &start))
12568 return;
12569
12570 offset = tg3_nvram_logical_addr(tp, offset);
12571
ff3a7cb2 12572 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12573 return;
12574
ff3a7cb2
MC		 12575 if ((val & 0xfc000000) == 0x0c000000) {
12576 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12577 return;
12578
ff3a7cb2
MC		 12579 if (val == 0)
12580 newver = true;
12581 }
12582
12583 if (newver) {
12584 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12585 return;
12586
12587 offset = offset + ver_offset - start;
12588 for (i = 0; i < 16; i += 4) {
12589 __be32 v;
12590 if (tg3_nvram_read_be32(tp, offset + i, &v))
12591 return;
12592
12593 memcpy(tp->fw_ver + i, &v, sizeof(v));
12594 }
12595 } else {
12596 u32 major, minor;
12597
12598 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12599 return;
12600
12601 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12602 TG3_NVM_BCVER_MAJSFT;
12603 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12604 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12605 }
12606}
12607
a6f6cb1c
MC		 12608static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12609{
12610 u32 val, major, minor;
12611
12612 /* Use native endian representation */
12613 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12614 return;
12615
12616 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12617 TG3_NVM_HWSB_CFG1_MAJSFT;
12618 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12619 TG3_NVM_HWSB_CFG1_MINSFT;
12620
12621 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12622}
12623
dfe00d7d
MC		 12624static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12625{
12626 u32 offset, major, minor, build;
12627
12628 tp->fw_ver[0] = 's';
12629 tp->fw_ver[1] = 'b';
12630 tp->fw_ver[2] = '\0';
12631
12632 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12633 return;
12634
12635 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12636 case TG3_EEPROM_SB_REVISION_0:
12637 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12638 break;
12639 case TG3_EEPROM_SB_REVISION_2:
12640 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12641 break;
12642 case TG3_EEPROM_SB_REVISION_3:
12643 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12644 break;
12645 default:
12646 return;
12647 }
12648
e4f34110 12649 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12650 return;
12651
12652 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12653 TG3_EEPROM_SB_EDH_BLD_SHFT;
12654 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12655 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12656 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12657
12658 if (minor > 99 || build > 26)
12659 return;
12660
12661 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12662
12663 if (build > 0) {
12664 tp->fw_ver[8] = 'a' + build - 1;
12665 tp->fw_ver[9] = '\0';
12666 }
12667}
12668
acd9c119 12669static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12670{
12671 u32 val, offset, start;
acd9c119 12672 int i, vlen;
9c8a620e
MC		 12673
12674 for (offset = TG3_NVM_DIR_START;
12675 offset < TG3_NVM_DIR_END;
12676 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12677 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12678 return;
12679
9c8a620e
MC		 12680 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12681 break;
12682 }
12683
12684 if (offset == TG3_NVM_DIR_END)
12685 return;
12686
12687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12688 start = 0x08000000;
e4f34110 12689 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12690 return;
12691
e4f34110 12692 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12693 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12694 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12695 return;
12696
12697 offset += val - start;
12698
acd9c119 12699 vlen = strlen(tp->fw_ver);
9c8a620e 12700
acd9c119
MC		 12701 tp->fw_ver[vlen++] = ',';
12702 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12703
12704 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12705 __be32 v;
12706 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12707 return;
12708
b9fc7dc5 12709 offset += sizeof(v);
c4e6575c 12710
acd9c119
MC		 12711 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12712 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12713 break;
c4e6575c 12714 }
9c8a620e 12715
acd9c119
MC		 12716 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12717 vlen += sizeof(v);
c4e6575c 12718 }
acd9c119
MC		 12719}
12720
7fd76445
MC		 12721static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12722{
12723 int vlen;
12724 u32 apedata;
12725
12726 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12727 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12728 return;
12729
12730 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12731 if (apedata != APE_SEG_SIG_MAGIC)
12732 return;
12733
12734 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12735 if (!(apedata & APE_FW_STATUS_READY))
12736 return;
12737
12738 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12739
12740 vlen = strlen(tp->fw_ver);
12741
12742 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12743 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12744 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12745 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12746 (apedata & APE_FW_VERSION_BLDMSK));
12747}
12748
acd9c119
MC		 12749static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12750{
12751 u32 val;
12752
df259d8c
MC		 12753 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12754 tp->fw_ver[0] = 's';
12755 tp->fw_ver[1] = 'b';
12756 tp->fw_ver[2] = '\0';
12757
12758 return;
12759 }
12760
acd9c119
MC		 12761 if (tg3_nvram_read(tp, 0, &val))
12762 return;
12763
12764 if (val == TG3_EEPROM_MAGIC)
12765 tg3_read_bc_ver(tp);
12766 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12767 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12768 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12769 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12770 else
12771 return;
12772
12773 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12774 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12775 return;
12776
12777 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12778
12779 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12780}
12781
7544b097
MC		 12782static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12783
1da177e4
LT		 12784static int __devinit tg3_get_invariants(struct tg3 *tp)
12785{
12786 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12787 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12788 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12789 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12790 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12791 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12792 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12793 { },
12794 };
12795 u32 misc_ctrl_reg;
1da177e4
LT		 12796 u32 pci_state_reg, grc_misc_cfg;
12797 u32 val;
12798 u16 pci_cmd;
5e7dfd0f 12799 int err;
1da177e4 12800
1da177e4
LT		 12801 /* Force memory write invalidate off. If we leave it on,
12802 * then on 5700_BX chips we have to enable a workaround.
12803 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12804 * to match the cacheline size. The Broadcom driver have this
12805 * workaround but turns MWI off all the times so never uses
12806 * it. This seems to suggest that the workaround is insufficient.
12807 */
12808 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12809 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12810 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12811
12812 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12813 * has the register indirect write enable bit set before
12814 * we try to access any of the MMIO registers. It is also
12815 * critical that the PCI-X hw workaround situation is decided
12816 * before that as well.
12817 */
12818 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12819 &misc_ctrl_reg);
12820
12821 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12822 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12824 u32 prod_id_asic_rev;
12825
5001e2f6
MC		 12826 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12827 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12828 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12829 pci_read_config_dword(tp->pdev,
12830 TG3PCI_GEN2_PRODID_ASICREV,
12831 &prod_id_asic_rev);
b703df6f
MC		 12832 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12833 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12834 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12835 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12836 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12837 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12838 pci_read_config_dword(tp->pdev,
12839 TG3PCI_GEN15_PRODID_ASICREV,
12840 &prod_id_asic_rev);
f6eb9b1f
MC		 12841 else
12842 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12843 &prod_id_asic_rev);
12844
321d32a0 12845 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12846 }
1da177e4 12847
ff645bec
MC		 12848 /* Wrong chip ID in 5752 A0. This code can be removed later
12849 * as A0 is not in production.
12850 */
12851 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12852 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12853
6892914f
MC		 12854 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12855 * we need to disable memory and use config. cycles
12856 * only to access all registers. The 5702/03 chips
12857 * can mistakenly decode the special cycles from the
12858 * ICH chipsets as memory write cycles, causing corruption
12859 * of register and memory space. Only certain ICH bridges
12860 * will drive special cycles with non-zero data during the
12861 * address phase which can fall within the 5703's address
12862 * range. This is not an ICH bug as the PCI spec allows
12863 * non-zero address during special cycles. However, only
12864 * these ICH bridges are known to drive non-zero addresses
12865 * during special cycles.
12866 *
12867 * Since special cycles do not cross PCI bridges, we only
12868 * enable this workaround if the 5703 is on the secondary
12869 * bus of these ICH bridges.
12870 */
12871 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12872 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12873 static struct tg3_dev_id {
12874 u32 vendor;
12875 u32 device;
12876 u32 rev;
12877 } ich_chipsets[] = {
12878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12879 PCI_ANY_ID },
12880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12881 PCI_ANY_ID },
12882 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12883 0xa },
12884 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12885 PCI_ANY_ID },
12886 { },
12887 };
12888 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12889 struct pci_dev *bridge = NULL;
12890
12891 while (pci_id->vendor != 0) {
12892 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12893 bridge);
12894 if (!bridge) {
12895 pci_id++;
12896 continue;
12897 }
12898 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12899 if (bridge->revision > pci_id->rev)
6892914f
MC		 12900 continue;
12901 }
12902 if (bridge->subordinate &&
12903 (bridge->subordinate->number ==
12904 tp->pdev->bus->number)) {
12905
12906 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12907 pci_dev_put(bridge);
12908 break;
12909 }
12910 }
12911 }
12912
41588ba1
MC		 12913 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12914 static struct tg3_dev_id {
12915 u32 vendor;
12916 u32 device;
12917 } bridge_chipsets[] = {
12918 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12919 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12920 { },
12921 };
12922 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12923 struct pci_dev *bridge = NULL;
12924
12925 while (pci_id->vendor != 0) {
12926 bridge = pci_get_device(pci_id->vendor,
12927 pci_id->device,
12928 bridge);
12929 if (!bridge) {
12930 pci_id++;
12931 continue;
12932 }
12933 if (bridge->subordinate &&
12934 (bridge->subordinate->number <=
12935 tp->pdev->bus->number) &&
12936 (bridge->subordinate->subordinate >=
12937 tp->pdev->bus->number)) {
12938 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12939 pci_dev_put(bridge);
12940 break;
12941 }
12942 }
12943 }
12944
4a29cc2e
MC		 12945 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12946 * DMA addresses > 40-bit. This bridge may have other additional
12947 * 57xx devices behind it in some 4-port NIC designs for example.
12948 * Any tg3 device found behind the bridge will also need the 40-bit
12949 * DMA workaround.
12950 */
a4e2b347
MC		 12951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12953 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12954 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12955 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12956 }
4a29cc2e
MC		 12957 else {
12958 struct pci_dev *bridge = NULL;
12959
12960 do {
12961 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12962 PCI_DEVICE_ID_SERVERWORKS_EPB,
12963 bridge);
12964 if (bridge && bridge->subordinate &&
12965 (bridge->subordinate->number <=
12966 tp->pdev->bus->number) &&
12967 (bridge->subordinate->subordinate >=
12968 tp->pdev->bus->number)) {
12969 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12970 pci_dev_put(bridge);
12971 break;
12972 }
12973 } while (bridge);
12974 }
4cf78e4f 12975
1da177e4
LT		 12976 /* Initialize misc host control in PCI block. */
12977 tp->misc_host_ctrl |= (misc_ctrl_reg &
12978 MISC_HOST_CTRL_CHIPREV);
12979 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12980 tp->misc_host_ctrl);
12981
f6eb9b1f
MC		 12982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12983 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12985 tp->pdev_peer = tg3_find_peer(tp);
12986
321d32a0
MC		 12987 /* Intentionally exclude ASIC_REV_5906 */
12988 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 12993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 12994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 12996 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12997
12998 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13001 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13002 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13003 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13004
1b440c56
JL		 13005 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13006 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13007 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13008
027455ad
MC		 13009 /* 5700 B0 chips do not support checksumming correctly due
13010 * to hardware bugs.
13011 */
13012 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13013 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13014 else {
13015 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13016 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13017 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13018 tp->dev->features |= NETIF_F_IPV6_CSUM;
13019 }
13020
507399f1 13021 /* Determine TSO capabilities */
b703df6f
MC		 13022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13024 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13025 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13027 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13028 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13029 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13031 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13032 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13033 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13034 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13035 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13036 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13038 tp->fw_needed = FIRMWARE_TG3TSO5;
13039 else
13040 tp->fw_needed = FIRMWARE_TG3TSO;
13041 }
13042
13043 tp->irq_max = 1;
13044
5a6f3074 13045 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13046 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13047 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13048 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13049 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13050 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13051 tp->pdev_peer == tp->pdev))
13052 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13053
321d32a0 13054 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13056 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13057 }
4f125f42 13058
b703df6f
MC		 13059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13061 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13062 tp->irq_max = TG3_IRQ_MAX_VECS;
13063 }
f6eb9b1f 13064 }
0e1406dd 13065
615774fe
MC		 13066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13068 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13069 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13070 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13071 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13072 }
f6eb9b1f 13073
b703df6f
MC		 13074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13076 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13077
f51f3562 13078 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13079 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13080 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13081 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13082
52f4490c
MC		 13083 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13084 &pci_state_reg);
13085
5e7dfd0f
MC		 13086 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13087 if (tp->pcie_cap != 0) {
13088 u16 lnkctl;
13089
1da177e4 13090 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13091
13092 pcie_set_readrq(tp->pdev, 4096);
13093
5e7dfd0f
MC		 13094 pci_read_config_word(tp->pdev,
13095 tp->pcie_cap + PCI_EXP_LNKCTL,
13096 &lnkctl);
13097 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13099 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13102 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13103 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13104 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 13105 }
52f4490c 13106 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13107 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13108 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13109 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13110 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13111 if (!tp->pcix_cap) {
13112 printk(KERN_ERR PFX "Cannot find PCI-X "
13113 "capability, aborting.\n");
13114 return -EIO;
13115 }
13116
13117 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13118 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13119 }
1da177e4 13120
399de50b
MC		 13121 /* If we have an AMD 762 or VIA K8T800 chipset, write
13122 * reordering to the mailbox registers done by the host
13123 * controller can cause major troubles. We read back from
13124 * every mailbox register write to force the writes to be
13125 * posted to the chip in order.
13126 */
13127 if (pci_dev_present(write_reorder_chipsets) &&
13128 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13129 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13130
69fc4053
MC		 13131 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13132 &tp->pci_cacheline_sz);
13133 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13134 &tp->pci_lat_timer);
1da177e4
LT		 13135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13136 tp->pci_lat_timer < 64) {
13137 tp->pci_lat_timer = 64;
69fc4053
MC		 13138 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13139 tp->pci_lat_timer);
1da177e4
LT		 13140 }
13141
52f4490c
MC		 13142 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13143 /* 5700 BX chips need to have their TX producer index
13144 * mailboxes written twice to workaround a bug.
13145 */
13146 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13147
52f4490c 13148 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13149 *
13150 * The workaround is to use indirect register accesses
13151 * for all chip writes not to mailbox registers.
13152 */
52f4490c 13153 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13154 u32 pm_reg;
1da177e4
LT		 13155
13156 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13157
13158 /* The chip can have it's power management PCI config
13159 * space registers clobbered due to this bug.
13160 * So explicitly force the chip into D0 here.
13161 */
9974a356
MC		 13162 pci_read_config_dword(tp->pdev,
13163 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13164 &pm_reg);
13165 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13166 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13167 pci_write_config_dword(tp->pdev,
13168 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13169 pm_reg);
13170
13171 /* Also, force SERR#/PERR# in PCI command. */
13172 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13173 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13174 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13175 }
13176 }
13177
1da177e4
LT		 13178 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13179 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13180 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13181 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13182
13183 /* Chip-specific fixup from Broadcom driver */
13184 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13185 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13186 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13187 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13188 }
13189
1ee582d8 13190 /* Default fast path register access methods */
20094930 13191 tp->read32 = tg3_read32;
1ee582d8 13192 tp->write32 = tg3_write32;
09ee929c 13193 tp->read32_mbox = tg3_read32;
20094930 13194 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13195 tp->write32_tx_mbox = tg3_write32;
13196 tp->write32_rx_mbox = tg3_write32;
13197
13198 /* Various workaround register access methods */
13199 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13200 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13201 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13202 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13203 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13204 /*
13205 * Back to back register writes can cause problems on these
13206 * chips, the workaround is to read back all reg writes
13207 * except those to mailbox regs.
13208 *
13209 * See tg3_write_indirect_reg32().
13210 */
1ee582d8 13211 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13212 }
13213
1ee582d8
MC		 13214 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13215 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13216 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13217 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13218 tp->write32_rx_mbox = tg3_write_flush_reg32;
13219 }
20094930 13220
6892914f
MC		 13221 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13222 tp->read32 = tg3_read_indirect_reg32;
13223 tp->write32 = tg3_write_indirect_reg32;
13224 tp->read32_mbox = tg3_read_indirect_mbox;
13225 tp->write32_mbox = tg3_write_indirect_mbox;
13226 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13227 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13228
13229 iounmap(tp->regs);
22abe310 13230 tp->regs = NULL;
6892914f
MC		 13231
13232 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13233 pci_cmd &= ~PCI_COMMAND_MEMORY;
13234 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13235 }
b5d3772c
MC		 13236 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13237 tp->read32_mbox = tg3_read32_mbox_5906;
13238 tp->write32_mbox = tg3_write32_mbox_5906;
13239 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13240 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13241 }
6892914f 13242
bbadf503
MC		 13243 if (tp->write32 == tg3_write_indirect_reg32 ||
13244 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13245 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13247 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13248
7d0c41ef 13249 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13250 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13251 * determined before calling tg3_set_power_state() so that
13252 * we know whether or not to switch out of Vaux power.
13253 * When the flag is set, it means that GPIO1 is used for eeprom
13254 * write protect and also implies that it is a LOM where GPIOs
13255 * are not used to switch power.
6aa20a22 13256 */
7d0c41ef
MC		 13257 tg3_get_eeprom_hw_cfg(tp);
13258
0d3031d9
MC		 13259 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13260 /* Allow reads and writes to the
13261 * APE register and memory space.
13262 */
13263 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13264 PCISTATE_ALLOW_APE_SHMEM_WR;
13265 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13266 pci_state_reg);
13267 }
13268
9936bcf6 13269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13271 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13274 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13275 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13276
314fba34
MC		 13277 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13278 * GPIO1 driven high will bring 5700's external PHY out of reset.
13279 * It is also used as eeprom write protect on LOMs.
13280 */
13281 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13282 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13283 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13284 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13285 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13286 /* Unused GPIO3 must be driven as output on 5752 because there
13287 * are no pull-up resistors on unused GPIO pins.
13288 */
13289 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13290 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13291
321d32a0
MC		 13292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 13294 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13295
8d519ab2
MC		 13296 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13297 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13298 /* Turn off the debug UART. */
13299 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13300 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13301 /* Keep VMain power. */
13302 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13303 GRC_LCLCTRL_GPIO_OUTPUT0;
13304 }
13305
1da177e4 13306 /* Force the chip into D0. */
bc1c7567 13307 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13308 if (err) {
13309 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13310 pci_name(tp->pdev));
13311 return err;
13312 }
13313
1da177e4
LT		 13314 /* Derive initial jumbo mode from MTU assigned in
13315 * ether_setup() via the alloc_etherdev() call
13316 */
0f893dc6 13317 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13318 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13319 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13320
13321 /* Determine WakeOnLan speed to use. */
13322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13323 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13324 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13325 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13326 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13327 } else {
13328 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13329 }
13330
7f97a4bd
MC		 13331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13332 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13333
1da177e4
LT		 13334 /* A few boards don't want Ethernet@WireSpeed phy feature */
13335 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13336 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13337 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13338 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13339 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13340 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13341 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13342
13343 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13344 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13345 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13346 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13347 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13348
321d32a0 13349 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13350 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13351 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13352 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13353 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13354 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13357 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13359 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13360 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13361 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13362 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13363 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13364 } else
c424cb24
MC		 13365 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13366 }
1da177e4 13367
b2a5c19c
MC		 13368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13369 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13370 tp->phy_otp = tg3_read_otp_phycfg(tp);
13371 if (tp->phy_otp == 0)
13372 tp->phy_otp = TG3_OTP_DEFAULT;
13373 }
13374
f51f3562 13375 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13376 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13377 else
13378 tp->mi_mode = MAC_MI_MODE_BASE;
13379
1da177e4 13380 tp->coalesce_mode = 0;
1da177e4
LT		 13381 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13382 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13383 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13384
321d32a0
MC		 13385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13386 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13387 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13388
158d7abd
MC		 13389 err = tg3_mdio_init(tp);
13390 if (err)
13391 return err;
1da177e4 13392
55dffe79
MC		 13393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13394 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13395 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13396 return -ENOTSUPP;
13397
1da177e4
LT		 13398 /* Initialize data/descriptor byte/word swapping. */
13399 val = tr32(GRC_MODE);
13400 val &= GRC_MODE_HOST_STACKUP;
13401 tw32(GRC_MODE, val | tp->grc_mode);
13402
13403 tg3_switch_clocks(tp);
13404
13405 /* Clear this out for sanity. */
13406 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13407
13408 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13409 &pci_state_reg);
13410 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13411 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13412 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13413
13414 if (chiprevid == CHIPREV_ID_5701_A0 ||
13415 chiprevid == CHIPREV_ID_5701_B0 ||
13416 chiprevid == CHIPREV_ID_5701_B2 ||
13417 chiprevid == CHIPREV_ID_5701_B5) {
13418 void __iomem *sram_base;
13419
13420 /* Write some dummy words into the SRAM status block
13421 * area, see if it reads back correctly. If the return
13422 * value is bad, force enable the PCIX workaround.
13423 */
13424 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13425
13426 writel(0x00000000, sram_base);
13427 writel(0x00000000, sram_base + 4);
13428 writel(0xffffffff, sram_base + 4);
13429 if (readl(sram_base) != 0x00000000)
13430 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13431 }
13432 }
13433
13434 udelay(50);
13435 tg3_nvram_init(tp);
13436
13437 grc_misc_cfg = tr32(GRC_MISC_CFG);
13438 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13439
1da177e4
LT		 13440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13441 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13442 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13443 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13444
fac9b83e
DM		 13445 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13446 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13447 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13448 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13449 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13450 HOSTCC_MODE_CLRTICK_TXBD);
13451
13452 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13453 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13454 tp->misc_host_ctrl);
13455 }
13456
3bda1258
MC		 13457 /* Preserve the APE MAC_MODE bits */
13458 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13459 tp->mac_mode = tr32(MAC_MODE) |
13460 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13461 else
13462 tp->mac_mode = TG3_DEF_MAC_MODE;
13463
1da177e4
LT		 13464 /* these are limited to 10/100 only */
13465 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13466 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13467 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13468 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13469 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13470 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13471 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13472 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13473 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13474 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13475 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13476 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13477 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13478 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13479
13480 err = tg3_phy_probe(tp);
13481 if (err) {
13482 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13483 pci_name(tp->pdev), err);
13484 /* ... but do not return immediately ... */
b02fd9e3 13485 tg3_mdio_fini(tp);
1da177e4
LT		 13486 }
13487
13488 tg3_read_partno(tp);
c4e6575c 13489 tg3_read_fw_ver(tp);
1da177e4
LT		 13490
13491 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13492 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13493 } else {
13494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13495 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13496 else
13497 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13498 }
13499
13500 /* 5700 {AX,BX} chips have a broken status block link
13501 * change bit implementation, so we must use the
13502 * status register in those cases.
13503 */
13504 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13505 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13506 else
13507 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13508
13509 /* The led_ctrl is set during tg3_phy_probe, here we might
13510 * have to force the link status polling mechanism based
13511 * upon subsystem IDs.
13512 */
13513 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13515 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13516 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13517 TG3_FLAG_USE_LINKCHG_REG);
13518 }
13519
13520 /* For all SERDES we poll the MAC status register. */
13521 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13522 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13523 else
13524 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13525
ad829268 13526 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13528 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13529 tp->rx_offset = 0;
13530
f92905de
MC		 13531 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13532
13533 /* Increment the rx prod index on the rx std ring by at most
13534 * 8 for these chips to workaround hw errata.
13535 */
13536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13539 tp->rx_std_max_post = 8;
13540
8ed5d97e
MC		 13541 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13542 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13543 PCIE_PWR_MGMT_L1_THRESH_MSK;
13544
1da177e4
LT		 13545 return err;
13546}
13547
49b6e95f 13548#ifdef CONFIG_SPARC
1da177e4
LT		 13549static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13550{
13551 struct net_device *dev = tp->dev;
13552 struct pci_dev *pdev = tp->pdev;
49b6e95f 13553 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13554 const unsigned char *addr;
49b6e95f
DM		 13555 int len;
13556
13557 addr = of_get_property(dp, "local-mac-address", &len);
13558 if (addr && len == 6) {
13559 memcpy(dev->dev_addr, addr, 6);
13560 memcpy(dev->perm_addr, dev->dev_addr, 6);
13561 return 0;
1da177e4
LT		 13562 }
13563 return -ENODEV;
13564}
13565
13566static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13567{
13568 struct net_device *dev = tp->dev;
13569
13570 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13571 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13572 return 0;
13573}
13574#endif
13575
13576static int __devinit tg3_get_device_address(struct tg3 *tp)
13577{
13578 struct net_device *dev = tp->dev;
13579 u32 hi, lo, mac_offset;
008652b3 13580 int addr_ok = 0;
1da177e4 13581
49b6e95f 13582#ifdef CONFIG_SPARC
1da177e4
LT		 13583 if (!tg3_get_macaddr_sparc(tp))
13584 return 0;
13585#endif
13586
13587 mac_offset = 0x7c;
f49639e6 13588 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13589 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13590 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13591 mac_offset = 0xcc;
13592 if (tg3_nvram_lock(tp))
13593 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13594 else
13595 tg3_nvram_unlock(tp);
a1b950d5
MC		 13596 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13597 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13598 mac_offset = 0xcc;
13599 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13600 mac_offset = 0x10;
1da177e4
LT		 13601
13602 /* First try to get it from MAC address mailbox. */
13603 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13604 if ((hi >> 16) == 0x484b) {
13605 dev->dev_addr[0] = (hi >> 8) & 0xff;
13606 dev->dev_addr[1] = (hi >> 0) & 0xff;
13607
13608 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13609 dev->dev_addr[2] = (lo >> 24) & 0xff;
13610 dev->dev_addr[3] = (lo >> 16) & 0xff;
13611 dev->dev_addr[4] = (lo >> 8) & 0xff;
13612 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13613
008652b3
MC		 13614 /* Some old bootcode may report a 0 MAC address in SRAM */
13615 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13616 }
13617 if (!addr_ok) {
13618 /* Next, try NVRAM. */
df259d8c
MC		 13619 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13620 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13621 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13622 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13623 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13624 }
13625 /* Finally just fetch it out of the MAC control regs. */
13626 else {
13627 hi = tr32(MAC_ADDR_0_HIGH);
13628 lo = tr32(MAC_ADDR_0_LOW);
13629
13630 dev->dev_addr[5] = lo & 0xff;
13631 dev->dev_addr[4] = (lo >> 8) & 0xff;
13632 dev->dev_addr[3] = (lo >> 16) & 0xff;
13633 dev->dev_addr[2] = (lo >> 24) & 0xff;
13634 dev->dev_addr[1] = hi & 0xff;
13635 dev->dev_addr[0] = (hi >> 8) & 0xff;
13636 }
1da177e4
LT		 13637 }
13638
13639 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13640#ifdef CONFIG_SPARC
1da177e4
LT		 13641 if (!tg3_get_default_macaddr_sparc(tp))
13642 return 0;
13643#endif
13644 return -EINVAL;
13645 }
2ff43697 13646 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13647 return 0;
13648}
13649
59e6b434
DM		 13650#define BOUNDARY_SINGLE_CACHELINE 1
13651#define BOUNDARY_MULTI_CACHELINE 2
13652
13653static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13654{
13655 int cacheline_size;
13656 u8 byte;
13657 int goal;
13658
13659 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13660 if (byte == 0)
13661 cacheline_size = 1024;
13662 else
13663 cacheline_size = (int) byte * 4;
13664
13665 /* On 5703 and later chips, the boundary bits have no
13666 * effect.
13667 */
13668 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13669 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13670 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13671 goto out;
13672
13673#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13674 goal = BOUNDARY_MULTI_CACHELINE;
13675#else
13676#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13677 goal = BOUNDARY_SINGLE_CACHELINE;
13678#else
13679 goal = 0;
13680#endif
13681#endif
13682
b703df6f
MC		 13683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13684 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13685 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13686 goto out;
13687 }
13688
59e6b434
DM		 13689 if (!goal)
13690 goto out;
13691
13692 /* PCI controllers on most RISC systems tend to disconnect
13693 * when a device tries to burst across a cache-line boundary.
13694 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13695 *
13696 * Unfortunately, for PCI-E there are only limited
13697 * write-side controls for this, and thus for reads
13698 * we will still get the disconnects. We'll also waste
13699 * these PCI cycles for both read and write for chips
13700 * other than 5700 and 5701 which do not implement the
13701 * boundary bits.
13702 */
13703 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13704 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13705 switch (cacheline_size) {
13706 case 16:
13707 case 32:
13708 case 64:
13709 case 128:
13710 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13711 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13712 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13713 } else {
13714 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13715 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13716 }
13717 break;
13718
13719 case 256:
13720 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13721 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13722 break;
13723
13724 default:
13725 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13726 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13727 break;
855e1111 13728 }
59e6b434
DM		 13729 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13730 switch (cacheline_size) {
13731 case 16:
13732 case 32:
13733 case 64:
13734 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13735 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13736 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13737 break;
13738 }
13739 /* fallthrough */
13740 case 128:
13741 default:
13742 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13743 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13744 break;
855e1111 13745 }
59e6b434
DM		 13746 } else {
13747 switch (cacheline_size) {
13748 case 16:
13749 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13750 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13751 DMA_RWCTRL_WRITE_BNDRY_16);
13752 break;
13753 }
13754 /* fallthrough */
13755 case 32:
13756 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13757 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13758 DMA_RWCTRL_WRITE_BNDRY_32);
13759 break;
13760 }
13761 /* fallthrough */
13762 case 64:
13763 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13764 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13765 DMA_RWCTRL_WRITE_BNDRY_64);
13766 break;
13767 }
13768 /* fallthrough */
13769 case 128:
13770 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13771 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13772 DMA_RWCTRL_WRITE_BNDRY_128);
13773 break;
13774 }
13775 /* fallthrough */
13776 case 256:
13777 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13778 DMA_RWCTRL_WRITE_BNDRY_256);
13779 break;
13780 case 512:
13781 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13782 DMA_RWCTRL_WRITE_BNDRY_512);
13783 break;
13784 case 1024:
13785 default:
13786 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13787 DMA_RWCTRL_WRITE_BNDRY_1024);
13788 break;
855e1111 13789 }
59e6b434
DM		 13790 }
13791
13792out:
13793 return val;
13794}
13795
1da177e4
LT		 13796static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13797{
13798 struct tg3_internal_buffer_desc test_desc;
13799 u32 sram_dma_descs;
13800 int i, ret;
13801
13802 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13803
13804 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13805 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13806 tw32(RDMAC_STATUS, 0);
13807 tw32(WDMAC_STATUS, 0);
13808
13809 tw32(BUFMGR_MODE, 0);
13810 tw32(FTQ_RESET, 0);
13811
13812 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13813 test_desc.addr_lo = buf_dma & 0xffffffff;
13814 test_desc.nic_mbuf = 0x00002100;
13815 test_desc.len = size;
13816
13817 /*
13818 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13819 * the *second* time the tg3 driver was getting loaded after an
13820 * initial scan.
13821 *
13822 * Broadcom tells me:
13823 * ...the DMA engine is connected to the GRC block and a DMA
13824 * reset may affect the GRC block in some unpredictable way...
13825 * The behavior of resets to individual blocks has not been tested.
13826 *
13827 * Broadcom noted the GRC reset will also reset all sub-components.
13828 */
13829 if (to_device) {
13830 test_desc.cqid_sqid = (13 << 8) | 2;
13831
13832 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13833 udelay(40);
13834 } else {
13835 test_desc.cqid_sqid = (16 << 8) | 7;
13836
13837 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13838 udelay(40);
13839 }
13840 test_desc.flags = 0x00000005;
13841
13842 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13843 u32 val;
13844
13845 val = *(((u32 *)&test_desc) + i);
13846 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13847 sram_dma_descs + (i * sizeof(u32)));
13848 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13849 }
13850 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13851
13852 if (to_device) {
13853 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13854 } else {
13855 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13856 }
13857
13858 ret = -ENODEV;
13859 for (i = 0; i < 40; i++) {
13860 u32 val;
13861
13862 if (to_device)
13863 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13864 else
13865 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13866 if ((val & 0xffff) == sram_dma_descs) {
13867 ret = 0;
13868 break;
13869 }
13870
13871 udelay(100);
13872 }
13873
13874 return ret;
13875}
13876
ded7340d 13877#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13878
13879static int __devinit tg3_test_dma(struct tg3 *tp)
13880{
13881 dma_addr_t buf_dma;
59e6b434 13882 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13883 int ret = 0;
1da177e4
LT		 13884
13885 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13886 if (!buf) {
13887 ret = -ENOMEM;
13888 goto out_nofree;
13889 }
13890
13891 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13892 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13893
59e6b434 13894 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13895
b703df6f
MC		 13896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13898 goto out;
13899
1da177e4
LT		 13900 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13901 /* DMA read watermark not used on PCIE */
13902 tp->dma_rwctrl |= 0x00180000;
13903 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13906 tp->dma_rwctrl |= 0x003f0000;
13907 else
13908 tp->dma_rwctrl |= 0x003f000f;
13909 } else {
13910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13912 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13913 u32 read_water = 0x7;
1da177e4 13914
4a29cc2e
MC		 13915 /* If the 5704 is behind the EPB bridge, we can
13916 * do the less restrictive ONE_DMA workaround for
13917 * better performance.
13918 */
13919 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13921 tp->dma_rwctrl |= 0x8000;
13922 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13923 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13924
49afdeb6
MC		 13925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13926 read_water = 4;
59e6b434 13927 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13928 tp->dma_rwctrl |=
13929 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13930 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13931 (1 << 23);
4cf78e4f
MC		 13932 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13933 /* 5780 always in PCIX mode */
13934 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13935 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13936 /* 5714 always in PCIX mode */
13937 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13938 } else {
13939 tp->dma_rwctrl |= 0x001b000f;
13940 }
13941 }
13942
13943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13945 tp->dma_rwctrl &= 0xfffffff0;
13946
13947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13949 /* Remove this if it causes problems for some boards. */
13950 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13951
13952 /* On 5700/5701 chips, we need to set this bit.
13953 * Otherwise the chip will issue cacheline transactions
13954 * to streamable DMA memory with not all the byte
13955 * enables turned on. This is an error on several
13956 * RISC PCI controllers, in particular sparc64.
13957 *
13958 * On 5703/5704 chips, this bit has been reassigned
13959 * a different meaning. In particular, it is used
13960 * on those chips to enable a PCI-X workaround.
13961 */
13962 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13963 }
13964
13965 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13966
13967#if 0
13968 /* Unneeded, already done by tg3_get_invariants. */
13969 tg3_switch_clocks(tp);
13970#endif
13971
1da177e4
LT		 13972 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13973 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13974 goto out;
13975
59e6b434
DM		 13976 /* It is best to perform DMA test with maximum write burst size
13977 * to expose the 5700/5701 write DMA bug.
13978 */
13979 saved_dma_rwctrl = tp->dma_rwctrl;
13980 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13981 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13982
1da177e4
LT		 13983 while (1) {
13984 u32 *p = buf, i;
13985
13986 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13987 p[i] = i;
13988
13989 /* Send the buffer to the chip. */
13990 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13991 if (ret) {
13992 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13993 break;
13994 }
13995
13996#if 0
13997 /* validate data reached card RAM correctly. */
13998 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13999 u32 val;
14000 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14001 if (le32_to_cpu(val) != p[i]) {
14002 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14003 /* ret = -ENODEV here? */
14004 }
14005 p[i] = 0;
14006 }
14007#endif
14008 /* Now read it back. */
14009 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14010 if (ret) {
14011 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14012
14013 break;
14014 }
14015
14016 /* Verify it. */
14017 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14018 if (p[i] == i)
14019 continue;
14020
59e6b434
DM		 14021 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14022 DMA_RWCTRL_WRITE_BNDRY_16) {
14023 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14024 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14025 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14026 break;
14027 } else {
14028 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14029 ret = -ENODEV;
14030 goto out;
14031 }
14032 }
14033
14034 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14035 /* Success. */
14036 ret = 0;
14037 break;
14038 }
14039 }
59e6b434
DM		 14040 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14041 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14042 static struct pci_device_id dma_wait_state_chipsets[] = {
14043 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14044 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14045 { },
14046 };
14047
59e6b434 14048 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14049 * now look for chipsets that are known to expose the
14050 * DMA bug without failing the test.
59e6b434 14051 */
6d1cfbab
MC		 14052 if (pci_dev_present(dma_wait_state_chipsets)) {
14053 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14054 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14055 }
14056 else
14057 /* Safe to use the calculated DMA boundary. */
14058 tp->dma_rwctrl = saved_dma_rwctrl;
14059
59e6b434
DM		 14060 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14061 }
1da177e4
LT		 14062
14063out:
14064 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14065out_nofree:
14066 return ret;
14067}
14068
14069static void __devinit tg3_init_link_config(struct tg3 *tp)
14070{
14071 tp->link_config.advertising =
14072 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14073 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14074 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14075 ADVERTISED_Autoneg | ADVERTISED_MII);
14076 tp->link_config.speed = SPEED_INVALID;
14077 tp->link_config.duplex = DUPLEX_INVALID;
14078 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14079 tp->link_config.active_speed = SPEED_INVALID;
14080 tp->link_config.active_duplex = DUPLEX_INVALID;
14081 tp->link_config.phy_is_low_power = 0;
14082 tp->link_config.orig_speed = SPEED_INVALID;
14083 tp->link_config.orig_duplex = DUPLEX_INVALID;
14084 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14085}
14086
14087static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14088{
f6eb9b1f 14089 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
b703df6f
MC		 14090 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14091 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
fdfec172
MC		 14092 tp->bufmgr_config.mbuf_read_dma_low_water =
14093 DEFAULT_MB_RDMA_LOW_WATER_5705;
14094 tp->bufmgr_config.mbuf_mac_rx_low_water =
14095 DEFAULT_MB_MACRX_LOW_WATER_5705;
14096 tp->bufmgr_config.mbuf_high_water =
14097 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14099 tp->bufmgr_config.mbuf_mac_rx_low_water =
14100 DEFAULT_MB_MACRX_LOW_WATER_5906;
14101 tp->bufmgr_config.mbuf_high_water =
14102 DEFAULT_MB_HIGH_WATER_5906;
14103 }
fdfec172
MC		 14104
14105 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14106 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14107 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14108 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14109 tp->bufmgr_config.mbuf_high_water_jumbo =
14110 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14111 } else {
14112 tp->bufmgr_config.mbuf_read_dma_low_water =
14113 DEFAULT_MB_RDMA_LOW_WATER;
14114 tp->bufmgr_config.mbuf_mac_rx_low_water =
14115 DEFAULT_MB_MACRX_LOW_WATER;
14116 tp->bufmgr_config.mbuf_high_water =
14117 DEFAULT_MB_HIGH_WATER;
14118
14119 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14120 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14121 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14122 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14123 tp->bufmgr_config.mbuf_high_water_jumbo =
14124 DEFAULT_MB_HIGH_WATER_JUMBO;
14125 }
1da177e4
LT		 14126
14127 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14128 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14129}
14130
14131static char * __devinit tg3_phy_string(struct tg3 *tp)
14132{
14133 switch (tp->phy_id & PHY_ID_MASK) {
14134 case PHY_ID_BCM5400: return "5400";
14135 case PHY_ID_BCM5401: return "5401";
14136 case PHY_ID_BCM5411: return "5411";
14137 case PHY_ID_BCM5701: return "5701";
14138 case PHY_ID_BCM5703: return "5703";
14139 case PHY_ID_BCM5704: return "5704";
14140 case PHY_ID_BCM5705: return "5705";
14141 case PHY_ID_BCM5750: return "5750";
85e94ced 14142 case PHY_ID_BCM5752: return "5752";
a4e2b347 14143 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14144 case PHY_ID_BCM5780: return "5780";
af36e6b6 14145 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14146 case PHY_ID_BCM5787: return "5787";
d30cdd28 14147 case PHY_ID_BCM5784: return "5784";
126a3368 14148 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14149 case PHY_ID_BCM5906: return "5906";
9936bcf6 14150 case PHY_ID_BCM5761: return "5761";
c2060fe1 14151 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 14152 case PHY_ID_BCM8002: return "8002/serdes";
14153 case 0: return "serdes";
14154 default: return "unknown";
855e1111 14155 }
1da177e4
LT		 14156}
14157
f9804ddb
MC		 14158static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14159{
14160 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14161 strcpy(str, "PCI Express");
14162 return str;
14163 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14164 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14165
14166 strcpy(str, "PCIX:");
14167
14168 if ((clock_ctrl == 7) ||
14169 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14170 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14171 strcat(str, "133MHz");
14172 else if (clock_ctrl == 0)
14173 strcat(str, "33MHz");
14174 else if (clock_ctrl == 2)
14175 strcat(str, "50MHz");
14176 else if (clock_ctrl == 4)
14177 strcat(str, "66MHz");
14178 else if (clock_ctrl == 6)
14179 strcat(str, "100MHz");
f9804ddb
MC		 14180 } else {
14181 strcpy(str, "PCI:");
14182 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14183 strcat(str, "66MHz");
14184 else
14185 strcat(str, "33MHz");
14186 }
14187 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14188 strcat(str, ":32-bit");
14189 else
14190 strcat(str, ":64-bit");
14191 return str;
14192}
14193
8c2dc7e1 14194static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14195{
14196 struct pci_dev *peer;
14197 unsigned int func, devnr = tp->pdev->devfn & ~7;
14198
14199 for (func = 0; func < 8; func++) {
14200 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14201 if (peer && peer != tp->pdev)
14202 break;
14203 pci_dev_put(peer);
14204 }
16fe9d74
MC		 14205 /* 5704 can be configured in single-port mode, set peer to
14206 * tp->pdev in that case.
14207 */
14208 if (!peer) {
14209 peer = tp->pdev;
14210 return peer;
14211 }
1da177e4
LT		 14212
14213 /*
14214 * We don't need to keep the refcount elevated; there's no way
14215 * to remove one half of this device without removing the other
14216 */
14217 pci_dev_put(peer);
14218
14219 return peer;
14220}
14221
15f9850d
DM		 14222static void __devinit tg3_init_coal(struct tg3 *tp)
14223{
14224 struct ethtool_coalesce *ec = &tp->coal;
14225
14226 memset(ec, 0, sizeof(*ec));
14227 ec->cmd = ETHTOOL_GCOALESCE;
14228 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14229 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14230 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14231 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14232 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14233 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14234 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14235 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14236 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14237
14238 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14239 HOSTCC_MODE_CLRTICK_TXBD)) {
14240 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14241 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14242 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14243 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14244 }
d244c892
MC		 14245
14246 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14247 ec->rx_coalesce_usecs_irq = 0;
14248 ec->tx_coalesce_usecs_irq = 0;
14249 ec->stats_block_coalesce_usecs = 0;
14250 }
15f9850d
DM		 14251}
14252
7c7d64b8
SH		 14253static const struct net_device_ops tg3_netdev_ops = {
14254 .ndo_open = tg3_open,
14255 .ndo_stop = tg3_close,
00829823
SH		 14256 .ndo_start_xmit = tg3_start_xmit,
14257 .ndo_get_stats = tg3_get_stats,
14258 .ndo_validate_addr = eth_validate_addr,
14259 .ndo_set_multicast_list = tg3_set_rx_mode,
14260 .ndo_set_mac_address = tg3_set_mac_addr,
14261 .ndo_do_ioctl = tg3_ioctl,
14262 .ndo_tx_timeout = tg3_tx_timeout,
14263 .ndo_change_mtu = tg3_change_mtu,
14264#if TG3_VLAN_TAG_USED
14265 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14266#endif
14267#ifdef CONFIG_NET_POLL_CONTROLLER
14268 .ndo_poll_controller = tg3_poll_controller,
14269#endif
14270};
14271
14272static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14273 .ndo_open = tg3_open,
14274 .ndo_stop = tg3_close,
14275 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14276 .ndo_get_stats = tg3_get_stats,
14277 .ndo_validate_addr = eth_validate_addr,
14278 .ndo_set_multicast_list = tg3_set_rx_mode,
14279 .ndo_set_mac_address = tg3_set_mac_addr,
14280 .ndo_do_ioctl = tg3_ioctl,
14281 .ndo_tx_timeout = tg3_tx_timeout,
14282 .ndo_change_mtu = tg3_change_mtu,
14283#if TG3_VLAN_TAG_USED
14284 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14285#endif
14286#ifdef CONFIG_NET_POLL_CONTROLLER
14287 .ndo_poll_controller = tg3_poll_controller,
14288#endif
14289};
14290
1da177e4
LT		 14291static int __devinit tg3_init_one(struct pci_dev *pdev,
14292 const struct pci_device_id *ent)
14293{
14294 static int tg3_version_printed = 0;
1da177e4
LT		 14295 struct net_device *dev;
14296 struct tg3 *tp;
646c9edd
MC		 14297 int i, err, pm_cap;
14298 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14299 char str[40];
72f2afb8 14300 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14301
14302 if (tg3_version_printed++ == 0)
14303 printk(KERN_INFO "%s", version);
14304
14305 err = pci_enable_device(pdev);
14306 if (err) {
14307 printk(KERN_ERR PFX "Cannot enable PCI device, "
14308 "aborting.\n");
14309 return err;
14310 }
14311
1da177e4
LT		 14312 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14313 if (err) {
14314 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14315 "aborting.\n");
14316 goto err_out_disable_pdev;
14317 }
14318
14319 pci_set_master(pdev);
14320
14321 /* Find power-management capability. */
14322 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14323 if (pm_cap == 0) {
14324 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14325 "aborting.\n");
14326 err = -EIO;
14327 goto err_out_free_res;
14328 }
14329
fe5f5787 14330 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14331 if (!dev) {
14332 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14333 err = -ENOMEM;
14334 goto err_out_free_res;
14335 }
14336
1da177e4
LT		 14337 SET_NETDEV_DEV(dev, &pdev->dev);
14338
1da177e4
LT		 14339#if TG3_VLAN_TAG_USED
14340 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14341#endif
14342
14343 tp = netdev_priv(dev);
14344 tp->pdev = pdev;
14345 tp->dev = dev;
14346 tp->pm_cap = pm_cap;
1da177e4
LT		 14347 tp->rx_mode = TG3_DEF_RX_MODE;
14348 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14349
1da177e4
LT		 14350 if (tg3_debug > 0)
14351 tp->msg_enable = tg3_debug;
14352 else
14353 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14354
14355 /* The word/byte swap controls here control register access byte
14356 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14357 * setting below.
14358 */
14359 tp->misc_host_ctrl =
14360 MISC_HOST_CTRL_MASK_PCI_INT |
14361 MISC_HOST_CTRL_WORD_SWAP |
14362 MISC_HOST_CTRL_INDIR_ACCESS |
14363 MISC_HOST_CTRL_PCISTATE_RW;
14364
14365 /* The NONFRM (non-frame) byte/word swap controls take effect
14366 * on descriptor entries, anything which isn't packet data.
14367 *
14368 * The StrongARM chips on the board (one for tx, one for rx)
14369 * are running in big-endian mode.
14370 */
14371 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14372 GRC_MODE_WSWAP_NONFRM_DATA);
14373#ifdef __BIG_ENDIAN
14374 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14375#endif
14376 spin_lock_init(&tp->lock);
1da177e4 14377 spin_lock_init(&tp->indirect_lock);
c4028958 14378 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14379
d5fe488a 14380 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14381 if (!tp->regs) {
1da177e4
LT		 14382 printk(KERN_ERR PFX "Cannot map device registers, "
14383 "aborting.\n");
14384 err = -ENOMEM;
14385 goto err_out_free_dev;
14386 }
14387
14388 tg3_init_link_config(tp);
14389
1da177e4
LT		 14390 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14391 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14392
1da177e4 14393 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14394 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14395 dev->irq = pdev->irq;
1da177e4
LT		 14396
14397 err = tg3_get_invariants(tp);
14398 if (err) {
14399 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14400 "aborting.\n");
14401 goto err_out_iounmap;
14402 }
14403
615774fe
MC		 14404 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14405 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14406 dev->netdev_ops = &tg3_netdev_ops;
14407 else
14408 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14409
14410
4a29cc2e
MC		 14411 /* The EPB bridge inside 5714, 5715, and 5780 and any
14412 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14413 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14414 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14415 * do DMA address check in tg3_start_xmit().
14416 */
4a29cc2e 14417 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14418 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14419 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14420 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14421#ifdef CONFIG_HIGHMEM
6a35528a 14422 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14423#endif
4a29cc2e 14424 } else
6a35528a 14425 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14426
14427 /* Configure DMA attributes. */
284901a9 14428 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14429 err = pci_set_dma_mask(pdev, dma_mask);
14430 if (!err) {
14431 dev->features |= NETIF_F_HIGHDMA;
14432 err = pci_set_consistent_dma_mask(pdev,
14433 persist_dma_mask);
14434 if (err < 0) {
14435 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14436 "DMA for consistent allocations\n");
14437 goto err_out_iounmap;
14438 }
14439 }
14440 }
284901a9
YH		 14441 if (err || dma_mask == DMA_BIT_MASK(32)) {
14442 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14443 if (err) {
14444 printk(KERN_ERR PFX "No usable DMA configuration, "
14445 "aborting.\n");
14446 goto err_out_iounmap;
14447 }
14448 }
14449
fdfec172 14450 tg3_init_bufmgr_config(tp);
1da177e4 14451
507399f1
MC		 14452 /* Selectively allow TSO based on operating conditions */
14453 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14454 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14455 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14456 else {
14457 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14458 tp->fw_needed = NULL;
1da177e4 14459 }
507399f1
MC		 14460
14461 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14462 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14463
4e3a7aaa
MC		 14464 /* TSO is on by default on chips that support hardware TSO.
14465 * Firmware TSO on older chips gives lower performance, so it
14466 * is off by default, but can be enabled using ethtool.
14467 */
e849cdc3
MC		 14468 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14469 (dev->features & NETIF_F_IP_CSUM))
14470 dev->features |= NETIF_F_TSO;
14471
14472 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14473 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14474 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14475 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14476 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14478 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14479 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14480 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14482 dev->features |= NETIF_F_TSO_ECN;
b0026624 14483 }
1da177e4 14484
1da177e4
LT		 14485 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14486 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14487 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14488 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14489 tp->rx_pending = 63;
14490 }
14491
1da177e4
LT		 14492 err = tg3_get_device_address(tp);
14493 if (err) {
14494 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14495 "aborting.\n");
026a6c21 14496 goto err_out_iounmap;
1da177e4
LT		 14497 }
14498
c88864df 14499 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14500 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14501 if (!tp->aperegs) {
c88864df
MC		 14502 printk(KERN_ERR PFX "Cannot map APE registers, "
14503 "aborting.\n");
14504 err = -ENOMEM;
026a6c21 14505 goto err_out_iounmap;
c88864df
MC		 14506 }
14507
14508 tg3_ape_lock_init(tp);
7fd76445
MC		 14509
14510 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14511 tg3_read_dash_ver(tp);
c88864df
MC		 14512 }
14513
1da177e4
LT		 14514 /*
14515 * Reset chip in case UNDI or EFI driver did not shutdown
14516 * DMA self test will enable WDMAC and we'll see (spurious)
14517 * pending DMA on the PCI bus at that point.
14518 */
14519 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14520 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14521 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14522 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14523 }
14524
14525 err = tg3_test_dma(tp);
14526 if (err) {
14527 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14528 goto err_out_apeunmap;
1da177e4
LT		 14529 }
14530
1da177e4
LT		 14531 /* flow control autonegotiation is default behavior */
14532 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14533 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14534
78f90dcf
MC		 14535 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14536 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14537 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14538 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14539 struct tg3_napi *tnapi = &tp->napi[i];
14540
14541 tnapi->tp = tp;
14542 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14543
14544 tnapi->int_mbox = intmbx;
14545 if (i < 4)
14546 intmbx += 0x8;
14547 else
14548 intmbx += 0x4;
14549
14550 tnapi->consmbox = rcvmbx;
14551 tnapi->prodmbox = sndmbx;
14552
14553 if (i) {
14554 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14555 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14556 } else {
14557 tnapi->coal_now = HOSTCC_MODE_NOW;
14558 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14559 }
14560
14561 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14562 break;
14563
14564 /*
14565 * If we support MSIX, we'll be using RSS. If we're using
14566 * RSS, the first vector only handles link interrupts and the
14567 * remaining vectors handle rx and tx interrupts. Reuse the
14568 * mailbox values for the next iteration. The values we setup
14569 * above are still useful for the single vectored mode.
14570 */
14571 if (!i)
14572 continue;
14573
14574 rcvmbx += 0x8;
14575
14576 if (sndmbx & 0x4)
14577 sndmbx -= 0x4;
14578 else
14579 sndmbx += 0xc;
14580 }
14581
15f9850d
DM		 14582 tg3_init_coal(tp);
14583
c49a1561
MC		 14584 pci_set_drvdata(pdev, dev);
14585
1da177e4
LT		 14586 err = register_netdev(dev);
14587 if (err) {
14588 printk(KERN_ERR PFX "Cannot register net device, "
14589 "aborting.\n");
0d3031d9 14590 goto err_out_apeunmap;
1da177e4
LT		 14591 }
14592
df59c940 14593 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14594 dev->name,
14595 tp->board_part_number,
14596 tp->pci_chip_rev_id,
f9804ddb 14597 tg3_bus_string(tp, str),
e174961c 14598 dev->dev_addr);
1da177e4 14599
3f0e3ad7
MC		 14600 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14601 struct phy_device *phydev;
14602 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14603 printk(KERN_INFO
14604 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14605 tp->dev->name, phydev->drv->name,
14606 dev_name(&phydev->dev));
14607 } else
df59c940
MC		 14608 printk(KERN_INFO
14609 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14610 tp->dev->name, tg3_phy_string(tp),
14611 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14612 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14613 "10/100/1000Base-T")),
14614 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14615
14616 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14617 dev->name,
14618 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14619 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14620 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14621 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14622 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14623 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14624 dev->name, tp->dma_rwctrl,
284901a9 14625 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14626 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14627
14628 return 0;
14629
0d3031d9
MC		 14630err_out_apeunmap:
14631 if (tp->aperegs) {
14632 iounmap(tp->aperegs);
14633 tp->aperegs = NULL;
14634 }
14635
1da177e4 14636err_out_iounmap:
6892914f
MC		 14637 if (tp->regs) {
14638 iounmap(tp->regs);
22abe310 14639 tp->regs = NULL;
6892914f 14640 }
1da177e4
LT		 14641
14642err_out_free_dev:
14643 free_netdev(dev);
14644
14645err_out_free_res:
14646 pci_release_regions(pdev);
14647
14648err_out_disable_pdev:
14649 pci_disable_device(pdev);
14650 pci_set_drvdata(pdev, NULL);
14651 return err;
14652}
14653
14654static void __devexit tg3_remove_one(struct pci_dev *pdev)
14655{
14656 struct net_device *dev = pci_get_drvdata(pdev);
14657
14658 if (dev) {
14659 struct tg3 *tp = netdev_priv(dev);
14660
077f849d
JSR		 14661 if (tp->fw)
14662 release_firmware(tp->fw);
14663
7faa006f 14664 flush_scheduled_work();
158d7abd 14665
b02fd9e3
MC		 14666 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14667 tg3_phy_fini(tp);
158d7abd 14668 tg3_mdio_fini(tp);
b02fd9e3 14669 }
158d7abd 14670
1da177e4 14671 unregister_netdev(dev);
0d3031d9
MC		 14672 if (tp->aperegs) {
14673 iounmap(tp->aperegs);
14674 tp->aperegs = NULL;
14675 }
6892914f
MC		 14676 if (tp->regs) {
14677 iounmap(tp->regs);
22abe310 14678 tp->regs = NULL;
6892914f 14679 }
1da177e4
LT		 14680 free_netdev(dev);
14681 pci_release_regions(pdev);
14682 pci_disable_device(pdev);
14683 pci_set_drvdata(pdev, NULL);
14684 }
14685}
14686
14687static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14688{
14689 struct net_device *dev = pci_get_drvdata(pdev);
14690 struct tg3 *tp = netdev_priv(dev);
12dac075 14691 pci_power_t target_state;
1da177e4
LT		 14692 int err;
14693
3e0c95fd
MC		 14694 /* PCI register 4 needs to be saved whether netif_running() or not.
14695 * MSI address and data need to be saved if using MSI and
14696 * netif_running().
14697 */
14698 pci_save_state(pdev);
14699
1da177e4
LT		 14700 if (!netif_running(dev))
14701 return 0;
14702
7faa006f 14703 flush_scheduled_work();
b02fd9e3 14704 tg3_phy_stop(tp);
1da177e4
LT		 14705 tg3_netif_stop(tp);
14706
14707 del_timer_sync(&tp->timer);
14708
f47c11ee 14709 tg3_full_lock(tp, 1);
1da177e4 14710 tg3_disable_ints(tp);
f47c11ee 14711 tg3_full_unlock(tp);
1da177e4
LT		 14712
14713 netif_device_detach(dev);
14714
f47c11ee 14715 tg3_full_lock(tp, 0);
944d980e 14716 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14717 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14718 tg3_full_unlock(tp);
1da177e4 14719
12dac075
RW		 14720 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14721
14722 err = tg3_set_power_state(tp, target_state);
1da177e4 14723 if (err) {
b02fd9e3
MC		 14724 int err2;
14725
f47c11ee 14726 tg3_full_lock(tp, 0);
1da177e4 14727
6a9eba15 14728 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14729 err2 = tg3_restart_hw(tp, 1);
14730 if (err2)
b9ec6c1b 14731 goto out;
1da177e4
LT		 14732
14733 tp->timer.expires = jiffies + tp->timer_offset;
14734 add_timer(&tp->timer);
14735
14736 netif_device_attach(dev);
14737 tg3_netif_start(tp);
14738
b9ec6c1b 14739out:
f47c11ee 14740 tg3_full_unlock(tp);
b02fd9e3
MC		 14741
14742 if (!err2)
14743 tg3_phy_start(tp);
1da177e4
LT		 14744 }
14745
14746 return err;
14747}
14748
14749static int tg3_resume(struct pci_dev *pdev)
14750{
14751 struct net_device *dev = pci_get_drvdata(pdev);
14752 struct tg3 *tp = netdev_priv(dev);
14753 int err;
14754
3e0c95fd
MC		 14755 pci_restore_state(tp->pdev);
14756
1da177e4
LT		 14757 if (!netif_running(dev))
14758 return 0;
14759
bc1c7567 14760 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14761 if (err)
14762 return err;
14763
14764 netif_device_attach(dev);
14765
f47c11ee 14766 tg3_full_lock(tp, 0);
1da177e4 14767
6a9eba15 14768 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14769 err = tg3_restart_hw(tp, 1);
14770 if (err)
14771 goto out;
1da177e4
LT		 14772
14773 tp->timer.expires = jiffies + tp->timer_offset;
14774 add_timer(&tp->timer);
14775
1da177e4
LT		 14776 tg3_netif_start(tp);
14777
b9ec6c1b 14778out:
f47c11ee 14779 tg3_full_unlock(tp);
1da177e4 14780
b02fd9e3
MC		 14781 if (!err)
14782 tg3_phy_start(tp);
14783
b9ec6c1b 14784 return err;
1da177e4
LT		 14785}
14786
14787static struct pci_driver tg3_driver = {
14788 .name = DRV_MODULE_NAME,
14789 .id_table = tg3_pci_tbl,
14790 .probe = tg3_init_one,
14791 .remove = __devexit_p(tg3_remove_one),
14792 .suspend = tg3_suspend,
14793 .resume = tg3_resume
14794};
14795
14796static int __init tg3_init(void)
14797{
29917620 14798 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14799}
14800
14801static void __exit tg3_cleanup(void)
14802{
14803 pci_unregister_driver(&tg3_driver);
14804}
14805
14806module_init(tg3_init);
14807module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree