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tg3: Fix std rx prod ring handling
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
cceea982
MC		 71#define DRV_MODULE_VERSION "3.105"
72#define DRV_MODULE_RELDATE "December 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
13185217
HK		 247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254 {}
1da177e4
LT		 255};
256
257MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
50da859d 259static const struct {
1da177e4
LT		 260 const char string[ETH_GSTRING_LEN];
261} ethtool_stats_keys[TG3_NUM_STATS] = {
262 { "rx_octets" },
263 { "rx_fragments" },
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
267 { "rx_fcs_errors" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
274 { "rx_jabbers" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
288
289 { "tx_octets" },
290 { "tx_collisions" },
291
292 { "tx_xon_sent" },
293 { "tx_xoff_sent" },
294 { "tx_flow_control" },
295 { "tx_mac_errors" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
298 { "tx_deferred" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
319 { "tx_discards" },
320 { "tx_errors" },
321
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
324 { "rxbds_empty" },
325 { "rx_discards" },
326 { "rx_errors" },
327 { "rx_threshold_hit" },
328
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
332
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
335 { "nic_irqs" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
338};
339
50da859d 340static const struct {
4cafd3f5
MC		 341 const char string[ETH_GSTRING_LEN];
342} ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
349};
350
b401e9e2
MC		 351static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354}
355
356static u32 tg3_read32(struct tg3 *tp, u32 off)
357{
6aa20a22 358 return (readl(tp->regs + off));
b401e9e2
MC		 359}
360
0d3031d9
MC		 361static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->aperegs + off);
364}
365
366static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367{
368 return (readl(tp->aperegs + off));
369}
370
1da177e4
LT		 371static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372{
6892914f
MC		 373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 379}
380
381static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382{
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
1da177e4
LT		 385}
386
6892914f 387static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 388{
6892914f
MC		 389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
399static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
66711e66 408 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
1da177e4 412 }
6892914f
MC		 413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427}
428
429static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430{
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439}
440
b401e9e2
MC		 441/* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 447{
b401e9e2
MC		 448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
1da177e4
LT		 464}
465
09ee929c
MC		 466static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467{
468 tp->write32_mbox(tp, off, val);
6892914f
MC		 469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
09ee929c
MC		 472}
473
20094930 474static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 475{
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482}
483
b5d3772c
MC		 484static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485{
486 return (readl(tp->regs + off + GRCMBOX_BASE));
487}
488
489static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off + GRCMBOX_BASE);
492}
493
20094930 494#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 495#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 496#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 498#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 499
500#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 501#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 503#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 504
505static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506{
6892914f
MC		 507 unsigned long flags;
508
b5d3772c
MC		 509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511 return;
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 528}
529
1da177e4
LT		 530static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536 *val = 0;
537 return;
538 }
539
6892914f 540 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 544
bbadf503
MC		 545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 } else {
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 }
6892914f 554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 555}
556
0d3031d9
MC		 557static void tg3_ape_lock_init(struct tg3 *tp)
558{
559 int i;
560
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
565}
566
567static int tg3_ape_lock(struct tg3 *tp, int locknum)
568{
569 int i, off;
570 int ret = 0;
571 u32 status;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return 0;
575
576 switch (locknum) {
77b483f1 577 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 off = 4 * locknum;
585
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
592 break;
593 udelay(10);
594 }
595
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
600
601 ret = -EBUSY;
602 }
603
604 return ret;
605}
606
607static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608{
609 int off;
610
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612 return;
613
614 switch (locknum) {
77b483f1 615 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 616 case TG3_APE_LOCK_MEM:
617 break;
618 default:
619 return;
620 }
621
622 off = 4 * locknum;
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624}
625
1da177e4
LT		 626static void tg3_disable_ints(struct tg3 *tp)
627{
89aeb3bc
MC		 628 int i;
629
1da177e4
LT		 630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 634}
635
1da177e4
LT		 636static void tg3_enable_ints(struct tg3 *tp)
637{
89aeb3bc
MC		 638 int i;
639 u32 coal_now = 0;
640
bbe832c0
MC		 641 tp->irq_sync = 0;
642 wmb();
643
1da177e4
LT		 644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 646
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 652
89aeb3bc
MC		 653 coal_now |= tnapi->coal_now;
654 }
f19af9c2
MC		 655
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660 else
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 663}
664
17375d25 665static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 666{
17375d25 667 struct tg3 *tp = tnapi->tp;
898a56f8 668 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 669 unsigned int work_exists = 0;
670
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
676 work_exists = 1;
677 }
678 /* check for RX/TX work to do */
f3f3f27e 679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 681 work_exists = 1;
682
683 return work_exists;
684}
685
17375d25 686/* tg3_int_reenable
04237ddd
MC		 687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
6aa20a22 689 * which reenables interrupts
1da177e4 690 */
17375d25 691static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 692{
17375d25
MC		 693 struct tg3 *tp = tnapi->tp;
694
898a56f8 695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 696 mmiowb();
697
fac9b83e
DM		 698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
701 */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 703 tg3_has_work(tnapi))
04237ddd 704 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 706}
707
fed97810
MC		 708static void tg3_napi_disable(struct tg3 *tp)
709{
710 int i;
711
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
714}
715
716static void tg3_napi_enable(struct tg3 *tp)
717{
718 int i;
719
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
722}
723
1da177e4
LT		 724static inline void tg3_netif_stop(struct tg3 *tp)
725{
bbe832c0 726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 727 tg3_napi_disable(tp);
1da177e4
LT		 728 netif_tx_disable(tp->dev);
729}
730
731static inline void tg3_netif_start(struct tg3 *tp)
732{
fe5f5787
MC		 733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
1da177e4 736 */
fe5f5787
MC		 737 netif_tx_wake_all_queues(tp->dev);
738
fed97810
MC		 739 tg3_napi_enable(tp);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 741 tg3_enable_ints(tp);
1da177e4
LT		 742}
743
744static void tg3_switch_clocks(struct tg3 *tp)
745{
f6eb9b1f 746 u32 clock_ctrl;
1da177e4
LT		 747 u32 orig_clock_ctrl;
748
795d01c5
MC		 749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 751 return;
752
f6eb9b1f
MC		 753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
1da177e4
LT		 755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
758 0x1f);
759 tp->pci_clock_ctrl = clock_ctrl;
760
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 765 }
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl |
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770 40);
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
773 40);
1da177e4 774 }
b401e9e2 775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 776}
777
778#define PHY_BUSY_LOOPS 5000
779
780static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781{
782 u32 frame_val;
783 unsigned int loops;
784 int ret;
785
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787 tw32_f(MAC_MI_MODE,
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789 udelay(80);
790 }
791
792 *val = 0x0;
793
882e9793 794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 799
1da177e4
LT		 800 tw32_f(MAC_MI_COM, frame_val);
801
802 loops = PHY_BUSY_LOOPS;
803 while (loops != 0) {
804 udelay(10);
805 frame_val = tr32(MAC_MI_COM);
806
807 if ((frame_val & MI_COM_BUSY) == 0) {
808 udelay(5);
809 frame_val = tr32(MAC_MI_COM);
810 break;
811 }
812 loops -= 1;
813 }
814
815 ret = -EBUSY;
816 if (loops != 0) {
817 *val = frame_val & MI_COM_DATA_MASK;
818 ret = 0;
819 }
820
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
823 udelay(80);
824 }
825
826 return ret;
827}
828
829static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830{
831 u32 frame_val;
832 unsigned int loops;
833 int ret;
834
7f97a4bd 835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837 return 0;
838
1da177e4
LT		 839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840 tw32_f(MAC_MI_MODE,
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842 udelay(80);
843 }
844
882e9793 845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 851
1da177e4
LT		 852 tw32_f(MAC_MI_COM, frame_val);
853
854 loops = PHY_BUSY_LOOPS;
855 while (loops != 0) {
856 udelay(10);
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
859 udelay(5);
860 frame_val = tr32(MAC_MI_COM);
861 break;
862 }
863 loops -= 1;
864 }
865
866 ret = -EBUSY;
867 if (loops != 0)
868 ret = 0;
869
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
872 udelay(80);
873 }
874
875 return ret;
876}
877
95e2869a
MC		 878static int tg3_bmcr_reset(struct tg3 *tp)
879{
880 u32 phy_control;
881 int limit, err;
882
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
885 */
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
888 if (err != 0)
889 return -EBUSY;
890
891 limit = 5000;
892 while (limit--) {
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 if ((phy_control & BMCR_RESET) == 0) {
898 udelay(40);
899 break;
900 }
901 udelay(10);
902 }
d4675b52 903 if (limit < 0)
95e2869a
MC		 904 return -EBUSY;
905
906 return 0;
907}
908
158d7abd
MC		 909static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910{
3d16543d 911 struct tg3 *tp = bp->priv;
158d7abd
MC		 912 u32 val;
913
24bb4fb6 914 spin_lock_bh(&tp->lock);
158d7abd
MC		 915
916 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 917 val = -EIO;
918
919 spin_unlock_bh(&tp->lock);
158d7abd
MC		 920
921 return val;
922}
923
924static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925{
3d16543d 926 struct tg3 *tp = bp->priv;
24bb4fb6 927 u32 ret = 0;
158d7abd 928
24bb4fb6 929 spin_lock_bh(&tp->lock);
158d7abd
MC		 930
931 if (tg3_writephy(tp, reg, val))
24bb4fb6 932 ret = -EIO;
158d7abd 933
24bb4fb6
MC		 934 spin_unlock_bh(&tp->lock);
935
936 return ret;
158d7abd
MC		 937}
938
939static int tg3_mdio_reset(struct mii_bus *bp)
940{
941 return 0;
942}
943
9c61d6bc 944static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 945{
946 u32 val;
fcb389df 947 struct phy_device *phydev;
a9daf367 948
3f0e3ad7 949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
c73430d0 952 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 953 val = MAC_PHYCFG2_50610_LED_MODES;
954 break;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960 break;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963 break;
964 default:
a9daf367 965 return;
fcb389df
MC		 966 }
967
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
970
971 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 975 tw32(MAC_PHYCFG1, val);
976
977 return;
978 }
979
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
987
988 tw32(MAC_PHYCFG2, val);
a9daf367 989
bb85fbb6
MC		 990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998 }
bb85fbb6
MC		 999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
a9daf367 1002
a9daf367
MC		 1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
fcb389df 1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1021 }
1022 tw32(MAC_EXT_RGMII_MODE, val);
1023}
1024
158d7abd
MC		 1025static void tg3_mdio_start(struct tg3 *tp)
1026{
158d7abd
MC		 1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1029 udelay(80);
a9daf367 1030
882e9793
MC		 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1033
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035 if (funcnum)
1036 tp->phy_addr = 2;
1037 else
1038 tp->phy_addr = 1;
1039
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041 if (is_serdes)
1042 tp->phy_addr += 7;
1043 } else
3f0e3ad7 1044 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1045
9c61d6bc
MC		 1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
158d7abd
MC		 1049}
1050
158d7abd
MC		 1051static int tg3_mdio_init(struct tg3 *tp)
1052{
1053 int i;
1054 u32 reg;
a9daf367 1055 struct phy_device *phydev;
158d7abd
MC		 1056
1057 tg3_mdio_start(tp);
1058
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061 return 0;
1062
298cf9be
LB		 1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1065 return -ENOMEM;
158d7abd 1066
298cf9be
LB		 1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1077
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1079 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1080
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1085 */
1086 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087 tg3_bmcr_reset(tp);
1088
298cf9be 1089 i = mdiobus_register(tp->mdio_bus);
a9daf367 1090 if (i) {
158d7abd
MC		 1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092 tp->dev->name, i);
9c61d6bc 1093 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1094 return i;
1095 }
158d7abd 1096
3f0e3ad7 1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1098
9c61d6bc
MC		 1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1103 return -ENODEV;
1104 }
1105
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1110 break;
a9daf367 1111 case TG3_PHY_ID_BCM50610:
c73430d0 1112 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1114 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1123 /* fallthru */
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1126 break;
fcb389df 1127 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1132 break;
1133 }
1134
9c61d6bc
MC		 1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
a9daf367
MC		 1139
1140 return 0;
158d7abd
MC		 1141}
1142
1143static void tg3_mdio_fini(struct tg3 *tp)
1144{
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1149 }
1150}
1151
4ba526ce
MC		 1152/* tp->lock is held. */
1153static inline void tg3_generate_fw_event(struct tg3 *tp)
1154{
1155 u32 val;
1156
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161 tp->last_event_jiffies = jiffies;
1162}
1163
1164#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
95e2869a
MC		 1166/* tp->lock is held. */
1167static void tg3_wait_for_event_ack(struct tg3 *tp)
1168{
1169 int i;
4ba526ce
MC		 1170 unsigned int delay_cnt;
1171 long time_remain;
1172
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176 (long)jiffies;
1177 if (time_remain < 0)
1178 return;
1179
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1185
4ba526ce 1186 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188 break;
4ba526ce 1189 udelay(8);
95e2869a
MC		 1190 }
1191}
1192
1193/* tp->lock is held. */
1194static void tg3_ump_link_report(struct tg3 *tp)
1195{
1196 u32 reg;
1197 u32 val;
1198
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1201 return;
1202
1203 tg3_wait_for_event_ack(tp);
1204
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209 val = 0;
1210 if (!tg3_readphy(tp, MII_BMCR, &reg))
1211 val = reg << 16;
1212 if (!tg3_readphy(tp, MII_BMSR, &reg))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216 val = 0;
1217 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218 val = reg << 16;
1219 if (!tg3_readphy(tp, MII_LPA, &reg))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223 val = 0;
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226 val = reg << 16;
1227 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228 val |= (reg & 0xffff);
1229 }
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233 val = reg << 16;
1234 else
1235 val = 0;
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
4ba526ce 1238 tg3_generate_fw_event(tp);
95e2869a
MC		 1239}
1240
1241static void tg3_link_report(struct tg3 *tp)
1242{
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1246 tp->dev->name);
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250 tp->dev->name,
1251 (tp->link_config.active_speed == SPEED_1000 ?
1252 1000 :
1253 (tp->link_config.active_speed == SPEED_100 ?
1254 100 : 10)),
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1256 "full" : "half"));
1257
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1260 tp->dev->name,
e18ce346 1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1262 "on" : "off",
e18ce346 1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1264 "on" : "off");
1265 tg3_ump_link_report(tp);
1266 }
1267}
1268
1269static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270{
1271 u16 miireg;
1272
e18ce346 1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1274 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1275 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1276 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1277 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279 else
1280 miireg = 0;
1281
1282 return miireg;
1283}
1284
1285static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286{
1287 u16 miireg;
1288
e18ce346 1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1290 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1291 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1292 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1293 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295 else
1296 miireg = 0;
1297
1298 return miireg;
1299}
1300
95e2869a
MC		 1301static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302{
1303 u8 cap = 0;
1304
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1310 cap = FLOW_CTRL_RX;
95e2869a
MC		 1311 } else {
1312 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1314 }
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1317 cap = FLOW_CTRL_TX;
95e2869a
MC		 1318 }
1319
1320 return cap;
1321}
1322
f51f3562 1323static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1324{
b02fd9e3 1325 u8 autoneg;
f51f3562 1326 u8 flowctrl = 0;
95e2869a
MC		 1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1329
b02fd9e3 1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1332 else
1333 autoneg = tp->link_config.autoneg;
1334
1335 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1339 else
bc02ff95 1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1341 } else
1342 flowctrl = tp->link_config.flowctrl;
95e2869a 1343
f51f3562 1344 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1345
e18ce346 1346 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348 else
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
f51f3562 1351 if (old_rx_mode != tp->rx_mode)
95e2869a 1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1353
e18ce346 1354 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356 else
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
f51f3562 1359 if (old_tx_mode != tp->tx_mode)
95e2869a 1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1361}
1362
b02fd9e3
MC		 1363static void tg3_adjust_link(struct net_device *dev)
1364{
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1369
24bb4fb6 1370 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1371
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1374
1375 oldflowctrl = tp->link_config.active_flowctrl;
1376
1377 if (phydev->link) {
1378 lcl_adv = 0;
1379 rmt_adv = 0;
1380
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1386 else
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1388
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1391 else {
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1394
1395 if (phydev->pause)
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1399 }
1400
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402 } else
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1408 udelay(40);
1409 }
1410
fcb389df
MC		 1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1413 tw32(MAC_MI_STAT,
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416 else
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418 }
1419
b02fd9e3
MC		 1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425 else
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1436 linkmesg = 1;
1437
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1440
24bb4fb6 1441 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1442
1443 if (linkmesg)
1444 tg3_link_report(tp);
1445}
1446
1447static int tg3_phy_init(struct tg3 *tp)
1448{
1449 struct phy_device *phydev;
1450
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452 return 0;
1453
1454 /* Bring the PHY back to a known state. */
1455 tg3_bmcr_reset(tp);
1456
3f0e3ad7 1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1458
1459 /* Attach the MAC to the PHY. */
fb28ad35 1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1461 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1465 }
1466
b02fd9e3 1467 /* Mask with MAC supported features. */
9c61d6bc
MC		 1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1473 SUPPORTED_Pause |
1474 SUPPORTED_Asym_Pause);
1475 break;
1476 }
1477 /* fallthru */
9c61d6bc
MC		 1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 default:
3f0e3ad7 1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1485 return -EINVAL;
1486 }
1487
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1489
1490 phydev->advertising = phydev->supported;
1491
b02fd9e3
MC		 1492 return 0;
1493}
1494
1495static void tg3_phy_start(struct tg3 *tp)
1496{
1497 struct phy_device *phydev;
1498
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1503
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1510 }
1511
1512 phy_start(phydev);
1513
1514 phy_start_aneg(phydev);
1515}
1516
1517static void tg3_phy_stop(struct tg3 *tp)
1518{
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520 return;
1521
3f0e3ad7 1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1523}
1524
1525static void tg3_phy_fini(struct tg3 *tp)
1526{
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530 }
1531}
1532
b2a5c19c
MC		 1533static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534{
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537}
1538
7f97a4bd
MC		 1539static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 phytest;
1542
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544 u32 phy;
1545
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549 if (enable)
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551 else
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554 }
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556 }
1557}
1558
6833c043
MC		 1559static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560{
1561 u32 reg;
1562
7f97a4bd 1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1564 return;
1565
7f97a4bd
MC		 1566 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567 tg3_phy_fet_toggle_apd(tp, enable);
1568 return;
1569 }
1570
6833c043
MC		 1571 reg = MII_TG3_MISC_SHDW_WREN |
1572 MII_TG3_MISC_SHDW_SCR5_SEL |
1573 MII_TG3_MISC_SHDW_SCR5_LPED |
1574 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575 MII_TG3_MISC_SHDW_SCR5_SDTL |
1576 MII_TG3_MISC_SHDW_SCR5_C125OE;
1577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1579
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581
1582
1583 reg = MII_TG3_MISC_SHDW_WREN |
1584 MII_TG3_MISC_SHDW_APD_SEL |
1585 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1586 if (enable)
1587 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1588
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590}
1591
9ef8ca99
MC		 1592static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1593{
1594 u32 phy;
1595
1596 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1598 return;
1599
7f97a4bd 1600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1601 u32 ephy;
1602
535ef6e1
MC		 1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1605
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 ephy | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1609 if (enable)
535ef6e1 1610 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1611 else
535ef6e1
MC		 1612 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613 tg3_writephy(tp, reg, phy);
9ef8ca99 1614 }
535ef6e1 1615 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1616 }
1617 } else {
1618 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619 MII_TG3_AUXCTL_SHDWSEL_MISC;
1620 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1622 if (enable)
1623 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1624 else
1625 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 phy |= MII_TG3_AUXCTL_MISC_WREN;
1627 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1628 }
1629 }
1630}
1631
1da177e4
LT		 1632static void tg3_phy_set_wirespeed(struct tg3 *tp)
1633{
1634 u32 val;
1635
1636 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1637 return;
1638
1639 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642 (val | (1 << 15) | (1 << 4)));
1643}
1644
b2a5c19c
MC		 1645static void tg3_phy_apply_otp(struct tg3 *tp)
1646{
1647 u32 otp, phy;
1648
1649 if (!tp->phy_otp)
1650 return;
1651
1652 otp = tp->phy_otp;
1653
1654 /* Enable SM_DSP clock and tx 6dB coding. */
1655 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657 MII_TG3_AUXCTL_ACTL_TX_6DB;
1658 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659
1660 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1663
1664 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1667
1668 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1671
1672 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1674
1675 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1677
1678 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1681
1682 /* Turn off SM_DSP clock. */
1683 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686}
1687
1da177e4
LT		 1688static int tg3_wait_macro_done(struct tg3 *tp)
1689{
1690 int limit = 100;
1691
1692 while (limit--) {
1693 u32 tmp32;
1694
1695 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696 if ((tmp32 & 0x1000) == 0)
1697 break;
1698 }
1699 }
d4675b52 1700 if (limit < 0)
1da177e4
LT		 1701 return -EBUSY;
1702
1703 return 0;
1704}
1705
1706static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1707{
1708 static const u32 test_pat[4][6] = {
1709 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1713 };
1714 int chan;
1715
1716 for (chan = 0; chan < 4; chan++) {
1717 int i;
1718
1719 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720 (chan * 0x2000) | 0x0200);
1721 tg3_writephy(tp, 0x16, 0x0002);
1722
1723 for (i = 0; i < 6; i++)
1724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1725 test_pat[chan][i]);
1726
1727 tg3_writephy(tp, 0x16, 0x0202);
1728 if (tg3_wait_macro_done(tp)) {
1729 *resetp = 1;
1730 return -EBUSY;
1731 }
1732
1733 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734 (chan * 0x2000) | 0x0200);
1735 tg3_writephy(tp, 0x16, 0x0082);
1736 if (tg3_wait_macro_done(tp)) {
1737 *resetp = 1;
1738 return -EBUSY;
1739 }
1740
1741 tg3_writephy(tp, 0x16, 0x0802);
1742 if (tg3_wait_macro_done(tp)) {
1743 *resetp = 1;
1744 return -EBUSY;
1745 }
1746
1747 for (i = 0; i < 6; i += 2) {
1748 u32 low, high;
1749
1750 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752 tg3_wait_macro_done(tp)) {
1753 *resetp = 1;
1754 return -EBUSY;
1755 }
1756 low &= 0x7fff;
1757 high &= 0x000f;
1758 if (low != test_pat[chan][i] ||
1759 high != test_pat[chan][i+1]) {
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1763
1764 return -EBUSY;
1765 }
1766 }
1767 }
1768
1769 return 0;
1770}
1771
1772static int tg3_phy_reset_chanpat(struct tg3 *tp)
1773{
1774 int chan;
1775
1776 for (chan = 0; chan < 4; chan++) {
1777 int i;
1778
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780 (chan * 0x2000) | 0x0200);
1781 tg3_writephy(tp, 0x16, 0x0002);
1782 for (i = 0; i < 6; i++)
1783 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784 tg3_writephy(tp, 0x16, 0x0202);
1785 if (tg3_wait_macro_done(tp))
1786 return -EBUSY;
1787 }
1788
1789 return 0;
1790}
1791
1792static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1793{
1794 u32 reg32, phy9_orig;
1795 int retries, do_phy_reset, err;
1796
1797 retries = 10;
1798 do_phy_reset = 1;
1799 do {
1800 if (do_phy_reset) {
1801 err = tg3_bmcr_reset(tp);
1802 if (err)
1803 return err;
1804 do_phy_reset = 0;
1805 }
1806
1807 /* Disable transmitter and interrupt. */
1808 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1809 continue;
1810
1811 reg32 |= 0x3000;
1812 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1813
1814 /* Set full-duplex, 1000 mbps. */
1815 tg3_writephy(tp, MII_BMCR,
1816 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1817
1818 /* Set to master mode. */
1819 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1820 continue;
1821
1822 tg3_writephy(tp, MII_TG3_CTRL,
1823 (MII_TG3_CTRL_AS_MASTER |
1824 MII_TG3_CTRL_ENABLE_AS_MASTER));
1825
1826 /* Enable SM_DSP_CLOCK and 6dB. */
1827 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1828
1829 /* Block the PHY control access. */
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1832
1833 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1834 if (!err)
1835 break;
1836 } while (--retries);
1837
1838 err = tg3_phy_reset_chanpat(tp);
1839 if (err)
1840 return err;
1841
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1844
1845 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846 tg3_writephy(tp, 0x16, 0x0000);
1847
1848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850 /* Set Extended packet length bit for jumbo frames */
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1852 }
1853 else {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1855 }
1856
1857 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1858
1859 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1860 reg32 &= ~0x3000;
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1862 } else if (!err)
1863 err = -EBUSY;
1864
1865 return err;
1866}
1867
1868/* This will reset the tigon3 PHY if there is no valid
1869 * link unless the FORCE argument is non-zero.
1870 */
1871static int tg3_phy_reset(struct tg3 *tp)
1872{
b2a5c19c 1873 u32 cpmuctrl;
1da177e4
LT		 1874 u32 phy_status;
1875 int err;
1876
60189ddf
MC		 1877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1878 u32 val;
1879
1880 val = tr32(GRC_MISC_CFG);
1881 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1882 udelay(40);
1883 }
1da177e4
LT		 1884 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1885 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1886 if (err != 0)
1887 return -EBUSY;
1888
c8e1e82b
MC		 1889 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890 netif_carrier_off(tp->dev);
1891 tg3_link_report(tp);
1892 }
1893
1da177e4
LT		 1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897 err = tg3_phy_reset_5703_4_5(tp);
1898 if (err)
1899 return err;
1900 goto out;
1901 }
1902
b2a5c19c
MC		 1903 cpmuctrl = 0;
1904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1908 tw32(TG3_CPMU_CTRL,
1909 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1910 }
1911
1da177e4
LT		 1912 err = tg3_bmcr_reset(tp);
1913 if (err)
1914 return err;
1915
b2a5c19c
MC		 1916 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1917 u32 phy;
1918
1919 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1921
1922 tw32(TG3_CPMU_CTRL, cpmuctrl);
1923 }
1924
bcb37f6c
MC		 1925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1927 u32 val;
1928
1929 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931 CPMU_LSPD_1000MB_MACCLK_12_5) {
1932 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1933 udelay(40);
1934 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1935 }
1936 }
1937
b2a5c19c
MC		 1938 tg3_phy_apply_otp(tp);
1939
6833c043
MC		 1940 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941 tg3_phy_toggle_apd(tp, true);
1942 else
1943 tg3_phy_toggle_apd(tp, false);
1944
1da177e4
LT		 1945out:
1946 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953 }
1954 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955 tg3_writephy(tp, 0x1c, 0x8d68);
1956 tg3_writephy(tp, 0x1c, 0x8d68);
1957 }
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1967 }
c424cb24
MC		 1968 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973 tg3_writephy(tp, MII_TG3_TEST1,
1974 MII_TG3_TEST1_TRIM_EN | 0x4);
1975 } else
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1978 }
1da177e4
LT		 1979 /* Set Extended packet length bit (bit 14) on all chips that */
1980 /* support jumbo frames */
1981 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982 /* Cannot do read-modify-write on 5401 */
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1984 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1985 u32 phy_reg;
1986
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1991 }
1992
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1995 */
8f666b07 1996 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1997 u32 phy_reg;
1998
1999 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002 }
2003
715116a1 2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2005 /* adjust output voltage */
535ef6e1 2006 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2007 }
2008
9ef8ca99 2009 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2010 tg3_phy_set_wirespeed(tp);
2011 return 0;
2012}
2013
2014static void tg3_frob_aux_power(struct tg3 *tp)
2015{
2016 struct tg3 *tp_peer = tp;
2017
9d26e213 2018 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2019 return;
2020
f6eb9b1f
MC		 2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2024 struct net_device *dev_peer;
2025
2026 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2027 /* remove_one() may have been run on the peer. */
8c2dc7e1 2028 if (!dev_peer)
bc1c7567
MC		 2029 tp_peer = tp;
2030 else
2031 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2032 }
2033
1da177e4 2034 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2035 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 (GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1),
2046 100);
8d519ab2
MC		 2047 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2049 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051 GRC_LCLCTRL_GPIO_OE1 |
2052 GRC_LCLCTRL_GPIO_OE2 |
2053 GRC_LCLCTRL_GPIO_OUTPUT0 |
2054 GRC_LCLCTRL_GPIO_OUTPUT1 |
2055 tp->grc_local_ctrl;
2056 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060
2061 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2063 } else {
2064 u32 no_gpio2;
dc56b7d4 2065 u32 grc_local_ctrl = 0;
1da177e4
LT		 2066
2067 if (tp_peer != tp &&
2068 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2069 return;
2070
dc56b7d4
MC		 2071 /* Workaround to prevent overdrawing Amps. */
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2073 ASIC_REV_5714) {
2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2075 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076 grc_local_ctrl, 100);
dc56b7d4
MC		 2077 }
2078
1da177e4
LT		 2079 /* On 5753 and variants, GPIO2 cannot be used. */
2080 no_gpio2 = tp->nic_sram_data_cfg &
2081 NIC_SRAM_DATA_CFG_NO_GPIO2;
2082
dc56b7d4 2083 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2084 GRC_LCLCTRL_GPIO_OE1 |
2085 GRC_LCLCTRL_GPIO_OE2 |
2086 GRC_LCLCTRL_GPIO_OUTPUT1 |
2087 GRC_LCLCTRL_GPIO_OUTPUT2;
2088 if (no_gpio2) {
2089 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090 GRC_LCLCTRL_GPIO_OUTPUT2);
2091 }
b401e9e2
MC		 2092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093 grc_local_ctrl, 100);
1da177e4
LT		 2094
2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2096
b401e9e2
MC		 2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 grc_local_ctrl, 100);
1da177e4
LT		 2099
2100 if (!no_gpio2) {
2101 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2102 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103 grc_local_ctrl, 100);
1da177e4
LT		 2104 }
2105 }
2106 } else {
2107 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109 if (tp_peer != tp &&
2110 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2111 return;
2112
b401e9e2
MC		 2113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114 (GRC_LCLCTRL_GPIO_OE1 |
2115 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2116
b401e9e2
MC		 2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2119
b401e9e2
MC		 2120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121 (GRC_LCLCTRL_GPIO_OE1 |
2122 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2123 }
2124 }
2125}
2126
e8f3f6ca
MC		 2127static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2128{
2129 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2130 return 1;
2131 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132 if (speed != SPEED_10)
2133 return 1;
2134 } else if (speed == SPEED_10)
2135 return 1;
2136
2137 return 0;
2138}
2139
1da177e4
LT		 2140static int tg3_setup_phy(struct tg3 *, int);
2141
2142#define RESET_KIND_SHUTDOWN 0
2143#define RESET_KIND_INIT 1
2144#define RESET_KIND_SUSPEND 2
2145
2146static void tg3_write_sig_post_reset(struct tg3 *, int);
2147static int tg3_halt_cpu(struct tg3 *, u32);
2148
0a459aac 2149static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2150{
ce057f01
MC		 2151 u32 val;
2152
5129724a
MC		 2153 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2157
2158 sg_dig_ctrl |=
2159 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2162 }
3f7045c1 2163 return;
5129724a 2164 }
3f7045c1 2165
60189ddf 2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2167 tg3_bmcr_reset(tp);
2168 val = tr32(GRC_MISC_CFG);
2169 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2170 udelay(40);
2171 return;
0e5f784c
MC		 2172 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2173 u32 phytest;
2174 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2175 u32 phy;
2176
2177 tg3_writephy(tp, MII_ADVERTISE, 0);
2178 tg3_writephy(tp, MII_BMCR,
2179 BMCR_ANENABLE | BMCR_ANRESTART);
2180
2181 tg3_writephy(tp, MII_TG3_FET_TEST,
2182 phytest | MII_TG3_FET_SHADOW_EN);
2183 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2185 tg3_writephy(tp,
2186 MII_TG3_FET_SHDW_AUXMODE4,
2187 phy);
2188 }
2189 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2190 }
2191 return;
0a459aac 2192 } else if (do_low_power) {
715116a1
MC		 2193 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2195
2196 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2201 }
3f7045c1 2202
15c3b696
MC		 2203 /* The PHY should not be powered down on some chips because
2204 * of bugs.
2205 */
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2210 return;
ce057f01 2211
bcb37f6c
MC		 2212 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2214 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2218 }
2219
15c3b696
MC		 2220 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2221}
2222
ffbcfed4
MC		 2223/* tp->lock is held. */
2224static int tg3_nvram_lock(struct tg3 *tp)
2225{
2226 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2227 int i;
2228
2229 if (tp->nvram_lock_cnt == 0) {
2230 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231 for (i = 0; i < 8000; i++) {
2232 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2233 break;
2234 udelay(20);
2235 }
2236 if (i == 8000) {
2237 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2238 return -ENODEV;
2239 }
2240 }
2241 tp->nvram_lock_cnt++;
2242 }
2243 return 0;
2244}
2245
2246/* tp->lock is held. */
2247static void tg3_nvram_unlock(struct tg3 *tp)
2248{
2249 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250 if (tp->nvram_lock_cnt > 0)
2251 tp->nvram_lock_cnt--;
2252 if (tp->nvram_lock_cnt == 0)
2253 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2254 }
2255}
2256
2257/* tp->lock is held. */
2258static void tg3_enable_nvram_access(struct tg3 *tp)
2259{
2260 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2261 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2262 u32 nvaccess = tr32(NVRAM_ACCESS);
2263
2264 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2265 }
2266}
2267
2268/* tp->lock is held. */
2269static void tg3_disable_nvram_access(struct tg3 *tp)
2270{
2271 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2272 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2273 u32 nvaccess = tr32(NVRAM_ACCESS);
2274
2275 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2276 }
2277}
2278
2279static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280 u32 offset, u32 *val)
2281{
2282 u32 tmp;
2283 int i;
2284
2285 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2286 return -EINVAL;
2287
2288 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289 EEPROM_ADDR_DEVID_MASK |
2290 EEPROM_ADDR_READ);
2291 tw32(GRC_EEPROM_ADDR,
2292 tmp |
2293 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295 EEPROM_ADDR_ADDR_MASK) |
2296 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2297
2298 for (i = 0; i < 1000; i++) {
2299 tmp = tr32(GRC_EEPROM_ADDR);
2300
2301 if (tmp & EEPROM_ADDR_COMPLETE)
2302 break;
2303 msleep(1);
2304 }
2305 if (!(tmp & EEPROM_ADDR_COMPLETE))
2306 return -EBUSY;
2307
62cedd11
MC		 2308 tmp = tr32(GRC_EEPROM_DATA);
2309
2310 /*
2311 * The data will always be opposite the native endian
2312 * format. Perform a blind byteswap to compensate.
2313 */
2314 *val = swab32(tmp);
2315
ffbcfed4
MC		 2316 return 0;
2317}
2318
2319#define NVRAM_CMD_TIMEOUT 10000
2320
2321static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2322{
2323 int i;
2324
2325 tw32(NVRAM_CMD, nvram_cmd);
2326 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2327 udelay(10);
2328 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2329 udelay(10);
2330 break;
2331 }
2332 }
2333
2334 if (i == NVRAM_CMD_TIMEOUT)
2335 return -EBUSY;
2336
2337 return 0;
2338}
2339
2340static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2341{
2342 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346 (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348 addr = ((addr / tp->nvram_pagesize) <<
2349 ATMEL_AT45DB0X1B_PAGE_POS) +
2350 (addr % tp->nvram_pagesize);
2351
2352 return addr;
2353}
2354
2355static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2356{
2357 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361 (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364 tp->nvram_pagesize) +
2365 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2366
2367 return addr;
2368}
2369
e4f34110
MC		 2370/* NOTE: Data read in from NVRAM is byteswapped according to
2371 * the byteswapping settings for all other register accesses.
2372 * tg3 devices are BE devices, so on a BE machine, the data
2373 * returned will be exactly as it is seen in NVRAM. On a LE
2374 * machine, the 32-bit value will be byteswapped.
2375 */
ffbcfed4
MC		 2376static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2377{
2378 int ret;
2379
2380 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381 return tg3_nvram_read_using_eeprom(tp, offset, val);
2382
2383 offset = tg3_nvram_phys_addr(tp, offset);
2384
2385 if (offset > NVRAM_ADDR_MSK)
2386 return -EINVAL;
2387
2388 ret = tg3_nvram_lock(tp);
2389 if (ret)
2390 return ret;
2391
2392 tg3_enable_nvram_access(tp);
2393
2394 tw32(NVRAM_ADDR, offset);
2395 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2397
2398 if (ret == 0)
e4f34110 2399 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2400
2401 tg3_disable_nvram_access(tp);
2402
2403 tg3_nvram_unlock(tp);
2404
2405 return ret;
2406}
2407
a9dc529d
MC		 2408/* Ensures NVRAM data is in bytestream format. */
2409static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2410{
2411 u32 v;
a9dc529d 2412 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2413 if (!res)
a9dc529d 2414 *val = cpu_to_be32(v);
ffbcfed4
MC		 2415 return res;
2416}
2417
3f007891
MC		 2418/* tp->lock is held. */
2419static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2420{
2421 u32 addr_high, addr_low;
2422 int i;
2423
2424 addr_high = ((tp->dev->dev_addr[0] << 8) |
2425 tp->dev->dev_addr[1]);
2426 addr_low = ((tp->dev->dev_addr[2] << 24) |
2427 (tp->dev->dev_addr[3] << 16) |
2428 (tp->dev->dev_addr[4] << 8) |
2429 (tp->dev->dev_addr[5] << 0));
2430 for (i = 0; i < 4; i++) {
2431 if (i == 1 && skip_mac_1)
2432 continue;
2433 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2435 }
2436
2437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439 for (i = 0; i < 12; i++) {
2440 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2442 }
2443 }
2444
2445 addr_high = (tp->dev->dev_addr[0] +
2446 tp->dev->dev_addr[1] +
2447 tp->dev->dev_addr[2] +
2448 tp->dev->dev_addr[3] +
2449 tp->dev->dev_addr[4] +
2450 tp->dev->dev_addr[5]) &
2451 TX_BACKOFF_SEED_MASK;
2452 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2453}
2454
bc1c7567 2455static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2456{
2457 u32 misc_host_ctrl;
0a459aac 2458 bool device_should_wake, do_low_power;
1da177e4
LT		 2459
2460 /* Make sure register accesses (indirect or otherwise)
2461 * will function correctly.
2462 */
2463 pci_write_config_dword(tp->pdev,
2464 TG3PCI_MISC_HOST_CTRL,
2465 tp->misc_host_ctrl);
2466
1da177e4 2467 switch (state) {
bc1c7567 2468 case PCI_D0:
12dac075
RW		 2469 pci_enable_wake(tp->pdev, state, false);
2470 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2471
9d26e213
MC		 2472 /* Switch out of Vaux if it is a NIC */
2473 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2474 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2475
2476 return 0;
2477
bc1c7567 2478 case PCI_D1:
bc1c7567 2479 case PCI_D2:
bc1c7567 2480 case PCI_D3hot:
1da177e4
LT		 2481 break;
2482
2483 default:
12dac075
RW		 2484 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485 tp->dev->name, state);
1da177e4 2486 return -EINVAL;
855e1111 2487 }
5e7dfd0f
MC		 2488
2489 /* Restore the CLKREQ setting. */
2490 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2491 u16 lnkctl;
2492
2493 pci_read_config_word(tp->pdev,
2494 tp->pcie_cap + PCI_EXP_LNKCTL,
2495 &lnkctl);
2496 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497 pci_write_config_word(tp->pdev,
2498 tp->pcie_cap + PCI_EXP_LNKCTL,
2499 lnkctl);
2500 }
2501
1da177e4
LT		 2502 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503 tw32(TG3PCI_MISC_HOST_CTRL,
2504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2505
05ac4cb7
MC		 2506 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507 device_may_wakeup(&tp->pdev->dev) &&
2508 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2509
dd477003 2510 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2511 do_low_power = false;
b02fd9e3
MC		 2512 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513 !tp->link_config.phy_is_low_power) {
2514 struct phy_device *phydev;
0a459aac 2515 u32 phyid, advertising;
b02fd9e3 2516
3f0e3ad7 2517 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2518
2519 tp->link_config.phy_is_low_power = 1;
2520
2521 tp->link_config.orig_speed = phydev->speed;
2522 tp->link_config.orig_duplex = phydev->duplex;
2523 tp->link_config.orig_autoneg = phydev->autoneg;
2524 tp->link_config.orig_advertising = phydev->advertising;
2525
2526 advertising = ADVERTISED_TP |
2527 ADVERTISED_Pause |
2528 ADVERTISED_Autoneg |
2529 ADVERTISED_10baseT_Half;
2530
2531 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2532 device_should_wake) {
b02fd9e3
MC		 2533 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2534 advertising |=
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full |
2537 ADVERTISED_10baseT_Full;
2538 else
2539 advertising |= ADVERTISED_10baseT_Full;
2540 }
2541
2542 phydev->advertising = advertising;
2543
2544 phy_start_aneg(phydev);
0a459aac
MC		 2545
2546 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547 if (phyid != TG3_PHY_ID_BCMAC131) {
2548 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2549 if (phyid == TG3_PHY_OUI_1 ||
2550 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2551 phyid == TG3_PHY_OUI_3)
2552 do_low_power = true;
2553 }
b02fd9e3 2554 }
dd477003 2555 } else {
2023276e 2556 do_low_power = true;
0a459aac 2557
dd477003
MC		 2558 if (tp->link_config.phy_is_low_power == 0) {
2559 tp->link_config.phy_is_low_power = 1;
2560 tp->link_config.orig_speed = tp->link_config.speed;
2561 tp->link_config.orig_duplex = tp->link_config.duplex;
2562 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2563 }
1da177e4 2564
dd477003
MC		 2565 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566 tp->link_config.speed = SPEED_10;
2567 tp->link_config.duplex = DUPLEX_HALF;
2568 tp->link_config.autoneg = AUTONEG_ENABLE;
2569 tg3_setup_phy(tp, 0);
2570 }
1da177e4
LT		 2571 }
2572
b5d3772c
MC		 2573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2574 u32 val;
2575
2576 val = tr32(GRC_VCPU_EXT_CTRL);
2577 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2579 int i;
2580 u32 val;
2581
2582 for (i = 0; i < 200; i++) {
2583 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2585 break;
2586 msleep(1);
2587 }
2588 }
a85feb8c
GZ		 2589 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591 WOL_DRV_STATE_SHUTDOWN |
2592 WOL_DRV_WOL |
2593 WOL_SET_MAGIC_PKT);
6921d201 2594
05ac4cb7 2595 if (device_should_wake) {
1da177e4
LT		 2596 u32 mac_mode;
2597
2598 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2599 if (do_low_power) {
dd477003
MC		 2600 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2601 udelay(40);
2602 }
1da177e4 2603
3f7045c1
MC		 2604 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605 mac_mode = MAC_MODE_PORT_MODE_GMII;
2606 else
2607 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2608
e8f3f6ca
MC		 2609 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2611 ASIC_REV_5700) {
2612 u32 speed = (tp->tg3_flags &
2613 TG3_FLAG_WOL_SPEED_100MB) ?
2614 SPEED_100 : SPEED_10;
2615 if (tg3_5700_link_polarity(tp, speed))
2616 mac_mode |= MAC_MODE_LINK_POLARITY;
2617 else
2618 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2619 }
1da177e4
LT		 2620 } else {
2621 mac_mode = MAC_MODE_PORT_MODE_TBI;
2622 }
2623
cbf46853 2624 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2625 tw32(MAC_LED_CTRL, tp->led_ctrl);
2626
05ac4cb7
MC		 2627 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2633
3bda1258
MC		 2634 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635 mac_mode |= tp->mac_mode &
2636 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637 if (mac_mode & MAC_MODE_APE_TX_EN)
2638 mac_mode |= MAC_MODE_TDE_ENABLE;
2639 }
2640
1da177e4
LT		 2641 tw32_f(MAC_MODE, mac_mode);
2642 udelay(100);
2643
2644 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2645 udelay(10);
2646 }
2647
2648 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2651 u32 base_val;
2652
2653 base_val = tp->pci_clock_ctrl;
2654 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655 CLOCK_CTRL_TXCLK_DISABLE);
2656
b401e9e2
MC		 2657 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2659 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2660 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2662 /* do nothing */
85e94ced 2663 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2664 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665 u32 newbits1, newbits2;
2666
2667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670 CLOCK_CTRL_TXCLK_DISABLE |
2671 CLOCK_CTRL_ALTCLK);
2672 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674 newbits1 = CLOCK_CTRL_625_CORE;
2675 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2676 } else {
2677 newbits1 = CLOCK_CTRL_ALTCLK;
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679 }
2680
b401e9e2
MC		 2681 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2682 40);
1da177e4 2683
b401e9e2
MC		 2684 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2685 40);
1da177e4
LT		 2686
2687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2688 u32 newbits3;
2689
2690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693 CLOCK_CTRL_TXCLK_DISABLE |
2694 CLOCK_CTRL_44MHZ_CORE);
2695 } else {
2696 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2697 }
2698
b401e9e2
MC		 2699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2701 }
2702 }
2703
05ac4cb7 2704 if (!(device_should_wake) &&
22435849 2705 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2706 tg3_power_down_phy(tp, do_low_power);
6921d201 2707
1da177e4
LT		 2708 tg3_frob_aux_power(tp);
2709
2710 /* Workaround for unstable PLL clock */
2711 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713 u32 val = tr32(0x7d00);
2714
2715 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2716 tw32(0x7d00, val);
6921d201 2717 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2718 int err;
2719
2720 err = tg3_nvram_lock(tp);
1da177e4 2721 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2722 if (!err)
2723 tg3_nvram_unlock(tp);
6921d201 2724 }
1da177e4
LT		 2725 }
2726
bbadf503
MC		 2727 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2728
05ac4cb7 2729 if (device_should_wake)
12dac075
RW		 2730 pci_enable_wake(tp->pdev, state, true);
2731
1da177e4 2732 /* Finally, set the new power state. */
12dac075 2733 pci_set_power_state(tp->pdev, state);
1da177e4 2734
1da177e4
LT		 2735 return 0;
2736}
2737
1da177e4
LT		 2738static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2739{
2740 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741 case MII_TG3_AUX_STAT_10HALF:
2742 *speed = SPEED_10;
2743 *duplex = DUPLEX_HALF;
2744 break;
2745
2746 case MII_TG3_AUX_STAT_10FULL:
2747 *speed = SPEED_10;
2748 *duplex = DUPLEX_FULL;
2749 break;
2750
2751 case MII_TG3_AUX_STAT_100HALF:
2752 *speed = SPEED_100;
2753 *duplex = DUPLEX_HALF;
2754 break;
2755
2756 case MII_TG3_AUX_STAT_100FULL:
2757 *speed = SPEED_100;
2758 *duplex = DUPLEX_FULL;
2759 break;
2760
2761 case MII_TG3_AUX_STAT_1000HALF:
2762 *speed = SPEED_1000;
2763 *duplex = DUPLEX_HALF;
2764 break;
2765
2766 case MII_TG3_AUX_STAT_1000FULL:
2767 *speed = SPEED_1000;
2768 *duplex = DUPLEX_FULL;
2769 break;
2770
2771 default:
7f97a4bd 2772 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2773 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2774 SPEED_10;
2775 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2776 DUPLEX_HALF;
2777 break;
2778 }
1da177e4
LT		 2779 *speed = SPEED_INVALID;
2780 *duplex = DUPLEX_INVALID;
2781 break;
855e1111 2782 }
1da177e4
LT		 2783}
2784
2785static void tg3_phy_copper_begin(struct tg3 *tp)
2786{
2787 u32 new_adv;
2788 int i;
2789
2790 if (tp->link_config.phy_is_low_power) {
2791 /* Entering low power mode. Disable gigabit and
2792 * 100baseT advertisements.
2793 */
2794 tg3_writephy(tp, MII_TG3_CTRL, 0);
2795
2796 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2800
2801 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2803 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804 tp->link_config.advertising &=
2805 ~(ADVERTISED_1000baseT_Half |
2806 ADVERTISED_1000baseT_Full);
2807
ba4d07a8 2808 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2809 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810 new_adv |= ADVERTISE_10HALF;
2811 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812 new_adv |= ADVERTISE_10FULL;
2813 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814 new_adv |= ADVERTISE_100HALF;
2815 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2817
2818 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2819
1da177e4
LT		 2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822 if (tp->link_config.advertising &
2823 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2824 new_adv = 0;
2825 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833 MII_TG3_CTRL_ENABLE_AS_MASTER);
2834 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2835 } else {
2836 tg3_writephy(tp, MII_TG3_CTRL, 0);
2837 }
2838 } else {
ba4d07a8
MC		 2839 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840 new_adv |= ADVERTISE_CSMA;
2841
1da177e4
LT		 2842 /* Asking for a specific link mode. */
2843 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2844 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2845
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2848 else
2849 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2854 } else {
1da177e4
LT		 2855 if (tp->link_config.speed == SPEED_100) {
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 new_adv |= ADVERTISE_100FULL;
2858 else
2859 new_adv |= ADVERTISE_100HALF;
2860 } else {
2861 if (tp->link_config.duplex == DUPLEX_FULL)
2862 new_adv |= ADVERTISE_10FULL;
2863 else
2864 new_adv |= ADVERTISE_10HALF;
2865 }
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2867
2868 new_adv = 0;
1da177e4 2869 }
ba4d07a8
MC		 2870
2871 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2872 }
2873
2874 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875 tp->link_config.speed != SPEED_INVALID) {
2876 u32 bmcr, orig_bmcr;
2877
2878 tp->link_config.active_speed = tp->link_config.speed;
2879 tp->link_config.active_duplex = tp->link_config.duplex;
2880
2881 bmcr = 0;
2882 switch (tp->link_config.speed) {
2883 default:
2884 case SPEED_10:
2885 break;
2886
2887 case SPEED_100:
2888 bmcr |= BMCR_SPEED100;
2889 break;
2890
2891 case SPEED_1000:
2892 bmcr |= TG3_BMCR_SPEED1000;
2893 break;
855e1111 2894 }
1da177e4
LT		 2895
2896 if (tp->link_config.duplex == DUPLEX_FULL)
2897 bmcr |= BMCR_FULLDPLX;
2898
2899 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900 (bmcr != orig_bmcr)) {
2901 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902 for (i = 0; i < 1500; i++) {
2903 u32 tmp;
2904
2905 udelay(10);
2906 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907 tg3_readphy(tp, MII_BMSR, &tmp))
2908 continue;
2909 if (!(tmp & BMSR_LSTATUS)) {
2910 udelay(40);
2911 break;
2912 }
2913 }
2914 tg3_writephy(tp, MII_BMCR, bmcr);
2915 udelay(40);
2916 }
2917 } else {
2918 tg3_writephy(tp, MII_BMCR,
2919 BMCR_ANENABLE | BMCR_ANRESTART);
2920 }
2921}
2922
2923static int tg3_init_5401phy_dsp(struct tg3 *tp)
2924{
2925 int err;
2926
2927 /* Turn off tap power management. */
2928 /* Set Extended packet length bit */
2929 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2936
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2939
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2942
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2945
2946 udelay(40);
2947
2948 return err;
2949}
2950
3600d918 2951static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2952{
3600d918
MC		 2953 u32 adv_reg, all_mask = 0;
2954
2955 if (mask & ADVERTISED_10baseT_Half)
2956 all_mask |= ADVERTISE_10HALF;
2957 if (mask & ADVERTISED_10baseT_Full)
2958 all_mask |= ADVERTISE_10FULL;
2959 if (mask & ADVERTISED_100baseT_Half)
2960 all_mask |= ADVERTISE_100HALF;
2961 if (mask & ADVERTISED_100baseT_Full)
2962 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2963
2964 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2965 return 0;
2966
1da177e4
LT		 2967 if ((adv_reg & all_mask) != all_mask)
2968 return 0;
2969 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2970 u32 tg3_ctrl;
2971
3600d918
MC		 2972 all_mask = 0;
2973 if (mask & ADVERTISED_1000baseT_Half)
2974 all_mask |= ADVERTISE_1000HALF;
2975 if (mask & ADVERTISED_1000baseT_Full)
2976 all_mask |= ADVERTISE_1000FULL;
2977
1da177e4
LT		 2978 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2979 return 0;
2980
1da177e4
LT		 2981 if ((tg3_ctrl & all_mask) != all_mask)
2982 return 0;
2983 }
2984 return 1;
2985}
2986
ef167e27
MC		 2987static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2988{
2989 u32 curadv, reqadv;
2990
2991 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2992 return 1;
2993
2994 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2996
2997 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998 if (curadv != reqadv)
2999 return 0;
3000
3001 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002 tg3_readphy(tp, MII_LPA, rmtadv);
3003 } else {
3004 /* Reprogram the advertisement register, even if it
3005 * does not affect the current link. If the link
3006 * gets renegotiated in the future, we can save an
3007 * additional renegotiation cycle by advertising
3008 * it correctly in the first place.
3009 */
3010 if (curadv != reqadv) {
3011 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012 ADVERTISE_PAUSE_ASYM);
3013 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3014 }
3015 }
3016
3017 return 1;
3018}
3019
1da177e4
LT		 3020static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3021{
3022 int current_link_up;
3023 u32 bmsr, dummy;
ef167e27 3024 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3025 u16 current_speed;
3026 u8 current_duplex;
3027 int i, err;
3028
3029 tw32(MAC_EVENT, 0);
3030
3031 tw32_f(MAC_STATUS,
3032 (MAC_STATUS_SYNC_CHANGED |
3033 MAC_STATUS_CFG_CHANGED |
3034 MAC_STATUS_MI_COMPLETION |
3035 MAC_STATUS_LNKSTATE_CHANGED));
3036 udelay(40);
3037
8ef21428
MC		 3038 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3039 tw32_f(MAC_MI_MODE,
3040 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3041 udelay(80);
3042 }
1da177e4
LT		 3043
3044 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3045
3046 /* Some third-party PHYs need to be reset on link going
3047 * down.
3048 */
3049 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052 netif_carrier_ok(tp->dev)) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055 !(bmsr & BMSR_LSTATUS))
3056 force_reset = 1;
3057 }
3058 if (force_reset)
3059 tg3_phy_reset(tp);
3060
3061 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062 tg3_readphy(tp, MII_BMSR, &bmsr);
3063 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3065 bmsr = 0;
3066
3067 if (!(bmsr & BMSR_LSTATUS)) {
3068 err = tg3_init_5401phy_dsp(tp);
3069 if (err)
3070 return err;
3071
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 for (i = 0; i < 1000; i++) {
3074 udelay(10);
3075 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076 (bmsr & BMSR_LSTATUS)) {
3077 udelay(40);
3078 break;
3079 }
3080 }
3081
3082 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083 !(bmsr & BMSR_LSTATUS) &&
3084 tp->link_config.active_speed == SPEED_1000) {
3085 err = tg3_phy_reset(tp);
3086 if (!err)
3087 err = tg3_init_5401phy_dsp(tp);
3088 if (err)
3089 return err;
3090 }
3091 }
3092 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094 /* 5701 {A0,B0} CRC bug workaround */
3095 tg3_writephy(tp, 0x15, 0x0a75);
3096 tg3_writephy(tp, 0x1c, 0x8c68);
3097 tg3_writephy(tp, 0x1c, 0x8d68);
3098 tg3_writephy(tp, 0x1c, 0x8c68);
3099 }
3100
3101 /* Clear pending interrupts... */
3102 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3104
3105 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3107 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3108 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3109
3110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3115 else
3116 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3117 }
3118
3119 current_link_up = 0;
3120 current_speed = SPEED_INVALID;
3121 current_duplex = DUPLEX_INVALID;
3122
3123 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3124 u32 val;
3125
3126 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128 if (!(val & (1 << 10))) {
3129 val |= (1 << 10);
3130 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3131 goto relink;
3132 }
3133 }
3134
3135 bmsr = 0;
3136 for (i = 0; i < 100; i++) {
3137 tg3_readphy(tp, MII_BMSR, &bmsr);
3138 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139 (bmsr & BMSR_LSTATUS))
3140 break;
3141 udelay(40);
3142 }
3143
3144 if (bmsr & BMSR_LSTATUS) {
3145 u32 aux_stat, bmcr;
3146
3147 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148 for (i = 0; i < 2000; i++) {
3149 udelay(10);
3150 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3151 aux_stat)
3152 break;
3153 }
3154
3155 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3156 &current_speed,
3157 &current_duplex);
3158
3159 bmcr = 0;
3160 for (i = 0; i < 200; i++) {
3161 tg3_readphy(tp, MII_BMCR, &bmcr);
3162 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3163 continue;
3164 if (bmcr && bmcr != 0x7fff)
3165 break;
3166 udelay(10);
3167 }
3168
ef167e27
MC		 3169 lcl_adv = 0;
3170 rmt_adv = 0;
1da177e4 3171
ef167e27
MC		 3172 tp->link_config.active_speed = current_speed;
3173 tp->link_config.active_duplex = current_duplex;
3174
3175 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176 if ((bmcr & BMCR_ANENABLE) &&
3177 tg3_copper_is_advertising_all(tp,
3178 tp->link_config.advertising)) {
3179 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3180 &rmt_adv))
3181 current_link_up = 1;
1da177e4
LT		 3182 }
3183 } else {
3184 if (!(bmcr & BMCR_ANENABLE) &&
3185 tp->link_config.speed == current_speed &&
ef167e27
MC		 3186 tp->link_config.duplex == current_duplex &&
3187 tp->link_config.flowctrl ==
3188 tp->link_config.active_flowctrl) {
1da177e4 3189 current_link_up = 1;
1da177e4
LT		 3190 }
3191 }
3192
ef167e27
MC		 3193 if (current_link_up == 1 &&
3194 tp->link_config.active_duplex == DUPLEX_FULL)
3195 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3196 }
3197
1da177e4 3198relink:
6921d201 3199 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3200 u32 tmp;
3201
3202 tg3_phy_copper_begin(tp);
3203
3204 tg3_readphy(tp, MII_BMSR, &tmp);
3205 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206 (tmp & BMSR_LSTATUS))
3207 current_link_up = 1;
3208 }
3209
3210 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211 if (current_link_up == 1) {
3212 if (tp->link_config.active_speed == SPEED_100 ||
3213 tp->link_config.active_speed == SPEED_10)
3214 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3215 else
3216 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3217 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219 else
1da177e4
LT		 3220 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3221
3222 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223 if (tp->link_config.active_duplex == DUPLEX_HALF)
3224 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3225
1da177e4 3226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3227 if (current_link_up == 1 &&
3228 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3229 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3230 else
3231 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3232 }
3233
3234 /* ??? Without this setting Netgear GA302T PHY does not
3235 * ??? send/receive packets...
3236 */
3237 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240 tw32_f(MAC_MI_MODE, tp->mi_mode);
3241 udelay(80);
3242 }
3243
3244 tw32_f(MAC_MODE, tp->mac_mode);
3245 udelay(40);
3246
3247 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248 /* Polled via timer. */
3249 tw32_f(MAC_EVENT, 0);
3250 } else {
3251 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3252 }
3253 udelay(40);
3254
3255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256 current_link_up == 1 &&
3257 tp->link_config.active_speed == SPEED_1000 &&
3258 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3260 udelay(120);
3261 tw32_f(MAC_STATUS,
3262 (MAC_STATUS_SYNC_CHANGED |
3263 MAC_STATUS_CFG_CHANGED));
3264 udelay(40);
3265 tg3_write_mem(tp,
3266 NIC_SRAM_FIRMWARE_MBOX,
3267 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3268 }
3269
5e7dfd0f
MC		 3270 /* Prevent send BD corruption. */
3271 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272 u16 oldlnkctl, newlnkctl;
3273
3274 pci_read_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3276 &oldlnkctl);
3277 if (tp->link_config.active_speed == SPEED_100 ||
3278 tp->link_config.active_speed == SPEED_10)
3279 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3280 else
3281 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282 if (newlnkctl != oldlnkctl)
3283 pci_write_config_word(tp->pdev,
3284 tp->pcie_cap + PCI_EXP_LNKCTL,
3285 newlnkctl);
3286 }
3287
1da177e4
LT		 3288 if (current_link_up != netif_carrier_ok(tp->dev)) {
3289 if (current_link_up)
3290 netif_carrier_on(tp->dev);
3291 else
3292 netif_carrier_off(tp->dev);
3293 tg3_link_report(tp);
3294 }
3295
3296 return 0;
3297}
3298
3299struct tg3_fiber_aneginfo {
3300 int state;
3301#define ANEG_STATE_UNKNOWN 0
3302#define ANEG_STATE_AN_ENABLE 1
3303#define ANEG_STATE_RESTART_INIT 2
3304#define ANEG_STATE_RESTART 3
3305#define ANEG_STATE_DISABLE_LINK_OK 4
3306#define ANEG_STATE_ABILITY_DETECT_INIT 5
3307#define ANEG_STATE_ABILITY_DETECT 6
3308#define ANEG_STATE_ACK_DETECT_INIT 7
3309#define ANEG_STATE_ACK_DETECT 8
3310#define ANEG_STATE_COMPLETE_ACK_INIT 9
3311#define ANEG_STATE_COMPLETE_ACK 10
3312#define ANEG_STATE_IDLE_DETECT_INIT 11
3313#define ANEG_STATE_IDLE_DETECT 12
3314#define ANEG_STATE_LINK_OK 13
3315#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3316#define ANEG_STATE_NEXT_PAGE_WAIT 15
3317
3318 u32 flags;
3319#define MR_AN_ENABLE 0x00000001
3320#define MR_RESTART_AN 0x00000002
3321#define MR_AN_COMPLETE 0x00000004
3322#define MR_PAGE_RX 0x00000008
3323#define MR_NP_LOADED 0x00000010
3324#define MR_TOGGLE_TX 0x00000020
3325#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3326#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3327#define MR_LP_ADV_SYM_PAUSE 0x00000100
3328#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3329#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331#define MR_LP_ADV_NEXT_PAGE 0x00001000
3332#define MR_TOGGLE_RX 0x00002000
3333#define MR_NP_RX 0x00004000
3334
3335#define MR_LINK_OK 0x80000000
3336
3337 unsigned long link_time, cur_time;
3338
3339 u32 ability_match_cfg;
3340 int ability_match_count;
3341
3342 char ability_match, idle_match, ack_match;
3343
3344 u32 txconfig, rxconfig;
3345#define ANEG_CFG_NP 0x00000080
3346#define ANEG_CFG_ACK 0x00000040
3347#define ANEG_CFG_RF2 0x00000020
3348#define ANEG_CFG_RF1 0x00000010
3349#define ANEG_CFG_PS2 0x00000001
3350#define ANEG_CFG_PS1 0x00008000
3351#define ANEG_CFG_HD 0x00004000
3352#define ANEG_CFG_FD 0x00002000
3353#define ANEG_CFG_INVAL 0x00001f06
3354
3355};
3356#define ANEG_OK 0
3357#define ANEG_DONE 1
3358#define ANEG_TIMER_ENAB 2
3359#define ANEG_FAILED -1
3360
3361#define ANEG_STATE_SETTLE_TIME 10000
3362
3363static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364 struct tg3_fiber_aneginfo *ap)
3365{
5be73b47 3366 u16 flowctrl;
1da177e4
LT		 3367 unsigned long delta;
3368 u32 rx_cfg_reg;
3369 int ret;
3370
3371 if (ap->state == ANEG_STATE_UNKNOWN) {
3372 ap->rxconfig = 0;
3373 ap->link_time = 0;
3374 ap->cur_time = 0;
3375 ap->ability_match_cfg = 0;
3376 ap->ability_match_count = 0;
3377 ap->ability_match = 0;
3378 ap->idle_match = 0;
3379 ap->ack_match = 0;
3380 }
3381 ap->cur_time++;
3382
3383 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3385
3386 if (rx_cfg_reg != ap->ability_match_cfg) {
3387 ap->ability_match_cfg = rx_cfg_reg;
3388 ap->ability_match = 0;
3389 ap->ability_match_count = 0;
3390 } else {
3391 if (++ap->ability_match_count > 1) {
3392 ap->ability_match = 1;
3393 ap->ability_match_cfg = rx_cfg_reg;
3394 }
3395 }
3396 if (rx_cfg_reg & ANEG_CFG_ACK)
3397 ap->ack_match = 1;
3398 else
3399 ap->ack_match = 0;
3400
3401 ap->idle_match = 0;
3402 } else {
3403 ap->idle_match = 1;
3404 ap->ability_match_cfg = 0;
3405 ap->ability_match_count = 0;
3406 ap->ability_match = 0;
3407 ap->ack_match = 0;
3408
3409 rx_cfg_reg = 0;
3410 }
3411
3412 ap->rxconfig = rx_cfg_reg;
3413 ret = ANEG_OK;
3414
3415 switch(ap->state) {
3416 case ANEG_STATE_UNKNOWN:
3417 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418 ap->state = ANEG_STATE_AN_ENABLE;
3419
3420 /* fallthru */
3421 case ANEG_STATE_AN_ENABLE:
3422 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423 if (ap->flags & MR_AN_ENABLE) {
3424 ap->link_time = 0;
3425 ap->cur_time = 0;
3426 ap->ability_match_cfg = 0;
3427 ap->ability_match_count = 0;
3428 ap->ability_match = 0;
3429 ap->idle_match = 0;
3430 ap->ack_match = 0;
3431
3432 ap->state = ANEG_STATE_RESTART_INIT;
3433 } else {
3434 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3435 }
3436 break;
3437
3438 case ANEG_STATE_RESTART_INIT:
3439 ap->link_time = ap->cur_time;
3440 ap->flags &= ~(MR_NP_LOADED);
3441 ap->txconfig = 0;
3442 tw32(MAC_TX_AUTO_NEG, 0);
3443 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444 tw32_f(MAC_MODE, tp->mac_mode);
3445 udelay(40);
3446
3447 ret = ANEG_TIMER_ENAB;
3448 ap->state = ANEG_STATE_RESTART;
3449
3450 /* fallthru */
3451 case ANEG_STATE_RESTART:
3452 delta = ap->cur_time - ap->link_time;
3453 if (delta > ANEG_STATE_SETTLE_TIME) {
3454 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3455 } else {
3456 ret = ANEG_TIMER_ENAB;
3457 }
3458 break;
3459
3460 case ANEG_STATE_DISABLE_LINK_OK:
3461 ret = ANEG_DONE;
3462 break;
3463
3464 case ANEG_STATE_ABILITY_DETECT_INIT:
3465 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3466 ap->txconfig = ANEG_CFG_FD;
3467 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468 if (flowctrl & ADVERTISE_1000XPAUSE)
3469 ap->txconfig |= ANEG_CFG_PS1;
3470 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3472 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474 tw32_f(MAC_MODE, tp->mac_mode);
3475 udelay(40);
3476
3477 ap->state = ANEG_STATE_ABILITY_DETECT;
3478 break;
3479
3480 case ANEG_STATE_ABILITY_DETECT:
3481 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3483 }
3484 break;
3485
3486 case ANEG_STATE_ACK_DETECT_INIT:
3487 ap->txconfig |= ANEG_CFG_ACK;
3488 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490 tw32_f(MAC_MODE, tp->mac_mode);
3491 udelay(40);
3492
3493 ap->state = ANEG_STATE_ACK_DETECT;
3494
3495 /* fallthru */
3496 case ANEG_STATE_ACK_DETECT:
3497 if (ap->ack_match != 0) {
3498 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3501 } else {
3502 ap->state = ANEG_STATE_AN_ENABLE;
3503 }
3504 } else if (ap->ability_match != 0 &&
3505 ap->rxconfig == 0) {
3506 ap->state = ANEG_STATE_AN_ENABLE;
3507 }
3508 break;
3509
3510 case ANEG_STATE_COMPLETE_ACK_INIT:
3511 if (ap->rxconfig & ANEG_CFG_INVAL) {
3512 ret = ANEG_FAILED;
3513 break;
3514 }
3515 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516 MR_LP_ADV_HALF_DUPLEX |
3517 MR_LP_ADV_SYM_PAUSE |
3518 MR_LP_ADV_ASYM_PAUSE |
3519 MR_LP_ADV_REMOTE_FAULT1 |
3520 MR_LP_ADV_REMOTE_FAULT2 |
3521 MR_LP_ADV_NEXT_PAGE |
3522 MR_TOGGLE_RX |
3523 MR_NP_RX);
3524 if (ap->rxconfig & ANEG_CFG_FD)
3525 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526 if (ap->rxconfig & ANEG_CFG_HD)
3527 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528 if (ap->rxconfig & ANEG_CFG_PS1)
3529 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530 if (ap->rxconfig & ANEG_CFG_PS2)
3531 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532 if (ap->rxconfig & ANEG_CFG_RF1)
3533 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534 if (ap->rxconfig & ANEG_CFG_RF2)
3535 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536 if (ap->rxconfig & ANEG_CFG_NP)
3537 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3538
3539 ap->link_time = ap->cur_time;
3540
3541 ap->flags ^= (MR_TOGGLE_TX);
3542 if (ap->rxconfig & 0x0008)
3543 ap->flags |= MR_TOGGLE_RX;
3544 if (ap->rxconfig & ANEG_CFG_NP)
3545 ap->flags |= MR_NP_RX;
3546 ap->flags |= MR_PAGE_RX;
3547
3548 ap->state = ANEG_STATE_COMPLETE_ACK;
3549 ret = ANEG_TIMER_ENAB;
3550 break;
3551
3552 case ANEG_STATE_COMPLETE_ACK:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3556 break;
3557 }
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3562 } else {
3563 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564 !(ap->flags & MR_NP_RX)) {
3565 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566 } else {
3567 ret = ANEG_FAILED;
3568 }
3569 }
3570 }
3571 break;
3572
3573 case ANEG_STATE_IDLE_DETECT_INIT:
3574 ap->link_time = ap->cur_time;
3575 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576 tw32_f(MAC_MODE, tp->mac_mode);
3577 udelay(40);
3578
3579 ap->state = ANEG_STATE_IDLE_DETECT;
3580 ret = ANEG_TIMER_ENAB;
3581 break;
3582
3583 case ANEG_STATE_IDLE_DETECT:
3584 if (ap->ability_match != 0 &&
3585 ap->rxconfig == 0) {
3586 ap->state = ANEG_STATE_AN_ENABLE;
3587 break;
3588 }
3589 delta = ap->cur_time - ap->link_time;
3590 if (delta > ANEG_STATE_SETTLE_TIME) {
3591 /* XXX another gem from the Broadcom driver :( */
3592 ap->state = ANEG_STATE_LINK_OK;
3593 }
3594 break;
3595
3596 case ANEG_STATE_LINK_OK:
3597 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3598 ret = ANEG_DONE;
3599 break;
3600
3601 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602 /* ??? unimplemented */
3603 break;
3604
3605 case ANEG_STATE_NEXT_PAGE_WAIT:
3606 /* ??? unimplemented */
3607 break;
3608
3609 default:
3610 ret = ANEG_FAILED;
3611 break;
855e1111 3612 }
1da177e4
LT		 3613
3614 return ret;
3615}
3616
5be73b47 3617static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3618{
3619 int res = 0;
3620 struct tg3_fiber_aneginfo aninfo;
3621 int status = ANEG_FAILED;
3622 unsigned int tick;
3623 u32 tmp;
3624
3625 tw32_f(MAC_TX_AUTO_NEG, 0);
3626
3627 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3629 udelay(40);
3630
3631 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3632 udelay(40);
3633
3634 memset(&aninfo, 0, sizeof(aninfo));
3635 aninfo.flags |= MR_AN_ENABLE;
3636 aninfo.state = ANEG_STATE_UNKNOWN;
3637 aninfo.cur_time = 0;
3638 tick = 0;
3639 while (++tick < 195000) {
3640 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641 if (status == ANEG_DONE || status == ANEG_FAILED)
3642 break;
3643
3644 udelay(1);
3645 }
3646
3647 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648 tw32_f(MAC_MODE, tp->mac_mode);
3649 udelay(40);
3650
5be73b47
MC		 3651 *txflags = aninfo.txconfig;
3652 *rxflags = aninfo.flags;
1da177e4
LT		 3653
3654 if (status == ANEG_DONE &&
3655 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656 MR_LP_ADV_FULL_DUPLEX)))
3657 res = 1;
3658
3659 return res;
3660}
3661
3662static void tg3_init_bcm8002(struct tg3 *tp)
3663{
3664 u32 mac_status = tr32(MAC_STATUS);
3665 int i;
3666
3667 /* Reset when initting first time or we have a link. */
3668 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669 !(mac_status & MAC_STATUS_PCS_SYNCED))
3670 return;
3671
3672 /* Set PLL lock range. */
3673 tg3_writephy(tp, 0x16, 0x8007);
3674
3675 /* SW reset */
3676 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3677
3678 /* Wait for reset to complete. */
3679 /* XXX schedule_timeout() ... */
3680 for (i = 0; i < 500; i++)
3681 udelay(10);
3682
3683 /* Config mode; select PMA/Ch 1 regs. */
3684 tg3_writephy(tp, 0x10, 0x8411);
3685
3686 /* Enable auto-lock and comdet, select txclk for tx. */
3687 tg3_writephy(tp, 0x11, 0x0a10);
3688
3689 tg3_writephy(tp, 0x18, 0x00a0);
3690 tg3_writephy(tp, 0x16, 0x41ff);
3691
3692 /* Assert and deassert POR. */
3693 tg3_writephy(tp, 0x13, 0x0400);
3694 udelay(40);
3695 tg3_writephy(tp, 0x13, 0x0000);
3696
3697 tg3_writephy(tp, 0x11, 0x0a50);
3698 udelay(40);
3699 tg3_writephy(tp, 0x11, 0x0a10);
3700
3701 /* Wait for signal to stabilize */
3702 /* XXX schedule_timeout() ... */
3703 for (i = 0; i < 15000; i++)
3704 udelay(10);
3705
3706 /* Deselect the channel register so we can read the PHYID
3707 * later.
3708 */
3709 tg3_writephy(tp, 0x10, 0x8011);
3710}
3711
3712static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3713{
82cd3d11 3714 u16 flowctrl;
1da177e4
LT		 3715 u32 sg_dig_ctrl, sg_dig_status;
3716 u32 serdes_cfg, expected_sg_dig_ctrl;
3717 int workaround, port_a;
3718 int current_link_up;
3719
3720 serdes_cfg = 0;
3721 expected_sg_dig_ctrl = 0;
3722 workaround = 0;
3723 port_a = 1;
3724 current_link_up = 0;
3725
3726 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3728 workaround = 1;
3729 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3730 port_a = 0;
3731
3732 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733 /* preserve bits 20-23 for voltage regulator */
3734 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3735 }
3736
3737 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3738
3739 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3740 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3741 if (workaround) {
3742 u32 val = serdes_cfg;
3743
3744 if (port_a)
3745 val |= 0xc010000;
3746 else
3747 val |= 0x4010000;
3748 tw32_f(MAC_SERDES_CFG, val);
3749 }
c98f6e3b
MC		 3750
3751 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3752 }
3753 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754 tg3_setup_flow_control(tp, 0, 0);
3755 current_link_up = 1;
3756 }
3757 goto out;
3758 }
3759
3760 /* Want auto-negotiation. */
c98f6e3b 3761 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3762
82cd3d11
MC		 3763 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764 if (flowctrl & ADVERTISE_1000XPAUSE)
3765 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3768
3769 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3770 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771 tp->serdes_counter &&
3772 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773 MAC_STATUS_RCVD_CFG)) ==
3774 MAC_STATUS_PCS_SYNCED)) {
3775 tp->serdes_counter--;
3776 current_link_up = 1;
3777 goto out;
3778 }
3779restart_autoneg:
1da177e4
LT		 3780 if (workaround)
3781 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3782 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3783 udelay(5);
3784 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3785
3d3ebe74
MC		 3786 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3788 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3790 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3791 mac_status = tr32(MAC_STATUS);
3792
c98f6e3b 3793 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3794 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3795 u32 local_adv = 0, remote_adv = 0;
3796
3797 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798 local_adv |= ADVERTISE_1000XPAUSE;
3799 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3801
c98f6e3b 3802 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3803 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3804 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3805 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3806
3807 tg3_setup_flow_control(tp, local_adv, remote_adv);
3808 current_link_up = 1;
3d3ebe74
MC		 3809 tp->serdes_counter = 0;
3810 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3811 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3812 if (tp->serdes_counter)
3813 tp->serdes_counter--;
1da177e4
LT		 3814 else {
3815 if (workaround) {
3816 u32 val = serdes_cfg;
3817
3818 if (port_a)
3819 val |= 0xc010000;
3820 else
3821 val |= 0x4010000;
3822
3823 tw32_f(MAC_SERDES_CFG, val);
3824 }
3825
c98f6e3b 3826 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3827 udelay(40);
3828
3829 /* Link parallel detection - link is up */
3830 /* only if we have PCS_SYNC and not */
3831 /* receiving config code words */
3832 mac_status = tr32(MAC_STATUS);
3833 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835 tg3_setup_flow_control(tp, 0, 0);
3836 current_link_up = 1;
3d3ebe74
MC		 3837 tp->tg3_flags2 |=
3838 TG3_FLG2_PARALLEL_DETECT;
3839 tp->serdes_counter =
3840 SERDES_PARALLEL_DET_TIMEOUT;
3841 } else
3842 goto restart_autoneg;
1da177e4
LT		 3843 }
3844 }
3d3ebe74
MC		 3845 } else {
3846 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3848 }
3849
3850out:
3851 return current_link_up;
3852}
3853
3854static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3855{
3856 int current_link_up = 0;
3857
5cf64b8a 3858 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3859 goto out;
1da177e4
LT		 3860
3861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3862 u32 txflags, rxflags;
1da177e4 3863 int i;
6aa20a22 3864
5be73b47
MC		 3865 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866 u32 local_adv = 0, remote_adv = 0;
1da177e4 3867
5be73b47
MC		 3868 if (txflags & ANEG_CFG_PS1)
3869 local_adv |= ADVERTISE_1000XPAUSE;
3870 if (txflags & ANEG_CFG_PS2)
3871 local_adv |= ADVERTISE_1000XPSE_ASYM;
3872
3873 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874 remote_adv |= LPA_1000XPAUSE;
3875 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3877
3878 tg3_setup_flow_control(tp, local_adv, remote_adv);
3879
1da177e4
LT		 3880 current_link_up = 1;
3881 }
3882 for (i = 0; i < 30; i++) {
3883 udelay(20);
3884 tw32_f(MAC_STATUS,
3885 (MAC_STATUS_SYNC_CHANGED |
3886 MAC_STATUS_CFG_CHANGED));
3887 udelay(40);
3888 if ((tr32(MAC_STATUS) &
3889 (MAC_STATUS_SYNC_CHANGED |
3890 MAC_STATUS_CFG_CHANGED)) == 0)
3891 break;
3892 }
3893
3894 mac_status = tr32(MAC_STATUS);
3895 if (current_link_up == 0 &&
3896 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897 !(mac_status & MAC_STATUS_RCVD_CFG))
3898 current_link_up = 1;
3899 } else {
5be73b47
MC		 3900 tg3_setup_flow_control(tp, 0, 0);
3901
1da177e4
LT		 3902 /* Forcing 1000FD link up. */
3903 current_link_up = 1;
1da177e4
LT		 3904
3905 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3906 udelay(40);
e8f3f6ca
MC		 3907
3908 tw32_f(MAC_MODE, tp->mac_mode);
3909 udelay(40);
1da177e4
LT		 3910 }
3911
3912out:
3913 return current_link_up;
3914}
3915
3916static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3917{
3918 u32 orig_pause_cfg;
3919 u16 orig_active_speed;
3920 u8 orig_active_duplex;
3921 u32 mac_status;
3922 int current_link_up;
3923 int i;
3924
8d018621 3925 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3926 orig_active_speed = tp->link_config.active_speed;
3927 orig_active_duplex = tp->link_config.active_duplex;
3928
3929 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930 netif_carrier_ok(tp->dev) &&
3931 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932 mac_status = tr32(MAC_STATUS);
3933 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934 MAC_STATUS_SIGNAL_DET |
3935 MAC_STATUS_CFG_CHANGED |
3936 MAC_STATUS_RCVD_CFG);
3937 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938 MAC_STATUS_SIGNAL_DET)) {
3939 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940 MAC_STATUS_CFG_CHANGED));
3941 return 0;
3942 }
3943 }
3944
3945 tw32_f(MAC_TX_AUTO_NEG, 0);
3946
3947 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949 tw32_f(MAC_MODE, tp->mac_mode);
3950 udelay(40);
3951
3952 if (tp->phy_id == PHY_ID_BCM8002)
3953 tg3_init_bcm8002(tp);
3954
3955 /* Enable link change event even when serdes polling. */
3956 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3957 udelay(40);
3958
3959 current_link_up = 0;
3960 mac_status = tr32(MAC_STATUS);
3961
3962 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3964 else
3965 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3966
898a56f8 3967 tp->napi[0].hw_status->status =
1da177e4 3968 (SD_STATUS_UPDATED |
898a56f8 3969 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3970
3971 for (i = 0; i < 100; i++) {
3972 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973 MAC_STATUS_CFG_CHANGED));
3974 udelay(5);
3975 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3976 MAC_STATUS_CFG_CHANGED |
3977 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3978 break;
3979 }
3980
3981 mac_status = tr32(MAC_STATUS);
3982 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983 current_link_up = 0;
3d3ebe74
MC		 3984 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985 tp->serdes_counter == 0) {
1da177e4
LT		 3986 tw32_f(MAC_MODE, (tp->mac_mode |
3987 MAC_MODE_SEND_CONFIGS));
3988 udelay(1);
3989 tw32_f(MAC_MODE, tp->mac_mode);
3990 }
3991 }
3992
3993 if (current_link_up == 1) {
3994 tp->link_config.active_speed = SPEED_1000;
3995 tp->link_config.active_duplex = DUPLEX_FULL;
3996 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997 LED_CTRL_LNKLED_OVERRIDE |
3998 LED_CTRL_1000MBPS_ON));
3999 } else {
4000 tp->link_config.active_speed = SPEED_INVALID;
4001 tp->link_config.active_duplex = DUPLEX_INVALID;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_TRAFFIC_OVERRIDE));
4005 }
4006
4007 if (current_link_up != netif_carrier_ok(tp->dev)) {
4008 if (current_link_up)
4009 netif_carrier_on(tp->dev);
4010 else
4011 netif_carrier_off(tp->dev);
4012 tg3_link_report(tp);
4013 } else {
8d018621 4014 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4015 if (orig_pause_cfg != now_pause_cfg ||
4016 orig_active_speed != tp->link_config.active_speed ||
4017 orig_active_duplex != tp->link_config.active_duplex)
4018 tg3_link_report(tp);
4019 }
4020
4021 return 0;
4022}
4023
747e8f8b
MC		 4024static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4025{
4026 int current_link_up, err = 0;
4027 u32 bmsr, bmcr;
4028 u16 current_speed;
4029 u8 current_duplex;
ef167e27 4030 u32 local_adv, remote_adv;
747e8f8b
MC		 4031
4032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033 tw32_f(MAC_MODE, tp->mac_mode);
4034 udelay(40);
4035
4036 tw32(MAC_EVENT, 0);
4037
4038 tw32_f(MAC_STATUS,
4039 (MAC_STATUS_SYNC_CHANGED |
4040 MAC_STATUS_CFG_CHANGED |
4041 MAC_STATUS_MI_COMPLETION |
4042 MAC_STATUS_LNKSTATE_CHANGED));
4043 udelay(40);
4044
4045 if (force_reset)
4046 tg3_phy_reset(tp);
4047
4048 current_link_up = 0;
4049 current_speed = SPEED_INVALID;
4050 current_duplex = DUPLEX_INVALID;
4051
4052 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056 bmsr |= BMSR_LSTATUS;
4057 else
4058 bmsr &= ~BMSR_LSTATUS;
4059 }
747e8f8b
MC		 4060
4061 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4062
4063 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4064 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4065 /* do nothing, just check for link up at the end */
4066 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4067 u32 adv, new_adv;
4068
4069 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071 ADVERTISE_1000XPAUSE |
4072 ADVERTISE_1000XPSE_ASYM |
4073 ADVERTISE_SLCT);
4074
ba4d07a8 4075 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4076
4077 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078 new_adv |= ADVERTISE_1000XHALF;
4079 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080 new_adv |= ADVERTISE_1000XFULL;
4081
4082 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085 tg3_writephy(tp, MII_BMCR, bmcr);
4086
4087 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4088 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4089 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4090
4091 return err;
4092 }
4093 } else {
4094 u32 new_bmcr;
4095
4096 bmcr &= ~BMCR_SPEED1000;
4097 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4098
4099 if (tp->link_config.duplex == DUPLEX_FULL)
4100 new_bmcr |= BMCR_FULLDPLX;
4101
4102 if (new_bmcr != bmcr) {
4103 /* BMCR_SPEED1000 is a reserved bit that needs
4104 * to be set on write.
4105 */
4106 new_bmcr |= BMCR_SPEED1000;
4107
4108 /* Force a linkdown */
4109 if (netif_carrier_ok(tp->dev)) {
4110 u32 adv;
4111
4112 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113 adv &= ~(ADVERTISE_1000XFULL |
4114 ADVERTISE_1000XHALF |
4115 ADVERTISE_SLCT);
4116 tg3_writephy(tp, MII_ADVERTISE, adv);
4117 tg3_writephy(tp, MII_BMCR, bmcr |
4118 BMCR_ANRESTART |
4119 BMCR_ANENABLE);
4120 udelay(10);
4121 netif_carrier_off(tp->dev);
4122 }
4123 tg3_writephy(tp, MII_BMCR, new_bmcr);
4124 bmcr = new_bmcr;
4125 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4127 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4128 ASIC_REV_5714) {
4129 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130 bmsr |= BMSR_LSTATUS;
4131 else
4132 bmsr &= ~BMSR_LSTATUS;
4133 }
747e8f8b
MC		 4134 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135 }
4136 }
4137
4138 if (bmsr & BMSR_LSTATUS) {
4139 current_speed = SPEED_1000;
4140 current_link_up = 1;
4141 if (bmcr & BMCR_FULLDPLX)
4142 current_duplex = DUPLEX_FULL;
4143 else
4144 current_duplex = DUPLEX_HALF;
4145
ef167e27
MC		 4146 local_adv = 0;
4147 remote_adv = 0;
4148
747e8f8b 4149 if (bmcr & BMCR_ANENABLE) {
ef167e27 4150 u32 common;
747e8f8b
MC		 4151
4152 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154 common = local_adv & remote_adv;
4155 if (common & (ADVERTISE_1000XHALF |
4156 ADVERTISE_1000XFULL)) {
4157 if (common & ADVERTISE_1000XFULL)
4158 current_duplex = DUPLEX_FULL;
4159 else
4160 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4161 }
4162 else
4163 current_link_up = 0;
4164 }
4165 }
4166
ef167e27
MC		 4167 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168 tg3_setup_flow_control(tp, local_adv, remote_adv);
4169
747e8f8b
MC		 4170 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171 if (tp->link_config.active_duplex == DUPLEX_HALF)
4172 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4173
4174 tw32_f(MAC_MODE, tp->mac_mode);
4175 udelay(40);
4176
4177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4178
4179 tp->link_config.active_speed = current_speed;
4180 tp->link_config.active_duplex = current_duplex;
4181
4182 if (current_link_up != netif_carrier_ok(tp->dev)) {
4183 if (current_link_up)
4184 netif_carrier_on(tp->dev);
4185 else {
4186 netif_carrier_off(tp->dev);
4187 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188 }
4189 tg3_link_report(tp);
4190 }
4191 return err;
4192}
4193
4194static void tg3_serdes_parallel_detect(struct tg3 *tp)
4195{
3d3ebe74 4196 if (tp->serdes_counter) {
747e8f8b 4197 /* Give autoneg time to complete. */
3d3ebe74 4198 tp->serdes_counter--;
747e8f8b
MC		 4199 return;
4200 }
4201 if (!netif_carrier_ok(tp->dev) &&
4202 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4203 u32 bmcr;
4204
4205 tg3_readphy(tp, MII_BMCR, &bmcr);
4206 if (bmcr & BMCR_ANENABLE) {
4207 u32 phy1, phy2;
4208
4209 /* Select shadow register 0x1f */
4210 tg3_writephy(tp, 0x1c, 0x7c00);
4211 tg3_readphy(tp, 0x1c, &phy1);
4212
4213 /* Select expansion interrupt status register */
4214 tg3_writephy(tp, 0x17, 0x0f01);
4215 tg3_readphy(tp, 0x15, &phy2);
4216 tg3_readphy(tp, 0x15, &phy2);
4217
4218 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219 /* We have signal detect and not receiving
4220 * config code words, link is up by parallel
4221 * detection.
4222 */
4223
4224 bmcr &= ~BMCR_ANENABLE;
4225 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226 tg3_writephy(tp, MII_BMCR, bmcr);
4227 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4228 }
4229 }
4230 }
4231 else if (netif_carrier_ok(tp->dev) &&
4232 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4234 u32 phy2;
4235
4236 /* Select expansion interrupt status register */
4237 tg3_writephy(tp, 0x17, 0x0f01);
4238 tg3_readphy(tp, 0x15, &phy2);
4239 if (phy2 & 0x20) {
4240 u32 bmcr;
4241
4242 /* Config code words received, turn on autoneg. */
4243 tg3_readphy(tp, MII_BMCR, &bmcr);
4244 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4245
4246 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4247
4248 }
4249 }
4250}
4251
1da177e4
LT		 4252static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4253{
4254 int err;
4255
4256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4258 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4260 } else {
4261 err = tg3_setup_copper_phy(tp, force_reset);
4262 }
4263
bcb37f6c 4264 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4265 u32 val, scale;
4266
4267 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4269 scale = 65;
4270 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4271 scale = 6;
4272 else
4273 scale = 12;
4274
4275 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277 tw32(GRC_MISC_CFG, val);
4278 }
4279
1da177e4
LT		 4280 if (tp->link_config.active_speed == SPEED_1000 &&
4281 tp->link_config.active_duplex == DUPLEX_HALF)
4282 tw32(MAC_TX_LENGTHS,
4283 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284 (6 << TX_LENGTHS_IPG_SHIFT) |
4285 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4286 else
4287 tw32(MAC_TX_LENGTHS,
4288 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289 (6 << TX_LENGTHS_IPG_SHIFT) |
4290 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4291
4292 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293 if (netif_carrier_ok(tp->dev)) {
4294 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4295 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4296 } else {
4297 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4298 }
4299 }
4300
8ed5d97e
MC		 4301 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303 if (!netif_carrier_ok(tp->dev))
4304 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4305 tp->pwrmgmt_thresh;
4306 else
4307 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308 tw32(PCIE_PWR_MGMT_THRESH, val);
4309 }
4310
1da177e4
LT		 4311 return err;
4312}
4313
df3e6548
MC		 4314/* This is called whenever we suspect that the system chipset is re-
4315 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316 * is bogus tx completions. We try to recover by setting the
4317 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318 * in the workqueue.
4319 */
4320static void tg3_tx_recover(struct tg3 *tp)
4321{
4322 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4324
4325 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326 "mapped I/O cycles to the network device, attempting to "
4327 "recover. Please report the problem to the driver maintainer "
4328 "and include system chipset information.\n", tp->dev->name);
4329
4330 spin_lock(&tp->lock);
df3e6548 4331 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4332 spin_unlock(&tp->lock);
4333}
4334
f3f3f27e 4335static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4336{
4337 smp_mb();
f3f3f27e
MC		 4338 return tnapi->tx_pending -
4339 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4340}
4341
1da177e4
LT		 4342/* Tigon3 never reports partial packet sends. So we do not
4343 * need special logic to handle SKBs that have not had all
4344 * of their frags sent yet, like SunGEM does.
4345 */
17375d25 4346static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4347{
17375d25 4348 struct tg3 *tp = tnapi->tp;
898a56f8 4349 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4350 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4351 struct netdev_queue *txq;
4352 int index = tnapi - tp->napi;
4353
19cfaecc 4354 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4355 index--;
4356
4357 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4358
4359 while (sw_idx != hw_idx) {
f4188d8a 4360 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4361 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4362 int i, tx_bug = 0;
4363
4364 if (unlikely(skb == NULL)) {
4365 tg3_tx_recover(tp);
4366 return;
4367 }
1da177e4 4368
f4188d8a
AD		 4369 pci_unmap_single(tp->pdev,
4370 pci_unmap_addr(ri, mapping),
4371 skb_headlen(skb),
4372 PCI_DMA_TODEVICE);
1da177e4
LT		 4373
4374 ri->skb = NULL;
4375
4376 sw_idx = NEXT_TX(sw_idx);
4377
4378 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4379 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4380 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4381 tx_bug = 1;
f4188d8a
AD		 4382
4383 pci_unmap_page(tp->pdev,
4384 pci_unmap_addr(ri, mapping),
4385 skb_shinfo(skb)->frags[i].size,
4386 PCI_DMA_TODEVICE);
1da177e4
LT		 4387 sw_idx = NEXT_TX(sw_idx);
4388 }
4389
f47c11ee 4390 dev_kfree_skb(skb);
df3e6548
MC		 4391
4392 if (unlikely(tx_bug)) {
4393 tg3_tx_recover(tp);
4394 return;
4395 }
1da177e4
LT		 4396 }
4397
f3f3f27e 4398 tnapi->tx_cons = sw_idx;
1da177e4 4399
1b2a7205
MC		 4400 /* Need to make the tx_cons update visible to tg3_start_xmit()
4401 * before checking for netif_queue_stopped(). Without the
4402 * memory barrier, there is a small possibility that tg3_start_xmit()
4403 * will miss it and cause the queue to be stopped forever.
4404 */
4405 smp_mb();
4406
fe5f5787 4407 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4408 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4409 __netif_tx_lock(txq, smp_processor_id());
4410 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4411 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4412 netif_tx_wake_queue(txq);
4413 __netif_tx_unlock(txq);
51b91468 4414 }
1da177e4
LT		 4415}
4416
2b2cdb65
MC		 4417static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4418{
4419 if (!ri->skb)
4420 return;
4421
4422 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423 map_sz, PCI_DMA_FROMDEVICE);
4424 dev_kfree_skb_any(ri->skb);
4425 ri->skb = NULL;
4426}
4427
1da177e4
LT		 4428/* Returns size of skb allocated or < 0 on error.
4429 *
4430 * We only need to fill in the address because the other members
4431 * of the RX descriptor are invariant, see tg3_init_rings.
4432 *
4433 * Note the purposeful assymetry of cpu vs. chip accesses. For
4434 * posting buffers we only dirty the first cache line of the RX
4435 * descriptor (containing the address). Whereas for the RX status
4436 * buffers the cpu only reads the last cacheline of the RX descriptor
4437 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4438 */
86b21e59 4439static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4440 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4441{
4442 struct tg3_rx_buffer_desc *desc;
4443 struct ring_info *map, *src_map;
4444 struct sk_buff *skb;
4445 dma_addr_t mapping;
4446 int skb_size, dest_idx;
4447
4448 src_map = NULL;
4449 switch (opaque_key) {
4450 case RXD_OPAQUE_RING_STD:
4451 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4452 desc = &tpr->rx_std[dest_idx];
4453 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4454 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4455 break;
4456
4457 case RXD_OPAQUE_RING_JUMBO:
4458 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4459 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4460 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4461 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4462 break;
4463
4464 default:
4465 return -EINVAL;
855e1111 4466 }
1da177e4
LT		 4467
4468 /* Do not overwrite any of the map or rp information
4469 * until we are sure we can commit to a new buffer.
4470 *
4471 * Callers depend upon this behavior and assume that
4472 * we leave everything unchanged if we fail.
4473 */
287be12e 4474 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4475 if (skb == NULL)
4476 return -ENOMEM;
4477
1da177e4
LT		 4478 skb_reserve(skb, tp->rx_offset);
4479
287be12e 4480 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4481 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4482 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4483 dev_kfree_skb(skb);
4484 return -EIO;
4485 }
1da177e4
LT		 4486
4487 map->skb = skb;
4488 pci_unmap_addr_set(map, mapping, mapping);
4489
1da177e4
LT		 4490 desc->addr_hi = ((u64)mapping >> 32);
4491 desc->addr_lo = ((u64)mapping & 0xffffffff);
4492
4493 return skb_size;
4494}
4495
4496/* We only need to move over in the address because the other
4497 * members of the RX descriptor are invariant. See notes above
4498 * tg3_alloc_rx_skb for full details.
4499 */
a3896167
MC		 4500static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501 struct tg3_rx_prodring_set *dpr,
4502 u32 opaque_key, int src_idx,
4503 u32 dest_idx_unmasked)
1da177e4 4504{
17375d25 4505 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4506 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507 struct ring_info *src_map, *dest_map;
4508 int dest_idx;
a3896167 4509 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4510
4511 switch (opaque_key) {
4512 case RXD_OPAQUE_RING_STD:
4513 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4514 dest_desc = &dpr->rx_std[dest_idx];
4515 dest_map = &dpr->rx_std_buffers[dest_idx];
4516 src_desc = &spr->rx_std[src_idx];
4517 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4518 break;
4519
4520 case RXD_OPAQUE_RING_JUMBO:
4521 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4522 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524 src_desc = &spr->rx_jmb[src_idx].std;
4525 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4526 break;
4527
4528 default:
4529 return;
855e1111 4530 }
1da177e4
LT		 4531
4532 dest_map->skb = src_map->skb;
4533 pci_unmap_addr_set(dest_map, mapping,
4534 pci_unmap_addr(src_map, mapping));
4535 dest_desc->addr_hi = src_desc->addr_hi;
4536 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4537 src_map->skb = NULL;
4538}
4539
1da177e4
LT		 4540/* The RX ring scheme is composed of multiple rings which post fresh
4541 * buffers to the chip, and one special ring the chip uses to report
4542 * status back to the host.
4543 *
4544 * The special ring reports the status of received packets to the
4545 * host. The chip does not write into the original descriptor the
4546 * RX buffer was obtained from. The chip simply takes the original
4547 * descriptor as provided by the host, updates the status and length
4548 * field, then writes this into the next status ring entry.
4549 *
4550 * Each ring the host uses to post buffers to the chip is described
4551 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4552 * it is first placed into the on-chip ram. When the packet's length
4553 * is known, it walks down the TG3_BDINFO entries to select the ring.
4554 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555 * which is within the range of the new packet's length is chosen.
4556 *
4557 * The "separate ring for rx status" scheme may sound queer, but it makes
4558 * sense from a cache coherency perspective. If only the host writes
4559 * to the buffer post rings, and only the chip writes to the rx status
4560 * rings, then cache lines never move beyond shared-modified state.
4561 * If both the host and chip were to write into the same ring, cache line
4562 * eviction could occur since both entities want it in an exclusive state.
4563 */
17375d25 4564static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4565{
17375d25 4566 struct tg3 *tp = tnapi->tp;
f92905de 4567 u32 work_mask, rx_std_posted = 0;
4361935a 4568 u32 std_prod_idx, jmb_prod_idx;
72334482 4569 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4570 u16 hw_idx;
1da177e4 4571 int received;
b196c7e4 4572 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4573
8d9d7cfc 4574 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4575 /*
4576 * We need to order the read of hw_idx and the read of
4577 * the opaque cookie.
4578 */
4579 rmb();
1da177e4
LT		 4580 work_mask = 0;
4581 received = 0;
4361935a
MC		 4582 std_prod_idx = tpr->rx_std_prod_idx;
4583 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4584 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4585 struct ring_info *ri;
72334482 4586 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4587 unsigned int len;
4588 struct sk_buff *skb;
4589 dma_addr_t dma_addr;
4590 u32 opaque_key, desc_idx, *post_ptr;
4591
4592 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4595 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4596 dma_addr = pci_unmap_addr(ri, mapping);
4597 skb = ri->skb;
4361935a 4598 post_ptr = &std_prod_idx;
f92905de 4599 rx_std_posted++;
1da177e4 4600 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4601 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4602 dma_addr = pci_unmap_addr(ri, mapping);
4603 skb = ri->skb;
4361935a 4604 post_ptr = &jmb_prod_idx;
21f581a5 4605 } else
1da177e4 4606 goto next_pkt_nopost;
1da177e4
LT		 4607
4608 work_mask |= opaque_key;
4609
4610 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4612 drop_it:
a3896167 4613 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4614 desc_idx, *post_ptr);
4615 drop_it_no_recycle:
4616 /* Other statistics kept track of by card. */
4617 tp->net_stats.rx_dropped++;
4618 goto next_pkt;
4619 }
4620
ad829268
MC		 4621 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4622 ETH_FCS_LEN;
1da177e4 4623
8e95a202
JP		 4624 if (len > RX_COPY_THRESHOLD &&
4625 tp->rx_offset == NET_IP_ALIGN) {
4626 /* rx_offset will likely not equal NET_IP_ALIGN
4627 * if this is a 5701 card running in PCI-X mode
4628 * [see tg3_get_invariants()]
4629 */
1da177e4
LT		 4630 int skb_size;
4631
86b21e59 4632 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4633 *post_ptr);
1da177e4
LT		 4634 if (skb_size < 0)
4635 goto drop_it;
4636
afc081f8
MC		 4637 ri->skb = NULL;
4638
287be12e 4639 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4640 PCI_DMA_FROMDEVICE);
4641
4642 skb_put(skb, len);
4643 } else {
4644 struct sk_buff *copy_skb;
4645
a3896167 4646 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4647 desc_idx, *post_ptr);
4648
ad829268
MC		 4649 copy_skb = netdev_alloc_skb(tp->dev,
4650 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4651 if (copy_skb == NULL)
4652 goto drop_it_no_recycle;
4653
ad829268 4654 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4655 skb_put(copy_skb, len);
4656 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4657 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4658 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4659
4660 /* We'll reuse the original ring buffer. */
4661 skb = copy_skb;
4662 }
4663
4664 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4665 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4666 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4667 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4668 skb->ip_summed = CHECKSUM_UNNECESSARY;
4669 else
4670 skb->ip_summed = CHECKSUM_NONE;
4671
4672 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4673
4674 if (len > (tp->dev->mtu + ETH_HLEN) &&
4675 skb->protocol != htons(ETH_P_8021Q)) {
4676 dev_kfree_skb(skb);
4677 goto next_pkt;
4678 }
4679
1da177e4
LT		 4680#if TG3_VLAN_TAG_USED
4681 if (tp->vlgrp != NULL &&
4682 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4683 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4684 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4685 } else
4686#endif
17375d25 4687 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4688
1da177e4
LT		 4689 received++;
4690 budget--;
4691
4692next_pkt:
4693 (*post_ptr)++;
f92905de
MC		 4694
4695 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4696 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4697 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4698 tpr->rx_std_prod_idx);
f92905de
MC		 4699 work_mask &= ~RXD_OPAQUE_RING_STD;
4700 rx_std_posted = 0;
4701 }
1da177e4 4702next_pkt_nopost:
483ba50b 4703 sw_idx++;
6b31a515 4704 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4705
4706 /* Refresh hw_idx to see if there is new work */
4707 if (sw_idx == hw_idx) {
8d9d7cfc 4708 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4709 rmb();
4710 }
1da177e4
LT		 4711 }
4712
4713 /* ACK the status ring. */
72334482
MC		 4714 tnapi->rx_rcb_ptr = sw_idx;
4715 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4716
4717 /* Refill RX ring(s). */
b196c7e4
MC		 4718 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4719 if (work_mask & RXD_OPAQUE_RING_STD) {
4720 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4721 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4722 tpr->rx_std_prod_idx);
4723 }
4724 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4725 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4726 TG3_RX_JUMBO_RING_SIZE;
4727 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4728 tpr->rx_jmb_prod_idx);
4729 }
4730 mmiowb();
4731 } else if (work_mask) {
4732 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4733 * updated before the producer indices can be updated.
4734 */
4735 smp_wmb();
4736
4361935a 4737 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4738 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4
MC		 4739
4740 napi_schedule(&tp->napi[1].napi);
1da177e4 4741 }
1da177e4
LT		 4742
4743 return received;
4744}
4745
35f2d7d0 4746static void tg3_poll_link(struct tg3 *tp)
1da177e4 4747{
1da177e4
LT		 4748 /* handle link change and other phy events */
4749 if (!(tp->tg3_flags &
4750 (TG3_FLAG_USE_LINKCHG_REG |
4751 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4752 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4753
1da177e4
LT		 4754 if (sblk->status & SD_STATUS_LINK_CHG) {
4755 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4756 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4757 spin_lock(&tp->lock);
dd477003
MC		 4758 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4759 tw32_f(MAC_STATUS,
4760 (MAC_STATUS_SYNC_CHANGED |
4761 MAC_STATUS_CFG_CHANGED |
4762 MAC_STATUS_MI_COMPLETION |
4763 MAC_STATUS_LNKSTATE_CHANGED));
4764 udelay(40);
4765 } else
4766 tg3_setup_phy(tp, 0);
f47c11ee 4767 spin_unlock(&tp->lock);
1da177e4
LT		 4768 }
4769 }
35f2d7d0
MC		 4770}
4771
b196c7e4
MC		 4772static void tg3_rx_prodring_xfer(struct tg3 *tp,
4773 struct tg3_rx_prodring_set *dpr,
4774 struct tg3_rx_prodring_set *spr)
4775{
4776 u32 si, di, cpycnt, src_prod_idx;
4777 int i;
4778
4779 while (1) {
4780 src_prod_idx = spr->rx_std_prod_idx;
4781
4782 /* Make sure updates to the rx_std_buffers[] entries and the
4783 * standard producer index are seen in the correct order.
4784 */
4785 smp_rmb();
4786
4787 if (spr->rx_std_cons_idx == src_prod_idx)
4788 break;
4789
4790 if (spr->rx_std_cons_idx < src_prod_idx)
4791 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4792 else
4793 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4794
4795 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4796
4797 si = spr->rx_std_cons_idx;
4798 di = dpr->rx_std_prod_idx;
4799
4800 memcpy(&dpr->rx_std_buffers[di],
4801 &spr->rx_std_buffers[si],
4802 cpycnt * sizeof(struct ring_info));
4803
4804 for (i = 0; i < cpycnt; i++, di++, si++) {
4805 struct tg3_rx_buffer_desc *sbd, *dbd;
4806 sbd = &spr->rx_std[si];
4807 dbd = &dpr->rx_std[di];
4808 dbd->addr_hi = sbd->addr_hi;
4809 dbd->addr_lo = sbd->addr_lo;
4810 }
4811
4812 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4813 TG3_RX_RING_SIZE;
4814 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4815 TG3_RX_RING_SIZE;
4816 }
4817
4818 while (1) {
4819 src_prod_idx = spr->rx_jmb_prod_idx;
4820
4821 /* Make sure updates to the rx_jmb_buffers[] entries and
4822 * the jumbo producer index are seen in the correct order.
4823 */
4824 smp_rmb();
4825
4826 if (spr->rx_jmb_cons_idx == src_prod_idx)
4827 break;
4828
4829 if (spr->rx_jmb_cons_idx < src_prod_idx)
4830 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4831 else
4832 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4833
4834 cpycnt = min(cpycnt,
4835 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4836
4837 si = spr->rx_jmb_cons_idx;
4838 di = dpr->rx_jmb_prod_idx;
4839
4840 memcpy(&dpr->rx_jmb_buffers[di],
4841 &spr->rx_jmb_buffers[si],
4842 cpycnt * sizeof(struct ring_info));
4843
4844 for (i = 0; i < cpycnt; i++, di++, si++) {
4845 struct tg3_rx_buffer_desc *sbd, *dbd;
4846 sbd = &spr->rx_jmb[si].std;
4847 dbd = &dpr->rx_jmb[di].std;
4848 dbd->addr_hi = sbd->addr_hi;
4849 dbd->addr_lo = sbd->addr_lo;
4850 }
4851
4852 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4853 TG3_RX_JUMBO_RING_SIZE;
4854 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4855 TG3_RX_JUMBO_RING_SIZE;
4856 }
4857}
4858
35f2d7d0
MC		 4859static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4860{
4861 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4862
4863 /* run TX completion thread */
f3f3f27e 4864 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4865 tg3_tx(tnapi);
6f535763 4866 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4867 return work_done;
1da177e4
LT		 4868 }
4869
1da177e4
LT		 4870 /* run RX thread, within the bounds set by NAPI.
4871 * All RX "locking" is done by ensuring outside
bea3348e 4872 * code synchronizes with tg3->napi.poll()
1da177e4 4873 */
8d9d7cfc 4874 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4875 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4876
b196c7e4
MC		 4877 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4878 int i;
4879 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4880 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4881
4882 for (i = 2; i < tp->irq_cnt; i++)
4883 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4884 tp->napi[i].prodring);
4885
4886 wmb();
4887
4888 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4889 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4890 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4891 }
4892
4893 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4894 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4895 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4896 }
4897
4898 mmiowb();
4899 }
4900
6f535763
DM		 4901 return work_done;
4902}
4903
35f2d7d0
MC		 4904static int tg3_poll_msix(struct napi_struct *napi, int budget)
4905{
4906 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4907 struct tg3 *tp = tnapi->tp;
4908 int work_done = 0;
4909 struct tg3_hw_status *sblk = tnapi->hw_status;
4910
4911 while (1) {
4912 work_done = tg3_poll_work(tnapi, work_done, budget);
4913
4914 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4915 goto tx_recovery;
4916
4917 if (unlikely(work_done >= budget))
4918 break;
4919
4920 /* tp->last_tag is used in tg3_restart_ints() below
4921 * to tell the hw how much work has been processed,
4922 * so we must read it before checking for more work.
4923 */
4924 tnapi->last_tag = sblk->status_tag;
4925 tnapi->last_irq_tag = tnapi->last_tag;
4926 rmb();
4927
4928 /* check for RX/TX work to do */
4929 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4930 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4931 napi_complete(napi);
4932 /* Reenable interrupts. */
4933 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4934 mmiowb();
4935 break;
4936 }
4937 }
4938
4939 return work_done;
4940
4941tx_recovery:
4942 /* work_done is guaranteed to be less than budget. */
4943 napi_complete(napi);
4944 schedule_work(&tp->reset_task);
4945 return work_done;
4946}
4947
6f535763
DM		 4948static int tg3_poll(struct napi_struct *napi, int budget)
4949{
8ef0442f
MC		 4950 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4951 struct tg3 *tp = tnapi->tp;
6f535763 4952 int work_done = 0;
898a56f8 4953 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4954
4955 while (1) {
35f2d7d0
MC		 4956 tg3_poll_link(tp);
4957
17375d25 4958 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4959
4960 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4961 goto tx_recovery;
4962
4963 if (unlikely(work_done >= budget))
4964 break;
4965
4fd7ab59 4966 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4967 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4968 * to tell the hw how much work has been processed,
4969 * so we must read it before checking for more work.
4970 */
898a56f8
MC		 4971 tnapi->last_tag = sblk->status_tag;
4972 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4973 rmb();
4974 } else
4975 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4976
17375d25 4977 if (likely(!tg3_has_work(tnapi))) {
288379f0 4978 napi_complete(napi);
17375d25 4979 tg3_int_reenable(tnapi);
6f535763
DM		 4980 break;
4981 }
1da177e4
LT		 4982 }
4983
bea3348e 4984 return work_done;
6f535763
DM		 4985
4986tx_recovery:
4fd7ab59 4987 /* work_done is guaranteed to be less than budget. */
288379f0 4988 napi_complete(napi);
6f535763 4989 schedule_work(&tp->reset_task);
4fd7ab59 4990 return work_done;
1da177e4
LT		 4991}
4992
f47c11ee
DM		 4993static void tg3_irq_quiesce(struct tg3 *tp)
4994{
4f125f42
MC		 4995 int i;
4996
f47c11ee
DM		 4997 BUG_ON(tp->irq_sync);
4998
4999 tp->irq_sync = 1;
5000 smp_mb();
5001
4f125f42
MC		 5002 for (i = 0; i < tp->irq_cnt; i++)
5003 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5004}
5005
5006static inline int tg3_irq_sync(struct tg3 *tp)
5007{
5008 return tp->irq_sync;
5009}
5010
5011/* Fully shutdown all tg3 driver activity elsewhere in the system.
5012 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5013 * with as well. Most of the time, this is not necessary except when
5014 * shutting down the device.
5015 */
5016static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5017{
46966545 5018 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5019 if (irq_sync)
5020 tg3_irq_quiesce(tp);
f47c11ee
DM		 5021}
5022
5023static inline void tg3_full_unlock(struct tg3 *tp)
5024{
f47c11ee
DM		 5025 spin_unlock_bh(&tp->lock);
5026}
5027
fcfa0a32
MC		 5028/* One-shot MSI handler - Chip automatically disables interrupt
5029 * after sending MSI so driver doesn't have to do it.
5030 */
7d12e780 5031static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5032{
09943a18
MC		 5033 struct tg3_napi *tnapi = dev_id;
5034 struct tg3 *tp = tnapi->tp;
fcfa0a32 5035
898a56f8 5036 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5037 if (tnapi->rx_rcb)
5038 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5039
5040 if (likely(!tg3_irq_sync(tp)))
09943a18 5041 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5042
5043 return IRQ_HANDLED;
5044}
5045
88b06bc2
MC		 5046/* MSI ISR - No need to check for interrupt sharing and no need to
5047 * flush status block and interrupt mailbox. PCI ordering rules
5048 * guarantee that MSI will arrive after the status block.
5049 */
7d12e780 5050static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5051{
09943a18
MC		 5052 struct tg3_napi *tnapi = dev_id;
5053 struct tg3 *tp = tnapi->tp;
88b06bc2 5054
898a56f8 5055 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5056 if (tnapi->rx_rcb)
5057 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5058 /*
fac9b83e 5059 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5060 * chip-internal interrupt pending events.
fac9b83e 5061 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5062 * NIC to stop sending us irqs, engaging "in-intr-handler"
5063 * event coalescing.
5064 */
5065 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5066 if (likely(!tg3_irq_sync(tp)))
09943a18 5067 napi_schedule(&tnapi->napi);
61487480 5068
88b06bc2
MC		 5069 return IRQ_RETVAL(1);
5070}
5071
7d12e780 5072static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5073{
09943a18
MC		 5074 struct tg3_napi *tnapi = dev_id;
5075 struct tg3 *tp = tnapi->tp;
898a56f8 5076 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5077 unsigned int handled = 1;
5078
1da177e4
LT		 5079 /* In INTx mode, it is possible for the interrupt to arrive at
5080 * the CPU before the status block posted prior to the interrupt.
5081 * Reading the PCI State register will confirm whether the
5082 * interrupt is ours and will flush the status block.
5083 */
d18edcb2
MC		 5084 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5085 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5086 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5087 handled = 0;
f47c11ee 5088 goto out;
fac9b83e 5089 }
d18edcb2
MC		 5090 }
5091
5092 /*
5093 * Writing any value to intr-mbox-0 clears PCI INTA# and
5094 * chip-internal interrupt pending events.
5095 * Writing non-zero to intr-mbox-0 additional tells the
5096 * NIC to stop sending us irqs, engaging "in-intr-handler"
5097 * event coalescing.
c04cb347
MC		 5098 *
5099 * Flush the mailbox to de-assert the IRQ immediately to prevent
5100 * spurious interrupts. The flush impacts performance but
5101 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5102 */
c04cb347 5103 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5104 if (tg3_irq_sync(tp))
5105 goto out;
5106 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5107 if (likely(tg3_has_work(tnapi))) {
72334482 5108 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5109 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5110 } else {
5111 /* No work, shared interrupt perhaps? re-enable
5112 * interrupts, and flush that PCI write
5113 */
5114 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5115 0x00000000);
fac9b83e 5116 }
f47c11ee 5117out:
fac9b83e
DM		 5118 return IRQ_RETVAL(handled);
5119}
5120
7d12e780 5121static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5122{
09943a18
MC		 5123 struct tg3_napi *tnapi = dev_id;
5124 struct tg3 *tp = tnapi->tp;
898a56f8 5125 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5126 unsigned int handled = 1;
5127
fac9b83e
DM		 5128 /* In INTx mode, it is possible for the interrupt to arrive at
5129 * the CPU before the status block posted prior to the interrupt.
5130 * Reading the PCI State register will confirm whether the
5131 * interrupt is ours and will flush the status block.
5132 */
898a56f8 5133 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5134 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5135 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5136 handled = 0;
f47c11ee 5137 goto out;
1da177e4 5138 }
d18edcb2
MC		 5139 }
5140
5141 /*
5142 * writing any value to intr-mbox-0 clears PCI INTA# and
5143 * chip-internal interrupt pending events.
5144 * writing non-zero to intr-mbox-0 additional tells the
5145 * NIC to stop sending us irqs, engaging "in-intr-handler"
5146 * event coalescing.
c04cb347
MC		 5147 *
5148 * Flush the mailbox to de-assert the IRQ immediately to prevent
5149 * spurious interrupts. The flush impacts performance but
5150 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5151 */
c04cb347 5152 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5153
5154 /*
5155 * In a shared interrupt configuration, sometimes other devices'
5156 * interrupts will scream. We record the current status tag here
5157 * so that the above check can report that the screaming interrupts
5158 * are unhandled. Eventually they will be silenced.
5159 */
898a56f8 5160 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5161
d18edcb2
MC		 5162 if (tg3_irq_sync(tp))
5163 goto out;
624f8e50 5164
72334482 5165 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5166
09943a18 5167 napi_schedule(&tnapi->napi);
624f8e50 5168
f47c11ee 5169out:
1da177e4
LT		 5170 return IRQ_RETVAL(handled);
5171}
5172
7938109f 5173/* ISR for interrupt test */
7d12e780 5174static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5175{
09943a18
MC		 5176 struct tg3_napi *tnapi = dev_id;
5177 struct tg3 *tp = tnapi->tp;
898a56f8 5178 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5179
f9804ddb
MC		 5180 if ((sblk->status & SD_STATUS_UPDATED) ||
5181 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5182 tg3_disable_ints(tp);
7938109f
MC		 5183 return IRQ_RETVAL(1);
5184 }
5185 return IRQ_RETVAL(0);
5186}
5187
8e7a22e3 5188static int tg3_init_hw(struct tg3 *, int);
944d980e 5189static int tg3_halt(struct tg3 *, int, int);
1da177e4 5190
b9ec6c1b
MC		 5191/* Restart hardware after configuration changes, self-test, etc.
5192 * Invoked with tp->lock held.
5193 */
5194static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5195 __releases(tp->lock)
5196 __acquires(tp->lock)
b9ec6c1b
MC		 5197{
5198 int err;
5199
5200 err = tg3_init_hw(tp, reset_phy);
5201 if (err) {
5202 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5203 "aborting.\n", tp->dev->name);
5204 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5205 tg3_full_unlock(tp);
5206 del_timer_sync(&tp->timer);
5207 tp->irq_sync = 0;
fed97810 5208 tg3_napi_enable(tp);
b9ec6c1b
MC		 5209 dev_close(tp->dev);
5210 tg3_full_lock(tp, 0);
5211 }
5212 return err;
5213}
5214
1da177e4
LT		 5215#ifdef CONFIG_NET_POLL_CONTROLLER
5216static void tg3_poll_controller(struct net_device *dev)
5217{
4f125f42 5218 int i;
88b06bc2
MC		 5219 struct tg3 *tp = netdev_priv(dev);
5220
4f125f42
MC		 5221 for (i = 0; i < tp->irq_cnt; i++)
5222 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5223}
5224#endif
5225
c4028958 5226static void tg3_reset_task(struct work_struct *work)
1da177e4 5227{
c4028958 5228 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5229 int err;
1da177e4
LT		 5230 unsigned int restart_timer;
5231
7faa006f 5232 tg3_full_lock(tp, 0);
7faa006f
MC		 5233
5234 if (!netif_running(tp->dev)) {
7faa006f
MC		 5235 tg3_full_unlock(tp);
5236 return;
5237 }
5238
5239 tg3_full_unlock(tp);
5240
b02fd9e3
MC		 5241 tg3_phy_stop(tp);
5242
1da177e4
LT		 5243 tg3_netif_stop(tp);
5244
f47c11ee 5245 tg3_full_lock(tp, 1);
1da177e4
LT		 5246
5247 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5248 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5249
df3e6548
MC		 5250 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5251 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5252 tp->write32_rx_mbox = tg3_write_flush_reg32;
5253 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5254 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5255 }
5256
944d980e 5257 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5258 err = tg3_init_hw(tp, 1);
5259 if (err)
b9ec6c1b 5260 goto out;
1da177e4
LT		 5261
5262 tg3_netif_start(tp);
5263
1da177e4
LT		 5264 if (restart_timer)
5265 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5266
b9ec6c1b 5267out:
7faa006f 5268 tg3_full_unlock(tp);
b02fd9e3
MC		 5269
5270 if (!err)
5271 tg3_phy_start(tp);
1da177e4
LT		 5272}
5273
b0408751
MC		 5274static void tg3_dump_short_state(struct tg3 *tp)
5275{
5276 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5277 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5278 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5279 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5280}
5281
1da177e4
LT		 5282static void tg3_tx_timeout(struct net_device *dev)
5283{
5284 struct tg3 *tp = netdev_priv(dev);
5285
b0408751 5286 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5287 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5288 dev->name);
b0408751
MC		 5289 tg3_dump_short_state(tp);
5290 }
1da177e4
LT		 5291
5292 schedule_work(&tp->reset_task);
5293}
5294
c58ec932
MC		 5295/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5296static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5297{
5298 u32 base = (u32) mapping & 0xffffffff;
5299
5300 return ((base > 0xffffdcc0) &&
5301 (base + len + 8 < base));
5302}
5303
72f2afb8
MC		 5304/* Test for DMA addresses > 40-bit */
5305static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5306 int len)
5307{
5308#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5309 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5310 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5311 return 0;
5312#else
5313 return 0;
5314#endif
5315}
5316
f3f3f27e 5317static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5318
72f2afb8 5319/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5320static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5321 struct sk_buff *skb, u32 last_plus_one,
5322 u32 *start, u32 base_flags, u32 mss)
1da177e4 5323{
24f4efd4 5324 struct tg3 *tp = tnapi->tp;
41588ba1 5325 struct sk_buff *new_skb;
c58ec932 5326 dma_addr_t new_addr = 0;
1da177e4 5327 u32 entry = *start;
c58ec932 5328 int i, ret = 0;
1da177e4 5329
41588ba1
MC		 5330 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5331 new_skb = skb_copy(skb, GFP_ATOMIC);
5332 else {
5333 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5334
5335 new_skb = skb_copy_expand(skb,
5336 skb_headroom(skb) + more_headroom,
5337 skb_tailroom(skb), GFP_ATOMIC);
5338 }
5339
1da177e4 5340 if (!new_skb) {
c58ec932
MC		 5341 ret = -1;
5342 } else {
5343 /* New SKB is guaranteed to be linear. */
5344 entry = *start;
f4188d8a
AD		 5345 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5346 PCI_DMA_TODEVICE);
5347 /* Make sure the mapping succeeded */
5348 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5349 ret = -1;
5350 dev_kfree_skb(new_skb);
5351 new_skb = NULL;
90079ce8 5352
c58ec932
MC		 5353 /* Make sure new skb does not cross any 4G boundaries.
5354 * Drop the packet if it does.
5355 */
f4188d8a
AD		 5356 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5357 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5358 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5359 PCI_DMA_TODEVICE);
c58ec932
MC		 5360 ret = -1;
5361 dev_kfree_skb(new_skb);
5362 new_skb = NULL;
5363 } else {
f3f3f27e 5364 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5365 base_flags, 1 | (mss << 1));
5366 *start = NEXT_TX(entry);
5367 }
1da177e4
LT		 5368 }
5369
1da177e4
LT		 5370 /* Now clean up the sw ring entries. */
5371 i = 0;
5372 while (entry != last_plus_one) {
f4188d8a
AD		 5373 int len;
5374
f3f3f27e 5375 if (i == 0)
f4188d8a 5376 len = skb_headlen(skb);
f3f3f27e 5377 else
f4188d8a
AD		 5378 len = skb_shinfo(skb)->frags[i-1].size;
5379
5380 pci_unmap_single(tp->pdev,
5381 pci_unmap_addr(&tnapi->tx_buffers[entry],
5382 mapping),
5383 len, PCI_DMA_TODEVICE);
5384 if (i == 0) {
5385 tnapi->tx_buffers[entry].skb = new_skb;
5386 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5387 new_addr);
5388 } else {
f3f3f27e 5389 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5390 }
1da177e4
LT		 5391 entry = NEXT_TX(entry);
5392 i++;
5393 }
5394
5395 dev_kfree_skb(skb);
5396
c58ec932 5397 return ret;
1da177e4
LT		 5398}
5399
f3f3f27e 5400static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5401 dma_addr_t mapping, int len, u32 flags,
5402 u32 mss_and_is_end)
5403{
f3f3f27e 5404 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5405 int is_end = (mss_and_is_end & 0x1);
5406 u32 mss = (mss_and_is_end >> 1);
5407 u32 vlan_tag = 0;
5408
5409 if (is_end)
5410 flags |= TXD_FLAG_END;
5411 if (flags & TXD_FLAG_VLAN) {
5412 vlan_tag = flags >> 16;
5413 flags &= 0xffff;
5414 }
5415 vlan_tag |= (mss << TXD_MSS_SHIFT);
5416
5417 txd->addr_hi = ((u64) mapping >> 32);
5418 txd->addr_lo = ((u64) mapping & 0xffffffff);
5419 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5420 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5421}
5422
5a6f3074 5423/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5424 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5425 */
61357325
SH		 5426static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5427 struct net_device *dev)
5a6f3074
MC		 5428{
5429 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5430 u32 len, entry, base_flags, mss;
90079ce8 5431 dma_addr_t mapping;
fe5f5787
MC		 5432 struct tg3_napi *tnapi;
5433 struct netdev_queue *txq;
f4188d8a
AD		 5434 unsigned int i, last;
5435
5a6f3074 5436
fe5f5787
MC		 5437 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5438 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5439 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5440 tnapi++;
5a6f3074 5441
00b70504 5442 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5443 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5444 * interrupt. Furthermore, IRQ processing runs lockless so we have
5445 * no IRQ context deadlocks to worry about either. Rejoice!
5446 */
f3f3f27e 5447 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5448 if (!netif_tx_queue_stopped(txq)) {
5449 netif_tx_stop_queue(txq);
5a6f3074
MC		 5450
5451 /* This is a hard error, log it. */
5452 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5453 "queue awake!\n", dev->name);
5454 }
5a6f3074
MC		 5455 return NETDEV_TX_BUSY;
5456 }
5457
f3f3f27e 5458 entry = tnapi->tx_prod;
5a6f3074 5459 base_flags = 0;
5a6f3074 5460 mss = 0;
c13e3713 5461 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5462 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5463 u32 hdrlen;
5a6f3074
MC		 5464
5465 if (skb_header_cloned(skb) &&
5466 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5467 dev_kfree_skb(skb);
5468 goto out_unlock;
5469 }
5470
b0026624 5471 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5472 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5473 else {
eddc9ec5
ACM		 5474 struct iphdr *iph = ip_hdr(skb);
5475
ab6a5bb6 5476 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5477 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5478
eddc9ec5
ACM		 5479 iph->check = 0;
5480 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5481 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5482 }
5a6f3074 5483
e849cdc3 5484 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5485 mss |= (hdrlen & 0xc) << 12;
5486 if (hdrlen & 0x10)
5487 base_flags |= 0x00000010;
5488 base_flags |= (hdrlen & 0x3e0) << 5;
5489 } else
5490 mss |= hdrlen << 9;
5491
5a6f3074
MC		 5492 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5493 TXD_FLAG_CPU_POST_DMA);
5494
aa8223c7 5495 tcp_hdr(skb)->check = 0;
5a6f3074 5496
5a6f3074 5497 }
84fa7933 5498 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5499 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5500#if TG3_VLAN_TAG_USED
5501 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5502 base_flags |= (TXD_FLAG_VLAN |
5503 (vlan_tx_tag_get(skb) << 16));
5504#endif
5505
f4188d8a
AD		 5506 len = skb_headlen(skb);
5507
5508 /* Queue skb data, a.k.a. the main skb fragment. */
5509 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5510 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5511 dev_kfree_skb(skb);
5512 goto out_unlock;
5513 }
5514
f3f3f27e 5515 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5516 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5517
b703df6f 5518 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5519 !mss && skb->len > ETH_DATA_LEN)
5520 base_flags |= TXD_FLAG_JMB_PKT;
5521
f3f3f27e 5522 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5523 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5524
5525 entry = NEXT_TX(entry);
5526
5527 /* Now loop through additional data fragments, and queue them. */
5528 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5529 last = skb_shinfo(skb)->nr_frags - 1;
5530 for (i = 0; i <= last; i++) {
5531 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5532
5533 len = frag->size;
f4188d8a
AD		 5534 mapping = pci_map_page(tp->pdev,
5535 frag->page,
5536 frag->page_offset,
5537 len, PCI_DMA_TODEVICE);
5538 if (pci_dma_mapping_error(tp->pdev, mapping))
5539 goto dma_error;
5540
f3f3f27e 5541 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5542 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5543 mapping);
5a6f3074 5544
f3f3f27e 5545 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5546 base_flags, (i == last) | (mss << 1));
5547
5548 entry = NEXT_TX(entry);
5549 }
5550 }
5551
5552 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5553 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5554
f3f3f27e
MC		 5555 tnapi->tx_prod = entry;
5556 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5557 netif_tx_stop_queue(txq);
f3f3f27e 5558 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5559 netif_tx_wake_queue(txq);
5a6f3074
MC		 5560 }
5561
5562out_unlock:
cdd0db05 5563 mmiowb();
5a6f3074
MC		 5564
5565 return NETDEV_TX_OK;
f4188d8a
AD		 5566
5567dma_error:
5568 last = i;
5569 entry = tnapi->tx_prod;
5570 tnapi->tx_buffers[entry].skb = NULL;
5571 pci_unmap_single(tp->pdev,
5572 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5573 skb_headlen(skb),
5574 PCI_DMA_TODEVICE);
5575 for (i = 0; i <= last; i++) {
5576 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5577 entry = NEXT_TX(entry);
5578
5579 pci_unmap_page(tp->pdev,
5580 pci_unmap_addr(&tnapi->tx_buffers[entry],
5581 mapping),
5582 frag->size, PCI_DMA_TODEVICE);
5583 }
5584
5585 dev_kfree_skb(skb);
5586 return NETDEV_TX_OK;
5a6f3074
MC		 5587}
5588
61357325
SH		 5589static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5590 struct net_device *);
52c0fd83
MC		 5591
5592/* Use GSO to workaround a rare TSO bug that may be triggered when the
5593 * TSO header is greater than 80 bytes.
5594 */
5595static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5596{
5597 struct sk_buff *segs, *nskb;
f3f3f27e 5598 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5599
5600 /* Estimate the number of fragments in the worst case */
f3f3f27e 5601 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5602 netif_stop_queue(tp->dev);
f3f3f27e 5603 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5604 return NETDEV_TX_BUSY;
5605
5606 netif_wake_queue(tp->dev);
52c0fd83
MC		 5607 }
5608
5609 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5610 if (IS_ERR(segs))
52c0fd83
MC		 5611 goto tg3_tso_bug_end;
5612
5613 do {
5614 nskb = segs;
5615 segs = segs->next;
5616 nskb->next = NULL;
5617 tg3_start_xmit_dma_bug(nskb, tp->dev);
5618 } while (segs);
5619
5620tg3_tso_bug_end:
5621 dev_kfree_skb(skb);
5622
5623 return NETDEV_TX_OK;
5624}
52c0fd83 5625
5a6f3074
MC		 5626/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5627 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5628 */
61357325
SH		 5629static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5630 struct net_device *dev)
1da177e4
LT		 5631{
5632 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5633 u32 len, entry, base_flags, mss;
5634 int would_hit_hwbug;
90079ce8 5635 dma_addr_t mapping;
24f4efd4
MC		 5636 struct tg3_napi *tnapi;
5637 struct netdev_queue *txq;
f4188d8a
AD		 5638 unsigned int i, last;
5639
1da177e4 5640
24f4efd4
MC		 5641 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5642 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5643 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5644 tnapi++;
1da177e4 5645
00b70504 5646 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5647 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5648 * interrupt. Furthermore, IRQ processing runs lockless so we have
5649 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5650 */
f3f3f27e 5651 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5652 if (!netif_tx_queue_stopped(txq)) {
5653 netif_tx_stop_queue(txq);
1f064a87
SH		 5654
5655 /* This is a hard error, log it. */
5656 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5657 "queue awake!\n", dev->name);
5658 }
1da177e4
LT		 5659 return NETDEV_TX_BUSY;
5660 }
5661
f3f3f27e 5662 entry = tnapi->tx_prod;
1da177e4 5663 base_flags = 0;
84fa7933 5664 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5665 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5666
c13e3713 5667 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5668 struct iphdr *iph;
92c6b8d1 5669 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5670
5671 if (skb_header_cloned(skb) &&
5672 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5673 dev_kfree_skb(skb);
5674 goto out_unlock;
5675 }
5676
ab6a5bb6 5677 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5678 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5679
52c0fd83
MC		 5680 hdr_len = ip_tcp_len + tcp_opt_len;
5681 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5682 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5683 return (tg3_tso_bug(tp, skb));
5684
1da177e4
LT		 5685 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5686 TXD_FLAG_CPU_POST_DMA);
5687
eddc9ec5
ACM		 5688 iph = ip_hdr(skb);
5689 iph->check = 0;
5690 iph->tot_len = htons(mss + hdr_len);
1da177e4 5691 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5692 tcp_hdr(skb)->check = 0;
1da177e4 5693 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5694 } else
5695 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5696 iph->daddr, 0,
5697 IPPROTO_TCP,
5698 0);
1da177e4 5699
615774fe
MC		 5700 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5701 mss |= (hdr_len & 0xc) << 12;
5702 if (hdr_len & 0x10)
5703 base_flags |= 0x00000010;
5704 base_flags |= (hdr_len & 0x3e0) << 5;
5705 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5706 mss |= hdr_len << 9;
5707 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5709 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5710 int tsflags;
5711
eddc9ec5 5712 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5713 mss |= (tsflags << 11);
5714 }
5715 } else {
eddc9ec5 5716 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5717 int tsflags;
5718
eddc9ec5 5719 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5720 base_flags |= tsflags << 12;
5721 }
5722 }
5723 }
1da177e4
LT		 5724#if TG3_VLAN_TAG_USED
5725 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5726 base_flags |= (TXD_FLAG_VLAN |
5727 (vlan_tx_tag_get(skb) << 16));
5728#endif
5729
b703df6f 5730 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5731 !mss && skb->len > ETH_DATA_LEN)
5732 base_flags |= TXD_FLAG_JMB_PKT;
5733
f4188d8a
AD		 5734 len = skb_headlen(skb);
5735
5736 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5737 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5738 dev_kfree_skb(skb);
5739 goto out_unlock;
5740 }
5741
f3f3f27e 5742 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5743 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5744
5745 would_hit_hwbug = 0;
5746
92c6b8d1
MC		 5747 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5748 would_hit_hwbug = 1;
5749
0e1406dd
MC		 5750 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5751 tg3_4g_overflow_test(mapping, len))
5752 would_hit_hwbug = 1;
5753
5754 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5755 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5756 would_hit_hwbug = 1;
0e1406dd
MC		 5757
5758 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5759 would_hit_hwbug = 1;
1da177e4 5760
f3f3f27e 5761 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5762 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5763
5764 entry = NEXT_TX(entry);
5765
5766 /* Now loop through additional data fragments, and queue them. */
5767 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5768 last = skb_shinfo(skb)->nr_frags - 1;
5769 for (i = 0; i <= last; i++) {
5770 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5771
5772 len = frag->size;
f4188d8a
AD		 5773 mapping = pci_map_page(tp->pdev,
5774 frag->page,
5775 frag->page_offset,
5776 len, PCI_DMA_TODEVICE);
1da177e4 5777
f3f3f27e 5778 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5779 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5780 mapping);
5781 if (pci_dma_mapping_error(tp->pdev, mapping))
5782 goto dma_error;
1da177e4 5783
92c6b8d1
MC		 5784 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5785 len <= 8)
5786 would_hit_hwbug = 1;
5787
0e1406dd
MC		 5788 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5789 tg3_4g_overflow_test(mapping, len))
c58ec932 5790 would_hit_hwbug = 1;
1da177e4 5791
0e1406dd
MC		 5792 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5793 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5794 would_hit_hwbug = 1;
5795
1da177e4 5796 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5797 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5798 base_flags, (i == last)|(mss << 1));
5799 else
f3f3f27e 5800 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5801 base_flags, (i == last));
5802
5803 entry = NEXT_TX(entry);
5804 }
5805 }
5806
5807 if (would_hit_hwbug) {
5808 u32 last_plus_one = entry;
5809 u32 start;
1da177e4 5810
c58ec932
MC		 5811 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5812 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5813
5814 /* If the workaround fails due to memory/mapping
5815 * failure, silently drop this packet.
5816 */
24f4efd4 5817 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5818 &start, base_flags, mss))
1da177e4
LT		 5819 goto out_unlock;
5820
5821 entry = start;
5822 }
5823
5824 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5825 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5826
f3f3f27e
MC		 5827 tnapi->tx_prod = entry;
5828 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5829 netif_tx_stop_queue(txq);
f3f3f27e 5830 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5831 netif_tx_wake_queue(txq);
51b91468 5832 }
1da177e4
LT		 5833
5834out_unlock:
cdd0db05 5835 mmiowb();
1da177e4
LT		 5836
5837 return NETDEV_TX_OK;
f4188d8a
AD		 5838
5839dma_error:
5840 last = i;
5841 entry = tnapi->tx_prod;
5842 tnapi->tx_buffers[entry].skb = NULL;
5843 pci_unmap_single(tp->pdev,
5844 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5845 skb_headlen(skb),
5846 PCI_DMA_TODEVICE);
5847 for (i = 0; i <= last; i++) {
5848 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5849 entry = NEXT_TX(entry);
5850
5851 pci_unmap_page(tp->pdev,
5852 pci_unmap_addr(&tnapi->tx_buffers[entry],
5853 mapping),
5854 frag->size, PCI_DMA_TODEVICE);
5855 }
5856
5857 dev_kfree_skb(skb);
5858 return NETDEV_TX_OK;
1da177e4
LT		 5859}
5860
5861static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5862 int new_mtu)
5863{
5864 dev->mtu = new_mtu;
5865
ef7f5ec0 5866 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5867 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5868 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5869 ethtool_op_set_tso(dev, 0);
5870 }
5871 else
5872 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5873 } else {
a4e2b347 5874 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5875 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5876 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5877 }
1da177e4
LT		 5878}
5879
5880static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5881{
5882 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5883 int err;
1da177e4
LT		 5884
5885 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5886 return -EINVAL;
5887
5888 if (!netif_running(dev)) {
5889 /* We'll just catch it later when the
5890 * device is up'd.
5891 */
5892 tg3_set_mtu(dev, tp, new_mtu);
5893 return 0;
5894 }
5895
b02fd9e3
MC		 5896 tg3_phy_stop(tp);
5897
1da177e4 5898 tg3_netif_stop(tp);
f47c11ee
DM		 5899
5900 tg3_full_lock(tp, 1);
1da177e4 5901
944d980e 5902 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5903
5904 tg3_set_mtu(dev, tp, new_mtu);
5905
b9ec6c1b 5906 err = tg3_restart_hw(tp, 0);
1da177e4 5907
b9ec6c1b
MC		 5908 if (!err)
5909 tg3_netif_start(tp);
1da177e4 5910
f47c11ee 5911 tg3_full_unlock(tp);
1da177e4 5912
b02fd9e3
MC		 5913 if (!err)
5914 tg3_phy_start(tp);
5915
b9ec6c1b 5916 return err;
1da177e4
LT		 5917}
5918
21f581a5
MC		 5919static void tg3_rx_prodring_free(struct tg3 *tp,
5920 struct tg3_rx_prodring_set *tpr)
1da177e4 5921{
1da177e4
LT		 5922 int i;
5923
b196c7e4
MC		 5924 if (tpr != &tp->prodring[0]) {
5925 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5926 i = (i + 1) % TG3_RX_RING_SIZE)
5927 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5928 tp->rx_pkt_map_sz);
5929
5930 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5931 for (i = tpr->rx_jmb_cons_idx;
5932 i != tpr->rx_jmb_prod_idx;
5933 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5934 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5935 TG3_RX_JMB_MAP_SZ);
5936 }
5937 }
5938
2b2cdb65 5939 return;
b196c7e4 5940 }
1da177e4 5941
2b2cdb65
MC		 5942 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5943 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5944 tp->rx_pkt_map_sz);
1da177e4 5945
cf7a7298 5946 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5947 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5948 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5949 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5950 }
5951}
5952
5953/* Initialize tx/rx rings for packet processing.
5954 *
5955 * The chip has been shut down and the driver detached from
5956 * the networking, so no interrupts or new tx packets will
5957 * end up in the driver. tp->{tx,}lock are held and thus
5958 * we may not sleep.
5959 */
21f581a5
MC		 5960static int tg3_rx_prodring_alloc(struct tg3 *tp,
5961 struct tg3_rx_prodring_set *tpr)
1da177e4 5962{
287be12e 5963 u32 i, rx_pkt_dma_sz;
1da177e4 5964
b196c7e4
MC		 5965 tpr->rx_std_cons_idx = 0;
5966 tpr->rx_std_prod_idx = 0;
5967 tpr->rx_jmb_cons_idx = 0;
5968 tpr->rx_jmb_prod_idx = 0;
5969
2b2cdb65
MC		 5970 if (tpr != &tp->prodring[0]) {
5971 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5972 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5973 memset(&tpr->rx_jmb_buffers[0], 0,
5974 TG3_RX_JMB_BUFF_RING_SIZE);
5975 goto done;
5976 }
5977
1da177e4 5978 /* Zero out all descriptors. */
21f581a5 5979 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5980
287be12e 5981 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5982 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5983 tp->dev->mtu > ETH_DATA_LEN)
5984 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5985 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5986
1da177e4
LT		 5987 /* Initialize invariants of the rings, we only set this
5988 * stuff once. This works because the card does not
5989 * write into the rx buffer posting rings.
5990 */
5991 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5992 struct tg3_rx_buffer_desc *rxd;
5993
21f581a5 5994 rxd = &tpr->rx_std[i];
287be12e 5995 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5996 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5997 rxd->opaque = (RXD_OPAQUE_RING_STD |
5998 (i << RXD_OPAQUE_INDEX_SHIFT));
5999 }
6000
1da177e4
LT		 6001 /* Now allocate fresh SKBs for each rx ring. */
6002 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6003 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6004 printk(KERN_WARNING PFX
6005 "%s: Using a smaller RX standard ring, "
6006 "only %d out of %d buffers were allocated "
6007 "successfully.\n",
6008 tp->dev->name, i, tp->rx_pending);
6009 if (i == 0)
cf7a7298 6010 goto initfail;
32d8c572 6011 tp->rx_pending = i;
1da177e4 6012 break;
32d8c572 6013 }
1da177e4
LT		 6014 }
6015
cf7a7298
MC		 6016 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6017 goto done;
6018
21f581a5 6019 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6020
0f893dc6 6021 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6022 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6023 struct tg3_rx_buffer_desc *rxd;
6024
79ed5ac7 6025 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6026 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6027 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6028 RXD_FLAG_JUMBO;
6029 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6030 (i << RXD_OPAQUE_INDEX_SHIFT));
6031 }
6032
1da177e4 6033 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6034 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6035 i) < 0) {
32d8c572
MC		 6036 printk(KERN_WARNING PFX
6037 "%s: Using a smaller RX jumbo ring, "
6038 "only %d out of %d buffers were "
6039 "allocated successfully.\n",
6040 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6041 if (i == 0)
6042 goto initfail;
32d8c572 6043 tp->rx_jumbo_pending = i;
1da177e4 6044 break;
32d8c572 6045 }
1da177e4
LT		 6046 }
6047 }
cf7a7298
MC		 6048
6049done:
32d8c572 6050 return 0;
cf7a7298
MC		 6051
6052initfail:
21f581a5 6053 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6054 return -ENOMEM;
1da177e4
LT		 6055}
6056
21f581a5
MC		 6057static void tg3_rx_prodring_fini(struct tg3 *tp,
6058 struct tg3_rx_prodring_set *tpr)
1da177e4 6059{
21f581a5
MC		 6060 kfree(tpr->rx_std_buffers);
6061 tpr->rx_std_buffers = NULL;
6062 kfree(tpr->rx_jmb_buffers);
6063 tpr->rx_jmb_buffers = NULL;
6064 if (tpr->rx_std) {
1da177e4 6065 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6066 tpr->rx_std, tpr->rx_std_mapping);
6067 tpr->rx_std = NULL;
1da177e4 6068 }
21f581a5 6069 if (tpr->rx_jmb) {
1da177e4 6070 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6071 tpr->rx_jmb, tpr->rx_jmb_mapping);
6072 tpr->rx_jmb = NULL;
1da177e4 6073 }
cf7a7298
MC		 6074}
6075
21f581a5
MC		 6076static int tg3_rx_prodring_init(struct tg3 *tp,
6077 struct tg3_rx_prodring_set *tpr)
cf7a7298 6078{
2b2cdb65 6079 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6080 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6081 return -ENOMEM;
6082
21f581a5
MC		 6083 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6084 &tpr->rx_std_mapping);
6085 if (!tpr->rx_std)
cf7a7298
MC		 6086 goto err_out;
6087
6088 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6089 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6090 GFP_KERNEL);
6091 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6092 goto err_out;
6093
21f581a5
MC		 6094 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6095 TG3_RX_JUMBO_RING_BYTES,
6096 &tpr->rx_jmb_mapping);
6097 if (!tpr->rx_jmb)
cf7a7298
MC		 6098 goto err_out;
6099 }
6100
6101 return 0;
6102
6103err_out:
21f581a5 6104 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6105 return -ENOMEM;
6106}
6107
6108/* Free up pending packets in all rx/tx rings.
6109 *
6110 * The chip has been shut down and the driver detached from
6111 * the networking, so no interrupts or new tx packets will
6112 * end up in the driver. tp->{tx,}lock is not held and we are not
6113 * in an interrupt context and thus may sleep.
6114 */
6115static void tg3_free_rings(struct tg3 *tp)
6116{
f77a6a8e 6117 int i, j;
cf7a7298 6118
f77a6a8e
MC		 6119 for (j = 0; j < tp->irq_cnt; j++) {
6120 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6121
0c1d0e2b
MC		 6122 if (!tnapi->tx_buffers)
6123 continue;
6124
f77a6a8e 6125 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6126 struct ring_info *txp;
f77a6a8e 6127 struct sk_buff *skb;
f4188d8a 6128 unsigned int k;
cf7a7298 6129
f77a6a8e
MC		 6130 txp = &tnapi->tx_buffers[i];
6131 skb = txp->skb;
cf7a7298 6132
f77a6a8e
MC		 6133 if (skb == NULL) {
6134 i++;
6135 continue;
6136 }
cf7a7298 6137
f4188d8a
AD		 6138 pci_unmap_single(tp->pdev,
6139 pci_unmap_addr(txp, mapping),
6140 skb_headlen(skb),
6141 PCI_DMA_TODEVICE);
f77a6a8e 6142 txp->skb = NULL;
cf7a7298 6143
f4188d8a
AD		 6144 i++;
6145
6146 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6147 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6148 pci_unmap_page(tp->pdev,
6149 pci_unmap_addr(txp, mapping),
6150 skb_shinfo(skb)->frags[k].size,
6151 PCI_DMA_TODEVICE);
6152 i++;
6153 }
f77a6a8e
MC		 6154
6155 dev_kfree_skb_any(skb);
6156 }
cf7a7298 6157
2b2cdb65
MC		 6158 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6159 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6160 }
cf7a7298
MC		 6161}
6162
6163/* Initialize tx/rx rings for packet processing.
6164 *
6165 * The chip has been shut down and the driver detached from
6166 * the networking, so no interrupts or new tx packets will
6167 * end up in the driver. tp->{tx,}lock are held and thus
6168 * we may not sleep.
6169 */
6170static int tg3_init_rings(struct tg3 *tp)
6171{
f77a6a8e 6172 int i;
72334482 6173
cf7a7298
MC		 6174 /* Free up all the SKBs. */
6175 tg3_free_rings(tp);
6176
f77a6a8e
MC		 6177 for (i = 0; i < tp->irq_cnt; i++) {
6178 struct tg3_napi *tnapi = &tp->napi[i];
6179
6180 tnapi->last_tag = 0;
6181 tnapi->last_irq_tag = 0;
6182 tnapi->hw_status->status = 0;
6183 tnapi->hw_status->status_tag = 0;
6184 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6185
f77a6a8e
MC		 6186 tnapi->tx_prod = 0;
6187 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6188 if (tnapi->tx_ring)
6189 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6190
6191 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6192 if (tnapi->rx_rcb)
6193 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 6194
6195 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6196 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6197 return -ENOMEM;
f77a6a8e 6198 }
72334482 6199
2b2cdb65 6200 return 0;
cf7a7298
MC		 6201}
6202
6203/*
6204 * Must not be invoked with interrupt sources disabled and
6205 * the hardware shutdown down.
6206 */
6207static void tg3_free_consistent(struct tg3 *tp)
6208{
f77a6a8e 6209 int i;
898a56f8 6210
f77a6a8e
MC		 6211 for (i = 0; i < tp->irq_cnt; i++) {
6212 struct tg3_napi *tnapi = &tp->napi[i];
6213
6214 if (tnapi->tx_ring) {
6215 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6216 tnapi->tx_ring, tnapi->tx_desc_mapping);
6217 tnapi->tx_ring = NULL;
6218 }
6219
6220 kfree(tnapi->tx_buffers);
6221 tnapi->tx_buffers = NULL;
6222
6223 if (tnapi->rx_rcb) {
6224 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6225 tnapi->rx_rcb,
6226 tnapi->rx_rcb_mapping);
6227 tnapi->rx_rcb = NULL;
6228 }
6229
6230 if (tnapi->hw_status) {
6231 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6232 tnapi->hw_status,
6233 tnapi->status_mapping);
6234 tnapi->hw_status = NULL;
6235 }
1da177e4 6236 }
f77a6a8e 6237
1da177e4
LT		 6238 if (tp->hw_stats) {
6239 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6240 tp->hw_stats, tp->stats_mapping);
6241 tp->hw_stats = NULL;
6242 }
f77a6a8e 6243
2b2cdb65
MC		 6244 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6245 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6246}
6247
6248/*
6249 * Must not be invoked with interrupt sources disabled and
6250 * the hardware shutdown down. Can sleep.
6251 */
6252static int tg3_alloc_consistent(struct tg3 *tp)
6253{
f77a6a8e 6254 int i;
898a56f8 6255
2b2cdb65
MC		 6256 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6257 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6258 goto err_out;
6259 }
1da177e4 6260
f77a6a8e
MC		 6261 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6262 sizeof(struct tg3_hw_stats),
6263 &tp->stats_mapping);
6264 if (!tp->hw_stats)
1da177e4
LT		 6265 goto err_out;
6266
f77a6a8e 6267 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6268
f77a6a8e
MC		 6269 for (i = 0; i < tp->irq_cnt; i++) {
6270 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6271 struct tg3_hw_status *sblk;
1da177e4 6272
f77a6a8e
MC		 6273 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6274 TG3_HW_STATUS_SIZE,
6275 &tnapi->status_mapping);
6276 if (!tnapi->hw_status)
6277 goto err_out;
898a56f8 6278
f77a6a8e 6279 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6280 sblk = tnapi->hw_status;
6281
19cfaecc
MC		 6282 /* If multivector TSS is enabled, vector 0 does not handle
6283 * tx interrupts. Don't allocate any resources for it.
6284 */
6285 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6286 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6287 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6288 TG3_TX_RING_SIZE,
6289 GFP_KERNEL);
6290 if (!tnapi->tx_buffers)
6291 goto err_out;
6292
6293 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6294 TG3_TX_RING_BYTES,
6295 &tnapi->tx_desc_mapping);
6296 if (!tnapi->tx_ring)
6297 goto err_out;
6298 }
6299
8d9d7cfc
MC		 6300 /*
6301 * When RSS is enabled, the status block format changes
6302 * slightly. The "rx_jumbo_consumer", "reserved",
6303 * and "rx_mini_consumer" members get mapped to the
6304 * other three rx return ring producer indexes.
6305 */
6306 switch (i) {
6307 default:
6308 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6309 break;
6310 case 2:
6311 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6312 break;
6313 case 3:
6314 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6315 break;
6316 case 4:
6317 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6318 break;
6319 }
72334482 6320
b196c7e4
MC		 6321 if (tp->irq_cnt == 1)
6322 tnapi->prodring = &tp->prodring[0];
6323 else if (i)
6324 tnapi->prodring = &tp->prodring[i - 1];
6325
0c1d0e2b
MC		 6326 /*
6327 * If multivector RSS is enabled, vector 0 does not handle
6328 * rx or tx interrupts. Don't allocate any resources for it.
6329 */
6330 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6331 continue;
6332
f77a6a8e
MC		 6333 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6334 TG3_RX_RCB_RING_BYTES(tp),
6335 &tnapi->rx_rcb_mapping);
6336 if (!tnapi->rx_rcb)
6337 goto err_out;
72334482 6338
f77a6a8e 6339 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6340 }
1da177e4
LT		 6341
6342 return 0;
6343
6344err_out:
6345 tg3_free_consistent(tp);
6346 return -ENOMEM;
6347}
6348
6349#define MAX_WAIT_CNT 1000
6350
6351/* To stop a block, clear the enable bit and poll till it
6352 * clears. tp->lock is held.
6353 */
b3b7d6be 6354static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6355{
6356 unsigned int i;
6357 u32 val;
6358
6359 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6360 switch (ofs) {
6361 case RCVLSC_MODE:
6362 case DMAC_MODE:
6363 case MBFREE_MODE:
6364 case BUFMGR_MODE:
6365 case MEMARB_MODE:
6366 /* We can't enable/disable these bits of the
6367 * 5705/5750, just say success.
6368 */
6369 return 0;
6370
6371 default:
6372 break;
855e1111 6373 }
1da177e4
LT		 6374 }
6375
6376 val = tr32(ofs);
6377 val &= ~enable_bit;
6378 tw32_f(ofs, val);
6379
6380 for (i = 0; i < MAX_WAIT_CNT; i++) {
6381 udelay(100);
6382 val = tr32(ofs);
6383 if ((val & enable_bit) == 0)
6384 break;
6385 }
6386
b3b7d6be 6387 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6388 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6389 "ofs=%lx enable_bit=%x\n",
6390 ofs, enable_bit);
6391 return -ENODEV;
6392 }
6393
6394 return 0;
6395}
6396
6397/* tp->lock is held. */
b3b7d6be 6398static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6399{
6400 int i, err;
6401
6402 tg3_disable_ints(tp);
6403
6404 tp->rx_mode &= ~RX_MODE_ENABLE;
6405 tw32_f(MAC_RX_MODE, tp->rx_mode);
6406 udelay(10);
6407
b3b7d6be
DM		 6408 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6409 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6410 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6411 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6412 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6413 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6414
6415 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6416 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6417 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6418 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6419 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6420 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6421 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6422
6423 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6424 tw32_f(MAC_MODE, tp->mac_mode);
6425 udelay(40);
6426
6427 tp->tx_mode &= ~TX_MODE_ENABLE;
6428 tw32_f(MAC_TX_MODE, tp->tx_mode);
6429
6430 for (i = 0; i < MAX_WAIT_CNT; i++) {
6431 udelay(100);
6432 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6433 break;
6434 }
6435 if (i >= MAX_WAIT_CNT) {
6436 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6437 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6438 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6439 err |= -ENODEV;
1da177e4
LT		 6440 }
6441
e6de8ad1 6442 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6443 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6444 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6445
6446 tw32(FTQ_RESET, 0xffffffff);
6447 tw32(FTQ_RESET, 0x00000000);
6448
b3b7d6be
DM		 6449 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6450 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6451
f77a6a8e
MC		 6452 for (i = 0; i < tp->irq_cnt; i++) {
6453 struct tg3_napi *tnapi = &tp->napi[i];
6454 if (tnapi->hw_status)
6455 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6456 }
1da177e4
LT		 6457 if (tp->hw_stats)
6458 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6459
1da177e4
LT		 6460 return err;
6461}
6462
0d3031d9
MC		 6463static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6464{
6465 int i;
6466 u32 apedata;
6467
6468 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6469 if (apedata != APE_SEG_SIG_MAGIC)
6470 return;
6471
6472 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6473 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6474 return;
6475
6476 /* Wait for up to 1 millisecond for APE to service previous event. */
6477 for (i = 0; i < 10; i++) {
6478 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6479 return;
6480
6481 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6482
6483 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6484 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6485 event | APE_EVENT_STATUS_EVENT_PENDING);
6486
6487 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6488
6489 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6490 break;
6491
6492 udelay(100);
6493 }
6494
6495 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6496 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6497}
6498
6499static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6500{
6501 u32 event;
6502 u32 apedata;
6503
6504 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6505 return;
6506
6507 switch (kind) {
6508 case RESET_KIND_INIT:
6509 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6510 APE_HOST_SEG_SIG_MAGIC);
6511 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6512 APE_HOST_SEG_LEN_MAGIC);
6513 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6514 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6515 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6516 APE_HOST_DRIVER_ID_MAGIC);
6517 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6518 APE_HOST_BEHAV_NO_PHYLOCK);
6519
6520 event = APE_EVENT_STATUS_STATE_START;
6521 break;
6522 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6523 /* With the interface we are currently using,
6524 * APE does not track driver state. Wiping
6525 * out the HOST SEGMENT SIGNATURE forces
6526 * the APE to assume OS absent status.
6527 */
6528 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6529
0d3031d9
MC		 6530 event = APE_EVENT_STATUS_STATE_UNLOAD;
6531 break;
6532 case RESET_KIND_SUSPEND:
6533 event = APE_EVENT_STATUS_STATE_SUSPEND;
6534 break;
6535 default:
6536 return;
6537 }
6538
6539 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6540
6541 tg3_ape_send_event(tp, event);
6542}
6543
1da177e4
LT		 6544/* tp->lock is held. */
6545static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6546{
f49639e6
DM		 6547 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6548 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6549
6550 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6551 switch (kind) {
6552 case RESET_KIND_INIT:
6553 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6554 DRV_STATE_START);
6555 break;
6556
6557 case RESET_KIND_SHUTDOWN:
6558 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6559 DRV_STATE_UNLOAD);
6560 break;
6561
6562 case RESET_KIND_SUSPEND:
6563 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6564 DRV_STATE_SUSPEND);
6565 break;
6566
6567 default:
6568 break;
855e1111 6569 }
1da177e4 6570 }
0d3031d9
MC		 6571
6572 if (kind == RESET_KIND_INIT ||
6573 kind == RESET_KIND_SUSPEND)
6574 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6575}
6576
6577/* tp->lock is held. */
6578static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6579{
6580 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6581 switch (kind) {
6582 case RESET_KIND_INIT:
6583 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6584 DRV_STATE_START_DONE);
6585 break;
6586
6587 case RESET_KIND_SHUTDOWN:
6588 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6589 DRV_STATE_UNLOAD_DONE);
6590 break;
6591
6592 default:
6593 break;
855e1111 6594 }
1da177e4 6595 }
0d3031d9
MC		 6596
6597 if (kind == RESET_KIND_SHUTDOWN)
6598 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6599}
6600
6601/* tp->lock is held. */
6602static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6603{
6604 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6605 switch (kind) {
6606 case RESET_KIND_INIT:
6607 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6608 DRV_STATE_START);
6609 break;
6610
6611 case RESET_KIND_SHUTDOWN:
6612 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6613 DRV_STATE_UNLOAD);
6614 break;
6615
6616 case RESET_KIND_SUSPEND:
6617 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6618 DRV_STATE_SUSPEND);
6619 break;
6620
6621 default:
6622 break;
855e1111 6623 }
1da177e4
LT		 6624 }
6625}
6626
7a6f4369
MC		 6627static int tg3_poll_fw(struct tg3 *tp)
6628{
6629 int i;
6630 u32 val;
6631
b5d3772c 6632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6633 /* Wait up to 20ms for init done. */
6634 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6635 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6636 return 0;
0ccead18 6637 udelay(100);
b5d3772c
MC		 6638 }
6639 return -ENODEV;
6640 }
6641
7a6f4369
MC		 6642 /* Wait for firmware initialization to complete. */
6643 for (i = 0; i < 100000; i++) {
6644 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6645 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6646 break;
6647 udelay(10);
6648 }
6649
6650 /* Chip might not be fitted with firmware. Some Sun onboard
6651 * parts are configured like that. So don't signal the timeout
6652 * of the above loop as an error, but do report the lack of
6653 * running firmware once.
6654 */
6655 if (i >= 100000 &&
6656 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6657 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6658
6659 printk(KERN_INFO PFX "%s: No firmware running.\n",
6660 tp->dev->name);
6661 }
6662
6663 return 0;
6664}
6665
ee6a99b5
MC		 6666/* Save PCI command register before chip reset */
6667static void tg3_save_pci_state(struct tg3 *tp)
6668{
8a6eac90 6669 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6670}
6671
6672/* Restore PCI state after chip reset */
6673static void tg3_restore_pci_state(struct tg3 *tp)
6674{
6675 u32 val;
6676
6677 /* Re-enable indirect register accesses. */
6678 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6679 tp->misc_host_ctrl);
6680
6681 /* Set MAX PCI retry to zero. */
6682 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6683 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6684 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6685 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6686 /* Allow reads and writes to the APE register and memory space. */
6687 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6688 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6689 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6690 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6691
8a6eac90 6692 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6693
fcb389df
MC		 6694 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6695 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6696 pcie_set_readrq(tp->pdev, 4096);
6697 else {
6698 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6699 tp->pci_cacheline_sz);
6700 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6701 tp->pci_lat_timer);
6702 }
114342f2 6703 }
5f5c51e3 6704
ee6a99b5 6705 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6706 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6707 u16 pcix_cmd;
6708
6709 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6710 &pcix_cmd);
6711 pcix_cmd &= ~PCI_X_CMD_ERO;
6712 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6713 pcix_cmd);
6714 }
ee6a99b5
MC		 6715
6716 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6717
6718 /* Chip reset on 5780 will reset MSI enable bit,
6719 * so need to restore it.
6720 */
6721 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6722 u16 ctrl;
6723
6724 pci_read_config_word(tp->pdev,
6725 tp->msi_cap + PCI_MSI_FLAGS,
6726 &ctrl);
6727 pci_write_config_word(tp->pdev,
6728 tp->msi_cap + PCI_MSI_FLAGS,
6729 ctrl | PCI_MSI_FLAGS_ENABLE);
6730 val = tr32(MSGINT_MODE);
6731 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6732 }
6733 }
6734}
6735
1da177e4
LT		 6736static void tg3_stop_fw(struct tg3 *);
6737
6738/* tp->lock is held. */
6739static int tg3_chip_reset(struct tg3 *tp)
6740{
6741 u32 val;
1ee582d8 6742 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6743 int i, err;
1da177e4 6744
f49639e6
DM		 6745 tg3_nvram_lock(tp);
6746
77b483f1
MC		 6747 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6748
f49639e6
DM		 6749 /* No matching tg3_nvram_unlock() after this because
6750 * chip reset below will undo the nvram lock.
6751 */
6752 tp->nvram_lock_cnt = 0;
1da177e4 6753
ee6a99b5
MC		 6754 /* GRC_MISC_CFG core clock reset will clear the memory
6755 * enable bit in PCI register 4 and the MSI enable bit
6756 * on some chips, so we save relevant registers here.
6757 */
6758 tg3_save_pci_state(tp);
6759
d9ab5ad1 6760 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6761 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6762 tw32(GRC_FASTBOOT_PC, 0);
6763
1da177e4
LT		 6764 /*
6765 * We must avoid the readl() that normally takes place.
6766 * It locks machines, causes machine checks, and other
6767 * fun things. So, temporarily disable the 5701
6768 * hardware workaround, while we do the reset.
6769 */
1ee582d8
MC		 6770 write_op = tp->write32;
6771 if (write_op == tg3_write_flush_reg32)
6772 tp->write32 = tg3_write32;
1da177e4 6773
d18edcb2
MC		 6774 /* Prevent the irq handler from reading or writing PCI registers
6775 * during chip reset when the memory enable bit in the PCI command
6776 * register may be cleared. The chip does not generate interrupt
6777 * at this time, but the irq handler may still be called due to irq
6778 * sharing or irqpoll.
6779 */
6780 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6781 for (i = 0; i < tp->irq_cnt; i++) {
6782 struct tg3_napi *tnapi = &tp->napi[i];
6783 if (tnapi->hw_status) {
6784 tnapi->hw_status->status = 0;
6785 tnapi->hw_status->status_tag = 0;
6786 }
6787 tnapi->last_tag = 0;
6788 tnapi->last_irq_tag = 0;
b8fa2f3a 6789 }
d18edcb2 6790 smp_mb();
4f125f42
MC		 6791
6792 for (i = 0; i < tp->irq_cnt; i++)
6793 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6794
255ca311
MC		 6795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6796 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6797 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6798 }
6799
1da177e4
LT		 6800 /* do the reset */
6801 val = GRC_MISC_CFG_CORECLK_RESET;
6802
6803 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6804 if (tr32(0x7e2c) == 0x60) {
6805 tw32(0x7e2c, 0x20);
6806 }
6807 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6808 tw32(GRC_MISC_CFG, (1 << 29));
6809 val |= (1 << 29);
6810 }
6811 }
6812
b5d3772c
MC		 6813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6814 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6815 tw32(GRC_VCPU_EXT_CTRL,
6816 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6817 }
6818
1da177e4
LT		 6819 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6820 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6821 tw32(GRC_MISC_CFG, val);
6822
1ee582d8
MC		 6823 /* restore 5701 hardware bug workaround write method */
6824 tp->write32 = write_op;
1da177e4
LT		 6825
6826 /* Unfortunately, we have to delay before the PCI read back.
6827 * Some 575X chips even will not respond to a PCI cfg access
6828 * when the reset command is given to the chip.
6829 *
6830 * How do these hardware designers expect things to work
6831 * properly if the PCI write is posted for a long period
6832 * of time? It is always necessary to have some method by
6833 * which a register read back can occur to push the write
6834 * out which does the reset.
6835 *
6836 * For most tg3 variants the trick below was working.
6837 * Ho hum...
6838 */
6839 udelay(120);
6840
6841 /* Flush PCI posted writes. The normal MMIO registers
6842 * are inaccessible at this time so this is the only
6843 * way to make this reliably (actually, this is no longer
6844 * the case, see above). I tried to use indirect
6845 * register read/write but this upset some 5701 variants.
6846 */
6847 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6848
6849 udelay(120);
6850
5e7dfd0f 6851 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6852 u16 val16;
6853
1da177e4
LT		 6854 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6855 int i;
6856 u32 cfg_val;
6857
6858 /* Wait for link training to complete. */
6859 for (i = 0; i < 5000; i++)
6860 udelay(100);
6861
6862 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6863 pci_write_config_dword(tp->pdev, 0xc4,
6864 cfg_val | (1 << 15));
6865 }
5e7dfd0f 6866
e7126997
MC		 6867 /* Clear the "no snoop" and "relaxed ordering" bits. */
6868 pci_read_config_word(tp->pdev,
6869 tp->pcie_cap + PCI_EXP_DEVCTL,
6870 &val16);
6871 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6872 PCI_EXP_DEVCTL_NOSNOOP_EN);
6873 /*
6874 * Older PCIe devices only support the 128 byte
6875 * MPS setting. Enforce the restriction.
5e7dfd0f 6876 */
e7126997
MC		 6877 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6878 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6879 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6880 pci_write_config_word(tp->pdev,
6881 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6882 val16);
5e7dfd0f
MC		 6883
6884 pcie_set_readrq(tp->pdev, 4096);
6885
6886 /* Clear error status */
6887 pci_write_config_word(tp->pdev,
6888 tp->pcie_cap + PCI_EXP_DEVSTA,
6889 PCI_EXP_DEVSTA_CED |
6890 PCI_EXP_DEVSTA_NFED |
6891 PCI_EXP_DEVSTA_FED |
6892 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6893 }
6894
ee6a99b5 6895 tg3_restore_pci_state(tp);
1da177e4 6896
d18edcb2
MC		 6897 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6898
ee6a99b5
MC		 6899 val = 0;
6900 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6901 val = tr32(MEMARB_MODE);
ee6a99b5 6902 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6903
6904 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6905 tg3_stop_fw(tp);
6906 tw32(0x5000, 0x400);
6907 }
6908
6909 tw32(GRC_MODE, tp->grc_mode);
6910
6911 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6912 val = tr32(0xc4);
1da177e4
LT		 6913
6914 tw32(0xc4, val | (1 << 15));
6915 }
6916
6917 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6918 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6919 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6920 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6921 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6922 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6923 }
6924
6925 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6926 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6927 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6928 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6929 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6930 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6931 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6932 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6933 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6934 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6935 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6936 } else
6937 tw32_f(MAC_MODE, 0);
6938 udelay(40);
6939
77b483f1
MC		 6940 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6941
7a6f4369
MC		 6942 err = tg3_poll_fw(tp);
6943 if (err)
6944 return err;
1da177e4 6945
0a9140cf
MC		 6946 tg3_mdio_start(tp);
6947
52cdf852
MC		 6948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6949 u8 phy_addr;
6950
6951 phy_addr = tp->phy_addr;
6952 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6953
6954 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6955 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6956 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6957 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6958 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6959 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6960 udelay(10);
6961
6962 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6963 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6964 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6965 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6966 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6967 udelay(10);
6968
6969 tp->phy_addr = phy_addr;
6970 }
6971
1da177e4 6972 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6973 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6974 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 6975 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6976 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 6977 val = tr32(0x7c00);
1da177e4
LT		 6978
6979 tw32(0x7c00, val | (1 << 25));
6980 }
6981
6982 /* Reprobe ASF enable state. */
6983 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6984 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6985 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6986 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6987 u32 nic_cfg;
6988
6989 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6990 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6991 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6992 tp->last_event_jiffies = jiffies;
cbf46853 6993 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6994 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6995 }
6996 }
6997
6998 return 0;
6999}
7000
7001/* tp->lock is held. */
7002static void tg3_stop_fw(struct tg3 *tp)
7003{
0d3031d9
MC		 7004 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7005 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7006 /* Wait for RX cpu to ACK the previous event. */
7007 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7008
7009 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7010
7011 tg3_generate_fw_event(tp);
1da177e4 7012
7c5026aa
MC		 7013 /* Wait for RX cpu to ACK this event. */
7014 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7015 }
7016}
7017
7018/* tp->lock is held. */
944d980e 7019static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7020{
7021 int err;
7022
7023 tg3_stop_fw(tp);
7024
944d980e 7025 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7026
b3b7d6be 7027 tg3_abort_hw(tp, silent);
1da177e4
LT		 7028 err = tg3_chip_reset(tp);
7029
daba2a63
MC		 7030 __tg3_set_mac_addr(tp, 0);
7031
944d980e
MC		 7032 tg3_write_sig_legacy(tp, kind);
7033 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7034
7035 if (err)
7036 return err;
7037
7038 return 0;
7039}
7040
1da177e4
LT		 7041#define RX_CPU_SCRATCH_BASE 0x30000
7042#define RX_CPU_SCRATCH_SIZE 0x04000
7043#define TX_CPU_SCRATCH_BASE 0x34000
7044#define TX_CPU_SCRATCH_SIZE 0x04000
7045
7046/* tp->lock is held. */
7047static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7048{
7049 int i;
7050
5d9428de
ES		 7051 BUG_ON(offset == TX_CPU_BASE &&
7052 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7053
b5d3772c
MC		 7054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7055 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7056
7057 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7058 return 0;
7059 }
1da177e4
LT		 7060 if (offset == RX_CPU_BASE) {
7061 for (i = 0; i < 10000; i++) {
7062 tw32(offset + CPU_STATE, 0xffffffff);
7063 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7064 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7065 break;
7066 }
7067
7068 tw32(offset + CPU_STATE, 0xffffffff);
7069 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7070 udelay(10);
7071 } else {
7072 for (i = 0; i < 10000; i++) {
7073 tw32(offset + CPU_STATE, 0xffffffff);
7074 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7075 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7076 break;
7077 }
7078 }
7079
7080 if (i >= 10000) {
7081 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7082 "and %s CPU\n",
7083 tp->dev->name,
7084 (offset == RX_CPU_BASE ? "RX" : "TX"));
7085 return -ENODEV;
7086 }
ec41c7df
MC		 7087
7088 /* Clear firmware's nvram arbitration. */
7089 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7090 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7091 return 0;
7092}
7093
7094struct fw_info {
077f849d
JSR		 7095 unsigned int fw_base;
7096 unsigned int fw_len;
7097 const __be32 *fw_data;
1da177e4
LT		 7098};
7099
7100/* tp->lock is held. */
7101static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7102 int cpu_scratch_size, struct fw_info *info)
7103{
ec41c7df 7104 int err, lock_err, i;
1da177e4
LT		 7105 void (*write_op)(struct tg3 *, u32, u32);
7106
7107 if (cpu_base == TX_CPU_BASE &&
7108 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7109 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7110 "TX cpu firmware on %s which is 5705.\n",
7111 tp->dev->name);
7112 return -EINVAL;
7113 }
7114
7115 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7116 write_op = tg3_write_mem;
7117 else
7118 write_op = tg3_write_indirect_reg32;
7119
1b628151
MC		 7120 /* It is possible that bootcode is still loading at this point.
7121 * Get the nvram lock first before halting the cpu.
7122 */
ec41c7df 7123 lock_err = tg3_nvram_lock(tp);
1da177e4 7124 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7125 if (!lock_err)
7126 tg3_nvram_unlock(tp);
1da177e4
LT		 7127 if (err)
7128 goto out;
7129
7130 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7131 write_op(tp, cpu_scratch_base + i, 0);
7132 tw32(cpu_base + CPU_STATE, 0xffffffff);
7133 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7134 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7135 write_op(tp, (cpu_scratch_base +
077f849d 7136 (info->fw_base & 0xffff) +
1da177e4 7137 (i * sizeof(u32))),
077f849d 7138 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7139
7140 err = 0;
7141
7142out:
1da177e4
LT		 7143 return err;
7144}
7145
7146/* tp->lock is held. */
7147static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7148{
7149 struct fw_info info;
077f849d 7150 const __be32 *fw_data;
1da177e4
LT		 7151 int err, i;
7152
077f849d
JSR		 7153 fw_data = (void *)tp->fw->data;
7154
7155 /* Firmware blob starts with version numbers, followed by
7156 start address and length. We are setting complete length.
7157 length = end_address_of_bss - start_address_of_text.
7158 Remainder is the blob to be loaded contiguously
7159 from start address. */
7160
7161 info.fw_base = be32_to_cpu(fw_data[1]);
7162 info.fw_len = tp->fw->size - 12;
7163 info.fw_data = &fw_data[3];
1da177e4
LT		 7164
7165 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7166 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7167 &info);
7168 if (err)
7169 return err;
7170
7171 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7172 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7173 &info);
7174 if (err)
7175 return err;
7176
7177 /* Now startup only the RX cpu. */
7178 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7179 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7180
7181 for (i = 0; i < 5; i++) {
077f849d 7182 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7183 break;
7184 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7185 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7186 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7187 udelay(1000);
7188 }
7189 if (i >= 5) {
7190 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7191 "to set RX CPU PC, is %08x should be %08x\n",
7192 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7193 info.fw_base);
1da177e4
LT		 7194 return -ENODEV;
7195 }
7196 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7197 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7198
7199 return 0;
7200}
7201
1da177e4 7202/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7203
7204/* tp->lock is held. */
7205static int tg3_load_tso_firmware(struct tg3 *tp)
7206{
7207 struct fw_info info;
077f849d 7208 const __be32 *fw_data;
1da177e4
LT		 7209 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7210 int err, i;
7211
7212 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7213 return 0;
7214
077f849d
JSR		 7215 fw_data = (void *)tp->fw->data;
7216
7217 /* Firmware blob starts with version numbers, followed by
7218 start address and length. We are setting complete length.
7219 length = end_address_of_bss - start_address_of_text.
7220 Remainder is the blob to be loaded contiguously
7221 from start address. */
7222
7223 info.fw_base = be32_to_cpu(fw_data[1]);
7224 cpu_scratch_size = tp->fw_len;
7225 info.fw_len = tp->fw->size - 12;
7226 info.fw_data = &fw_data[3];
7227
1da177e4 7228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7229 cpu_base = RX_CPU_BASE;
7230 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7231 } else {
1da177e4
LT		 7232 cpu_base = TX_CPU_BASE;
7233 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7234 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7235 }
7236
7237 err = tg3_load_firmware_cpu(tp, cpu_base,
7238 cpu_scratch_base, cpu_scratch_size,
7239 &info);
7240 if (err)
7241 return err;
7242
7243 /* Now startup the cpu. */
7244 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7245 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7246
7247 for (i = 0; i < 5; i++) {
077f849d 7248 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7249 break;
7250 tw32(cpu_base + CPU_STATE, 0xffffffff);
7251 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7252 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7253 udelay(1000);
7254 }
7255 if (i >= 5) {
7256 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7257 "to set CPU PC, is %08x should be %08x\n",
7258 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7259 info.fw_base);
1da177e4
LT		 7260 return -ENODEV;
7261 }
7262 tw32(cpu_base + CPU_STATE, 0xffffffff);
7263 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7264 return 0;
7265}
7266
1da177e4 7267
1da177e4
LT		 7268static int tg3_set_mac_addr(struct net_device *dev, void *p)
7269{
7270 struct tg3 *tp = netdev_priv(dev);
7271 struct sockaddr *addr = p;
986e0aeb 7272 int err = 0, skip_mac_1 = 0;
1da177e4 7273
f9804ddb
MC		 7274 if (!is_valid_ether_addr(addr->sa_data))
7275 return -EINVAL;
7276
1da177e4
LT		 7277 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7278
e75f7c90
MC		 7279 if (!netif_running(dev))
7280 return 0;
7281
58712ef9 7282 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7283 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7284
986e0aeb
MC		 7285 addr0_high = tr32(MAC_ADDR_0_HIGH);
7286 addr0_low = tr32(MAC_ADDR_0_LOW);
7287 addr1_high = tr32(MAC_ADDR_1_HIGH);
7288 addr1_low = tr32(MAC_ADDR_1_LOW);
7289
7290 /* Skip MAC addr 1 if ASF is using it. */
7291 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7292 !(addr1_high == 0 && addr1_low == 0))
7293 skip_mac_1 = 1;
58712ef9 7294 }
986e0aeb
MC		 7295 spin_lock_bh(&tp->lock);
7296 __tg3_set_mac_addr(tp, skip_mac_1);
7297 spin_unlock_bh(&tp->lock);
1da177e4 7298
b9ec6c1b 7299 return err;
1da177e4
LT		 7300}
7301
7302/* tp->lock is held. */
7303static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7304 dma_addr_t mapping, u32 maxlen_flags,
7305 u32 nic_addr)
7306{
7307 tg3_write_mem(tp,
7308 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7309 ((u64) mapping >> 32));
7310 tg3_write_mem(tp,
7311 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7312 ((u64) mapping & 0xffffffff));
7313 tg3_write_mem(tp,
7314 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7315 maxlen_flags);
7316
7317 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7318 tg3_write_mem(tp,
7319 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7320 nic_addr);
7321}
7322
7323static void __tg3_set_rx_mode(struct net_device *);
d244c892 7324static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7325{
b6080e12
MC		 7326 int i;
7327
19cfaecc 7328 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7329 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7330 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7331 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7332 } else {
7333 tw32(HOSTCC_TXCOL_TICKS, 0);
7334 tw32(HOSTCC_TXMAX_FRAMES, 0);
7335 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7336 }
b6080e12 7337
19cfaecc
MC		 7338 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7339 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7340 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7341 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7342 } else {
b6080e12
MC		 7343 tw32(HOSTCC_RXCOL_TICKS, 0);
7344 tw32(HOSTCC_RXMAX_FRAMES, 0);
7345 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7346 }
b6080e12 7347
15f9850d
DM		 7348 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7349 u32 val = ec->stats_block_coalesce_usecs;
7350
b6080e12
MC		 7351 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7352 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7353
15f9850d
DM		 7354 if (!netif_carrier_ok(tp->dev))
7355 val = 0;
7356
7357 tw32(HOSTCC_STAT_COAL_TICKS, val);
7358 }
b6080e12
MC		 7359
7360 for (i = 0; i < tp->irq_cnt - 1; i++) {
7361 u32 reg;
7362
7363 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7364 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7365 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7366 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7367 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7368 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7369
7370 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7371 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7372 tw32(reg, ec->tx_coalesce_usecs);
7373 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7374 tw32(reg, ec->tx_max_coalesced_frames);
7375 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7376 tw32(reg, ec->tx_max_coalesced_frames_irq);
7377 }
b6080e12
MC		 7378 }
7379
7380 for (; i < tp->irq_max - 1; i++) {
7381 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7382 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7383 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7384
7385 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7386 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7387 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7388 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7389 }
b6080e12 7390 }
15f9850d 7391}
1da177e4 7392
2d31ecaf
MC		 7393/* tp->lock is held. */
7394static void tg3_rings_reset(struct tg3 *tp)
7395{
7396 int i;
f77a6a8e 7397 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7398 struct tg3_napi *tnapi = &tp->napi[0];
7399
7400 /* Disable all transmit rings but the first. */
7401 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7402 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7403 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7404 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7405 else
7406 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7407
7408 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7409 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7410 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7411 BDINFO_FLAGS_DISABLED);
7412
7413
7414 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7416 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7417 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7418 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7419 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7420 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7421 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7422 else
7423 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7424
7425 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7426 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7427 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7428 BDINFO_FLAGS_DISABLED);
7429
7430 /* Disable interrupts */
7431 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7432
7433 /* Zero mailbox registers. */
f77a6a8e
MC		 7434 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7435 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7436 tp->napi[i].tx_prod = 0;
7437 tp->napi[i].tx_cons = 0;
7438 tw32_mailbox(tp->napi[i].prodmbox, 0);
7439 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7440 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7441 }
7442 } else {
7443 tp->napi[0].tx_prod = 0;
7444 tp->napi[0].tx_cons = 0;
7445 tw32_mailbox(tp->napi[0].prodmbox, 0);
7446 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7447 }
2d31ecaf
MC		 7448
7449 /* Make sure the NIC-based send BD rings are disabled. */
7450 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7451 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7452 for (i = 0; i < 16; i++)
7453 tw32_tx_mbox(mbox + i * 8, 0);
7454 }
7455
7456 txrcb = NIC_SRAM_SEND_RCB;
7457 rxrcb = NIC_SRAM_RCV_RET_RCB;
7458
7459 /* Clear status block in ram. */
7460 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7461
7462 /* Set status block DMA address */
7463 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7464 ((u64) tnapi->status_mapping >> 32));
7465 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7466 ((u64) tnapi->status_mapping & 0xffffffff));
7467
f77a6a8e
MC		 7468 if (tnapi->tx_ring) {
7469 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7470 (TG3_TX_RING_SIZE <<
7471 BDINFO_FLAGS_MAXLEN_SHIFT),
7472 NIC_SRAM_TX_BUFFER_DESC);
7473 txrcb += TG3_BDINFO_SIZE;
7474 }
7475
7476 if (tnapi->rx_rcb) {
7477 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7478 (TG3_RX_RCB_RING_SIZE(tp) <<
7479 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7480 rxrcb += TG3_BDINFO_SIZE;
7481 }
7482
7483 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7484
f77a6a8e
MC		 7485 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7486 u64 mapping = (u64)tnapi->status_mapping;
7487 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7488 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7489
7490 /* Clear status block in ram. */
7491 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7492
19cfaecc
MC		 7493 if (tnapi->tx_ring) {
7494 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7495 (TG3_TX_RING_SIZE <<
7496 BDINFO_FLAGS_MAXLEN_SHIFT),
7497 NIC_SRAM_TX_BUFFER_DESC);
7498 txrcb += TG3_BDINFO_SIZE;
7499 }
f77a6a8e
MC		 7500
7501 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7502 (TG3_RX_RCB_RING_SIZE(tp) <<
7503 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7504
7505 stblk += 8;
f77a6a8e
MC		 7506 rxrcb += TG3_BDINFO_SIZE;
7507 }
2d31ecaf
MC		 7508}
7509
1da177e4 7510/* tp->lock is held. */
8e7a22e3 7511static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7512{
7513 u32 val, rdmac_mode;
7514 int i, err, limit;
21f581a5 7515 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7516
7517 tg3_disable_ints(tp);
7518
7519 tg3_stop_fw(tp);
7520
7521 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7522
7523 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7524 tg3_abort_hw(tp, 1);
1da177e4
LT		 7525 }
7526
dd477003
MC		 7527 if (reset_phy &&
7528 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7529 tg3_phy_reset(tp);
7530
1da177e4
LT		 7531 err = tg3_chip_reset(tp);
7532 if (err)
7533 return err;
7534
7535 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7536
bcb37f6c 7537 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7538 val = tr32(TG3_CPMU_CTRL);
7539 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7540 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7541
7542 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7543 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7544 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7545 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7546
7547 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7548 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7549 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7550 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7551
7552 val = tr32(TG3_CPMU_HST_ACC);
7553 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7554 val |= CPMU_HST_ACC_MACCLK_6_25;
7555 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7556 }
7557
33466d93
MC		 7558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7559 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7560 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7561 PCIE_PWR_MGMT_L1_THRESH_4MS;
7562 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7563
7564 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7565 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7566
7567 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7568
f40386c8
MC		 7569 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7570 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7571 }
7572
1da177e4
LT		 7573 /* This works around an issue with Athlon chipsets on
7574 * B3 tigon3 silicon. This bit has no effect on any
7575 * other revision. But do not set this on PCI Express
795d01c5 7576 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7577 */
795d01c5
MC		 7578 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7579 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7580 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7581 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7582 }
1da177e4
LT		 7583
7584 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7585 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7586 val = tr32(TG3PCI_PCISTATE);
7587 val |= PCISTATE_RETRY_SAME_DMA;
7588 tw32(TG3PCI_PCISTATE, val);
7589 }
7590
0d3031d9
MC		 7591 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7592 /* Allow reads and writes to the
7593 * APE register and memory space.
7594 */
7595 val = tr32(TG3PCI_PCISTATE);
7596 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7597 PCISTATE_ALLOW_APE_SHMEM_WR;
7598 tw32(TG3PCI_PCISTATE, val);
7599 }
7600
1da177e4
LT		 7601 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7602 /* Enable some hw fixes. */
7603 val = tr32(TG3PCI_MSI_DATA);
7604 val |= (1 << 26) | (1 << 28) | (1 << 29);
7605 tw32(TG3PCI_MSI_DATA, val);
7606 }
7607
7608 /* Descriptor ring init may make accesses to the
7609 * NIC SRAM area to setup the TX descriptors, so we
7610 * can only do this after the hardware has been
7611 * successfully reset.
7612 */
32d8c572
MC		 7613 err = tg3_init_rings(tp);
7614 if (err)
7615 return err;
1da177e4 7616
b703df6f
MC		 7617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7619 val = tr32(TG3PCI_DMA_RW_CTRL) &
7620 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7621 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7622 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7623 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7624 /* This value is determined during the probe time DMA
7625 * engine test, tg3_test_dma.
7626 */
7627 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7628 }
1da177e4
LT		 7629
7630 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7631 GRC_MODE_4X_NIC_SEND_RINGS |
7632 GRC_MODE_NO_TX_PHDR_CSUM |
7633 GRC_MODE_NO_RX_PHDR_CSUM);
7634 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7635
7636 /* Pseudo-header checksum is done by hardware logic and not
7637 * the offload processers, so make the chip do the pseudo-
7638 * header checksums on receive. For transmit it is more
7639 * convenient to do the pseudo-header checksum in software
7640 * as Linux does that on transmit for us in all cases.
7641 */
7642 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7643
7644 tw32(GRC_MODE,
7645 tp->grc_mode |
7646 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7647
7648 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7649 val = tr32(GRC_MISC_CFG);
7650 val &= ~0xff;
7651 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7652 tw32(GRC_MISC_CFG, val);
7653
7654 /* Initialize MBUF/DESC pool. */
cbf46853 7655 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7656 /* Do nothing. */
7657 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7658 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7659 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7660 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7661 else
7662 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7663 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7664 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7665 }
1da177e4
LT		 7666 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7667 int fw_len;
7668
077f849d 7669 fw_len = tp->fw_len;
1da177e4
LT		 7670 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7671 tw32(BUFMGR_MB_POOL_ADDR,
7672 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7673 tw32(BUFMGR_MB_POOL_SIZE,
7674 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7675 }
1da177e4 7676
0f893dc6 7677 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7678 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7679 tp->bufmgr_config.mbuf_read_dma_low_water);
7680 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7681 tp->bufmgr_config.mbuf_mac_rx_low_water);
7682 tw32(BUFMGR_MB_HIGH_WATER,
7683 tp->bufmgr_config.mbuf_high_water);
7684 } else {
7685 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7686 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7687 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7688 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7689 tw32(BUFMGR_MB_HIGH_WATER,
7690 tp->bufmgr_config.mbuf_high_water_jumbo);
7691 }
7692 tw32(BUFMGR_DMA_LOW_WATER,
7693 tp->bufmgr_config.dma_low_water);
7694 tw32(BUFMGR_DMA_HIGH_WATER,
7695 tp->bufmgr_config.dma_high_water);
7696
7697 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7698 for (i = 0; i < 2000; i++) {
7699 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7700 break;
7701 udelay(10);
7702 }
7703 if (i >= 2000) {
7704 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7705 tp->dev->name);
7706 return -ENODEV;
7707 }
7708
7709 /* Setup replenish threshold. */
f92905de
MC		 7710 val = tp->rx_pending / 8;
7711 if (val == 0)
7712 val = 1;
7713 else if (val > tp->rx_std_max_post)
7714 val = tp->rx_std_max_post;
b5d3772c
MC		 7715 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7716 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7717 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7718
7719 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7720 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7721 }
f92905de
MC		 7722
7723 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7724
7725 /* Initialize TG3_BDINFO's at:
7726 * RCVDBDI_STD_BD: standard eth size rx ring
7727 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7728 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7729 *
7730 * like so:
7731 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7732 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7733 * ring attribute flags
7734 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7735 *
7736 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7737 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7738 *
7739 * The size of each ring is fixed in the firmware, but the location is
7740 * configurable.
7741 */
7742 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7743 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7744 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7745 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7746 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7747 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7748 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7749
fdb72b38
MC		 7750 /* Disable the mini ring */
7751 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7752 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7753 BDINFO_FLAGS_DISABLED);
7754
fdb72b38
MC		 7755 /* Program the jumbo buffer descriptor ring control
7756 * blocks on those devices that have them.
7757 */
8f666b07 7758 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7759 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7760 /* Setup replenish threshold. */
7761 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7762
0f893dc6 7763 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7764 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7765 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7766 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7767 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7768 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7769 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7770 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7771 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7772 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7773 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7774 } else {
7775 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7776 BDINFO_FLAGS_DISABLED);
7777 }
7778
b703df6f
MC		 7779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7780 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7781 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7782 (RX_STD_MAX_SIZE << 2);
7783 else
7784 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7785 } else
7786 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7787
7788 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7789
411da640 7790 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7791 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7792
411da640 7793 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7794 tp->rx_jumbo_pending : 0;
66711e66 7795 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7796
b703df6f
MC		 7797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7799 tw32(STD_REPLENISH_LWM, 32);
7800 tw32(JMB_REPLENISH_LWM, 16);
7801 }
7802
2d31ecaf
MC		 7803 tg3_rings_reset(tp);
7804
1da177e4 7805 /* Initialize MAC address and backoff seed. */
986e0aeb 7806 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7807
7808 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7809 tw32(MAC_RX_MTU_SIZE,
7810 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7811
7812 /* The slot time is changed by tg3_setup_phy if we
7813 * run at gigabit with half duplex.
7814 */
7815 tw32(MAC_TX_LENGTHS,
7816 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7817 (6 << TX_LENGTHS_IPG_SHIFT) |
7818 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7819
7820 /* Receive rules. */
7821 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7822 tw32(RCVLPC_CONFIG, 0x0181);
7823
7824 /* Calculate RDMAC_MODE setting early, we need it to determine
7825 * the RCVLPC_STATE_ENABLE mask.
7826 */
7827 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7828 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7829 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7830 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7831 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7832
57e6983c 7833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7836 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7837 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7838 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7839
85e94ced
MC		 7840 /* If statement applies to 5705 and 5750 PCI devices only */
7841 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7842 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7843 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7844 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7846 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7847 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7848 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7849 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7850 }
7851 }
7852
85e94ced
MC		 7853 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7854 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7855
1da177e4 7856 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7857 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7858
e849cdc3
MC		 7859 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7860 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7861 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7862 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7863
7864 /* Receive/send statistics. */
1661394e
MC		 7865 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7866 val = tr32(RCVLPC_STATS_ENABLE);
7867 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7868 tw32(RCVLPC_STATS_ENABLE, val);
7869 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7870 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7871 val = tr32(RCVLPC_STATS_ENABLE);
7872 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7873 tw32(RCVLPC_STATS_ENABLE, val);
7874 } else {
7875 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7876 }
7877 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7878 tw32(SNDDATAI_STATSENAB, 0xffffff);
7879 tw32(SNDDATAI_STATSCTRL,
7880 (SNDDATAI_SCTRL_ENABLE |
7881 SNDDATAI_SCTRL_FASTUPD));
7882
7883 /* Setup host coalescing engine. */
7884 tw32(HOSTCC_MODE, 0);
7885 for (i = 0; i < 2000; i++) {
7886 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7887 break;
7888 udelay(10);
7889 }
7890
d244c892 7891 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7892
1da177e4
LT		 7893 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7894 /* Status/statistics block address. See tg3_timer,
7895 * the tg3_periodic_fetch_stats call there, and
7896 * tg3_get_stats to see how this works for 5705/5750 chips.
7897 */
1da177e4
LT		 7898 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7899 ((u64) tp->stats_mapping >> 32));
7900 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7901 ((u64) tp->stats_mapping & 0xffffffff));
7902 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7903
1da177e4 7904 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7905
7906 /* Clear statistics and status block memory areas */
7907 for (i = NIC_SRAM_STATS_BLK;
7908 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7909 i += sizeof(u32)) {
7910 tg3_write_mem(tp, i, 0);
7911 udelay(40);
7912 }
1da177e4
LT		 7913 }
7914
7915 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7916
7917 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7918 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7919 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7920 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7921
c94e3941
MC		 7922 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7923 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7924 /* reset to prevent losing 1st rx packet intermittently */
7925 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7926 udelay(10);
7927 }
7928
3bda1258
MC		 7929 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7930 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7931 else
7932 tp->mac_mode = 0;
7933 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7934 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7935 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7936 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7937 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7938 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7939 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7940 udelay(40);
7941
314fba34 7942 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7943 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7944 * register to preserve the GPIO settings for LOMs. The GPIOs,
7945 * whether used as inputs or outputs, are set by boot code after
7946 * reset.
7947 */
9d26e213 7948 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7949 u32 gpio_mask;
7950
9d26e213
MC		 7951 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7952 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7953 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7954
7955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7956 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7957 GRC_LCLCTRL_GPIO_OUTPUT3;
7958
af36e6b6
MC		 7959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7960 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7961
aaf84465 7962 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7963 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7964
7965 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7966 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7967 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7968 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7969 }
1da177e4
LT		 7970 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7971 udelay(100);
7972
baf8a94a
MC		 7973 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7974 val = tr32(MSGINT_MODE);
7975 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7976 tw32(MSGINT_MODE, val);
7977 }
7978
1da177e4
LT		 7979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7980 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7981 udelay(40);
7982 }
7983
7984 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7985 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7986 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7987 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7988 WDMAC_MODE_LNGREAD_ENAB);
7989
85e94ced
MC		 7990 /* If statement applies to 5705 and 5750 PCI devices only */
7991 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7992 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7994 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7995 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7996 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7997 /* nothing */
7998 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7999 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8000 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8001 val |= WDMAC_MODE_RX_ACCEL;
8002 }
8003 }
8004
d9ab5ad1 8005 /* Enable host coalescing bug fix */
321d32a0 8006 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8007 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8008
788a035e
MC		 8009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8010 val |= WDMAC_MODE_BURST_ALL_DATA;
8011
1da177e4
LT		 8012 tw32_f(WDMAC_MODE, val);
8013 udelay(40);
8014
9974a356
MC		 8015 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8016 u16 pcix_cmd;
8017
8018 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8019 &pcix_cmd);
1da177e4 8020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8021 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8022 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8023 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8024 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8025 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8026 }
9974a356
MC		 8027 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8028 pcix_cmd);
1da177e4
LT		 8029 }
8030
8031 tw32_f(RDMAC_MODE, rdmac_mode);
8032 udelay(40);
8033
8034 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8035 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8036 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8037
8038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8039 tw32(SNDDATAC_MODE,
8040 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8041 else
8042 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8043
1da177e4
LT		 8044 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8045 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8046 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8047 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8048 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8049 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8050 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8051 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8052 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8053 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8054 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8055
8056 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8057 err = tg3_load_5701_a0_firmware_fix(tp);
8058 if (err)
8059 return err;
8060 }
8061
1da177e4
LT		 8062 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8063 err = tg3_load_tso_firmware(tp);
8064 if (err)
8065 return err;
8066 }
1da177e4
LT		 8067
8068 tp->tx_mode = TX_MODE_ENABLE;
8069 tw32_f(MAC_TX_MODE, tp->tx_mode);
8070 udelay(100);
8071
baf8a94a
MC		 8072 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8073 u32 reg = MAC_RSS_INDIR_TBL_0;
8074 u8 *ent = (u8 *)&val;
8075
8076 /* Setup the indirection table */
8077 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8078 int idx = i % sizeof(val);
8079
8080 ent[idx] = i % (tp->irq_cnt - 1);
8081 if (idx == sizeof(val) - 1) {
8082 tw32(reg, val);
8083 reg += 4;
8084 }
8085 }
8086
8087 /* Setup the "secret" hash key. */
8088 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8089 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8090 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8091 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8092 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8093 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8094 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8095 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8096 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8097 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8098 }
8099
1da177e4 8100 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8101 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8102 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8103
baf8a94a
MC		 8104 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8105 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8106 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8107 RX_MODE_RSS_IPV6_HASH_EN |
8108 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8109 RX_MODE_RSS_IPV4_HASH_EN |
8110 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8111
1da177e4
LT		 8112 tw32_f(MAC_RX_MODE, tp->rx_mode);
8113 udelay(10);
8114
1da177e4
LT		 8115 tw32(MAC_LED_CTRL, tp->led_ctrl);
8116
8117 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8118 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8119 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8120 udelay(10);
8121 }
8122 tw32_f(MAC_RX_MODE, tp->rx_mode);
8123 udelay(10);
8124
8125 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8126 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8127 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8128 /* Set drive transmission level to 1.2V */
8129 /* only if the signal pre-emphasis bit is not set */
8130 val = tr32(MAC_SERDES_CFG);
8131 val &= 0xfffff000;
8132 val |= 0x880;
8133 tw32(MAC_SERDES_CFG, val);
8134 }
8135 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8136 tw32(MAC_SERDES_CFG, 0x616000);
8137 }
8138
8139 /* Prevent chip from dropping frames when flow control
8140 * is enabled.
8141 */
8142 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8143
8144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8145 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8146 /* Use hardware link auto-negotiation */
8147 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8148 }
8149
d4d2c558
MC		 8150 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8151 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8152 u32 tmp;
8153
8154 tmp = tr32(SERDES_RX_CTRL);
8155 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8156 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8157 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8158 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8159 }
8160
dd477003
MC		 8161 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8162 if (tp->link_config.phy_is_low_power) {
8163 tp->link_config.phy_is_low_power = 0;
8164 tp->link_config.speed = tp->link_config.orig_speed;
8165 tp->link_config.duplex = tp->link_config.orig_duplex;
8166 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8167 }
1da177e4 8168
dd477003
MC		 8169 err = tg3_setup_phy(tp, 0);
8170 if (err)
8171 return err;
1da177e4 8172
dd477003 8173 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8174 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8175 u32 tmp;
8176
8177 /* Clear CRC stats. */
8178 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8179 tg3_writephy(tp, MII_TG3_TEST1,
8180 tmp | MII_TG3_TEST1_CRC_EN);
8181 tg3_readphy(tp, 0x14, &tmp);
8182 }
1da177e4
LT		 8183 }
8184 }
8185
8186 __tg3_set_rx_mode(tp->dev);
8187
8188 /* Initialize receive rules. */
8189 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8190 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8191 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8192 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8193
4cf78e4f 8194 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8195 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8196 limit = 8;
8197 else
8198 limit = 16;
8199 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8200 limit -= 4;
8201 switch (limit) {
8202 case 16:
8203 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8204 case 15:
8205 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8206 case 14:
8207 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8208 case 13:
8209 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8210 case 12:
8211 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8212 case 11:
8213 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8214 case 10:
8215 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8216 case 9:
8217 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8218 case 8:
8219 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8220 case 7:
8221 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8222 case 6:
8223 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8224 case 5:
8225 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8226 case 4:
8227 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8228 case 3:
8229 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8230 case 2:
8231 case 1:
8232
8233 default:
8234 break;
855e1111 8235 }
1da177e4 8236
9ce768ea
MC		 8237 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8238 /* Write our heartbeat update interval to APE. */
8239 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8240 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8241
1da177e4
LT		 8242 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8243
1da177e4
LT		 8244 return 0;
8245}
8246
8247/* Called at device open time to get the chip ready for
8248 * packet processing. Invoked with tp->lock held.
8249 */
8e7a22e3 8250static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8251{
1da177e4
LT		 8252 tg3_switch_clocks(tp);
8253
8254 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8255
2f751b67 8256 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8257}
8258
8259#define TG3_STAT_ADD32(PSTAT, REG) \
8260do { u32 __val = tr32(REG); \
8261 (PSTAT)->low += __val; \
8262 if ((PSTAT)->low < __val) \
8263 (PSTAT)->high += 1; \
8264} while (0)
8265
8266static void tg3_periodic_fetch_stats(struct tg3 *tp)
8267{
8268 struct tg3_hw_stats *sp = tp->hw_stats;
8269
8270 if (!netif_carrier_ok(tp->dev))
8271 return;
8272
8273 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8274 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8275 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8276 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8277 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8278 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8279 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8280 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8281 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8282 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8283 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8284 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8285 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8286
8287 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8288 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8289 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8290 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8291 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8292 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8293 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8294 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8295 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8296 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8297 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8298 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8299 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8300 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8301
8302 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8303 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8304 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8305}
8306
8307static void tg3_timer(unsigned long __opaque)
8308{
8309 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8310
f475f163
MC		 8311 if (tp->irq_sync)
8312 goto restart_timer;
8313
f47c11ee 8314 spin_lock(&tp->lock);
1da177e4 8315
fac9b83e
DM		 8316 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8317 /* All of this garbage is because when using non-tagged
8318 * IRQ status the mailbox/status_block protocol the chip
8319 * uses with the cpu is race prone.
8320 */
898a56f8 8321 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8322 tw32(GRC_LOCAL_CTRL,
8323 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8324 } else {
8325 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8326 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8327 }
1da177e4 8328
fac9b83e
DM		 8329 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8330 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8331 spin_unlock(&tp->lock);
fac9b83e
DM		 8332 schedule_work(&tp->reset_task);
8333 return;
8334 }
1da177e4
LT		 8335 }
8336
1da177e4
LT		 8337 /* This part only runs once per second. */
8338 if (!--tp->timer_counter) {
fac9b83e
DM		 8339 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8340 tg3_periodic_fetch_stats(tp);
8341
1da177e4
LT		 8342 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8343 u32 mac_stat;
8344 int phy_event;
8345
8346 mac_stat = tr32(MAC_STATUS);
8347
8348 phy_event = 0;
8349 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8350 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8351 phy_event = 1;
8352 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8353 phy_event = 1;
8354
8355 if (phy_event)
8356 tg3_setup_phy(tp, 0);
8357 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8358 u32 mac_stat = tr32(MAC_STATUS);
8359 int need_setup = 0;
8360
8361 if (netif_carrier_ok(tp->dev) &&
8362 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8363 need_setup = 1;
8364 }
8365 if (! netif_carrier_ok(tp->dev) &&
8366 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8367 MAC_STATUS_SIGNAL_DET))) {
8368 need_setup = 1;
8369 }
8370 if (need_setup) {
3d3ebe74
MC		 8371 if (!tp->serdes_counter) {
8372 tw32_f(MAC_MODE,
8373 (tp->mac_mode &
8374 ~MAC_MODE_PORT_MODE_MASK));
8375 udelay(40);
8376 tw32_f(MAC_MODE, tp->mac_mode);
8377 udelay(40);
8378 }
1da177e4
LT		 8379 tg3_setup_phy(tp, 0);
8380 }
747e8f8b
MC		 8381 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8382 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8383
8384 tp->timer_counter = tp->timer_multiplier;
8385 }
8386
130b8e4d
MC		 8387 /* Heartbeat is only sent once every 2 seconds.
8388 *
8389 * The heartbeat is to tell the ASF firmware that the host
8390 * driver is still alive. In the event that the OS crashes,
8391 * ASF needs to reset the hardware to free up the FIFO space
8392 * that may be filled with rx packets destined for the host.
8393 * If the FIFO is full, ASF will no longer function properly.
8394 *
8395 * Unintended resets have been reported on real time kernels
8396 * where the timer doesn't run on time. Netpoll will also have
8397 * same problem.
8398 *
8399 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8400 * to check the ring condition when the heartbeat is expiring
8401 * before doing the reset. This will prevent most unintended
8402 * resets.
8403 */
1da177e4 8404 if (!--tp->asf_counter) {
bc7959b2
MC		 8405 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8406 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8407 tg3_wait_for_event_ack(tp);
8408
bbadf503 8409 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8410 FWCMD_NICDRV_ALIVE3);
bbadf503 8411 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8412 /* 5 seconds timeout */
bbadf503 8413 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8414
8415 tg3_generate_fw_event(tp);
1da177e4
LT		 8416 }
8417 tp->asf_counter = tp->asf_multiplier;
8418 }
8419
f47c11ee 8420 spin_unlock(&tp->lock);
1da177e4 8421
f475f163 8422restart_timer:
1da177e4
LT		 8423 tp->timer.expires = jiffies + tp->timer_offset;
8424 add_timer(&tp->timer);
8425}
8426
4f125f42 8427static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8428{
7d12e780 8429 irq_handler_t fn;
fcfa0a32 8430 unsigned long flags;
4f125f42
MC		 8431 char *name;
8432 struct tg3_napi *tnapi = &tp->napi[irq_num];
8433
8434 if (tp->irq_cnt == 1)
8435 name = tp->dev->name;
8436 else {
8437 name = &tnapi->irq_lbl[0];
8438 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8439 name[IFNAMSIZ-1] = 0;
8440 }
fcfa0a32 8441
679563f4 8442 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8443 fn = tg3_msi;
8444 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8445 fn = tg3_msi_1shot;
1fb9df5d 8446 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8447 } else {
8448 fn = tg3_interrupt;
8449 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8450 fn = tg3_interrupt_tagged;
1fb9df5d 8451 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8452 }
4f125f42
MC		 8453
8454 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8455}
8456
7938109f
MC		 8457static int tg3_test_interrupt(struct tg3 *tp)
8458{
09943a18 8459 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8460 struct net_device *dev = tp->dev;
b16250e3 8461 int err, i, intr_ok = 0;
f6eb9b1f 8462 u32 val;
7938109f 8463
d4bc3927
MC		 8464 if (!netif_running(dev))
8465 return -ENODEV;
8466
7938109f
MC		 8467 tg3_disable_ints(tp);
8468
4f125f42 8469 free_irq(tnapi->irq_vec, tnapi);
7938109f 8470
f6eb9b1f
MC		 8471 /*
8472 * Turn off MSI one shot mode. Otherwise this test has no
8473 * observable way to know whether the interrupt was delivered.
8474 */
b703df6f
MC		 8475 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8477 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8478 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8479 tw32(MSGINT_MODE, val);
8480 }
8481
4f125f42 8482 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8483 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8484 if (err)
8485 return err;
8486
898a56f8 8487 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8488 tg3_enable_ints(tp);
8489
8490 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8491 tnapi->coal_now);
7938109f
MC		 8492
8493 for (i = 0; i < 5; i++) {
b16250e3
MC		 8494 u32 int_mbox, misc_host_ctrl;
8495
898a56f8 8496 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8497 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8498
8499 if ((int_mbox != 0) ||
8500 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8501 intr_ok = 1;
7938109f 8502 break;
b16250e3
MC		 8503 }
8504
7938109f
MC		 8505 msleep(10);
8506 }
8507
8508 tg3_disable_ints(tp);
8509
4f125f42 8510 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8511
4f125f42 8512 err = tg3_request_irq(tp, 0);
7938109f
MC		 8513
8514 if (err)
8515 return err;
8516
f6eb9b1f
MC		 8517 if (intr_ok) {
8518 /* Reenable MSI one shot mode. */
b703df6f
MC		 8519 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8521 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8522 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8523 tw32(MSGINT_MODE, val);
8524 }
7938109f 8525 return 0;
f6eb9b1f 8526 }
7938109f
MC		 8527
8528 return -EIO;
8529}
8530
8531/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8532 * successfully restored
8533 */
8534static int tg3_test_msi(struct tg3 *tp)
8535{
7938109f
MC		 8536 int err;
8537 u16 pci_cmd;
8538
8539 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8540 return 0;
8541
8542 /* Turn off SERR reporting in case MSI terminates with Master
8543 * Abort.
8544 */
8545 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8546 pci_write_config_word(tp->pdev, PCI_COMMAND,
8547 pci_cmd & ~PCI_COMMAND_SERR);
8548
8549 err = tg3_test_interrupt(tp);
8550
8551 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8552
8553 if (!err)
8554 return 0;
8555
8556 /* other failures */
8557 if (err != -EIO)
8558 return err;
8559
8560 /* MSI test failed, go back to INTx mode */
8561 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8562 "switching to INTx mode. Please report this failure to "
8563 "the PCI maintainer and include system chipset information.\n",
8564 tp->dev->name);
8565
4f125f42 8566 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8567
7938109f
MC		 8568 pci_disable_msi(tp->pdev);
8569
8570 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8571
4f125f42 8572 err = tg3_request_irq(tp, 0);
7938109f
MC		 8573 if (err)
8574 return err;
8575
8576 /* Need to reset the chip because the MSI cycle may have terminated
8577 * with Master Abort.
8578 */
f47c11ee 8579 tg3_full_lock(tp, 1);
7938109f 8580
944d980e 8581 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8582 err = tg3_init_hw(tp, 1);
7938109f 8583
f47c11ee 8584 tg3_full_unlock(tp);
7938109f
MC		 8585
8586 if (err)
4f125f42 8587 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8588
8589 return err;
8590}
8591
9e9fd12d
MC		 8592static int tg3_request_firmware(struct tg3 *tp)
8593{
8594 const __be32 *fw_data;
8595
8596 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8597 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8598 tp->dev->name, tp->fw_needed);
8599 return -ENOENT;
8600 }
8601
8602 fw_data = (void *)tp->fw->data;
8603
8604 /* Firmware blob starts with version numbers, followed by
8605 * start address and _full_ length including BSS sections
8606 * (which must be longer than the actual data, of course
8607 */
8608
8609 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8610 if (tp->fw_len < (tp->fw->size - 12)) {
8611 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8612 tp->dev->name, tp->fw_len, tp->fw_needed);
8613 release_firmware(tp->fw);
8614 tp->fw = NULL;
8615 return -EINVAL;
8616 }
8617
8618 /* We no longer need firmware; we have it. */
8619 tp->fw_needed = NULL;
8620 return 0;
8621}
8622
679563f4
MC		 8623static bool tg3_enable_msix(struct tg3 *tp)
8624{
8625 int i, rc, cpus = num_online_cpus();
8626 struct msix_entry msix_ent[tp->irq_max];
8627
8628 if (cpus == 1)
8629 /* Just fallback to the simpler MSI mode. */
8630 return false;
8631
8632 /*
8633 * We want as many rx rings enabled as there are cpus.
8634 * The first MSIX vector only deals with link interrupts, etc,
8635 * so we add one to the number of vectors we are requesting.
8636 */
8637 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8638
8639 for (i = 0; i < tp->irq_max; i++) {
8640 msix_ent[i].entry = i;
8641 msix_ent[i].vector = 0;
8642 }
8643
8644 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8645 if (rc != 0) {
8646 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8647 return false;
8648 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8649 return false;
8650 printk(KERN_NOTICE
8651 "%s: Requested %d MSI-X vectors, received %d\n",
8652 tp->dev->name, tp->irq_cnt, rc);
8653 tp->irq_cnt = rc;
8654 }
8655
baf8a94a
MC		 8656 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8657
679563f4
MC		 8658 for (i = 0; i < tp->irq_max; i++)
8659 tp->napi[i].irq_vec = msix_ent[i].vector;
8660
19cfaecc
MC		 8661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8662 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8663 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8664 } else
8665 tp->dev->real_num_tx_queues = 1;
fe5f5787 8666
679563f4
MC		 8667 return true;
8668}
8669
07b0173c
MC		 8670static void tg3_ints_init(struct tg3 *tp)
8671{
679563f4
MC		 8672 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8673 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8674 /* All MSI supporting chips should support tagged
8675 * status. Assert that this is the case.
8676 */
679563f4
MC		 8677 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8678 "Not using MSI.\n", tp->dev->name);
8679 goto defcfg;
07b0173c 8680 }
4f125f42 8681
679563f4
MC		 8682 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8683 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8684 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8685 pci_enable_msi(tp->pdev) == 0)
8686 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8687
8688 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8689 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8690 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8691 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8692 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8693 }
8694defcfg:
8695 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8696 tp->irq_cnt = 1;
8697 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8698 tp->dev->real_num_tx_queues = 1;
679563f4 8699 }
07b0173c
MC		 8700}
8701
8702static void tg3_ints_fini(struct tg3 *tp)
8703{
679563f4
MC		 8704 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8705 pci_disable_msix(tp->pdev);
8706 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8707 pci_disable_msi(tp->pdev);
8708 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8709 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8710}
8711
1da177e4
LT		 8712static int tg3_open(struct net_device *dev)
8713{
8714 struct tg3 *tp = netdev_priv(dev);
4f125f42 8715 int i, err;
1da177e4 8716
9e9fd12d
MC		 8717 if (tp->fw_needed) {
8718 err = tg3_request_firmware(tp);
8719 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8720 if (err)
8721 return err;
8722 } else if (err) {
8723 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8724 tp->dev->name);
8725 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8726 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8727 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8728 tp->dev->name);
8729 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8730 }
8731 }
8732
c49a1561
MC		 8733 netif_carrier_off(tp->dev);
8734
bc1c7567 8735 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8736 if (err)
bc1c7567 8737 return err;
2f751b67
MC		 8738
8739 tg3_full_lock(tp, 0);
bc1c7567 8740
1da177e4
LT		 8741 tg3_disable_ints(tp);
8742 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8743
f47c11ee 8744 tg3_full_unlock(tp);
1da177e4 8745
679563f4
MC		 8746 /*
8747 * Setup interrupts first so we know how
8748 * many NAPI resources to allocate
8749 */
8750 tg3_ints_init(tp);
8751
1da177e4
LT		 8752 /* The placement of this call is tied
8753 * to the setup and use of Host TX descriptors.
8754 */
8755 err = tg3_alloc_consistent(tp);
8756 if (err)
679563f4 8757 goto err_out1;
88b06bc2 8758
fed97810 8759 tg3_napi_enable(tp);
1da177e4 8760
4f125f42
MC		 8761 for (i = 0; i < tp->irq_cnt; i++) {
8762 struct tg3_napi *tnapi = &tp->napi[i];
8763 err = tg3_request_irq(tp, i);
8764 if (err) {
8765 for (i--; i >= 0; i--)
8766 free_irq(tnapi->irq_vec, tnapi);
8767 break;
8768 }
8769 }
1da177e4 8770
07b0173c 8771 if (err)
679563f4 8772 goto err_out2;
bea3348e 8773
f47c11ee 8774 tg3_full_lock(tp, 0);
1da177e4 8775
8e7a22e3 8776 err = tg3_init_hw(tp, 1);
1da177e4 8777 if (err) {
944d980e 8778 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8779 tg3_free_rings(tp);
8780 } else {
fac9b83e
DM		 8781 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8782 tp->timer_offset = HZ;
8783 else
8784 tp->timer_offset = HZ / 10;
8785
8786 BUG_ON(tp->timer_offset > HZ);
8787 tp->timer_counter = tp->timer_multiplier =
8788 (HZ / tp->timer_offset);
8789 tp->asf_counter = tp->asf_multiplier =
28fbef78 8790 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8791
8792 init_timer(&tp->timer);
8793 tp->timer.expires = jiffies + tp->timer_offset;
8794 tp->timer.data = (unsigned long) tp;
8795 tp->timer.function = tg3_timer;
1da177e4
LT		 8796 }
8797
f47c11ee 8798 tg3_full_unlock(tp);
1da177e4 8799
07b0173c 8800 if (err)
679563f4 8801 goto err_out3;
1da177e4 8802
7938109f
MC		 8803 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8804 err = tg3_test_msi(tp);
fac9b83e 8805
7938109f 8806 if (err) {
f47c11ee 8807 tg3_full_lock(tp, 0);
944d980e 8808 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8809 tg3_free_rings(tp);
f47c11ee 8810 tg3_full_unlock(tp);
7938109f 8811
679563f4 8812 goto err_out2;
7938109f 8813 }
fcfa0a32 8814
f6eb9b1f 8815 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8816 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8817 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8818 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8819 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8820
f6eb9b1f
MC		 8821 tw32(PCIE_TRANSACTION_CFG,
8822 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8823 }
7938109f
MC		 8824 }
8825
b02fd9e3
MC		 8826 tg3_phy_start(tp);
8827
f47c11ee 8828 tg3_full_lock(tp, 0);
1da177e4 8829
7938109f
MC		 8830 add_timer(&tp->timer);
8831 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8832 tg3_enable_ints(tp);
8833
f47c11ee 8834 tg3_full_unlock(tp);
1da177e4 8835
fe5f5787 8836 netif_tx_start_all_queues(dev);
1da177e4
LT		 8837
8838 return 0;
07b0173c 8839
679563f4 8840err_out3:
4f125f42
MC		 8841 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8842 struct tg3_napi *tnapi = &tp->napi[i];
8843 free_irq(tnapi->irq_vec, tnapi);
8844 }
07b0173c 8845
679563f4 8846err_out2:
fed97810 8847 tg3_napi_disable(tp);
07b0173c 8848 tg3_free_consistent(tp);
679563f4
MC		 8849
8850err_out1:
8851 tg3_ints_fini(tp);
07b0173c 8852 return err;
1da177e4
LT		 8853}
8854
8855#if 0
8856/*static*/ void tg3_dump_state(struct tg3 *tp)
8857{
8858 u32 val32, val32_2, val32_3, val32_4, val32_5;
8859 u16 val16;
8860 int i;
898a56f8 8861 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8862
8863 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8864 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8865 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8866 val16, val32);
8867
8868 /* MAC block */
8869 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8870 tr32(MAC_MODE), tr32(MAC_STATUS));
8871 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8872 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8873 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8874 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8875 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8876 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8877
8878 /* Send data initiator control block */
8879 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8880 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8881 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8882 tr32(SNDDATAI_STATSCTRL));
8883
8884 /* Send data completion control block */
8885 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8886
8887 /* Send BD ring selector block */
8888 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8889 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8890
8891 /* Send BD initiator control block */
8892 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8893 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8894
8895 /* Send BD completion control block */
8896 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8897
8898 /* Receive list placement control block */
8899 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8900 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8901 printk(" RCVLPC_STATSCTRL[%08x]\n",
8902 tr32(RCVLPC_STATSCTRL));
8903
8904 /* Receive data and receive BD initiator control block */
8905 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8906 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8907
8908 /* Receive data completion control block */
8909 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8910 tr32(RCVDCC_MODE));
8911
8912 /* Receive BD initiator control block */
8913 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8914 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8915
8916 /* Receive BD completion control block */
8917 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8918 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8919
8920 /* Receive list selector control block */
8921 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8922 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8923
8924 /* Mbuf cluster free block */
8925 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8926 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8927
8928 /* Host coalescing control block */
8929 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8930 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8931 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8932 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8933 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8934 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8935 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8936 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8937 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8938 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8939 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8940 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8941
8942 /* Memory arbiter control block */
8943 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8944 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8945
8946 /* Buffer manager control block */
8947 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8948 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8949 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8950 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8951 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8952 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8953 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8954 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8955
8956 /* Read DMA control block */
8957 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8958 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8959
8960 /* Write DMA control block */
8961 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8962 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8963
8964 /* DMA completion block */
8965 printk("DEBUG: DMAC_MODE[%08x]\n",
8966 tr32(DMAC_MODE));
8967
8968 /* GRC block */
8969 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8970 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8971 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8972 tr32(GRC_LOCAL_CTRL));
8973
8974 /* TG3_BDINFOs */
8975 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8976 tr32(RCVDBDI_JUMBO_BD + 0x0),
8977 tr32(RCVDBDI_JUMBO_BD + 0x4),
8978 tr32(RCVDBDI_JUMBO_BD + 0x8),
8979 tr32(RCVDBDI_JUMBO_BD + 0xc));
8980 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8981 tr32(RCVDBDI_STD_BD + 0x0),
8982 tr32(RCVDBDI_STD_BD + 0x4),
8983 tr32(RCVDBDI_STD_BD + 0x8),
8984 tr32(RCVDBDI_STD_BD + 0xc));
8985 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8986 tr32(RCVDBDI_MINI_BD + 0x0),
8987 tr32(RCVDBDI_MINI_BD + 0x4),
8988 tr32(RCVDBDI_MINI_BD + 0x8),
8989 tr32(RCVDBDI_MINI_BD + 0xc));
8990
8991 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8992 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8993 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8994 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8995 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8996 val32, val32_2, val32_3, val32_4);
8997
8998 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8999 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9000 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9001 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9002 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9003 val32, val32_2, val32_3, val32_4);
9004
9005 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9006 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9007 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9008 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9009 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9010 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9011 val32, val32_2, val32_3, val32_4, val32_5);
9012
9013 /* SW status block */
898a56f8
MC		 9014 printk(KERN_DEBUG
9015 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9016 sblk->status,
9017 sblk->status_tag,
9018 sblk->rx_jumbo_consumer,
9019 sblk->rx_consumer,
9020 sblk->rx_mini_consumer,
9021 sblk->idx[0].rx_producer,
9022 sblk->idx[0].tx_consumer);
1da177e4
LT		 9023
9024 /* SW statistics block */
9025 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9026 ((u32 *)tp->hw_stats)[0],
9027 ((u32 *)tp->hw_stats)[1],
9028 ((u32 *)tp->hw_stats)[2],
9029 ((u32 *)tp->hw_stats)[3]);
9030
9031 /* Mailboxes */
9032 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9033 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9034 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9035 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9036 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9037
9038 /* NIC side send descriptors. */
9039 for (i = 0; i < 6; i++) {
9040 unsigned long txd;
9041
9042 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9043 + (i * sizeof(struct tg3_tx_buffer_desc));
9044 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9045 i,
9046 readl(txd + 0x0), readl(txd + 0x4),
9047 readl(txd + 0x8), readl(txd + 0xc));
9048 }
9049
9050 /* NIC side RX descriptors. */
9051 for (i = 0; i < 6; i++) {
9052 unsigned long rxd;
9053
9054 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9055 + (i * sizeof(struct tg3_rx_buffer_desc));
9056 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9057 i,
9058 readl(rxd + 0x0), readl(rxd + 0x4),
9059 readl(rxd + 0x8), readl(rxd + 0xc));
9060 rxd += (4 * sizeof(u32));
9061 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9062 i,
9063 readl(rxd + 0x0), readl(rxd + 0x4),
9064 readl(rxd + 0x8), readl(rxd + 0xc));
9065 }
9066
9067 for (i = 0; i < 6; i++) {
9068 unsigned long rxd;
9069
9070 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9071 + (i * sizeof(struct tg3_rx_buffer_desc));
9072 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9073 i,
9074 readl(rxd + 0x0), readl(rxd + 0x4),
9075 readl(rxd + 0x8), readl(rxd + 0xc));
9076 rxd += (4 * sizeof(u32));
9077 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9078 i,
9079 readl(rxd + 0x0), readl(rxd + 0x4),
9080 readl(rxd + 0x8), readl(rxd + 0xc));
9081 }
9082}
9083#endif
9084
9085static struct net_device_stats *tg3_get_stats(struct net_device *);
9086static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9087
9088static int tg3_close(struct net_device *dev)
9089{
4f125f42 9090 int i;
1da177e4
LT		 9091 struct tg3 *tp = netdev_priv(dev);
9092
fed97810 9093 tg3_napi_disable(tp);
28e53bdd 9094 cancel_work_sync(&tp->reset_task);
7faa006f 9095
fe5f5787 9096 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9097
9098 del_timer_sync(&tp->timer);
9099
24bb4fb6
MC		 9100 tg3_phy_stop(tp);
9101
f47c11ee 9102 tg3_full_lock(tp, 1);
1da177e4
LT		 9103#if 0
9104 tg3_dump_state(tp);
9105#endif
9106
9107 tg3_disable_ints(tp);
9108
944d980e 9109 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9110 tg3_free_rings(tp);
5cf64b8a 9111 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9112
f47c11ee 9113 tg3_full_unlock(tp);
1da177e4 9114
4f125f42
MC		 9115 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9116 struct tg3_napi *tnapi = &tp->napi[i];
9117 free_irq(tnapi->irq_vec, tnapi);
9118 }
07b0173c
MC		 9119
9120 tg3_ints_fini(tp);
1da177e4
LT		 9121
9122 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9123 sizeof(tp->net_stats_prev));
9124 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9125 sizeof(tp->estats_prev));
9126
9127 tg3_free_consistent(tp);
9128
bc1c7567
MC		 9129 tg3_set_power_state(tp, PCI_D3hot);
9130
9131 netif_carrier_off(tp->dev);
9132
1da177e4
LT		 9133 return 0;
9134}
9135
9136static inline unsigned long get_stat64(tg3_stat64_t *val)
9137{
9138 unsigned long ret;
9139
9140#if (BITS_PER_LONG == 32)
9141 ret = val->low;
9142#else
9143 ret = ((u64)val->high << 32) | ((u64)val->low);
9144#endif
9145 return ret;
9146}
9147
816f8b86
SB		 9148static inline u64 get_estat64(tg3_stat64_t *val)
9149{
9150 return ((u64)val->high << 32) | ((u64)val->low);
9151}
9152
1da177e4
LT		 9153static unsigned long calc_crc_errors(struct tg3 *tp)
9154{
9155 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9156
9157 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9158 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9160 u32 val;
9161
f47c11ee 9162 spin_lock_bh(&tp->lock);
569a5df8
MC		 9163 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9164 tg3_writephy(tp, MII_TG3_TEST1,
9165 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9166 tg3_readphy(tp, 0x14, &val);
9167 } else
9168 val = 0;
f47c11ee 9169 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9170
9171 tp->phy_crc_errors += val;
9172
9173 return tp->phy_crc_errors;
9174 }
9175
9176 return get_stat64(&hw_stats->rx_fcs_errors);
9177}
9178
9179#define ESTAT_ADD(member) \
9180 estats->member = old_estats->member + \
816f8b86 9181 get_estat64(&hw_stats->member)
1da177e4
LT		 9182
9183static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9184{
9185 struct tg3_ethtool_stats *estats = &tp->estats;
9186 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9187 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9188
9189 if (!hw_stats)
9190 return old_estats;
9191
9192 ESTAT_ADD(rx_octets);
9193 ESTAT_ADD(rx_fragments);
9194 ESTAT_ADD(rx_ucast_packets);
9195 ESTAT_ADD(rx_mcast_packets);
9196 ESTAT_ADD(rx_bcast_packets);
9197 ESTAT_ADD(rx_fcs_errors);
9198 ESTAT_ADD(rx_align_errors);
9199 ESTAT_ADD(rx_xon_pause_rcvd);
9200 ESTAT_ADD(rx_xoff_pause_rcvd);
9201 ESTAT_ADD(rx_mac_ctrl_rcvd);
9202 ESTAT_ADD(rx_xoff_entered);
9203 ESTAT_ADD(rx_frame_too_long_errors);
9204 ESTAT_ADD(rx_jabbers);
9205 ESTAT_ADD(rx_undersize_packets);
9206 ESTAT_ADD(rx_in_length_errors);
9207 ESTAT_ADD(rx_out_length_errors);
9208 ESTAT_ADD(rx_64_or_less_octet_packets);
9209 ESTAT_ADD(rx_65_to_127_octet_packets);
9210 ESTAT_ADD(rx_128_to_255_octet_packets);
9211 ESTAT_ADD(rx_256_to_511_octet_packets);
9212 ESTAT_ADD(rx_512_to_1023_octet_packets);
9213 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9214 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9215 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9216 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9217 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9218
9219 ESTAT_ADD(tx_octets);
9220 ESTAT_ADD(tx_collisions);
9221 ESTAT_ADD(tx_xon_sent);
9222 ESTAT_ADD(tx_xoff_sent);
9223 ESTAT_ADD(tx_flow_control);
9224 ESTAT_ADD(tx_mac_errors);
9225 ESTAT_ADD(tx_single_collisions);
9226 ESTAT_ADD(tx_mult_collisions);
9227 ESTAT_ADD(tx_deferred);
9228 ESTAT_ADD(tx_excessive_collisions);
9229 ESTAT_ADD(tx_late_collisions);
9230 ESTAT_ADD(tx_collide_2times);
9231 ESTAT_ADD(tx_collide_3times);
9232 ESTAT_ADD(tx_collide_4times);
9233 ESTAT_ADD(tx_collide_5times);
9234 ESTAT_ADD(tx_collide_6times);
9235 ESTAT_ADD(tx_collide_7times);
9236 ESTAT_ADD(tx_collide_8times);
9237 ESTAT_ADD(tx_collide_9times);
9238 ESTAT_ADD(tx_collide_10times);
9239 ESTAT_ADD(tx_collide_11times);
9240 ESTAT_ADD(tx_collide_12times);
9241 ESTAT_ADD(tx_collide_13times);
9242 ESTAT_ADD(tx_collide_14times);
9243 ESTAT_ADD(tx_collide_15times);
9244 ESTAT_ADD(tx_ucast_packets);
9245 ESTAT_ADD(tx_mcast_packets);
9246 ESTAT_ADD(tx_bcast_packets);
9247 ESTAT_ADD(tx_carrier_sense_errors);
9248 ESTAT_ADD(tx_discards);
9249 ESTAT_ADD(tx_errors);
9250
9251 ESTAT_ADD(dma_writeq_full);
9252 ESTAT_ADD(dma_write_prioq_full);
9253 ESTAT_ADD(rxbds_empty);
9254 ESTAT_ADD(rx_discards);
9255 ESTAT_ADD(rx_errors);
9256 ESTAT_ADD(rx_threshold_hit);
9257
9258 ESTAT_ADD(dma_readq_full);
9259 ESTAT_ADD(dma_read_prioq_full);
9260 ESTAT_ADD(tx_comp_queue_full);
9261
9262 ESTAT_ADD(ring_set_send_prod_index);
9263 ESTAT_ADD(ring_status_update);
9264 ESTAT_ADD(nic_irqs);
9265 ESTAT_ADD(nic_avoided_irqs);
9266 ESTAT_ADD(nic_tx_threshold_hit);
9267
9268 return estats;
9269}
9270
9271static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9272{
9273 struct tg3 *tp = netdev_priv(dev);
9274 struct net_device_stats *stats = &tp->net_stats;
9275 struct net_device_stats *old_stats = &tp->net_stats_prev;
9276 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9277
9278 if (!hw_stats)
9279 return old_stats;
9280
9281 stats->rx_packets = old_stats->rx_packets +
9282 get_stat64(&hw_stats->rx_ucast_packets) +
9283 get_stat64(&hw_stats->rx_mcast_packets) +
9284 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9285
1da177e4
LT		 9286 stats->tx_packets = old_stats->tx_packets +
9287 get_stat64(&hw_stats->tx_ucast_packets) +
9288 get_stat64(&hw_stats->tx_mcast_packets) +
9289 get_stat64(&hw_stats->tx_bcast_packets);
9290
9291 stats->rx_bytes = old_stats->rx_bytes +
9292 get_stat64(&hw_stats->rx_octets);
9293 stats->tx_bytes = old_stats->tx_bytes +
9294 get_stat64(&hw_stats->tx_octets);
9295
9296 stats->rx_errors = old_stats->rx_errors +
4f63b877 9297 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9298 stats->tx_errors = old_stats->tx_errors +
9299 get_stat64(&hw_stats->tx_errors) +
9300 get_stat64(&hw_stats->tx_mac_errors) +
9301 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9302 get_stat64(&hw_stats->tx_discards);
9303
9304 stats->multicast = old_stats->multicast +
9305 get_stat64(&hw_stats->rx_mcast_packets);
9306 stats->collisions = old_stats->collisions +
9307 get_stat64(&hw_stats->tx_collisions);
9308
9309 stats->rx_length_errors = old_stats->rx_length_errors +
9310 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9311 get_stat64(&hw_stats->rx_undersize_packets);
9312
9313 stats->rx_over_errors = old_stats->rx_over_errors +
9314 get_stat64(&hw_stats->rxbds_empty);
9315 stats->rx_frame_errors = old_stats->rx_frame_errors +
9316 get_stat64(&hw_stats->rx_align_errors);
9317 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9318 get_stat64(&hw_stats->tx_discards);
9319 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9320 get_stat64(&hw_stats->tx_carrier_sense_errors);
9321
9322 stats->rx_crc_errors = old_stats->rx_crc_errors +
9323 calc_crc_errors(tp);
9324
4f63b877
JL		 9325 stats->rx_missed_errors = old_stats->rx_missed_errors +
9326 get_stat64(&hw_stats->rx_discards);
9327
1da177e4
LT		 9328 return stats;
9329}
9330
9331static inline u32 calc_crc(unsigned char *buf, int len)
9332{
9333 u32 reg;
9334 u32 tmp;
9335 int j, k;
9336
9337 reg = 0xffffffff;
9338
9339 for (j = 0; j < len; j++) {
9340 reg ^= buf[j];
9341
9342 for (k = 0; k < 8; k++) {
9343 tmp = reg & 0x01;
9344
9345 reg >>= 1;
9346
9347 if (tmp) {
9348 reg ^= 0xedb88320;
9349 }
9350 }
9351 }
9352
9353 return ~reg;
9354}
9355
9356static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9357{
9358 /* accept or reject all multicast frames */
9359 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9360 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9361 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9362 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9363}
9364
9365static void __tg3_set_rx_mode(struct net_device *dev)
9366{
9367 struct tg3 *tp = netdev_priv(dev);
9368 u32 rx_mode;
9369
9370 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9371 RX_MODE_KEEP_VLAN_TAG);
9372
9373 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9374 * flag clear.
9375 */
9376#if TG3_VLAN_TAG_USED
9377 if (!tp->vlgrp &&
9378 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9379 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9380#else
9381 /* By definition, VLAN is disabled always in this
9382 * case.
9383 */
9384 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9385 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9386#endif
9387
9388 if (dev->flags & IFF_PROMISC) {
9389 /* Promiscuous mode. */
9390 rx_mode |= RX_MODE_PROMISC;
9391 } else if (dev->flags & IFF_ALLMULTI) {
9392 /* Accept all multicast. */
9393 tg3_set_multi (tp, 1);
9394 } else if (dev->mc_count < 1) {
9395 /* Reject all multicast. */
9396 tg3_set_multi (tp, 0);
9397 } else {
9398 /* Accept one or more multicast(s). */
9399 struct dev_mc_list *mclist;
9400 unsigned int i;
9401 u32 mc_filter[4] = { 0, };
9402 u32 regidx;
9403 u32 bit;
9404 u32 crc;
9405
9406 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9407 i++, mclist = mclist->next) {
9408
9409 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9410 bit = ~crc & 0x7f;
9411 regidx = (bit & 0x60) >> 5;
9412 bit &= 0x1f;
9413 mc_filter[regidx] |= (1 << bit);
9414 }
9415
9416 tw32(MAC_HASH_REG_0, mc_filter[0]);
9417 tw32(MAC_HASH_REG_1, mc_filter[1]);
9418 tw32(MAC_HASH_REG_2, mc_filter[2]);
9419 tw32(MAC_HASH_REG_3, mc_filter[3]);
9420 }
9421
9422 if (rx_mode != tp->rx_mode) {
9423 tp->rx_mode = rx_mode;
9424 tw32_f(MAC_RX_MODE, rx_mode);
9425 udelay(10);
9426 }
9427}
9428
9429static void tg3_set_rx_mode(struct net_device *dev)
9430{
9431 struct tg3 *tp = netdev_priv(dev);
9432
e75f7c90
MC		 9433 if (!netif_running(dev))
9434 return;
9435
f47c11ee 9436 tg3_full_lock(tp, 0);
1da177e4 9437 __tg3_set_rx_mode(dev);
f47c11ee 9438 tg3_full_unlock(tp);
1da177e4
LT		 9439}
9440
9441#define TG3_REGDUMP_LEN (32 * 1024)
9442
9443static int tg3_get_regs_len(struct net_device *dev)
9444{
9445 return TG3_REGDUMP_LEN;
9446}
9447
9448static void tg3_get_regs(struct net_device *dev,
9449 struct ethtool_regs *regs, void *_p)
9450{
9451 u32 *p = _p;
9452 struct tg3 *tp = netdev_priv(dev);
9453 u8 *orig_p = _p;
9454 int i;
9455
9456 regs->version = 0;
9457
9458 memset(p, 0, TG3_REGDUMP_LEN);
9459
bc1c7567
MC		 9460 if (tp->link_config.phy_is_low_power)
9461 return;
9462
f47c11ee 9463 tg3_full_lock(tp, 0);
1da177e4
LT		 9464
9465#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9466#define GET_REG32_LOOP(base,len) \
9467do { p = (u32 *)(orig_p + (base)); \
9468 for (i = 0; i < len; i += 4) \
9469 __GET_REG32((base) + i); \
9470} while (0)
9471#define GET_REG32_1(reg) \
9472do { p = (u32 *)(orig_p + (reg)); \
9473 __GET_REG32((reg)); \
9474} while (0)
9475
9476 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9477 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9478 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9479 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9480 GET_REG32_1(SNDDATAC_MODE);
9481 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9482 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9483 GET_REG32_1(SNDBDC_MODE);
9484 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9485 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9486 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9487 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9488 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9489 GET_REG32_1(RCVDCC_MODE);
9490 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9491 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9492 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9493 GET_REG32_1(MBFREE_MODE);
9494 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9495 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9496 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9497 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9498 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9499 GET_REG32_1(RX_CPU_MODE);
9500 GET_REG32_1(RX_CPU_STATE);
9501 GET_REG32_1(RX_CPU_PGMCTR);
9502 GET_REG32_1(RX_CPU_HWBKPT);
9503 GET_REG32_1(TX_CPU_MODE);
9504 GET_REG32_1(TX_CPU_STATE);
9505 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9506 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9507 GET_REG32_LOOP(FTQ_RESET, 0x120);
9508 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9509 GET_REG32_1(DMAC_MODE);
9510 GET_REG32_LOOP(GRC_MODE, 0x4c);
9511 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9512 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9513
9514#undef __GET_REG32
9515#undef GET_REG32_LOOP
9516#undef GET_REG32_1
9517
f47c11ee 9518 tg3_full_unlock(tp);
1da177e4
LT		 9519}
9520
9521static int tg3_get_eeprom_len(struct net_device *dev)
9522{
9523 struct tg3 *tp = netdev_priv(dev);
9524
9525 return tp->nvram_size;
9526}
9527
1da177e4
LT		 9528static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9529{
9530 struct tg3 *tp = netdev_priv(dev);
9531 int ret;
9532 u8 *pd;
b9fc7dc5 9533 u32 i, offset, len, b_offset, b_count;
a9dc529d 9534 __be32 val;
1da177e4 9535
df259d8c
MC		 9536 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9537 return -EINVAL;
9538
bc1c7567
MC		 9539 if (tp->link_config.phy_is_low_power)
9540 return -EAGAIN;
9541
1da177e4
LT		 9542 offset = eeprom->offset;
9543 len = eeprom->len;
9544 eeprom->len = 0;
9545
9546 eeprom->magic = TG3_EEPROM_MAGIC;
9547
9548 if (offset & 3) {
9549 /* adjustments to start on required 4 byte boundary */
9550 b_offset = offset & 3;
9551 b_count = 4 - b_offset;
9552 if (b_count > len) {
9553 /* i.e. offset=1 len=2 */
9554 b_count = len;
9555 }
a9dc529d 9556 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9557 if (ret)
9558 return ret;
1da177e4
LT		 9559 memcpy(data, ((char*)&val) + b_offset, b_count);
9560 len -= b_count;
9561 offset += b_count;
9562 eeprom->len += b_count;
9563 }
9564
9565 /* read bytes upto the last 4 byte boundary */
9566 pd = &data[eeprom->len];
9567 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9568 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9569 if (ret) {
9570 eeprom->len += i;
9571 return ret;
9572 }
1da177e4
LT		 9573 memcpy(pd + i, &val, 4);
9574 }
9575 eeprom->len += i;
9576
9577 if (len & 3) {
9578 /* read last bytes not ending on 4 byte boundary */
9579 pd = &data[eeprom->len];
9580 b_count = len & 3;
9581 b_offset = offset + len - b_count;
a9dc529d 9582 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9583 if (ret)
9584 return ret;
b9fc7dc5 9585 memcpy(pd, &val, b_count);
1da177e4
LT		 9586 eeprom->len += b_count;
9587 }
9588 return 0;
9589}
9590
6aa20a22 9591static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9592
9593static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9594{
9595 struct tg3 *tp = netdev_priv(dev);
9596 int ret;
b9fc7dc5 9597 u32 offset, len, b_offset, odd_len;
1da177e4 9598 u8 *buf;
a9dc529d 9599 __be32 start, end;
1da177e4 9600
bc1c7567
MC		 9601 if (tp->link_config.phy_is_low_power)
9602 return -EAGAIN;
9603
df259d8c
MC		 9604 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9605 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9606 return -EINVAL;
9607
9608 offset = eeprom->offset;
9609 len = eeprom->len;
9610
9611 if ((b_offset = (offset & 3))) {
9612 /* adjustments to start on required 4 byte boundary */
a9dc529d 9613 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9614 if (ret)
9615 return ret;
1da177e4
LT		 9616 len += b_offset;
9617 offset &= ~3;
1c8594b4
MC		 9618 if (len < 4)
9619 len = 4;
1da177e4
LT		 9620 }
9621
9622 odd_len = 0;
1c8594b4 9623 if (len & 3) {
1da177e4
LT		 9624 /* adjustments to end on required 4 byte boundary */
9625 odd_len = 1;
9626 len = (len + 3) & ~3;
a9dc529d 9627 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9628 if (ret)
9629 return ret;
1da177e4
LT		 9630 }
9631
9632 buf = data;
9633 if (b_offset || odd_len) {
9634 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9635 if (!buf)
1da177e4
LT		 9636 return -ENOMEM;
9637 if (b_offset)
9638 memcpy(buf, &start, 4);
9639 if (odd_len)
9640 memcpy(buf+len-4, &end, 4);
9641 memcpy(buf + b_offset, data, eeprom->len);
9642 }
9643
9644 ret = tg3_nvram_write_block(tp, offset, len, buf);
9645
9646 if (buf != data)
9647 kfree(buf);
9648
9649 return ret;
9650}
9651
9652static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9653{
b02fd9e3
MC		 9654 struct tg3 *tp = netdev_priv(dev);
9655
9656 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9657 struct phy_device *phydev;
b02fd9e3
MC		 9658 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9659 return -EAGAIN;
3f0e3ad7
MC		 9660 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9661 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9662 }
6aa20a22 9663
1da177e4
LT		 9664 cmd->supported = (SUPPORTED_Autoneg);
9665
9666 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9667 cmd->supported |= (SUPPORTED_1000baseT_Half |
9668 SUPPORTED_1000baseT_Full);
9669
ef348144 9670 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9671 cmd->supported |= (SUPPORTED_100baseT_Half |
9672 SUPPORTED_100baseT_Full |
9673 SUPPORTED_10baseT_Half |
9674 SUPPORTED_10baseT_Full |
3bebab59 9675 SUPPORTED_TP);
ef348144
KK		 9676 cmd->port = PORT_TP;
9677 } else {
1da177e4 9678 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9679 cmd->port = PORT_FIBRE;
9680 }
6aa20a22 9681
1da177e4
LT		 9682 cmd->advertising = tp->link_config.advertising;
9683 if (netif_running(dev)) {
9684 cmd->speed = tp->link_config.active_speed;
9685 cmd->duplex = tp->link_config.active_duplex;
9686 }
882e9793 9687 cmd->phy_address = tp->phy_addr;
7e5856bd 9688 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9689 cmd->autoneg = tp->link_config.autoneg;
9690 cmd->maxtxpkt = 0;
9691 cmd->maxrxpkt = 0;
9692 return 0;
9693}
6aa20a22 9694
1da177e4
LT		 9695static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9696{
9697 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9698
b02fd9e3 9699 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9700 struct phy_device *phydev;
b02fd9e3
MC		 9701 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9702 return -EAGAIN;
3f0e3ad7
MC		 9703 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9704 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9705 }
9706
7e5856bd
MC		 9707 if (cmd->autoneg != AUTONEG_ENABLE &&
9708 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9709 return -EINVAL;
7e5856bd
MC		 9710
9711 if (cmd->autoneg == AUTONEG_DISABLE &&
9712 cmd->duplex != DUPLEX_FULL &&
9713 cmd->duplex != DUPLEX_HALF)
37ff238d 9714 return -EINVAL;
1da177e4 9715
7e5856bd
MC		 9716 if (cmd->autoneg == AUTONEG_ENABLE) {
9717 u32 mask = ADVERTISED_Autoneg |
9718 ADVERTISED_Pause |
9719 ADVERTISED_Asym_Pause;
9720
9721 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9722 mask |= ADVERTISED_1000baseT_Half |
9723 ADVERTISED_1000baseT_Full;
9724
9725 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9726 mask |= ADVERTISED_100baseT_Half |
9727 ADVERTISED_100baseT_Full |
9728 ADVERTISED_10baseT_Half |
9729 ADVERTISED_10baseT_Full |
9730 ADVERTISED_TP;
9731 else
9732 mask |= ADVERTISED_FIBRE;
9733
9734 if (cmd->advertising & ~mask)
9735 return -EINVAL;
9736
9737 mask &= (ADVERTISED_1000baseT_Half |
9738 ADVERTISED_1000baseT_Full |
9739 ADVERTISED_100baseT_Half |
9740 ADVERTISED_100baseT_Full |
9741 ADVERTISED_10baseT_Half |
9742 ADVERTISED_10baseT_Full);
9743
9744 cmd->advertising &= mask;
9745 } else {
9746 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9747 if (cmd->speed != SPEED_1000)
9748 return -EINVAL;
9749
9750 if (cmd->duplex != DUPLEX_FULL)
9751 return -EINVAL;
9752 } else {
9753 if (cmd->speed != SPEED_100 &&
9754 cmd->speed != SPEED_10)
9755 return -EINVAL;
9756 }
9757 }
9758
f47c11ee 9759 tg3_full_lock(tp, 0);
1da177e4
LT		 9760
9761 tp->link_config.autoneg = cmd->autoneg;
9762 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9763 tp->link_config.advertising = (cmd->advertising |
9764 ADVERTISED_Autoneg);
1da177e4
LT		 9765 tp->link_config.speed = SPEED_INVALID;
9766 tp->link_config.duplex = DUPLEX_INVALID;
9767 } else {
9768 tp->link_config.advertising = 0;
9769 tp->link_config.speed = cmd->speed;
9770 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9771 }
6aa20a22 9772
24fcad6b
MC		 9773 tp->link_config.orig_speed = tp->link_config.speed;
9774 tp->link_config.orig_duplex = tp->link_config.duplex;
9775 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9776
1da177e4
LT		 9777 if (netif_running(dev))
9778 tg3_setup_phy(tp, 1);
9779
f47c11ee 9780 tg3_full_unlock(tp);
6aa20a22 9781
1da177e4
LT		 9782 return 0;
9783}
6aa20a22 9784
1da177e4
LT		 9785static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9786{
9787 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9788
1da177e4
LT		 9789 strcpy(info->driver, DRV_MODULE_NAME);
9790 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9791 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9792 strcpy(info->bus_info, pci_name(tp->pdev));
9793}
6aa20a22 9794
1da177e4
LT		 9795static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9796{
9797 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9798
12dac075
RW		 9799 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9800 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9801 wol->supported = WAKE_MAGIC;
9802 else
9803 wol->supported = 0;
1da177e4 9804 wol->wolopts = 0;
05ac4cb7
MC		 9805 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9806 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9807 wol->wolopts = WAKE_MAGIC;
9808 memset(&wol->sopass, 0, sizeof(wol->sopass));
9809}
6aa20a22 9810
1da177e4
LT		 9811static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9812{
9813 struct tg3 *tp = netdev_priv(dev);
12dac075 9814 struct device *dp = &tp->pdev->dev;
6aa20a22 9815
1da177e4
LT		 9816 if (wol->wolopts & ~WAKE_MAGIC)
9817 return -EINVAL;
9818 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9819 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9820 return -EINVAL;
6aa20a22 9821
f47c11ee 9822 spin_lock_bh(&tp->lock);
12dac075 9823 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9824 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9825 device_set_wakeup_enable(dp, true);
9826 } else {
1da177e4 9827 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9828 device_set_wakeup_enable(dp, false);
9829 }
f47c11ee 9830 spin_unlock_bh(&tp->lock);
6aa20a22 9831
1da177e4
LT		 9832 return 0;
9833}
6aa20a22 9834
1da177e4
LT		 9835static u32 tg3_get_msglevel(struct net_device *dev)
9836{
9837 struct tg3 *tp = netdev_priv(dev);
9838 return tp->msg_enable;
9839}
6aa20a22 9840
1da177e4
LT		 9841static void tg3_set_msglevel(struct net_device *dev, u32 value)
9842{
9843 struct tg3 *tp = netdev_priv(dev);
9844 tp->msg_enable = value;
9845}
6aa20a22 9846
1da177e4
LT		 9847static int tg3_set_tso(struct net_device *dev, u32 value)
9848{
9849 struct tg3 *tp = netdev_priv(dev);
9850
9851 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9852 if (value)
9853 return -EINVAL;
9854 return 0;
9855 }
027455ad 9856 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9857 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9858 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9859 if (value) {
b0026624 9860 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9861 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9863 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9864 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9867 dev->features |= NETIF_F_TSO_ECN;
9868 } else
9869 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9870 }
1da177e4
LT		 9871 return ethtool_op_set_tso(dev, value);
9872}
6aa20a22 9873
1da177e4
LT		 9874static int tg3_nway_reset(struct net_device *dev)
9875{
9876 struct tg3 *tp = netdev_priv(dev);
1da177e4 9877 int r;
6aa20a22 9878
1da177e4
LT		 9879 if (!netif_running(dev))
9880 return -EAGAIN;
9881
c94e3941
MC		 9882 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9883 return -EINVAL;
9884
b02fd9e3
MC		 9885 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9886 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9887 return -EAGAIN;
3f0e3ad7 9888 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9889 } else {
9890 u32 bmcr;
9891
9892 spin_lock_bh(&tp->lock);
9893 r = -EINVAL;
9894 tg3_readphy(tp, MII_BMCR, &bmcr);
9895 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9896 ((bmcr & BMCR_ANENABLE) ||
9897 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9898 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9899 BMCR_ANENABLE);
9900 r = 0;
9901 }
9902 spin_unlock_bh(&tp->lock);
1da177e4 9903 }
6aa20a22 9904
1da177e4
LT		 9905 return r;
9906}
6aa20a22 9907
1da177e4
LT		 9908static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9909{
9910 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9911
1da177e4
LT		 9912 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9913 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9914 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9915 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9916 else
9917 ering->rx_jumbo_max_pending = 0;
9918
9919 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9920
9921 ering->rx_pending = tp->rx_pending;
9922 ering->rx_mini_pending = 0;
4f81c32b
MC		 9923 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9924 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9925 else
9926 ering->rx_jumbo_pending = 0;
9927
f3f3f27e 9928 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9929}
6aa20a22 9930
1da177e4
LT		 9931static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9932{
9933 struct tg3 *tp = netdev_priv(dev);
646c9edd 9934 int i, irq_sync = 0, err = 0;
6aa20a22 9935
1da177e4
LT		 9936 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9937 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9938 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9939 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9940 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9941 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9942 return -EINVAL;
6aa20a22 9943
bbe832c0 9944 if (netif_running(dev)) {
b02fd9e3 9945 tg3_phy_stop(tp);
1da177e4 9946 tg3_netif_stop(tp);
bbe832c0
MC		 9947 irq_sync = 1;
9948 }
1da177e4 9949
bbe832c0 9950 tg3_full_lock(tp, irq_sync);
6aa20a22 9951
1da177e4
LT		 9952 tp->rx_pending = ering->rx_pending;
9953
9954 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9955 tp->rx_pending > 63)
9956 tp->rx_pending = 63;
9957 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9958
9959 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9960 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9961
9962 if (netif_running(dev)) {
944d980e 9963 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9964 err = tg3_restart_hw(tp, 1);
9965 if (!err)
9966 tg3_netif_start(tp);
1da177e4
LT		 9967 }
9968
f47c11ee 9969 tg3_full_unlock(tp);
6aa20a22 9970
b02fd9e3
MC		 9971 if (irq_sync && !err)
9972 tg3_phy_start(tp);
9973
b9ec6c1b 9974 return err;
1da177e4 9975}
6aa20a22 9976
1da177e4
LT		 9977static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9978{
9979 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9980
1da177e4 9981 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9982
e18ce346 9983 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9984 epause->rx_pause = 1;
9985 else
9986 epause->rx_pause = 0;
9987
e18ce346 9988 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9989 epause->tx_pause = 1;
9990 else
9991 epause->tx_pause = 0;
1da177e4 9992}
6aa20a22 9993
1da177e4
LT		 9994static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9995{
9996 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9997 int err = 0;
6aa20a22 9998
b02fd9e3
MC		 9999 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10000 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10001 return -EAGAIN;
1da177e4 10002
b02fd9e3
MC		 10003 if (epause->autoneg) {
10004 u32 newadv;
10005 struct phy_device *phydev;
f47c11ee 10006
3f0e3ad7 10007 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 10008
b02fd9e3
MC		 10009 if (epause->rx_pause) {
10010 if (epause->tx_pause)
10011 newadv = ADVERTISED_Pause;
10012 else
10013 newadv = ADVERTISED_Pause |
10014 ADVERTISED_Asym_Pause;
10015 } else if (epause->tx_pause) {
10016 newadv = ADVERTISED_Asym_Pause;
10017 } else
10018 newadv = 0;
10019
10020 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10021 u32 oldadv = phydev->advertising &
10022 (ADVERTISED_Pause |
10023 ADVERTISED_Asym_Pause);
10024 if (oldadv != newadv) {
10025 phydev->advertising &=
10026 ~(ADVERTISED_Pause |
10027 ADVERTISED_Asym_Pause);
10028 phydev->advertising |= newadv;
10029 err = phy_start_aneg(phydev);
10030 }
10031 } else {
10032 tp->link_config.advertising &=
10033 ~(ADVERTISED_Pause |
10034 ADVERTISED_Asym_Pause);
10035 tp->link_config.advertising |= newadv;
10036 }
10037 } else {
10038 if (epause->rx_pause)
e18ce346 10039 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10040 else
e18ce346 10041 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10042
b02fd9e3 10043 if (epause->tx_pause)
e18ce346 10044 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10045 else
e18ce346 10046 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10047
10048 if (netif_running(dev))
10049 tg3_setup_flow_control(tp, 0, 0);
10050 }
10051 } else {
10052 int irq_sync = 0;
10053
10054 if (netif_running(dev)) {
10055 tg3_netif_stop(tp);
10056 irq_sync = 1;
10057 }
10058
10059 tg3_full_lock(tp, irq_sync);
10060
10061 if (epause->autoneg)
10062 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10063 else
10064 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10065 if (epause->rx_pause)
e18ce346 10066 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10067 else
e18ce346 10068 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10069 if (epause->tx_pause)
e18ce346 10070 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10071 else
e18ce346 10072 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10073
10074 if (netif_running(dev)) {
10075 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10076 err = tg3_restart_hw(tp, 1);
10077 if (!err)
10078 tg3_netif_start(tp);
10079 }
10080
10081 tg3_full_unlock(tp);
10082 }
6aa20a22 10083
b9ec6c1b 10084 return err;
1da177e4 10085}
6aa20a22 10086
1da177e4
LT		 10087static u32 tg3_get_rx_csum(struct net_device *dev)
10088{
10089 struct tg3 *tp = netdev_priv(dev);
10090 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10091}
6aa20a22 10092
1da177e4
LT		 10093static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10094{
10095 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10096
1da177e4
LT		 10097 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10098 if (data != 0)
10099 return -EINVAL;
10100 return 0;
10101 }
6aa20a22 10102
f47c11ee 10103 spin_lock_bh(&tp->lock);
1da177e4
LT		 10104 if (data)
10105 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10106 else
10107 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10108 spin_unlock_bh(&tp->lock);
6aa20a22 10109
1da177e4
LT		 10110 return 0;
10111}
6aa20a22 10112
1da177e4
LT		 10113static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10114{
10115 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10116
1da177e4
LT		 10117 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10118 if (data != 0)
10119 return -EINVAL;
10120 return 0;
10121 }
6aa20a22 10122
321d32a0 10123 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10124 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10125 else
9c27dbdf 10126 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10127
10128 return 0;
10129}
10130
b9f2c044 10131static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10132{
b9f2c044
JG		 10133 switch (sset) {
10134 case ETH_SS_TEST:
10135 return TG3_NUM_TEST;
10136 case ETH_SS_STATS:
10137 return TG3_NUM_STATS;
10138 default:
10139 return -EOPNOTSUPP;
10140 }
4cafd3f5
MC		 10141}
10142
1da177e4
LT		 10143static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10144{
10145 switch (stringset) {
10146 case ETH_SS_STATS:
10147 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10148 break;
4cafd3f5
MC		 10149 case ETH_SS_TEST:
10150 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10151 break;
1da177e4
LT		 10152 default:
10153 WARN_ON(1); /* we need a WARN() */
10154 break;
10155 }
10156}
10157
4009a93d
MC		 10158static int tg3_phys_id(struct net_device *dev, u32 data)
10159{
10160 struct tg3 *tp = netdev_priv(dev);
10161 int i;
10162
10163 if (!netif_running(tp->dev))
10164 return -EAGAIN;
10165
10166 if (data == 0)
759afc31 10167 data = UINT_MAX / 2;
4009a93d
MC		 10168
10169 for (i = 0; i < (data * 2); i++) {
10170 if ((i % 2) == 0)
10171 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10172 LED_CTRL_1000MBPS_ON |
10173 LED_CTRL_100MBPS_ON |
10174 LED_CTRL_10MBPS_ON |
10175 LED_CTRL_TRAFFIC_OVERRIDE |
10176 LED_CTRL_TRAFFIC_BLINK |
10177 LED_CTRL_TRAFFIC_LED);
6aa20a22 10178
4009a93d
MC		 10179 else
10180 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10181 LED_CTRL_TRAFFIC_OVERRIDE);
10182
10183 if (msleep_interruptible(500))
10184 break;
10185 }
10186 tw32(MAC_LED_CTRL, tp->led_ctrl);
10187 return 0;
10188}
10189
1da177e4
LT		 10190static void tg3_get_ethtool_stats (struct net_device *dev,
10191 struct ethtool_stats *estats, u64 *tmp_stats)
10192{
10193 struct tg3 *tp = netdev_priv(dev);
10194 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10195}
10196
566f86ad 10197#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10198#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10199#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10200#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10201#define NVRAM_SELFBOOT_HW_SIZE 0x20
10202#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10203
10204static int tg3_test_nvram(struct tg3 *tp)
10205{
b9fc7dc5 10206 u32 csum, magic;
a9dc529d 10207 __be32 *buf;
ab0049b4 10208 int i, j, k, err = 0, size;
566f86ad 10209
df259d8c
MC		 10210 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10211 return 0;
10212
e4f34110 10213 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10214 return -EIO;
10215
1b27777a
MC		 10216 if (magic == TG3_EEPROM_MAGIC)
10217 size = NVRAM_TEST_SIZE;
b16250e3 10218 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10219 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10220 TG3_EEPROM_SB_FORMAT_1) {
10221 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10222 case TG3_EEPROM_SB_REVISION_0:
10223 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10224 break;
10225 case TG3_EEPROM_SB_REVISION_2:
10226 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10227 break;
10228 case TG3_EEPROM_SB_REVISION_3:
10229 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10230 break;
10231 default:
10232 return 0;
10233 }
10234 } else
1b27777a 10235 return 0;
b16250e3
MC		 10236 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10237 size = NVRAM_SELFBOOT_HW_SIZE;
10238 else
1b27777a
MC		 10239 return -EIO;
10240
10241 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10242 if (buf == NULL)
10243 return -ENOMEM;
10244
1b27777a
MC		 10245 err = -EIO;
10246 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10247 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10248 if (err)
566f86ad 10249 break;
566f86ad 10250 }
1b27777a 10251 if (i < size)
566f86ad
MC		 10252 goto out;
10253
1b27777a 10254 /* Selfboot format */
a9dc529d 10255 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10256 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10257 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10258 u8 *buf8 = (u8 *) buf, csum8 = 0;
10259
b9fc7dc5 10260 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10261 TG3_EEPROM_SB_REVISION_2) {
10262 /* For rev 2, the csum doesn't include the MBA. */
10263 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10264 csum8 += buf8[i];
10265 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10266 csum8 += buf8[i];
10267 } else {
10268 for (i = 0; i < size; i++)
10269 csum8 += buf8[i];
10270 }
1b27777a 10271
ad96b485
AB		 10272 if (csum8 == 0) {
10273 err = 0;
10274 goto out;
10275 }
10276
10277 err = -EIO;
10278 goto out;
1b27777a 10279 }
566f86ad 10280
b9fc7dc5 10281 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10282 TG3_EEPROM_MAGIC_HW) {
10283 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10284 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10285 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10286
10287 /* Separate the parity bits and the data bytes. */
10288 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10289 if ((i == 0) || (i == 8)) {
10290 int l;
10291 u8 msk;
10292
10293 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10294 parity[k++] = buf8[i] & msk;
10295 i++;
10296 }
10297 else if (i == 16) {
10298 int l;
10299 u8 msk;
10300
10301 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10302 parity[k++] = buf8[i] & msk;
10303 i++;
10304
10305 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10306 parity[k++] = buf8[i] & msk;
10307 i++;
10308 }
10309 data[j++] = buf8[i];
10310 }
10311
10312 err = -EIO;
10313 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10314 u8 hw8 = hweight8(data[i]);
10315
10316 if ((hw8 & 0x1) && parity[i])
10317 goto out;
10318 else if (!(hw8 & 0x1) && !parity[i])
10319 goto out;
10320 }
10321 err = 0;
10322 goto out;
10323 }
10324
566f86ad
MC		 10325 /* Bootstrap checksum at offset 0x10 */
10326 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10327 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10328 goto out;
10329
10330 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10331 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10332 if (csum != be32_to_cpu(buf[0xfc/4]))
10333 goto out;
566f86ad
MC		 10334
10335 err = 0;
10336
10337out:
10338 kfree(buf);
10339 return err;
10340}
10341
ca43007a
MC		 10342#define TG3_SERDES_TIMEOUT_SEC 2
10343#define TG3_COPPER_TIMEOUT_SEC 6
10344
10345static int tg3_test_link(struct tg3 *tp)
10346{
10347 int i, max;
10348
10349 if (!netif_running(tp->dev))
10350 return -ENODEV;
10351
4c987487 10352 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10353 max = TG3_SERDES_TIMEOUT_SEC;
10354 else
10355 max = TG3_COPPER_TIMEOUT_SEC;
10356
10357 for (i = 0; i < max; i++) {
10358 if (netif_carrier_ok(tp->dev))
10359 return 0;
10360
10361 if (msleep_interruptible(1000))
10362 break;
10363 }
10364
10365 return -EIO;
10366}
10367
a71116d1 10368/* Only test the commonly used registers */
30ca3e37 10369static int tg3_test_registers(struct tg3 *tp)
a71116d1 10370{
b16250e3 10371 int i, is_5705, is_5750;
a71116d1
MC		 10372 u32 offset, read_mask, write_mask, val, save_val, read_val;
10373 static struct {
10374 u16 offset;
10375 u16 flags;
10376#define TG3_FL_5705 0x1
10377#define TG3_FL_NOT_5705 0x2
10378#define TG3_FL_NOT_5788 0x4
b16250e3 10379#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10380 u32 read_mask;
10381 u32 write_mask;
10382 } reg_tbl[] = {
10383 /* MAC Control Registers */
10384 { MAC_MODE, TG3_FL_NOT_5705,
10385 0x00000000, 0x00ef6f8c },
10386 { MAC_MODE, TG3_FL_5705,
10387 0x00000000, 0x01ef6b8c },
10388 { MAC_STATUS, TG3_FL_NOT_5705,
10389 0x03800107, 0x00000000 },
10390 { MAC_STATUS, TG3_FL_5705,
10391 0x03800100, 0x00000000 },
10392 { MAC_ADDR_0_HIGH, 0x0000,
10393 0x00000000, 0x0000ffff },
10394 { MAC_ADDR_0_LOW, 0x0000,
10395 0x00000000, 0xffffffff },
10396 { MAC_RX_MTU_SIZE, 0x0000,
10397 0x00000000, 0x0000ffff },
10398 { MAC_TX_MODE, 0x0000,
10399 0x00000000, 0x00000070 },
10400 { MAC_TX_LENGTHS, 0x0000,
10401 0x00000000, 0x00003fff },
10402 { MAC_RX_MODE, TG3_FL_NOT_5705,
10403 0x00000000, 0x000007fc },
10404 { MAC_RX_MODE, TG3_FL_5705,
10405 0x00000000, 0x000007dc },
10406 { MAC_HASH_REG_0, 0x0000,
10407 0x00000000, 0xffffffff },
10408 { MAC_HASH_REG_1, 0x0000,
10409 0x00000000, 0xffffffff },
10410 { MAC_HASH_REG_2, 0x0000,
10411 0x00000000, 0xffffffff },
10412 { MAC_HASH_REG_3, 0x0000,
10413 0x00000000, 0xffffffff },
10414
10415 /* Receive Data and Receive BD Initiator Control Registers. */
10416 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10417 0x00000000, 0xffffffff },
10418 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10419 0x00000000, 0xffffffff },
10420 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10421 0x00000000, 0x00000003 },
10422 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10423 0x00000000, 0xffffffff },
10424 { RCVDBDI_STD_BD+0, 0x0000,
10425 0x00000000, 0xffffffff },
10426 { RCVDBDI_STD_BD+4, 0x0000,
10427 0x00000000, 0xffffffff },
10428 { RCVDBDI_STD_BD+8, 0x0000,
10429 0x00000000, 0xffff0002 },
10430 { RCVDBDI_STD_BD+0xc, 0x0000,
10431 0x00000000, 0xffffffff },
6aa20a22 10432
a71116d1
MC		 10433 /* Receive BD Initiator Control Registers. */
10434 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10435 0x00000000, 0xffffffff },
10436 { RCVBDI_STD_THRESH, TG3_FL_5705,
10437 0x00000000, 0x000003ff },
10438 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10439 0x00000000, 0xffffffff },
6aa20a22 10440
a71116d1
MC		 10441 /* Host Coalescing Control Registers. */
10442 { HOSTCC_MODE, TG3_FL_NOT_5705,
10443 0x00000000, 0x00000004 },
10444 { HOSTCC_MODE, TG3_FL_5705,
10445 0x00000000, 0x000000f6 },
10446 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10447 0x00000000, 0xffffffff },
10448 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10449 0x00000000, 0x000003ff },
10450 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10451 0x00000000, 0xffffffff },
10452 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10453 0x00000000, 0x000003ff },
10454 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10455 0x00000000, 0xffffffff },
10456 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10457 0x00000000, 0x000000ff },
10458 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10459 0x00000000, 0xffffffff },
10460 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10461 0x00000000, 0x000000ff },
10462 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10463 0x00000000, 0xffffffff },
10464 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10465 0x00000000, 0xffffffff },
10466 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10467 0x00000000, 0xffffffff },
10468 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10469 0x00000000, 0x000000ff },
10470 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10471 0x00000000, 0xffffffff },
10472 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10473 0x00000000, 0x000000ff },
10474 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10475 0x00000000, 0xffffffff },
10476 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10477 0x00000000, 0xffffffff },
10478 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10479 0x00000000, 0xffffffff },
10480 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10481 0x00000000, 0xffffffff },
10482 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10483 0x00000000, 0xffffffff },
10484 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10485 0xffffffff, 0x00000000 },
10486 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10487 0xffffffff, 0x00000000 },
10488
10489 /* Buffer Manager Control Registers. */
b16250e3 10490 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10491 0x00000000, 0x007fff80 },
b16250e3 10492 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10493 0x00000000, 0x007fffff },
10494 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10495 0x00000000, 0x0000003f },
10496 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10497 0x00000000, 0x000001ff },
10498 { BUFMGR_MB_HIGH_WATER, 0x0000,
10499 0x00000000, 0x000001ff },
10500 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10501 0xffffffff, 0x00000000 },
10502 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10503 0xffffffff, 0x00000000 },
6aa20a22 10504
a71116d1
MC		 10505 /* Mailbox Registers */
10506 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10507 0x00000000, 0x000001ff },
10508 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10509 0x00000000, 0x000001ff },
10510 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10511 0x00000000, 0x000007ff },
10512 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10513 0x00000000, 0x000001ff },
10514
10515 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10516 };
10517
b16250e3
MC		 10518 is_5705 = is_5750 = 0;
10519 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10520 is_5705 = 1;
b16250e3
MC		 10521 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10522 is_5750 = 1;
10523 }
a71116d1
MC		 10524
10525 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10526 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10527 continue;
10528
10529 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10530 continue;
10531
10532 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10533 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10534 continue;
10535
b16250e3
MC		 10536 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10537 continue;
10538
a71116d1
MC		 10539 offset = (u32) reg_tbl[i].offset;
10540 read_mask = reg_tbl[i].read_mask;
10541 write_mask = reg_tbl[i].write_mask;
10542
10543 /* Save the original register content */
10544 save_val = tr32(offset);
10545
10546 /* Determine the read-only value. */
10547 read_val = save_val & read_mask;
10548
10549 /* Write zero to the register, then make sure the read-only bits
10550 * are not changed and the read/write bits are all zeros.
10551 */
10552 tw32(offset, 0);
10553
10554 val = tr32(offset);
10555
10556 /* Test the read-only and read/write bits. */
10557 if (((val & read_mask) != read_val) || (val & write_mask))
10558 goto out;
10559
10560 /* Write ones to all the bits defined by RdMask and WrMask, then
10561 * make sure the read-only bits are not changed and the
10562 * read/write bits are all ones.
10563 */
10564 tw32(offset, read_mask | write_mask);
10565
10566 val = tr32(offset);
10567
10568 /* Test the read-only bits. */
10569 if ((val & read_mask) != read_val)
10570 goto out;
10571
10572 /* Test the read/write bits. */
10573 if ((val & write_mask) != write_mask)
10574 goto out;
10575
10576 tw32(offset, save_val);
10577 }
10578
10579 return 0;
10580
10581out:
9f88f29f
MC		 10582 if (netif_msg_hw(tp))
10583 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10584 offset);
a71116d1
MC		 10585 tw32(offset, save_val);
10586 return -EIO;
10587}
10588
7942e1db
MC		 10589static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10590{
f71e1309 10591 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10592 int i;
10593 u32 j;
10594
e9edda69 10595 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10596 for (j = 0; j < len; j += 4) {
10597 u32 val;
10598
10599 tg3_write_mem(tp, offset + j, test_pattern[i]);
10600 tg3_read_mem(tp, offset + j, &val);
10601 if (val != test_pattern[i])
10602 return -EIO;
10603 }
10604 }
10605 return 0;
10606}
10607
10608static int tg3_test_memory(struct tg3 *tp)
10609{
10610 static struct mem_entry {
10611 u32 offset;
10612 u32 len;
10613 } mem_tbl_570x[] = {
38690194 10614 { 0x00000000, 0x00b50},
7942e1db
MC		 10615 { 0x00002000, 0x1c000},
10616 { 0xffffffff, 0x00000}
10617 }, mem_tbl_5705[] = {
10618 { 0x00000100, 0x0000c},
10619 { 0x00000200, 0x00008},
7942e1db
MC		 10620 { 0x00004000, 0x00800},
10621 { 0x00006000, 0x01000},
10622 { 0x00008000, 0x02000},
10623 { 0x00010000, 0x0e000},
10624 { 0xffffffff, 0x00000}
79f4d13a
MC		 10625 }, mem_tbl_5755[] = {
10626 { 0x00000200, 0x00008},
10627 { 0x00004000, 0x00800},
10628 { 0x00006000, 0x00800},
10629 { 0x00008000, 0x02000},
10630 { 0x00010000, 0x0c000},
10631 { 0xffffffff, 0x00000}
b16250e3
MC		 10632 }, mem_tbl_5906[] = {
10633 { 0x00000200, 0x00008},
10634 { 0x00004000, 0x00400},
10635 { 0x00006000, 0x00400},
10636 { 0x00008000, 0x01000},
10637 { 0x00010000, 0x01000},
10638 { 0xffffffff, 0x00000}
7942e1db
MC		 10639 };
10640 struct mem_entry *mem_tbl;
10641 int err = 0;
10642 int i;
10643
321d32a0
MC		 10644 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10645 mem_tbl = mem_tbl_5755;
10646 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10647 mem_tbl = mem_tbl_5906;
10648 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10649 mem_tbl = mem_tbl_5705;
10650 else
7942e1db
MC		 10651 mem_tbl = mem_tbl_570x;
10652
10653 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10654 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10655 mem_tbl[i].len)) != 0)
10656 break;
10657 }
6aa20a22 10658
7942e1db
MC		 10659 return err;
10660}
10661
9f40dead
MC		 10662#define TG3_MAC_LOOPBACK 0
10663#define TG3_PHY_LOOPBACK 1
10664
10665static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10666{
9f40dead 10667 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10668 u32 desc_idx, coal_now;
c76949a6
MC		 10669 struct sk_buff *skb, *rx_skb;
10670 u8 *tx_data;
10671 dma_addr_t map;
10672 int num_pkts, tx_len, rx_len, i, err;
10673 struct tg3_rx_buffer_desc *desc;
898a56f8 10674 struct tg3_napi *tnapi, *rnapi;
21f581a5 10675 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10676
0c1d0e2b
MC		 10677 if (tp->irq_cnt > 1) {
10678 tnapi = &tp->napi[1];
10679 rnapi = &tp->napi[1];
10680 } else {
10681 tnapi = &tp->napi[0];
10682 rnapi = &tp->napi[0];
10683 }
fd2ce37f 10684 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10685
9f40dead 10686 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10687 /* HW errata - mac loopback fails in some cases on 5780.
10688 * Normal traffic and PHY loopback are not affected by
10689 * errata.
10690 */
10691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10692 return 0;
10693
9f40dead 10694 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10695 MAC_MODE_PORT_INT_LPBACK;
10696 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10697 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10698 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10699 mac_mode |= MAC_MODE_PORT_MODE_MII;
10700 else
10701 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10702 tw32(MAC_MODE, mac_mode);
10703 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10704 u32 val;
10705
7f97a4bd
MC		 10706 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10707 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10708 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10709 } else
10710 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10711
9ef8ca99
MC		 10712 tg3_phy_toggle_automdix(tp, 0);
10713
3f7045c1 10714 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10715 udelay(40);
5d64ad34 10716
e8f3f6ca 10717 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10718 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10719 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10720 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10721 mac_mode |= MAC_MODE_PORT_MODE_MII;
10722 } else
10723 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10724
c94e3941
MC		 10725 /* reset to prevent losing 1st rx packet intermittently */
10726 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10727 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10728 udelay(10);
10729 tw32_f(MAC_RX_MODE, tp->rx_mode);
10730 }
e8f3f6ca
MC		 10731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10732 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10733 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10734 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10735 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10736 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10737 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10738 }
9f40dead 10739 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10740 }
10741 else
10742 return -EINVAL;
c76949a6
MC		 10743
10744 err = -EIO;
10745
c76949a6 10746 tx_len = 1514;
a20e9c62 10747 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10748 if (!skb)
10749 return -ENOMEM;
10750
c76949a6
MC		 10751 tx_data = skb_put(skb, tx_len);
10752 memcpy(tx_data, tp->dev->dev_addr, 6);
10753 memset(tx_data + 6, 0x0, 8);
10754
10755 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10756
10757 for (i = 14; i < tx_len; i++)
10758 tx_data[i] = (u8) (i & 0xff);
10759
f4188d8a
AD		 10760 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10761 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10762 dev_kfree_skb(skb);
10763 return -EIO;
10764 }
c76949a6
MC		 10765
10766 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10767 rnapi->coal_now);
c76949a6
MC		 10768
10769 udelay(10);
10770
898a56f8 10771 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10772
c76949a6
MC		 10773 num_pkts = 0;
10774
f4188d8a 10775 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10776
f3f3f27e 10777 tnapi->tx_prod++;
c76949a6
MC		 10778 num_pkts++;
10779
f3f3f27e
MC		 10780 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10781 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10782
10783 udelay(10);
10784
303fc921
MC		 10785 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10786 for (i = 0; i < 35; i++) {
c76949a6 10787 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10788 coal_now);
c76949a6
MC		 10789
10790 udelay(10);
10791
898a56f8
MC		 10792 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10793 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10794 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10795 (rx_idx == (rx_start_idx + num_pkts)))
10796 break;
10797 }
10798
f4188d8a 10799 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10800 dev_kfree_skb(skb);
10801
f3f3f27e 10802 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10803 goto out;
10804
10805 if (rx_idx != rx_start_idx + num_pkts)
10806 goto out;
10807
72334482 10808 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10809 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10810 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10811 if (opaque_key != RXD_OPAQUE_RING_STD)
10812 goto out;
10813
10814 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10815 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10816 goto out;
10817
10818 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10819 if (rx_len != tx_len)
10820 goto out;
10821
21f581a5 10822 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10823
21f581a5 10824 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10825 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10826
10827 for (i = 14; i < tx_len; i++) {
10828 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10829 goto out;
10830 }
10831 err = 0;
6aa20a22 10832
c76949a6
MC		 10833 /* tg3_free_rings will unmap and free the rx_skb */
10834out:
10835 return err;
10836}
10837
9f40dead
MC		 10838#define TG3_MAC_LOOPBACK_FAILED 1
10839#define TG3_PHY_LOOPBACK_FAILED 2
10840#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10841 TG3_PHY_LOOPBACK_FAILED)
10842
10843static int tg3_test_loopback(struct tg3 *tp)
10844{
10845 int err = 0;
9936bcf6 10846 u32 cpmuctrl = 0;
9f40dead
MC		 10847
10848 if (!netif_running(tp->dev))
10849 return TG3_LOOPBACK_FAILED;
10850
b9ec6c1b
MC		 10851 err = tg3_reset_hw(tp, 1);
10852 if (err)
10853 return TG3_LOOPBACK_FAILED;
9f40dead 10854
6833c043
MC		 10855 /* Turn off gphy autopowerdown. */
10856 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10857 tg3_phy_toggle_apd(tp, false);
10858
321d32a0 10859 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10860 int i;
10861 u32 status;
10862
10863 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10864
10865 /* Wait for up to 40 microseconds to acquire lock. */
10866 for (i = 0; i < 4; i++) {
10867 status = tr32(TG3_CPMU_MUTEX_GNT);
10868 if (status == CPMU_MUTEX_GNT_DRIVER)
10869 break;
10870 udelay(10);
10871 }
10872
10873 if (status != CPMU_MUTEX_GNT_DRIVER)
10874 return TG3_LOOPBACK_FAILED;
10875
b2a5c19c 10876 /* Turn off link-based power management. */
e875093c 10877 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10878 tw32(TG3_CPMU_CTRL,
10879 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10880 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10881 }
10882
9f40dead
MC		 10883 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10884 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10885
321d32a0 10886 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10887 tw32(TG3_CPMU_CTRL, cpmuctrl);
10888
10889 /* Release the mutex */
10890 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10891 }
10892
dd477003
MC		 10893 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10894 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10895 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10896 err |= TG3_PHY_LOOPBACK_FAILED;
10897 }
10898
6833c043
MC		 10899 /* Re-enable gphy autopowerdown. */
10900 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10901 tg3_phy_toggle_apd(tp, true);
10902
9f40dead
MC		 10903 return err;
10904}
10905
4cafd3f5
MC		 10906static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10907 u64 *data)
10908{
566f86ad
MC		 10909 struct tg3 *tp = netdev_priv(dev);
10910
bc1c7567
MC		 10911 if (tp->link_config.phy_is_low_power)
10912 tg3_set_power_state(tp, PCI_D0);
10913
566f86ad
MC		 10914 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10915
10916 if (tg3_test_nvram(tp) != 0) {
10917 etest->flags |= ETH_TEST_FL_FAILED;
10918 data[0] = 1;
10919 }
ca43007a
MC		 10920 if (tg3_test_link(tp) != 0) {
10921 etest->flags |= ETH_TEST_FL_FAILED;
10922 data[1] = 1;
10923 }
a71116d1 10924 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10925 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10926
10927 if (netif_running(dev)) {
b02fd9e3 10928 tg3_phy_stop(tp);
a71116d1 10929 tg3_netif_stop(tp);
bbe832c0
MC		 10930 irq_sync = 1;
10931 }
a71116d1 10932
bbe832c0 10933 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10934
10935 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10936 err = tg3_nvram_lock(tp);
a71116d1
MC		 10937 tg3_halt_cpu(tp, RX_CPU_BASE);
10938 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10939 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10940 if (!err)
10941 tg3_nvram_unlock(tp);
a71116d1 10942
d9ab5ad1
MC		 10943 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10944 tg3_phy_reset(tp);
10945
a71116d1
MC		 10946 if (tg3_test_registers(tp) != 0) {
10947 etest->flags |= ETH_TEST_FL_FAILED;
10948 data[2] = 1;
10949 }
7942e1db
MC		 10950 if (tg3_test_memory(tp) != 0) {
10951 etest->flags |= ETH_TEST_FL_FAILED;
10952 data[3] = 1;
10953 }
9f40dead 10954 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10955 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10956
f47c11ee
DM		 10957 tg3_full_unlock(tp);
10958
d4bc3927
MC		 10959 if (tg3_test_interrupt(tp) != 0) {
10960 etest->flags |= ETH_TEST_FL_FAILED;
10961 data[5] = 1;
10962 }
f47c11ee
DM		 10963
10964 tg3_full_lock(tp, 0);
d4bc3927 10965
a71116d1
MC		 10966 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10967 if (netif_running(dev)) {
10968 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10969 err2 = tg3_restart_hw(tp, 1);
10970 if (!err2)
b9ec6c1b 10971 tg3_netif_start(tp);
a71116d1 10972 }
f47c11ee
DM		 10973
10974 tg3_full_unlock(tp);
b02fd9e3
MC		 10975
10976 if (irq_sync && !err2)
10977 tg3_phy_start(tp);
a71116d1 10978 }
bc1c7567
MC		 10979 if (tp->link_config.phy_is_low_power)
10980 tg3_set_power_state(tp, PCI_D3hot);
10981
4cafd3f5
MC		 10982}
10983
1da177e4
LT		 10984static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10985{
10986 struct mii_ioctl_data *data = if_mii(ifr);
10987 struct tg3 *tp = netdev_priv(dev);
10988 int err;
10989
b02fd9e3 10990 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10991 struct phy_device *phydev;
b02fd9e3
MC		 10992 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10993 return -EAGAIN;
3f0e3ad7
MC		 10994 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10995 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10996 }
10997
1da177e4
LT		 10998 switch(cmd) {
10999 case SIOCGMIIPHY:
882e9793 11000 data->phy_id = tp->phy_addr;
1da177e4
LT		 11001
11002 /* fallthru */
11003 case SIOCGMIIREG: {
11004 u32 mii_regval;
11005
11006 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11007 break; /* We have no PHY */
11008
bc1c7567
MC		 11009 if (tp->link_config.phy_is_low_power)
11010 return -EAGAIN;
11011
f47c11ee 11012 spin_lock_bh(&tp->lock);
1da177e4 11013 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11014 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11015
11016 data->val_out = mii_regval;
11017
11018 return err;
11019 }
11020
11021 case SIOCSMIIREG:
11022 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11023 break; /* We have no PHY */
11024
bc1c7567
MC		 11025 if (tp->link_config.phy_is_low_power)
11026 return -EAGAIN;
11027
f47c11ee 11028 spin_lock_bh(&tp->lock);
1da177e4 11029 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11030 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11031
11032 return err;
11033
11034 default:
11035 /* do nothing */
11036 break;
11037 }
11038 return -EOPNOTSUPP;
11039}
11040
11041#if TG3_VLAN_TAG_USED
11042static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11043{
11044 struct tg3 *tp = netdev_priv(dev);
11045
844b3eed
MC		 11046 if (!netif_running(dev)) {
11047 tp->vlgrp = grp;
11048 return;
11049 }
11050
11051 tg3_netif_stop(tp);
29315e87 11052
f47c11ee 11053 tg3_full_lock(tp, 0);
1da177e4
LT		 11054
11055 tp->vlgrp = grp;
11056
11057 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11058 __tg3_set_rx_mode(dev);
11059
844b3eed 11060 tg3_netif_start(tp);
46966545
MC		 11061
11062 tg3_full_unlock(tp);
1da177e4 11063}
1da177e4
LT		 11064#endif
11065
15f9850d
DM		 11066static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11067{
11068 struct tg3 *tp = netdev_priv(dev);
11069
11070 memcpy(ec, &tp->coal, sizeof(*ec));
11071 return 0;
11072}
11073
d244c892
MC		 11074static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11075{
11076 struct tg3 *tp = netdev_priv(dev);
11077 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11078 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11079
11080 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11081 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11082 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11083 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11084 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11085 }
11086
11087 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11088 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11089 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11090 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11091 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11092 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11093 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11094 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11095 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11096 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11097 return -EINVAL;
11098
11099 /* No rx interrupts will be generated if both are zero */
11100 if ((ec->rx_coalesce_usecs == 0) &&
11101 (ec->rx_max_coalesced_frames == 0))
11102 return -EINVAL;
11103
11104 /* No tx interrupts will be generated if both are zero */
11105 if ((ec->tx_coalesce_usecs == 0) &&
11106 (ec->tx_max_coalesced_frames == 0))
11107 return -EINVAL;
11108
11109 /* Only copy relevant parameters, ignore all others. */
11110 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11111 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11112 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11113 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11114 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11115 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11116 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11117 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11118 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11119
11120 if (netif_running(dev)) {
11121 tg3_full_lock(tp, 0);
11122 __tg3_set_coalesce(tp, &tp->coal);
11123 tg3_full_unlock(tp);
11124 }
11125 return 0;
11126}
11127
7282d491 11128static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11129 .get_settings = tg3_get_settings,
11130 .set_settings = tg3_set_settings,
11131 .get_drvinfo = tg3_get_drvinfo,
11132 .get_regs_len = tg3_get_regs_len,
11133 .get_regs = tg3_get_regs,
11134 .get_wol = tg3_get_wol,
11135 .set_wol = tg3_set_wol,
11136 .get_msglevel = tg3_get_msglevel,
11137 .set_msglevel = tg3_set_msglevel,
11138 .nway_reset = tg3_nway_reset,
11139 .get_link = ethtool_op_get_link,
11140 .get_eeprom_len = tg3_get_eeprom_len,
11141 .get_eeprom = tg3_get_eeprom,
11142 .set_eeprom = tg3_set_eeprom,
11143 .get_ringparam = tg3_get_ringparam,
11144 .set_ringparam = tg3_set_ringparam,
11145 .get_pauseparam = tg3_get_pauseparam,
11146 .set_pauseparam = tg3_set_pauseparam,
11147 .get_rx_csum = tg3_get_rx_csum,
11148 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11149 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11150 .set_sg = ethtool_op_set_sg,
1da177e4 11151 .set_tso = tg3_set_tso,
4cafd3f5 11152 .self_test = tg3_self_test,
1da177e4 11153 .get_strings = tg3_get_strings,
4009a93d 11154 .phys_id = tg3_phys_id,
1da177e4 11155 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11156 .get_coalesce = tg3_get_coalesce,
d244c892 11157 .set_coalesce = tg3_set_coalesce,
b9f2c044 11158 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11159};
11160
11161static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11162{
1b27777a 11163 u32 cursize, val, magic;
1da177e4
LT		 11164
11165 tp->nvram_size = EEPROM_CHIP_SIZE;
11166
e4f34110 11167 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11168 return;
11169
b16250e3
MC		 11170 if ((magic != TG3_EEPROM_MAGIC) &&
11171 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11172 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11173 return;
11174
11175 /*
11176 * Size the chip by reading offsets at increasing powers of two.
11177 * When we encounter our validation signature, we know the addressing
11178 * has wrapped around, and thus have our chip size.
11179 */
1b27777a 11180 cursize = 0x10;
1da177e4
LT		 11181
11182 while (cursize < tp->nvram_size) {
e4f34110 11183 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11184 return;
11185
1820180b 11186 if (val == magic)
1da177e4
LT		 11187 break;
11188
11189 cursize <<= 1;
11190 }
11191
11192 tp->nvram_size = cursize;
11193}
6aa20a22 11194
1da177e4
LT		 11195static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11196{
11197 u32 val;
11198
df259d8c
MC		 11199 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11200 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11201 return;
11202
11203 /* Selfboot format */
1820180b 11204 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11205 tg3_get_eeprom_size(tp);
11206 return;
11207 }
11208
6d348f2c 11209 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11210 if (val != 0) {
6d348f2c
MC		 11211 /* This is confusing. We want to operate on the
11212 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11213 * call will read from NVRAM and byteswap the data
11214 * according to the byteswapping settings for all
11215 * other register accesses. This ensures the data we
11216 * want will always reside in the lower 16-bits.
11217 * However, the data in NVRAM is in LE format, which
11218 * means the data from the NVRAM read will always be
11219 * opposite the endianness of the CPU. The 16-bit
11220 * byteswap then brings the data to CPU endianness.
11221 */
11222 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11223 return;
11224 }
11225 }
fd1122a2 11226 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11227}
11228
11229static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11230{
11231 u32 nvcfg1;
11232
11233 nvcfg1 = tr32(NVRAM_CFG1);
11234 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11235 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11236 } else {
1da177e4
LT		 11237 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11238 tw32(NVRAM_CFG1, nvcfg1);
11239 }
11240
4c987487 11241 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11242 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11243 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11244 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11245 tp->nvram_jedecnum = JEDEC_ATMEL;
11246 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11247 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11248 break;
11249 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11250 tp->nvram_jedecnum = JEDEC_ATMEL;
11251 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11252 break;
11253 case FLASH_VENDOR_ATMEL_EEPROM:
11254 tp->nvram_jedecnum = JEDEC_ATMEL;
11255 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11256 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11257 break;
11258 case FLASH_VENDOR_ST:
11259 tp->nvram_jedecnum = JEDEC_ST;
11260 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11261 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11262 break;
11263 case FLASH_VENDOR_SAIFUN:
11264 tp->nvram_jedecnum = JEDEC_SAIFUN;
11265 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11266 break;
11267 case FLASH_VENDOR_SST_SMALL:
11268 case FLASH_VENDOR_SST_LARGE:
11269 tp->nvram_jedecnum = JEDEC_SST;
11270 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11271 break;
1da177e4 11272 }
8590a603 11273 } else {
1da177e4
LT		 11274 tp->nvram_jedecnum = JEDEC_ATMEL;
11275 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11276 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11277 }
11278}
11279
a1b950d5
MC		 11280static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11281{
11282 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11283 case FLASH_5752PAGE_SIZE_256:
11284 tp->nvram_pagesize = 256;
11285 break;
11286 case FLASH_5752PAGE_SIZE_512:
11287 tp->nvram_pagesize = 512;
11288 break;
11289 case FLASH_5752PAGE_SIZE_1K:
11290 tp->nvram_pagesize = 1024;
11291 break;
11292 case FLASH_5752PAGE_SIZE_2K:
11293 tp->nvram_pagesize = 2048;
11294 break;
11295 case FLASH_5752PAGE_SIZE_4K:
11296 tp->nvram_pagesize = 4096;
11297 break;
11298 case FLASH_5752PAGE_SIZE_264:
11299 tp->nvram_pagesize = 264;
11300 break;
11301 case FLASH_5752PAGE_SIZE_528:
11302 tp->nvram_pagesize = 528;
11303 break;
11304 }
11305}
11306
361b4ac2
MC		 11307static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11308{
11309 u32 nvcfg1;
11310
11311 nvcfg1 = tr32(NVRAM_CFG1);
11312
e6af301b
MC		 11313 /* NVRAM protection for TPM */
11314 if (nvcfg1 & (1 << 27))
f66a29b0 11315 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11316
361b4ac2 11317 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11318 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11319 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11320 tp->nvram_jedecnum = JEDEC_ATMEL;
11321 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11322 break;
11323 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11324 tp->nvram_jedecnum = JEDEC_ATMEL;
11325 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11326 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11327 break;
11328 case FLASH_5752VENDOR_ST_M45PE10:
11329 case FLASH_5752VENDOR_ST_M45PE20:
11330 case FLASH_5752VENDOR_ST_M45PE40:
11331 tp->nvram_jedecnum = JEDEC_ST;
11332 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11333 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11334 break;
361b4ac2
MC		 11335 }
11336
11337 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11338 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11339 } else {
361b4ac2
MC		 11340 /* For eeprom, set pagesize to maximum eeprom size */
11341 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11342
11343 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11344 tw32(NVRAM_CFG1, nvcfg1);
11345 }
11346}
11347
d3c7b886
MC		 11348static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11349{
989a9d23 11350 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11351
11352 nvcfg1 = tr32(NVRAM_CFG1);
11353
11354 /* NVRAM protection for TPM */
989a9d23 11355 if (nvcfg1 & (1 << 27)) {
f66a29b0 11356 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11357 protect = 1;
11358 }
d3c7b886 11359
989a9d23
MC		 11360 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11361 switch (nvcfg1) {
8590a603
MC		 11362 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11363 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11364 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11365 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11366 tp->nvram_jedecnum = JEDEC_ATMEL;
11367 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11368 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11369 tp->nvram_pagesize = 264;
11370 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11371 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11372 tp->nvram_size = (protect ? 0x3e200 :
11373 TG3_NVRAM_SIZE_512KB);
11374 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11375 tp->nvram_size = (protect ? 0x1f200 :
11376 TG3_NVRAM_SIZE_256KB);
11377 else
11378 tp->nvram_size = (protect ? 0x1f200 :
11379 TG3_NVRAM_SIZE_128KB);
11380 break;
11381 case FLASH_5752VENDOR_ST_M45PE10:
11382 case FLASH_5752VENDOR_ST_M45PE20:
11383 case FLASH_5752VENDOR_ST_M45PE40:
11384 tp->nvram_jedecnum = JEDEC_ST;
11385 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11386 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11387 tp->nvram_pagesize = 256;
11388 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11389 tp->nvram_size = (protect ?
11390 TG3_NVRAM_SIZE_64KB :
11391 TG3_NVRAM_SIZE_128KB);
11392 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11393 tp->nvram_size = (protect ?
11394 TG3_NVRAM_SIZE_64KB :
11395 TG3_NVRAM_SIZE_256KB);
11396 else
11397 tp->nvram_size = (protect ?
11398 TG3_NVRAM_SIZE_128KB :
11399 TG3_NVRAM_SIZE_512KB);
11400 break;
d3c7b886
MC		 11401 }
11402}
11403
1b27777a
MC		 11404static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11405{
11406 u32 nvcfg1;
11407
11408 nvcfg1 = tr32(NVRAM_CFG1);
11409
11410 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11411 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11412 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11413 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11414 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11415 tp->nvram_jedecnum = JEDEC_ATMEL;
11416 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11417 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11418
8590a603
MC		 11419 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11420 tw32(NVRAM_CFG1, nvcfg1);
11421 break;
11422 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11423 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11424 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11425 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11426 tp->nvram_jedecnum = JEDEC_ATMEL;
11427 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11428 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11429 tp->nvram_pagesize = 264;
11430 break;
11431 case FLASH_5752VENDOR_ST_M45PE10:
11432 case FLASH_5752VENDOR_ST_M45PE20:
11433 case FLASH_5752VENDOR_ST_M45PE40:
11434 tp->nvram_jedecnum = JEDEC_ST;
11435 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11436 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11437 tp->nvram_pagesize = 256;
11438 break;
1b27777a
MC		 11439 }
11440}
11441
6b91fa02
MC		 11442static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11443{
11444 u32 nvcfg1, protect = 0;
11445
11446 nvcfg1 = tr32(NVRAM_CFG1);
11447
11448 /* NVRAM protection for TPM */
11449 if (nvcfg1 & (1 << 27)) {
f66a29b0 11450 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11451 protect = 1;
11452 }
11453
11454 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11455 switch (nvcfg1) {
8590a603
MC		 11456 case FLASH_5761VENDOR_ATMEL_ADB021D:
11457 case FLASH_5761VENDOR_ATMEL_ADB041D:
11458 case FLASH_5761VENDOR_ATMEL_ADB081D:
11459 case FLASH_5761VENDOR_ATMEL_ADB161D:
11460 case FLASH_5761VENDOR_ATMEL_MDB021D:
11461 case FLASH_5761VENDOR_ATMEL_MDB041D:
11462 case FLASH_5761VENDOR_ATMEL_MDB081D:
11463 case FLASH_5761VENDOR_ATMEL_MDB161D:
11464 tp->nvram_jedecnum = JEDEC_ATMEL;
11465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11466 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11467 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11468 tp->nvram_pagesize = 256;
11469 break;
11470 case FLASH_5761VENDOR_ST_A_M45PE20:
11471 case FLASH_5761VENDOR_ST_A_M45PE40:
11472 case FLASH_5761VENDOR_ST_A_M45PE80:
11473 case FLASH_5761VENDOR_ST_A_M45PE16:
11474 case FLASH_5761VENDOR_ST_M_M45PE20:
11475 case FLASH_5761VENDOR_ST_M_M45PE40:
11476 case FLASH_5761VENDOR_ST_M_M45PE80:
11477 case FLASH_5761VENDOR_ST_M_M45PE16:
11478 tp->nvram_jedecnum = JEDEC_ST;
11479 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11480 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11481 tp->nvram_pagesize = 256;
11482 break;
6b91fa02
MC		 11483 }
11484
11485 if (protect) {
11486 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11487 } else {
11488 switch (nvcfg1) {
8590a603
MC		 11489 case FLASH_5761VENDOR_ATMEL_ADB161D:
11490 case FLASH_5761VENDOR_ATMEL_MDB161D:
11491 case FLASH_5761VENDOR_ST_A_M45PE16:
11492 case FLASH_5761VENDOR_ST_M_M45PE16:
11493 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11494 break;
11495 case FLASH_5761VENDOR_ATMEL_ADB081D:
11496 case FLASH_5761VENDOR_ATMEL_MDB081D:
11497 case FLASH_5761VENDOR_ST_A_M45PE80:
11498 case FLASH_5761VENDOR_ST_M_M45PE80:
11499 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11500 break;
11501 case FLASH_5761VENDOR_ATMEL_ADB041D:
11502 case FLASH_5761VENDOR_ATMEL_MDB041D:
11503 case FLASH_5761VENDOR_ST_A_M45PE40:
11504 case FLASH_5761VENDOR_ST_M_M45PE40:
11505 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11506 break;
11507 case FLASH_5761VENDOR_ATMEL_ADB021D:
11508 case FLASH_5761VENDOR_ATMEL_MDB021D:
11509 case FLASH_5761VENDOR_ST_A_M45PE20:
11510 case FLASH_5761VENDOR_ST_M_M45PE20:
11511 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11512 break;
6b91fa02
MC		 11513 }
11514 }
11515}
11516
b5d3772c
MC		 11517static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11518{
11519 tp->nvram_jedecnum = JEDEC_ATMEL;
11520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11522}
11523
321d32a0
MC		 11524static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11525{
11526 u32 nvcfg1;
11527
11528 nvcfg1 = tr32(NVRAM_CFG1);
11529
11530 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11531 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11532 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11533 tp->nvram_jedecnum = JEDEC_ATMEL;
11534 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11535 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11536
11537 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11538 tw32(NVRAM_CFG1, nvcfg1);
11539 return;
11540 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11541 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11542 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11543 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11544 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11545 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11546 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11547 tp->nvram_jedecnum = JEDEC_ATMEL;
11548 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11549 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11550
11551 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11552 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11553 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11554 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11555 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11556 break;
11557 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11558 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11559 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11560 break;
11561 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11562 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11563 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11564 break;
11565 }
11566 break;
11567 case FLASH_5752VENDOR_ST_M45PE10:
11568 case FLASH_5752VENDOR_ST_M45PE20:
11569 case FLASH_5752VENDOR_ST_M45PE40:
11570 tp->nvram_jedecnum = JEDEC_ST;
11571 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11572 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11573
11574 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11575 case FLASH_5752VENDOR_ST_M45PE10:
11576 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11577 break;
11578 case FLASH_5752VENDOR_ST_M45PE20:
11579 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11580 break;
11581 case FLASH_5752VENDOR_ST_M45PE40:
11582 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11583 break;
11584 }
11585 break;
11586 default:
df259d8c 11587 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11588 return;
11589 }
11590
a1b950d5
MC		 11591 tg3_nvram_get_pagesize(tp, nvcfg1);
11592 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11593 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11594}
11595
11596
11597static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11598{
11599 u32 nvcfg1;
11600
11601 nvcfg1 = tr32(NVRAM_CFG1);
11602
11603 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11604 case FLASH_5717VENDOR_ATMEL_EEPROM:
11605 case FLASH_5717VENDOR_MICRO_EEPROM:
11606 tp->nvram_jedecnum = JEDEC_ATMEL;
11607 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11608 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11609
11610 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11611 tw32(NVRAM_CFG1, nvcfg1);
11612 return;
11613 case FLASH_5717VENDOR_ATMEL_MDB011D:
11614 case FLASH_5717VENDOR_ATMEL_ADB011B:
11615 case FLASH_5717VENDOR_ATMEL_ADB011D:
11616 case FLASH_5717VENDOR_ATMEL_MDB021D:
11617 case FLASH_5717VENDOR_ATMEL_ADB021B:
11618 case FLASH_5717VENDOR_ATMEL_ADB021D:
11619 case FLASH_5717VENDOR_ATMEL_45USPT:
11620 tp->nvram_jedecnum = JEDEC_ATMEL;
11621 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11622 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11623
11624 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11625 case FLASH_5717VENDOR_ATMEL_MDB021D:
11626 case FLASH_5717VENDOR_ATMEL_ADB021B:
11627 case FLASH_5717VENDOR_ATMEL_ADB021D:
11628 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11629 break;
11630 default:
11631 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11632 break;
11633 }
321d32a0 11634 break;
a1b950d5
MC		 11635 case FLASH_5717VENDOR_ST_M_M25PE10:
11636 case FLASH_5717VENDOR_ST_A_M25PE10:
11637 case FLASH_5717VENDOR_ST_M_M45PE10:
11638 case FLASH_5717VENDOR_ST_A_M45PE10:
11639 case FLASH_5717VENDOR_ST_M_M25PE20:
11640 case FLASH_5717VENDOR_ST_A_M25PE20:
11641 case FLASH_5717VENDOR_ST_M_M45PE20:
11642 case FLASH_5717VENDOR_ST_A_M45PE20:
11643 case FLASH_5717VENDOR_ST_25USPT:
11644 case FLASH_5717VENDOR_ST_45USPT:
11645 tp->nvram_jedecnum = JEDEC_ST;
11646 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11647 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11648
11649 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11650 case FLASH_5717VENDOR_ST_M_M25PE20:
11651 case FLASH_5717VENDOR_ST_A_M25PE20:
11652 case FLASH_5717VENDOR_ST_M_M45PE20:
11653 case FLASH_5717VENDOR_ST_A_M45PE20:
11654 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11655 break;
11656 default:
11657 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11658 break;
11659 }
321d32a0 11660 break;
a1b950d5
MC		 11661 default:
11662 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11663 return;
321d32a0 11664 }
a1b950d5
MC		 11665
11666 tg3_nvram_get_pagesize(tp, nvcfg1);
11667 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11668 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11669}
11670
1da177e4
LT		 11671/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11672static void __devinit tg3_nvram_init(struct tg3 *tp)
11673{
1da177e4
LT		 11674 tw32_f(GRC_EEPROM_ADDR,
11675 (EEPROM_ADDR_FSM_RESET |
11676 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11677 EEPROM_ADDR_CLKPERD_SHIFT)));
11678
9d57f01c 11679 msleep(1);
1da177e4
LT		 11680
11681 /* Enable seeprom accesses. */
11682 tw32_f(GRC_LOCAL_CTRL,
11683 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11684 udelay(100);
11685
11686 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11687 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11688 tp->tg3_flags |= TG3_FLAG_NVRAM;
11689
ec41c7df
MC		 11690 if (tg3_nvram_lock(tp)) {
11691 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11692 "tg3_nvram_init failed.\n", tp->dev->name);
11693 return;
11694 }
e6af301b 11695 tg3_enable_nvram_access(tp);
1da177e4 11696
989a9d23
MC		 11697 tp->nvram_size = 0;
11698
361b4ac2
MC		 11699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11700 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11701 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11702 tg3_get_5755_nvram_info(tp);
d30cdd28 11703 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11706 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11707 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11708 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11709 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11710 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11711 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11712 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11713 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11714 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11715 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11716 else
11717 tg3_get_nvram_info(tp);
11718
989a9d23
MC		 11719 if (tp->nvram_size == 0)
11720 tg3_get_nvram_size(tp);
1da177e4 11721
e6af301b 11722 tg3_disable_nvram_access(tp);
381291b7 11723 tg3_nvram_unlock(tp);
1da177e4
LT		 11724
11725 } else {
11726 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11727
11728 tg3_get_eeprom_size(tp);
11729 }
11730}
11731
1da177e4
LT		 11732static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11733 u32 offset, u32 len, u8 *buf)
11734{
11735 int i, j, rc = 0;
11736 u32 val;
11737
11738 for (i = 0; i < len; i += 4) {
b9fc7dc5 11739 u32 addr;
a9dc529d 11740 __be32 data;
1da177e4
LT		 11741
11742 addr = offset + i;
11743
11744 memcpy(&data, buf + i, 4);
11745
62cedd11
MC		 11746 /*
11747 * The SEEPROM interface expects the data to always be opposite
11748 * the native endian format. We accomplish this by reversing
11749 * all the operations that would have been performed on the
11750 * data from a call to tg3_nvram_read_be32().
11751 */
11752 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11753
11754 val = tr32(GRC_EEPROM_ADDR);
11755 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11756
11757 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11758 EEPROM_ADDR_READ);
11759 tw32(GRC_EEPROM_ADDR, val |
11760 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11761 (addr & EEPROM_ADDR_ADDR_MASK) |
11762 EEPROM_ADDR_START |
11763 EEPROM_ADDR_WRITE);
6aa20a22 11764
9d57f01c 11765 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11766 val = tr32(GRC_EEPROM_ADDR);
11767
11768 if (val & EEPROM_ADDR_COMPLETE)
11769 break;
9d57f01c 11770 msleep(1);
1da177e4
LT		 11771 }
11772 if (!(val & EEPROM_ADDR_COMPLETE)) {
11773 rc = -EBUSY;
11774 break;
11775 }
11776 }
11777
11778 return rc;
11779}
11780
11781/* offset and length are dword aligned */
11782static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11783 u8 *buf)
11784{
11785 int ret = 0;
11786 u32 pagesize = tp->nvram_pagesize;
11787 u32 pagemask = pagesize - 1;
11788 u32 nvram_cmd;
11789 u8 *tmp;
11790
11791 tmp = kmalloc(pagesize, GFP_KERNEL);
11792 if (tmp == NULL)
11793 return -ENOMEM;
11794
11795 while (len) {
11796 int j;
e6af301b 11797 u32 phy_addr, page_off, size;
1da177e4
LT		 11798
11799 phy_addr = offset & ~pagemask;
6aa20a22 11800
1da177e4 11801 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11802 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11803 (__be32 *) (tmp + j));
11804 if (ret)
1da177e4
LT		 11805 break;
11806 }
11807 if (ret)
11808 break;
11809
11810 page_off = offset & pagemask;
11811 size = pagesize;
11812 if (len < size)
11813 size = len;
11814
11815 len -= size;
11816
11817 memcpy(tmp + page_off, buf, size);
11818
11819 offset = offset + (pagesize - page_off);
11820
e6af301b 11821 tg3_enable_nvram_access(tp);
1da177e4
LT		 11822
11823 /*
11824 * Before we can erase the flash page, we need
11825 * to issue a special "write enable" command.
11826 */
11827 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11828
11829 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11830 break;
11831
11832 /* Erase the target page */
11833 tw32(NVRAM_ADDR, phy_addr);
11834
11835 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11836 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11837
11838 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11839 break;
11840
11841 /* Issue another write enable to start the write. */
11842 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11843
11844 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11845 break;
11846
11847 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11848 __be32 data;
1da177e4 11849
b9fc7dc5 11850 data = *((__be32 *) (tmp + j));
a9dc529d 11851
b9fc7dc5 11852 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11853
11854 tw32(NVRAM_ADDR, phy_addr + j);
11855
11856 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11857 NVRAM_CMD_WR;
11858
11859 if (j == 0)
11860 nvram_cmd |= NVRAM_CMD_FIRST;
11861 else if (j == (pagesize - 4))
11862 nvram_cmd |= NVRAM_CMD_LAST;
11863
11864 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11865 break;
11866 }
11867 if (ret)
11868 break;
11869 }
11870
11871 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11872 tg3_nvram_exec_cmd(tp, nvram_cmd);
11873
11874 kfree(tmp);
11875
11876 return ret;
11877}
11878
11879/* offset and length are dword aligned */
11880static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11881 u8 *buf)
11882{
11883 int i, ret = 0;
11884
11885 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11886 u32 page_off, phy_addr, nvram_cmd;
11887 __be32 data;
1da177e4
LT		 11888
11889 memcpy(&data, buf + i, 4);
b9fc7dc5 11890 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11891
11892 page_off = offset % tp->nvram_pagesize;
11893
1820180b 11894 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11895
11896 tw32(NVRAM_ADDR, phy_addr);
11897
11898 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11899
11900 if ((page_off == 0) || (i == 0))
11901 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11902 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11903 nvram_cmd |= NVRAM_CMD_LAST;
11904
11905 if (i == (len - 4))
11906 nvram_cmd |= NVRAM_CMD_LAST;
11907
321d32a0
MC		 11908 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11909 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11910 (tp->nvram_jedecnum == JEDEC_ST) &&
11911 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11912
11913 if ((ret = tg3_nvram_exec_cmd(tp,
11914 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11915 NVRAM_CMD_DONE)))
11916
11917 break;
11918 }
11919 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11920 /* We always do complete word writes to eeprom. */
11921 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11922 }
11923
11924 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11925 break;
11926 }
11927 return ret;
11928}
11929
11930/* offset and length are dword aligned */
11931static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11932{
11933 int ret;
11934
1da177e4 11935 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11936 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11937 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11938 udelay(40);
11939 }
11940
11941 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11942 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11943 }
11944 else {
11945 u32 grc_mode;
11946
ec41c7df
MC		 11947 ret = tg3_nvram_lock(tp);
11948 if (ret)
11949 return ret;
1da177e4 11950
e6af301b
MC		 11951 tg3_enable_nvram_access(tp);
11952 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11953 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11954 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11955
11956 grc_mode = tr32(GRC_MODE);
11957 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11958
11959 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11960 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11961
11962 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11963 buf);
11964 }
11965 else {
11966 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11967 buf);
11968 }
11969
11970 grc_mode = tr32(GRC_MODE);
11971 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11972
e6af301b 11973 tg3_disable_nvram_access(tp);
1da177e4
LT		 11974 tg3_nvram_unlock(tp);
11975 }
11976
11977 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11978 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11979 udelay(40);
11980 }
11981
11982 return ret;
11983}
11984
11985struct subsys_tbl_ent {
11986 u16 subsys_vendor, subsys_devid;
11987 u32 phy_id;
11988};
11989
11990static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11991 /* Broadcom boards. */
11992 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11993 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11994 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11995 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11996 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11997 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11998 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11999 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12000 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12001 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12002 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12003
12004 /* 3com boards. */
12005 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12006 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12007 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12008 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12009 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12010
12011 /* DELL boards. */
12012 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12013 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12014 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12015 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12016
12017 /* Compaq boards. */
12018 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12019 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12020 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12021 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12022 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12023
12024 /* IBM boards. */
12025 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12026};
12027
12028static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12029{
12030 int i;
12031
12032 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12033 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12034 tp->pdev->subsystem_vendor) &&
12035 (subsys_id_to_phy_id[i].subsys_devid ==
12036 tp->pdev->subsystem_device))
12037 return &subsys_id_to_phy_id[i];
12038 }
12039 return NULL;
12040}
12041
7d0c41ef 12042static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12043{
1da177e4 12044 u32 val;
caf636c7
MC		 12045 u16 pmcsr;
12046
12047 /* On some early chips the SRAM cannot be accessed in D3hot state,
12048 * so need make sure we're in D0.
12049 */
12050 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12051 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12052 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12053 msleep(1);
7d0c41ef
MC		 12054
12055 /* Make sure register accesses (indirect or otherwise)
12056 * will function correctly.
12057 */
12058 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12059 tp->misc_host_ctrl);
1da177e4 12060
f49639e6
DM		 12061 /* The memory arbiter has to be enabled in order for SRAM accesses
12062 * to succeed. Normally on powerup the tg3 chip firmware will make
12063 * sure it is enabled, but other entities such as system netboot
12064 * code might disable it.
12065 */
12066 val = tr32(MEMARB_MODE);
12067 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12068
1da177e4 12069 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12070 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12071
a85feb8c
GZ		 12072 /* Assume an onboard device and WOL capable by default. */
12073 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12074
b5d3772c 12075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12076 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12077 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12078 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12079 }
0527ba35
MC		 12080 val = tr32(VCPU_CFGSHDW);
12081 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12082 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12083 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12084 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12085 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12086 goto done;
b5d3772c
MC		 12087 }
12088
1da177e4
LT		 12089 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12090 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12091 u32 nic_cfg, led_cfg;
a9daf367 12092 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12093 int eeprom_phy_serdes = 0;
1da177e4
LT		 12094
12095 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12096 tp->nic_sram_data_cfg = nic_cfg;
12097
12098 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12099 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12100 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12101 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12102 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12103 (ver > 0) && (ver < 0x100))
12104 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12105
a9daf367
MC		 12106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12107 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12108
1da177e4
LT		 12109 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12110 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12111 eeprom_phy_serdes = 1;
12112
12113 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12114 if (nic_phy_id != 0) {
12115 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12116 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12117
12118 eeprom_phy_id = (id1 >> 16) << 10;
12119 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12120 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12121 } else
12122 eeprom_phy_id = 0;
12123
7d0c41ef 12124 tp->phy_id = eeprom_phy_id;
747e8f8b 12125 if (eeprom_phy_serdes) {
a4e2b347 12126 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 12127 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12128 else
12129 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12130 }
7d0c41ef 12131
cbf46853 12132 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12133 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12134 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12135 else
1da177e4
LT		 12136 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12137
12138 switch (led_cfg) {
12139 default:
12140 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12141 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12142 break;
12143
12144 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12145 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12146 break;
12147
12148 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12149 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12150
12151 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12152 * read on some older 5700/5701 bootcode.
12153 */
12154 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12155 ASIC_REV_5700 ||
12156 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12157 ASIC_REV_5701)
12158 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12159
1da177e4
LT		 12160 break;
12161
12162 case SHASTA_EXT_LED_SHARED:
12163 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12164 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12165 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12166 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12167 LED_CTRL_MODE_PHY_2);
12168 break;
12169
12170 case SHASTA_EXT_LED_MAC:
12171 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12172 break;
12173
12174 case SHASTA_EXT_LED_COMBO:
12175 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12176 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12177 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12178 LED_CTRL_MODE_PHY_2);
12179 break;
12180
855e1111 12181 }
1da177e4
LT		 12182
12183 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12184 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12185 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12186 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12187
b2a5c19c
MC		 12188 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12189 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12190
9d26e213 12191 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12192 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12193 if ((tp->pdev->subsystem_vendor ==
12194 PCI_VENDOR_ID_ARIMA) &&
12195 (tp->pdev->subsystem_device == 0x205a ||
12196 tp->pdev->subsystem_device == 0x2063))
12197 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12198 } else {
f49639e6 12199 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12200 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12201 }
1da177e4
LT		 12202
12203 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12204 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12205 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12206 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12207 }
b2b98d4a
MC		 12208
12209 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12210 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12211 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12212
a85feb8c
GZ		 12213 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12214 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12215 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12216
12dac075 12217 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12218 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12219 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12220
1da177e4
LT		 12221 if (cfg2 & (1 << 17))
12222 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12223
12224 /* serdes signal pre-emphasis in register 0x590 set by */
12225 /* bootcode if bit 18 is set */
12226 if (cfg2 & (1 << 18))
12227 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12228
321d32a0
MC		 12229 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12230 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12231 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12232 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12233
8ed5d97e
MC		 12234 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12235 u32 cfg3;
12236
12237 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12238 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12239 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12240 }
a9daf367
MC		 12241
12242 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12243 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12244 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12245 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12246 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12247 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12248 }
05ac4cb7
MC		 12249done:
12250 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12251 device_set_wakeup_enable(&tp->pdev->dev,
12252 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12253}
12254
b2a5c19c
MC		 12255static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12256{
12257 int i;
12258 u32 val;
12259
12260 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12261 tw32(OTP_CTRL, cmd);
12262
12263 /* Wait for up to 1 ms for command to execute. */
12264 for (i = 0; i < 100; i++) {
12265 val = tr32(OTP_STATUS);
12266 if (val & OTP_STATUS_CMD_DONE)
12267 break;
12268 udelay(10);
12269 }
12270
12271 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12272}
12273
12274/* Read the gphy configuration from the OTP region of the chip. The gphy
12275 * configuration is a 32-bit value that straddles the alignment boundary.
12276 * We do two 32-bit reads and then shift and merge the results.
12277 */
12278static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12279{
12280 u32 bhalf_otp, thalf_otp;
12281
12282 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12283
12284 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12285 return 0;
12286
12287 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12288
12289 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12290 return 0;
12291
12292 thalf_otp = tr32(OTP_READ_DATA);
12293
12294 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12295
12296 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12297 return 0;
12298
12299 bhalf_otp = tr32(OTP_READ_DATA);
12300
12301 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12302}
12303
7d0c41ef
MC		 12304static int __devinit tg3_phy_probe(struct tg3 *tp)
12305{
12306 u32 hw_phy_id_1, hw_phy_id_2;
12307 u32 hw_phy_id, hw_phy_id_masked;
12308 int err;
1da177e4 12309
b02fd9e3
MC		 12310 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12311 return tg3_phy_init(tp);
12312
1da177e4 12313 /* Reading the PHY ID register can conflict with ASF
877d0310 12314 * firmware access to the PHY hardware.
1da177e4
LT		 12315 */
12316 err = 0;
0d3031d9
MC		 12317 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12318 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12319 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12320 } else {
12321 /* Now read the physical PHY_ID from the chip and verify
12322 * that it is sane. If it doesn't look good, we fall back
12323 * to either the hard-coded table based PHY_ID and failing
12324 * that the value found in the eeprom area.
12325 */
12326 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12327 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12328
12329 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12330 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12331 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12332
12333 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12334 }
12335
12336 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12337 tp->phy_id = hw_phy_id;
12338 if (hw_phy_id_masked == PHY_ID_BCM8002)
12339 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12340 else
12341 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12342 } else {
7d0c41ef
MC		 12343 if (tp->phy_id != PHY_ID_INVALID) {
12344 /* Do nothing, phy ID already set up in
12345 * tg3_get_eeprom_hw_cfg().
12346 */
1da177e4
LT		 12347 } else {
12348 struct subsys_tbl_ent *p;
12349
12350 /* No eeprom signature? Try the hardcoded
12351 * subsys device table.
12352 */
12353 p = lookup_by_subsys(tp);
12354 if (!p)
12355 return -ENODEV;
12356
12357 tp->phy_id = p->phy_id;
12358 if (!tp->phy_id ||
12359 tp->phy_id == PHY_ID_BCM8002)
12360 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12361 }
12362 }
12363
747e8f8b 12364 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12365 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12366 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12367 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12368
12369 tg3_readphy(tp, MII_BMSR, &bmsr);
12370 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12371 (bmsr & BMSR_LSTATUS))
12372 goto skip_phy_reset;
6aa20a22 12373
1da177e4
LT		 12374 err = tg3_phy_reset(tp);
12375 if (err)
12376 return err;
12377
12378 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12379 ADVERTISE_100HALF | ADVERTISE_100FULL |
12380 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12381 tg3_ctrl = 0;
12382 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12383 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12384 MII_TG3_CTRL_ADV_1000_FULL);
12385 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12386 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12387 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12388 MII_TG3_CTRL_ENABLE_AS_MASTER);
12389 }
12390
3600d918
MC		 12391 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12392 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12393 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12394 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12395 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12396
12397 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12398 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12399
12400 tg3_writephy(tp, MII_BMCR,
12401 BMCR_ANENABLE | BMCR_ANRESTART);
12402 }
12403 tg3_phy_set_wirespeed(tp);
12404
12405 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12406 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12407 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12408 }
12409
12410skip_phy_reset:
12411 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12412 err = tg3_init_5401phy_dsp(tp);
12413 if (err)
12414 return err;
12415 }
12416
12417 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12418 err = tg3_init_5401phy_dsp(tp);
12419 }
12420
747e8f8b 12421 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12422 tp->link_config.advertising =
12423 (ADVERTISED_1000baseT_Half |
12424 ADVERTISED_1000baseT_Full |
12425 ADVERTISED_Autoneg |
12426 ADVERTISED_FIBRE);
12427 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12428 tp->link_config.advertising &=
12429 ~(ADVERTISED_1000baseT_Half |
12430 ADVERTISED_1000baseT_Full);
12431
12432 return err;
12433}
12434
12435static void __devinit tg3_read_partno(struct tg3 *tp)
12436{
141518c9 12437 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12438 unsigned int i;
1b27777a 12439 u32 magic;
1da177e4 12440
df259d8c
MC		 12441 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12442 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12443 goto out_not_found;
1da177e4 12444
1820180b 12445 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12446 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12447 u32 tmp;
1da177e4 12448
6d348f2c
MC		 12449 /* The data is in little-endian format in NVRAM.
12450 * Use the big-endian read routines to preserve
12451 * the byte order as it exists in NVRAM.
12452 */
141518c9 12453 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12454 goto out_not_found;
12455
6d348f2c 12456 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12457 }
12458 } else {
94c982bd
MC		 12459 ssize_t cnt;
12460 unsigned int pos = 0, i = 0;
12461
12462 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12463 cnt = pci_read_vpd(tp->pdev, pos,
12464 TG3_NVM_VPD_LEN - pos,
12465 &vpd_data[pos]);
12466 if (cnt == -ETIMEDOUT || -EINTR)
12467 cnt = 0;
12468 else if (cnt < 0)
f49639e6 12469 goto out_not_found;
1b27777a 12470 }
94c982bd
MC		 12471 if (pos != TG3_NVM_VPD_LEN)
12472 goto out_not_found;
1da177e4
LT		 12473 }
12474
12475 /* Now parse and find the part number. */
141518c9 12476 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12477 unsigned char val = vpd_data[i];
af2c6a4a 12478 unsigned int block_end;
1da177e4
LT		 12479
12480 if (val == 0x82 || val == 0x91) {
12481 i = (i + 3 +
12482 (vpd_data[i + 1] +
12483 (vpd_data[i + 2] << 8)));
12484 continue;
12485 }
12486
12487 if (val != 0x90)
12488 goto out_not_found;
12489
12490 block_end = (i + 3 +
12491 (vpd_data[i + 1] +
12492 (vpd_data[i + 2] << 8)));
12493 i += 3;
af2c6a4a 12494
141518c9 12495 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12496 goto out_not_found;
12497
12498 while (i < (block_end - 2)) {
1da177e4
LT		 12499 if (vpd_data[i + 0] == 'P' &&
12500 vpd_data[i + 1] == 'N') {
12501 int partno_len = vpd_data[i + 2];
12502
af2c6a4a 12503 i += 3;
141518c9
MC		 12504 if (partno_len > TG3_BPN_SIZE ||
12505 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12506 goto out_not_found;
12507
12508 memcpy(tp->board_part_number,
af2c6a4a 12509 &vpd_data[i], partno_len);
1da177e4
LT		 12510
12511 /* Success. */
12512 return;
12513 }
af2c6a4a 12514 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12515 }
12516
12517 /* Part number not found. */
12518 goto out_not_found;
12519 }
12520
12521out_not_found:
b5d3772c
MC		 12522 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12523 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12524 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12525 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12526 strcpy(tp->board_part_number, "BCM57780");
12527 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12528 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12529 strcpy(tp->board_part_number, "BCM57760");
12530 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12531 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12532 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12533 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12534 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12535 strcpy(tp->board_part_number, "BCM57788");
b703df6f
MC		 12536 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12537 strcpy(tp->board_part_number, "BCM57765");
b5d3772c
MC		 12538 else
12539 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12540}
12541
9c8a620e
MC		 12542static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12543{
12544 u32 val;
12545
e4f34110 12546 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12547 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12548 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12549 val != 0)
12550 return 0;
12551
12552 return 1;
12553}
12554
acd9c119
MC		 12555static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12556{
ff3a7cb2 12557 u32 val, offset, start, ver_offset;
acd9c119 12558 int i;
ff3a7cb2 12559 bool newver = false;
acd9c119
MC		 12560
12561 if (tg3_nvram_read(tp, 0xc, &offset) ||
12562 tg3_nvram_read(tp, 0x4, &start))
12563 return;
12564
12565 offset = tg3_nvram_logical_addr(tp, offset);
12566
ff3a7cb2 12567 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12568 return;
12569
ff3a7cb2
MC		 12570 if ((val & 0xfc000000) == 0x0c000000) {
12571 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12572 return;
12573
ff3a7cb2
MC		 12574 if (val == 0)
12575 newver = true;
12576 }
12577
12578 if (newver) {
12579 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12580 return;
12581
12582 offset = offset + ver_offset - start;
12583 for (i = 0; i < 16; i += 4) {
12584 __be32 v;
12585 if (tg3_nvram_read_be32(tp, offset + i, &v))
12586 return;
12587
12588 memcpy(tp->fw_ver + i, &v, sizeof(v));
12589 }
12590 } else {
12591 u32 major, minor;
12592
12593 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12594 return;
12595
12596 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12597 TG3_NVM_BCVER_MAJSFT;
12598 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12599 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12600 }
12601}
12602
a6f6cb1c
MC		 12603static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12604{
12605 u32 val, major, minor;
12606
12607 /* Use native endian representation */
12608 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12609 return;
12610
12611 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12612 TG3_NVM_HWSB_CFG1_MAJSFT;
12613 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12614 TG3_NVM_HWSB_CFG1_MINSFT;
12615
12616 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12617}
12618
dfe00d7d
MC		 12619static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12620{
12621 u32 offset, major, minor, build;
12622
12623 tp->fw_ver[0] = 's';
12624 tp->fw_ver[1] = 'b';
12625 tp->fw_ver[2] = '\0';
12626
12627 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12628 return;
12629
12630 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12631 case TG3_EEPROM_SB_REVISION_0:
12632 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12633 break;
12634 case TG3_EEPROM_SB_REVISION_2:
12635 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12636 break;
12637 case TG3_EEPROM_SB_REVISION_3:
12638 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12639 break;
12640 default:
12641 return;
12642 }
12643
e4f34110 12644 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12645 return;
12646
12647 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12648 TG3_EEPROM_SB_EDH_BLD_SHFT;
12649 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12650 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12651 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12652
12653 if (minor > 99 || build > 26)
12654 return;
12655
12656 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12657
12658 if (build > 0) {
12659 tp->fw_ver[8] = 'a' + build - 1;
12660 tp->fw_ver[9] = '\0';
12661 }
12662}
12663
acd9c119 12664static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12665{
12666 u32 val, offset, start;
acd9c119 12667 int i, vlen;
9c8a620e
MC		 12668
12669 for (offset = TG3_NVM_DIR_START;
12670 offset < TG3_NVM_DIR_END;
12671 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12672 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12673 return;
12674
9c8a620e
MC		 12675 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12676 break;
12677 }
12678
12679 if (offset == TG3_NVM_DIR_END)
12680 return;
12681
12682 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12683 start = 0x08000000;
e4f34110 12684 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12685 return;
12686
e4f34110 12687 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12688 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12689 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12690 return;
12691
12692 offset += val - start;
12693
acd9c119 12694 vlen = strlen(tp->fw_ver);
9c8a620e 12695
acd9c119
MC		 12696 tp->fw_ver[vlen++] = ',';
12697 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12698
12699 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12700 __be32 v;
12701 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12702 return;
12703
b9fc7dc5 12704 offset += sizeof(v);
c4e6575c 12705
acd9c119
MC		 12706 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12707 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12708 break;
c4e6575c 12709 }
9c8a620e 12710
acd9c119
MC		 12711 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12712 vlen += sizeof(v);
c4e6575c 12713 }
acd9c119
MC		 12714}
12715
7fd76445
MC		 12716static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12717{
12718 int vlen;
12719 u32 apedata;
12720
12721 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12722 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12723 return;
12724
12725 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12726 if (apedata != APE_SEG_SIG_MAGIC)
12727 return;
12728
12729 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12730 if (!(apedata & APE_FW_STATUS_READY))
12731 return;
12732
12733 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12734
12735 vlen = strlen(tp->fw_ver);
12736
12737 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12738 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12739 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12740 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12741 (apedata & APE_FW_VERSION_BLDMSK));
12742}
12743
acd9c119
MC		 12744static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12745{
12746 u32 val;
12747
df259d8c
MC		 12748 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12749 tp->fw_ver[0] = 's';
12750 tp->fw_ver[1] = 'b';
12751 tp->fw_ver[2] = '\0';
12752
12753 return;
12754 }
12755
acd9c119
MC		 12756 if (tg3_nvram_read(tp, 0, &val))
12757 return;
12758
12759 if (val == TG3_EEPROM_MAGIC)
12760 tg3_read_bc_ver(tp);
12761 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12762 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12763 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12764 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12765 else
12766 return;
12767
12768 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12769 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12770 return;
12771
12772 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12773
12774 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12775}
12776
7544b097
MC		 12777static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12778
1da177e4
LT		 12779static int __devinit tg3_get_invariants(struct tg3 *tp)
12780{
12781 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12782 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12783 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12784 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12785 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12786 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12787 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12788 { },
12789 };
12790 u32 misc_ctrl_reg;
1da177e4
LT		 12791 u32 pci_state_reg, grc_misc_cfg;
12792 u32 val;
12793 u16 pci_cmd;
5e7dfd0f 12794 int err;
1da177e4 12795
1da177e4
LT		 12796 /* Force memory write invalidate off. If we leave it on,
12797 * then on 5700_BX chips we have to enable a workaround.
12798 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12799 * to match the cacheline size. The Broadcom driver have this
12800 * workaround but turns MWI off all the times so never uses
12801 * it. This seems to suggest that the workaround is insufficient.
12802 */
12803 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12804 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12805 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12806
12807 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12808 * has the register indirect write enable bit set before
12809 * we try to access any of the MMIO registers. It is also
12810 * critical that the PCI-X hw workaround situation is decided
12811 * before that as well.
12812 */
12813 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12814 &misc_ctrl_reg);
12815
12816 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12817 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12819 u32 prod_id_asic_rev;
12820
5001e2f6
MC		 12821 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12822 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12823 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12824 pci_read_config_dword(tp->pdev,
12825 TG3PCI_GEN2_PRODID_ASICREV,
12826 &prod_id_asic_rev);
b703df6f
MC		 12827 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12828 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12829 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12830 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12831 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12832 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12833 pci_read_config_dword(tp->pdev,
12834 TG3PCI_GEN15_PRODID_ASICREV,
12835 &prod_id_asic_rev);
f6eb9b1f
MC		 12836 else
12837 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12838 &prod_id_asic_rev);
12839
321d32a0 12840 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12841 }
1da177e4 12842
ff645bec
MC		 12843 /* Wrong chip ID in 5752 A0. This code can be removed later
12844 * as A0 is not in production.
12845 */
12846 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12847 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12848
6892914f
MC		 12849 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12850 * we need to disable memory and use config. cycles
12851 * only to access all registers. The 5702/03 chips
12852 * can mistakenly decode the special cycles from the
12853 * ICH chipsets as memory write cycles, causing corruption
12854 * of register and memory space. Only certain ICH bridges
12855 * will drive special cycles with non-zero data during the
12856 * address phase which can fall within the 5703's address
12857 * range. This is not an ICH bug as the PCI spec allows
12858 * non-zero address during special cycles. However, only
12859 * these ICH bridges are known to drive non-zero addresses
12860 * during special cycles.
12861 *
12862 * Since special cycles do not cross PCI bridges, we only
12863 * enable this workaround if the 5703 is on the secondary
12864 * bus of these ICH bridges.
12865 */
12866 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12867 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12868 static struct tg3_dev_id {
12869 u32 vendor;
12870 u32 device;
12871 u32 rev;
12872 } ich_chipsets[] = {
12873 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12874 PCI_ANY_ID },
12875 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12876 PCI_ANY_ID },
12877 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12878 0xa },
12879 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12880 PCI_ANY_ID },
12881 { },
12882 };
12883 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12884 struct pci_dev *bridge = NULL;
12885
12886 while (pci_id->vendor != 0) {
12887 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12888 bridge);
12889 if (!bridge) {
12890 pci_id++;
12891 continue;
12892 }
12893 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12894 if (bridge->revision > pci_id->rev)
6892914f
MC		 12895 continue;
12896 }
12897 if (bridge->subordinate &&
12898 (bridge->subordinate->number ==
12899 tp->pdev->bus->number)) {
12900
12901 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12902 pci_dev_put(bridge);
12903 break;
12904 }
12905 }
12906 }
12907
41588ba1
MC		 12908 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12909 static struct tg3_dev_id {
12910 u32 vendor;
12911 u32 device;
12912 } bridge_chipsets[] = {
12913 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12914 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12915 { },
12916 };
12917 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12918 struct pci_dev *bridge = NULL;
12919
12920 while (pci_id->vendor != 0) {
12921 bridge = pci_get_device(pci_id->vendor,
12922 pci_id->device,
12923 bridge);
12924 if (!bridge) {
12925 pci_id++;
12926 continue;
12927 }
12928 if (bridge->subordinate &&
12929 (bridge->subordinate->number <=
12930 tp->pdev->bus->number) &&
12931 (bridge->subordinate->subordinate >=
12932 tp->pdev->bus->number)) {
12933 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12934 pci_dev_put(bridge);
12935 break;
12936 }
12937 }
12938 }
12939
4a29cc2e
MC		 12940 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12941 * DMA addresses > 40-bit. This bridge may have other additional
12942 * 57xx devices behind it in some 4-port NIC designs for example.
12943 * Any tg3 device found behind the bridge will also need the 40-bit
12944 * DMA workaround.
12945 */
a4e2b347
MC		 12946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12948 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12949 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12950 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12951 }
4a29cc2e
MC		 12952 else {
12953 struct pci_dev *bridge = NULL;
12954
12955 do {
12956 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12957 PCI_DEVICE_ID_SERVERWORKS_EPB,
12958 bridge);
12959 if (bridge && bridge->subordinate &&
12960 (bridge->subordinate->number <=
12961 tp->pdev->bus->number) &&
12962 (bridge->subordinate->subordinate >=
12963 tp->pdev->bus->number)) {
12964 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12965 pci_dev_put(bridge);
12966 break;
12967 }
12968 } while (bridge);
12969 }
4cf78e4f 12970
1da177e4
LT		 12971 /* Initialize misc host control in PCI block. */
12972 tp->misc_host_ctrl |= (misc_ctrl_reg &
12973 MISC_HOST_CTRL_CHIPREV);
12974 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12975 tp->misc_host_ctrl);
12976
f6eb9b1f
MC		 12977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12980 tp->pdev_peer = tg3_find_peer(tp);
12981
321d32a0
MC		 12982 /* Intentionally exclude ASIC_REV_5906 */
12983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 12988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 12989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 12991 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12992
12993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12996 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12997 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12998 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12999
1b440c56
JL		 13000 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13001 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13002 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13003
027455ad
MC		 13004 /* 5700 B0 chips do not support checksumming correctly due
13005 * to hardware bugs.
13006 */
13007 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13008 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13009 else {
13010 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13011 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13012 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13013 tp->dev->features |= NETIF_F_IPV6_CSUM;
13014 }
13015
507399f1 13016 /* Determine TSO capabilities */
b703df6f
MC		 13017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13019 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13020 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13022 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13023 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13024 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13026 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13027 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13028 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13029 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13030 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13031 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13033 tp->fw_needed = FIRMWARE_TG3TSO5;
13034 else
13035 tp->fw_needed = FIRMWARE_TG3TSO;
13036 }
13037
13038 tp->irq_max = 1;
13039
5a6f3074 13040 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13041 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13042 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13043 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13044 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13045 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13046 tp->pdev_peer == tp->pdev))
13047 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13048
321d32a0 13049 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13051 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13052 }
4f125f42 13053
b703df6f
MC		 13054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13056 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13057 tp->irq_max = TG3_IRQ_MAX_VECS;
13058 }
f6eb9b1f 13059 }
0e1406dd 13060
615774fe
MC		 13061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13063 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13064 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13065 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13066 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13067 }
f6eb9b1f 13068
b703df6f
MC		 13069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13071 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13072
f51f3562 13073 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13074 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13075 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13076 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13077
52f4490c
MC		 13078 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13079 &pci_state_reg);
13080
5e7dfd0f
MC		 13081 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13082 if (tp->pcie_cap != 0) {
13083 u16 lnkctl;
13084
1da177e4 13085 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13086
13087 pcie_set_readrq(tp->pdev, 4096);
13088
5e7dfd0f
MC		 13089 pci_read_config_word(tp->pdev,
13090 tp->pcie_cap + PCI_EXP_LNKCTL,
13091 &lnkctl);
13092 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13094 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13097 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13098 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13099 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 13100 }
52f4490c 13101 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13102 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13103 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13104 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13105 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13106 if (!tp->pcix_cap) {
13107 printk(KERN_ERR PFX "Cannot find PCI-X "
13108 "capability, aborting.\n");
13109 return -EIO;
13110 }
13111
13112 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13113 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13114 }
1da177e4 13115
399de50b
MC		 13116 /* If we have an AMD 762 or VIA K8T800 chipset, write
13117 * reordering to the mailbox registers done by the host
13118 * controller can cause major troubles. We read back from
13119 * every mailbox register write to force the writes to be
13120 * posted to the chip in order.
13121 */
13122 if (pci_dev_present(write_reorder_chipsets) &&
13123 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13124 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13125
69fc4053
MC		 13126 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13127 &tp->pci_cacheline_sz);
13128 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13129 &tp->pci_lat_timer);
1da177e4
LT		 13130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13131 tp->pci_lat_timer < 64) {
13132 tp->pci_lat_timer = 64;
69fc4053
MC		 13133 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13134 tp->pci_lat_timer);
1da177e4
LT		 13135 }
13136
52f4490c
MC		 13137 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13138 /* 5700 BX chips need to have their TX producer index
13139 * mailboxes written twice to workaround a bug.
13140 */
13141 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13142
52f4490c 13143 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13144 *
13145 * The workaround is to use indirect register accesses
13146 * for all chip writes not to mailbox registers.
13147 */
52f4490c 13148 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13149 u32 pm_reg;
1da177e4
LT		 13150
13151 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13152
13153 /* The chip can have it's power management PCI config
13154 * space registers clobbered due to this bug.
13155 * So explicitly force the chip into D0 here.
13156 */
9974a356
MC		 13157 pci_read_config_dword(tp->pdev,
13158 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13159 &pm_reg);
13160 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13161 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13162 pci_write_config_dword(tp->pdev,
13163 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13164 pm_reg);
13165
13166 /* Also, force SERR#/PERR# in PCI command. */
13167 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13168 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13169 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13170 }
13171 }
13172
1da177e4
LT		 13173 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13174 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13175 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13176 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13177
13178 /* Chip-specific fixup from Broadcom driver */
13179 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13180 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13181 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13182 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13183 }
13184
1ee582d8 13185 /* Default fast path register access methods */
20094930 13186 tp->read32 = tg3_read32;
1ee582d8 13187 tp->write32 = tg3_write32;
09ee929c 13188 tp->read32_mbox = tg3_read32;
20094930 13189 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13190 tp->write32_tx_mbox = tg3_write32;
13191 tp->write32_rx_mbox = tg3_write32;
13192
13193 /* Various workaround register access methods */
13194 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13195 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13196 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13197 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13198 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13199 /*
13200 * Back to back register writes can cause problems on these
13201 * chips, the workaround is to read back all reg writes
13202 * except those to mailbox regs.
13203 *
13204 * See tg3_write_indirect_reg32().
13205 */
1ee582d8 13206 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13207 }
13208
1ee582d8
MC		 13209 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13210 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13211 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13212 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13213 tp->write32_rx_mbox = tg3_write_flush_reg32;
13214 }
20094930 13215
6892914f
MC		 13216 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13217 tp->read32 = tg3_read_indirect_reg32;
13218 tp->write32 = tg3_write_indirect_reg32;
13219 tp->read32_mbox = tg3_read_indirect_mbox;
13220 tp->write32_mbox = tg3_write_indirect_mbox;
13221 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13222 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13223
13224 iounmap(tp->regs);
22abe310 13225 tp->regs = NULL;
6892914f
MC		 13226
13227 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13228 pci_cmd &= ~PCI_COMMAND_MEMORY;
13229 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13230 }
b5d3772c
MC		 13231 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13232 tp->read32_mbox = tg3_read32_mbox_5906;
13233 tp->write32_mbox = tg3_write32_mbox_5906;
13234 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13235 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13236 }
6892914f 13237
bbadf503
MC		 13238 if (tp->write32 == tg3_write_indirect_reg32 ||
13239 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13240 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13242 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13243
7d0c41ef 13244 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13245 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13246 * determined before calling tg3_set_power_state() so that
13247 * we know whether or not to switch out of Vaux power.
13248 * When the flag is set, it means that GPIO1 is used for eeprom
13249 * write protect and also implies that it is a LOM where GPIOs
13250 * are not used to switch power.
6aa20a22 13251 */
7d0c41ef
MC		 13252 tg3_get_eeprom_hw_cfg(tp);
13253
0d3031d9
MC		 13254 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13255 /* Allow reads and writes to the
13256 * APE register and memory space.
13257 */
13258 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13259 PCISTATE_ALLOW_APE_SHMEM_WR;
13260 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13261 pci_state_reg);
13262 }
13263
9936bcf6 13264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13265 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13266 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13268 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13270 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13271
314fba34
MC		 13272 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13273 * GPIO1 driven high will bring 5700's external PHY out of reset.
13274 * It is also used as eeprom write protect on LOMs.
13275 */
13276 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13277 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13278 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13279 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13280 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13281 /* Unused GPIO3 must be driven as output on 5752 because there
13282 * are no pull-up resistors on unused GPIO pins.
13283 */
13284 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13285 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13286
321d32a0
MC		 13287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 13289 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13290
8d519ab2
MC		 13291 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13292 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13293 /* Turn off the debug UART. */
13294 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13295 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13296 /* Keep VMain power. */
13297 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13298 GRC_LCLCTRL_GPIO_OUTPUT0;
13299 }
13300
1da177e4 13301 /* Force the chip into D0. */
bc1c7567 13302 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13303 if (err) {
13304 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13305 pci_name(tp->pdev));
13306 return err;
13307 }
13308
1da177e4
LT		 13309 /* Derive initial jumbo mode from MTU assigned in
13310 * ether_setup() via the alloc_etherdev() call
13311 */
0f893dc6 13312 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13313 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13314 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13315
13316 /* Determine WakeOnLan speed to use. */
13317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13318 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13319 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13320 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13321 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13322 } else {
13323 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13324 }
13325
7f97a4bd
MC		 13326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13327 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13328
1da177e4
LT		 13329 /* A few boards don't want Ethernet@WireSpeed phy feature */
13330 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13331 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13332 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13333 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13334 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13335 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13336 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13337
13338 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13339 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13340 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13341 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13342 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13343
321d32a0 13344 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13345 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13346 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13347 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13348 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13349 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13354 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13355 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13356 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13357 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13358 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13359 } else
c424cb24
MC		 13360 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13361 }
1da177e4 13362
b2a5c19c
MC		 13363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13364 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13365 tp->phy_otp = tg3_read_otp_phycfg(tp);
13366 if (tp->phy_otp == 0)
13367 tp->phy_otp = TG3_OTP_DEFAULT;
13368 }
13369
f51f3562 13370 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13371 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13372 else
13373 tp->mi_mode = MAC_MI_MODE_BASE;
13374
1da177e4 13375 tp->coalesce_mode = 0;
1da177e4
LT		 13376 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13377 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13378 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13379
321d32a0
MC		 13380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13381 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13382 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13383
158d7abd
MC		 13384 err = tg3_mdio_init(tp);
13385 if (err)
13386 return err;
1da177e4
LT		 13387
13388 /* Initialize data/descriptor byte/word swapping. */
13389 val = tr32(GRC_MODE);
13390 val &= GRC_MODE_HOST_STACKUP;
13391 tw32(GRC_MODE, val | tp->grc_mode);
13392
13393 tg3_switch_clocks(tp);
13394
13395 /* Clear this out for sanity. */
13396 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13397
13398 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13399 &pci_state_reg);
13400 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13401 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13402 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13403
13404 if (chiprevid == CHIPREV_ID_5701_A0 ||
13405 chiprevid == CHIPREV_ID_5701_B0 ||
13406 chiprevid == CHIPREV_ID_5701_B2 ||
13407 chiprevid == CHIPREV_ID_5701_B5) {
13408 void __iomem *sram_base;
13409
13410 /* Write some dummy words into the SRAM status block
13411 * area, see if it reads back correctly. If the return
13412 * value is bad, force enable the PCIX workaround.
13413 */
13414 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13415
13416 writel(0x00000000, sram_base);
13417 writel(0x00000000, sram_base + 4);
13418 writel(0xffffffff, sram_base + 4);
13419 if (readl(sram_base) != 0x00000000)
13420 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13421 }
13422 }
13423
13424 udelay(50);
13425 tg3_nvram_init(tp);
13426
13427 grc_misc_cfg = tr32(GRC_MISC_CFG);
13428 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13429
1da177e4
LT		 13430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13431 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13432 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13433 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13434
fac9b83e
DM		 13435 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13436 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13437 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13438 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13439 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13440 HOSTCC_MODE_CLRTICK_TXBD);
13441
13442 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13443 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13444 tp->misc_host_ctrl);
13445 }
13446
3bda1258
MC		 13447 /* Preserve the APE MAC_MODE bits */
13448 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13449 tp->mac_mode = tr32(MAC_MODE) |
13450 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13451 else
13452 tp->mac_mode = TG3_DEF_MAC_MODE;
13453
1da177e4
LT		 13454 /* these are limited to 10/100 only */
13455 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13456 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13457 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13458 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13459 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13460 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13461 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13462 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13463 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13464 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13465 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13466 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13467 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13468 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13469
13470 err = tg3_phy_probe(tp);
13471 if (err) {
13472 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13473 pci_name(tp->pdev), err);
13474 /* ... but do not return immediately ... */
b02fd9e3 13475 tg3_mdio_fini(tp);
1da177e4
LT		 13476 }
13477
13478 tg3_read_partno(tp);
c4e6575c 13479 tg3_read_fw_ver(tp);
1da177e4
LT		 13480
13481 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13482 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13483 } else {
13484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13485 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13486 else
13487 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13488 }
13489
13490 /* 5700 {AX,BX} chips have a broken status block link
13491 * change bit implementation, so we must use the
13492 * status register in those cases.
13493 */
13494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13495 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13496 else
13497 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13498
13499 /* The led_ctrl is set during tg3_phy_probe, here we might
13500 * have to force the link status polling mechanism based
13501 * upon subsystem IDs.
13502 */
13503 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13505 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13506 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13507 TG3_FLAG_USE_LINKCHG_REG);
13508 }
13509
13510 /* For all SERDES we poll the MAC status register. */
13511 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13512 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13513 else
13514 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13515
ad829268 13516 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13518 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13519 tp->rx_offset = 0;
13520
f92905de
MC		 13521 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13522
13523 /* Increment the rx prod index on the rx std ring by at most
13524 * 8 for these chips to workaround hw errata.
13525 */
13526 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13529 tp->rx_std_max_post = 8;
13530
8ed5d97e
MC		 13531 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13532 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13533 PCIE_PWR_MGMT_L1_THRESH_MSK;
13534
1da177e4
LT		 13535 return err;
13536}
13537
49b6e95f 13538#ifdef CONFIG_SPARC
1da177e4
LT		 13539static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13540{
13541 struct net_device *dev = tp->dev;
13542 struct pci_dev *pdev = tp->pdev;
49b6e95f 13543 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13544 const unsigned char *addr;
49b6e95f
DM		 13545 int len;
13546
13547 addr = of_get_property(dp, "local-mac-address", &len);
13548 if (addr && len == 6) {
13549 memcpy(dev->dev_addr, addr, 6);
13550 memcpy(dev->perm_addr, dev->dev_addr, 6);
13551 return 0;
1da177e4
LT		 13552 }
13553 return -ENODEV;
13554}
13555
13556static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13557{
13558 struct net_device *dev = tp->dev;
13559
13560 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13561 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13562 return 0;
13563}
13564#endif
13565
13566static int __devinit tg3_get_device_address(struct tg3 *tp)
13567{
13568 struct net_device *dev = tp->dev;
13569 u32 hi, lo, mac_offset;
008652b3 13570 int addr_ok = 0;
1da177e4 13571
49b6e95f 13572#ifdef CONFIG_SPARC
1da177e4
LT		 13573 if (!tg3_get_macaddr_sparc(tp))
13574 return 0;
13575#endif
13576
13577 mac_offset = 0x7c;
f49639e6 13578 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13579 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13580 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13581 mac_offset = 0xcc;
13582 if (tg3_nvram_lock(tp))
13583 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13584 else
13585 tg3_nvram_unlock(tp);
a1b950d5
MC		 13586 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13587 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13588 mac_offset = 0xcc;
13589 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13590 mac_offset = 0x10;
1da177e4
LT		 13591
13592 /* First try to get it from MAC address mailbox. */
13593 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13594 if ((hi >> 16) == 0x484b) {
13595 dev->dev_addr[0] = (hi >> 8) & 0xff;
13596 dev->dev_addr[1] = (hi >> 0) & 0xff;
13597
13598 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13599 dev->dev_addr[2] = (lo >> 24) & 0xff;
13600 dev->dev_addr[3] = (lo >> 16) & 0xff;
13601 dev->dev_addr[4] = (lo >> 8) & 0xff;
13602 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13603
008652b3
MC		 13604 /* Some old bootcode may report a 0 MAC address in SRAM */
13605 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13606 }
13607 if (!addr_ok) {
13608 /* Next, try NVRAM. */
df259d8c
MC		 13609 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13610 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13611 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13612 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13613 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13614 }
13615 /* Finally just fetch it out of the MAC control regs. */
13616 else {
13617 hi = tr32(MAC_ADDR_0_HIGH);
13618 lo = tr32(MAC_ADDR_0_LOW);
13619
13620 dev->dev_addr[5] = lo & 0xff;
13621 dev->dev_addr[4] = (lo >> 8) & 0xff;
13622 dev->dev_addr[3] = (lo >> 16) & 0xff;
13623 dev->dev_addr[2] = (lo >> 24) & 0xff;
13624 dev->dev_addr[1] = hi & 0xff;
13625 dev->dev_addr[0] = (hi >> 8) & 0xff;
13626 }
1da177e4
LT		 13627 }
13628
13629 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13630#ifdef CONFIG_SPARC
1da177e4
LT		 13631 if (!tg3_get_default_macaddr_sparc(tp))
13632 return 0;
13633#endif
13634 return -EINVAL;
13635 }
2ff43697 13636 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13637 return 0;
13638}
13639
59e6b434
DM		 13640#define BOUNDARY_SINGLE_CACHELINE 1
13641#define BOUNDARY_MULTI_CACHELINE 2
13642
13643static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13644{
13645 int cacheline_size;
13646 u8 byte;
13647 int goal;
13648
13649 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13650 if (byte == 0)
13651 cacheline_size = 1024;
13652 else
13653 cacheline_size = (int) byte * 4;
13654
13655 /* On 5703 and later chips, the boundary bits have no
13656 * effect.
13657 */
13658 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13659 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13660 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13661 goto out;
13662
13663#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13664 goal = BOUNDARY_MULTI_CACHELINE;
13665#else
13666#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13667 goal = BOUNDARY_SINGLE_CACHELINE;
13668#else
13669 goal = 0;
13670#endif
13671#endif
13672
b703df6f
MC		 13673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13675 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13676 goto out;
13677 }
13678
59e6b434
DM		 13679 if (!goal)
13680 goto out;
13681
13682 /* PCI controllers on most RISC systems tend to disconnect
13683 * when a device tries to burst across a cache-line boundary.
13684 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13685 *
13686 * Unfortunately, for PCI-E there are only limited
13687 * write-side controls for this, and thus for reads
13688 * we will still get the disconnects. We'll also waste
13689 * these PCI cycles for both read and write for chips
13690 * other than 5700 and 5701 which do not implement the
13691 * boundary bits.
13692 */
13693 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13694 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13695 switch (cacheline_size) {
13696 case 16:
13697 case 32:
13698 case 64:
13699 case 128:
13700 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13701 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13702 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13703 } else {
13704 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13705 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13706 }
13707 break;
13708
13709 case 256:
13710 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13711 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13712 break;
13713
13714 default:
13715 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13716 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13717 break;
855e1111 13718 }
59e6b434
DM		 13719 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13720 switch (cacheline_size) {
13721 case 16:
13722 case 32:
13723 case 64:
13724 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13725 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13726 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13727 break;
13728 }
13729 /* fallthrough */
13730 case 128:
13731 default:
13732 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13733 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13734 break;
855e1111 13735 }
59e6b434
DM		 13736 } else {
13737 switch (cacheline_size) {
13738 case 16:
13739 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13740 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13741 DMA_RWCTRL_WRITE_BNDRY_16);
13742 break;
13743 }
13744 /* fallthrough */
13745 case 32:
13746 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13747 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13748 DMA_RWCTRL_WRITE_BNDRY_32);
13749 break;
13750 }
13751 /* fallthrough */
13752 case 64:
13753 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13754 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13755 DMA_RWCTRL_WRITE_BNDRY_64);
13756 break;
13757 }
13758 /* fallthrough */
13759 case 128:
13760 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13761 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13762 DMA_RWCTRL_WRITE_BNDRY_128);
13763 break;
13764 }
13765 /* fallthrough */
13766 case 256:
13767 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13768 DMA_RWCTRL_WRITE_BNDRY_256);
13769 break;
13770 case 512:
13771 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13772 DMA_RWCTRL_WRITE_BNDRY_512);
13773 break;
13774 case 1024:
13775 default:
13776 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13777 DMA_RWCTRL_WRITE_BNDRY_1024);
13778 break;
855e1111 13779 }
59e6b434
DM		 13780 }
13781
13782out:
13783 return val;
13784}
13785
1da177e4
LT		 13786static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13787{
13788 struct tg3_internal_buffer_desc test_desc;
13789 u32 sram_dma_descs;
13790 int i, ret;
13791
13792 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13793
13794 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13795 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13796 tw32(RDMAC_STATUS, 0);
13797 tw32(WDMAC_STATUS, 0);
13798
13799 tw32(BUFMGR_MODE, 0);
13800 tw32(FTQ_RESET, 0);
13801
13802 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13803 test_desc.addr_lo = buf_dma & 0xffffffff;
13804 test_desc.nic_mbuf = 0x00002100;
13805 test_desc.len = size;
13806
13807 /*
13808 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13809 * the *second* time the tg3 driver was getting loaded after an
13810 * initial scan.
13811 *
13812 * Broadcom tells me:
13813 * ...the DMA engine is connected to the GRC block and a DMA
13814 * reset may affect the GRC block in some unpredictable way...
13815 * The behavior of resets to individual blocks has not been tested.
13816 *
13817 * Broadcom noted the GRC reset will also reset all sub-components.
13818 */
13819 if (to_device) {
13820 test_desc.cqid_sqid = (13 << 8) | 2;
13821
13822 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13823 udelay(40);
13824 } else {
13825 test_desc.cqid_sqid = (16 << 8) | 7;
13826
13827 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13828 udelay(40);
13829 }
13830 test_desc.flags = 0x00000005;
13831
13832 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13833 u32 val;
13834
13835 val = *(((u32 *)&test_desc) + i);
13836 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13837 sram_dma_descs + (i * sizeof(u32)));
13838 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13839 }
13840 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13841
13842 if (to_device) {
13843 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13844 } else {
13845 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13846 }
13847
13848 ret = -ENODEV;
13849 for (i = 0; i < 40; i++) {
13850 u32 val;
13851
13852 if (to_device)
13853 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13854 else
13855 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13856 if ((val & 0xffff) == sram_dma_descs) {
13857 ret = 0;
13858 break;
13859 }
13860
13861 udelay(100);
13862 }
13863
13864 return ret;
13865}
13866
ded7340d 13867#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13868
13869static int __devinit tg3_test_dma(struct tg3 *tp)
13870{
13871 dma_addr_t buf_dma;
59e6b434 13872 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13873 int ret = 0;
1da177e4
LT		 13874
13875 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13876 if (!buf) {
13877 ret = -ENOMEM;
13878 goto out_nofree;
13879 }
13880
13881 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13882 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13883
59e6b434 13884 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13885
b703df6f
MC		 13886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13888 goto out;
13889
1da177e4
LT		 13890 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13891 /* DMA read watermark not used on PCIE */
13892 tp->dma_rwctrl |= 0x00180000;
13893 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13896 tp->dma_rwctrl |= 0x003f0000;
13897 else
13898 tp->dma_rwctrl |= 0x003f000f;
13899 } else {
13900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13901 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13902 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13903 u32 read_water = 0x7;
1da177e4 13904
4a29cc2e
MC		 13905 /* If the 5704 is behind the EPB bridge, we can
13906 * do the less restrictive ONE_DMA workaround for
13907 * better performance.
13908 */
13909 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13911 tp->dma_rwctrl |= 0x8000;
13912 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13913 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13914
49afdeb6
MC		 13915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13916 read_water = 4;
59e6b434 13917 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13918 tp->dma_rwctrl |=
13919 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13920 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13921 (1 << 23);
4cf78e4f
MC		 13922 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13923 /* 5780 always in PCIX mode */
13924 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13925 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13926 /* 5714 always in PCIX mode */
13927 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13928 } else {
13929 tp->dma_rwctrl |= 0x001b000f;
13930 }
13931 }
13932
13933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13935 tp->dma_rwctrl &= 0xfffffff0;
13936
13937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13939 /* Remove this if it causes problems for some boards. */
13940 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13941
13942 /* On 5700/5701 chips, we need to set this bit.
13943 * Otherwise the chip will issue cacheline transactions
13944 * to streamable DMA memory with not all the byte
13945 * enables turned on. This is an error on several
13946 * RISC PCI controllers, in particular sparc64.
13947 *
13948 * On 5703/5704 chips, this bit has been reassigned
13949 * a different meaning. In particular, it is used
13950 * on those chips to enable a PCI-X workaround.
13951 */
13952 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13953 }
13954
13955 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13956
13957#if 0
13958 /* Unneeded, already done by tg3_get_invariants. */
13959 tg3_switch_clocks(tp);
13960#endif
13961
1da177e4
LT		 13962 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13963 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13964 goto out;
13965
59e6b434
DM		 13966 /* It is best to perform DMA test with maximum write burst size
13967 * to expose the 5700/5701 write DMA bug.
13968 */
13969 saved_dma_rwctrl = tp->dma_rwctrl;
13970 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13971 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13972
1da177e4
LT		 13973 while (1) {
13974 u32 *p = buf, i;
13975
13976 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13977 p[i] = i;
13978
13979 /* Send the buffer to the chip. */
13980 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13981 if (ret) {
13982 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13983 break;
13984 }
13985
13986#if 0
13987 /* validate data reached card RAM correctly. */
13988 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13989 u32 val;
13990 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13991 if (le32_to_cpu(val) != p[i]) {
13992 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13993 /* ret = -ENODEV here? */
13994 }
13995 p[i] = 0;
13996 }
13997#endif
13998 /* Now read it back. */
13999 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14000 if (ret) {
14001 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14002
14003 break;
14004 }
14005
14006 /* Verify it. */
14007 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14008 if (p[i] == i)
14009 continue;
14010
59e6b434
DM		 14011 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14012 DMA_RWCTRL_WRITE_BNDRY_16) {
14013 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14014 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14015 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14016 break;
14017 } else {
14018 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14019 ret = -ENODEV;
14020 goto out;
14021 }
14022 }
14023
14024 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14025 /* Success. */
14026 ret = 0;
14027 break;
14028 }
14029 }
59e6b434
DM		 14030 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14031 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14032 static struct pci_device_id dma_wait_state_chipsets[] = {
14033 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14034 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14035 { },
14036 };
14037
59e6b434 14038 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14039 * now look for chipsets that are known to expose the
14040 * DMA bug without failing the test.
59e6b434 14041 */
6d1cfbab
MC		 14042 if (pci_dev_present(dma_wait_state_chipsets)) {
14043 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14044 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14045 }
14046 else
14047 /* Safe to use the calculated DMA boundary. */
14048 tp->dma_rwctrl = saved_dma_rwctrl;
14049
59e6b434
DM		 14050 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14051 }
1da177e4
LT		 14052
14053out:
14054 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14055out_nofree:
14056 return ret;
14057}
14058
14059static void __devinit tg3_init_link_config(struct tg3 *tp)
14060{
14061 tp->link_config.advertising =
14062 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14063 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14064 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14065 ADVERTISED_Autoneg | ADVERTISED_MII);
14066 tp->link_config.speed = SPEED_INVALID;
14067 tp->link_config.duplex = DUPLEX_INVALID;
14068 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14069 tp->link_config.active_speed = SPEED_INVALID;
14070 tp->link_config.active_duplex = DUPLEX_INVALID;
14071 tp->link_config.phy_is_low_power = 0;
14072 tp->link_config.orig_speed = SPEED_INVALID;
14073 tp->link_config.orig_duplex = DUPLEX_INVALID;
14074 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14075}
14076
14077static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14078{
f6eb9b1f 14079 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
b703df6f
MC		 14080 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14081 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
fdfec172
MC		 14082 tp->bufmgr_config.mbuf_read_dma_low_water =
14083 DEFAULT_MB_RDMA_LOW_WATER_5705;
14084 tp->bufmgr_config.mbuf_mac_rx_low_water =
14085 DEFAULT_MB_MACRX_LOW_WATER_5705;
14086 tp->bufmgr_config.mbuf_high_water =
14087 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14089 tp->bufmgr_config.mbuf_mac_rx_low_water =
14090 DEFAULT_MB_MACRX_LOW_WATER_5906;
14091 tp->bufmgr_config.mbuf_high_water =
14092 DEFAULT_MB_HIGH_WATER_5906;
14093 }
fdfec172
MC		 14094
14095 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14096 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14097 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14098 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14099 tp->bufmgr_config.mbuf_high_water_jumbo =
14100 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14101 } else {
14102 tp->bufmgr_config.mbuf_read_dma_low_water =
14103 DEFAULT_MB_RDMA_LOW_WATER;
14104 tp->bufmgr_config.mbuf_mac_rx_low_water =
14105 DEFAULT_MB_MACRX_LOW_WATER;
14106 tp->bufmgr_config.mbuf_high_water =
14107 DEFAULT_MB_HIGH_WATER;
14108
14109 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14110 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14111 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14112 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14113 tp->bufmgr_config.mbuf_high_water_jumbo =
14114 DEFAULT_MB_HIGH_WATER_JUMBO;
14115 }
1da177e4
LT		 14116
14117 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14118 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14119}
14120
14121static char * __devinit tg3_phy_string(struct tg3 *tp)
14122{
14123 switch (tp->phy_id & PHY_ID_MASK) {
14124 case PHY_ID_BCM5400: return "5400";
14125 case PHY_ID_BCM5401: return "5401";
14126 case PHY_ID_BCM5411: return "5411";
14127 case PHY_ID_BCM5701: return "5701";
14128 case PHY_ID_BCM5703: return "5703";
14129 case PHY_ID_BCM5704: return "5704";
14130 case PHY_ID_BCM5705: return "5705";
14131 case PHY_ID_BCM5750: return "5750";
85e94ced 14132 case PHY_ID_BCM5752: return "5752";
a4e2b347 14133 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14134 case PHY_ID_BCM5780: return "5780";
af36e6b6 14135 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14136 case PHY_ID_BCM5787: return "5787";
d30cdd28 14137 case PHY_ID_BCM5784: return "5784";
126a3368 14138 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14139 case PHY_ID_BCM5906: return "5906";
9936bcf6 14140 case PHY_ID_BCM5761: return "5761";
c2060fe1 14141 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 14142 case PHY_ID_BCM8002: return "8002/serdes";
14143 case 0: return "serdes";
14144 default: return "unknown";
855e1111 14145 }
1da177e4
LT		 14146}
14147
f9804ddb
MC		 14148static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14149{
14150 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14151 strcpy(str, "PCI Express");
14152 return str;
14153 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14154 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14155
14156 strcpy(str, "PCIX:");
14157
14158 if ((clock_ctrl == 7) ||
14159 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14160 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14161 strcat(str, "133MHz");
14162 else if (clock_ctrl == 0)
14163 strcat(str, "33MHz");
14164 else if (clock_ctrl == 2)
14165 strcat(str, "50MHz");
14166 else if (clock_ctrl == 4)
14167 strcat(str, "66MHz");
14168 else if (clock_ctrl == 6)
14169 strcat(str, "100MHz");
f9804ddb
MC		 14170 } else {
14171 strcpy(str, "PCI:");
14172 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14173 strcat(str, "66MHz");
14174 else
14175 strcat(str, "33MHz");
14176 }
14177 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14178 strcat(str, ":32-bit");
14179 else
14180 strcat(str, ":64-bit");
14181 return str;
14182}
14183
8c2dc7e1 14184static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14185{
14186 struct pci_dev *peer;
14187 unsigned int func, devnr = tp->pdev->devfn & ~7;
14188
14189 for (func = 0; func < 8; func++) {
14190 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14191 if (peer && peer != tp->pdev)
14192 break;
14193 pci_dev_put(peer);
14194 }
16fe9d74
MC		 14195 /* 5704 can be configured in single-port mode, set peer to
14196 * tp->pdev in that case.
14197 */
14198 if (!peer) {
14199 peer = tp->pdev;
14200 return peer;
14201 }
1da177e4
LT		 14202
14203 /*
14204 * We don't need to keep the refcount elevated; there's no way
14205 * to remove one half of this device without removing the other
14206 */
14207 pci_dev_put(peer);
14208
14209 return peer;
14210}
14211
15f9850d
DM		 14212static void __devinit tg3_init_coal(struct tg3 *tp)
14213{
14214 struct ethtool_coalesce *ec = &tp->coal;
14215
14216 memset(ec, 0, sizeof(*ec));
14217 ec->cmd = ETHTOOL_GCOALESCE;
14218 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14219 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14220 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14221 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14222 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14223 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14224 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14225 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14226 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14227
14228 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14229 HOSTCC_MODE_CLRTICK_TXBD)) {
14230 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14231 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14232 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14233 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14234 }
d244c892
MC		 14235
14236 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14237 ec->rx_coalesce_usecs_irq = 0;
14238 ec->tx_coalesce_usecs_irq = 0;
14239 ec->stats_block_coalesce_usecs = 0;
14240 }
15f9850d
DM		 14241}
14242
7c7d64b8
SH		 14243static const struct net_device_ops tg3_netdev_ops = {
14244 .ndo_open = tg3_open,
14245 .ndo_stop = tg3_close,
00829823
SH		 14246 .ndo_start_xmit = tg3_start_xmit,
14247 .ndo_get_stats = tg3_get_stats,
14248 .ndo_validate_addr = eth_validate_addr,
14249 .ndo_set_multicast_list = tg3_set_rx_mode,
14250 .ndo_set_mac_address = tg3_set_mac_addr,
14251 .ndo_do_ioctl = tg3_ioctl,
14252 .ndo_tx_timeout = tg3_tx_timeout,
14253 .ndo_change_mtu = tg3_change_mtu,
14254#if TG3_VLAN_TAG_USED
14255 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14256#endif
14257#ifdef CONFIG_NET_POLL_CONTROLLER
14258 .ndo_poll_controller = tg3_poll_controller,
14259#endif
14260};
14261
14262static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14263 .ndo_open = tg3_open,
14264 .ndo_stop = tg3_close,
14265 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14266 .ndo_get_stats = tg3_get_stats,
14267 .ndo_validate_addr = eth_validate_addr,
14268 .ndo_set_multicast_list = tg3_set_rx_mode,
14269 .ndo_set_mac_address = tg3_set_mac_addr,
14270 .ndo_do_ioctl = tg3_ioctl,
14271 .ndo_tx_timeout = tg3_tx_timeout,
14272 .ndo_change_mtu = tg3_change_mtu,
14273#if TG3_VLAN_TAG_USED
14274 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14275#endif
14276#ifdef CONFIG_NET_POLL_CONTROLLER
14277 .ndo_poll_controller = tg3_poll_controller,
14278#endif
14279};
14280
1da177e4
LT		 14281static int __devinit tg3_init_one(struct pci_dev *pdev,
14282 const struct pci_device_id *ent)
14283{
14284 static int tg3_version_printed = 0;
1da177e4
LT		 14285 struct net_device *dev;
14286 struct tg3 *tp;
646c9edd
MC		 14287 int i, err, pm_cap;
14288 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14289 char str[40];
72f2afb8 14290 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14291
14292 if (tg3_version_printed++ == 0)
14293 printk(KERN_INFO "%s", version);
14294
14295 err = pci_enable_device(pdev);
14296 if (err) {
14297 printk(KERN_ERR PFX "Cannot enable PCI device, "
14298 "aborting.\n");
14299 return err;
14300 }
14301
1da177e4
LT		 14302 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14303 if (err) {
14304 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14305 "aborting.\n");
14306 goto err_out_disable_pdev;
14307 }
14308
14309 pci_set_master(pdev);
14310
14311 /* Find power-management capability. */
14312 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14313 if (pm_cap == 0) {
14314 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14315 "aborting.\n");
14316 err = -EIO;
14317 goto err_out_free_res;
14318 }
14319
fe5f5787 14320 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14321 if (!dev) {
14322 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14323 err = -ENOMEM;
14324 goto err_out_free_res;
14325 }
14326
1da177e4
LT		 14327 SET_NETDEV_DEV(dev, &pdev->dev);
14328
1da177e4
LT		 14329#if TG3_VLAN_TAG_USED
14330 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14331#endif
14332
14333 tp = netdev_priv(dev);
14334 tp->pdev = pdev;
14335 tp->dev = dev;
14336 tp->pm_cap = pm_cap;
1da177e4
LT		 14337 tp->rx_mode = TG3_DEF_RX_MODE;
14338 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14339
1da177e4
LT		 14340 if (tg3_debug > 0)
14341 tp->msg_enable = tg3_debug;
14342 else
14343 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14344
14345 /* The word/byte swap controls here control register access byte
14346 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14347 * setting below.
14348 */
14349 tp->misc_host_ctrl =
14350 MISC_HOST_CTRL_MASK_PCI_INT |
14351 MISC_HOST_CTRL_WORD_SWAP |
14352 MISC_HOST_CTRL_INDIR_ACCESS |
14353 MISC_HOST_CTRL_PCISTATE_RW;
14354
14355 /* The NONFRM (non-frame) byte/word swap controls take effect
14356 * on descriptor entries, anything which isn't packet data.
14357 *
14358 * The StrongARM chips on the board (one for tx, one for rx)
14359 * are running in big-endian mode.
14360 */
14361 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14362 GRC_MODE_WSWAP_NONFRM_DATA);
14363#ifdef __BIG_ENDIAN
14364 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14365#endif
14366 spin_lock_init(&tp->lock);
1da177e4 14367 spin_lock_init(&tp->indirect_lock);
c4028958 14368 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14369
d5fe488a 14370 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14371 if (!tp->regs) {
1da177e4
LT		 14372 printk(KERN_ERR PFX "Cannot map device registers, "
14373 "aborting.\n");
14374 err = -ENOMEM;
14375 goto err_out_free_dev;
14376 }
14377
14378 tg3_init_link_config(tp);
14379
1da177e4
LT		 14380 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14381 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14382
1da177e4 14383 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14384 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14385 dev->irq = pdev->irq;
1da177e4
LT		 14386
14387 err = tg3_get_invariants(tp);
14388 if (err) {
14389 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14390 "aborting.\n");
14391 goto err_out_iounmap;
14392 }
14393
615774fe
MC		 14394 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14395 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14396 dev->netdev_ops = &tg3_netdev_ops;
14397 else
14398 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14399
14400
4a29cc2e
MC		 14401 /* The EPB bridge inside 5714, 5715, and 5780 and any
14402 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14403 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14404 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14405 * do DMA address check in tg3_start_xmit().
14406 */
4a29cc2e 14407 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14408 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14409 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14410 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14411#ifdef CONFIG_HIGHMEM
6a35528a 14412 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14413#endif
4a29cc2e 14414 } else
6a35528a 14415 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14416
14417 /* Configure DMA attributes. */
284901a9 14418 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14419 err = pci_set_dma_mask(pdev, dma_mask);
14420 if (!err) {
14421 dev->features |= NETIF_F_HIGHDMA;
14422 err = pci_set_consistent_dma_mask(pdev,
14423 persist_dma_mask);
14424 if (err < 0) {
14425 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14426 "DMA for consistent allocations\n");
14427 goto err_out_iounmap;
14428 }
14429 }
14430 }
284901a9
YH		 14431 if (err || dma_mask == DMA_BIT_MASK(32)) {
14432 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14433 if (err) {
14434 printk(KERN_ERR PFX "No usable DMA configuration, "
14435 "aborting.\n");
14436 goto err_out_iounmap;
14437 }
14438 }
14439
fdfec172 14440 tg3_init_bufmgr_config(tp);
1da177e4 14441
507399f1
MC		 14442 /* Selectively allow TSO based on operating conditions */
14443 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14444 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14445 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14446 else {
14447 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14448 tp->fw_needed = NULL;
1da177e4 14449 }
507399f1
MC		 14450
14451 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14452 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14453
4e3a7aaa
MC		 14454 /* TSO is on by default on chips that support hardware TSO.
14455 * Firmware TSO on older chips gives lower performance, so it
14456 * is off by default, but can be enabled using ethtool.
14457 */
e849cdc3
MC		 14458 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14459 (dev->features & NETIF_F_IP_CSUM))
14460 dev->features |= NETIF_F_TSO;
14461
14462 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14463 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14464 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14465 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14466 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14468 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14469 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14470 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14472 dev->features |= NETIF_F_TSO_ECN;
b0026624 14473 }
1da177e4 14474
1da177e4
LT		 14475 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14476 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14477 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14478 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14479 tp->rx_pending = 63;
14480 }
14481
1da177e4
LT		 14482 err = tg3_get_device_address(tp);
14483 if (err) {
14484 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14485 "aborting.\n");
026a6c21 14486 goto err_out_iounmap;
1da177e4
LT		 14487 }
14488
c88864df 14489 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14490 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14491 if (!tp->aperegs) {
c88864df
MC		 14492 printk(KERN_ERR PFX "Cannot map APE registers, "
14493 "aborting.\n");
14494 err = -ENOMEM;
026a6c21 14495 goto err_out_iounmap;
c88864df
MC		 14496 }
14497
14498 tg3_ape_lock_init(tp);
7fd76445
MC		 14499
14500 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14501 tg3_read_dash_ver(tp);
c88864df
MC		 14502 }
14503
1da177e4
LT		 14504 /*
14505 * Reset chip in case UNDI or EFI driver did not shutdown
14506 * DMA self test will enable WDMAC and we'll see (spurious)
14507 * pending DMA on the PCI bus at that point.
14508 */
14509 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14510 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14511 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14512 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14513 }
14514
14515 err = tg3_test_dma(tp);
14516 if (err) {
14517 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14518 goto err_out_apeunmap;
1da177e4
LT		 14519 }
14520
1da177e4
LT		 14521 /* flow control autonegotiation is default behavior */
14522 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14523 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14524
78f90dcf
MC		 14525 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14526 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14527 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14528 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14529 struct tg3_napi *tnapi = &tp->napi[i];
14530
14531 tnapi->tp = tp;
14532 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14533
14534 tnapi->int_mbox = intmbx;
14535 if (i < 4)
14536 intmbx += 0x8;
14537 else
14538 intmbx += 0x4;
14539
14540 tnapi->consmbox = rcvmbx;
14541 tnapi->prodmbox = sndmbx;
14542
14543 if (i) {
14544 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14545 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14546 } else {
14547 tnapi->coal_now = HOSTCC_MODE_NOW;
14548 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14549 }
14550
14551 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14552 break;
14553
14554 /*
14555 * If we support MSIX, we'll be using RSS. If we're using
14556 * RSS, the first vector only handles link interrupts and the
14557 * remaining vectors handle rx and tx interrupts. Reuse the
14558 * mailbox values for the next iteration. The values we setup
14559 * above are still useful for the single vectored mode.
14560 */
14561 if (!i)
14562 continue;
14563
14564 rcvmbx += 0x8;
14565
14566 if (sndmbx & 0x4)
14567 sndmbx -= 0x4;
14568 else
14569 sndmbx += 0xc;
14570 }
14571
15f9850d
DM		 14572 tg3_init_coal(tp);
14573
c49a1561
MC		 14574 pci_set_drvdata(pdev, dev);
14575
1da177e4
LT		 14576 err = register_netdev(dev);
14577 if (err) {
14578 printk(KERN_ERR PFX "Cannot register net device, "
14579 "aborting.\n");
0d3031d9 14580 goto err_out_apeunmap;
1da177e4
LT		 14581 }
14582
df59c940 14583 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14584 dev->name,
14585 tp->board_part_number,
14586 tp->pci_chip_rev_id,
f9804ddb 14587 tg3_bus_string(tp, str),
e174961c 14588 dev->dev_addr);
1da177e4 14589
3f0e3ad7
MC		 14590 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14591 struct phy_device *phydev;
14592 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14593 printk(KERN_INFO
14594 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14595 tp->dev->name, phydev->drv->name,
14596 dev_name(&phydev->dev));
14597 } else
df59c940
MC		 14598 printk(KERN_INFO
14599 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14600 tp->dev->name, tg3_phy_string(tp),
14601 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14602 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14603 "10/100/1000Base-T")),
14604 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14605
14606 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14607 dev->name,
14608 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14609 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14610 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14611 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14612 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14613 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14614 dev->name, tp->dma_rwctrl,
284901a9 14615 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14616 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14617
14618 return 0;
14619
0d3031d9
MC		 14620err_out_apeunmap:
14621 if (tp->aperegs) {
14622 iounmap(tp->aperegs);
14623 tp->aperegs = NULL;
14624 }
14625
1da177e4 14626err_out_iounmap:
6892914f
MC		 14627 if (tp->regs) {
14628 iounmap(tp->regs);
22abe310 14629 tp->regs = NULL;
6892914f 14630 }
1da177e4
LT		 14631
14632err_out_free_dev:
14633 free_netdev(dev);
14634
14635err_out_free_res:
14636 pci_release_regions(pdev);
14637
14638err_out_disable_pdev:
14639 pci_disable_device(pdev);
14640 pci_set_drvdata(pdev, NULL);
14641 return err;
14642}
14643
14644static void __devexit tg3_remove_one(struct pci_dev *pdev)
14645{
14646 struct net_device *dev = pci_get_drvdata(pdev);
14647
14648 if (dev) {
14649 struct tg3 *tp = netdev_priv(dev);
14650
077f849d
JSR		 14651 if (tp->fw)
14652 release_firmware(tp->fw);
14653
7faa006f 14654 flush_scheduled_work();
158d7abd 14655
b02fd9e3
MC		 14656 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14657 tg3_phy_fini(tp);
158d7abd 14658 tg3_mdio_fini(tp);
b02fd9e3 14659 }
158d7abd 14660
1da177e4 14661 unregister_netdev(dev);
0d3031d9
MC		 14662 if (tp->aperegs) {
14663 iounmap(tp->aperegs);
14664 tp->aperegs = NULL;
14665 }
6892914f
MC		 14666 if (tp->regs) {
14667 iounmap(tp->regs);
22abe310 14668 tp->regs = NULL;
6892914f 14669 }
1da177e4
LT		 14670 free_netdev(dev);
14671 pci_release_regions(pdev);
14672 pci_disable_device(pdev);
14673 pci_set_drvdata(pdev, NULL);
14674 }
14675}
14676
14677static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14678{
14679 struct net_device *dev = pci_get_drvdata(pdev);
14680 struct tg3 *tp = netdev_priv(dev);
12dac075 14681 pci_power_t target_state;
1da177e4
LT		 14682 int err;
14683
3e0c95fd
MC		 14684 /* PCI register 4 needs to be saved whether netif_running() or not.
14685 * MSI address and data need to be saved if using MSI and
14686 * netif_running().
14687 */
14688 pci_save_state(pdev);
14689
1da177e4
LT		 14690 if (!netif_running(dev))
14691 return 0;
14692
7faa006f 14693 flush_scheduled_work();
b02fd9e3 14694 tg3_phy_stop(tp);
1da177e4
LT		 14695 tg3_netif_stop(tp);
14696
14697 del_timer_sync(&tp->timer);
14698
f47c11ee 14699 tg3_full_lock(tp, 1);
1da177e4 14700 tg3_disable_ints(tp);
f47c11ee 14701 tg3_full_unlock(tp);
1da177e4
LT		 14702
14703 netif_device_detach(dev);
14704
f47c11ee 14705 tg3_full_lock(tp, 0);
944d980e 14706 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14707 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14708 tg3_full_unlock(tp);
1da177e4 14709
12dac075
RW		 14710 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14711
14712 err = tg3_set_power_state(tp, target_state);
1da177e4 14713 if (err) {
b02fd9e3
MC		 14714 int err2;
14715
f47c11ee 14716 tg3_full_lock(tp, 0);
1da177e4 14717
6a9eba15 14718 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14719 err2 = tg3_restart_hw(tp, 1);
14720 if (err2)
b9ec6c1b 14721 goto out;
1da177e4
LT		 14722
14723 tp->timer.expires = jiffies + tp->timer_offset;
14724 add_timer(&tp->timer);
14725
14726 netif_device_attach(dev);
14727 tg3_netif_start(tp);
14728
b9ec6c1b 14729out:
f47c11ee 14730 tg3_full_unlock(tp);
b02fd9e3
MC		 14731
14732 if (!err2)
14733 tg3_phy_start(tp);
1da177e4
LT		 14734 }
14735
14736 return err;
14737}
14738
14739static int tg3_resume(struct pci_dev *pdev)
14740{
14741 struct net_device *dev = pci_get_drvdata(pdev);
14742 struct tg3 *tp = netdev_priv(dev);
14743 int err;
14744
3e0c95fd
MC		 14745 pci_restore_state(tp->pdev);
14746
1da177e4
LT		 14747 if (!netif_running(dev))
14748 return 0;
14749
bc1c7567 14750 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14751 if (err)
14752 return err;
14753
14754 netif_device_attach(dev);
14755
f47c11ee 14756 tg3_full_lock(tp, 0);
1da177e4 14757
6a9eba15 14758 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14759 err = tg3_restart_hw(tp, 1);
14760 if (err)
14761 goto out;
1da177e4
LT		 14762
14763 tp->timer.expires = jiffies + tp->timer_offset;
14764 add_timer(&tp->timer);
14765
1da177e4
LT		 14766 tg3_netif_start(tp);
14767
b9ec6c1b 14768out:
f47c11ee 14769 tg3_full_unlock(tp);
1da177e4 14770
b02fd9e3
MC		 14771 if (!err)
14772 tg3_phy_start(tp);
14773
b9ec6c1b 14774 return err;
1da177e4
LT		 14775}
14776
14777static struct pci_driver tg3_driver = {
14778 .name = DRV_MODULE_NAME,
14779 .id_table = tg3_pci_tbl,
14780 .probe = tg3_init_one,
14781 .remove = __devexit_p(tg3_remove_one),
14782 .suspend = tg3_suspend,
14783 .resume = tg3_resume
14784};
14785
14786static int __init tg3_init(void)
14787{
29917620 14788 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14789}
14790
14791static void __exit tg3_cleanup(void)
14792{
14793 pci_unregister_driver(&tg3_driver);
14794}
14795
14796module_init(tg3_init);
14797module_exit(tg3_cleanup);
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