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r8169: check dma mapping failures
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
1da177e4 27
99f252b0 28#include <asm/system.h>
1da177e4
LT		 29#include <asm/io.h>
30#include <asm/irq.h>
31
865c652d 32#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 33#define MODULENAME "r8169"
34#define PFX MODULENAME ": "
35
36#ifdef RTL8169_DEBUG
37#define assert(expr) \
5b0384f4
FR		 38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 40 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 41 }
06fa7358
JP		 42#define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 44#else
45#define assert(expr) do {} while (0)
46#define dprintk(fmt, args...) do {} while (0)
47#endif /* RTL8169_DEBUG */
48
b57b7e5a 49#define R8169_MSG_DEFAULT \
f0e837d9 50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 51
1da177e4
LT		 52#define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
1da177e4
LT		 55/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 57static const int multicast_filter_limit = 32;
1da177e4
LT		 58
59/* MAC address length */
60#define MAC_ADDR_LEN 6
61
9c14ceaf 62#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 63#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 66#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 67#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
71#define R8169_NAPI_WEIGHT 64
72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74#define RX_BUF_SIZE 1536 /* Rx Buffer size */
75#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78#define RTL8169_TX_TIMEOUT (6*HZ)
79#define RTL8169_PHY_TIMEOUT (10*HZ)
80
ea8dbdd1 81#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 83#define RTL_EEPROM_SIG_ADDR 0x0000
84
1da177e4
LT		 85/* write/read MMIO register */
86#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89#define RTL_R8(reg) readb (ioaddr + (reg))
90#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 91#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 92
93enum mac_version {
f21b75e9 94 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 159};
160#undef _R
161
bcf0bf90
FR		 162enum cfg_version {
163 RTL_CFG_0 = 0x00,
164 RTL_CFG_1,
165 RTL_CFG_2
166};
167
07ce4064
FR		 168static void rtl_hw_start_8169(struct net_device *);
169static void rtl_hw_start_8168(struct net_device *);
170static void rtl_hw_start_8101(struct net_device *);
171
a3aa1884 172static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 183 { 0x0001, 0x8168,
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 185 {0,},
186};
187
188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189
6f0333b8 190static int rx_buf_sz = 16383;
4300e8c7 191static int use_dac;
b57b7e5a
SH		 192static struct {
193 u32 msg_enable;
194} debug = { -1 };
1da177e4 195
07d3f51f
FR		 196enum rtl_registers {
197 MAC0 = 0, /* Ethernet hardware address. */
773d2021 198 MAC4 = 4,
07d3f51f
FR		 199 MAR0 = 8, /* Multicast filter. */
200 CounterAddrLow = 0x10,
201 CounterAddrHigh = 0x14,
202 TxDescStartAddrLow = 0x20,
203 TxDescStartAddrHigh = 0x24,
204 TxHDescStartAddrLow = 0x28,
205 TxHDescStartAddrHigh = 0x2c,
206 FLASH = 0x30,
207 ERSR = 0x36,
208 ChipCmd = 0x37,
209 TxPoll = 0x38,
210 IntrMask = 0x3c,
211 IntrStatus = 0x3e,
212 TxConfig = 0x40,
213 RxConfig = 0x44,
214 RxMissed = 0x4c,
215 Cfg9346 = 0x50,
216 Config0 = 0x51,
217 Config1 = 0x52,
218 Config2 = 0x53,
219 Config3 = 0x54,
220 Config4 = 0x55,
221 Config5 = 0x56,
222 MultiIntr = 0x5c,
223 PHYAR = 0x60,
07d3f51f
FR		 224 PHYstatus = 0x6c,
225 RxMaxSize = 0xda,
226 CPlusCmd = 0xe0,
227 IntrMitigate = 0xe2,
228 RxDescAddrLow = 0xe4,
229 RxDescAddrHigh = 0xe8,
230 EarlyTxThres = 0xec,
231 FuncEvent = 0xf0,
232 FuncEventMask = 0xf4,
233 FuncPresetState = 0xf8,
234 FuncForceEvent = 0xfc,
1da177e4
LT		 235};
236
f162a5d1
FR		 237enum rtl8110_registers {
238 TBICSR = 0x64,
239 TBI_ANAR = 0x68,
240 TBI_LPAR = 0x6a,
241};
242
243enum rtl8168_8101_registers {
244 CSIDR = 0x64,
245 CSIAR = 0x68,
246#define CSIAR_FLAG 0x80000000
247#define CSIAR_WRITE_CMD 0x80000000
248#define CSIAR_BYTE_ENABLE 0x0f
249#define CSIAR_BYTE_ENABLE_SHIFT 12
250#define CSIAR_ADDR_MASK 0x0fff
251
252 EPHYAR = 0x80,
253#define EPHYAR_FLAG 0x80000000
254#define EPHYAR_WRITE_CMD 0x80000000
255#define EPHYAR_REG_MASK 0x1f
256#define EPHYAR_REG_SHIFT 16
257#define EPHYAR_DATA_MASK 0xffff
258 DBG_REG = 0xd1,
259#define FIX_NAK_1 (1 << 4)
260#define FIX_NAK_2 (1 << 3)
daf9df6d 261 EFUSEAR = 0xdc,
262#define EFUSEAR_FLAG 0x80000000
263#define EFUSEAR_WRITE_CMD 0x80000000
264#define EFUSEAR_READ_CMD 0x00000000
265#define EFUSEAR_REG_MASK 0x03ff
266#define EFUSEAR_REG_SHIFT 8
267#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 268};
269
07d3f51f 270enum rtl_register_content {
1da177e4 271 /* InterruptStatusBits */
07d3f51f
FR		 272 SYSErr = 0x8000,
273 PCSTimeout = 0x4000,
274 SWInt = 0x0100,
275 TxDescUnavail = 0x0080,
276 RxFIFOOver = 0x0040,
277 LinkChg = 0x0020,
278 RxOverflow = 0x0010,
279 TxErr = 0x0008,
280 TxOK = 0x0004,
281 RxErr = 0x0002,
282 RxOK = 0x0001,
1da177e4
LT		 283
284 /* RxStatusDesc */
9dccf611
FR		 285 RxFOVF = (1 << 23),
286 RxRWT = (1 << 22),
287 RxRES = (1 << 21),
288 RxRUNT = (1 << 20),
289 RxCRC = (1 << 19),
1da177e4
LT		 290
291 /* ChipCmdBits */
07d3f51f
FR		 292 CmdReset = 0x10,
293 CmdRxEnb = 0x08,
294 CmdTxEnb = 0x04,
295 RxBufEmpty = 0x01,
1da177e4 296
275391a4
FR		 297 /* TXPoll register p.5 */
298 HPQ = 0x80, /* Poll cmd on the high prio queue */
299 NPQ = 0x40, /* Poll cmd on the low prio queue */
300 FSWInt = 0x01, /* Forced software interrupt */
301
1da177e4 302 /* Cfg9346Bits */
07d3f51f
FR		 303 Cfg9346_Lock = 0x00,
304 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 305
306 /* rx_mode_bits */
07d3f51f
FR		 307 AcceptErr = 0x20,
308 AcceptRunt = 0x10,
309 AcceptBroadcast = 0x08,
310 AcceptMulticast = 0x04,
311 AcceptMyPhys = 0x02,
312 AcceptAllPhys = 0x01,
1da177e4
LT		 313
314 /* RxConfigBits */
07d3f51f
FR		 315 RxCfgFIFOShift = 13,
316 RxCfgDMAShift = 8,
1da177e4
LT		 317
318 /* TxConfigBits */
319 TxInterFrameGapShift = 24,
320 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
321
5d06a99f 322 /* Config1 register p.24 */
f162a5d1
FR		 323 LEDS1 = (1 << 7),
324 LEDS0 = (1 << 6),
fbac58fc 325 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 326 Speed_down = (1 << 4),
327 MEMMAP = (1 << 3),
328 IOMAP = (1 << 2),
329 VPD = (1 << 1),
5d06a99f
FR		 330 PMEnable = (1 << 0), /* Power Management Enable */
331
6dccd16b
FR		 332 /* Config2 register p. 25 */
333 PCI_Clock_66MHz = 0x01,
334 PCI_Clock_33MHz = 0x00,
335
61a4dcc2
FR		 336 /* Config3 register p.25 */
337 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
338 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 339 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 340
5d06a99f 341 /* Config5 register p.27 */
61a4dcc2
FR		 342 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF = (1 << 5), /* Accept Multicast wakeup frame */
344 UWF = (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 346 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
347
1da177e4
LT		 348 /* TBICSR p.28 */
349 TBIReset = 0x80000000,
350 TBILoopback = 0x40000000,
351 TBINwEnable = 0x20000000,
352 TBINwRestart = 0x10000000,
353 TBILinkOk = 0x02000000,
354 TBINwComplete = 0x01000000,
355
356 /* CPlusCmd p.31 */
f162a5d1
FR		 357 EnableBist = (1 << 15), // 8168 8101
358 Mac_dbgo_oe = (1 << 14), // 8168 8101
359 Normal_mode = (1 << 13), // unused
360 Force_half_dup = (1 << 12), // 8168 8101
361 Force_rxflow_en = (1 << 11), // 8168 8101
362 Force_txflow_en = (1 << 10), // 8168 8101
363 Cxpl_dbg_sel = (1 << 9), // 8168 8101
364 ASF = (1 << 8), // 8168 8101
365 PktCntrDisable = (1 << 7), // 8168 8101
366 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 367 RxVlan = (1 << 6),
368 RxChkSum = (1 << 5),
369 PCIDAC = (1 << 4),
370 PCIMulRW = (1 << 3),
0e485150
FR		 371 INTT_0 = 0x0000, // 8168
372 INTT_1 = 0x0001, // 8168
373 INTT_2 = 0x0002, // 8168
374 INTT_3 = 0x0003, // 8168
1da177e4
LT		 375
376 /* rtl8169_PHYstatus */
07d3f51f
FR		 377 TBI_Enable = 0x80,
378 TxFlowCtrl = 0x40,
379 RxFlowCtrl = 0x20,
380 _1000bpsF = 0x10,
381 _100bps = 0x08,
382 _10bps = 0x04,
383 LinkStatus = 0x02,
384 FullDup = 0x01,
1da177e4 385
1da177e4 386 /* _TBICSRBit */
07d3f51f 387 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 388
389 /* DumpCounterCommand */
07d3f51f 390 CounterDump = 0x8,
1da177e4
LT		 391};
392
07d3f51f 393enum desc_status_bit {
1da177e4
LT		 394 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
395 RingEnd = (1 << 30), /* End of descriptor ring */
396 FirstFrag = (1 << 29), /* First segment of a packet */
397 LastFrag = (1 << 28), /* Final segment of a packet */
398
399 /* Tx private */
400 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
401 MSSShift = 16, /* MSS value position */
402 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
403 IPCS = (1 << 18), /* Calculate IP checksum */
404 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
405 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
406 TxVlanTag = (1 << 17), /* Add VLAN tag */
407
408 /* Rx private */
409 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
410 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
411
412#define RxProtoUDP (PID1)
413#define RxProtoTCP (PID0)
414#define RxProtoIP (PID1 | PID0)
415#define RxProtoMask RxProtoIP
416
417 IPFail = (1 << 16), /* IP checksum failed */
418 UDPFail = (1 << 15), /* UDP/IP checksum failed */
419 TCPFail = (1 << 14), /* TCP/IP checksum failed */
420 RxVlanTag = (1 << 16), /* VLAN tag available */
421};
422
423#define RsvdMask 0x3fffc000
424
425struct TxDesc {
6cccd6e7
REB		 426 __le32 opts1;
427 __le32 opts2;
428 __le64 addr;
1da177e4
LT		 429};
430
431struct RxDesc {
6cccd6e7
REB		 432 __le32 opts1;
433 __le32 opts2;
434 __le64 addr;
1da177e4
LT		 435};
436
437struct ring_info {
438 struct sk_buff *skb;
439 u32 len;
440 u8 __pad[sizeof(void *) - sizeof(u32)];
441};
442
f23e7fda 443enum features {
ccdffb9a
FR		 444 RTL_FEATURE_WOL = (1 << 0),
445 RTL_FEATURE_MSI = (1 << 1),
446 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 447};
448
355423d0
IV		 449struct rtl8169_counters {
450 __le64 tx_packets;
451 __le64 rx_packets;
452 __le64 tx_errors;
453 __le32 rx_errors;
454 __le16 rx_missed;
455 __le16 align_errors;
456 __le32 tx_one_collision;
457 __le32 tx_multi_collision;
458 __le64 rx_unicast;
459 __le64 rx_broadcast;
460 __le32 rx_multicast;
461 __le16 tx_aborted;
462 __le16 tx_underun;
463};
464
1da177e4
LT		 465struct rtl8169_private {
466 void __iomem *mmio_addr; /* memory map physical address */
467 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 468 struct net_device *dev;
bea3348e 469 struct napi_struct napi;
1da177e4 470 spinlock_t lock; /* spin lock flag */
b57b7e5a 471 u32 msg_enable;
1da177e4
LT		 472 int chipset;
473 int mac_version;
1da177e4
LT		 474 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
475 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
476 u32 dirty_rx;
477 u32 dirty_tx;
478 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
479 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
480 dma_addr_t TxPhyAddr;
481 dma_addr_t RxPhyAddr;
6f0333b8 482 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 483 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 484 struct timer_list timer;
485 u16 cp_cmd;
0e485150
FR		 486 u16 intr_event;
487 u16 napi_event;
1da177e4 488 u16 intr_mask;
1da177e4
LT		 489 int phy_1000_ctrl_reg;
490#ifdef CONFIG_R8169_VLAN
491 struct vlan_group *vlgrp;
492#endif
493 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 494 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 495 void (*phy_reset_enable)(void __iomem *);
07ce4064 496 void (*hw_start)(struct net_device *);
1da177e4
LT		 497 unsigned int (*phy_reset_pending)(void __iomem *);
498 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 499 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 500 int pcie_cap;
c4028958 501 struct delayed_work task;
f23e7fda 502 unsigned features;
ccdffb9a
FR		 503
504 struct mii_if_info mii;
355423d0 505 struct rtl8169_counters counters;
e1759441 506 u32 saved_wolopts;
1da177e4
LT		 507};
508
979b6c13 509MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 510MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 511module_param(use_dac, int, 0);
4300e8c7 512MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 513module_param_named(debug, debug.msg_enable, int, 0);
514MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 515MODULE_LICENSE("GPL");
516MODULE_VERSION(RTL8169_VERSION);
517
518static int rtl8169_open(struct net_device *dev);
61357325
SH		 519static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
520 struct net_device *dev);
7d12e780 521static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 522static int rtl8169_init_ring(struct net_device *dev);
07ce4064 523static void rtl_hw_start(struct net_device *dev);
1da177e4 524static int rtl8169_close(struct net_device *dev);
07ce4064 525static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 526static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 527static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 528static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 529 void __iomem *, u32 budget);
4dcb7d33 530static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 531static void rtl8169_down(struct net_device *dev);
99f252b0 532static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 533static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 534
1da177e4 535static const unsigned int rtl8169_rx_config =
5b0384f4 536 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 537
07d3f51f 538static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 539{
540 int i;
541
a6baf3af 542 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 543
2371408c 544 for (i = 20; i > 0; i--) {
07d3f51f
FR		 545 /*
546 * Check if the RTL8169 has completed writing to the specified
547 * MII register.
548 */
5b0384f4 549 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 550 break;
2371408c 551 udelay(25);
1da177e4 552 }
024a07ba 553 /*
81a95f04
TT		 554 * According to hardware specs a 20us delay is required after write
555 * complete indication, but before sending next command.
024a07ba 556 */
81a95f04 557 udelay(20);
1da177e4
LT		 558}
559
07d3f51f 560static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 561{
562 int i, value = -1;
563
a6baf3af 564 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 565
2371408c 566 for (i = 20; i > 0; i--) {
07d3f51f
FR		 567 /*
568 * Check if the RTL8169 has completed retrieving data from
569 * the specified MII register.
570 */
1da177e4 571 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 572 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 573 break;
574 }
2371408c 575 udelay(25);
1da177e4 576 }
81a95f04
TT		 577 /*
578 * According to hardware specs a 20us delay is required after read
579 * complete indication, but before sending next command.
580 */
581 udelay(20);
582
1da177e4
LT		 583 return value;
584}
585
dacf8154
FR		 586static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
587{
588 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
589}
590
daf9df6d 591static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
592{
593 int val;
594
595 val = mdio_read(ioaddr, reg_addr);
596 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
597}
598
ccdffb9a
FR		 599static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
600 int val)
601{
602 struct rtl8169_private *tp = netdev_priv(dev);
603 void __iomem *ioaddr = tp->mmio_addr;
604
605 mdio_write(ioaddr, location, val);
606}
607
608static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
609{
610 struct rtl8169_private *tp = netdev_priv(dev);
611 void __iomem *ioaddr = tp->mmio_addr;
612
613 return mdio_read(ioaddr, location);
614}
615
dacf8154
FR		 616static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
617{
618 unsigned int i;
619
620 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
621 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
622
623 for (i = 0; i < 100; i++) {
624 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
625 break;
626 udelay(10);
627 }
628}
629
630static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
631{
632 u16 value = 0xffff;
633 unsigned int i;
634
635 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
636
637 for (i = 0; i < 100; i++) {
638 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
639 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
640 break;
641 }
642 udelay(10);
643 }
644
645 return value;
646}
647
648static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
649{
650 unsigned int i;
651
652 RTL_W32(CSIDR, value);
653 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
654 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
655
656 for (i = 0; i < 100; i++) {
657 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
658 break;
659 udelay(10);
660 }
661}
662
663static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
664{
665 u32 value = ~0x00;
666 unsigned int i;
667
668 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
669 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
670
671 for (i = 0; i < 100; i++) {
672 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
673 value = RTL_R32(CSIDR);
674 break;
675 }
676 udelay(10);
677 }
678
679 return value;
680}
681
daf9df6d 682static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
683{
684 u8 value = 0xff;
685 unsigned int i;
686
687 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
688
689 for (i = 0; i < 300; i++) {
690 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
691 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
692 break;
693 }
694 udelay(100);
695 }
696
697 return value;
698}
699
1da177e4
LT		 700static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
701{
702 RTL_W16(IntrMask, 0x0000);
703
704 RTL_W16(IntrStatus, 0xffff);
705}
706
707static void rtl8169_asic_down(void __iomem *ioaddr)
708{
709 RTL_W8(ChipCmd, 0x00);
710 rtl8169_irq_mask_and_ack(ioaddr);
711 RTL_R16(CPlusCmd);
712}
713
714static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
715{
716 return RTL_R32(TBICSR) & TBIReset;
717}
718
719static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
720{
64e4bfb4 721 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 722}
723
724static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
725{
726 return RTL_R32(TBICSR) & TBILinkOk;
727}
728
729static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
730{
731 return RTL_R8(PHYstatus) & LinkStatus;
732}
733
734static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
735{
736 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
737}
738
739static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
740{
741 unsigned int val;
742
9e0db8ef
FR		 743 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
744 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 745}
746
747static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 748 struct rtl8169_private *tp,
749 void __iomem *ioaddr)
1da177e4
LT		 750{
751 unsigned long flags;
752
753 spin_lock_irqsave(&tp->lock, flags);
754 if (tp->link_ok(ioaddr)) {
e1759441
RW		 755 /* This is to cancel a scheduled suspend if there's one. */
756 pm_request_resume(&tp->pci_dev->dev);
1da177e4 757 netif_carrier_on(dev);
bf82c189 758 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 759 } else {
1da177e4 760 netif_carrier_off(dev);
bf82c189 761 netif_info(tp, ifdown, dev, "link down\n");
e1759441 762 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 763 }
1da177e4
LT		 764 spin_unlock_irqrestore(&tp->lock, flags);
765}
766
e1759441
RW		 767#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
768
769static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 770{
61a4dcc2
FR		 771 void __iomem *ioaddr = tp->mmio_addr;
772 u8 options;
e1759441 773 u32 wolopts = 0;
61a4dcc2
FR		 774
775 options = RTL_R8(Config1);
776 if (!(options & PMEnable))
e1759441 777 return 0;
61a4dcc2
FR		 778
779 options = RTL_R8(Config3);
780 if (options & LinkUp)
e1759441 781 wolopts |= WAKE_PHY;
61a4dcc2 782 if (options & MagicPacket)
e1759441 783 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 784
785 options = RTL_R8(Config5);
786 if (options & UWF)
e1759441 787 wolopts |= WAKE_UCAST;
61a4dcc2 788 if (options & BWF)
e1759441 789 wolopts |= WAKE_BCAST;
61a4dcc2 790 if (options & MWF)
e1759441 791 wolopts |= WAKE_MCAST;
61a4dcc2 792
e1759441 793 return wolopts;
61a4dcc2
FR		 794}
795
e1759441 796static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 797{
798 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 799
800 spin_lock_irq(&tp->lock);
801
802 wol->supported = WAKE_ANY;
803 wol->wolopts = __rtl8169_get_wol(tp);
804
805 spin_unlock_irq(&tp->lock);
806}
807
808static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
809{
61a4dcc2 810 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 811 unsigned int i;
350f7596 812 static const struct {
61a4dcc2
FR		 813 u32 opt;
814 u16 reg;
815 u8 mask;
816 } cfg[] = {
817 { WAKE_ANY, Config1, PMEnable },
818 { WAKE_PHY, Config3, LinkUp },
819 { WAKE_MAGIC, Config3, MagicPacket },
820 { WAKE_UCAST, Config5, UWF },
821 { WAKE_BCAST, Config5, BWF },
822 { WAKE_MCAST, Config5, MWF },
823 { WAKE_ANY, Config5, LanWake }
824 };
825
61a4dcc2
FR		 826 RTL_W8(Cfg9346, Cfg9346_Unlock);
827
828 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
829 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 830 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 831 options |= cfg[i].mask;
832 RTL_W8(cfg[i].reg, options);
833 }
834
835 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 836}
837
838static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
839{
840 struct rtl8169_private *tp = netdev_priv(dev);
841
842 spin_lock_irq(&tp->lock);
61a4dcc2 843
f23e7fda
FR		 844 if (wol->wolopts)
845 tp->features |= RTL_FEATURE_WOL;
846 else
847 tp->features &= ~RTL_FEATURE_WOL;
e1759441 848 __rtl8169_set_wol(tp, wol->wolopts);
8b76ab39 849 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 850
851 spin_unlock_irq(&tp->lock);
852
853 return 0;
854}
855
1da177e4
LT		 856static void rtl8169_get_drvinfo(struct net_device *dev,
857 struct ethtool_drvinfo *info)
858{
859 struct rtl8169_private *tp = netdev_priv(dev);
860
861 strcpy(info->driver, MODULENAME);
862 strcpy(info->version, RTL8169_VERSION);
863 strcpy(info->bus_info, pci_name(tp->pci_dev));
864}
865
866static int rtl8169_get_regs_len(struct net_device *dev)
867{
868 return R8169_REGS_SIZE;
869}
870
871static int rtl8169_set_speed_tbi(struct net_device *dev,
872 u8 autoneg, u16 speed, u8 duplex)
873{
874 struct rtl8169_private *tp = netdev_priv(dev);
875 void __iomem *ioaddr = tp->mmio_addr;
876 int ret = 0;
877 u32 reg;
878
879 reg = RTL_R32(TBICSR);
880 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
881 (duplex == DUPLEX_FULL)) {
882 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
883 } else if (autoneg == AUTONEG_ENABLE)
884 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
885 else {
bf82c189
JP		 886 netif_warn(tp, link, dev,
887 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 888 ret = -EOPNOTSUPP;
889 }
890
891 return ret;
892}
893
894static int rtl8169_set_speed_xmii(struct net_device *dev,
895 u8 autoneg, u16 speed, u8 duplex)
896{
897 struct rtl8169_private *tp = netdev_priv(dev);
898 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 899 int giga_ctrl, bmcr;
1da177e4
LT		 900
901 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 902 int auto_nego;
903
904 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 905 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
906 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 907 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 908
3577aa1b 909 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
910 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 911
3577aa1b 912 /* The 8100e/8101e/8102e do Fast Ethernet only. */
913 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
914 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
915 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
916 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
917 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
918 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
919 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
920 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
921 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 922 } else {
923 netif_info(tp, link, dev,
924 "PHY does not support 1000Mbps\n");
bcf0bf90 925 }
1da177e4 926
3577aa1b 927 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
928
929 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
930 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
931 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
932 /*
933 * Wake up the PHY.
934 * Vendor specific (0x1f) and reserved (0x0e) MII
935 * registers.
936 */
937 mdio_write(ioaddr, 0x1f, 0x0000);
938 mdio_write(ioaddr, 0x0e, 0x0000);
939 }
940
941 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
942 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
943 } else {
944 giga_ctrl = 0;
945
946 if (speed == SPEED_10)
947 bmcr = 0;
948 else if (speed == SPEED_100)
949 bmcr = BMCR_SPEED100;
950 else
951 return -EINVAL;
952
953 if (duplex == DUPLEX_FULL)
954 bmcr |= BMCR_FULLDPLX;
623a1593 955
2584fbc3 956 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 957 }
958
1da177e4
LT		 959 tp->phy_1000_ctrl_reg = giga_ctrl;
960
3577aa1b 961 mdio_write(ioaddr, MII_BMCR, bmcr);
962
963 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
964 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
965 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
966 mdio_write(ioaddr, 0x17, 0x2138);
967 mdio_write(ioaddr, 0x0e, 0x0260);
968 } else {
969 mdio_write(ioaddr, 0x17, 0x2108);
970 mdio_write(ioaddr, 0x0e, 0x0000);
971 }
972 }
973
1da177e4
LT		 974 return 0;
975}
976
977static int rtl8169_set_speed(struct net_device *dev,
978 u8 autoneg, u16 speed, u8 duplex)
979{
980 struct rtl8169_private *tp = netdev_priv(dev);
981 int ret;
982
983 ret = tp->set_speed(dev, autoneg, speed, duplex);
984
64e4bfb4 985 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 986 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
987
988 return ret;
989}
990
991static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
992{
993 struct rtl8169_private *tp = netdev_priv(dev);
994 unsigned long flags;
995 int ret;
996
997 spin_lock_irqsave(&tp->lock, flags);
998 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
999 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1000
1da177e4
LT		 1001 return ret;
1002}
1003
1004static u32 rtl8169_get_rx_csum(struct net_device *dev)
1005{
1006 struct rtl8169_private *tp = netdev_priv(dev);
1007
1008 return tp->cp_cmd & RxChkSum;
1009}
1010
1011static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1012{
1013 struct rtl8169_private *tp = netdev_priv(dev);
1014 void __iomem *ioaddr = tp->mmio_addr;
1015 unsigned long flags;
1016
1017 spin_lock_irqsave(&tp->lock, flags);
1018
1019 if (data)
1020 tp->cp_cmd |= RxChkSum;
1021 else
1022 tp->cp_cmd &= ~RxChkSum;
1023
1024 RTL_W16(CPlusCmd, tp->cp_cmd);
1025 RTL_R16(CPlusCmd);
1026
1027 spin_unlock_irqrestore(&tp->lock, flags);
1028
1029 return 0;
1030}
1031
1032#ifdef CONFIG_R8169_VLAN
1033
1034static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1035 struct sk_buff *skb)
1036{
eab6d18d 1037 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1038 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1039}
1040
1041static void rtl8169_vlan_rx_register(struct net_device *dev,
1042 struct vlan_group *grp)
1043{
1044 struct rtl8169_private *tp = netdev_priv(dev);
1045 void __iomem *ioaddr = tp->mmio_addr;
1046 unsigned long flags;
1047
1048 spin_lock_irqsave(&tp->lock, flags);
1049 tp->vlgrp = grp;
05af2142
SW		 1050 /*
1051 * Do not disable RxVlan on 8110SCd.
1052 */
1053 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1054 tp->cp_cmd |= RxVlan;
1055 else
1056 tp->cp_cmd &= ~RxVlan;
1057 RTL_W16(CPlusCmd, tp->cp_cmd);
1058 RTL_R16(CPlusCmd);
1059 spin_unlock_irqrestore(&tp->lock, flags);
1060}
1061
1da177e4 1062static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1063 struct sk_buff *skb, int polling)
1da177e4
LT		 1064{
1065 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1066 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1067 int ret;
1068
865c652d 1069 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1070 u16 vtag = swab16(opts2 & 0xffff);
1071
1072 if (likely(polling))
1073 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1074 else
1075 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1076 ret = 0;
1077 } else
1078 ret = -1;
1079 desc->opts2 = 0;
1080 return ret;
1081}
1082
1083#else /* !CONFIG_R8169_VLAN */
1084
1085static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1086 struct sk_buff *skb)
1087{
1088 return 0;
1089}
1090
1091static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1092 struct sk_buff *skb, int polling)
1da177e4
LT		 1093{
1094 return -1;
1095}
1096
1097#endif
1098
ccdffb9a 1099static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1100{
1101 struct rtl8169_private *tp = netdev_priv(dev);
1102 void __iomem *ioaddr = tp->mmio_addr;
1103 u32 status;
1104
1105 cmd->supported =
1106 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1107 cmd->port = PORT_FIBRE;
1108 cmd->transceiver = XCVR_INTERNAL;
1109
1110 status = RTL_R32(TBICSR);
1111 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1112 cmd->autoneg = !!(status & TBINwEnable);
1113
1114 cmd->speed = SPEED_1000;
1115 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1116
1117 return 0;
1da177e4
LT		 1118}
1119
ccdffb9a 1120static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1121{
1122 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1123
1124 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1125}
1126
1127static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1128{
1129 struct rtl8169_private *tp = netdev_priv(dev);
1130 unsigned long flags;
ccdffb9a 1131 int rc;
1da177e4
LT		 1132
1133 spin_lock_irqsave(&tp->lock, flags);
1134
ccdffb9a 1135 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1136
1137 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1138 return rc;
1da177e4
LT		 1139}
1140
1141static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1142 void *p)
1143{
5b0384f4
FR		 1144 struct rtl8169_private *tp = netdev_priv(dev);
1145 unsigned long flags;
1da177e4 1146
5b0384f4
FR		 1147 if (regs->len > R8169_REGS_SIZE)
1148 regs->len = R8169_REGS_SIZE;
1da177e4 1149
5b0384f4
FR		 1150 spin_lock_irqsave(&tp->lock, flags);
1151 memcpy_fromio(p, tp->mmio_addr, regs->len);
1152 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1153}
1154
b57b7e5a
SH		 1155static u32 rtl8169_get_msglevel(struct net_device *dev)
1156{
1157 struct rtl8169_private *tp = netdev_priv(dev);
1158
1159 return tp->msg_enable;
1160}
1161
1162static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1163{
1164 struct rtl8169_private *tp = netdev_priv(dev);
1165
1166 tp->msg_enable = value;
1167}
1168
d4a3a0fc
SH		 1169static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1170 "tx_packets",
1171 "rx_packets",
1172 "tx_errors",
1173 "rx_errors",
1174 "rx_missed",
1175 "align_errors",
1176 "tx_single_collisions",
1177 "tx_multi_collisions",
1178 "unicast",
1179 "broadcast",
1180 "multicast",
1181 "tx_aborted",
1182 "tx_underrun",
1183};
1184
b9f2c044 1185static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1186{
b9f2c044
JG		 1187 switch (sset) {
1188 case ETH_SS_STATS:
1189 return ARRAY_SIZE(rtl8169_gstrings);
1190 default:
1191 return -EOPNOTSUPP;
1192 }
d4a3a0fc
SH		 1193}
1194
355423d0 1195static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1196{
1197 struct rtl8169_private *tp = netdev_priv(dev);
1198 void __iomem *ioaddr = tp->mmio_addr;
1199 struct rtl8169_counters *counters;
1200 dma_addr_t paddr;
1201 u32 cmd;
355423d0 1202 int wait = 1000;
d4a3a0fc 1203
355423d0
IV		 1204 /*
1205 * Some chips are unable to dump tally counters when the receiver
1206 * is disabled.
1207 */
1208 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1209 return;
d4a3a0fc 1210
82553bb6
SG		 1211 counters = dma_alloc_coherent(&tp->pci_dev->dev, sizeof(*counters),
1212 &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1213 if (!counters)
1214 return;
1215
1216 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1217 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1218 RTL_W32(CounterAddrLow, cmd);
1219 RTL_W32(CounterAddrLow, cmd | CounterDump);
1220
355423d0
IV		 1221 while (wait--) {
1222 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1223 /* copy updated counters */
1224 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1225 break;
355423d0
IV		 1226 }
1227 udelay(10);
d4a3a0fc
SH		 1228 }
1229
1230 RTL_W32(CounterAddrLow, 0);
1231 RTL_W32(CounterAddrHigh, 0);
1232
82553bb6
SG		 1233 dma_free_coherent(&tp->pci_dev->dev, sizeof(*counters), counters,
1234 paddr);
d4a3a0fc
SH		 1235}
1236
355423d0
IV		 1237static void rtl8169_get_ethtool_stats(struct net_device *dev,
1238 struct ethtool_stats *stats, u64 *data)
1239{
1240 struct rtl8169_private *tp = netdev_priv(dev);
1241
1242 ASSERT_RTNL();
1243
1244 rtl8169_update_counters(dev);
1245
1246 data[0] = le64_to_cpu(tp->counters.tx_packets);
1247 data[1] = le64_to_cpu(tp->counters.rx_packets);
1248 data[2] = le64_to_cpu(tp->counters.tx_errors);
1249 data[3] = le32_to_cpu(tp->counters.rx_errors);
1250 data[4] = le16_to_cpu(tp->counters.rx_missed);
1251 data[5] = le16_to_cpu(tp->counters.align_errors);
1252 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1253 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1254 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1255 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1256 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1257 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1258 data[12] = le16_to_cpu(tp->counters.tx_underun);
1259}
1260
d4a3a0fc
SH		 1261static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1262{
1263 switch(stringset) {
1264 case ETH_SS_STATS:
1265 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1266 break;
1267 }
1268}
1269
7282d491 1270static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1271 .get_drvinfo = rtl8169_get_drvinfo,
1272 .get_regs_len = rtl8169_get_regs_len,
1273 .get_link = ethtool_op_get_link,
1274 .get_settings = rtl8169_get_settings,
1275 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1276 .get_msglevel = rtl8169_get_msglevel,
1277 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1278 .get_rx_csum = rtl8169_get_rx_csum,
1279 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1280 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1281 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1282 .set_tso = ethtool_op_set_tso,
1283 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1284 .get_wol = rtl8169_get_wol,
1285 .set_wol = rtl8169_set_wol,
d4a3a0fc 1286 .get_strings = rtl8169_get_strings,
b9f2c044 1287 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1288 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1289};
1290
07d3f51f
FR		 1291static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1292 void __iomem *ioaddr)
1da177e4 1293{
0e485150
FR		 1294 /*
1295 * The driver currently handles the 8168Bf and the 8168Be identically
1296 * but they can be identified more specifically through the test below
1297 * if needed:
1298 *
1299 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1300 *
1301 * Same thing for the 8101Eb and the 8101Ec:
1302 *
1303 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1304 */
350f7596 1305 static const struct {
1da177e4 1306 u32 mask;
e3cf0cc0 1307 u32 val;
1da177e4
LT		 1308 int mac_version;
1309 } mac_info[] = {
5b538df9 1310 /* 8168D family. */
daf9df6d 1311 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1312 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1313 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1314 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1315
ef808d50 1316 /* 8168C family. */
17c99297 1317 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1318 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1319 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1320 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1321 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1322 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1323 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1324 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1325 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1326
1327 /* 8168B family. */
1328 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1329 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1330 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1331 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1332
1333 /* 8101 family. */
2857ffb7
FR		 1334 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1335 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1336 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1337 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1338 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1339 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1340 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1341 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1342 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1343 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1344 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1345 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1346 /* FIXME: where did these entries come from ? -- FR */
1347 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1348 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1349
1350 /* 8110 family. */
1351 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1352 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1353 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1354 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1355 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1356 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1357
f21b75e9
JD		 1358 /* Catch-all */
1359 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1360 }, *p = mac_info;
1361 u32 reg;
1362
e3cf0cc0
FR		 1363 reg = RTL_R32(TxConfig);
1364 while ((reg & p->mask) != p->val)
1da177e4
LT		 1365 p++;
1366 tp->mac_version = p->mac_version;
1367}
1368
1369static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1370{
bcf0bf90 1371 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1372}
1373
867763c1
FR		 1374struct phy_reg {
1375 u16 reg;
1376 u16 val;
1377};
1378
350f7596 1379static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1380{
1381 while (len-- > 0) {
1382 mdio_write(ioaddr, regs->reg, regs->val);
1383 regs++;
1384 }
1385}
1386
5615d9f1 1387static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1388{
350f7596 1389 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1390 { 0x1f, 0x0001 },
1391 { 0x06, 0x006e },
1392 { 0x08, 0x0708 },
1393 { 0x15, 0x4000 },
1394 { 0x18, 0x65c7 },
1da177e4 1395
0b9b571d 1396 { 0x1f, 0x0001 },
1397 { 0x03, 0x00a1 },
1398 { 0x02, 0x0008 },
1399 { 0x01, 0x0120 },
1400 { 0x00, 0x1000 },
1401 { 0x04, 0x0800 },
1402 { 0x04, 0x0000 },
1da177e4 1403
0b9b571d 1404 { 0x03, 0xff41 },
1405 { 0x02, 0xdf60 },
1406 { 0x01, 0x0140 },
1407 { 0x00, 0x0077 },
1408 { 0x04, 0x7800 },
1409 { 0x04, 0x7000 },
1410
1411 { 0x03, 0x802f },
1412 { 0x02, 0x4f02 },
1413 { 0x01, 0x0409 },
1414 { 0x00, 0xf0f9 },
1415 { 0x04, 0x9800 },
1416 { 0x04, 0x9000 },
1417
1418 { 0x03, 0xdf01 },
1419 { 0x02, 0xdf20 },
1420 { 0x01, 0xff95 },
1421 { 0x00, 0xba00 },
1422 { 0x04, 0xa800 },
1423 { 0x04, 0xa000 },
1424
1425 { 0x03, 0xff41 },
1426 { 0x02, 0xdf20 },
1427 { 0x01, 0x0140 },
1428 { 0x00, 0x00bb },
1429 { 0x04, 0xb800 },
1430 { 0x04, 0xb000 },
1431
1432 { 0x03, 0xdf41 },
1433 { 0x02, 0xdc60 },
1434 { 0x01, 0x6340 },
1435 { 0x00, 0x007d },
1436 { 0x04, 0xd800 },
1437 { 0x04, 0xd000 },
1438
1439 { 0x03, 0xdf01 },
1440 { 0x02, 0xdf20 },
1441 { 0x01, 0x100a },
1442 { 0x00, 0xa0ff },
1443 { 0x04, 0xf800 },
1444 { 0x04, 0xf000 },
1445
1446 { 0x1f, 0x0000 },
1447 { 0x0b, 0x0000 },
1448 { 0x00, 0x9200 }
1449 };
1da177e4 1450
0b9b571d 1451 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1452}
1453
5615d9f1
FR		 1454static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1455{
350f7596 1456 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1457 { 0x1f, 0x0002 },
1458 { 0x01, 0x90d0 },
1459 { 0x1f, 0x0000 }
1460 };
1461
1462 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1463}
1464
2e955856 1465static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1466 void __iomem *ioaddr)
1467{
1468 struct pci_dev *pdev = tp->pci_dev;
1469 u16 vendor_id, device_id;
1470
1471 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1472 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1473
1474 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1475 return;
1476
1477 mdio_write(ioaddr, 0x1f, 0x0001);
1478 mdio_write(ioaddr, 0x10, 0xf01b);
1479 mdio_write(ioaddr, 0x1f, 0x0000);
1480}
1481
1482static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1483 void __iomem *ioaddr)
1484{
350f7596 1485 static const struct phy_reg phy_reg_init[] = {
2e955856 1486 { 0x1f, 0x0001 },
1487 { 0x04, 0x0000 },
1488 { 0x03, 0x00a1 },
1489 { 0x02, 0x0008 },
1490 { 0x01, 0x0120 },
1491 { 0x00, 0x1000 },
1492 { 0x04, 0x0800 },
1493 { 0x04, 0x9000 },
1494 { 0x03, 0x802f },
1495 { 0x02, 0x4f02 },
1496 { 0x01, 0x0409 },
1497 { 0x00, 0xf099 },
1498 { 0x04, 0x9800 },
1499 { 0x04, 0xa000 },
1500 { 0x03, 0xdf01 },
1501 { 0x02, 0xdf20 },
1502 { 0x01, 0xff95 },
1503 { 0x00, 0xba00 },
1504 { 0x04, 0xa800 },
1505 { 0x04, 0xf000 },
1506 { 0x03, 0xdf01 },
1507 { 0x02, 0xdf20 },
1508 { 0x01, 0x101a },
1509 { 0x00, 0xa0ff },
1510 { 0x04, 0xf800 },
1511 { 0x04, 0x0000 },
1512 { 0x1f, 0x0000 },
1513
1514 { 0x1f, 0x0001 },
1515 { 0x10, 0xf41b },
1516 { 0x14, 0xfb54 },
1517 { 0x18, 0xf5c7 },
1518 { 0x1f, 0x0000 },
1519
1520 { 0x1f, 0x0001 },
1521 { 0x17, 0x0cc0 },
1522 { 0x1f, 0x0000 }
1523 };
1524
1525 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1526
1527 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1528}
1529
8c7006aa 1530static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1531{
350f7596 1532 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1533 { 0x1f, 0x0001 },
1534 { 0x04, 0x0000 },
1535 { 0x03, 0x00a1 },
1536 { 0x02, 0x0008 },
1537 { 0x01, 0x0120 },
1538 { 0x00, 0x1000 },
1539 { 0x04, 0x0800 },
1540 { 0x04, 0x9000 },
1541 { 0x03, 0x802f },
1542 { 0x02, 0x4f02 },
1543 { 0x01, 0x0409 },
1544 { 0x00, 0xf099 },
1545 { 0x04, 0x9800 },
1546 { 0x04, 0xa000 },
1547 { 0x03, 0xdf01 },
1548 { 0x02, 0xdf20 },
1549 { 0x01, 0xff95 },
1550 { 0x00, 0xba00 },
1551 { 0x04, 0xa800 },
1552 { 0x04, 0xf000 },
1553 { 0x03, 0xdf01 },
1554 { 0x02, 0xdf20 },
1555 { 0x01, 0x101a },
1556 { 0x00, 0xa0ff },
1557 { 0x04, 0xf800 },
1558 { 0x04, 0x0000 },
1559 { 0x1f, 0x0000 },
1560
1561 { 0x1f, 0x0001 },
1562 { 0x0b, 0x8480 },
1563 { 0x1f, 0x0000 },
1564
1565 { 0x1f, 0x0001 },
1566 { 0x18, 0x67c7 },
1567 { 0x04, 0x2000 },
1568 { 0x03, 0x002f },
1569 { 0x02, 0x4360 },
1570 { 0x01, 0x0109 },
1571 { 0x00, 0x3022 },
1572 { 0x04, 0x2800 },
1573 { 0x1f, 0x0000 },
1574
1575 { 0x1f, 0x0001 },
1576 { 0x17, 0x0cc0 },
1577 { 0x1f, 0x0000 }
1578 };
1579
1580 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1581}
1582
236b8082
FR		 1583static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1584{
350f7596 1585 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1586 { 0x10, 0xf41b },
1587 { 0x1f, 0x0000 }
1588 };
1589
1590 mdio_write(ioaddr, 0x1f, 0x0001);
1591 mdio_patch(ioaddr, 0x16, 1 << 0);
1592
1593 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1594}
1595
1596static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1597{
350f7596 1598 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1599 { 0x1f, 0x0001 },
1600 { 0x10, 0xf41b },
1601 { 0x1f, 0x0000 }
1602 };
1603
1604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1605}
1606
ef3386f0 1607static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1608{
350f7596 1609 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1610 { 0x1f, 0x0000 },
1611 { 0x1d, 0x0f00 },
1612 { 0x1f, 0x0002 },
1613 { 0x0c, 0x1ec8 },
1614 { 0x1f, 0x0000 }
1615 };
1616
1617 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1618}
1619
ef3386f0
FR		 1620static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1621{
350f7596 1622 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1623 { 0x1f, 0x0001 },
1624 { 0x1d, 0x3d98 },
1625 { 0x1f, 0x0000 }
1626 };
1627
1628 mdio_write(ioaddr, 0x1f, 0x0000);
1629 mdio_patch(ioaddr, 0x14, 1 << 5);
1630 mdio_patch(ioaddr, 0x0d, 1 << 5);
1631
1632 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1633}
1634
219a1e9d 1635static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1636{
350f7596 1637 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1638 { 0x1f, 0x0001 },
1639 { 0x12, 0x2300 },
867763c1
FR		 1640 { 0x1f, 0x0002 },
1641 { 0x00, 0x88d4 },
1642 { 0x01, 0x82b1 },
1643 { 0x03, 0x7002 },
1644 { 0x08, 0x9e30 },
1645 { 0x09, 0x01f0 },
1646 { 0x0a, 0x5500 },
1647 { 0x0c, 0x00c8 },
1648 { 0x1f, 0x0003 },
1649 { 0x12, 0xc096 },
1650 { 0x16, 0x000a },
f50d4275
FR		 1651 { 0x1f, 0x0000 },
1652 { 0x1f, 0x0000 },
1653 { 0x09, 0x2000 },
1654 { 0x09, 0x0000 }
867763c1
FR		 1655 };
1656
1657 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1658
1659 mdio_patch(ioaddr, 0x14, 1 << 5);
1660 mdio_patch(ioaddr, 0x0d, 1 << 5);
1661 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1662}
1663
219a1e9d 1664static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1665{
350f7596 1666 static const struct phy_reg phy_reg_init[] = {
f50d4275 1667 { 0x1f, 0x0001 },
7da97ec9 1668 { 0x12, 0x2300 },
f50d4275
FR		 1669 { 0x03, 0x802f },
1670 { 0x02, 0x4f02 },
1671 { 0x01, 0x0409 },
1672 { 0x00, 0xf099 },
1673 { 0x04, 0x9800 },
1674 { 0x04, 0x9000 },
1675 { 0x1d, 0x3d98 },
7da97ec9
FR		 1676 { 0x1f, 0x0002 },
1677 { 0x0c, 0x7eb8 },
f50d4275
FR		 1678 { 0x06, 0x0761 },
1679 { 0x1f, 0x0003 },
1680 { 0x16, 0x0f0a },
7da97ec9
FR		 1681 { 0x1f, 0x0000 }
1682 };
1683
1684 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1685
1686 mdio_patch(ioaddr, 0x16, 1 << 0);
1687 mdio_patch(ioaddr, 0x14, 1 << 5);
1688 mdio_patch(ioaddr, 0x0d, 1 << 5);
1689 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1690}
1691
197ff761
FR		 1692static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1693{
350f7596 1694 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1695 { 0x1f, 0x0001 },
1696 { 0x12, 0x2300 },
1697 { 0x1d, 0x3d98 },
1698 { 0x1f, 0x0002 },
1699 { 0x0c, 0x7eb8 },
1700 { 0x06, 0x5461 },
1701 { 0x1f, 0x0003 },
1702 { 0x16, 0x0f0a },
1703 { 0x1f, 0x0000 }
1704 };
1705
1706 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1707
1708 mdio_patch(ioaddr, 0x16, 1 << 0);
1709 mdio_patch(ioaddr, 0x14, 1 << 5);
1710 mdio_patch(ioaddr, 0x0d, 1 << 5);
1711 mdio_write(ioaddr, 0x1f, 0x0000);
1712}
1713
6fb07058
FR		 1714static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1715{
1716 rtl8168c_3_hw_phy_config(ioaddr);
1717}
1718
daf9df6d 1719static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1720{
350f7596 1721 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1722 { 0x1f, 0x0001 },
daf9df6d 1723 { 0x06, 0x4064 },
1724 { 0x07, 0x2863 },
1725 { 0x08, 0x059c },
1726 { 0x09, 0x26b4 },
1727 { 0x0a, 0x6a19 },
1728 { 0x0b, 0xdcc8 },
1729 { 0x10, 0xf06d },
1730 { 0x14, 0x7f68 },
1731 { 0x18, 0x7fd9 },
1732 { 0x1c, 0xf0ff },
1733 { 0x1d, 0x3d9c },
5b538df9 1734 { 0x1f, 0x0003 },
daf9df6d 1735 { 0x12, 0xf49f },
1736 { 0x13, 0x070b },
1737 { 0x1a, 0x05ad },
1738 { 0x14, 0x94c0 }
1739 };
350f7596 1740 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1741 { 0x1f, 0x0002 },
daf9df6d 1742 { 0x06, 0x5561 },
1743 { 0x1f, 0x0005 },
1744 { 0x05, 0x8332 },
1745 { 0x06, 0x5561 }
1746 };
350f7596 1747 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1748 { 0x1f, 0x0005 },
1749 { 0x05, 0xffc2 },
1750 { 0x1f, 0x0005 },
1751 { 0x05, 0x8000 },
1752 { 0x06, 0xf8f9 },
1753 { 0x06, 0xfaef },
1754 { 0x06, 0x59ee },
1755 { 0x06, 0xf8ea },
1756 { 0x06, 0x00ee },
1757 { 0x06, 0xf8eb },
1758 { 0x06, 0x00e0 },
1759 { 0x06, 0xf87c },
1760 { 0x06, 0xe1f8 },
1761 { 0x06, 0x7d59 },
1762 { 0x06, 0x0fef },
1763 { 0x06, 0x0139 },
1764 { 0x06, 0x029e },
1765 { 0x06, 0x06ef },
1766 { 0x06, 0x1039 },
1767 { 0x06, 0x089f },
1768 { 0x06, 0x2aee },
1769 { 0x06, 0xf8ea },
1770 { 0x06, 0x00ee },
1771 { 0x06, 0xf8eb },
1772 { 0x06, 0x01e0 },
1773 { 0x06, 0xf87c },
1774 { 0x06, 0xe1f8 },
1775 { 0x06, 0x7d58 },
1776 { 0x06, 0x409e },
1777 { 0x06, 0x0f39 },
1778 { 0x06, 0x46aa },
1779 { 0x06, 0x0bbf },
1780 { 0x06, 0x8290 },
1781 { 0x06, 0xd682 },
1782 { 0x06, 0x9802 },
1783 { 0x06, 0x014f },
1784 { 0x06, 0xae09 },
1785 { 0x06, 0xbf82 },
1786 { 0x06, 0x98d6 },
1787 { 0x06, 0x82a0 },
1788 { 0x06, 0x0201 },
1789 { 0x06, 0x4fef },
1790 { 0x06, 0x95fe },
1791 { 0x06, 0xfdfc },
1792 { 0x06, 0x05f8 },
1793 { 0x06, 0xf9fa },
1794 { 0x06, 0xeef8 },
1795 { 0x06, 0xea00 },
1796 { 0x06, 0xeef8 },
1797 { 0x06, 0xeb00 },
1798 { 0x06, 0xe2f8 },
1799 { 0x06, 0x7ce3 },
1800 { 0x06, 0xf87d },
1801 { 0x06, 0xa511 },
1802 { 0x06, 0x1112 },
1803 { 0x06, 0xd240 },
1804 { 0x06, 0xd644 },
1805 { 0x06, 0x4402 },
1806 { 0x06, 0x8217 },
1807 { 0x06, 0xd2a0 },
1808 { 0x06, 0xd6aa },
1809 { 0x06, 0xaa02 },
1810 { 0x06, 0x8217 },
1811 { 0x06, 0xae0f },
1812 { 0x06, 0xa544 },
1813 { 0x06, 0x4402 },
1814 { 0x06, 0xae4d },
1815 { 0x06, 0xa5aa },
1816 { 0x06, 0xaa02 },
1817 { 0x06, 0xae47 },
1818 { 0x06, 0xaf82 },
1819 { 0x06, 0x13ee },
1820 { 0x06, 0x834e },
1821 { 0x06, 0x00ee },
1822 { 0x06, 0x834d },
1823 { 0x06, 0x0fee },
1824 { 0x06, 0x834c },
1825 { 0x06, 0x0fee },
1826 { 0x06, 0x834f },
1827 { 0x06, 0x00ee },
1828 { 0x06, 0x8351 },
1829 { 0x06, 0x00ee },
1830 { 0x06, 0x834a },
1831 { 0x06, 0xffee },
1832 { 0x06, 0x834b },
1833 { 0x06, 0xffe0 },
1834 { 0x06, 0x8330 },
1835 { 0x06, 0xe183 },
1836 { 0x06, 0x3158 },
1837 { 0x06, 0xfee4 },
1838 { 0x06, 0xf88a },
1839 { 0x06, 0xe5f8 },
1840 { 0x06, 0x8be0 },
1841 { 0x06, 0x8332 },
1842 { 0x06, 0xe183 },
1843 { 0x06, 0x3359 },
1844 { 0x06, 0x0fe2 },
1845 { 0x06, 0x834d },
1846 { 0x06, 0x0c24 },
1847 { 0x06, 0x5af0 },
1848 { 0x06, 0x1e12 },
1849 { 0x06, 0xe4f8 },
1850 { 0x06, 0x8ce5 },
1851 { 0x06, 0xf88d },
1852 { 0x06, 0xaf82 },
1853 { 0x06, 0x13e0 },
1854 { 0x06, 0x834f },
1855 { 0x06, 0x10e4 },
1856 { 0x06, 0x834f },
1857 { 0x06, 0xe083 },
1858 { 0x06, 0x4e78 },
1859 { 0x06, 0x009f },
1860 { 0x06, 0x0ae0 },
1861 { 0x06, 0x834f },
1862 { 0x06, 0xa010 },
1863 { 0x06, 0xa5ee },
1864 { 0x06, 0x834e },
1865 { 0x06, 0x01e0 },
1866 { 0x06, 0x834e },
1867 { 0x06, 0x7805 },
1868 { 0x06, 0x9e9a },
1869 { 0x06, 0xe083 },
1870 { 0x06, 0x4e78 },
1871 { 0x06, 0x049e },
1872 { 0x06, 0x10e0 },
1873 { 0x06, 0x834e },
1874 { 0x06, 0x7803 },
1875 { 0x06, 0x9e0f },
1876 { 0x06, 0xe083 },
1877 { 0x06, 0x4e78 },
1878 { 0x06, 0x019e },
1879 { 0x06, 0x05ae },
1880 { 0x06, 0x0caf },
1881 { 0x06, 0x81f8 },
1882 { 0x06, 0xaf81 },
1883 { 0x06, 0xa3af },
1884 { 0x06, 0x81dc },
1885 { 0x06, 0xaf82 },
1886 { 0x06, 0x13ee },
1887 { 0x06, 0x8348 },
1888 { 0x06, 0x00ee },
1889 { 0x06, 0x8349 },
1890 { 0x06, 0x00e0 },
1891 { 0x06, 0x8351 },
1892 { 0x06, 0x10e4 },
1893 { 0x06, 0x8351 },
1894 { 0x06, 0x5801 },
1895 { 0x06, 0x9fea },
1896 { 0x06, 0xd000 },
1897 { 0x06, 0xd180 },
1898 { 0x06, 0x1f66 },
1899 { 0x06, 0xe2f8 },
1900 { 0x06, 0xeae3 },
1901 { 0x06, 0xf8eb },
1902 { 0x06, 0x5af8 },
1903 { 0x06, 0x1e20 },
1904 { 0x06, 0xe6f8 },
1905 { 0x06, 0xeae5 },
1906 { 0x06, 0xf8eb },
1907 { 0x06, 0xd302 },
1908 { 0x06, 0xb3fe },
1909 { 0x06, 0xe2f8 },
1910 { 0x06, 0x7cef },
1911 { 0x06, 0x325b },
1912 { 0x06, 0x80e3 },
1913 { 0x06, 0xf87d },
1914 { 0x06, 0x9e03 },
1915 { 0x06, 0x7dff },
1916 { 0x06, 0xff0d },
1917 { 0x06, 0x581c },
1918 { 0x06, 0x551a },
1919 { 0x06, 0x6511 },
1920 { 0x06, 0xa190 },
1921 { 0x06, 0xd3e2 },
1922 { 0x06, 0x8348 },
1923 { 0x06, 0xe383 },
1924 { 0x06, 0x491b },
1925 { 0x06, 0x56ab },
1926 { 0x06, 0x08ef },
1927 { 0x06, 0x56e6 },
1928 { 0x06, 0x8348 },
1929 { 0x06, 0xe783 },
1930 { 0x06, 0x4910 },
1931 { 0x06, 0xd180 },
1932 { 0x06, 0x1f66 },
1933 { 0x06, 0xa004 },
1934 { 0x06, 0xb9e2 },
1935 { 0x06, 0x8348 },
1936 { 0x06, 0xe383 },
1937 { 0x06, 0x49ef },
1938 { 0x06, 0x65e2 },
1939 { 0x06, 0x834a },
1940 { 0x06, 0xe383 },
1941 { 0x06, 0x4b1b },
1942 { 0x06, 0x56aa },
1943 { 0x06, 0x0eef },
1944 { 0x06, 0x56e6 },
1945 { 0x06, 0x834a },
1946 { 0x06, 0xe783 },
1947 { 0x06, 0x4be2 },
1948 { 0x06, 0x834d },
1949 { 0x06, 0xe683 },
1950 { 0x06, 0x4ce0 },
1951 { 0x06, 0x834d },
1952 { 0x06, 0xa000 },
1953 { 0x06, 0x0caf },
1954 { 0x06, 0x81dc },
1955 { 0x06, 0xe083 },
1956 { 0x06, 0x4d10 },
1957 { 0x06, 0xe483 },
1958 { 0x06, 0x4dae },
1959 { 0x06, 0x0480 },
1960 { 0x06, 0xe483 },
1961 { 0x06, 0x4de0 },
1962 { 0x06, 0x834e },
1963 { 0x06, 0x7803 },
1964 { 0x06, 0x9e0b },
1965 { 0x06, 0xe083 },
1966 { 0x06, 0x4e78 },
1967 { 0x06, 0x049e },
1968 { 0x06, 0x04ee },
1969 { 0x06, 0x834e },
1970 { 0x06, 0x02e0 },
1971 { 0x06, 0x8332 },
1972 { 0x06, 0xe183 },
1973 { 0x06, 0x3359 },
1974 { 0x06, 0x0fe2 },
1975 { 0x06, 0x834d },
1976 { 0x06, 0x0c24 },
1977 { 0x06, 0x5af0 },
1978 { 0x06, 0x1e12 },
1979 { 0x06, 0xe4f8 },
1980 { 0x06, 0x8ce5 },
1981 { 0x06, 0xf88d },
1982 { 0x06, 0xe083 },
1983 { 0x06, 0x30e1 },
1984 { 0x06, 0x8331 },
1985 { 0x06, 0x6801 },
1986 { 0x06, 0xe4f8 },
1987 { 0x06, 0x8ae5 },
1988 { 0x06, 0xf88b },
1989 { 0x06, 0xae37 },
1990 { 0x06, 0xee83 },
1991 { 0x06, 0x4e03 },
1992 { 0x06, 0xe083 },
1993 { 0x06, 0x4ce1 },
1994 { 0x06, 0x834d },
1995 { 0x06, 0x1b01 },
1996 { 0x06, 0x9e04 },
1997 { 0x06, 0xaaa1 },
1998 { 0x06, 0xaea8 },
1999 { 0x06, 0xee83 },
2000 { 0x06, 0x4e04 },
2001 { 0x06, 0xee83 },
2002 { 0x06, 0x4f00 },
2003 { 0x06, 0xaeab },
2004 { 0x06, 0xe083 },
2005 { 0x06, 0x4f78 },
2006 { 0x06, 0x039f },
2007 { 0x06, 0x14ee },
2008 { 0x06, 0x834e },
2009 { 0x06, 0x05d2 },
2010 { 0x06, 0x40d6 },
2011 { 0x06, 0x5554 },
2012 { 0x06, 0x0282 },
2013 { 0x06, 0x17d2 },
2014 { 0x06, 0xa0d6 },
2015 { 0x06, 0xba00 },
2016 { 0x06, 0x0282 },
2017 { 0x06, 0x17fe },
2018 { 0x06, 0xfdfc },
2019 { 0x06, 0x05f8 },
2020 { 0x06, 0xe0f8 },
2021 { 0x06, 0x60e1 },
2022 { 0x06, 0xf861 },
2023 { 0x06, 0x6802 },
2024 { 0x06, 0xe4f8 },
2025 { 0x06, 0x60e5 },
2026 { 0x06, 0xf861 },
2027 { 0x06, 0xe0f8 },
2028 { 0x06, 0x48e1 },
2029 { 0x06, 0xf849 },
2030 { 0x06, 0x580f },
2031 { 0x06, 0x1e02 },
2032 { 0x06, 0xe4f8 },
2033 { 0x06, 0x48e5 },
2034 { 0x06, 0xf849 },
2035 { 0x06, 0xd000 },
2036 { 0x06, 0x0282 },
2037 { 0x06, 0x5bbf },
2038 { 0x06, 0x8350 },
2039 { 0x06, 0xef46 },
2040 { 0x06, 0xdc19 },
2041 { 0x06, 0xddd0 },
2042 { 0x06, 0x0102 },
2043 { 0x06, 0x825b },
2044 { 0x06, 0x0282 },
2045 { 0x06, 0x77e0 },
2046 { 0x06, 0xf860 },
2047 { 0x06, 0xe1f8 },
2048 { 0x06, 0x6158 },
2049 { 0x06, 0xfde4 },
2050 { 0x06, 0xf860 },
2051 { 0x06, 0xe5f8 },
2052 { 0x06, 0x61fc },
2053 { 0x06, 0x04f9 },
2054 { 0x06, 0xfafb },
2055 { 0x06, 0xc6bf },
2056 { 0x06, 0xf840 },
2057 { 0x06, 0xbe83 },
2058 { 0x06, 0x50a0 },
2059 { 0x06, 0x0101 },
2060 { 0x06, 0x071b },
2061 { 0x06, 0x89cf },
2062 { 0x06, 0xd208 },
2063 { 0x06, 0xebdb },
2064 { 0x06, 0x19b2 },
2065 { 0x06, 0xfbff },
2066 { 0x06, 0xfefd },
2067 { 0x06, 0x04f8 },
2068 { 0x06, 0xe0f8 },
2069 { 0x06, 0x48e1 },
2070 { 0x06, 0xf849 },
2071 { 0x06, 0x6808 },
2072 { 0x06, 0xe4f8 },
2073 { 0x06, 0x48e5 },
2074 { 0x06, 0xf849 },
2075 { 0x06, 0x58f7 },
2076 { 0x06, 0xe4f8 },
2077 { 0x06, 0x48e5 },
2078 { 0x06, 0xf849 },
2079 { 0x06, 0xfc04 },
2080 { 0x06, 0x4d20 },
2081 { 0x06, 0x0002 },
2082 { 0x06, 0x4e22 },
2083 { 0x06, 0x0002 },
2084 { 0x06, 0x4ddf },
2085 { 0x06, 0xff01 },
2086 { 0x06, 0x4edd },
2087 { 0x06, 0xff01 },
2088 { 0x05, 0x83d4 },
2089 { 0x06, 0x8000 },
2090 { 0x05, 0x83d8 },
2091 { 0x06, 0x8051 },
2092 { 0x02, 0x6010 },
2093 { 0x03, 0xdc00 },
2094 { 0x05, 0xfff6 },
2095 { 0x06, 0x00fc },
5b538df9 2096 { 0x1f, 0x0000 },
daf9df6d 2097
5b538df9 2098 { 0x1f, 0x0000 },
daf9df6d 2099 { 0x0d, 0xf880 },
2100 { 0x1f, 0x0000 }
2101 };
2102
2103 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2104
2105 mdio_write(ioaddr, 0x1f, 0x0002);
2106 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2107 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2108
2109 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2110
2111 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2112 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2113 { 0x1f, 0x0002 },
2114 { 0x05, 0x669a },
2115 { 0x1f, 0x0005 },
2116 { 0x05, 0x8330 },
2117 { 0x06, 0x669a },
2118 { 0x1f, 0x0002 }
2119 };
2120 int val;
2121
2122 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2123
2124 val = mdio_read(ioaddr, 0x0d);
2125
2126 if ((val & 0x00ff) != 0x006c) {
350f7596 2127 static const u32 set[] = {
daf9df6d 2128 0x0065, 0x0066, 0x0067, 0x0068,
2129 0x0069, 0x006a, 0x006b, 0x006c
2130 };
2131 int i;
2132
2133 mdio_write(ioaddr, 0x1f, 0x0002);
2134
2135 val &= 0xff00;
2136 for (i = 0; i < ARRAY_SIZE(set); i++)
2137 mdio_write(ioaddr, 0x0d, val | set[i]);
2138 }
2139 } else {
350f7596 2140 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2141 { 0x1f, 0x0002 },
2142 { 0x05, 0x6662 },
2143 { 0x1f, 0x0005 },
2144 { 0x05, 0x8330 },
2145 { 0x06, 0x6662 }
2146 };
2147
2148 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2149 }
2150
2151 mdio_write(ioaddr, 0x1f, 0x0002);
2152 mdio_patch(ioaddr, 0x0d, 0x0300);
2153 mdio_patch(ioaddr, 0x0f, 0x0010);
2154
2155 mdio_write(ioaddr, 0x1f, 0x0002);
2156 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2157 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2158
2159 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2160}
2161
2162static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2163{
350f7596 2164 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2165 { 0x1f, 0x0001 },
2166 { 0x06, 0x4064 },
2167 { 0x07, 0x2863 },
2168 { 0x08, 0x059c },
2169 { 0x09, 0x26b4 },
2170 { 0x0a, 0x6a19 },
2171 { 0x0b, 0xdcc8 },
2172 { 0x10, 0xf06d },
2173 { 0x14, 0x7f68 },
2174 { 0x18, 0x7fd9 },
2175 { 0x1c, 0xf0ff },
2176 { 0x1d, 0x3d9c },
2177 { 0x1f, 0x0003 },
2178 { 0x12, 0xf49f },
2179 { 0x13, 0x070b },
2180 { 0x1a, 0x05ad },
2181 { 0x14, 0x94c0 },
2182
2183 { 0x1f, 0x0002 },
2184 { 0x06, 0x5561 },
2185 { 0x1f, 0x0005 },
2186 { 0x05, 0x8332 },
2187 { 0x06, 0x5561 }
2188 };
350f7596 2189 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2190 { 0x1f, 0x0005 },
2191 { 0x05, 0xffc2 },
5b538df9 2192 { 0x1f, 0x0005 },
daf9df6d 2193 { 0x05, 0x8000 },
2194 { 0x06, 0xf8f9 },
2195 { 0x06, 0xfaee },
2196 { 0x06, 0xf8ea },
2197 { 0x06, 0x00ee },
2198 { 0x06, 0xf8eb },
2199 { 0x06, 0x00e2 },
2200 { 0x06, 0xf87c },
2201 { 0x06, 0xe3f8 },
2202 { 0x06, 0x7da5 },
2203 { 0x06, 0x1111 },
2204 { 0x06, 0x12d2 },
2205 { 0x06, 0x40d6 },
2206 { 0x06, 0x4444 },
2207 { 0x06, 0x0281 },
2208 { 0x06, 0xc6d2 },
2209 { 0x06, 0xa0d6 },
2210 { 0x06, 0xaaaa },
2211 { 0x06, 0x0281 },
2212 { 0x06, 0xc6ae },
2213 { 0x06, 0x0fa5 },
2214 { 0x06, 0x4444 },
2215 { 0x06, 0x02ae },
2216 { 0x06, 0x4da5 },
2217 { 0x06, 0xaaaa },
2218 { 0x06, 0x02ae },
2219 { 0x06, 0x47af },
2220 { 0x06, 0x81c2 },
2221 { 0x06, 0xee83 },
2222 { 0x06, 0x4e00 },
2223 { 0x06, 0xee83 },
2224 { 0x06, 0x4d0f },
2225 { 0x06, 0xee83 },
2226 { 0x06, 0x4c0f },
2227 { 0x06, 0xee83 },
2228 { 0x06, 0x4f00 },
2229 { 0x06, 0xee83 },
2230 { 0x06, 0x5100 },
2231 { 0x06, 0xee83 },
2232 { 0x06, 0x4aff },
2233 { 0x06, 0xee83 },
2234 { 0x06, 0x4bff },
2235 { 0x06, 0xe083 },
2236 { 0x06, 0x30e1 },
2237 { 0x06, 0x8331 },
2238 { 0x06, 0x58fe },
2239 { 0x06, 0xe4f8 },
2240 { 0x06, 0x8ae5 },
2241 { 0x06, 0xf88b },
2242 { 0x06, 0xe083 },
2243 { 0x06, 0x32e1 },
2244 { 0x06, 0x8333 },
2245 { 0x06, 0x590f },
2246 { 0x06, 0xe283 },
2247 { 0x06, 0x4d0c },
2248 { 0x06, 0x245a },
2249 { 0x06, 0xf01e },
2250 { 0x06, 0x12e4 },
2251 { 0x06, 0xf88c },
2252 { 0x06, 0xe5f8 },
2253 { 0x06, 0x8daf },
2254 { 0x06, 0x81c2 },
2255 { 0x06, 0xe083 },
2256 { 0x06, 0x4f10 },
2257 { 0x06, 0xe483 },
2258 { 0x06, 0x4fe0 },
2259 { 0x06, 0x834e },
2260 { 0x06, 0x7800 },
2261 { 0x06, 0x9f0a },
2262 { 0x06, 0xe083 },
2263 { 0x06, 0x4fa0 },
2264 { 0x06, 0x10a5 },
2265 { 0x06, 0xee83 },
2266 { 0x06, 0x4e01 },
2267 { 0x06, 0xe083 },
2268 { 0x06, 0x4e78 },
2269 { 0x06, 0x059e },
2270 { 0x06, 0x9ae0 },
2271 { 0x06, 0x834e },
2272 { 0x06, 0x7804 },
2273 { 0x06, 0x9e10 },
2274 { 0x06, 0xe083 },
2275 { 0x06, 0x4e78 },
2276 { 0x06, 0x039e },
2277 { 0x06, 0x0fe0 },
2278 { 0x06, 0x834e },
2279 { 0x06, 0x7801 },
2280 { 0x06, 0x9e05 },
2281 { 0x06, 0xae0c },
2282 { 0x06, 0xaf81 },
2283 { 0x06, 0xa7af },
2284 { 0x06, 0x8152 },
2285 { 0x06, 0xaf81 },
2286 { 0x06, 0x8baf },
2287 { 0x06, 0x81c2 },
2288 { 0x06, 0xee83 },
2289 { 0x06, 0x4800 },
2290 { 0x06, 0xee83 },
2291 { 0x06, 0x4900 },
2292 { 0x06, 0xe083 },
2293 { 0x06, 0x5110 },
2294 { 0x06, 0xe483 },
2295 { 0x06, 0x5158 },
2296 { 0x06, 0x019f },
2297 { 0x06, 0xead0 },
2298 { 0x06, 0x00d1 },
2299 { 0x06, 0x801f },
2300 { 0x06, 0x66e2 },
2301 { 0x06, 0xf8ea },
2302 { 0x06, 0xe3f8 },
2303 { 0x06, 0xeb5a },
2304 { 0x06, 0xf81e },
2305 { 0x06, 0x20e6 },
2306 { 0x06, 0xf8ea },
2307 { 0x06, 0xe5f8 },
2308 { 0x06, 0xebd3 },
2309 { 0x06, 0x02b3 },
2310 { 0x06, 0xfee2 },
2311 { 0x06, 0xf87c },
2312 { 0x06, 0xef32 },
2313 { 0x06, 0x5b80 },
2314 { 0x06, 0xe3f8 },
2315 { 0x06, 0x7d9e },
2316 { 0x06, 0x037d },
2317 { 0x06, 0xffff },
2318 { 0x06, 0x0d58 },
2319 { 0x06, 0x1c55 },
2320 { 0x06, 0x1a65 },
2321 { 0x06, 0x11a1 },
2322 { 0x06, 0x90d3 },
2323 { 0x06, 0xe283 },
2324 { 0x06, 0x48e3 },
2325 { 0x06, 0x8349 },
2326 { 0x06, 0x1b56 },
2327 { 0x06, 0xab08 },
2328 { 0x06, 0xef56 },
2329 { 0x06, 0xe683 },
2330 { 0x06, 0x48e7 },
2331 { 0x06, 0x8349 },
2332 { 0x06, 0x10d1 },
2333 { 0x06, 0x801f },
2334 { 0x06, 0x66a0 },
2335 { 0x06, 0x04b9 },
2336 { 0x06, 0xe283 },
2337 { 0x06, 0x48e3 },
2338 { 0x06, 0x8349 },
2339 { 0x06, 0xef65 },
2340 { 0x06, 0xe283 },
2341 { 0x06, 0x4ae3 },
2342 { 0x06, 0x834b },
2343 { 0x06, 0x1b56 },
2344 { 0x06, 0xaa0e },
2345 { 0x06, 0xef56 },
2346 { 0x06, 0xe683 },
2347 { 0x06, 0x4ae7 },
2348 { 0x06, 0x834b },
2349 { 0x06, 0xe283 },
2350 { 0x06, 0x4de6 },
2351 { 0x06, 0x834c },
2352 { 0x06, 0xe083 },
2353 { 0x06, 0x4da0 },
2354 { 0x06, 0x000c },
2355 { 0x06, 0xaf81 },
2356 { 0x06, 0x8be0 },
2357 { 0x06, 0x834d },
2358 { 0x06, 0x10e4 },
2359 { 0x06, 0x834d },
2360 { 0x06, 0xae04 },
2361 { 0x06, 0x80e4 },
2362 { 0x06, 0x834d },
2363 { 0x06, 0xe083 },
2364 { 0x06, 0x4e78 },
2365 { 0x06, 0x039e },
2366 { 0x06, 0x0be0 },
2367 { 0x06, 0x834e },
2368 { 0x06, 0x7804 },
2369 { 0x06, 0x9e04 },
2370 { 0x06, 0xee83 },
2371 { 0x06, 0x4e02 },
2372 { 0x06, 0xe083 },
2373 { 0x06, 0x32e1 },
2374 { 0x06, 0x8333 },
2375 { 0x06, 0x590f },
2376 { 0x06, 0xe283 },
2377 { 0x06, 0x4d0c },
2378 { 0x06, 0x245a },
2379 { 0x06, 0xf01e },
2380 { 0x06, 0x12e4 },
2381 { 0x06, 0xf88c },
2382 { 0x06, 0xe5f8 },
2383 { 0x06, 0x8de0 },
2384 { 0x06, 0x8330 },
2385 { 0x06, 0xe183 },
2386 { 0x06, 0x3168 },
2387 { 0x06, 0x01e4 },
2388 { 0x06, 0xf88a },
2389 { 0x06, 0xe5f8 },
2390 { 0x06, 0x8bae },
2391 { 0x06, 0x37ee },
2392 { 0x06, 0x834e },
2393 { 0x06, 0x03e0 },
2394 { 0x06, 0x834c },
2395 { 0x06, 0xe183 },
2396 { 0x06, 0x4d1b },
2397 { 0x06, 0x019e },
2398 { 0x06, 0x04aa },
2399 { 0x06, 0xa1ae },
2400 { 0x06, 0xa8ee },
2401 { 0x06, 0x834e },
2402 { 0x06, 0x04ee },
2403 { 0x06, 0x834f },
2404 { 0x06, 0x00ae },
2405 { 0x06, 0xabe0 },
2406 { 0x06, 0x834f },
2407 { 0x06, 0x7803 },
2408 { 0x06, 0x9f14 },
2409 { 0x06, 0xee83 },
2410 { 0x06, 0x4e05 },
2411 { 0x06, 0xd240 },
2412 { 0x06, 0xd655 },
2413 { 0x06, 0x5402 },
2414 { 0x06, 0x81c6 },
2415 { 0x06, 0xd2a0 },
2416 { 0x06, 0xd6ba },
2417 { 0x06, 0x0002 },
2418 { 0x06, 0x81c6 },
2419 { 0x06, 0xfefd },
2420 { 0x06, 0xfc05 },
2421 { 0x06, 0xf8e0 },
2422 { 0x06, 0xf860 },
2423 { 0x06, 0xe1f8 },
2424 { 0x06, 0x6168 },
2425 { 0x06, 0x02e4 },
2426 { 0x06, 0xf860 },
2427 { 0x06, 0xe5f8 },
2428 { 0x06, 0x61e0 },
2429 { 0x06, 0xf848 },
2430 { 0x06, 0xe1f8 },
2431 { 0x06, 0x4958 },
2432 { 0x06, 0x0f1e },
2433 { 0x06, 0x02e4 },
2434 { 0x06, 0xf848 },
2435 { 0x06, 0xe5f8 },
2436 { 0x06, 0x49d0 },
2437 { 0x06, 0x0002 },
2438 { 0x06, 0x820a },
2439 { 0x06, 0xbf83 },
2440 { 0x06, 0x50ef },
2441 { 0x06, 0x46dc },
2442 { 0x06, 0x19dd },
2443 { 0x06, 0xd001 },
2444 { 0x06, 0x0282 },
2445 { 0x06, 0x0a02 },
2446 { 0x06, 0x8226 },
2447 { 0x06, 0xe0f8 },
2448 { 0x06, 0x60e1 },
2449 { 0x06, 0xf861 },
2450 { 0x06, 0x58fd },
2451 { 0x06, 0xe4f8 },
2452 { 0x06, 0x60e5 },
2453 { 0x06, 0xf861 },
2454 { 0x06, 0xfc04 },
2455 { 0x06, 0xf9fa },
2456 { 0x06, 0xfbc6 },
2457 { 0x06, 0xbff8 },
2458 { 0x06, 0x40be },
2459 { 0x06, 0x8350 },
2460 { 0x06, 0xa001 },
2461 { 0x06, 0x0107 },
2462 { 0x06, 0x1b89 },
2463 { 0x06, 0xcfd2 },
2464 { 0x06, 0x08eb },
2465 { 0x06, 0xdb19 },
2466 { 0x06, 0xb2fb },
2467 { 0x06, 0xfffe },
2468 { 0x06, 0xfd04 },
2469 { 0x06, 0xf8e0 },
2470 { 0x06, 0xf848 },
2471 { 0x06, 0xe1f8 },
2472 { 0x06, 0x4968 },
2473 { 0x06, 0x08e4 },
2474 { 0x06, 0xf848 },
2475 { 0x06, 0xe5f8 },
2476 { 0x06, 0x4958 },
2477 { 0x06, 0xf7e4 },
2478 { 0x06, 0xf848 },
2479 { 0x06, 0xe5f8 },
2480 { 0x06, 0x49fc },
2481 { 0x06, 0x044d },
2482 { 0x06, 0x2000 },
2483 { 0x06, 0x024e },
2484 { 0x06, 0x2200 },
2485 { 0x06, 0x024d },
2486 { 0x06, 0xdfff },
2487 { 0x06, 0x014e },
2488 { 0x06, 0xddff },
2489 { 0x06, 0x0100 },
2490 { 0x05, 0x83d8 },
2491 { 0x06, 0x8000 },
2492 { 0x03, 0xdc00 },
2493 { 0x05, 0xfff6 },
2494 { 0x06, 0x00fc },
2495 { 0x1f, 0x0000 },
2496
2497 { 0x1f, 0x0000 },
2498 { 0x0d, 0xf880 },
2499 { 0x1f, 0x0000 }
5b538df9
FR		 2500 };
2501
2502 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2503
daf9df6d 2504 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2505 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2506 { 0x1f, 0x0002 },
2507 { 0x05, 0x669a },
5b538df9 2508 { 0x1f, 0x0005 },
daf9df6d 2509 { 0x05, 0x8330 },
2510 { 0x06, 0x669a },
2511
2512 { 0x1f, 0x0002 }
2513 };
2514 int val;
2515
2516 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517
2518 val = mdio_read(ioaddr, 0x0d);
2519 if ((val & 0x00ff) != 0x006c) {
2520 u32 set[] = {
2521 0x0065, 0x0066, 0x0067, 0x0068,
2522 0x0069, 0x006a, 0x006b, 0x006c
2523 };
2524 int i;
2525
2526 mdio_write(ioaddr, 0x1f, 0x0002);
2527
2528 val &= 0xff00;
2529 for (i = 0; i < ARRAY_SIZE(set); i++)
2530 mdio_write(ioaddr, 0x0d, val | set[i]);
2531 }
2532 } else {
350f7596 2533 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2534 { 0x1f, 0x0002 },
2535 { 0x05, 0x2642 },
5b538df9 2536 { 0x1f, 0x0005 },
daf9df6d 2537 { 0x05, 0x8330 },
2538 { 0x06, 0x2642 }
5b538df9
FR		 2539 };
2540
daf9df6d 2541 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2542 }
2543
daf9df6d 2544 mdio_write(ioaddr, 0x1f, 0x0002);
2545 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2546 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2547
2548 mdio_write(ioaddr, 0x1f, 0x0001);
2549 mdio_write(ioaddr, 0x17, 0x0cc0);
2550
2551 mdio_write(ioaddr, 0x1f, 0x0002);
2552 mdio_patch(ioaddr, 0x0f, 0x0017);
2553
2554 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2555}
2556
2557static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2558{
350f7596 2559 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2560 { 0x1f, 0x0002 },
2561 { 0x10, 0x0008 },
2562 { 0x0d, 0x006c },
2563
2564 { 0x1f, 0x0000 },
2565 { 0x0d, 0xf880 },
2566
2567 { 0x1f, 0x0001 },
2568 { 0x17, 0x0cc0 },
2569
2570 { 0x1f, 0x0001 },
2571 { 0x0b, 0xa4d8 },
2572 { 0x09, 0x281c },
2573 { 0x07, 0x2883 },
2574 { 0x0a, 0x6b35 },
2575 { 0x1d, 0x3da4 },
2576 { 0x1c, 0xeffd },
2577 { 0x14, 0x7f52 },
2578 { 0x18, 0x7fc6 },
2579 { 0x08, 0x0601 },
2580 { 0x06, 0x4063 },
2581 { 0x10, 0xf074 },
2582 { 0x1f, 0x0003 },
2583 { 0x13, 0x0789 },
2584 { 0x12, 0xf4bd },
2585 { 0x1a, 0x04fd },
2586 { 0x14, 0x84b0 },
2587 { 0x1f, 0x0000 },
2588 { 0x00, 0x9200 },
2589
2590 { 0x1f, 0x0005 },
2591 { 0x01, 0x0340 },
2592 { 0x1f, 0x0001 },
2593 { 0x04, 0x4000 },
2594 { 0x03, 0x1d21 },
2595 { 0x02, 0x0c32 },
2596 { 0x01, 0x0200 },
2597 { 0x00, 0x5554 },
2598 { 0x04, 0x4800 },
2599 { 0x04, 0x4000 },
2600 { 0x04, 0xf000 },
2601 { 0x03, 0xdf01 },
2602 { 0x02, 0xdf20 },
2603 { 0x01, 0x101a },
2604 { 0x00, 0xa0ff },
2605 { 0x04, 0xf800 },
2606 { 0x04, 0xf000 },
2607 { 0x1f, 0x0000 },
2608
2609 { 0x1f, 0x0007 },
2610 { 0x1e, 0x0023 },
2611 { 0x16, 0x0000 },
2612 { 0x1f, 0x0000 }
2613 };
2614
2615 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2616}
2617
2857ffb7
FR		 2618static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2619{
350f7596 2620 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2621 { 0x1f, 0x0003 },
2622 { 0x08, 0x441d },
2623 { 0x01, 0x9100 },
2624 { 0x1f, 0x0000 }
2625 };
2626
2627 mdio_write(ioaddr, 0x1f, 0x0000);
2628 mdio_patch(ioaddr, 0x11, 1 << 12);
2629 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2630 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2631
2632 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2633}
2634
5615d9f1
FR		 2635static void rtl_hw_phy_config(struct net_device *dev)
2636{
2637 struct rtl8169_private *tp = netdev_priv(dev);
2638 void __iomem *ioaddr = tp->mmio_addr;
2639
2640 rtl8169_print_mac_version(tp);
2641
2642 switch (tp->mac_version) {
2643 case RTL_GIGA_MAC_VER_01:
2644 break;
2645 case RTL_GIGA_MAC_VER_02:
2646 case RTL_GIGA_MAC_VER_03:
2647 rtl8169s_hw_phy_config(ioaddr);
2648 break;
2649 case RTL_GIGA_MAC_VER_04:
2650 rtl8169sb_hw_phy_config(ioaddr);
2651 break;
2e955856 2652 case RTL_GIGA_MAC_VER_05:
2653 rtl8169scd_hw_phy_config(tp, ioaddr);
2654 break;
8c7006aa 2655 case RTL_GIGA_MAC_VER_06:
2656 rtl8169sce_hw_phy_config(ioaddr);
2657 break;
2857ffb7
FR		 2658 case RTL_GIGA_MAC_VER_07:
2659 case RTL_GIGA_MAC_VER_08:
2660 case RTL_GIGA_MAC_VER_09:
2661 rtl8102e_hw_phy_config(ioaddr);
2662 break;
236b8082
FR		 2663 case RTL_GIGA_MAC_VER_11:
2664 rtl8168bb_hw_phy_config(ioaddr);
2665 break;
2666 case RTL_GIGA_MAC_VER_12:
2667 rtl8168bef_hw_phy_config(ioaddr);
2668 break;
2669 case RTL_GIGA_MAC_VER_17:
2670 rtl8168bef_hw_phy_config(ioaddr);
2671 break;
867763c1 2672 case RTL_GIGA_MAC_VER_18:
ef3386f0 2673 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2674 break;
2675 case RTL_GIGA_MAC_VER_19:
219a1e9d 2676 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2677 break;
7da97ec9 2678 case RTL_GIGA_MAC_VER_20:
219a1e9d 2679 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2680 break;
197ff761
FR		 2681 case RTL_GIGA_MAC_VER_21:
2682 rtl8168c_3_hw_phy_config(ioaddr);
2683 break;
6fb07058
FR		 2684 case RTL_GIGA_MAC_VER_22:
2685 rtl8168c_4_hw_phy_config(ioaddr);
2686 break;
ef3386f0 2687 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2688 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2689 rtl8168cp_2_hw_phy_config(ioaddr);
2690 break;
5b538df9 2691 case RTL_GIGA_MAC_VER_25:
daf9df6d 2692 rtl8168d_1_hw_phy_config(ioaddr);
2693 break;
2694 case RTL_GIGA_MAC_VER_26:
2695 rtl8168d_2_hw_phy_config(ioaddr);
2696 break;
2697 case RTL_GIGA_MAC_VER_27:
2698 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2699 break;
ef3386f0 2700
5615d9f1
FR		 2701 default:
2702 break;
2703 }
2704}
2705
1da177e4
LT		 2706static void rtl8169_phy_timer(unsigned long __opaque)
2707{
2708 struct net_device *dev = (struct net_device *)__opaque;
2709 struct rtl8169_private *tp = netdev_priv(dev);
2710 struct timer_list *timer = &tp->timer;
2711 void __iomem *ioaddr = tp->mmio_addr;
2712 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2713
bcf0bf90 2714 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2715
64e4bfb4 2716 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2717 return;
2718
2719 spin_lock_irq(&tp->lock);
2720
2721 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2722 /*
1da177e4
LT		 2723 * A busy loop could burn quite a few cycles on nowadays CPU.
2724 * Let's delay the execution of the timer for a few ticks.
2725 */
2726 timeout = HZ/10;
2727 goto out_mod_timer;
2728 }
2729
2730 if (tp->link_ok(ioaddr))
2731 goto out_unlock;
2732
bf82c189 2733 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2734
2735 tp->phy_reset_enable(ioaddr);
2736
2737out_mod_timer:
2738 mod_timer(timer, jiffies + timeout);
2739out_unlock:
2740 spin_unlock_irq(&tp->lock);
2741}
2742
2743static inline void rtl8169_delete_timer(struct net_device *dev)
2744{
2745 struct rtl8169_private *tp = netdev_priv(dev);
2746 struct timer_list *timer = &tp->timer;
2747
e179bb7b 2748 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2749 return;
2750
2751 del_timer_sync(timer);
2752}
2753
2754static inline void rtl8169_request_timer(struct net_device *dev)
2755{
2756 struct rtl8169_private *tp = netdev_priv(dev);
2757 struct timer_list *timer = &tp->timer;
2758
e179bb7b 2759 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2760 return;
2761
2efa53f3 2762 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2763}
2764
2765#ifdef CONFIG_NET_POLL_CONTROLLER
2766/*
2767 * Polling 'interrupt' - used by things like netconsole to send skbs
2768 * without having to re-enable interrupts. It's not called while
2769 * the interrupt routine is executing.
2770 */
2771static void rtl8169_netpoll(struct net_device *dev)
2772{
2773 struct rtl8169_private *tp = netdev_priv(dev);
2774 struct pci_dev *pdev = tp->pci_dev;
2775
2776 disable_irq(pdev->irq);
7d12e780 2777 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2778 enable_irq(pdev->irq);
2779}
2780#endif
2781
2782static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2783 void __iomem *ioaddr)
2784{
2785 iounmap(ioaddr);
2786 pci_release_regions(pdev);
87aeec76 2787 pci_clear_mwi(pdev);
1da177e4
LT		 2788 pci_disable_device(pdev);
2789 free_netdev(dev);
2790}
2791
bf793295
FR		 2792static void rtl8169_phy_reset(struct net_device *dev,
2793 struct rtl8169_private *tp)
2794{
2795 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2796 unsigned int i;
bf793295
FR		 2797
2798 tp->phy_reset_enable(ioaddr);
2799 for (i = 0; i < 100; i++) {
2800 if (!tp->phy_reset_pending(ioaddr))
2801 return;
2802 msleep(1);
2803 }
bf82c189 2804 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2805}
2806
4ff96fa6
FR		 2807static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2808{
2809 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2810
5615d9f1 2811 rtl_hw_phy_config(dev);
4ff96fa6 2812
77332894
MS		 2813 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2814 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2815 RTL_W8(0x82, 0x01);
2816 }
4ff96fa6 2817
6dccd16b
FR		 2818 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2819
2820 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2821 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2822
bcf0bf90 2823 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2824 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2825 RTL_W8(0x82, 0x01);
2826 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2827 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2828 }
2829
bf793295
FR		 2830 rtl8169_phy_reset(dev, tp);
2831
901dda2b
FR		 2832 /*
2833 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2834 * only 8101. Don't panic.
2835 */
2836 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2837
bf82c189
JP		 2838 if (RTL_R8(PHYstatus) & TBI_Enable)
2839 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2840}
2841
773d2021
FR		 2842static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2843{
2844 void __iomem *ioaddr = tp->mmio_addr;
2845 u32 high;
2846 u32 low;
2847
2848 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2849 high = addr[4] | (addr[5] << 8);
2850
2851 spin_lock_irq(&tp->lock);
2852
2853 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2854
773d2021 2855 RTL_W32(MAC4, high);
908ba2bf 2856 RTL_R32(MAC4);
2857
78f1cd02 2858 RTL_W32(MAC0, low);
908ba2bf 2859 RTL_R32(MAC0);
2860
773d2021
FR		 2861 RTL_W8(Cfg9346, Cfg9346_Lock);
2862
2863 spin_unlock_irq(&tp->lock);
2864}
2865
2866static int rtl_set_mac_address(struct net_device *dev, void *p)
2867{
2868 struct rtl8169_private *tp = netdev_priv(dev);
2869 struct sockaddr *addr = p;
2870
2871 if (!is_valid_ether_addr(addr->sa_data))
2872 return -EADDRNOTAVAIL;
2873
2874 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2875
2876 rtl_rar_set(tp, dev->dev_addr);
2877
2878 return 0;
2879}
2880
5f787a1a
FR		 2881static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2882{
2883 struct rtl8169_private *tp = netdev_priv(dev);
2884 struct mii_ioctl_data *data = if_mii(ifr);
2885
8b4ab28d
FR		 2886 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2887}
5f787a1a 2888
8b4ab28d
FR		 2889static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2890{
5f787a1a
FR		 2891 switch (cmd) {
2892 case SIOCGMIIPHY:
2893 data->phy_id = 32; /* Internal PHY */
2894 return 0;
2895
2896 case SIOCGMIIREG:
2897 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2898 return 0;
2899
2900 case SIOCSMIIREG:
5f787a1a
FR		 2901 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2902 return 0;
2903 }
2904 return -EOPNOTSUPP;
2905}
2906
8b4ab28d
FR		 2907static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2908{
2909 return -EOPNOTSUPP;
2910}
2911
0e485150
FR		 2912static const struct rtl_cfg_info {
2913 void (*hw_start)(struct net_device *);
2914 unsigned int region;
2915 unsigned int align;
2916 u16 intr_event;
2917 u16 napi_event;
ccdffb9a 2918 unsigned features;
f21b75e9 2919 u8 default_ver;
0e485150
FR		 2920} rtl_cfg_infos [] = {
2921 [RTL_CFG_0] = {
2922 .hw_start = rtl_hw_start_8169,
2923 .region = 1,
e9f63f30 2924 .align = 0,
0e485150
FR		 2925 .intr_event = SYSErr | LinkChg | RxOverflow |
2926 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2927 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2928 .features = RTL_FEATURE_GMII,
2929 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2930 },
2931 [RTL_CFG_1] = {
2932 .hw_start = rtl_hw_start_8168,
2933 .region = 2,
2934 .align = 8,
801e147c 2935 .intr_event = SYSErr | RxFIFOOver | LinkChg | RxOverflow |
0e485150 2936 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2937 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2938 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2939 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2940 },
2941 [RTL_CFG_2] = {
2942 .hw_start = rtl_hw_start_8101,
2943 .region = 2,
2944 .align = 8,
2945 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2946 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2947 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2948 .features = RTL_FEATURE_MSI,
2949 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2950 }
2951};
2952
fbac58fc
FR		 2953/* Cfg9346_Unlock assumed. */
2954static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2955 const struct rtl_cfg_info *cfg)
2956{
2957 unsigned msi = 0;
2958 u8 cfg2;
2959
2960 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2961 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2962 if (pci_enable_msi(pdev)) {
2963 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2964 } else {
2965 cfg2 |= MSIEnable;
2966 msi = RTL_FEATURE_MSI;
2967 }
2968 }
2969 RTL_W8(Config2, cfg2);
2970 return msi;
2971}
2972
2973static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2974{
2975 if (tp->features & RTL_FEATURE_MSI) {
2976 pci_disable_msi(pdev);
2977 tp->features &= ~RTL_FEATURE_MSI;
2978 }
2979}
2980
8b4ab28d
FR		 2981static const struct net_device_ops rtl8169_netdev_ops = {
2982 .ndo_open = rtl8169_open,
2983 .ndo_stop = rtl8169_close,
2984 .ndo_get_stats = rtl8169_get_stats,
00829823 2985 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2986 .ndo_tx_timeout = rtl8169_tx_timeout,
2987 .ndo_validate_addr = eth_validate_addr,
2988 .ndo_change_mtu = rtl8169_change_mtu,
2989 .ndo_set_mac_address = rtl_set_mac_address,
2990 .ndo_do_ioctl = rtl8169_ioctl,
2991 .ndo_set_multicast_list = rtl_set_rx_mode,
2992#ifdef CONFIG_R8169_VLAN
2993 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2994#endif
2995#ifdef CONFIG_NET_POLL_CONTROLLER
2996 .ndo_poll_controller = rtl8169_netpoll,
2997#endif
2998
2999};
3000
1da177e4 3001static int __devinit
4ff96fa6 3002rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3003{
0e485150
FR		 3004 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3005 const unsigned int region = cfg->region;
1da177e4 3006 struct rtl8169_private *tp;
ccdffb9a 3007 struct mii_if_info *mii;
4ff96fa6
FR		 3008 struct net_device *dev;
3009 void __iomem *ioaddr;
07d3f51f
FR		 3010 unsigned int i;
3011 int rc;
1da177e4 3012
4ff96fa6
FR		 3013 if (netif_msg_drv(&debug)) {
3014 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3015 MODULENAME, RTL8169_VERSION);
3016 }
1da177e4 3017
1da177e4 3018 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3019 if (!dev) {
b57b7e5a 3020 if (netif_msg_drv(&debug))
9b91cf9d 3021 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3022 rc = -ENOMEM;
3023 goto out;
1da177e4
LT		 3024 }
3025
1da177e4 3026 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3027 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3028 tp = netdev_priv(dev);
c4028958 3029 tp->dev = dev;
21e197f2 3030 tp->pci_dev = pdev;
b57b7e5a 3031 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3032
ccdffb9a
FR		 3033 mii = &tp->mii;
3034 mii->dev = dev;
3035 mii->mdio_read = rtl_mdio_read;
3036 mii->mdio_write = rtl_mdio_write;
3037 mii->phy_id_mask = 0x1f;
3038 mii->reg_num_mask = 0x1f;
3039 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3040
1da177e4
LT		 3041 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3042 rc = pci_enable_device(pdev);
b57b7e5a 3043 if (rc < 0) {
bf82c189 3044 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3045 goto err_out_free_dev_1;
1da177e4
LT		 3046 }
3047
87aeec76 3048 if (pci_set_mwi(pdev) < 0)
3049 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3050
1da177e4 3051 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3052 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3053 netif_err(tp, probe, dev,
3054 "region #%d not an MMIO resource, aborting\n",
3055 region);
1da177e4 3056 rc = -ENODEV;
87aeec76 3057 goto err_out_mwi_2;
1da177e4 3058 }
4ff96fa6 3059
1da177e4 3060 /* check for weird/broken PCI region reporting */
bcf0bf90 3061 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3062 netif_err(tp, probe, dev,
3063 "Invalid PCI region size(s), aborting\n");
1da177e4 3064 rc = -ENODEV;
87aeec76 3065 goto err_out_mwi_2;
1da177e4
LT		 3066 }
3067
3068 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3069 if (rc < 0) {
bf82c189 3070 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3071 goto err_out_mwi_2;
1da177e4
LT		 3072 }
3073
3074 tp->cp_cmd = PCIMulRW | RxChkSum;
3075
3076 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3077 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3078 tp->cp_cmd |= PCIDAC;
3079 dev->features |= NETIF_F_HIGHDMA;
3080 } else {
284901a9 3081 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3082 if (rc < 0) {
bf82c189 3083 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3084 goto err_out_free_res_3;
1da177e4
LT		 3085 }
3086 }
3087
1da177e4 3088 /* ioremap MMIO region */
bcf0bf90 3089 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3090 if (!ioaddr) {
bf82c189 3091 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3092 rc = -EIO;
87aeec76 3093 goto err_out_free_res_3;
1da177e4
LT		 3094 }
3095
4300e8c7
DM		 3096 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3097 if (!tp->pcie_cap)
3098 netif_info(tp, probe, dev, "no PCI Express capability\n");
3099
d78ad8cb 3100 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3101
3102 /* Soft reset the chip. */
3103 RTL_W8(ChipCmd, CmdReset);
3104
3105 /* Check that the chip has finished the reset. */
07d3f51f 3106 for (i = 0; i < 100; i++) {
1da177e4
LT		 3107 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3108 break;
b518fa8e 3109 msleep_interruptible(1);
1da177e4
LT		 3110 }
3111
d78ad8cb
KW		 3112 RTL_W16(IntrStatus, 0xffff);
3113
ca52efd5 3114 pci_set_master(pdev);
3115
1da177e4
LT		 3116 /* Identify chip attached to board */
3117 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3118
f21b75e9
JD		 3119 /* Use appropriate default if unknown */
3120 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3121 netif_notice(tp, probe, dev,
3122 "unknown MAC, using family default\n");
f21b75e9
JD		 3123 tp->mac_version = cfg->default_ver;
3124 }
3125
1da177e4 3126 rtl8169_print_mac_version(tp);
1da177e4 3127
cee60c37 3128 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3129 if (tp->mac_version == rtl_chip_info[i].mac_version)
3130 break;
3131 }
cee60c37 3132 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3133 dev_err(&pdev->dev,
3134 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3135 goto err_out_msi_4;
1da177e4
LT		 3136 }
3137 tp->chipset = i;
3138
5d06a99f
FR		 3139 RTL_W8(Cfg9346, Cfg9346_Unlock);
3140 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3141 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3142 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3143 tp->features |= RTL_FEATURE_WOL;
3144 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3145 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3146 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3147 RTL_W8(Cfg9346, Cfg9346_Lock);
3148
66ec5d4f
FR		 3149 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3150 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3151 tp->set_speed = rtl8169_set_speed_tbi;
3152 tp->get_settings = rtl8169_gset_tbi;
3153 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3154 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3155 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3156 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3157
64e4bfb4 3158 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3159 } else {
3160 tp->set_speed = rtl8169_set_speed_xmii;
3161 tp->get_settings = rtl8169_gset_xmii;
3162 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3163 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3164 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3165 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3166 }
3167
df58ef51
FR		 3168 spin_lock_init(&tp->lock);
3169
738e1e69
PV		 3170 tp->mmio_addr = ioaddr;
3171
7bf6bf48 3172 /* Get MAC address */
1da177e4
LT		 3173 for (i = 0; i < MAC_ADDR_LEN; i++)
3174 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3175 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3176
1da177e4 3177 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3178 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3179 dev->irq = pdev->irq;
3180 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3181
bea3348e 3182 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3183
3184#ifdef CONFIG_R8169_VLAN
3185 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3186#endif
2edae08e 3187 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3188
3189 tp->intr_mask = 0xffff;
0e485150
FR		 3190 tp->hw_start = cfg->hw_start;
3191 tp->intr_event = cfg->intr_event;
3192 tp->napi_event = cfg->napi_event;
1da177e4 3193
2efa53f3
FR		 3194 init_timer(&tp->timer);
3195 tp->timer.data = (unsigned long) dev;
3196 tp->timer.function = rtl8169_phy_timer;
3197
1da177e4 3198 rc = register_netdev(dev);
4ff96fa6 3199 if (rc < 0)
87aeec76 3200 goto err_out_msi_4;
1da177e4
LT		 3201
3202 pci_set_drvdata(pdev, dev);
3203
bf82c189
JP		 3204 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3205 rtl_chip_info[tp->chipset].name,
3206 dev->base_addr, dev->dev_addr,
3207 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3208
4ff96fa6 3209 rtl8169_init_phy(dev, tp);
05af2142
SW		 3210
3211 /*
3212 * Pretend we are using VLANs; This bypasses a nasty bug where
3213 * Interrupts stop flowing on high load on 8110SCd controllers.
3214 */
3215 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3216 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3217
8b76ab39 3218 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3219
f3ec4f87
AS		 3220 if (pci_dev_run_wake(pdev))
3221 pm_runtime_put_noidle(&pdev->dev);
e1759441 3222
4ff96fa6
FR		 3223out:
3224 return rc;
1da177e4 3225
87aeec76 3226err_out_msi_4:
fbac58fc 3227 rtl_disable_msi(pdev, tp);
4ff96fa6 3228 iounmap(ioaddr);
87aeec76 3229err_out_free_res_3:
4ff96fa6 3230 pci_release_regions(pdev);
87aeec76 3231err_out_mwi_2:
4ff96fa6 3232 pci_clear_mwi(pdev);
4ff96fa6
FR		 3233 pci_disable_device(pdev);
3234err_out_free_dev_1:
3235 free_netdev(dev);
3236 goto out;
1da177e4
LT		 3237}
3238
07d3f51f 3239static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3240{
3241 struct net_device *dev = pci_get_drvdata(pdev);
3242 struct rtl8169_private *tp = netdev_priv(dev);
3243
eb2a021c
FR		 3244 flush_scheduled_work();
3245
1da177e4 3246 unregister_netdev(dev);
cc098dc7 3247
f3ec4f87
AS		 3248 if (pci_dev_run_wake(pdev))
3249 pm_runtime_get_noresume(&pdev->dev);
e1759441 3250
cc098dc7
IV		 3251 /* restore original MAC address */
3252 rtl_rar_set(tp, dev->perm_addr);
3253
fbac58fc 3254 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3255 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3256 pci_set_drvdata(pdev, NULL);
3257}
3258
1da177e4
LT		 3259static int rtl8169_open(struct net_device *dev)
3260{
3261 struct rtl8169_private *tp = netdev_priv(dev);
3262 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3263 int retval = -ENOMEM;
1da177e4 3264
e1759441 3265 pm_runtime_get_sync(&pdev->dev);
1da177e4 3266
1da177e4
LT		 3267 /*
3268 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3269 * dma_alloc_coherent provides more.
1da177e4 3270 */
82553bb6
SG		 3271 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3272 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3273 if (!tp->TxDescArray)
e1759441 3274 goto err_pm_runtime_put;
1da177e4 3275
82553bb6
SG		 3276 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3277 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3278 if (!tp->RxDescArray)
99f252b0 3279 goto err_free_tx_0;
1da177e4
LT		 3280
3281 retval = rtl8169_init_ring(dev);
3282 if (retval < 0)
99f252b0 3283 goto err_free_rx_1;
1da177e4 3284
c4028958 3285 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3286
99f252b0
FR		 3287 smp_mb();
3288
fbac58fc
FR		 3289 retval = request_irq(dev->irq, rtl8169_interrupt,
3290 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3291 dev->name, dev);
3292 if (retval < 0)
3293 goto err_release_ring_2;
3294
bea3348e 3295 napi_enable(&tp->napi);
bea3348e 3296
07ce4064 3297 rtl_hw_start(dev);
1da177e4
LT		 3298
3299 rtl8169_request_timer(dev);
3300
e1759441
RW		 3301 tp->saved_wolopts = 0;
3302 pm_runtime_put_noidle(&pdev->dev);
3303
1da177e4
LT		 3304 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3305out:
3306 return retval;
3307
99f252b0
FR		 3308err_release_ring_2:
3309 rtl8169_rx_clear(tp);
3310err_free_rx_1:
82553bb6
SG		 3311 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3312 tp->RxPhyAddr);
e1759441 3313 tp->RxDescArray = NULL;
99f252b0 3314err_free_tx_0:
82553bb6
SG		 3315 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3316 tp->TxPhyAddr);
e1759441
RW		 3317 tp->TxDescArray = NULL;
3318err_pm_runtime_put:
3319 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3320 goto out;
3321}
3322
3323static void rtl8169_hw_reset(void __iomem *ioaddr)
3324{
3325 /* Disable interrupts */
3326 rtl8169_irq_mask_and_ack(ioaddr);
3327
3328 /* Reset the chipset */
3329 RTL_W8(ChipCmd, CmdReset);
3330
3331 /* PCI commit */
3332 RTL_R8(ChipCmd);
3333}
3334
7f796d83 3335static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3336{
3337 void __iomem *ioaddr = tp->mmio_addr;
3338 u32 cfg = rtl8169_rx_config;
3339
3340 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3341 RTL_W32(RxConfig, cfg);
3342
3343 /* Set DMA burst size and Interframe Gap Time */
3344 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3345 (InterFrameGap << TxInterFrameGapShift));
3346}
3347
07ce4064 3348static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3349{
3350 struct rtl8169_private *tp = netdev_priv(dev);
3351 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3352 unsigned int i;
1da177e4
LT		 3353
3354 /* Soft reset the chip. */
3355 RTL_W8(ChipCmd, CmdReset);
3356
3357 /* Check that the chip has finished the reset. */
07d3f51f 3358 for (i = 0; i < 100; i++) {
1da177e4
LT		 3359 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3360 break;
b518fa8e 3361 msleep_interruptible(1);
1da177e4
LT		 3362 }
3363
07ce4064
FR		 3364 tp->hw_start(dev);
3365
07ce4064
FR		 3366 netif_start_queue(dev);
3367}
3368
3369
7f796d83
FR		 3370static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3371 void __iomem *ioaddr)
3372{
3373 /*
3374 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3375 * register to be written before TxDescAddrLow to work.
3376 * Switching from MMIO to I/O access fixes the issue as well.
3377 */
3378 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3379 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3380 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3381 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3382}
3383
3384static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3385{
3386 u16 cmd;
3387
3388 cmd = RTL_R16(CPlusCmd);
3389 RTL_W16(CPlusCmd, cmd);
3390 return cmd;
3391}
3392
fdd7b4c3 3393static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3394{
3395 /* Low hurts. Let's disable the filtering. */
207d6e87 3396 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3397}
3398
6dccd16b
FR		 3399static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3400{
350f7596 3401 static const struct {
6dccd16b
FR		 3402 u32 mac_version;
3403 u32 clk;
3404 u32 val;
3405 } cfg2_info [] = {
3406 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3407 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3408 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3409 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3410 }, *p = cfg2_info;
3411 unsigned int i;
3412 u32 clk;
3413
3414 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3415 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3416 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3417 RTL_W32(0x7c, p->val);
3418 break;
3419 }
3420 }
3421}
3422
07ce4064
FR		 3423static void rtl_hw_start_8169(struct net_device *dev)
3424{
3425 struct rtl8169_private *tp = netdev_priv(dev);
3426 void __iomem *ioaddr = tp->mmio_addr;
3427 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3428
9cb427b6
FR		 3429 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3430 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3431 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3432 }
3433
1da177e4 3434 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3435 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3436 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3437 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3438 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3439 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3440
1da177e4
LT		 3441 RTL_W8(EarlyTxThres, EarlyTxThld);
3442
6f0333b8 3443 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3444
c946b304
FR		 3445 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3446 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3447 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3448 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3449 rtl_set_rx_tx_config_registers(tp);
1da177e4 3450
7f796d83 3451 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3452
bcf0bf90
FR		 3453 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3454 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3455 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3456 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3457 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3458 }
3459
bcf0bf90
FR		 3460 RTL_W16(CPlusCmd, tp->cp_cmd);
3461
6dccd16b
FR		 3462 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3463
1da177e4
LT		 3464 /*
3465 * Undocumented corner. Supposedly:
3466 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3467 */
3468 RTL_W16(IntrMitigate, 0x0000);
3469
7f796d83 3470 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3471
c946b304
FR		 3472 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3473 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3474 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3475 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3476 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3477 rtl_set_rx_tx_config_registers(tp);
3478 }
3479
1da177e4 3480 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3481
3482 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3483 RTL_R8(IntrMask);
1da177e4
LT		 3484
3485 RTL_W32(RxMissed, 0);
3486
07ce4064 3487 rtl_set_rx_mode(dev);
1da177e4
LT		 3488
3489 /* no early-rx interrupts */
3490 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3491
3492 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3493 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3494}
1da177e4 3495
9c14ceaf 3496static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3497{
9c14ceaf
FR		 3498 struct net_device *dev = pci_get_drvdata(pdev);
3499 struct rtl8169_private *tp = netdev_priv(dev);
3500 int cap = tp->pcie_cap;
3501
3502 if (cap) {
3503 u16 ctl;
458a9f61 3504
9c14ceaf
FR		 3505 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3506 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3507 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3508 }
458a9f61
FR		 3509}
3510
dacf8154
FR		 3511static void rtl_csi_access_enable(void __iomem *ioaddr)
3512{
3513 u32 csi;
3514
3515 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3516 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3517}
3518
3519struct ephy_info {
3520 unsigned int offset;
3521 u16 mask;
3522 u16 bits;
3523};
3524
350f7596 3525static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3526{
3527 u16 w;
3528
3529 while (len-- > 0) {
3530 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3531 rtl_ephy_write(ioaddr, e->offset, w);
3532 e++;
3533 }
3534}
3535
b726e493
FR		 3536static void rtl_disable_clock_request(struct pci_dev *pdev)
3537{
3538 struct net_device *dev = pci_get_drvdata(pdev);
3539 struct rtl8169_private *tp = netdev_priv(dev);
3540 int cap = tp->pcie_cap;
3541
3542 if (cap) {
3543 u16 ctl;
3544
3545 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3546 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3547 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3548 }
3549}
3550
3551#define R8168_CPCMD_QUIRK_MASK (\
3552 EnableBist | \
3553 Mac_dbgo_oe | \
3554 Force_half_dup | \
3555 Force_rxflow_en | \
3556 Force_txflow_en | \
3557 Cxpl_dbg_sel | \
3558 ASF | \
3559 PktCntrDisable | \
3560 Mac_dbgo_sel)
3561
219a1e9d
FR		 3562static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3563{
b726e493
FR		 3564 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3565
3566 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3567
2e68ae44
FR		 3568 rtl_tx_performance_tweak(pdev,
3569 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3570}
3571
3572static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3573{
3574 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3575
3576 RTL_W8(EarlyTxThres, EarlyTxThld);
3577
3578 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3579}
3580
3581static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3582{
b726e493
FR		 3583 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3584
3585 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3586
219a1e9d 3587 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3588
3589 rtl_disable_clock_request(pdev);
3590
3591 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3592}
3593
ef3386f0 3594static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3595{
350f7596 3596 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3597 { 0x01, 0, 0x0001 },
3598 { 0x02, 0x0800, 0x1000 },
3599 { 0x03, 0, 0x0042 },
3600 { 0x06, 0x0080, 0x0000 },
3601 { 0x07, 0, 0x2000 }
3602 };
3603
3604 rtl_csi_access_enable(ioaddr);
3605
3606 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3607
219a1e9d
FR		 3608 __rtl_hw_start_8168cp(ioaddr, pdev);
3609}
3610
ef3386f0
FR		 3611static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3612{
3613 rtl_csi_access_enable(ioaddr);
3614
3615 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3616
3617 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3618
3619 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3620}
3621
7f3e3d3a
FR		 3622static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3623{
3624 rtl_csi_access_enable(ioaddr);
3625
3626 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3627
3628 /* Magic. */
3629 RTL_W8(DBG_REG, 0x20);
3630
3631 RTL_W8(EarlyTxThres, EarlyTxThld);
3632
3633 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3634
3635 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3636}
3637
219a1e9d
FR		 3638static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3639{
350f7596 3640 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3641 { 0x02, 0x0800, 0x1000 },
3642 { 0x03, 0, 0x0002 },
3643 { 0x06, 0x0080, 0x0000 }
3644 };
3645
3646 rtl_csi_access_enable(ioaddr);
3647
3648 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3649
3650 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3651
219a1e9d
FR		 3652 __rtl_hw_start_8168cp(ioaddr, pdev);
3653}
3654
3655static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3656{
350f7596 3657 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3658 { 0x01, 0, 0x0001 },
3659 { 0x03, 0x0400, 0x0220 }
3660 };
3661
3662 rtl_csi_access_enable(ioaddr);
3663
3664 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3665
219a1e9d
FR		 3666 __rtl_hw_start_8168cp(ioaddr, pdev);
3667}
3668
197ff761
FR		 3669static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3670{
3671 rtl_hw_start_8168c_2(ioaddr, pdev);
3672}
3673
6fb07058
FR		 3674static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3675{
3676 rtl_csi_access_enable(ioaddr);
3677
3678 __rtl_hw_start_8168cp(ioaddr, pdev);
3679}
3680
5b538df9
FR		 3681static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3682{
3683 rtl_csi_access_enable(ioaddr);
3684
3685 rtl_disable_clock_request(pdev);
3686
3687 RTL_W8(EarlyTxThres, EarlyTxThld);
3688
3689 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3690
3691 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3692}
3693
07ce4064
FR		 3694static void rtl_hw_start_8168(struct net_device *dev)
3695{
2dd99530
FR		 3696 struct rtl8169_private *tp = netdev_priv(dev);
3697 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3698 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3699
3700 RTL_W8(Cfg9346, Cfg9346_Unlock);
3701
3702 RTL_W8(EarlyTxThres, EarlyTxThld);
3703
6f0333b8 3704 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3705
0e485150 3706 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3707
3708 RTL_W16(CPlusCmd, tp->cp_cmd);
3709
0e485150 3710 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3711
0e485150
FR		 3712 /* Work around for RxFIFO overflow. */
3713 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3714 tp->intr_event |= RxFIFOOver | PCSTimeout;
3715 tp->intr_event &= ~RxOverflow;
3716 }
3717
3718 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3719
b8363901
FR		 3720 rtl_set_rx_mode(dev);
3721
3722 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3723 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3724
3725 RTL_R8(IntrMask);
3726
219a1e9d
FR		 3727 switch (tp->mac_version) {
3728 case RTL_GIGA_MAC_VER_11:
3729 rtl_hw_start_8168bb(ioaddr, pdev);
3730 break;
3731
3732 case RTL_GIGA_MAC_VER_12:
3733 case RTL_GIGA_MAC_VER_17:
3734 rtl_hw_start_8168bef(ioaddr, pdev);
3735 break;
3736
3737 case RTL_GIGA_MAC_VER_18:
ef3386f0 3738 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3739 break;
3740
3741 case RTL_GIGA_MAC_VER_19:
3742 rtl_hw_start_8168c_1(ioaddr, pdev);
3743 break;
3744
3745 case RTL_GIGA_MAC_VER_20:
3746 rtl_hw_start_8168c_2(ioaddr, pdev);
3747 break;
3748
197ff761
FR		 3749 case RTL_GIGA_MAC_VER_21:
3750 rtl_hw_start_8168c_3(ioaddr, pdev);
3751 break;
3752
6fb07058
FR		 3753 case RTL_GIGA_MAC_VER_22:
3754 rtl_hw_start_8168c_4(ioaddr, pdev);
3755 break;
3756
ef3386f0
FR		 3757 case RTL_GIGA_MAC_VER_23:
3758 rtl_hw_start_8168cp_2(ioaddr, pdev);
3759 break;
3760
7f3e3d3a
FR		 3761 case RTL_GIGA_MAC_VER_24:
3762 rtl_hw_start_8168cp_3(ioaddr, pdev);
3763 break;
3764
5b538df9 3765 case RTL_GIGA_MAC_VER_25:
daf9df6d 3766 case RTL_GIGA_MAC_VER_26:
3767 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3768 rtl_hw_start_8168d(ioaddr, pdev);
3769 break;
3770
219a1e9d
FR		 3771 default:
3772 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3773 dev->name, tp->mac_version);
3774 break;
3775 }
2dd99530 3776
0e485150
FR		 3777 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3778
b8363901
FR		 3779 RTL_W8(Cfg9346, Cfg9346_Lock);
3780
2dd99530 3781 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3782
0e485150 3783 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3784}
1da177e4 3785
2857ffb7
FR		 3786#define R810X_CPCMD_QUIRK_MASK (\
3787 EnableBist | \
3788 Mac_dbgo_oe | \
3789 Force_half_dup | \
5edcc537 3790 Force_rxflow_en | \
2857ffb7
FR		 3791 Force_txflow_en | \
3792 Cxpl_dbg_sel | \
3793 ASF | \
3794 PktCntrDisable | \
3795 PCIDAC | \
3796 PCIMulRW)
3797
3798static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3799{
350f7596 3800 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3801 { 0x01, 0, 0x6e65 },
3802 { 0x02, 0, 0x091f },
3803 { 0x03, 0, 0xc2f9 },
3804 { 0x06, 0, 0xafb5 },
3805 { 0x07, 0, 0x0e00 },
3806 { 0x19, 0, 0xec80 },
3807 { 0x01, 0, 0x2e65 },
3808 { 0x01, 0, 0x6e65 }
3809 };
3810 u8 cfg1;
3811
3812 rtl_csi_access_enable(ioaddr);
3813
3814 RTL_W8(DBG_REG, FIX_NAK_1);
3815
3816 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3817
3818 RTL_W8(Config1,
3819 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3820 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3821
3822 cfg1 = RTL_R8(Config1);
3823 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3824 RTL_W8(Config1, cfg1 & ~LEDS0);
3825
3826 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3827
3828 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3829}
3830
3831static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3832{
3833 rtl_csi_access_enable(ioaddr);
3834
3835 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3836
3837 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3838 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3839
3840 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3841}
3842
3843static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3844{
3845 rtl_hw_start_8102e_2(ioaddr, pdev);
3846
3847 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3848}
3849
07ce4064
FR		 3850static void rtl_hw_start_8101(struct net_device *dev)
3851{
cdf1a608
FR		 3852 struct rtl8169_private *tp = netdev_priv(dev);
3853 void __iomem *ioaddr = tp->mmio_addr;
3854 struct pci_dev *pdev = tp->pci_dev;
3855
e3cf0cc0
FR		 3856 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3857 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3858 int cap = tp->pcie_cap;
3859
3860 if (cap) {
3861 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3862 PCI_EXP_DEVCTL_NOSNOOP_EN);
3863 }
cdf1a608
FR		 3864 }
3865
2857ffb7
FR		 3866 switch (tp->mac_version) {
3867 case RTL_GIGA_MAC_VER_07:
3868 rtl_hw_start_8102e_1(ioaddr, pdev);
3869 break;
3870
3871 case RTL_GIGA_MAC_VER_08:
3872 rtl_hw_start_8102e_3(ioaddr, pdev);
3873 break;
3874
3875 case RTL_GIGA_MAC_VER_09:
3876 rtl_hw_start_8102e_2(ioaddr, pdev);
3877 break;
cdf1a608
FR		 3878 }
3879
3880 RTL_W8(Cfg9346, Cfg9346_Unlock);
3881
3882 RTL_W8(EarlyTxThres, EarlyTxThld);
3883
6f0333b8 3884 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3885
3886 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3887
3888 RTL_W16(CPlusCmd, tp->cp_cmd);
3889
3890 RTL_W16(IntrMitigate, 0x0000);
3891
3892 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3893
3894 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3895 rtl_set_rx_tx_config_registers(tp);
3896
3897 RTL_W8(Cfg9346, Cfg9346_Lock);
3898
3899 RTL_R8(IntrMask);
3900
cdf1a608
FR		 3901 rtl_set_rx_mode(dev);
3902
0e485150
FR		 3903 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3904
cdf1a608 3905 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3906
0e485150 3907 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3908}
3909
3910static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3911{
3912 struct rtl8169_private *tp = netdev_priv(dev);
3913 int ret = 0;
3914
3915 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3916 return -EINVAL;
3917
3918 dev->mtu = new_mtu;
3919
3920 if (!netif_running(dev))
3921 goto out;
3922
3923 rtl8169_down(dev);
3924
1da177e4
LT		 3925 ret = rtl8169_init_ring(dev);
3926 if (ret < 0)
3927 goto out;
3928
bea3348e 3929 napi_enable(&tp->napi);
1da177e4 3930
07ce4064 3931 rtl_hw_start(dev);
1da177e4
LT		 3932
3933 rtl8169_request_timer(dev);
3934
3935out:
3936 return ret;
3937}
3938
3939static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3940{
95e0918d 3941 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3942 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3943}
3944
6f0333b8
ED		 3945static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3946 void **data_buff, struct RxDesc *desc)
1da177e4
LT		 3947{
3948 struct pci_dev *pdev = tp->pci_dev;
3949
6f0333b8 3950 dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
1da177e4 3951 PCI_DMA_FROMDEVICE);
6f0333b8
ED		 3952 kfree(*data_buff);
3953 *data_buff = NULL;
1da177e4
LT		 3954 rtl8169_make_unusable_by_asic(desc);
3955}
3956
3957static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3958{
3959 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3960
3961 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3962}
3963
3964static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3965 u32 rx_buf_sz)
3966{
3967 desc->addr = cpu_to_le64(mapping);
3968 wmb();
3969 rtl8169_mark_to_asic(desc, rx_buf_sz);
3970}
3971
6f0333b8
ED		 3972static inline void *rtl8169_align(void *data)
3973{
3974 return (void *)ALIGN((long)data, 16);
3975}
3976
3977static struct sk_buff *rtl8169_alloc_rx_data(struct pci_dev *pdev,
15d31758 3978 struct net_device *dev,
6f0333b8 3979 struct RxDesc *desc)
1da177e4 3980{
6f0333b8 3981 void *data;
1da177e4 3982 dma_addr_t mapping;
6f0333b8 3983 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 3984
6f0333b8
ED		 3985 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3986 if (!data)
3987 return NULL;
e9f63f30 3988
6f0333b8
ED		 3989 if (rtl8169_align(data) != data) {
3990 kfree(data);
3991 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3992 if (!data)
3993 return NULL;
3994 }
3eafe507 3995
6f0333b8 3996 mapping = dma_map_single(&pdev->dev, rtl8169_align(data), rx_buf_sz,
1da177e4 3997 PCI_DMA_FROMDEVICE);
3eafe507
SG		 3998 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
3999 goto err_out;
1da177e4
LT		 4000
4001 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4002 return data;
3eafe507
SG		 4003
4004err_out:
4005 kfree(data);
4006 return NULL;
1da177e4
LT		 4007}
4008
4009static void rtl8169_rx_clear(struct rtl8169_private *tp)
4010{
07d3f51f 4011 unsigned int i;
1da177e4
LT		 4012
4013 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4014 if (tp->Rx_databuff[i]) {
4015 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4016 tp->RxDescArray + i);
4017 }
4018 }
4019}
4020
4021static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
aeb19f60 4022 u32 start, u32 end, gfp_t gfp)
1da177e4
LT		 4023{
4024 u32 cur;
5b0384f4 4025
4ae47c2d 4026 for (cur = start; end - cur != 0; cur++) {
6f0333b8 4027 void *data;
15d31758 4028 unsigned int i = cur % NUM_RX_DESC;
1da177e4 4029
4ae47c2d
FR		 4030 WARN_ON((s32)(end - cur) < 0);
4031
6f0333b8 4032 if (tp->Rx_databuff[i])
1da177e4 4033 continue;
bcf0bf90 4034
6f0333b8
ED		 4035 data = rtl8169_alloc_rx_data(tp->pci_dev, dev,
4036 tp->RxDescArray + i);
4037 if (!data) {
4038 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
1da177e4 4039 break;
6f0333b8
ED		 4040 }
4041 tp->Rx_databuff[i] = data;
1da177e4
LT		 4042 }
4043 return cur - start;
4044}
4045
4046static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4047{
4048 desc->opts1 |= cpu_to_le32(RingEnd);
4049}
4050
4051static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4052{
4053 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4054}
4055
4056static int rtl8169_init_ring(struct net_device *dev)
4057{
4058 struct rtl8169_private *tp = netdev_priv(dev);
4059
4060 rtl8169_init_ring_indexes(tp);
4061
4062 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4063 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4064
aeb19f60 4065 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC, GFP_KERNEL) != NUM_RX_DESC)
1da177e4
LT		 4066 goto err_out;
4067
4068 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4069
4070 return 0;
4071
4072err_out:
4073 rtl8169_rx_clear(tp);
4074 return -ENOMEM;
4075}
4076
4077static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4078 struct TxDesc *desc)
4079{
4080 unsigned int len = tx_skb->len;
4081
82553bb6
SG		 4082 dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len,
4083 PCI_DMA_TODEVICE);
1da177e4
LT		 4084 desc->opts1 = 0x00;
4085 desc->opts2 = 0x00;
4086 desc->addr = 0x00;
4087 tx_skb->len = 0;
4088}
4089
3eafe507
SG		 4090static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4091 unsigned int n)
1da177e4
LT		 4092{
4093 unsigned int i;
4094
3eafe507
SG		 4095 for (i = 0; i < n; i++) {
4096 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4097 struct ring_info *tx_skb = tp->tx_skb + entry;
4098 unsigned int len = tx_skb->len;
4099
4100 if (len) {
4101 struct sk_buff *skb = tx_skb->skb;
4102
4103 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4104 tp->TxDescArray + entry);
4105 if (skb) {
4106 dev_kfree_skb(skb);
4107 tx_skb->skb = NULL;
4108 }
cebf8cc7 4109 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4110 }
4111 }
3eafe507
SG		 4112}
4113
4114static void rtl8169_tx_clear(struct rtl8169_private *tp)
4115{
4116 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4117 tp->cur_tx = tp->dirty_tx = 0;
4118}
4119
c4028958 4120static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4121{
4122 struct rtl8169_private *tp = netdev_priv(dev);
4123
c4028958 4124 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4125 schedule_delayed_work(&tp->task, 4);
4126}
4127
4128static void rtl8169_wait_for_quiescence(struct net_device *dev)
4129{
4130 struct rtl8169_private *tp = netdev_priv(dev);
4131 void __iomem *ioaddr = tp->mmio_addr;
4132
4133 synchronize_irq(dev->irq);
4134
4135 /* Wait for any pending NAPI task to complete */
bea3348e 4136 napi_disable(&tp->napi);
1da177e4
LT		 4137
4138 rtl8169_irq_mask_and_ack(ioaddr);
4139
d1d08d12
DM		 4140 tp->intr_mask = 0xffff;
4141 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4142 napi_enable(&tp->napi);
1da177e4
LT		 4143}
4144
c4028958 4145static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4146{
c4028958
DH		 4147 struct rtl8169_private *tp =
4148 container_of(work, struct rtl8169_private, task.work);
4149 struct net_device *dev = tp->dev;
1da177e4
LT		 4150 int ret;
4151
eb2a021c
FR		 4152 rtnl_lock();
4153
4154 if (!netif_running(dev))
4155 goto out_unlock;
4156
4157 rtl8169_wait_for_quiescence(dev);
4158 rtl8169_close(dev);
1da177e4
LT		 4159
4160 ret = rtl8169_open(dev);
4161 if (unlikely(ret < 0)) {
bf82c189
JP		 4162 if (net_ratelimit())
4163 netif_err(tp, drv, dev,
4164 "reinit failure (status = %d). Rescheduling\n",
4165 ret);
1da177e4
LT		 4166 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4167 }
eb2a021c
FR		 4168
4169out_unlock:
4170 rtnl_unlock();
1da177e4
LT		 4171}
4172
c4028958 4173static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4174{
c4028958
DH		 4175 struct rtl8169_private *tp =
4176 container_of(work, struct rtl8169_private, task.work);
4177 struct net_device *dev = tp->dev;
1da177e4 4178
eb2a021c
FR		 4179 rtnl_lock();
4180
1da177e4 4181 if (!netif_running(dev))
eb2a021c 4182 goto out_unlock;
1da177e4
LT		 4183
4184 rtl8169_wait_for_quiescence(dev);
4185
bea3348e 4186 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4187 rtl8169_tx_clear(tp);
4188
4189 if (tp->dirty_rx == tp->cur_rx) {
4190 rtl8169_init_ring_indexes(tp);
07ce4064 4191 rtl_hw_start(dev);
1da177e4 4192 netif_wake_queue(dev);
cebf8cc7 4193 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4194 } else {
bf82c189
JP		 4195 if (net_ratelimit())
4196 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4197 rtl8169_schedule_work(dev, rtl8169_reset_task);
4198 }
eb2a021c
FR		 4199
4200out_unlock:
4201 rtnl_unlock();
1da177e4
LT		 4202}
4203
4204static void rtl8169_tx_timeout(struct net_device *dev)
4205{
4206 struct rtl8169_private *tp = netdev_priv(dev);
4207
4208 rtl8169_hw_reset(tp->mmio_addr);
4209
4210 /* Let's wait a bit while any (async) irq lands on */
4211 rtl8169_schedule_work(dev, rtl8169_reset_task);
4212}
4213
4214static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4215 u32 opts1)
4216{
4217 struct skb_shared_info *info = skb_shinfo(skb);
4218 unsigned int cur_frag, entry;
a6343afb 4219 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4220
4221 entry = tp->cur_tx;
4222 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4223 skb_frag_t *frag = info->frags + cur_frag;
4224 dma_addr_t mapping;
4225 u32 status, len;
4226 void *addr;
4227
4228 entry = (entry + 1) % NUM_TX_DESC;
4229
4230 txd = tp->TxDescArray + entry;
4231 len = frag->size;
4232 addr = ((void *) page_address(frag->page)) + frag->page_offset;
82553bb6
SG		 4233 mapping = dma_map_single(&tp->pci_dev->dev, addr, len,
4234 PCI_DMA_TODEVICE);
3eafe507
SG		 4235 if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping)))
4236 goto err_out;
1da177e4
LT		 4237
4238 /* anti gcc 2.95.3 bugware (sic) */
4239 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4240
4241 txd->opts1 = cpu_to_le32(status);
4242 txd->addr = cpu_to_le64(mapping);
4243
4244 tp->tx_skb[entry].len = len;
4245 }
4246
4247 if (cur_frag) {
4248 tp->tx_skb[entry].skb = skb;
4249 txd->opts1 |= cpu_to_le32(LastFrag);
4250 }
4251
4252 return cur_frag;
3eafe507
SG		 4253
4254err_out:
4255 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4256 return -EIO;
1da177e4
LT		 4257}
4258
4259static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4260{
4261 if (dev->features & NETIF_F_TSO) {
7967168c 4262 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4263
4264 if (mss)
4265 return LargeSend | ((mss & MSSMask) << MSSShift);
4266 }
84fa7933 4267 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4268 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4269
4270 if (ip->protocol == IPPROTO_TCP)
4271 return IPCS | TCPCS;
4272 else if (ip->protocol == IPPROTO_UDP)
4273 return IPCS | UDPCS;
4274 WARN_ON(1); /* we need a WARN() */
4275 }
4276 return 0;
4277}
4278
61357325
SH		 4279static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4280 struct net_device *dev)
1da177e4
LT		 4281{
4282 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4283 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4284 struct TxDesc *txd = tp->TxDescArray + entry;
4285 void __iomem *ioaddr = tp->mmio_addr;
4286 dma_addr_t mapping;
4287 u32 status, len;
4288 u32 opts1;
3eafe507 4289 int frags;
5b0384f4 4290
1da177e4 4291 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4292 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4293 goto err_stop_0;
1da177e4
LT		 4294 }
4295
4296 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4297 goto err_stop_0;
4298
4299 len = skb_headlen(skb);
4300 mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len,
4301 PCI_DMA_TODEVICE);
4302 if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping)))
4303 goto err_dma_0;
4304
4305 tp->tx_skb[entry].len = len;
4306 txd->addr = cpu_to_le64(mapping);
4307 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4308
4309 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4310
4311 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4312 if (frags < 0)
4313 goto err_dma_1;
4314 else if (frags)
1da177e4 4315 opts1 |= FirstFrag;
3eafe507 4316 else {
1da177e4
LT		 4317 opts1 |= FirstFrag | LastFrag;
4318 tp->tx_skb[entry].skb = skb;
4319 }
4320
1da177e4
LT		 4321 wmb();
4322
4323 /* anti gcc 2.95.3 bugware (sic) */
4324 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4325 txd->opts1 = cpu_to_le32(status);
4326
1da177e4
LT		 4327 tp->cur_tx += frags + 1;
4328
4c020a96 4329 wmb();
1da177e4 4330
275391a4 4331 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4332
4333 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4334 netif_stop_queue(dev);
4335 smp_rmb();
4336 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4337 netif_wake_queue(dev);
4338 }
4339
61357325 4340 return NETDEV_TX_OK;
1da177e4 4341
3eafe507
SG		 4342err_dma_1:
4343 rtl8169_unmap_tx_skb(tp->pci_dev, tp->tx_skb + entry, txd);
4344err_dma_0:
4345 dev_kfree_skb(skb);
4346 dev->stats.tx_dropped++;
4347 return NETDEV_TX_OK;
4348
4349err_stop_0:
1da177e4 4350 netif_stop_queue(dev);
cebf8cc7 4351 dev->stats.tx_dropped++;
61357325 4352 return NETDEV_TX_BUSY;
1da177e4
LT		 4353}
4354
4355static void rtl8169_pcierr_interrupt(struct net_device *dev)
4356{
4357 struct rtl8169_private *tp = netdev_priv(dev);
4358 struct pci_dev *pdev = tp->pci_dev;
4359 void __iomem *ioaddr = tp->mmio_addr;
4360 u16 pci_status, pci_cmd;
4361
4362 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4363 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4364
bf82c189
JP		 4365 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4366 pci_cmd, pci_status);
1da177e4
LT		 4367
4368 /*
4369 * The recovery sequence below admits a very elaborated explanation:
4370 * - it seems to work;
d03902b8
FR		 4371 * - I did not see what else could be done;
4372 * - it makes iop3xx happy.
1da177e4
LT		 4373 *
4374 * Feel free to adjust to your needs.
4375 */
a27993f3 4376 if (pdev->broken_parity_status)
d03902b8
FR		 4377 pci_cmd &= ~PCI_COMMAND_PARITY;
4378 else
4379 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4380
4381 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4382
4383 pci_write_config_word(pdev, PCI_STATUS,
4384 pci_status & (PCI_STATUS_DETECTED_PARITY |
4385 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4386 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4387
4388 /* The infamous DAC f*ckup only happens at boot time */
4389 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4390 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4391 tp->cp_cmd &= ~PCIDAC;
4392 RTL_W16(CPlusCmd, tp->cp_cmd);
4393 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4394 }
4395
4396 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4397
4398 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4399}
4400
07d3f51f
FR		 4401static void rtl8169_tx_interrupt(struct net_device *dev,
4402 struct rtl8169_private *tp,
4403 void __iomem *ioaddr)
1da177e4
LT		 4404{
4405 unsigned int dirty_tx, tx_left;
4406
1da177e4
LT		 4407 dirty_tx = tp->dirty_tx;
4408 smp_rmb();
4409 tx_left = tp->cur_tx - dirty_tx;
4410
4411 while (tx_left > 0) {
4412 unsigned int entry = dirty_tx % NUM_TX_DESC;
4413 struct ring_info *tx_skb = tp->tx_skb + entry;
4414 u32 len = tx_skb->len;
4415 u32 status;
4416
4417 rmb();
4418 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4419 if (status & DescOwn)
4420 break;
4421
cebf8cc7
FR		 4422 dev->stats.tx_bytes += len;
4423 dev->stats.tx_packets++;
1da177e4
LT		 4424
4425 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4426
4427 if (status & LastFrag) {
87433bfc 4428 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4429 tx_skb->skb = NULL;
4430 }
4431 dirty_tx++;
4432 tx_left--;
4433 }
4434
4435 if (tp->dirty_tx != dirty_tx) {
4436 tp->dirty_tx = dirty_tx;
4437 smp_wmb();
4438 if (netif_queue_stopped(dev) &&
4439 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4440 netif_wake_queue(dev);
4441 }
d78ae2dc
FR		 4442 /*
4443 * 8168 hack: TxPoll requests are lost when the Tx packets are
4444 * too close. Let's kick an extra TxPoll request when a burst
4445 * of start_xmit activity is detected (if it is not detected,
4446 * it is slow enough). -- FR
4447 */
4448 smp_rmb();
4449 if (tp->cur_tx != dirty_tx)
4450 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4451 }
4452}
4453
126fa4b9
FR		 4454static inline int rtl8169_fragmented_frame(u32 status)
4455{
4456 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4457}
4458
adea1ac7 4459static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4460{
1da177e4
LT		 4461 u32 status = opts1 & RxProtoMask;
4462
4463 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4464 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4465 ((status == RxProtoIP) && !(opts1 & IPFail)))
4466 skb->ip_summed = CHECKSUM_UNNECESSARY;
4467 else
bc8acf2c 4468 skb_checksum_none_assert(skb);
1da177e4
LT		 4469}
4470
6f0333b8
ED		 4471static struct sk_buff *rtl8169_try_rx_copy(void *data,
4472 struct rtl8169_private *tp,
4473 int pkt_size,
4474 dma_addr_t addr)
1da177e4 4475{
b449655f 4476 struct sk_buff *skb;
b449655f 4477
6f0333b8 4478 data = rtl8169_align(data);
82553bb6
SG		 4479 dma_sync_single_for_cpu(&tp->pci_dev->dev, addr, pkt_size,
4480 PCI_DMA_FROMDEVICE);
6f0333b8
ED		 4481 prefetch(data);
4482 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4483 if (skb)
4484 memcpy(skb->data, data, pkt_size);
4485 dma_sync_single_for_device(&tp->pci_dev->dev, addr, pkt_size,
4486 PCI_DMA_FROMDEVICE);
4487 return skb;
1da177e4
LT		 4488}
4489
630b943c
ED		 4490/*
4491 * Warning : rtl8169_rx_interrupt() might be called :
4492 * 1) from NAPI (softirq) context
4493 * (polling = 1 : we should call netif_receive_skb())
4494 * 2) from process context (rtl8169_reset_task())
4495 * (polling = 0 : we must call netif_rx() instead)
4496 */
07d3f51f
FR		 4497static int rtl8169_rx_interrupt(struct net_device *dev,
4498 struct rtl8169_private *tp,
bea3348e 4499 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4500{
4501 unsigned int cur_rx, rx_left;
6f0333b8 4502 unsigned int count;
630b943c 4503 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4504
1da177e4
LT		 4505 cur_rx = tp->cur_rx;
4506 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4507 rx_left = min(rx_left, budget);
1da177e4 4508
4dcb7d33 4509 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4510 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4511 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4512 u32 status;
4513
4514 rmb();
126fa4b9 4515 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4516
4517 if (status & DescOwn)
4518 break;
4dcb7d33 4519 if (unlikely(status & RxRES)) {
bf82c189
JP		 4520 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4521 status);
cebf8cc7 4522 dev->stats.rx_errors++;
1da177e4 4523 if (status & (RxRWT | RxRUNT))
cebf8cc7 4524 dev->stats.rx_length_errors++;
1da177e4 4525 if (status & RxCRC)
cebf8cc7 4526 dev->stats.rx_crc_errors++;
9dccf611
FR		 4527 if (status & RxFOVF) {
4528 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4529 dev->stats.rx_fifo_errors++;
9dccf611 4530 }
6f0333b8 4531 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4532 } else {
6f0333b8 4533 struct sk_buff *skb;
b449655f 4534 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4535 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4536
126fa4b9
FR		 4537 /*
4538 * The driver does not support incoming fragmented
4539 * frames. They are seen as a symptom of over-mtu
4540 * sized frames.
4541 */
4542 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4543 dev->stats.rx_dropped++;
4544 dev->stats.rx_length_errors++;
6f0333b8 4545 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4546 continue;
126fa4b9
FR		 4547 }
4548
6f0333b8
ED		 4549 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4550 tp, pkt_size, addr);
4551 rtl8169_mark_to_asic(desc, rx_buf_sz);
4552 if (!skb) {
4553 dev->stats.rx_dropped++;
4554 continue;
1da177e4
LT		 4555 }
4556
adea1ac7 4557 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4558 skb_put(skb, pkt_size);
4559 skb->protocol = eth_type_trans(skb, dev);
4560
630b943c
ED		 4561 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4562 if (likely(polling))
2edae08e 4563 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4564 else
4565 netif_rx(skb);
4566 }
1da177e4 4567
cebf8cc7
FR		 4568 dev->stats.rx_bytes += pkt_size;
4569 dev->stats.rx_packets++;
1da177e4 4570 }
6dccd16b
FR		 4571
4572 /* Work around for AMD plateform. */
95e0918d 4573 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4574 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4575 desc->opts2 = 0;
4576 cur_rx++;
4577 }
1da177e4
LT		 4578 }
4579
4580 count = cur_rx - tp->cur_rx;
4581 tp->cur_rx = cur_rx;
4582
6f0333b8 4583 tp->dirty_rx += count;
1da177e4
LT		 4584
4585 return count;
4586}
4587
07d3f51f 4588static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4589{
07d3f51f 4590 struct net_device *dev = dev_instance;
1da177e4 4591 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4592 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4593 int handled = 0;
865c652d 4594 int status;
1da177e4 4595
f11a377b
DD		 4596 /* loop handling interrupts until we have no new ones or
4597 * we hit a invalid/hotplug case.
4598 */
865c652d 4599 status = RTL_R16(IntrStatus);
f11a377b
DD		 4600 while (status && status != 0xffff) {
4601 handled = 1;
1da177e4 4602
f11a377b
DD		 4603 /* Handle all of the error cases first. These will reset
4604 * the chip, so just exit the loop.
4605 */
4606 if (unlikely(!netif_running(dev))) {
4607 rtl8169_asic_down(ioaddr);
4608 break;
4609 }
1da177e4 4610
f11a377b 4611 /* Work around for rx fifo overflow */
801e147c 4612 if (unlikely(status & RxFIFOOver)) {
f11a377b
DD		 4613 netif_stop_queue(dev);
4614 rtl8169_tx_timeout(dev);
4615 break;
4616 }
1da177e4 4617
f11a377b
DD		 4618 if (unlikely(status & SYSErr)) {
4619 rtl8169_pcierr_interrupt(dev);
4620 break;
4621 }
1da177e4 4622
f11a377b
DD		 4623 if (status & LinkChg)
4624 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4625
f11a377b
DD		 4626 /* We need to see the lastest version of tp->intr_mask to
4627 * avoid ignoring an MSI interrupt and having to wait for
4628 * another event which may never come.
4629 */
4630 smp_rmb();
4631 if (status & tp->intr_mask & tp->napi_event) {
4632 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4633 tp->intr_mask = ~tp->napi_event;
4634
4635 if (likely(napi_schedule_prep(&tp->napi)))
4636 __napi_schedule(&tp->napi);
bf82c189
JP		 4637 else
4638 netif_info(tp, intr, dev,
4639 "interrupt %04x in poll\n", status);
f11a377b 4640 }
1da177e4 4641
f11a377b
DD		 4642 /* We only get a new MSI interrupt when all active irq
4643 * sources on the chip have been acknowledged. So, ack
4644 * everything we've seen and check if new sources have become
4645 * active to avoid blocking all interrupts from the chip.
4646 */
4647 RTL_W16(IntrStatus,
4648 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4649 status = RTL_R16(IntrStatus);
865c652d 4650 }
1da177e4 4651
1da177e4
LT		 4652 return IRQ_RETVAL(handled);
4653}
4654
bea3348e 4655static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4656{
bea3348e
SH		 4657 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4658 struct net_device *dev = tp->dev;
1da177e4 4659 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4660 int work_done;
1da177e4 4661
bea3348e 4662 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4663 rtl8169_tx_interrupt(dev, tp, ioaddr);
4664
bea3348e 4665 if (work_done < budget) {
288379f0 4666 napi_complete(napi);
f11a377b
DD		 4667
4668 /* We need for force the visibility of tp->intr_mask
4669 * for other CPUs, as we can loose an MSI interrupt
4670 * and potentially wait for a retransmit timeout if we don't.
4671 * The posted write to IntrMask is safe, as it will
4672 * eventually make it to the chip and we won't loose anything
4673 * until it does.
1da177e4 4674 */
f11a377b 4675 tp->intr_mask = 0xffff;
4c020a96 4676 wmb();
0e485150 4677 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4678 }
4679
bea3348e 4680 return work_done;
1da177e4 4681}
1da177e4 4682
523a6094
FR		 4683static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4684{
4685 struct rtl8169_private *tp = netdev_priv(dev);
4686
4687 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4688 return;
4689
4690 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4691 RTL_W32(RxMissed, 0);
4692}
4693
1da177e4
LT		 4694static void rtl8169_down(struct net_device *dev)
4695{
4696 struct rtl8169_private *tp = netdev_priv(dev);
4697 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4698 unsigned int intrmask;
1da177e4
LT		 4699
4700 rtl8169_delete_timer(dev);
4701
4702 netif_stop_queue(dev);
4703
93dd79e8 4704 napi_disable(&tp->napi);
93dd79e8 4705
1da177e4
LT		 4706core_down:
4707 spin_lock_irq(&tp->lock);
4708
4709 rtl8169_asic_down(ioaddr);
4710
523a6094 4711 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4712
4713 spin_unlock_irq(&tp->lock);
4714
4715 synchronize_irq(dev->irq);
4716
1da177e4 4717 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4718 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4719
4720 /*
4721 * And now for the 50k$ question: are IRQ disabled or not ?
4722 *
4723 * Two paths lead here:
4724 * 1) dev->close
4725 * -> netif_running() is available to sync the current code and the
4726 * IRQ handler. See rtl8169_interrupt for details.
4727 * 2) dev->change_mtu
4728 * -> rtl8169_poll can not be issued again and re-enable the
4729 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4730 *
4731 * No loop if hotpluged or major error (0xffff).
1da177e4 4732 */
733b736c
AP		 4733 intrmask = RTL_R16(IntrMask);
4734 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4735 goto core_down;
4736
4737 rtl8169_tx_clear(tp);
4738
4739 rtl8169_rx_clear(tp);
4740}
4741
4742static int rtl8169_close(struct net_device *dev)
4743{
4744 struct rtl8169_private *tp = netdev_priv(dev);
4745 struct pci_dev *pdev = tp->pci_dev;
4746
e1759441
RW		 4747 pm_runtime_get_sync(&pdev->dev);
4748
355423d0
IV		 4749 /* update counters before going down */
4750 rtl8169_update_counters(dev);
4751
1da177e4
LT		 4752 rtl8169_down(dev);
4753
4754 free_irq(dev->irq, dev);
4755
82553bb6
SG		 4756 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4757 tp->RxPhyAddr);
4758 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4759 tp->TxPhyAddr);
1da177e4
LT		 4760 tp->TxDescArray = NULL;
4761 tp->RxDescArray = NULL;
4762
e1759441
RW		 4763 pm_runtime_put_sync(&pdev->dev);
4764
1da177e4
LT		 4765 return 0;
4766}
4767
07ce4064 4768static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4769{
4770 struct rtl8169_private *tp = netdev_priv(dev);
4771 void __iomem *ioaddr = tp->mmio_addr;
4772 unsigned long flags;
4773 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4774 int rx_mode;
1da177e4
LT		 4775 u32 tmp = 0;
4776
4777 if (dev->flags & IFF_PROMISC) {
4778 /* Unconditionally log net taps. */
bf82c189 4779 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4780 rx_mode =
4781 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4782 AcceptAllPhys;
4783 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4784 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4785 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4786 /* Too many to filter perfectly -- accept all multicasts. */
4787 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4788 mc_filter[1] = mc_filter[0] = 0xffffffff;
4789 } else {
22bedad3 4790 struct netdev_hw_addr *ha;
07d3f51f 4791
1da177e4
LT		 4792 rx_mode = AcceptBroadcast | AcceptMyPhys;
4793 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4794 netdev_for_each_mc_addr(ha, dev) {
4795 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4796 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4797 rx_mode |= AcceptMulticast;
4798 }
4799 }
4800
4801 spin_lock_irqsave(&tp->lock, flags);
4802
4803 tmp = rtl8169_rx_config | rx_mode |
4804 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4805
f887cce8 4806 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4807 u32 data = mc_filter[0];
4808
4809 mc_filter[0] = swab32(mc_filter[1]);
4810 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4811 }
4812
1da177e4 4813 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4814 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4815
57a9f236
FR		 4816 RTL_W32(RxConfig, tmp);
4817
1da177e4
LT		 4818 spin_unlock_irqrestore(&tp->lock, flags);
4819}
4820
4821/**
4822 * rtl8169_get_stats - Get rtl8169 read/write statistics
4823 * @dev: The Ethernet Device to get statistics for
4824 *
4825 * Get TX/RX statistics for rtl8169
4826 */
4827static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4828{
4829 struct rtl8169_private *tp = netdev_priv(dev);
4830 void __iomem *ioaddr = tp->mmio_addr;
4831 unsigned long flags;
4832
4833 if (netif_running(dev)) {
4834 spin_lock_irqsave(&tp->lock, flags);
523a6094 4835 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4836 spin_unlock_irqrestore(&tp->lock, flags);
4837 }
5b0384f4 4838
cebf8cc7 4839 return &dev->stats;
1da177e4
LT		 4840}
4841
861ab440 4842static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4843{
5d06a99f 4844 if (!netif_running(dev))
861ab440 4845 return;
5d06a99f
FR		 4846
4847 netif_device_detach(dev);
4848 netif_stop_queue(dev);
861ab440
RW		 4849}
4850
4851#ifdef CONFIG_PM
4852
4853static int rtl8169_suspend(struct device *device)
4854{
4855 struct pci_dev *pdev = to_pci_dev(device);
4856 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4857
861ab440 4858 rtl8169_net_suspend(dev);
1371fa6d 4859
5d06a99f
FR		 4860 return 0;
4861}
4862
e1759441
RW		 4863static void __rtl8169_resume(struct net_device *dev)
4864{
4865 netif_device_attach(dev);
4866 rtl8169_schedule_work(dev, rtl8169_reset_task);
4867}
4868
861ab440 4869static int rtl8169_resume(struct device *device)
5d06a99f 4870{
861ab440 4871 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4872 struct net_device *dev = pci_get_drvdata(pdev);
4873
e1759441
RW		 4874 if (netif_running(dev))
4875 __rtl8169_resume(dev);
5d06a99f 4876
e1759441
RW		 4877 return 0;
4878}
4879
4880static int rtl8169_runtime_suspend(struct device *device)
4881{
4882 struct pci_dev *pdev = to_pci_dev(device);
4883 struct net_device *dev = pci_get_drvdata(pdev);
4884 struct rtl8169_private *tp = netdev_priv(dev);
4885
4886 if (!tp->TxDescArray)
4887 return 0;
4888
4889 spin_lock_irq(&tp->lock);
4890 tp->saved_wolopts = __rtl8169_get_wol(tp);
4891 __rtl8169_set_wol(tp, WAKE_ANY);
4892 spin_unlock_irq(&tp->lock);
4893
4894 rtl8169_net_suspend(dev);
4895
4896 return 0;
4897}
4898
4899static int rtl8169_runtime_resume(struct device *device)
4900{
4901 struct pci_dev *pdev = to_pci_dev(device);
4902 struct net_device *dev = pci_get_drvdata(pdev);
4903 struct rtl8169_private *tp = netdev_priv(dev);
4904
4905 if (!tp->TxDescArray)
4906 return 0;
4907
4908 spin_lock_irq(&tp->lock);
4909 __rtl8169_set_wol(tp, tp->saved_wolopts);
4910 tp->saved_wolopts = 0;
4911 spin_unlock_irq(&tp->lock);
4912
4913 __rtl8169_resume(dev);
5d06a99f 4914
5d06a99f
FR		 4915 return 0;
4916}
4917
e1759441
RW		 4918static int rtl8169_runtime_idle(struct device *device)
4919{
4920 struct pci_dev *pdev = to_pci_dev(device);
4921 struct net_device *dev = pci_get_drvdata(pdev);
4922 struct rtl8169_private *tp = netdev_priv(dev);
4923
4924 if (!tp->TxDescArray)
4925 return 0;
4926
4927 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4928 return -EBUSY;
4929}
4930
47145210 4931static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4932 .suspend = rtl8169_suspend,
4933 .resume = rtl8169_resume,
4934 .freeze = rtl8169_suspend,
4935 .thaw = rtl8169_resume,
4936 .poweroff = rtl8169_suspend,
4937 .restore = rtl8169_resume,
e1759441
RW		 4938 .runtime_suspend = rtl8169_runtime_suspend,
4939 .runtime_resume = rtl8169_runtime_resume,
4940 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4941};
4942
4943#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4944
4945#else /* !CONFIG_PM */
4946
4947#define RTL8169_PM_OPS NULL
4948
4949#endif /* !CONFIG_PM */
4950
1765f95d
FR		 4951static void rtl_shutdown(struct pci_dev *pdev)
4952{
861ab440 4953 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4954 struct rtl8169_private *tp = netdev_priv(dev);
4955 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4956
4957 rtl8169_net_suspend(dev);
1765f95d 4958
cc098dc7
IV		 4959 /* restore original MAC address */
4960 rtl_rar_set(tp, dev->perm_addr);
4961
4bb3f522 4962 spin_lock_irq(&tp->lock);
4963
4964 rtl8169_asic_down(ioaddr);
4965
4966 spin_unlock_irq(&tp->lock);
4967
861ab440 4968 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4969 /* WoL fails with some 8168 when the receiver is disabled. */
4970 if (tp->features & RTL_FEATURE_WOL) {
4971 pci_clear_master(pdev);
4972
4973 RTL_W8(ChipCmd, CmdRxEnb);
4974 /* PCI commit */
4975 RTL_R8(ChipCmd);
4976 }
4977
861ab440
RW		 4978 pci_wake_from_d3(pdev, true);
4979 pci_set_power_state(pdev, PCI_D3hot);
4980 }
4981}
5d06a99f 4982
1da177e4
LT		 4983static struct pci_driver rtl8169_pci_driver = {
4984 .name = MODULENAME,
4985 .id_table = rtl8169_pci_tbl,
4986 .probe = rtl8169_init_one,
4987 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4988 .shutdown = rtl_shutdown,
861ab440 4989 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4990};
4991
07d3f51f 4992static int __init rtl8169_init_module(void)
1da177e4 4993{
29917620 4994 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4995}
4996
07d3f51f 4997static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4998{
4999 pci_unregister_driver(&rtl8169_pci_driver);
5000}
5001
5002module_init(rtl8169_init_module);
5003module_exit(rtl8169_cleanup_module);
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