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r8169: cleanup
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
1da177e4
LT		 47#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59#ifdef CONFIG_R8169_NAPI
60#define rtl8169_rx_skb netif_receive_skb
0b50f81d 61#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 62#define rtl8169_rx_quota(count, quota) min(count, quota)
63#else
64#define rtl8169_rx_skb netif_rx
0b50f81d 65#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 66#define rtl8169_rx_quota(count, quota) count
67#endif
68
1da177e4 69/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 70static const int max_interrupt_work = 20;
1da177e4
LT		 71
72/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 74static const int multicast_filter_limit = 32;
1da177e4
LT		 75
76/* MAC address length */
77#define MAC_ADDR_LEN 6
78
79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 83#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87#define R8169_REGS_SIZE 256
88#define R8169_NAPI_WEIGHT 64
89#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91#define RX_BUF_SIZE 1536 /* Rx Buffer size */
92#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94
95#define RTL8169_TX_TIMEOUT (6*HZ)
96#define RTL8169_PHY_TIMEOUT (10*HZ)
97
98/* write/read MMIO register */
99#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb (ioaddr + (reg))
103#define RTL_R16(reg) readw (ioaddr + (reg))
104#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
105
106enum mac_version {
ba6eb6ee
FR		 107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 118};
119
120enum phy_version {
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
127};
128
1da177e4
LT		 129#define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131
3c6bee1d 132static const struct {
1da177e4
LT		 133 const char *name;
134 u8 mac_version;
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136} rtl_chip_info[] = {
ba6eb6ee
FR		 137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 148};
149#undef _R
150
bcf0bf90
FR		 151enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155};
156
07ce4064
FR		 157static void rtl_hw_start_8169(struct net_device *);
158static void rtl_hw_start_8168(struct net_device *);
159static void rtl_hw_start_8101(struct net_device *);
160
1da177e4 161static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 172 {0,},
173};
174
175MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176
177static int rx_copybreak = 200;
178static int use_dac;
b57b7e5a
SH		 179static struct {
180 u32 msg_enable;
181} debug = { -1 };
1da177e4 182
07d3f51f
FR		 183enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
185 MAR0 = 8, /* Multicast filter. */
186 CounterAddrLow = 0x10,
187 CounterAddrHigh = 0x14,
188 TxDescStartAddrLow = 0x20,
189 TxDescStartAddrHigh = 0x24,
190 TxHDescStartAddrLow = 0x28,
191 TxHDescStartAddrHigh = 0x2c,
192 FLASH = 0x30,
193 ERSR = 0x36,
194 ChipCmd = 0x37,
195 TxPoll = 0x38,
196 IntrMask = 0x3c,
197 IntrStatus = 0x3e,
198 TxConfig = 0x40,
199 RxConfig = 0x44,
200 RxMissed = 0x4c,
201 Cfg9346 = 0x50,
202 Config0 = 0x51,
203 Config1 = 0x52,
204 Config2 = 0x53,
205 Config3 = 0x54,
206 Config4 = 0x55,
207 Config5 = 0x56,
208 MultiIntr = 0x5c,
209 PHYAR = 0x60,
210 TBICSR = 0x64,
211 TBI_ANAR = 0x68,
212 TBI_LPAR = 0x6a,
213 PHYstatus = 0x6c,
214 RxMaxSize = 0xda,
215 CPlusCmd = 0xe0,
216 IntrMitigate = 0xe2,
217 RxDescAddrLow = 0xe4,
218 RxDescAddrHigh = 0xe8,
219 EarlyTxThres = 0xec,
220 FuncEvent = 0xf0,
221 FuncEventMask = 0xf4,
222 FuncPresetState = 0xf8,
223 FuncForceEvent = 0xfc,
1da177e4
LT		 224};
225
07d3f51f 226enum rtl_register_content {
1da177e4 227 /* InterruptStatusBits */
07d3f51f
FR		 228 SYSErr = 0x8000,
229 PCSTimeout = 0x4000,
230 SWInt = 0x0100,
231 TxDescUnavail = 0x0080,
232 RxFIFOOver = 0x0040,
233 LinkChg = 0x0020,
234 RxOverflow = 0x0010,
235 TxErr = 0x0008,
236 TxOK = 0x0004,
237 RxErr = 0x0002,
238 RxOK = 0x0001,
1da177e4
LT		 239
240 /* RxStatusDesc */
9dccf611
FR		 241 RxFOVF = (1 << 23),
242 RxRWT = (1 << 22),
243 RxRES = (1 << 21),
244 RxRUNT = (1 << 20),
245 RxCRC = (1 << 19),
1da177e4
LT		 246
247 /* ChipCmdBits */
07d3f51f
FR		 248 CmdReset = 0x10,
249 CmdRxEnb = 0x08,
250 CmdTxEnb = 0x04,
251 RxBufEmpty = 0x01,
1da177e4
LT		 252
253 /* Cfg9346Bits */
07d3f51f
FR		 254 Cfg9346_Lock = 0x00,
255 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 256
257 /* rx_mode_bits */
07d3f51f
FR		 258 AcceptErr = 0x20,
259 AcceptRunt = 0x10,
260 AcceptBroadcast = 0x08,
261 AcceptMulticast = 0x04,
262 AcceptMyPhys = 0x02,
263 AcceptAllPhys = 0x01,
1da177e4
LT		 264
265 /* RxConfigBits */
07d3f51f
FR		 266 RxCfgFIFOShift = 13,
267 RxCfgDMAShift = 8,
1da177e4
LT		 268
269 /* TxConfigBits */
270 TxInterFrameGapShift = 24,
271 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
272
5d06a99f
FR		 273 /* Config1 register p.24 */
274 PMEnable = (1 << 0), /* Power Management Enable */
275
6dccd16b
FR		 276 /* Config2 register p. 25 */
277 PCI_Clock_66MHz = 0x01,
278 PCI_Clock_33MHz = 0x00,
279
61a4dcc2
FR		 280 /* Config3 register p.25 */
281 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
282 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
283
5d06a99f 284 /* Config5 register p.27 */
61a4dcc2
FR		 285 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
286 MWF = (1 << 5), /* Accept Multicast wakeup frame */
287 UWF = (1 << 4), /* Accept Unicast wakeup frame */
288 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 289 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
290
1da177e4
LT		 291 /* TBICSR p.28 */
292 TBIReset = 0x80000000,
293 TBILoopback = 0x40000000,
294 TBINwEnable = 0x20000000,
295 TBINwRestart = 0x10000000,
296 TBILinkOk = 0x02000000,
297 TBINwComplete = 0x01000000,
298
299 /* CPlusCmd p.31 */
0e485150 300 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 301 RxVlan = (1 << 6),
302 RxChkSum = (1 << 5),
303 PCIDAC = (1 << 4),
304 PCIMulRW = (1 << 3),
0e485150
FR		 305 INTT_0 = 0x0000, // 8168
306 INTT_1 = 0x0001, // 8168
307 INTT_2 = 0x0002, // 8168
308 INTT_3 = 0x0003, // 8168
1da177e4
LT		 309
310 /* rtl8169_PHYstatus */
07d3f51f
FR		 311 TBI_Enable = 0x80,
312 TxFlowCtrl = 0x40,
313 RxFlowCtrl = 0x20,
314 _1000bpsF = 0x10,
315 _100bps = 0x08,
316 _10bps = 0x04,
317 LinkStatus = 0x02,
318 FullDup = 0x01,
1da177e4 319
1da177e4 320 /* _TBICSRBit */
07d3f51f 321 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 322
323 /* DumpCounterCommand */
07d3f51f 324 CounterDump = 0x8,
1da177e4
LT		 325};
326
07d3f51f 327enum desc_status_bit {
1da177e4
LT		 328 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
329 RingEnd = (1 << 30), /* End of descriptor ring */
330 FirstFrag = (1 << 29), /* First segment of a packet */
331 LastFrag = (1 << 28), /* Final segment of a packet */
332
333 /* Tx private */
334 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
335 MSSShift = 16, /* MSS value position */
336 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
337 IPCS = (1 << 18), /* Calculate IP checksum */
338 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
339 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
340 TxVlanTag = (1 << 17), /* Add VLAN tag */
341
342 /* Rx private */
343 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
344 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
345
346#define RxProtoUDP (PID1)
347#define RxProtoTCP (PID0)
348#define RxProtoIP (PID1 | PID0)
349#define RxProtoMask RxProtoIP
350
351 IPFail = (1 << 16), /* IP checksum failed */
352 UDPFail = (1 << 15), /* UDP/IP checksum failed */
353 TCPFail = (1 << 14), /* TCP/IP checksum failed */
354 RxVlanTag = (1 << 16), /* VLAN tag available */
355};
356
357#define RsvdMask 0x3fffc000
358
359struct TxDesc {
360 u32 opts1;
361 u32 opts2;
362 u64 addr;
363};
364
365struct RxDesc {
366 u32 opts1;
367 u32 opts2;
368 u64 addr;
369};
370
371struct ring_info {
372 struct sk_buff *skb;
373 u32 len;
374 u8 __pad[sizeof(void *) - sizeof(u32)];
375};
376
377struct rtl8169_private {
378 void __iomem *mmio_addr; /* memory map physical address */
379 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 380 struct net_device *dev;
1da177e4
LT		 381 struct net_device_stats stats; /* statistics of net device */
382 spinlock_t lock; /* spin lock flag */
b57b7e5a 383 u32 msg_enable;
1da177e4
LT		 384 int chipset;
385 int mac_version;
386 int phy_version;
387 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
388 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
389 u32 dirty_rx;
390 u32 dirty_tx;
391 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
392 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
393 dma_addr_t TxPhyAddr;
394 dma_addr_t RxPhyAddr;
395 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
396 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 397 unsigned align;
1da177e4
LT		 398 unsigned rx_buf_sz;
399 struct timer_list timer;
400 u16 cp_cmd;
0e485150
FR		 401 u16 intr_event;
402 u16 napi_event;
1da177e4
LT		 403 u16 intr_mask;
404 int phy_auto_nego_reg;
405 int phy_1000_ctrl_reg;
406#ifdef CONFIG_R8169_VLAN
407 struct vlan_group *vlgrp;
408#endif
409 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
410 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
411 void (*phy_reset_enable)(void __iomem *);
07ce4064 412 void (*hw_start)(struct net_device *);
1da177e4
LT		 413 unsigned int (*phy_reset_pending)(void __iomem *);
414 unsigned int (*link_ok)(void __iomem *);
c4028958 415 struct delayed_work task;
61a4dcc2 416 unsigned wol_enabled : 1;
1da177e4
LT		 417};
418
979b6c13 419MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 420MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 421module_param(rx_copybreak, int, 0);
1b7efd58 422MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 423module_param(use_dac, int, 0);
424MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 425module_param_named(debug, debug.msg_enable, int, 0);
426MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 427MODULE_LICENSE("GPL");
428MODULE_VERSION(RTL8169_VERSION);
429
430static int rtl8169_open(struct net_device *dev);
431static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 432static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 433static int rtl8169_init_ring(struct net_device *dev);
07ce4064 434static void rtl_hw_start(struct net_device *dev);
1da177e4 435static int rtl8169_close(struct net_device *dev);
07ce4064 436static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 437static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 438static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 439static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
440 void __iomem *);
4dcb7d33 441static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 442static void rtl8169_down(struct net_device *dev);
99f252b0 443static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 444
445#ifdef CONFIG_R8169_NAPI
446static int rtl8169_poll(struct net_device *dev, int *budget);
447#endif
448
1da177e4 449static const unsigned int rtl8169_rx_config =
5b0384f4 450 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 451
07d3f51f 452static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 453{
454 int i;
455
07d3f51f 456 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 457
2371408c 458 for (i = 20; i > 0; i--) {
07d3f51f
FR		 459 /*
460 * Check if the RTL8169 has completed writing to the specified
461 * MII register.
462 */
5b0384f4 463 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 464 break;
2371408c 465 udelay(25);
1da177e4
LT		 466 }
467}
468
07d3f51f 469static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 470{
471 int i, value = -1;
472
07d3f51f 473 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 474
2371408c 475 for (i = 20; i > 0; i--) {
07d3f51f
FR		 476 /*
477 * Check if the RTL8169 has completed retrieving data from
478 * the specified MII register.
479 */
1da177e4
LT		 480 if (RTL_R32(PHYAR) & 0x80000000) {
481 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
482 break;
483 }
2371408c 484 udelay(25);
1da177e4
LT		 485 }
486 return value;
487}
488
489static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
490{
491 RTL_W16(IntrMask, 0x0000);
492
493 RTL_W16(IntrStatus, 0xffff);
494}
495
496static void rtl8169_asic_down(void __iomem *ioaddr)
497{
498 RTL_W8(ChipCmd, 0x00);
499 rtl8169_irq_mask_and_ack(ioaddr);
500 RTL_R16(CPlusCmd);
501}
502
503static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
504{
505 return RTL_R32(TBICSR) & TBIReset;
506}
507
508static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
509{
64e4bfb4 510 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 511}
512
513static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
514{
515 return RTL_R32(TBICSR) & TBILinkOk;
516}
517
518static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
519{
520 return RTL_R8(PHYstatus) & LinkStatus;
521}
522
523static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
524{
525 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
526}
527
528static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
529{
530 unsigned int val;
531
9e0db8ef
FR		 532 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
533 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 534}
535
536static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 537 struct rtl8169_private *tp,
538 void __iomem *ioaddr)
1da177e4
LT		 539{
540 unsigned long flags;
541
542 spin_lock_irqsave(&tp->lock, flags);
543 if (tp->link_ok(ioaddr)) {
544 netif_carrier_on(dev);
b57b7e5a
SH		 545 if (netif_msg_ifup(tp))
546 printk(KERN_INFO PFX "%s: link up\n", dev->name);
547 } else {
548 if (netif_msg_ifdown(tp))
549 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 550 netif_carrier_off(dev);
b57b7e5a 551 }
1da177e4
LT		 552 spin_unlock_irqrestore(&tp->lock, flags);
553}
554
61a4dcc2
FR		 555static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
556{
557 struct rtl8169_private *tp = netdev_priv(dev);
558 void __iomem *ioaddr = tp->mmio_addr;
559 u8 options;
560
561 wol->wolopts = 0;
562
563#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
564 wol->supported = WAKE_ANY;
565
566 spin_lock_irq(&tp->lock);
567
568 options = RTL_R8(Config1);
569 if (!(options & PMEnable))
570 goto out_unlock;
571
572 options = RTL_R8(Config3);
573 if (options & LinkUp)
574 wol->wolopts |= WAKE_PHY;
575 if (options & MagicPacket)
576 wol->wolopts |= WAKE_MAGIC;
577
578 options = RTL_R8(Config5);
579 if (options & UWF)
580 wol->wolopts |= WAKE_UCAST;
581 if (options & BWF)
5b0384f4 582 wol->wolopts |= WAKE_BCAST;
61a4dcc2 583 if (options & MWF)
5b0384f4 584 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 585
586out_unlock:
587 spin_unlock_irq(&tp->lock);
588}
589
590static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
591{
592 struct rtl8169_private *tp = netdev_priv(dev);
593 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 594 unsigned int i;
61a4dcc2
FR		 595 static struct {
596 u32 opt;
597 u16 reg;
598 u8 mask;
599 } cfg[] = {
600 { WAKE_ANY, Config1, PMEnable },
601 { WAKE_PHY, Config3, LinkUp },
602 { WAKE_MAGIC, Config3, MagicPacket },
603 { WAKE_UCAST, Config5, UWF },
604 { WAKE_BCAST, Config5, BWF },
605 { WAKE_MCAST, Config5, MWF },
606 { WAKE_ANY, Config5, LanWake }
607 };
608
609 spin_lock_irq(&tp->lock);
610
611 RTL_W8(Cfg9346, Cfg9346_Unlock);
612
613 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
614 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
615 if (wol->wolopts & cfg[i].opt)
616 options |= cfg[i].mask;
617 RTL_W8(cfg[i].reg, options);
618 }
619
620 RTL_W8(Cfg9346, Cfg9346_Lock);
621
622 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
623
624 spin_unlock_irq(&tp->lock);
625
626 return 0;
627}
628
1da177e4
LT		 629static void rtl8169_get_drvinfo(struct net_device *dev,
630 struct ethtool_drvinfo *info)
631{
632 struct rtl8169_private *tp = netdev_priv(dev);
633
634 strcpy(info->driver, MODULENAME);
635 strcpy(info->version, RTL8169_VERSION);
636 strcpy(info->bus_info, pci_name(tp->pci_dev));
637}
638
639static int rtl8169_get_regs_len(struct net_device *dev)
640{
641 return R8169_REGS_SIZE;
642}
643
644static int rtl8169_set_speed_tbi(struct net_device *dev,
645 u8 autoneg, u16 speed, u8 duplex)
646{
647 struct rtl8169_private *tp = netdev_priv(dev);
648 void __iomem *ioaddr = tp->mmio_addr;
649 int ret = 0;
650 u32 reg;
651
652 reg = RTL_R32(TBICSR);
653 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
654 (duplex == DUPLEX_FULL)) {
655 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
656 } else if (autoneg == AUTONEG_ENABLE)
657 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
658 else {
b57b7e5a
SH		 659 if (netif_msg_link(tp)) {
660 printk(KERN_WARNING "%s: "
661 "incorrect speed setting refused in TBI mode\n",
662 dev->name);
663 }
1da177e4
LT		 664 ret = -EOPNOTSUPP;
665 }
666
667 return ret;
668}
669
670static int rtl8169_set_speed_xmii(struct net_device *dev,
671 u8 autoneg, u16 speed, u8 duplex)
672{
673 struct rtl8169_private *tp = netdev_priv(dev);
674 void __iomem *ioaddr = tp->mmio_addr;
675 int auto_nego, giga_ctrl;
676
64e4bfb4
FR		 677 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
678 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
679 ADVERTISE_100HALF | ADVERTISE_100FULL);
680 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
681 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 682
683 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 684 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
685 ADVERTISE_100HALF | ADVERTISE_100FULL);
686 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 687 } else {
688 if (speed == SPEED_10)
64e4bfb4 689 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 690 else if (speed == SPEED_100)
64e4bfb4 691 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 692 else if (speed == SPEED_1000)
64e4bfb4 693 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 694
695 if (duplex == DUPLEX_HALF)
64e4bfb4 696 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 697
698 if (duplex == DUPLEX_FULL)
64e4bfb4 699 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 700
701 /* This tweak comes straight from Realtek's driver. */
702 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
703 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 704 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 705 }
706 }
707
708 /* The 8100e/8101e do Fast Ethernet only. */
709 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
710 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
711 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 712 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 713 netif_msg_link(tp)) {
714 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
715 dev->name);
716 }
64e4bfb4 717 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 718 }
719
623a1593
FR		 720 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
721
1da177e4
LT		 722 tp->phy_auto_nego_reg = auto_nego;
723 tp->phy_1000_ctrl_reg = giga_ctrl;
724
64e4bfb4
FR		 725 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
726 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
727 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 728 return 0;
729}
730
731static int rtl8169_set_speed(struct net_device *dev,
732 u8 autoneg, u16 speed, u8 duplex)
733{
734 struct rtl8169_private *tp = netdev_priv(dev);
735 int ret;
736
737 ret = tp->set_speed(dev, autoneg, speed, duplex);
738
64e4bfb4 739 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 740 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
741
742 return ret;
743}
744
745static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
746{
747 struct rtl8169_private *tp = netdev_priv(dev);
748 unsigned long flags;
749 int ret;
750
751 spin_lock_irqsave(&tp->lock, flags);
752 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
753 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 754
1da177e4
LT		 755 return ret;
756}
757
758static u32 rtl8169_get_rx_csum(struct net_device *dev)
759{
760 struct rtl8169_private *tp = netdev_priv(dev);
761
762 return tp->cp_cmd & RxChkSum;
763}
764
765static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
766{
767 struct rtl8169_private *tp = netdev_priv(dev);
768 void __iomem *ioaddr = tp->mmio_addr;
769 unsigned long flags;
770
771 spin_lock_irqsave(&tp->lock, flags);
772
773 if (data)
774 tp->cp_cmd |= RxChkSum;
775 else
776 tp->cp_cmd &= ~RxChkSum;
777
778 RTL_W16(CPlusCmd, tp->cp_cmd);
779 RTL_R16(CPlusCmd);
780
781 spin_unlock_irqrestore(&tp->lock, flags);
782
783 return 0;
784}
785
786#ifdef CONFIG_R8169_VLAN
787
788static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
789 struct sk_buff *skb)
790{
791 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
792 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
793}
794
795static void rtl8169_vlan_rx_register(struct net_device *dev,
796 struct vlan_group *grp)
797{
798 struct rtl8169_private *tp = netdev_priv(dev);
799 void __iomem *ioaddr = tp->mmio_addr;
800 unsigned long flags;
801
802 spin_lock_irqsave(&tp->lock, flags);
803 tp->vlgrp = grp;
804 if (tp->vlgrp)
805 tp->cp_cmd |= RxVlan;
806 else
807 tp->cp_cmd &= ~RxVlan;
808 RTL_W16(CPlusCmd, tp->cp_cmd);
809 RTL_R16(CPlusCmd);
810 spin_unlock_irqrestore(&tp->lock, flags);
811}
812
1da177e4
LT		 813static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
814 struct sk_buff *skb)
815{
816 u32 opts2 = le32_to_cpu(desc->opts2);
817 int ret;
818
819 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 820 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 821 ret = 0;
822 } else
823 ret = -1;
824 desc->opts2 = 0;
825 return ret;
826}
827
828#else /* !CONFIG_R8169_VLAN */
829
830static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
831 struct sk_buff *skb)
832{
833 return 0;
834}
835
836static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
837 struct sk_buff *skb)
838{
839 return -1;
840}
841
842#endif
843
844static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
845{
846 struct rtl8169_private *tp = netdev_priv(dev);
847 void __iomem *ioaddr = tp->mmio_addr;
848 u32 status;
849
850 cmd->supported =
851 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
852 cmd->port = PORT_FIBRE;
853 cmd->transceiver = XCVR_INTERNAL;
854
855 status = RTL_R32(TBICSR);
856 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
857 cmd->autoneg = !!(status & TBINwEnable);
858
859 cmd->speed = SPEED_1000;
860 cmd->duplex = DUPLEX_FULL; /* Always set */
861}
862
863static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
864{
865 struct rtl8169_private *tp = netdev_priv(dev);
866 void __iomem *ioaddr = tp->mmio_addr;
867 u8 status;
868
869 cmd->supported = SUPPORTED_10baseT_Half |
870 SUPPORTED_10baseT_Full |
871 SUPPORTED_100baseT_Half |
872 SUPPORTED_100baseT_Full |
873 SUPPORTED_1000baseT_Full |
874 SUPPORTED_Autoneg |
5b0384f4 875 SUPPORTED_TP;
1da177e4
LT		 876
877 cmd->autoneg = 1;
878 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
879
64e4bfb4 880 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 881 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 882 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 883 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 884 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 885 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 886 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 887 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 888 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 889 cmd->advertising |= ADVERTISED_1000baseT_Full;
890
891 status = RTL_R8(PHYstatus);
892
893 if (status & _1000bpsF)
894 cmd->speed = SPEED_1000;
895 else if (status & _100bps)
896 cmd->speed = SPEED_100;
897 else if (status & _10bps)
898 cmd->speed = SPEED_10;
899
623a1593
FR		 900 if (status & TxFlowCtrl)
901 cmd->advertising |= ADVERTISED_Asym_Pause;
902 if (status & RxFlowCtrl)
903 cmd->advertising |= ADVERTISED_Pause;
904
1da177e4
LT		 905 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
906 DUPLEX_FULL : DUPLEX_HALF;
907}
908
909static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
910{
911 struct rtl8169_private *tp = netdev_priv(dev);
912 unsigned long flags;
913
914 spin_lock_irqsave(&tp->lock, flags);
915
916 tp->get_settings(dev, cmd);
917
918 spin_unlock_irqrestore(&tp->lock, flags);
919 return 0;
920}
921
922static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
923 void *p)
924{
5b0384f4
FR		 925 struct rtl8169_private *tp = netdev_priv(dev);
926 unsigned long flags;
1da177e4 927
5b0384f4
FR		 928 if (regs->len > R8169_REGS_SIZE)
929 regs->len = R8169_REGS_SIZE;
1da177e4 930
5b0384f4
FR		 931 spin_lock_irqsave(&tp->lock, flags);
932 memcpy_fromio(p, tp->mmio_addr, regs->len);
933 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 934}
935
b57b7e5a
SH		 936static u32 rtl8169_get_msglevel(struct net_device *dev)
937{
938 struct rtl8169_private *tp = netdev_priv(dev);
939
940 return tp->msg_enable;
941}
942
943static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
944{
945 struct rtl8169_private *tp = netdev_priv(dev);
946
947 tp->msg_enable = value;
948}
949
d4a3a0fc
SH		 950static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
951 "tx_packets",
952 "rx_packets",
953 "tx_errors",
954 "rx_errors",
955 "rx_missed",
956 "align_errors",
957 "tx_single_collisions",
958 "tx_multi_collisions",
959 "unicast",
960 "broadcast",
961 "multicast",
962 "tx_aborted",
963 "tx_underrun",
964};
965
966struct rtl8169_counters {
967 u64 tx_packets;
968 u64 rx_packets;
969 u64 tx_errors;
970 u32 rx_errors;
971 u16 rx_missed;
972 u16 align_errors;
973 u32 tx_one_collision;
974 u32 tx_multi_collision;
975 u64 rx_unicast;
976 u64 rx_broadcast;
977 u32 rx_multicast;
978 u16 tx_aborted;
979 u16 tx_underun;
980};
981
982static int rtl8169_get_stats_count(struct net_device *dev)
983{
984 return ARRAY_SIZE(rtl8169_gstrings);
985}
986
987static void rtl8169_get_ethtool_stats(struct net_device *dev,
988 struct ethtool_stats *stats, u64 *data)
989{
990 struct rtl8169_private *tp = netdev_priv(dev);
991 void __iomem *ioaddr = tp->mmio_addr;
992 struct rtl8169_counters *counters;
993 dma_addr_t paddr;
994 u32 cmd;
995
996 ASSERT_RTNL();
997
998 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
999 if (!counters)
1000 return;
1001
1002 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1003 cmd = (u64)paddr & DMA_32BIT_MASK;
1004 RTL_W32(CounterAddrLow, cmd);
1005 RTL_W32(CounterAddrLow, cmd | CounterDump);
1006
1007 while (RTL_R32(CounterAddrLow) & CounterDump) {
1008 if (msleep_interruptible(1))
1009 break;
1010 }
1011
1012 RTL_W32(CounterAddrLow, 0);
1013 RTL_W32(CounterAddrHigh, 0);
1014
5b0384f4 1015 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1016 data[1] = le64_to_cpu(counters->rx_packets);
1017 data[2] = le64_to_cpu(counters->tx_errors);
1018 data[3] = le32_to_cpu(counters->rx_errors);
1019 data[4] = le16_to_cpu(counters->rx_missed);
1020 data[5] = le16_to_cpu(counters->align_errors);
1021 data[6] = le32_to_cpu(counters->tx_one_collision);
1022 data[7] = le32_to_cpu(counters->tx_multi_collision);
1023 data[8] = le64_to_cpu(counters->rx_unicast);
1024 data[9] = le64_to_cpu(counters->rx_broadcast);
1025 data[10] = le32_to_cpu(counters->rx_multicast);
1026 data[11] = le16_to_cpu(counters->tx_aborted);
1027 data[12] = le16_to_cpu(counters->tx_underun);
1028
1029 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1030}
1031
1032static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1033{
1034 switch(stringset) {
1035 case ETH_SS_STATS:
1036 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1037 break;
1038 }
1039}
1040
7282d491 1041static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1042 .get_drvinfo = rtl8169_get_drvinfo,
1043 .get_regs_len = rtl8169_get_regs_len,
1044 .get_link = ethtool_op_get_link,
1045 .get_settings = rtl8169_get_settings,
1046 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1047 .get_msglevel = rtl8169_get_msglevel,
1048 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1049 .get_rx_csum = rtl8169_get_rx_csum,
1050 .set_rx_csum = rtl8169_set_rx_csum,
1051 .get_tx_csum = ethtool_op_get_tx_csum,
1052 .set_tx_csum = ethtool_op_set_tx_csum,
1053 .get_sg = ethtool_op_get_sg,
1054 .set_sg = ethtool_op_set_sg,
1055 .get_tso = ethtool_op_get_tso,
1056 .set_tso = ethtool_op_set_tso,
1057 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1058 .get_wol = rtl8169_get_wol,
1059 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1060 .get_strings = rtl8169_get_strings,
1061 .get_stats_count = rtl8169_get_stats_count,
1062 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1063 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1064};
1065
07d3f51f
FR		 1066static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1067 int bitnum, int bitval)
1da177e4
LT		 1068{
1069 int val;
1070
1071 val = mdio_read(ioaddr, reg);
1072 val = (bitval == 1) ?
1073 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1074 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1075}
1076
07d3f51f
FR		 1077static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1078 void __iomem *ioaddr)
1da177e4 1079{
0e485150
FR		 1080 /*
1081 * The driver currently handles the 8168Bf and the 8168Be identically
1082 * but they can be identified more specifically through the test below
1083 * if needed:
1084 *
1085 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1086 *
1087 * Same thing for the 8101Eb and the 8101Ec:
1088 *
1089 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1090 */
1da177e4
LT		 1091 const struct {
1092 u32 mask;
1093 int mac_version;
1094 } mac_info[] = {
bcf0bf90
FR		 1095 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1096 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1097 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1098 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1099 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1100 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1101 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1102 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1103 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1104 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1105 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1106 }, *p = mac_info;
1107 u32 reg;
1108
6dccd16b 1109 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1110 while ((reg & p->mask) != p->mask)
1111 p++;
1112 tp->mac_version = p->mac_version;
1113}
1114
1115static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1116{
bcf0bf90 1117 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1118}
1119
07d3f51f
FR		 1120static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1121 void __iomem *ioaddr)
1da177e4
LT		 1122{
1123 const struct {
1124 u16 mask;
1125 u16 set;
1126 int phy_version;
1127 } phy_info[] = {
1128 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1129 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1130 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1131 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1132 }, *p = phy_info;
1133 u16 reg;
1134
64e4bfb4 1135 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1136 while ((reg & p->mask) != p->set)
1137 p++;
1138 tp->phy_version = p->phy_version;
1139}
1140
1141static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1142{
1143 struct {
1144 int version;
1145 char *msg;
1146 u32 reg;
1147 } phy_print[] = {
1148 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1149 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1150 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1151 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1152 { 0, NULL, 0x0000 }
1153 }, *p;
1154
1155 for (p = phy_print; p->msg; p++) {
1156 if (tp->phy_version == p->version) {
1157 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1158 return;
1159 }
1160 }
1161 dprintk("phy_version == Unknown\n");
1162}
1163
1164static void rtl8169_hw_phy_config(struct net_device *dev)
1165{
1166 struct rtl8169_private *tp = netdev_priv(dev);
1167 void __iomem *ioaddr = tp->mmio_addr;
1168 struct {
1169 u16 regs[5]; /* Beware of bit-sign propagation */
1170 } phy_magic[5] = { {
1171 { 0x0000, //w 4 15 12 0
1172 0x00a1, //w 3 15 0 00a1
1173 0x0008, //w 2 15 0 0008
1174 0x1020, //w 1 15 0 1020
1175 0x1000 } },{ //w 0 15 0 1000
1176 { 0x7000, //w 4 15 12 7
1177 0xff41, //w 3 15 0 ff41
1178 0xde60, //w 2 15 0 de60
1179 0x0140, //w 1 15 0 0140
1180 0x0077 } },{ //w 0 15 0 0077
1181 { 0xa000, //w 4 15 12 a
1182 0xdf01, //w 3 15 0 df01
1183 0xdf20, //w 2 15 0 df20
1184 0xff95, //w 1 15 0 ff95
1185 0xfa00 } },{ //w 0 15 0 fa00
1186 { 0xb000, //w 4 15 12 b
1187 0xff41, //w 3 15 0 ff41
1188 0xde20, //w 2 15 0 de20
1189 0x0140, //w 1 15 0 0140
1190 0x00bb } },{ //w 0 15 0 00bb
1191 { 0xf000, //w 4 15 12 f
1192 0xdf01, //w 3 15 0 df01
1193 0xdf20, //w 2 15 0 df20
1194 0xff95, //w 1 15 0 ff95
1195 0xbf00 } //w 0 15 0 bf00
1196 }
1197 }, *p = phy_magic;
07d3f51f 1198 unsigned int i;
1da177e4
LT		 1199
1200 rtl8169_print_mac_version(tp);
1201 rtl8169_print_phy_version(tp);
1202
bcf0bf90 1203 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1204 return;
1205 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1206 return;
1207
1208 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1209 dprintk("Do final_reg2.cfg\n");
1210
1211 /* Shazam ! */
1212
bcf0bf90 1213 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1214 mdio_write(ioaddr, 31, 0x0002);
1215 mdio_write(ioaddr, 1, 0x90d0);
1216 mdio_write(ioaddr, 31, 0x0000);
1217 return;
1218 }
1219
1220 /* phy config for RTL8169s mac_version C chip */
1221 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1222 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1223 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1224 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1225
1226 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1227 int val, pos = 4;
1228
1229 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1230 mdio_write(ioaddr, pos, val);
1231 while (--pos >= 0)
1232 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1233 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1234 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1235 }
1236 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1237}
1238
1239static void rtl8169_phy_timer(unsigned long __opaque)
1240{
1241 struct net_device *dev = (struct net_device *)__opaque;
1242 struct rtl8169_private *tp = netdev_priv(dev);
1243 struct timer_list *timer = &tp->timer;
1244 void __iomem *ioaddr = tp->mmio_addr;
1245 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1246
bcf0bf90 1247 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1248 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1249
64e4bfb4 1250 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1251 return;
1252
1253 spin_lock_irq(&tp->lock);
1254
1255 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1256 /*
1da177e4
LT		 1257 * A busy loop could burn quite a few cycles on nowadays CPU.
1258 * Let's delay the execution of the timer for a few ticks.
1259 */
1260 timeout = HZ/10;
1261 goto out_mod_timer;
1262 }
1263
1264 if (tp->link_ok(ioaddr))
1265 goto out_unlock;
1266
b57b7e5a
SH		 1267 if (netif_msg_link(tp))
1268 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1269
1270 tp->phy_reset_enable(ioaddr);
1271
1272out_mod_timer:
1273 mod_timer(timer, jiffies + timeout);
1274out_unlock:
1275 spin_unlock_irq(&tp->lock);
1276}
1277
1278static inline void rtl8169_delete_timer(struct net_device *dev)
1279{
1280 struct rtl8169_private *tp = netdev_priv(dev);
1281 struct timer_list *timer = &tp->timer;
1282
bcf0bf90 1283 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1284 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1285 return;
1286
1287 del_timer_sync(timer);
1288}
1289
1290static inline void rtl8169_request_timer(struct net_device *dev)
1291{
1292 struct rtl8169_private *tp = netdev_priv(dev);
1293 struct timer_list *timer = &tp->timer;
1294
bcf0bf90 1295 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1296 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1297 return;
1298
2efa53f3 1299 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1300}
1301
1302#ifdef CONFIG_NET_POLL_CONTROLLER
1303/*
1304 * Polling 'interrupt' - used by things like netconsole to send skbs
1305 * without having to re-enable interrupts. It's not called while
1306 * the interrupt routine is executing.
1307 */
1308static void rtl8169_netpoll(struct net_device *dev)
1309{
1310 struct rtl8169_private *tp = netdev_priv(dev);
1311 struct pci_dev *pdev = tp->pci_dev;
1312
1313 disable_irq(pdev->irq);
7d12e780 1314 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1315 enable_irq(pdev->irq);
1316}
1317#endif
1318
1319static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1320 void __iomem *ioaddr)
1321{
1322 iounmap(ioaddr);
1323 pci_release_regions(pdev);
1324 pci_disable_device(pdev);
1325 free_netdev(dev);
1326}
1327
bf793295
FR		 1328static void rtl8169_phy_reset(struct net_device *dev,
1329 struct rtl8169_private *tp)
1330{
1331 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1332 unsigned int i;
bf793295
FR		 1333
1334 tp->phy_reset_enable(ioaddr);
1335 for (i = 0; i < 100; i++) {
1336 if (!tp->phy_reset_pending(ioaddr))
1337 return;
1338 msleep(1);
1339 }
1340 if (netif_msg_link(tp))
1341 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1342}
1343
4ff96fa6
FR		 1344static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1345{
1346 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6
FR		 1347
1348 rtl8169_hw_phy_config(dev);
1349
1350 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1351 RTL_W8(0x82, 0x01);
1352
6dccd16b
FR		 1353 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1354
1355 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1356 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1357
bcf0bf90 1358 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1359 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1360 RTL_W8(0x82, 0x01);
1361 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1362 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1363 }
1364
bf793295
FR		 1365 rtl8169_phy_reset(dev, tp);
1366
901dda2b
FR		 1367 /*
1368 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1369 * only 8101. Don't panic.
1370 */
1371 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1372
1373 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1374 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1375}
1376
5f787a1a
FR		 1377static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1378{
1379 struct rtl8169_private *tp = netdev_priv(dev);
1380 struct mii_ioctl_data *data = if_mii(ifr);
1381
1382 if (!netif_running(dev))
1383 return -ENODEV;
1384
1385 switch (cmd) {
1386 case SIOCGMIIPHY:
1387 data->phy_id = 32; /* Internal PHY */
1388 return 0;
1389
1390 case SIOCGMIIREG:
1391 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1392 return 0;
1393
1394 case SIOCSMIIREG:
1395 if (!capable(CAP_NET_ADMIN))
1396 return -EPERM;
1397 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1398 return 0;
1399 }
1400 return -EOPNOTSUPP;
1401}
1402
0e485150
FR		 1403static const struct rtl_cfg_info {
1404 void (*hw_start)(struct net_device *);
1405 unsigned int region;
1406 unsigned int align;
1407 u16 intr_event;
1408 u16 napi_event;
1409} rtl_cfg_infos [] = {
1410 [RTL_CFG_0] = {
1411 .hw_start = rtl_hw_start_8169,
1412 .region = 1,
86402234 1413 .align = 2,
0e485150
FR		 1414 .intr_event = SYSErr | LinkChg | RxOverflow |
1415 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1416 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1417 },
1418 [RTL_CFG_1] = {
1419 .hw_start = rtl_hw_start_8168,
1420 .region = 2,
1421 .align = 8,
1422 .intr_event = SYSErr | LinkChg | RxOverflow |
1423 TxErr | TxOK | RxOK | RxErr,
1424 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1425 },
1426 [RTL_CFG_2] = {
1427 .hw_start = rtl_hw_start_8101,
1428 .region = 2,
1429 .align = 8,
1430 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1431 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1432 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1433 }
1434};
1435
1da177e4 1436static int __devinit
4ff96fa6 1437rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1438{
0e485150
FR		 1439 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1440 const unsigned int region = cfg->region;
1da177e4 1441 struct rtl8169_private *tp;
4ff96fa6
FR		 1442 struct net_device *dev;
1443 void __iomem *ioaddr;
07d3f51f
FR		 1444 unsigned int i;
1445 int rc;
1da177e4 1446
4ff96fa6
FR		 1447 if (netif_msg_drv(&debug)) {
1448 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1449 MODULENAME, RTL8169_VERSION);
1450 }
1da177e4 1451
1da177e4 1452 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1453 if (!dev) {
b57b7e5a 1454 if (netif_msg_drv(&debug))
9b91cf9d 1455 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1456 rc = -ENOMEM;
1457 goto out;
1da177e4
LT		 1458 }
1459
1460 SET_MODULE_OWNER(dev);
1461 SET_NETDEV_DEV(dev, &pdev->dev);
1462 tp = netdev_priv(dev);
c4028958 1463 tp->dev = dev;
b57b7e5a 1464 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1465
1466 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1467 rc = pci_enable_device(pdev);
b57b7e5a 1468 if (rc < 0) {
2e8a538d 1469 if (netif_msg_probe(tp))
9b91cf9d 1470 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1471 goto err_out_free_dev_1;
1da177e4
LT		 1472 }
1473
1474 rc = pci_set_mwi(pdev);
1475 if (rc < 0)
4ff96fa6 1476 goto err_out_disable_2;
1da177e4 1477
1da177e4 1478 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1479 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1480 if (netif_msg_probe(tp)) {
9b91cf9d 1481 dev_err(&pdev->dev,
bcf0bf90
FR		 1482 "region #%d not an MMIO resource, aborting\n",
1483 region);
4ff96fa6 1484 }
1da177e4 1485 rc = -ENODEV;
4ff96fa6 1486 goto err_out_mwi_3;
1da177e4 1487 }
4ff96fa6 1488
1da177e4 1489 /* check for weird/broken PCI region reporting */
bcf0bf90 1490 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1491 if (netif_msg_probe(tp)) {
9b91cf9d 1492 dev_err(&pdev->dev,
4ff96fa6
FR		 1493 "Invalid PCI region size(s), aborting\n");
1494 }
1da177e4 1495 rc = -ENODEV;
4ff96fa6 1496 goto err_out_mwi_3;
1da177e4
LT		 1497 }
1498
1499 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1500 if (rc < 0) {
2e8a538d 1501 if (netif_msg_probe(tp))
9b91cf9d 1502 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1503 goto err_out_mwi_3;
1da177e4
LT		 1504 }
1505
1506 tp->cp_cmd = PCIMulRW | RxChkSum;
1507
1508 if ((sizeof(dma_addr_t) > 4) &&
1509 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1510 tp->cp_cmd |= PCIDAC;
1511 dev->features |= NETIF_F_HIGHDMA;
1512 } else {
1513 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1514 if (rc < 0) {
4ff96fa6 1515 if (netif_msg_probe(tp)) {
9b91cf9d 1516 dev_err(&pdev->dev,
4ff96fa6
FR		 1517 "DMA configuration failed.\n");
1518 }
1519 goto err_out_free_res_4;
1da177e4
LT		 1520 }
1521 }
1522
1523 pci_set_master(pdev);
1524
1525 /* ioremap MMIO region */
bcf0bf90 1526 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1527 if (!ioaddr) {
b57b7e5a 1528 if (netif_msg_probe(tp))
9b91cf9d 1529 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1530 rc = -EIO;
4ff96fa6 1531 goto err_out_free_res_4;
1da177e4
LT		 1532 }
1533
1534 /* Unneeded ? Don't mess with Mrs. Murphy. */
1535 rtl8169_irq_mask_and_ack(ioaddr);
1536
1537 /* Soft reset the chip. */
1538 RTL_W8(ChipCmd, CmdReset);
1539
1540 /* Check that the chip has finished the reset. */
07d3f51f 1541 for (i = 0; i < 100; i++) {
1da177e4
LT		 1542 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1543 break;
b518fa8e 1544 msleep_interruptible(1);
1da177e4
LT		 1545 }
1546
1547 /* Identify chip attached to board */
1548 rtl8169_get_mac_version(tp, ioaddr);
1549 rtl8169_get_phy_version(tp, ioaddr);
1550
1551 rtl8169_print_mac_version(tp);
1552 rtl8169_print_phy_version(tp);
1553
1554 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1555 if (tp->mac_version == rtl_chip_info[i].mac_version)
1556 break;
1557 }
1558 if (i < 0) {
1559 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1560 if (netif_msg_probe(tp)) {
2e8a538d 1561 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1562 "unknown chip version, assuming %s\n",
1563 rtl_chip_info[0].name);
b57b7e5a 1564 }
1da177e4
LT		 1565 i++;
1566 }
1567 tp->chipset = i;
1568
5d06a99f
FR		 1569 RTL_W8(Cfg9346, Cfg9346_Unlock);
1570 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1571 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1572 RTL_W8(Cfg9346, Cfg9346_Lock);
1573
1da177e4
LT		 1574 if (RTL_R8(PHYstatus) & TBI_Enable) {
1575 tp->set_speed = rtl8169_set_speed_tbi;
1576 tp->get_settings = rtl8169_gset_tbi;
1577 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1578 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1579 tp->link_ok = rtl8169_tbi_link_ok;
1580
64e4bfb4 1581 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1582 } else {
1583 tp->set_speed = rtl8169_set_speed_xmii;
1584 tp->get_settings = rtl8169_gset_xmii;
1585 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1586 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1587 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1588
1589 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1590 }
1591
1592 /* Get MAC address. FIXME: read EEPROM */
1593 for (i = 0; i < MAC_ADDR_LEN; i++)
1594 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1595 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1596
1597 dev->open = rtl8169_open;
1598 dev->hard_start_xmit = rtl8169_start_xmit;
1599 dev->get_stats = rtl8169_get_stats;
1600 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1601 dev->stop = rtl8169_close;
1602 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1603 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1604 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1605 dev->irq = pdev->irq;
1606 dev->base_addr = (unsigned long) ioaddr;
1607 dev->change_mtu = rtl8169_change_mtu;
1608
1609#ifdef CONFIG_R8169_NAPI
1610 dev->poll = rtl8169_poll;
1611 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1612#endif
1613
1614#ifdef CONFIG_R8169_VLAN
1615 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1616 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1617#endif
1618
1619#ifdef CONFIG_NET_POLL_CONTROLLER
1620 dev->poll_controller = rtl8169_netpoll;
1621#endif
1622
1623 tp->intr_mask = 0xffff;
1624 tp->pci_dev = pdev;
1625 tp->mmio_addr = ioaddr;
0e485150
FR		 1626 tp->align = cfg->align;
1627 tp->hw_start = cfg->hw_start;
1628 tp->intr_event = cfg->intr_event;
1629 tp->napi_event = cfg->napi_event;
1da177e4 1630
2efa53f3
FR		 1631 init_timer(&tp->timer);
1632 tp->timer.data = (unsigned long) dev;
1633 tp->timer.function = rtl8169_phy_timer;
1634
1da177e4
LT		 1635 spin_lock_init(&tp->lock);
1636
1637 rc = register_netdev(dev);
4ff96fa6
FR		 1638 if (rc < 0)
1639 goto err_out_unmap_5;
1da177e4
LT		 1640
1641 pci_set_drvdata(pdev, dev);
1642
b57b7e5a
SH		 1643 if (netif_msg_probe(tp)) {
1644 printk(KERN_INFO "%s: %s at 0x%lx, "
1645 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1646 "IRQ %d\n",
1647 dev->name,
bcf0bf90 1648 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1649 dev->base_addr,
1650 dev->dev_addr[0], dev->dev_addr[1],
1651 dev->dev_addr[2], dev->dev_addr[3],
1652 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1653 }
1da177e4 1654
4ff96fa6 1655 rtl8169_init_phy(dev, tp);
1da177e4 1656
4ff96fa6
FR		 1657out:
1658 return rc;
1da177e4 1659
4ff96fa6
FR		 1660err_out_unmap_5:
1661 iounmap(ioaddr);
1662err_out_free_res_4:
1663 pci_release_regions(pdev);
1664err_out_mwi_3:
1665 pci_clear_mwi(pdev);
1666err_out_disable_2:
1667 pci_disable_device(pdev);
1668err_out_free_dev_1:
1669 free_netdev(dev);
1670 goto out;
1da177e4
LT		 1671}
1672
07d3f51f 1673static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1674{
1675 struct net_device *dev = pci_get_drvdata(pdev);
1676 struct rtl8169_private *tp = netdev_priv(dev);
1677
eb2a021c
FR		 1678 flush_scheduled_work();
1679
1da177e4
LT		 1680 unregister_netdev(dev);
1681 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1682 pci_set_drvdata(pdev, NULL);
1683}
1684
1da177e4
LT		 1685static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1686 struct net_device *dev)
1687{
1688 unsigned int mtu = dev->mtu;
1689
1690 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1691}
1692
1693static int rtl8169_open(struct net_device *dev)
1694{
1695 struct rtl8169_private *tp = netdev_priv(dev);
1696 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1697 int retval = -ENOMEM;
1da177e4 1698
1da177e4 1699
99f252b0 1700 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1701
1702 /*
1703 * Rx and Tx desscriptors needs 256 bytes alignment.
1704 * pci_alloc_consistent provides more.
1705 */
1706 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1707 &tp->TxPhyAddr);
1708 if (!tp->TxDescArray)
99f252b0 1709 goto out;
1da177e4
LT		 1710
1711 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1712 &tp->RxPhyAddr);
1713 if (!tp->RxDescArray)
99f252b0 1714 goto err_free_tx_0;
1da177e4
LT		 1715
1716 retval = rtl8169_init_ring(dev);
1717 if (retval < 0)
99f252b0 1718 goto err_free_rx_1;
1da177e4 1719
c4028958 1720 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1721
99f252b0
FR		 1722 smp_mb();
1723
1724 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1725 dev->name, dev);
1726 if (retval < 0)
1727 goto err_release_ring_2;
1728
07ce4064 1729 rtl_hw_start(dev);
1da177e4
LT		 1730
1731 rtl8169_request_timer(dev);
1732
1733 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1734out:
1735 return retval;
1736
99f252b0
FR		 1737err_release_ring_2:
1738 rtl8169_rx_clear(tp);
1739err_free_rx_1:
1da177e4
LT		 1740 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1741 tp->RxPhyAddr);
99f252b0 1742err_free_tx_0:
1da177e4
LT		 1743 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1744 tp->TxPhyAddr);
1da177e4
LT		 1745 goto out;
1746}
1747
1748static void rtl8169_hw_reset(void __iomem *ioaddr)
1749{
1750 /* Disable interrupts */
1751 rtl8169_irq_mask_and_ack(ioaddr);
1752
1753 /* Reset the chipset */
1754 RTL_W8(ChipCmd, CmdReset);
1755
1756 /* PCI commit */
1757 RTL_R8(ChipCmd);
1758}
1759
7f796d83 1760static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1761{
1762 void __iomem *ioaddr = tp->mmio_addr;
1763 u32 cfg = rtl8169_rx_config;
1764
1765 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1766 RTL_W32(RxConfig, cfg);
1767
1768 /* Set DMA burst size and Interframe Gap Time */
1769 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1770 (InterFrameGap << TxInterFrameGapShift));
1771}
1772
07ce4064 1773static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1774{
1775 struct rtl8169_private *tp = netdev_priv(dev);
1776 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1777 unsigned int i;
1da177e4
LT		 1778
1779 /* Soft reset the chip. */
1780 RTL_W8(ChipCmd, CmdReset);
1781
1782 /* Check that the chip has finished the reset. */
07d3f51f 1783 for (i = 0; i < 100; i++) {
1da177e4
LT		 1784 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1785 break;
b518fa8e 1786 msleep_interruptible(1);
1da177e4
LT		 1787 }
1788
07ce4064
FR		 1789 tp->hw_start(dev);
1790
07ce4064
FR		 1791 netif_start_queue(dev);
1792}
1793
1794
7f796d83
FR		 1795static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1796 void __iomem *ioaddr)
1797{
1798 /*
1799 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1800 * register to be written before TxDescAddrLow to work.
1801 * Switching from MMIO to I/O access fixes the issue as well.
1802 */
1803 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1804 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1805 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1806 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1807}
1808
1809static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1810{
1811 u16 cmd;
1812
1813 cmd = RTL_R16(CPlusCmd);
1814 RTL_W16(CPlusCmd, cmd);
1815 return cmd;
1816}
1817
1818static void rtl_set_rx_max_size(void __iomem *ioaddr)
1819{
1820 /* Low hurts. Let's disable the filtering. */
1821 RTL_W16(RxMaxSize, 16383);
1822}
1823
6dccd16b
FR		 1824static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1825{
1826 struct {
1827 u32 mac_version;
1828 u32 clk;
1829 u32 val;
1830 } cfg2_info [] = {
1831 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1832 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1833 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1834 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1835 }, *p = cfg2_info;
1836 unsigned int i;
1837 u32 clk;
1838
1839 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1840 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1841 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1842 RTL_W32(0x7c, p->val);
1843 break;
1844 }
1845 }
1846}
1847
07ce4064
FR		 1848static void rtl_hw_start_8169(struct net_device *dev)
1849{
1850 struct rtl8169_private *tp = netdev_priv(dev);
1851 void __iomem *ioaddr = tp->mmio_addr;
1852 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1853
9cb427b6
FR		 1854 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1855 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1856 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1857 }
1858
1da177e4 1859 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1860 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1861 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1862 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1863 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1864 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1865
1da177e4
LT		 1866 RTL_W8(EarlyTxThres, EarlyTxThld);
1867
7f796d83 1868 rtl_set_rx_max_size(ioaddr);
1da177e4 1869
6dccd16b 1870 rtl_set_rx_tx_config_registers(tp);
1da177e4 1871
7f796d83 1872 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1873
bcf0bf90
FR		 1874 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1876 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1877 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1878 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1879 }
1880
bcf0bf90
FR		 1881 RTL_W16(CPlusCmd, tp->cp_cmd);
1882
6dccd16b
FR		 1883 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1884
1da177e4
LT		 1885 /*
1886 * Undocumented corner. Supposedly:
1887 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1888 */
1889 RTL_W16(IntrMitigate, 0x0000);
1890
7f796d83 1891 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1892
1da177e4 1893 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1894
1895 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1896 RTL_R8(IntrMask);
1da177e4
LT		 1897
1898 RTL_W32(RxMissed, 0);
1899
07ce4064 1900 rtl_set_rx_mode(dev);
1da177e4
LT		 1901
1902 /* no early-rx interrupts */
1903 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 1904
1905 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 1906 RTL_W16(IntrMask, tp->intr_event);
6dccd16b
FR		 1907
1908 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 1909}
1da177e4 1910
07ce4064
FR		 1911static void rtl_hw_start_8168(struct net_device *dev)
1912{
2dd99530
FR		 1913 struct rtl8169_private *tp = netdev_priv(dev);
1914 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1915 struct pci_dev *pdev = tp->pci_dev;
1916 u8 ctl;
2dd99530
FR		 1917
1918 RTL_W8(Cfg9346, Cfg9346_Unlock);
1919
1920 RTL_W8(EarlyTxThres, EarlyTxThld);
1921
1922 rtl_set_rx_max_size(ioaddr);
1923
0e485150
FR		 1924 rtl_set_rx_tx_config_registers(tp);
1925
1926 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 1927
1928 RTL_W16(CPlusCmd, tp->cp_cmd);
1929
0e485150
FR		 1930 /* Tx performance tweak. */
1931 pci_read_config_byte(pdev, 0x69, &ctl);
1932 ctl = (ctl & ~0x70) | 0x50;
1933 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 1934
0e485150 1935 RTL_W16(IntrMitigate, 0x5151);
2dd99530 1936
0e485150
FR		 1937 /* Work around for RxFIFO overflow. */
1938 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1939 tp->intr_event |= RxFIFOOver | PCSTimeout;
1940 tp->intr_event &= ~RxOverflow;
1941 }
1942
1943 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 1944
1945 RTL_W8(Cfg9346, Cfg9346_Lock);
1946
1947 RTL_R8(IntrMask);
1948
1949 RTL_W32(RxMissed, 0);
1950
1951 rtl_set_rx_mode(dev);
1952
0e485150
FR		 1953 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1954
2dd99530 1955 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 1956
0e485150 1957 RTL_W16(IntrMask, tp->intr_event);
07ce4064 1958}
1da177e4 1959
07ce4064
FR		 1960static void rtl_hw_start_8101(struct net_device *dev)
1961{
cdf1a608
FR		 1962 struct rtl8169_private *tp = netdev_priv(dev);
1963 void __iomem *ioaddr = tp->mmio_addr;
1964 struct pci_dev *pdev = tp->pci_dev;
1965
1966 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1967 pci_write_config_word(pdev, 0x68, 0x00);
1968 pci_write_config_word(pdev, 0x69, 0x08);
1969 }
1970
1971 RTL_W8(Cfg9346, Cfg9346_Unlock);
1972
1973 RTL_W8(EarlyTxThres, EarlyTxThld);
1974
1975 rtl_set_rx_max_size(ioaddr);
1976
1977 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1978
1979 RTL_W16(CPlusCmd, tp->cp_cmd);
1980
1981 RTL_W16(IntrMitigate, 0x0000);
1982
1983 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1984
1985 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1986 rtl_set_rx_tx_config_registers(tp);
1987
1988 RTL_W8(Cfg9346, Cfg9346_Lock);
1989
1990 RTL_R8(IntrMask);
1991
1992 RTL_W32(RxMissed, 0);
1993
1994 rtl_set_rx_mode(dev);
1995
0e485150
FR		 1996 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1997
cdf1a608 1998 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 1999
0e485150 2000 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2001}
2002
2003static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2004{
2005 struct rtl8169_private *tp = netdev_priv(dev);
2006 int ret = 0;
2007
2008 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2009 return -EINVAL;
2010
2011 dev->mtu = new_mtu;
2012
2013 if (!netif_running(dev))
2014 goto out;
2015
2016 rtl8169_down(dev);
2017
2018 rtl8169_set_rxbufsize(tp, dev);
2019
2020 ret = rtl8169_init_ring(dev);
2021 if (ret < 0)
2022 goto out;
2023
2024 netif_poll_enable(dev);
2025
07ce4064 2026 rtl_hw_start(dev);
1da177e4
LT		 2027
2028 rtl8169_request_timer(dev);
2029
2030out:
2031 return ret;
2032}
2033
2034static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2035{
2036 desc->addr = 0x0badbadbadbadbadull;
2037 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2038}
2039
2040static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2041 struct sk_buff **sk_buff, struct RxDesc *desc)
2042{
2043 struct pci_dev *pdev = tp->pci_dev;
2044
2045 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2046 PCI_DMA_FROMDEVICE);
2047 dev_kfree_skb(*sk_buff);
2048 *sk_buff = NULL;
2049 rtl8169_make_unusable_by_asic(desc);
2050}
2051
2052static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2053{
2054 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2055
2056 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2057}
2058
2059static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2060 u32 rx_buf_sz)
2061{
2062 desc->addr = cpu_to_le64(mapping);
2063 wmb();
2064 rtl8169_mark_to_asic(desc, rx_buf_sz);
2065}
2066
15d31758
SH		 2067static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2068 struct net_device *dev,
2069 struct RxDesc *desc, int rx_buf_sz,
2070 unsigned int align)
1da177e4
LT		 2071{
2072 struct sk_buff *skb;
2073 dma_addr_t mapping;
1da177e4 2074
15d31758 2075 skb = netdev_alloc_skb(dev, rx_buf_sz + align);
1da177e4
LT		 2076 if (!skb)
2077 goto err_out;
2078
dcb92f88 2079 skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
1da177e4 2080
689be439 2081 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2082 PCI_DMA_FROMDEVICE);
2083
2084 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2085out:
15d31758 2086 return skb;
1da177e4
LT		 2087
2088err_out:
1da177e4
LT		 2089 rtl8169_make_unusable_by_asic(desc);
2090 goto out;
2091}
2092
2093static void rtl8169_rx_clear(struct rtl8169_private *tp)
2094{
07d3f51f 2095 unsigned int i;
1da177e4
LT		 2096
2097 for (i = 0; i < NUM_RX_DESC; i++) {
2098 if (tp->Rx_skbuff[i]) {
2099 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2100 tp->RxDescArray + i);
2101 }
2102 }
2103}
2104
2105static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2106 u32 start, u32 end)
2107{
2108 u32 cur;
5b0384f4 2109
4ae47c2d 2110 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2111 struct sk_buff *skb;
2112 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2113
4ae47c2d
FR		 2114 WARN_ON((s32)(end - cur) < 0);
2115
1da177e4
LT		 2116 if (tp->Rx_skbuff[i])
2117 continue;
bcf0bf90 2118
15d31758
SH		 2119 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2120 tp->RxDescArray + i,
2121 tp->rx_buf_sz, tp->align);
2122 if (!skb)
1da177e4 2123 break;
15d31758
SH		 2124
2125 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2126 }
2127 return cur - start;
2128}
2129
2130static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2131{
2132 desc->opts1 |= cpu_to_le32(RingEnd);
2133}
2134
2135static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2136{
2137 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2138}
2139
2140static int rtl8169_init_ring(struct net_device *dev)
2141{
2142 struct rtl8169_private *tp = netdev_priv(dev);
2143
2144 rtl8169_init_ring_indexes(tp);
2145
2146 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2147 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2148
2149 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2150 goto err_out;
2151
2152 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2153
2154 return 0;
2155
2156err_out:
2157 rtl8169_rx_clear(tp);
2158 return -ENOMEM;
2159}
2160
2161static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2162 struct TxDesc *desc)
2163{
2164 unsigned int len = tx_skb->len;
2165
2166 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2167 desc->opts1 = 0x00;
2168 desc->opts2 = 0x00;
2169 desc->addr = 0x00;
2170 tx_skb->len = 0;
2171}
2172
2173static void rtl8169_tx_clear(struct rtl8169_private *tp)
2174{
2175 unsigned int i;
2176
2177 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2178 unsigned int entry = i % NUM_TX_DESC;
2179 struct ring_info *tx_skb = tp->tx_skb + entry;
2180 unsigned int len = tx_skb->len;
2181
2182 if (len) {
2183 struct sk_buff *skb = tx_skb->skb;
2184
2185 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2186 tp->TxDescArray + entry);
2187 if (skb) {
2188 dev_kfree_skb(skb);
2189 tx_skb->skb = NULL;
2190 }
2191 tp->stats.tx_dropped++;
2192 }
2193 }
2194 tp->cur_tx = tp->dirty_tx = 0;
2195}
2196
c4028958 2197static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2198{
2199 struct rtl8169_private *tp = netdev_priv(dev);
2200
c4028958 2201 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2202 schedule_delayed_work(&tp->task, 4);
2203}
2204
2205static void rtl8169_wait_for_quiescence(struct net_device *dev)
2206{
2207 struct rtl8169_private *tp = netdev_priv(dev);
2208 void __iomem *ioaddr = tp->mmio_addr;
2209
2210 synchronize_irq(dev->irq);
2211
2212 /* Wait for any pending NAPI task to complete */
2213 netif_poll_disable(dev);
2214
2215 rtl8169_irq_mask_and_ack(ioaddr);
2216
2217 netif_poll_enable(dev);
2218}
2219
c4028958 2220static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2221{
c4028958
DH		 2222 struct rtl8169_private *tp =
2223 container_of(work, struct rtl8169_private, task.work);
2224 struct net_device *dev = tp->dev;
1da177e4
LT		 2225 int ret;
2226
eb2a021c
FR		 2227 rtnl_lock();
2228
2229 if (!netif_running(dev))
2230 goto out_unlock;
2231
2232 rtl8169_wait_for_quiescence(dev);
2233 rtl8169_close(dev);
1da177e4
LT		 2234
2235 ret = rtl8169_open(dev);
2236 if (unlikely(ret < 0)) {
07d3f51f
FR		 2237 if (net_ratelimit() && netif_msg_drv(tp)) {
2238 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2239 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2240 }
2241 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2242 }
eb2a021c
FR		 2243
2244out_unlock:
2245 rtnl_unlock();
1da177e4
LT		 2246}
2247
c4028958 2248static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2249{
c4028958
DH		 2250 struct rtl8169_private *tp =
2251 container_of(work, struct rtl8169_private, task.work);
2252 struct net_device *dev = tp->dev;
1da177e4 2253
eb2a021c
FR		 2254 rtnl_lock();
2255
1da177e4 2256 if (!netif_running(dev))
eb2a021c 2257 goto out_unlock;
1da177e4
LT		 2258
2259 rtl8169_wait_for_quiescence(dev);
2260
2261 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2262 rtl8169_tx_clear(tp);
2263
2264 if (tp->dirty_rx == tp->cur_rx) {
2265 rtl8169_init_ring_indexes(tp);
07ce4064 2266 rtl_hw_start(dev);
1da177e4
LT		 2267 netif_wake_queue(dev);
2268 } else {
07d3f51f
FR		 2269 if (net_ratelimit() && netif_msg_intr(tp)) {
2270 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2271 dev->name);
1da177e4
LT		 2272 }
2273 rtl8169_schedule_work(dev, rtl8169_reset_task);
2274 }
eb2a021c
FR		 2275
2276out_unlock:
2277 rtnl_unlock();
1da177e4
LT		 2278}
2279
2280static void rtl8169_tx_timeout(struct net_device *dev)
2281{
2282 struct rtl8169_private *tp = netdev_priv(dev);
2283
2284 rtl8169_hw_reset(tp->mmio_addr);
2285
2286 /* Let's wait a bit while any (async) irq lands on */
2287 rtl8169_schedule_work(dev, rtl8169_reset_task);
2288}
2289
2290static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2291 u32 opts1)
2292{
2293 struct skb_shared_info *info = skb_shinfo(skb);
2294 unsigned int cur_frag, entry;
2295 struct TxDesc *txd;
2296
2297 entry = tp->cur_tx;
2298 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2299 skb_frag_t *frag = info->frags + cur_frag;
2300 dma_addr_t mapping;
2301 u32 status, len;
2302 void *addr;
2303
2304 entry = (entry + 1) % NUM_TX_DESC;
2305
2306 txd = tp->TxDescArray + entry;
2307 len = frag->size;
2308 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2309 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2310
2311 /* anti gcc 2.95.3 bugware (sic) */
2312 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2313
2314 txd->opts1 = cpu_to_le32(status);
2315 txd->addr = cpu_to_le64(mapping);
2316
2317 tp->tx_skb[entry].len = len;
2318 }
2319
2320 if (cur_frag) {
2321 tp->tx_skb[entry].skb = skb;
2322 txd->opts1 |= cpu_to_le32(LastFrag);
2323 }
2324
2325 return cur_frag;
2326}
2327
2328static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2329{
2330 if (dev->features & NETIF_F_TSO) {
7967168c 2331 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2332
2333 if (mss)
2334 return LargeSend | ((mss & MSSMask) << MSSShift);
2335 }
84fa7933 2336 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2337 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2338
2339 if (ip->protocol == IPPROTO_TCP)
2340 return IPCS | TCPCS;
2341 else if (ip->protocol == IPPROTO_UDP)
2342 return IPCS | UDPCS;
2343 WARN_ON(1); /* we need a WARN() */
2344 }
2345 return 0;
2346}
2347
2348static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2349{
2350 struct rtl8169_private *tp = netdev_priv(dev);
2351 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2352 struct TxDesc *txd = tp->TxDescArray + entry;
2353 void __iomem *ioaddr = tp->mmio_addr;
2354 dma_addr_t mapping;
2355 u32 status, len;
2356 u32 opts1;
188f4af0 2357 int ret = NETDEV_TX_OK;
5b0384f4 2358
1da177e4 2359 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2360 if (netif_msg_drv(tp)) {
2361 printk(KERN_ERR
2362 "%s: BUG! Tx Ring full when queue awake!\n",
2363 dev->name);
2364 }
1da177e4
LT		 2365 goto err_stop;
2366 }
2367
2368 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2369 goto err_stop;
2370
2371 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2372
2373 frags = rtl8169_xmit_frags(tp, skb, opts1);
2374 if (frags) {
2375 len = skb_headlen(skb);
2376 opts1 |= FirstFrag;
2377 } else {
2378 len = skb->len;
2379
2380 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2381 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2382 goto err_update_stats;
2383 len = ETH_ZLEN;
2384 }
2385
2386 opts1 |= FirstFrag | LastFrag;
2387 tp->tx_skb[entry].skb = skb;
2388 }
2389
2390 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2391
2392 tp->tx_skb[entry].len = len;
2393 txd->addr = cpu_to_le64(mapping);
2394 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2395
2396 wmb();
2397
2398 /* anti gcc 2.95.3 bugware (sic) */
2399 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2400 txd->opts1 = cpu_to_le32(status);
2401
2402 dev->trans_start = jiffies;
2403
2404 tp->cur_tx += frags + 1;
2405
2406 smp_wmb();
2407
2408 RTL_W8(TxPoll, 0x40); /* set polling bit */
2409
2410 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2411 netif_stop_queue(dev);
2412 smp_rmb();
2413 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2414 netif_wake_queue(dev);
2415 }
2416
2417out:
2418 return ret;
2419
2420err_stop:
2421 netif_stop_queue(dev);
188f4af0 2422 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2423err_update_stats:
2424 tp->stats.tx_dropped++;
2425 goto out;
2426}
2427
2428static void rtl8169_pcierr_interrupt(struct net_device *dev)
2429{
2430 struct rtl8169_private *tp = netdev_priv(dev);
2431 struct pci_dev *pdev = tp->pci_dev;
2432 void __iomem *ioaddr = tp->mmio_addr;
2433 u16 pci_status, pci_cmd;
2434
2435 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2436 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2437
b57b7e5a
SH		 2438 if (netif_msg_intr(tp)) {
2439 printk(KERN_ERR
2440 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2441 dev->name, pci_cmd, pci_status);
2442 }
1da177e4
LT		 2443
2444 /*
2445 * The recovery sequence below admits a very elaborated explanation:
2446 * - it seems to work;
d03902b8
FR		 2447 * - I did not see what else could be done;
2448 * - it makes iop3xx happy.
1da177e4
LT		 2449 *
2450 * Feel free to adjust to your needs.
2451 */
a27993f3 2452 if (pdev->broken_parity_status)
d03902b8
FR		 2453 pci_cmd &= ~PCI_COMMAND_PARITY;
2454 else
2455 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2456
2457 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2458
2459 pci_write_config_word(pdev, PCI_STATUS,
2460 pci_status & (PCI_STATUS_DETECTED_PARITY |
2461 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2462 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2463
2464 /* The infamous DAC f*ckup only happens at boot time */
2465 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2466 if (netif_msg_intr(tp))
2467 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2468 tp->cp_cmd &= ~PCIDAC;
2469 RTL_W16(CPlusCmd, tp->cp_cmd);
2470 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2471 }
2472
2473 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2474
2475 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2476}
2477
07d3f51f
FR		 2478static void rtl8169_tx_interrupt(struct net_device *dev,
2479 struct rtl8169_private *tp,
2480 void __iomem *ioaddr)
1da177e4
LT		 2481{
2482 unsigned int dirty_tx, tx_left;
2483
1da177e4
LT		 2484 dirty_tx = tp->dirty_tx;
2485 smp_rmb();
2486 tx_left = tp->cur_tx - dirty_tx;
2487
2488 while (tx_left > 0) {
2489 unsigned int entry = dirty_tx % NUM_TX_DESC;
2490 struct ring_info *tx_skb = tp->tx_skb + entry;
2491 u32 len = tx_skb->len;
2492 u32 status;
2493
2494 rmb();
2495 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2496 if (status & DescOwn)
2497 break;
2498
2499 tp->stats.tx_bytes += len;
2500 tp->stats.tx_packets++;
2501
2502 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2503
2504 if (status & LastFrag) {
2505 dev_kfree_skb_irq(tx_skb->skb);
2506 tx_skb->skb = NULL;
2507 }
2508 dirty_tx++;
2509 tx_left--;
2510 }
2511
2512 if (tp->dirty_tx != dirty_tx) {
2513 tp->dirty_tx = dirty_tx;
2514 smp_wmb();
2515 if (netif_queue_stopped(dev) &&
2516 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2517 netif_wake_queue(dev);
2518 }
2519 }
2520}
2521
126fa4b9
FR		 2522static inline int rtl8169_fragmented_frame(u32 status)
2523{
2524 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2525}
2526
1da177e4
LT		 2527static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2528{
2529 u32 opts1 = le32_to_cpu(desc->opts1);
2530 u32 status = opts1 & RxProtoMask;
2531
2532 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2533 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2534 ((status == RxProtoIP) && !(opts1 & IPFail)))
2535 skb->ip_summed = CHECKSUM_UNNECESSARY;
2536 else
2537 skb->ip_summed = CHECKSUM_NONE;
2538}
2539
07d3f51f
FR		 2540static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2541 struct rtl8169_private *tp, int pkt_size,
2542 dma_addr_t addr)
1da177e4 2543{
b449655f
SH		 2544 struct sk_buff *skb;
2545 bool done = false;
1da177e4 2546
b449655f
SH		 2547 if (pkt_size >= rx_copybreak)
2548 goto out;
1da177e4 2549
07d3f51f 2550 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2551 if (!skb)
2552 goto out;
2553
07d3f51f
FR		 2554 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2555 PCI_DMA_FROMDEVICE);
86402234 2556 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2557 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2558 *sk_buff = skb;
2559 done = true;
2560out:
2561 return done;
1da177e4
LT		 2562}
2563
07d3f51f
FR		 2564static int rtl8169_rx_interrupt(struct net_device *dev,
2565 struct rtl8169_private *tp,
2566 void __iomem *ioaddr)
1da177e4
LT		 2567{
2568 unsigned int cur_rx, rx_left;
2569 unsigned int delta, count;
2570
1da177e4
LT		 2571 cur_rx = tp->cur_rx;
2572 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2573 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2574
4dcb7d33 2575 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2576 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2577 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2578 u32 status;
2579
2580 rmb();
126fa4b9 2581 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2582
2583 if (status & DescOwn)
2584 break;
4dcb7d33 2585 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2586 if (netif_msg_rx_err(tp)) {
2587 printk(KERN_INFO
2588 "%s: Rx ERROR. status = %08x\n",
2589 dev->name, status);
2590 }
1da177e4
LT		 2591 tp->stats.rx_errors++;
2592 if (status & (RxRWT | RxRUNT))
2593 tp->stats.rx_length_errors++;
2594 if (status & RxCRC)
2595 tp->stats.rx_crc_errors++;
9dccf611
FR		 2596 if (status & RxFOVF) {
2597 rtl8169_schedule_work(dev, rtl8169_reset_task);
2598 tp->stats.rx_fifo_errors++;
2599 }
126fa4b9 2600 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2601 } else {
1da177e4 2602 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2603 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2604 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2605 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2606
126fa4b9
FR		 2607 /*
2608 * The driver does not support incoming fragmented
2609 * frames. They are seen as a symptom of over-mtu
2610 * sized frames.
2611 */
2612 if (unlikely(rtl8169_fragmented_frame(status))) {
2613 tp->stats.rx_dropped++;
2614 tp->stats.rx_length_errors++;
2615 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2616 continue;
126fa4b9
FR		 2617 }
2618
1da177e4 2619 rtl8169_rx_csum(skb, desc);
bcf0bf90 2620
07d3f51f 2621 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2622 pci_dma_sync_single_for_device(pdev, addr,
2623 pkt_size, PCI_DMA_FROMDEVICE);
2624 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2625 } else {
2626 pci_unmap_single(pdev, addr, pkt_size,
2627 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2628 tp->Rx_skbuff[entry] = NULL;
2629 }
2630
1da177e4
LT		 2631 skb_put(skb, pkt_size);
2632 skb->protocol = eth_type_trans(skb, dev);
2633
2634 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2635 rtl8169_rx_skb(skb);
2636
2637 dev->last_rx = jiffies;
2638 tp->stats.rx_bytes += pkt_size;
2639 tp->stats.rx_packets++;
2640 }
6dccd16b
FR		 2641
2642 /* Work around for AMD plateform. */
2643 if ((desc->opts2 & 0xfffe000) &&
2644 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2645 desc->opts2 = 0;
2646 cur_rx++;
2647 }
1da177e4
LT		 2648 }
2649
2650 count = cur_rx - tp->cur_rx;
2651 tp->cur_rx = cur_rx;
2652
2653 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2654 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2655 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2656 tp->dirty_rx += delta;
2657
2658 /*
2659 * FIXME: until there is periodic timer to try and refill the ring,
2660 * a temporary shortage may definitely kill the Rx process.
2661 * - disable the asic to try and avoid an overflow and kick it again
2662 * after refill ?
2663 * - how do others driver handle this condition (Uh oh...).
2664 */
b57b7e5a 2665 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2666 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2667
2668 return count;
2669}
2670
07d3f51f 2671static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2672{
07d3f51f 2673 struct net_device *dev = dev_instance;
1da177e4
LT		 2674 struct rtl8169_private *tp = netdev_priv(dev);
2675 int boguscnt = max_interrupt_work;
2676 void __iomem *ioaddr = tp->mmio_addr;
2677 int status;
2678 int handled = 0;
2679
2680 do {
2681 status = RTL_R16(IntrStatus);
2682
2683 /* hotplug/major error/no more work/shared irq */
2684 if ((status == 0xFFFF) || !status)
2685 break;
2686
2687 handled = 1;
2688
2689 if (unlikely(!netif_running(dev))) {
2690 rtl8169_asic_down(ioaddr);
2691 goto out;
2692 }
2693
2694 status &= tp->intr_mask;
2695 RTL_W16(IntrStatus,
2696 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2697
0e485150
FR		 2698 if (!(status & tp->intr_event))
2699 break;
2700
2701 /* Work around for rx fifo overflow */
2702 if (unlikely(status & RxFIFOOver) &&
2703 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2704 netif_stop_queue(dev);
2705 rtl8169_tx_timeout(dev);
1da177e4 2706 break;
0e485150 2707 }
1da177e4
LT		 2708
2709 if (unlikely(status & SYSErr)) {
2710 rtl8169_pcierr_interrupt(dev);
2711 break;
2712 }
2713
2714 if (status & LinkChg)
2715 rtl8169_check_link_status(dev, tp, ioaddr);
2716
2717#ifdef CONFIG_R8169_NAPI
0e485150
FR		 2718 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2719 tp->intr_mask = ~tp->napi_event;
1da177e4
LT		 2720
2721 if (likely(netif_rx_schedule_prep(dev)))
2722 __netif_rx_schedule(dev);
b57b7e5a 2723 else if (netif_msg_intr(tp)) {
1da177e4 2724 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2725 dev->name, status);
1da177e4
LT		 2726 }
2727 break;
2728#else
2729 /* Rx interrupt */
07d3f51f 2730 if (status & (RxOK | RxOverflow | RxFIFOOver))
1da177e4 2731 rtl8169_rx_interrupt(dev, tp, ioaddr);
07d3f51f 2732
1da177e4
LT		 2733 /* Tx interrupt */
2734 if (status & (TxOK | TxErr))
2735 rtl8169_tx_interrupt(dev, tp, ioaddr);
2736#endif
2737
2738 boguscnt--;
2739 } while (boguscnt > 0);
2740
2741 if (boguscnt <= 0) {
7c8b2eb4 2742 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2743 printk(KERN_WARNING
2744 "%s: Too much work at interrupt!\n", dev->name);
2745 }
1da177e4
LT		 2746 /* Clear all interrupt sources. */
2747 RTL_W16(IntrStatus, 0xffff);
2748 }
2749out:
2750 return IRQ_RETVAL(handled);
2751}
2752
2753#ifdef CONFIG_R8169_NAPI
2754static int rtl8169_poll(struct net_device *dev, int *budget)
2755{
2756 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2757 struct rtl8169_private *tp = netdev_priv(dev);
2758 void __iomem *ioaddr = tp->mmio_addr;
2759
2760 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2761 rtl8169_tx_interrupt(dev, tp, ioaddr);
2762
2763 *budget -= work_done;
2764 dev->quota -= work_done;
2765
2766 if (work_done < work_to_do) {
2767 netif_rx_complete(dev);
2768 tp->intr_mask = 0xffff;
2769 /*
2770 * 20040426: the barrier is not strictly required but the
2771 * behavior of the irq handler could be less predictable
2772 * without it. Btw, the lack of flush for the posted pci
2773 * write is safe - FR
2774 */
2775 smp_wmb();
0e485150 2776 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2777 }
2778
2779 return (work_done >= work_to_do);
2780}
2781#endif
2782
2783static void rtl8169_down(struct net_device *dev)
2784{
2785 struct rtl8169_private *tp = netdev_priv(dev);
2786 void __iomem *ioaddr = tp->mmio_addr;
2787 unsigned int poll_locked = 0;
733b736c 2788 unsigned int intrmask;
1da177e4
LT		 2789
2790 rtl8169_delete_timer(dev);
2791
2792 netif_stop_queue(dev);
2793
1da177e4
LT		 2794core_down:
2795 spin_lock_irq(&tp->lock);
2796
2797 rtl8169_asic_down(ioaddr);
2798
2799 /* Update the error counts. */
2800 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2801 RTL_W32(RxMissed, 0);
2802
2803 spin_unlock_irq(&tp->lock);
2804
2805 synchronize_irq(dev->irq);
2806
2807 if (!poll_locked) {
2808 netif_poll_disable(dev);
2809 poll_locked++;
2810 }
2811
2812 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2813 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2814
2815 /*
2816 * And now for the 50k$ question: are IRQ disabled or not ?
2817 *
2818 * Two paths lead here:
2819 * 1) dev->close
2820 * -> netif_running() is available to sync the current code and the
2821 * IRQ handler. See rtl8169_interrupt for details.
2822 * 2) dev->change_mtu
2823 * -> rtl8169_poll can not be issued again and re-enable the
2824 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2825 *
2826 * No loop if hotpluged or major error (0xffff).
1da177e4 2827 */
733b736c
AP		 2828 intrmask = RTL_R16(IntrMask);
2829 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2830 goto core_down;
2831
2832 rtl8169_tx_clear(tp);
2833
2834 rtl8169_rx_clear(tp);
2835}
2836
2837static int rtl8169_close(struct net_device *dev)
2838{
2839 struct rtl8169_private *tp = netdev_priv(dev);
2840 struct pci_dev *pdev = tp->pci_dev;
2841
2842 rtl8169_down(dev);
2843
2844 free_irq(dev->irq, dev);
2845
2846 netif_poll_enable(dev);
2847
2848 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2849 tp->RxPhyAddr);
2850 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2851 tp->TxPhyAddr);
2852 tp->TxDescArray = NULL;
2853 tp->RxDescArray = NULL;
2854
2855 return 0;
2856}
2857
07ce4064 2858static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2859{
2860 struct rtl8169_private *tp = netdev_priv(dev);
2861 void __iomem *ioaddr = tp->mmio_addr;
2862 unsigned long flags;
2863 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2864 int rx_mode;
1da177e4
LT		 2865 u32 tmp = 0;
2866
2867 if (dev->flags & IFF_PROMISC) {
2868 /* Unconditionally log net taps. */
b57b7e5a
SH		 2869 if (netif_msg_link(tp)) {
2870 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2871 dev->name);
2872 }
1da177e4
LT		 2873 rx_mode =
2874 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2875 AcceptAllPhys;
2876 mc_filter[1] = mc_filter[0] = 0xffffffff;
2877 } else if ((dev->mc_count > multicast_filter_limit)
2878 || (dev->flags & IFF_ALLMULTI)) {
2879 /* Too many to filter perfectly -- accept all multicasts. */
2880 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2881 mc_filter[1] = mc_filter[0] = 0xffffffff;
2882 } else {
2883 struct dev_mc_list *mclist;
07d3f51f
FR		 2884 unsigned int i;
2885
1da177e4
LT		 2886 rx_mode = AcceptBroadcast | AcceptMyPhys;
2887 mc_filter[1] = mc_filter[0] = 0;
2888 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2889 i++, mclist = mclist->next) {
2890 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2891 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2892 rx_mode |= AcceptMulticast;
2893 }
2894 }
2895
2896 spin_lock_irqsave(&tp->lock, flags);
2897
2898 tmp = rtl8169_rx_config | rx_mode |
2899 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2900
bcf0bf90
FR		 2901 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2902 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2903 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2904 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2905 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2906 mc_filter[0] = 0xffffffff;
2907 mc_filter[1] = 0xffffffff;
2908 }
2909
1da177e4
LT		 2910 RTL_W32(RxConfig, tmp);
2911 RTL_W32(MAR0 + 0, mc_filter[0]);
2912 RTL_W32(MAR0 + 4, mc_filter[1]);
2913
2914 spin_unlock_irqrestore(&tp->lock, flags);
2915}
2916
2917/**
2918 * rtl8169_get_stats - Get rtl8169 read/write statistics
2919 * @dev: The Ethernet Device to get statistics for
2920 *
2921 * Get TX/RX statistics for rtl8169
2922 */
2923static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2924{
2925 struct rtl8169_private *tp = netdev_priv(dev);
2926 void __iomem *ioaddr = tp->mmio_addr;
2927 unsigned long flags;
2928
2929 if (netif_running(dev)) {
2930 spin_lock_irqsave(&tp->lock, flags);
2931 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2932 RTL_W32(RxMissed, 0);
2933 spin_unlock_irqrestore(&tp->lock, flags);
2934 }
5b0384f4 2935
1da177e4
LT		 2936 return &tp->stats;
2937}
2938
5d06a99f
FR		 2939#ifdef CONFIG_PM
2940
2941static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2942{
2943 struct net_device *dev = pci_get_drvdata(pdev);
2944 struct rtl8169_private *tp = netdev_priv(dev);
2945 void __iomem *ioaddr = tp->mmio_addr;
2946
2947 if (!netif_running(dev))
1371fa6d 2948 goto out_pci_suspend;
5d06a99f
FR		 2949
2950 netif_device_detach(dev);
2951 netif_stop_queue(dev);
2952
2953 spin_lock_irq(&tp->lock);
2954
2955 rtl8169_asic_down(ioaddr);
2956
2957 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2958 RTL_W32(RxMissed, 0);
2959
2960 spin_unlock_irq(&tp->lock);
2961
1371fa6d 2962out_pci_suspend:
5d06a99f 2963 pci_save_state(pdev);
61a4dcc2 2964 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 2965 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 2966
5d06a99f
FR		 2967 return 0;
2968}
2969
2970static int rtl8169_resume(struct pci_dev *pdev)
2971{
2972 struct net_device *dev = pci_get_drvdata(pdev);
2973
1371fa6d
FR		 2974 pci_set_power_state(pdev, PCI_D0);
2975 pci_restore_state(pdev);
2976 pci_enable_wake(pdev, PCI_D0, 0);
2977
5d06a99f
FR		 2978 if (!netif_running(dev))
2979 goto out;
2980
2981 netif_device_attach(dev);
2982
5d06a99f
FR		 2983 rtl8169_schedule_work(dev, rtl8169_reset_task);
2984out:
2985 return 0;
2986}
2987
2988#endif /* CONFIG_PM */
2989
1da177e4
LT		 2990static struct pci_driver rtl8169_pci_driver = {
2991 .name = MODULENAME,
2992 .id_table = rtl8169_pci_tbl,
2993 .probe = rtl8169_init_one,
2994 .remove = __devexit_p(rtl8169_remove_one),
2995#ifdef CONFIG_PM
2996 .suspend = rtl8169_suspend,
2997 .resume = rtl8169_resume,
2998#endif
2999};
3000
07d3f51f 3001static int __init rtl8169_init_module(void)
1da177e4 3002{
29917620 3003 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3004}
3005
07d3f51f 3006static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3007{
3008 pci_unregister_driver(&rtl8169_pci_driver);
3009}
3010
3011module_init(rtl8169_init_module);
3012module_exit(rtl8169_cleanup_module);
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