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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
116static int max_interrupt_work = 20;
117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
120static int multicast_filter_limit = 32;
121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
153 RTL_GIGA_MAC_VER_B = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */
155 RTL_GIGA_MAC_VER_D = 0x01,
156 RTL_GIGA_MAC_VER_E = 0x02,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
158};
159
160enum phy_version {
161 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
162 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
165 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
167};
168
169
170#define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
172
3c6bee1d 173static const struct {
1da177e4
LT		 174 const char *name;
175 u8 mac_version;
176 u32 RxConfigMask; /* Clears the bits supported by this chip */
177} rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
182};
183#undef _R
184
185static struct pci_device_id rtl8169_pci_tbl[] = {
53456f60
FR		 186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
187 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
188 { PCI_DEVICE(0x16ec, 0x0116), },
86f0cd50 189 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195static int rx_copybreak = 200;
196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4
LT		 200
201enum RTL8169_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 204 CounterAddrLow = 0x10,
205 CounterAddrHigh = 0x14,
1da177e4
LT		 206 TxDescStartAddrLow = 0x20,
207 TxDescStartAddrHigh = 0x24,
208 TxHDescStartAddrLow = 0x28,
209 TxHDescStartAddrHigh = 0x2c,
210 FLASH = 0x30,
211 ERSR = 0x36,
212 ChipCmd = 0x37,
213 TxPoll = 0x38,
214 IntrMask = 0x3C,
215 IntrStatus = 0x3E,
216 TxConfig = 0x40,
217 RxConfig = 0x44,
218 RxMissed = 0x4C,
219 Cfg9346 = 0x50,
220 Config0 = 0x51,
221 Config1 = 0x52,
222 Config2 = 0x53,
223 Config3 = 0x54,
224 Config4 = 0x55,
225 Config5 = 0x56,
226 MultiIntr = 0x5C,
227 PHYAR = 0x60,
228 TBICSR = 0x64,
229 TBI_ANAR = 0x68,
230 TBI_LPAR = 0x6A,
231 PHYstatus = 0x6C,
232 RxMaxSize = 0xDA,
233 CPlusCmd = 0xE0,
234 IntrMitigate = 0xE2,
235 RxDescAddrLow = 0xE4,
236 RxDescAddrHigh = 0xE8,
237 EarlyTxThres = 0xEC,
238 FuncEvent = 0xF0,
239 FuncEventMask = 0xF4,
240 FuncPresetState = 0xF8,
241 FuncForceEvent = 0xFC,
242};
243
244enum RTL8169_register_content {
245 /* InterruptStatusBits */
246 SYSErr = 0x8000,
247 PCSTimeout = 0x4000,
248 SWInt = 0x0100,
249 TxDescUnavail = 0x80,
250 RxFIFOOver = 0x40,
251 LinkChg = 0x20,
252 RxOverflow = 0x10,
253 TxErr = 0x08,
254 TxOK = 0x04,
255 RxErr = 0x02,
256 RxOK = 0x01,
257
258 /* RxStatusDesc */
259 RxRES = 0x00200000,
260 RxCRC = 0x00080000,
261 RxRUNT = 0x00100000,
262 RxRWT = 0x00400000,
263
264 /* ChipCmdBits */
265 CmdReset = 0x10,
266 CmdRxEnb = 0x08,
267 CmdTxEnb = 0x04,
268 RxBufEmpty = 0x01,
269
270 /* Cfg9346Bits */
271 Cfg9346_Lock = 0x00,
272 Cfg9346_Unlock = 0xC0,
273
274 /* rx_mode_bits */
275 AcceptErr = 0x20,
276 AcceptRunt = 0x10,
277 AcceptBroadcast = 0x08,
278 AcceptMulticast = 0x04,
279 AcceptMyPhys = 0x02,
280 AcceptAllPhys = 0x01,
281
282 /* RxConfigBits */
283 RxCfgFIFOShift = 13,
284 RxCfgDMAShift = 8,
285
286 /* TxConfigBits */
287 TxInterFrameGapShift = 24,
288 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
289
290 /* TBICSR p.28 */
291 TBIReset = 0x80000000,
292 TBILoopback = 0x40000000,
293 TBINwEnable = 0x20000000,
294 TBINwRestart = 0x10000000,
295 TBILinkOk = 0x02000000,
296 TBINwComplete = 0x01000000,
297
298 /* CPlusCmd p.31 */
299 RxVlan = (1 << 6),
300 RxChkSum = (1 << 5),
301 PCIDAC = (1 << 4),
302 PCIMulRW = (1 << 3),
303
304 /* rtl8169_PHYstatus */
305 TBI_Enable = 0x80,
306 TxFlowCtrl = 0x40,
307 RxFlowCtrl = 0x20,
308 _1000bpsF = 0x10,
309 _100bps = 0x08,
310 _10bps = 0x04,
311 LinkStatus = 0x02,
312 FullDup = 0x01,
313
314 /* GIGABIT_PHY_registers */
315 PHY_CTRL_REG = 0,
316 PHY_STAT_REG = 1,
317 PHY_AUTO_NEGO_REG = 4,
318 PHY_1000_CTRL_REG = 9,
319
320 /* GIGABIT_PHY_REG_BIT */
321 PHY_Restart_Auto_Nego = 0x0200,
322 PHY_Enable_Auto_Nego = 0x1000,
323
324 /* PHY_STAT_REG = 1 */
325 PHY_Auto_Neco_Comp = 0x0020,
326
327 /* PHY_AUTO_NEGO_REG = 4 */
328 PHY_Cap_10_Half = 0x0020,
329 PHY_Cap_10_Full = 0x0040,
330 PHY_Cap_100_Half = 0x0080,
331 PHY_Cap_100_Full = 0x0100,
332
333 /* PHY_1000_CTRL_REG = 9 */
334 PHY_Cap_1000_Full = 0x0200,
335
336 PHY_Cap_Null = 0x0,
337
338 /* _MediaType */
339 _10_Half = 0x01,
340 _10_Full = 0x02,
341 _100_Half = 0x04,
342 _100_Full = 0x08,
343 _1000_Full = 0x10,
344
345 /* _TBICSRBit */
346 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 347
348 /* DumpCounterCommand */
349 CounterDump = 0x8,
1da177e4
LT		 350};
351
352enum _DescStatusBit {
353 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
354 RingEnd = (1 << 30), /* End of descriptor ring */
355 FirstFrag = (1 << 29), /* First segment of a packet */
356 LastFrag = (1 << 28), /* Final segment of a packet */
357
358 /* Tx private */
359 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
360 MSSShift = 16, /* MSS value position */
361 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
362 IPCS = (1 << 18), /* Calculate IP checksum */
363 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
364 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
365 TxVlanTag = (1 << 17), /* Add VLAN tag */
366
367 /* Rx private */
368 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
369 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
370
371#define RxProtoUDP (PID1)
372#define RxProtoTCP (PID0)
373#define RxProtoIP (PID1 | PID0)
374#define RxProtoMask RxProtoIP
375
376 IPFail = (1 << 16), /* IP checksum failed */
377 UDPFail = (1 << 15), /* UDP/IP checksum failed */
378 TCPFail = (1 << 14), /* TCP/IP checksum failed */
379 RxVlanTag = (1 << 16), /* VLAN tag available */
380};
381
382#define RsvdMask 0x3fffc000
383
384struct TxDesc {
385 u32 opts1;
386 u32 opts2;
387 u64 addr;
388};
389
390struct RxDesc {
391 u32 opts1;
392 u32 opts2;
393 u64 addr;
394};
395
396struct ring_info {
397 struct sk_buff *skb;
398 u32 len;
399 u8 __pad[sizeof(void *) - sizeof(u32)];
400};
401
402struct rtl8169_private {
403 void __iomem *mmio_addr; /* memory map physical address */
404 struct pci_dev *pci_dev; /* Index of PCI device */
405 struct net_device_stats stats; /* statistics of net device */
406 spinlock_t lock; /* spin lock flag */
b57b7e5a 407 u32 msg_enable;
1da177e4
LT		 408 int chipset;
409 int mac_version;
410 int phy_version;
411 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
412 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
413 u32 dirty_rx;
414 u32 dirty_tx;
415 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
416 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
417 dma_addr_t TxPhyAddr;
418 dma_addr_t RxPhyAddr;
419 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
420 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
421 unsigned rx_buf_sz;
422 struct timer_list timer;
423 u16 cp_cmd;
424 u16 intr_mask;
425 int phy_auto_nego_reg;
426 int phy_1000_ctrl_reg;
427#ifdef CONFIG_R8169_VLAN
428 struct vlan_group *vlgrp;
429#endif
430 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
431 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
432 void (*phy_reset_enable)(void __iomem *);
433 unsigned int (*phy_reset_pending)(void __iomem *);
434 unsigned int (*link_ok)(void __iomem *);
435 struct work_struct task;
436};
437
979b6c13 438MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 439MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
440module_param_array(media, int, &num_media, 0);
df0a1bf6 441MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 442module_param(rx_copybreak, int, 0);
1b7efd58 443MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 444module_param(use_dac, int, 0);
445MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 446module_param_named(debug, debug.msg_enable, int, 0);
447MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 448MODULE_LICENSE("GPL");
449MODULE_VERSION(RTL8169_VERSION);
450
451static int rtl8169_open(struct net_device *dev);
452static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
453static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
454 struct pt_regs *regs);
455static int rtl8169_init_ring(struct net_device *dev);
456static void rtl8169_hw_start(struct net_device *dev);
457static int rtl8169_close(struct net_device *dev);
458static void rtl8169_set_rx_mode(struct net_device *dev);
459static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 460static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 461static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
462 void __iomem *);
4dcb7d33 463static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 464static void rtl8169_down(struct net_device *dev);
465
466#ifdef CONFIG_R8169_NAPI
467static int rtl8169_poll(struct net_device *dev, int *budget);
468#endif
469
470static const u16 rtl8169_intr_mask =
471 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
472static const u16 rtl8169_napi_event =
473 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
474static const unsigned int rtl8169_rx_config =
475 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
476
477#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
478#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
479#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
480#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
481
482static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
483{
484 int i;
485
486 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 487
2371408c 488 for (i = 20; i > 0; i--) {
1da177e4
LT		 489 /* Check if the RTL8169 has completed writing to the specified MII register */
490 if (!(RTL_R32(PHYAR) & 0x80000000))
491 break;
2371408c 492 udelay(25);
1da177e4
LT		 493 }
494}
495
496static int mdio_read(void __iomem *ioaddr, int RegAddr)
497{
498 int i, value = -1;
499
500 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 501
2371408c 502 for (i = 20; i > 0; i--) {
1da177e4
LT		 503 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
504 if (RTL_R32(PHYAR) & 0x80000000) {
505 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
506 break;
507 }
2371408c 508 udelay(25);
1da177e4
LT		 509 }
510 return value;
511}
512
513static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
514{
515 RTL_W16(IntrMask, 0x0000);
516
517 RTL_W16(IntrStatus, 0xffff);
518}
519
520static void rtl8169_asic_down(void __iomem *ioaddr)
521{
522 RTL_W8(ChipCmd, 0x00);
523 rtl8169_irq_mask_and_ack(ioaddr);
524 RTL_R16(CPlusCmd);
525}
526
527static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
528{
529 return RTL_R32(TBICSR) & TBIReset;
530}
531
532static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
533{
534 return mdio_read(ioaddr, 0) & 0x8000;
535}
536
537static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
538{
539 return RTL_R32(TBICSR) & TBILinkOk;
540}
541
542static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
543{
544 return RTL_R8(PHYstatus) & LinkStatus;
545}
546
547static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
548{
549 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
550}
551
552static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
553{
554 unsigned int val;
555
556 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
557 mdio_write(ioaddr, PHY_CTRL_REG, val);
558}
559
560static void rtl8169_check_link_status(struct net_device *dev,
561 struct rtl8169_private *tp, void __iomem *ioaddr)
562{
563 unsigned long flags;
564
565 spin_lock_irqsave(&tp->lock, flags);
566 if (tp->link_ok(ioaddr)) {
567 netif_carrier_on(dev);
b57b7e5a
SH		 568 if (netif_msg_ifup(tp))
569 printk(KERN_INFO PFX "%s: link up\n", dev->name);
570 } else {
571 if (netif_msg_ifdown(tp))
572 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 573 netif_carrier_off(dev);
b57b7e5a 574 }
1da177e4
LT		 575 spin_unlock_irqrestore(&tp->lock, flags);
576}
577
578static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
579{
580 struct {
581 u16 speed;
582 u8 duplex;
583 u8 autoneg;
584 u8 media;
585 } link_settings[] = {
586 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
587 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
588 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
589 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
590 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
591 /* Make TBI happy */
592 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
593 }, *p;
594 unsigned char option;
595
596 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
597
b57b7e5a 598 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 599 printk(KERN_WARNING PFX "media option is deprecated.\n");
600
601 for (p = link_settings; p->media != 0xff; p++) {
602 if (p->media == option)
603 break;
604 }
605 *autoneg = p->autoneg;
606 *speed = p->speed;
607 *duplex = p->duplex;
608}
609
610static void rtl8169_get_drvinfo(struct net_device *dev,
611 struct ethtool_drvinfo *info)
612{
613 struct rtl8169_private *tp = netdev_priv(dev);
614
615 strcpy(info->driver, MODULENAME);
616 strcpy(info->version, RTL8169_VERSION);
617 strcpy(info->bus_info, pci_name(tp->pci_dev));
618}
619
620static int rtl8169_get_regs_len(struct net_device *dev)
621{
622 return R8169_REGS_SIZE;
623}
624
625static int rtl8169_set_speed_tbi(struct net_device *dev,
626 u8 autoneg, u16 speed, u8 duplex)
627{
628 struct rtl8169_private *tp = netdev_priv(dev);
629 void __iomem *ioaddr = tp->mmio_addr;
630 int ret = 0;
631 u32 reg;
632
633 reg = RTL_R32(TBICSR);
634 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
635 (duplex == DUPLEX_FULL)) {
636 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
637 } else if (autoneg == AUTONEG_ENABLE)
638 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
639 else {
b57b7e5a
SH		 640 if (netif_msg_link(tp)) {
641 printk(KERN_WARNING "%s: "
642 "incorrect speed setting refused in TBI mode\n",
643 dev->name);
644 }
1da177e4
LT		 645 ret = -EOPNOTSUPP;
646 }
647
648 return ret;
649}
650
651static int rtl8169_set_speed_xmii(struct net_device *dev,
652 u8 autoneg, u16 speed, u8 duplex)
653{
654 struct rtl8169_private *tp = netdev_priv(dev);
655 void __iomem *ioaddr = tp->mmio_addr;
656 int auto_nego, giga_ctrl;
657
658 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
659 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
660 PHY_Cap_100_Half | PHY_Cap_100_Full);
661 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
662 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
663
664 if (autoneg == AUTONEG_ENABLE) {
665 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
666 PHY_Cap_100_Half | PHY_Cap_100_Full);
667 giga_ctrl |= PHY_Cap_1000_Full;
668 } else {
669 if (speed == SPEED_10)
670 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
671 else if (speed == SPEED_100)
672 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
673 else if (speed == SPEED_1000)
674 giga_ctrl |= PHY_Cap_1000_Full;
675
676 if (duplex == DUPLEX_HALF)
677 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
726ecdcf
AG		 678
679 if (duplex == DUPLEX_FULL)
680 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
1da177e4
LT		 681 }
682
683 tp->phy_auto_nego_reg = auto_nego;
684 tp->phy_1000_ctrl_reg = giga_ctrl;
685
686 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
687 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
688 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
689 PHY_Restart_Auto_Nego);
690 return 0;
691}
692
693static int rtl8169_set_speed(struct net_device *dev,
694 u8 autoneg, u16 speed, u8 duplex)
695{
696 struct rtl8169_private *tp = netdev_priv(dev);
697 int ret;
698
699 ret = tp->set_speed(dev, autoneg, speed, duplex);
700
701 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
702 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
703
704 return ret;
705}
706
707static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
708{
709 struct rtl8169_private *tp = netdev_priv(dev);
710 unsigned long flags;
711 int ret;
712
713 spin_lock_irqsave(&tp->lock, flags);
714 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
715 spin_unlock_irqrestore(&tp->lock, flags);
716
717 return ret;
718}
719
720static u32 rtl8169_get_rx_csum(struct net_device *dev)
721{
722 struct rtl8169_private *tp = netdev_priv(dev);
723
724 return tp->cp_cmd & RxChkSum;
725}
726
727static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
728{
729 struct rtl8169_private *tp = netdev_priv(dev);
730 void __iomem *ioaddr = tp->mmio_addr;
731 unsigned long flags;
732
733 spin_lock_irqsave(&tp->lock, flags);
734
735 if (data)
736 tp->cp_cmd |= RxChkSum;
737 else
738 tp->cp_cmd &= ~RxChkSum;
739
740 RTL_W16(CPlusCmd, tp->cp_cmd);
741 RTL_R16(CPlusCmd);
742
743 spin_unlock_irqrestore(&tp->lock, flags);
744
745 return 0;
746}
747
748#ifdef CONFIG_R8169_VLAN
749
750static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
751 struct sk_buff *skb)
752{
753 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
754 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
755}
756
757static void rtl8169_vlan_rx_register(struct net_device *dev,
758 struct vlan_group *grp)
759{
760 struct rtl8169_private *tp = netdev_priv(dev);
761 void __iomem *ioaddr = tp->mmio_addr;
762 unsigned long flags;
763
764 spin_lock_irqsave(&tp->lock, flags);
765 tp->vlgrp = grp;
766 if (tp->vlgrp)
767 tp->cp_cmd |= RxVlan;
768 else
769 tp->cp_cmd &= ~RxVlan;
770 RTL_W16(CPlusCmd, tp->cp_cmd);
771 RTL_R16(CPlusCmd);
772 spin_unlock_irqrestore(&tp->lock, flags);
773}
774
775static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
776{
777 struct rtl8169_private *tp = netdev_priv(dev);
778 unsigned long flags;
779
780 spin_lock_irqsave(&tp->lock, flags);
781 if (tp->vlgrp)
782 tp->vlgrp->vlan_devices[vid] = NULL;
783 spin_unlock_irqrestore(&tp->lock, flags);
784}
785
786static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
787 struct sk_buff *skb)
788{
789 u32 opts2 = le32_to_cpu(desc->opts2);
790 int ret;
791
792 if (tp->vlgrp && (opts2 & RxVlanTag)) {
793 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
794 swab16(opts2 & 0xffff));
795 ret = 0;
796 } else
797 ret = -1;
798 desc->opts2 = 0;
799 return ret;
800}
801
802#else /* !CONFIG_R8169_VLAN */
803
804static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
805 struct sk_buff *skb)
806{
807 return 0;
808}
809
810static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
811 struct sk_buff *skb)
812{
813 return -1;
814}
815
816#endif
817
818static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
819{
820 struct rtl8169_private *tp = netdev_priv(dev);
821 void __iomem *ioaddr = tp->mmio_addr;
822 u32 status;
823
824 cmd->supported =
825 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
826 cmd->port = PORT_FIBRE;
827 cmd->transceiver = XCVR_INTERNAL;
828
829 status = RTL_R32(TBICSR);
830 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
831 cmd->autoneg = !!(status & TBINwEnable);
832
833 cmd->speed = SPEED_1000;
834 cmd->duplex = DUPLEX_FULL; /* Always set */
835}
836
837static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
838{
839 struct rtl8169_private *tp = netdev_priv(dev);
840 void __iomem *ioaddr = tp->mmio_addr;
841 u8 status;
842
843 cmd->supported = SUPPORTED_10baseT_Half |
844 SUPPORTED_10baseT_Full |
845 SUPPORTED_100baseT_Half |
846 SUPPORTED_100baseT_Full |
847 SUPPORTED_1000baseT_Full |
848 SUPPORTED_Autoneg |
849 SUPPORTED_TP;
850
851 cmd->autoneg = 1;
852 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
853
854 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
855 cmd->advertising |= ADVERTISED_10baseT_Half;
856 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
857 cmd->advertising |= ADVERTISED_10baseT_Full;
858 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
859 cmd->advertising |= ADVERTISED_100baseT_Half;
860 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
861 cmd->advertising |= ADVERTISED_100baseT_Full;
862 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
863 cmd->advertising |= ADVERTISED_1000baseT_Full;
864
865 status = RTL_R8(PHYstatus);
866
867 if (status & _1000bpsF)
868 cmd->speed = SPEED_1000;
869 else if (status & _100bps)
870 cmd->speed = SPEED_100;
871 else if (status & _10bps)
872 cmd->speed = SPEED_10;
873
874 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
875 DUPLEX_FULL : DUPLEX_HALF;
876}
877
878static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
879{
880 struct rtl8169_private *tp = netdev_priv(dev);
881 unsigned long flags;
882
883 spin_lock_irqsave(&tp->lock, flags);
884
885 tp->get_settings(dev, cmd);
886
887 spin_unlock_irqrestore(&tp->lock, flags);
888 return 0;
889}
890
891static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
892 void *p)
893{
894 struct rtl8169_private *tp = netdev_priv(dev);
895 unsigned long flags;
896
897 if (regs->len > R8169_REGS_SIZE)
898 regs->len = R8169_REGS_SIZE;
899
900 spin_lock_irqsave(&tp->lock, flags);
901 memcpy_fromio(p, tp->mmio_addr, regs->len);
902 spin_unlock_irqrestore(&tp->lock, flags);
903}
904
b57b7e5a
SH		 905static u32 rtl8169_get_msglevel(struct net_device *dev)
906{
907 struct rtl8169_private *tp = netdev_priv(dev);
908
909 return tp->msg_enable;
910}
911
912static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
913{
914 struct rtl8169_private *tp = netdev_priv(dev);
915
916 tp->msg_enable = value;
917}
918
d4a3a0fc
SH		 919static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
920 "tx_packets",
921 "rx_packets",
922 "tx_errors",
923 "rx_errors",
924 "rx_missed",
925 "align_errors",
926 "tx_single_collisions",
927 "tx_multi_collisions",
928 "unicast",
929 "broadcast",
930 "multicast",
931 "tx_aborted",
932 "tx_underrun",
933};
934
935struct rtl8169_counters {
936 u64 tx_packets;
937 u64 rx_packets;
938 u64 tx_errors;
939 u32 rx_errors;
940 u16 rx_missed;
941 u16 align_errors;
942 u32 tx_one_collision;
943 u32 tx_multi_collision;
944 u64 rx_unicast;
945 u64 rx_broadcast;
946 u32 rx_multicast;
947 u16 tx_aborted;
948 u16 tx_underun;
949};
950
951static int rtl8169_get_stats_count(struct net_device *dev)
952{
953 return ARRAY_SIZE(rtl8169_gstrings);
954}
955
956static void rtl8169_get_ethtool_stats(struct net_device *dev,
957 struct ethtool_stats *stats, u64 *data)
958{
959 struct rtl8169_private *tp = netdev_priv(dev);
960 void __iomem *ioaddr = tp->mmio_addr;
961 struct rtl8169_counters *counters;
962 dma_addr_t paddr;
963 u32 cmd;
964
965 ASSERT_RTNL();
966
967 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
968 if (!counters)
969 return;
970
971 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
972 cmd = (u64)paddr & DMA_32BIT_MASK;
973 RTL_W32(CounterAddrLow, cmd);
974 RTL_W32(CounterAddrLow, cmd | CounterDump);
975
976 while (RTL_R32(CounterAddrLow) & CounterDump) {
977 if (msleep_interruptible(1))
978 break;
979 }
980
981 RTL_W32(CounterAddrLow, 0);
982 RTL_W32(CounterAddrHigh, 0);
983
984 data[0] = le64_to_cpu(counters->tx_packets);
985 data[1] = le64_to_cpu(counters->rx_packets);
986 data[2] = le64_to_cpu(counters->tx_errors);
987 data[3] = le32_to_cpu(counters->rx_errors);
988 data[4] = le16_to_cpu(counters->rx_missed);
989 data[5] = le16_to_cpu(counters->align_errors);
990 data[6] = le32_to_cpu(counters->tx_one_collision);
991 data[7] = le32_to_cpu(counters->tx_multi_collision);
992 data[8] = le64_to_cpu(counters->rx_unicast);
993 data[9] = le64_to_cpu(counters->rx_broadcast);
994 data[10] = le32_to_cpu(counters->rx_multicast);
995 data[11] = le16_to_cpu(counters->tx_aborted);
996 data[12] = le16_to_cpu(counters->tx_underun);
997
998 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
999}
1000
1001static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1002{
1003 switch(stringset) {
1004 case ETH_SS_STATS:
1005 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1006 break;
1007 }
1008}
1009
1010
1da177e4
LT		 1011static struct ethtool_ops rtl8169_ethtool_ops = {
1012 .get_drvinfo = rtl8169_get_drvinfo,
1013 .get_regs_len = rtl8169_get_regs_len,
1014 .get_link = ethtool_op_get_link,
1015 .get_settings = rtl8169_get_settings,
1016 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1017 .get_msglevel = rtl8169_get_msglevel,
1018 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1019 .get_rx_csum = rtl8169_get_rx_csum,
1020 .set_rx_csum = rtl8169_set_rx_csum,
1021 .get_tx_csum = ethtool_op_get_tx_csum,
1022 .set_tx_csum = ethtool_op_set_tx_csum,
1023 .get_sg = ethtool_op_get_sg,
1024 .set_sg = ethtool_op_set_sg,
1025 .get_tso = ethtool_op_get_tso,
1026 .set_tso = ethtool_op_set_tso,
1027 .get_regs = rtl8169_get_regs,
d4a3a0fc
SH		 1028 .get_strings = rtl8169_get_strings,
1029 .get_stats_count = rtl8169_get_stats_count,
1030 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1031 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1032};
1033
1034static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1035 int bitval)
1036{
1037 int val;
1038
1039 val = mdio_read(ioaddr, reg);
1040 val = (bitval == 1) ?
1041 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1042 mdio_write(ioaddr, reg, val & 0xffff);
1043}
1044
1045static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1046{
1047 const struct {
1048 u32 mask;
1049 int mac_version;
1050 } mac_info[] = {
1051 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
1052 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
1053 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
1054 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
1055 }, *p = mac_info;
1056 u32 reg;
1057
1058 reg = RTL_R32(TxConfig) & 0x7c800000;
1059 while ((reg & p->mask) != p->mask)
1060 p++;
1061 tp->mac_version = p->mac_version;
1062}
1063
1064static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1065{
1066 struct {
1067 int version;
1068 char *msg;
1069 } mac_print[] = {
1070 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1071 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1072 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1073 { 0, NULL }
1074 }, *p;
1075
1076 for (p = mac_print; p->msg; p++) {
1077 if (tp->mac_version == p->version) {
1078 dprintk("mac_version == %s (%04d)\n", p->msg,
1079 p->version);
1080 return;
1081 }
1082 }
1083 dprintk("mac_version == Unknown\n");
1084}
1085
1086static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1087{
1088 const struct {
1089 u16 mask;
1090 u16 set;
1091 int phy_version;
1092 } phy_info[] = {
1093 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1094 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1095 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1096 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1097 }, *p = phy_info;
1098 u16 reg;
1099
1100 reg = mdio_read(ioaddr, 3) & 0xffff;
1101 while ((reg & p->mask) != p->set)
1102 p++;
1103 tp->phy_version = p->phy_version;
1104}
1105
1106static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1107{
1108 struct {
1109 int version;
1110 char *msg;
1111 u32 reg;
1112 } phy_print[] = {
1113 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1114 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1115 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1116 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1117 { 0, NULL, 0x0000 }
1118 }, *p;
1119
1120 for (p = phy_print; p->msg; p++) {
1121 if (tp->phy_version == p->version) {
1122 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1123 return;
1124 }
1125 }
1126 dprintk("phy_version == Unknown\n");
1127}
1128
1129static void rtl8169_hw_phy_config(struct net_device *dev)
1130{
1131 struct rtl8169_private *tp = netdev_priv(dev);
1132 void __iomem *ioaddr = tp->mmio_addr;
1133 struct {
1134 u16 regs[5]; /* Beware of bit-sign propagation */
1135 } phy_magic[5] = { {
1136 { 0x0000, //w 4 15 12 0
1137 0x00a1, //w 3 15 0 00a1
1138 0x0008, //w 2 15 0 0008
1139 0x1020, //w 1 15 0 1020
1140 0x1000 } },{ //w 0 15 0 1000
1141 { 0x7000, //w 4 15 12 7
1142 0xff41, //w 3 15 0 ff41
1143 0xde60, //w 2 15 0 de60
1144 0x0140, //w 1 15 0 0140
1145 0x0077 } },{ //w 0 15 0 0077
1146 { 0xa000, //w 4 15 12 a
1147 0xdf01, //w 3 15 0 df01
1148 0xdf20, //w 2 15 0 df20
1149 0xff95, //w 1 15 0 ff95
1150 0xfa00 } },{ //w 0 15 0 fa00
1151 { 0xb000, //w 4 15 12 b
1152 0xff41, //w 3 15 0 ff41
1153 0xde20, //w 2 15 0 de20
1154 0x0140, //w 1 15 0 0140
1155 0x00bb } },{ //w 0 15 0 00bb
1156 { 0xf000, //w 4 15 12 f
1157 0xdf01, //w 3 15 0 df01
1158 0xdf20, //w 2 15 0 df20
1159 0xff95, //w 1 15 0 ff95
1160 0xbf00 } //w 0 15 0 bf00
1161 }
1162 }, *p = phy_magic;
1163 int i;
1164
1165 rtl8169_print_mac_version(tp);
1166 rtl8169_print_phy_version(tp);
1167
1168 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1169 return;
1170 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1171 return;
1172
1173 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1174 dprintk("Do final_reg2.cfg\n");
1175
1176 /* Shazam ! */
1177
1178 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1179 mdio_write(ioaddr, 31, 0x0001);
1180 mdio_write(ioaddr, 9, 0x273a);
1181 mdio_write(ioaddr, 14, 0x7bfb);
1182 mdio_write(ioaddr, 27, 0x841e);
1183
1184 mdio_write(ioaddr, 31, 0x0002);
1185 mdio_write(ioaddr, 1, 0x90d0);
1186 mdio_write(ioaddr, 31, 0x0000);
1187 return;
1188 }
1189
1190 /* phy config for RTL8169s mac_version C chip */
1191 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1192 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1193 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1194 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1195
1196 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1197 int val, pos = 4;
1198
1199 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1200 mdio_write(ioaddr, pos, val);
1201 while (--pos >= 0)
1202 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1203 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1204 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1205 }
1206 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1207}
1208
1209static void rtl8169_phy_timer(unsigned long __opaque)
1210{
1211 struct net_device *dev = (struct net_device *)__opaque;
1212 struct rtl8169_private *tp = netdev_priv(dev);
1213 struct timer_list *timer = &tp->timer;
1214 void __iomem *ioaddr = tp->mmio_addr;
1215 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1216
1217 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1218 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1219
1220 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1221 return;
1222
1223 spin_lock_irq(&tp->lock);
1224
1225 if (tp->phy_reset_pending(ioaddr)) {
1226 /*
1227 * A busy loop could burn quite a few cycles on nowadays CPU.
1228 * Let's delay the execution of the timer for a few ticks.
1229 */
1230 timeout = HZ/10;
1231 goto out_mod_timer;
1232 }
1233
1234 if (tp->link_ok(ioaddr))
1235 goto out_unlock;
1236
b57b7e5a
SH		 1237 if (netif_msg_link(tp))
1238 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1239
1240 tp->phy_reset_enable(ioaddr);
1241
1242out_mod_timer:
1243 mod_timer(timer, jiffies + timeout);
1244out_unlock:
1245 spin_unlock_irq(&tp->lock);
1246}
1247
1248static inline void rtl8169_delete_timer(struct net_device *dev)
1249{
1250 struct rtl8169_private *tp = netdev_priv(dev);
1251 struct timer_list *timer = &tp->timer;
1252
1253 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1254 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1255 return;
1256
1257 del_timer_sync(timer);
1258}
1259
1260static inline void rtl8169_request_timer(struct net_device *dev)
1261{
1262 struct rtl8169_private *tp = netdev_priv(dev);
1263 struct timer_list *timer = &tp->timer;
1264
1265 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1266 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1267 return;
1268
1269 init_timer(timer);
1270 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1271 timer->data = (unsigned long)(dev);
1272 timer->function = rtl8169_phy_timer;
1273 add_timer(timer);
1274}
1275
1276#ifdef CONFIG_NET_POLL_CONTROLLER
1277/*
1278 * Polling 'interrupt' - used by things like netconsole to send skbs
1279 * without having to re-enable interrupts. It's not called while
1280 * the interrupt routine is executing.
1281 */
1282static void rtl8169_netpoll(struct net_device *dev)
1283{
1284 struct rtl8169_private *tp = netdev_priv(dev);
1285 struct pci_dev *pdev = tp->pci_dev;
1286
1287 disable_irq(pdev->irq);
1288 rtl8169_interrupt(pdev->irq, dev, NULL);
1289 enable_irq(pdev->irq);
1290}
1291#endif
1292
1293static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1294 void __iomem *ioaddr)
1295{
1296 iounmap(ioaddr);
1297 pci_release_regions(pdev);
1298 pci_disable_device(pdev);
1299 free_netdev(dev);
1300}
1301
1302static int __devinit
1303rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1304 void __iomem **ioaddr_out)
1305{
1306 void __iomem *ioaddr;
1307 struct net_device *dev;
1308 struct rtl8169_private *tp;
1309 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1310
1311 assert(ioaddr_out != NULL);
1312
1313 /* dev zeroed in alloc_etherdev */
1314 dev = alloc_etherdev(sizeof (*tp));
1315 if (dev == NULL) {
b57b7e5a
SH		 1316 if (netif_msg_drv(&debug))
1317 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1da177e4
LT		 1318 goto err_out;
1319 }
1320
1321 SET_MODULE_OWNER(dev);
1322 SET_NETDEV_DEV(dev, &pdev->dev);
1323 tp = netdev_priv(dev);
b57b7e5a 1324 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1325
1326 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1327 rc = pci_enable_device(pdev);
b57b7e5a
SH		 1328 if (rc < 0) {
1329 if (netif_msg_probe(tp)) {
1330 printk(KERN_ERR PFX "%s: enable failure\n",
1331 pci_name(pdev));
1332 }
1da177e4
LT		 1333 goto err_out_free_dev;
1334 }
1335
1336 rc = pci_set_mwi(pdev);
1337 if (rc < 0)
1338 goto err_out_disable;
1339
1340 /* save power state before pci_enable_device overwrites it */
1341 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1342 if (pm_cap) {
1343 u16 pwr_command;
1344
1345 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1346 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1347 } else {
b57b7e5a
SH		 1348 if (netif_msg_probe(tp)) {
1349 printk(KERN_ERR PFX
e53091fa 1350 "PowerManagement capability not found.\n");
b57b7e5a 1351 }
1da177e4
LT		 1352 }
1353
1354 /* make sure PCI base addr 1 is MMIO */
1355 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
b57b7e5a
SH		 1356 if (netif_msg_probe(tp)) {
1357 printk(KERN_ERR PFX
1358 "region #1 not an MMIO resource, aborting\n");
1359 }
1da177e4
LT		 1360 rc = -ENODEV;
1361 goto err_out_mwi;
1362 }
1363 /* check for weird/broken PCI region reporting */
1364 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
b57b7e5a
SH		 1365 if (netif_msg_probe(tp)) {
1366 printk(KERN_ERR PFX
1367 "Invalid PCI region size(s), aborting\n");
1368 }
1da177e4
LT		 1369 rc = -ENODEV;
1370 goto err_out_mwi;
1371 }
1372
1373 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a
SH		 1374 if (rc < 0) {
1375 if (netif_msg_probe(tp)) {
1376 printk(KERN_ERR PFX "%s: could not request regions.\n",
1377 pci_name(pdev));
1378 }
1da177e4
LT		 1379 goto err_out_mwi;
1380 }
1381
1382 tp->cp_cmd = PCIMulRW | RxChkSum;
1383
1384 if ((sizeof(dma_addr_t) > 4) &&
1385 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1386 tp->cp_cmd |= PCIDAC;
1387 dev->features |= NETIF_F_HIGHDMA;
1388 } else {
1389 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1390 if (rc < 0) {
b57b7e5a
SH		 1391 if (netif_msg_probe(tp)) {
1392 printk(KERN_ERR PFX
1393 "DMA configuration failed.\n");
1394 }
1da177e4
LT		 1395 goto err_out_free_res;
1396 }
1397 }
1398
1399 pci_set_master(pdev);
1400
1401 /* ioremap MMIO region */
1402 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1403 if (ioaddr == NULL) {
b57b7e5a
SH		 1404 if (netif_msg_probe(tp))
1405 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1da177e4
LT		 1406 rc = -EIO;
1407 goto err_out_free_res;
1408 }
1409
1410 /* Unneeded ? Don't mess with Mrs. Murphy. */
1411 rtl8169_irq_mask_and_ack(ioaddr);
1412
1413 /* Soft reset the chip. */
1414 RTL_W8(ChipCmd, CmdReset);
1415
1416 /* Check that the chip has finished the reset. */
1417 for (i = 1000; i > 0; i--) {
1418 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1419 break;
1420 udelay(10);
1421 }
1422
1423 /* Identify chip attached to board */
1424 rtl8169_get_mac_version(tp, ioaddr);
1425 rtl8169_get_phy_version(tp, ioaddr);
1426
1427 rtl8169_print_mac_version(tp);
1428 rtl8169_print_phy_version(tp);
1429
1430 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1431 if (tp->mac_version == rtl_chip_info[i].mac_version)
1432 break;
1433 }
1434 if (i < 0) {
1435 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a
SH		 1436 if (netif_msg_probe(tp)) {
1437 printk(KERN_DEBUG PFX "PCI device %s: "
1438 "unknown chip version, assuming %s\n",
1439 pci_name(pdev), rtl_chip_info[0].name);
1440 }
1da177e4
LT		 1441 i++;
1442 }
1443 tp->chipset = i;
1444
1445 *ioaddr_out = ioaddr;
1446 *dev_out = dev;
1447out:
1448 return rc;
1449
1450err_out_free_res:
1451 pci_release_regions(pdev);
1452
1453err_out_mwi:
1454 pci_clear_mwi(pdev);
1455
1456err_out_disable:
1457 pci_disable_device(pdev);
1458
1459err_out_free_dev:
1460 free_netdev(dev);
1461err_out:
1462 *ioaddr_out = NULL;
1463 *dev_out = NULL;
1464 goto out;
1465}
1466
1467static int __devinit
1468rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1469{
1470 struct net_device *dev = NULL;
1471 struct rtl8169_private *tp;
1472 void __iomem *ioaddr = NULL;
1473 static int board_idx = -1;
1da177e4
LT		 1474 u8 autoneg, duplex;
1475 u16 speed;
1476 int i, rc;
1477
1478 assert(pdev != NULL);
1479 assert(ent != NULL);
1480
1481 board_idx++;
1482
b57b7e5a 1483 if (netif_msg_drv(&debug)) {
1da177e4
LT		 1484 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1485 MODULENAME, RTL8169_VERSION);
1da177e4
LT		 1486 }
1487
1488 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1489 if (rc)
1490 return rc;
1491
1492 tp = netdev_priv(dev);
1493 assert(ioaddr != NULL);
1494
1495 if (RTL_R8(PHYstatus) & TBI_Enable) {
1496 tp->set_speed = rtl8169_set_speed_tbi;
1497 tp->get_settings = rtl8169_gset_tbi;
1498 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1499 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1500 tp->link_ok = rtl8169_tbi_link_ok;
1501
1502 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1503 } else {
1504 tp->set_speed = rtl8169_set_speed_xmii;
1505 tp->get_settings = rtl8169_gset_xmii;
1506 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1507 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1508 tp->link_ok = rtl8169_xmii_link_ok;
1509 }
1510
1511 /* Get MAC address. FIXME: read EEPROM */
1512 for (i = 0; i < MAC_ADDR_LEN; i++)
1513 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1514 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1515
1516 dev->open = rtl8169_open;
1517 dev->hard_start_xmit = rtl8169_start_xmit;
1518 dev->get_stats = rtl8169_get_stats;
1519 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1520 dev->stop = rtl8169_close;
1521 dev->tx_timeout = rtl8169_tx_timeout;
1522 dev->set_multicast_list = rtl8169_set_rx_mode;
1523 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1524 dev->irq = pdev->irq;
1525 dev->base_addr = (unsigned long) ioaddr;
1526 dev->change_mtu = rtl8169_change_mtu;
1527
1528#ifdef CONFIG_R8169_NAPI
1529 dev->poll = rtl8169_poll;
1530 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1531#endif
1532
1533#ifdef CONFIG_R8169_VLAN
1534 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1535 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1536 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1537#endif
1538
1539#ifdef CONFIG_NET_POLL_CONTROLLER
1540 dev->poll_controller = rtl8169_netpoll;
1541#endif
1542
1543 tp->intr_mask = 0xffff;
1544 tp->pci_dev = pdev;
1545 tp->mmio_addr = ioaddr;
1546
1547 spin_lock_init(&tp->lock);
1548
1549 rc = register_netdev(dev);
1550 if (rc) {
1551 rtl8169_release_board(pdev, dev, ioaddr);
1552 return rc;
1553 }
1554
b57b7e5a
SH		 1555 if (netif_msg_probe(tp)) {
1556 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1557 dev->name, rtl_chip_info[tp->chipset].name);
1558 }
1da177e4
LT		 1559
1560 pci_set_drvdata(pdev, dev);
1561
b57b7e5a
SH		 1562 if (netif_msg_probe(tp)) {
1563 printk(KERN_INFO "%s: %s at 0x%lx, "
1564 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1565 "IRQ %d\n",
1566 dev->name,
1567 rtl_chip_info[ent->driver_data].name,
1568 dev->base_addr,
1569 dev->dev_addr[0], dev->dev_addr[1],
1570 dev->dev_addr[2], dev->dev_addr[3],
1571 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1572 }
1da177e4
LT		 1573
1574 rtl8169_hw_phy_config(dev);
1575
1576 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1577 RTL_W8(0x82, 0x01);
1578
1579 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1580 dprintk("Set PCI Latency=0x40\n");
1581 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1582 }
1583
1584 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1585 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1586 RTL_W8(0x82, 0x01);
1587 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1588 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1589 }
1590
1591 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1592
1593 rtl8169_set_speed(dev, autoneg, speed, duplex);
1594
b57b7e5a 1595 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1da177e4
LT		 1596 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1597
1598 return 0;
1599}
1600
1601static void __devexit
1602rtl8169_remove_one(struct pci_dev *pdev)
1603{
1604 struct net_device *dev = pci_get_drvdata(pdev);
1605 struct rtl8169_private *tp = netdev_priv(dev);
1606
1607 assert(dev != NULL);
1608 assert(tp != NULL);
1609
1610 unregister_netdev(dev);
1611 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1612 pci_set_drvdata(pdev, NULL);
1613}
1614
1615#ifdef CONFIG_PM
1616
05adc3b7 1617static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1618{
1619 struct net_device *dev = pci_get_drvdata(pdev);
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 void __iomem *ioaddr = tp->mmio_addr;
1622 unsigned long flags;
1623
1624 if (!netif_running(dev))
1625 return 0;
1626
1627 netif_device_detach(dev);
1628 netif_stop_queue(dev);
1629 spin_lock_irqsave(&tp->lock, flags);
1630
1631 /* Disable interrupts, stop Rx and Tx */
1632 RTL_W16(IntrMask, 0);
1633 RTL_W8(ChipCmd, 0);
1634
1635 /* Update the error counts. */
1636 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1637 RTL_W32(RxMissed, 0);
1638 spin_unlock_irqrestore(&tp->lock, flags);
1639
1640 return 0;
1641}
1642
1643static int rtl8169_resume(struct pci_dev *pdev)
1644{
1645 struct net_device *dev = pci_get_drvdata(pdev);
1646
1647 if (!netif_running(dev))
1648 return 0;
1649
1650 netif_device_attach(dev);
1651 rtl8169_hw_start(dev);
1652
1653 return 0;
1654}
1655
1656#endif /* CONFIG_PM */
1657
1658static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1659 struct net_device *dev)
1660{
1661 unsigned int mtu = dev->mtu;
1662
1663 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1664}
1665
1666static int rtl8169_open(struct net_device *dev)
1667{
1668 struct rtl8169_private *tp = netdev_priv(dev);
1669 struct pci_dev *pdev = tp->pci_dev;
1670 int retval;
1671
1672 rtl8169_set_rxbufsize(tp, dev);
1673
1674 retval =
1675 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1676 if (retval < 0)
1677 goto out;
1678
1679 retval = -ENOMEM;
1680
1681 /*
1682 * Rx and Tx desscriptors needs 256 bytes alignment.
1683 * pci_alloc_consistent provides more.
1684 */
1685 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1686 &tp->TxPhyAddr);
1687 if (!tp->TxDescArray)
1688 goto err_free_irq;
1689
1690 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1691 &tp->RxPhyAddr);
1692 if (!tp->RxDescArray)
1693 goto err_free_tx;
1694
1695 retval = rtl8169_init_ring(dev);
1696 if (retval < 0)
1697 goto err_free_rx;
1698
1699 INIT_WORK(&tp->task, NULL, dev);
1700
1701 rtl8169_hw_start(dev);
1702
1703 rtl8169_request_timer(dev);
1704
1705 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1706out:
1707 return retval;
1708
1709err_free_rx:
1710 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1711 tp->RxPhyAddr);
1712err_free_tx:
1713 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1714 tp->TxPhyAddr);
1715err_free_irq:
1716 free_irq(dev->irq, dev);
1717 goto out;
1718}
1719
1720static void rtl8169_hw_reset(void __iomem *ioaddr)
1721{
1722 /* Disable interrupts */
1723 rtl8169_irq_mask_and_ack(ioaddr);
1724
1725 /* Reset the chipset */
1726 RTL_W8(ChipCmd, CmdReset);
1727
1728 /* PCI commit */
1729 RTL_R8(ChipCmd);
1730}
1731
1732static void
1733rtl8169_hw_start(struct net_device *dev)
1734{
1735 struct rtl8169_private *tp = netdev_priv(dev);
1736 void __iomem *ioaddr = tp->mmio_addr;
1737 u32 i;
1738
1739 /* Soft reset the chip. */
1740 RTL_W8(ChipCmd, CmdReset);
1741
1742 /* Check that the chip has finished the reset. */
1743 for (i = 1000; i > 0; i--) {
1744 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1745 break;
1746 udelay(10);
1747 }
1748
1749 RTL_W8(Cfg9346, Cfg9346_Unlock);
1750 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1751 RTL_W8(EarlyTxThres, EarlyTxThld);
1752
126fa4b9
FR		 1753 /* Low hurts. Let's disable the filtering. */
1754 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1755
1756 /* Set Rx Config register */
1757 i = rtl8169_rx_config |
1758 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1759 RTL_W32(RxConfig, i);
1760
1761 /* Set DMA burst size and Interframe Gap Time */
1762 RTL_W32(TxConfig,
1763 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1764 TxInterFrameGapShift));
1765 tp->cp_cmd |= RTL_R16(CPlusCmd);
1766 RTL_W16(CPlusCmd, tp->cp_cmd);
1767
1768 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1769 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1770 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1771 "Bit-3 and bit-14 MUST be 1\n");
1772 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1773 RTL_W16(CPlusCmd, tp->cp_cmd);
1774 }
1775
1776 /*
1777 * Undocumented corner. Supposedly:
1778 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1779 */
1780 RTL_W16(IntrMitigate, 0x0000);
1781
1782 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1783 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1784 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1785 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1786 RTL_W8(Cfg9346, Cfg9346_Lock);
1787 udelay(10);
1788
1789 RTL_W32(RxMissed, 0);
1790
1791 rtl8169_set_rx_mode(dev);
1792
1793 /* no early-rx interrupts */
1794 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1795
1796 /* Enable all known interrupts by setting the interrupt mask. */
1797 RTL_W16(IntrMask, rtl8169_intr_mask);
1798
1799 netif_start_queue(dev);
1800}
1801
1802static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1803{
1804 struct rtl8169_private *tp = netdev_priv(dev);
1805 int ret = 0;
1806
1807 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1808 return -EINVAL;
1809
1810 dev->mtu = new_mtu;
1811
1812 if (!netif_running(dev))
1813 goto out;
1814
1815 rtl8169_down(dev);
1816
1817 rtl8169_set_rxbufsize(tp, dev);
1818
1819 ret = rtl8169_init_ring(dev);
1820 if (ret < 0)
1821 goto out;
1822
1823 netif_poll_enable(dev);
1824
1825 rtl8169_hw_start(dev);
1826
1827 rtl8169_request_timer(dev);
1828
1829out:
1830 return ret;
1831}
1832
1833static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1834{
1835 desc->addr = 0x0badbadbadbadbadull;
1836 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1837}
1838
1839static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1840 struct sk_buff **sk_buff, struct RxDesc *desc)
1841{
1842 struct pci_dev *pdev = tp->pci_dev;
1843
1844 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1845 PCI_DMA_FROMDEVICE);
1846 dev_kfree_skb(*sk_buff);
1847 *sk_buff = NULL;
1848 rtl8169_make_unusable_by_asic(desc);
1849}
1850
1851static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1852{
1853 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1854
1855 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1856}
1857
1858static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1859 u32 rx_buf_sz)
1860{
1861 desc->addr = cpu_to_le64(mapping);
1862 wmb();
1863 rtl8169_mark_to_asic(desc, rx_buf_sz);
1864}
1865
1866static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1867 struct RxDesc *desc, int rx_buf_sz)
1868{
1869 struct sk_buff *skb;
1870 dma_addr_t mapping;
1871 int ret = 0;
1872
1873 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1874 if (!skb)
1875 goto err_out;
1876
1877 skb_reserve(skb, NET_IP_ALIGN);
1878 *sk_buff = skb;
1879
689be439 1880 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 1881 PCI_DMA_FROMDEVICE);
1882
1883 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1884
1885out:
1886 return ret;
1887
1888err_out:
1889 ret = -ENOMEM;
1890 rtl8169_make_unusable_by_asic(desc);
1891 goto out;
1892}
1893
1894static void rtl8169_rx_clear(struct rtl8169_private *tp)
1895{
1896 int i;
1897
1898 for (i = 0; i < NUM_RX_DESC; i++) {
1899 if (tp->Rx_skbuff[i]) {
1900 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1901 tp->RxDescArray + i);
1902 }
1903 }
1904}
1905
1906static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1907 u32 start, u32 end)
1908{
1909 u32 cur;
1910
1911 for (cur = start; end - cur > 0; cur++) {
1912 int ret, i = cur % NUM_RX_DESC;
1913
1914 if (tp->Rx_skbuff[i])
1915 continue;
1916
1917 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1918 tp->RxDescArray + i, tp->rx_buf_sz);
1919 if (ret < 0)
1920 break;
1921 }
1922 return cur - start;
1923}
1924
1925static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1926{
1927 desc->opts1 |= cpu_to_le32(RingEnd);
1928}
1929
1930static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1931{
1932 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1933}
1934
1935static int rtl8169_init_ring(struct net_device *dev)
1936{
1937 struct rtl8169_private *tp = netdev_priv(dev);
1938
1939 rtl8169_init_ring_indexes(tp);
1940
1941 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1942 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1943
1944 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1945 goto err_out;
1946
1947 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1948
1949 return 0;
1950
1951err_out:
1952 rtl8169_rx_clear(tp);
1953 return -ENOMEM;
1954}
1955
1956static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
1957 struct TxDesc *desc)
1958{
1959 unsigned int len = tx_skb->len;
1960
1961 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
1962 desc->opts1 = 0x00;
1963 desc->opts2 = 0x00;
1964 desc->addr = 0x00;
1965 tx_skb->len = 0;
1966}
1967
1968static void rtl8169_tx_clear(struct rtl8169_private *tp)
1969{
1970 unsigned int i;
1971
1972 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
1973 unsigned int entry = i % NUM_TX_DESC;
1974 struct ring_info *tx_skb = tp->tx_skb + entry;
1975 unsigned int len = tx_skb->len;
1976
1977 if (len) {
1978 struct sk_buff *skb = tx_skb->skb;
1979
1980 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
1981 tp->TxDescArray + entry);
1982 if (skb) {
1983 dev_kfree_skb(skb);
1984 tx_skb->skb = NULL;
1985 }
1986 tp->stats.tx_dropped++;
1987 }
1988 }
1989 tp->cur_tx = tp->dirty_tx = 0;
1990}
1991
1992static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995
1996 PREPARE_WORK(&tp->task, task, dev);
1997 schedule_delayed_work(&tp->task, 4);
1998}
1999
2000static void rtl8169_wait_for_quiescence(struct net_device *dev)
2001{
2002 struct rtl8169_private *tp = netdev_priv(dev);
2003 void __iomem *ioaddr = tp->mmio_addr;
2004
2005 synchronize_irq(dev->irq);
2006
2007 /* Wait for any pending NAPI task to complete */
2008 netif_poll_disable(dev);
2009
2010 rtl8169_irq_mask_and_ack(ioaddr);
2011
2012 netif_poll_enable(dev);
2013}
2014
2015static void rtl8169_reinit_task(void *_data)
2016{
2017 struct net_device *dev = _data;
2018 int ret;
2019
2020 if (netif_running(dev)) {
2021 rtl8169_wait_for_quiescence(dev);
2022 rtl8169_close(dev);
2023 }
2024
2025 ret = rtl8169_open(dev);
2026 if (unlikely(ret < 0)) {
2027 if (net_ratelimit()) {
b57b7e5a
SH		 2028 struct rtl8169_private *tp = netdev_priv(dev);
2029
2030 if (netif_msg_drv(tp)) {
2031 printk(PFX KERN_ERR
2032 "%s: reinit failure (status = %d)."
2033 " Rescheduling.\n", dev->name, ret);
2034 }
1da177e4
LT		 2035 }
2036 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2037 }
2038}
2039
2040static void rtl8169_reset_task(void *_data)
2041{
2042 struct net_device *dev = _data;
2043 struct rtl8169_private *tp = netdev_priv(dev);
2044
2045 if (!netif_running(dev))
2046 return;
2047
2048 rtl8169_wait_for_quiescence(dev);
2049
2050 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2051 rtl8169_tx_clear(tp);
2052
2053 if (tp->dirty_rx == tp->cur_rx) {
2054 rtl8169_init_ring_indexes(tp);
2055 rtl8169_hw_start(dev);
2056 netif_wake_queue(dev);
2057 } else {
2058 if (net_ratelimit()) {
b57b7e5a
SH		 2059 struct rtl8169_private *tp = netdev_priv(dev);
2060
2061 if (netif_msg_intr(tp)) {
2062 printk(PFX KERN_EMERG
2063 "%s: Rx buffers shortage\n", dev->name);
2064 }
1da177e4
LT		 2065 }
2066 rtl8169_schedule_work(dev, rtl8169_reset_task);
2067 }
2068}
2069
2070static void rtl8169_tx_timeout(struct net_device *dev)
2071{
2072 struct rtl8169_private *tp = netdev_priv(dev);
2073
2074 rtl8169_hw_reset(tp->mmio_addr);
2075
2076 /* Let's wait a bit while any (async) irq lands on */
2077 rtl8169_schedule_work(dev, rtl8169_reset_task);
2078}
2079
2080static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2081 u32 opts1)
2082{
2083 struct skb_shared_info *info = skb_shinfo(skb);
2084 unsigned int cur_frag, entry;
2085 struct TxDesc *txd;
2086
2087 entry = tp->cur_tx;
2088 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2089 skb_frag_t *frag = info->frags + cur_frag;
2090 dma_addr_t mapping;
2091 u32 status, len;
2092 void *addr;
2093
2094 entry = (entry + 1) % NUM_TX_DESC;
2095
2096 txd = tp->TxDescArray + entry;
2097 len = frag->size;
2098 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2099 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2100
2101 /* anti gcc 2.95.3 bugware (sic) */
2102 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2103
2104 txd->opts1 = cpu_to_le32(status);
2105 txd->addr = cpu_to_le64(mapping);
2106
2107 tp->tx_skb[entry].len = len;
2108 }
2109
2110 if (cur_frag) {
2111 tp->tx_skb[entry].skb = skb;
2112 txd->opts1 |= cpu_to_le32(LastFrag);
2113 }
2114
2115 return cur_frag;
2116}
2117
2118static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2119{
2120 if (dev->features & NETIF_F_TSO) {
2121 u32 mss = skb_shinfo(skb)->tso_size;
2122
2123 if (mss)
2124 return LargeSend | ((mss & MSSMask) << MSSShift);
2125 }
2126 if (skb->ip_summed == CHECKSUM_HW) {
2127 const struct iphdr *ip = skb->nh.iph;
2128
2129 if (ip->protocol == IPPROTO_TCP)
2130 return IPCS | TCPCS;
2131 else if (ip->protocol == IPPROTO_UDP)
2132 return IPCS | UDPCS;
2133 WARN_ON(1); /* we need a WARN() */
2134 }
2135 return 0;
2136}
2137
2138static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2139{
2140 struct rtl8169_private *tp = netdev_priv(dev);
2141 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2142 struct TxDesc *txd = tp->TxDescArray + entry;
2143 void __iomem *ioaddr = tp->mmio_addr;
2144 dma_addr_t mapping;
2145 u32 status, len;
2146 u32 opts1;
2147 int ret = 0;
2148
2149 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2150 if (netif_msg_drv(tp)) {
2151 printk(KERN_ERR
2152 "%s: BUG! Tx Ring full when queue awake!\n",
2153 dev->name);
2154 }
1da177e4
LT		 2155 goto err_stop;
2156 }
2157
2158 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2159 goto err_stop;
2160
2161 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2162
2163 frags = rtl8169_xmit_frags(tp, skb, opts1);
2164 if (frags) {
2165 len = skb_headlen(skb);
2166 opts1 |= FirstFrag;
2167 } else {
2168 len = skb->len;
2169
2170 if (unlikely(len < ETH_ZLEN)) {
2171 skb = skb_padto(skb, ETH_ZLEN);
2172 if (!skb)
2173 goto err_update_stats;
2174 len = ETH_ZLEN;
2175 }
2176
2177 opts1 |= FirstFrag | LastFrag;
2178 tp->tx_skb[entry].skb = skb;
2179 }
2180
2181 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2182
2183 tp->tx_skb[entry].len = len;
2184 txd->addr = cpu_to_le64(mapping);
2185 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2186
2187 wmb();
2188
2189 /* anti gcc 2.95.3 bugware (sic) */
2190 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2191 txd->opts1 = cpu_to_le32(status);
2192
2193 dev->trans_start = jiffies;
2194
2195 tp->cur_tx += frags + 1;
2196
2197 smp_wmb();
2198
2199 RTL_W8(TxPoll, 0x40); /* set polling bit */
2200
2201 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2202 netif_stop_queue(dev);
2203 smp_rmb();
2204 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2205 netif_wake_queue(dev);
2206 }
2207
2208out:
2209 return ret;
2210
2211err_stop:
2212 netif_stop_queue(dev);
2213 ret = 1;
2214err_update_stats:
2215 tp->stats.tx_dropped++;
2216 goto out;
2217}
2218
2219static void rtl8169_pcierr_interrupt(struct net_device *dev)
2220{
2221 struct rtl8169_private *tp = netdev_priv(dev);
2222 struct pci_dev *pdev = tp->pci_dev;
2223 void __iomem *ioaddr = tp->mmio_addr;
2224 u16 pci_status, pci_cmd;
2225
2226 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2227 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2228
b57b7e5a
SH		 2229 if (netif_msg_intr(tp)) {
2230 printk(KERN_ERR
2231 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2232 dev->name, pci_cmd, pci_status);
2233 }
1da177e4
LT		 2234
2235 /*
2236 * The recovery sequence below admits a very elaborated explanation:
2237 * - it seems to work;
2238 * - I did not see what else could be done.
2239 *
2240 * Feel free to adjust to your needs.
2241 */
2242 pci_write_config_word(pdev, PCI_COMMAND,
2243 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2244
2245 pci_write_config_word(pdev, PCI_STATUS,
2246 pci_status & (PCI_STATUS_DETECTED_PARITY |
2247 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2248 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2249
2250 /* The infamous DAC f*ckup only happens at boot time */
2251 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2252 if (netif_msg_intr(tp))
2253 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2254 tp->cp_cmd &= ~PCIDAC;
2255 RTL_W16(CPlusCmd, tp->cp_cmd);
2256 dev->features &= ~NETIF_F_HIGHDMA;
2257 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2258 }
2259
2260 rtl8169_hw_reset(ioaddr);
2261}
2262
2263static void
2264rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2265 void __iomem *ioaddr)
2266{
2267 unsigned int dirty_tx, tx_left;
2268
2269 assert(dev != NULL);
2270 assert(tp != NULL);
2271 assert(ioaddr != NULL);
2272
2273 dirty_tx = tp->dirty_tx;
2274 smp_rmb();
2275 tx_left = tp->cur_tx - dirty_tx;
2276
2277 while (tx_left > 0) {
2278 unsigned int entry = dirty_tx % NUM_TX_DESC;
2279 struct ring_info *tx_skb = tp->tx_skb + entry;
2280 u32 len = tx_skb->len;
2281 u32 status;
2282
2283 rmb();
2284 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2285 if (status & DescOwn)
2286 break;
2287
2288 tp->stats.tx_bytes += len;
2289 tp->stats.tx_packets++;
2290
2291 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2292
2293 if (status & LastFrag) {
2294 dev_kfree_skb_irq(tx_skb->skb);
2295 tx_skb->skb = NULL;
2296 }
2297 dirty_tx++;
2298 tx_left--;
2299 }
2300
2301 if (tp->dirty_tx != dirty_tx) {
2302 tp->dirty_tx = dirty_tx;
2303 smp_wmb();
2304 if (netif_queue_stopped(dev) &&
2305 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2306 netif_wake_queue(dev);
2307 }
2308 }
2309}
2310
126fa4b9
FR		 2311static inline int rtl8169_fragmented_frame(u32 status)
2312{
2313 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2314}
2315
1da177e4
LT		 2316static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2317{
2318 u32 opts1 = le32_to_cpu(desc->opts1);
2319 u32 status = opts1 & RxProtoMask;
2320
2321 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2322 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2323 ((status == RxProtoIP) && !(opts1 & IPFail)))
2324 skb->ip_summed = CHECKSUM_UNNECESSARY;
2325 else
2326 skb->ip_summed = CHECKSUM_NONE;
2327}
2328
2329static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2330 struct RxDesc *desc, int rx_buf_sz)
2331{
2332 int ret = -1;
2333
2334 if (pkt_size < rx_copybreak) {
2335 struct sk_buff *skb;
2336
2337 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2338 if (skb) {
2339 skb_reserve(skb, NET_IP_ALIGN);
689be439 2340 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2341 *sk_buff = skb;
2342 rtl8169_mark_to_asic(desc, rx_buf_sz);
2343 ret = 0;
2344 }
2345 }
2346 return ret;
2347}
2348
2349static int
2350rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2351 void __iomem *ioaddr)
2352{
2353 unsigned int cur_rx, rx_left;
2354 unsigned int delta, count;
2355
2356 assert(dev != NULL);
2357 assert(tp != NULL);
2358 assert(ioaddr != NULL);
2359
2360 cur_rx = tp->cur_rx;
2361 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2362 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2363
4dcb7d33 2364 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2365 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2366 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2367 u32 status;
2368
2369 rmb();
126fa4b9 2370 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2371
2372 if (status & DescOwn)
2373 break;
4dcb7d33 2374 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2375 if (netif_msg_rx_err(tp)) {
2376 printk(KERN_INFO
2377 "%s: Rx ERROR. status = %08x\n",
2378 dev->name, status);
2379 }
1da177e4
LT		 2380 tp->stats.rx_errors++;
2381 if (status & (RxRWT | RxRUNT))
2382 tp->stats.rx_length_errors++;
2383 if (status & RxCRC)
2384 tp->stats.rx_crc_errors++;
126fa4b9 2385 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2386 } else {
1da177e4
LT		 2387 struct sk_buff *skb = tp->Rx_skbuff[entry];
2388 int pkt_size = (status & 0x00001FFF) - 4;
2389 void (*pci_action)(struct pci_dev *, dma_addr_t,
2390 size_t, int) = pci_dma_sync_single_for_device;
2391
126fa4b9
FR		 2392 /*
2393 * The driver does not support incoming fragmented
2394 * frames. They are seen as a symptom of over-mtu
2395 * sized frames.
2396 */
2397 if (unlikely(rtl8169_fragmented_frame(status))) {
2398 tp->stats.rx_dropped++;
2399 tp->stats.rx_length_errors++;
2400 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2401 continue;
126fa4b9
FR		 2402 }
2403
1da177e4
LT		 2404 rtl8169_rx_csum(skb, desc);
2405
2406 pci_dma_sync_single_for_cpu(tp->pci_dev,
2407 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2408 PCI_DMA_FROMDEVICE);
2409
2410 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2411 tp->rx_buf_sz)) {
2412 pci_action = pci_unmap_single;
2413 tp->Rx_skbuff[entry] = NULL;
2414 }
2415
2416 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2417 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2418
2419 skb->dev = dev;
2420 skb_put(skb, pkt_size);
2421 skb->protocol = eth_type_trans(skb, dev);
2422
2423 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2424 rtl8169_rx_skb(skb);
2425
2426 dev->last_rx = jiffies;
2427 tp->stats.rx_bytes += pkt_size;
2428 tp->stats.rx_packets++;
2429 }
1da177e4
LT		 2430 }
2431
2432 count = cur_rx - tp->cur_rx;
2433 tp->cur_rx = cur_rx;
2434
2435 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2436 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2437 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2438 tp->dirty_rx += delta;
2439
2440 /*
2441 * FIXME: until there is periodic timer to try and refill the ring,
2442 * a temporary shortage may definitely kill the Rx process.
2443 * - disable the asic to try and avoid an overflow and kick it again
2444 * after refill ?
2445 * - how do others driver handle this condition (Uh oh...).
2446 */
b57b7e5a 2447 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2448 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2449
2450 return count;
2451}
2452
2453/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2454static irqreturn_t
2455rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2456{
2457 struct net_device *dev = (struct net_device *) dev_instance;
2458 struct rtl8169_private *tp = netdev_priv(dev);
2459 int boguscnt = max_interrupt_work;
2460 void __iomem *ioaddr = tp->mmio_addr;
2461 int status;
2462 int handled = 0;
2463
2464 do {
2465 status = RTL_R16(IntrStatus);
2466
2467 /* hotplug/major error/no more work/shared irq */
2468 if ((status == 0xFFFF) || !status)
2469 break;
2470
2471 handled = 1;
2472
2473 if (unlikely(!netif_running(dev))) {
2474 rtl8169_asic_down(ioaddr);
2475 goto out;
2476 }
2477
2478 status &= tp->intr_mask;
2479 RTL_W16(IntrStatus,
2480 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2481
2482 if (!(status & rtl8169_intr_mask))
2483 break;
2484
2485 if (unlikely(status & SYSErr)) {
2486 rtl8169_pcierr_interrupt(dev);
2487 break;
2488 }
2489
2490 if (status & LinkChg)
2491 rtl8169_check_link_status(dev, tp, ioaddr);
2492
2493#ifdef CONFIG_R8169_NAPI
2494 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2495 tp->intr_mask = ~rtl8169_napi_event;
2496
2497 if (likely(netif_rx_schedule_prep(dev)))
2498 __netif_rx_schedule(dev);
b57b7e5a 2499 else if (netif_msg_intr(tp)) {
1da177e4
LT		 2500 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2501 dev->name, status);
2502 }
2503 break;
2504#else
2505 /* Rx interrupt */
2506 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2507 rtl8169_rx_interrupt(dev, tp, ioaddr);
2508 }
2509 /* Tx interrupt */
2510 if (status & (TxOK | TxErr))
2511 rtl8169_tx_interrupt(dev, tp, ioaddr);
2512#endif
2513
2514 boguscnt--;
2515 } while (boguscnt > 0);
2516
2517 if (boguscnt <= 0) {
7c8b2eb4 2518 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2519 printk(KERN_WARNING
2520 "%s: Too much work at interrupt!\n", dev->name);
2521 }
1da177e4
LT		 2522 /* Clear all interrupt sources. */
2523 RTL_W16(IntrStatus, 0xffff);
2524 }
2525out:
2526 return IRQ_RETVAL(handled);
2527}
2528
2529#ifdef CONFIG_R8169_NAPI
2530static int rtl8169_poll(struct net_device *dev, int *budget)
2531{
2532 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2533 struct rtl8169_private *tp = netdev_priv(dev);
2534 void __iomem *ioaddr = tp->mmio_addr;
2535
2536 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2537 rtl8169_tx_interrupt(dev, tp, ioaddr);
2538
2539 *budget -= work_done;
2540 dev->quota -= work_done;
2541
2542 if (work_done < work_to_do) {
2543 netif_rx_complete(dev);
2544 tp->intr_mask = 0xffff;
2545 /*
2546 * 20040426: the barrier is not strictly required but the
2547 * behavior of the irq handler could be less predictable
2548 * without it. Btw, the lack of flush for the posted pci
2549 * write is safe - FR
2550 */
2551 smp_wmb();
2552 RTL_W16(IntrMask, rtl8169_intr_mask);
2553 }
2554
2555 return (work_done >= work_to_do);
2556}
2557#endif
2558
2559static void rtl8169_down(struct net_device *dev)
2560{
2561 struct rtl8169_private *tp = netdev_priv(dev);
2562 void __iomem *ioaddr = tp->mmio_addr;
2563 unsigned int poll_locked = 0;
2564
2565 rtl8169_delete_timer(dev);
2566
2567 netif_stop_queue(dev);
2568
2569 flush_scheduled_work();
2570
2571core_down:
2572 spin_lock_irq(&tp->lock);
2573
2574 rtl8169_asic_down(ioaddr);
2575
2576 /* Update the error counts. */
2577 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2578 RTL_W32(RxMissed, 0);
2579
2580 spin_unlock_irq(&tp->lock);
2581
2582 synchronize_irq(dev->irq);
2583
2584 if (!poll_locked) {
2585 netif_poll_disable(dev);
2586 poll_locked++;
2587 }
2588
2589 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2590 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2591
2592 /*
2593 * And now for the 50k$ question: are IRQ disabled or not ?
2594 *
2595 * Two paths lead here:
2596 * 1) dev->close
2597 * -> netif_running() is available to sync the current code and the
2598 * IRQ handler. See rtl8169_interrupt for details.
2599 * 2) dev->change_mtu
2600 * -> rtl8169_poll can not be issued again and re-enable the
2601 * interruptions. Let's simply issue the IRQ down sequence again.
2602 */
2603 if (RTL_R16(IntrMask))
2604 goto core_down;
2605
2606 rtl8169_tx_clear(tp);
2607
2608 rtl8169_rx_clear(tp);
2609}
2610
2611static int rtl8169_close(struct net_device *dev)
2612{
2613 struct rtl8169_private *tp = netdev_priv(dev);
2614 struct pci_dev *pdev = tp->pci_dev;
2615
2616 rtl8169_down(dev);
2617
2618 free_irq(dev->irq, dev);
2619
2620 netif_poll_enable(dev);
2621
2622 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2623 tp->RxPhyAddr);
2624 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2625 tp->TxPhyAddr);
2626 tp->TxDescArray = NULL;
2627 tp->RxDescArray = NULL;
2628
2629 return 0;
2630}
2631
2632static void
2633rtl8169_set_rx_mode(struct net_device *dev)
2634{
2635 struct rtl8169_private *tp = netdev_priv(dev);
2636 void __iomem *ioaddr = tp->mmio_addr;
2637 unsigned long flags;
2638 u32 mc_filter[2]; /* Multicast hash filter */
2639 int i, rx_mode;
2640 u32 tmp = 0;
2641
2642 if (dev->flags & IFF_PROMISC) {
2643 /* Unconditionally log net taps. */
b57b7e5a
SH		 2644 if (netif_msg_link(tp)) {
2645 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2646 dev->name);
2647 }
1da177e4
LT		 2648 rx_mode =
2649 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2650 AcceptAllPhys;
2651 mc_filter[1] = mc_filter[0] = 0xffffffff;
2652 } else if ((dev->mc_count > multicast_filter_limit)
2653 || (dev->flags & IFF_ALLMULTI)) {
2654 /* Too many to filter perfectly -- accept all multicasts. */
2655 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2656 mc_filter[1] = mc_filter[0] = 0xffffffff;
2657 } else {
2658 struct dev_mc_list *mclist;
2659 rx_mode = AcceptBroadcast | AcceptMyPhys;
2660 mc_filter[1] = mc_filter[0] = 0;
2661 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2662 i++, mclist = mclist->next) {
2663 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2664 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2665 rx_mode |= AcceptMulticast;
2666 }
2667 }
2668
2669 spin_lock_irqsave(&tp->lock, flags);
2670
2671 tmp = rtl8169_rx_config | rx_mode |
2672 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2673
2674 RTL_W32(RxConfig, tmp);
2675 RTL_W32(MAR0 + 0, mc_filter[0]);
2676 RTL_W32(MAR0 + 4, mc_filter[1]);
2677
2678 spin_unlock_irqrestore(&tp->lock, flags);
2679}
2680
2681/**
2682 * rtl8169_get_stats - Get rtl8169 read/write statistics
2683 * @dev: The Ethernet Device to get statistics for
2684 *
2685 * Get TX/RX statistics for rtl8169
2686 */
2687static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2688{
2689 struct rtl8169_private *tp = netdev_priv(dev);
2690 void __iomem *ioaddr = tp->mmio_addr;
2691 unsigned long flags;
2692
2693 if (netif_running(dev)) {
2694 spin_lock_irqsave(&tp->lock, flags);
2695 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2696 RTL_W32(RxMissed, 0);
2697 spin_unlock_irqrestore(&tp->lock, flags);
2698 }
2699
2700 return &tp->stats;
2701}
2702
2703static struct pci_driver rtl8169_pci_driver = {
2704 .name = MODULENAME,
2705 .id_table = rtl8169_pci_tbl,
2706 .probe = rtl8169_init_one,
2707 .remove = __devexit_p(rtl8169_remove_one),
2708#ifdef CONFIG_PM
2709 .suspend = rtl8169_suspend,
2710 .resume = rtl8169_resume,
2711#endif
2712};
2713
2714static int __init
2715rtl8169_init_module(void)
2716{
2717 return pci_module_init(&rtl8169_pci_driver);
2718}
2719
2720static void __exit
2721rtl8169_cleanup_module(void)
2722{
2723 pci_unregister_driver(&rtl8169_pci_driver);
2724}
2725
2726module_init(rtl8169_init_module);
2727module_exit(rtl8169_cleanup_module);
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