]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/r8169.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: more magic during initialization of the hardware
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4 9 2004 - Massive updates. See kernel SCM system for details.
1da177e4
LT		 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4 14
1da177e4
LT		 15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
5b0384f4 21
1da177e4
LT		 22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4 28 exchanging Link Code Word (FLP).
1da177e4
LT		 29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
5b0384f4
FR		 84 if (!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
1da177e4
LT		 88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 116static const int max_interrupt_work = 20;
1da177e4
LT		 117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 120static const int multicast_filter_limit = 32;
1da177e4
LT		 121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
bcf0bf90
FR		 153 RTL_GIGA_MAC_VER_01 = 0x00,
154 RTL_GIGA_MAC_VER_02 = 0x01,
155 RTL_GIGA_MAC_VER_03 = 0x02,
156 RTL_GIGA_MAC_VER_04 = 0x03,
157 RTL_GIGA_MAC_VER_05 = 0x04,
158 RTL_GIGA_MAC_VER_11 = 0x0b,
159 RTL_GIGA_MAC_VER_12 = 0x0c,
160 RTL_GIGA_MAC_VER_13 = 0x0d,
161 RTL_GIGA_MAC_VER_14 = 0x0e,
162 RTL_GIGA_MAC_VER_15 = 0x0f
1da177e4
LT		 163};
164
165enum phy_version {
166 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
167 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
168 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
170 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
171 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
172};
173
1da177e4
LT		 174#define _R(NAME,MAC,MASK) \
175 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
176
3c6bee1d 177static const struct {
1da177e4
LT		 178 const char *name;
179 u8 mac_version;
180 u32 RxConfigMask; /* Clears the bits supported by this chip */
181} rtl_chip_info[] = {
bcf0bf90
FR		 182 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
183 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
185 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
186 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
187 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
189 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
190 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
191 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 192};
193#undef _R
194
bcf0bf90
FR		 195enum cfg_version {
196 RTL_CFG_0 = 0x00,
197 RTL_CFG_1,
198 RTL_CFG_2
199};
200
201static const struct {
202 unsigned int region;
203 unsigned int align;
204} rtl_cfg_info[] = {
205 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
206 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
207 [RTL_CFG_2] = { 2, 8 }
208};
209
1da177e4 210static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
216 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 217 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 218 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
219 { PCI_VENDOR_ID_LINKSYS, 0x1032,
220 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 221 {0,},
222};
223
224MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
226static int rx_copybreak = 200;
227static int use_dac;
b57b7e5a
SH		 228static struct {
229 u32 msg_enable;
230} debug = { -1 };
1da177e4
LT		 231
232enum RTL8169_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
234 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 235 CounterAddrLow = 0x10,
236 CounterAddrHigh = 0x14,
1da177e4
LT		 237 TxDescStartAddrLow = 0x20,
238 TxDescStartAddrHigh = 0x24,
239 TxHDescStartAddrLow = 0x28,
240 TxHDescStartAddrHigh = 0x2c,
241 FLASH = 0x30,
242 ERSR = 0x36,
243 ChipCmd = 0x37,
244 TxPoll = 0x38,
245 IntrMask = 0x3C,
246 IntrStatus = 0x3E,
247 TxConfig = 0x40,
248 RxConfig = 0x44,
249 RxMissed = 0x4C,
250 Cfg9346 = 0x50,
251 Config0 = 0x51,
252 Config1 = 0x52,
253 Config2 = 0x53,
254 Config3 = 0x54,
255 Config4 = 0x55,
256 Config5 = 0x56,
257 MultiIntr = 0x5C,
258 PHYAR = 0x60,
259 TBICSR = 0x64,
260 TBI_ANAR = 0x68,
261 TBI_LPAR = 0x6A,
262 PHYstatus = 0x6C,
263 RxMaxSize = 0xDA,
264 CPlusCmd = 0xE0,
265 IntrMitigate = 0xE2,
266 RxDescAddrLow = 0xE4,
267 RxDescAddrHigh = 0xE8,
268 EarlyTxThres = 0xEC,
269 FuncEvent = 0xF0,
270 FuncEventMask = 0xF4,
271 FuncPresetState = 0xF8,
272 FuncForceEvent = 0xFC,
273};
274
275enum RTL8169_register_content {
276 /* InterruptStatusBits */
277 SYSErr = 0x8000,
278 PCSTimeout = 0x4000,
279 SWInt = 0x0100,
280 TxDescUnavail = 0x80,
281 RxFIFOOver = 0x40,
282 LinkChg = 0x20,
283 RxOverflow = 0x10,
284 TxErr = 0x08,
285 TxOK = 0x04,
286 RxErr = 0x02,
287 RxOK = 0x01,
288
289 /* RxStatusDesc */
9dccf611
FR		 290 RxFOVF = (1 << 23),
291 RxRWT = (1 << 22),
292 RxRES = (1 << 21),
293 RxRUNT = (1 << 20),
294 RxCRC = (1 << 19),
1da177e4
LT		 295
296 /* ChipCmdBits */
297 CmdReset = 0x10,
298 CmdRxEnb = 0x08,
299 CmdTxEnb = 0x04,
300 RxBufEmpty = 0x01,
301
302 /* Cfg9346Bits */
303 Cfg9346_Lock = 0x00,
304 Cfg9346_Unlock = 0xC0,
305
306 /* rx_mode_bits */
307 AcceptErr = 0x20,
308 AcceptRunt = 0x10,
309 AcceptBroadcast = 0x08,
310 AcceptMulticast = 0x04,
311 AcceptMyPhys = 0x02,
312 AcceptAllPhys = 0x01,
313
314 /* RxConfigBits */
315 RxCfgFIFOShift = 13,
316 RxCfgDMAShift = 8,
317
318 /* TxConfigBits */
319 TxInterFrameGapShift = 24,
320 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
321
5d06a99f
FR		 322 /* Config1 register p.24 */
323 PMEnable = (1 << 0), /* Power Management Enable */
324
61a4dcc2
FR		 325 /* Config3 register p.25 */
326 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
327 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
328
5d06a99f 329 /* Config5 register p.27 */
61a4dcc2
FR		 330 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF = (1 << 5), /* Accept Multicast wakeup frame */
332 UWF = (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 334 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
335
1da177e4
LT		 336 /* TBICSR p.28 */
337 TBIReset = 0x80000000,
338 TBILoopback = 0x40000000,
339 TBINwEnable = 0x20000000,
340 TBINwRestart = 0x10000000,
341 TBILinkOk = 0x02000000,
342 TBINwComplete = 0x01000000,
343
344 /* CPlusCmd p.31 */
345 RxVlan = (1 << 6),
346 RxChkSum = (1 << 5),
347 PCIDAC = (1 << 4),
348 PCIMulRW = (1 << 3),
349
350 /* rtl8169_PHYstatus */
351 TBI_Enable = 0x80,
352 TxFlowCtrl = 0x40,
353 RxFlowCtrl = 0x20,
354 _1000bpsF = 0x10,
355 _100bps = 0x08,
356 _10bps = 0x04,
357 LinkStatus = 0x02,
358 FullDup = 0x01,
359
1da177e4
LT		 360 /* _MediaType */
361 _10_Half = 0x01,
362 _10_Full = 0x02,
363 _100_Half = 0x04,
364 _100_Full = 0x08,
365 _1000_Full = 0x10,
366
367 /* _TBICSRBit */
368 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 369
370 /* DumpCounterCommand */
371 CounterDump = 0x8,
1da177e4
LT		 372};
373
374enum _DescStatusBit {
375 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
376 RingEnd = (1 << 30), /* End of descriptor ring */
377 FirstFrag = (1 << 29), /* First segment of a packet */
378 LastFrag = (1 << 28), /* Final segment of a packet */
379
380 /* Tx private */
381 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
382 MSSShift = 16, /* MSS value position */
383 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
384 IPCS = (1 << 18), /* Calculate IP checksum */
385 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
386 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
387 TxVlanTag = (1 << 17), /* Add VLAN tag */
388
389 /* Rx private */
390 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
391 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
392
393#define RxProtoUDP (PID1)
394#define RxProtoTCP (PID0)
395#define RxProtoIP (PID1 | PID0)
396#define RxProtoMask RxProtoIP
397
398 IPFail = (1 << 16), /* IP checksum failed */
399 UDPFail = (1 << 15), /* UDP/IP checksum failed */
400 TCPFail = (1 << 14), /* TCP/IP checksum failed */
401 RxVlanTag = (1 << 16), /* VLAN tag available */
402};
403
404#define RsvdMask 0x3fffc000
405
406struct TxDesc {
407 u32 opts1;
408 u32 opts2;
409 u64 addr;
410};
411
412struct RxDesc {
413 u32 opts1;
414 u32 opts2;
415 u64 addr;
416};
417
418struct ring_info {
419 struct sk_buff *skb;
420 u32 len;
421 u8 __pad[sizeof(void *) - sizeof(u32)];
422};
423
424struct rtl8169_private {
425 void __iomem *mmio_addr; /* memory map physical address */
426 struct pci_dev *pci_dev; /* Index of PCI device */
427 struct net_device_stats stats; /* statistics of net device */
428 spinlock_t lock; /* spin lock flag */
b57b7e5a 429 u32 msg_enable;
1da177e4
LT		 430 int chipset;
431 int mac_version;
432 int phy_version;
433 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
434 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
435 u32 dirty_rx;
436 u32 dirty_tx;
437 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
438 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
439 dma_addr_t TxPhyAddr;
440 dma_addr_t RxPhyAddr;
441 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
442 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 443 unsigned align;
1da177e4
LT		 444 unsigned rx_buf_sz;
445 struct timer_list timer;
446 u16 cp_cmd;
447 u16 intr_mask;
448 int phy_auto_nego_reg;
449 int phy_1000_ctrl_reg;
450#ifdef CONFIG_R8169_VLAN
451 struct vlan_group *vlgrp;
452#endif
453 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
454 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
455 void (*phy_reset_enable)(void __iomem *);
456 unsigned int (*phy_reset_pending)(void __iomem *);
457 unsigned int (*link_ok)(void __iomem *);
458 struct work_struct task;
61a4dcc2 459 unsigned wol_enabled : 1;
1da177e4
LT		 460};
461
979b6c13 462MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 463MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
464module_param_array(media, int, &num_media, 0);
df0a1bf6 465MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 466module_param(rx_copybreak, int, 0);
1b7efd58 467MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 468module_param(use_dac, int, 0);
469MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 470module_param_named(debug, debug.msg_enable, int, 0);
471MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 472MODULE_LICENSE("GPL");
473MODULE_VERSION(RTL8169_VERSION);
474
475static int rtl8169_open(struct net_device *dev);
476static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 477static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4
LT		 478static int rtl8169_init_ring(struct net_device *dev);
479static void rtl8169_hw_start(struct net_device *dev);
480static int rtl8169_close(struct net_device *dev);
481static void rtl8169_set_rx_mode(struct net_device *dev);
482static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 483static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 484static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
485 void __iomem *);
4dcb7d33 486static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 487static void rtl8169_down(struct net_device *dev);
488
489#ifdef CONFIG_R8169_NAPI
490static int rtl8169_poll(struct net_device *dev, int *budget);
491#endif
492
493static const u16 rtl8169_intr_mask =
494 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
495static const u16 rtl8169_napi_event =
496 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
497static const unsigned int rtl8169_rx_config =
5b0384f4 498 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4
LT		 499
500static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
501{
502 int i;
503
504 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 505
2371408c 506 for (i = 20; i > 0; i--) {
1da177e4 507 /* Check if the RTL8169 has completed writing to the specified MII register */
5b0384f4 508 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 509 break;
2371408c 510 udelay(25);
1da177e4
LT		 511 }
512}
513
514static int mdio_read(void __iomem *ioaddr, int RegAddr)
515{
516 int i, value = -1;
517
518 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 519
2371408c 520 for (i = 20; i > 0; i--) {
1da177e4
LT		 521 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
522 if (RTL_R32(PHYAR) & 0x80000000) {
523 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
524 break;
525 }
2371408c 526 udelay(25);
1da177e4
LT		 527 }
528 return value;
529}
530
531static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
532{
533 RTL_W16(IntrMask, 0x0000);
534
535 RTL_W16(IntrStatus, 0xffff);
536}
537
538static void rtl8169_asic_down(void __iomem *ioaddr)
539{
540 RTL_W8(ChipCmd, 0x00);
541 rtl8169_irq_mask_and_ack(ioaddr);
542 RTL_R16(CPlusCmd);
543}
544
545static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
546{
547 return RTL_R32(TBICSR) & TBIReset;
548}
549
550static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
551{
64e4bfb4 552 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 553}
554
555static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
556{
557 return RTL_R32(TBICSR) & TBILinkOk;
558}
559
560static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
561{
562 return RTL_R8(PHYstatus) & LinkStatus;
563}
564
565static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
566{
567 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
568}
569
570static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
571{
572 unsigned int val;
573
bf793295
FR		 574 mdio_write(ioaddr, MII_BMCR, BMCR_RESET);
575 val = mdio_read(ioaddr, MII_BMCR);
1da177e4
LT		 576}
577
578static void rtl8169_check_link_status(struct net_device *dev,
579 struct rtl8169_private *tp, void __iomem *ioaddr)
580{
581 unsigned long flags;
582
583 spin_lock_irqsave(&tp->lock, flags);
584 if (tp->link_ok(ioaddr)) {
585 netif_carrier_on(dev);
b57b7e5a
SH		 586 if (netif_msg_ifup(tp))
587 printk(KERN_INFO PFX "%s: link up\n", dev->name);
588 } else {
589 if (netif_msg_ifdown(tp))
590 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 591 netif_carrier_off(dev);
b57b7e5a 592 }
1da177e4
LT		 593 spin_unlock_irqrestore(&tp->lock, flags);
594}
595
596static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
597{
598 struct {
599 u16 speed;
600 u8 duplex;
601 u8 autoneg;
602 u8 media;
603 } link_settings[] = {
604 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
605 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
606 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
607 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
608 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
609 /* Make TBI happy */
610 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
611 }, *p;
612 unsigned char option;
5b0384f4 613
1da177e4
LT		 614 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
615
b57b7e5a 616 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 617 printk(KERN_WARNING PFX "media option is deprecated.\n");
618
619 for (p = link_settings; p->media != 0xff; p++) {
620 if (p->media == option)
621 break;
622 }
623 *autoneg = p->autoneg;
624 *speed = p->speed;
625 *duplex = p->duplex;
626}
627
61a4dcc2
FR		 628static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
629{
630 struct rtl8169_private *tp = netdev_priv(dev);
631 void __iomem *ioaddr = tp->mmio_addr;
632 u8 options;
633
634 wol->wolopts = 0;
635
636#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
637 wol->supported = WAKE_ANY;
638
639 spin_lock_irq(&tp->lock);
640
641 options = RTL_R8(Config1);
642 if (!(options & PMEnable))
643 goto out_unlock;
644
645 options = RTL_R8(Config3);
646 if (options & LinkUp)
647 wol->wolopts |= WAKE_PHY;
648 if (options & MagicPacket)
649 wol->wolopts |= WAKE_MAGIC;
650
651 options = RTL_R8(Config5);
652 if (options & UWF)
653 wol->wolopts |= WAKE_UCAST;
654 if (options & BWF)
5b0384f4 655 wol->wolopts |= WAKE_BCAST;
61a4dcc2 656 if (options & MWF)
5b0384f4 657 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 658
659out_unlock:
660 spin_unlock_irq(&tp->lock);
661}
662
663static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
664{
665 struct rtl8169_private *tp = netdev_priv(dev);
666 void __iomem *ioaddr = tp->mmio_addr;
667 int i;
668 static struct {
669 u32 opt;
670 u16 reg;
671 u8 mask;
672 } cfg[] = {
673 { WAKE_ANY, Config1, PMEnable },
674 { WAKE_PHY, Config3, LinkUp },
675 { WAKE_MAGIC, Config3, MagicPacket },
676 { WAKE_UCAST, Config5, UWF },
677 { WAKE_BCAST, Config5, BWF },
678 { WAKE_MCAST, Config5, MWF },
679 { WAKE_ANY, Config5, LanWake }
680 };
681
682 spin_lock_irq(&tp->lock);
683
684 RTL_W8(Cfg9346, Cfg9346_Unlock);
685
686 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
687 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
688 if (wol->wolopts & cfg[i].opt)
689 options |= cfg[i].mask;
690 RTL_W8(cfg[i].reg, options);
691 }
692
693 RTL_W8(Cfg9346, Cfg9346_Lock);
694
695 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
696
697 spin_unlock_irq(&tp->lock);
698
699 return 0;
700}
701
1da177e4
LT		 702static void rtl8169_get_drvinfo(struct net_device *dev,
703 struct ethtool_drvinfo *info)
704{
705 struct rtl8169_private *tp = netdev_priv(dev);
706
707 strcpy(info->driver, MODULENAME);
708 strcpy(info->version, RTL8169_VERSION);
709 strcpy(info->bus_info, pci_name(tp->pci_dev));
710}
711
712static int rtl8169_get_regs_len(struct net_device *dev)
713{
714 return R8169_REGS_SIZE;
715}
716
717static int rtl8169_set_speed_tbi(struct net_device *dev,
718 u8 autoneg, u16 speed, u8 duplex)
719{
720 struct rtl8169_private *tp = netdev_priv(dev);
721 void __iomem *ioaddr = tp->mmio_addr;
722 int ret = 0;
723 u32 reg;
724
725 reg = RTL_R32(TBICSR);
726 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
727 (duplex == DUPLEX_FULL)) {
728 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
729 } else if (autoneg == AUTONEG_ENABLE)
730 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
731 else {
b57b7e5a
SH		 732 if (netif_msg_link(tp)) {
733 printk(KERN_WARNING "%s: "
734 "incorrect speed setting refused in TBI mode\n",
735 dev->name);
736 }
1da177e4
LT		 737 ret = -EOPNOTSUPP;
738 }
739
740 return ret;
741}
742
743static int rtl8169_set_speed_xmii(struct net_device *dev,
744 u8 autoneg, u16 speed, u8 duplex)
745{
746 struct rtl8169_private *tp = netdev_priv(dev);
747 void __iomem *ioaddr = tp->mmio_addr;
748 int auto_nego, giga_ctrl;
749
64e4bfb4
FR		 750 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
751 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
752 ADVERTISE_100HALF | ADVERTISE_100FULL);
753 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
754 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 755
756 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 757 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
758 ADVERTISE_100HALF | ADVERTISE_100FULL);
759 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 760 } else {
761 if (speed == SPEED_10)
64e4bfb4 762 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 763 else if (speed == SPEED_100)
64e4bfb4 764 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 765 else if (speed == SPEED_1000)
64e4bfb4 766 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 767
768 if (duplex == DUPLEX_HALF)
64e4bfb4 769 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 770
771 if (duplex == DUPLEX_FULL)
64e4bfb4 772 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 773
774 /* This tweak comes straight from Realtek's driver. */
775 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
776 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 777 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 778 }
779 }
780
781 /* The 8100e/8101e do Fast Ethernet only. */
782 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
783 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
784 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 785 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 786 netif_msg_link(tp)) {
787 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
788 dev->name);
789 }
64e4bfb4 790 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 791 }
792
623a1593
FR		 793 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
794
1da177e4
LT		 795 tp->phy_auto_nego_reg = auto_nego;
796 tp->phy_1000_ctrl_reg = giga_ctrl;
797
64e4bfb4
FR		 798 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
799 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
800 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 801 return 0;
802}
803
804static int rtl8169_set_speed(struct net_device *dev,
805 u8 autoneg, u16 speed, u8 duplex)
806{
807 struct rtl8169_private *tp = netdev_priv(dev);
808 int ret;
809
810 ret = tp->set_speed(dev, autoneg, speed, duplex);
811
64e4bfb4 812 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 813 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
814
815 return ret;
816}
817
818static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
819{
820 struct rtl8169_private *tp = netdev_priv(dev);
821 unsigned long flags;
822 int ret;
823
824 spin_lock_irqsave(&tp->lock, flags);
825 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
826 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 827
1da177e4
LT		 828 return ret;
829}
830
831static u32 rtl8169_get_rx_csum(struct net_device *dev)
832{
833 struct rtl8169_private *tp = netdev_priv(dev);
834
835 return tp->cp_cmd & RxChkSum;
836}
837
838static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
839{
840 struct rtl8169_private *tp = netdev_priv(dev);
841 void __iomem *ioaddr = tp->mmio_addr;
842 unsigned long flags;
843
844 spin_lock_irqsave(&tp->lock, flags);
845
846 if (data)
847 tp->cp_cmd |= RxChkSum;
848 else
849 tp->cp_cmd &= ~RxChkSum;
850
851 RTL_W16(CPlusCmd, tp->cp_cmd);
852 RTL_R16(CPlusCmd);
853
854 spin_unlock_irqrestore(&tp->lock, flags);
855
856 return 0;
857}
858
859#ifdef CONFIG_R8169_VLAN
860
861static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
862 struct sk_buff *skb)
863{
864 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
865 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
866}
867
868static void rtl8169_vlan_rx_register(struct net_device *dev,
869 struct vlan_group *grp)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 unsigned long flags;
874
875 spin_lock_irqsave(&tp->lock, flags);
876 tp->vlgrp = grp;
877 if (tp->vlgrp)
878 tp->cp_cmd |= RxVlan;
879 else
880 tp->cp_cmd &= ~RxVlan;
881 RTL_W16(CPlusCmd, tp->cp_cmd);
882 RTL_R16(CPlusCmd);
883 spin_unlock_irqrestore(&tp->lock, flags);
884}
885
886static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
887{
888 struct rtl8169_private *tp = netdev_priv(dev);
889 unsigned long flags;
890
891 spin_lock_irqsave(&tp->lock, flags);
892 if (tp->vlgrp)
893 tp->vlgrp->vlan_devices[vid] = NULL;
894 spin_unlock_irqrestore(&tp->lock, flags);
895}
896
897static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
898 struct sk_buff *skb)
899{
900 u32 opts2 = le32_to_cpu(desc->opts2);
901 int ret;
902
903 if (tp->vlgrp && (opts2 & RxVlanTag)) {
904 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
905 swab16(opts2 & 0xffff));
906 ret = 0;
907 } else
908 ret = -1;
909 desc->opts2 = 0;
910 return ret;
911}
912
913#else /* !CONFIG_R8169_VLAN */
914
915static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
916 struct sk_buff *skb)
917{
918 return 0;
919}
920
921static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
922 struct sk_buff *skb)
923{
924 return -1;
925}
926
927#endif
928
929static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
930{
931 struct rtl8169_private *tp = netdev_priv(dev);
932 void __iomem *ioaddr = tp->mmio_addr;
933 u32 status;
934
935 cmd->supported =
936 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
937 cmd->port = PORT_FIBRE;
938 cmd->transceiver = XCVR_INTERNAL;
939
940 status = RTL_R32(TBICSR);
941 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
942 cmd->autoneg = !!(status & TBINwEnable);
943
944 cmd->speed = SPEED_1000;
945 cmd->duplex = DUPLEX_FULL; /* Always set */
946}
947
948static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
949{
950 struct rtl8169_private *tp = netdev_priv(dev);
951 void __iomem *ioaddr = tp->mmio_addr;
952 u8 status;
953
954 cmd->supported = SUPPORTED_10baseT_Half |
955 SUPPORTED_10baseT_Full |
956 SUPPORTED_100baseT_Half |
957 SUPPORTED_100baseT_Full |
958 SUPPORTED_1000baseT_Full |
959 SUPPORTED_Autoneg |
5b0384f4 960 SUPPORTED_TP;
1da177e4
LT		 961
962 cmd->autoneg = 1;
963 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
964
64e4bfb4 965 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 966 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 967 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 968 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 969 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 970 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 971 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 972 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 973 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 974 cmd->advertising |= ADVERTISED_1000baseT_Full;
975
976 status = RTL_R8(PHYstatus);
977
978 if (status & _1000bpsF)
979 cmd->speed = SPEED_1000;
980 else if (status & _100bps)
981 cmd->speed = SPEED_100;
982 else if (status & _10bps)
983 cmd->speed = SPEED_10;
984
623a1593
FR		 985 if (status & TxFlowCtrl)
986 cmd->advertising |= ADVERTISED_Asym_Pause;
987 if (status & RxFlowCtrl)
988 cmd->advertising |= ADVERTISED_Pause;
989
1da177e4
LT		 990 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
991 DUPLEX_FULL : DUPLEX_HALF;
992}
993
994static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
995{
996 struct rtl8169_private *tp = netdev_priv(dev);
997 unsigned long flags;
998
999 spin_lock_irqsave(&tp->lock, flags);
1000
1001 tp->get_settings(dev, cmd);
1002
1003 spin_unlock_irqrestore(&tp->lock, flags);
1004 return 0;
1005}
1006
1007static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1008 void *p)
1009{
5b0384f4
FR		 1010 struct rtl8169_private *tp = netdev_priv(dev);
1011 unsigned long flags;
1da177e4 1012
5b0384f4
FR		 1013 if (regs->len > R8169_REGS_SIZE)
1014 regs->len = R8169_REGS_SIZE;
1da177e4 1015
5b0384f4
FR		 1016 spin_lock_irqsave(&tp->lock, flags);
1017 memcpy_fromio(p, tp->mmio_addr, regs->len);
1018 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1019}
1020
b57b7e5a
SH		 1021static u32 rtl8169_get_msglevel(struct net_device *dev)
1022{
1023 struct rtl8169_private *tp = netdev_priv(dev);
1024
1025 return tp->msg_enable;
1026}
1027
1028static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1029{
1030 struct rtl8169_private *tp = netdev_priv(dev);
1031
1032 tp->msg_enable = value;
1033}
1034
d4a3a0fc
SH		 1035static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1036 "tx_packets",
1037 "rx_packets",
1038 "tx_errors",
1039 "rx_errors",
1040 "rx_missed",
1041 "align_errors",
1042 "tx_single_collisions",
1043 "tx_multi_collisions",
1044 "unicast",
1045 "broadcast",
1046 "multicast",
1047 "tx_aborted",
1048 "tx_underrun",
1049};
1050
1051struct rtl8169_counters {
1052 u64 tx_packets;
1053 u64 rx_packets;
1054 u64 tx_errors;
1055 u32 rx_errors;
1056 u16 rx_missed;
1057 u16 align_errors;
1058 u32 tx_one_collision;
1059 u32 tx_multi_collision;
1060 u64 rx_unicast;
1061 u64 rx_broadcast;
1062 u32 rx_multicast;
1063 u16 tx_aborted;
1064 u16 tx_underun;
1065};
1066
1067static int rtl8169_get_stats_count(struct net_device *dev)
1068{
1069 return ARRAY_SIZE(rtl8169_gstrings);
1070}
1071
1072static void rtl8169_get_ethtool_stats(struct net_device *dev,
1073 struct ethtool_stats *stats, u64 *data)
1074{
1075 struct rtl8169_private *tp = netdev_priv(dev);
1076 void __iomem *ioaddr = tp->mmio_addr;
1077 struct rtl8169_counters *counters;
1078 dma_addr_t paddr;
1079 u32 cmd;
1080
1081 ASSERT_RTNL();
1082
1083 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1084 if (!counters)
1085 return;
1086
1087 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1088 cmd = (u64)paddr & DMA_32BIT_MASK;
1089 RTL_W32(CounterAddrLow, cmd);
1090 RTL_W32(CounterAddrLow, cmd | CounterDump);
1091
1092 while (RTL_R32(CounterAddrLow) & CounterDump) {
1093 if (msleep_interruptible(1))
1094 break;
1095 }
1096
1097 RTL_W32(CounterAddrLow, 0);
1098 RTL_W32(CounterAddrHigh, 0);
1099
5b0384f4 1100 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1101 data[1] = le64_to_cpu(counters->rx_packets);
1102 data[2] = le64_to_cpu(counters->tx_errors);
1103 data[3] = le32_to_cpu(counters->rx_errors);
1104 data[4] = le16_to_cpu(counters->rx_missed);
1105 data[5] = le16_to_cpu(counters->align_errors);
1106 data[6] = le32_to_cpu(counters->tx_one_collision);
1107 data[7] = le32_to_cpu(counters->tx_multi_collision);
1108 data[8] = le64_to_cpu(counters->rx_unicast);
1109 data[9] = le64_to_cpu(counters->rx_broadcast);
1110 data[10] = le32_to_cpu(counters->rx_multicast);
1111 data[11] = le16_to_cpu(counters->tx_aborted);
1112 data[12] = le16_to_cpu(counters->tx_underun);
1113
1114 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1115}
1116
1117static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1118{
1119 switch(stringset) {
1120 case ETH_SS_STATS:
1121 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1122 break;
1123 }
1124}
1125
1126
7282d491 1127static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1128 .get_drvinfo = rtl8169_get_drvinfo,
1129 .get_regs_len = rtl8169_get_regs_len,
1130 .get_link = ethtool_op_get_link,
1131 .get_settings = rtl8169_get_settings,
1132 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1133 .get_msglevel = rtl8169_get_msglevel,
1134 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1135 .get_rx_csum = rtl8169_get_rx_csum,
1136 .set_rx_csum = rtl8169_set_rx_csum,
1137 .get_tx_csum = ethtool_op_get_tx_csum,
1138 .set_tx_csum = ethtool_op_set_tx_csum,
1139 .get_sg = ethtool_op_get_sg,
1140 .set_sg = ethtool_op_set_sg,
1141 .get_tso = ethtool_op_get_tso,
1142 .set_tso = ethtool_op_set_tso,
1143 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1144 .get_wol = rtl8169_get_wol,
1145 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1146 .get_strings = rtl8169_get_strings,
1147 .get_stats_count = rtl8169_get_stats_count,
1148 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1149 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1150};
1151
1152static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1153 int bitval)
1154{
1155 int val;
1156
1157 val = mdio_read(ioaddr, reg);
1158 val = (bitval == 1) ?
1159 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1160 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1161}
1162
1163static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1164{
1165 const struct {
1166 u32 mask;
1167 int mac_version;
1168 } mac_info[] = {
bcf0bf90
FR		 1169 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1170 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1171 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1172 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1173 { 0x30000000, RTL_GIGA_MAC_VER_11 },
bcf0bf90
FR		 1174 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1175 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1176 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1177 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1178 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1179 }, *p = mac_info;
1180 u32 reg;
1181
1182 reg = RTL_R32(TxConfig) & 0x7c800000;
1183 while ((reg & p->mask) != p->mask)
1184 p++;
1185 tp->mac_version = p->mac_version;
1186}
1187
1188static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1189{
bcf0bf90 1190 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1191}
1192
1193static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1194{
1195 const struct {
1196 u16 mask;
1197 u16 set;
1198 int phy_version;
1199 } phy_info[] = {
1200 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1201 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1202 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1203 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1204 }, *p = phy_info;
1205 u16 reg;
1206
64e4bfb4 1207 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1208 while ((reg & p->mask) != p->set)
1209 p++;
1210 tp->phy_version = p->phy_version;
1211}
1212
1213static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1214{
1215 struct {
1216 int version;
1217 char *msg;
1218 u32 reg;
1219 } phy_print[] = {
1220 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1221 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1222 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1223 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1224 { 0, NULL, 0x0000 }
1225 }, *p;
1226
1227 for (p = phy_print; p->msg; p++) {
1228 if (tp->phy_version == p->version) {
1229 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1230 return;
1231 }
1232 }
1233 dprintk("phy_version == Unknown\n");
1234}
1235
1236static void rtl8169_hw_phy_config(struct net_device *dev)
1237{
1238 struct rtl8169_private *tp = netdev_priv(dev);
1239 void __iomem *ioaddr = tp->mmio_addr;
1240 struct {
1241 u16 regs[5]; /* Beware of bit-sign propagation */
1242 } phy_magic[5] = { {
1243 { 0x0000, //w 4 15 12 0
1244 0x00a1, //w 3 15 0 00a1
1245 0x0008, //w 2 15 0 0008
1246 0x1020, //w 1 15 0 1020
1247 0x1000 } },{ //w 0 15 0 1000
1248 { 0x7000, //w 4 15 12 7
1249 0xff41, //w 3 15 0 ff41
1250 0xde60, //w 2 15 0 de60
1251 0x0140, //w 1 15 0 0140
1252 0x0077 } },{ //w 0 15 0 0077
1253 { 0xa000, //w 4 15 12 a
1254 0xdf01, //w 3 15 0 df01
1255 0xdf20, //w 2 15 0 df20
1256 0xff95, //w 1 15 0 ff95
1257 0xfa00 } },{ //w 0 15 0 fa00
1258 { 0xb000, //w 4 15 12 b
1259 0xff41, //w 3 15 0 ff41
1260 0xde20, //w 2 15 0 de20
1261 0x0140, //w 1 15 0 0140
1262 0x00bb } },{ //w 0 15 0 00bb
1263 { 0xf000, //w 4 15 12 f
1264 0xdf01, //w 3 15 0 df01
1265 0xdf20, //w 2 15 0 df20
1266 0xff95, //w 1 15 0 ff95
1267 0xbf00 } //w 0 15 0 bf00
1268 }
1269 }, *p = phy_magic;
1270 int i;
1271
1272 rtl8169_print_mac_version(tp);
1273 rtl8169_print_phy_version(tp);
1274
bcf0bf90 1275 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1276 return;
1277 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1278 return;
1279
1280 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1281 dprintk("Do final_reg2.cfg\n");
1282
1283 /* Shazam ! */
1284
bcf0bf90 1285 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1286 mdio_write(ioaddr, 31, 0x0001);
1287 mdio_write(ioaddr, 9, 0x273a);
1288 mdio_write(ioaddr, 14, 0x7bfb);
1289 mdio_write(ioaddr, 27, 0x841e);
1290
1291 mdio_write(ioaddr, 31, 0x0002);
1292 mdio_write(ioaddr, 1, 0x90d0);
1293 mdio_write(ioaddr, 31, 0x0000);
1294 return;
1295 }
1296
1297 /* phy config for RTL8169s mac_version C chip */
1298 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1299 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1300 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1301 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1302
1303 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1304 int val, pos = 4;
1305
1306 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1307 mdio_write(ioaddr, pos, val);
1308 while (--pos >= 0)
1309 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1310 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1311 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1312 }
1313 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1314}
1315
1316static void rtl8169_phy_timer(unsigned long __opaque)
1317{
1318 struct net_device *dev = (struct net_device *)__opaque;
1319 struct rtl8169_private *tp = netdev_priv(dev);
1320 struct timer_list *timer = &tp->timer;
1321 void __iomem *ioaddr = tp->mmio_addr;
1322 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1323
bcf0bf90 1324 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1325 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1326
64e4bfb4 1327 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1328 return;
1329
1330 spin_lock_irq(&tp->lock);
1331
1332 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1333 /*
1da177e4
LT		 1334 * A busy loop could burn quite a few cycles on nowadays CPU.
1335 * Let's delay the execution of the timer for a few ticks.
1336 */
1337 timeout = HZ/10;
1338 goto out_mod_timer;
1339 }
1340
1341 if (tp->link_ok(ioaddr))
1342 goto out_unlock;
1343
b57b7e5a
SH		 1344 if (netif_msg_link(tp))
1345 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1346
1347 tp->phy_reset_enable(ioaddr);
1348
1349out_mod_timer:
1350 mod_timer(timer, jiffies + timeout);
1351out_unlock:
1352 spin_unlock_irq(&tp->lock);
1353}
1354
1355static inline void rtl8169_delete_timer(struct net_device *dev)
1356{
1357 struct rtl8169_private *tp = netdev_priv(dev);
1358 struct timer_list *timer = &tp->timer;
1359
bcf0bf90 1360 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1361 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1362 return;
1363
1364 del_timer_sync(timer);
1365}
1366
1367static inline void rtl8169_request_timer(struct net_device *dev)
1368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 struct timer_list *timer = &tp->timer;
1371
bcf0bf90 1372 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1373 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1374 return;
1375
1376 init_timer(timer);
1377 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1378 timer->data = (unsigned long)(dev);
1379 timer->function = rtl8169_phy_timer;
1380 add_timer(timer);
1381}
1382
1383#ifdef CONFIG_NET_POLL_CONTROLLER
1384/*
1385 * Polling 'interrupt' - used by things like netconsole to send skbs
1386 * without having to re-enable interrupts. It's not called while
1387 * the interrupt routine is executing.
1388 */
1389static void rtl8169_netpoll(struct net_device *dev)
1390{
1391 struct rtl8169_private *tp = netdev_priv(dev);
1392 struct pci_dev *pdev = tp->pci_dev;
1393
1394 disable_irq(pdev->irq);
7d12e780 1395 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1396 enable_irq(pdev->irq);
1397}
1398#endif
1399
1400static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1401 void __iomem *ioaddr)
1402{
1403 iounmap(ioaddr);
1404 pci_release_regions(pdev);
1405 pci_disable_device(pdev);
1406 free_netdev(dev);
1407}
1408
bf793295
FR		 1409static void rtl8169_phy_reset(struct net_device *dev,
1410 struct rtl8169_private *tp)
1411{
1412 void __iomem *ioaddr = tp->mmio_addr;
1413 int i;
1414
1415 tp->phy_reset_enable(ioaddr);
1416 for (i = 0; i < 100; i++) {
1417 if (!tp->phy_reset_pending(ioaddr))
1418 return;
1419 msleep(1);
1420 }
1421 if (netif_msg_link(tp))
1422 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1423}
1424
4ff96fa6
FR		 1425static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1426{
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 static int board_idx = -1;
1429 u8 autoneg, duplex;
1430 u16 speed;
1431
1432 board_idx++;
1433
1434 rtl8169_hw_phy_config(dev);
1435
1436 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1437 RTL_W8(0x82, 0x01);
1438
bcf0bf90 1439 if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
4ff96fa6
FR		 1440 dprintk("Set PCI Latency=0x40\n");
1441 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1442 }
1443
bcf0bf90 1444 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1445 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1446 RTL_W8(0x82, 0x01);
1447 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1448 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1449 }
1450
1451 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1452
bf793295
FR		 1453 rtl8169_phy_reset(dev, tp);
1454
4ff96fa6
FR		 1455 rtl8169_set_speed(dev, autoneg, speed, duplex);
1456
1457 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1458 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1459}
1460
5f787a1a
FR		 1461static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1462{
1463 struct rtl8169_private *tp = netdev_priv(dev);
1464 struct mii_ioctl_data *data = if_mii(ifr);
1465
1466 if (!netif_running(dev))
1467 return -ENODEV;
1468
1469 switch (cmd) {
1470 case SIOCGMIIPHY:
1471 data->phy_id = 32; /* Internal PHY */
1472 return 0;
1473
1474 case SIOCGMIIREG:
1475 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1476 return 0;
1477
1478 case SIOCSMIIREG:
1479 if (!capable(CAP_NET_ADMIN))
1480 return -EPERM;
1481 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1482 return 0;
1483 }
1484 return -EOPNOTSUPP;
1485}
1486
1da177e4 1487static int __devinit
4ff96fa6 1488rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1489{
bcf0bf90 1490 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1da177e4 1491 struct rtl8169_private *tp;
4ff96fa6
FR		 1492 struct net_device *dev;
1493 void __iomem *ioaddr;
315917d2
FR		 1494 unsigned int pm_cap;
1495 int i, rc;
1da177e4 1496
4ff96fa6
FR		 1497 if (netif_msg_drv(&debug)) {
1498 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1499 MODULENAME, RTL8169_VERSION);
1500 }
1da177e4 1501
1da177e4 1502 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1503 if (!dev) {
b57b7e5a 1504 if (netif_msg_drv(&debug))
9b91cf9d 1505 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1506 rc = -ENOMEM;
1507 goto out;
1da177e4
LT		 1508 }
1509
1510 SET_MODULE_OWNER(dev);
1511 SET_NETDEV_DEV(dev, &pdev->dev);
1512 tp = netdev_priv(dev);
b57b7e5a 1513 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1514
1515 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1516 rc = pci_enable_device(pdev);
b57b7e5a 1517 if (rc < 0) {
2e8a538d 1518 if (netif_msg_probe(tp))
9b91cf9d 1519 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1520 goto err_out_free_dev_1;
1da177e4
LT		 1521 }
1522
1523 rc = pci_set_mwi(pdev);
1524 if (rc < 0)
4ff96fa6 1525 goto err_out_disable_2;
1da177e4
LT		 1526
1527 /* save power state before pci_enable_device overwrites it */
1528 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1529 if (pm_cap) {
4ff96fa6 1530 u16 pwr_command, acpi_idle_state;
1da177e4
LT		 1531
1532 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1533 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1534 } else {
4ff96fa6 1535 if (netif_msg_probe(tp)) {
9b91cf9d 1536 dev_err(&pdev->dev,
4ff96fa6
FR		 1537 "PowerManagement capability not found.\n");
1538 }
1da177e4
LT		 1539 }
1540
1541 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1542 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1543 if (netif_msg_probe(tp)) {
9b91cf9d 1544 dev_err(&pdev->dev,
bcf0bf90
FR		 1545 "region #%d not an MMIO resource, aborting\n",
1546 region);
4ff96fa6 1547 }
1da177e4 1548 rc = -ENODEV;
4ff96fa6 1549 goto err_out_mwi_3;
1da177e4 1550 }
4ff96fa6 1551
1da177e4 1552 /* check for weird/broken PCI region reporting */
bcf0bf90 1553 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1554 if (netif_msg_probe(tp)) {
9b91cf9d 1555 dev_err(&pdev->dev,
4ff96fa6
FR		 1556 "Invalid PCI region size(s), aborting\n");
1557 }
1da177e4 1558 rc = -ENODEV;
4ff96fa6 1559 goto err_out_mwi_3;
1da177e4
LT		 1560 }
1561
1562 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1563 if (rc < 0) {
2e8a538d 1564 if (netif_msg_probe(tp))
9b91cf9d 1565 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1566 goto err_out_mwi_3;
1da177e4
LT		 1567 }
1568
1569 tp->cp_cmd = PCIMulRW | RxChkSum;
1570
1571 if ((sizeof(dma_addr_t) > 4) &&
1572 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1573 tp->cp_cmd |= PCIDAC;
1574 dev->features |= NETIF_F_HIGHDMA;
1575 } else {
1576 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1577 if (rc < 0) {
4ff96fa6 1578 if (netif_msg_probe(tp)) {
9b91cf9d 1579 dev_err(&pdev->dev,
4ff96fa6
FR		 1580 "DMA configuration failed.\n");
1581 }
1582 goto err_out_free_res_4;
1da177e4
LT		 1583 }
1584 }
1585
1586 pci_set_master(pdev);
1587
1588 /* ioremap MMIO region */
bcf0bf90 1589 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1590 if (!ioaddr) {
b57b7e5a 1591 if (netif_msg_probe(tp))
9b91cf9d 1592 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1593 rc = -EIO;
4ff96fa6 1594 goto err_out_free_res_4;
1da177e4
LT		 1595 }
1596
1597 /* Unneeded ? Don't mess with Mrs. Murphy. */
1598 rtl8169_irq_mask_and_ack(ioaddr);
1599
1600 /* Soft reset the chip. */
1601 RTL_W8(ChipCmd, CmdReset);
1602
1603 /* Check that the chip has finished the reset. */
b518fa8e 1604 for (i = 100; i > 0; i--) {
1da177e4
LT		 1605 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1606 break;
b518fa8e 1607 msleep_interruptible(1);
1da177e4
LT		 1608 }
1609
1610 /* Identify chip attached to board */
1611 rtl8169_get_mac_version(tp, ioaddr);
1612 rtl8169_get_phy_version(tp, ioaddr);
1613
1614 rtl8169_print_mac_version(tp);
1615 rtl8169_print_phy_version(tp);
1616
1617 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1618 if (tp->mac_version == rtl_chip_info[i].mac_version)
1619 break;
1620 }
1621 if (i < 0) {
1622 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1623 if (netif_msg_probe(tp)) {
2e8a538d 1624 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1625 "unknown chip version, assuming %s\n",
1626 rtl_chip_info[0].name);
b57b7e5a 1627 }
1da177e4
LT		 1628 i++;
1629 }
1630 tp->chipset = i;
1631
5d06a99f
FR		 1632 RTL_W8(Cfg9346, Cfg9346_Unlock);
1633 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1634 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1635 RTL_W8(Cfg9346, Cfg9346_Lock);
1636
1da177e4
LT		 1637 if (RTL_R8(PHYstatus) & TBI_Enable) {
1638 tp->set_speed = rtl8169_set_speed_tbi;
1639 tp->get_settings = rtl8169_gset_tbi;
1640 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1641 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1642 tp->link_ok = rtl8169_tbi_link_ok;
1643
64e4bfb4 1644 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1645 } else {
1646 tp->set_speed = rtl8169_set_speed_xmii;
1647 tp->get_settings = rtl8169_gset_xmii;
1648 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1649 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1650 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1651
1652 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1653 }
1654
1655 /* Get MAC address. FIXME: read EEPROM */
1656 for (i = 0; i < MAC_ADDR_LEN; i++)
1657 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1658 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1659
1660 dev->open = rtl8169_open;
1661 dev->hard_start_xmit = rtl8169_start_xmit;
1662 dev->get_stats = rtl8169_get_stats;
1663 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1664 dev->stop = rtl8169_close;
1665 dev->tx_timeout = rtl8169_tx_timeout;
1666 dev->set_multicast_list = rtl8169_set_rx_mode;
1667 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1668 dev->irq = pdev->irq;
1669 dev->base_addr = (unsigned long) ioaddr;
1670 dev->change_mtu = rtl8169_change_mtu;
1671
1672#ifdef CONFIG_R8169_NAPI
1673 dev->poll = rtl8169_poll;
1674 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1675#endif
1676
1677#ifdef CONFIG_R8169_VLAN
1678 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1679 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1680 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1681#endif
1682
1683#ifdef CONFIG_NET_POLL_CONTROLLER
1684 dev->poll_controller = rtl8169_netpoll;
1685#endif
1686
1687 tp->intr_mask = 0xffff;
1688 tp->pci_dev = pdev;
1689 tp->mmio_addr = ioaddr;
bcf0bf90 1690 tp->align = rtl_cfg_info[ent->driver_data].align;
1da177e4
LT		 1691
1692 spin_lock_init(&tp->lock);
1693
1694 rc = register_netdev(dev);
4ff96fa6
FR		 1695 if (rc < 0)
1696 goto err_out_unmap_5;
1da177e4
LT		 1697
1698 pci_set_drvdata(pdev, dev);
1699
b57b7e5a
SH		 1700 if (netif_msg_probe(tp)) {
1701 printk(KERN_INFO "%s: %s at 0x%lx, "
1702 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1703 "IRQ %d\n",
1704 dev->name,
bcf0bf90 1705 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1706 dev->base_addr,
1707 dev->dev_addr[0], dev->dev_addr[1],
1708 dev->dev_addr[2], dev->dev_addr[3],
1709 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1710 }
1da177e4 1711
4ff96fa6 1712 rtl8169_init_phy(dev, tp);
1da177e4 1713
4ff96fa6
FR		 1714out:
1715 return rc;
1da177e4 1716
4ff96fa6
FR		 1717err_out_unmap_5:
1718 iounmap(ioaddr);
1719err_out_free_res_4:
1720 pci_release_regions(pdev);
1721err_out_mwi_3:
1722 pci_clear_mwi(pdev);
1723err_out_disable_2:
1724 pci_disable_device(pdev);
1725err_out_free_dev_1:
1726 free_netdev(dev);
1727 goto out;
1da177e4
LT		 1728}
1729
1730static void __devexit
1731rtl8169_remove_one(struct pci_dev *pdev)
1732{
1733 struct net_device *dev = pci_get_drvdata(pdev);
1734 struct rtl8169_private *tp = netdev_priv(dev);
1735
1736 assert(dev != NULL);
1737 assert(tp != NULL);
1738
1739 unregister_netdev(dev);
1740 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1741 pci_set_drvdata(pdev, NULL);
1742}
1743
1da177e4
LT		 1744static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1745 struct net_device *dev)
1746{
1747 unsigned int mtu = dev->mtu;
1748
1749 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1750}
1751
1752static int rtl8169_open(struct net_device *dev)
1753{
1754 struct rtl8169_private *tp = netdev_priv(dev);
1755 struct pci_dev *pdev = tp->pci_dev;
1756 int retval;
1757
1758 rtl8169_set_rxbufsize(tp, dev);
1759
1760 retval =
1fb9df5d 1761 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1762 if (retval < 0)
1763 goto out;
1764
1765 retval = -ENOMEM;
1766
1767 /*
1768 * Rx and Tx desscriptors needs 256 bytes alignment.
1769 * pci_alloc_consistent provides more.
1770 */
1771 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1772 &tp->TxPhyAddr);
1773 if (!tp->TxDescArray)
1774 goto err_free_irq;
1775
1776 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1777 &tp->RxPhyAddr);
1778 if (!tp->RxDescArray)
1779 goto err_free_tx;
1780
1781 retval = rtl8169_init_ring(dev);
1782 if (retval < 0)
1783 goto err_free_rx;
1784
1785 INIT_WORK(&tp->task, NULL, dev);
1786
1787 rtl8169_hw_start(dev);
1788
1789 rtl8169_request_timer(dev);
1790
1791 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1792out:
1793 return retval;
1794
1795err_free_rx:
1796 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1797 tp->RxPhyAddr);
1798err_free_tx:
1799 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1800 tp->TxPhyAddr);
1801err_free_irq:
1802 free_irq(dev->irq, dev);
1803 goto out;
1804}
1805
1806static void rtl8169_hw_reset(void __iomem *ioaddr)
1807{
1808 /* Disable interrupts */
1809 rtl8169_irq_mask_and_ack(ioaddr);
1810
1811 /* Reset the chipset */
1812 RTL_W8(ChipCmd, CmdReset);
1813
1814 /* PCI commit */
1815 RTL_R8(ChipCmd);
1816}
1817
9cb427b6
FR		 1818static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
1819{
1820 void __iomem *ioaddr = tp->mmio_addr;
1821 u32 cfg = rtl8169_rx_config;
1822
1823 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1824 RTL_W32(RxConfig, cfg);
1825
1826 /* Set DMA burst size and Interframe Gap Time */
1827 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1828 (InterFrameGap << TxInterFrameGapShift));
1829}
1830
1831static void rtl8169_hw_start(struct net_device *dev)
1da177e4
LT		 1832{
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 void __iomem *ioaddr = tp->mmio_addr;
bcf0bf90 1835 struct pci_dev *pdev = tp->pci_dev;
9cb427b6 1836 u16 cmd;
1da177e4
LT		 1837 u32 i;
1838
1839 /* Soft reset the chip. */
1840 RTL_W8(ChipCmd, CmdReset);
1841
1842 /* Check that the chip has finished the reset. */
b518fa8e 1843 for (i = 100; i > 0; i--) {
1da177e4
LT		 1844 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1845 break;
b518fa8e 1846 msleep_interruptible(1);
1da177e4
LT		 1847 }
1848
9cb427b6
FR		 1849 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1850 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1851 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1852 }
1853
bcf0bf90
FR		 1854 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1855 pci_write_config_word(pdev, 0x68, 0x00);
1856 pci_write_config_word(pdev, 0x69, 0x08);
1857 }
1858
1859 /* Undocumented stuff. */
1860 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
bcf0bf90
FR		 1861 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1862 if ((RTL_R8(Config2) & 0x07) & 0x01)
1863 RTL_W32(0x7c, 0x0007ffff);
1864
1865 RTL_W32(0x7c, 0x0007ff00);
1866
1867 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1868 cmd = cmd & 0xef;
1869 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1da177e4
LT		 1870 }
1871
1872 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1873 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1874 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1876 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1877 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1878
1da177e4
LT		 1879 RTL_W8(EarlyTxThres, EarlyTxThld);
1880
126fa4b9
FR		 1881 /* Low hurts. Let's disable the filtering. */
1882 RTL_W16(RxMaxSize, 16383);
1da177e4 1883
9cb427b6
FR		 1884 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1885 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1886 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1887 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1888 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1889 rtl8169_set_rx_tx_config_registers(tp);
1da177e4 1890
9cb427b6
FR		 1891 cmd = RTL_R16(CPlusCmd);
1892 RTL_W16(CPlusCmd, cmd);
1da177e4 1893
9cb427b6 1894 tp->cp_cmd |= cmd | PCIMulRW;
1da177e4 1895
bcf0bf90
FR		 1896 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1897 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1898 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1899 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1900 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1901 }
1902
bcf0bf90
FR		 1903 RTL_W16(CPlusCmd, tp->cp_cmd);
1904
1da177e4
LT		 1905 /*
1906 * Undocumented corner. Supposedly:
1907 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1908 */
1909 RTL_W16(IntrMitigate, 0x0000);
1910
b39fe41f
FR		 1911 /*
1912 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1913 * register to be written before TxDescAddrLow to work.
1914 * Switching from MMIO to I/O access fixes the issue as well.
1915 */
1da177e4 1916 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
b39fe41f 1917 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1da177e4 1918 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
b39fe41f 1919 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
9cb427b6
FR		 1920
1921 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1922 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1923 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1924 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1925 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1926 rtl8169_set_rx_tx_config_registers(tp);
1927 }
1928
1da177e4 1929 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1930
1931 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1932 RTL_R8(IntrMask);
1da177e4
LT		 1933
1934 RTL_W32(RxMissed, 0);
1935
1936 rtl8169_set_rx_mode(dev);
1937
1938 /* no early-rx interrupts */
1939 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1940
1941 /* Enable all known interrupts by setting the interrupt mask. */
1942 RTL_W16(IntrMask, rtl8169_intr_mask);
1943
1944 netif_start_queue(dev);
1945}
1946
1947static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1948{
1949 struct rtl8169_private *tp = netdev_priv(dev);
1950 int ret = 0;
1951
1952 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1953 return -EINVAL;
1954
1955 dev->mtu = new_mtu;
1956
1957 if (!netif_running(dev))
1958 goto out;
1959
1960 rtl8169_down(dev);
1961
1962 rtl8169_set_rxbufsize(tp, dev);
1963
1964 ret = rtl8169_init_ring(dev);
1965 if (ret < 0)
1966 goto out;
1967
1968 netif_poll_enable(dev);
1969
1970 rtl8169_hw_start(dev);
1971
1972 rtl8169_request_timer(dev);
1973
1974out:
1975 return ret;
1976}
1977
1978static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1979{
1980 desc->addr = 0x0badbadbadbadbadull;
1981 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1982}
1983
1984static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1985 struct sk_buff **sk_buff, struct RxDesc *desc)
1986{
1987 struct pci_dev *pdev = tp->pci_dev;
1988
1989 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1990 PCI_DMA_FROMDEVICE);
1991 dev_kfree_skb(*sk_buff);
1992 *sk_buff = NULL;
1993 rtl8169_make_unusable_by_asic(desc);
1994}
1995
1996static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1997{
1998 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1999
2000 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2001}
2002
2003static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2004 u32 rx_buf_sz)
2005{
2006 desc->addr = cpu_to_le64(mapping);
2007 wmb();
2008 rtl8169_mark_to_asic(desc, rx_buf_sz);
2009}
2010
2011static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
bcf0bf90
FR		 2012 struct RxDesc *desc, int rx_buf_sz,
2013 unsigned int align)
1da177e4
LT		 2014{
2015 struct sk_buff *skb;
2016 dma_addr_t mapping;
2017 int ret = 0;
2018
bcf0bf90 2019 skb = dev_alloc_skb(rx_buf_sz + align);
1da177e4
LT		 2020 if (!skb)
2021 goto err_out;
2022
bcf0bf90 2023 skb_reserve(skb, align);
1da177e4
LT		 2024 *sk_buff = skb;
2025
689be439 2026 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2027 PCI_DMA_FROMDEVICE);
2028
2029 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2030
2031out:
2032 return ret;
2033
2034err_out:
2035 ret = -ENOMEM;
2036 rtl8169_make_unusable_by_asic(desc);
2037 goto out;
2038}
2039
2040static void rtl8169_rx_clear(struct rtl8169_private *tp)
2041{
2042 int i;
2043
2044 for (i = 0; i < NUM_RX_DESC; i++) {
2045 if (tp->Rx_skbuff[i]) {
2046 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2047 tp->RxDescArray + i);
2048 }
2049 }
2050}
2051
2052static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2053 u32 start, u32 end)
2054{
2055 u32 cur;
5b0384f4 2056
1da177e4
LT		 2057 for (cur = start; end - cur > 0; cur++) {
2058 int ret, i = cur % NUM_RX_DESC;
2059
2060 if (tp->Rx_skbuff[i])
2061 continue;
bcf0bf90 2062
1da177e4 2063 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
bcf0bf90 2064 tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
1da177e4
LT		 2065 if (ret < 0)
2066 break;
2067 }
2068 return cur - start;
2069}
2070
2071static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2072{
2073 desc->opts1 |= cpu_to_le32(RingEnd);
2074}
2075
2076static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2077{
2078 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2079}
2080
2081static int rtl8169_init_ring(struct net_device *dev)
2082{
2083 struct rtl8169_private *tp = netdev_priv(dev);
2084
2085 rtl8169_init_ring_indexes(tp);
2086
2087 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2088 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2089
2090 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2091 goto err_out;
2092
2093 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2094
2095 return 0;
2096
2097err_out:
2098 rtl8169_rx_clear(tp);
2099 return -ENOMEM;
2100}
2101
2102static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2103 struct TxDesc *desc)
2104{
2105 unsigned int len = tx_skb->len;
2106
2107 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2108 desc->opts1 = 0x00;
2109 desc->opts2 = 0x00;
2110 desc->addr = 0x00;
2111 tx_skb->len = 0;
2112}
2113
2114static void rtl8169_tx_clear(struct rtl8169_private *tp)
2115{
2116 unsigned int i;
2117
2118 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2119 unsigned int entry = i % NUM_TX_DESC;
2120 struct ring_info *tx_skb = tp->tx_skb + entry;
2121 unsigned int len = tx_skb->len;
2122
2123 if (len) {
2124 struct sk_buff *skb = tx_skb->skb;
2125
2126 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2127 tp->TxDescArray + entry);
2128 if (skb) {
2129 dev_kfree_skb(skb);
2130 tx_skb->skb = NULL;
2131 }
2132 tp->stats.tx_dropped++;
2133 }
2134 }
2135 tp->cur_tx = tp->dirty_tx = 0;
2136}
2137
2138static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2139{
2140 struct rtl8169_private *tp = netdev_priv(dev);
2141
2142 PREPARE_WORK(&tp->task, task, dev);
2143 schedule_delayed_work(&tp->task, 4);
2144}
2145
2146static void rtl8169_wait_for_quiescence(struct net_device *dev)
2147{
2148 struct rtl8169_private *tp = netdev_priv(dev);
2149 void __iomem *ioaddr = tp->mmio_addr;
2150
2151 synchronize_irq(dev->irq);
2152
2153 /* Wait for any pending NAPI task to complete */
2154 netif_poll_disable(dev);
2155
2156 rtl8169_irq_mask_and_ack(ioaddr);
2157
2158 netif_poll_enable(dev);
2159}
2160
2161static void rtl8169_reinit_task(void *_data)
2162{
2163 struct net_device *dev = _data;
2164 int ret;
2165
2166 if (netif_running(dev)) {
2167 rtl8169_wait_for_quiescence(dev);
2168 rtl8169_close(dev);
2169 }
2170
2171 ret = rtl8169_open(dev);
2172 if (unlikely(ret < 0)) {
2173 if (net_ratelimit()) {
b57b7e5a
SH		 2174 struct rtl8169_private *tp = netdev_priv(dev);
2175
2176 if (netif_msg_drv(tp)) {
2177 printk(PFX KERN_ERR
2178 "%s: reinit failure (status = %d)."
2179 " Rescheduling.\n", dev->name, ret);
2180 }
1da177e4
LT		 2181 }
2182 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2183 }
2184}
2185
2186static void rtl8169_reset_task(void *_data)
2187{
2188 struct net_device *dev = _data;
2189 struct rtl8169_private *tp = netdev_priv(dev);
2190
2191 if (!netif_running(dev))
2192 return;
2193
2194 rtl8169_wait_for_quiescence(dev);
2195
2196 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2197 rtl8169_tx_clear(tp);
2198
2199 if (tp->dirty_rx == tp->cur_rx) {
2200 rtl8169_init_ring_indexes(tp);
2201 rtl8169_hw_start(dev);
2202 netif_wake_queue(dev);
2203 } else {
2204 if (net_ratelimit()) {
b57b7e5a
SH		 2205 struct rtl8169_private *tp = netdev_priv(dev);
2206
2207 if (netif_msg_intr(tp)) {
2208 printk(PFX KERN_EMERG
2209 "%s: Rx buffers shortage\n", dev->name);
2210 }
1da177e4
LT		 2211 }
2212 rtl8169_schedule_work(dev, rtl8169_reset_task);
2213 }
2214}
2215
2216static void rtl8169_tx_timeout(struct net_device *dev)
2217{
2218 struct rtl8169_private *tp = netdev_priv(dev);
2219
2220 rtl8169_hw_reset(tp->mmio_addr);
2221
2222 /* Let's wait a bit while any (async) irq lands on */
2223 rtl8169_schedule_work(dev, rtl8169_reset_task);
2224}
2225
2226static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2227 u32 opts1)
2228{
2229 struct skb_shared_info *info = skb_shinfo(skb);
2230 unsigned int cur_frag, entry;
2231 struct TxDesc *txd;
2232
2233 entry = tp->cur_tx;
2234 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2235 skb_frag_t *frag = info->frags + cur_frag;
2236 dma_addr_t mapping;
2237 u32 status, len;
2238 void *addr;
2239
2240 entry = (entry + 1) % NUM_TX_DESC;
2241
2242 txd = tp->TxDescArray + entry;
2243 len = frag->size;
2244 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2245 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2246
2247 /* anti gcc 2.95.3 bugware (sic) */
2248 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2249
2250 txd->opts1 = cpu_to_le32(status);
2251 txd->addr = cpu_to_le64(mapping);
2252
2253 tp->tx_skb[entry].len = len;
2254 }
2255
2256 if (cur_frag) {
2257 tp->tx_skb[entry].skb = skb;
2258 txd->opts1 |= cpu_to_le32(LastFrag);
2259 }
2260
2261 return cur_frag;
2262}
2263
2264static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2265{
2266 if (dev->features & NETIF_F_TSO) {
7967168c 2267 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2268
2269 if (mss)
2270 return LargeSend | ((mss & MSSMask) << MSSShift);
2271 }
84fa7933 2272 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 2273 const struct iphdr *ip = skb->nh.iph;
2274
2275 if (ip->protocol == IPPROTO_TCP)
2276 return IPCS | TCPCS;
2277 else if (ip->protocol == IPPROTO_UDP)
2278 return IPCS | UDPCS;
2279 WARN_ON(1); /* we need a WARN() */
2280 }
2281 return 0;
2282}
2283
2284static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2285{
2286 struct rtl8169_private *tp = netdev_priv(dev);
2287 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2288 struct TxDesc *txd = tp->TxDescArray + entry;
2289 void __iomem *ioaddr = tp->mmio_addr;
2290 dma_addr_t mapping;
2291 u32 status, len;
2292 u32 opts1;
188f4af0 2293 int ret = NETDEV_TX_OK;
5b0384f4 2294
1da177e4 2295 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2296 if (netif_msg_drv(tp)) {
2297 printk(KERN_ERR
2298 "%s: BUG! Tx Ring full when queue awake!\n",
2299 dev->name);
2300 }
1da177e4
LT		 2301 goto err_stop;
2302 }
2303
2304 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2305 goto err_stop;
2306
2307 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2308
2309 frags = rtl8169_xmit_frags(tp, skb, opts1);
2310 if (frags) {
2311 len = skb_headlen(skb);
2312 opts1 |= FirstFrag;
2313 } else {
2314 len = skb->len;
2315
2316 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2317 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2318 goto err_update_stats;
2319 len = ETH_ZLEN;
2320 }
2321
2322 opts1 |= FirstFrag | LastFrag;
2323 tp->tx_skb[entry].skb = skb;
2324 }
2325
2326 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2327
2328 tp->tx_skb[entry].len = len;
2329 txd->addr = cpu_to_le64(mapping);
2330 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2331
2332 wmb();
2333
2334 /* anti gcc 2.95.3 bugware (sic) */
2335 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2336 txd->opts1 = cpu_to_le32(status);
2337
2338 dev->trans_start = jiffies;
2339
2340 tp->cur_tx += frags + 1;
2341
2342 smp_wmb();
2343
2344 RTL_W8(TxPoll, 0x40); /* set polling bit */
2345
2346 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2347 netif_stop_queue(dev);
2348 smp_rmb();
2349 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2350 netif_wake_queue(dev);
2351 }
2352
2353out:
2354 return ret;
2355
2356err_stop:
2357 netif_stop_queue(dev);
188f4af0 2358 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2359err_update_stats:
2360 tp->stats.tx_dropped++;
2361 goto out;
2362}
2363
2364static void rtl8169_pcierr_interrupt(struct net_device *dev)
2365{
2366 struct rtl8169_private *tp = netdev_priv(dev);
2367 struct pci_dev *pdev = tp->pci_dev;
2368 void __iomem *ioaddr = tp->mmio_addr;
2369 u16 pci_status, pci_cmd;
2370
2371 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2372 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2373
b57b7e5a
SH		 2374 if (netif_msg_intr(tp)) {
2375 printk(KERN_ERR
2376 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2377 dev->name, pci_cmd, pci_status);
2378 }
1da177e4
LT		 2379
2380 /*
2381 * The recovery sequence below admits a very elaborated explanation:
2382 * - it seems to work;
2383 * - I did not see what else could be done.
2384 *
2385 * Feel free to adjust to your needs.
2386 */
2387 pci_write_config_word(pdev, PCI_COMMAND,
2388 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2389
2390 pci_write_config_word(pdev, PCI_STATUS,
2391 pci_status & (PCI_STATUS_DETECTED_PARITY |
2392 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2393 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2394
2395 /* The infamous DAC f*ckup only happens at boot time */
2396 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2397 if (netif_msg_intr(tp))
2398 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2399 tp->cp_cmd &= ~PCIDAC;
2400 RTL_W16(CPlusCmd, tp->cp_cmd);
2401 dev->features &= ~NETIF_F_HIGHDMA;
2402 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2403 }
2404
2405 rtl8169_hw_reset(ioaddr);
2406}
2407
2408static void
2409rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2410 void __iomem *ioaddr)
2411{
2412 unsigned int dirty_tx, tx_left;
2413
2414 assert(dev != NULL);
2415 assert(tp != NULL);
2416 assert(ioaddr != NULL);
2417
2418 dirty_tx = tp->dirty_tx;
2419 smp_rmb();
2420 tx_left = tp->cur_tx - dirty_tx;
2421
2422 while (tx_left > 0) {
2423 unsigned int entry = dirty_tx % NUM_TX_DESC;
2424 struct ring_info *tx_skb = tp->tx_skb + entry;
2425 u32 len = tx_skb->len;
2426 u32 status;
2427
2428 rmb();
2429 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2430 if (status & DescOwn)
2431 break;
2432
2433 tp->stats.tx_bytes += len;
2434 tp->stats.tx_packets++;
2435
2436 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2437
2438 if (status & LastFrag) {
2439 dev_kfree_skb_irq(tx_skb->skb);
2440 tx_skb->skb = NULL;
2441 }
2442 dirty_tx++;
2443 tx_left--;
2444 }
2445
2446 if (tp->dirty_tx != dirty_tx) {
2447 tp->dirty_tx = dirty_tx;
2448 smp_wmb();
2449 if (netif_queue_stopped(dev) &&
2450 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2451 netif_wake_queue(dev);
2452 }
2453 }
2454}
2455
126fa4b9
FR		 2456static inline int rtl8169_fragmented_frame(u32 status)
2457{
2458 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2459}
2460
1da177e4
LT		 2461static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2462{
2463 u32 opts1 = le32_to_cpu(desc->opts1);
2464 u32 status = opts1 & RxProtoMask;
2465
2466 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2467 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2468 ((status == RxProtoIP) && !(opts1 & IPFail)))
2469 skb->ip_summed = CHECKSUM_UNNECESSARY;
2470 else
2471 skb->ip_summed = CHECKSUM_NONE;
2472}
2473
2474static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
bcf0bf90
FR		 2475 struct RxDesc *desc, int rx_buf_sz,
2476 unsigned int align)
1da177e4
LT		 2477{
2478 int ret = -1;
2479
2480 if (pkt_size < rx_copybreak) {
2481 struct sk_buff *skb;
2482
bcf0bf90 2483 skb = dev_alloc_skb(pkt_size + align);
1da177e4 2484 if (skb) {
bcf0bf90 2485 skb_reserve(skb, align);
689be439 2486 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2487 *sk_buff = skb;
2488 rtl8169_mark_to_asic(desc, rx_buf_sz);
2489 ret = 0;
2490 }
2491 }
2492 return ret;
2493}
2494
2495static int
2496rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2497 void __iomem *ioaddr)
2498{
2499 unsigned int cur_rx, rx_left;
2500 unsigned int delta, count;
2501
2502 assert(dev != NULL);
2503 assert(tp != NULL);
2504 assert(ioaddr != NULL);
2505
2506 cur_rx = tp->cur_rx;
2507 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2508 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2509
4dcb7d33 2510 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2511 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2512 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2513 u32 status;
2514
2515 rmb();
126fa4b9 2516 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2517
2518 if (status & DescOwn)
2519 break;
4dcb7d33 2520 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2521 if (netif_msg_rx_err(tp)) {
2522 printk(KERN_INFO
2523 "%s: Rx ERROR. status = %08x\n",
2524 dev->name, status);
2525 }
1da177e4
LT		 2526 tp->stats.rx_errors++;
2527 if (status & (RxRWT | RxRUNT))
2528 tp->stats.rx_length_errors++;
2529 if (status & RxCRC)
2530 tp->stats.rx_crc_errors++;
9dccf611
FR		 2531 if (status & RxFOVF) {
2532 rtl8169_schedule_work(dev, rtl8169_reset_task);
2533 tp->stats.rx_fifo_errors++;
2534 }
126fa4b9 2535 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2536 } else {
1da177e4
LT		 2537 struct sk_buff *skb = tp->Rx_skbuff[entry];
2538 int pkt_size = (status & 0x00001FFF) - 4;
2539 void (*pci_action)(struct pci_dev *, dma_addr_t,
2540 size_t, int) = pci_dma_sync_single_for_device;
2541
126fa4b9
FR		 2542 /*
2543 * The driver does not support incoming fragmented
2544 * frames. They are seen as a symptom of over-mtu
2545 * sized frames.
2546 */
2547 if (unlikely(rtl8169_fragmented_frame(status))) {
2548 tp->stats.rx_dropped++;
2549 tp->stats.rx_length_errors++;
2550 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2551 continue;
126fa4b9
FR		 2552 }
2553
1da177e4 2554 rtl8169_rx_csum(skb, desc);
bcf0bf90 2555
1da177e4
LT		 2556 pci_dma_sync_single_for_cpu(tp->pci_dev,
2557 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2558 PCI_DMA_FROMDEVICE);
2559
2560 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
bcf0bf90 2561 tp->rx_buf_sz, tp->align)) {
1da177e4
LT		 2562 pci_action = pci_unmap_single;
2563 tp->Rx_skbuff[entry] = NULL;
2564 }
2565
2566 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2567 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2568
2569 skb->dev = dev;
2570 skb_put(skb, pkt_size);
2571 skb->protocol = eth_type_trans(skb, dev);
2572
2573 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2574 rtl8169_rx_skb(skb);
2575
2576 dev->last_rx = jiffies;
2577 tp->stats.rx_bytes += pkt_size;
2578 tp->stats.rx_packets++;
2579 }
1da177e4
LT		 2580 }
2581
2582 count = cur_rx - tp->cur_rx;
2583 tp->cur_rx = cur_rx;
2584
2585 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2586 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2587 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2588 tp->dirty_rx += delta;
2589
2590 /*
2591 * FIXME: until there is periodic timer to try and refill the ring,
2592 * a temporary shortage may definitely kill the Rx process.
2593 * - disable the asic to try and avoid an overflow and kick it again
2594 * after refill ?
2595 * - how do others driver handle this condition (Uh oh...).
2596 */
b57b7e5a 2597 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2598 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2599
2600 return count;
2601}
2602
2603/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2604static irqreturn_t
7d12e780 2605rtl8169_interrupt(int irq, void *dev_instance)
1da177e4
LT		 2606{
2607 struct net_device *dev = (struct net_device *) dev_instance;
2608 struct rtl8169_private *tp = netdev_priv(dev);
2609 int boguscnt = max_interrupt_work;
2610 void __iomem *ioaddr = tp->mmio_addr;
2611 int status;
2612 int handled = 0;
2613
2614 do {
2615 status = RTL_R16(IntrStatus);
2616
2617 /* hotplug/major error/no more work/shared irq */
2618 if ((status == 0xFFFF) || !status)
2619 break;
2620
2621 handled = 1;
2622
2623 if (unlikely(!netif_running(dev))) {
2624 rtl8169_asic_down(ioaddr);
2625 goto out;
2626 }
2627
2628 status &= tp->intr_mask;
2629 RTL_W16(IntrStatus,
2630 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2631
2632 if (!(status & rtl8169_intr_mask))
2633 break;
2634
2635 if (unlikely(status & SYSErr)) {
2636 rtl8169_pcierr_interrupt(dev);
2637 break;
2638 }
2639
2640 if (status & LinkChg)
2641 rtl8169_check_link_status(dev, tp, ioaddr);
2642
2643#ifdef CONFIG_R8169_NAPI
2644 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2645 tp->intr_mask = ~rtl8169_napi_event;
2646
2647 if (likely(netif_rx_schedule_prep(dev)))
2648 __netif_rx_schedule(dev);
b57b7e5a 2649 else if (netif_msg_intr(tp)) {
1da177e4 2650 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2651 dev->name, status);
1da177e4
LT		 2652 }
2653 break;
2654#else
2655 /* Rx interrupt */
2656 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2657 rtl8169_rx_interrupt(dev, tp, ioaddr);
2658 }
2659 /* Tx interrupt */
2660 if (status & (TxOK | TxErr))
2661 rtl8169_tx_interrupt(dev, tp, ioaddr);
2662#endif
2663
2664 boguscnt--;
2665 } while (boguscnt > 0);
2666
2667 if (boguscnt <= 0) {
7c8b2eb4 2668 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2669 printk(KERN_WARNING
2670 "%s: Too much work at interrupt!\n", dev->name);
2671 }
1da177e4
LT		 2672 /* Clear all interrupt sources. */
2673 RTL_W16(IntrStatus, 0xffff);
2674 }
2675out:
2676 return IRQ_RETVAL(handled);
2677}
2678
2679#ifdef CONFIG_R8169_NAPI
2680static int rtl8169_poll(struct net_device *dev, int *budget)
2681{
2682 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2683 struct rtl8169_private *tp = netdev_priv(dev);
2684 void __iomem *ioaddr = tp->mmio_addr;
2685
2686 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2687 rtl8169_tx_interrupt(dev, tp, ioaddr);
2688
2689 *budget -= work_done;
2690 dev->quota -= work_done;
2691
2692 if (work_done < work_to_do) {
2693 netif_rx_complete(dev);
2694 tp->intr_mask = 0xffff;
2695 /*
2696 * 20040426: the barrier is not strictly required but the
2697 * behavior of the irq handler could be less predictable
2698 * without it. Btw, the lack of flush for the posted pci
2699 * write is safe - FR
2700 */
2701 smp_wmb();
2702 RTL_W16(IntrMask, rtl8169_intr_mask);
2703 }
2704
2705 return (work_done >= work_to_do);
2706}
2707#endif
2708
2709static void rtl8169_down(struct net_device *dev)
2710{
2711 struct rtl8169_private *tp = netdev_priv(dev);
2712 void __iomem *ioaddr = tp->mmio_addr;
2713 unsigned int poll_locked = 0;
733b736c 2714 unsigned int intrmask;
1da177e4
LT		 2715
2716 rtl8169_delete_timer(dev);
2717
2718 netif_stop_queue(dev);
2719
2720 flush_scheduled_work();
2721
2722core_down:
2723 spin_lock_irq(&tp->lock);
2724
2725 rtl8169_asic_down(ioaddr);
2726
2727 /* Update the error counts. */
2728 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2729 RTL_W32(RxMissed, 0);
2730
2731 spin_unlock_irq(&tp->lock);
2732
2733 synchronize_irq(dev->irq);
2734
2735 if (!poll_locked) {
2736 netif_poll_disable(dev);
2737 poll_locked++;
2738 }
2739
2740 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2741 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2742
2743 /*
2744 * And now for the 50k$ question: are IRQ disabled or not ?
2745 *
2746 * Two paths lead here:
2747 * 1) dev->close
2748 * -> netif_running() is available to sync the current code and the
2749 * IRQ handler. See rtl8169_interrupt for details.
2750 * 2) dev->change_mtu
2751 * -> rtl8169_poll can not be issued again and re-enable the
2752 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2753 *
2754 * No loop if hotpluged or major error (0xffff).
1da177e4 2755 */
733b736c
AP		 2756 intrmask = RTL_R16(IntrMask);
2757 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2758 goto core_down;
2759
2760 rtl8169_tx_clear(tp);
2761
2762 rtl8169_rx_clear(tp);
2763}
2764
2765static int rtl8169_close(struct net_device *dev)
2766{
2767 struct rtl8169_private *tp = netdev_priv(dev);
2768 struct pci_dev *pdev = tp->pci_dev;
2769
2770 rtl8169_down(dev);
2771
2772 free_irq(dev->irq, dev);
2773
2774 netif_poll_enable(dev);
2775
2776 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2777 tp->RxPhyAddr);
2778 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2779 tp->TxPhyAddr);
2780 tp->TxDescArray = NULL;
2781 tp->RxDescArray = NULL;
2782
2783 return 0;
2784}
2785
2786static void
2787rtl8169_set_rx_mode(struct net_device *dev)
2788{
2789 struct rtl8169_private *tp = netdev_priv(dev);
2790 void __iomem *ioaddr = tp->mmio_addr;
2791 unsigned long flags;
2792 u32 mc_filter[2]; /* Multicast hash filter */
2793 int i, rx_mode;
2794 u32 tmp = 0;
2795
2796 if (dev->flags & IFF_PROMISC) {
2797 /* Unconditionally log net taps. */
b57b7e5a
SH		 2798 if (netif_msg_link(tp)) {
2799 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2800 dev->name);
2801 }
1da177e4
LT		 2802 rx_mode =
2803 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2804 AcceptAllPhys;
2805 mc_filter[1] = mc_filter[0] = 0xffffffff;
2806 } else if ((dev->mc_count > multicast_filter_limit)
2807 || (dev->flags & IFF_ALLMULTI)) {
2808 /* Too many to filter perfectly -- accept all multicasts. */
2809 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2810 mc_filter[1] = mc_filter[0] = 0xffffffff;
2811 } else {
2812 struct dev_mc_list *mclist;
2813 rx_mode = AcceptBroadcast | AcceptMyPhys;
2814 mc_filter[1] = mc_filter[0] = 0;
2815 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2816 i++, mclist = mclist->next) {
2817 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2818 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2819 rx_mode |= AcceptMulticast;
2820 }
2821 }
2822
2823 spin_lock_irqsave(&tp->lock, flags);
2824
2825 tmp = rtl8169_rx_config | rx_mode |
2826 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2827
bcf0bf90
FR		 2828 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2829 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2830 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2831 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2832 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2833 mc_filter[0] = 0xffffffff;
2834 mc_filter[1] = 0xffffffff;
2835 }
2836
1da177e4
LT		 2837 RTL_W32(RxConfig, tmp);
2838 RTL_W32(MAR0 + 0, mc_filter[0]);
2839 RTL_W32(MAR0 + 4, mc_filter[1]);
2840
2841 spin_unlock_irqrestore(&tp->lock, flags);
2842}
2843
2844/**
2845 * rtl8169_get_stats - Get rtl8169 read/write statistics
2846 * @dev: The Ethernet Device to get statistics for
2847 *
2848 * Get TX/RX statistics for rtl8169
2849 */
2850static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2851{
2852 struct rtl8169_private *tp = netdev_priv(dev);
2853 void __iomem *ioaddr = tp->mmio_addr;
2854 unsigned long flags;
2855
2856 if (netif_running(dev)) {
2857 spin_lock_irqsave(&tp->lock, flags);
2858 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2859 RTL_W32(RxMissed, 0);
2860 spin_unlock_irqrestore(&tp->lock, flags);
2861 }
5b0384f4 2862
1da177e4
LT		 2863 return &tp->stats;
2864}
2865
5d06a99f
FR		 2866#ifdef CONFIG_PM
2867
2868static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2869{
2870 struct net_device *dev = pci_get_drvdata(pdev);
2871 struct rtl8169_private *tp = netdev_priv(dev);
2872 void __iomem *ioaddr = tp->mmio_addr;
2873
2874 if (!netif_running(dev))
2875 goto out;
2876
2877 netif_device_detach(dev);
2878 netif_stop_queue(dev);
2879
2880 spin_lock_irq(&tp->lock);
2881
2882 rtl8169_asic_down(ioaddr);
2883
2884 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2885 RTL_W32(RxMissed, 0);
2886
2887 spin_unlock_irq(&tp->lock);
2888
2889 pci_save_state(pdev);
61a4dcc2 2890 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f
FR		 2891 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2892out:
2893 return 0;
2894}
2895
2896static int rtl8169_resume(struct pci_dev *pdev)
2897{
2898 struct net_device *dev = pci_get_drvdata(pdev);
2899
2900 if (!netif_running(dev))
2901 goto out;
2902
2903 netif_device_attach(dev);
2904
2905 pci_set_power_state(pdev, PCI_D0);
2906 pci_restore_state(pdev);
61a4dcc2 2907 pci_enable_wake(pdev, PCI_D0, 0);
5d06a99f
FR		 2908
2909 rtl8169_schedule_work(dev, rtl8169_reset_task);
2910out:
2911 return 0;
2912}
2913
2914#endif /* CONFIG_PM */
2915
1da177e4
LT		 2916static struct pci_driver rtl8169_pci_driver = {
2917 .name = MODULENAME,
2918 .id_table = rtl8169_pci_tbl,
2919 .probe = rtl8169_init_one,
2920 .remove = __devexit_p(rtl8169_remove_one),
2921#ifdef CONFIG_PM
2922 .suspend = rtl8169_suspend,
2923 .resume = rtl8169_resume,
2924#endif
2925};
2926
2927static int __init
2928rtl8169_init_module(void)
2929{
29917620 2930 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 2931}
2932
2933static void __exit
2934rtl8169_cleanup_module(void)
2935{
2936 pci_unregister_driver(&rtl8169_pci_driver);
2937}
2938
2939module_init(rtl8169_init_module);
2940module_exit(rtl8169_cleanup_module);
Clone of davem's net-next-2.6 tree