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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4 9 2004 - Massive updates. See kernel SCM system for details.
1da177e4
LT		 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4 14
1da177e4
LT		 15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
5b0384f4 21
1da177e4
LT		 22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4 28 exchanging Link Code Word (FLP).
1da177e4
LT		 29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
5b0384f4
FR		 84 if (!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
1da177e4
LT		 88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 116static const int max_interrupt_work = 20;
1da177e4
LT		 117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 120static const int multicast_filter_limit = 32;
1da177e4
LT		 121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
bcf0bf90
FR		 153 RTL_GIGA_MAC_VER_01 = 0x00,
154 RTL_GIGA_MAC_VER_02 = 0x01,
155 RTL_GIGA_MAC_VER_03 = 0x02,
156 RTL_GIGA_MAC_VER_04 = 0x03,
157 RTL_GIGA_MAC_VER_05 = 0x04,
158 RTL_GIGA_MAC_VER_11 = 0x0b,
159 RTL_GIGA_MAC_VER_12 = 0x0c,
160 RTL_GIGA_MAC_VER_13 = 0x0d,
161 RTL_GIGA_MAC_VER_14 = 0x0e,
162 RTL_GIGA_MAC_VER_15 = 0x0f
1da177e4
LT		 163};
164
165enum phy_version {
166 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
167 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
168 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
170 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
171 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
172};
173
1da177e4
LT		 174#define _R(NAME,MAC,MASK) \
175 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
176
3c6bee1d 177static const struct {
1da177e4
LT		 178 const char *name;
179 u8 mac_version;
180 u32 RxConfigMask; /* Clears the bits supported by this chip */
181} rtl_chip_info[] = {
bcf0bf90
FR		 182 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
183 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
185 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
186 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
187 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
189 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
190 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
191 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 192};
193#undef _R
194
bcf0bf90
FR		 195enum cfg_version {
196 RTL_CFG_0 = 0x00,
197 RTL_CFG_1,
198 RTL_CFG_2
199};
200
201static const struct {
202 unsigned int region;
203 unsigned int align;
204} rtl_cfg_info[] = {
205 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
206 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
207 [RTL_CFG_2] = { 2, 8 }
208};
209
1da177e4 210static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90
FR		 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_1 },
213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_1 },
214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
216 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
218 { PCI_VENDOR_ID_LINKSYS, 0x1032,
219 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 220 {0,},
221};
222
223MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
224
225static int rx_copybreak = 200;
226static int use_dac;
b57b7e5a
SH		 227static struct {
228 u32 msg_enable;
229} debug = { -1 };
1da177e4
LT		 230
231enum RTL8169_registers {
232 MAC0 = 0, /* Ethernet hardware address. */
233 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 234 CounterAddrLow = 0x10,
235 CounterAddrHigh = 0x14,
1da177e4
LT		 236 TxDescStartAddrLow = 0x20,
237 TxDescStartAddrHigh = 0x24,
238 TxHDescStartAddrLow = 0x28,
239 TxHDescStartAddrHigh = 0x2c,
240 FLASH = 0x30,
241 ERSR = 0x36,
242 ChipCmd = 0x37,
243 TxPoll = 0x38,
244 IntrMask = 0x3C,
245 IntrStatus = 0x3E,
246 TxConfig = 0x40,
247 RxConfig = 0x44,
248 RxMissed = 0x4C,
249 Cfg9346 = 0x50,
250 Config0 = 0x51,
251 Config1 = 0x52,
252 Config2 = 0x53,
253 Config3 = 0x54,
254 Config4 = 0x55,
255 Config5 = 0x56,
256 MultiIntr = 0x5C,
257 PHYAR = 0x60,
258 TBICSR = 0x64,
259 TBI_ANAR = 0x68,
260 TBI_LPAR = 0x6A,
261 PHYstatus = 0x6C,
262 RxMaxSize = 0xDA,
263 CPlusCmd = 0xE0,
264 IntrMitigate = 0xE2,
265 RxDescAddrLow = 0xE4,
266 RxDescAddrHigh = 0xE8,
267 EarlyTxThres = 0xEC,
268 FuncEvent = 0xF0,
269 FuncEventMask = 0xF4,
270 FuncPresetState = 0xF8,
271 FuncForceEvent = 0xFC,
272};
273
274enum RTL8169_register_content {
275 /* InterruptStatusBits */
276 SYSErr = 0x8000,
277 PCSTimeout = 0x4000,
278 SWInt = 0x0100,
279 TxDescUnavail = 0x80,
280 RxFIFOOver = 0x40,
281 LinkChg = 0x20,
282 RxOverflow = 0x10,
283 TxErr = 0x08,
284 TxOK = 0x04,
285 RxErr = 0x02,
286 RxOK = 0x01,
287
288 /* RxStatusDesc */
9dccf611
FR		 289 RxFOVF = (1 << 23),
290 RxRWT = (1 << 22),
291 RxRES = (1 << 21),
292 RxRUNT = (1 << 20),
293 RxCRC = (1 << 19),
1da177e4
LT		 294
295 /* ChipCmdBits */
296 CmdReset = 0x10,
297 CmdRxEnb = 0x08,
298 CmdTxEnb = 0x04,
299 RxBufEmpty = 0x01,
300
301 /* Cfg9346Bits */
302 Cfg9346_Lock = 0x00,
303 Cfg9346_Unlock = 0xC0,
304
305 /* rx_mode_bits */
306 AcceptErr = 0x20,
307 AcceptRunt = 0x10,
308 AcceptBroadcast = 0x08,
309 AcceptMulticast = 0x04,
310 AcceptMyPhys = 0x02,
311 AcceptAllPhys = 0x01,
312
313 /* RxConfigBits */
314 RxCfgFIFOShift = 13,
315 RxCfgDMAShift = 8,
316
317 /* TxConfigBits */
318 TxInterFrameGapShift = 24,
319 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
320
5d06a99f
FR		 321 /* Config1 register p.24 */
322 PMEnable = (1 << 0), /* Power Management Enable */
323
61a4dcc2
FR		 324 /* Config3 register p.25 */
325 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
326 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
327
5d06a99f 328 /* Config5 register p.27 */
61a4dcc2
FR		 329 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
330 MWF = (1 << 5), /* Accept Multicast wakeup frame */
331 UWF = (1 << 4), /* Accept Unicast wakeup frame */
332 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 333 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
334
1da177e4
LT		 335 /* TBICSR p.28 */
336 TBIReset = 0x80000000,
337 TBILoopback = 0x40000000,
338 TBINwEnable = 0x20000000,
339 TBINwRestart = 0x10000000,
340 TBILinkOk = 0x02000000,
341 TBINwComplete = 0x01000000,
342
343 /* CPlusCmd p.31 */
344 RxVlan = (1 << 6),
345 RxChkSum = (1 << 5),
346 PCIDAC = (1 << 4),
347 PCIMulRW = (1 << 3),
348
349 /* rtl8169_PHYstatus */
350 TBI_Enable = 0x80,
351 TxFlowCtrl = 0x40,
352 RxFlowCtrl = 0x20,
353 _1000bpsF = 0x10,
354 _100bps = 0x08,
355 _10bps = 0x04,
356 LinkStatus = 0x02,
357 FullDup = 0x01,
358
359 /* GIGABIT_PHY_registers */
360 PHY_CTRL_REG = 0,
361 PHY_STAT_REG = 1,
362 PHY_AUTO_NEGO_REG = 4,
363 PHY_1000_CTRL_REG = 9,
364
365 /* GIGABIT_PHY_REG_BIT */
366 PHY_Restart_Auto_Nego = 0x0200,
367 PHY_Enable_Auto_Nego = 0x1000,
368
369 /* PHY_STAT_REG = 1 */
370 PHY_Auto_Neco_Comp = 0x0020,
371
372 /* PHY_AUTO_NEGO_REG = 4 */
373 PHY_Cap_10_Half = 0x0020,
374 PHY_Cap_10_Full = 0x0040,
375 PHY_Cap_100_Half = 0x0080,
376 PHY_Cap_100_Full = 0x0100,
377
378 /* PHY_1000_CTRL_REG = 9 */
bcf0bf90 379 PHY_Cap_1000_Half = 0x0100,
1da177e4
LT		 380 PHY_Cap_1000_Full = 0x0200,
381
382 PHY_Cap_Null = 0x0,
383
384 /* _MediaType */
385 _10_Half = 0x01,
386 _10_Full = 0x02,
387 _100_Half = 0x04,
388 _100_Full = 0x08,
389 _1000_Full = 0x10,
390
391 /* _TBICSRBit */
392 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 393
394 /* DumpCounterCommand */
395 CounterDump = 0x8,
1da177e4
LT		 396};
397
398enum _DescStatusBit {
399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */
403
404 /* Tx private */
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift = 16, /* MSS value position */
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS = (1 << 18), /* Calculate IP checksum */
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag = (1 << 17), /* Add VLAN tag */
412
413 /* Rx private */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
416
417#define RxProtoUDP (PID1)
418#define RxProtoTCP (PID0)
419#define RxProtoIP (PID1 | PID0)
420#define RxProtoMask RxProtoIP
421
422 IPFail = (1 << 16), /* IP checksum failed */
423 UDPFail = (1 << 15), /* UDP/IP checksum failed */
424 TCPFail = (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag = (1 << 16), /* VLAN tag available */
426};
427
428#define RsvdMask 0x3fffc000
429
430struct TxDesc {
431 u32 opts1;
432 u32 opts2;
433 u64 addr;
434};
435
436struct RxDesc {
437 u32 opts1;
438 u32 opts2;
439 u64 addr;
440};
441
442struct ring_info {
443 struct sk_buff *skb;
444 u32 len;
445 u8 __pad[sizeof(void *) - sizeof(u32)];
446};
447
448struct rtl8169_private {
449 void __iomem *mmio_addr; /* memory map physical address */
450 struct pci_dev *pci_dev; /* Index of PCI device */
451 struct net_device_stats stats; /* statistics of net device */
452 spinlock_t lock; /* spin lock flag */
b57b7e5a 453 u32 msg_enable;
1da177e4
LT		 454 int chipset;
455 int mac_version;
456 int phy_version;
457 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
458 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
459 u32 dirty_rx;
460 u32 dirty_tx;
461 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
462 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
463 dma_addr_t TxPhyAddr;
464 dma_addr_t RxPhyAddr;
465 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
466 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 467 unsigned align;
1da177e4
LT		 468 unsigned rx_buf_sz;
469 struct timer_list timer;
470 u16 cp_cmd;
471 u16 intr_mask;
472 int phy_auto_nego_reg;
473 int phy_1000_ctrl_reg;
474#ifdef CONFIG_R8169_VLAN
475 struct vlan_group *vlgrp;
476#endif
477 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
478 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
479 void (*phy_reset_enable)(void __iomem *);
480 unsigned int (*phy_reset_pending)(void __iomem *);
481 unsigned int (*link_ok)(void __iomem *);
482 struct work_struct task;
61a4dcc2 483 unsigned wol_enabled : 1;
1da177e4
LT		 484};
485
979b6c13 486MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 487MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
488module_param_array(media, int, &num_media, 0);
df0a1bf6 489MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 490module_param(rx_copybreak, int, 0);
1b7efd58 491MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 492module_param(use_dac, int, 0);
493MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 494module_param_named(debug, debug.msg_enable, int, 0);
495MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 496MODULE_LICENSE("GPL");
497MODULE_VERSION(RTL8169_VERSION);
498
499static int rtl8169_open(struct net_device *dev);
500static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
501static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
502 struct pt_regs *regs);
503static int rtl8169_init_ring(struct net_device *dev);
504static void rtl8169_hw_start(struct net_device *dev);
505static int rtl8169_close(struct net_device *dev);
506static void rtl8169_set_rx_mode(struct net_device *dev);
507static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 508static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 509static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
510 void __iomem *);
4dcb7d33 511static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 512static void rtl8169_down(struct net_device *dev);
513
514#ifdef CONFIG_R8169_NAPI
515static int rtl8169_poll(struct net_device *dev, int *budget);
516#endif
517
518static const u16 rtl8169_intr_mask =
519 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
520static const u16 rtl8169_napi_event =
521 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
522static const unsigned int rtl8169_rx_config =
5b0384f4 523 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4
LT		 524
525#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
526#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
527#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
528#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
529
530static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
531{
532 int i;
533
534 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 535
2371408c 536 for (i = 20; i > 0; i--) {
1da177e4 537 /* Check if the RTL8169 has completed writing to the specified MII register */
5b0384f4 538 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 539 break;
2371408c 540 udelay(25);
1da177e4
LT		 541 }
542}
543
544static int mdio_read(void __iomem *ioaddr, int RegAddr)
545{
546 int i, value = -1;
547
548 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 549
2371408c 550 for (i = 20; i > 0; i--) {
1da177e4
LT		 551 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
552 if (RTL_R32(PHYAR) & 0x80000000) {
553 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
554 break;
555 }
2371408c 556 udelay(25);
1da177e4
LT		 557 }
558 return value;
559}
560
561static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
562{
563 RTL_W16(IntrMask, 0x0000);
564
565 RTL_W16(IntrStatus, 0xffff);
566}
567
568static void rtl8169_asic_down(void __iomem *ioaddr)
569{
570 RTL_W8(ChipCmd, 0x00);
571 rtl8169_irq_mask_and_ack(ioaddr);
572 RTL_R16(CPlusCmd);
573}
574
575static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
576{
577 return RTL_R32(TBICSR) & TBIReset;
578}
579
580static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
581{
582 return mdio_read(ioaddr, 0) & 0x8000;
583}
584
585static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
586{
587 return RTL_R32(TBICSR) & TBILinkOk;
588}
589
590static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
591{
592 return RTL_R8(PHYstatus) & LinkStatus;
593}
594
595static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
596{
597 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
598}
599
600static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
601{
602 unsigned int val;
603
604 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
605 mdio_write(ioaddr, PHY_CTRL_REG, val);
606}
607
608static void rtl8169_check_link_status(struct net_device *dev,
609 struct rtl8169_private *tp, void __iomem *ioaddr)
610{
611 unsigned long flags;
612
613 spin_lock_irqsave(&tp->lock, flags);
614 if (tp->link_ok(ioaddr)) {
615 netif_carrier_on(dev);
b57b7e5a
SH		 616 if (netif_msg_ifup(tp))
617 printk(KERN_INFO PFX "%s: link up\n", dev->name);
618 } else {
619 if (netif_msg_ifdown(tp))
620 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 621 netif_carrier_off(dev);
b57b7e5a 622 }
1da177e4
LT		 623 spin_unlock_irqrestore(&tp->lock, flags);
624}
625
626static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
627{
628 struct {
629 u16 speed;
630 u8 duplex;
631 u8 autoneg;
632 u8 media;
633 } link_settings[] = {
634 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
635 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
636 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
637 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
638 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
639 /* Make TBI happy */
640 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
641 }, *p;
642 unsigned char option;
5b0384f4 643
1da177e4
LT		 644 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
645
b57b7e5a 646 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 647 printk(KERN_WARNING PFX "media option is deprecated.\n");
648
649 for (p = link_settings; p->media != 0xff; p++) {
650 if (p->media == option)
651 break;
652 }
653 *autoneg = p->autoneg;
654 *speed = p->speed;
655 *duplex = p->duplex;
656}
657
61a4dcc2
FR		 658static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
659{
660 struct rtl8169_private *tp = netdev_priv(dev);
661 void __iomem *ioaddr = tp->mmio_addr;
662 u8 options;
663
664 wol->wolopts = 0;
665
666#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
667 wol->supported = WAKE_ANY;
668
669 spin_lock_irq(&tp->lock);
670
671 options = RTL_R8(Config1);
672 if (!(options & PMEnable))
673 goto out_unlock;
674
675 options = RTL_R8(Config3);
676 if (options & LinkUp)
677 wol->wolopts |= WAKE_PHY;
678 if (options & MagicPacket)
679 wol->wolopts |= WAKE_MAGIC;
680
681 options = RTL_R8(Config5);
682 if (options & UWF)
683 wol->wolopts |= WAKE_UCAST;
684 if (options & BWF)
5b0384f4 685 wol->wolopts |= WAKE_BCAST;
61a4dcc2 686 if (options & MWF)
5b0384f4 687 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 688
689out_unlock:
690 spin_unlock_irq(&tp->lock);
691}
692
693static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
694{
695 struct rtl8169_private *tp = netdev_priv(dev);
696 void __iomem *ioaddr = tp->mmio_addr;
697 int i;
698 static struct {
699 u32 opt;
700 u16 reg;
701 u8 mask;
702 } cfg[] = {
703 { WAKE_ANY, Config1, PMEnable },
704 { WAKE_PHY, Config3, LinkUp },
705 { WAKE_MAGIC, Config3, MagicPacket },
706 { WAKE_UCAST, Config5, UWF },
707 { WAKE_BCAST, Config5, BWF },
708 { WAKE_MCAST, Config5, MWF },
709 { WAKE_ANY, Config5, LanWake }
710 };
711
712 spin_lock_irq(&tp->lock);
713
714 RTL_W8(Cfg9346, Cfg9346_Unlock);
715
716 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
717 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
718 if (wol->wolopts & cfg[i].opt)
719 options |= cfg[i].mask;
720 RTL_W8(cfg[i].reg, options);
721 }
722
723 RTL_W8(Cfg9346, Cfg9346_Lock);
724
725 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
726
727 spin_unlock_irq(&tp->lock);
728
729 return 0;
730}
731
1da177e4
LT		 732static void rtl8169_get_drvinfo(struct net_device *dev,
733 struct ethtool_drvinfo *info)
734{
735 struct rtl8169_private *tp = netdev_priv(dev);
736
737 strcpy(info->driver, MODULENAME);
738 strcpy(info->version, RTL8169_VERSION);
739 strcpy(info->bus_info, pci_name(tp->pci_dev));
740}
741
742static int rtl8169_get_regs_len(struct net_device *dev)
743{
744 return R8169_REGS_SIZE;
745}
746
747static int rtl8169_set_speed_tbi(struct net_device *dev,
748 u8 autoneg, u16 speed, u8 duplex)
749{
750 struct rtl8169_private *tp = netdev_priv(dev);
751 void __iomem *ioaddr = tp->mmio_addr;
752 int ret = 0;
753 u32 reg;
754
755 reg = RTL_R32(TBICSR);
756 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
757 (duplex == DUPLEX_FULL)) {
758 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
759 } else if (autoneg == AUTONEG_ENABLE)
760 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
761 else {
b57b7e5a
SH		 762 if (netif_msg_link(tp)) {
763 printk(KERN_WARNING "%s: "
764 "incorrect speed setting refused in TBI mode\n",
765 dev->name);
766 }
1da177e4
LT		 767 ret = -EOPNOTSUPP;
768 }
769
770 return ret;
771}
772
773static int rtl8169_set_speed_xmii(struct net_device *dev,
774 u8 autoneg, u16 speed, u8 duplex)
775{
776 struct rtl8169_private *tp = netdev_priv(dev);
777 void __iomem *ioaddr = tp->mmio_addr;
778 int auto_nego, giga_ctrl;
779
780 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
781 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
782 PHY_Cap_100_Half | PHY_Cap_100_Full);
783 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
bcf0bf90 784 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half | PHY_Cap_Null);
1da177e4
LT		 785
786 if (autoneg == AUTONEG_ENABLE) {
787 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
788 PHY_Cap_100_Half | PHY_Cap_100_Full);
bcf0bf90 789 giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half;
1da177e4
LT		 790 } else {
791 if (speed == SPEED_10)
792 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
793 else if (speed == SPEED_100)
794 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
795 else if (speed == SPEED_1000)
bcf0bf90 796 giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half;
1da177e4
LT		 797
798 if (duplex == DUPLEX_HALF)
799 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
726ecdcf
AG		 800
801 if (duplex == DUPLEX_FULL)
802 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
bcf0bf90
FR		 803
804 /* This tweak comes straight from Realtek's driver. */
805 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
806 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
807 auto_nego = PHY_Cap_100_Half | 0x01;
808 }
809 }
810
811 /* The 8100e/8101e do Fast Ethernet only. */
812 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
813 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
814 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
815 if ((giga_ctrl & (PHY_Cap_1000_Full | PHY_Cap_1000_Half)) &&
816 netif_msg_link(tp)) {
817 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
818 dev->name);
819 }
820 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half);
1da177e4
LT		 821 }
822
623a1593
FR		 823 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
824
1da177e4
LT		 825 tp->phy_auto_nego_reg = auto_nego;
826 tp->phy_1000_ctrl_reg = giga_ctrl;
827
828 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
829 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
830 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
831 PHY_Restart_Auto_Nego);
832 return 0;
833}
834
835static int rtl8169_set_speed(struct net_device *dev,
836 u8 autoneg, u16 speed, u8 duplex)
837{
838 struct rtl8169_private *tp = netdev_priv(dev);
839 int ret;
840
841 ret = tp->set_speed(dev, autoneg, speed, duplex);
842
843 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
844 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
845
846 return ret;
847}
848
849static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
850{
851 struct rtl8169_private *tp = netdev_priv(dev);
852 unsigned long flags;
853 int ret;
854
855 spin_lock_irqsave(&tp->lock, flags);
856 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
857 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 858
1da177e4
LT		 859 return ret;
860}
861
862static u32 rtl8169_get_rx_csum(struct net_device *dev)
863{
864 struct rtl8169_private *tp = netdev_priv(dev);
865
866 return tp->cp_cmd & RxChkSum;
867}
868
869static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 unsigned long flags;
874
875 spin_lock_irqsave(&tp->lock, flags);
876
877 if (data)
878 tp->cp_cmd |= RxChkSum;
879 else
880 tp->cp_cmd &= ~RxChkSum;
881
882 RTL_W16(CPlusCmd, tp->cp_cmd);
883 RTL_R16(CPlusCmd);
884
885 spin_unlock_irqrestore(&tp->lock, flags);
886
887 return 0;
888}
889
890#ifdef CONFIG_R8169_VLAN
891
892static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
893 struct sk_buff *skb)
894{
895 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
896 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
897}
898
899static void rtl8169_vlan_rx_register(struct net_device *dev,
900 struct vlan_group *grp)
901{
902 struct rtl8169_private *tp = netdev_priv(dev);
903 void __iomem *ioaddr = tp->mmio_addr;
904 unsigned long flags;
905
906 spin_lock_irqsave(&tp->lock, flags);
907 tp->vlgrp = grp;
908 if (tp->vlgrp)
909 tp->cp_cmd |= RxVlan;
910 else
911 tp->cp_cmd &= ~RxVlan;
912 RTL_W16(CPlusCmd, tp->cp_cmd);
913 RTL_R16(CPlusCmd);
914 spin_unlock_irqrestore(&tp->lock, flags);
915}
916
917static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
918{
919 struct rtl8169_private *tp = netdev_priv(dev);
920 unsigned long flags;
921
922 spin_lock_irqsave(&tp->lock, flags);
923 if (tp->vlgrp)
924 tp->vlgrp->vlan_devices[vid] = NULL;
925 spin_unlock_irqrestore(&tp->lock, flags);
926}
927
928static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
929 struct sk_buff *skb)
930{
931 u32 opts2 = le32_to_cpu(desc->opts2);
932 int ret;
933
934 if (tp->vlgrp && (opts2 & RxVlanTag)) {
935 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
936 swab16(opts2 & 0xffff));
937 ret = 0;
938 } else
939 ret = -1;
940 desc->opts2 = 0;
941 return ret;
942}
943
944#else /* !CONFIG_R8169_VLAN */
945
946static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
947 struct sk_buff *skb)
948{
949 return 0;
950}
951
952static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
953 struct sk_buff *skb)
954{
955 return -1;
956}
957
958#endif
959
960static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
961{
962 struct rtl8169_private *tp = netdev_priv(dev);
963 void __iomem *ioaddr = tp->mmio_addr;
964 u32 status;
965
966 cmd->supported =
967 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
968 cmd->port = PORT_FIBRE;
969 cmd->transceiver = XCVR_INTERNAL;
970
971 status = RTL_R32(TBICSR);
972 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
973 cmd->autoneg = !!(status & TBINwEnable);
974
975 cmd->speed = SPEED_1000;
976 cmd->duplex = DUPLEX_FULL; /* Always set */
977}
978
979static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
980{
981 struct rtl8169_private *tp = netdev_priv(dev);
982 void __iomem *ioaddr = tp->mmio_addr;
983 u8 status;
984
985 cmd->supported = SUPPORTED_10baseT_Half |
986 SUPPORTED_10baseT_Full |
987 SUPPORTED_100baseT_Half |
988 SUPPORTED_100baseT_Full |
989 SUPPORTED_1000baseT_Full |
990 SUPPORTED_Autoneg |
5b0384f4 991 SUPPORTED_TP;
1da177e4
LT		 992
993 cmd->autoneg = 1;
994 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
995
996 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
997 cmd->advertising |= ADVERTISED_10baseT_Half;
998 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
999 cmd->advertising |= ADVERTISED_10baseT_Full;
1000 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
1001 cmd->advertising |= ADVERTISED_100baseT_Half;
1002 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
1003 cmd->advertising |= ADVERTISED_100baseT_Full;
1004 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
1005 cmd->advertising |= ADVERTISED_1000baseT_Full;
1006
1007 status = RTL_R8(PHYstatus);
1008
1009 if (status & _1000bpsF)
1010 cmd->speed = SPEED_1000;
1011 else if (status & _100bps)
1012 cmd->speed = SPEED_100;
1013 else if (status & _10bps)
1014 cmd->speed = SPEED_10;
1015
623a1593
FR		 1016 if (status & TxFlowCtrl)
1017 cmd->advertising |= ADVERTISED_Asym_Pause;
1018 if (status & RxFlowCtrl)
1019 cmd->advertising |= ADVERTISED_Pause;
1020
1da177e4
LT		 1021 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
1022 DUPLEX_FULL : DUPLEX_HALF;
1023}
1024
1025static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1026{
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028 unsigned long flags;
1029
1030 spin_lock_irqsave(&tp->lock, flags);
1031
1032 tp->get_settings(dev, cmd);
1033
1034 spin_unlock_irqrestore(&tp->lock, flags);
1035 return 0;
1036}
1037
1038static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1039 void *p)
1040{
5b0384f4
FR		 1041 struct rtl8169_private *tp = netdev_priv(dev);
1042 unsigned long flags;
1da177e4 1043
5b0384f4
FR		 1044 if (regs->len > R8169_REGS_SIZE)
1045 regs->len = R8169_REGS_SIZE;
1da177e4 1046
5b0384f4
FR		 1047 spin_lock_irqsave(&tp->lock, flags);
1048 memcpy_fromio(p, tp->mmio_addr, regs->len);
1049 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1050}
1051
b57b7e5a
SH		 1052static u32 rtl8169_get_msglevel(struct net_device *dev)
1053{
1054 struct rtl8169_private *tp = netdev_priv(dev);
1055
1056 return tp->msg_enable;
1057}
1058
1059static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1060{
1061 struct rtl8169_private *tp = netdev_priv(dev);
1062
1063 tp->msg_enable = value;
1064}
1065
d4a3a0fc
SH		 1066static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1067 "tx_packets",
1068 "rx_packets",
1069 "tx_errors",
1070 "rx_errors",
1071 "rx_missed",
1072 "align_errors",
1073 "tx_single_collisions",
1074 "tx_multi_collisions",
1075 "unicast",
1076 "broadcast",
1077 "multicast",
1078 "tx_aborted",
1079 "tx_underrun",
1080};
1081
1082struct rtl8169_counters {
1083 u64 tx_packets;
1084 u64 rx_packets;
1085 u64 tx_errors;
1086 u32 rx_errors;
1087 u16 rx_missed;
1088 u16 align_errors;
1089 u32 tx_one_collision;
1090 u32 tx_multi_collision;
1091 u64 rx_unicast;
1092 u64 rx_broadcast;
1093 u32 rx_multicast;
1094 u16 tx_aborted;
1095 u16 tx_underun;
1096};
1097
1098static int rtl8169_get_stats_count(struct net_device *dev)
1099{
1100 return ARRAY_SIZE(rtl8169_gstrings);
1101}
1102
1103static void rtl8169_get_ethtool_stats(struct net_device *dev,
1104 struct ethtool_stats *stats, u64 *data)
1105{
1106 struct rtl8169_private *tp = netdev_priv(dev);
1107 void __iomem *ioaddr = tp->mmio_addr;
1108 struct rtl8169_counters *counters;
1109 dma_addr_t paddr;
1110 u32 cmd;
1111
1112 ASSERT_RTNL();
1113
1114 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1115 if (!counters)
1116 return;
1117
1118 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1119 cmd = (u64)paddr & DMA_32BIT_MASK;
1120 RTL_W32(CounterAddrLow, cmd);
1121 RTL_W32(CounterAddrLow, cmd | CounterDump);
1122
1123 while (RTL_R32(CounterAddrLow) & CounterDump) {
1124 if (msleep_interruptible(1))
1125 break;
1126 }
1127
1128 RTL_W32(CounterAddrLow, 0);
1129 RTL_W32(CounterAddrHigh, 0);
1130
5b0384f4 1131 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1132 data[1] = le64_to_cpu(counters->rx_packets);
1133 data[2] = le64_to_cpu(counters->tx_errors);
1134 data[3] = le32_to_cpu(counters->rx_errors);
1135 data[4] = le16_to_cpu(counters->rx_missed);
1136 data[5] = le16_to_cpu(counters->align_errors);
1137 data[6] = le32_to_cpu(counters->tx_one_collision);
1138 data[7] = le32_to_cpu(counters->tx_multi_collision);
1139 data[8] = le64_to_cpu(counters->rx_unicast);
1140 data[9] = le64_to_cpu(counters->rx_broadcast);
1141 data[10] = le32_to_cpu(counters->rx_multicast);
1142 data[11] = le16_to_cpu(counters->tx_aborted);
1143 data[12] = le16_to_cpu(counters->tx_underun);
1144
1145 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1146}
1147
1148static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1149{
1150 switch(stringset) {
1151 case ETH_SS_STATS:
1152 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1153 break;
1154 }
1155}
1156
1157
1da177e4
LT		 1158static struct ethtool_ops rtl8169_ethtool_ops = {
1159 .get_drvinfo = rtl8169_get_drvinfo,
1160 .get_regs_len = rtl8169_get_regs_len,
1161 .get_link = ethtool_op_get_link,
1162 .get_settings = rtl8169_get_settings,
1163 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1164 .get_msglevel = rtl8169_get_msglevel,
1165 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1166 .get_rx_csum = rtl8169_get_rx_csum,
1167 .set_rx_csum = rtl8169_set_rx_csum,
1168 .get_tx_csum = ethtool_op_get_tx_csum,
1169 .set_tx_csum = ethtool_op_set_tx_csum,
1170 .get_sg = ethtool_op_get_sg,
1171 .set_sg = ethtool_op_set_sg,
1172 .get_tso = ethtool_op_get_tso,
1173 .set_tso = ethtool_op_set_tso,
1174 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1175 .get_wol = rtl8169_get_wol,
1176 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1177 .get_strings = rtl8169_get_strings,
1178 .get_stats_count = rtl8169_get_stats_count,
1179 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1180 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1181};
1182
1183static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1184 int bitval)
1185{
1186 int val;
1187
1188 val = mdio_read(ioaddr, reg);
1189 val = (bitval == 1) ?
1190 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1191 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1192}
1193
1194static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1195{
1196 const struct {
1197 u32 mask;
1198 int mac_version;
1199 } mac_info[] = {
bcf0bf90
FR		 1200 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1201 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1202 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1203 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1204 { 0x30000000, RTL_GIGA_MAC_VER_11 },
bcf0bf90
FR		 1205 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1206 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1207 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1208 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1209 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1210 }, *p = mac_info;
1211 u32 reg;
1212
1213 reg = RTL_R32(TxConfig) & 0x7c800000;
1214 while ((reg & p->mask) != p->mask)
1215 p++;
1216 tp->mac_version = p->mac_version;
1217}
1218
1219static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1220{
bcf0bf90 1221 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1222}
1223
1224static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1225{
1226 const struct {
1227 u16 mask;
1228 u16 set;
1229 int phy_version;
1230 } phy_info[] = {
1231 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1232 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1233 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1234 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1235 }, *p = phy_info;
1236 u16 reg;
1237
1238 reg = mdio_read(ioaddr, 3) & 0xffff;
1239 while ((reg & p->mask) != p->set)
1240 p++;
1241 tp->phy_version = p->phy_version;
1242}
1243
1244static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1245{
1246 struct {
1247 int version;
1248 char *msg;
1249 u32 reg;
1250 } phy_print[] = {
1251 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1252 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1253 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1254 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1255 { 0, NULL, 0x0000 }
1256 }, *p;
1257
1258 for (p = phy_print; p->msg; p++) {
1259 if (tp->phy_version == p->version) {
1260 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1261 return;
1262 }
1263 }
1264 dprintk("phy_version == Unknown\n");
1265}
1266
1267static void rtl8169_hw_phy_config(struct net_device *dev)
1268{
1269 struct rtl8169_private *tp = netdev_priv(dev);
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 struct {
1272 u16 regs[5]; /* Beware of bit-sign propagation */
1273 } phy_magic[5] = { {
1274 { 0x0000, //w 4 15 12 0
1275 0x00a1, //w 3 15 0 00a1
1276 0x0008, //w 2 15 0 0008
1277 0x1020, //w 1 15 0 1020
1278 0x1000 } },{ //w 0 15 0 1000
1279 { 0x7000, //w 4 15 12 7
1280 0xff41, //w 3 15 0 ff41
1281 0xde60, //w 2 15 0 de60
1282 0x0140, //w 1 15 0 0140
1283 0x0077 } },{ //w 0 15 0 0077
1284 { 0xa000, //w 4 15 12 a
1285 0xdf01, //w 3 15 0 df01
1286 0xdf20, //w 2 15 0 df20
1287 0xff95, //w 1 15 0 ff95
1288 0xfa00 } },{ //w 0 15 0 fa00
1289 { 0xb000, //w 4 15 12 b
1290 0xff41, //w 3 15 0 ff41
1291 0xde20, //w 2 15 0 de20
1292 0x0140, //w 1 15 0 0140
1293 0x00bb } },{ //w 0 15 0 00bb
1294 { 0xf000, //w 4 15 12 f
1295 0xdf01, //w 3 15 0 df01
1296 0xdf20, //w 2 15 0 df20
1297 0xff95, //w 1 15 0 ff95
1298 0xbf00 } //w 0 15 0 bf00
1299 }
1300 }, *p = phy_magic;
1301 int i;
1302
1303 rtl8169_print_mac_version(tp);
1304 rtl8169_print_phy_version(tp);
1305
bcf0bf90 1306 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1307 return;
1308 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1309 return;
1310
1311 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1312 dprintk("Do final_reg2.cfg\n");
1313
1314 /* Shazam ! */
1315
bcf0bf90 1316 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1317 mdio_write(ioaddr, 31, 0x0001);
1318 mdio_write(ioaddr, 9, 0x273a);
1319 mdio_write(ioaddr, 14, 0x7bfb);
1320 mdio_write(ioaddr, 27, 0x841e);
1321
1322 mdio_write(ioaddr, 31, 0x0002);
1323 mdio_write(ioaddr, 1, 0x90d0);
1324 mdio_write(ioaddr, 31, 0x0000);
1325 return;
1326 }
1327
1328 /* phy config for RTL8169s mac_version C chip */
1329 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1330 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1331 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1332 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1333
1334 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1335 int val, pos = 4;
1336
1337 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1338 mdio_write(ioaddr, pos, val);
1339 while (--pos >= 0)
1340 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1341 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1342 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1343 }
1344 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1345}
1346
1347static void rtl8169_phy_timer(unsigned long __opaque)
1348{
1349 struct net_device *dev = (struct net_device *)__opaque;
1350 struct rtl8169_private *tp = netdev_priv(dev);
1351 struct timer_list *timer = &tp->timer;
1352 void __iomem *ioaddr = tp->mmio_addr;
1353 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1354
bcf0bf90 1355 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1356 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1357
1358 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1359 return;
1360
1361 spin_lock_irq(&tp->lock);
1362
1363 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1364 /*
1da177e4
LT		 1365 * A busy loop could burn quite a few cycles on nowadays CPU.
1366 * Let's delay the execution of the timer for a few ticks.
1367 */
1368 timeout = HZ/10;
1369 goto out_mod_timer;
1370 }
1371
1372 if (tp->link_ok(ioaddr))
1373 goto out_unlock;
1374
b57b7e5a
SH		 1375 if (netif_msg_link(tp))
1376 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1377
1378 tp->phy_reset_enable(ioaddr);
1379
1380out_mod_timer:
1381 mod_timer(timer, jiffies + timeout);
1382out_unlock:
1383 spin_unlock_irq(&tp->lock);
1384}
1385
1386static inline void rtl8169_delete_timer(struct net_device *dev)
1387{
1388 struct rtl8169_private *tp = netdev_priv(dev);
1389 struct timer_list *timer = &tp->timer;
1390
bcf0bf90 1391 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1392 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1393 return;
1394
1395 del_timer_sync(timer);
1396}
1397
1398static inline void rtl8169_request_timer(struct net_device *dev)
1399{
1400 struct rtl8169_private *tp = netdev_priv(dev);
1401 struct timer_list *timer = &tp->timer;
1402
bcf0bf90 1403 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1404 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1405 return;
1406
1407 init_timer(timer);
1408 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1409 timer->data = (unsigned long)(dev);
1410 timer->function = rtl8169_phy_timer;
1411 add_timer(timer);
1412}
1413
1414#ifdef CONFIG_NET_POLL_CONTROLLER
1415/*
1416 * Polling 'interrupt' - used by things like netconsole to send skbs
1417 * without having to re-enable interrupts. It's not called while
1418 * the interrupt routine is executing.
1419 */
1420static void rtl8169_netpoll(struct net_device *dev)
1421{
1422 struct rtl8169_private *tp = netdev_priv(dev);
1423 struct pci_dev *pdev = tp->pci_dev;
1424
1425 disable_irq(pdev->irq);
1426 rtl8169_interrupt(pdev->irq, dev, NULL);
1427 enable_irq(pdev->irq);
1428}
1429#endif
1430
a2b98a69
FR		 1431static void __rtl8169_set_mac_addr(struct net_device *dev, void __iomem *ioaddr)
1432{
1433 unsigned int i, j;
1434
1435 RTL_W8(Cfg9346, Cfg9346_Unlock);
1436 for (i = 0; i < 2; i++) {
1437 __le32 l = 0;
1438
1439 for (j = 0; j < 4; j++) {
1440 l <<= 8;
1441 l |= dev->dev_addr[4*i + j];
1442 }
1443 RTL_W32(MAC0 + 4*i, cpu_to_be32(l));
1444 }
1445 RTL_W8(Cfg9346, Cfg9346_Lock);
1446}
1447
1448static int rtl8169_set_mac_addr(struct net_device *dev, void *p)
1449{
1450 struct rtl8169_private *tp = netdev_priv(dev);
1451 struct sockaddr *addr = p;
1452
1453 if (!is_valid_ether_addr(addr->sa_data))
1454 return -EINVAL;
1455
1456 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1457
1458 if (netif_running(dev)) {
1459 spin_lock_irq(&tp->lock);
1460 __rtl8169_set_mac_addr(dev, tp->mmio_addr);
1461 spin_unlock_irq(&tp->lock);
1462 }
1463 return 0;
1464}
1465
1da177e4
LT		 1466static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1467 void __iomem *ioaddr)
1468{
1469 iounmap(ioaddr);
1470 pci_release_regions(pdev);
1471 pci_disable_device(pdev);
1472 free_netdev(dev);
1473}
1474
4ff96fa6
FR		 1475static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1476{
1477 void __iomem *ioaddr = tp->mmio_addr;
1478 static int board_idx = -1;
1479 u8 autoneg, duplex;
1480 u16 speed;
1481
1482 board_idx++;
1483
1484 rtl8169_hw_phy_config(dev);
1485
1486 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1487 RTL_W8(0x82, 0x01);
1488
bcf0bf90 1489 if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
4ff96fa6
FR		 1490 dprintk("Set PCI Latency=0x40\n");
1491 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1492 }
1493
bcf0bf90 1494 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1495 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1496 RTL_W8(0x82, 0x01);
1497 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1498 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1499 }
1500
1501 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1502
1503 rtl8169_set_speed(dev, autoneg, speed, duplex);
1504
1505 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1506 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1507}
1508
1da177e4 1509static int __devinit
4ff96fa6 1510rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1511{
bcf0bf90 1512 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1da177e4 1513 struct rtl8169_private *tp;
4ff96fa6
FR		 1514 struct net_device *dev;
1515 void __iomem *ioaddr;
1516 unsigned int i, pm_cap;
1517 int rc;
1da177e4 1518
4ff96fa6
FR		 1519 if (netif_msg_drv(&debug)) {
1520 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1521 MODULENAME, RTL8169_VERSION);
1522 }
1da177e4 1523
1da177e4 1524 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1525 if (!dev) {
b57b7e5a 1526 if (netif_msg_drv(&debug))
9b91cf9d 1527 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1528 rc = -ENOMEM;
1529 goto out;
1da177e4
LT		 1530 }
1531
1532 SET_MODULE_OWNER(dev);
1533 SET_NETDEV_DEV(dev, &pdev->dev);
1534 tp = netdev_priv(dev);
b57b7e5a 1535 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1536
1537 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1538 rc = pci_enable_device(pdev);
b57b7e5a 1539 if (rc < 0) {
2e8a538d 1540 if (netif_msg_probe(tp))
9b91cf9d 1541 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1542 goto err_out_free_dev_1;
1da177e4
LT		 1543 }
1544
1545 rc = pci_set_mwi(pdev);
1546 if (rc < 0)
4ff96fa6 1547 goto err_out_disable_2;
1da177e4
LT		 1548
1549 /* save power state before pci_enable_device overwrites it */
1550 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1551 if (pm_cap) {
4ff96fa6 1552 u16 pwr_command, acpi_idle_state;
1da177e4
LT		 1553
1554 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1555 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1556 } else {
4ff96fa6 1557 if (netif_msg_probe(tp)) {
9b91cf9d 1558 dev_err(&pdev->dev,
4ff96fa6
FR		 1559 "PowerManagement capability not found.\n");
1560 }
1da177e4
LT		 1561 }
1562
1563 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1564 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1565 if (netif_msg_probe(tp)) {
9b91cf9d 1566 dev_err(&pdev->dev,
bcf0bf90
FR		 1567 "region #%d not an MMIO resource, aborting\n",
1568 region);
4ff96fa6 1569 }
1da177e4 1570 rc = -ENODEV;
4ff96fa6 1571 goto err_out_mwi_3;
1da177e4 1572 }
4ff96fa6 1573
1da177e4 1574 /* check for weird/broken PCI region reporting */
bcf0bf90 1575 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1576 if (netif_msg_probe(tp)) {
9b91cf9d 1577 dev_err(&pdev->dev,
4ff96fa6
FR		 1578 "Invalid PCI region size(s), aborting\n");
1579 }
1da177e4 1580 rc = -ENODEV;
4ff96fa6 1581 goto err_out_mwi_3;
1da177e4
LT		 1582 }
1583
1584 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1585 if (rc < 0) {
2e8a538d 1586 if (netif_msg_probe(tp))
9b91cf9d 1587 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1588 goto err_out_mwi_3;
1da177e4
LT		 1589 }
1590
1591 tp->cp_cmd = PCIMulRW | RxChkSum;
1592
1593 if ((sizeof(dma_addr_t) > 4) &&
1594 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1595 tp->cp_cmd |= PCIDAC;
1596 dev->features |= NETIF_F_HIGHDMA;
1597 } else {
1598 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1599 if (rc < 0) {
4ff96fa6 1600 if (netif_msg_probe(tp)) {
9b91cf9d 1601 dev_err(&pdev->dev,
4ff96fa6
FR		 1602 "DMA configuration failed.\n");
1603 }
1604 goto err_out_free_res_4;
1da177e4
LT		 1605 }
1606 }
1607
1608 pci_set_master(pdev);
1609
1610 /* ioremap MMIO region */
bcf0bf90 1611 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1612 if (!ioaddr) {
b57b7e5a 1613 if (netif_msg_probe(tp))
9b91cf9d 1614 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1615 rc = -EIO;
4ff96fa6 1616 goto err_out_free_res_4;
1da177e4
LT		 1617 }
1618
1619 /* Unneeded ? Don't mess with Mrs. Murphy. */
1620 rtl8169_irq_mask_and_ack(ioaddr);
1621
1622 /* Soft reset the chip. */
1623 RTL_W8(ChipCmd, CmdReset);
1624
1625 /* Check that the chip has finished the reset. */
b518fa8e 1626 for (i = 100; i > 0; i--) {
1da177e4
LT		 1627 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1628 break;
b518fa8e 1629 msleep_interruptible(1);
1da177e4
LT		 1630 }
1631
1632 /* Identify chip attached to board */
1633 rtl8169_get_mac_version(tp, ioaddr);
1634 rtl8169_get_phy_version(tp, ioaddr);
1635
1636 rtl8169_print_mac_version(tp);
1637 rtl8169_print_phy_version(tp);
1638
1639 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1640 if (tp->mac_version == rtl_chip_info[i].mac_version)
1641 break;
1642 }
1643 if (i < 0) {
1644 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1645 if (netif_msg_probe(tp)) {
2e8a538d 1646 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1647 "unknown chip version, assuming %s\n",
1648 rtl_chip_info[0].name);
b57b7e5a 1649 }
1da177e4
LT		 1650 i++;
1651 }
1652 tp->chipset = i;
1653
5d06a99f
FR		 1654 RTL_W8(Cfg9346, Cfg9346_Unlock);
1655 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1656 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1657 RTL_W8(Cfg9346, Cfg9346_Lock);
1658
1da177e4
LT		 1659 if (RTL_R8(PHYstatus) & TBI_Enable) {
1660 tp->set_speed = rtl8169_set_speed_tbi;
1661 tp->get_settings = rtl8169_gset_tbi;
1662 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1663 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1664 tp->link_ok = rtl8169_tbi_link_ok;
1665
1666 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1667 } else {
1668 tp->set_speed = rtl8169_set_speed_xmii;
1669 tp->get_settings = rtl8169_gset_xmii;
1670 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1671 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1672 tp->link_ok = rtl8169_xmii_link_ok;
1673 }
1674
1675 /* Get MAC address. FIXME: read EEPROM */
1676 for (i = 0; i < MAC_ADDR_LEN; i++)
1677 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1678 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1679
1680 dev->open = rtl8169_open;
1681 dev->hard_start_xmit = rtl8169_start_xmit;
1682 dev->get_stats = rtl8169_get_stats;
1683 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1684 dev->stop = rtl8169_close;
1685 dev->tx_timeout = rtl8169_tx_timeout;
1686 dev->set_multicast_list = rtl8169_set_rx_mode;
a2b98a69 1687 dev->set_mac_address = rtl8169_set_mac_addr;
1da177e4
LT		 1688 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1689 dev->irq = pdev->irq;
1690 dev->base_addr = (unsigned long) ioaddr;
1691 dev->change_mtu = rtl8169_change_mtu;
1692
1693#ifdef CONFIG_R8169_NAPI
1694 dev->poll = rtl8169_poll;
1695 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1696#endif
1697
1698#ifdef CONFIG_R8169_VLAN
1699 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1700 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1701 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1702#endif
1703
1704#ifdef CONFIG_NET_POLL_CONTROLLER
1705 dev->poll_controller = rtl8169_netpoll;
1706#endif
1707
1708 tp->intr_mask = 0xffff;
1709 tp->pci_dev = pdev;
1710 tp->mmio_addr = ioaddr;
bcf0bf90 1711 tp->align = rtl_cfg_info[ent->driver_data].align;
1da177e4
LT		 1712
1713 spin_lock_init(&tp->lock);
1714
1715 rc = register_netdev(dev);
4ff96fa6
FR		 1716 if (rc < 0)
1717 goto err_out_unmap_5;
1da177e4 1718
1da177e4
LT		 1719 pci_set_drvdata(pdev, dev);
1720
b57b7e5a
SH		 1721 if (netif_msg_probe(tp)) {
1722 printk(KERN_INFO "%s: %s at 0x%lx, "
1723 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1724 "IRQ %d\n",
1725 dev->name,
bcf0bf90 1726 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1727 dev->base_addr,
1728 dev->dev_addr[0], dev->dev_addr[1],
1729 dev->dev_addr[2], dev->dev_addr[3],
1730 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1731 }
1da177e4 1732
4ff96fa6 1733 rtl8169_init_phy(dev, tp);
1da177e4 1734
4ff96fa6
FR		 1735out:
1736 return rc;
1da177e4 1737
4ff96fa6
FR		 1738err_out_unmap_5:
1739 iounmap(ioaddr);
1740err_out_free_res_4:
1741 pci_release_regions(pdev);
1742err_out_mwi_3:
1743 pci_clear_mwi(pdev);
1744err_out_disable_2:
1745 pci_disable_device(pdev);
1746err_out_free_dev_1:
1747 free_netdev(dev);
1748 goto out;
1da177e4
LT		 1749}
1750
1751static void __devexit
1752rtl8169_remove_one(struct pci_dev *pdev)
1753{
1754 struct net_device *dev = pci_get_drvdata(pdev);
1755 struct rtl8169_private *tp = netdev_priv(dev);
1756
1757 assert(dev != NULL);
1758 assert(tp != NULL);
1759
1760 unregister_netdev(dev);
1761 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1762 pci_set_drvdata(pdev, NULL);
1763}
1764
1da177e4
LT		 1765static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1766 struct net_device *dev)
1767{
1768 unsigned int mtu = dev->mtu;
1769
1770 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1771}
1772
1773static int rtl8169_open(struct net_device *dev)
1774{
1775 struct rtl8169_private *tp = netdev_priv(dev);
1776 struct pci_dev *pdev = tp->pci_dev;
1777 int retval;
1778
1779 rtl8169_set_rxbufsize(tp, dev);
1780
1781 retval =
1fb9df5d 1782 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1783 if (retval < 0)
1784 goto out;
1785
1786 retval = -ENOMEM;
1787
1788 /*
1789 * Rx and Tx desscriptors needs 256 bytes alignment.
1790 * pci_alloc_consistent provides more.
1791 */
1792 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1793 &tp->TxPhyAddr);
1794 if (!tp->TxDescArray)
1795 goto err_free_irq;
1796
1797 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1798 &tp->RxPhyAddr);
1799 if (!tp->RxDescArray)
1800 goto err_free_tx;
1801
1802 retval = rtl8169_init_ring(dev);
1803 if (retval < 0)
1804 goto err_free_rx;
1805
1806 INIT_WORK(&tp->task, NULL, dev);
1807
1808 rtl8169_hw_start(dev);
1809
1810 rtl8169_request_timer(dev);
1811
1812 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1813out:
1814 return retval;
1815
1816err_free_rx:
1817 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1818 tp->RxPhyAddr);
1819err_free_tx:
1820 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1821 tp->TxPhyAddr);
1822err_free_irq:
1823 free_irq(dev->irq, dev);
1824 goto out;
1825}
1826
1827static void rtl8169_hw_reset(void __iomem *ioaddr)
1828{
1829 /* Disable interrupts */
1830 rtl8169_irq_mask_and_ack(ioaddr);
1831
1832 /* Reset the chipset */
1833 RTL_W8(ChipCmd, CmdReset);
1834
1835 /* PCI commit */
1836 RTL_R8(ChipCmd);
1837}
1838
1839static void
1840rtl8169_hw_start(struct net_device *dev)
1841{
1842 struct rtl8169_private *tp = netdev_priv(dev);
1843 void __iomem *ioaddr = tp->mmio_addr;
bcf0bf90 1844 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 1845 u32 i;
1846
1847 /* Soft reset the chip. */
1848 RTL_W8(ChipCmd, CmdReset);
1849
1850 /* Check that the chip has finished the reset. */
b518fa8e 1851 for (i = 100; i > 0; i--) {
1da177e4
LT		 1852 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1853 break;
b518fa8e 1854 msleep_interruptible(1);
1da177e4
LT		 1855 }
1856
bcf0bf90
FR		 1857 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1858 pci_write_config_word(pdev, 0x68, 0x00);
1859 pci_write_config_word(pdev, 0x69, 0x08);
1860 }
1861
1862 /* Undocumented stuff. */
1863 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1864 u16 cmd;
1865
1866 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1867 if ((RTL_R8(Config2) & 0x07) & 0x01)
1868 RTL_W32(0x7c, 0x0007ffff);
1869
1870 RTL_W32(0x7c, 0x0007ff00);
1871
1872 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1873 cmd = cmd & 0xef;
1874 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1875 }
1876
1877
1da177e4 1878 RTL_W8(Cfg9346, Cfg9346_Unlock);
1da177e4
LT		 1879 RTL_W8(EarlyTxThres, EarlyTxThld);
1880
126fa4b9
FR		 1881 /* Low hurts. Let's disable the filtering. */
1882 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1883
1884 /* Set Rx Config register */
1885 i = rtl8169_rx_config |
1886 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1887 RTL_W32(RxConfig, i);
1888
1889 /* Set DMA burst size and Interframe Gap Time */
5b0384f4
FR		 1890 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1891 (InterFrameGap << TxInterFrameGapShift));
1da177e4 1892
bcf0bf90
FR		 1893 tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;
1894
1895 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1896 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1897 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1898 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1899 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1900 }
1901
bcf0bf90
FR		 1902 RTL_W16(CPlusCmd, tp->cp_cmd);
1903
1da177e4
LT		 1904 /*
1905 * Undocumented corner. Supposedly:
1906 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1907 */
1908 RTL_W16(IntrMitigate, 0x0000);
1909
1910 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1911 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1912 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1913 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
bcf0bf90 1914 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1da177e4 1915 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1916
1917 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1918 RTL_R8(IntrMask);
1da177e4
LT		 1919
1920 RTL_W32(RxMissed, 0);
1921
1922 rtl8169_set_rx_mode(dev);
1923
1924 /* no early-rx interrupts */
1925 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1926
1927 /* Enable all known interrupts by setting the interrupt mask. */
1928 RTL_W16(IntrMask, rtl8169_intr_mask);
1929
a2b98a69
FR		 1930 __rtl8169_set_mac_addr(dev, ioaddr);
1931
1da177e4
LT		 1932 netif_start_queue(dev);
1933}
1934
1935static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1936{
1937 struct rtl8169_private *tp = netdev_priv(dev);
1938 int ret = 0;
1939
1940 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1941 return -EINVAL;
1942
1943 dev->mtu = new_mtu;
1944
1945 if (!netif_running(dev))
1946 goto out;
1947
1948 rtl8169_down(dev);
1949
1950 rtl8169_set_rxbufsize(tp, dev);
1951
1952 ret = rtl8169_init_ring(dev);
1953 if (ret < 0)
1954 goto out;
1955
1956 netif_poll_enable(dev);
1957
1958 rtl8169_hw_start(dev);
1959
1960 rtl8169_request_timer(dev);
1961
1962out:
1963 return ret;
1964}
1965
1966static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1967{
1968 desc->addr = 0x0badbadbadbadbadull;
1969 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1970}
1971
1972static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1973 struct sk_buff **sk_buff, struct RxDesc *desc)
1974{
1975 struct pci_dev *pdev = tp->pci_dev;
1976
1977 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1978 PCI_DMA_FROMDEVICE);
1979 dev_kfree_skb(*sk_buff);
1980 *sk_buff = NULL;
1981 rtl8169_make_unusable_by_asic(desc);
1982}
1983
1984static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1985{
1986 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1987
1988 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1989}
1990
1991static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1992 u32 rx_buf_sz)
1993{
1994 desc->addr = cpu_to_le64(mapping);
1995 wmb();
1996 rtl8169_mark_to_asic(desc, rx_buf_sz);
1997}
1998
1999static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
bcf0bf90
FR		 2000 struct RxDesc *desc, int rx_buf_sz,
2001 unsigned int align)
1da177e4
LT		 2002{
2003 struct sk_buff *skb;
2004 dma_addr_t mapping;
2005 int ret = 0;
2006
bcf0bf90 2007 skb = dev_alloc_skb(rx_buf_sz + align);
1da177e4
LT		 2008 if (!skb)
2009 goto err_out;
2010
bcf0bf90 2011 skb_reserve(skb, align);
1da177e4
LT		 2012 *sk_buff = skb;
2013
689be439 2014 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2015 PCI_DMA_FROMDEVICE);
2016
2017 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2018
2019out:
2020 return ret;
2021
2022err_out:
2023 ret = -ENOMEM;
2024 rtl8169_make_unusable_by_asic(desc);
2025 goto out;
2026}
2027
2028static void rtl8169_rx_clear(struct rtl8169_private *tp)
2029{
2030 int i;
2031
2032 for (i = 0; i < NUM_RX_DESC; i++) {
2033 if (tp->Rx_skbuff[i]) {
2034 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2035 tp->RxDescArray + i);
2036 }
2037 }
2038}
2039
2040static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2041 u32 start, u32 end)
2042{
2043 u32 cur;
5b0384f4 2044
1da177e4
LT		 2045 for (cur = start; end - cur > 0; cur++) {
2046 int ret, i = cur % NUM_RX_DESC;
2047
2048 if (tp->Rx_skbuff[i])
2049 continue;
bcf0bf90 2050
1da177e4 2051 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
bcf0bf90 2052 tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
1da177e4
LT		 2053 if (ret < 0)
2054 break;
2055 }
2056 return cur - start;
2057}
2058
2059static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2060{
2061 desc->opts1 |= cpu_to_le32(RingEnd);
2062}
2063
2064static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2065{
2066 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2067}
2068
2069static int rtl8169_init_ring(struct net_device *dev)
2070{
2071 struct rtl8169_private *tp = netdev_priv(dev);
2072
2073 rtl8169_init_ring_indexes(tp);
2074
2075 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2076 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2077
2078 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2079 goto err_out;
2080
2081 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2082
2083 return 0;
2084
2085err_out:
2086 rtl8169_rx_clear(tp);
2087 return -ENOMEM;
2088}
2089
2090static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2091 struct TxDesc *desc)
2092{
2093 unsigned int len = tx_skb->len;
2094
2095 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2096 desc->opts1 = 0x00;
2097 desc->opts2 = 0x00;
2098 desc->addr = 0x00;
2099 tx_skb->len = 0;
2100}
2101
2102static void rtl8169_tx_clear(struct rtl8169_private *tp)
2103{
2104 unsigned int i;
2105
2106 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2107 unsigned int entry = i % NUM_TX_DESC;
2108 struct ring_info *tx_skb = tp->tx_skb + entry;
2109 unsigned int len = tx_skb->len;
2110
2111 if (len) {
2112 struct sk_buff *skb = tx_skb->skb;
2113
2114 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2115 tp->TxDescArray + entry);
2116 if (skb) {
2117 dev_kfree_skb(skb);
2118 tx_skb->skb = NULL;
2119 }
2120 tp->stats.tx_dropped++;
2121 }
2122 }
2123 tp->cur_tx = tp->dirty_tx = 0;
2124}
2125
2126static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2127{
2128 struct rtl8169_private *tp = netdev_priv(dev);
2129
2130 PREPARE_WORK(&tp->task, task, dev);
2131 schedule_delayed_work(&tp->task, 4);
2132}
2133
2134static void rtl8169_wait_for_quiescence(struct net_device *dev)
2135{
2136 struct rtl8169_private *tp = netdev_priv(dev);
2137 void __iomem *ioaddr = tp->mmio_addr;
2138
2139 synchronize_irq(dev->irq);
2140
2141 /* Wait for any pending NAPI task to complete */
2142 netif_poll_disable(dev);
2143
2144 rtl8169_irq_mask_and_ack(ioaddr);
2145
2146 netif_poll_enable(dev);
2147}
2148
2149static void rtl8169_reinit_task(void *_data)
2150{
2151 struct net_device *dev = _data;
2152 int ret;
2153
2154 if (netif_running(dev)) {
2155 rtl8169_wait_for_quiescence(dev);
2156 rtl8169_close(dev);
2157 }
2158
2159 ret = rtl8169_open(dev);
2160 if (unlikely(ret < 0)) {
2161 if (net_ratelimit()) {
b57b7e5a
SH		 2162 struct rtl8169_private *tp = netdev_priv(dev);
2163
2164 if (netif_msg_drv(tp)) {
2165 printk(PFX KERN_ERR
2166 "%s: reinit failure (status = %d)."
2167 " Rescheduling.\n", dev->name, ret);
2168 }
1da177e4
LT		 2169 }
2170 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2171 }
2172}
2173
2174static void rtl8169_reset_task(void *_data)
2175{
2176 struct net_device *dev = _data;
2177 struct rtl8169_private *tp = netdev_priv(dev);
2178
2179 if (!netif_running(dev))
2180 return;
2181
2182 rtl8169_wait_for_quiescence(dev);
2183
2184 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2185 rtl8169_tx_clear(tp);
2186
2187 if (tp->dirty_rx == tp->cur_rx) {
2188 rtl8169_init_ring_indexes(tp);
2189 rtl8169_hw_start(dev);
2190 netif_wake_queue(dev);
2191 } else {
2192 if (net_ratelimit()) {
b57b7e5a
SH		 2193 struct rtl8169_private *tp = netdev_priv(dev);
2194
2195 if (netif_msg_intr(tp)) {
2196 printk(PFX KERN_EMERG
2197 "%s: Rx buffers shortage\n", dev->name);
2198 }
1da177e4
LT		 2199 }
2200 rtl8169_schedule_work(dev, rtl8169_reset_task);
2201 }
2202}
2203
2204static void rtl8169_tx_timeout(struct net_device *dev)
2205{
2206 struct rtl8169_private *tp = netdev_priv(dev);
2207
2208 rtl8169_hw_reset(tp->mmio_addr);
2209
2210 /* Let's wait a bit while any (async) irq lands on */
2211 rtl8169_schedule_work(dev, rtl8169_reset_task);
2212}
2213
2214static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2215 u32 opts1)
2216{
2217 struct skb_shared_info *info = skb_shinfo(skb);
2218 unsigned int cur_frag, entry;
2219 struct TxDesc *txd;
2220
2221 entry = tp->cur_tx;
2222 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2223 skb_frag_t *frag = info->frags + cur_frag;
2224 dma_addr_t mapping;
2225 u32 status, len;
2226 void *addr;
2227
2228 entry = (entry + 1) % NUM_TX_DESC;
2229
2230 txd = tp->TxDescArray + entry;
2231 len = frag->size;
2232 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2233 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2234
2235 /* anti gcc 2.95.3 bugware (sic) */
2236 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2237
2238 txd->opts1 = cpu_to_le32(status);
2239 txd->addr = cpu_to_le64(mapping);
2240
2241 tp->tx_skb[entry].len = len;
2242 }
2243
2244 if (cur_frag) {
2245 tp->tx_skb[entry].skb = skb;
2246 txd->opts1 |= cpu_to_le32(LastFrag);
2247 }
2248
2249 return cur_frag;
2250}
2251
2252static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2253{
2254 if (dev->features & NETIF_F_TSO) {
7967168c 2255 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2256
2257 if (mss)
2258 return LargeSend | ((mss & MSSMask) << MSSShift);
2259 }
2260 if (skb->ip_summed == CHECKSUM_HW) {
2261 const struct iphdr *ip = skb->nh.iph;
2262
2263 if (ip->protocol == IPPROTO_TCP)
2264 return IPCS | TCPCS;
2265 else if (ip->protocol == IPPROTO_UDP)
2266 return IPCS | UDPCS;
2267 WARN_ON(1); /* we need a WARN() */
2268 }
2269 return 0;
2270}
2271
2272static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2273{
2274 struct rtl8169_private *tp = netdev_priv(dev);
2275 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2276 struct TxDesc *txd = tp->TxDescArray + entry;
2277 void __iomem *ioaddr = tp->mmio_addr;
2278 dma_addr_t mapping;
2279 u32 status, len;
2280 u32 opts1;
188f4af0 2281 int ret = NETDEV_TX_OK;
5b0384f4 2282
1da177e4 2283 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2284 if (netif_msg_drv(tp)) {
2285 printk(KERN_ERR
2286 "%s: BUG! Tx Ring full when queue awake!\n",
2287 dev->name);
2288 }
1da177e4
LT		 2289 goto err_stop;
2290 }
2291
2292 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2293 goto err_stop;
2294
2295 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2296
2297 frags = rtl8169_xmit_frags(tp, skb, opts1);
2298 if (frags) {
2299 len = skb_headlen(skb);
2300 opts1 |= FirstFrag;
2301 } else {
2302 len = skb->len;
2303
2304 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2305 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2306 goto err_update_stats;
2307 len = ETH_ZLEN;
2308 }
2309
2310 opts1 |= FirstFrag | LastFrag;
2311 tp->tx_skb[entry].skb = skb;
2312 }
2313
2314 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2315
2316 tp->tx_skb[entry].len = len;
2317 txd->addr = cpu_to_le64(mapping);
2318 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2319
2320 wmb();
2321
2322 /* anti gcc 2.95.3 bugware (sic) */
2323 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2324 txd->opts1 = cpu_to_le32(status);
2325
2326 dev->trans_start = jiffies;
2327
2328 tp->cur_tx += frags + 1;
2329
2330 smp_wmb();
2331
2332 RTL_W8(TxPoll, 0x40); /* set polling bit */
2333
2334 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2335 netif_stop_queue(dev);
2336 smp_rmb();
2337 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2338 netif_wake_queue(dev);
2339 }
2340
2341out:
2342 return ret;
2343
2344err_stop:
2345 netif_stop_queue(dev);
188f4af0 2346 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2347err_update_stats:
2348 tp->stats.tx_dropped++;
2349 goto out;
2350}
2351
2352static void rtl8169_pcierr_interrupt(struct net_device *dev)
2353{
2354 struct rtl8169_private *tp = netdev_priv(dev);
2355 struct pci_dev *pdev = tp->pci_dev;
2356 void __iomem *ioaddr = tp->mmio_addr;
2357 u16 pci_status, pci_cmd;
2358
2359 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2360 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2361
b57b7e5a
SH		 2362 if (netif_msg_intr(tp)) {
2363 printk(KERN_ERR
2364 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2365 dev->name, pci_cmd, pci_status);
2366 }
1da177e4
LT		 2367
2368 /*
2369 * The recovery sequence below admits a very elaborated explanation:
2370 * - it seems to work;
2371 * - I did not see what else could be done.
2372 *
2373 * Feel free to adjust to your needs.
2374 */
2375 pci_write_config_word(pdev, PCI_COMMAND,
2376 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2377
2378 pci_write_config_word(pdev, PCI_STATUS,
2379 pci_status & (PCI_STATUS_DETECTED_PARITY |
2380 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2381 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2382
2383 /* The infamous DAC f*ckup only happens at boot time */
2384 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2385 if (netif_msg_intr(tp))
2386 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2387 tp->cp_cmd &= ~PCIDAC;
2388 RTL_W16(CPlusCmd, tp->cp_cmd);
2389 dev->features &= ~NETIF_F_HIGHDMA;
2390 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2391 }
2392
2393 rtl8169_hw_reset(ioaddr);
2394}
2395
2396static void
2397rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2398 void __iomem *ioaddr)
2399{
2400 unsigned int dirty_tx, tx_left;
2401
2402 assert(dev != NULL);
2403 assert(tp != NULL);
2404 assert(ioaddr != NULL);
2405
2406 dirty_tx = tp->dirty_tx;
2407 smp_rmb();
2408 tx_left = tp->cur_tx - dirty_tx;
2409
2410 while (tx_left > 0) {
2411 unsigned int entry = dirty_tx % NUM_TX_DESC;
2412 struct ring_info *tx_skb = tp->tx_skb + entry;
2413 u32 len = tx_skb->len;
2414 u32 status;
2415
2416 rmb();
2417 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2418 if (status & DescOwn)
2419 break;
2420
2421 tp->stats.tx_bytes += len;
2422 tp->stats.tx_packets++;
2423
2424 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2425
2426 if (status & LastFrag) {
2427 dev_kfree_skb_irq(tx_skb->skb);
2428 tx_skb->skb = NULL;
2429 }
2430 dirty_tx++;
2431 tx_left--;
2432 }
2433
2434 if (tp->dirty_tx != dirty_tx) {
2435 tp->dirty_tx = dirty_tx;
2436 smp_wmb();
2437 if (netif_queue_stopped(dev) &&
2438 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2439 netif_wake_queue(dev);
2440 }
2441 }
2442}
2443
126fa4b9
FR		 2444static inline int rtl8169_fragmented_frame(u32 status)
2445{
2446 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2447}
2448
1da177e4
LT		 2449static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2450{
2451 u32 opts1 = le32_to_cpu(desc->opts1);
2452 u32 status = opts1 & RxProtoMask;
2453
2454 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2455 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2456 ((status == RxProtoIP) && !(opts1 & IPFail)))
2457 skb->ip_summed = CHECKSUM_UNNECESSARY;
2458 else
2459 skb->ip_summed = CHECKSUM_NONE;
2460}
2461
2462static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
bcf0bf90
FR		 2463 struct RxDesc *desc, int rx_buf_sz,
2464 unsigned int align)
1da177e4
LT		 2465{
2466 int ret = -1;
2467
2468 if (pkt_size < rx_copybreak) {
2469 struct sk_buff *skb;
2470
bcf0bf90 2471 skb = dev_alloc_skb(pkt_size + align);
1da177e4 2472 if (skb) {
bcf0bf90 2473 skb_reserve(skb, align);
689be439 2474 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2475 *sk_buff = skb;
2476 rtl8169_mark_to_asic(desc, rx_buf_sz);
2477 ret = 0;
2478 }
2479 }
2480 return ret;
2481}
2482
2483static int
2484rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2485 void __iomem *ioaddr)
2486{
2487 unsigned int cur_rx, rx_left;
2488 unsigned int delta, count;
2489
2490 assert(dev != NULL);
2491 assert(tp != NULL);
2492 assert(ioaddr != NULL);
2493
2494 cur_rx = tp->cur_rx;
2495 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2496 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2497
4dcb7d33 2498 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2499 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2500 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2501 u32 status;
2502
2503 rmb();
126fa4b9 2504 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2505
2506 if (status & DescOwn)
2507 break;
4dcb7d33 2508 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2509 if (netif_msg_rx_err(tp)) {
2510 printk(KERN_INFO
2511 "%s: Rx ERROR. status = %08x\n",
2512 dev->name, status);
2513 }
1da177e4
LT		 2514 tp->stats.rx_errors++;
2515 if (status & (RxRWT | RxRUNT))
2516 tp->stats.rx_length_errors++;
2517 if (status & RxCRC)
2518 tp->stats.rx_crc_errors++;
9dccf611
FR		 2519 if (status & RxFOVF) {
2520 rtl8169_schedule_work(dev, rtl8169_reset_task);
2521 tp->stats.rx_fifo_errors++;
2522 }
126fa4b9 2523 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2524 } else {
1da177e4
LT		 2525 struct sk_buff *skb = tp->Rx_skbuff[entry];
2526 int pkt_size = (status & 0x00001FFF) - 4;
2527 void (*pci_action)(struct pci_dev *, dma_addr_t,
2528 size_t, int) = pci_dma_sync_single_for_device;
2529
126fa4b9
FR		 2530 /*
2531 * The driver does not support incoming fragmented
2532 * frames. They are seen as a symptom of over-mtu
2533 * sized frames.
2534 */
2535 if (unlikely(rtl8169_fragmented_frame(status))) {
2536 tp->stats.rx_dropped++;
2537 tp->stats.rx_length_errors++;
2538 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2539 continue;
126fa4b9
FR		 2540 }
2541
1da177e4 2542 rtl8169_rx_csum(skb, desc);
bcf0bf90 2543
1da177e4
LT		 2544 pci_dma_sync_single_for_cpu(tp->pci_dev,
2545 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2546 PCI_DMA_FROMDEVICE);
2547
2548 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
bcf0bf90 2549 tp->rx_buf_sz, tp->align)) {
1da177e4
LT		 2550 pci_action = pci_unmap_single;
2551 tp->Rx_skbuff[entry] = NULL;
2552 }
2553
2554 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2555 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2556
2557 skb->dev = dev;
2558 skb_put(skb, pkt_size);
2559 skb->protocol = eth_type_trans(skb, dev);
2560
2561 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2562 rtl8169_rx_skb(skb);
2563
2564 dev->last_rx = jiffies;
2565 tp->stats.rx_bytes += pkt_size;
2566 tp->stats.rx_packets++;
2567 }
1da177e4
LT		 2568 }
2569
2570 count = cur_rx - tp->cur_rx;
2571 tp->cur_rx = cur_rx;
2572
2573 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2574 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2575 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2576 tp->dirty_rx += delta;
2577
2578 /*
2579 * FIXME: until there is periodic timer to try and refill the ring,
2580 * a temporary shortage may definitely kill the Rx process.
2581 * - disable the asic to try and avoid an overflow and kick it again
2582 * after refill ?
2583 * - how do others driver handle this condition (Uh oh...).
2584 */
b57b7e5a 2585 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2586 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2587
2588 return count;
2589}
2590
2591/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2592static irqreturn_t
2593rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2594{
2595 struct net_device *dev = (struct net_device *) dev_instance;
2596 struct rtl8169_private *tp = netdev_priv(dev);
2597 int boguscnt = max_interrupt_work;
2598 void __iomem *ioaddr = tp->mmio_addr;
2599 int status;
2600 int handled = 0;
2601
2602 do {
2603 status = RTL_R16(IntrStatus);
2604
2605 /* hotplug/major error/no more work/shared irq */
2606 if ((status == 0xFFFF) || !status)
2607 break;
2608
2609 handled = 1;
2610
2611 if (unlikely(!netif_running(dev))) {
2612 rtl8169_asic_down(ioaddr);
2613 goto out;
2614 }
2615
2616 status &= tp->intr_mask;
2617 RTL_W16(IntrStatus,
2618 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2619
2620 if (!(status & rtl8169_intr_mask))
2621 break;
2622
2623 if (unlikely(status & SYSErr)) {
2624 rtl8169_pcierr_interrupt(dev);
2625 break;
2626 }
2627
2628 if (status & LinkChg)
2629 rtl8169_check_link_status(dev, tp, ioaddr);
2630
2631#ifdef CONFIG_R8169_NAPI
2632 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2633 tp->intr_mask = ~rtl8169_napi_event;
2634
2635 if (likely(netif_rx_schedule_prep(dev)))
2636 __netif_rx_schedule(dev);
b57b7e5a 2637 else if (netif_msg_intr(tp)) {
1da177e4 2638 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2639 dev->name, status);
1da177e4
LT		 2640 }
2641 break;
2642#else
2643 /* Rx interrupt */
2644 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2645 rtl8169_rx_interrupt(dev, tp, ioaddr);
2646 }
2647 /* Tx interrupt */
2648 if (status & (TxOK | TxErr))
2649 rtl8169_tx_interrupt(dev, tp, ioaddr);
2650#endif
2651
2652 boguscnt--;
2653 } while (boguscnt > 0);
2654
2655 if (boguscnt <= 0) {
7c8b2eb4 2656 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2657 printk(KERN_WARNING
2658 "%s: Too much work at interrupt!\n", dev->name);
2659 }
1da177e4
LT		 2660 /* Clear all interrupt sources. */
2661 RTL_W16(IntrStatus, 0xffff);
2662 }
2663out:
2664 return IRQ_RETVAL(handled);
2665}
2666
2667#ifdef CONFIG_R8169_NAPI
2668static int rtl8169_poll(struct net_device *dev, int *budget)
2669{
2670 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2671 struct rtl8169_private *tp = netdev_priv(dev);
2672 void __iomem *ioaddr = tp->mmio_addr;
2673
2674 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2675 rtl8169_tx_interrupt(dev, tp, ioaddr);
2676
2677 *budget -= work_done;
2678 dev->quota -= work_done;
2679
2680 if (work_done < work_to_do) {
2681 netif_rx_complete(dev);
2682 tp->intr_mask = 0xffff;
2683 /*
2684 * 20040426: the barrier is not strictly required but the
2685 * behavior of the irq handler could be less predictable
2686 * without it. Btw, the lack of flush for the posted pci
2687 * write is safe - FR
2688 */
2689 smp_wmb();
2690 RTL_W16(IntrMask, rtl8169_intr_mask);
2691 }
2692
2693 return (work_done >= work_to_do);
2694}
2695#endif
2696
2697static void rtl8169_down(struct net_device *dev)
2698{
2699 struct rtl8169_private *tp = netdev_priv(dev);
2700 void __iomem *ioaddr = tp->mmio_addr;
2701 unsigned int poll_locked = 0;
2702
2703 rtl8169_delete_timer(dev);
2704
2705 netif_stop_queue(dev);
2706
2707 flush_scheduled_work();
2708
2709core_down:
2710 spin_lock_irq(&tp->lock);
2711
2712 rtl8169_asic_down(ioaddr);
2713
2714 /* Update the error counts. */
2715 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2716 RTL_W32(RxMissed, 0);
2717
2718 spin_unlock_irq(&tp->lock);
2719
2720 synchronize_irq(dev->irq);
2721
2722 if (!poll_locked) {
2723 netif_poll_disable(dev);
2724 poll_locked++;
2725 }
2726
2727 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2728 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2729
2730 /*
2731 * And now for the 50k$ question: are IRQ disabled or not ?
2732 *
2733 * Two paths lead here:
2734 * 1) dev->close
2735 * -> netif_running() is available to sync the current code and the
2736 * IRQ handler. See rtl8169_interrupt for details.
2737 * 2) dev->change_mtu
2738 * -> rtl8169_poll can not be issued again and re-enable the
2739 * interruptions. Let's simply issue the IRQ down sequence again.
2740 */
2741 if (RTL_R16(IntrMask))
2742 goto core_down;
2743
2744 rtl8169_tx_clear(tp);
2745
2746 rtl8169_rx_clear(tp);
2747}
2748
2749static int rtl8169_close(struct net_device *dev)
2750{
2751 struct rtl8169_private *tp = netdev_priv(dev);
2752 struct pci_dev *pdev = tp->pci_dev;
2753
2754 rtl8169_down(dev);
2755
2756 free_irq(dev->irq, dev);
2757
2758 netif_poll_enable(dev);
2759
2760 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2761 tp->RxPhyAddr);
2762 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2763 tp->TxPhyAddr);
2764 tp->TxDescArray = NULL;
2765 tp->RxDescArray = NULL;
2766
2767 return 0;
2768}
2769
2770static void
2771rtl8169_set_rx_mode(struct net_device *dev)
2772{
2773 struct rtl8169_private *tp = netdev_priv(dev);
2774 void __iomem *ioaddr = tp->mmio_addr;
2775 unsigned long flags;
2776 u32 mc_filter[2]; /* Multicast hash filter */
2777 int i, rx_mode;
2778 u32 tmp = 0;
2779
2780 if (dev->flags & IFF_PROMISC) {
2781 /* Unconditionally log net taps. */
b57b7e5a
SH		 2782 if (netif_msg_link(tp)) {
2783 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2784 dev->name);
2785 }
1da177e4
LT		 2786 rx_mode =
2787 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2788 AcceptAllPhys;
2789 mc_filter[1] = mc_filter[0] = 0xffffffff;
2790 } else if ((dev->mc_count > multicast_filter_limit)
2791 || (dev->flags & IFF_ALLMULTI)) {
2792 /* Too many to filter perfectly -- accept all multicasts. */
2793 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2794 mc_filter[1] = mc_filter[0] = 0xffffffff;
2795 } else {
2796 struct dev_mc_list *mclist;
2797 rx_mode = AcceptBroadcast | AcceptMyPhys;
2798 mc_filter[1] = mc_filter[0] = 0;
2799 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2800 i++, mclist = mclist->next) {
2801 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2802 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2803 rx_mode |= AcceptMulticast;
2804 }
2805 }
2806
2807 spin_lock_irqsave(&tp->lock, flags);
2808
2809 tmp = rtl8169_rx_config | rx_mode |
2810 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2811
bcf0bf90
FR		 2812 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2813 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2814 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2815 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2816 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2817 mc_filter[0] = 0xffffffff;
2818 mc_filter[1] = 0xffffffff;
2819 }
2820
1da177e4
LT		 2821 RTL_W32(RxConfig, tmp);
2822 RTL_W32(MAR0 + 0, mc_filter[0]);
2823 RTL_W32(MAR0 + 4, mc_filter[1]);
2824
2825 spin_unlock_irqrestore(&tp->lock, flags);
2826}
2827
2828/**
2829 * rtl8169_get_stats - Get rtl8169 read/write statistics
2830 * @dev: The Ethernet Device to get statistics for
2831 *
2832 * Get TX/RX statistics for rtl8169
2833 */
2834static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2835{
2836 struct rtl8169_private *tp = netdev_priv(dev);
2837 void __iomem *ioaddr = tp->mmio_addr;
2838 unsigned long flags;
2839
2840 if (netif_running(dev)) {
2841 spin_lock_irqsave(&tp->lock, flags);
2842 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2843 RTL_W32(RxMissed, 0);
2844 spin_unlock_irqrestore(&tp->lock, flags);
2845 }
5b0384f4 2846
1da177e4
LT		 2847 return &tp->stats;
2848}
2849
5d06a99f
FR		 2850#ifdef CONFIG_PM
2851
2852static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2853{
2854 struct net_device *dev = pci_get_drvdata(pdev);
2855 struct rtl8169_private *tp = netdev_priv(dev);
2856 void __iomem *ioaddr = tp->mmio_addr;
2857
2858 if (!netif_running(dev))
2859 goto out;
2860
2861 netif_device_detach(dev);
2862 netif_stop_queue(dev);
2863
2864 spin_lock_irq(&tp->lock);
2865
2866 rtl8169_asic_down(ioaddr);
2867
2868 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2869 RTL_W32(RxMissed, 0);
2870
2871 spin_unlock_irq(&tp->lock);
2872
2873 pci_save_state(pdev);
61a4dcc2 2874 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f
FR		 2875 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2876out:
2877 return 0;
2878}
2879
2880static int rtl8169_resume(struct pci_dev *pdev)
2881{
2882 struct net_device *dev = pci_get_drvdata(pdev);
2883
2884 if (!netif_running(dev))
2885 goto out;
2886
2887 netif_device_attach(dev);
2888
2889 pci_set_power_state(pdev, PCI_D0);
2890 pci_restore_state(pdev);
61a4dcc2 2891 pci_enable_wake(pdev, PCI_D0, 0);
5d06a99f
FR		 2892
2893 rtl8169_schedule_work(dev, rtl8169_reset_task);
2894out:
2895 return 0;
2896}
2897
2898#endif /* CONFIG_PM */
2899
1da177e4
LT		 2900static struct pci_driver rtl8169_pci_driver = {
2901 .name = MODULENAME,
2902 .id_table = rtl8169_pci_tbl,
2903 .probe = rtl8169_init_one,
2904 .remove = __devexit_p(rtl8169_remove_one),
2905#ifdef CONFIG_PM
2906 .suspend = rtl8169_suspend,
2907 .resume = rtl8169_resume,
2908#endif
2909};
2910
2911static int __init
2912rtl8169_init_module(void)
2913{
2914 return pci_module_init(&rtl8169_pci_driver);
2915}
2916
2917static void __exit
2918rtl8169_cleanup_module(void)
2919{
2920 pci_unregister_driver(&rtl8169_pci_driver);
2921}
2922
2923module_init(rtl8169_init_module);
2924module_exit(rtl8169_cleanup_module);
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