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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
116static int max_interrupt_work = 20;
117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
120static int multicast_filter_limit = 32;
121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
153 RTL_GIGA_MAC_VER_B = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */
155 RTL_GIGA_MAC_VER_D = 0x01,
156 RTL_GIGA_MAC_VER_E = 0x02,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
158};
159
160enum phy_version {
161 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
162 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
165 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
167};
168
169
170#define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
172
3c6bee1d 173static const struct {
1da177e4
LT		 174 const char *name;
175 u8 mac_version;
176 u32 RxConfigMask; /* Clears the bits supported by this chip */
177} rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
182};
183#undef _R
184
185static struct pci_device_id rtl8169_pci_tbl[] = {
53456f60
FR		 186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
187 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
188 { PCI_DEVICE(0x16ec, 0x0116), },
86f0cd50 189 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195static int rx_copybreak = 200;
196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4
LT		 200
201enum RTL8169_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 204 CounterAddrLow = 0x10,
205 CounterAddrHigh = 0x14,
1da177e4
LT		 206 TxDescStartAddrLow = 0x20,
207 TxDescStartAddrHigh = 0x24,
208 TxHDescStartAddrLow = 0x28,
209 TxHDescStartAddrHigh = 0x2c,
210 FLASH = 0x30,
211 ERSR = 0x36,
212 ChipCmd = 0x37,
213 TxPoll = 0x38,
214 IntrMask = 0x3C,
215 IntrStatus = 0x3E,
216 TxConfig = 0x40,
217 RxConfig = 0x44,
218 RxMissed = 0x4C,
219 Cfg9346 = 0x50,
220 Config0 = 0x51,
221 Config1 = 0x52,
222 Config2 = 0x53,
223 Config3 = 0x54,
224 Config4 = 0x55,
225 Config5 = 0x56,
226 MultiIntr = 0x5C,
227 PHYAR = 0x60,
228 TBICSR = 0x64,
229 TBI_ANAR = 0x68,
230 TBI_LPAR = 0x6A,
231 PHYstatus = 0x6C,
232 RxMaxSize = 0xDA,
233 CPlusCmd = 0xE0,
234 IntrMitigate = 0xE2,
235 RxDescAddrLow = 0xE4,
236 RxDescAddrHigh = 0xE8,
237 EarlyTxThres = 0xEC,
238 FuncEvent = 0xF0,
239 FuncEventMask = 0xF4,
240 FuncPresetState = 0xF8,
241 FuncForceEvent = 0xFC,
242};
243
244enum RTL8169_register_content {
245 /* InterruptStatusBits */
246 SYSErr = 0x8000,
247 PCSTimeout = 0x4000,
248 SWInt = 0x0100,
249 TxDescUnavail = 0x80,
250 RxFIFOOver = 0x40,
251 LinkChg = 0x20,
252 RxOverflow = 0x10,
253 TxErr = 0x08,
254 TxOK = 0x04,
255 RxErr = 0x02,
256 RxOK = 0x01,
257
258 /* RxStatusDesc */
259 RxRES = 0x00200000,
260 RxCRC = 0x00080000,
261 RxRUNT = 0x00100000,
262 RxRWT = 0x00400000,
263
264 /* ChipCmdBits */
265 CmdReset = 0x10,
266 CmdRxEnb = 0x08,
267 CmdTxEnb = 0x04,
268 RxBufEmpty = 0x01,
269
270 /* Cfg9346Bits */
271 Cfg9346_Lock = 0x00,
272 Cfg9346_Unlock = 0xC0,
273
274 /* rx_mode_bits */
275 AcceptErr = 0x20,
276 AcceptRunt = 0x10,
277 AcceptBroadcast = 0x08,
278 AcceptMulticast = 0x04,
279 AcceptMyPhys = 0x02,
280 AcceptAllPhys = 0x01,
281
282 /* RxConfigBits */
283 RxCfgFIFOShift = 13,
284 RxCfgDMAShift = 8,
285
286 /* TxConfigBits */
287 TxInterFrameGapShift = 24,
288 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
289
5d06a99f
FR		 290 /* Config1 register p.24 */
291 PMEnable = (1 << 0), /* Power Management Enable */
292
61a4dcc2
FR		 293 /* Config3 register p.25 */
294 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
295 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
296
5d06a99f 297 /* Config5 register p.27 */
61a4dcc2
FR		 298 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
299 MWF = (1 << 5), /* Accept Multicast wakeup frame */
300 UWF = (1 << 4), /* Accept Unicast wakeup frame */
301 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 302 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
303
1da177e4
LT		 304 /* TBICSR p.28 */
305 TBIReset = 0x80000000,
306 TBILoopback = 0x40000000,
307 TBINwEnable = 0x20000000,
308 TBINwRestart = 0x10000000,
309 TBILinkOk = 0x02000000,
310 TBINwComplete = 0x01000000,
311
312 /* CPlusCmd p.31 */
313 RxVlan = (1 << 6),
314 RxChkSum = (1 << 5),
315 PCIDAC = (1 << 4),
316 PCIMulRW = (1 << 3),
317
318 /* rtl8169_PHYstatus */
319 TBI_Enable = 0x80,
320 TxFlowCtrl = 0x40,
321 RxFlowCtrl = 0x20,
322 _1000bpsF = 0x10,
323 _100bps = 0x08,
324 _10bps = 0x04,
325 LinkStatus = 0x02,
326 FullDup = 0x01,
327
328 /* GIGABIT_PHY_registers */
329 PHY_CTRL_REG = 0,
330 PHY_STAT_REG = 1,
331 PHY_AUTO_NEGO_REG = 4,
332 PHY_1000_CTRL_REG = 9,
333
334 /* GIGABIT_PHY_REG_BIT */
335 PHY_Restart_Auto_Nego = 0x0200,
336 PHY_Enable_Auto_Nego = 0x1000,
337
338 /* PHY_STAT_REG = 1 */
339 PHY_Auto_Neco_Comp = 0x0020,
340
341 /* PHY_AUTO_NEGO_REG = 4 */
342 PHY_Cap_10_Half = 0x0020,
343 PHY_Cap_10_Full = 0x0040,
344 PHY_Cap_100_Half = 0x0080,
345 PHY_Cap_100_Full = 0x0100,
346
347 /* PHY_1000_CTRL_REG = 9 */
348 PHY_Cap_1000_Full = 0x0200,
349
350 PHY_Cap_Null = 0x0,
351
352 /* _MediaType */
353 _10_Half = 0x01,
354 _10_Full = 0x02,
355 _100_Half = 0x04,
356 _100_Full = 0x08,
357 _1000_Full = 0x10,
358
359 /* _TBICSRBit */
360 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 361
362 /* DumpCounterCommand */
363 CounterDump = 0x8,
1da177e4
LT		 364};
365
366enum _DescStatusBit {
367 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
368 RingEnd = (1 << 30), /* End of descriptor ring */
369 FirstFrag = (1 << 29), /* First segment of a packet */
370 LastFrag = (1 << 28), /* Final segment of a packet */
371
372 /* Tx private */
373 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
374 MSSShift = 16, /* MSS value position */
375 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
376 IPCS = (1 << 18), /* Calculate IP checksum */
377 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
378 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
379 TxVlanTag = (1 << 17), /* Add VLAN tag */
380
381 /* Rx private */
382 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
383 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
384
385#define RxProtoUDP (PID1)
386#define RxProtoTCP (PID0)
387#define RxProtoIP (PID1 | PID0)
388#define RxProtoMask RxProtoIP
389
390 IPFail = (1 << 16), /* IP checksum failed */
391 UDPFail = (1 << 15), /* UDP/IP checksum failed */
392 TCPFail = (1 << 14), /* TCP/IP checksum failed */
393 RxVlanTag = (1 << 16), /* VLAN tag available */
394};
395
396#define RsvdMask 0x3fffc000
397
398struct TxDesc {
399 u32 opts1;
400 u32 opts2;
401 u64 addr;
402};
403
404struct RxDesc {
405 u32 opts1;
406 u32 opts2;
407 u64 addr;
408};
409
410struct ring_info {
411 struct sk_buff *skb;
412 u32 len;
413 u8 __pad[sizeof(void *) - sizeof(u32)];
414};
415
416struct rtl8169_private {
417 void __iomem *mmio_addr; /* memory map physical address */
418 struct pci_dev *pci_dev; /* Index of PCI device */
419 struct net_device_stats stats; /* statistics of net device */
420 spinlock_t lock; /* spin lock flag */
b57b7e5a 421 u32 msg_enable;
1da177e4
LT		 422 int chipset;
423 int mac_version;
424 int phy_version;
425 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
426 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
427 u32 dirty_rx;
428 u32 dirty_tx;
429 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
430 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
431 dma_addr_t TxPhyAddr;
432 dma_addr_t RxPhyAddr;
433 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
434 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
435 unsigned rx_buf_sz;
436 struct timer_list timer;
437 u16 cp_cmd;
438 u16 intr_mask;
439 int phy_auto_nego_reg;
440 int phy_1000_ctrl_reg;
441#ifdef CONFIG_R8169_VLAN
442 struct vlan_group *vlgrp;
443#endif
444 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
445 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
446 void (*phy_reset_enable)(void __iomem *);
447 unsigned int (*phy_reset_pending)(void __iomem *);
448 unsigned int (*link_ok)(void __iomem *);
449 struct work_struct task;
61a4dcc2 450 unsigned wol_enabled : 1;
1da177e4
LT		 451};
452
979b6c13 453MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 454MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
455module_param_array(media, int, &num_media, 0);
df0a1bf6 456MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 457module_param(rx_copybreak, int, 0);
1b7efd58 458MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 459module_param(use_dac, int, 0);
460MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 461module_param_named(debug, debug.msg_enable, int, 0);
462MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 463MODULE_LICENSE("GPL");
464MODULE_VERSION(RTL8169_VERSION);
465
466static int rtl8169_open(struct net_device *dev);
467static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
468static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
469 struct pt_regs *regs);
470static int rtl8169_init_ring(struct net_device *dev);
471static void rtl8169_hw_start(struct net_device *dev);
472static int rtl8169_close(struct net_device *dev);
473static void rtl8169_set_rx_mode(struct net_device *dev);
474static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 475static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 476static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
477 void __iomem *);
4dcb7d33 478static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 479static void rtl8169_down(struct net_device *dev);
480
481#ifdef CONFIG_R8169_NAPI
482static int rtl8169_poll(struct net_device *dev, int *budget);
483#endif
484
485static const u16 rtl8169_intr_mask =
486 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
487static const u16 rtl8169_napi_event =
488 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
489static const unsigned int rtl8169_rx_config =
490 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
491
492#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
493#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
494#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
495#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
496
497static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
498{
499 int i;
500
501 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 502
2371408c 503 for (i = 20; i > 0; i--) {
1da177e4
LT		 504 /* Check if the RTL8169 has completed writing to the specified MII register */
505 if (!(RTL_R32(PHYAR) & 0x80000000))
506 break;
2371408c 507 udelay(25);
1da177e4
LT		 508 }
509}
510
511static int mdio_read(void __iomem *ioaddr, int RegAddr)
512{
513 int i, value = -1;
514
515 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 516
2371408c 517 for (i = 20; i > 0; i--) {
1da177e4
LT		 518 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
519 if (RTL_R32(PHYAR) & 0x80000000) {
520 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
521 break;
522 }
2371408c 523 udelay(25);
1da177e4
LT		 524 }
525 return value;
526}
527
528static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
529{
530 RTL_W16(IntrMask, 0x0000);
531
532 RTL_W16(IntrStatus, 0xffff);
533}
534
535static void rtl8169_asic_down(void __iomem *ioaddr)
536{
537 RTL_W8(ChipCmd, 0x00);
538 rtl8169_irq_mask_and_ack(ioaddr);
539 RTL_R16(CPlusCmd);
540}
541
542static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
543{
544 return RTL_R32(TBICSR) & TBIReset;
545}
546
547static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
548{
549 return mdio_read(ioaddr, 0) & 0x8000;
550}
551
552static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
553{
554 return RTL_R32(TBICSR) & TBILinkOk;
555}
556
557static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
558{
559 return RTL_R8(PHYstatus) & LinkStatus;
560}
561
562static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
563{
564 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
565}
566
567static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
568{
569 unsigned int val;
570
571 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
572 mdio_write(ioaddr, PHY_CTRL_REG, val);
573}
574
575static void rtl8169_check_link_status(struct net_device *dev,
576 struct rtl8169_private *tp, void __iomem *ioaddr)
577{
578 unsigned long flags;
579
580 spin_lock_irqsave(&tp->lock, flags);
581 if (tp->link_ok(ioaddr)) {
582 netif_carrier_on(dev);
b57b7e5a
SH		 583 if (netif_msg_ifup(tp))
584 printk(KERN_INFO PFX "%s: link up\n", dev->name);
585 } else {
586 if (netif_msg_ifdown(tp))
587 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 588 netif_carrier_off(dev);
b57b7e5a 589 }
1da177e4
LT		 590 spin_unlock_irqrestore(&tp->lock, flags);
591}
592
593static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
594{
595 struct {
596 u16 speed;
597 u8 duplex;
598 u8 autoneg;
599 u8 media;
600 } link_settings[] = {
601 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
602 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
603 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
604 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
605 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
606 /* Make TBI happy */
607 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
608 }, *p;
609 unsigned char option;
610
611 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
612
b57b7e5a 613 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 614 printk(KERN_WARNING PFX "media option is deprecated.\n");
615
616 for (p = link_settings; p->media != 0xff; p++) {
617 if (p->media == option)
618 break;
619 }
620 *autoneg = p->autoneg;
621 *speed = p->speed;
622 *duplex = p->duplex;
623}
624
61a4dcc2
FR		 625static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
626{
627 struct rtl8169_private *tp = netdev_priv(dev);
628 void __iomem *ioaddr = tp->mmio_addr;
629 u8 options;
630
631 wol->wolopts = 0;
632
633#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
634 wol->supported = WAKE_ANY;
635
636 spin_lock_irq(&tp->lock);
637
638 options = RTL_R8(Config1);
639 if (!(options & PMEnable))
640 goto out_unlock;
641
642 options = RTL_R8(Config3);
643 if (options & LinkUp)
644 wol->wolopts |= WAKE_PHY;
645 if (options & MagicPacket)
646 wol->wolopts |= WAKE_MAGIC;
647
648 options = RTL_R8(Config5);
649 if (options & UWF)
650 wol->wolopts |= WAKE_UCAST;
651 if (options & BWF)
652 wol->wolopts |= WAKE_BCAST;
653 if (options & MWF)
654 wol->wolopts |= WAKE_MCAST;
655
656out_unlock:
657 spin_unlock_irq(&tp->lock);
658}
659
660static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
661{
662 struct rtl8169_private *tp = netdev_priv(dev);
663 void __iomem *ioaddr = tp->mmio_addr;
664 int i;
665 static struct {
666 u32 opt;
667 u16 reg;
668 u8 mask;
669 } cfg[] = {
670 { WAKE_ANY, Config1, PMEnable },
671 { WAKE_PHY, Config3, LinkUp },
672 { WAKE_MAGIC, Config3, MagicPacket },
673 { WAKE_UCAST, Config5, UWF },
674 { WAKE_BCAST, Config5, BWF },
675 { WAKE_MCAST, Config5, MWF },
676 { WAKE_ANY, Config5, LanWake }
677 };
678
679 spin_lock_irq(&tp->lock);
680
681 RTL_W8(Cfg9346, Cfg9346_Unlock);
682
683 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
684 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
685 if (wol->wolopts & cfg[i].opt)
686 options |= cfg[i].mask;
687 RTL_W8(cfg[i].reg, options);
688 }
689
690 RTL_W8(Cfg9346, Cfg9346_Lock);
691
692 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
693
694 spin_unlock_irq(&tp->lock);
695
696 return 0;
697}
698
1da177e4
LT		 699static void rtl8169_get_drvinfo(struct net_device *dev,
700 struct ethtool_drvinfo *info)
701{
702 struct rtl8169_private *tp = netdev_priv(dev);
703
704 strcpy(info->driver, MODULENAME);
705 strcpy(info->version, RTL8169_VERSION);
706 strcpy(info->bus_info, pci_name(tp->pci_dev));
707}
708
709static int rtl8169_get_regs_len(struct net_device *dev)
710{
711 return R8169_REGS_SIZE;
712}
713
714static int rtl8169_set_speed_tbi(struct net_device *dev,
715 u8 autoneg, u16 speed, u8 duplex)
716{
717 struct rtl8169_private *tp = netdev_priv(dev);
718 void __iomem *ioaddr = tp->mmio_addr;
719 int ret = 0;
720 u32 reg;
721
722 reg = RTL_R32(TBICSR);
723 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
724 (duplex == DUPLEX_FULL)) {
725 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
726 } else if (autoneg == AUTONEG_ENABLE)
727 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
728 else {
b57b7e5a
SH		 729 if (netif_msg_link(tp)) {
730 printk(KERN_WARNING "%s: "
731 "incorrect speed setting refused in TBI mode\n",
732 dev->name);
733 }
1da177e4
LT		 734 ret = -EOPNOTSUPP;
735 }
736
737 return ret;
738}
739
740static int rtl8169_set_speed_xmii(struct net_device *dev,
741 u8 autoneg, u16 speed, u8 duplex)
742{
743 struct rtl8169_private *tp = netdev_priv(dev);
744 void __iomem *ioaddr = tp->mmio_addr;
745 int auto_nego, giga_ctrl;
746
747 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
748 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
749 PHY_Cap_100_Half | PHY_Cap_100_Full);
750 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
751 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
752
753 if (autoneg == AUTONEG_ENABLE) {
754 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
755 PHY_Cap_100_Half | PHY_Cap_100_Full);
756 giga_ctrl |= PHY_Cap_1000_Full;
757 } else {
758 if (speed == SPEED_10)
759 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
760 else if (speed == SPEED_100)
761 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
762 else if (speed == SPEED_1000)
763 giga_ctrl |= PHY_Cap_1000_Full;
764
765 if (duplex == DUPLEX_HALF)
766 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
726ecdcf
AG		 767
768 if (duplex == DUPLEX_FULL)
769 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
1da177e4
LT		 770 }
771
772 tp->phy_auto_nego_reg = auto_nego;
773 tp->phy_1000_ctrl_reg = giga_ctrl;
774
775 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
776 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
777 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
778 PHY_Restart_Auto_Nego);
779 return 0;
780}
781
782static int rtl8169_set_speed(struct net_device *dev,
783 u8 autoneg, u16 speed, u8 duplex)
784{
785 struct rtl8169_private *tp = netdev_priv(dev);
786 int ret;
787
788 ret = tp->set_speed(dev, autoneg, speed, duplex);
789
790 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
791 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
792
793 return ret;
794}
795
796static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
797{
798 struct rtl8169_private *tp = netdev_priv(dev);
799 unsigned long flags;
800 int ret;
801
802 spin_lock_irqsave(&tp->lock, flags);
803 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
804 spin_unlock_irqrestore(&tp->lock, flags);
805
806 return ret;
807}
808
809static u32 rtl8169_get_rx_csum(struct net_device *dev)
810{
811 struct rtl8169_private *tp = netdev_priv(dev);
812
813 return tp->cp_cmd & RxChkSum;
814}
815
816static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
817{
818 struct rtl8169_private *tp = netdev_priv(dev);
819 void __iomem *ioaddr = tp->mmio_addr;
820 unsigned long flags;
821
822 spin_lock_irqsave(&tp->lock, flags);
823
824 if (data)
825 tp->cp_cmd |= RxChkSum;
826 else
827 tp->cp_cmd &= ~RxChkSum;
828
829 RTL_W16(CPlusCmd, tp->cp_cmd);
830 RTL_R16(CPlusCmd);
831
832 spin_unlock_irqrestore(&tp->lock, flags);
833
834 return 0;
835}
836
837#ifdef CONFIG_R8169_VLAN
838
839static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
840 struct sk_buff *skb)
841{
842 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
843 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
844}
845
846static void rtl8169_vlan_rx_register(struct net_device *dev,
847 struct vlan_group *grp)
848{
849 struct rtl8169_private *tp = netdev_priv(dev);
850 void __iomem *ioaddr = tp->mmio_addr;
851 unsigned long flags;
852
853 spin_lock_irqsave(&tp->lock, flags);
854 tp->vlgrp = grp;
855 if (tp->vlgrp)
856 tp->cp_cmd |= RxVlan;
857 else
858 tp->cp_cmd &= ~RxVlan;
859 RTL_W16(CPlusCmd, tp->cp_cmd);
860 RTL_R16(CPlusCmd);
861 spin_unlock_irqrestore(&tp->lock, flags);
862}
863
864static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
865{
866 struct rtl8169_private *tp = netdev_priv(dev);
867 unsigned long flags;
868
869 spin_lock_irqsave(&tp->lock, flags);
870 if (tp->vlgrp)
871 tp->vlgrp->vlan_devices[vid] = NULL;
872 spin_unlock_irqrestore(&tp->lock, flags);
873}
874
875static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
876 struct sk_buff *skb)
877{
878 u32 opts2 = le32_to_cpu(desc->opts2);
879 int ret;
880
881 if (tp->vlgrp && (opts2 & RxVlanTag)) {
882 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
883 swab16(opts2 & 0xffff));
884 ret = 0;
885 } else
886 ret = -1;
887 desc->opts2 = 0;
888 return ret;
889}
890
891#else /* !CONFIG_R8169_VLAN */
892
893static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
894 struct sk_buff *skb)
895{
896 return 0;
897}
898
899static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
900 struct sk_buff *skb)
901{
902 return -1;
903}
904
905#endif
906
907static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
908{
909 struct rtl8169_private *tp = netdev_priv(dev);
910 void __iomem *ioaddr = tp->mmio_addr;
911 u32 status;
912
913 cmd->supported =
914 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
915 cmd->port = PORT_FIBRE;
916 cmd->transceiver = XCVR_INTERNAL;
917
918 status = RTL_R32(TBICSR);
919 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
920 cmd->autoneg = !!(status & TBINwEnable);
921
922 cmd->speed = SPEED_1000;
923 cmd->duplex = DUPLEX_FULL; /* Always set */
924}
925
926static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
927{
928 struct rtl8169_private *tp = netdev_priv(dev);
929 void __iomem *ioaddr = tp->mmio_addr;
930 u8 status;
931
932 cmd->supported = SUPPORTED_10baseT_Half |
933 SUPPORTED_10baseT_Full |
934 SUPPORTED_100baseT_Half |
935 SUPPORTED_100baseT_Full |
936 SUPPORTED_1000baseT_Full |
937 SUPPORTED_Autoneg |
938 SUPPORTED_TP;
939
940 cmd->autoneg = 1;
941 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
942
943 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
944 cmd->advertising |= ADVERTISED_10baseT_Half;
945 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
946 cmd->advertising |= ADVERTISED_10baseT_Full;
947 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
948 cmd->advertising |= ADVERTISED_100baseT_Half;
949 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
950 cmd->advertising |= ADVERTISED_100baseT_Full;
951 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
952 cmd->advertising |= ADVERTISED_1000baseT_Full;
953
954 status = RTL_R8(PHYstatus);
955
956 if (status & _1000bpsF)
957 cmd->speed = SPEED_1000;
958 else if (status & _100bps)
959 cmd->speed = SPEED_100;
960 else if (status & _10bps)
961 cmd->speed = SPEED_10;
962
963 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
964 DUPLEX_FULL : DUPLEX_HALF;
965}
966
967static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
968{
969 struct rtl8169_private *tp = netdev_priv(dev);
970 unsigned long flags;
971
972 spin_lock_irqsave(&tp->lock, flags);
973
974 tp->get_settings(dev, cmd);
975
976 spin_unlock_irqrestore(&tp->lock, flags);
977 return 0;
978}
979
980static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
981 void *p)
982{
983 struct rtl8169_private *tp = netdev_priv(dev);
984 unsigned long flags;
985
986 if (regs->len > R8169_REGS_SIZE)
987 regs->len = R8169_REGS_SIZE;
988
989 spin_lock_irqsave(&tp->lock, flags);
990 memcpy_fromio(p, tp->mmio_addr, regs->len);
991 spin_unlock_irqrestore(&tp->lock, flags);
992}
993
b57b7e5a
SH		 994static u32 rtl8169_get_msglevel(struct net_device *dev)
995{
996 struct rtl8169_private *tp = netdev_priv(dev);
997
998 return tp->msg_enable;
999}
1000
1001static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1002{
1003 struct rtl8169_private *tp = netdev_priv(dev);
1004
1005 tp->msg_enable = value;
1006}
1007
d4a3a0fc
SH		 1008static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1009 "tx_packets",
1010 "rx_packets",
1011 "tx_errors",
1012 "rx_errors",
1013 "rx_missed",
1014 "align_errors",
1015 "tx_single_collisions",
1016 "tx_multi_collisions",
1017 "unicast",
1018 "broadcast",
1019 "multicast",
1020 "tx_aborted",
1021 "tx_underrun",
1022};
1023
1024struct rtl8169_counters {
1025 u64 tx_packets;
1026 u64 rx_packets;
1027 u64 tx_errors;
1028 u32 rx_errors;
1029 u16 rx_missed;
1030 u16 align_errors;
1031 u32 tx_one_collision;
1032 u32 tx_multi_collision;
1033 u64 rx_unicast;
1034 u64 rx_broadcast;
1035 u32 rx_multicast;
1036 u16 tx_aborted;
1037 u16 tx_underun;
1038};
1039
1040static int rtl8169_get_stats_count(struct net_device *dev)
1041{
1042 return ARRAY_SIZE(rtl8169_gstrings);
1043}
1044
1045static void rtl8169_get_ethtool_stats(struct net_device *dev,
1046 struct ethtool_stats *stats, u64 *data)
1047{
1048 struct rtl8169_private *tp = netdev_priv(dev);
1049 void __iomem *ioaddr = tp->mmio_addr;
1050 struct rtl8169_counters *counters;
1051 dma_addr_t paddr;
1052 u32 cmd;
1053
1054 ASSERT_RTNL();
1055
1056 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1057 if (!counters)
1058 return;
1059
1060 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1061 cmd = (u64)paddr & DMA_32BIT_MASK;
1062 RTL_W32(CounterAddrLow, cmd);
1063 RTL_W32(CounterAddrLow, cmd | CounterDump);
1064
1065 while (RTL_R32(CounterAddrLow) & CounterDump) {
1066 if (msleep_interruptible(1))
1067 break;
1068 }
1069
1070 RTL_W32(CounterAddrLow, 0);
1071 RTL_W32(CounterAddrHigh, 0);
1072
1073 data[0] = le64_to_cpu(counters->tx_packets);
1074 data[1] = le64_to_cpu(counters->rx_packets);
1075 data[2] = le64_to_cpu(counters->tx_errors);
1076 data[3] = le32_to_cpu(counters->rx_errors);
1077 data[4] = le16_to_cpu(counters->rx_missed);
1078 data[5] = le16_to_cpu(counters->align_errors);
1079 data[6] = le32_to_cpu(counters->tx_one_collision);
1080 data[7] = le32_to_cpu(counters->tx_multi_collision);
1081 data[8] = le64_to_cpu(counters->rx_unicast);
1082 data[9] = le64_to_cpu(counters->rx_broadcast);
1083 data[10] = le32_to_cpu(counters->rx_multicast);
1084 data[11] = le16_to_cpu(counters->tx_aborted);
1085 data[12] = le16_to_cpu(counters->tx_underun);
1086
1087 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1088}
1089
1090static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1091{
1092 switch(stringset) {
1093 case ETH_SS_STATS:
1094 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1095 break;
1096 }
1097}
1098
1099
1da177e4
LT		 1100static struct ethtool_ops rtl8169_ethtool_ops = {
1101 .get_drvinfo = rtl8169_get_drvinfo,
1102 .get_regs_len = rtl8169_get_regs_len,
1103 .get_link = ethtool_op_get_link,
1104 .get_settings = rtl8169_get_settings,
1105 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1106 .get_msglevel = rtl8169_get_msglevel,
1107 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1108 .get_rx_csum = rtl8169_get_rx_csum,
1109 .set_rx_csum = rtl8169_set_rx_csum,
1110 .get_tx_csum = ethtool_op_get_tx_csum,
1111 .set_tx_csum = ethtool_op_set_tx_csum,
1112 .get_sg = ethtool_op_get_sg,
1113 .set_sg = ethtool_op_set_sg,
1114 .get_tso = ethtool_op_get_tso,
1115 .set_tso = ethtool_op_set_tso,
1116 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1117 .get_wol = rtl8169_get_wol,
1118 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1119 .get_strings = rtl8169_get_strings,
1120 .get_stats_count = rtl8169_get_stats_count,
1121 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1122 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1123};
1124
1125static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1126 int bitval)
1127{
1128 int val;
1129
1130 val = mdio_read(ioaddr, reg);
1131 val = (bitval == 1) ?
1132 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1133 mdio_write(ioaddr, reg, val & 0xffff);
1134}
1135
1136static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1137{
1138 const struct {
1139 u32 mask;
1140 int mac_version;
1141 } mac_info[] = {
1142 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
1143 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
1144 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
1145 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
1146 }, *p = mac_info;
1147 u32 reg;
1148
1149 reg = RTL_R32(TxConfig) & 0x7c800000;
1150 while ((reg & p->mask) != p->mask)
1151 p++;
1152 tp->mac_version = p->mac_version;
1153}
1154
1155static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1156{
1157 struct {
1158 int version;
1159 char *msg;
1160 } mac_print[] = {
1161 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1162 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1163 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1164 { 0, NULL }
1165 }, *p;
1166
1167 for (p = mac_print; p->msg; p++) {
1168 if (tp->mac_version == p->version) {
1169 dprintk("mac_version == %s (%04d)\n", p->msg,
1170 p->version);
1171 return;
1172 }
1173 }
1174 dprintk("mac_version == Unknown\n");
1175}
1176
1177static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1178{
1179 const struct {
1180 u16 mask;
1181 u16 set;
1182 int phy_version;
1183 } phy_info[] = {
1184 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1185 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1186 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1187 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1188 }, *p = phy_info;
1189 u16 reg;
1190
1191 reg = mdio_read(ioaddr, 3) & 0xffff;
1192 while ((reg & p->mask) != p->set)
1193 p++;
1194 tp->phy_version = p->phy_version;
1195}
1196
1197static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1198{
1199 struct {
1200 int version;
1201 char *msg;
1202 u32 reg;
1203 } phy_print[] = {
1204 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1205 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1206 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1207 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1208 { 0, NULL, 0x0000 }
1209 }, *p;
1210
1211 for (p = phy_print; p->msg; p++) {
1212 if (tp->phy_version == p->version) {
1213 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1214 return;
1215 }
1216 }
1217 dprintk("phy_version == Unknown\n");
1218}
1219
1220static void rtl8169_hw_phy_config(struct net_device *dev)
1221{
1222 struct rtl8169_private *tp = netdev_priv(dev);
1223 void __iomem *ioaddr = tp->mmio_addr;
1224 struct {
1225 u16 regs[5]; /* Beware of bit-sign propagation */
1226 } phy_magic[5] = { {
1227 { 0x0000, //w 4 15 12 0
1228 0x00a1, //w 3 15 0 00a1
1229 0x0008, //w 2 15 0 0008
1230 0x1020, //w 1 15 0 1020
1231 0x1000 } },{ //w 0 15 0 1000
1232 { 0x7000, //w 4 15 12 7
1233 0xff41, //w 3 15 0 ff41
1234 0xde60, //w 2 15 0 de60
1235 0x0140, //w 1 15 0 0140
1236 0x0077 } },{ //w 0 15 0 0077
1237 { 0xa000, //w 4 15 12 a
1238 0xdf01, //w 3 15 0 df01
1239 0xdf20, //w 2 15 0 df20
1240 0xff95, //w 1 15 0 ff95
1241 0xfa00 } },{ //w 0 15 0 fa00
1242 { 0xb000, //w 4 15 12 b
1243 0xff41, //w 3 15 0 ff41
1244 0xde20, //w 2 15 0 de20
1245 0x0140, //w 1 15 0 0140
1246 0x00bb } },{ //w 0 15 0 00bb
1247 { 0xf000, //w 4 15 12 f
1248 0xdf01, //w 3 15 0 df01
1249 0xdf20, //w 2 15 0 df20
1250 0xff95, //w 1 15 0 ff95
1251 0xbf00 } //w 0 15 0 bf00
1252 }
1253 }, *p = phy_magic;
1254 int i;
1255
1256 rtl8169_print_mac_version(tp);
1257 rtl8169_print_phy_version(tp);
1258
1259 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1260 return;
1261 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1262 return;
1263
1264 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1265 dprintk("Do final_reg2.cfg\n");
1266
1267 /* Shazam ! */
1268
1269 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1270 mdio_write(ioaddr, 31, 0x0001);
1271 mdio_write(ioaddr, 9, 0x273a);
1272 mdio_write(ioaddr, 14, 0x7bfb);
1273 mdio_write(ioaddr, 27, 0x841e);
1274
1275 mdio_write(ioaddr, 31, 0x0002);
1276 mdio_write(ioaddr, 1, 0x90d0);
1277 mdio_write(ioaddr, 31, 0x0000);
1278 return;
1279 }
1280
1281 /* phy config for RTL8169s mac_version C chip */
1282 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1283 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1284 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1285 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1286
1287 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1288 int val, pos = 4;
1289
1290 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1291 mdio_write(ioaddr, pos, val);
1292 while (--pos >= 0)
1293 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1294 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1295 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1296 }
1297 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1298}
1299
1300static void rtl8169_phy_timer(unsigned long __opaque)
1301{
1302 struct net_device *dev = (struct net_device *)__opaque;
1303 struct rtl8169_private *tp = netdev_priv(dev);
1304 struct timer_list *timer = &tp->timer;
1305 void __iomem *ioaddr = tp->mmio_addr;
1306 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1307
1308 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1309 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1310
1311 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1312 return;
1313
1314 spin_lock_irq(&tp->lock);
1315
1316 if (tp->phy_reset_pending(ioaddr)) {
1317 /*
1318 * A busy loop could burn quite a few cycles on nowadays CPU.
1319 * Let's delay the execution of the timer for a few ticks.
1320 */
1321 timeout = HZ/10;
1322 goto out_mod_timer;
1323 }
1324
1325 if (tp->link_ok(ioaddr))
1326 goto out_unlock;
1327
b57b7e5a
SH		 1328 if (netif_msg_link(tp))
1329 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1330
1331 tp->phy_reset_enable(ioaddr);
1332
1333out_mod_timer:
1334 mod_timer(timer, jiffies + timeout);
1335out_unlock:
1336 spin_unlock_irq(&tp->lock);
1337}
1338
1339static inline void rtl8169_delete_timer(struct net_device *dev)
1340{
1341 struct rtl8169_private *tp = netdev_priv(dev);
1342 struct timer_list *timer = &tp->timer;
1343
1344 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1345 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1346 return;
1347
1348 del_timer_sync(timer);
1349}
1350
1351static inline void rtl8169_request_timer(struct net_device *dev)
1352{
1353 struct rtl8169_private *tp = netdev_priv(dev);
1354 struct timer_list *timer = &tp->timer;
1355
1356 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1357 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1358 return;
1359
1360 init_timer(timer);
1361 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1362 timer->data = (unsigned long)(dev);
1363 timer->function = rtl8169_phy_timer;
1364 add_timer(timer);
1365}
1366
1367#ifdef CONFIG_NET_POLL_CONTROLLER
1368/*
1369 * Polling 'interrupt' - used by things like netconsole to send skbs
1370 * without having to re-enable interrupts. It's not called while
1371 * the interrupt routine is executing.
1372 */
1373static void rtl8169_netpoll(struct net_device *dev)
1374{
1375 struct rtl8169_private *tp = netdev_priv(dev);
1376 struct pci_dev *pdev = tp->pci_dev;
1377
1378 disable_irq(pdev->irq);
1379 rtl8169_interrupt(pdev->irq, dev, NULL);
1380 enable_irq(pdev->irq);
1381}
1382#endif
1383
1384static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1385 void __iomem *ioaddr)
1386{
1387 iounmap(ioaddr);
1388 pci_release_regions(pdev);
1389 pci_disable_device(pdev);
1390 free_netdev(dev);
1391}
1392
1393static int __devinit
1394rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1395 void __iomem **ioaddr_out)
1396{
1397 void __iomem *ioaddr;
1398 struct net_device *dev;
1399 struct rtl8169_private *tp;
1400 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1401
1402 assert(ioaddr_out != NULL);
1403
1404 /* dev zeroed in alloc_etherdev */
1405 dev = alloc_etherdev(sizeof (*tp));
1406 if (dev == NULL) {
b57b7e5a
SH		 1407 if (netif_msg_drv(&debug))
1408 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1da177e4
LT		 1409 goto err_out;
1410 }
1411
1412 SET_MODULE_OWNER(dev);
1413 SET_NETDEV_DEV(dev, &pdev->dev);
1414 tp = netdev_priv(dev);
b57b7e5a 1415 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1416
1417 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1418 rc = pci_enable_device(pdev);
b57b7e5a
SH		 1419 if (rc < 0) {
1420 if (netif_msg_probe(tp)) {
1421 printk(KERN_ERR PFX "%s: enable failure\n",
1422 pci_name(pdev));
1423 }
1da177e4
LT		 1424 goto err_out_free_dev;
1425 }
1426
1427 rc = pci_set_mwi(pdev);
1428 if (rc < 0)
1429 goto err_out_disable;
1430
1431 /* save power state before pci_enable_device overwrites it */
1432 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1433 if (pm_cap) {
1434 u16 pwr_command;
1435
1436 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1437 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1438 } else {
b57b7e5a
SH		 1439 if (netif_msg_probe(tp)) {
1440 printk(KERN_ERR PFX
e53091fa 1441 "PowerManagement capability not found.\n");
b57b7e5a 1442 }
1da177e4
LT		 1443 }
1444
1445 /* make sure PCI base addr 1 is MMIO */
1446 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
b57b7e5a
SH		 1447 if (netif_msg_probe(tp)) {
1448 printk(KERN_ERR PFX
1449 "region #1 not an MMIO resource, aborting\n");
1450 }
1da177e4
LT		 1451 rc = -ENODEV;
1452 goto err_out_mwi;
1453 }
1454 /* check for weird/broken PCI region reporting */
1455 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
b57b7e5a
SH		 1456 if (netif_msg_probe(tp)) {
1457 printk(KERN_ERR PFX
1458 "Invalid PCI region size(s), aborting\n");
1459 }
1da177e4
LT		 1460 rc = -ENODEV;
1461 goto err_out_mwi;
1462 }
1463
1464 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a
SH		 1465 if (rc < 0) {
1466 if (netif_msg_probe(tp)) {
1467 printk(KERN_ERR PFX "%s: could not request regions.\n",
1468 pci_name(pdev));
1469 }
1da177e4
LT		 1470 goto err_out_mwi;
1471 }
1472
1473 tp->cp_cmd = PCIMulRW | RxChkSum;
1474
1475 if ((sizeof(dma_addr_t) > 4) &&
1476 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1477 tp->cp_cmd |= PCIDAC;
1478 dev->features |= NETIF_F_HIGHDMA;
1479 } else {
1480 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1481 if (rc < 0) {
b57b7e5a
SH		 1482 if (netif_msg_probe(tp)) {
1483 printk(KERN_ERR PFX
1484 "DMA configuration failed.\n");
1485 }
1da177e4
LT		 1486 goto err_out_free_res;
1487 }
1488 }
1489
1490 pci_set_master(pdev);
1491
1492 /* ioremap MMIO region */
1493 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1494 if (ioaddr == NULL) {
b57b7e5a
SH		 1495 if (netif_msg_probe(tp))
1496 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1da177e4
LT		 1497 rc = -EIO;
1498 goto err_out_free_res;
1499 }
1500
1501 /* Unneeded ? Don't mess with Mrs. Murphy. */
1502 rtl8169_irq_mask_and_ack(ioaddr);
1503
1504 /* Soft reset the chip. */
1505 RTL_W8(ChipCmd, CmdReset);
1506
1507 /* Check that the chip has finished the reset. */
1508 for (i = 1000; i > 0; i--) {
1509 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1510 break;
1511 udelay(10);
1512 }
1513
1514 /* Identify chip attached to board */
1515 rtl8169_get_mac_version(tp, ioaddr);
1516 rtl8169_get_phy_version(tp, ioaddr);
1517
1518 rtl8169_print_mac_version(tp);
1519 rtl8169_print_phy_version(tp);
1520
1521 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1522 if (tp->mac_version == rtl_chip_info[i].mac_version)
1523 break;
1524 }
1525 if (i < 0) {
1526 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a
SH		 1527 if (netif_msg_probe(tp)) {
1528 printk(KERN_DEBUG PFX "PCI device %s: "
1529 "unknown chip version, assuming %s\n",
1530 pci_name(pdev), rtl_chip_info[0].name);
1531 }
1da177e4
LT		 1532 i++;
1533 }
1534 tp->chipset = i;
1535
5d06a99f
FR		 1536 RTL_W8(Cfg9346, Cfg9346_Unlock);
1537 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1538 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1539 RTL_W8(Cfg9346, Cfg9346_Lock);
1540
1da177e4
LT		 1541 *ioaddr_out = ioaddr;
1542 *dev_out = dev;
1543out:
1544 return rc;
1545
1546err_out_free_res:
1547 pci_release_regions(pdev);
1548
1549err_out_mwi:
1550 pci_clear_mwi(pdev);
1551
1552err_out_disable:
1553 pci_disable_device(pdev);
1554
1555err_out_free_dev:
1556 free_netdev(dev);
1557err_out:
1558 *ioaddr_out = NULL;
1559 *dev_out = NULL;
1560 goto out;
1561}
1562
1563static int __devinit
1564rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1565{
1566 struct net_device *dev = NULL;
1567 struct rtl8169_private *tp;
1568 void __iomem *ioaddr = NULL;
1569 static int board_idx = -1;
1da177e4
LT		 1570 u8 autoneg, duplex;
1571 u16 speed;
1572 int i, rc;
1573
1574 assert(pdev != NULL);
1575 assert(ent != NULL);
1576
1577 board_idx++;
1578
b57b7e5a 1579 if (netif_msg_drv(&debug)) {
1da177e4
LT		 1580 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1581 MODULENAME, RTL8169_VERSION);
1da177e4
LT		 1582 }
1583
1584 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1585 if (rc)
1586 return rc;
1587
1588 tp = netdev_priv(dev);
1589 assert(ioaddr != NULL);
1590
1591 if (RTL_R8(PHYstatus) & TBI_Enable) {
1592 tp->set_speed = rtl8169_set_speed_tbi;
1593 tp->get_settings = rtl8169_gset_tbi;
1594 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1595 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1596 tp->link_ok = rtl8169_tbi_link_ok;
1597
1598 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1599 } else {
1600 tp->set_speed = rtl8169_set_speed_xmii;
1601 tp->get_settings = rtl8169_gset_xmii;
1602 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1603 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1604 tp->link_ok = rtl8169_xmii_link_ok;
1605 }
1606
1607 /* Get MAC address. FIXME: read EEPROM */
1608 for (i = 0; i < MAC_ADDR_LEN; i++)
1609 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1610 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1611
1612 dev->open = rtl8169_open;
1613 dev->hard_start_xmit = rtl8169_start_xmit;
1614 dev->get_stats = rtl8169_get_stats;
1615 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1616 dev->stop = rtl8169_close;
1617 dev->tx_timeout = rtl8169_tx_timeout;
1618 dev->set_multicast_list = rtl8169_set_rx_mode;
1619 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1620 dev->irq = pdev->irq;
1621 dev->base_addr = (unsigned long) ioaddr;
1622 dev->change_mtu = rtl8169_change_mtu;
1623
1624#ifdef CONFIG_R8169_NAPI
1625 dev->poll = rtl8169_poll;
1626 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1627#endif
1628
1629#ifdef CONFIG_R8169_VLAN
1630 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1631 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1632 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1633#endif
1634
1635#ifdef CONFIG_NET_POLL_CONTROLLER
1636 dev->poll_controller = rtl8169_netpoll;
1637#endif
1638
1639 tp->intr_mask = 0xffff;
1640 tp->pci_dev = pdev;
1641 tp->mmio_addr = ioaddr;
1642
1643 spin_lock_init(&tp->lock);
1644
1645 rc = register_netdev(dev);
1646 if (rc) {
1647 rtl8169_release_board(pdev, dev, ioaddr);
1648 return rc;
1649 }
1650
b57b7e5a
SH		 1651 if (netif_msg_probe(tp)) {
1652 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1653 dev->name, rtl_chip_info[tp->chipset].name);
1654 }
1da177e4
LT		 1655
1656 pci_set_drvdata(pdev, dev);
1657
b57b7e5a
SH		 1658 if (netif_msg_probe(tp)) {
1659 printk(KERN_INFO "%s: %s at 0x%lx, "
1660 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1661 "IRQ %d\n",
1662 dev->name,
1663 rtl_chip_info[ent->driver_data].name,
1664 dev->base_addr,
1665 dev->dev_addr[0], dev->dev_addr[1],
1666 dev->dev_addr[2], dev->dev_addr[3],
1667 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1668 }
1da177e4
LT		 1669
1670 rtl8169_hw_phy_config(dev);
1671
1672 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1673 RTL_W8(0x82, 0x01);
1674
1675 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1676 dprintk("Set PCI Latency=0x40\n");
1677 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1678 }
1679
1680 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1681 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1682 RTL_W8(0x82, 0x01);
1683 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1684 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1685 }
1686
1687 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1688
1689 rtl8169_set_speed(dev, autoneg, speed, duplex);
1690
b57b7e5a 1691 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1da177e4
LT		 1692 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1693
1694 return 0;
1695}
1696
1697static void __devexit
1698rtl8169_remove_one(struct pci_dev *pdev)
1699{
1700 struct net_device *dev = pci_get_drvdata(pdev);
1701 struct rtl8169_private *tp = netdev_priv(dev);
1702
1703 assert(dev != NULL);
1704 assert(tp != NULL);
1705
1706 unregister_netdev(dev);
1707 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1708 pci_set_drvdata(pdev, NULL);
1709}
1710
1da177e4
LT		 1711static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1712 struct net_device *dev)
1713{
1714 unsigned int mtu = dev->mtu;
1715
1716 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1717}
1718
1719static int rtl8169_open(struct net_device *dev)
1720{
1721 struct rtl8169_private *tp = netdev_priv(dev);
1722 struct pci_dev *pdev = tp->pci_dev;
1723 int retval;
1724
1725 rtl8169_set_rxbufsize(tp, dev);
1726
1727 retval =
1728 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1729 if (retval < 0)
1730 goto out;
1731
1732 retval = -ENOMEM;
1733
1734 /*
1735 * Rx and Tx desscriptors needs 256 bytes alignment.
1736 * pci_alloc_consistent provides more.
1737 */
1738 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1739 &tp->TxPhyAddr);
1740 if (!tp->TxDescArray)
1741 goto err_free_irq;
1742
1743 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1744 &tp->RxPhyAddr);
1745 if (!tp->RxDescArray)
1746 goto err_free_tx;
1747
1748 retval = rtl8169_init_ring(dev);
1749 if (retval < 0)
1750 goto err_free_rx;
1751
1752 INIT_WORK(&tp->task, NULL, dev);
1753
1754 rtl8169_hw_start(dev);
1755
1756 rtl8169_request_timer(dev);
1757
1758 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1759out:
1760 return retval;
1761
1762err_free_rx:
1763 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1764 tp->RxPhyAddr);
1765err_free_tx:
1766 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1767 tp->TxPhyAddr);
1768err_free_irq:
1769 free_irq(dev->irq, dev);
1770 goto out;
1771}
1772
1773static void rtl8169_hw_reset(void __iomem *ioaddr)
1774{
1775 /* Disable interrupts */
1776 rtl8169_irq_mask_and_ack(ioaddr);
1777
1778 /* Reset the chipset */
1779 RTL_W8(ChipCmd, CmdReset);
1780
1781 /* PCI commit */
1782 RTL_R8(ChipCmd);
1783}
1784
1785static void
1786rtl8169_hw_start(struct net_device *dev)
1787{
1788 struct rtl8169_private *tp = netdev_priv(dev);
1789 void __iomem *ioaddr = tp->mmio_addr;
1790 u32 i;
1791
1792 /* Soft reset the chip. */
1793 RTL_W8(ChipCmd, CmdReset);
1794
1795 /* Check that the chip has finished the reset. */
1796 for (i = 1000; i > 0; i--) {
1797 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1798 break;
1799 udelay(10);
1800 }
1801
1802 RTL_W8(Cfg9346, Cfg9346_Unlock);
1803 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1804 RTL_W8(EarlyTxThres, EarlyTxThld);
1805
126fa4b9
FR		 1806 /* Low hurts. Let's disable the filtering. */
1807 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1808
1809 /* Set Rx Config register */
1810 i = rtl8169_rx_config |
1811 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1812 RTL_W32(RxConfig, i);
1813
1814 /* Set DMA burst size and Interframe Gap Time */
1815 RTL_W32(TxConfig,
1816 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1817 TxInterFrameGapShift));
1818 tp->cp_cmd |= RTL_R16(CPlusCmd);
1819 RTL_W16(CPlusCmd, tp->cp_cmd);
1820
1821 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1822 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1823 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1824 "Bit-3 and bit-14 MUST be 1\n");
1825 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1826 RTL_W16(CPlusCmd, tp->cp_cmd);
1827 }
1828
1829 /*
1830 * Undocumented corner. Supposedly:
1831 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1832 */
1833 RTL_W16(IntrMitigate, 0x0000);
1834
1835 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1836 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1837 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1838 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1839 RTL_W8(Cfg9346, Cfg9346_Lock);
1840 udelay(10);
1841
1842 RTL_W32(RxMissed, 0);
1843
1844 rtl8169_set_rx_mode(dev);
1845
1846 /* no early-rx interrupts */
1847 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1848
1849 /* Enable all known interrupts by setting the interrupt mask. */
1850 RTL_W16(IntrMask, rtl8169_intr_mask);
1851
1852 netif_start_queue(dev);
1853}
1854
1855static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1856{
1857 struct rtl8169_private *tp = netdev_priv(dev);
1858 int ret = 0;
1859
1860 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1861 return -EINVAL;
1862
1863 dev->mtu = new_mtu;
1864
1865 if (!netif_running(dev))
1866 goto out;
1867
1868 rtl8169_down(dev);
1869
1870 rtl8169_set_rxbufsize(tp, dev);
1871
1872 ret = rtl8169_init_ring(dev);
1873 if (ret < 0)
1874 goto out;
1875
1876 netif_poll_enable(dev);
1877
1878 rtl8169_hw_start(dev);
1879
1880 rtl8169_request_timer(dev);
1881
1882out:
1883 return ret;
1884}
1885
1886static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1887{
1888 desc->addr = 0x0badbadbadbadbadull;
1889 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1890}
1891
1892static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1893 struct sk_buff **sk_buff, struct RxDesc *desc)
1894{
1895 struct pci_dev *pdev = tp->pci_dev;
1896
1897 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1898 PCI_DMA_FROMDEVICE);
1899 dev_kfree_skb(*sk_buff);
1900 *sk_buff = NULL;
1901 rtl8169_make_unusable_by_asic(desc);
1902}
1903
1904static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1905{
1906 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1907
1908 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1909}
1910
1911static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1912 u32 rx_buf_sz)
1913{
1914 desc->addr = cpu_to_le64(mapping);
1915 wmb();
1916 rtl8169_mark_to_asic(desc, rx_buf_sz);
1917}
1918
1919static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1920 struct RxDesc *desc, int rx_buf_sz)
1921{
1922 struct sk_buff *skb;
1923 dma_addr_t mapping;
1924 int ret = 0;
1925
1926 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1927 if (!skb)
1928 goto err_out;
1929
1930 skb_reserve(skb, NET_IP_ALIGN);
1931 *sk_buff = skb;
1932
689be439 1933 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 1934 PCI_DMA_FROMDEVICE);
1935
1936 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1937
1938out:
1939 return ret;
1940
1941err_out:
1942 ret = -ENOMEM;
1943 rtl8169_make_unusable_by_asic(desc);
1944 goto out;
1945}
1946
1947static void rtl8169_rx_clear(struct rtl8169_private *tp)
1948{
1949 int i;
1950
1951 for (i = 0; i < NUM_RX_DESC; i++) {
1952 if (tp->Rx_skbuff[i]) {
1953 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1954 tp->RxDescArray + i);
1955 }
1956 }
1957}
1958
1959static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1960 u32 start, u32 end)
1961{
1962 u32 cur;
1963
1964 for (cur = start; end - cur > 0; cur++) {
1965 int ret, i = cur % NUM_RX_DESC;
1966
1967 if (tp->Rx_skbuff[i])
1968 continue;
1969
1970 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1971 tp->RxDescArray + i, tp->rx_buf_sz);
1972 if (ret < 0)
1973 break;
1974 }
1975 return cur - start;
1976}
1977
1978static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1979{
1980 desc->opts1 |= cpu_to_le32(RingEnd);
1981}
1982
1983static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1984{
1985 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1986}
1987
1988static int rtl8169_init_ring(struct net_device *dev)
1989{
1990 struct rtl8169_private *tp = netdev_priv(dev);
1991
1992 rtl8169_init_ring_indexes(tp);
1993
1994 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1995 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1996
1997 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1998 goto err_out;
1999
2000 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2001
2002 return 0;
2003
2004err_out:
2005 rtl8169_rx_clear(tp);
2006 return -ENOMEM;
2007}
2008
2009static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2010 struct TxDesc *desc)
2011{
2012 unsigned int len = tx_skb->len;
2013
2014 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2015 desc->opts1 = 0x00;
2016 desc->opts2 = 0x00;
2017 desc->addr = 0x00;
2018 tx_skb->len = 0;
2019}
2020
2021static void rtl8169_tx_clear(struct rtl8169_private *tp)
2022{
2023 unsigned int i;
2024
2025 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2026 unsigned int entry = i % NUM_TX_DESC;
2027 struct ring_info *tx_skb = tp->tx_skb + entry;
2028 unsigned int len = tx_skb->len;
2029
2030 if (len) {
2031 struct sk_buff *skb = tx_skb->skb;
2032
2033 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2034 tp->TxDescArray + entry);
2035 if (skb) {
2036 dev_kfree_skb(skb);
2037 tx_skb->skb = NULL;
2038 }
2039 tp->stats.tx_dropped++;
2040 }
2041 }
2042 tp->cur_tx = tp->dirty_tx = 0;
2043}
2044
2045static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2046{
2047 struct rtl8169_private *tp = netdev_priv(dev);
2048
2049 PREPARE_WORK(&tp->task, task, dev);
2050 schedule_delayed_work(&tp->task, 4);
2051}
2052
2053static void rtl8169_wait_for_quiescence(struct net_device *dev)
2054{
2055 struct rtl8169_private *tp = netdev_priv(dev);
2056 void __iomem *ioaddr = tp->mmio_addr;
2057
2058 synchronize_irq(dev->irq);
2059
2060 /* Wait for any pending NAPI task to complete */
2061 netif_poll_disable(dev);
2062
2063 rtl8169_irq_mask_and_ack(ioaddr);
2064
2065 netif_poll_enable(dev);
2066}
2067
2068static void rtl8169_reinit_task(void *_data)
2069{
2070 struct net_device *dev = _data;
2071 int ret;
2072
2073 if (netif_running(dev)) {
2074 rtl8169_wait_for_quiescence(dev);
2075 rtl8169_close(dev);
2076 }
2077
2078 ret = rtl8169_open(dev);
2079 if (unlikely(ret < 0)) {
2080 if (net_ratelimit()) {
b57b7e5a
SH		 2081 struct rtl8169_private *tp = netdev_priv(dev);
2082
2083 if (netif_msg_drv(tp)) {
2084 printk(PFX KERN_ERR
2085 "%s: reinit failure (status = %d)."
2086 " Rescheduling.\n", dev->name, ret);
2087 }
1da177e4
LT		 2088 }
2089 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2090 }
2091}
2092
2093static void rtl8169_reset_task(void *_data)
2094{
2095 struct net_device *dev = _data;
2096 struct rtl8169_private *tp = netdev_priv(dev);
2097
2098 if (!netif_running(dev))
2099 return;
2100
2101 rtl8169_wait_for_quiescence(dev);
2102
2103 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2104 rtl8169_tx_clear(tp);
2105
2106 if (tp->dirty_rx == tp->cur_rx) {
2107 rtl8169_init_ring_indexes(tp);
2108 rtl8169_hw_start(dev);
2109 netif_wake_queue(dev);
2110 } else {
2111 if (net_ratelimit()) {
b57b7e5a
SH		 2112 struct rtl8169_private *tp = netdev_priv(dev);
2113
2114 if (netif_msg_intr(tp)) {
2115 printk(PFX KERN_EMERG
2116 "%s: Rx buffers shortage\n", dev->name);
2117 }
1da177e4
LT		 2118 }
2119 rtl8169_schedule_work(dev, rtl8169_reset_task);
2120 }
2121}
2122
2123static void rtl8169_tx_timeout(struct net_device *dev)
2124{
2125 struct rtl8169_private *tp = netdev_priv(dev);
2126
2127 rtl8169_hw_reset(tp->mmio_addr);
2128
2129 /* Let's wait a bit while any (async) irq lands on */
2130 rtl8169_schedule_work(dev, rtl8169_reset_task);
2131}
2132
2133static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2134 u32 opts1)
2135{
2136 struct skb_shared_info *info = skb_shinfo(skb);
2137 unsigned int cur_frag, entry;
2138 struct TxDesc *txd;
2139
2140 entry = tp->cur_tx;
2141 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2142 skb_frag_t *frag = info->frags + cur_frag;
2143 dma_addr_t mapping;
2144 u32 status, len;
2145 void *addr;
2146
2147 entry = (entry + 1) % NUM_TX_DESC;
2148
2149 txd = tp->TxDescArray + entry;
2150 len = frag->size;
2151 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2152 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2153
2154 /* anti gcc 2.95.3 bugware (sic) */
2155 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2156
2157 txd->opts1 = cpu_to_le32(status);
2158 txd->addr = cpu_to_le64(mapping);
2159
2160 tp->tx_skb[entry].len = len;
2161 }
2162
2163 if (cur_frag) {
2164 tp->tx_skb[entry].skb = skb;
2165 txd->opts1 |= cpu_to_le32(LastFrag);
2166 }
2167
2168 return cur_frag;
2169}
2170
2171static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2172{
2173 if (dev->features & NETIF_F_TSO) {
2174 u32 mss = skb_shinfo(skb)->tso_size;
2175
2176 if (mss)
2177 return LargeSend | ((mss & MSSMask) << MSSShift);
2178 }
2179 if (skb->ip_summed == CHECKSUM_HW) {
2180 const struct iphdr *ip = skb->nh.iph;
2181
2182 if (ip->protocol == IPPROTO_TCP)
2183 return IPCS | TCPCS;
2184 else if (ip->protocol == IPPROTO_UDP)
2185 return IPCS | UDPCS;
2186 WARN_ON(1); /* we need a WARN() */
2187 }
2188 return 0;
2189}
2190
2191static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2192{
2193 struct rtl8169_private *tp = netdev_priv(dev);
2194 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2195 struct TxDesc *txd = tp->TxDescArray + entry;
2196 void __iomem *ioaddr = tp->mmio_addr;
2197 dma_addr_t mapping;
2198 u32 status, len;
2199 u32 opts1;
2200 int ret = 0;
2201
2202 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2203 if (netif_msg_drv(tp)) {
2204 printk(KERN_ERR
2205 "%s: BUG! Tx Ring full when queue awake!\n",
2206 dev->name);
2207 }
1da177e4
LT		 2208 goto err_stop;
2209 }
2210
2211 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2212 goto err_stop;
2213
2214 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2215
2216 frags = rtl8169_xmit_frags(tp, skb, opts1);
2217 if (frags) {
2218 len = skb_headlen(skb);
2219 opts1 |= FirstFrag;
2220 } else {
2221 len = skb->len;
2222
2223 if (unlikely(len < ETH_ZLEN)) {
2224 skb = skb_padto(skb, ETH_ZLEN);
2225 if (!skb)
2226 goto err_update_stats;
2227 len = ETH_ZLEN;
2228 }
2229
2230 opts1 |= FirstFrag | LastFrag;
2231 tp->tx_skb[entry].skb = skb;
2232 }
2233
2234 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2235
2236 tp->tx_skb[entry].len = len;
2237 txd->addr = cpu_to_le64(mapping);
2238 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2239
2240 wmb();
2241
2242 /* anti gcc 2.95.3 bugware (sic) */
2243 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2244 txd->opts1 = cpu_to_le32(status);
2245
2246 dev->trans_start = jiffies;
2247
2248 tp->cur_tx += frags + 1;
2249
2250 smp_wmb();
2251
2252 RTL_W8(TxPoll, 0x40); /* set polling bit */
2253
2254 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2255 netif_stop_queue(dev);
2256 smp_rmb();
2257 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2258 netif_wake_queue(dev);
2259 }
2260
2261out:
2262 return ret;
2263
2264err_stop:
2265 netif_stop_queue(dev);
2266 ret = 1;
2267err_update_stats:
2268 tp->stats.tx_dropped++;
2269 goto out;
2270}
2271
2272static void rtl8169_pcierr_interrupt(struct net_device *dev)
2273{
2274 struct rtl8169_private *tp = netdev_priv(dev);
2275 struct pci_dev *pdev = tp->pci_dev;
2276 void __iomem *ioaddr = tp->mmio_addr;
2277 u16 pci_status, pci_cmd;
2278
2279 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2280 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2281
b57b7e5a
SH		 2282 if (netif_msg_intr(tp)) {
2283 printk(KERN_ERR
2284 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2285 dev->name, pci_cmd, pci_status);
2286 }
1da177e4
LT		 2287
2288 /*
2289 * The recovery sequence below admits a very elaborated explanation:
2290 * - it seems to work;
2291 * - I did not see what else could be done.
2292 *
2293 * Feel free to adjust to your needs.
2294 */
2295 pci_write_config_word(pdev, PCI_COMMAND,
2296 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2297
2298 pci_write_config_word(pdev, PCI_STATUS,
2299 pci_status & (PCI_STATUS_DETECTED_PARITY |
2300 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2301 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2302
2303 /* The infamous DAC f*ckup only happens at boot time */
2304 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2305 if (netif_msg_intr(tp))
2306 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2307 tp->cp_cmd &= ~PCIDAC;
2308 RTL_W16(CPlusCmd, tp->cp_cmd);
2309 dev->features &= ~NETIF_F_HIGHDMA;
2310 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2311 }
2312
2313 rtl8169_hw_reset(ioaddr);
2314}
2315
2316static void
2317rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2318 void __iomem *ioaddr)
2319{
2320 unsigned int dirty_tx, tx_left;
2321
2322 assert(dev != NULL);
2323 assert(tp != NULL);
2324 assert(ioaddr != NULL);
2325
2326 dirty_tx = tp->dirty_tx;
2327 smp_rmb();
2328 tx_left = tp->cur_tx - dirty_tx;
2329
2330 while (tx_left > 0) {
2331 unsigned int entry = dirty_tx % NUM_TX_DESC;
2332 struct ring_info *tx_skb = tp->tx_skb + entry;
2333 u32 len = tx_skb->len;
2334 u32 status;
2335
2336 rmb();
2337 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2338 if (status & DescOwn)
2339 break;
2340
2341 tp->stats.tx_bytes += len;
2342 tp->stats.tx_packets++;
2343
2344 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2345
2346 if (status & LastFrag) {
2347 dev_kfree_skb_irq(tx_skb->skb);
2348 tx_skb->skb = NULL;
2349 }
2350 dirty_tx++;
2351 tx_left--;
2352 }
2353
2354 if (tp->dirty_tx != dirty_tx) {
2355 tp->dirty_tx = dirty_tx;
2356 smp_wmb();
2357 if (netif_queue_stopped(dev) &&
2358 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2359 netif_wake_queue(dev);
2360 }
2361 }
2362}
2363
126fa4b9
FR		 2364static inline int rtl8169_fragmented_frame(u32 status)
2365{
2366 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2367}
2368
1da177e4
LT		 2369static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2370{
2371 u32 opts1 = le32_to_cpu(desc->opts1);
2372 u32 status = opts1 & RxProtoMask;
2373
2374 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2375 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2376 ((status == RxProtoIP) && !(opts1 & IPFail)))
2377 skb->ip_summed = CHECKSUM_UNNECESSARY;
2378 else
2379 skb->ip_summed = CHECKSUM_NONE;
2380}
2381
2382static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2383 struct RxDesc *desc, int rx_buf_sz)
2384{
2385 int ret = -1;
2386
2387 if (pkt_size < rx_copybreak) {
2388 struct sk_buff *skb;
2389
2390 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2391 if (skb) {
2392 skb_reserve(skb, NET_IP_ALIGN);
689be439 2393 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2394 *sk_buff = skb;
2395 rtl8169_mark_to_asic(desc, rx_buf_sz);
2396 ret = 0;
2397 }
2398 }
2399 return ret;
2400}
2401
2402static int
2403rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2404 void __iomem *ioaddr)
2405{
2406 unsigned int cur_rx, rx_left;
2407 unsigned int delta, count;
2408
2409 assert(dev != NULL);
2410 assert(tp != NULL);
2411 assert(ioaddr != NULL);
2412
2413 cur_rx = tp->cur_rx;
2414 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2415 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2416
4dcb7d33 2417 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2418 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2419 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2420 u32 status;
2421
2422 rmb();
126fa4b9 2423 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2424
2425 if (status & DescOwn)
2426 break;
4dcb7d33 2427 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2428 if (netif_msg_rx_err(tp)) {
2429 printk(KERN_INFO
2430 "%s: Rx ERROR. status = %08x\n",
2431 dev->name, status);
2432 }
1da177e4
LT		 2433 tp->stats.rx_errors++;
2434 if (status & (RxRWT | RxRUNT))
2435 tp->stats.rx_length_errors++;
2436 if (status & RxCRC)
2437 tp->stats.rx_crc_errors++;
126fa4b9 2438 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2439 } else {
1da177e4
LT		 2440 struct sk_buff *skb = tp->Rx_skbuff[entry];
2441 int pkt_size = (status & 0x00001FFF) - 4;
2442 void (*pci_action)(struct pci_dev *, dma_addr_t,
2443 size_t, int) = pci_dma_sync_single_for_device;
2444
126fa4b9
FR		 2445 /*
2446 * The driver does not support incoming fragmented
2447 * frames. They are seen as a symptom of over-mtu
2448 * sized frames.
2449 */
2450 if (unlikely(rtl8169_fragmented_frame(status))) {
2451 tp->stats.rx_dropped++;
2452 tp->stats.rx_length_errors++;
2453 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2454 continue;
126fa4b9
FR		 2455 }
2456
1da177e4
LT		 2457 rtl8169_rx_csum(skb, desc);
2458
2459 pci_dma_sync_single_for_cpu(tp->pci_dev,
2460 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2461 PCI_DMA_FROMDEVICE);
2462
2463 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2464 tp->rx_buf_sz)) {
2465 pci_action = pci_unmap_single;
2466 tp->Rx_skbuff[entry] = NULL;
2467 }
2468
2469 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2470 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2471
2472 skb->dev = dev;
2473 skb_put(skb, pkt_size);
2474 skb->protocol = eth_type_trans(skb, dev);
2475
2476 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2477 rtl8169_rx_skb(skb);
2478
2479 dev->last_rx = jiffies;
2480 tp->stats.rx_bytes += pkt_size;
2481 tp->stats.rx_packets++;
2482 }
1da177e4
LT		 2483 }
2484
2485 count = cur_rx - tp->cur_rx;
2486 tp->cur_rx = cur_rx;
2487
2488 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2489 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2490 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2491 tp->dirty_rx += delta;
2492
2493 /*
2494 * FIXME: until there is periodic timer to try and refill the ring,
2495 * a temporary shortage may definitely kill the Rx process.
2496 * - disable the asic to try and avoid an overflow and kick it again
2497 * after refill ?
2498 * - how do others driver handle this condition (Uh oh...).
2499 */
b57b7e5a 2500 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2501 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2502
2503 return count;
2504}
2505
2506/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2507static irqreturn_t
2508rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2509{
2510 struct net_device *dev = (struct net_device *) dev_instance;
2511 struct rtl8169_private *tp = netdev_priv(dev);
2512 int boguscnt = max_interrupt_work;
2513 void __iomem *ioaddr = tp->mmio_addr;
2514 int status;
2515 int handled = 0;
2516
2517 do {
2518 status = RTL_R16(IntrStatus);
2519
2520 /* hotplug/major error/no more work/shared irq */
2521 if ((status == 0xFFFF) || !status)
2522 break;
2523
2524 handled = 1;
2525
2526 if (unlikely(!netif_running(dev))) {
2527 rtl8169_asic_down(ioaddr);
2528 goto out;
2529 }
2530
2531 status &= tp->intr_mask;
2532 RTL_W16(IntrStatus,
2533 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2534
2535 if (!(status & rtl8169_intr_mask))
2536 break;
2537
2538 if (unlikely(status & SYSErr)) {
2539 rtl8169_pcierr_interrupt(dev);
2540 break;
2541 }
2542
2543 if (status & LinkChg)
2544 rtl8169_check_link_status(dev, tp, ioaddr);
2545
2546#ifdef CONFIG_R8169_NAPI
2547 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2548 tp->intr_mask = ~rtl8169_napi_event;
2549
2550 if (likely(netif_rx_schedule_prep(dev)))
2551 __netif_rx_schedule(dev);
b57b7e5a 2552 else if (netif_msg_intr(tp)) {
1da177e4
LT		 2553 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2554 dev->name, status);
2555 }
2556 break;
2557#else
2558 /* Rx interrupt */
2559 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2560 rtl8169_rx_interrupt(dev, tp, ioaddr);
2561 }
2562 /* Tx interrupt */
2563 if (status & (TxOK | TxErr))
2564 rtl8169_tx_interrupt(dev, tp, ioaddr);
2565#endif
2566
2567 boguscnt--;
2568 } while (boguscnt > 0);
2569
2570 if (boguscnt <= 0) {
7c8b2eb4 2571 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2572 printk(KERN_WARNING
2573 "%s: Too much work at interrupt!\n", dev->name);
2574 }
1da177e4
LT		 2575 /* Clear all interrupt sources. */
2576 RTL_W16(IntrStatus, 0xffff);
2577 }
2578out:
2579 return IRQ_RETVAL(handled);
2580}
2581
2582#ifdef CONFIG_R8169_NAPI
2583static int rtl8169_poll(struct net_device *dev, int *budget)
2584{
2585 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2586 struct rtl8169_private *tp = netdev_priv(dev);
2587 void __iomem *ioaddr = tp->mmio_addr;
2588
2589 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2590 rtl8169_tx_interrupt(dev, tp, ioaddr);
2591
2592 *budget -= work_done;
2593 dev->quota -= work_done;
2594
2595 if (work_done < work_to_do) {
2596 netif_rx_complete(dev);
2597 tp->intr_mask = 0xffff;
2598 /*
2599 * 20040426: the barrier is not strictly required but the
2600 * behavior of the irq handler could be less predictable
2601 * without it. Btw, the lack of flush for the posted pci
2602 * write is safe - FR
2603 */
2604 smp_wmb();
2605 RTL_W16(IntrMask, rtl8169_intr_mask);
2606 }
2607
2608 return (work_done >= work_to_do);
2609}
2610#endif
2611
2612static void rtl8169_down(struct net_device *dev)
2613{
2614 struct rtl8169_private *tp = netdev_priv(dev);
2615 void __iomem *ioaddr = tp->mmio_addr;
2616 unsigned int poll_locked = 0;
2617
2618 rtl8169_delete_timer(dev);
2619
2620 netif_stop_queue(dev);
2621
2622 flush_scheduled_work();
2623
2624core_down:
2625 spin_lock_irq(&tp->lock);
2626
2627 rtl8169_asic_down(ioaddr);
2628
2629 /* Update the error counts. */
2630 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2631 RTL_W32(RxMissed, 0);
2632
2633 spin_unlock_irq(&tp->lock);
2634
2635 synchronize_irq(dev->irq);
2636
2637 if (!poll_locked) {
2638 netif_poll_disable(dev);
2639 poll_locked++;
2640 }
2641
2642 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2643 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2644
2645 /*
2646 * And now for the 50k$ question: are IRQ disabled or not ?
2647 *
2648 * Two paths lead here:
2649 * 1) dev->close
2650 * -> netif_running() is available to sync the current code and the
2651 * IRQ handler. See rtl8169_interrupt for details.
2652 * 2) dev->change_mtu
2653 * -> rtl8169_poll can not be issued again and re-enable the
2654 * interruptions. Let's simply issue the IRQ down sequence again.
2655 */
2656 if (RTL_R16(IntrMask))
2657 goto core_down;
2658
2659 rtl8169_tx_clear(tp);
2660
2661 rtl8169_rx_clear(tp);
2662}
2663
2664static int rtl8169_close(struct net_device *dev)
2665{
2666 struct rtl8169_private *tp = netdev_priv(dev);
2667 struct pci_dev *pdev = tp->pci_dev;
2668
2669 rtl8169_down(dev);
2670
2671 free_irq(dev->irq, dev);
2672
2673 netif_poll_enable(dev);
2674
2675 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2676 tp->RxPhyAddr);
2677 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2678 tp->TxPhyAddr);
2679 tp->TxDescArray = NULL;
2680 tp->RxDescArray = NULL;
2681
2682 return 0;
2683}
2684
2685static void
2686rtl8169_set_rx_mode(struct net_device *dev)
2687{
2688 struct rtl8169_private *tp = netdev_priv(dev);
2689 void __iomem *ioaddr = tp->mmio_addr;
2690 unsigned long flags;
2691 u32 mc_filter[2]; /* Multicast hash filter */
2692 int i, rx_mode;
2693 u32 tmp = 0;
2694
2695 if (dev->flags & IFF_PROMISC) {
2696 /* Unconditionally log net taps. */
b57b7e5a
SH		 2697 if (netif_msg_link(tp)) {
2698 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2699 dev->name);
2700 }
1da177e4
LT		 2701 rx_mode =
2702 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2703 AcceptAllPhys;
2704 mc_filter[1] = mc_filter[0] = 0xffffffff;
2705 } else if ((dev->mc_count > multicast_filter_limit)
2706 || (dev->flags & IFF_ALLMULTI)) {
2707 /* Too many to filter perfectly -- accept all multicasts. */
2708 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2709 mc_filter[1] = mc_filter[0] = 0xffffffff;
2710 } else {
2711 struct dev_mc_list *mclist;
2712 rx_mode = AcceptBroadcast | AcceptMyPhys;
2713 mc_filter[1] = mc_filter[0] = 0;
2714 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2715 i++, mclist = mclist->next) {
2716 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2717 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2718 rx_mode |= AcceptMulticast;
2719 }
2720 }
2721
2722 spin_lock_irqsave(&tp->lock, flags);
2723
2724 tmp = rtl8169_rx_config | rx_mode |
2725 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2726
2727 RTL_W32(RxConfig, tmp);
2728 RTL_W32(MAR0 + 0, mc_filter[0]);
2729 RTL_W32(MAR0 + 4, mc_filter[1]);
2730
2731 spin_unlock_irqrestore(&tp->lock, flags);
2732}
2733
2734/**
2735 * rtl8169_get_stats - Get rtl8169 read/write statistics
2736 * @dev: The Ethernet Device to get statistics for
2737 *
2738 * Get TX/RX statistics for rtl8169
2739 */
2740static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2741{
2742 struct rtl8169_private *tp = netdev_priv(dev);
2743 void __iomem *ioaddr = tp->mmio_addr;
2744 unsigned long flags;
2745
2746 if (netif_running(dev)) {
2747 spin_lock_irqsave(&tp->lock, flags);
2748 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2749 RTL_W32(RxMissed, 0);
2750 spin_unlock_irqrestore(&tp->lock, flags);
2751 }
2752
2753 return &tp->stats;
2754}
2755
5d06a99f
FR		 2756#ifdef CONFIG_PM
2757
2758static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2759{
2760 struct net_device *dev = pci_get_drvdata(pdev);
2761 struct rtl8169_private *tp = netdev_priv(dev);
2762 void __iomem *ioaddr = tp->mmio_addr;
2763
2764 if (!netif_running(dev))
2765 goto out;
2766
2767 netif_device_detach(dev);
2768 netif_stop_queue(dev);
2769
2770 spin_lock_irq(&tp->lock);
2771
2772 rtl8169_asic_down(ioaddr);
2773
2774 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2775 RTL_W32(RxMissed, 0);
2776
2777 spin_unlock_irq(&tp->lock);
2778
2779 pci_save_state(pdev);
61a4dcc2 2780 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f
FR		 2781 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2782out:
2783 return 0;
2784}
2785
2786static int rtl8169_resume(struct pci_dev *pdev)
2787{
2788 struct net_device *dev = pci_get_drvdata(pdev);
2789
2790 if (!netif_running(dev))
2791 goto out;
2792
2793 netif_device_attach(dev);
2794
2795 pci_set_power_state(pdev, PCI_D0);
2796 pci_restore_state(pdev);
61a4dcc2 2797 pci_enable_wake(pdev, PCI_D0, 0);
5d06a99f
FR		 2798
2799 rtl8169_schedule_work(dev, rtl8169_reset_task);
2800out:
2801 return 0;
2802}
2803
2804#endif /* CONFIG_PM */
2805
1da177e4
LT		 2806static struct pci_driver rtl8169_pci_driver = {
2807 .name = MODULENAME,
2808 .id_table = rtl8169_pci_tbl,
2809 .probe = rtl8169_init_one,
2810 .remove = __devexit_p(rtl8169_remove_one),
2811#ifdef CONFIG_PM
2812 .suspend = rtl8169_suspend,
2813 .resume = rtl8169_resume,
2814#endif
2815};
2816
2817static int __init
2818rtl8169_init_module(void)
2819{
2820 return pci_module_init(&rtl8169_pci_driver);
2821}
2822
2823static void __exit
2824rtl8169_cleanup_module(void)
2825{
2826 pci_unregister_driver(&rtl8169_pci_driver);
2827}
2828
2829module_init(rtl8169_init_module);
2830module_exit(rtl8169_cleanup_module);
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