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net: convert multiple drivers to use netdev_for_each_mc_addr, part7
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4
LT		 54/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 56static const int multicast_filter_limit = 32;
1da177e4
LT		 57
58/* MAC address length */
59#define MAC_ADDR_LEN 6
60
9c14ceaf 61#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 62#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 65#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 66#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_NAPI_WEIGHT 64
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77#define RTL8169_TX_TIMEOUT (6*HZ)
78#define RTL8169_PHY_TIMEOUT (10*HZ)
79
ea8dbdd1 80#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 82#define RTL_EEPROM_SIG_ADDR 0x0000
83
1da177e4
LT		 84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
f21b75e9 93 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 121};
122
1da177e4
LT		 123#define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
3c6bee1d 126static const struct {
1da177e4
LT		 127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130} rtl_chip_info[] = {
ba6eb6ee
FR		 131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 158};
159#undef _R
160
bcf0bf90
FR		 161enum cfg_version {
162 RTL_CFG_0 = 0x00,
163 RTL_CFG_1,
164 RTL_CFG_2
165};
166
07ce4064
FR		 167static void rtl_hw_start_8169(struct net_device *);
168static void rtl_hw_start_8168(struct net_device *);
169static void rtl_hw_start_8101(struct net_device *);
170
a3aa1884 171static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 182 { 0x0001, 0x8168,
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 184 {0,},
185};
186
187MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
189static int rx_copybreak = 200;
35317688 190static int use_dac = -1;
b57b7e5a
SH		 191static struct {
192 u32 msg_enable;
193} debug = { -1 };
1da177e4 194
07d3f51f
FR		 195enum rtl_registers {
196 MAC0 = 0, /* Ethernet hardware address. */
773d2021 197 MAC4 = 4,
07d3f51f
FR		 198 MAR0 = 8, /* Multicast filter. */
199 CounterAddrLow = 0x10,
200 CounterAddrHigh = 0x14,
201 TxDescStartAddrLow = 0x20,
202 TxDescStartAddrHigh = 0x24,
203 TxHDescStartAddrLow = 0x28,
204 TxHDescStartAddrHigh = 0x2c,
205 FLASH = 0x30,
206 ERSR = 0x36,
207 ChipCmd = 0x37,
208 TxPoll = 0x38,
209 IntrMask = 0x3c,
210 IntrStatus = 0x3e,
211 TxConfig = 0x40,
212 RxConfig = 0x44,
213 RxMissed = 0x4c,
214 Cfg9346 = 0x50,
215 Config0 = 0x51,
216 Config1 = 0x52,
217 Config2 = 0x53,
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 MultiIntr = 0x5c,
222 PHYAR = 0x60,
07d3f51f
FR		 223 PHYstatus = 0x6c,
224 RxMaxSize = 0xda,
225 CPlusCmd = 0xe0,
226 IntrMitigate = 0xe2,
227 RxDescAddrLow = 0xe4,
228 RxDescAddrHigh = 0xe8,
229 EarlyTxThres = 0xec,
230 FuncEvent = 0xf0,
231 FuncEventMask = 0xf4,
232 FuncPresetState = 0xf8,
233 FuncForceEvent = 0xfc,
1da177e4
LT		 234};
235
f162a5d1
FR		 236enum rtl8110_registers {
237 TBICSR = 0x64,
238 TBI_ANAR = 0x68,
239 TBI_LPAR = 0x6a,
240};
241
242enum rtl8168_8101_registers {
243 CSIDR = 0x64,
244 CSIAR = 0x68,
245#define CSIAR_FLAG 0x80000000
246#define CSIAR_WRITE_CMD 0x80000000
247#define CSIAR_BYTE_ENABLE 0x0f
248#define CSIAR_BYTE_ENABLE_SHIFT 12
249#define CSIAR_ADDR_MASK 0x0fff
250
251 EPHYAR = 0x80,
252#define EPHYAR_FLAG 0x80000000
253#define EPHYAR_WRITE_CMD 0x80000000
254#define EPHYAR_REG_MASK 0x1f
255#define EPHYAR_REG_SHIFT 16
256#define EPHYAR_DATA_MASK 0xffff
257 DBG_REG = 0xd1,
258#define FIX_NAK_1 (1 << 4)
259#define FIX_NAK_2 (1 << 3)
daf9df6d 260 EFUSEAR = 0xdc,
261#define EFUSEAR_FLAG 0x80000000
262#define EFUSEAR_WRITE_CMD 0x80000000
263#define EFUSEAR_READ_CMD 0x00000000
264#define EFUSEAR_REG_MASK 0x03ff
265#define EFUSEAR_REG_SHIFT 8
266#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 267};
268
07d3f51f 269enum rtl_register_content {
1da177e4 270 /* InterruptStatusBits */
07d3f51f
FR		 271 SYSErr = 0x8000,
272 PCSTimeout = 0x4000,
273 SWInt = 0x0100,
274 TxDescUnavail = 0x0080,
275 RxFIFOOver = 0x0040,
276 LinkChg = 0x0020,
277 RxOverflow = 0x0010,
278 TxErr = 0x0008,
279 TxOK = 0x0004,
280 RxErr = 0x0002,
281 RxOK = 0x0001,
1da177e4
LT		 282
283 /* RxStatusDesc */
9dccf611
FR		 284 RxFOVF = (1 << 23),
285 RxRWT = (1 << 22),
286 RxRES = (1 << 21),
287 RxRUNT = (1 << 20),
288 RxCRC = (1 << 19),
1da177e4
LT		 289
290 /* ChipCmdBits */
07d3f51f
FR		 291 CmdReset = 0x10,
292 CmdRxEnb = 0x08,
293 CmdTxEnb = 0x04,
294 RxBufEmpty = 0x01,
1da177e4 295
275391a4
FR		 296 /* TXPoll register p.5 */
297 HPQ = 0x80, /* Poll cmd on the high prio queue */
298 NPQ = 0x40, /* Poll cmd on the low prio queue */
299 FSWInt = 0x01, /* Forced software interrupt */
300
1da177e4 301 /* Cfg9346Bits */
07d3f51f
FR		 302 Cfg9346_Lock = 0x00,
303 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 304
305 /* rx_mode_bits */
07d3f51f
FR		 306 AcceptErr = 0x20,
307 AcceptRunt = 0x10,
308 AcceptBroadcast = 0x08,
309 AcceptMulticast = 0x04,
310 AcceptMyPhys = 0x02,
311 AcceptAllPhys = 0x01,
1da177e4
LT		 312
313 /* RxConfigBits */
07d3f51f
FR		 314 RxCfgFIFOShift = 13,
315 RxCfgDMAShift = 8,
1da177e4
LT		 316
317 /* TxConfigBits */
318 TxInterFrameGapShift = 24,
319 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
320
5d06a99f 321 /* Config1 register p.24 */
f162a5d1
FR		 322 LEDS1 = (1 << 7),
323 LEDS0 = (1 << 6),
fbac58fc 324 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 325 Speed_down = (1 << 4),
326 MEMMAP = (1 << 3),
327 IOMAP = (1 << 2),
328 VPD = (1 << 1),
5d06a99f
FR		 329 PMEnable = (1 << 0), /* Power Management Enable */
330
6dccd16b
FR		 331 /* Config2 register p. 25 */
332 PCI_Clock_66MHz = 0x01,
333 PCI_Clock_33MHz = 0x00,
334
61a4dcc2
FR		 335 /* Config3 register p.25 */
336 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
337 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 338 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 339
5d06a99f 340 /* Config5 register p.27 */
61a4dcc2
FR		 341 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
342 MWF = (1 << 5), /* Accept Multicast wakeup frame */
343 UWF = (1 << 4), /* Accept Unicast wakeup frame */
344 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 345 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
346
1da177e4
LT		 347 /* TBICSR p.28 */
348 TBIReset = 0x80000000,
349 TBILoopback = 0x40000000,
350 TBINwEnable = 0x20000000,
351 TBINwRestart = 0x10000000,
352 TBILinkOk = 0x02000000,
353 TBINwComplete = 0x01000000,
354
355 /* CPlusCmd p.31 */
f162a5d1
FR		 356 EnableBist = (1 << 15), // 8168 8101
357 Mac_dbgo_oe = (1 << 14), // 8168 8101
358 Normal_mode = (1 << 13), // unused
359 Force_half_dup = (1 << 12), // 8168 8101
360 Force_rxflow_en = (1 << 11), // 8168 8101
361 Force_txflow_en = (1 << 10), // 8168 8101
362 Cxpl_dbg_sel = (1 << 9), // 8168 8101
363 ASF = (1 << 8), // 8168 8101
364 PktCntrDisable = (1 << 7), // 8168 8101
365 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 366 RxVlan = (1 << 6),
367 RxChkSum = (1 << 5),
368 PCIDAC = (1 << 4),
369 PCIMulRW = (1 << 3),
0e485150
FR		 370 INTT_0 = 0x0000, // 8168
371 INTT_1 = 0x0001, // 8168
372 INTT_2 = 0x0002, // 8168
373 INTT_3 = 0x0003, // 8168
1da177e4
LT		 374
375 /* rtl8169_PHYstatus */
07d3f51f
FR		 376 TBI_Enable = 0x80,
377 TxFlowCtrl = 0x40,
378 RxFlowCtrl = 0x20,
379 _1000bpsF = 0x10,
380 _100bps = 0x08,
381 _10bps = 0x04,
382 LinkStatus = 0x02,
383 FullDup = 0x01,
1da177e4 384
1da177e4 385 /* _TBICSRBit */
07d3f51f 386 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 387
388 /* DumpCounterCommand */
07d3f51f 389 CounterDump = 0x8,
1da177e4
LT		 390};
391
07d3f51f 392enum desc_status_bit {
1da177e4
LT		 393 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
394 RingEnd = (1 << 30), /* End of descriptor ring */
395 FirstFrag = (1 << 29), /* First segment of a packet */
396 LastFrag = (1 << 28), /* Final segment of a packet */
397
398 /* Tx private */
399 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
400 MSSShift = 16, /* MSS value position */
401 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
402 IPCS = (1 << 18), /* Calculate IP checksum */
403 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
404 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
405 TxVlanTag = (1 << 17), /* Add VLAN tag */
406
407 /* Rx private */
408 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
409 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
410
411#define RxProtoUDP (PID1)
412#define RxProtoTCP (PID0)
413#define RxProtoIP (PID1 | PID0)
414#define RxProtoMask RxProtoIP
415
416 IPFail = (1 << 16), /* IP checksum failed */
417 UDPFail = (1 << 15), /* UDP/IP checksum failed */
418 TCPFail = (1 << 14), /* TCP/IP checksum failed */
419 RxVlanTag = (1 << 16), /* VLAN tag available */
420};
421
422#define RsvdMask 0x3fffc000
423
424struct TxDesc {
6cccd6e7
REB		 425 __le32 opts1;
426 __le32 opts2;
427 __le64 addr;
1da177e4
LT		 428};
429
430struct RxDesc {
6cccd6e7
REB		 431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
1da177e4
LT		 434};
435
436struct ring_info {
437 struct sk_buff *skb;
438 u32 len;
439 u8 __pad[sizeof(void *) - sizeof(u32)];
440};
441
f23e7fda 442enum features {
ccdffb9a
FR		 443 RTL_FEATURE_WOL = (1 << 0),
444 RTL_FEATURE_MSI = (1 << 1),
445 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 446};
447
355423d0
IV		 448struct rtl8169_counters {
449 __le64 tx_packets;
450 __le64 rx_packets;
451 __le64 tx_errors;
452 __le32 rx_errors;
453 __le16 rx_missed;
454 __le16 align_errors;
455 __le32 tx_one_collision;
456 __le32 tx_multi_collision;
457 __le64 rx_unicast;
458 __le64 rx_broadcast;
459 __le32 rx_multicast;
460 __le16 tx_aborted;
461 __le16 tx_underun;
462};
463
1da177e4
LT		 464struct rtl8169_private {
465 void __iomem *mmio_addr; /* memory map physical address */
466 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 467 struct net_device *dev;
bea3348e 468 struct napi_struct napi;
1da177e4 469 spinlock_t lock; /* spin lock flag */
b57b7e5a 470 u32 msg_enable;
1da177e4
LT		 471 int chipset;
472 int mac_version;
1da177e4
LT		 473 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
474 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
475 u32 dirty_rx;
476 u32 dirty_tx;
477 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
478 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
479 dma_addr_t TxPhyAddr;
480 dma_addr_t RxPhyAddr;
481 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
482 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 483 unsigned align;
1da177e4
LT		 484 unsigned rx_buf_sz;
485 struct timer_list timer;
486 u16 cp_cmd;
0e485150
FR		 487 u16 intr_event;
488 u16 napi_event;
1da177e4 489 u16 intr_mask;
1da177e4
LT		 490 int phy_1000_ctrl_reg;
491#ifdef CONFIG_R8169_VLAN
492 struct vlan_group *vlgrp;
493#endif
494 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 495 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 496 void (*phy_reset_enable)(void __iomem *);
07ce4064 497 void (*hw_start)(struct net_device *);
1da177e4
LT		 498 unsigned int (*phy_reset_pending)(void __iomem *);
499 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 500 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 501 int pcie_cap;
c4028958 502 struct delayed_work task;
f23e7fda 503 unsigned features;
ccdffb9a
FR		 504
505 struct mii_if_info mii;
355423d0 506 struct rtl8169_counters counters;
1da177e4
LT		 507};
508
979b6c13 509MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 510MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 511module_param(rx_copybreak, int, 0);
1b7efd58 512MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4 513module_param(use_dac, int, 0);
35317688
RH		 514MODULE_PARM_DESC(use_dac, "Enable PCI DAC. -1 defaults on for PCI Express only."
515" Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 516module_param_named(debug, debug.msg_enable, int, 0);
517MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 518MODULE_LICENSE("GPL");
519MODULE_VERSION(RTL8169_VERSION);
520
521static int rtl8169_open(struct net_device *dev);
61357325
SH		 522static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
523 struct net_device *dev);
7d12e780 524static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 525static int rtl8169_init_ring(struct net_device *dev);
07ce4064 526static void rtl_hw_start(struct net_device *dev);
1da177e4 527static int rtl8169_close(struct net_device *dev);
07ce4064 528static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 529static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 530static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 531static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 532 void __iomem *, u32 budget);
4dcb7d33 533static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 534static void rtl8169_down(struct net_device *dev);
99f252b0 535static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 536static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 537
1da177e4 538static const unsigned int rtl8169_rx_config =
5b0384f4 539 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 540
07d3f51f 541static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 542{
543 int i;
544
a6baf3af 545 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 546
2371408c 547 for (i = 20; i > 0; i--) {
07d3f51f
FR		 548 /*
549 * Check if the RTL8169 has completed writing to the specified
550 * MII register.
551 */
5b0384f4 552 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 553 break;
2371408c 554 udelay(25);
1da177e4
LT		 555 }
556}
557
07d3f51f 558static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 559{
560 int i, value = -1;
561
a6baf3af 562 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 563
2371408c 564 for (i = 20; i > 0; i--) {
07d3f51f
FR		 565 /*
566 * Check if the RTL8169 has completed retrieving data from
567 * the specified MII register.
568 */
1da177e4 569 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 570 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 571 break;
572 }
2371408c 573 udelay(25);
1da177e4
LT		 574 }
575 return value;
576}
577
dacf8154
FR		 578static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
579{
580 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
581}
582
daf9df6d 583static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
584{
585 int val;
586
587 val = mdio_read(ioaddr, reg_addr);
588 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
589}
590
ccdffb9a
FR		 591static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
592 int val)
593{
594 struct rtl8169_private *tp = netdev_priv(dev);
595 void __iomem *ioaddr = tp->mmio_addr;
596
597 mdio_write(ioaddr, location, val);
598}
599
600static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
601{
602 struct rtl8169_private *tp = netdev_priv(dev);
603 void __iomem *ioaddr = tp->mmio_addr;
604
605 return mdio_read(ioaddr, location);
606}
607
dacf8154
FR		 608static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
609{
610 unsigned int i;
611
612 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
613 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
614
615 for (i = 0; i < 100; i++) {
616 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
617 break;
618 udelay(10);
619 }
620}
621
622static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
623{
624 u16 value = 0xffff;
625 unsigned int i;
626
627 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
628
629 for (i = 0; i < 100; i++) {
630 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
631 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
632 break;
633 }
634 udelay(10);
635 }
636
637 return value;
638}
639
640static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
641{
642 unsigned int i;
643
644 RTL_W32(CSIDR, value);
645 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
646 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
647
648 for (i = 0; i < 100; i++) {
649 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
650 break;
651 udelay(10);
652 }
653}
654
655static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
656{
657 u32 value = ~0x00;
658 unsigned int i;
659
660 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
661 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
662
663 for (i = 0; i < 100; i++) {
664 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
665 value = RTL_R32(CSIDR);
666 break;
667 }
668 udelay(10);
669 }
670
671 return value;
672}
673
daf9df6d 674static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
675{
676 u8 value = 0xff;
677 unsigned int i;
678
679 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
680
681 for (i = 0; i < 300; i++) {
682 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
683 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
684 break;
685 }
686 udelay(100);
687 }
688
689 return value;
690}
691
1da177e4
LT		 692static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
693{
694 RTL_W16(IntrMask, 0x0000);
695
696 RTL_W16(IntrStatus, 0xffff);
697}
698
699static void rtl8169_asic_down(void __iomem *ioaddr)
700{
701 RTL_W8(ChipCmd, 0x00);
702 rtl8169_irq_mask_and_ack(ioaddr);
703 RTL_R16(CPlusCmd);
704}
705
706static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
707{
708 return RTL_R32(TBICSR) & TBIReset;
709}
710
711static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
712{
64e4bfb4 713 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 714}
715
716static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
717{
718 return RTL_R32(TBICSR) & TBILinkOk;
719}
720
721static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
722{
723 return RTL_R8(PHYstatus) & LinkStatus;
724}
725
726static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
727{
728 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
729}
730
731static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
732{
733 unsigned int val;
734
9e0db8ef
FR		 735 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
736 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 737}
738
739static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 740 struct rtl8169_private *tp,
741 void __iomem *ioaddr)
1da177e4
LT		 742{
743 unsigned long flags;
744
745 spin_lock_irqsave(&tp->lock, flags);
746 if (tp->link_ok(ioaddr)) {
747 netif_carrier_on(dev);
bf82c189 748 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 749 } else {
1da177e4 750 netif_carrier_off(dev);
bf82c189 751 netif_info(tp, ifdown, dev, "link down\n");
b57b7e5a 752 }
1da177e4
LT		 753 spin_unlock_irqrestore(&tp->lock, flags);
754}
755
61a4dcc2
FR		 756static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
757{
758 struct rtl8169_private *tp = netdev_priv(dev);
759 void __iomem *ioaddr = tp->mmio_addr;
760 u8 options;
761
762 wol->wolopts = 0;
763
764#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
765 wol->supported = WAKE_ANY;
766
767 spin_lock_irq(&tp->lock);
768
769 options = RTL_R8(Config1);
770 if (!(options & PMEnable))
771 goto out_unlock;
772
773 options = RTL_R8(Config3);
774 if (options & LinkUp)
775 wol->wolopts |= WAKE_PHY;
776 if (options & MagicPacket)
777 wol->wolopts |= WAKE_MAGIC;
778
779 options = RTL_R8(Config5);
780 if (options & UWF)
781 wol->wolopts |= WAKE_UCAST;
782 if (options & BWF)
5b0384f4 783 wol->wolopts |= WAKE_BCAST;
61a4dcc2 784 if (options & MWF)
5b0384f4 785 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 786
787out_unlock:
788 spin_unlock_irq(&tp->lock);
789}
790
791static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
792{
793 struct rtl8169_private *tp = netdev_priv(dev);
794 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 795 unsigned int i;
350f7596 796 static const struct {
61a4dcc2
FR		 797 u32 opt;
798 u16 reg;
799 u8 mask;
800 } cfg[] = {
801 { WAKE_ANY, Config1, PMEnable },
802 { WAKE_PHY, Config3, LinkUp },
803 { WAKE_MAGIC, Config3, MagicPacket },
804 { WAKE_UCAST, Config5, UWF },
805 { WAKE_BCAST, Config5, BWF },
806 { WAKE_MCAST, Config5, MWF },
807 { WAKE_ANY, Config5, LanWake }
808 };
809
810 spin_lock_irq(&tp->lock);
811
812 RTL_W8(Cfg9346, Cfg9346_Unlock);
813
814 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
815 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
816 if (wol->wolopts & cfg[i].opt)
817 options |= cfg[i].mask;
818 RTL_W8(cfg[i].reg, options);
819 }
820
821 RTL_W8(Cfg9346, Cfg9346_Lock);
822
f23e7fda
FR		 823 if (wol->wolopts)
824 tp->features |= RTL_FEATURE_WOL;
825 else
826 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 827 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 828
829 spin_unlock_irq(&tp->lock);
830
831 return 0;
832}
833
1da177e4
LT		 834static void rtl8169_get_drvinfo(struct net_device *dev,
835 struct ethtool_drvinfo *info)
836{
837 struct rtl8169_private *tp = netdev_priv(dev);
838
839 strcpy(info->driver, MODULENAME);
840 strcpy(info->version, RTL8169_VERSION);
841 strcpy(info->bus_info, pci_name(tp->pci_dev));
842}
843
844static int rtl8169_get_regs_len(struct net_device *dev)
845{
846 return R8169_REGS_SIZE;
847}
848
849static int rtl8169_set_speed_tbi(struct net_device *dev,
850 u8 autoneg, u16 speed, u8 duplex)
851{
852 struct rtl8169_private *tp = netdev_priv(dev);
853 void __iomem *ioaddr = tp->mmio_addr;
854 int ret = 0;
855 u32 reg;
856
857 reg = RTL_R32(TBICSR);
858 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
859 (duplex == DUPLEX_FULL)) {
860 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
861 } else if (autoneg == AUTONEG_ENABLE)
862 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
863 else {
bf82c189
JP		 864 netif_warn(tp, link, dev,
865 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 866 ret = -EOPNOTSUPP;
867 }
868
869 return ret;
870}
871
872static int rtl8169_set_speed_xmii(struct net_device *dev,
873 u8 autoneg, u16 speed, u8 duplex)
874{
875 struct rtl8169_private *tp = netdev_priv(dev);
876 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 877 int giga_ctrl, bmcr;
1da177e4
LT		 878
879 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 880 int auto_nego;
881
882 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 883 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
884 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 885 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 886
3577aa1b 887 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
888 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 889
3577aa1b 890 /* The 8100e/8101e/8102e do Fast Ethernet only. */
891 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
892 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
893 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
894 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
895 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
898 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
899 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 900 } else {
901 netif_info(tp, link, dev,
902 "PHY does not support 1000Mbps\n");
bcf0bf90 903 }
1da177e4 904
3577aa1b 905 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
906
907 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
908 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
909 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
910 /*
911 * Wake up the PHY.
912 * Vendor specific (0x1f) and reserved (0x0e) MII
913 * registers.
914 */
915 mdio_write(ioaddr, 0x1f, 0x0000);
916 mdio_write(ioaddr, 0x0e, 0x0000);
917 }
918
919 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
920 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
921 } else {
922 giga_ctrl = 0;
923
924 if (speed == SPEED_10)
925 bmcr = 0;
926 else if (speed == SPEED_100)
927 bmcr = BMCR_SPEED100;
928 else
929 return -EINVAL;
930
931 if (duplex == DUPLEX_FULL)
932 bmcr |= BMCR_FULLDPLX;
623a1593 933
2584fbc3 934 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 935 }
936
1da177e4
LT		 937 tp->phy_1000_ctrl_reg = giga_ctrl;
938
3577aa1b 939 mdio_write(ioaddr, MII_BMCR, bmcr);
940
941 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
942 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
943 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
944 mdio_write(ioaddr, 0x17, 0x2138);
945 mdio_write(ioaddr, 0x0e, 0x0260);
946 } else {
947 mdio_write(ioaddr, 0x17, 0x2108);
948 mdio_write(ioaddr, 0x0e, 0x0000);
949 }
950 }
951
1da177e4
LT		 952 return 0;
953}
954
955static int rtl8169_set_speed(struct net_device *dev,
956 u8 autoneg, u16 speed, u8 duplex)
957{
958 struct rtl8169_private *tp = netdev_priv(dev);
959 int ret;
960
961 ret = tp->set_speed(dev, autoneg, speed, duplex);
962
64e4bfb4 963 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 964 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
965
966 return ret;
967}
968
969static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
970{
971 struct rtl8169_private *tp = netdev_priv(dev);
972 unsigned long flags;
973 int ret;
974
975 spin_lock_irqsave(&tp->lock, flags);
976 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
977 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 978
1da177e4
LT		 979 return ret;
980}
981
982static u32 rtl8169_get_rx_csum(struct net_device *dev)
983{
984 struct rtl8169_private *tp = netdev_priv(dev);
985
986 return tp->cp_cmd & RxChkSum;
987}
988
989static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
990{
991 struct rtl8169_private *tp = netdev_priv(dev);
992 void __iomem *ioaddr = tp->mmio_addr;
993 unsigned long flags;
994
995 spin_lock_irqsave(&tp->lock, flags);
996
997 if (data)
998 tp->cp_cmd |= RxChkSum;
999 else
1000 tp->cp_cmd &= ~RxChkSum;
1001
1002 RTL_W16(CPlusCmd, tp->cp_cmd);
1003 RTL_R16(CPlusCmd);
1004
1005 spin_unlock_irqrestore(&tp->lock, flags);
1006
1007 return 0;
1008}
1009
1010#ifdef CONFIG_R8169_VLAN
1011
1012static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1013 struct sk_buff *skb)
1014{
1015 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1016 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1017}
1018
1019static void rtl8169_vlan_rx_register(struct net_device *dev,
1020 struct vlan_group *grp)
1021{
1022 struct rtl8169_private *tp = netdev_priv(dev);
1023 void __iomem *ioaddr = tp->mmio_addr;
1024 unsigned long flags;
1025
1026 spin_lock_irqsave(&tp->lock, flags);
1027 tp->vlgrp = grp;
05af2142
SW		 1028 /*
1029 * Do not disable RxVlan on 8110SCd.
1030 */
1031 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1032 tp->cp_cmd |= RxVlan;
1033 else
1034 tp->cp_cmd &= ~RxVlan;
1035 RTL_W16(CPlusCmd, tp->cp_cmd);
1036 RTL_R16(CPlusCmd);
1037 spin_unlock_irqrestore(&tp->lock, flags);
1038}
1039
1da177e4
LT		 1040static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1041 struct sk_buff *skb)
1042{
1043 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1044 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1045 int ret;
1046
865c652d
FR		 1047 if (vlgrp && (opts2 & RxVlanTag)) {
1048 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1049 ret = 0;
1050 } else
1051 ret = -1;
1052 desc->opts2 = 0;
1053 return ret;
1054}
1055
1056#else /* !CONFIG_R8169_VLAN */
1057
1058static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1059 struct sk_buff *skb)
1060{
1061 return 0;
1062}
1063
1064static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1065 struct sk_buff *skb)
1066{
1067 return -1;
1068}
1069
1070#endif
1071
ccdffb9a 1072static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1073{
1074 struct rtl8169_private *tp = netdev_priv(dev);
1075 void __iomem *ioaddr = tp->mmio_addr;
1076 u32 status;
1077
1078 cmd->supported =
1079 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1080 cmd->port = PORT_FIBRE;
1081 cmd->transceiver = XCVR_INTERNAL;
1082
1083 status = RTL_R32(TBICSR);
1084 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1085 cmd->autoneg = !!(status & TBINwEnable);
1086
1087 cmd->speed = SPEED_1000;
1088 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1089
1090 return 0;
1da177e4
LT		 1091}
1092
ccdffb9a 1093static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1094{
1095 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1096
1097 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1098}
1099
1100static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1101{
1102 struct rtl8169_private *tp = netdev_priv(dev);
1103 unsigned long flags;
ccdffb9a 1104 int rc;
1da177e4
LT		 1105
1106 spin_lock_irqsave(&tp->lock, flags);
1107
ccdffb9a 1108 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1109
1110 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1111 return rc;
1da177e4
LT		 1112}
1113
1114static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1115 void *p)
1116{
5b0384f4
FR		 1117 struct rtl8169_private *tp = netdev_priv(dev);
1118 unsigned long flags;
1da177e4 1119
5b0384f4
FR		 1120 if (regs->len > R8169_REGS_SIZE)
1121 regs->len = R8169_REGS_SIZE;
1da177e4 1122
5b0384f4
FR		 1123 spin_lock_irqsave(&tp->lock, flags);
1124 memcpy_fromio(p, tp->mmio_addr, regs->len);
1125 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1126}
1127
b57b7e5a
SH		 1128static u32 rtl8169_get_msglevel(struct net_device *dev)
1129{
1130 struct rtl8169_private *tp = netdev_priv(dev);
1131
1132 return tp->msg_enable;
1133}
1134
1135static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1136{
1137 struct rtl8169_private *tp = netdev_priv(dev);
1138
1139 tp->msg_enable = value;
1140}
1141
d4a3a0fc
SH		 1142static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1143 "tx_packets",
1144 "rx_packets",
1145 "tx_errors",
1146 "rx_errors",
1147 "rx_missed",
1148 "align_errors",
1149 "tx_single_collisions",
1150 "tx_multi_collisions",
1151 "unicast",
1152 "broadcast",
1153 "multicast",
1154 "tx_aborted",
1155 "tx_underrun",
1156};
1157
b9f2c044 1158static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1159{
b9f2c044
JG		 1160 switch (sset) {
1161 case ETH_SS_STATS:
1162 return ARRAY_SIZE(rtl8169_gstrings);
1163 default:
1164 return -EOPNOTSUPP;
1165 }
d4a3a0fc
SH		 1166}
1167
355423d0 1168static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1169{
1170 struct rtl8169_private *tp = netdev_priv(dev);
1171 void __iomem *ioaddr = tp->mmio_addr;
1172 struct rtl8169_counters *counters;
1173 dma_addr_t paddr;
1174 u32 cmd;
355423d0 1175 int wait = 1000;
d4a3a0fc 1176
355423d0
IV		 1177 /*
1178 * Some chips are unable to dump tally counters when the receiver
1179 * is disabled.
1180 */
1181 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1182 return;
d4a3a0fc
SH		 1183
1184 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1185 if (!counters)
1186 return;
1187
1188 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1189 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1190 RTL_W32(CounterAddrLow, cmd);
1191 RTL_W32(CounterAddrLow, cmd | CounterDump);
1192
355423d0
IV		 1193 while (wait--) {
1194 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1195 /* copy updated counters */
1196 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1197 break;
355423d0
IV		 1198 }
1199 udelay(10);
d4a3a0fc
SH		 1200 }
1201
1202 RTL_W32(CounterAddrLow, 0);
1203 RTL_W32(CounterAddrHigh, 0);
1204
d4a3a0fc
SH		 1205 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1206}
1207
355423d0
IV		 1208static void rtl8169_get_ethtool_stats(struct net_device *dev,
1209 struct ethtool_stats *stats, u64 *data)
1210{
1211 struct rtl8169_private *tp = netdev_priv(dev);
1212
1213 ASSERT_RTNL();
1214
1215 rtl8169_update_counters(dev);
1216
1217 data[0] = le64_to_cpu(tp->counters.tx_packets);
1218 data[1] = le64_to_cpu(tp->counters.rx_packets);
1219 data[2] = le64_to_cpu(tp->counters.tx_errors);
1220 data[3] = le32_to_cpu(tp->counters.rx_errors);
1221 data[4] = le16_to_cpu(tp->counters.rx_missed);
1222 data[5] = le16_to_cpu(tp->counters.align_errors);
1223 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1224 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1225 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1226 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1227 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1228 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1229 data[12] = le16_to_cpu(tp->counters.tx_underun);
1230}
1231
d4a3a0fc
SH		 1232static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1233{
1234 switch(stringset) {
1235 case ETH_SS_STATS:
1236 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1237 break;
1238 }
1239}
1240
7282d491 1241static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1242 .get_drvinfo = rtl8169_get_drvinfo,
1243 .get_regs_len = rtl8169_get_regs_len,
1244 .get_link = ethtool_op_get_link,
1245 .get_settings = rtl8169_get_settings,
1246 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1247 .get_msglevel = rtl8169_get_msglevel,
1248 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1249 .get_rx_csum = rtl8169_get_rx_csum,
1250 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1251 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1252 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1253 .set_tso = ethtool_op_set_tso,
1254 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1255 .get_wol = rtl8169_get_wol,
1256 .set_wol = rtl8169_set_wol,
d4a3a0fc 1257 .get_strings = rtl8169_get_strings,
b9f2c044 1258 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1259 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1260};
1261
07d3f51f
FR		 1262static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1263 void __iomem *ioaddr)
1da177e4 1264{
0e485150
FR		 1265 /*
1266 * The driver currently handles the 8168Bf and the 8168Be identically
1267 * but they can be identified more specifically through the test below
1268 * if needed:
1269 *
1270 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1271 *
1272 * Same thing for the 8101Eb and the 8101Ec:
1273 *
1274 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1275 */
350f7596 1276 static const struct {
1da177e4 1277 u32 mask;
e3cf0cc0 1278 u32 val;
1da177e4
LT		 1279 int mac_version;
1280 } mac_info[] = {
5b538df9 1281 /* 8168D family. */
daf9df6d 1282 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1283 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1284 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1285 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1286
ef808d50 1287 /* 8168C family. */
7f3e3d3a 1288 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1289 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1290 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1291 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1292 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1293 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1294 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1295 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1296 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1297
1298 /* 8168B family. */
1299 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1300 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1301 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1302 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1303
1304 /* 8101 family. */
2857ffb7
FR		 1305 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1306 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1307 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1308 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1309 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1310 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1311 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1312 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1313 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1314 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1315 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1316 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1317 /* FIXME: where did these entries come from ? -- FR */
1318 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1319 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1320
1321 /* 8110 family. */
1322 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1323 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1324 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1325 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1326 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1327 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1328
f21b75e9
JD		 1329 /* Catch-all */
1330 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1331 }, *p = mac_info;
1332 u32 reg;
1333
e3cf0cc0
FR		 1334 reg = RTL_R32(TxConfig);
1335 while ((reg & p->mask) != p->val)
1da177e4
LT		 1336 p++;
1337 tp->mac_version = p->mac_version;
1338}
1339
1340static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1341{
bcf0bf90 1342 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1343}
1344
867763c1
FR		 1345struct phy_reg {
1346 u16 reg;
1347 u16 val;
1348};
1349
350f7596 1350static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1351{
1352 while (len-- > 0) {
1353 mdio_write(ioaddr, regs->reg, regs->val);
1354 regs++;
1355 }
1356}
1357
5615d9f1 1358static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1359{
350f7596 1360 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1361 { 0x1f, 0x0001 },
1362 { 0x06, 0x006e },
1363 { 0x08, 0x0708 },
1364 { 0x15, 0x4000 },
1365 { 0x18, 0x65c7 },
1da177e4 1366
0b9b571d 1367 { 0x1f, 0x0001 },
1368 { 0x03, 0x00a1 },
1369 { 0x02, 0x0008 },
1370 { 0x01, 0x0120 },
1371 { 0x00, 0x1000 },
1372 { 0x04, 0x0800 },
1373 { 0x04, 0x0000 },
1da177e4 1374
0b9b571d 1375 { 0x03, 0xff41 },
1376 { 0x02, 0xdf60 },
1377 { 0x01, 0x0140 },
1378 { 0x00, 0x0077 },
1379 { 0x04, 0x7800 },
1380 { 0x04, 0x7000 },
1381
1382 { 0x03, 0x802f },
1383 { 0x02, 0x4f02 },
1384 { 0x01, 0x0409 },
1385 { 0x00, 0xf0f9 },
1386 { 0x04, 0x9800 },
1387 { 0x04, 0x9000 },
1388
1389 { 0x03, 0xdf01 },
1390 { 0x02, 0xdf20 },
1391 { 0x01, 0xff95 },
1392 { 0x00, 0xba00 },
1393 { 0x04, 0xa800 },
1394 { 0x04, 0xa000 },
1395
1396 { 0x03, 0xff41 },
1397 { 0x02, 0xdf20 },
1398 { 0x01, 0x0140 },
1399 { 0x00, 0x00bb },
1400 { 0x04, 0xb800 },
1401 { 0x04, 0xb000 },
1402
1403 { 0x03, 0xdf41 },
1404 { 0x02, 0xdc60 },
1405 { 0x01, 0x6340 },
1406 { 0x00, 0x007d },
1407 { 0x04, 0xd800 },
1408 { 0x04, 0xd000 },
1409
1410 { 0x03, 0xdf01 },
1411 { 0x02, 0xdf20 },
1412 { 0x01, 0x100a },
1413 { 0x00, 0xa0ff },
1414 { 0x04, 0xf800 },
1415 { 0x04, 0xf000 },
1416
1417 { 0x1f, 0x0000 },
1418 { 0x0b, 0x0000 },
1419 { 0x00, 0x9200 }
1420 };
1da177e4 1421
0b9b571d 1422 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1423}
1424
5615d9f1
FR		 1425static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1426{
350f7596 1427 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1428 { 0x1f, 0x0002 },
1429 { 0x01, 0x90d0 },
1430 { 0x1f, 0x0000 }
1431 };
1432
1433 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1434}
1435
2e955856 1436static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1437 void __iomem *ioaddr)
1438{
1439 struct pci_dev *pdev = tp->pci_dev;
1440 u16 vendor_id, device_id;
1441
1442 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1443 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1444
1445 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1446 return;
1447
1448 mdio_write(ioaddr, 0x1f, 0x0001);
1449 mdio_write(ioaddr, 0x10, 0xf01b);
1450 mdio_write(ioaddr, 0x1f, 0x0000);
1451}
1452
1453static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1454 void __iomem *ioaddr)
1455{
350f7596 1456 static const struct phy_reg phy_reg_init[] = {
2e955856 1457 { 0x1f, 0x0001 },
1458 { 0x04, 0x0000 },
1459 { 0x03, 0x00a1 },
1460 { 0x02, 0x0008 },
1461 { 0x01, 0x0120 },
1462 { 0x00, 0x1000 },
1463 { 0x04, 0x0800 },
1464 { 0x04, 0x9000 },
1465 { 0x03, 0x802f },
1466 { 0x02, 0x4f02 },
1467 { 0x01, 0x0409 },
1468 { 0x00, 0xf099 },
1469 { 0x04, 0x9800 },
1470 { 0x04, 0xa000 },
1471 { 0x03, 0xdf01 },
1472 { 0x02, 0xdf20 },
1473 { 0x01, 0xff95 },
1474 { 0x00, 0xba00 },
1475 { 0x04, 0xa800 },
1476 { 0x04, 0xf000 },
1477 { 0x03, 0xdf01 },
1478 { 0x02, 0xdf20 },
1479 { 0x01, 0x101a },
1480 { 0x00, 0xa0ff },
1481 { 0x04, 0xf800 },
1482 { 0x04, 0x0000 },
1483 { 0x1f, 0x0000 },
1484
1485 { 0x1f, 0x0001 },
1486 { 0x10, 0xf41b },
1487 { 0x14, 0xfb54 },
1488 { 0x18, 0xf5c7 },
1489 { 0x1f, 0x0000 },
1490
1491 { 0x1f, 0x0001 },
1492 { 0x17, 0x0cc0 },
1493 { 0x1f, 0x0000 }
1494 };
1495
1496 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1497
1498 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1499}
1500
8c7006aa 1501static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1502{
350f7596 1503 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1504 { 0x1f, 0x0001 },
1505 { 0x04, 0x0000 },
1506 { 0x03, 0x00a1 },
1507 { 0x02, 0x0008 },
1508 { 0x01, 0x0120 },
1509 { 0x00, 0x1000 },
1510 { 0x04, 0x0800 },
1511 { 0x04, 0x9000 },
1512 { 0x03, 0x802f },
1513 { 0x02, 0x4f02 },
1514 { 0x01, 0x0409 },
1515 { 0x00, 0xf099 },
1516 { 0x04, 0x9800 },
1517 { 0x04, 0xa000 },
1518 { 0x03, 0xdf01 },
1519 { 0x02, 0xdf20 },
1520 { 0x01, 0xff95 },
1521 { 0x00, 0xba00 },
1522 { 0x04, 0xa800 },
1523 { 0x04, 0xf000 },
1524 { 0x03, 0xdf01 },
1525 { 0x02, 0xdf20 },
1526 { 0x01, 0x101a },
1527 { 0x00, 0xa0ff },
1528 { 0x04, 0xf800 },
1529 { 0x04, 0x0000 },
1530 { 0x1f, 0x0000 },
1531
1532 { 0x1f, 0x0001 },
1533 { 0x0b, 0x8480 },
1534 { 0x1f, 0x0000 },
1535
1536 { 0x1f, 0x0001 },
1537 { 0x18, 0x67c7 },
1538 { 0x04, 0x2000 },
1539 { 0x03, 0x002f },
1540 { 0x02, 0x4360 },
1541 { 0x01, 0x0109 },
1542 { 0x00, 0x3022 },
1543 { 0x04, 0x2800 },
1544 { 0x1f, 0x0000 },
1545
1546 { 0x1f, 0x0001 },
1547 { 0x17, 0x0cc0 },
1548 { 0x1f, 0x0000 }
1549 };
1550
1551 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1552}
1553
236b8082
FR		 1554static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1555{
350f7596 1556 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1557 { 0x10, 0xf41b },
1558 { 0x1f, 0x0000 }
1559 };
1560
1561 mdio_write(ioaddr, 0x1f, 0x0001);
1562 mdio_patch(ioaddr, 0x16, 1 << 0);
1563
1564 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1565}
1566
1567static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1568{
350f7596 1569 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1570 { 0x1f, 0x0001 },
1571 { 0x10, 0xf41b },
1572 { 0x1f, 0x0000 }
1573 };
1574
1575 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1576}
1577
ef3386f0 1578static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1579{
350f7596 1580 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1581 { 0x1f, 0x0000 },
1582 { 0x1d, 0x0f00 },
1583 { 0x1f, 0x0002 },
1584 { 0x0c, 0x1ec8 },
1585 { 0x1f, 0x0000 }
1586 };
1587
1588 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1589}
1590
ef3386f0
FR		 1591static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1592{
350f7596 1593 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1594 { 0x1f, 0x0001 },
1595 { 0x1d, 0x3d98 },
1596 { 0x1f, 0x0000 }
1597 };
1598
1599 mdio_write(ioaddr, 0x1f, 0x0000);
1600 mdio_patch(ioaddr, 0x14, 1 << 5);
1601 mdio_patch(ioaddr, 0x0d, 1 << 5);
1602
1603 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1604}
1605
219a1e9d 1606static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1607{
350f7596 1608 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1609 { 0x1f, 0x0001 },
1610 { 0x12, 0x2300 },
867763c1
FR		 1611 { 0x1f, 0x0002 },
1612 { 0x00, 0x88d4 },
1613 { 0x01, 0x82b1 },
1614 { 0x03, 0x7002 },
1615 { 0x08, 0x9e30 },
1616 { 0x09, 0x01f0 },
1617 { 0x0a, 0x5500 },
1618 { 0x0c, 0x00c8 },
1619 { 0x1f, 0x0003 },
1620 { 0x12, 0xc096 },
1621 { 0x16, 0x000a },
f50d4275
FR		 1622 { 0x1f, 0x0000 },
1623 { 0x1f, 0x0000 },
1624 { 0x09, 0x2000 },
1625 { 0x09, 0x0000 }
867763c1
FR		 1626 };
1627
1628 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1629
1630 mdio_patch(ioaddr, 0x14, 1 << 5);
1631 mdio_patch(ioaddr, 0x0d, 1 << 5);
1632 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1633}
1634
219a1e9d 1635static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1636{
350f7596 1637 static const struct phy_reg phy_reg_init[] = {
f50d4275 1638 { 0x1f, 0x0001 },
7da97ec9 1639 { 0x12, 0x2300 },
f50d4275
FR		 1640 { 0x03, 0x802f },
1641 { 0x02, 0x4f02 },
1642 { 0x01, 0x0409 },
1643 { 0x00, 0xf099 },
1644 { 0x04, 0x9800 },
1645 { 0x04, 0x9000 },
1646 { 0x1d, 0x3d98 },
7da97ec9
FR		 1647 { 0x1f, 0x0002 },
1648 { 0x0c, 0x7eb8 },
f50d4275
FR		 1649 { 0x06, 0x0761 },
1650 { 0x1f, 0x0003 },
1651 { 0x16, 0x0f0a },
7da97ec9
FR		 1652 { 0x1f, 0x0000 }
1653 };
1654
1655 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1656
1657 mdio_patch(ioaddr, 0x16, 1 << 0);
1658 mdio_patch(ioaddr, 0x14, 1 << 5);
1659 mdio_patch(ioaddr, 0x0d, 1 << 5);
1660 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1661}
1662
197ff761
FR		 1663static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1664{
350f7596 1665 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1666 { 0x1f, 0x0001 },
1667 { 0x12, 0x2300 },
1668 { 0x1d, 0x3d98 },
1669 { 0x1f, 0x0002 },
1670 { 0x0c, 0x7eb8 },
1671 { 0x06, 0x5461 },
1672 { 0x1f, 0x0003 },
1673 { 0x16, 0x0f0a },
1674 { 0x1f, 0x0000 }
1675 };
1676
1677 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1678
1679 mdio_patch(ioaddr, 0x16, 1 << 0);
1680 mdio_patch(ioaddr, 0x14, 1 << 5);
1681 mdio_patch(ioaddr, 0x0d, 1 << 5);
1682 mdio_write(ioaddr, 0x1f, 0x0000);
1683}
1684
6fb07058
FR		 1685static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1686{
1687 rtl8168c_3_hw_phy_config(ioaddr);
1688}
1689
daf9df6d 1690static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1691{
350f7596 1692 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1693 { 0x1f, 0x0001 },
daf9df6d 1694 { 0x06, 0x4064 },
1695 { 0x07, 0x2863 },
1696 { 0x08, 0x059c },
1697 { 0x09, 0x26b4 },
1698 { 0x0a, 0x6a19 },
1699 { 0x0b, 0xdcc8 },
1700 { 0x10, 0xf06d },
1701 { 0x14, 0x7f68 },
1702 { 0x18, 0x7fd9 },
1703 { 0x1c, 0xf0ff },
1704 { 0x1d, 0x3d9c },
5b538df9 1705 { 0x1f, 0x0003 },
daf9df6d 1706 { 0x12, 0xf49f },
1707 { 0x13, 0x070b },
1708 { 0x1a, 0x05ad },
1709 { 0x14, 0x94c0 }
1710 };
350f7596 1711 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1712 { 0x1f, 0x0002 },
daf9df6d 1713 { 0x06, 0x5561 },
1714 { 0x1f, 0x0005 },
1715 { 0x05, 0x8332 },
1716 { 0x06, 0x5561 }
1717 };
350f7596 1718 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1719 { 0x1f, 0x0005 },
1720 { 0x05, 0xffc2 },
1721 { 0x1f, 0x0005 },
1722 { 0x05, 0x8000 },
1723 { 0x06, 0xf8f9 },
1724 { 0x06, 0xfaef },
1725 { 0x06, 0x59ee },
1726 { 0x06, 0xf8ea },
1727 { 0x06, 0x00ee },
1728 { 0x06, 0xf8eb },
1729 { 0x06, 0x00e0 },
1730 { 0x06, 0xf87c },
1731 { 0x06, 0xe1f8 },
1732 { 0x06, 0x7d59 },
1733 { 0x06, 0x0fef },
1734 { 0x06, 0x0139 },
1735 { 0x06, 0x029e },
1736 { 0x06, 0x06ef },
1737 { 0x06, 0x1039 },
1738 { 0x06, 0x089f },
1739 { 0x06, 0x2aee },
1740 { 0x06, 0xf8ea },
1741 { 0x06, 0x00ee },
1742 { 0x06, 0xf8eb },
1743 { 0x06, 0x01e0 },
1744 { 0x06, 0xf87c },
1745 { 0x06, 0xe1f8 },
1746 { 0x06, 0x7d58 },
1747 { 0x06, 0x409e },
1748 { 0x06, 0x0f39 },
1749 { 0x06, 0x46aa },
1750 { 0x06, 0x0bbf },
1751 { 0x06, 0x8290 },
1752 { 0x06, 0xd682 },
1753 { 0x06, 0x9802 },
1754 { 0x06, 0x014f },
1755 { 0x06, 0xae09 },
1756 { 0x06, 0xbf82 },
1757 { 0x06, 0x98d6 },
1758 { 0x06, 0x82a0 },
1759 { 0x06, 0x0201 },
1760 { 0x06, 0x4fef },
1761 { 0x06, 0x95fe },
1762 { 0x06, 0xfdfc },
1763 { 0x06, 0x05f8 },
1764 { 0x06, 0xf9fa },
1765 { 0x06, 0xeef8 },
1766 { 0x06, 0xea00 },
1767 { 0x06, 0xeef8 },
1768 { 0x06, 0xeb00 },
1769 { 0x06, 0xe2f8 },
1770 { 0x06, 0x7ce3 },
1771 { 0x06, 0xf87d },
1772 { 0x06, 0xa511 },
1773 { 0x06, 0x1112 },
1774 { 0x06, 0xd240 },
1775 { 0x06, 0xd644 },
1776 { 0x06, 0x4402 },
1777 { 0x06, 0x8217 },
1778 { 0x06, 0xd2a0 },
1779 { 0x06, 0xd6aa },
1780 { 0x06, 0xaa02 },
1781 { 0x06, 0x8217 },
1782 { 0x06, 0xae0f },
1783 { 0x06, 0xa544 },
1784 { 0x06, 0x4402 },
1785 { 0x06, 0xae4d },
1786 { 0x06, 0xa5aa },
1787 { 0x06, 0xaa02 },
1788 { 0x06, 0xae47 },
1789 { 0x06, 0xaf82 },
1790 { 0x06, 0x13ee },
1791 { 0x06, 0x834e },
1792 { 0x06, 0x00ee },
1793 { 0x06, 0x834d },
1794 { 0x06, 0x0fee },
1795 { 0x06, 0x834c },
1796 { 0x06, 0x0fee },
1797 { 0x06, 0x834f },
1798 { 0x06, 0x00ee },
1799 { 0x06, 0x8351 },
1800 { 0x06, 0x00ee },
1801 { 0x06, 0x834a },
1802 { 0x06, 0xffee },
1803 { 0x06, 0x834b },
1804 { 0x06, 0xffe0 },
1805 { 0x06, 0x8330 },
1806 { 0x06, 0xe183 },
1807 { 0x06, 0x3158 },
1808 { 0x06, 0xfee4 },
1809 { 0x06, 0xf88a },
1810 { 0x06, 0xe5f8 },
1811 { 0x06, 0x8be0 },
1812 { 0x06, 0x8332 },
1813 { 0x06, 0xe183 },
1814 { 0x06, 0x3359 },
1815 { 0x06, 0x0fe2 },
1816 { 0x06, 0x834d },
1817 { 0x06, 0x0c24 },
1818 { 0x06, 0x5af0 },
1819 { 0x06, 0x1e12 },
1820 { 0x06, 0xe4f8 },
1821 { 0x06, 0x8ce5 },
1822 { 0x06, 0xf88d },
1823 { 0x06, 0xaf82 },
1824 { 0x06, 0x13e0 },
1825 { 0x06, 0x834f },
1826 { 0x06, 0x10e4 },
1827 { 0x06, 0x834f },
1828 { 0x06, 0xe083 },
1829 { 0x06, 0x4e78 },
1830 { 0x06, 0x009f },
1831 { 0x06, 0x0ae0 },
1832 { 0x06, 0x834f },
1833 { 0x06, 0xa010 },
1834 { 0x06, 0xa5ee },
1835 { 0x06, 0x834e },
1836 { 0x06, 0x01e0 },
1837 { 0x06, 0x834e },
1838 { 0x06, 0x7805 },
1839 { 0x06, 0x9e9a },
1840 { 0x06, 0xe083 },
1841 { 0x06, 0x4e78 },
1842 { 0x06, 0x049e },
1843 { 0x06, 0x10e0 },
1844 { 0x06, 0x834e },
1845 { 0x06, 0x7803 },
1846 { 0x06, 0x9e0f },
1847 { 0x06, 0xe083 },
1848 { 0x06, 0x4e78 },
1849 { 0x06, 0x019e },
1850 { 0x06, 0x05ae },
1851 { 0x06, 0x0caf },
1852 { 0x06, 0x81f8 },
1853 { 0x06, 0xaf81 },
1854 { 0x06, 0xa3af },
1855 { 0x06, 0x81dc },
1856 { 0x06, 0xaf82 },
1857 { 0x06, 0x13ee },
1858 { 0x06, 0x8348 },
1859 { 0x06, 0x00ee },
1860 { 0x06, 0x8349 },
1861 { 0x06, 0x00e0 },
1862 { 0x06, 0x8351 },
1863 { 0x06, 0x10e4 },
1864 { 0x06, 0x8351 },
1865 { 0x06, 0x5801 },
1866 { 0x06, 0x9fea },
1867 { 0x06, 0xd000 },
1868 { 0x06, 0xd180 },
1869 { 0x06, 0x1f66 },
1870 { 0x06, 0xe2f8 },
1871 { 0x06, 0xeae3 },
1872 { 0x06, 0xf8eb },
1873 { 0x06, 0x5af8 },
1874 { 0x06, 0x1e20 },
1875 { 0x06, 0xe6f8 },
1876 { 0x06, 0xeae5 },
1877 { 0x06, 0xf8eb },
1878 { 0x06, 0xd302 },
1879 { 0x06, 0xb3fe },
1880 { 0x06, 0xe2f8 },
1881 { 0x06, 0x7cef },
1882 { 0x06, 0x325b },
1883 { 0x06, 0x80e3 },
1884 { 0x06, 0xf87d },
1885 { 0x06, 0x9e03 },
1886 { 0x06, 0x7dff },
1887 { 0x06, 0xff0d },
1888 { 0x06, 0x581c },
1889 { 0x06, 0x551a },
1890 { 0x06, 0x6511 },
1891 { 0x06, 0xa190 },
1892 { 0x06, 0xd3e2 },
1893 { 0x06, 0x8348 },
1894 { 0x06, 0xe383 },
1895 { 0x06, 0x491b },
1896 { 0x06, 0x56ab },
1897 { 0x06, 0x08ef },
1898 { 0x06, 0x56e6 },
1899 { 0x06, 0x8348 },
1900 { 0x06, 0xe783 },
1901 { 0x06, 0x4910 },
1902 { 0x06, 0xd180 },
1903 { 0x06, 0x1f66 },
1904 { 0x06, 0xa004 },
1905 { 0x06, 0xb9e2 },
1906 { 0x06, 0x8348 },
1907 { 0x06, 0xe383 },
1908 { 0x06, 0x49ef },
1909 { 0x06, 0x65e2 },
1910 { 0x06, 0x834a },
1911 { 0x06, 0xe383 },
1912 { 0x06, 0x4b1b },
1913 { 0x06, 0x56aa },
1914 { 0x06, 0x0eef },
1915 { 0x06, 0x56e6 },
1916 { 0x06, 0x834a },
1917 { 0x06, 0xe783 },
1918 { 0x06, 0x4be2 },
1919 { 0x06, 0x834d },
1920 { 0x06, 0xe683 },
1921 { 0x06, 0x4ce0 },
1922 { 0x06, 0x834d },
1923 { 0x06, 0xa000 },
1924 { 0x06, 0x0caf },
1925 { 0x06, 0x81dc },
1926 { 0x06, 0xe083 },
1927 { 0x06, 0x4d10 },
1928 { 0x06, 0xe483 },
1929 { 0x06, 0x4dae },
1930 { 0x06, 0x0480 },
1931 { 0x06, 0xe483 },
1932 { 0x06, 0x4de0 },
1933 { 0x06, 0x834e },
1934 { 0x06, 0x7803 },
1935 { 0x06, 0x9e0b },
1936 { 0x06, 0xe083 },
1937 { 0x06, 0x4e78 },
1938 { 0x06, 0x049e },
1939 { 0x06, 0x04ee },
1940 { 0x06, 0x834e },
1941 { 0x06, 0x02e0 },
1942 { 0x06, 0x8332 },
1943 { 0x06, 0xe183 },
1944 { 0x06, 0x3359 },
1945 { 0x06, 0x0fe2 },
1946 { 0x06, 0x834d },
1947 { 0x06, 0x0c24 },
1948 { 0x06, 0x5af0 },
1949 { 0x06, 0x1e12 },
1950 { 0x06, 0xe4f8 },
1951 { 0x06, 0x8ce5 },
1952 { 0x06, 0xf88d },
1953 { 0x06, 0xe083 },
1954 { 0x06, 0x30e1 },
1955 { 0x06, 0x8331 },
1956 { 0x06, 0x6801 },
1957 { 0x06, 0xe4f8 },
1958 { 0x06, 0x8ae5 },
1959 { 0x06, 0xf88b },
1960 { 0x06, 0xae37 },
1961 { 0x06, 0xee83 },
1962 { 0x06, 0x4e03 },
1963 { 0x06, 0xe083 },
1964 { 0x06, 0x4ce1 },
1965 { 0x06, 0x834d },
1966 { 0x06, 0x1b01 },
1967 { 0x06, 0x9e04 },
1968 { 0x06, 0xaaa1 },
1969 { 0x06, 0xaea8 },
1970 { 0x06, 0xee83 },
1971 { 0x06, 0x4e04 },
1972 { 0x06, 0xee83 },
1973 { 0x06, 0x4f00 },
1974 { 0x06, 0xaeab },
1975 { 0x06, 0xe083 },
1976 { 0x06, 0x4f78 },
1977 { 0x06, 0x039f },
1978 { 0x06, 0x14ee },
1979 { 0x06, 0x834e },
1980 { 0x06, 0x05d2 },
1981 { 0x06, 0x40d6 },
1982 { 0x06, 0x5554 },
1983 { 0x06, 0x0282 },
1984 { 0x06, 0x17d2 },
1985 { 0x06, 0xa0d6 },
1986 { 0x06, 0xba00 },
1987 { 0x06, 0x0282 },
1988 { 0x06, 0x17fe },
1989 { 0x06, 0xfdfc },
1990 { 0x06, 0x05f8 },
1991 { 0x06, 0xe0f8 },
1992 { 0x06, 0x60e1 },
1993 { 0x06, 0xf861 },
1994 { 0x06, 0x6802 },
1995 { 0x06, 0xe4f8 },
1996 { 0x06, 0x60e5 },
1997 { 0x06, 0xf861 },
1998 { 0x06, 0xe0f8 },
1999 { 0x06, 0x48e1 },
2000 { 0x06, 0xf849 },
2001 { 0x06, 0x580f },
2002 { 0x06, 0x1e02 },
2003 { 0x06, 0xe4f8 },
2004 { 0x06, 0x48e5 },
2005 { 0x06, 0xf849 },
2006 { 0x06, 0xd000 },
2007 { 0x06, 0x0282 },
2008 { 0x06, 0x5bbf },
2009 { 0x06, 0x8350 },
2010 { 0x06, 0xef46 },
2011 { 0x06, 0xdc19 },
2012 { 0x06, 0xddd0 },
2013 { 0x06, 0x0102 },
2014 { 0x06, 0x825b },
2015 { 0x06, 0x0282 },
2016 { 0x06, 0x77e0 },
2017 { 0x06, 0xf860 },
2018 { 0x06, 0xe1f8 },
2019 { 0x06, 0x6158 },
2020 { 0x06, 0xfde4 },
2021 { 0x06, 0xf860 },
2022 { 0x06, 0xe5f8 },
2023 { 0x06, 0x61fc },
2024 { 0x06, 0x04f9 },
2025 { 0x06, 0xfafb },
2026 { 0x06, 0xc6bf },
2027 { 0x06, 0xf840 },
2028 { 0x06, 0xbe83 },
2029 { 0x06, 0x50a0 },
2030 { 0x06, 0x0101 },
2031 { 0x06, 0x071b },
2032 { 0x06, 0x89cf },
2033 { 0x06, 0xd208 },
2034 { 0x06, 0xebdb },
2035 { 0x06, 0x19b2 },
2036 { 0x06, 0xfbff },
2037 { 0x06, 0xfefd },
2038 { 0x06, 0x04f8 },
2039 { 0x06, 0xe0f8 },
2040 { 0x06, 0x48e1 },
2041 { 0x06, 0xf849 },
2042 { 0x06, 0x6808 },
2043 { 0x06, 0xe4f8 },
2044 { 0x06, 0x48e5 },
2045 { 0x06, 0xf849 },
2046 { 0x06, 0x58f7 },
2047 { 0x06, 0xe4f8 },
2048 { 0x06, 0x48e5 },
2049 { 0x06, 0xf849 },
2050 { 0x06, 0xfc04 },
2051 { 0x06, 0x4d20 },
2052 { 0x06, 0x0002 },
2053 { 0x06, 0x4e22 },
2054 { 0x06, 0x0002 },
2055 { 0x06, 0x4ddf },
2056 { 0x06, 0xff01 },
2057 { 0x06, 0x4edd },
2058 { 0x06, 0xff01 },
2059 { 0x05, 0x83d4 },
2060 { 0x06, 0x8000 },
2061 { 0x05, 0x83d8 },
2062 { 0x06, 0x8051 },
2063 { 0x02, 0x6010 },
2064 { 0x03, 0xdc00 },
2065 { 0x05, 0xfff6 },
2066 { 0x06, 0x00fc },
5b538df9 2067 { 0x1f, 0x0000 },
daf9df6d 2068
5b538df9 2069 { 0x1f, 0x0000 },
daf9df6d 2070 { 0x0d, 0xf880 },
2071 { 0x1f, 0x0000 }
2072 };
2073
2074 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2075
2076 mdio_write(ioaddr, 0x1f, 0x0002);
2077 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2078 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2079
2080 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2081
2082 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2083 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2084 { 0x1f, 0x0002 },
2085 { 0x05, 0x669a },
2086 { 0x1f, 0x0005 },
2087 { 0x05, 0x8330 },
2088 { 0x06, 0x669a },
2089 { 0x1f, 0x0002 }
2090 };
2091 int val;
2092
2093 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2094
2095 val = mdio_read(ioaddr, 0x0d);
2096
2097 if ((val & 0x00ff) != 0x006c) {
350f7596 2098 static const u32 set[] = {
daf9df6d 2099 0x0065, 0x0066, 0x0067, 0x0068,
2100 0x0069, 0x006a, 0x006b, 0x006c
2101 };
2102 int i;
2103
2104 mdio_write(ioaddr, 0x1f, 0x0002);
2105
2106 val &= 0xff00;
2107 for (i = 0; i < ARRAY_SIZE(set); i++)
2108 mdio_write(ioaddr, 0x0d, val | set[i]);
2109 }
2110 } else {
350f7596 2111 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2112 { 0x1f, 0x0002 },
2113 { 0x05, 0x6662 },
2114 { 0x1f, 0x0005 },
2115 { 0x05, 0x8330 },
2116 { 0x06, 0x6662 }
2117 };
2118
2119 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2120 }
2121
2122 mdio_write(ioaddr, 0x1f, 0x0002);
2123 mdio_patch(ioaddr, 0x0d, 0x0300);
2124 mdio_patch(ioaddr, 0x0f, 0x0010);
2125
2126 mdio_write(ioaddr, 0x1f, 0x0002);
2127 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2128 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2129
2130 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2131}
2132
2133static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2134{
350f7596 2135 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2136 { 0x1f, 0x0001 },
2137 { 0x06, 0x4064 },
2138 { 0x07, 0x2863 },
2139 { 0x08, 0x059c },
2140 { 0x09, 0x26b4 },
2141 { 0x0a, 0x6a19 },
2142 { 0x0b, 0xdcc8 },
2143 { 0x10, 0xf06d },
2144 { 0x14, 0x7f68 },
2145 { 0x18, 0x7fd9 },
2146 { 0x1c, 0xf0ff },
2147 { 0x1d, 0x3d9c },
2148 { 0x1f, 0x0003 },
2149 { 0x12, 0xf49f },
2150 { 0x13, 0x070b },
2151 { 0x1a, 0x05ad },
2152 { 0x14, 0x94c0 },
2153
2154 { 0x1f, 0x0002 },
2155 { 0x06, 0x5561 },
2156 { 0x1f, 0x0005 },
2157 { 0x05, 0x8332 },
2158 { 0x06, 0x5561 }
2159 };
350f7596 2160 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2161 { 0x1f, 0x0005 },
2162 { 0x05, 0xffc2 },
5b538df9 2163 { 0x1f, 0x0005 },
daf9df6d 2164 { 0x05, 0x8000 },
2165 { 0x06, 0xf8f9 },
2166 { 0x06, 0xfaee },
2167 { 0x06, 0xf8ea },
2168 { 0x06, 0x00ee },
2169 { 0x06, 0xf8eb },
2170 { 0x06, 0x00e2 },
2171 { 0x06, 0xf87c },
2172 { 0x06, 0xe3f8 },
2173 { 0x06, 0x7da5 },
2174 { 0x06, 0x1111 },
2175 { 0x06, 0x12d2 },
2176 { 0x06, 0x40d6 },
2177 { 0x06, 0x4444 },
2178 { 0x06, 0x0281 },
2179 { 0x06, 0xc6d2 },
2180 { 0x06, 0xa0d6 },
2181 { 0x06, 0xaaaa },
2182 { 0x06, 0x0281 },
2183 { 0x06, 0xc6ae },
2184 { 0x06, 0x0fa5 },
2185 { 0x06, 0x4444 },
2186 { 0x06, 0x02ae },
2187 { 0x06, 0x4da5 },
2188 { 0x06, 0xaaaa },
2189 { 0x06, 0x02ae },
2190 { 0x06, 0x47af },
2191 { 0x06, 0x81c2 },
2192 { 0x06, 0xee83 },
2193 { 0x06, 0x4e00 },
2194 { 0x06, 0xee83 },
2195 { 0x06, 0x4d0f },
2196 { 0x06, 0xee83 },
2197 { 0x06, 0x4c0f },
2198 { 0x06, 0xee83 },
2199 { 0x06, 0x4f00 },
2200 { 0x06, 0xee83 },
2201 { 0x06, 0x5100 },
2202 { 0x06, 0xee83 },
2203 { 0x06, 0x4aff },
2204 { 0x06, 0xee83 },
2205 { 0x06, 0x4bff },
2206 { 0x06, 0xe083 },
2207 { 0x06, 0x30e1 },
2208 { 0x06, 0x8331 },
2209 { 0x06, 0x58fe },
2210 { 0x06, 0xe4f8 },
2211 { 0x06, 0x8ae5 },
2212 { 0x06, 0xf88b },
2213 { 0x06, 0xe083 },
2214 { 0x06, 0x32e1 },
2215 { 0x06, 0x8333 },
2216 { 0x06, 0x590f },
2217 { 0x06, 0xe283 },
2218 { 0x06, 0x4d0c },
2219 { 0x06, 0x245a },
2220 { 0x06, 0xf01e },
2221 { 0x06, 0x12e4 },
2222 { 0x06, 0xf88c },
2223 { 0x06, 0xe5f8 },
2224 { 0x06, 0x8daf },
2225 { 0x06, 0x81c2 },
2226 { 0x06, 0xe083 },
2227 { 0x06, 0x4f10 },
2228 { 0x06, 0xe483 },
2229 { 0x06, 0x4fe0 },
2230 { 0x06, 0x834e },
2231 { 0x06, 0x7800 },
2232 { 0x06, 0x9f0a },
2233 { 0x06, 0xe083 },
2234 { 0x06, 0x4fa0 },
2235 { 0x06, 0x10a5 },
2236 { 0x06, 0xee83 },
2237 { 0x06, 0x4e01 },
2238 { 0x06, 0xe083 },
2239 { 0x06, 0x4e78 },
2240 { 0x06, 0x059e },
2241 { 0x06, 0x9ae0 },
2242 { 0x06, 0x834e },
2243 { 0x06, 0x7804 },
2244 { 0x06, 0x9e10 },
2245 { 0x06, 0xe083 },
2246 { 0x06, 0x4e78 },
2247 { 0x06, 0x039e },
2248 { 0x06, 0x0fe0 },
2249 { 0x06, 0x834e },
2250 { 0x06, 0x7801 },
2251 { 0x06, 0x9e05 },
2252 { 0x06, 0xae0c },
2253 { 0x06, 0xaf81 },
2254 { 0x06, 0xa7af },
2255 { 0x06, 0x8152 },
2256 { 0x06, 0xaf81 },
2257 { 0x06, 0x8baf },
2258 { 0x06, 0x81c2 },
2259 { 0x06, 0xee83 },
2260 { 0x06, 0x4800 },
2261 { 0x06, 0xee83 },
2262 { 0x06, 0x4900 },
2263 { 0x06, 0xe083 },
2264 { 0x06, 0x5110 },
2265 { 0x06, 0xe483 },
2266 { 0x06, 0x5158 },
2267 { 0x06, 0x019f },
2268 { 0x06, 0xead0 },
2269 { 0x06, 0x00d1 },
2270 { 0x06, 0x801f },
2271 { 0x06, 0x66e2 },
2272 { 0x06, 0xf8ea },
2273 { 0x06, 0xe3f8 },
2274 { 0x06, 0xeb5a },
2275 { 0x06, 0xf81e },
2276 { 0x06, 0x20e6 },
2277 { 0x06, 0xf8ea },
2278 { 0x06, 0xe5f8 },
2279 { 0x06, 0xebd3 },
2280 { 0x06, 0x02b3 },
2281 { 0x06, 0xfee2 },
2282 { 0x06, 0xf87c },
2283 { 0x06, 0xef32 },
2284 { 0x06, 0x5b80 },
2285 { 0x06, 0xe3f8 },
2286 { 0x06, 0x7d9e },
2287 { 0x06, 0x037d },
2288 { 0x06, 0xffff },
2289 { 0x06, 0x0d58 },
2290 { 0x06, 0x1c55 },
2291 { 0x06, 0x1a65 },
2292 { 0x06, 0x11a1 },
2293 { 0x06, 0x90d3 },
2294 { 0x06, 0xe283 },
2295 { 0x06, 0x48e3 },
2296 { 0x06, 0x8349 },
2297 { 0x06, 0x1b56 },
2298 { 0x06, 0xab08 },
2299 { 0x06, 0xef56 },
2300 { 0x06, 0xe683 },
2301 { 0x06, 0x48e7 },
2302 { 0x06, 0x8349 },
2303 { 0x06, 0x10d1 },
2304 { 0x06, 0x801f },
2305 { 0x06, 0x66a0 },
2306 { 0x06, 0x04b9 },
2307 { 0x06, 0xe283 },
2308 { 0x06, 0x48e3 },
2309 { 0x06, 0x8349 },
2310 { 0x06, 0xef65 },
2311 { 0x06, 0xe283 },
2312 { 0x06, 0x4ae3 },
2313 { 0x06, 0x834b },
2314 { 0x06, 0x1b56 },
2315 { 0x06, 0xaa0e },
2316 { 0x06, 0xef56 },
2317 { 0x06, 0xe683 },
2318 { 0x06, 0x4ae7 },
2319 { 0x06, 0x834b },
2320 { 0x06, 0xe283 },
2321 { 0x06, 0x4de6 },
2322 { 0x06, 0x834c },
2323 { 0x06, 0xe083 },
2324 { 0x06, 0x4da0 },
2325 { 0x06, 0x000c },
2326 { 0x06, 0xaf81 },
2327 { 0x06, 0x8be0 },
2328 { 0x06, 0x834d },
2329 { 0x06, 0x10e4 },
2330 { 0x06, 0x834d },
2331 { 0x06, 0xae04 },
2332 { 0x06, 0x80e4 },
2333 { 0x06, 0x834d },
2334 { 0x06, 0xe083 },
2335 { 0x06, 0x4e78 },
2336 { 0x06, 0x039e },
2337 { 0x06, 0x0be0 },
2338 { 0x06, 0x834e },
2339 { 0x06, 0x7804 },
2340 { 0x06, 0x9e04 },
2341 { 0x06, 0xee83 },
2342 { 0x06, 0x4e02 },
2343 { 0x06, 0xe083 },
2344 { 0x06, 0x32e1 },
2345 { 0x06, 0x8333 },
2346 { 0x06, 0x590f },
2347 { 0x06, 0xe283 },
2348 { 0x06, 0x4d0c },
2349 { 0x06, 0x245a },
2350 { 0x06, 0xf01e },
2351 { 0x06, 0x12e4 },
2352 { 0x06, 0xf88c },
2353 { 0x06, 0xe5f8 },
2354 { 0x06, 0x8de0 },
2355 { 0x06, 0x8330 },
2356 { 0x06, 0xe183 },
2357 { 0x06, 0x3168 },
2358 { 0x06, 0x01e4 },
2359 { 0x06, 0xf88a },
2360 { 0x06, 0xe5f8 },
2361 { 0x06, 0x8bae },
2362 { 0x06, 0x37ee },
2363 { 0x06, 0x834e },
2364 { 0x06, 0x03e0 },
2365 { 0x06, 0x834c },
2366 { 0x06, 0xe183 },
2367 { 0x06, 0x4d1b },
2368 { 0x06, 0x019e },
2369 { 0x06, 0x04aa },
2370 { 0x06, 0xa1ae },
2371 { 0x06, 0xa8ee },
2372 { 0x06, 0x834e },
2373 { 0x06, 0x04ee },
2374 { 0x06, 0x834f },
2375 { 0x06, 0x00ae },
2376 { 0x06, 0xabe0 },
2377 { 0x06, 0x834f },
2378 { 0x06, 0x7803 },
2379 { 0x06, 0x9f14 },
2380 { 0x06, 0xee83 },
2381 { 0x06, 0x4e05 },
2382 { 0x06, 0xd240 },
2383 { 0x06, 0xd655 },
2384 { 0x06, 0x5402 },
2385 { 0x06, 0x81c6 },
2386 { 0x06, 0xd2a0 },
2387 { 0x06, 0xd6ba },
2388 { 0x06, 0x0002 },
2389 { 0x06, 0x81c6 },
2390 { 0x06, 0xfefd },
2391 { 0x06, 0xfc05 },
2392 { 0x06, 0xf8e0 },
2393 { 0x06, 0xf860 },
2394 { 0x06, 0xe1f8 },
2395 { 0x06, 0x6168 },
2396 { 0x06, 0x02e4 },
2397 { 0x06, 0xf860 },
2398 { 0x06, 0xe5f8 },
2399 { 0x06, 0x61e0 },
2400 { 0x06, 0xf848 },
2401 { 0x06, 0xe1f8 },
2402 { 0x06, 0x4958 },
2403 { 0x06, 0x0f1e },
2404 { 0x06, 0x02e4 },
2405 { 0x06, 0xf848 },
2406 { 0x06, 0xe5f8 },
2407 { 0x06, 0x49d0 },
2408 { 0x06, 0x0002 },
2409 { 0x06, 0x820a },
2410 { 0x06, 0xbf83 },
2411 { 0x06, 0x50ef },
2412 { 0x06, 0x46dc },
2413 { 0x06, 0x19dd },
2414 { 0x06, 0xd001 },
2415 { 0x06, 0x0282 },
2416 { 0x06, 0x0a02 },
2417 { 0x06, 0x8226 },
2418 { 0x06, 0xe0f8 },
2419 { 0x06, 0x60e1 },
2420 { 0x06, 0xf861 },
2421 { 0x06, 0x58fd },
2422 { 0x06, 0xe4f8 },
2423 { 0x06, 0x60e5 },
2424 { 0x06, 0xf861 },
2425 { 0x06, 0xfc04 },
2426 { 0x06, 0xf9fa },
2427 { 0x06, 0xfbc6 },
2428 { 0x06, 0xbff8 },
2429 { 0x06, 0x40be },
2430 { 0x06, 0x8350 },
2431 { 0x06, 0xa001 },
2432 { 0x06, 0x0107 },
2433 { 0x06, 0x1b89 },
2434 { 0x06, 0xcfd2 },
2435 { 0x06, 0x08eb },
2436 { 0x06, 0xdb19 },
2437 { 0x06, 0xb2fb },
2438 { 0x06, 0xfffe },
2439 { 0x06, 0xfd04 },
2440 { 0x06, 0xf8e0 },
2441 { 0x06, 0xf848 },
2442 { 0x06, 0xe1f8 },
2443 { 0x06, 0x4968 },
2444 { 0x06, 0x08e4 },
2445 { 0x06, 0xf848 },
2446 { 0x06, 0xe5f8 },
2447 { 0x06, 0x4958 },
2448 { 0x06, 0xf7e4 },
2449 { 0x06, 0xf848 },
2450 { 0x06, 0xe5f8 },
2451 { 0x06, 0x49fc },
2452 { 0x06, 0x044d },
2453 { 0x06, 0x2000 },
2454 { 0x06, 0x024e },
2455 { 0x06, 0x2200 },
2456 { 0x06, 0x024d },
2457 { 0x06, 0xdfff },
2458 { 0x06, 0x014e },
2459 { 0x06, 0xddff },
2460 { 0x06, 0x0100 },
2461 { 0x05, 0x83d8 },
2462 { 0x06, 0x8000 },
2463 { 0x03, 0xdc00 },
2464 { 0x05, 0xfff6 },
2465 { 0x06, 0x00fc },
2466 { 0x1f, 0x0000 },
2467
2468 { 0x1f, 0x0000 },
2469 { 0x0d, 0xf880 },
2470 { 0x1f, 0x0000 }
5b538df9
FR		 2471 };
2472
2473 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2474
daf9df6d 2475 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2476 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2477 { 0x1f, 0x0002 },
2478 { 0x05, 0x669a },
5b538df9 2479 { 0x1f, 0x0005 },
daf9df6d 2480 { 0x05, 0x8330 },
2481 { 0x06, 0x669a },
2482
2483 { 0x1f, 0x0002 }
2484 };
2485 int val;
2486
2487 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2488
2489 val = mdio_read(ioaddr, 0x0d);
2490 if ((val & 0x00ff) != 0x006c) {
2491 u32 set[] = {
2492 0x0065, 0x0066, 0x0067, 0x0068,
2493 0x0069, 0x006a, 0x006b, 0x006c
2494 };
2495 int i;
2496
2497 mdio_write(ioaddr, 0x1f, 0x0002);
2498
2499 val &= 0xff00;
2500 for (i = 0; i < ARRAY_SIZE(set); i++)
2501 mdio_write(ioaddr, 0x0d, val | set[i]);
2502 }
2503 } else {
350f7596 2504 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2505 { 0x1f, 0x0002 },
2506 { 0x05, 0x2642 },
5b538df9 2507 { 0x1f, 0x0005 },
daf9df6d 2508 { 0x05, 0x8330 },
2509 { 0x06, 0x2642 }
5b538df9
FR		 2510 };
2511
daf9df6d 2512 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2513 }
2514
daf9df6d 2515 mdio_write(ioaddr, 0x1f, 0x0002);
2516 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2517 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2518
2519 mdio_write(ioaddr, 0x1f, 0x0001);
2520 mdio_write(ioaddr, 0x17, 0x0cc0);
2521
2522 mdio_write(ioaddr, 0x1f, 0x0002);
2523 mdio_patch(ioaddr, 0x0f, 0x0017);
2524
2525 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2526}
2527
2528static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2529{
350f7596 2530 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2531 { 0x1f, 0x0002 },
2532 { 0x10, 0x0008 },
2533 { 0x0d, 0x006c },
2534
2535 { 0x1f, 0x0000 },
2536 { 0x0d, 0xf880 },
2537
2538 { 0x1f, 0x0001 },
2539 { 0x17, 0x0cc0 },
2540
2541 { 0x1f, 0x0001 },
2542 { 0x0b, 0xa4d8 },
2543 { 0x09, 0x281c },
2544 { 0x07, 0x2883 },
2545 { 0x0a, 0x6b35 },
2546 { 0x1d, 0x3da4 },
2547 { 0x1c, 0xeffd },
2548 { 0x14, 0x7f52 },
2549 { 0x18, 0x7fc6 },
2550 { 0x08, 0x0601 },
2551 { 0x06, 0x4063 },
2552 { 0x10, 0xf074 },
2553 { 0x1f, 0x0003 },
2554 { 0x13, 0x0789 },
2555 { 0x12, 0xf4bd },
2556 { 0x1a, 0x04fd },
2557 { 0x14, 0x84b0 },
2558 { 0x1f, 0x0000 },
2559 { 0x00, 0x9200 },
2560
2561 { 0x1f, 0x0005 },
2562 { 0x01, 0x0340 },
2563 { 0x1f, 0x0001 },
2564 { 0x04, 0x4000 },
2565 { 0x03, 0x1d21 },
2566 { 0x02, 0x0c32 },
2567 { 0x01, 0x0200 },
2568 { 0x00, 0x5554 },
2569 { 0x04, 0x4800 },
2570 { 0x04, 0x4000 },
2571 { 0x04, 0xf000 },
2572 { 0x03, 0xdf01 },
2573 { 0x02, 0xdf20 },
2574 { 0x01, 0x101a },
2575 { 0x00, 0xa0ff },
2576 { 0x04, 0xf800 },
2577 { 0x04, 0xf000 },
2578 { 0x1f, 0x0000 },
2579
2580 { 0x1f, 0x0007 },
2581 { 0x1e, 0x0023 },
2582 { 0x16, 0x0000 },
2583 { 0x1f, 0x0000 }
2584 };
2585
2586 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2587}
2588
2857ffb7
FR		 2589static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2590{
350f7596 2591 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2592 { 0x1f, 0x0003 },
2593 { 0x08, 0x441d },
2594 { 0x01, 0x9100 },
2595 { 0x1f, 0x0000 }
2596 };
2597
2598 mdio_write(ioaddr, 0x1f, 0x0000);
2599 mdio_patch(ioaddr, 0x11, 1 << 12);
2600 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2601 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2602
2603 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2604}
2605
5615d9f1
FR		 2606static void rtl_hw_phy_config(struct net_device *dev)
2607{
2608 struct rtl8169_private *tp = netdev_priv(dev);
2609 void __iomem *ioaddr = tp->mmio_addr;
2610
2611 rtl8169_print_mac_version(tp);
2612
2613 switch (tp->mac_version) {
2614 case RTL_GIGA_MAC_VER_01:
2615 break;
2616 case RTL_GIGA_MAC_VER_02:
2617 case RTL_GIGA_MAC_VER_03:
2618 rtl8169s_hw_phy_config(ioaddr);
2619 break;
2620 case RTL_GIGA_MAC_VER_04:
2621 rtl8169sb_hw_phy_config(ioaddr);
2622 break;
2e955856 2623 case RTL_GIGA_MAC_VER_05:
2624 rtl8169scd_hw_phy_config(tp, ioaddr);
2625 break;
8c7006aa 2626 case RTL_GIGA_MAC_VER_06:
2627 rtl8169sce_hw_phy_config(ioaddr);
2628 break;
2857ffb7
FR		 2629 case RTL_GIGA_MAC_VER_07:
2630 case RTL_GIGA_MAC_VER_08:
2631 case RTL_GIGA_MAC_VER_09:
2632 rtl8102e_hw_phy_config(ioaddr);
2633 break;
236b8082
FR		 2634 case RTL_GIGA_MAC_VER_11:
2635 rtl8168bb_hw_phy_config(ioaddr);
2636 break;
2637 case RTL_GIGA_MAC_VER_12:
2638 rtl8168bef_hw_phy_config(ioaddr);
2639 break;
2640 case RTL_GIGA_MAC_VER_17:
2641 rtl8168bef_hw_phy_config(ioaddr);
2642 break;
867763c1 2643 case RTL_GIGA_MAC_VER_18:
ef3386f0 2644 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2645 break;
2646 case RTL_GIGA_MAC_VER_19:
219a1e9d 2647 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2648 break;
7da97ec9 2649 case RTL_GIGA_MAC_VER_20:
219a1e9d 2650 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2651 break;
197ff761
FR		 2652 case RTL_GIGA_MAC_VER_21:
2653 rtl8168c_3_hw_phy_config(ioaddr);
2654 break;
6fb07058
FR		 2655 case RTL_GIGA_MAC_VER_22:
2656 rtl8168c_4_hw_phy_config(ioaddr);
2657 break;
ef3386f0 2658 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2659 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2660 rtl8168cp_2_hw_phy_config(ioaddr);
2661 break;
5b538df9 2662 case RTL_GIGA_MAC_VER_25:
daf9df6d 2663 rtl8168d_1_hw_phy_config(ioaddr);
2664 break;
2665 case RTL_GIGA_MAC_VER_26:
2666 rtl8168d_2_hw_phy_config(ioaddr);
2667 break;
2668 case RTL_GIGA_MAC_VER_27:
2669 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2670 break;
ef3386f0 2671
5615d9f1
FR		 2672 default:
2673 break;
2674 }
2675}
2676
1da177e4
LT		 2677static void rtl8169_phy_timer(unsigned long __opaque)
2678{
2679 struct net_device *dev = (struct net_device *)__opaque;
2680 struct rtl8169_private *tp = netdev_priv(dev);
2681 struct timer_list *timer = &tp->timer;
2682 void __iomem *ioaddr = tp->mmio_addr;
2683 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2684
bcf0bf90 2685 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2686
64e4bfb4 2687 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2688 return;
2689
2690 spin_lock_irq(&tp->lock);
2691
2692 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2693 /*
1da177e4
LT		 2694 * A busy loop could burn quite a few cycles on nowadays CPU.
2695 * Let's delay the execution of the timer for a few ticks.
2696 */
2697 timeout = HZ/10;
2698 goto out_mod_timer;
2699 }
2700
2701 if (tp->link_ok(ioaddr))
2702 goto out_unlock;
2703
bf82c189 2704 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2705
2706 tp->phy_reset_enable(ioaddr);
2707
2708out_mod_timer:
2709 mod_timer(timer, jiffies + timeout);
2710out_unlock:
2711 spin_unlock_irq(&tp->lock);
2712}
2713
2714static inline void rtl8169_delete_timer(struct net_device *dev)
2715{
2716 struct rtl8169_private *tp = netdev_priv(dev);
2717 struct timer_list *timer = &tp->timer;
2718
e179bb7b 2719 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2720 return;
2721
2722 del_timer_sync(timer);
2723}
2724
2725static inline void rtl8169_request_timer(struct net_device *dev)
2726{
2727 struct rtl8169_private *tp = netdev_priv(dev);
2728 struct timer_list *timer = &tp->timer;
2729
e179bb7b 2730 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2731 return;
2732
2efa53f3 2733 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2734}
2735
2736#ifdef CONFIG_NET_POLL_CONTROLLER
2737/*
2738 * Polling 'interrupt' - used by things like netconsole to send skbs
2739 * without having to re-enable interrupts. It's not called while
2740 * the interrupt routine is executing.
2741 */
2742static void rtl8169_netpoll(struct net_device *dev)
2743{
2744 struct rtl8169_private *tp = netdev_priv(dev);
2745 struct pci_dev *pdev = tp->pci_dev;
2746
2747 disable_irq(pdev->irq);
7d12e780 2748 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2749 enable_irq(pdev->irq);
2750}
2751#endif
2752
2753static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2754 void __iomem *ioaddr)
2755{
2756 iounmap(ioaddr);
2757 pci_release_regions(pdev);
2758 pci_disable_device(pdev);
2759 free_netdev(dev);
2760}
2761
bf793295
FR		 2762static void rtl8169_phy_reset(struct net_device *dev,
2763 struct rtl8169_private *tp)
2764{
2765 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2766 unsigned int i;
bf793295
FR		 2767
2768 tp->phy_reset_enable(ioaddr);
2769 for (i = 0; i < 100; i++) {
2770 if (!tp->phy_reset_pending(ioaddr))
2771 return;
2772 msleep(1);
2773 }
bf82c189 2774 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2775}
2776
4ff96fa6
FR		 2777static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2778{
2779 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2780
5615d9f1 2781 rtl_hw_phy_config(dev);
4ff96fa6 2782
77332894
MS		 2783 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2784 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2785 RTL_W8(0x82, 0x01);
2786 }
4ff96fa6 2787
6dccd16b
FR		 2788 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2789
2790 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2791 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2792
bcf0bf90 2793 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2794 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2795 RTL_W8(0x82, 0x01);
2796 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2797 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2798 }
2799
bf793295
FR		 2800 rtl8169_phy_reset(dev, tp);
2801
901dda2b
FR		 2802 /*
2803 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2804 * only 8101. Don't panic.
2805 */
2806 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2807
bf82c189
JP		 2808 if (RTL_R8(PHYstatus) & TBI_Enable)
2809 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2810}
2811
773d2021
FR		 2812static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2813{
2814 void __iomem *ioaddr = tp->mmio_addr;
2815 u32 high;
2816 u32 low;
2817
2818 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2819 high = addr[4] | (addr[5] << 8);
2820
2821 spin_lock_irq(&tp->lock);
2822
2823 RTL_W8(Cfg9346, Cfg9346_Unlock);
2824 RTL_W32(MAC0, low);
2825 RTL_W32(MAC4, high);
2826 RTL_W8(Cfg9346, Cfg9346_Lock);
2827
2828 spin_unlock_irq(&tp->lock);
2829}
2830
2831static int rtl_set_mac_address(struct net_device *dev, void *p)
2832{
2833 struct rtl8169_private *tp = netdev_priv(dev);
2834 struct sockaddr *addr = p;
2835
2836 if (!is_valid_ether_addr(addr->sa_data))
2837 return -EADDRNOTAVAIL;
2838
2839 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2840
2841 rtl_rar_set(tp, dev->dev_addr);
2842
2843 return 0;
2844}
2845
5f787a1a
FR		 2846static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2847{
2848 struct rtl8169_private *tp = netdev_priv(dev);
2849 struct mii_ioctl_data *data = if_mii(ifr);
2850
8b4ab28d
FR		 2851 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2852}
5f787a1a 2853
8b4ab28d
FR		 2854static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2855{
5f787a1a
FR		 2856 switch (cmd) {
2857 case SIOCGMIIPHY:
2858 data->phy_id = 32; /* Internal PHY */
2859 return 0;
2860
2861 case SIOCGMIIREG:
2862 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2863 return 0;
2864
2865 case SIOCSMIIREG:
5f787a1a
FR		 2866 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2867 return 0;
2868 }
2869 return -EOPNOTSUPP;
2870}
2871
8b4ab28d
FR		 2872static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2873{
2874 return -EOPNOTSUPP;
2875}
2876
0e485150
FR		 2877static const struct rtl_cfg_info {
2878 void (*hw_start)(struct net_device *);
2879 unsigned int region;
2880 unsigned int align;
2881 u16 intr_event;
2882 u16 napi_event;
ccdffb9a 2883 unsigned features;
f21b75e9 2884 u8 default_ver;
0e485150
FR		 2885} rtl_cfg_infos [] = {
2886 [RTL_CFG_0] = {
2887 .hw_start = rtl_hw_start_8169,
2888 .region = 1,
e9f63f30 2889 .align = 0,
0e485150
FR		 2890 .intr_event = SYSErr | LinkChg | RxOverflow |
2891 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2892 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2893 .features = RTL_FEATURE_GMII,
2894 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2895 },
2896 [RTL_CFG_1] = {
2897 .hw_start = rtl_hw_start_8168,
2898 .region = 2,
2899 .align = 8,
2900 .intr_event = SYSErr | LinkChg | RxOverflow |
2901 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2902 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2903 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2904 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2905 },
2906 [RTL_CFG_2] = {
2907 .hw_start = rtl_hw_start_8101,
2908 .region = 2,
2909 .align = 8,
2910 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2911 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2912 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2913 .features = RTL_FEATURE_MSI,
2914 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2915 }
2916};
2917
fbac58fc
FR		 2918/* Cfg9346_Unlock assumed. */
2919static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2920 const struct rtl_cfg_info *cfg)
2921{
2922 unsigned msi = 0;
2923 u8 cfg2;
2924
2925 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2926 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2927 if (pci_enable_msi(pdev)) {
2928 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2929 } else {
2930 cfg2 |= MSIEnable;
2931 msi = RTL_FEATURE_MSI;
2932 }
2933 }
2934 RTL_W8(Config2, cfg2);
2935 return msi;
2936}
2937
2938static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2939{
2940 if (tp->features & RTL_FEATURE_MSI) {
2941 pci_disable_msi(pdev);
2942 tp->features &= ~RTL_FEATURE_MSI;
2943 }
2944}
2945
8b4ab28d
FR		 2946static const struct net_device_ops rtl8169_netdev_ops = {
2947 .ndo_open = rtl8169_open,
2948 .ndo_stop = rtl8169_close,
2949 .ndo_get_stats = rtl8169_get_stats,
00829823 2950 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2951 .ndo_tx_timeout = rtl8169_tx_timeout,
2952 .ndo_validate_addr = eth_validate_addr,
2953 .ndo_change_mtu = rtl8169_change_mtu,
2954 .ndo_set_mac_address = rtl_set_mac_address,
2955 .ndo_do_ioctl = rtl8169_ioctl,
2956 .ndo_set_multicast_list = rtl_set_rx_mode,
2957#ifdef CONFIG_R8169_VLAN
2958 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2959#endif
2960#ifdef CONFIG_NET_POLL_CONTROLLER
2961 .ndo_poll_controller = rtl8169_netpoll,
2962#endif
2963
2964};
2965
1da177e4 2966static int __devinit
4ff96fa6 2967rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2968{
0e485150
FR		 2969 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2970 const unsigned int region = cfg->region;
1da177e4 2971 struct rtl8169_private *tp;
ccdffb9a 2972 struct mii_if_info *mii;
4ff96fa6
FR		 2973 struct net_device *dev;
2974 void __iomem *ioaddr;
07d3f51f
FR		 2975 unsigned int i;
2976 int rc;
35317688 2977 int this_use_dac = use_dac;
1da177e4 2978
4ff96fa6
FR		 2979 if (netif_msg_drv(&debug)) {
2980 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2981 MODULENAME, RTL8169_VERSION);
2982 }
1da177e4 2983
1da177e4 2984 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2985 if (!dev) {
b57b7e5a 2986 if (netif_msg_drv(&debug))
9b91cf9d 2987 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2988 rc = -ENOMEM;
2989 goto out;
1da177e4
LT		 2990 }
2991
1da177e4 2992 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2993 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2994 tp = netdev_priv(dev);
c4028958 2995 tp->dev = dev;
21e197f2 2996 tp->pci_dev = pdev;
b57b7e5a 2997 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2998
ccdffb9a
FR		 2999 mii = &tp->mii;
3000 mii->dev = dev;
3001 mii->mdio_read = rtl_mdio_read;
3002 mii->mdio_write = rtl_mdio_write;
3003 mii->phy_id_mask = 0x1f;
3004 mii->reg_num_mask = 0x1f;
3005 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3006
1da177e4
LT		 3007 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3008 rc = pci_enable_device(pdev);
b57b7e5a 3009 if (rc < 0) {
bf82c189 3010 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3011 goto err_out_free_dev_1;
1da177e4
LT		 3012 }
3013
3014 rc = pci_set_mwi(pdev);
3015 if (rc < 0)
4ff96fa6 3016 goto err_out_disable_2;
1da177e4 3017
1da177e4 3018 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3019 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3020 netif_err(tp, probe, dev,
3021 "region #%d not an MMIO resource, aborting\n",
3022 region);
1da177e4 3023 rc = -ENODEV;
4ff96fa6 3024 goto err_out_mwi_3;
1da177e4 3025 }
4ff96fa6 3026
1da177e4 3027 /* check for weird/broken PCI region reporting */
bcf0bf90 3028 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3029 netif_err(tp, probe, dev,
3030 "Invalid PCI region size(s), aborting\n");
1da177e4 3031 rc = -ENODEV;
4ff96fa6 3032 goto err_out_mwi_3;
1da177e4
LT		 3033 }
3034
3035 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3036 if (rc < 0) {
bf82c189 3037 netif_err(tp, probe, dev, "could not request regions\n");
4ff96fa6 3038 goto err_out_mwi_3;
1da177e4
LT		 3039 }
3040
3041 tp->cp_cmd = PCIMulRW | RxChkSum;
3042
35317688
RH		 3043 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3044 if (!tp->pcie_cap)
3045 netif_info(tp, probe, dev, "no PCI Express capability\n");
3046
3047 if (this_use_dac < 0)
3048 this_use_dac = tp->pcie_cap != 0;
3049
1da177e4 3050 if ((sizeof(dma_addr_t) > 4) &&
35317688
RH		 3051 this_use_dac &&
3052 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3053 netif_info(tp, probe, dev, "using 64-bit DMA\n");
1da177e4
LT		 3054 tp->cp_cmd |= PCIDAC;
3055 dev->features |= NETIF_F_HIGHDMA;
3056 } else {
284901a9 3057 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3058 if (rc < 0) {
bf82c189 3059 netif_err(tp, probe, dev, "DMA configuration failed\n");
4ff96fa6 3060 goto err_out_free_res_4;
1da177e4
LT		 3061 }
3062 }
3063
1da177e4 3064 /* ioremap MMIO region */
bcf0bf90 3065 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3066 if (!ioaddr) {
bf82c189 3067 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3068 rc = -EIO;
4ff96fa6 3069 goto err_out_free_res_4;
1da177e4
LT		 3070 }
3071
d78ad8cb 3072 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3073
3074 /* Soft reset the chip. */
3075 RTL_W8(ChipCmd, CmdReset);
3076
3077 /* Check that the chip has finished the reset. */
07d3f51f 3078 for (i = 0; i < 100; i++) {
1da177e4
LT		 3079 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3080 break;
b518fa8e 3081 msleep_interruptible(1);
1da177e4
LT		 3082 }
3083
d78ad8cb
KW		 3084 RTL_W16(IntrStatus, 0xffff);
3085
ca52efd5 3086 pci_set_master(pdev);
3087
1da177e4
LT		 3088 /* Identify chip attached to board */
3089 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3090
f21b75e9
JD		 3091 /* Use appropriate default if unknown */
3092 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3093 netif_notice(tp, probe, dev,
3094 "unknown MAC, using family default\n");
f21b75e9
JD		 3095 tp->mac_version = cfg->default_ver;
3096 }
3097
1da177e4 3098 rtl8169_print_mac_version(tp);
1da177e4 3099
cee60c37 3100 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3101 if (tp->mac_version == rtl_chip_info[i].mac_version)
3102 break;
3103 }
cee60c37 3104 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3105 dev_err(&pdev->dev,
3106 "driver bug, MAC version not found in rtl_chip_info\n");
3107 goto err_out_msi_5;
1da177e4
LT		 3108 }
3109 tp->chipset = i;
3110
5d06a99f
FR		 3111 RTL_W8(Cfg9346, Cfg9346_Unlock);
3112 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3113 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3114 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3115 tp->features |= RTL_FEATURE_WOL;
3116 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3117 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3118 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3119 RTL_W8(Cfg9346, Cfg9346_Lock);
3120
66ec5d4f
FR		 3121 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3122 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3123 tp->set_speed = rtl8169_set_speed_tbi;
3124 tp->get_settings = rtl8169_gset_tbi;
3125 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3126 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3127 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3128 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3129
64e4bfb4 3130 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3131 } else {
3132 tp->set_speed = rtl8169_set_speed_xmii;
3133 tp->get_settings = rtl8169_gset_xmii;
3134 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3135 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3136 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3137 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3138 }
3139
df58ef51
FR		 3140 spin_lock_init(&tp->lock);
3141
738e1e69
PV		 3142 tp->mmio_addr = ioaddr;
3143
7bf6bf48 3144 /* Get MAC address */
1da177e4
LT		 3145 for (i = 0; i < MAC_ADDR_LEN; i++)
3146 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3147 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3148
1da177e4 3149 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3150 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3151 dev->irq = pdev->irq;
3152 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3153
bea3348e 3154 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3155
3156#ifdef CONFIG_R8169_VLAN
3157 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3158#endif
3159
3160 tp->intr_mask = 0xffff;
0e485150
FR		 3161 tp->align = cfg->align;
3162 tp->hw_start = cfg->hw_start;
3163 tp->intr_event = cfg->intr_event;
3164 tp->napi_event = cfg->napi_event;
1da177e4 3165
2efa53f3
FR		 3166 init_timer(&tp->timer);
3167 tp->timer.data = (unsigned long) dev;
3168 tp->timer.function = rtl8169_phy_timer;
3169
1da177e4 3170 rc = register_netdev(dev);
4ff96fa6 3171 if (rc < 0)
fbac58fc 3172 goto err_out_msi_5;
1da177e4
LT		 3173
3174 pci_set_drvdata(pdev, dev);
3175
bf82c189
JP		 3176 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3177 rtl_chip_info[tp->chipset].name,
3178 dev->base_addr, dev->dev_addr,
3179 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3180
4ff96fa6 3181 rtl8169_init_phy(dev, tp);
05af2142
SW		 3182
3183 /*
3184 * Pretend we are using VLANs; This bypasses a nasty bug where
3185 * Interrupts stop flowing on high load on 8110SCd controllers.
3186 */
3187 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3188 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3189
8b76ab39 3190 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3191
4ff96fa6
FR		 3192out:
3193 return rc;
1da177e4 3194
fbac58fc
FR		 3195err_out_msi_5:
3196 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 3197 iounmap(ioaddr);
3198err_out_free_res_4:
3199 pci_release_regions(pdev);
3200err_out_mwi_3:
3201 pci_clear_mwi(pdev);
3202err_out_disable_2:
3203 pci_disable_device(pdev);
3204err_out_free_dev_1:
3205 free_netdev(dev);
3206 goto out;
1da177e4
LT		 3207}
3208
07d3f51f 3209static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3210{
3211 struct net_device *dev = pci_get_drvdata(pdev);
3212 struct rtl8169_private *tp = netdev_priv(dev);
3213
eb2a021c
FR		 3214 flush_scheduled_work();
3215
1da177e4 3216 unregister_netdev(dev);
cc098dc7
IV		 3217
3218 /* restore original MAC address */
3219 rtl_rar_set(tp, dev->perm_addr);
3220
fbac58fc 3221 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3222 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3223 pci_set_drvdata(pdev, NULL);
3224}
3225
1da177e4
LT		 3226static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3227 struct net_device *dev)
3228{
8812304c 3229 unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
1da177e4 3230
8812304c 3231 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
1da177e4
LT		 3232}
3233
3234static int rtl8169_open(struct net_device *dev)
3235{
3236 struct rtl8169_private *tp = netdev_priv(dev);
3237 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3238 int retval = -ENOMEM;
1da177e4 3239
1da177e4 3240
99f252b0 3241 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 3242
3243 /*
3244 * Rx and Tx desscriptors needs 256 bytes alignment.
3245 * pci_alloc_consistent provides more.
3246 */
3247 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3248 &tp->TxPhyAddr);
3249 if (!tp->TxDescArray)
99f252b0 3250 goto out;
1da177e4
LT		 3251
3252 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3253 &tp->RxPhyAddr);
3254 if (!tp->RxDescArray)
99f252b0 3255 goto err_free_tx_0;
1da177e4
LT		 3256
3257 retval = rtl8169_init_ring(dev);
3258 if (retval < 0)
99f252b0 3259 goto err_free_rx_1;
1da177e4 3260
c4028958 3261 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3262
99f252b0
FR		 3263 smp_mb();
3264
fbac58fc
FR		 3265 retval = request_irq(dev->irq, rtl8169_interrupt,
3266 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3267 dev->name, dev);
3268 if (retval < 0)
3269 goto err_release_ring_2;
3270
bea3348e 3271 napi_enable(&tp->napi);
bea3348e 3272
07ce4064 3273 rtl_hw_start(dev);
1da177e4
LT		 3274
3275 rtl8169_request_timer(dev);
3276
3277 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3278out:
3279 return retval;
3280
99f252b0
FR		 3281err_release_ring_2:
3282 rtl8169_rx_clear(tp);
3283err_free_rx_1:
1da177e4
LT		 3284 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3285 tp->RxPhyAddr);
99f252b0 3286err_free_tx_0:
1da177e4
LT		 3287 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3288 tp->TxPhyAddr);
1da177e4
LT		 3289 goto out;
3290}
3291
3292static void rtl8169_hw_reset(void __iomem *ioaddr)
3293{
3294 /* Disable interrupts */
3295 rtl8169_irq_mask_and_ack(ioaddr);
3296
3297 /* Reset the chipset */
3298 RTL_W8(ChipCmd, CmdReset);
3299
3300 /* PCI commit */
3301 RTL_R8(ChipCmd);
3302}
3303
7f796d83 3304static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3305{
3306 void __iomem *ioaddr = tp->mmio_addr;
3307 u32 cfg = rtl8169_rx_config;
3308
3309 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3310 RTL_W32(RxConfig, cfg);
3311
3312 /* Set DMA burst size and Interframe Gap Time */
3313 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3314 (InterFrameGap << TxInterFrameGapShift));
3315}
3316
07ce4064 3317static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3318{
3319 struct rtl8169_private *tp = netdev_priv(dev);
3320 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3321 unsigned int i;
1da177e4
LT		 3322
3323 /* Soft reset the chip. */
3324 RTL_W8(ChipCmd, CmdReset);
3325
3326 /* Check that the chip has finished the reset. */
07d3f51f 3327 for (i = 0; i < 100; i++) {
1da177e4
LT		 3328 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3329 break;
b518fa8e 3330 msleep_interruptible(1);
1da177e4
LT		 3331 }
3332
07ce4064
FR		 3333 tp->hw_start(dev);
3334
07ce4064
FR		 3335 netif_start_queue(dev);
3336}
3337
3338
7f796d83
FR		 3339static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3340 void __iomem *ioaddr)
3341{
3342 /*
3343 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3344 * register to be written before TxDescAddrLow to work.
3345 * Switching from MMIO to I/O access fixes the issue as well.
3346 */
3347 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3348 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3349 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3350 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3351}
3352
3353static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3354{
3355 u16 cmd;
3356
3357 cmd = RTL_R16(CPlusCmd);
3358 RTL_W16(CPlusCmd, cmd);
3359 return cmd;
3360}
3361
fdd7b4c3 3362static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3363{
3364 /* Low hurts. Let's disable the filtering. */
207d6e87 3365 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3366}
3367
6dccd16b
FR		 3368static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3369{
350f7596 3370 static const struct {
6dccd16b
FR		 3371 u32 mac_version;
3372 u32 clk;
3373 u32 val;
3374 } cfg2_info [] = {
3375 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3376 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3377 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3378 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3379 }, *p = cfg2_info;
3380 unsigned int i;
3381 u32 clk;
3382
3383 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3384 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3385 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3386 RTL_W32(0x7c, p->val);
3387 break;
3388 }
3389 }
3390}
3391
07ce4064
FR		 3392static void rtl_hw_start_8169(struct net_device *dev)
3393{
3394 struct rtl8169_private *tp = netdev_priv(dev);
3395 void __iomem *ioaddr = tp->mmio_addr;
3396 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3397
9cb427b6
FR		 3398 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3399 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3400 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3401 }
3402
1da177e4 3403 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3404 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3405 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3406 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3407 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3408 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3409
1da177e4
LT		 3410 RTL_W8(EarlyTxThres, EarlyTxThld);
3411
fdd7b4c3 3412 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3413
c946b304
FR		 3414 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3415 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3416 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3417 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3418 rtl_set_rx_tx_config_registers(tp);
1da177e4 3419
7f796d83 3420 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3421
bcf0bf90
FR		 3422 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3424 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3425 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3426 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3427 }
3428
bcf0bf90
FR		 3429 RTL_W16(CPlusCmd, tp->cp_cmd);
3430
6dccd16b
FR		 3431 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3432
1da177e4
LT		 3433 /*
3434 * Undocumented corner. Supposedly:
3435 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3436 */
3437 RTL_W16(IntrMitigate, 0x0000);
3438
7f796d83 3439 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3440
c946b304
FR		 3441 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3442 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3443 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3444 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3445 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3446 rtl_set_rx_tx_config_registers(tp);
3447 }
3448
1da177e4 3449 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3450
3451 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3452 RTL_R8(IntrMask);
1da177e4
LT		 3453
3454 RTL_W32(RxMissed, 0);
3455
07ce4064 3456 rtl_set_rx_mode(dev);
1da177e4
LT		 3457
3458 /* no early-rx interrupts */
3459 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3460
3461 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3462 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3463}
1da177e4 3464
9c14ceaf 3465static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3466{
9c14ceaf
FR		 3467 struct net_device *dev = pci_get_drvdata(pdev);
3468 struct rtl8169_private *tp = netdev_priv(dev);
3469 int cap = tp->pcie_cap;
3470
3471 if (cap) {
3472 u16 ctl;
458a9f61 3473
9c14ceaf
FR		 3474 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3475 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3476 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3477 }
458a9f61
FR		 3478}
3479
dacf8154
FR		 3480static void rtl_csi_access_enable(void __iomem *ioaddr)
3481{
3482 u32 csi;
3483
3484 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3485 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3486}
3487
3488struct ephy_info {
3489 unsigned int offset;
3490 u16 mask;
3491 u16 bits;
3492};
3493
350f7596 3494static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3495{
3496 u16 w;
3497
3498 while (len-- > 0) {
3499 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3500 rtl_ephy_write(ioaddr, e->offset, w);
3501 e++;
3502 }
3503}
3504
b726e493
FR		 3505static void rtl_disable_clock_request(struct pci_dev *pdev)
3506{
3507 struct net_device *dev = pci_get_drvdata(pdev);
3508 struct rtl8169_private *tp = netdev_priv(dev);
3509 int cap = tp->pcie_cap;
3510
3511 if (cap) {
3512 u16 ctl;
3513
3514 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3515 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3516 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3517 }
3518}
3519
3520#define R8168_CPCMD_QUIRK_MASK (\
3521 EnableBist | \
3522 Mac_dbgo_oe | \
3523 Force_half_dup | \
3524 Force_rxflow_en | \
3525 Force_txflow_en | \
3526 Cxpl_dbg_sel | \
3527 ASF | \
3528 PktCntrDisable | \
3529 Mac_dbgo_sel)
3530
219a1e9d
FR		 3531static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3532{
b726e493
FR		 3533 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3534
3535 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3536
2e68ae44
FR		 3537 rtl_tx_performance_tweak(pdev,
3538 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3539}
3540
3541static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3542{
3543 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3544
3545 RTL_W8(EarlyTxThres, EarlyTxThld);
3546
3547 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3548}
3549
3550static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3551{
b726e493
FR		 3552 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3553
3554 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3555
219a1e9d 3556 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3557
3558 rtl_disable_clock_request(pdev);
3559
3560 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3561}
3562
ef3386f0 3563static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3564{
350f7596 3565 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3566 { 0x01, 0, 0x0001 },
3567 { 0x02, 0x0800, 0x1000 },
3568 { 0x03, 0, 0x0042 },
3569 { 0x06, 0x0080, 0x0000 },
3570 { 0x07, 0, 0x2000 }
3571 };
3572
3573 rtl_csi_access_enable(ioaddr);
3574
3575 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3576
219a1e9d
FR		 3577 __rtl_hw_start_8168cp(ioaddr, pdev);
3578}
3579
ef3386f0
FR		 3580static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3581{
3582 rtl_csi_access_enable(ioaddr);
3583
3584 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3585
3586 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3587
3588 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3589}
3590
7f3e3d3a
FR		 3591static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3592{
3593 rtl_csi_access_enable(ioaddr);
3594
3595 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3596
3597 /* Magic. */
3598 RTL_W8(DBG_REG, 0x20);
3599
3600 RTL_W8(EarlyTxThres, EarlyTxThld);
3601
3602 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3603
3604 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3605}
3606
219a1e9d
FR		 3607static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3608{
350f7596 3609 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3610 { 0x02, 0x0800, 0x1000 },
3611 { 0x03, 0, 0x0002 },
3612 { 0x06, 0x0080, 0x0000 }
3613 };
3614
3615 rtl_csi_access_enable(ioaddr);
3616
3617 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3618
3619 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3620
219a1e9d
FR		 3621 __rtl_hw_start_8168cp(ioaddr, pdev);
3622}
3623
3624static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3625{
350f7596 3626 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3627 { 0x01, 0, 0x0001 },
3628 { 0x03, 0x0400, 0x0220 }
3629 };
3630
3631 rtl_csi_access_enable(ioaddr);
3632
3633 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3634
219a1e9d
FR		 3635 __rtl_hw_start_8168cp(ioaddr, pdev);
3636}
3637
197ff761
FR		 3638static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3639{
3640 rtl_hw_start_8168c_2(ioaddr, pdev);
3641}
3642
6fb07058
FR		 3643static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3644{
3645 rtl_csi_access_enable(ioaddr);
3646
3647 __rtl_hw_start_8168cp(ioaddr, pdev);
3648}
3649
5b538df9
FR		 3650static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3651{
3652 rtl_csi_access_enable(ioaddr);
3653
3654 rtl_disable_clock_request(pdev);
3655
3656 RTL_W8(EarlyTxThres, EarlyTxThld);
3657
3658 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3659
3660 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3661}
3662
07ce4064
FR		 3663static void rtl_hw_start_8168(struct net_device *dev)
3664{
2dd99530
FR		 3665 struct rtl8169_private *tp = netdev_priv(dev);
3666 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3667 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3668
3669 RTL_W8(Cfg9346, Cfg9346_Unlock);
3670
3671 RTL_W8(EarlyTxThres, EarlyTxThld);
3672
fdd7b4c3 3673 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3674
0e485150 3675 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3676
3677 RTL_W16(CPlusCmd, tp->cp_cmd);
3678
0e485150 3679 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3680
0e485150
FR		 3681 /* Work around for RxFIFO overflow. */
3682 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3683 tp->intr_event |= RxFIFOOver | PCSTimeout;
3684 tp->intr_event &= ~RxOverflow;
3685 }
3686
3687 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3688
b8363901
FR		 3689 rtl_set_rx_mode(dev);
3690
3691 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3692 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3693
3694 RTL_R8(IntrMask);
3695
219a1e9d
FR		 3696 switch (tp->mac_version) {
3697 case RTL_GIGA_MAC_VER_11:
3698 rtl_hw_start_8168bb(ioaddr, pdev);
3699 break;
3700
3701 case RTL_GIGA_MAC_VER_12:
3702 case RTL_GIGA_MAC_VER_17:
3703 rtl_hw_start_8168bef(ioaddr, pdev);
3704 break;
3705
3706 case RTL_GIGA_MAC_VER_18:
ef3386f0 3707 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3708 break;
3709
3710 case RTL_GIGA_MAC_VER_19:
3711 rtl_hw_start_8168c_1(ioaddr, pdev);
3712 break;
3713
3714 case RTL_GIGA_MAC_VER_20:
3715 rtl_hw_start_8168c_2(ioaddr, pdev);
3716 break;
3717
197ff761
FR		 3718 case RTL_GIGA_MAC_VER_21:
3719 rtl_hw_start_8168c_3(ioaddr, pdev);
3720 break;
3721
6fb07058
FR		 3722 case RTL_GIGA_MAC_VER_22:
3723 rtl_hw_start_8168c_4(ioaddr, pdev);
3724 break;
3725
ef3386f0
FR		 3726 case RTL_GIGA_MAC_VER_23:
3727 rtl_hw_start_8168cp_2(ioaddr, pdev);
3728 break;
3729
7f3e3d3a
FR		 3730 case RTL_GIGA_MAC_VER_24:
3731 rtl_hw_start_8168cp_3(ioaddr, pdev);
3732 break;
3733
5b538df9 3734 case RTL_GIGA_MAC_VER_25:
daf9df6d 3735 case RTL_GIGA_MAC_VER_26:
3736 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3737 rtl_hw_start_8168d(ioaddr, pdev);
3738 break;
3739
219a1e9d
FR		 3740 default:
3741 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3742 dev->name, tp->mac_version);
3743 break;
3744 }
2dd99530 3745
0e485150
FR		 3746 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3747
b8363901
FR		 3748 RTL_W8(Cfg9346, Cfg9346_Lock);
3749
2dd99530 3750 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3751
0e485150 3752 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3753}
1da177e4 3754
2857ffb7
FR		 3755#define R810X_CPCMD_QUIRK_MASK (\
3756 EnableBist | \
3757 Mac_dbgo_oe | \
3758 Force_half_dup | \
5edcc537 3759 Force_rxflow_en | \
2857ffb7
FR		 3760 Force_txflow_en | \
3761 Cxpl_dbg_sel | \
3762 ASF | \
3763 PktCntrDisable | \
3764 PCIDAC | \
3765 PCIMulRW)
3766
3767static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3768{
350f7596 3769 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3770 { 0x01, 0, 0x6e65 },
3771 { 0x02, 0, 0x091f },
3772 { 0x03, 0, 0xc2f9 },
3773 { 0x06, 0, 0xafb5 },
3774 { 0x07, 0, 0x0e00 },
3775 { 0x19, 0, 0xec80 },
3776 { 0x01, 0, 0x2e65 },
3777 { 0x01, 0, 0x6e65 }
3778 };
3779 u8 cfg1;
3780
3781 rtl_csi_access_enable(ioaddr);
3782
3783 RTL_W8(DBG_REG, FIX_NAK_1);
3784
3785 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3786
3787 RTL_W8(Config1,
3788 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3789 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3790
3791 cfg1 = RTL_R8(Config1);
3792 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3793 RTL_W8(Config1, cfg1 & ~LEDS0);
3794
3795 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3796
3797 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3798}
3799
3800static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3801{
3802 rtl_csi_access_enable(ioaddr);
3803
3804 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3805
3806 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3807 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3808
3809 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3810}
3811
3812static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3813{
3814 rtl_hw_start_8102e_2(ioaddr, pdev);
3815
3816 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3817}
3818
07ce4064
FR		 3819static void rtl_hw_start_8101(struct net_device *dev)
3820{
cdf1a608
FR		 3821 struct rtl8169_private *tp = netdev_priv(dev);
3822 void __iomem *ioaddr = tp->mmio_addr;
3823 struct pci_dev *pdev = tp->pci_dev;
3824
e3cf0cc0
FR		 3825 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3826 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3827 int cap = tp->pcie_cap;
3828
3829 if (cap) {
3830 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3831 PCI_EXP_DEVCTL_NOSNOOP_EN);
3832 }
cdf1a608
FR		 3833 }
3834
2857ffb7
FR		 3835 switch (tp->mac_version) {
3836 case RTL_GIGA_MAC_VER_07:
3837 rtl_hw_start_8102e_1(ioaddr, pdev);
3838 break;
3839
3840 case RTL_GIGA_MAC_VER_08:
3841 rtl_hw_start_8102e_3(ioaddr, pdev);
3842 break;
3843
3844 case RTL_GIGA_MAC_VER_09:
3845 rtl_hw_start_8102e_2(ioaddr, pdev);
3846 break;
cdf1a608
FR		 3847 }
3848
3849 RTL_W8(Cfg9346, Cfg9346_Unlock);
3850
3851 RTL_W8(EarlyTxThres, EarlyTxThld);
3852
fdd7b4c3 3853 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3854
3855 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3856
3857 RTL_W16(CPlusCmd, tp->cp_cmd);
3858
3859 RTL_W16(IntrMitigate, 0x0000);
3860
3861 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3862
3863 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3864 rtl_set_rx_tx_config_registers(tp);
3865
3866 RTL_W8(Cfg9346, Cfg9346_Lock);
3867
3868 RTL_R8(IntrMask);
3869
cdf1a608
FR		 3870 rtl_set_rx_mode(dev);
3871
0e485150
FR		 3872 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3873
cdf1a608 3874 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3875
0e485150 3876 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3877}
3878
3879static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3880{
3881 struct rtl8169_private *tp = netdev_priv(dev);
3882 int ret = 0;
3883
3884 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3885 return -EINVAL;
3886
3887 dev->mtu = new_mtu;
3888
3889 if (!netif_running(dev))
3890 goto out;
3891
3892 rtl8169_down(dev);
3893
3894 rtl8169_set_rxbufsize(tp, dev);
3895
3896 ret = rtl8169_init_ring(dev);
3897 if (ret < 0)
3898 goto out;
3899
bea3348e 3900 napi_enable(&tp->napi);
1da177e4 3901
07ce4064 3902 rtl_hw_start(dev);
1da177e4
LT		 3903
3904 rtl8169_request_timer(dev);
3905
3906out:
3907 return ret;
3908}
3909
3910static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3911{
95e0918d 3912 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3913 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3914}
3915
3916static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3917 struct sk_buff **sk_buff, struct RxDesc *desc)
3918{
3919 struct pci_dev *pdev = tp->pci_dev;
3920
3921 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3922 PCI_DMA_FROMDEVICE);
3923 dev_kfree_skb(*sk_buff);
3924 *sk_buff = NULL;
3925 rtl8169_make_unusable_by_asic(desc);
3926}
3927
3928static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3929{
3930 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3931
3932 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3933}
3934
3935static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3936 u32 rx_buf_sz)
3937{
3938 desc->addr = cpu_to_le64(mapping);
3939 wmb();
3940 rtl8169_mark_to_asic(desc, rx_buf_sz);
3941}
3942
15d31758
SH		 3943static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3944 struct net_device *dev,
3945 struct RxDesc *desc, int rx_buf_sz,
3946 unsigned int align)
1da177e4
LT		 3947{
3948 struct sk_buff *skb;
3949 dma_addr_t mapping;
e9f63f30 3950 unsigned int pad;
1da177e4 3951
e9f63f30
FR		 3952 pad = align ? align : NET_IP_ALIGN;
3953
3954 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3955 if (!skb)
3956 goto err_out;
3957
e9f63f30 3958 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3959
689be439 3960 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3961 PCI_DMA_FROMDEVICE);
3962
3963 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3964out:
15d31758 3965 return skb;
1da177e4
LT		 3966
3967err_out:
1da177e4
LT		 3968 rtl8169_make_unusable_by_asic(desc);
3969 goto out;
3970}
3971
3972static void rtl8169_rx_clear(struct rtl8169_private *tp)
3973{
07d3f51f 3974 unsigned int i;
1da177e4
LT		 3975
3976 for (i = 0; i < NUM_RX_DESC; i++) {
3977 if (tp->Rx_skbuff[i]) {
3978 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3979 tp->RxDescArray + i);
3980 }
3981 }
3982}
3983
3984static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3985 u32 start, u32 end)
3986{
3987 u32 cur;
5b0384f4 3988
4ae47c2d 3989 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 3990 struct sk_buff *skb;
3991 unsigned int i = cur % NUM_RX_DESC;
1da177e4 3992
4ae47c2d
FR		 3993 WARN_ON((s32)(end - cur) < 0);
3994
1da177e4
LT		 3995 if (tp->Rx_skbuff[i])
3996 continue;
bcf0bf90 3997
15d31758
SH		 3998 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3999 tp->RxDescArray + i,
4000 tp->rx_buf_sz, tp->align);
4001 if (!skb)
1da177e4 4002 break;
15d31758
SH		 4003
4004 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 4005 }
4006 return cur - start;
4007}
4008
4009static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4010{
4011 desc->opts1 |= cpu_to_le32(RingEnd);
4012}
4013
4014static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4015{
4016 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4017}
4018
4019static int rtl8169_init_ring(struct net_device *dev)
4020{
4021 struct rtl8169_private *tp = netdev_priv(dev);
4022
4023 rtl8169_init_ring_indexes(tp);
4024
4025 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4026 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4027
4028 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4029 goto err_out;
4030
4031 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4032
4033 return 0;
4034
4035err_out:
4036 rtl8169_rx_clear(tp);
4037 return -ENOMEM;
4038}
4039
4040static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4041 struct TxDesc *desc)
4042{
4043 unsigned int len = tx_skb->len;
4044
4045 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4046 desc->opts1 = 0x00;
4047 desc->opts2 = 0x00;
4048 desc->addr = 0x00;
4049 tx_skb->len = 0;
4050}
4051
4052static void rtl8169_tx_clear(struct rtl8169_private *tp)
4053{
4054 unsigned int i;
4055
4056 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4057 unsigned int entry = i % NUM_TX_DESC;
4058 struct ring_info *tx_skb = tp->tx_skb + entry;
4059 unsigned int len = tx_skb->len;
4060
4061 if (len) {
4062 struct sk_buff *skb = tx_skb->skb;
4063
4064 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4065 tp->TxDescArray + entry);
4066 if (skb) {
4067 dev_kfree_skb(skb);
4068 tx_skb->skb = NULL;
4069 }
cebf8cc7 4070 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4071 }
4072 }
4073 tp->cur_tx = tp->dirty_tx = 0;
4074}
4075
c4028958 4076static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4077{
4078 struct rtl8169_private *tp = netdev_priv(dev);
4079
c4028958 4080 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4081 schedule_delayed_work(&tp->task, 4);
4082}
4083
4084static void rtl8169_wait_for_quiescence(struct net_device *dev)
4085{
4086 struct rtl8169_private *tp = netdev_priv(dev);
4087 void __iomem *ioaddr = tp->mmio_addr;
4088
4089 synchronize_irq(dev->irq);
4090
4091 /* Wait for any pending NAPI task to complete */
bea3348e 4092 napi_disable(&tp->napi);
1da177e4
LT		 4093
4094 rtl8169_irq_mask_and_ack(ioaddr);
4095
d1d08d12
DM		 4096 tp->intr_mask = 0xffff;
4097 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4098 napi_enable(&tp->napi);
1da177e4
LT		 4099}
4100
c4028958 4101static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4102{
c4028958
DH		 4103 struct rtl8169_private *tp =
4104 container_of(work, struct rtl8169_private, task.work);
4105 struct net_device *dev = tp->dev;
1da177e4
LT		 4106 int ret;
4107
eb2a021c
FR		 4108 rtnl_lock();
4109
4110 if (!netif_running(dev))
4111 goto out_unlock;
4112
4113 rtl8169_wait_for_quiescence(dev);
4114 rtl8169_close(dev);
1da177e4
LT		 4115
4116 ret = rtl8169_open(dev);
4117 if (unlikely(ret < 0)) {
bf82c189
JP		 4118 if (net_ratelimit())
4119 netif_err(tp, drv, dev,
4120 "reinit failure (status = %d). Rescheduling\n",
4121 ret);
1da177e4
LT		 4122 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4123 }
eb2a021c
FR		 4124
4125out_unlock:
4126 rtnl_unlock();
1da177e4
LT		 4127}
4128
c4028958 4129static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4130{
c4028958
DH		 4131 struct rtl8169_private *tp =
4132 container_of(work, struct rtl8169_private, task.work);
4133 struct net_device *dev = tp->dev;
1da177e4 4134
eb2a021c
FR		 4135 rtnl_lock();
4136
1da177e4 4137 if (!netif_running(dev))
eb2a021c 4138 goto out_unlock;
1da177e4
LT		 4139
4140 rtl8169_wait_for_quiescence(dev);
4141
bea3348e 4142 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4143 rtl8169_tx_clear(tp);
4144
4145 if (tp->dirty_rx == tp->cur_rx) {
4146 rtl8169_init_ring_indexes(tp);
07ce4064 4147 rtl_hw_start(dev);
1da177e4 4148 netif_wake_queue(dev);
cebf8cc7 4149 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4150 } else {
bf82c189
JP		 4151 if (net_ratelimit())
4152 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4153 rtl8169_schedule_work(dev, rtl8169_reset_task);
4154 }
eb2a021c
FR		 4155
4156out_unlock:
4157 rtnl_unlock();
1da177e4
LT		 4158}
4159
4160static void rtl8169_tx_timeout(struct net_device *dev)
4161{
4162 struct rtl8169_private *tp = netdev_priv(dev);
4163
4164 rtl8169_hw_reset(tp->mmio_addr);
4165
4166 /* Let's wait a bit while any (async) irq lands on */
4167 rtl8169_schedule_work(dev, rtl8169_reset_task);
4168}
4169
4170static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4171 u32 opts1)
4172{
4173 struct skb_shared_info *info = skb_shinfo(skb);
4174 unsigned int cur_frag, entry;
a6343afb 4175 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4176
4177 entry = tp->cur_tx;
4178 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4179 skb_frag_t *frag = info->frags + cur_frag;
4180 dma_addr_t mapping;
4181 u32 status, len;
4182 void *addr;
4183
4184 entry = (entry + 1) % NUM_TX_DESC;
4185
4186 txd = tp->TxDescArray + entry;
4187 len = frag->size;
4188 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4189 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4190
4191 /* anti gcc 2.95.3 bugware (sic) */
4192 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4193
4194 txd->opts1 = cpu_to_le32(status);
4195 txd->addr = cpu_to_le64(mapping);
4196
4197 tp->tx_skb[entry].len = len;
4198 }
4199
4200 if (cur_frag) {
4201 tp->tx_skb[entry].skb = skb;
4202 txd->opts1 |= cpu_to_le32(LastFrag);
4203 }
4204
4205 return cur_frag;
4206}
4207
4208static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4209{
4210 if (dev->features & NETIF_F_TSO) {
7967168c 4211 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4212
4213 if (mss)
4214 return LargeSend | ((mss & MSSMask) << MSSShift);
4215 }
84fa7933 4216 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4217 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4218
4219 if (ip->protocol == IPPROTO_TCP)
4220 return IPCS | TCPCS;
4221 else if (ip->protocol == IPPROTO_UDP)
4222 return IPCS | UDPCS;
4223 WARN_ON(1); /* we need a WARN() */
4224 }
4225 return 0;
4226}
4227
61357325
SH		 4228static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4229 struct net_device *dev)
1da177e4
LT		 4230{
4231 struct rtl8169_private *tp = netdev_priv(dev);
4232 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4233 struct TxDesc *txd = tp->TxDescArray + entry;
4234 void __iomem *ioaddr = tp->mmio_addr;
4235 dma_addr_t mapping;
4236 u32 status, len;
4237 u32 opts1;
5b0384f4 4238
1da177e4 4239 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4240 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 4241 goto err_stop;
4242 }
4243
4244 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4245 goto err_stop;
4246
4247 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4248
4249 frags = rtl8169_xmit_frags(tp, skb, opts1);
4250 if (frags) {
4251 len = skb_headlen(skb);
4252 opts1 |= FirstFrag;
4253 } else {
4254 len = skb->len;
1da177e4
LT		 4255 opts1 |= FirstFrag | LastFrag;
4256 tp->tx_skb[entry].skb = skb;
4257 }
4258
4259 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4260
4261 tp->tx_skb[entry].len = len;
4262 txd->addr = cpu_to_le64(mapping);
4263 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4264
4265 wmb();
4266
4267 /* anti gcc 2.95.3 bugware (sic) */
4268 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4269 txd->opts1 = cpu_to_le32(status);
4270
1da177e4
LT		 4271 tp->cur_tx += frags + 1;
4272
4c020a96 4273 wmb();
1da177e4 4274
275391a4 4275 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4276
4277 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4278 netif_stop_queue(dev);
4279 smp_rmb();
4280 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4281 netif_wake_queue(dev);
4282 }
4283
61357325 4284 return NETDEV_TX_OK;
1da177e4
LT		 4285
4286err_stop:
4287 netif_stop_queue(dev);
cebf8cc7 4288 dev->stats.tx_dropped++;
61357325 4289 return NETDEV_TX_BUSY;
1da177e4
LT		 4290}
4291
4292static void rtl8169_pcierr_interrupt(struct net_device *dev)
4293{
4294 struct rtl8169_private *tp = netdev_priv(dev);
4295 struct pci_dev *pdev = tp->pci_dev;
4296 void __iomem *ioaddr = tp->mmio_addr;
4297 u16 pci_status, pci_cmd;
4298
4299 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4300 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4301
bf82c189
JP		 4302 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4303 pci_cmd, pci_status);
1da177e4
LT		 4304
4305 /*
4306 * The recovery sequence below admits a very elaborated explanation:
4307 * - it seems to work;
d03902b8
FR		 4308 * - I did not see what else could be done;
4309 * - it makes iop3xx happy.
1da177e4
LT		 4310 *
4311 * Feel free to adjust to your needs.
4312 */
a27993f3 4313 if (pdev->broken_parity_status)
d03902b8
FR		 4314 pci_cmd &= ~PCI_COMMAND_PARITY;
4315 else
4316 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4317
4318 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4319
4320 pci_write_config_word(pdev, PCI_STATUS,
4321 pci_status & (PCI_STATUS_DETECTED_PARITY |
4322 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4323 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4324
4325 /* The infamous DAC f*ckup only happens at boot time */
4326 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4327 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4328 tp->cp_cmd &= ~PCIDAC;
4329 RTL_W16(CPlusCmd, tp->cp_cmd);
4330 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4331 }
4332
4333 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4334
4335 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4336}
4337
07d3f51f
FR		 4338static void rtl8169_tx_interrupt(struct net_device *dev,
4339 struct rtl8169_private *tp,
4340 void __iomem *ioaddr)
1da177e4
LT		 4341{
4342 unsigned int dirty_tx, tx_left;
4343
1da177e4
LT		 4344 dirty_tx = tp->dirty_tx;
4345 smp_rmb();
4346 tx_left = tp->cur_tx - dirty_tx;
4347
4348 while (tx_left > 0) {
4349 unsigned int entry = dirty_tx % NUM_TX_DESC;
4350 struct ring_info *tx_skb = tp->tx_skb + entry;
4351 u32 len = tx_skb->len;
4352 u32 status;
4353
4354 rmb();
4355 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4356 if (status & DescOwn)
4357 break;
4358
cebf8cc7
FR		 4359 dev->stats.tx_bytes += len;
4360 dev->stats.tx_packets++;
1da177e4
LT		 4361
4362 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4363
4364 if (status & LastFrag) {
87433bfc 4365 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4366 tx_skb->skb = NULL;
4367 }
4368 dirty_tx++;
4369 tx_left--;
4370 }
4371
4372 if (tp->dirty_tx != dirty_tx) {
4373 tp->dirty_tx = dirty_tx;
4374 smp_wmb();
4375 if (netif_queue_stopped(dev) &&
4376 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4377 netif_wake_queue(dev);
4378 }
d78ae2dc
FR		 4379 /*
4380 * 8168 hack: TxPoll requests are lost when the Tx packets are
4381 * too close. Let's kick an extra TxPoll request when a burst
4382 * of start_xmit activity is detected (if it is not detected,
4383 * it is slow enough). -- FR
4384 */
4385 smp_rmb();
4386 if (tp->cur_tx != dirty_tx)
4387 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4388 }
4389}
4390
126fa4b9
FR		 4391static inline int rtl8169_fragmented_frame(u32 status)
4392{
4393 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4394}
4395
1da177e4
LT		 4396static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4397{
4398 u32 opts1 = le32_to_cpu(desc->opts1);
4399 u32 status = opts1 & RxProtoMask;
4400
4401 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4402 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4403 ((status == RxProtoIP) && !(opts1 & IPFail)))
4404 skb->ip_summed = CHECKSUM_UNNECESSARY;
4405 else
4406 skb->ip_summed = CHECKSUM_NONE;
4407}
4408
07d3f51f
FR		 4409static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4410 struct rtl8169_private *tp, int pkt_size,
4411 dma_addr_t addr)
1da177e4 4412{
b449655f
SH		 4413 struct sk_buff *skb;
4414 bool done = false;
1da177e4 4415
b449655f
SH		 4416 if (pkt_size >= rx_copybreak)
4417 goto out;
1da177e4 4418
89d71a66 4419 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
b449655f
SH		 4420 if (!skb)
4421 goto out;
4422
07d3f51f
FR		 4423 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4424 PCI_DMA_FROMDEVICE);
b449655f
SH		 4425 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4426 *sk_buff = skb;
4427 done = true;
4428out:
4429 return done;
1da177e4
LT		 4430}
4431
07d3f51f
FR		 4432static int rtl8169_rx_interrupt(struct net_device *dev,
4433 struct rtl8169_private *tp,
bea3348e 4434 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4435{
4436 unsigned int cur_rx, rx_left;
4437 unsigned int delta, count;
4438
1da177e4
LT		 4439 cur_rx = tp->cur_rx;
4440 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4441 rx_left = min(rx_left, budget);
1da177e4 4442
4dcb7d33 4443 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4444 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4445 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4446 u32 status;
4447
4448 rmb();
126fa4b9 4449 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4450
4451 if (status & DescOwn)
4452 break;
4dcb7d33 4453 if (unlikely(status & RxRES)) {
bf82c189
JP		 4454 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4455 status);
cebf8cc7 4456 dev->stats.rx_errors++;
1da177e4 4457 if (status & (RxRWT | RxRUNT))
cebf8cc7 4458 dev->stats.rx_length_errors++;
1da177e4 4459 if (status & RxCRC)
cebf8cc7 4460 dev->stats.rx_crc_errors++;
9dccf611
FR		 4461 if (status & RxFOVF) {
4462 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4463 dev->stats.rx_fifo_errors++;
9dccf611 4464 }
126fa4b9 4465 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4466 } else {
1da177e4 4467 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4468 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4469 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4470 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4471
126fa4b9
FR		 4472 /*
4473 * The driver does not support incoming fragmented
4474 * frames. They are seen as a symptom of over-mtu
4475 * sized frames.
4476 */
4477 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4478 dev->stats.rx_dropped++;
4479 dev->stats.rx_length_errors++;
126fa4b9 4480 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4481 continue;
126fa4b9
FR		 4482 }
4483
1da177e4 4484 rtl8169_rx_csum(skb, desc);
bcf0bf90 4485
07d3f51f 4486 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 4487 pci_dma_sync_single_for_device(pdev, addr,
4488 pkt_size, PCI_DMA_FROMDEVICE);
4489 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4490 } else {
a866bbf6 4491 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 4492 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4493 tp->Rx_skbuff[entry] = NULL;
4494 }
4495
1da177e4
LT		 4496 skb_put(skb, pkt_size);
4497 skb->protocol = eth_type_trans(skb, dev);
4498
4499 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 4500 netif_receive_skb(skb);
1da177e4 4501
cebf8cc7
FR		 4502 dev->stats.rx_bytes += pkt_size;
4503 dev->stats.rx_packets++;
1da177e4 4504 }
6dccd16b
FR		 4505
4506 /* Work around for AMD plateform. */
95e0918d 4507 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4508 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4509 desc->opts2 = 0;
4510 cur_rx++;
4511 }
1da177e4
LT		 4512 }
4513
4514 count = cur_rx - tp->cur_rx;
4515 tp->cur_rx = cur_rx;
4516
4517 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
bf82c189
JP		 4518 if (!delta && count)
4519 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
1da177e4
LT		 4520 tp->dirty_rx += delta;
4521
4522 /*
4523 * FIXME: until there is periodic timer to try and refill the ring,
4524 * a temporary shortage may definitely kill the Rx process.
4525 * - disable the asic to try and avoid an overflow and kick it again
4526 * after refill ?
4527 * - how do others driver handle this condition (Uh oh...).
4528 */
bf82c189
JP		 4529 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4530 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
1da177e4
LT		 4531
4532 return count;
4533}
4534
07d3f51f 4535static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4536{
07d3f51f 4537 struct net_device *dev = dev_instance;
1da177e4 4538 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4539 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4540 int handled = 0;
865c652d 4541 int status;
1da177e4 4542
f11a377b
DD		 4543 /* loop handling interrupts until we have no new ones or
4544 * we hit a invalid/hotplug case.
4545 */
865c652d 4546 status = RTL_R16(IntrStatus);
f11a377b
DD		 4547 while (status && status != 0xffff) {
4548 handled = 1;
1da177e4 4549
f11a377b
DD		 4550 /* Handle all of the error cases first. These will reset
4551 * the chip, so just exit the loop.
4552 */
4553 if (unlikely(!netif_running(dev))) {
4554 rtl8169_asic_down(ioaddr);
4555 break;
4556 }
1da177e4 4557
f11a377b
DD		 4558 /* Work around for rx fifo overflow */
4559 if (unlikely(status & RxFIFOOver) &&
4560 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4561 netif_stop_queue(dev);
4562 rtl8169_tx_timeout(dev);
4563 break;
4564 }
1da177e4 4565
f11a377b
DD		 4566 if (unlikely(status & SYSErr)) {
4567 rtl8169_pcierr_interrupt(dev);
4568 break;
4569 }
1da177e4 4570
f11a377b
DD		 4571 if (status & LinkChg)
4572 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4573
f11a377b
DD		 4574 /* We need to see the lastest version of tp->intr_mask to
4575 * avoid ignoring an MSI interrupt and having to wait for
4576 * another event which may never come.
4577 */
4578 smp_rmb();
4579 if (status & tp->intr_mask & tp->napi_event) {
4580 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4581 tp->intr_mask = ~tp->napi_event;
4582
4583 if (likely(napi_schedule_prep(&tp->napi)))
4584 __napi_schedule(&tp->napi);
bf82c189
JP		 4585 else
4586 netif_info(tp, intr, dev,
4587 "interrupt %04x in poll\n", status);
f11a377b 4588 }
1da177e4 4589
f11a377b
DD		 4590 /* We only get a new MSI interrupt when all active irq
4591 * sources on the chip have been acknowledged. So, ack
4592 * everything we've seen and check if new sources have become
4593 * active to avoid blocking all interrupts from the chip.
4594 */
4595 RTL_W16(IntrStatus,
4596 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4597 status = RTL_R16(IntrStatus);
865c652d 4598 }
1da177e4 4599
1da177e4
LT		 4600 return IRQ_RETVAL(handled);
4601}
4602
bea3348e 4603static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4604{
bea3348e
SH		 4605 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4606 struct net_device *dev = tp->dev;
1da177e4 4607 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4608 int work_done;
1da177e4 4609
bea3348e 4610 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4611 rtl8169_tx_interrupt(dev, tp, ioaddr);
4612
bea3348e 4613 if (work_done < budget) {
288379f0 4614 napi_complete(napi);
f11a377b
DD		 4615
4616 /* We need for force the visibility of tp->intr_mask
4617 * for other CPUs, as we can loose an MSI interrupt
4618 * and potentially wait for a retransmit timeout if we don't.
4619 * The posted write to IntrMask is safe, as it will
4620 * eventually make it to the chip and we won't loose anything
4621 * until it does.
1da177e4 4622 */
f11a377b 4623 tp->intr_mask = 0xffff;
4c020a96 4624 wmb();
0e485150 4625 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4626 }
4627
bea3348e 4628 return work_done;
1da177e4 4629}
1da177e4 4630
523a6094
FR		 4631static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4632{
4633 struct rtl8169_private *tp = netdev_priv(dev);
4634
4635 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4636 return;
4637
4638 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4639 RTL_W32(RxMissed, 0);
4640}
4641
1da177e4
LT		 4642static void rtl8169_down(struct net_device *dev)
4643{
4644 struct rtl8169_private *tp = netdev_priv(dev);
4645 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4646 unsigned int intrmask;
1da177e4
LT		 4647
4648 rtl8169_delete_timer(dev);
4649
4650 netif_stop_queue(dev);
4651
93dd79e8 4652 napi_disable(&tp->napi);
93dd79e8 4653
1da177e4
LT		 4654core_down:
4655 spin_lock_irq(&tp->lock);
4656
4657 rtl8169_asic_down(ioaddr);
4658
523a6094 4659 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4660
4661 spin_unlock_irq(&tp->lock);
4662
4663 synchronize_irq(dev->irq);
4664
1da177e4 4665 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4666 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4667
4668 /*
4669 * And now for the 50k$ question: are IRQ disabled or not ?
4670 *
4671 * Two paths lead here:
4672 * 1) dev->close
4673 * -> netif_running() is available to sync the current code and the
4674 * IRQ handler. See rtl8169_interrupt for details.
4675 * 2) dev->change_mtu
4676 * -> rtl8169_poll can not be issued again and re-enable the
4677 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4678 *
4679 * No loop if hotpluged or major error (0xffff).
1da177e4 4680 */
733b736c
AP		 4681 intrmask = RTL_R16(IntrMask);
4682 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4683 goto core_down;
4684
4685 rtl8169_tx_clear(tp);
4686
4687 rtl8169_rx_clear(tp);
4688}
4689
4690static int rtl8169_close(struct net_device *dev)
4691{
4692 struct rtl8169_private *tp = netdev_priv(dev);
4693 struct pci_dev *pdev = tp->pci_dev;
4694
355423d0
IV		 4695 /* update counters before going down */
4696 rtl8169_update_counters(dev);
4697
1da177e4
LT		 4698 rtl8169_down(dev);
4699
4700 free_irq(dev->irq, dev);
4701
1da177e4
LT		 4702 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4703 tp->RxPhyAddr);
4704 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4705 tp->TxPhyAddr);
4706 tp->TxDescArray = NULL;
4707 tp->RxDescArray = NULL;
4708
4709 return 0;
4710}
4711
07ce4064 4712static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4713{
4714 struct rtl8169_private *tp = netdev_priv(dev);
4715 void __iomem *ioaddr = tp->mmio_addr;
4716 unsigned long flags;
4717 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4718 int rx_mode;
1da177e4
LT		 4719 u32 tmp = 0;
4720
4721 if (dev->flags & IFF_PROMISC) {
4722 /* Unconditionally log net taps. */
bf82c189 4723 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4724 rx_mode =
4725 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4726 AcceptAllPhys;
4727 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4728 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4729 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4730 /* Too many to filter perfectly -- accept all multicasts. */
4731 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4732 mc_filter[1] = mc_filter[0] = 0xffffffff;
4733 } else {
4734 struct dev_mc_list *mclist;
07d3f51f 4735
1da177e4
LT		 4736 rx_mode = AcceptBroadcast | AcceptMyPhys;
4737 mc_filter[1] = mc_filter[0] = 0;
f9dcbcc9 4738 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 4739 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4740 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4741 rx_mode |= AcceptMulticast;
4742 }
4743 }
4744
4745 spin_lock_irqsave(&tp->lock, flags);
4746
4747 tmp = rtl8169_rx_config | rx_mode |
4748 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4749
f887cce8 4750 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4751 u32 data = mc_filter[0];
4752
4753 mc_filter[0] = swab32(mc_filter[1]);
4754 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4755 }
4756
1da177e4
LT		 4757 RTL_W32(MAR0 + 0, mc_filter[0]);
4758 RTL_W32(MAR0 + 4, mc_filter[1]);
4759
57a9f236
FR		 4760 RTL_W32(RxConfig, tmp);
4761
1da177e4
LT		 4762 spin_unlock_irqrestore(&tp->lock, flags);
4763}
4764
4765/**
4766 * rtl8169_get_stats - Get rtl8169 read/write statistics
4767 * @dev: The Ethernet Device to get statistics for
4768 *
4769 * Get TX/RX statistics for rtl8169
4770 */
4771static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4772{
4773 struct rtl8169_private *tp = netdev_priv(dev);
4774 void __iomem *ioaddr = tp->mmio_addr;
4775 unsigned long flags;
4776
4777 if (netif_running(dev)) {
4778 spin_lock_irqsave(&tp->lock, flags);
523a6094 4779 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4780 spin_unlock_irqrestore(&tp->lock, flags);
4781 }
5b0384f4 4782
cebf8cc7 4783 return &dev->stats;
1da177e4
LT		 4784}
4785
861ab440 4786static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4787{
5d06a99f 4788 if (!netif_running(dev))
861ab440 4789 return;
5d06a99f
FR		 4790
4791 netif_device_detach(dev);
4792 netif_stop_queue(dev);
861ab440
RW		 4793}
4794
4795#ifdef CONFIG_PM
4796
4797static int rtl8169_suspend(struct device *device)
4798{
4799 struct pci_dev *pdev = to_pci_dev(device);
4800 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4801
861ab440 4802 rtl8169_net_suspend(dev);
1371fa6d 4803
5d06a99f
FR		 4804 return 0;
4805}
4806
861ab440 4807static int rtl8169_resume(struct device *device)
5d06a99f 4808{
861ab440 4809 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4810 struct net_device *dev = pci_get_drvdata(pdev);
4811
4812 if (!netif_running(dev))
4813 goto out;
4814
4815 netif_device_attach(dev);
4816
5d06a99f
FR		 4817 rtl8169_schedule_work(dev, rtl8169_reset_task);
4818out:
4819 return 0;
4820}
4821
47145210 4822static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4823 .suspend = rtl8169_suspend,
4824 .resume = rtl8169_resume,
4825 .freeze = rtl8169_suspend,
4826 .thaw = rtl8169_resume,
4827 .poweroff = rtl8169_suspend,
4828 .restore = rtl8169_resume,
4829};
4830
4831#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4832
4833#else /* !CONFIG_PM */
4834
4835#define RTL8169_PM_OPS NULL
4836
4837#endif /* !CONFIG_PM */
4838
1765f95d
FR		 4839static void rtl_shutdown(struct pci_dev *pdev)
4840{
861ab440 4841 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4842 struct rtl8169_private *tp = netdev_priv(dev);
4843 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4844
4845 rtl8169_net_suspend(dev);
1765f95d 4846
cc098dc7
IV		 4847 /* restore original MAC address */
4848 rtl_rar_set(tp, dev->perm_addr);
4849
4bb3f522 4850 spin_lock_irq(&tp->lock);
4851
4852 rtl8169_asic_down(ioaddr);
4853
4854 spin_unlock_irq(&tp->lock);
4855
861ab440 4856 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4857 /* WoL fails with some 8168 when the receiver is disabled. */
4858 if (tp->features & RTL_FEATURE_WOL) {
4859 pci_clear_master(pdev);
4860
4861 RTL_W8(ChipCmd, CmdRxEnb);
4862 /* PCI commit */
4863 RTL_R8(ChipCmd);
4864 }
4865
861ab440
RW		 4866 pci_wake_from_d3(pdev, true);
4867 pci_set_power_state(pdev, PCI_D3hot);
4868 }
4869}
5d06a99f 4870
1da177e4
LT		 4871static struct pci_driver rtl8169_pci_driver = {
4872 .name = MODULENAME,
4873 .id_table = rtl8169_pci_tbl,
4874 .probe = rtl8169_init_one,
4875 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4876 .shutdown = rtl_shutdown,
861ab440 4877 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4878};
4879
07d3f51f 4880static int __init rtl8169_init_module(void)
1da177e4 4881{
29917620 4882 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4883}
4884
07d3f51f 4885static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4886{
4887 pci_unregister_driver(&rtl8169_pci_driver);
4888}
4889
4890module_init(rtl8169_init_module);
4891module_exit(rtl8169_cleanup_module);
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