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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
64#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 67#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 68#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
69#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
70#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71
72#define R8169_REGS_SIZE 256
73#define R8169_NAPI_WEIGHT 64
74#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
76#define RX_BUF_SIZE 1536 /* Rx Buffer size */
77#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80#define RTL8169_TX_TIMEOUT (6*HZ)
81#define RTL8169_PHY_TIMEOUT (10*HZ)
82
83/* write/read MMIO register */
84#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
85#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
86#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
87#define RTL_R8(reg) readb (ioaddr + (reg))
88#define RTL_R16(reg) readw (ioaddr + (reg))
89#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
90
91enum mac_version {
ba6eb6ee
FR		 92 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
93 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
94 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
95 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
96 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 97 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 98 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 99 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
100 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
101 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
102 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
103 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
104 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
105 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
106 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
107 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 108};
109
1da177e4
LT		 110#define _R(NAME,MAC,MASK) \
111 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
112
3c6bee1d 113static const struct {
1da177e4
LT		 114 const char *name;
115 u8 mac_version;
116 u32 RxConfigMask; /* Clears the bits supported by this chip */
117} rtl_chip_info[] = {
ba6eb6ee
FR		 118 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
119 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
120 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
121 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
122 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 124 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
126 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
127 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 128 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
129 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
130 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
131 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
132 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 134};
135#undef _R
136
bcf0bf90
FR		 137enum cfg_version {
138 RTL_CFG_0 = 0x00,
139 RTL_CFG_1,
140 RTL_CFG_2
141};
142
07ce4064
FR		 143static void rtl_hw_start_8169(struct net_device *);
144static void rtl_hw_start_8168(struct net_device *);
145static void rtl_hw_start_8101(struct net_device *);
146
1da177e4 147static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 148 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
153 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 154 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 155 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
156 { PCI_VENDOR_ID_LINKSYS, 0x1032,
157 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 158 { 0x0001, 0x8168,
159 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 160 {0,},
161};
162
163MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
164
165static int rx_copybreak = 200;
166static int use_dac;
b57b7e5a
SH		 167static struct {
168 u32 msg_enable;
169} debug = { -1 };
1da177e4 170
07d3f51f
FR		 171enum rtl_registers {
172 MAC0 = 0, /* Ethernet hardware address. */
773d2021 173 MAC4 = 4,
07d3f51f
FR		 174 MAR0 = 8, /* Multicast filter. */
175 CounterAddrLow = 0x10,
176 CounterAddrHigh = 0x14,
177 TxDescStartAddrLow = 0x20,
178 TxDescStartAddrHigh = 0x24,
179 TxHDescStartAddrLow = 0x28,
180 TxHDescStartAddrHigh = 0x2c,
181 FLASH = 0x30,
182 ERSR = 0x36,
183 ChipCmd = 0x37,
184 TxPoll = 0x38,
185 IntrMask = 0x3c,
186 IntrStatus = 0x3e,
187 TxConfig = 0x40,
188 RxConfig = 0x44,
189 RxMissed = 0x4c,
190 Cfg9346 = 0x50,
191 Config0 = 0x51,
192 Config1 = 0x52,
193 Config2 = 0x53,
194 Config3 = 0x54,
195 Config4 = 0x55,
196 Config5 = 0x56,
197 MultiIntr = 0x5c,
198 PHYAR = 0x60,
199 TBICSR = 0x64,
200 TBI_ANAR = 0x68,
201 TBI_LPAR = 0x6a,
202 PHYstatus = 0x6c,
203 RxMaxSize = 0xda,
204 CPlusCmd = 0xe0,
205 IntrMitigate = 0xe2,
206 RxDescAddrLow = 0xe4,
207 RxDescAddrHigh = 0xe8,
208 EarlyTxThres = 0xec,
209 FuncEvent = 0xf0,
210 FuncEventMask = 0xf4,
211 FuncPresetState = 0xf8,
212 FuncForceEvent = 0xfc,
1da177e4
LT		 213};
214
07d3f51f 215enum rtl_register_content {
1da177e4 216 /* InterruptStatusBits */
07d3f51f
FR		 217 SYSErr = 0x8000,
218 PCSTimeout = 0x4000,
219 SWInt = 0x0100,
220 TxDescUnavail = 0x0080,
221 RxFIFOOver = 0x0040,
222 LinkChg = 0x0020,
223 RxOverflow = 0x0010,
224 TxErr = 0x0008,
225 TxOK = 0x0004,
226 RxErr = 0x0002,
227 RxOK = 0x0001,
1da177e4
LT		 228
229 /* RxStatusDesc */
9dccf611
FR		 230 RxFOVF = (1 << 23),
231 RxRWT = (1 << 22),
232 RxRES = (1 << 21),
233 RxRUNT = (1 << 20),
234 RxCRC = (1 << 19),
1da177e4
LT		 235
236 /* ChipCmdBits */
07d3f51f
FR		 237 CmdReset = 0x10,
238 CmdRxEnb = 0x08,
239 CmdTxEnb = 0x04,
240 RxBufEmpty = 0x01,
1da177e4 241
275391a4
FR		 242 /* TXPoll register p.5 */
243 HPQ = 0x80, /* Poll cmd on the high prio queue */
244 NPQ = 0x40, /* Poll cmd on the low prio queue */
245 FSWInt = 0x01, /* Forced software interrupt */
246
1da177e4 247 /* Cfg9346Bits */
07d3f51f
FR		 248 Cfg9346_Lock = 0x00,
249 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 250
251 /* rx_mode_bits */
07d3f51f
FR		 252 AcceptErr = 0x20,
253 AcceptRunt = 0x10,
254 AcceptBroadcast = 0x08,
255 AcceptMulticast = 0x04,
256 AcceptMyPhys = 0x02,
257 AcceptAllPhys = 0x01,
1da177e4
LT		 258
259 /* RxConfigBits */
07d3f51f
FR		 260 RxCfgFIFOShift = 13,
261 RxCfgDMAShift = 8,
1da177e4
LT		 262
263 /* TxConfigBits */
264 TxInterFrameGapShift = 24,
265 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
266
5d06a99f 267 /* Config1 register p.24 */
fbac58fc 268 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 269 PMEnable = (1 << 0), /* Power Management Enable */
270
6dccd16b
FR		 271 /* Config2 register p. 25 */
272 PCI_Clock_66MHz = 0x01,
273 PCI_Clock_33MHz = 0x00,
274
61a4dcc2
FR		 275 /* Config3 register p.25 */
276 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
277 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
278
5d06a99f 279 /* Config5 register p.27 */
61a4dcc2
FR		 280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
1da177e4
LT		 286 /* TBICSR p.28 */
287 TBIReset = 0x80000000,
288 TBILoopback = 0x40000000,
289 TBINwEnable = 0x20000000,
290 TBINwRestart = 0x10000000,
291 TBILinkOk = 0x02000000,
292 TBINwComplete = 0x01000000,
293
294 /* CPlusCmd p.31 */
0e485150 295 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 296 RxVlan = (1 << 6),
297 RxChkSum = (1 << 5),
298 PCIDAC = (1 << 4),
299 PCIMulRW = (1 << 3),
0e485150
FR		 300 INTT_0 = 0x0000, // 8168
301 INTT_1 = 0x0001, // 8168
302 INTT_2 = 0x0002, // 8168
303 INTT_3 = 0x0003, // 8168
1da177e4
LT		 304
305 /* rtl8169_PHYstatus */
07d3f51f
FR		 306 TBI_Enable = 0x80,
307 TxFlowCtrl = 0x40,
308 RxFlowCtrl = 0x20,
309 _1000bpsF = 0x10,
310 _100bps = 0x08,
311 _10bps = 0x04,
312 LinkStatus = 0x02,
313 FullDup = 0x01,
1da177e4 314
1da177e4 315 /* _TBICSRBit */
07d3f51f 316 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 317
318 /* DumpCounterCommand */
07d3f51f 319 CounterDump = 0x8,
1da177e4
LT		 320};
321
07d3f51f 322enum desc_status_bit {
1da177e4
LT		 323 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
324 RingEnd = (1 << 30), /* End of descriptor ring */
325 FirstFrag = (1 << 29), /* First segment of a packet */
326 LastFrag = (1 << 28), /* Final segment of a packet */
327
328 /* Tx private */
329 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
330 MSSShift = 16, /* MSS value position */
331 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
332 IPCS = (1 << 18), /* Calculate IP checksum */
333 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
334 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
335 TxVlanTag = (1 << 17), /* Add VLAN tag */
336
337 /* Rx private */
338 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
339 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
340
341#define RxProtoUDP (PID1)
342#define RxProtoTCP (PID0)
343#define RxProtoIP (PID1 | PID0)
344#define RxProtoMask RxProtoIP
345
346 IPFail = (1 << 16), /* IP checksum failed */
347 UDPFail = (1 << 15), /* UDP/IP checksum failed */
348 TCPFail = (1 << 14), /* TCP/IP checksum failed */
349 RxVlanTag = (1 << 16), /* VLAN tag available */
350};
351
352#define RsvdMask 0x3fffc000
353
354struct TxDesc {
6cccd6e7
REB		 355 __le32 opts1;
356 __le32 opts2;
357 __le64 addr;
1da177e4
LT		 358};
359
360struct RxDesc {
6cccd6e7
REB		 361 __le32 opts1;
362 __le32 opts2;
363 __le64 addr;
1da177e4
LT		 364};
365
366struct ring_info {
367 struct sk_buff *skb;
368 u32 len;
369 u8 __pad[sizeof(void *) - sizeof(u32)];
370};
371
f23e7fda
FR		 372enum features {
373 RTL_FEATURE_WOL = (1 << 0),
fbac58fc 374 RTL_FEATURE_MSI = (1 << 1),
f23e7fda
FR		 375};
376
1da177e4
LT		 377struct rtl8169_private {
378 void __iomem *mmio_addr; /* memory map physical address */
379 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 380 struct net_device *dev;
bea3348e 381 struct napi_struct napi;
1da177e4 382 spinlock_t lock; /* spin lock flag */
b57b7e5a 383 u32 msg_enable;
1da177e4
LT		 384 int chipset;
385 int mac_version;
1da177e4
LT		 386 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
387 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
388 u32 dirty_rx;
389 u32 dirty_tx;
390 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
391 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
392 dma_addr_t TxPhyAddr;
393 dma_addr_t RxPhyAddr;
394 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
395 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 396 unsigned align;
1da177e4
LT		 397 unsigned rx_buf_sz;
398 struct timer_list timer;
399 u16 cp_cmd;
0e485150
FR		 400 u16 intr_event;
401 u16 napi_event;
1da177e4
LT		 402 u16 intr_mask;
403 int phy_auto_nego_reg;
404 int phy_1000_ctrl_reg;
405#ifdef CONFIG_R8169_VLAN
406 struct vlan_group *vlgrp;
407#endif
408 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
409 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
410 void (*phy_reset_enable)(void __iomem *);
07ce4064 411 void (*hw_start)(struct net_device *);
1da177e4
LT		 412 unsigned int (*phy_reset_pending)(void __iomem *);
413 unsigned int (*link_ok)(void __iomem *);
c4028958 414 struct delayed_work task;
f23e7fda 415 unsigned features;
1da177e4
LT		 416};
417
979b6c13 418MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 419MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 420module_param(rx_copybreak, int, 0);
1b7efd58 421MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 422module_param(use_dac, int, 0);
423MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 424module_param_named(debug, debug.msg_enable, int, 0);
425MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 426MODULE_LICENSE("GPL");
427MODULE_VERSION(RTL8169_VERSION);
428
429static int rtl8169_open(struct net_device *dev);
430static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 431static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 432static int rtl8169_init_ring(struct net_device *dev);
07ce4064 433static void rtl_hw_start(struct net_device *dev);
1da177e4 434static int rtl8169_close(struct net_device *dev);
07ce4064 435static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 436static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 437static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 438static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 439 void __iomem *, u32 budget);
4dcb7d33 440static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 441static void rtl8169_down(struct net_device *dev);
99f252b0 442static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 443static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 444
1da177e4 445static const unsigned int rtl8169_rx_config =
5b0384f4 446 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 447
07d3f51f 448static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 449{
450 int i;
451
a6baf3af 452 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 453
2371408c 454 for (i = 20; i > 0; i--) {
07d3f51f
FR		 455 /*
456 * Check if the RTL8169 has completed writing to the specified
457 * MII register.
458 */
5b0384f4 459 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 460 break;
2371408c 461 udelay(25);
1da177e4
LT		 462 }
463}
464
07d3f51f 465static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 466{
467 int i, value = -1;
468
a6baf3af 469 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 470
2371408c 471 for (i = 20; i > 0; i--) {
07d3f51f
FR		 472 /*
473 * Check if the RTL8169 has completed retrieving data from
474 * the specified MII register.
475 */
1da177e4 476 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 477 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 478 break;
479 }
2371408c 480 udelay(25);
1da177e4
LT		 481 }
482 return value;
483}
484
485static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
486{
487 RTL_W16(IntrMask, 0x0000);
488
489 RTL_W16(IntrStatus, 0xffff);
490}
491
492static void rtl8169_asic_down(void __iomem *ioaddr)
493{
494 RTL_W8(ChipCmd, 0x00);
495 rtl8169_irq_mask_and_ack(ioaddr);
496 RTL_R16(CPlusCmd);
497}
498
499static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
500{
501 return RTL_R32(TBICSR) & TBIReset;
502}
503
504static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
505{
64e4bfb4 506 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 507}
508
509static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
510{
511 return RTL_R32(TBICSR) & TBILinkOk;
512}
513
514static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
515{
516 return RTL_R8(PHYstatus) & LinkStatus;
517}
518
519static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
520{
521 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
522}
523
524static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
525{
526 unsigned int val;
527
9e0db8ef
FR		 528 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
529 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 530}
531
532static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 533 struct rtl8169_private *tp,
534 void __iomem *ioaddr)
1da177e4
LT		 535{
536 unsigned long flags;
537
538 spin_lock_irqsave(&tp->lock, flags);
539 if (tp->link_ok(ioaddr)) {
540 netif_carrier_on(dev);
b57b7e5a
SH		 541 if (netif_msg_ifup(tp))
542 printk(KERN_INFO PFX "%s: link up\n", dev->name);
543 } else {
544 if (netif_msg_ifdown(tp))
545 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 546 netif_carrier_off(dev);
b57b7e5a 547 }
1da177e4
LT		 548 spin_unlock_irqrestore(&tp->lock, flags);
549}
550
61a4dcc2
FR		 551static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
552{
553 struct rtl8169_private *tp = netdev_priv(dev);
554 void __iomem *ioaddr = tp->mmio_addr;
555 u8 options;
556
557 wol->wolopts = 0;
558
559#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
560 wol->supported = WAKE_ANY;
561
562 spin_lock_irq(&tp->lock);
563
564 options = RTL_R8(Config1);
565 if (!(options & PMEnable))
566 goto out_unlock;
567
568 options = RTL_R8(Config3);
569 if (options & LinkUp)
570 wol->wolopts |= WAKE_PHY;
571 if (options & MagicPacket)
572 wol->wolopts |= WAKE_MAGIC;
573
574 options = RTL_R8(Config5);
575 if (options & UWF)
576 wol->wolopts |= WAKE_UCAST;
577 if (options & BWF)
5b0384f4 578 wol->wolopts |= WAKE_BCAST;
61a4dcc2 579 if (options & MWF)
5b0384f4 580 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 581
582out_unlock:
583 spin_unlock_irq(&tp->lock);
584}
585
586static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
587{
588 struct rtl8169_private *tp = netdev_priv(dev);
589 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 590 unsigned int i;
61a4dcc2
FR		 591 static struct {
592 u32 opt;
593 u16 reg;
594 u8 mask;
595 } cfg[] = {
596 { WAKE_ANY, Config1, PMEnable },
597 { WAKE_PHY, Config3, LinkUp },
598 { WAKE_MAGIC, Config3, MagicPacket },
599 { WAKE_UCAST, Config5, UWF },
600 { WAKE_BCAST, Config5, BWF },
601 { WAKE_MCAST, Config5, MWF },
602 { WAKE_ANY, Config5, LanWake }
603 };
604
605 spin_lock_irq(&tp->lock);
606
607 RTL_W8(Cfg9346, Cfg9346_Unlock);
608
609 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
610 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
611 if (wol->wolopts & cfg[i].opt)
612 options |= cfg[i].mask;
613 RTL_W8(cfg[i].reg, options);
614 }
615
616 RTL_W8(Cfg9346, Cfg9346_Lock);
617
f23e7fda
FR		 618 if (wol->wolopts)
619 tp->features |= RTL_FEATURE_WOL;
620 else
621 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 622
623 spin_unlock_irq(&tp->lock);
624
625 return 0;
626}
627
1da177e4
LT		 628static void rtl8169_get_drvinfo(struct net_device *dev,
629 struct ethtool_drvinfo *info)
630{
631 struct rtl8169_private *tp = netdev_priv(dev);
632
633 strcpy(info->driver, MODULENAME);
634 strcpy(info->version, RTL8169_VERSION);
635 strcpy(info->bus_info, pci_name(tp->pci_dev));
636}
637
638static int rtl8169_get_regs_len(struct net_device *dev)
639{
640 return R8169_REGS_SIZE;
641}
642
643static int rtl8169_set_speed_tbi(struct net_device *dev,
644 u8 autoneg, u16 speed, u8 duplex)
645{
646 struct rtl8169_private *tp = netdev_priv(dev);
647 void __iomem *ioaddr = tp->mmio_addr;
648 int ret = 0;
649 u32 reg;
650
651 reg = RTL_R32(TBICSR);
652 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
653 (duplex == DUPLEX_FULL)) {
654 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
655 } else if (autoneg == AUTONEG_ENABLE)
656 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
657 else {
b57b7e5a
SH		 658 if (netif_msg_link(tp)) {
659 printk(KERN_WARNING "%s: "
660 "incorrect speed setting refused in TBI mode\n",
661 dev->name);
662 }
1da177e4
LT		 663 ret = -EOPNOTSUPP;
664 }
665
666 return ret;
667}
668
669static int rtl8169_set_speed_xmii(struct net_device *dev,
670 u8 autoneg, u16 speed, u8 duplex)
671{
672 struct rtl8169_private *tp = netdev_priv(dev);
673 void __iomem *ioaddr = tp->mmio_addr;
674 int auto_nego, giga_ctrl;
675
64e4bfb4
FR		 676 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
677 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
678 ADVERTISE_100HALF | ADVERTISE_100FULL);
679 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
680 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 681
682 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 683 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
684 ADVERTISE_100HALF | ADVERTISE_100FULL);
685 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 686 } else {
687 if (speed == SPEED_10)
64e4bfb4 688 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 689 else if (speed == SPEED_100)
64e4bfb4 690 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 691 else if (speed == SPEED_1000)
64e4bfb4 692 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 693
694 if (duplex == DUPLEX_HALF)
64e4bfb4 695 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 696
697 if (duplex == DUPLEX_FULL)
64e4bfb4 698 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 699
700 /* This tweak comes straight from Realtek's driver. */
701 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 702 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
703 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 704 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 705 }
706 }
707
708 /* The 8100e/8101e do Fast Ethernet only. */
709 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
710 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 711 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
712 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 713 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 714 netif_msg_link(tp)) {
715 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
716 dev->name);
717 }
64e4bfb4 718 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 719 }
720
623a1593
FR		 721 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
722
e3cf0cc0
FR		 723 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
724 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 725 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
726 mdio_write(ioaddr, 0x1f, 0x0000);
727 mdio_write(ioaddr, 0x0e, 0x0000);
728 }
729
1da177e4
LT		 730 tp->phy_auto_nego_reg = auto_nego;
731 tp->phy_1000_ctrl_reg = giga_ctrl;
732
64e4bfb4
FR		 733 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
734 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
735 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 736 return 0;
737}
738
739static int rtl8169_set_speed(struct net_device *dev,
740 u8 autoneg, u16 speed, u8 duplex)
741{
742 struct rtl8169_private *tp = netdev_priv(dev);
743 int ret;
744
745 ret = tp->set_speed(dev, autoneg, speed, duplex);
746
64e4bfb4 747 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 748 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
749
750 return ret;
751}
752
753static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
754{
755 struct rtl8169_private *tp = netdev_priv(dev);
756 unsigned long flags;
757 int ret;
758
759 spin_lock_irqsave(&tp->lock, flags);
760 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
761 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 762
1da177e4
LT		 763 return ret;
764}
765
766static u32 rtl8169_get_rx_csum(struct net_device *dev)
767{
768 struct rtl8169_private *tp = netdev_priv(dev);
769
770 return tp->cp_cmd & RxChkSum;
771}
772
773static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
774{
775 struct rtl8169_private *tp = netdev_priv(dev);
776 void __iomem *ioaddr = tp->mmio_addr;
777 unsigned long flags;
778
779 spin_lock_irqsave(&tp->lock, flags);
780
781 if (data)
782 tp->cp_cmd |= RxChkSum;
783 else
784 tp->cp_cmd &= ~RxChkSum;
785
786 RTL_W16(CPlusCmd, tp->cp_cmd);
787 RTL_R16(CPlusCmd);
788
789 spin_unlock_irqrestore(&tp->lock, flags);
790
791 return 0;
792}
793
794#ifdef CONFIG_R8169_VLAN
795
796static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
797 struct sk_buff *skb)
798{
799 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
800 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
801}
802
803static void rtl8169_vlan_rx_register(struct net_device *dev,
804 struct vlan_group *grp)
805{
806 struct rtl8169_private *tp = netdev_priv(dev);
807 void __iomem *ioaddr = tp->mmio_addr;
808 unsigned long flags;
809
810 spin_lock_irqsave(&tp->lock, flags);
811 tp->vlgrp = grp;
812 if (tp->vlgrp)
813 tp->cp_cmd |= RxVlan;
814 else
815 tp->cp_cmd &= ~RxVlan;
816 RTL_W16(CPlusCmd, tp->cp_cmd);
817 RTL_R16(CPlusCmd);
818 spin_unlock_irqrestore(&tp->lock, flags);
819}
820
1da177e4
LT		 821static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
822 struct sk_buff *skb)
823{
824 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 825 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 826 int ret;
827
865c652d
FR		 828 if (vlgrp && (opts2 & RxVlanTag)) {
829 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 830 ret = 0;
831 } else
832 ret = -1;
833 desc->opts2 = 0;
834 return ret;
835}
836
837#else /* !CONFIG_R8169_VLAN */
838
839static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
840 struct sk_buff *skb)
841{
842 return 0;
843}
844
845static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
846 struct sk_buff *skb)
847{
848 return -1;
849}
850
851#endif
852
853static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
854{
855 struct rtl8169_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->mmio_addr;
857 u32 status;
858
859 cmd->supported =
860 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
861 cmd->port = PORT_FIBRE;
862 cmd->transceiver = XCVR_INTERNAL;
863
864 status = RTL_R32(TBICSR);
865 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
866 cmd->autoneg = !!(status & TBINwEnable);
867
868 cmd->speed = SPEED_1000;
869 cmd->duplex = DUPLEX_FULL; /* Always set */
870}
871
872static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
873{
874 struct rtl8169_private *tp = netdev_priv(dev);
875 void __iomem *ioaddr = tp->mmio_addr;
876 u8 status;
877
878 cmd->supported = SUPPORTED_10baseT_Half |
879 SUPPORTED_10baseT_Full |
880 SUPPORTED_100baseT_Half |
881 SUPPORTED_100baseT_Full |
882 SUPPORTED_1000baseT_Full |
883 SUPPORTED_Autoneg |
5b0384f4 884 SUPPORTED_TP;
1da177e4
LT		 885
886 cmd->autoneg = 1;
887 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
888
64e4bfb4 889 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 890 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 891 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 892 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 893 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 894 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 895 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 896 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 897 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 898 cmd->advertising |= ADVERTISED_1000baseT_Full;
899
900 status = RTL_R8(PHYstatus);
901
902 if (status & _1000bpsF)
903 cmd->speed = SPEED_1000;
904 else if (status & _100bps)
905 cmd->speed = SPEED_100;
906 else if (status & _10bps)
907 cmd->speed = SPEED_10;
908
623a1593
FR		 909 if (status & TxFlowCtrl)
910 cmd->advertising |= ADVERTISED_Asym_Pause;
911 if (status & RxFlowCtrl)
912 cmd->advertising |= ADVERTISED_Pause;
913
1da177e4
LT		 914 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
915 DUPLEX_FULL : DUPLEX_HALF;
916}
917
918static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
919{
920 struct rtl8169_private *tp = netdev_priv(dev);
921 unsigned long flags;
922
923 spin_lock_irqsave(&tp->lock, flags);
924
925 tp->get_settings(dev, cmd);
926
927 spin_unlock_irqrestore(&tp->lock, flags);
928 return 0;
929}
930
931static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
932 void *p)
933{
5b0384f4
FR		 934 struct rtl8169_private *tp = netdev_priv(dev);
935 unsigned long flags;
1da177e4 936
5b0384f4
FR		 937 if (regs->len > R8169_REGS_SIZE)
938 regs->len = R8169_REGS_SIZE;
1da177e4 939
5b0384f4
FR		 940 spin_lock_irqsave(&tp->lock, flags);
941 memcpy_fromio(p, tp->mmio_addr, regs->len);
942 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 943}
944
b57b7e5a
SH		 945static u32 rtl8169_get_msglevel(struct net_device *dev)
946{
947 struct rtl8169_private *tp = netdev_priv(dev);
948
949 return tp->msg_enable;
950}
951
952static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
953{
954 struct rtl8169_private *tp = netdev_priv(dev);
955
956 tp->msg_enable = value;
957}
958
d4a3a0fc
SH		 959static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
960 "tx_packets",
961 "rx_packets",
962 "tx_errors",
963 "rx_errors",
964 "rx_missed",
965 "align_errors",
966 "tx_single_collisions",
967 "tx_multi_collisions",
968 "unicast",
969 "broadcast",
970 "multicast",
971 "tx_aborted",
972 "tx_underrun",
973};
974
975struct rtl8169_counters {
b1eab701
AV		 976 __le64 tx_packets;
977 __le64 rx_packets;
978 __le64 tx_errors;
979 __le32 rx_errors;
980 __le16 rx_missed;
981 __le16 align_errors;
982 __le32 tx_one_collision;
983 __le32 tx_multi_collision;
984 __le64 rx_unicast;
985 __le64 rx_broadcast;
986 __le32 rx_multicast;
987 __le16 tx_aborted;
988 __le16 tx_underun;
d4a3a0fc
SH		 989};
990
b9f2c044 991static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 992{
b9f2c044
JG		 993 switch (sset) {
994 case ETH_SS_STATS:
995 return ARRAY_SIZE(rtl8169_gstrings);
996 default:
997 return -EOPNOTSUPP;
998 }
d4a3a0fc
SH		 999}
1000
1001static void rtl8169_get_ethtool_stats(struct net_device *dev,
1002 struct ethtool_stats *stats, u64 *data)
1003{
1004 struct rtl8169_private *tp = netdev_priv(dev);
1005 void __iomem *ioaddr = tp->mmio_addr;
1006 struct rtl8169_counters *counters;
1007 dma_addr_t paddr;
1008 u32 cmd;
1009
1010 ASSERT_RTNL();
1011
1012 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1013 if (!counters)
1014 return;
1015
1016 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1017 cmd = (u64)paddr & DMA_32BIT_MASK;
1018 RTL_W32(CounterAddrLow, cmd);
1019 RTL_W32(CounterAddrLow, cmd | CounterDump);
1020
1021 while (RTL_R32(CounterAddrLow) & CounterDump) {
1022 if (msleep_interruptible(1))
1023 break;
1024 }
1025
1026 RTL_W32(CounterAddrLow, 0);
1027 RTL_W32(CounterAddrHigh, 0);
1028
5b0384f4 1029 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1030 data[1] = le64_to_cpu(counters->rx_packets);
1031 data[2] = le64_to_cpu(counters->tx_errors);
1032 data[3] = le32_to_cpu(counters->rx_errors);
1033 data[4] = le16_to_cpu(counters->rx_missed);
1034 data[5] = le16_to_cpu(counters->align_errors);
1035 data[6] = le32_to_cpu(counters->tx_one_collision);
1036 data[7] = le32_to_cpu(counters->tx_multi_collision);
1037 data[8] = le64_to_cpu(counters->rx_unicast);
1038 data[9] = le64_to_cpu(counters->rx_broadcast);
1039 data[10] = le32_to_cpu(counters->rx_multicast);
1040 data[11] = le16_to_cpu(counters->tx_aborted);
1041 data[12] = le16_to_cpu(counters->tx_underun);
1042
1043 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1044}
1045
1046static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1047{
1048 switch(stringset) {
1049 case ETH_SS_STATS:
1050 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1051 break;
1052 }
1053}
1054
7282d491 1055static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1056 .get_drvinfo = rtl8169_get_drvinfo,
1057 .get_regs_len = rtl8169_get_regs_len,
1058 .get_link = ethtool_op_get_link,
1059 .get_settings = rtl8169_get_settings,
1060 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1061 .get_msglevel = rtl8169_get_msglevel,
1062 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1063 .get_rx_csum = rtl8169_get_rx_csum,
1064 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1065 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1066 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1067 .set_tso = ethtool_op_set_tso,
1068 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1069 .get_wol = rtl8169_get_wol,
1070 .set_wol = rtl8169_set_wol,
d4a3a0fc 1071 .get_strings = rtl8169_get_strings,
b9f2c044 1072 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1073 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1074};
1075
07d3f51f
FR		 1076static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1077 int bitnum, int bitval)
1da177e4
LT		 1078{
1079 int val;
1080
1081 val = mdio_read(ioaddr, reg);
1082 val = (bitval == 1) ?
1083 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1084 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1085}
1086
07d3f51f
FR		 1087static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1088 void __iomem *ioaddr)
1da177e4 1089{
0e485150
FR		 1090 /*
1091 * The driver currently handles the 8168Bf and the 8168Be identically
1092 * but they can be identified more specifically through the test below
1093 * if needed:
1094 *
1095 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1096 *
1097 * Same thing for the 8101Eb and the 8101Ec:
1098 *
1099 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1100 */
1da177e4
LT		 1101 const struct {
1102 u32 mask;
e3cf0cc0 1103 u32 val;
1da177e4
LT		 1104 int mac_version;
1105 } mac_info[] = {
e3cf0cc0
FR		 1106 /* 8168B family. */
1107 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1108 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1109 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1110 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1111
1112 /* 8168B family. */
1113 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1114 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1115 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1116 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1117
1118 /* 8101 family. */
1119 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1120 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1121 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1122 /* FIXME: where did these entries come from ? -- FR */
1123 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1124 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1125
1126 /* 8110 family. */
1127 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1128 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1129 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1130 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1131 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1132 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1133
1134 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1135 }, *p = mac_info;
1136 u32 reg;
1137
e3cf0cc0
FR		 1138 reg = RTL_R32(TxConfig);
1139 while ((reg & p->mask) != p->val)
1da177e4
LT		 1140 p++;
1141 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1142
1143 if (p->mask == 0x00000000) {
1144 struct pci_dev *pdev = tp->pci_dev;
1145
1146 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1147 }
1da177e4
LT		 1148}
1149
1150static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1151{
bcf0bf90 1152 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1153}
1154
867763c1
FR		 1155struct phy_reg {
1156 u16 reg;
1157 u16 val;
1158};
1159
1160static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1161{
1162 while (len-- > 0) {
1163 mdio_write(ioaddr, regs->reg, regs->val);
1164 regs++;
1165 }
1166}
1167
5615d9f1 1168static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1169{
1da177e4
LT		 1170 struct {
1171 u16 regs[5]; /* Beware of bit-sign propagation */
1172 } phy_magic[5] = { {
1173 { 0x0000, //w 4 15 12 0
1174 0x00a1, //w 3 15 0 00a1
1175 0x0008, //w 2 15 0 0008
1176 0x1020, //w 1 15 0 1020
1177 0x1000 } },{ //w 0 15 0 1000
1178 { 0x7000, //w 4 15 12 7
1179 0xff41, //w 3 15 0 ff41
1180 0xde60, //w 2 15 0 de60
1181 0x0140, //w 1 15 0 0140
1182 0x0077 } },{ //w 0 15 0 0077
1183 { 0xa000, //w 4 15 12 a
1184 0xdf01, //w 3 15 0 df01
1185 0xdf20, //w 2 15 0 df20
1186 0xff95, //w 1 15 0 ff95
1187 0xfa00 } },{ //w 0 15 0 fa00
1188 { 0xb000, //w 4 15 12 b
1189 0xff41, //w 3 15 0 ff41
1190 0xde20, //w 2 15 0 de20
1191 0x0140, //w 1 15 0 0140
1192 0x00bb } },{ //w 0 15 0 00bb
1193 { 0xf000, //w 4 15 12 f
1194 0xdf01, //w 3 15 0 df01
1195 0xdf20, //w 2 15 0 df20
1196 0xff95, //w 1 15 0 ff95
1197 0xbf00 } //w 0 15 0 bf00
1198 }
1199 }, *p = phy_magic;
07d3f51f 1200 unsigned int i;
1da177e4 1201
a441d7b6
FR		 1202 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1203 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1204 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1205 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1206
1207 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1208 int val, pos = 4;
1209
1210 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1211 mdio_write(ioaddr, pos, val);
1212 while (--pos >= 0)
1213 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1214 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1215 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1216 }
a441d7b6 1217 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1218}
1219
5615d9f1
FR		 1220static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1221{
a441d7b6
FR		 1222 struct phy_reg phy_reg_init[] = {
1223 { 0x1f, 0x0002 },
1224 { 0x01, 0x90d0 },
1225 { 0x1f, 0x0000 }
1226 };
1227
1228 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1229}
1230
867763c1
FR		 1231static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1232{
1233 struct phy_reg phy_reg_init[] = {
1234 { 0x1f, 0x0000 },
1235 { 0x1d, 0x0f00 },
1236 { 0x1f, 0x0002 },
1237 { 0x0c, 0x1ec8 },
1238 { 0x1f, 0x0000 }
1239 };
1240
1241 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1242}
1243
1244static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1245{
1246 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1247 { 0x1f, 0x0001 },
1248 { 0x12, 0x2300 },
867763c1
FR		 1249 { 0x1f, 0x0002 },
1250 { 0x00, 0x88d4 },
1251 { 0x01, 0x82b1 },
1252 { 0x03, 0x7002 },
1253 { 0x08, 0x9e30 },
1254 { 0x09, 0x01f0 },
1255 { 0x0a, 0x5500 },
1256 { 0x0c, 0x00c8 },
1257 { 0x1f, 0x0003 },
1258 { 0x12, 0xc096 },
1259 { 0x16, 0x000a },
1260 { 0x1f, 0x0000 }
1261 };
1262
1263 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1264}
1265
7da97ec9
FR		 1266static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1267{
1268 struct phy_reg phy_reg_init[] = {
1269 { 0x1f, 0x0000 },
1270 { 0x12, 0x2300 },
1271 { 0x1f, 0x0003 },
1272 { 0x16, 0x0f0a },
1273 { 0x1f, 0x0000 },
1274 { 0x1f, 0x0002 },
1275 { 0x0c, 0x7eb8 },
1276 { 0x1f, 0x0000 }
1277 };
1278
1279 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1280}
1281
5615d9f1
FR		 1282static void rtl_hw_phy_config(struct net_device *dev)
1283{
1284 struct rtl8169_private *tp = netdev_priv(dev);
1285 void __iomem *ioaddr = tp->mmio_addr;
1286
1287 rtl8169_print_mac_version(tp);
1288
1289 switch (tp->mac_version) {
1290 case RTL_GIGA_MAC_VER_01:
1291 break;
1292 case RTL_GIGA_MAC_VER_02:
1293 case RTL_GIGA_MAC_VER_03:
1294 rtl8169s_hw_phy_config(ioaddr);
1295 break;
1296 case RTL_GIGA_MAC_VER_04:
1297 rtl8169sb_hw_phy_config(ioaddr);
1298 break;
867763c1
FR		 1299 case RTL_GIGA_MAC_VER_18:
1300 rtl8168cp_hw_phy_config(ioaddr);
1301 break;
1302 case RTL_GIGA_MAC_VER_19:
1303 rtl8168c_hw_phy_config(ioaddr);
1304 break;
7da97ec9
FR		 1305 case RTL_GIGA_MAC_VER_20:
1306 rtl8168cx_hw_phy_config(ioaddr);
1307 break;
5615d9f1
FR		 1308 default:
1309 break;
1310 }
1311}
1312
1da177e4
LT		 1313static void rtl8169_phy_timer(unsigned long __opaque)
1314{
1315 struct net_device *dev = (struct net_device *)__opaque;
1316 struct rtl8169_private *tp = netdev_priv(dev);
1317 struct timer_list *timer = &tp->timer;
1318 void __iomem *ioaddr = tp->mmio_addr;
1319 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1320
bcf0bf90 1321 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1322
64e4bfb4 1323 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1324 return;
1325
1326 spin_lock_irq(&tp->lock);
1327
1328 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1329 /*
1da177e4
LT		 1330 * A busy loop could burn quite a few cycles on nowadays CPU.
1331 * Let's delay the execution of the timer for a few ticks.
1332 */
1333 timeout = HZ/10;
1334 goto out_mod_timer;
1335 }
1336
1337 if (tp->link_ok(ioaddr))
1338 goto out_unlock;
1339
b57b7e5a
SH		 1340 if (netif_msg_link(tp))
1341 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1342
1343 tp->phy_reset_enable(ioaddr);
1344
1345out_mod_timer:
1346 mod_timer(timer, jiffies + timeout);
1347out_unlock:
1348 spin_unlock_irq(&tp->lock);
1349}
1350
1351static inline void rtl8169_delete_timer(struct net_device *dev)
1352{
1353 struct rtl8169_private *tp = netdev_priv(dev);
1354 struct timer_list *timer = &tp->timer;
1355
e179bb7b 1356 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1357 return;
1358
1359 del_timer_sync(timer);
1360}
1361
1362static inline void rtl8169_request_timer(struct net_device *dev)
1363{
1364 struct rtl8169_private *tp = netdev_priv(dev);
1365 struct timer_list *timer = &tp->timer;
1366
e179bb7b 1367 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1368 return;
1369
2efa53f3 1370 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1371}
1372
1373#ifdef CONFIG_NET_POLL_CONTROLLER
1374/*
1375 * Polling 'interrupt' - used by things like netconsole to send skbs
1376 * without having to re-enable interrupts. It's not called while
1377 * the interrupt routine is executing.
1378 */
1379static void rtl8169_netpoll(struct net_device *dev)
1380{
1381 struct rtl8169_private *tp = netdev_priv(dev);
1382 struct pci_dev *pdev = tp->pci_dev;
1383
1384 disable_irq(pdev->irq);
7d12e780 1385 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1386 enable_irq(pdev->irq);
1387}
1388#endif
1389
1390static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1391 void __iomem *ioaddr)
1392{
1393 iounmap(ioaddr);
1394 pci_release_regions(pdev);
1395 pci_disable_device(pdev);
1396 free_netdev(dev);
1397}
1398
bf793295
FR		 1399static void rtl8169_phy_reset(struct net_device *dev,
1400 struct rtl8169_private *tp)
1401{
1402 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1403 unsigned int i;
bf793295
FR		 1404
1405 tp->phy_reset_enable(ioaddr);
1406 for (i = 0; i < 100; i++) {
1407 if (!tp->phy_reset_pending(ioaddr))
1408 return;
1409 msleep(1);
1410 }
1411 if (netif_msg_link(tp))
1412 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1413}
1414
4ff96fa6
FR		 1415static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1416{
1417 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1418
5615d9f1 1419 rtl_hw_phy_config(dev);
4ff96fa6
FR		 1420
1421 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1422 RTL_W8(0x82, 0x01);
1423
6dccd16b
FR		 1424 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1425
1426 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1427 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1428
bcf0bf90 1429 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1430 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1431 RTL_W8(0x82, 0x01);
1432 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1433 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1434 }
1435
bf793295
FR		 1436 rtl8169_phy_reset(dev, tp);
1437
901dda2b
FR		 1438 /*
1439 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1440 * only 8101. Don't panic.
1441 */
1442 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1443
1444 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1445 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1446}
1447
773d2021
FR		 1448static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1449{
1450 void __iomem *ioaddr = tp->mmio_addr;
1451 u32 high;
1452 u32 low;
1453
1454 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1455 high = addr[4] | (addr[5] << 8);
1456
1457 spin_lock_irq(&tp->lock);
1458
1459 RTL_W8(Cfg9346, Cfg9346_Unlock);
1460 RTL_W32(MAC0, low);
1461 RTL_W32(MAC4, high);
1462 RTL_W8(Cfg9346, Cfg9346_Lock);
1463
1464 spin_unlock_irq(&tp->lock);
1465}
1466
1467static int rtl_set_mac_address(struct net_device *dev, void *p)
1468{
1469 struct rtl8169_private *tp = netdev_priv(dev);
1470 struct sockaddr *addr = p;
1471
1472 if (!is_valid_ether_addr(addr->sa_data))
1473 return -EADDRNOTAVAIL;
1474
1475 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1476
1477 rtl_rar_set(tp, dev->dev_addr);
1478
1479 return 0;
1480}
1481
5f787a1a
FR		 1482static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1483{
1484 struct rtl8169_private *tp = netdev_priv(dev);
1485 struct mii_ioctl_data *data = if_mii(ifr);
1486
1487 if (!netif_running(dev))
1488 return -ENODEV;
1489
1490 switch (cmd) {
1491 case SIOCGMIIPHY:
1492 data->phy_id = 32; /* Internal PHY */
1493 return 0;
1494
1495 case SIOCGMIIREG:
1496 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1497 return 0;
1498
1499 case SIOCSMIIREG:
1500 if (!capable(CAP_NET_ADMIN))
1501 return -EPERM;
1502 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1503 return 0;
1504 }
1505 return -EOPNOTSUPP;
1506}
1507
0e485150
FR		 1508static const struct rtl_cfg_info {
1509 void (*hw_start)(struct net_device *);
1510 unsigned int region;
1511 unsigned int align;
1512 u16 intr_event;
1513 u16 napi_event;
fbac58fc 1514 unsigned msi;
0e485150
FR		 1515} rtl_cfg_infos [] = {
1516 [RTL_CFG_0] = {
1517 .hw_start = rtl_hw_start_8169,
1518 .region = 1,
e9f63f30 1519 .align = 0,
0e485150
FR		 1520 .intr_event = SYSErr | LinkChg | RxOverflow |
1521 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1522 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1523 .msi = 0
0e485150
FR		 1524 },
1525 [RTL_CFG_1] = {
1526 .hw_start = rtl_hw_start_8168,
1527 .region = 2,
1528 .align = 8,
1529 .intr_event = SYSErr | LinkChg | RxOverflow |
1530 TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1531 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1532 .msi = RTL_FEATURE_MSI
0e485150
FR		 1533 },
1534 [RTL_CFG_2] = {
1535 .hw_start = rtl_hw_start_8101,
1536 .region = 2,
1537 .align = 8,
1538 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1539 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1540 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1541 .msi = RTL_FEATURE_MSI
0e485150
FR		 1542 }
1543};
1544
fbac58fc
FR		 1545/* Cfg9346_Unlock assumed. */
1546static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1547 const struct rtl_cfg_info *cfg)
1548{
1549 unsigned msi = 0;
1550 u8 cfg2;
1551
1552 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1553 if (cfg->msi) {
1554 if (pci_enable_msi(pdev)) {
1555 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1556 } else {
1557 cfg2 |= MSIEnable;
1558 msi = RTL_FEATURE_MSI;
1559 }
1560 }
1561 RTL_W8(Config2, cfg2);
1562 return msi;
1563}
1564
1565static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1566{
1567 if (tp->features & RTL_FEATURE_MSI) {
1568 pci_disable_msi(pdev);
1569 tp->features &= ~RTL_FEATURE_MSI;
1570 }
1571}
1572
1da177e4 1573static int __devinit
4ff96fa6 1574rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1575{
0e485150
FR		 1576 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1577 const unsigned int region = cfg->region;
1da177e4 1578 struct rtl8169_private *tp;
4ff96fa6
FR		 1579 struct net_device *dev;
1580 void __iomem *ioaddr;
07d3f51f
FR		 1581 unsigned int i;
1582 int rc;
1da177e4 1583
4ff96fa6
FR		 1584 if (netif_msg_drv(&debug)) {
1585 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1586 MODULENAME, RTL8169_VERSION);
1587 }
1da177e4 1588
1da177e4 1589 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1590 if (!dev) {
b57b7e5a 1591 if (netif_msg_drv(&debug))
9b91cf9d 1592 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1593 rc = -ENOMEM;
1594 goto out;
1da177e4
LT		 1595 }
1596
1da177e4
LT		 1597 SET_NETDEV_DEV(dev, &pdev->dev);
1598 tp = netdev_priv(dev);
c4028958 1599 tp->dev = dev;
21e197f2 1600 tp->pci_dev = pdev;
b57b7e5a 1601 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1602
1603 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1604 rc = pci_enable_device(pdev);
b57b7e5a 1605 if (rc < 0) {
2e8a538d 1606 if (netif_msg_probe(tp))
9b91cf9d 1607 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1608 goto err_out_free_dev_1;
1da177e4
LT		 1609 }
1610
1611 rc = pci_set_mwi(pdev);
1612 if (rc < 0)
4ff96fa6 1613 goto err_out_disable_2;
1da177e4 1614
1da177e4 1615 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1616 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1617 if (netif_msg_probe(tp)) {
9b91cf9d 1618 dev_err(&pdev->dev,
bcf0bf90
FR		 1619 "region #%d not an MMIO resource, aborting\n",
1620 region);
4ff96fa6 1621 }
1da177e4 1622 rc = -ENODEV;
4ff96fa6 1623 goto err_out_mwi_3;
1da177e4 1624 }
4ff96fa6 1625
1da177e4 1626 /* check for weird/broken PCI region reporting */
bcf0bf90 1627 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1628 if (netif_msg_probe(tp)) {
9b91cf9d 1629 dev_err(&pdev->dev,
4ff96fa6
FR		 1630 "Invalid PCI region size(s), aborting\n");
1631 }
1da177e4 1632 rc = -ENODEV;
4ff96fa6 1633 goto err_out_mwi_3;
1da177e4
LT		 1634 }
1635
1636 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1637 if (rc < 0) {
2e8a538d 1638 if (netif_msg_probe(tp))
9b91cf9d 1639 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1640 goto err_out_mwi_3;
1da177e4
LT		 1641 }
1642
1643 tp->cp_cmd = PCIMulRW | RxChkSum;
1644
1645 if ((sizeof(dma_addr_t) > 4) &&
1646 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1647 tp->cp_cmd |= PCIDAC;
1648 dev->features |= NETIF_F_HIGHDMA;
1649 } else {
1650 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1651 if (rc < 0) {
4ff96fa6 1652 if (netif_msg_probe(tp)) {
9b91cf9d 1653 dev_err(&pdev->dev,
4ff96fa6
FR		 1654 "DMA configuration failed.\n");
1655 }
1656 goto err_out_free_res_4;
1da177e4
LT		 1657 }
1658 }
1659
1660 pci_set_master(pdev);
1661
1662 /* ioremap MMIO region */
bcf0bf90 1663 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1664 if (!ioaddr) {
b57b7e5a 1665 if (netif_msg_probe(tp))
9b91cf9d 1666 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1667 rc = -EIO;
4ff96fa6 1668 goto err_out_free_res_4;
1da177e4
LT		 1669 }
1670
1671 /* Unneeded ? Don't mess with Mrs. Murphy. */
1672 rtl8169_irq_mask_and_ack(ioaddr);
1673
1674 /* Soft reset the chip. */
1675 RTL_W8(ChipCmd, CmdReset);
1676
1677 /* Check that the chip has finished the reset. */
07d3f51f 1678 for (i = 0; i < 100; i++) {
1da177e4
LT		 1679 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1680 break;
b518fa8e 1681 msleep_interruptible(1);
1da177e4
LT		 1682 }
1683
1684 /* Identify chip attached to board */
1685 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1686
1687 rtl8169_print_mac_version(tp);
1da177e4 1688
cee60c37 1689 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 1690 if (tp->mac_version == rtl_chip_info[i].mac_version)
1691 break;
1692 }
cee60c37 1693 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 1694 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1695 if (netif_msg_probe(tp)) {
2e8a538d 1696 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1697 "unknown chip version, assuming %s\n",
1698 rtl_chip_info[0].name);
b57b7e5a 1699 }
cee60c37 1700 i = 0;
1da177e4
LT		 1701 }
1702 tp->chipset = i;
1703
5d06a99f
FR		 1704 RTL_W8(Cfg9346, Cfg9346_Unlock);
1705 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1706 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1707 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1708 RTL_W8(Cfg9346, Cfg9346_Lock);
1709
66ec5d4f
FR		 1710 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1711 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 1712 tp->set_speed = rtl8169_set_speed_tbi;
1713 tp->get_settings = rtl8169_gset_tbi;
1714 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1715 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1716 tp->link_ok = rtl8169_tbi_link_ok;
1717
64e4bfb4 1718 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1719 } else {
1720 tp->set_speed = rtl8169_set_speed_xmii;
1721 tp->get_settings = rtl8169_gset_xmii;
1722 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1723 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1724 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1725
1726 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1727 }
1728
1729 /* Get MAC address. FIXME: read EEPROM */
1730 for (i = 0; i < MAC_ADDR_LEN; i++)
1731 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1732 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1733
1734 dev->open = rtl8169_open;
1735 dev->hard_start_xmit = rtl8169_start_xmit;
1736 dev->get_stats = rtl8169_get_stats;
1737 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1738 dev->stop = rtl8169_close;
1739 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1740 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1741 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1742 dev->irq = pdev->irq;
1743 dev->base_addr = (unsigned long) ioaddr;
1744 dev->change_mtu = rtl8169_change_mtu;
773d2021 1745 dev->set_mac_address = rtl_set_mac_address;
1da177e4 1746
bea3348e 1747 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1748
1749#ifdef CONFIG_R8169_VLAN
1750 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1751 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1752#endif
1753
1754#ifdef CONFIG_NET_POLL_CONTROLLER
1755 dev->poll_controller = rtl8169_netpoll;
1756#endif
1757
1758 tp->intr_mask = 0xffff;
1da177e4 1759 tp->mmio_addr = ioaddr;
0e485150
FR		 1760 tp->align = cfg->align;
1761 tp->hw_start = cfg->hw_start;
1762 tp->intr_event = cfg->intr_event;
1763 tp->napi_event = cfg->napi_event;
1da177e4 1764
2efa53f3
FR		 1765 init_timer(&tp->timer);
1766 tp->timer.data = (unsigned long) dev;
1767 tp->timer.function = rtl8169_phy_timer;
1768
1da177e4
LT		 1769 spin_lock_init(&tp->lock);
1770
1771 rc = register_netdev(dev);
4ff96fa6 1772 if (rc < 0)
fbac58fc 1773 goto err_out_msi_5;
1da177e4
LT		 1774
1775 pci_set_drvdata(pdev, dev);
1776
b57b7e5a 1777 if (netif_msg_probe(tp)) {
96b9709c
FR		 1778 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1779
b57b7e5a
SH		 1780 printk(KERN_INFO "%s: %s at 0x%lx, "
1781 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1782 "XID %08x IRQ %d\n",
b57b7e5a 1783 dev->name,
bcf0bf90 1784 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1785 dev->base_addr,
1786 dev->dev_addr[0], dev->dev_addr[1],
1787 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1788 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1789 }
1da177e4 1790
4ff96fa6 1791 rtl8169_init_phy(dev, tp);
1da177e4 1792
4ff96fa6
FR		 1793out:
1794 return rc;
1da177e4 1795
fbac58fc
FR		 1796err_out_msi_5:
1797 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1798 iounmap(ioaddr);
1799err_out_free_res_4:
1800 pci_release_regions(pdev);
1801err_out_mwi_3:
1802 pci_clear_mwi(pdev);
1803err_out_disable_2:
1804 pci_disable_device(pdev);
1805err_out_free_dev_1:
1806 free_netdev(dev);
1807 goto out;
1da177e4
LT		 1808}
1809
07d3f51f 1810static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1811{
1812 struct net_device *dev = pci_get_drvdata(pdev);
1813 struct rtl8169_private *tp = netdev_priv(dev);
1814
eb2a021c
FR		 1815 flush_scheduled_work();
1816
1da177e4 1817 unregister_netdev(dev);
fbac58fc 1818 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1819 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1820 pci_set_drvdata(pdev, NULL);
1821}
1822
1da177e4
LT		 1823static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1824 struct net_device *dev)
1825{
1826 unsigned int mtu = dev->mtu;
1827
1828 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1829}
1830
1831static int rtl8169_open(struct net_device *dev)
1832{
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1835 int retval = -ENOMEM;
1da177e4 1836
1da177e4 1837
99f252b0 1838 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1839
1840 /*
1841 * Rx and Tx desscriptors needs 256 bytes alignment.
1842 * pci_alloc_consistent provides more.
1843 */
1844 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1845 &tp->TxPhyAddr);
1846 if (!tp->TxDescArray)
99f252b0 1847 goto out;
1da177e4
LT		 1848
1849 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1850 &tp->RxPhyAddr);
1851 if (!tp->RxDescArray)
99f252b0 1852 goto err_free_tx_0;
1da177e4
LT		 1853
1854 retval = rtl8169_init_ring(dev);
1855 if (retval < 0)
99f252b0 1856 goto err_free_rx_1;
1da177e4 1857
c4028958 1858 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1859
99f252b0
FR		 1860 smp_mb();
1861
fbac58fc
FR		 1862 retval = request_irq(dev->irq, rtl8169_interrupt,
1863 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1864 dev->name, dev);
1865 if (retval < 0)
1866 goto err_release_ring_2;
1867
bea3348e 1868 napi_enable(&tp->napi);
bea3348e 1869
07ce4064 1870 rtl_hw_start(dev);
1da177e4
LT		 1871
1872 rtl8169_request_timer(dev);
1873
1874 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1875out:
1876 return retval;
1877
99f252b0
FR		 1878err_release_ring_2:
1879 rtl8169_rx_clear(tp);
1880err_free_rx_1:
1da177e4
LT		 1881 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1882 tp->RxPhyAddr);
99f252b0 1883err_free_tx_0:
1da177e4
LT		 1884 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1885 tp->TxPhyAddr);
1da177e4
LT		 1886 goto out;
1887}
1888
1889static void rtl8169_hw_reset(void __iomem *ioaddr)
1890{
1891 /* Disable interrupts */
1892 rtl8169_irq_mask_and_ack(ioaddr);
1893
1894 /* Reset the chipset */
1895 RTL_W8(ChipCmd, CmdReset);
1896
1897 /* PCI commit */
1898 RTL_R8(ChipCmd);
1899}
1900
7f796d83 1901static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1902{
1903 void __iomem *ioaddr = tp->mmio_addr;
1904 u32 cfg = rtl8169_rx_config;
1905
1906 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1907 RTL_W32(RxConfig, cfg);
1908
1909 /* Set DMA burst size and Interframe Gap Time */
1910 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1911 (InterFrameGap << TxInterFrameGapShift));
1912}
1913
07ce4064 1914static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1915{
1916 struct rtl8169_private *tp = netdev_priv(dev);
1917 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1918 unsigned int i;
1da177e4
LT		 1919
1920 /* Soft reset the chip. */
1921 RTL_W8(ChipCmd, CmdReset);
1922
1923 /* Check that the chip has finished the reset. */
07d3f51f 1924 for (i = 0; i < 100; i++) {
1da177e4
LT		 1925 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1926 break;
b518fa8e 1927 msleep_interruptible(1);
1da177e4
LT		 1928 }
1929
07ce4064
FR		 1930 tp->hw_start(dev);
1931
07ce4064
FR		 1932 netif_start_queue(dev);
1933}
1934
1935
7f796d83
FR		 1936static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1937 void __iomem *ioaddr)
1938{
1939 /*
1940 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1941 * register to be written before TxDescAddrLow to work.
1942 * Switching from MMIO to I/O access fixes the issue as well.
1943 */
1944 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1945 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1946 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1947 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1948}
1949
1950static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1951{
1952 u16 cmd;
1953
1954 cmd = RTL_R16(CPlusCmd);
1955 RTL_W16(CPlusCmd, cmd);
1956 return cmd;
1957}
1958
1959static void rtl_set_rx_max_size(void __iomem *ioaddr)
1960{
1961 /* Low hurts. Let's disable the filtering. */
1962 RTL_W16(RxMaxSize, 16383);
1963}
1964
6dccd16b
FR		 1965static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1966{
1967 struct {
1968 u32 mac_version;
1969 u32 clk;
1970 u32 val;
1971 } cfg2_info [] = {
1972 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1973 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1974 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1975 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1976 }, *p = cfg2_info;
1977 unsigned int i;
1978 u32 clk;
1979
1980 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 1981 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 1982 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1983 RTL_W32(0x7c, p->val);
1984 break;
1985 }
1986 }
1987}
1988
07ce4064
FR		 1989static void rtl_hw_start_8169(struct net_device *dev)
1990{
1991 struct rtl8169_private *tp = netdev_priv(dev);
1992 void __iomem *ioaddr = tp->mmio_addr;
1993 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1994
9cb427b6
FR		 1995 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1996 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1997 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1998 }
1999
1da177e4 2000 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2001 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2002 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2003 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2004 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2005 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2006
1da177e4
LT		 2007 RTL_W8(EarlyTxThres, EarlyTxThld);
2008
7f796d83 2009 rtl_set_rx_max_size(ioaddr);
1da177e4 2010
c946b304
FR		 2011 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2012 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2013 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2014 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2015 rtl_set_rx_tx_config_registers(tp);
1da177e4 2016
7f796d83 2017 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2018
bcf0bf90
FR		 2019 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2020 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2021 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2022 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2023 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2024 }
2025
bcf0bf90
FR		 2026 RTL_W16(CPlusCmd, tp->cp_cmd);
2027
6dccd16b
FR		 2028 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2029
1da177e4
LT		 2030 /*
2031 * Undocumented corner. Supposedly:
2032 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2033 */
2034 RTL_W16(IntrMitigate, 0x0000);
2035
7f796d83 2036 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2037
c946b304
FR		 2038 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2039 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2040 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2041 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2042 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2043 rtl_set_rx_tx_config_registers(tp);
2044 }
2045
1da177e4 2046 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2047
2048 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2049 RTL_R8(IntrMask);
1da177e4
LT		 2050
2051 RTL_W32(RxMissed, 0);
2052
07ce4064 2053 rtl_set_rx_mode(dev);
1da177e4
LT		 2054
2055 /* no early-rx interrupts */
2056 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2057
2058 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2059 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2060}
1da177e4 2061
07ce4064
FR		 2062static void rtl_hw_start_8168(struct net_device *dev)
2063{
2dd99530
FR		 2064 struct rtl8169_private *tp = netdev_priv(dev);
2065 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2066 struct pci_dev *pdev = tp->pci_dev;
2067 u8 ctl;
2dd99530
FR		 2068
2069 RTL_W8(Cfg9346, Cfg9346_Unlock);
2070
2071 RTL_W8(EarlyTxThres, EarlyTxThld);
2072
2073 rtl_set_rx_max_size(ioaddr);
2074
0e485150
FR		 2075 rtl_set_rx_tx_config_registers(tp);
2076
2077 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2078
2079 RTL_W16(CPlusCmd, tp->cp_cmd);
2080
0e485150
FR		 2081 /* Tx performance tweak. */
2082 pci_read_config_byte(pdev, 0x69, &ctl);
2083 ctl = (ctl & ~0x70) | 0x50;
2084 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2085
0e485150 2086 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2087
0e485150
FR		 2088 /* Work around for RxFIFO overflow. */
2089 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2090 tp->intr_event |= RxFIFOOver | PCSTimeout;
2091 tp->intr_event &= ~RxOverflow;
2092 }
2093
2094 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2095
2096 RTL_W8(Cfg9346, Cfg9346_Lock);
2097
2098 RTL_R8(IntrMask);
2099
2100 RTL_W32(RxMissed, 0);
2101
2102 rtl_set_rx_mode(dev);
2103
0e485150
FR		 2104 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2105
2dd99530 2106 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2107
0e485150 2108 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2109}
1da177e4 2110
07ce4064
FR		 2111static void rtl_hw_start_8101(struct net_device *dev)
2112{
cdf1a608
FR		 2113 struct rtl8169_private *tp = netdev_priv(dev);
2114 void __iomem *ioaddr = tp->mmio_addr;
2115 struct pci_dev *pdev = tp->pci_dev;
2116
e3cf0cc0
FR		 2117 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2118 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
cdf1a608
FR		 2119 pci_write_config_word(pdev, 0x68, 0x00);
2120 pci_write_config_word(pdev, 0x69, 0x08);
2121 }
2122
2123 RTL_W8(Cfg9346, Cfg9346_Unlock);
2124
2125 RTL_W8(EarlyTxThres, EarlyTxThld);
2126
2127 rtl_set_rx_max_size(ioaddr);
2128
2129 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2130
2131 RTL_W16(CPlusCmd, tp->cp_cmd);
2132
2133 RTL_W16(IntrMitigate, 0x0000);
2134
2135 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2136
2137 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2138 rtl_set_rx_tx_config_registers(tp);
2139
2140 RTL_W8(Cfg9346, Cfg9346_Lock);
2141
2142 RTL_R8(IntrMask);
2143
2144 RTL_W32(RxMissed, 0);
2145
2146 rtl_set_rx_mode(dev);
2147
0e485150
FR		 2148 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2149
cdf1a608 2150 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2151
0e485150 2152 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2153}
2154
2155static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2156{
2157 struct rtl8169_private *tp = netdev_priv(dev);
2158 int ret = 0;
2159
2160 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2161 return -EINVAL;
2162
2163 dev->mtu = new_mtu;
2164
2165 if (!netif_running(dev))
2166 goto out;
2167
2168 rtl8169_down(dev);
2169
2170 rtl8169_set_rxbufsize(tp, dev);
2171
2172 ret = rtl8169_init_ring(dev);
2173 if (ret < 0)
2174 goto out;
2175
bea3348e 2176 napi_enable(&tp->napi);
1da177e4 2177
07ce4064 2178 rtl_hw_start(dev);
1da177e4
LT		 2179
2180 rtl8169_request_timer(dev);
2181
2182out:
2183 return ret;
2184}
2185
2186static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2187{
95e0918d 2188 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2189 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2190}
2191
2192static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2193 struct sk_buff **sk_buff, struct RxDesc *desc)
2194{
2195 struct pci_dev *pdev = tp->pci_dev;
2196
2197 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2198 PCI_DMA_FROMDEVICE);
2199 dev_kfree_skb(*sk_buff);
2200 *sk_buff = NULL;
2201 rtl8169_make_unusable_by_asic(desc);
2202}
2203
2204static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2205{
2206 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2207
2208 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2209}
2210
2211static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2212 u32 rx_buf_sz)
2213{
2214 desc->addr = cpu_to_le64(mapping);
2215 wmb();
2216 rtl8169_mark_to_asic(desc, rx_buf_sz);
2217}
2218
15d31758
SH		 2219static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2220 struct net_device *dev,
2221 struct RxDesc *desc, int rx_buf_sz,
2222 unsigned int align)
1da177e4
LT		 2223{
2224 struct sk_buff *skb;
2225 dma_addr_t mapping;
e9f63f30 2226 unsigned int pad;
1da177e4 2227
e9f63f30
FR		 2228 pad = align ? align : NET_IP_ALIGN;
2229
2230 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2231 if (!skb)
2232 goto err_out;
2233
e9f63f30 2234 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2235
689be439 2236 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2237 PCI_DMA_FROMDEVICE);
2238
2239 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2240out:
15d31758 2241 return skb;
1da177e4
LT		 2242
2243err_out:
1da177e4
LT		 2244 rtl8169_make_unusable_by_asic(desc);
2245 goto out;
2246}
2247
2248static void rtl8169_rx_clear(struct rtl8169_private *tp)
2249{
07d3f51f 2250 unsigned int i;
1da177e4
LT		 2251
2252 for (i = 0; i < NUM_RX_DESC; i++) {
2253 if (tp->Rx_skbuff[i]) {
2254 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2255 tp->RxDescArray + i);
2256 }
2257 }
2258}
2259
2260static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2261 u32 start, u32 end)
2262{
2263 u32 cur;
5b0384f4 2264
4ae47c2d 2265 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2266 struct sk_buff *skb;
2267 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2268
4ae47c2d
FR		 2269 WARN_ON((s32)(end - cur) < 0);
2270
1da177e4
LT		 2271 if (tp->Rx_skbuff[i])
2272 continue;
bcf0bf90 2273
15d31758
SH		 2274 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2275 tp->RxDescArray + i,
2276 tp->rx_buf_sz, tp->align);
2277 if (!skb)
1da177e4 2278 break;
15d31758
SH		 2279
2280 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2281 }
2282 return cur - start;
2283}
2284
2285static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2286{
2287 desc->opts1 |= cpu_to_le32(RingEnd);
2288}
2289
2290static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2291{
2292 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2293}
2294
2295static int rtl8169_init_ring(struct net_device *dev)
2296{
2297 struct rtl8169_private *tp = netdev_priv(dev);
2298
2299 rtl8169_init_ring_indexes(tp);
2300
2301 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2302 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2303
2304 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2305 goto err_out;
2306
2307 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2308
2309 return 0;
2310
2311err_out:
2312 rtl8169_rx_clear(tp);
2313 return -ENOMEM;
2314}
2315
2316static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2317 struct TxDesc *desc)
2318{
2319 unsigned int len = tx_skb->len;
2320
2321 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2322 desc->opts1 = 0x00;
2323 desc->opts2 = 0x00;
2324 desc->addr = 0x00;
2325 tx_skb->len = 0;
2326}
2327
2328static void rtl8169_tx_clear(struct rtl8169_private *tp)
2329{
2330 unsigned int i;
2331
2332 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2333 unsigned int entry = i % NUM_TX_DESC;
2334 struct ring_info *tx_skb = tp->tx_skb + entry;
2335 unsigned int len = tx_skb->len;
2336
2337 if (len) {
2338 struct sk_buff *skb = tx_skb->skb;
2339
2340 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2341 tp->TxDescArray + entry);
2342 if (skb) {
2343 dev_kfree_skb(skb);
2344 tx_skb->skb = NULL;
2345 }
cebf8cc7 2346 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2347 }
2348 }
2349 tp->cur_tx = tp->dirty_tx = 0;
2350}
2351
c4028958 2352static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2353{
2354 struct rtl8169_private *tp = netdev_priv(dev);
2355
c4028958 2356 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2357 schedule_delayed_work(&tp->task, 4);
2358}
2359
2360static void rtl8169_wait_for_quiescence(struct net_device *dev)
2361{
2362 struct rtl8169_private *tp = netdev_priv(dev);
2363 void __iomem *ioaddr = tp->mmio_addr;
2364
2365 synchronize_irq(dev->irq);
2366
2367 /* Wait for any pending NAPI task to complete */
bea3348e 2368 napi_disable(&tp->napi);
1da177e4
LT		 2369
2370 rtl8169_irq_mask_and_ack(ioaddr);
2371
d1d08d12
DM		 2372 tp->intr_mask = 0xffff;
2373 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2374 napi_enable(&tp->napi);
1da177e4
LT		 2375}
2376
c4028958 2377static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2378{
c4028958
DH		 2379 struct rtl8169_private *tp =
2380 container_of(work, struct rtl8169_private, task.work);
2381 struct net_device *dev = tp->dev;
1da177e4
LT		 2382 int ret;
2383
eb2a021c
FR		 2384 rtnl_lock();
2385
2386 if (!netif_running(dev))
2387 goto out_unlock;
2388
2389 rtl8169_wait_for_quiescence(dev);
2390 rtl8169_close(dev);
1da177e4
LT		 2391
2392 ret = rtl8169_open(dev);
2393 if (unlikely(ret < 0)) {
07d3f51f 2394 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2395 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2396 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2397 }
2398 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2399 }
eb2a021c
FR		 2400
2401out_unlock:
2402 rtnl_unlock();
1da177e4
LT		 2403}
2404
c4028958 2405static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2406{
c4028958
DH		 2407 struct rtl8169_private *tp =
2408 container_of(work, struct rtl8169_private, task.work);
2409 struct net_device *dev = tp->dev;
1da177e4 2410
eb2a021c
FR		 2411 rtnl_lock();
2412
1da177e4 2413 if (!netif_running(dev))
eb2a021c 2414 goto out_unlock;
1da177e4
LT		 2415
2416 rtl8169_wait_for_quiescence(dev);
2417
bea3348e 2418 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2419 rtl8169_tx_clear(tp);
2420
2421 if (tp->dirty_rx == tp->cur_rx) {
2422 rtl8169_init_ring_indexes(tp);
07ce4064 2423 rtl_hw_start(dev);
1da177e4 2424 netif_wake_queue(dev);
cebf8cc7 2425 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2426 } else {
07d3f51f 2427 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2428 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2429 dev->name);
1da177e4
LT		 2430 }
2431 rtl8169_schedule_work(dev, rtl8169_reset_task);
2432 }
eb2a021c
FR		 2433
2434out_unlock:
2435 rtnl_unlock();
1da177e4
LT		 2436}
2437
2438static void rtl8169_tx_timeout(struct net_device *dev)
2439{
2440 struct rtl8169_private *tp = netdev_priv(dev);
2441
2442 rtl8169_hw_reset(tp->mmio_addr);
2443
2444 /* Let's wait a bit while any (async) irq lands on */
2445 rtl8169_schedule_work(dev, rtl8169_reset_task);
2446}
2447
2448static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2449 u32 opts1)
2450{
2451 struct skb_shared_info *info = skb_shinfo(skb);
2452 unsigned int cur_frag, entry;
a6343afb 2453 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2454
2455 entry = tp->cur_tx;
2456 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2457 skb_frag_t *frag = info->frags + cur_frag;
2458 dma_addr_t mapping;
2459 u32 status, len;
2460 void *addr;
2461
2462 entry = (entry + 1) % NUM_TX_DESC;
2463
2464 txd = tp->TxDescArray + entry;
2465 len = frag->size;
2466 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2467 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2468
2469 /* anti gcc 2.95.3 bugware (sic) */
2470 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2471
2472 txd->opts1 = cpu_to_le32(status);
2473 txd->addr = cpu_to_le64(mapping);
2474
2475 tp->tx_skb[entry].len = len;
2476 }
2477
2478 if (cur_frag) {
2479 tp->tx_skb[entry].skb = skb;
2480 txd->opts1 |= cpu_to_le32(LastFrag);
2481 }
2482
2483 return cur_frag;
2484}
2485
2486static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2487{
2488 if (dev->features & NETIF_F_TSO) {
7967168c 2489 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2490
2491 if (mss)
2492 return LargeSend | ((mss & MSSMask) << MSSShift);
2493 }
84fa7933 2494 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2495 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2496
2497 if (ip->protocol == IPPROTO_TCP)
2498 return IPCS | TCPCS;
2499 else if (ip->protocol == IPPROTO_UDP)
2500 return IPCS | UDPCS;
2501 WARN_ON(1); /* we need a WARN() */
2502 }
2503 return 0;
2504}
2505
2506static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2507{
2508 struct rtl8169_private *tp = netdev_priv(dev);
2509 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2510 struct TxDesc *txd = tp->TxDescArray + entry;
2511 void __iomem *ioaddr = tp->mmio_addr;
2512 dma_addr_t mapping;
2513 u32 status, len;
2514 u32 opts1;
188f4af0 2515 int ret = NETDEV_TX_OK;
5b0384f4 2516
1da177e4 2517 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2518 if (netif_msg_drv(tp)) {
2519 printk(KERN_ERR
2520 "%s: BUG! Tx Ring full when queue awake!\n",
2521 dev->name);
2522 }
1da177e4
LT		 2523 goto err_stop;
2524 }
2525
2526 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2527 goto err_stop;
2528
2529 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2530
2531 frags = rtl8169_xmit_frags(tp, skb, opts1);
2532 if (frags) {
2533 len = skb_headlen(skb);
2534 opts1 |= FirstFrag;
2535 } else {
2536 len = skb->len;
2537
2538 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2539 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2540 goto err_update_stats;
2541 len = ETH_ZLEN;
2542 }
2543
2544 opts1 |= FirstFrag | LastFrag;
2545 tp->tx_skb[entry].skb = skb;
2546 }
2547
2548 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2549
2550 tp->tx_skb[entry].len = len;
2551 txd->addr = cpu_to_le64(mapping);
2552 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2553
2554 wmb();
2555
2556 /* anti gcc 2.95.3 bugware (sic) */
2557 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2558 txd->opts1 = cpu_to_le32(status);
2559
2560 dev->trans_start = jiffies;
2561
2562 tp->cur_tx += frags + 1;
2563
2564 smp_wmb();
2565
275391a4 2566 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2567
2568 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2569 netif_stop_queue(dev);
2570 smp_rmb();
2571 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2572 netif_wake_queue(dev);
2573 }
2574
2575out:
2576 return ret;
2577
2578err_stop:
2579 netif_stop_queue(dev);
188f4af0 2580 ret = NETDEV_TX_BUSY;
1da177e4 2581err_update_stats:
cebf8cc7 2582 dev->stats.tx_dropped++;
1da177e4
LT		 2583 goto out;
2584}
2585
2586static void rtl8169_pcierr_interrupt(struct net_device *dev)
2587{
2588 struct rtl8169_private *tp = netdev_priv(dev);
2589 struct pci_dev *pdev = tp->pci_dev;
2590 void __iomem *ioaddr = tp->mmio_addr;
2591 u16 pci_status, pci_cmd;
2592
2593 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2594 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2595
b57b7e5a
SH		 2596 if (netif_msg_intr(tp)) {
2597 printk(KERN_ERR
2598 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2599 dev->name, pci_cmd, pci_status);
2600 }
1da177e4
LT		 2601
2602 /*
2603 * The recovery sequence below admits a very elaborated explanation:
2604 * - it seems to work;
d03902b8
FR		 2605 * - I did not see what else could be done;
2606 * - it makes iop3xx happy.
1da177e4
LT		 2607 *
2608 * Feel free to adjust to your needs.
2609 */
a27993f3 2610 if (pdev->broken_parity_status)
d03902b8
FR		 2611 pci_cmd &= ~PCI_COMMAND_PARITY;
2612 else
2613 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2614
2615 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2616
2617 pci_write_config_word(pdev, PCI_STATUS,
2618 pci_status & (PCI_STATUS_DETECTED_PARITY |
2619 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2620 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2621
2622 /* The infamous DAC f*ckup only happens at boot time */
2623 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2624 if (netif_msg_intr(tp))
2625 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2626 tp->cp_cmd &= ~PCIDAC;
2627 RTL_W16(CPlusCmd, tp->cp_cmd);
2628 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2629 }
2630
2631 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2632
2633 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2634}
2635
07d3f51f
FR		 2636static void rtl8169_tx_interrupt(struct net_device *dev,
2637 struct rtl8169_private *tp,
2638 void __iomem *ioaddr)
1da177e4
LT		 2639{
2640 unsigned int dirty_tx, tx_left;
2641
1da177e4
LT		 2642 dirty_tx = tp->dirty_tx;
2643 smp_rmb();
2644 tx_left = tp->cur_tx - dirty_tx;
2645
2646 while (tx_left > 0) {
2647 unsigned int entry = dirty_tx % NUM_TX_DESC;
2648 struct ring_info *tx_skb = tp->tx_skb + entry;
2649 u32 len = tx_skb->len;
2650 u32 status;
2651
2652 rmb();
2653 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2654 if (status & DescOwn)
2655 break;
2656
cebf8cc7
FR		 2657 dev->stats.tx_bytes += len;
2658 dev->stats.tx_packets++;
1da177e4
LT		 2659
2660 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2661
2662 if (status & LastFrag) {
2663 dev_kfree_skb_irq(tx_skb->skb);
2664 tx_skb->skb = NULL;
2665 }
2666 dirty_tx++;
2667 tx_left--;
2668 }
2669
2670 if (tp->dirty_tx != dirty_tx) {
2671 tp->dirty_tx = dirty_tx;
2672 smp_wmb();
2673 if (netif_queue_stopped(dev) &&
2674 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2675 netif_wake_queue(dev);
2676 }
d78ae2dc
FR		 2677 /*
2678 * 8168 hack: TxPoll requests are lost when the Tx packets are
2679 * too close. Let's kick an extra TxPoll request when a burst
2680 * of start_xmit activity is detected (if it is not detected,
2681 * it is slow enough). -- FR
2682 */
2683 smp_rmb();
2684 if (tp->cur_tx != dirty_tx)
2685 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2686 }
2687}
2688
126fa4b9
FR		 2689static inline int rtl8169_fragmented_frame(u32 status)
2690{
2691 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2692}
2693
1da177e4
LT		 2694static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2695{
2696 u32 opts1 = le32_to_cpu(desc->opts1);
2697 u32 status = opts1 & RxProtoMask;
2698
2699 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2700 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2701 ((status == RxProtoIP) && !(opts1 & IPFail)))
2702 skb->ip_summed = CHECKSUM_UNNECESSARY;
2703 else
2704 skb->ip_summed = CHECKSUM_NONE;
2705}
2706
07d3f51f
FR		 2707static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2708 struct rtl8169_private *tp, int pkt_size,
2709 dma_addr_t addr)
1da177e4 2710{
b449655f
SH		 2711 struct sk_buff *skb;
2712 bool done = false;
1da177e4 2713
b449655f
SH		 2714 if (pkt_size >= rx_copybreak)
2715 goto out;
1da177e4 2716
07d3f51f 2717 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2718 if (!skb)
2719 goto out;
2720
07d3f51f
FR		 2721 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2722 PCI_DMA_FROMDEVICE);
86402234 2723 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2724 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2725 *sk_buff = skb;
2726 done = true;
2727out:
2728 return done;
1da177e4
LT		 2729}
2730
07d3f51f
FR		 2731static int rtl8169_rx_interrupt(struct net_device *dev,
2732 struct rtl8169_private *tp,
bea3348e 2733 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2734{
2735 unsigned int cur_rx, rx_left;
2736 unsigned int delta, count;
2737
1da177e4
LT		 2738 cur_rx = tp->cur_rx;
2739 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 2740 rx_left = min(rx_left, budget);
1da177e4 2741
4dcb7d33 2742 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2743 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2744 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2745 u32 status;
2746
2747 rmb();
126fa4b9 2748 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2749
2750 if (status & DescOwn)
2751 break;
4dcb7d33 2752 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2753 if (netif_msg_rx_err(tp)) {
2754 printk(KERN_INFO
2755 "%s: Rx ERROR. status = %08x\n",
2756 dev->name, status);
2757 }
cebf8cc7 2758 dev->stats.rx_errors++;
1da177e4 2759 if (status & (RxRWT | RxRUNT))
cebf8cc7 2760 dev->stats.rx_length_errors++;
1da177e4 2761 if (status & RxCRC)
cebf8cc7 2762 dev->stats.rx_crc_errors++;
9dccf611
FR		 2763 if (status & RxFOVF) {
2764 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2765 dev->stats.rx_fifo_errors++;
9dccf611 2766 }
126fa4b9 2767 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2768 } else {
1da177e4 2769 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2770 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2771 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2772 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2773
126fa4b9
FR		 2774 /*
2775 * The driver does not support incoming fragmented
2776 * frames. They are seen as a symptom of over-mtu
2777 * sized frames.
2778 */
2779 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2780 dev->stats.rx_dropped++;
2781 dev->stats.rx_length_errors++;
126fa4b9 2782 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2783 continue;
126fa4b9
FR		 2784 }
2785
1da177e4 2786 rtl8169_rx_csum(skb, desc);
bcf0bf90 2787
07d3f51f 2788 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2789 pci_dma_sync_single_for_device(pdev, addr,
2790 pkt_size, PCI_DMA_FROMDEVICE);
2791 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2792 } else {
2793 pci_unmap_single(pdev, addr, pkt_size,
2794 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2795 tp->Rx_skbuff[entry] = NULL;
2796 }
2797
1da177e4
LT		 2798 skb_put(skb, pkt_size);
2799 skb->protocol = eth_type_trans(skb, dev);
2800
2801 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 2802 netif_receive_skb(skb);
1da177e4
LT		 2803
2804 dev->last_rx = jiffies;
cebf8cc7
FR		 2805 dev->stats.rx_bytes += pkt_size;
2806 dev->stats.rx_packets++;
1da177e4 2807 }
6dccd16b
FR		 2808
2809 /* Work around for AMD plateform. */
95e0918d 2810 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 2811 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2812 desc->opts2 = 0;
2813 cur_rx++;
2814 }
1da177e4
LT		 2815 }
2816
2817 count = cur_rx - tp->cur_rx;
2818 tp->cur_rx = cur_rx;
2819
2820 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2821 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2822 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2823 tp->dirty_rx += delta;
2824
2825 /*
2826 * FIXME: until there is periodic timer to try and refill the ring,
2827 * a temporary shortage may definitely kill the Rx process.
2828 * - disable the asic to try and avoid an overflow and kick it again
2829 * after refill ?
2830 * - how do others driver handle this condition (Uh oh...).
2831 */
b57b7e5a 2832 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2833 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2834
2835 return count;
2836}
2837
07d3f51f 2838static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2839{
07d3f51f 2840 struct net_device *dev = dev_instance;
1da177e4 2841 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 2842 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 2843 int handled = 0;
865c652d 2844 int status;
1da177e4 2845
865c652d 2846 status = RTL_R16(IntrStatus);
1da177e4 2847
865c652d
FR		 2848 /* hotplug/major error/no more work/shared irq */
2849 if ((status == 0xffff) || !status)
2850 goto out;
1da177e4 2851
865c652d 2852 handled = 1;
1da177e4 2853
865c652d
FR		 2854 if (unlikely(!netif_running(dev))) {
2855 rtl8169_asic_down(ioaddr);
2856 goto out;
2857 }
1da177e4 2858
865c652d
FR		 2859 status &= tp->intr_mask;
2860 RTL_W16(IntrStatus,
2861 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 2862
865c652d
FR		 2863 if (!(status & tp->intr_event))
2864 goto out;
0e485150 2865
865c652d
FR		 2866 /* Work around for rx fifo overflow */
2867 if (unlikely(status & RxFIFOOver) &&
2868 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2869 netif_stop_queue(dev);
2870 rtl8169_tx_timeout(dev);
2871 goto out;
2872 }
1da177e4 2873
865c652d
FR		 2874 if (unlikely(status & SYSErr)) {
2875 rtl8169_pcierr_interrupt(dev);
2876 goto out;
2877 }
1da177e4 2878
865c652d
FR		 2879 if (status & LinkChg)
2880 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 2881
865c652d
FR		 2882 if (status & tp->napi_event) {
2883 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2884 tp->intr_mask = ~tp->napi_event;
313b0305 2885
bea3348e
SH		 2886 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2887 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 2888 else if (netif_msg_intr(tp)) {
2889 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2890 dev->name, status);
b57b7e5a 2891 }
1da177e4
LT		 2892 }
2893out:
2894 return IRQ_RETVAL(handled);
2895}
2896
bea3348e 2897static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2898{
bea3348e
SH		 2899 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2900 struct net_device *dev = tp->dev;
1da177e4 2901 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2902 int work_done;
1da177e4 2903
bea3348e 2904 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2905 rtl8169_tx_interrupt(dev, tp, ioaddr);
2906
bea3348e
SH		 2907 if (work_done < budget) {
2908 netif_rx_complete(dev, napi);
1da177e4
LT		 2909 tp->intr_mask = 0xffff;
2910 /*
2911 * 20040426: the barrier is not strictly required but the
2912 * behavior of the irq handler could be less predictable
2913 * without it. Btw, the lack of flush for the posted pci
2914 * write is safe - FR
2915 */
2916 smp_wmb();
0e485150 2917 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2918 }
2919
bea3348e 2920 return work_done;
1da177e4 2921}
1da177e4
LT		 2922
2923static void rtl8169_down(struct net_device *dev)
2924{
2925 struct rtl8169_private *tp = netdev_priv(dev);
2926 void __iomem *ioaddr = tp->mmio_addr;
733b736c 2927 unsigned int intrmask;
1da177e4
LT		 2928
2929 rtl8169_delete_timer(dev);
2930
2931 netif_stop_queue(dev);
2932
93dd79e8 2933 napi_disable(&tp->napi);
93dd79e8 2934
1da177e4
LT		 2935core_down:
2936 spin_lock_irq(&tp->lock);
2937
2938 rtl8169_asic_down(ioaddr);
2939
2940 /* Update the error counts. */
cebf8cc7 2941 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 2942 RTL_W32(RxMissed, 0);
2943
2944 spin_unlock_irq(&tp->lock);
2945
2946 synchronize_irq(dev->irq);
2947
1da177e4 2948 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2949 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2950
2951 /*
2952 * And now for the 50k$ question: are IRQ disabled or not ?
2953 *
2954 * Two paths lead here:
2955 * 1) dev->close
2956 * -> netif_running() is available to sync the current code and the
2957 * IRQ handler. See rtl8169_interrupt for details.
2958 * 2) dev->change_mtu
2959 * -> rtl8169_poll can not be issued again and re-enable the
2960 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2961 *
2962 * No loop if hotpluged or major error (0xffff).
1da177e4 2963 */
733b736c
AP		 2964 intrmask = RTL_R16(IntrMask);
2965 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2966 goto core_down;
2967
2968 rtl8169_tx_clear(tp);
2969
2970 rtl8169_rx_clear(tp);
2971}
2972
2973static int rtl8169_close(struct net_device *dev)
2974{
2975 struct rtl8169_private *tp = netdev_priv(dev);
2976 struct pci_dev *pdev = tp->pci_dev;
2977
2978 rtl8169_down(dev);
2979
2980 free_irq(dev->irq, dev);
2981
1da177e4
LT		 2982 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2983 tp->RxPhyAddr);
2984 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2985 tp->TxPhyAddr);
2986 tp->TxDescArray = NULL;
2987 tp->RxDescArray = NULL;
2988
2989 return 0;
2990}
2991
07ce4064 2992static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2993{
2994 struct rtl8169_private *tp = netdev_priv(dev);
2995 void __iomem *ioaddr = tp->mmio_addr;
2996 unsigned long flags;
2997 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2998 int rx_mode;
1da177e4
LT		 2999 u32 tmp = 0;
3000
3001 if (dev->flags & IFF_PROMISC) {
3002 /* Unconditionally log net taps. */
b57b7e5a
SH		 3003 if (netif_msg_link(tp)) {
3004 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3005 dev->name);
3006 }
1da177e4
LT		 3007 rx_mode =
3008 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3009 AcceptAllPhys;
3010 mc_filter[1] = mc_filter[0] = 0xffffffff;
3011 } else if ((dev->mc_count > multicast_filter_limit)
3012 || (dev->flags & IFF_ALLMULTI)) {
3013 /* Too many to filter perfectly -- accept all multicasts. */
3014 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3015 mc_filter[1] = mc_filter[0] = 0xffffffff;
3016 } else {
3017 struct dev_mc_list *mclist;
07d3f51f
FR		 3018 unsigned int i;
3019
1da177e4
LT		 3020 rx_mode = AcceptBroadcast | AcceptMyPhys;
3021 mc_filter[1] = mc_filter[0] = 0;
3022 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3023 i++, mclist = mclist->next) {
3024 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3025 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3026 rx_mode |= AcceptMulticast;
3027 }
3028 }
3029
3030 spin_lock_irqsave(&tp->lock, flags);
3031
3032 tmp = rtl8169_rx_config | rx_mode |
3033 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3034
bcf0bf90
FR		 3035 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3036 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3037 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3038 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 3039 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3040 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3041 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
1087f4f4
FR		 3042 u32 data = mc_filter[0];
3043
3044 mc_filter[0] = swab32(mc_filter[1]);
3045 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3046 }
3047
1da177e4
LT		 3048 RTL_W32(MAR0 + 0, mc_filter[0]);
3049 RTL_W32(MAR0 + 4, mc_filter[1]);
3050
57a9f236
FR		 3051 RTL_W32(RxConfig, tmp);
3052
1da177e4
LT		 3053 spin_unlock_irqrestore(&tp->lock, flags);
3054}
3055
3056/**
3057 * rtl8169_get_stats - Get rtl8169 read/write statistics
3058 * @dev: The Ethernet Device to get statistics for
3059 *
3060 * Get TX/RX statistics for rtl8169
3061 */
3062static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3063{
3064 struct rtl8169_private *tp = netdev_priv(dev);
3065 void __iomem *ioaddr = tp->mmio_addr;
3066 unsigned long flags;
3067
3068 if (netif_running(dev)) {
3069 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3070 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3071 RTL_W32(RxMissed, 0);
3072 spin_unlock_irqrestore(&tp->lock, flags);
3073 }
5b0384f4 3074
cebf8cc7 3075 return &dev->stats;
1da177e4
LT		 3076}
3077
5d06a99f
FR		 3078#ifdef CONFIG_PM
3079
3080static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3081{
3082 struct net_device *dev = pci_get_drvdata(pdev);
3083 struct rtl8169_private *tp = netdev_priv(dev);
3084 void __iomem *ioaddr = tp->mmio_addr;
3085
3086 if (!netif_running(dev))
1371fa6d 3087 goto out_pci_suspend;
5d06a99f
FR		 3088
3089 netif_device_detach(dev);
3090 netif_stop_queue(dev);
3091
3092 spin_lock_irq(&tp->lock);
3093
3094 rtl8169_asic_down(ioaddr);
3095
cebf8cc7 3096 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3097 RTL_W32(RxMissed, 0);
3098
3099 spin_unlock_irq(&tp->lock);
3100
1371fa6d 3101out_pci_suspend:
5d06a99f 3102 pci_save_state(pdev);
f23e7fda
FR		 3103 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3104 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3105 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3106
5d06a99f
FR		 3107 return 0;
3108}
3109
3110static int rtl8169_resume(struct pci_dev *pdev)
3111{
3112 struct net_device *dev = pci_get_drvdata(pdev);
3113
1371fa6d
FR		 3114 pci_set_power_state(pdev, PCI_D0);
3115 pci_restore_state(pdev);
3116 pci_enable_wake(pdev, PCI_D0, 0);
3117
5d06a99f
FR		 3118 if (!netif_running(dev))
3119 goto out;
3120
3121 netif_device_attach(dev);
3122
5d06a99f
FR		 3123 rtl8169_schedule_work(dev, rtl8169_reset_task);
3124out:
3125 return 0;
3126}
3127
3128#endif /* CONFIG_PM */
3129
1da177e4
LT		 3130static struct pci_driver rtl8169_pci_driver = {
3131 .name = MODULENAME,
3132 .id_table = rtl8169_pci_tbl,
3133 .probe = rtl8169_init_one,
3134 .remove = __devexit_p(rtl8169_remove_one),
3135#ifdef CONFIG_PM
3136 .suspend = rtl8169_suspend,
3137 .resume = rtl8169_resume,
3138#endif
3139};
3140
07d3f51f 3141static int __init rtl8169_init_module(void)
1da177e4 3142{
29917620 3143 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3144}
3145
07d3f51f 3146static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3147{
3148 pci_unregister_driver(&rtl8169_pci_driver);
3149}
3150
3151module_init(rtl8169_init_module);
3152module_exit(rtl8169_cleanup_module);
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