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Fix a potential NULL pointer dereference in mace_interrupt() in drivers/net/pcmcia...
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
1da177e4
LT		 47#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59#ifdef CONFIG_R8169_NAPI
60#define rtl8169_rx_skb netif_receive_skb
0b50f81d 61#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 62#define rtl8169_rx_quota(count, quota) min(count, quota)
63#else
64#define rtl8169_rx_skb netif_rx
0b50f81d 65#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 66#define rtl8169_rx_quota(count, quota) count
67#endif
68
1da177e4 69/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 70static const int max_interrupt_work = 20;
1da177e4
LT		 71
72/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 74static const int multicast_filter_limit = 32;
1da177e4
LT		 75
76/* MAC address length */
77#define MAC_ADDR_LEN 6
78
79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 83#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87#define R8169_REGS_SIZE 256
88#define R8169_NAPI_WEIGHT 64
89#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91#define RX_BUF_SIZE 1536 /* Rx Buffer size */
92#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94
95#define RTL8169_TX_TIMEOUT (6*HZ)
96#define RTL8169_PHY_TIMEOUT (10*HZ)
97
98/* write/read MMIO register */
99#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb (ioaddr + (reg))
103#define RTL_R16(reg) readw (ioaddr + (reg))
104#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
105
106enum mac_version {
ba6eb6ee
FR		 107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 118};
119
120enum phy_version {
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
127};
128
1da177e4
LT		 129#define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131
3c6bee1d 132static const struct {
1da177e4
LT		 133 const char *name;
134 u8 mac_version;
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136} rtl_chip_info[] = {
ba6eb6ee
FR		 137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 148};
149#undef _R
150
bcf0bf90
FR		 151enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155};
156
07ce4064
FR		 157static void rtl_hw_start_8169(struct net_device *);
158static void rtl_hw_start_8168(struct net_device *);
159static void rtl_hw_start_8101(struct net_device *);
160
1da177e4 161static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 172 {0,},
173};
174
175MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176
177static int rx_copybreak = 200;
178static int use_dac;
b57b7e5a
SH		 179static struct {
180 u32 msg_enable;
181} debug = { -1 };
1da177e4 182
07d3f51f
FR		 183enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
773d2021 185 MAC4 = 4,
07d3f51f
FR		 186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
193 FLASH = 0x30,
194 ERSR = 0x36,
195 ChipCmd = 0x37,
196 TxPoll = 0x38,
197 IntrMask = 0x3c,
198 IntrStatus = 0x3e,
199 TxConfig = 0x40,
200 RxConfig = 0x44,
201 RxMissed = 0x4c,
202 Cfg9346 = 0x50,
203 Config0 = 0x51,
204 Config1 = 0x52,
205 Config2 = 0x53,
206 Config3 = 0x54,
207 Config4 = 0x55,
208 Config5 = 0x56,
209 MultiIntr = 0x5c,
210 PHYAR = 0x60,
211 TBICSR = 0x64,
212 TBI_ANAR = 0x68,
213 TBI_LPAR = 0x6a,
214 PHYstatus = 0x6c,
215 RxMaxSize = 0xda,
216 CPlusCmd = 0xe0,
217 IntrMitigate = 0xe2,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
220 EarlyTxThres = 0xec,
221 FuncEvent = 0xf0,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
1da177e4
LT		 225};
226
07d3f51f 227enum rtl_register_content {
1da177e4 228 /* InterruptStatusBits */
07d3f51f
FR		 229 SYSErr = 0x8000,
230 PCSTimeout = 0x4000,
231 SWInt = 0x0100,
232 TxDescUnavail = 0x0080,
233 RxFIFOOver = 0x0040,
234 LinkChg = 0x0020,
235 RxOverflow = 0x0010,
236 TxErr = 0x0008,
237 TxOK = 0x0004,
238 RxErr = 0x0002,
239 RxOK = 0x0001,
1da177e4
LT		 240
241 /* RxStatusDesc */
9dccf611
FR		 242 RxFOVF = (1 << 23),
243 RxRWT = (1 << 22),
244 RxRES = (1 << 21),
245 RxRUNT = (1 << 20),
246 RxCRC = (1 << 19),
1da177e4
LT		 247
248 /* ChipCmdBits */
07d3f51f
FR		 249 CmdReset = 0x10,
250 CmdRxEnb = 0x08,
251 CmdTxEnb = 0x04,
252 RxBufEmpty = 0x01,
1da177e4 253
275391a4
FR		 254 /* TXPoll register p.5 */
255 HPQ = 0x80, /* Poll cmd on the high prio queue */
256 NPQ = 0x40, /* Poll cmd on the low prio queue */
257 FSWInt = 0x01, /* Forced software interrupt */
258
1da177e4 259 /* Cfg9346Bits */
07d3f51f
FR		 260 Cfg9346_Lock = 0x00,
261 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 262
263 /* rx_mode_bits */
07d3f51f
FR		 264 AcceptErr = 0x20,
265 AcceptRunt = 0x10,
266 AcceptBroadcast = 0x08,
267 AcceptMulticast = 0x04,
268 AcceptMyPhys = 0x02,
269 AcceptAllPhys = 0x01,
1da177e4
LT		 270
271 /* RxConfigBits */
07d3f51f
FR		 272 RxCfgFIFOShift = 13,
273 RxCfgDMAShift = 8,
1da177e4
LT		 274
275 /* TxConfigBits */
276 TxInterFrameGapShift = 24,
277 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
278
5d06a99f
FR		 279 /* Config1 register p.24 */
280 PMEnable = (1 << 0), /* Power Management Enable */
281
6dccd16b
FR		 282 /* Config2 register p. 25 */
283 PCI_Clock_66MHz = 0x01,
284 PCI_Clock_33MHz = 0x00,
285
61a4dcc2
FR		 286 /* Config3 register p.25 */
287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289
5d06a99f 290 /* Config5 register p.27 */
61a4dcc2
FR		 291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296
1da177e4
LT		 297 /* TBICSR p.28 */
298 TBIReset = 0x80000000,
299 TBILoopback = 0x40000000,
300 TBINwEnable = 0x20000000,
301 TBINwRestart = 0x10000000,
302 TBILinkOk = 0x02000000,
303 TBINwComplete = 0x01000000,
304
305 /* CPlusCmd p.31 */
0e485150 306 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 307 RxVlan = (1 << 6),
308 RxChkSum = (1 << 5),
309 PCIDAC = (1 << 4),
310 PCIMulRW = (1 << 3),
0e485150
FR		 311 INTT_0 = 0x0000, // 8168
312 INTT_1 = 0x0001, // 8168
313 INTT_2 = 0x0002, // 8168
314 INTT_3 = 0x0003, // 8168
1da177e4
LT		 315
316 /* rtl8169_PHYstatus */
07d3f51f
FR		 317 TBI_Enable = 0x80,
318 TxFlowCtrl = 0x40,
319 RxFlowCtrl = 0x20,
320 _1000bpsF = 0x10,
321 _100bps = 0x08,
322 _10bps = 0x04,
323 LinkStatus = 0x02,
324 FullDup = 0x01,
1da177e4 325
1da177e4 326 /* _TBICSRBit */
07d3f51f 327 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 328
329 /* DumpCounterCommand */
07d3f51f 330 CounterDump = 0x8,
1da177e4
LT		 331};
332
07d3f51f 333enum desc_status_bit {
1da177e4
LT		 334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
335 RingEnd = (1 << 30), /* End of descriptor ring */
336 FirstFrag = (1 << 29), /* First segment of a packet */
337 LastFrag = (1 << 28), /* Final segment of a packet */
338
339 /* Tx private */
340 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
341 MSSShift = 16, /* MSS value position */
342 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
343 IPCS = (1 << 18), /* Calculate IP checksum */
344 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
345 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
346 TxVlanTag = (1 << 17), /* Add VLAN tag */
347
348 /* Rx private */
349 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
350 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
351
352#define RxProtoUDP (PID1)
353#define RxProtoTCP (PID0)
354#define RxProtoIP (PID1 | PID0)
355#define RxProtoMask RxProtoIP
356
357 IPFail = (1 << 16), /* IP checksum failed */
358 UDPFail = (1 << 15), /* UDP/IP checksum failed */
359 TCPFail = (1 << 14), /* TCP/IP checksum failed */
360 RxVlanTag = (1 << 16), /* VLAN tag available */
361};
362
363#define RsvdMask 0x3fffc000
364
365struct TxDesc {
6cccd6e7
REB		 366 __le32 opts1;
367 __le32 opts2;
368 __le64 addr;
1da177e4
LT		 369};
370
371struct RxDesc {
6cccd6e7
REB		 372 __le32 opts1;
373 __le32 opts2;
374 __le64 addr;
1da177e4
LT		 375};
376
377struct ring_info {
378 struct sk_buff *skb;
379 u32 len;
380 u8 __pad[sizeof(void *) - sizeof(u32)];
381};
382
383struct rtl8169_private {
384 void __iomem *mmio_addr; /* memory map physical address */
385 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 386 struct net_device *dev;
1da177e4
LT		 387 struct net_device_stats stats; /* statistics of net device */
388 spinlock_t lock; /* spin lock flag */
b57b7e5a 389 u32 msg_enable;
1da177e4
LT		 390 int chipset;
391 int mac_version;
392 int phy_version;
393 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
394 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
395 u32 dirty_rx;
396 u32 dirty_tx;
397 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
398 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
399 dma_addr_t TxPhyAddr;
400 dma_addr_t RxPhyAddr;
401 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
402 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 403 unsigned align;
1da177e4
LT		 404 unsigned rx_buf_sz;
405 struct timer_list timer;
406 u16 cp_cmd;
0e485150
FR		 407 u16 intr_event;
408 u16 napi_event;
1da177e4
LT		 409 u16 intr_mask;
410 int phy_auto_nego_reg;
411 int phy_1000_ctrl_reg;
412#ifdef CONFIG_R8169_VLAN
413 struct vlan_group *vlgrp;
414#endif
415 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
416 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
417 void (*phy_reset_enable)(void __iomem *);
07ce4064 418 void (*hw_start)(struct net_device *);
1da177e4
LT		 419 unsigned int (*phy_reset_pending)(void __iomem *);
420 unsigned int (*link_ok)(void __iomem *);
c4028958 421 struct delayed_work task;
61a4dcc2 422 unsigned wol_enabled : 1;
1da177e4
LT		 423};
424
979b6c13 425MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 426MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 427module_param(rx_copybreak, int, 0);
1b7efd58 428MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 429module_param(use_dac, int, 0);
430MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 431module_param_named(debug, debug.msg_enable, int, 0);
432MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 433MODULE_LICENSE("GPL");
434MODULE_VERSION(RTL8169_VERSION);
435
436static int rtl8169_open(struct net_device *dev);
437static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 438static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 439static int rtl8169_init_ring(struct net_device *dev);
07ce4064 440static void rtl_hw_start(struct net_device *dev);
1da177e4 441static int rtl8169_close(struct net_device *dev);
07ce4064 442static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 443static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 444static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 445static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
446 void __iomem *);
4dcb7d33 447static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 448static void rtl8169_down(struct net_device *dev);
99f252b0 449static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 450
451#ifdef CONFIG_R8169_NAPI
452static int rtl8169_poll(struct net_device *dev, int *budget);
453#endif
454
1da177e4 455static const unsigned int rtl8169_rx_config =
5b0384f4 456 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 457
07d3f51f 458static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 459{
460 int i;
461
07d3f51f 462 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 463
2371408c 464 for (i = 20; i > 0; i--) {
07d3f51f
FR		 465 /*
466 * Check if the RTL8169 has completed writing to the specified
467 * MII register.
468 */
5b0384f4 469 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 470 break;
2371408c 471 udelay(25);
1da177e4
LT		 472 }
473}
474
07d3f51f 475static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 476{
477 int i, value = -1;
478
07d3f51f 479 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 480
2371408c 481 for (i = 20; i > 0; i--) {
07d3f51f
FR		 482 /*
483 * Check if the RTL8169 has completed retrieving data from
484 * the specified MII register.
485 */
1da177e4
LT		 486 if (RTL_R32(PHYAR) & 0x80000000) {
487 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
488 break;
489 }
2371408c 490 udelay(25);
1da177e4
LT		 491 }
492 return value;
493}
494
495static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
496{
497 RTL_W16(IntrMask, 0x0000);
498
499 RTL_W16(IntrStatus, 0xffff);
500}
501
502static void rtl8169_asic_down(void __iomem *ioaddr)
503{
504 RTL_W8(ChipCmd, 0x00);
505 rtl8169_irq_mask_and_ack(ioaddr);
506 RTL_R16(CPlusCmd);
507}
508
509static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
510{
511 return RTL_R32(TBICSR) & TBIReset;
512}
513
514static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
515{
64e4bfb4 516 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 517}
518
519static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
520{
521 return RTL_R32(TBICSR) & TBILinkOk;
522}
523
524static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
525{
526 return RTL_R8(PHYstatus) & LinkStatus;
527}
528
529static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
530{
531 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
532}
533
534static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
535{
536 unsigned int val;
537
9e0db8ef
FR		 538 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
539 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 540}
541
542static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 543 struct rtl8169_private *tp,
544 void __iomem *ioaddr)
1da177e4
LT		 545{
546 unsigned long flags;
547
548 spin_lock_irqsave(&tp->lock, flags);
549 if (tp->link_ok(ioaddr)) {
550 netif_carrier_on(dev);
b57b7e5a
SH		 551 if (netif_msg_ifup(tp))
552 printk(KERN_INFO PFX "%s: link up\n", dev->name);
553 } else {
554 if (netif_msg_ifdown(tp))
555 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 556 netif_carrier_off(dev);
b57b7e5a 557 }
1da177e4
LT		 558 spin_unlock_irqrestore(&tp->lock, flags);
559}
560
61a4dcc2
FR		 561static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
562{
563 struct rtl8169_private *tp = netdev_priv(dev);
564 void __iomem *ioaddr = tp->mmio_addr;
565 u8 options;
566
567 wol->wolopts = 0;
568
569#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
570 wol->supported = WAKE_ANY;
571
572 spin_lock_irq(&tp->lock);
573
574 options = RTL_R8(Config1);
575 if (!(options & PMEnable))
576 goto out_unlock;
577
578 options = RTL_R8(Config3);
579 if (options & LinkUp)
580 wol->wolopts |= WAKE_PHY;
581 if (options & MagicPacket)
582 wol->wolopts |= WAKE_MAGIC;
583
584 options = RTL_R8(Config5);
585 if (options & UWF)
586 wol->wolopts |= WAKE_UCAST;
587 if (options & BWF)
5b0384f4 588 wol->wolopts |= WAKE_BCAST;
61a4dcc2 589 if (options & MWF)
5b0384f4 590 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 591
592out_unlock:
593 spin_unlock_irq(&tp->lock);
594}
595
596static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
597{
598 struct rtl8169_private *tp = netdev_priv(dev);
599 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 600 unsigned int i;
61a4dcc2
FR		 601 static struct {
602 u32 opt;
603 u16 reg;
604 u8 mask;
605 } cfg[] = {
606 { WAKE_ANY, Config1, PMEnable },
607 { WAKE_PHY, Config3, LinkUp },
608 { WAKE_MAGIC, Config3, MagicPacket },
609 { WAKE_UCAST, Config5, UWF },
610 { WAKE_BCAST, Config5, BWF },
611 { WAKE_MCAST, Config5, MWF },
612 { WAKE_ANY, Config5, LanWake }
613 };
614
615 spin_lock_irq(&tp->lock);
616
617 RTL_W8(Cfg9346, Cfg9346_Unlock);
618
619 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
620 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
621 if (wol->wolopts & cfg[i].opt)
622 options |= cfg[i].mask;
623 RTL_W8(cfg[i].reg, options);
624 }
625
626 RTL_W8(Cfg9346, Cfg9346_Lock);
627
628 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
629
630 spin_unlock_irq(&tp->lock);
631
632 return 0;
633}
634
1da177e4
LT		 635static void rtl8169_get_drvinfo(struct net_device *dev,
636 struct ethtool_drvinfo *info)
637{
638 struct rtl8169_private *tp = netdev_priv(dev);
639
640 strcpy(info->driver, MODULENAME);
641 strcpy(info->version, RTL8169_VERSION);
642 strcpy(info->bus_info, pci_name(tp->pci_dev));
643}
644
645static int rtl8169_get_regs_len(struct net_device *dev)
646{
647 return R8169_REGS_SIZE;
648}
649
650static int rtl8169_set_speed_tbi(struct net_device *dev,
651 u8 autoneg, u16 speed, u8 duplex)
652{
653 struct rtl8169_private *tp = netdev_priv(dev);
654 void __iomem *ioaddr = tp->mmio_addr;
655 int ret = 0;
656 u32 reg;
657
658 reg = RTL_R32(TBICSR);
659 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
660 (duplex == DUPLEX_FULL)) {
661 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
662 } else if (autoneg == AUTONEG_ENABLE)
663 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
664 else {
b57b7e5a
SH		 665 if (netif_msg_link(tp)) {
666 printk(KERN_WARNING "%s: "
667 "incorrect speed setting refused in TBI mode\n",
668 dev->name);
669 }
1da177e4
LT		 670 ret = -EOPNOTSUPP;
671 }
672
673 return ret;
674}
675
676static int rtl8169_set_speed_xmii(struct net_device *dev,
677 u8 autoneg, u16 speed, u8 duplex)
678{
679 struct rtl8169_private *tp = netdev_priv(dev);
680 void __iomem *ioaddr = tp->mmio_addr;
681 int auto_nego, giga_ctrl;
682
64e4bfb4
FR		 683 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
684 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
685 ADVERTISE_100HALF | ADVERTISE_100FULL);
686 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
687 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 688
689 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 690 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
691 ADVERTISE_100HALF | ADVERTISE_100FULL);
692 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 693 } else {
694 if (speed == SPEED_10)
64e4bfb4 695 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 696 else if (speed == SPEED_100)
64e4bfb4 697 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 698 else if (speed == SPEED_1000)
64e4bfb4 699 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 700
701 if (duplex == DUPLEX_HALF)
64e4bfb4 702 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 703
704 if (duplex == DUPLEX_FULL)
64e4bfb4 705 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 706
707 /* This tweak comes straight from Realtek's driver. */
708 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
709 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 710 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 711 }
712 }
713
714 /* The 8100e/8101e do Fast Ethernet only. */
715 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
716 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
717 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 718 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 719 netif_msg_link(tp)) {
720 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
721 dev->name);
722 }
64e4bfb4 723 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 724 }
725
623a1593
FR		 726 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
727
1da177e4
LT		 728 tp->phy_auto_nego_reg = auto_nego;
729 tp->phy_1000_ctrl_reg = giga_ctrl;
730
64e4bfb4
FR		 731 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
732 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
733 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 734 return 0;
735}
736
737static int rtl8169_set_speed(struct net_device *dev,
738 u8 autoneg, u16 speed, u8 duplex)
739{
740 struct rtl8169_private *tp = netdev_priv(dev);
741 int ret;
742
743 ret = tp->set_speed(dev, autoneg, speed, duplex);
744
64e4bfb4 745 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 746 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
747
748 return ret;
749}
750
751static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
752{
753 struct rtl8169_private *tp = netdev_priv(dev);
754 unsigned long flags;
755 int ret;
756
757 spin_lock_irqsave(&tp->lock, flags);
758 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
759 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 760
1da177e4
LT		 761 return ret;
762}
763
764static u32 rtl8169_get_rx_csum(struct net_device *dev)
765{
766 struct rtl8169_private *tp = netdev_priv(dev);
767
768 return tp->cp_cmd & RxChkSum;
769}
770
771static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
772{
773 struct rtl8169_private *tp = netdev_priv(dev);
774 void __iomem *ioaddr = tp->mmio_addr;
775 unsigned long flags;
776
777 spin_lock_irqsave(&tp->lock, flags);
778
779 if (data)
780 tp->cp_cmd |= RxChkSum;
781 else
782 tp->cp_cmd &= ~RxChkSum;
783
784 RTL_W16(CPlusCmd, tp->cp_cmd);
785 RTL_R16(CPlusCmd);
786
787 spin_unlock_irqrestore(&tp->lock, flags);
788
789 return 0;
790}
791
792#ifdef CONFIG_R8169_VLAN
793
794static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
795 struct sk_buff *skb)
796{
797 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
798 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
799}
800
801static void rtl8169_vlan_rx_register(struct net_device *dev,
802 struct vlan_group *grp)
803{
804 struct rtl8169_private *tp = netdev_priv(dev);
805 void __iomem *ioaddr = tp->mmio_addr;
806 unsigned long flags;
807
808 spin_lock_irqsave(&tp->lock, flags);
809 tp->vlgrp = grp;
810 if (tp->vlgrp)
811 tp->cp_cmd |= RxVlan;
812 else
813 tp->cp_cmd &= ~RxVlan;
814 RTL_W16(CPlusCmd, tp->cp_cmd);
815 RTL_R16(CPlusCmd);
816 spin_unlock_irqrestore(&tp->lock, flags);
817}
818
1da177e4
LT		 819static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
820 struct sk_buff *skb)
821{
822 u32 opts2 = le32_to_cpu(desc->opts2);
823 int ret;
824
825 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 826 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 827 ret = 0;
828 } else
829 ret = -1;
830 desc->opts2 = 0;
831 return ret;
832}
833
834#else /* !CONFIG_R8169_VLAN */
835
836static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
837 struct sk_buff *skb)
838{
839 return 0;
840}
841
842static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
843 struct sk_buff *skb)
844{
845 return -1;
846}
847
848#endif
849
850static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
851{
852 struct rtl8169_private *tp = netdev_priv(dev);
853 void __iomem *ioaddr = tp->mmio_addr;
854 u32 status;
855
856 cmd->supported =
857 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
858 cmd->port = PORT_FIBRE;
859 cmd->transceiver = XCVR_INTERNAL;
860
861 status = RTL_R32(TBICSR);
862 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
863 cmd->autoneg = !!(status & TBINwEnable);
864
865 cmd->speed = SPEED_1000;
866 cmd->duplex = DUPLEX_FULL; /* Always set */
867}
868
869static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 u8 status;
874
875 cmd->supported = SUPPORTED_10baseT_Half |
876 SUPPORTED_10baseT_Full |
877 SUPPORTED_100baseT_Half |
878 SUPPORTED_100baseT_Full |
879 SUPPORTED_1000baseT_Full |
880 SUPPORTED_Autoneg |
5b0384f4 881 SUPPORTED_TP;
1da177e4
LT		 882
883 cmd->autoneg = 1;
884 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
885
64e4bfb4 886 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 887 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 888 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 889 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 890 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 891 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 892 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 893 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 894 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 895 cmd->advertising |= ADVERTISED_1000baseT_Full;
896
897 status = RTL_R8(PHYstatus);
898
899 if (status & _1000bpsF)
900 cmd->speed = SPEED_1000;
901 else if (status & _100bps)
902 cmd->speed = SPEED_100;
903 else if (status & _10bps)
904 cmd->speed = SPEED_10;
905
623a1593
FR		 906 if (status & TxFlowCtrl)
907 cmd->advertising |= ADVERTISED_Asym_Pause;
908 if (status & RxFlowCtrl)
909 cmd->advertising |= ADVERTISED_Pause;
910
1da177e4
LT		 911 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
912 DUPLEX_FULL : DUPLEX_HALF;
913}
914
915static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
916{
917 struct rtl8169_private *tp = netdev_priv(dev);
918 unsigned long flags;
919
920 spin_lock_irqsave(&tp->lock, flags);
921
922 tp->get_settings(dev, cmd);
923
924 spin_unlock_irqrestore(&tp->lock, flags);
925 return 0;
926}
927
928static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
929 void *p)
930{
5b0384f4
FR		 931 struct rtl8169_private *tp = netdev_priv(dev);
932 unsigned long flags;
1da177e4 933
5b0384f4
FR		 934 if (regs->len > R8169_REGS_SIZE)
935 regs->len = R8169_REGS_SIZE;
1da177e4 936
5b0384f4
FR		 937 spin_lock_irqsave(&tp->lock, flags);
938 memcpy_fromio(p, tp->mmio_addr, regs->len);
939 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 940}
941
b57b7e5a
SH		 942static u32 rtl8169_get_msglevel(struct net_device *dev)
943{
944 struct rtl8169_private *tp = netdev_priv(dev);
945
946 return tp->msg_enable;
947}
948
949static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
950{
951 struct rtl8169_private *tp = netdev_priv(dev);
952
953 tp->msg_enable = value;
954}
955
d4a3a0fc
SH		 956static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
957 "tx_packets",
958 "rx_packets",
959 "tx_errors",
960 "rx_errors",
961 "rx_missed",
962 "align_errors",
963 "tx_single_collisions",
964 "tx_multi_collisions",
965 "unicast",
966 "broadcast",
967 "multicast",
968 "tx_aborted",
969 "tx_underrun",
970};
971
972struct rtl8169_counters {
973 u64 tx_packets;
974 u64 rx_packets;
975 u64 tx_errors;
976 u32 rx_errors;
977 u16 rx_missed;
978 u16 align_errors;
979 u32 tx_one_collision;
980 u32 tx_multi_collision;
981 u64 rx_unicast;
982 u64 rx_broadcast;
983 u32 rx_multicast;
984 u16 tx_aborted;
985 u16 tx_underun;
986};
987
988static int rtl8169_get_stats_count(struct net_device *dev)
989{
990 return ARRAY_SIZE(rtl8169_gstrings);
991}
992
993static void rtl8169_get_ethtool_stats(struct net_device *dev,
994 struct ethtool_stats *stats, u64 *data)
995{
996 struct rtl8169_private *tp = netdev_priv(dev);
997 void __iomem *ioaddr = tp->mmio_addr;
998 struct rtl8169_counters *counters;
999 dma_addr_t paddr;
1000 u32 cmd;
1001
1002 ASSERT_RTNL();
1003
1004 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1005 if (!counters)
1006 return;
1007
1008 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1009 cmd = (u64)paddr & DMA_32BIT_MASK;
1010 RTL_W32(CounterAddrLow, cmd);
1011 RTL_W32(CounterAddrLow, cmd | CounterDump);
1012
1013 while (RTL_R32(CounterAddrLow) & CounterDump) {
1014 if (msleep_interruptible(1))
1015 break;
1016 }
1017
1018 RTL_W32(CounterAddrLow, 0);
1019 RTL_W32(CounterAddrHigh, 0);
1020
5b0384f4 1021 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1022 data[1] = le64_to_cpu(counters->rx_packets);
1023 data[2] = le64_to_cpu(counters->tx_errors);
1024 data[3] = le32_to_cpu(counters->rx_errors);
1025 data[4] = le16_to_cpu(counters->rx_missed);
1026 data[5] = le16_to_cpu(counters->align_errors);
1027 data[6] = le32_to_cpu(counters->tx_one_collision);
1028 data[7] = le32_to_cpu(counters->tx_multi_collision);
1029 data[8] = le64_to_cpu(counters->rx_unicast);
1030 data[9] = le64_to_cpu(counters->rx_broadcast);
1031 data[10] = le32_to_cpu(counters->rx_multicast);
1032 data[11] = le16_to_cpu(counters->tx_aborted);
1033 data[12] = le16_to_cpu(counters->tx_underun);
1034
1035 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1036}
1037
1038static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1039{
1040 switch(stringset) {
1041 case ETH_SS_STATS:
1042 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1043 break;
1044 }
1045}
1046
7282d491 1047static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1048 .get_drvinfo = rtl8169_get_drvinfo,
1049 .get_regs_len = rtl8169_get_regs_len,
1050 .get_link = ethtool_op_get_link,
1051 .get_settings = rtl8169_get_settings,
1052 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1053 .get_msglevel = rtl8169_get_msglevel,
1054 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1055 .get_rx_csum = rtl8169_get_rx_csum,
1056 .set_rx_csum = rtl8169_set_rx_csum,
1057 .get_tx_csum = ethtool_op_get_tx_csum,
1058 .set_tx_csum = ethtool_op_set_tx_csum,
1059 .get_sg = ethtool_op_get_sg,
1060 .set_sg = ethtool_op_set_sg,
1061 .get_tso = ethtool_op_get_tso,
1062 .set_tso = ethtool_op_set_tso,
1063 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1064 .get_wol = rtl8169_get_wol,
1065 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1066 .get_strings = rtl8169_get_strings,
1067 .get_stats_count = rtl8169_get_stats_count,
1068 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1069 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1070};
1071
07d3f51f
FR		 1072static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1073 int bitnum, int bitval)
1da177e4
LT		 1074{
1075 int val;
1076
1077 val = mdio_read(ioaddr, reg);
1078 val = (bitval == 1) ?
1079 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1080 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1081}
1082
07d3f51f
FR		 1083static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1084 void __iomem *ioaddr)
1da177e4 1085{
0e485150
FR		 1086 /*
1087 * The driver currently handles the 8168Bf and the 8168Be identically
1088 * but they can be identified more specifically through the test below
1089 * if needed:
1090 *
1091 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1092 *
1093 * Same thing for the 8101Eb and the 8101Ec:
1094 *
1095 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1096 */
1da177e4
LT		 1097 const struct {
1098 u32 mask;
1099 int mac_version;
1100 } mac_info[] = {
bcf0bf90
FR		 1101 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1102 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1103 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1104 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1105 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1106 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1107 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1108 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1109 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1110 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1111 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1112 }, *p = mac_info;
1113 u32 reg;
1114
6dccd16b 1115 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1116 while ((reg & p->mask) != p->mask)
1117 p++;
1118 tp->mac_version = p->mac_version;
1119}
1120
1121static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1122{
bcf0bf90 1123 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1124}
1125
07d3f51f
FR		 1126static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1127 void __iomem *ioaddr)
1da177e4
LT		 1128{
1129 const struct {
1130 u16 mask;
1131 u16 set;
1132 int phy_version;
1133 } phy_info[] = {
1134 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1135 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1136 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1137 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1138 }, *p = phy_info;
1139 u16 reg;
1140
64e4bfb4 1141 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1142 while ((reg & p->mask) != p->set)
1143 p++;
1144 tp->phy_version = p->phy_version;
1145}
1146
1147static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1148{
1149 struct {
1150 int version;
1151 char *msg;
1152 u32 reg;
1153 } phy_print[] = {
1154 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1155 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1156 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1157 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1158 { 0, NULL, 0x0000 }
1159 }, *p;
1160
1161 for (p = phy_print; p->msg; p++) {
1162 if (tp->phy_version == p->version) {
1163 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1164 return;
1165 }
1166 }
1167 dprintk("phy_version == Unknown\n");
1168}
1169
1170static void rtl8169_hw_phy_config(struct net_device *dev)
1171{
1172 struct rtl8169_private *tp = netdev_priv(dev);
1173 void __iomem *ioaddr = tp->mmio_addr;
1174 struct {
1175 u16 regs[5]; /* Beware of bit-sign propagation */
1176 } phy_magic[5] = { {
1177 { 0x0000, //w 4 15 12 0
1178 0x00a1, //w 3 15 0 00a1
1179 0x0008, //w 2 15 0 0008
1180 0x1020, //w 1 15 0 1020
1181 0x1000 } },{ //w 0 15 0 1000
1182 { 0x7000, //w 4 15 12 7
1183 0xff41, //w 3 15 0 ff41
1184 0xde60, //w 2 15 0 de60
1185 0x0140, //w 1 15 0 0140
1186 0x0077 } },{ //w 0 15 0 0077
1187 { 0xa000, //w 4 15 12 a
1188 0xdf01, //w 3 15 0 df01
1189 0xdf20, //w 2 15 0 df20
1190 0xff95, //w 1 15 0 ff95
1191 0xfa00 } },{ //w 0 15 0 fa00
1192 { 0xb000, //w 4 15 12 b
1193 0xff41, //w 3 15 0 ff41
1194 0xde20, //w 2 15 0 de20
1195 0x0140, //w 1 15 0 0140
1196 0x00bb } },{ //w 0 15 0 00bb
1197 { 0xf000, //w 4 15 12 f
1198 0xdf01, //w 3 15 0 df01
1199 0xdf20, //w 2 15 0 df20
1200 0xff95, //w 1 15 0 ff95
1201 0xbf00 } //w 0 15 0 bf00
1202 }
1203 }, *p = phy_magic;
07d3f51f 1204 unsigned int i;
1da177e4
LT		 1205
1206 rtl8169_print_mac_version(tp);
1207 rtl8169_print_phy_version(tp);
1208
bcf0bf90 1209 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1210 return;
1211 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1212 return;
1213
1214 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1215 dprintk("Do final_reg2.cfg\n");
1216
1217 /* Shazam ! */
1218
bcf0bf90 1219 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1220 mdio_write(ioaddr, 31, 0x0002);
1221 mdio_write(ioaddr, 1, 0x90d0);
1222 mdio_write(ioaddr, 31, 0x0000);
1223 return;
1224 }
1225
1226 /* phy config for RTL8169s mac_version C chip */
1227 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1228 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1229 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1230 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1231
1232 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1233 int val, pos = 4;
1234
1235 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1236 mdio_write(ioaddr, pos, val);
1237 while (--pos >= 0)
1238 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1239 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1240 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1241 }
1242 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1243}
1244
1245static void rtl8169_phy_timer(unsigned long __opaque)
1246{
1247 struct net_device *dev = (struct net_device *)__opaque;
1248 struct rtl8169_private *tp = netdev_priv(dev);
1249 struct timer_list *timer = &tp->timer;
1250 void __iomem *ioaddr = tp->mmio_addr;
1251 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1252
bcf0bf90 1253 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1254 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1255
64e4bfb4 1256 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1257 return;
1258
1259 spin_lock_irq(&tp->lock);
1260
1261 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1262 /*
1da177e4
LT		 1263 * A busy loop could burn quite a few cycles on nowadays CPU.
1264 * Let's delay the execution of the timer for a few ticks.
1265 */
1266 timeout = HZ/10;
1267 goto out_mod_timer;
1268 }
1269
1270 if (tp->link_ok(ioaddr))
1271 goto out_unlock;
1272
b57b7e5a
SH		 1273 if (netif_msg_link(tp))
1274 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1275
1276 tp->phy_reset_enable(ioaddr);
1277
1278out_mod_timer:
1279 mod_timer(timer, jiffies + timeout);
1280out_unlock:
1281 spin_unlock_irq(&tp->lock);
1282}
1283
1284static inline void rtl8169_delete_timer(struct net_device *dev)
1285{
1286 struct rtl8169_private *tp = netdev_priv(dev);
1287 struct timer_list *timer = &tp->timer;
1288
bcf0bf90 1289 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1290 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1291 return;
1292
1293 del_timer_sync(timer);
1294}
1295
1296static inline void rtl8169_request_timer(struct net_device *dev)
1297{
1298 struct rtl8169_private *tp = netdev_priv(dev);
1299 struct timer_list *timer = &tp->timer;
1300
bcf0bf90 1301 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1302 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1303 return;
1304
2efa53f3 1305 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1306}
1307
1308#ifdef CONFIG_NET_POLL_CONTROLLER
1309/*
1310 * Polling 'interrupt' - used by things like netconsole to send skbs
1311 * without having to re-enable interrupts. It's not called while
1312 * the interrupt routine is executing.
1313 */
1314static void rtl8169_netpoll(struct net_device *dev)
1315{
1316 struct rtl8169_private *tp = netdev_priv(dev);
1317 struct pci_dev *pdev = tp->pci_dev;
1318
1319 disable_irq(pdev->irq);
7d12e780 1320 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1321 enable_irq(pdev->irq);
1322}
1323#endif
1324
1325static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1326 void __iomem *ioaddr)
1327{
1328 iounmap(ioaddr);
1329 pci_release_regions(pdev);
1330 pci_disable_device(pdev);
1331 free_netdev(dev);
1332}
1333
bf793295
FR		 1334static void rtl8169_phy_reset(struct net_device *dev,
1335 struct rtl8169_private *tp)
1336{
1337 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1338 unsigned int i;
bf793295
FR		 1339
1340 tp->phy_reset_enable(ioaddr);
1341 for (i = 0; i < 100; i++) {
1342 if (!tp->phy_reset_pending(ioaddr))
1343 return;
1344 msleep(1);
1345 }
1346 if (netif_msg_link(tp))
1347 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1348}
1349
4ff96fa6
FR		 1350static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1351{
1352 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6
FR		 1353
1354 rtl8169_hw_phy_config(dev);
1355
1356 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1357 RTL_W8(0x82, 0x01);
1358
6dccd16b
FR		 1359 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1360
1361 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1362 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1363
bcf0bf90 1364 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1365 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1366 RTL_W8(0x82, 0x01);
1367 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1368 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1369 }
1370
bf793295
FR		 1371 rtl8169_phy_reset(dev, tp);
1372
901dda2b
FR		 1373 /*
1374 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1375 * only 8101. Don't panic.
1376 */
1377 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1378
1379 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1380 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1381}
1382
773d2021
FR		 1383static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1384{
1385 void __iomem *ioaddr = tp->mmio_addr;
1386 u32 high;
1387 u32 low;
1388
1389 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1390 high = addr[4] | (addr[5] << 8);
1391
1392 spin_lock_irq(&tp->lock);
1393
1394 RTL_W8(Cfg9346, Cfg9346_Unlock);
1395 RTL_W32(MAC0, low);
1396 RTL_W32(MAC4, high);
1397 RTL_W8(Cfg9346, Cfg9346_Lock);
1398
1399 spin_unlock_irq(&tp->lock);
1400}
1401
1402static int rtl_set_mac_address(struct net_device *dev, void *p)
1403{
1404 struct rtl8169_private *tp = netdev_priv(dev);
1405 struct sockaddr *addr = p;
1406
1407 if (!is_valid_ether_addr(addr->sa_data))
1408 return -EADDRNOTAVAIL;
1409
1410 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1411
1412 rtl_rar_set(tp, dev->dev_addr);
1413
1414 return 0;
1415}
1416
5f787a1a
FR		 1417static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1418{
1419 struct rtl8169_private *tp = netdev_priv(dev);
1420 struct mii_ioctl_data *data = if_mii(ifr);
1421
1422 if (!netif_running(dev))
1423 return -ENODEV;
1424
1425 switch (cmd) {
1426 case SIOCGMIIPHY:
1427 data->phy_id = 32; /* Internal PHY */
1428 return 0;
1429
1430 case SIOCGMIIREG:
1431 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1432 return 0;
1433
1434 case SIOCSMIIREG:
1435 if (!capable(CAP_NET_ADMIN))
1436 return -EPERM;
1437 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1438 return 0;
1439 }
1440 return -EOPNOTSUPP;
1441}
1442
0e485150
FR		 1443static const struct rtl_cfg_info {
1444 void (*hw_start)(struct net_device *);
1445 unsigned int region;
1446 unsigned int align;
1447 u16 intr_event;
1448 u16 napi_event;
1449} rtl_cfg_infos [] = {
1450 [RTL_CFG_0] = {
1451 .hw_start = rtl_hw_start_8169,
1452 .region = 1,
e9f63f30 1453 .align = 0,
0e485150
FR		 1454 .intr_event = SYSErr | LinkChg | RxOverflow |
1455 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1456 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1457 },
1458 [RTL_CFG_1] = {
1459 .hw_start = rtl_hw_start_8168,
1460 .region = 2,
1461 .align = 8,
1462 .intr_event = SYSErr | LinkChg | RxOverflow |
1463 TxErr | TxOK | RxOK | RxErr,
1464 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1465 },
1466 [RTL_CFG_2] = {
1467 .hw_start = rtl_hw_start_8101,
1468 .region = 2,
1469 .align = 8,
1470 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1471 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1472 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1473 }
1474};
1475
1da177e4 1476static int __devinit
4ff96fa6 1477rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1478{
0e485150
FR		 1479 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1480 const unsigned int region = cfg->region;
1da177e4 1481 struct rtl8169_private *tp;
4ff96fa6
FR		 1482 struct net_device *dev;
1483 void __iomem *ioaddr;
07d3f51f
FR		 1484 unsigned int i;
1485 int rc;
1da177e4 1486
4ff96fa6
FR		 1487 if (netif_msg_drv(&debug)) {
1488 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1489 MODULENAME, RTL8169_VERSION);
1490 }
1da177e4 1491
1da177e4 1492 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1493 if (!dev) {
b57b7e5a 1494 if (netif_msg_drv(&debug))
9b91cf9d 1495 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1496 rc = -ENOMEM;
1497 goto out;
1da177e4
LT		 1498 }
1499
1500 SET_MODULE_OWNER(dev);
1501 SET_NETDEV_DEV(dev, &pdev->dev);
1502 tp = netdev_priv(dev);
c4028958 1503 tp->dev = dev;
b57b7e5a 1504 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1505
1506 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1507 rc = pci_enable_device(pdev);
b57b7e5a 1508 if (rc < 0) {
2e8a538d 1509 if (netif_msg_probe(tp))
9b91cf9d 1510 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1511 goto err_out_free_dev_1;
1da177e4
LT		 1512 }
1513
1514 rc = pci_set_mwi(pdev);
1515 if (rc < 0)
4ff96fa6 1516 goto err_out_disable_2;
1da177e4 1517
1da177e4 1518 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1519 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1520 if (netif_msg_probe(tp)) {
9b91cf9d 1521 dev_err(&pdev->dev,
bcf0bf90
FR		 1522 "region #%d not an MMIO resource, aborting\n",
1523 region);
4ff96fa6 1524 }
1da177e4 1525 rc = -ENODEV;
4ff96fa6 1526 goto err_out_mwi_3;
1da177e4 1527 }
4ff96fa6 1528
1da177e4 1529 /* check for weird/broken PCI region reporting */
bcf0bf90 1530 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1531 if (netif_msg_probe(tp)) {
9b91cf9d 1532 dev_err(&pdev->dev,
4ff96fa6
FR		 1533 "Invalid PCI region size(s), aborting\n");
1534 }
1da177e4 1535 rc = -ENODEV;
4ff96fa6 1536 goto err_out_mwi_3;
1da177e4
LT		 1537 }
1538
1539 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1540 if (rc < 0) {
2e8a538d 1541 if (netif_msg_probe(tp))
9b91cf9d 1542 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1543 goto err_out_mwi_3;
1da177e4
LT		 1544 }
1545
1546 tp->cp_cmd = PCIMulRW | RxChkSum;
1547
1548 if ((sizeof(dma_addr_t) > 4) &&
1549 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1550 tp->cp_cmd |= PCIDAC;
1551 dev->features |= NETIF_F_HIGHDMA;
1552 } else {
1553 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1554 if (rc < 0) {
4ff96fa6 1555 if (netif_msg_probe(tp)) {
9b91cf9d 1556 dev_err(&pdev->dev,
4ff96fa6
FR		 1557 "DMA configuration failed.\n");
1558 }
1559 goto err_out_free_res_4;
1da177e4
LT		 1560 }
1561 }
1562
1563 pci_set_master(pdev);
1564
1565 /* ioremap MMIO region */
bcf0bf90 1566 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1567 if (!ioaddr) {
b57b7e5a 1568 if (netif_msg_probe(tp))
9b91cf9d 1569 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1570 rc = -EIO;
4ff96fa6 1571 goto err_out_free_res_4;
1da177e4
LT		 1572 }
1573
1574 /* Unneeded ? Don't mess with Mrs. Murphy. */
1575 rtl8169_irq_mask_and_ack(ioaddr);
1576
1577 /* Soft reset the chip. */
1578 RTL_W8(ChipCmd, CmdReset);
1579
1580 /* Check that the chip has finished the reset. */
07d3f51f 1581 for (i = 0; i < 100; i++) {
1da177e4
LT		 1582 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1583 break;
b518fa8e 1584 msleep_interruptible(1);
1da177e4
LT		 1585 }
1586
1587 /* Identify chip attached to board */
1588 rtl8169_get_mac_version(tp, ioaddr);
1589 rtl8169_get_phy_version(tp, ioaddr);
1590
1591 rtl8169_print_mac_version(tp);
1592 rtl8169_print_phy_version(tp);
1593
1594 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1595 if (tp->mac_version == rtl_chip_info[i].mac_version)
1596 break;
1597 }
1598 if (i < 0) {
1599 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1600 if (netif_msg_probe(tp)) {
2e8a538d 1601 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1602 "unknown chip version, assuming %s\n",
1603 rtl_chip_info[0].name);
b57b7e5a 1604 }
1da177e4
LT		 1605 i++;
1606 }
1607 tp->chipset = i;
1608
5d06a99f
FR		 1609 RTL_W8(Cfg9346, Cfg9346_Unlock);
1610 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1611 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1612 RTL_W8(Cfg9346, Cfg9346_Lock);
1613
1da177e4
LT		 1614 if (RTL_R8(PHYstatus) & TBI_Enable) {
1615 tp->set_speed = rtl8169_set_speed_tbi;
1616 tp->get_settings = rtl8169_gset_tbi;
1617 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1618 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1619 tp->link_ok = rtl8169_tbi_link_ok;
1620
64e4bfb4 1621 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1622 } else {
1623 tp->set_speed = rtl8169_set_speed_xmii;
1624 tp->get_settings = rtl8169_gset_xmii;
1625 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1626 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1627 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1628
1629 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1630 }
1631
1632 /* Get MAC address. FIXME: read EEPROM */
1633 for (i = 0; i < MAC_ADDR_LEN; i++)
1634 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1635 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1636
1637 dev->open = rtl8169_open;
1638 dev->hard_start_xmit = rtl8169_start_xmit;
1639 dev->get_stats = rtl8169_get_stats;
1640 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1641 dev->stop = rtl8169_close;
1642 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1643 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1644 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1645 dev->irq = pdev->irq;
1646 dev->base_addr = (unsigned long) ioaddr;
1647 dev->change_mtu = rtl8169_change_mtu;
773d2021 1648 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1649
1650#ifdef CONFIG_R8169_NAPI
1651 dev->poll = rtl8169_poll;
1652 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1653#endif
1654
1655#ifdef CONFIG_R8169_VLAN
1656 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1657 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1658#endif
1659
1660#ifdef CONFIG_NET_POLL_CONTROLLER
1661 dev->poll_controller = rtl8169_netpoll;
1662#endif
1663
1664 tp->intr_mask = 0xffff;
1665 tp->pci_dev = pdev;
1666 tp->mmio_addr = ioaddr;
0e485150
FR		 1667 tp->align = cfg->align;
1668 tp->hw_start = cfg->hw_start;
1669 tp->intr_event = cfg->intr_event;
1670 tp->napi_event = cfg->napi_event;
1da177e4 1671
2efa53f3
FR		 1672 init_timer(&tp->timer);
1673 tp->timer.data = (unsigned long) dev;
1674 tp->timer.function = rtl8169_phy_timer;
1675
1da177e4
LT		 1676 spin_lock_init(&tp->lock);
1677
1678 rc = register_netdev(dev);
4ff96fa6
FR		 1679 if (rc < 0)
1680 goto err_out_unmap_5;
1da177e4
LT		 1681
1682 pci_set_drvdata(pdev, dev);
1683
b57b7e5a 1684 if (netif_msg_probe(tp)) {
96b9709c
FR		 1685 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1686
b57b7e5a
SH		 1687 printk(KERN_INFO "%s: %s at 0x%lx, "
1688 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1689 "XID %08x IRQ %d\n",
b57b7e5a 1690 dev->name,
bcf0bf90 1691 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1692 dev->base_addr,
1693 dev->dev_addr[0], dev->dev_addr[1],
1694 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1695 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1696 }
1da177e4 1697
4ff96fa6 1698 rtl8169_init_phy(dev, tp);
1da177e4 1699
4ff96fa6
FR		 1700out:
1701 return rc;
1da177e4 1702
4ff96fa6
FR		 1703err_out_unmap_5:
1704 iounmap(ioaddr);
1705err_out_free_res_4:
1706 pci_release_regions(pdev);
1707err_out_mwi_3:
1708 pci_clear_mwi(pdev);
1709err_out_disable_2:
1710 pci_disable_device(pdev);
1711err_out_free_dev_1:
1712 free_netdev(dev);
1713 goto out;
1da177e4
LT		 1714}
1715
07d3f51f 1716static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1717{
1718 struct net_device *dev = pci_get_drvdata(pdev);
1719 struct rtl8169_private *tp = netdev_priv(dev);
1720
eb2a021c
FR		 1721 flush_scheduled_work();
1722
1da177e4
LT		 1723 unregister_netdev(dev);
1724 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1725 pci_set_drvdata(pdev, NULL);
1726}
1727
1da177e4
LT		 1728static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1729 struct net_device *dev)
1730{
1731 unsigned int mtu = dev->mtu;
1732
1733 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1734}
1735
1736static int rtl8169_open(struct net_device *dev)
1737{
1738 struct rtl8169_private *tp = netdev_priv(dev);
1739 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1740 int retval = -ENOMEM;
1da177e4 1741
1da177e4 1742
99f252b0 1743 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1744
1745 /*
1746 * Rx and Tx desscriptors needs 256 bytes alignment.
1747 * pci_alloc_consistent provides more.
1748 */
1749 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1750 &tp->TxPhyAddr);
1751 if (!tp->TxDescArray)
99f252b0 1752 goto out;
1da177e4
LT		 1753
1754 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1755 &tp->RxPhyAddr);
1756 if (!tp->RxDescArray)
99f252b0 1757 goto err_free_tx_0;
1da177e4
LT		 1758
1759 retval = rtl8169_init_ring(dev);
1760 if (retval < 0)
99f252b0 1761 goto err_free_rx_1;
1da177e4 1762
c4028958 1763 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1764
99f252b0
FR		 1765 smp_mb();
1766
1767 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1768 dev->name, dev);
1769 if (retval < 0)
1770 goto err_release_ring_2;
1771
07ce4064 1772 rtl_hw_start(dev);
1da177e4
LT		 1773
1774 rtl8169_request_timer(dev);
1775
1776 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1777out:
1778 return retval;
1779
99f252b0
FR		 1780err_release_ring_2:
1781 rtl8169_rx_clear(tp);
1782err_free_rx_1:
1da177e4
LT		 1783 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1784 tp->RxPhyAddr);
99f252b0 1785err_free_tx_0:
1da177e4
LT		 1786 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1787 tp->TxPhyAddr);
1da177e4
LT		 1788 goto out;
1789}
1790
1791static void rtl8169_hw_reset(void __iomem *ioaddr)
1792{
1793 /* Disable interrupts */
1794 rtl8169_irq_mask_and_ack(ioaddr);
1795
1796 /* Reset the chipset */
1797 RTL_W8(ChipCmd, CmdReset);
1798
1799 /* PCI commit */
1800 RTL_R8(ChipCmd);
1801}
1802
7f796d83 1803static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1804{
1805 void __iomem *ioaddr = tp->mmio_addr;
1806 u32 cfg = rtl8169_rx_config;
1807
1808 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1809 RTL_W32(RxConfig, cfg);
1810
1811 /* Set DMA burst size and Interframe Gap Time */
1812 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1813 (InterFrameGap << TxInterFrameGapShift));
1814}
1815
07ce4064 1816static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1817{
1818 struct rtl8169_private *tp = netdev_priv(dev);
1819 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1820 unsigned int i;
1da177e4
LT		 1821
1822 /* Soft reset the chip. */
1823 RTL_W8(ChipCmd, CmdReset);
1824
1825 /* Check that the chip has finished the reset. */
07d3f51f 1826 for (i = 0; i < 100; i++) {
1da177e4
LT		 1827 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1828 break;
b518fa8e 1829 msleep_interruptible(1);
1da177e4
LT		 1830 }
1831
07ce4064
FR		 1832 tp->hw_start(dev);
1833
07ce4064
FR		 1834 netif_start_queue(dev);
1835}
1836
1837
7f796d83
FR		 1838static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1839 void __iomem *ioaddr)
1840{
1841 /*
1842 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1843 * register to be written before TxDescAddrLow to work.
1844 * Switching from MMIO to I/O access fixes the issue as well.
1845 */
1846 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1847 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1848 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1849 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1850}
1851
1852static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1853{
1854 u16 cmd;
1855
1856 cmd = RTL_R16(CPlusCmd);
1857 RTL_W16(CPlusCmd, cmd);
1858 return cmd;
1859}
1860
1861static void rtl_set_rx_max_size(void __iomem *ioaddr)
1862{
1863 /* Low hurts. Let's disable the filtering. */
1864 RTL_W16(RxMaxSize, 16383);
1865}
1866
6dccd16b
FR		 1867static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1868{
1869 struct {
1870 u32 mac_version;
1871 u32 clk;
1872 u32 val;
1873 } cfg2_info [] = {
1874 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1875 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1876 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1877 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1878 }, *p = cfg2_info;
1879 unsigned int i;
1880 u32 clk;
1881
1882 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1883 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1884 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1885 RTL_W32(0x7c, p->val);
1886 break;
1887 }
1888 }
1889}
1890
07ce4064
FR		 1891static void rtl_hw_start_8169(struct net_device *dev)
1892{
1893 struct rtl8169_private *tp = netdev_priv(dev);
1894 void __iomem *ioaddr = tp->mmio_addr;
1895 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1896
9cb427b6
FR		 1897 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1898 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1899 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1900 }
1901
1da177e4 1902 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1903 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1904 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1905 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1906 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1907 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1908
1da177e4
LT		 1909 RTL_W8(EarlyTxThres, EarlyTxThld);
1910
7f796d83 1911 rtl_set_rx_max_size(ioaddr);
1da177e4 1912
6dccd16b 1913 rtl_set_rx_tx_config_registers(tp);
1da177e4 1914
7f796d83 1915 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1916
bcf0bf90
FR		 1917 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1918 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1919 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1920 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1921 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1922 }
1923
bcf0bf90
FR		 1924 RTL_W16(CPlusCmd, tp->cp_cmd);
1925
6dccd16b
FR		 1926 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1927
1da177e4
LT		 1928 /*
1929 * Undocumented corner. Supposedly:
1930 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1931 */
1932 RTL_W16(IntrMitigate, 0x0000);
1933
7f796d83 1934 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1935
1da177e4 1936 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1937
1938 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1939 RTL_R8(IntrMask);
1da177e4
LT		 1940
1941 RTL_W32(RxMissed, 0);
1942
07ce4064 1943 rtl_set_rx_mode(dev);
1da177e4
LT		 1944
1945 /* no early-rx interrupts */
1946 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 1947
1948 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 1949 RTL_W16(IntrMask, tp->intr_event);
6dccd16b
FR		 1950
1951 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 1952}
1da177e4 1953
07ce4064
FR		 1954static void rtl_hw_start_8168(struct net_device *dev)
1955{
2dd99530
FR		 1956 struct rtl8169_private *tp = netdev_priv(dev);
1957 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1958 struct pci_dev *pdev = tp->pci_dev;
1959 u8 ctl;
2dd99530
FR		 1960
1961 RTL_W8(Cfg9346, Cfg9346_Unlock);
1962
1963 RTL_W8(EarlyTxThres, EarlyTxThld);
1964
1965 rtl_set_rx_max_size(ioaddr);
1966
0e485150
FR		 1967 rtl_set_rx_tx_config_registers(tp);
1968
1969 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 1970
1971 RTL_W16(CPlusCmd, tp->cp_cmd);
1972
0e485150
FR		 1973 /* Tx performance tweak. */
1974 pci_read_config_byte(pdev, 0x69, &ctl);
1975 ctl = (ctl & ~0x70) | 0x50;
1976 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 1977
0e485150 1978 RTL_W16(IntrMitigate, 0x5151);
2dd99530 1979
0e485150
FR		 1980 /* Work around for RxFIFO overflow. */
1981 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1982 tp->intr_event |= RxFIFOOver | PCSTimeout;
1983 tp->intr_event &= ~RxOverflow;
1984 }
1985
1986 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 1987
1988 RTL_W8(Cfg9346, Cfg9346_Lock);
1989
1990 RTL_R8(IntrMask);
1991
1992 RTL_W32(RxMissed, 0);
1993
1994 rtl_set_rx_mode(dev);
1995
0e485150
FR		 1996 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1997
2dd99530 1998 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 1999
0e485150 2000 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2001}
1da177e4 2002
07ce4064
FR		 2003static void rtl_hw_start_8101(struct net_device *dev)
2004{
cdf1a608
FR		 2005 struct rtl8169_private *tp = netdev_priv(dev);
2006 void __iomem *ioaddr = tp->mmio_addr;
2007 struct pci_dev *pdev = tp->pci_dev;
2008
2009 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2010 pci_write_config_word(pdev, 0x68, 0x00);
2011 pci_write_config_word(pdev, 0x69, 0x08);
2012 }
2013
2014 RTL_W8(Cfg9346, Cfg9346_Unlock);
2015
2016 RTL_W8(EarlyTxThres, EarlyTxThld);
2017
2018 rtl_set_rx_max_size(ioaddr);
2019
2020 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2021
2022 RTL_W16(CPlusCmd, tp->cp_cmd);
2023
2024 RTL_W16(IntrMitigate, 0x0000);
2025
2026 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2027
2028 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2029 rtl_set_rx_tx_config_registers(tp);
2030
2031 RTL_W8(Cfg9346, Cfg9346_Lock);
2032
2033 RTL_R8(IntrMask);
2034
2035 RTL_W32(RxMissed, 0);
2036
2037 rtl_set_rx_mode(dev);
2038
0e485150
FR		 2039 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2040
cdf1a608 2041 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2042
0e485150 2043 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2044}
2045
2046static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2047{
2048 struct rtl8169_private *tp = netdev_priv(dev);
2049 int ret = 0;
2050
2051 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2052 return -EINVAL;
2053
2054 dev->mtu = new_mtu;
2055
2056 if (!netif_running(dev))
2057 goto out;
2058
2059 rtl8169_down(dev);
2060
2061 rtl8169_set_rxbufsize(tp, dev);
2062
2063 ret = rtl8169_init_ring(dev);
2064 if (ret < 0)
2065 goto out;
2066
2067 netif_poll_enable(dev);
2068
07ce4064 2069 rtl_hw_start(dev);
1da177e4
LT		 2070
2071 rtl8169_request_timer(dev);
2072
2073out:
2074 return ret;
2075}
2076
2077static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2078{
2079 desc->addr = 0x0badbadbadbadbadull;
2080 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2081}
2082
2083static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2084 struct sk_buff **sk_buff, struct RxDesc *desc)
2085{
2086 struct pci_dev *pdev = tp->pci_dev;
2087
2088 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2089 PCI_DMA_FROMDEVICE);
2090 dev_kfree_skb(*sk_buff);
2091 *sk_buff = NULL;
2092 rtl8169_make_unusable_by_asic(desc);
2093}
2094
2095static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2096{
2097 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2098
2099 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2100}
2101
2102static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2103 u32 rx_buf_sz)
2104{
2105 desc->addr = cpu_to_le64(mapping);
2106 wmb();
2107 rtl8169_mark_to_asic(desc, rx_buf_sz);
2108}
2109
15d31758
SH		 2110static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2111 struct net_device *dev,
2112 struct RxDesc *desc, int rx_buf_sz,
2113 unsigned int align)
1da177e4
LT		 2114{
2115 struct sk_buff *skb;
2116 dma_addr_t mapping;
e9f63f30 2117 unsigned int pad;
1da177e4 2118
e9f63f30
FR		 2119 pad = align ? align : NET_IP_ALIGN;
2120
2121 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2122 if (!skb)
2123 goto err_out;
2124
e9f63f30 2125 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2126
689be439 2127 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2128 PCI_DMA_FROMDEVICE);
2129
2130 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2131out:
15d31758 2132 return skb;
1da177e4
LT		 2133
2134err_out:
1da177e4
LT		 2135 rtl8169_make_unusable_by_asic(desc);
2136 goto out;
2137}
2138
2139static void rtl8169_rx_clear(struct rtl8169_private *tp)
2140{
07d3f51f 2141 unsigned int i;
1da177e4
LT		 2142
2143 for (i = 0; i < NUM_RX_DESC; i++) {
2144 if (tp->Rx_skbuff[i]) {
2145 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2146 tp->RxDescArray + i);
2147 }
2148 }
2149}
2150
2151static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2152 u32 start, u32 end)
2153{
2154 u32 cur;
5b0384f4 2155
4ae47c2d 2156 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2157 struct sk_buff *skb;
2158 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2159
4ae47c2d
FR		 2160 WARN_ON((s32)(end - cur) < 0);
2161
1da177e4
LT		 2162 if (tp->Rx_skbuff[i])
2163 continue;
bcf0bf90 2164
15d31758
SH		 2165 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2166 tp->RxDescArray + i,
2167 tp->rx_buf_sz, tp->align);
2168 if (!skb)
1da177e4 2169 break;
15d31758
SH		 2170
2171 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2172 }
2173 return cur - start;
2174}
2175
2176static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2177{
2178 desc->opts1 |= cpu_to_le32(RingEnd);
2179}
2180
2181static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2182{
2183 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2184}
2185
2186static int rtl8169_init_ring(struct net_device *dev)
2187{
2188 struct rtl8169_private *tp = netdev_priv(dev);
2189
2190 rtl8169_init_ring_indexes(tp);
2191
2192 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2193 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2194
2195 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2196 goto err_out;
2197
2198 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2199
2200 return 0;
2201
2202err_out:
2203 rtl8169_rx_clear(tp);
2204 return -ENOMEM;
2205}
2206
2207static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2208 struct TxDesc *desc)
2209{
2210 unsigned int len = tx_skb->len;
2211
2212 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2213 desc->opts1 = 0x00;
2214 desc->opts2 = 0x00;
2215 desc->addr = 0x00;
2216 tx_skb->len = 0;
2217}
2218
2219static void rtl8169_tx_clear(struct rtl8169_private *tp)
2220{
2221 unsigned int i;
2222
2223 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2224 unsigned int entry = i % NUM_TX_DESC;
2225 struct ring_info *tx_skb = tp->tx_skb + entry;
2226 unsigned int len = tx_skb->len;
2227
2228 if (len) {
2229 struct sk_buff *skb = tx_skb->skb;
2230
2231 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2232 tp->TxDescArray + entry);
2233 if (skb) {
2234 dev_kfree_skb(skb);
2235 tx_skb->skb = NULL;
2236 }
2237 tp->stats.tx_dropped++;
2238 }
2239 }
2240 tp->cur_tx = tp->dirty_tx = 0;
2241}
2242
c4028958 2243static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2244{
2245 struct rtl8169_private *tp = netdev_priv(dev);
2246
c4028958 2247 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2248 schedule_delayed_work(&tp->task, 4);
2249}
2250
2251static void rtl8169_wait_for_quiescence(struct net_device *dev)
2252{
2253 struct rtl8169_private *tp = netdev_priv(dev);
2254 void __iomem *ioaddr = tp->mmio_addr;
2255
2256 synchronize_irq(dev->irq);
2257
2258 /* Wait for any pending NAPI task to complete */
2259 netif_poll_disable(dev);
2260
2261 rtl8169_irq_mask_and_ack(ioaddr);
2262
2263 netif_poll_enable(dev);
2264}
2265
c4028958 2266static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2267{
c4028958
DH		 2268 struct rtl8169_private *tp =
2269 container_of(work, struct rtl8169_private, task.work);
2270 struct net_device *dev = tp->dev;
1da177e4
LT		 2271 int ret;
2272
eb2a021c
FR		 2273 rtnl_lock();
2274
2275 if (!netif_running(dev))
2276 goto out_unlock;
2277
2278 rtl8169_wait_for_quiescence(dev);
2279 rtl8169_close(dev);
1da177e4
LT		 2280
2281 ret = rtl8169_open(dev);
2282 if (unlikely(ret < 0)) {
07d3f51f
FR		 2283 if (net_ratelimit() && netif_msg_drv(tp)) {
2284 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2285 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2286 }
2287 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2288 }
eb2a021c
FR		 2289
2290out_unlock:
2291 rtnl_unlock();
1da177e4
LT		 2292}
2293
c4028958 2294static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2295{
c4028958
DH		 2296 struct rtl8169_private *tp =
2297 container_of(work, struct rtl8169_private, task.work);
2298 struct net_device *dev = tp->dev;
1da177e4 2299
eb2a021c
FR		 2300 rtnl_lock();
2301
1da177e4 2302 if (!netif_running(dev))
eb2a021c 2303 goto out_unlock;
1da177e4
LT		 2304
2305 rtl8169_wait_for_quiescence(dev);
2306
2307 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2308 rtl8169_tx_clear(tp);
2309
2310 if (tp->dirty_rx == tp->cur_rx) {
2311 rtl8169_init_ring_indexes(tp);
07ce4064 2312 rtl_hw_start(dev);
1da177e4
LT		 2313 netif_wake_queue(dev);
2314 } else {
07d3f51f
FR		 2315 if (net_ratelimit() && netif_msg_intr(tp)) {
2316 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2317 dev->name);
1da177e4
LT		 2318 }
2319 rtl8169_schedule_work(dev, rtl8169_reset_task);
2320 }
eb2a021c
FR		 2321
2322out_unlock:
2323 rtnl_unlock();
1da177e4
LT		 2324}
2325
2326static void rtl8169_tx_timeout(struct net_device *dev)
2327{
2328 struct rtl8169_private *tp = netdev_priv(dev);
2329
2330 rtl8169_hw_reset(tp->mmio_addr);
2331
2332 /* Let's wait a bit while any (async) irq lands on */
2333 rtl8169_schedule_work(dev, rtl8169_reset_task);
2334}
2335
2336static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2337 u32 opts1)
2338{
2339 struct skb_shared_info *info = skb_shinfo(skb);
2340 unsigned int cur_frag, entry;
a6343afb 2341 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2342
2343 entry = tp->cur_tx;
2344 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2345 skb_frag_t *frag = info->frags + cur_frag;
2346 dma_addr_t mapping;
2347 u32 status, len;
2348 void *addr;
2349
2350 entry = (entry + 1) % NUM_TX_DESC;
2351
2352 txd = tp->TxDescArray + entry;
2353 len = frag->size;
2354 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2355 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2356
2357 /* anti gcc 2.95.3 bugware (sic) */
2358 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2359
2360 txd->opts1 = cpu_to_le32(status);
2361 txd->addr = cpu_to_le64(mapping);
2362
2363 tp->tx_skb[entry].len = len;
2364 }
2365
2366 if (cur_frag) {
2367 tp->tx_skb[entry].skb = skb;
2368 txd->opts1 |= cpu_to_le32(LastFrag);
2369 }
2370
2371 return cur_frag;
2372}
2373
2374static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2375{
2376 if (dev->features & NETIF_F_TSO) {
7967168c 2377 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2378
2379 if (mss)
2380 return LargeSend | ((mss & MSSMask) << MSSShift);
2381 }
84fa7933 2382 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2383 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2384
2385 if (ip->protocol == IPPROTO_TCP)
2386 return IPCS | TCPCS;
2387 else if (ip->protocol == IPPROTO_UDP)
2388 return IPCS | UDPCS;
2389 WARN_ON(1); /* we need a WARN() */
2390 }
2391 return 0;
2392}
2393
2394static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2395{
2396 struct rtl8169_private *tp = netdev_priv(dev);
2397 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2398 struct TxDesc *txd = tp->TxDescArray + entry;
2399 void __iomem *ioaddr = tp->mmio_addr;
2400 dma_addr_t mapping;
2401 u32 status, len;
2402 u32 opts1;
188f4af0 2403 int ret = NETDEV_TX_OK;
5b0384f4 2404
1da177e4 2405 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2406 if (netif_msg_drv(tp)) {
2407 printk(KERN_ERR
2408 "%s: BUG! Tx Ring full when queue awake!\n",
2409 dev->name);
2410 }
1da177e4
LT		 2411 goto err_stop;
2412 }
2413
2414 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2415 goto err_stop;
2416
2417 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2418
2419 frags = rtl8169_xmit_frags(tp, skb, opts1);
2420 if (frags) {
2421 len = skb_headlen(skb);
2422 opts1 |= FirstFrag;
2423 } else {
2424 len = skb->len;
2425
2426 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2427 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2428 goto err_update_stats;
2429 len = ETH_ZLEN;
2430 }
2431
2432 opts1 |= FirstFrag | LastFrag;
2433 tp->tx_skb[entry].skb = skb;
2434 }
2435
2436 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2437
2438 tp->tx_skb[entry].len = len;
2439 txd->addr = cpu_to_le64(mapping);
2440 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2441
2442 wmb();
2443
2444 /* anti gcc 2.95.3 bugware (sic) */
2445 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2446 txd->opts1 = cpu_to_le32(status);
2447
2448 dev->trans_start = jiffies;
2449
2450 tp->cur_tx += frags + 1;
2451
2452 smp_wmb();
2453
275391a4 2454 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2455
2456 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2457 netif_stop_queue(dev);
2458 smp_rmb();
2459 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2460 netif_wake_queue(dev);
2461 }
2462
2463out:
2464 return ret;
2465
2466err_stop:
2467 netif_stop_queue(dev);
188f4af0 2468 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2469err_update_stats:
2470 tp->stats.tx_dropped++;
2471 goto out;
2472}
2473
2474static void rtl8169_pcierr_interrupt(struct net_device *dev)
2475{
2476 struct rtl8169_private *tp = netdev_priv(dev);
2477 struct pci_dev *pdev = tp->pci_dev;
2478 void __iomem *ioaddr = tp->mmio_addr;
2479 u16 pci_status, pci_cmd;
2480
2481 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2482 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2483
b57b7e5a
SH		 2484 if (netif_msg_intr(tp)) {
2485 printk(KERN_ERR
2486 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2487 dev->name, pci_cmd, pci_status);
2488 }
1da177e4
LT		 2489
2490 /*
2491 * The recovery sequence below admits a very elaborated explanation:
2492 * - it seems to work;
d03902b8
FR		 2493 * - I did not see what else could be done;
2494 * - it makes iop3xx happy.
1da177e4
LT		 2495 *
2496 * Feel free to adjust to your needs.
2497 */
a27993f3 2498 if (pdev->broken_parity_status)
d03902b8
FR		 2499 pci_cmd &= ~PCI_COMMAND_PARITY;
2500 else
2501 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2502
2503 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2504
2505 pci_write_config_word(pdev, PCI_STATUS,
2506 pci_status & (PCI_STATUS_DETECTED_PARITY |
2507 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2508 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2509
2510 /* The infamous DAC f*ckup only happens at boot time */
2511 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2512 if (netif_msg_intr(tp))
2513 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2514 tp->cp_cmd &= ~PCIDAC;
2515 RTL_W16(CPlusCmd, tp->cp_cmd);
2516 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2517 }
2518
2519 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2520
2521 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2522}
2523
07d3f51f
FR		 2524static void rtl8169_tx_interrupt(struct net_device *dev,
2525 struct rtl8169_private *tp,
2526 void __iomem *ioaddr)
1da177e4
LT		 2527{
2528 unsigned int dirty_tx, tx_left;
2529
1da177e4
LT		 2530 dirty_tx = tp->dirty_tx;
2531 smp_rmb();
2532 tx_left = tp->cur_tx - dirty_tx;
2533
2534 while (tx_left > 0) {
2535 unsigned int entry = dirty_tx % NUM_TX_DESC;
2536 struct ring_info *tx_skb = tp->tx_skb + entry;
2537 u32 len = tx_skb->len;
2538 u32 status;
2539
2540 rmb();
2541 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2542 if (status & DescOwn)
2543 break;
2544
2545 tp->stats.tx_bytes += len;
2546 tp->stats.tx_packets++;
2547
2548 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2549
2550 if (status & LastFrag) {
2551 dev_kfree_skb_irq(tx_skb->skb);
2552 tx_skb->skb = NULL;
2553 }
2554 dirty_tx++;
2555 tx_left--;
2556 }
2557
2558 if (tp->dirty_tx != dirty_tx) {
2559 tp->dirty_tx = dirty_tx;
2560 smp_wmb();
2561 if (netif_queue_stopped(dev) &&
2562 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2563 netif_wake_queue(dev);
2564 }
2565 }
2566}
2567
126fa4b9
FR		 2568static inline int rtl8169_fragmented_frame(u32 status)
2569{
2570 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2571}
2572
1da177e4
LT		 2573static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2574{
2575 u32 opts1 = le32_to_cpu(desc->opts1);
2576 u32 status = opts1 & RxProtoMask;
2577
2578 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2579 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2580 ((status == RxProtoIP) && !(opts1 & IPFail)))
2581 skb->ip_summed = CHECKSUM_UNNECESSARY;
2582 else
2583 skb->ip_summed = CHECKSUM_NONE;
2584}
2585
07d3f51f
FR		 2586static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2587 struct rtl8169_private *tp, int pkt_size,
2588 dma_addr_t addr)
1da177e4 2589{
b449655f
SH		 2590 struct sk_buff *skb;
2591 bool done = false;
1da177e4 2592
b449655f
SH		 2593 if (pkt_size >= rx_copybreak)
2594 goto out;
1da177e4 2595
07d3f51f 2596 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2597 if (!skb)
2598 goto out;
2599
07d3f51f
FR		 2600 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2601 PCI_DMA_FROMDEVICE);
86402234 2602 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2603 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2604 *sk_buff = skb;
2605 done = true;
2606out:
2607 return done;
1da177e4
LT		 2608}
2609
07d3f51f
FR		 2610static int rtl8169_rx_interrupt(struct net_device *dev,
2611 struct rtl8169_private *tp,
2612 void __iomem *ioaddr)
1da177e4
LT		 2613{
2614 unsigned int cur_rx, rx_left;
2615 unsigned int delta, count;
2616
1da177e4
LT		 2617 cur_rx = tp->cur_rx;
2618 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2619 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2620
4dcb7d33 2621 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2622 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2623 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2624 u32 status;
2625
2626 rmb();
126fa4b9 2627 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2628
2629 if (status & DescOwn)
2630 break;
4dcb7d33 2631 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2632 if (netif_msg_rx_err(tp)) {
2633 printk(KERN_INFO
2634 "%s: Rx ERROR. status = %08x\n",
2635 dev->name, status);
2636 }
1da177e4
LT		 2637 tp->stats.rx_errors++;
2638 if (status & (RxRWT | RxRUNT))
2639 tp->stats.rx_length_errors++;
2640 if (status & RxCRC)
2641 tp->stats.rx_crc_errors++;
9dccf611
FR		 2642 if (status & RxFOVF) {
2643 rtl8169_schedule_work(dev, rtl8169_reset_task);
2644 tp->stats.rx_fifo_errors++;
2645 }
126fa4b9 2646 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2647 } else {
1da177e4 2648 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2649 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2650 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2651 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2652
126fa4b9
FR		 2653 /*
2654 * The driver does not support incoming fragmented
2655 * frames. They are seen as a symptom of over-mtu
2656 * sized frames.
2657 */
2658 if (unlikely(rtl8169_fragmented_frame(status))) {
2659 tp->stats.rx_dropped++;
2660 tp->stats.rx_length_errors++;
2661 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2662 continue;
126fa4b9
FR		 2663 }
2664
1da177e4 2665 rtl8169_rx_csum(skb, desc);
bcf0bf90 2666
07d3f51f 2667 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2668 pci_dma_sync_single_for_device(pdev, addr,
2669 pkt_size, PCI_DMA_FROMDEVICE);
2670 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2671 } else {
2672 pci_unmap_single(pdev, addr, pkt_size,
2673 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2674 tp->Rx_skbuff[entry] = NULL;
2675 }
2676
1da177e4
LT		 2677 skb_put(skb, pkt_size);
2678 skb->protocol = eth_type_trans(skb, dev);
2679
2680 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2681 rtl8169_rx_skb(skb);
2682
2683 dev->last_rx = jiffies;
2684 tp->stats.rx_bytes += pkt_size;
2685 tp->stats.rx_packets++;
2686 }
6dccd16b
FR		 2687
2688 /* Work around for AMD plateform. */
2689 if ((desc->opts2 & 0xfffe000) &&
2690 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2691 desc->opts2 = 0;
2692 cur_rx++;
2693 }
1da177e4
LT		 2694 }
2695
2696 count = cur_rx - tp->cur_rx;
2697 tp->cur_rx = cur_rx;
2698
2699 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2700 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2701 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2702 tp->dirty_rx += delta;
2703
2704 /*
2705 * FIXME: until there is periodic timer to try and refill the ring,
2706 * a temporary shortage may definitely kill the Rx process.
2707 * - disable the asic to try and avoid an overflow and kick it again
2708 * after refill ?
2709 * - how do others driver handle this condition (Uh oh...).
2710 */
b57b7e5a 2711 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2712 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2713
2714 return count;
2715}
2716
07d3f51f 2717static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2718{
07d3f51f 2719 struct net_device *dev = dev_instance;
1da177e4
LT		 2720 struct rtl8169_private *tp = netdev_priv(dev);
2721 int boguscnt = max_interrupt_work;
2722 void __iomem *ioaddr = tp->mmio_addr;
2723 int status;
2724 int handled = 0;
2725
2726 do {
2727 status = RTL_R16(IntrStatus);
2728
2729 /* hotplug/major error/no more work/shared irq */
2730 if ((status == 0xFFFF) || !status)
2731 break;
2732
2733 handled = 1;
2734
2735 if (unlikely(!netif_running(dev))) {
2736 rtl8169_asic_down(ioaddr);
2737 goto out;
2738 }
2739
2740 status &= tp->intr_mask;
2741 RTL_W16(IntrStatus,
2742 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2743
0e485150
FR		 2744 if (!(status & tp->intr_event))
2745 break;
2746
2747 /* Work around for rx fifo overflow */
2748 if (unlikely(status & RxFIFOOver) &&
2749 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2750 netif_stop_queue(dev);
2751 rtl8169_tx_timeout(dev);
1da177e4 2752 break;
0e485150 2753 }
1da177e4
LT		 2754
2755 if (unlikely(status & SYSErr)) {
2756 rtl8169_pcierr_interrupt(dev);
2757 break;
2758 }
2759
2760 if (status & LinkChg)
2761 rtl8169_check_link_status(dev, tp, ioaddr);
2762
2763#ifdef CONFIG_R8169_NAPI
0e485150
FR		 2764 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2765 tp->intr_mask = ~tp->napi_event;
1da177e4
LT		 2766
2767 if (likely(netif_rx_schedule_prep(dev)))
2768 __netif_rx_schedule(dev);
b57b7e5a 2769 else if (netif_msg_intr(tp)) {
1da177e4 2770 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2771 dev->name, status);
1da177e4
LT		 2772 }
2773 break;
2774#else
2775 /* Rx interrupt */
07d3f51f 2776 if (status & (RxOK | RxOverflow | RxFIFOOver))
1da177e4 2777 rtl8169_rx_interrupt(dev, tp, ioaddr);
07d3f51f 2778
1da177e4
LT		 2779 /* Tx interrupt */
2780 if (status & (TxOK | TxErr))
2781 rtl8169_tx_interrupt(dev, tp, ioaddr);
2782#endif
2783
2784 boguscnt--;
2785 } while (boguscnt > 0);
2786
2787 if (boguscnt <= 0) {
7c8b2eb4 2788 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2789 printk(KERN_WARNING
2790 "%s: Too much work at interrupt!\n", dev->name);
2791 }
1da177e4
LT		 2792 /* Clear all interrupt sources. */
2793 RTL_W16(IntrStatus, 0xffff);
2794 }
2795out:
2796 return IRQ_RETVAL(handled);
2797}
2798
2799#ifdef CONFIG_R8169_NAPI
2800static int rtl8169_poll(struct net_device *dev, int *budget)
2801{
2802 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2803 struct rtl8169_private *tp = netdev_priv(dev);
2804 void __iomem *ioaddr = tp->mmio_addr;
2805
2806 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2807 rtl8169_tx_interrupt(dev, tp, ioaddr);
2808
2809 *budget -= work_done;
2810 dev->quota -= work_done;
2811
2812 if (work_done < work_to_do) {
2813 netif_rx_complete(dev);
2814 tp->intr_mask = 0xffff;
2815 /*
2816 * 20040426: the barrier is not strictly required but the
2817 * behavior of the irq handler could be less predictable
2818 * without it. Btw, the lack of flush for the posted pci
2819 * write is safe - FR
2820 */
2821 smp_wmb();
0e485150 2822 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2823 }
2824
2825 return (work_done >= work_to_do);
2826}
2827#endif
2828
2829static void rtl8169_down(struct net_device *dev)
2830{
2831 struct rtl8169_private *tp = netdev_priv(dev);
2832 void __iomem *ioaddr = tp->mmio_addr;
2833 unsigned int poll_locked = 0;
733b736c 2834 unsigned int intrmask;
1da177e4
LT		 2835
2836 rtl8169_delete_timer(dev);
2837
2838 netif_stop_queue(dev);
2839
1da177e4
LT		 2840core_down:
2841 spin_lock_irq(&tp->lock);
2842
2843 rtl8169_asic_down(ioaddr);
2844
2845 /* Update the error counts. */
2846 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2847 RTL_W32(RxMissed, 0);
2848
2849 spin_unlock_irq(&tp->lock);
2850
2851 synchronize_irq(dev->irq);
2852
2853 if (!poll_locked) {
2854 netif_poll_disable(dev);
2855 poll_locked++;
2856 }
2857
2858 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2859 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2860
2861 /*
2862 * And now for the 50k$ question: are IRQ disabled or not ?
2863 *
2864 * Two paths lead here:
2865 * 1) dev->close
2866 * -> netif_running() is available to sync the current code and the
2867 * IRQ handler. See rtl8169_interrupt for details.
2868 * 2) dev->change_mtu
2869 * -> rtl8169_poll can not be issued again and re-enable the
2870 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2871 *
2872 * No loop if hotpluged or major error (0xffff).
1da177e4 2873 */
733b736c
AP		 2874 intrmask = RTL_R16(IntrMask);
2875 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2876 goto core_down;
2877
2878 rtl8169_tx_clear(tp);
2879
2880 rtl8169_rx_clear(tp);
2881}
2882
2883static int rtl8169_close(struct net_device *dev)
2884{
2885 struct rtl8169_private *tp = netdev_priv(dev);
2886 struct pci_dev *pdev = tp->pci_dev;
2887
2888 rtl8169_down(dev);
2889
2890 free_irq(dev->irq, dev);
2891
2892 netif_poll_enable(dev);
2893
2894 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2895 tp->RxPhyAddr);
2896 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2897 tp->TxPhyAddr);
2898 tp->TxDescArray = NULL;
2899 tp->RxDescArray = NULL;
2900
2901 return 0;
2902}
2903
07ce4064 2904static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2905{
2906 struct rtl8169_private *tp = netdev_priv(dev);
2907 void __iomem *ioaddr = tp->mmio_addr;
2908 unsigned long flags;
2909 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2910 int rx_mode;
1da177e4
LT		 2911 u32 tmp = 0;
2912
2913 if (dev->flags & IFF_PROMISC) {
2914 /* Unconditionally log net taps. */
b57b7e5a
SH		 2915 if (netif_msg_link(tp)) {
2916 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2917 dev->name);
2918 }
1da177e4
LT		 2919 rx_mode =
2920 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2921 AcceptAllPhys;
2922 mc_filter[1] = mc_filter[0] = 0xffffffff;
2923 } else if ((dev->mc_count > multicast_filter_limit)
2924 || (dev->flags & IFF_ALLMULTI)) {
2925 /* Too many to filter perfectly -- accept all multicasts. */
2926 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2927 mc_filter[1] = mc_filter[0] = 0xffffffff;
2928 } else {
2929 struct dev_mc_list *mclist;
07d3f51f
FR		 2930 unsigned int i;
2931
1da177e4
LT		 2932 rx_mode = AcceptBroadcast | AcceptMyPhys;
2933 mc_filter[1] = mc_filter[0] = 0;
2934 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2935 i++, mclist = mclist->next) {
2936 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2937 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2938 rx_mode |= AcceptMulticast;
2939 }
2940 }
2941
2942 spin_lock_irqsave(&tp->lock, flags);
2943
2944 tmp = rtl8169_rx_config | rx_mode |
2945 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2946
bcf0bf90
FR		 2947 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2948 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2949 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2950 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2951 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2952 mc_filter[0] = 0xffffffff;
2953 mc_filter[1] = 0xffffffff;
2954 }
2955
1da177e4
LT		 2956 RTL_W32(MAR0 + 0, mc_filter[0]);
2957 RTL_W32(MAR0 + 4, mc_filter[1]);
2958
57a9f236
FR		 2959 RTL_W32(RxConfig, tmp);
2960
1da177e4
LT		 2961 spin_unlock_irqrestore(&tp->lock, flags);
2962}
2963
2964/**
2965 * rtl8169_get_stats - Get rtl8169 read/write statistics
2966 * @dev: The Ethernet Device to get statistics for
2967 *
2968 * Get TX/RX statistics for rtl8169
2969 */
2970static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2971{
2972 struct rtl8169_private *tp = netdev_priv(dev);
2973 void __iomem *ioaddr = tp->mmio_addr;
2974 unsigned long flags;
2975
2976 if (netif_running(dev)) {
2977 spin_lock_irqsave(&tp->lock, flags);
2978 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2979 RTL_W32(RxMissed, 0);
2980 spin_unlock_irqrestore(&tp->lock, flags);
2981 }
5b0384f4 2982
1da177e4
LT		 2983 return &tp->stats;
2984}
2985
5d06a99f
FR		 2986#ifdef CONFIG_PM
2987
2988static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2989{
2990 struct net_device *dev = pci_get_drvdata(pdev);
2991 struct rtl8169_private *tp = netdev_priv(dev);
2992 void __iomem *ioaddr = tp->mmio_addr;
2993
2994 if (!netif_running(dev))
1371fa6d 2995 goto out_pci_suspend;
5d06a99f
FR		 2996
2997 netif_device_detach(dev);
2998 netif_stop_queue(dev);
2999
3000 spin_lock_irq(&tp->lock);
3001
3002 rtl8169_asic_down(ioaddr);
3003
3004 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3005 RTL_W32(RxMissed, 0);
3006
3007 spin_unlock_irq(&tp->lock);
3008
1371fa6d 3009out_pci_suspend:
5d06a99f 3010 pci_save_state(pdev);
61a4dcc2 3011 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 3012 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3013
5d06a99f
FR		 3014 return 0;
3015}
3016
3017static int rtl8169_resume(struct pci_dev *pdev)
3018{
3019 struct net_device *dev = pci_get_drvdata(pdev);
3020
1371fa6d
FR		 3021 pci_set_power_state(pdev, PCI_D0);
3022 pci_restore_state(pdev);
3023 pci_enable_wake(pdev, PCI_D0, 0);
3024
5d06a99f
FR		 3025 if (!netif_running(dev))
3026 goto out;
3027
3028 netif_device_attach(dev);
3029
5d06a99f
FR		 3030 rtl8169_schedule_work(dev, rtl8169_reset_task);
3031out:
3032 return 0;
3033}
3034
3035#endif /* CONFIG_PM */
3036
1da177e4
LT		 3037static struct pci_driver rtl8169_pci_driver = {
3038 .name = MODULENAME,
3039 .id_table = rtl8169_pci_tbl,
3040 .probe = rtl8169_init_one,
3041 .remove = __devexit_p(rtl8169_remove_one),
3042#ifdef CONFIG_PM
3043 .suspend = rtl8169_suspend,
3044 .resume = rtl8169_resume,
3045#endif
3046};
3047
07d3f51f 3048static int __init rtl8169_init_module(void)
1da177e4 3049{
29917620 3050 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3051}
3052
07d3f51f 3053static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3054{
3055 pci_unregister_driver(&rtl8169_pci_driver);
3056}
3057
3058module_init(rtl8169_init_module);
3059module_exit(rtl8169_cleanup_module);
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