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r8169: display some extra debug information during startup
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
1da177e4
LT		 47#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59#ifdef CONFIG_R8169_NAPI
60#define rtl8169_rx_skb netif_receive_skb
0b50f81d 61#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 62#define rtl8169_rx_quota(count, quota) min(count, quota)
63#else
64#define rtl8169_rx_skb netif_rx
0b50f81d 65#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 66#define rtl8169_rx_quota(count, quota) count
67#endif
68
1da177e4 69/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 70static const int max_interrupt_work = 20;
1da177e4
LT		 71
72/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 74static const int multicast_filter_limit = 32;
1da177e4
LT		 75
76/* MAC address length */
77#define MAC_ADDR_LEN 6
78
79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 83#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87#define R8169_REGS_SIZE 256
88#define R8169_NAPI_WEIGHT 64
89#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91#define RX_BUF_SIZE 1536 /* Rx Buffer size */
92#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94
95#define RTL8169_TX_TIMEOUT (6*HZ)
96#define RTL8169_PHY_TIMEOUT (10*HZ)
97
98/* write/read MMIO register */
99#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb (ioaddr + (reg))
103#define RTL_R16(reg) readw (ioaddr + (reg))
104#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
105
106enum mac_version {
ba6eb6ee
FR		 107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 118};
119
120enum phy_version {
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
127};
128
1da177e4
LT		 129#define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131
3c6bee1d 132static const struct {
1da177e4
LT		 133 const char *name;
134 u8 mac_version;
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136} rtl_chip_info[] = {
ba6eb6ee
FR		 137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 148};
149#undef _R
150
bcf0bf90
FR		 151enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155};
156
07ce4064
FR		 157static void rtl_hw_start_8169(struct net_device *);
158static void rtl_hw_start_8168(struct net_device *);
159static void rtl_hw_start_8101(struct net_device *);
160
1da177e4 161static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 172 {0,},
173};
174
175MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176
177static int rx_copybreak = 200;
178static int use_dac;
b57b7e5a
SH		 179static struct {
180 u32 msg_enable;
181} debug = { -1 };
1da177e4 182
07d3f51f
FR		 183enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
185 MAR0 = 8, /* Multicast filter. */
186 CounterAddrLow = 0x10,
187 CounterAddrHigh = 0x14,
188 TxDescStartAddrLow = 0x20,
189 TxDescStartAddrHigh = 0x24,
190 TxHDescStartAddrLow = 0x28,
191 TxHDescStartAddrHigh = 0x2c,
192 FLASH = 0x30,
193 ERSR = 0x36,
194 ChipCmd = 0x37,
195 TxPoll = 0x38,
196 IntrMask = 0x3c,
197 IntrStatus = 0x3e,
198 TxConfig = 0x40,
199 RxConfig = 0x44,
200 RxMissed = 0x4c,
201 Cfg9346 = 0x50,
202 Config0 = 0x51,
203 Config1 = 0x52,
204 Config2 = 0x53,
205 Config3 = 0x54,
206 Config4 = 0x55,
207 Config5 = 0x56,
208 MultiIntr = 0x5c,
209 PHYAR = 0x60,
210 TBICSR = 0x64,
211 TBI_ANAR = 0x68,
212 TBI_LPAR = 0x6a,
213 PHYstatus = 0x6c,
214 RxMaxSize = 0xda,
215 CPlusCmd = 0xe0,
216 IntrMitigate = 0xe2,
217 RxDescAddrLow = 0xe4,
218 RxDescAddrHigh = 0xe8,
219 EarlyTxThres = 0xec,
220 FuncEvent = 0xf0,
221 FuncEventMask = 0xf4,
222 FuncPresetState = 0xf8,
223 FuncForceEvent = 0xfc,
1da177e4
LT		 224};
225
07d3f51f 226enum rtl_register_content {
1da177e4 227 /* InterruptStatusBits */
07d3f51f
FR		 228 SYSErr = 0x8000,
229 PCSTimeout = 0x4000,
230 SWInt = 0x0100,
231 TxDescUnavail = 0x0080,
232 RxFIFOOver = 0x0040,
233 LinkChg = 0x0020,
234 RxOverflow = 0x0010,
235 TxErr = 0x0008,
236 TxOK = 0x0004,
237 RxErr = 0x0002,
238 RxOK = 0x0001,
1da177e4
LT		 239
240 /* RxStatusDesc */
9dccf611
FR		 241 RxFOVF = (1 << 23),
242 RxRWT = (1 << 22),
243 RxRES = (1 << 21),
244 RxRUNT = (1 << 20),
245 RxCRC = (1 << 19),
1da177e4
LT		 246
247 /* ChipCmdBits */
07d3f51f
FR		 248 CmdReset = 0x10,
249 CmdRxEnb = 0x08,
250 CmdTxEnb = 0x04,
251 RxBufEmpty = 0x01,
1da177e4 252
275391a4
FR		 253 /* TXPoll register p.5 */
254 HPQ = 0x80, /* Poll cmd on the high prio queue */
255 NPQ = 0x40, /* Poll cmd on the low prio queue */
256 FSWInt = 0x01, /* Forced software interrupt */
257
1da177e4 258 /* Cfg9346Bits */
07d3f51f
FR		 259 Cfg9346_Lock = 0x00,
260 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 261
262 /* rx_mode_bits */
07d3f51f
FR		 263 AcceptErr = 0x20,
264 AcceptRunt = 0x10,
265 AcceptBroadcast = 0x08,
266 AcceptMulticast = 0x04,
267 AcceptMyPhys = 0x02,
268 AcceptAllPhys = 0x01,
1da177e4
LT		 269
270 /* RxConfigBits */
07d3f51f
FR		 271 RxCfgFIFOShift = 13,
272 RxCfgDMAShift = 8,
1da177e4
LT		 273
274 /* TxConfigBits */
275 TxInterFrameGapShift = 24,
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
5d06a99f
FR		 278 /* Config1 register p.24 */
279 PMEnable = (1 << 0), /* Power Management Enable */
280
6dccd16b
FR		 281 /* Config2 register p. 25 */
282 PCI_Clock_66MHz = 0x01,
283 PCI_Clock_33MHz = 0x00,
284
61a4dcc2
FR		 285 /* Config3 register p.25 */
286 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
287 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
288
5d06a99f 289 /* Config5 register p.27 */
61a4dcc2
FR		 290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
1da177e4
LT		 296 /* TBICSR p.28 */
297 TBIReset = 0x80000000,
298 TBILoopback = 0x40000000,
299 TBINwEnable = 0x20000000,
300 TBINwRestart = 0x10000000,
301 TBILinkOk = 0x02000000,
302 TBINwComplete = 0x01000000,
303
304 /* CPlusCmd p.31 */
0e485150 305 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 306 RxVlan = (1 << 6),
307 RxChkSum = (1 << 5),
308 PCIDAC = (1 << 4),
309 PCIMulRW = (1 << 3),
0e485150
FR		 310 INTT_0 = 0x0000, // 8168
311 INTT_1 = 0x0001, // 8168
312 INTT_2 = 0x0002, // 8168
313 INTT_3 = 0x0003, // 8168
1da177e4
LT		 314
315 /* rtl8169_PHYstatus */
07d3f51f
FR		 316 TBI_Enable = 0x80,
317 TxFlowCtrl = 0x40,
318 RxFlowCtrl = 0x20,
319 _1000bpsF = 0x10,
320 _100bps = 0x08,
321 _10bps = 0x04,
322 LinkStatus = 0x02,
323 FullDup = 0x01,
1da177e4 324
1da177e4 325 /* _TBICSRBit */
07d3f51f 326 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 327
328 /* DumpCounterCommand */
07d3f51f 329 CounterDump = 0x8,
1da177e4
LT		 330};
331
07d3f51f 332enum desc_status_bit {
1da177e4
LT		 333 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
334 RingEnd = (1 << 30), /* End of descriptor ring */
335 FirstFrag = (1 << 29), /* First segment of a packet */
336 LastFrag = (1 << 28), /* Final segment of a packet */
337
338 /* Tx private */
339 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
340 MSSShift = 16, /* MSS value position */
341 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
342 IPCS = (1 << 18), /* Calculate IP checksum */
343 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
344 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
345 TxVlanTag = (1 << 17), /* Add VLAN tag */
346
347 /* Rx private */
348 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
349 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
350
351#define RxProtoUDP (PID1)
352#define RxProtoTCP (PID0)
353#define RxProtoIP (PID1 | PID0)
354#define RxProtoMask RxProtoIP
355
356 IPFail = (1 << 16), /* IP checksum failed */
357 UDPFail = (1 << 15), /* UDP/IP checksum failed */
358 TCPFail = (1 << 14), /* TCP/IP checksum failed */
359 RxVlanTag = (1 << 16), /* VLAN tag available */
360};
361
362#define RsvdMask 0x3fffc000
363
364struct TxDesc {
6cccd6e7
REB		 365 __le32 opts1;
366 __le32 opts2;
367 __le64 addr;
1da177e4
LT		 368};
369
370struct RxDesc {
6cccd6e7
REB		 371 __le32 opts1;
372 __le32 opts2;
373 __le64 addr;
1da177e4
LT		 374};
375
376struct ring_info {
377 struct sk_buff *skb;
378 u32 len;
379 u8 __pad[sizeof(void *) - sizeof(u32)];
380};
381
382struct rtl8169_private {
383 void __iomem *mmio_addr; /* memory map physical address */
384 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 385 struct net_device *dev;
1da177e4
LT		 386 struct net_device_stats stats; /* statistics of net device */
387 spinlock_t lock; /* spin lock flag */
b57b7e5a 388 u32 msg_enable;
1da177e4
LT		 389 int chipset;
390 int mac_version;
391 int phy_version;
392 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
393 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
394 u32 dirty_rx;
395 u32 dirty_tx;
396 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
397 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
398 dma_addr_t TxPhyAddr;
399 dma_addr_t RxPhyAddr;
400 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
401 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 402 unsigned align;
1da177e4
LT		 403 unsigned rx_buf_sz;
404 struct timer_list timer;
405 u16 cp_cmd;
0e485150
FR		 406 u16 intr_event;
407 u16 napi_event;
1da177e4
LT		 408 u16 intr_mask;
409 int phy_auto_nego_reg;
410 int phy_1000_ctrl_reg;
411#ifdef CONFIG_R8169_VLAN
412 struct vlan_group *vlgrp;
413#endif
414 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
415 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
416 void (*phy_reset_enable)(void __iomem *);
07ce4064 417 void (*hw_start)(struct net_device *);
1da177e4
LT		 418 unsigned int (*phy_reset_pending)(void __iomem *);
419 unsigned int (*link_ok)(void __iomem *);
c4028958 420 struct delayed_work task;
61a4dcc2 421 unsigned wol_enabled : 1;
1da177e4
LT		 422};
423
979b6c13 424MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 425MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 426module_param(rx_copybreak, int, 0);
1b7efd58 427MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 428module_param(use_dac, int, 0);
429MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 430module_param_named(debug, debug.msg_enable, int, 0);
431MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 432MODULE_LICENSE("GPL");
433MODULE_VERSION(RTL8169_VERSION);
434
435static int rtl8169_open(struct net_device *dev);
436static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 437static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 438static int rtl8169_init_ring(struct net_device *dev);
07ce4064 439static void rtl_hw_start(struct net_device *dev);
1da177e4 440static int rtl8169_close(struct net_device *dev);
07ce4064 441static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 442static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 443static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 444static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
445 void __iomem *);
4dcb7d33 446static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 447static void rtl8169_down(struct net_device *dev);
99f252b0 448static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 449
450#ifdef CONFIG_R8169_NAPI
451static int rtl8169_poll(struct net_device *dev, int *budget);
452#endif
453
1da177e4 454static const unsigned int rtl8169_rx_config =
5b0384f4 455 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 456
07d3f51f 457static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 458{
459 int i;
460
07d3f51f 461 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 462
2371408c 463 for (i = 20; i > 0; i--) {
07d3f51f
FR		 464 /*
465 * Check if the RTL8169 has completed writing to the specified
466 * MII register.
467 */
5b0384f4 468 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 469 break;
2371408c 470 udelay(25);
1da177e4
LT		 471 }
472}
473
07d3f51f 474static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 475{
476 int i, value = -1;
477
07d3f51f 478 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 479
2371408c 480 for (i = 20; i > 0; i--) {
07d3f51f
FR		 481 /*
482 * Check if the RTL8169 has completed retrieving data from
483 * the specified MII register.
484 */
1da177e4
LT		 485 if (RTL_R32(PHYAR) & 0x80000000) {
486 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
487 break;
488 }
2371408c 489 udelay(25);
1da177e4
LT		 490 }
491 return value;
492}
493
494static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
495{
496 RTL_W16(IntrMask, 0x0000);
497
498 RTL_W16(IntrStatus, 0xffff);
499}
500
501static void rtl8169_asic_down(void __iomem *ioaddr)
502{
503 RTL_W8(ChipCmd, 0x00);
504 rtl8169_irq_mask_and_ack(ioaddr);
505 RTL_R16(CPlusCmd);
506}
507
508static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
509{
510 return RTL_R32(TBICSR) & TBIReset;
511}
512
513static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
514{
64e4bfb4 515 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 516}
517
518static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
519{
520 return RTL_R32(TBICSR) & TBILinkOk;
521}
522
523static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
524{
525 return RTL_R8(PHYstatus) & LinkStatus;
526}
527
528static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
529{
530 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
531}
532
533static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
534{
535 unsigned int val;
536
9e0db8ef
FR		 537 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
538 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 539}
540
541static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 542 struct rtl8169_private *tp,
543 void __iomem *ioaddr)
1da177e4
LT		 544{
545 unsigned long flags;
546
547 spin_lock_irqsave(&tp->lock, flags);
548 if (tp->link_ok(ioaddr)) {
549 netif_carrier_on(dev);
b57b7e5a
SH		 550 if (netif_msg_ifup(tp))
551 printk(KERN_INFO PFX "%s: link up\n", dev->name);
552 } else {
553 if (netif_msg_ifdown(tp))
554 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 555 netif_carrier_off(dev);
b57b7e5a 556 }
1da177e4
LT		 557 spin_unlock_irqrestore(&tp->lock, flags);
558}
559
61a4dcc2
FR		 560static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
561{
562 struct rtl8169_private *tp = netdev_priv(dev);
563 void __iomem *ioaddr = tp->mmio_addr;
564 u8 options;
565
566 wol->wolopts = 0;
567
568#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
569 wol->supported = WAKE_ANY;
570
571 spin_lock_irq(&tp->lock);
572
573 options = RTL_R8(Config1);
574 if (!(options & PMEnable))
575 goto out_unlock;
576
577 options = RTL_R8(Config3);
578 if (options & LinkUp)
579 wol->wolopts |= WAKE_PHY;
580 if (options & MagicPacket)
581 wol->wolopts |= WAKE_MAGIC;
582
583 options = RTL_R8(Config5);
584 if (options & UWF)
585 wol->wolopts |= WAKE_UCAST;
586 if (options & BWF)
5b0384f4 587 wol->wolopts |= WAKE_BCAST;
61a4dcc2 588 if (options & MWF)
5b0384f4 589 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 590
591out_unlock:
592 spin_unlock_irq(&tp->lock);
593}
594
595static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
596{
597 struct rtl8169_private *tp = netdev_priv(dev);
598 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 599 unsigned int i;
61a4dcc2
FR		 600 static struct {
601 u32 opt;
602 u16 reg;
603 u8 mask;
604 } cfg[] = {
605 { WAKE_ANY, Config1, PMEnable },
606 { WAKE_PHY, Config3, LinkUp },
607 { WAKE_MAGIC, Config3, MagicPacket },
608 { WAKE_UCAST, Config5, UWF },
609 { WAKE_BCAST, Config5, BWF },
610 { WAKE_MCAST, Config5, MWF },
611 { WAKE_ANY, Config5, LanWake }
612 };
613
614 spin_lock_irq(&tp->lock);
615
616 RTL_W8(Cfg9346, Cfg9346_Unlock);
617
618 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
619 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
620 if (wol->wolopts & cfg[i].opt)
621 options |= cfg[i].mask;
622 RTL_W8(cfg[i].reg, options);
623 }
624
625 RTL_W8(Cfg9346, Cfg9346_Lock);
626
627 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
628
629 spin_unlock_irq(&tp->lock);
630
631 return 0;
632}
633
1da177e4
LT		 634static void rtl8169_get_drvinfo(struct net_device *dev,
635 struct ethtool_drvinfo *info)
636{
637 struct rtl8169_private *tp = netdev_priv(dev);
638
639 strcpy(info->driver, MODULENAME);
640 strcpy(info->version, RTL8169_VERSION);
641 strcpy(info->bus_info, pci_name(tp->pci_dev));
642}
643
644static int rtl8169_get_regs_len(struct net_device *dev)
645{
646 return R8169_REGS_SIZE;
647}
648
649static int rtl8169_set_speed_tbi(struct net_device *dev,
650 u8 autoneg, u16 speed, u8 duplex)
651{
652 struct rtl8169_private *tp = netdev_priv(dev);
653 void __iomem *ioaddr = tp->mmio_addr;
654 int ret = 0;
655 u32 reg;
656
657 reg = RTL_R32(TBICSR);
658 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
659 (duplex == DUPLEX_FULL)) {
660 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
661 } else if (autoneg == AUTONEG_ENABLE)
662 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
663 else {
b57b7e5a
SH		 664 if (netif_msg_link(tp)) {
665 printk(KERN_WARNING "%s: "
666 "incorrect speed setting refused in TBI mode\n",
667 dev->name);
668 }
1da177e4
LT		 669 ret = -EOPNOTSUPP;
670 }
671
672 return ret;
673}
674
675static int rtl8169_set_speed_xmii(struct net_device *dev,
676 u8 autoneg, u16 speed, u8 duplex)
677{
678 struct rtl8169_private *tp = netdev_priv(dev);
679 void __iomem *ioaddr = tp->mmio_addr;
680 int auto_nego, giga_ctrl;
681
64e4bfb4
FR		 682 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
683 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
684 ADVERTISE_100HALF | ADVERTISE_100FULL);
685 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
686 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 687
688 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 689 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
690 ADVERTISE_100HALF | ADVERTISE_100FULL);
691 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 692 } else {
693 if (speed == SPEED_10)
64e4bfb4 694 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 695 else if (speed == SPEED_100)
64e4bfb4 696 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 697 else if (speed == SPEED_1000)
64e4bfb4 698 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 699
700 if (duplex == DUPLEX_HALF)
64e4bfb4 701 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 702
703 if (duplex == DUPLEX_FULL)
64e4bfb4 704 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 705
706 /* This tweak comes straight from Realtek's driver. */
707 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
708 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 709 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 710 }
711 }
712
713 /* The 8100e/8101e do Fast Ethernet only. */
714 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
715 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
716 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 717 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 718 netif_msg_link(tp)) {
719 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
720 dev->name);
721 }
64e4bfb4 722 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 723 }
724
623a1593
FR		 725 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
726
1da177e4
LT		 727 tp->phy_auto_nego_reg = auto_nego;
728 tp->phy_1000_ctrl_reg = giga_ctrl;
729
64e4bfb4
FR		 730 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
731 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
732 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 733 return 0;
734}
735
736static int rtl8169_set_speed(struct net_device *dev,
737 u8 autoneg, u16 speed, u8 duplex)
738{
739 struct rtl8169_private *tp = netdev_priv(dev);
740 int ret;
741
742 ret = tp->set_speed(dev, autoneg, speed, duplex);
743
64e4bfb4 744 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 745 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
746
747 return ret;
748}
749
750static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
751{
752 struct rtl8169_private *tp = netdev_priv(dev);
753 unsigned long flags;
754 int ret;
755
756 spin_lock_irqsave(&tp->lock, flags);
757 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
758 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 759
1da177e4
LT		 760 return ret;
761}
762
763static u32 rtl8169_get_rx_csum(struct net_device *dev)
764{
765 struct rtl8169_private *tp = netdev_priv(dev);
766
767 return tp->cp_cmd & RxChkSum;
768}
769
770static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773 void __iomem *ioaddr = tp->mmio_addr;
774 unsigned long flags;
775
776 spin_lock_irqsave(&tp->lock, flags);
777
778 if (data)
779 tp->cp_cmd |= RxChkSum;
780 else
781 tp->cp_cmd &= ~RxChkSum;
782
783 RTL_W16(CPlusCmd, tp->cp_cmd);
784 RTL_R16(CPlusCmd);
785
786 spin_unlock_irqrestore(&tp->lock, flags);
787
788 return 0;
789}
790
791#ifdef CONFIG_R8169_VLAN
792
793static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
794 struct sk_buff *skb)
795{
796 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
797 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
798}
799
800static void rtl8169_vlan_rx_register(struct net_device *dev,
801 struct vlan_group *grp)
802{
803 struct rtl8169_private *tp = netdev_priv(dev);
804 void __iomem *ioaddr = tp->mmio_addr;
805 unsigned long flags;
806
807 spin_lock_irqsave(&tp->lock, flags);
808 tp->vlgrp = grp;
809 if (tp->vlgrp)
810 tp->cp_cmd |= RxVlan;
811 else
812 tp->cp_cmd &= ~RxVlan;
813 RTL_W16(CPlusCmd, tp->cp_cmd);
814 RTL_R16(CPlusCmd);
815 spin_unlock_irqrestore(&tp->lock, flags);
816}
817
1da177e4
LT		 818static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
819 struct sk_buff *skb)
820{
821 u32 opts2 = le32_to_cpu(desc->opts2);
822 int ret;
823
824 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 825 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 826 ret = 0;
827 } else
828 ret = -1;
829 desc->opts2 = 0;
830 return ret;
831}
832
833#else /* !CONFIG_R8169_VLAN */
834
835static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
836 struct sk_buff *skb)
837{
838 return 0;
839}
840
841static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
842 struct sk_buff *skb)
843{
844 return -1;
845}
846
847#endif
848
849static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
850{
851 struct rtl8169_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->mmio_addr;
853 u32 status;
854
855 cmd->supported =
856 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
857 cmd->port = PORT_FIBRE;
858 cmd->transceiver = XCVR_INTERNAL;
859
860 status = RTL_R32(TBICSR);
861 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
862 cmd->autoneg = !!(status & TBINwEnable);
863
864 cmd->speed = SPEED_1000;
865 cmd->duplex = DUPLEX_FULL; /* Always set */
866}
867
868static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
869{
870 struct rtl8169_private *tp = netdev_priv(dev);
871 void __iomem *ioaddr = tp->mmio_addr;
872 u8 status;
873
874 cmd->supported = SUPPORTED_10baseT_Half |
875 SUPPORTED_10baseT_Full |
876 SUPPORTED_100baseT_Half |
877 SUPPORTED_100baseT_Full |
878 SUPPORTED_1000baseT_Full |
879 SUPPORTED_Autoneg |
5b0384f4 880 SUPPORTED_TP;
1da177e4
LT		 881
882 cmd->autoneg = 1;
883 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
884
64e4bfb4 885 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 886 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 887 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 888 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 889 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 890 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 891 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 892 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 893 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 894 cmd->advertising |= ADVERTISED_1000baseT_Full;
895
896 status = RTL_R8(PHYstatus);
897
898 if (status & _1000bpsF)
899 cmd->speed = SPEED_1000;
900 else if (status & _100bps)
901 cmd->speed = SPEED_100;
902 else if (status & _10bps)
903 cmd->speed = SPEED_10;
904
623a1593
FR		 905 if (status & TxFlowCtrl)
906 cmd->advertising |= ADVERTISED_Asym_Pause;
907 if (status & RxFlowCtrl)
908 cmd->advertising |= ADVERTISED_Pause;
909
1da177e4
LT		 910 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
911 DUPLEX_FULL : DUPLEX_HALF;
912}
913
914static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
915{
916 struct rtl8169_private *tp = netdev_priv(dev);
917 unsigned long flags;
918
919 spin_lock_irqsave(&tp->lock, flags);
920
921 tp->get_settings(dev, cmd);
922
923 spin_unlock_irqrestore(&tp->lock, flags);
924 return 0;
925}
926
927static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
928 void *p)
929{
5b0384f4
FR		 930 struct rtl8169_private *tp = netdev_priv(dev);
931 unsigned long flags;
1da177e4 932
5b0384f4
FR		 933 if (regs->len > R8169_REGS_SIZE)
934 regs->len = R8169_REGS_SIZE;
1da177e4 935
5b0384f4
FR		 936 spin_lock_irqsave(&tp->lock, flags);
937 memcpy_fromio(p, tp->mmio_addr, regs->len);
938 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 939}
940
b57b7e5a
SH		 941static u32 rtl8169_get_msglevel(struct net_device *dev)
942{
943 struct rtl8169_private *tp = netdev_priv(dev);
944
945 return tp->msg_enable;
946}
947
948static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
949{
950 struct rtl8169_private *tp = netdev_priv(dev);
951
952 tp->msg_enable = value;
953}
954
d4a3a0fc
SH		 955static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
956 "tx_packets",
957 "rx_packets",
958 "tx_errors",
959 "rx_errors",
960 "rx_missed",
961 "align_errors",
962 "tx_single_collisions",
963 "tx_multi_collisions",
964 "unicast",
965 "broadcast",
966 "multicast",
967 "tx_aborted",
968 "tx_underrun",
969};
970
971struct rtl8169_counters {
972 u64 tx_packets;
973 u64 rx_packets;
974 u64 tx_errors;
975 u32 rx_errors;
976 u16 rx_missed;
977 u16 align_errors;
978 u32 tx_one_collision;
979 u32 tx_multi_collision;
980 u64 rx_unicast;
981 u64 rx_broadcast;
982 u32 rx_multicast;
983 u16 tx_aborted;
984 u16 tx_underun;
985};
986
987static int rtl8169_get_stats_count(struct net_device *dev)
988{
989 return ARRAY_SIZE(rtl8169_gstrings);
990}
991
992static void rtl8169_get_ethtool_stats(struct net_device *dev,
993 struct ethtool_stats *stats, u64 *data)
994{
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
997 struct rtl8169_counters *counters;
998 dma_addr_t paddr;
999 u32 cmd;
1000
1001 ASSERT_RTNL();
1002
1003 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1004 if (!counters)
1005 return;
1006
1007 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1008 cmd = (u64)paddr & DMA_32BIT_MASK;
1009 RTL_W32(CounterAddrLow, cmd);
1010 RTL_W32(CounterAddrLow, cmd | CounterDump);
1011
1012 while (RTL_R32(CounterAddrLow) & CounterDump) {
1013 if (msleep_interruptible(1))
1014 break;
1015 }
1016
1017 RTL_W32(CounterAddrLow, 0);
1018 RTL_W32(CounterAddrHigh, 0);
1019
5b0384f4 1020 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1021 data[1] = le64_to_cpu(counters->rx_packets);
1022 data[2] = le64_to_cpu(counters->tx_errors);
1023 data[3] = le32_to_cpu(counters->rx_errors);
1024 data[4] = le16_to_cpu(counters->rx_missed);
1025 data[5] = le16_to_cpu(counters->align_errors);
1026 data[6] = le32_to_cpu(counters->tx_one_collision);
1027 data[7] = le32_to_cpu(counters->tx_multi_collision);
1028 data[8] = le64_to_cpu(counters->rx_unicast);
1029 data[9] = le64_to_cpu(counters->rx_broadcast);
1030 data[10] = le32_to_cpu(counters->rx_multicast);
1031 data[11] = le16_to_cpu(counters->tx_aborted);
1032 data[12] = le16_to_cpu(counters->tx_underun);
1033
1034 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1035}
1036
1037static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1038{
1039 switch(stringset) {
1040 case ETH_SS_STATS:
1041 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1042 break;
1043 }
1044}
1045
7282d491 1046static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1047 .get_drvinfo = rtl8169_get_drvinfo,
1048 .get_regs_len = rtl8169_get_regs_len,
1049 .get_link = ethtool_op_get_link,
1050 .get_settings = rtl8169_get_settings,
1051 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1052 .get_msglevel = rtl8169_get_msglevel,
1053 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1054 .get_rx_csum = rtl8169_get_rx_csum,
1055 .set_rx_csum = rtl8169_set_rx_csum,
1056 .get_tx_csum = ethtool_op_get_tx_csum,
1057 .set_tx_csum = ethtool_op_set_tx_csum,
1058 .get_sg = ethtool_op_get_sg,
1059 .set_sg = ethtool_op_set_sg,
1060 .get_tso = ethtool_op_get_tso,
1061 .set_tso = ethtool_op_set_tso,
1062 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1063 .get_wol = rtl8169_get_wol,
1064 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1065 .get_strings = rtl8169_get_strings,
1066 .get_stats_count = rtl8169_get_stats_count,
1067 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1068 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1069};
1070
07d3f51f
FR		 1071static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1072 int bitnum, int bitval)
1da177e4
LT		 1073{
1074 int val;
1075
1076 val = mdio_read(ioaddr, reg);
1077 val = (bitval == 1) ?
1078 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1079 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1080}
1081
07d3f51f
FR		 1082static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1083 void __iomem *ioaddr)
1da177e4 1084{
0e485150
FR		 1085 /*
1086 * The driver currently handles the 8168Bf and the 8168Be identically
1087 * but they can be identified more specifically through the test below
1088 * if needed:
1089 *
1090 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1091 *
1092 * Same thing for the 8101Eb and the 8101Ec:
1093 *
1094 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1095 */
1da177e4
LT		 1096 const struct {
1097 u32 mask;
1098 int mac_version;
1099 } mac_info[] = {
bcf0bf90
FR		 1100 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1101 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1102 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1103 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1104 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1105 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1106 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1107 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1108 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1109 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1110 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1111 }, *p = mac_info;
1112 u32 reg;
1113
6dccd16b 1114 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1115 while ((reg & p->mask) != p->mask)
1116 p++;
1117 tp->mac_version = p->mac_version;
1118}
1119
1120static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1121{
bcf0bf90 1122 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1123}
1124
07d3f51f
FR		 1125static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1126 void __iomem *ioaddr)
1da177e4
LT		 1127{
1128 const struct {
1129 u16 mask;
1130 u16 set;
1131 int phy_version;
1132 } phy_info[] = {
1133 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1134 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1135 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1136 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1137 }, *p = phy_info;
1138 u16 reg;
1139
64e4bfb4 1140 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1141 while ((reg & p->mask) != p->set)
1142 p++;
1143 tp->phy_version = p->phy_version;
1144}
1145
1146static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1147{
1148 struct {
1149 int version;
1150 char *msg;
1151 u32 reg;
1152 } phy_print[] = {
1153 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1154 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1155 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1156 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1157 { 0, NULL, 0x0000 }
1158 }, *p;
1159
1160 for (p = phy_print; p->msg; p++) {
1161 if (tp->phy_version == p->version) {
1162 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1163 return;
1164 }
1165 }
1166 dprintk("phy_version == Unknown\n");
1167}
1168
1169static void rtl8169_hw_phy_config(struct net_device *dev)
1170{
1171 struct rtl8169_private *tp = netdev_priv(dev);
1172 void __iomem *ioaddr = tp->mmio_addr;
1173 struct {
1174 u16 regs[5]; /* Beware of bit-sign propagation */
1175 } phy_magic[5] = { {
1176 { 0x0000, //w 4 15 12 0
1177 0x00a1, //w 3 15 0 00a1
1178 0x0008, //w 2 15 0 0008
1179 0x1020, //w 1 15 0 1020
1180 0x1000 } },{ //w 0 15 0 1000
1181 { 0x7000, //w 4 15 12 7
1182 0xff41, //w 3 15 0 ff41
1183 0xde60, //w 2 15 0 de60
1184 0x0140, //w 1 15 0 0140
1185 0x0077 } },{ //w 0 15 0 0077
1186 { 0xa000, //w 4 15 12 a
1187 0xdf01, //w 3 15 0 df01
1188 0xdf20, //w 2 15 0 df20
1189 0xff95, //w 1 15 0 ff95
1190 0xfa00 } },{ //w 0 15 0 fa00
1191 { 0xb000, //w 4 15 12 b
1192 0xff41, //w 3 15 0 ff41
1193 0xde20, //w 2 15 0 de20
1194 0x0140, //w 1 15 0 0140
1195 0x00bb } },{ //w 0 15 0 00bb
1196 { 0xf000, //w 4 15 12 f
1197 0xdf01, //w 3 15 0 df01
1198 0xdf20, //w 2 15 0 df20
1199 0xff95, //w 1 15 0 ff95
1200 0xbf00 } //w 0 15 0 bf00
1201 }
1202 }, *p = phy_magic;
07d3f51f 1203 unsigned int i;
1da177e4
LT		 1204
1205 rtl8169_print_mac_version(tp);
1206 rtl8169_print_phy_version(tp);
1207
bcf0bf90 1208 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1209 return;
1210 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1211 return;
1212
1213 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1214 dprintk("Do final_reg2.cfg\n");
1215
1216 /* Shazam ! */
1217
bcf0bf90 1218 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1219 mdio_write(ioaddr, 31, 0x0002);
1220 mdio_write(ioaddr, 1, 0x90d0);
1221 mdio_write(ioaddr, 31, 0x0000);
1222 return;
1223 }
1224
1225 /* phy config for RTL8169s mac_version C chip */
1226 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1227 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1228 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1229 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1230
1231 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1232 int val, pos = 4;
1233
1234 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1235 mdio_write(ioaddr, pos, val);
1236 while (--pos >= 0)
1237 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1238 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1239 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1240 }
1241 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1242}
1243
1244static void rtl8169_phy_timer(unsigned long __opaque)
1245{
1246 struct net_device *dev = (struct net_device *)__opaque;
1247 struct rtl8169_private *tp = netdev_priv(dev);
1248 struct timer_list *timer = &tp->timer;
1249 void __iomem *ioaddr = tp->mmio_addr;
1250 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1251
bcf0bf90 1252 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1253 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1254
64e4bfb4 1255 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1256 return;
1257
1258 spin_lock_irq(&tp->lock);
1259
1260 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1261 /*
1da177e4
LT		 1262 * A busy loop could burn quite a few cycles on nowadays CPU.
1263 * Let's delay the execution of the timer for a few ticks.
1264 */
1265 timeout = HZ/10;
1266 goto out_mod_timer;
1267 }
1268
1269 if (tp->link_ok(ioaddr))
1270 goto out_unlock;
1271
b57b7e5a
SH		 1272 if (netif_msg_link(tp))
1273 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1274
1275 tp->phy_reset_enable(ioaddr);
1276
1277out_mod_timer:
1278 mod_timer(timer, jiffies + timeout);
1279out_unlock:
1280 spin_unlock_irq(&tp->lock);
1281}
1282
1283static inline void rtl8169_delete_timer(struct net_device *dev)
1284{
1285 struct rtl8169_private *tp = netdev_priv(dev);
1286 struct timer_list *timer = &tp->timer;
1287
bcf0bf90 1288 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1289 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1290 return;
1291
1292 del_timer_sync(timer);
1293}
1294
1295static inline void rtl8169_request_timer(struct net_device *dev)
1296{
1297 struct rtl8169_private *tp = netdev_priv(dev);
1298 struct timer_list *timer = &tp->timer;
1299
bcf0bf90 1300 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1301 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1302 return;
1303
2efa53f3 1304 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1305}
1306
1307#ifdef CONFIG_NET_POLL_CONTROLLER
1308/*
1309 * Polling 'interrupt' - used by things like netconsole to send skbs
1310 * without having to re-enable interrupts. It's not called while
1311 * the interrupt routine is executing.
1312 */
1313static void rtl8169_netpoll(struct net_device *dev)
1314{
1315 struct rtl8169_private *tp = netdev_priv(dev);
1316 struct pci_dev *pdev = tp->pci_dev;
1317
1318 disable_irq(pdev->irq);
7d12e780 1319 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1320 enable_irq(pdev->irq);
1321}
1322#endif
1323
1324static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1325 void __iomem *ioaddr)
1326{
1327 iounmap(ioaddr);
1328 pci_release_regions(pdev);
1329 pci_disable_device(pdev);
1330 free_netdev(dev);
1331}
1332
bf793295
FR		 1333static void rtl8169_phy_reset(struct net_device *dev,
1334 struct rtl8169_private *tp)
1335{
1336 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1337 unsigned int i;
bf793295
FR		 1338
1339 tp->phy_reset_enable(ioaddr);
1340 for (i = 0; i < 100; i++) {
1341 if (!tp->phy_reset_pending(ioaddr))
1342 return;
1343 msleep(1);
1344 }
1345 if (netif_msg_link(tp))
1346 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1347}
1348
4ff96fa6
FR		 1349static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1350{
1351 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6
FR		 1352
1353 rtl8169_hw_phy_config(dev);
1354
1355 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1356 RTL_W8(0x82, 0x01);
1357
6dccd16b
FR		 1358 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1359
1360 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1361 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1362
bcf0bf90 1363 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1364 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1365 RTL_W8(0x82, 0x01);
1366 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1367 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1368 }
1369
bf793295
FR		 1370 rtl8169_phy_reset(dev, tp);
1371
901dda2b
FR		 1372 /*
1373 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1374 * only 8101. Don't panic.
1375 */
1376 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1377
1378 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1379 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1380}
1381
5f787a1a
FR		 1382static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1383{
1384 struct rtl8169_private *tp = netdev_priv(dev);
1385 struct mii_ioctl_data *data = if_mii(ifr);
1386
1387 if (!netif_running(dev))
1388 return -ENODEV;
1389
1390 switch (cmd) {
1391 case SIOCGMIIPHY:
1392 data->phy_id = 32; /* Internal PHY */
1393 return 0;
1394
1395 case SIOCGMIIREG:
1396 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1397 return 0;
1398
1399 case SIOCSMIIREG:
1400 if (!capable(CAP_NET_ADMIN))
1401 return -EPERM;
1402 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1403 return 0;
1404 }
1405 return -EOPNOTSUPP;
1406}
1407
0e485150
FR		 1408static const struct rtl_cfg_info {
1409 void (*hw_start)(struct net_device *);
1410 unsigned int region;
1411 unsigned int align;
1412 u16 intr_event;
1413 u16 napi_event;
1414} rtl_cfg_infos [] = {
1415 [RTL_CFG_0] = {
1416 .hw_start = rtl_hw_start_8169,
1417 .region = 1,
e9f63f30 1418 .align = 0,
0e485150
FR		 1419 .intr_event = SYSErr | LinkChg | RxOverflow |
1420 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1421 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1422 },
1423 [RTL_CFG_1] = {
1424 .hw_start = rtl_hw_start_8168,
1425 .region = 2,
1426 .align = 8,
1427 .intr_event = SYSErr | LinkChg | RxOverflow |
1428 TxErr | TxOK | RxOK | RxErr,
1429 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1430 },
1431 [RTL_CFG_2] = {
1432 .hw_start = rtl_hw_start_8101,
1433 .region = 2,
1434 .align = 8,
1435 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1436 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1437 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1438 }
1439};
1440
1da177e4 1441static int __devinit
4ff96fa6 1442rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1443{
0e485150
FR		 1444 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1445 const unsigned int region = cfg->region;
1da177e4 1446 struct rtl8169_private *tp;
4ff96fa6
FR		 1447 struct net_device *dev;
1448 void __iomem *ioaddr;
07d3f51f
FR		 1449 unsigned int i;
1450 int rc;
1da177e4 1451
4ff96fa6
FR		 1452 if (netif_msg_drv(&debug)) {
1453 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1454 MODULENAME, RTL8169_VERSION);
1455 }
1da177e4 1456
1da177e4 1457 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1458 if (!dev) {
b57b7e5a 1459 if (netif_msg_drv(&debug))
9b91cf9d 1460 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1461 rc = -ENOMEM;
1462 goto out;
1da177e4
LT		 1463 }
1464
1465 SET_MODULE_OWNER(dev);
1466 SET_NETDEV_DEV(dev, &pdev->dev);
1467 tp = netdev_priv(dev);
c4028958 1468 tp->dev = dev;
b57b7e5a 1469 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1470
1471 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1472 rc = pci_enable_device(pdev);
b57b7e5a 1473 if (rc < 0) {
2e8a538d 1474 if (netif_msg_probe(tp))
9b91cf9d 1475 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1476 goto err_out_free_dev_1;
1da177e4
LT		 1477 }
1478
1479 rc = pci_set_mwi(pdev);
1480 if (rc < 0)
4ff96fa6 1481 goto err_out_disable_2;
1da177e4 1482
1da177e4 1483 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1484 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1485 if (netif_msg_probe(tp)) {
9b91cf9d 1486 dev_err(&pdev->dev,
bcf0bf90
FR		 1487 "region #%d not an MMIO resource, aborting\n",
1488 region);
4ff96fa6 1489 }
1da177e4 1490 rc = -ENODEV;
4ff96fa6 1491 goto err_out_mwi_3;
1da177e4 1492 }
4ff96fa6 1493
1da177e4 1494 /* check for weird/broken PCI region reporting */
bcf0bf90 1495 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1496 if (netif_msg_probe(tp)) {
9b91cf9d 1497 dev_err(&pdev->dev,
4ff96fa6
FR		 1498 "Invalid PCI region size(s), aborting\n");
1499 }
1da177e4 1500 rc = -ENODEV;
4ff96fa6 1501 goto err_out_mwi_3;
1da177e4
LT		 1502 }
1503
1504 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1505 if (rc < 0) {
2e8a538d 1506 if (netif_msg_probe(tp))
9b91cf9d 1507 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1508 goto err_out_mwi_3;
1da177e4
LT		 1509 }
1510
1511 tp->cp_cmd = PCIMulRW | RxChkSum;
1512
1513 if ((sizeof(dma_addr_t) > 4) &&
1514 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1515 tp->cp_cmd |= PCIDAC;
1516 dev->features |= NETIF_F_HIGHDMA;
1517 } else {
1518 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1519 if (rc < 0) {
4ff96fa6 1520 if (netif_msg_probe(tp)) {
9b91cf9d 1521 dev_err(&pdev->dev,
4ff96fa6
FR		 1522 "DMA configuration failed.\n");
1523 }
1524 goto err_out_free_res_4;
1da177e4
LT		 1525 }
1526 }
1527
1528 pci_set_master(pdev);
1529
1530 /* ioremap MMIO region */
bcf0bf90 1531 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1532 if (!ioaddr) {
b57b7e5a 1533 if (netif_msg_probe(tp))
9b91cf9d 1534 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1535 rc = -EIO;
4ff96fa6 1536 goto err_out_free_res_4;
1da177e4
LT		 1537 }
1538
1539 /* Unneeded ? Don't mess with Mrs. Murphy. */
1540 rtl8169_irq_mask_and_ack(ioaddr);
1541
1542 /* Soft reset the chip. */
1543 RTL_W8(ChipCmd, CmdReset);
1544
1545 /* Check that the chip has finished the reset. */
07d3f51f 1546 for (i = 0; i < 100; i++) {
1da177e4
LT		 1547 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1548 break;
b518fa8e 1549 msleep_interruptible(1);
1da177e4
LT		 1550 }
1551
1552 /* Identify chip attached to board */
1553 rtl8169_get_mac_version(tp, ioaddr);
1554 rtl8169_get_phy_version(tp, ioaddr);
1555
1556 rtl8169_print_mac_version(tp);
1557 rtl8169_print_phy_version(tp);
1558
1559 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1560 if (tp->mac_version == rtl_chip_info[i].mac_version)
1561 break;
1562 }
1563 if (i < 0) {
1564 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1565 if (netif_msg_probe(tp)) {
2e8a538d 1566 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1567 "unknown chip version, assuming %s\n",
1568 rtl_chip_info[0].name);
b57b7e5a 1569 }
1da177e4
LT		 1570 i++;
1571 }
1572 tp->chipset = i;
1573
5d06a99f
FR		 1574 RTL_W8(Cfg9346, Cfg9346_Unlock);
1575 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1576 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1577 RTL_W8(Cfg9346, Cfg9346_Lock);
1578
1da177e4
LT		 1579 if (RTL_R8(PHYstatus) & TBI_Enable) {
1580 tp->set_speed = rtl8169_set_speed_tbi;
1581 tp->get_settings = rtl8169_gset_tbi;
1582 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1583 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1584 tp->link_ok = rtl8169_tbi_link_ok;
1585
64e4bfb4 1586 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1587 } else {
1588 tp->set_speed = rtl8169_set_speed_xmii;
1589 tp->get_settings = rtl8169_gset_xmii;
1590 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1591 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1592 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1593
1594 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1595 }
1596
1597 /* Get MAC address. FIXME: read EEPROM */
1598 for (i = 0; i < MAC_ADDR_LEN; i++)
1599 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1600 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1601
1602 dev->open = rtl8169_open;
1603 dev->hard_start_xmit = rtl8169_start_xmit;
1604 dev->get_stats = rtl8169_get_stats;
1605 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1606 dev->stop = rtl8169_close;
1607 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1608 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1609 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1610 dev->irq = pdev->irq;
1611 dev->base_addr = (unsigned long) ioaddr;
1612 dev->change_mtu = rtl8169_change_mtu;
1613
1614#ifdef CONFIG_R8169_NAPI
1615 dev->poll = rtl8169_poll;
1616 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1617#endif
1618
1619#ifdef CONFIG_R8169_VLAN
1620 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1621 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1622#endif
1623
1624#ifdef CONFIG_NET_POLL_CONTROLLER
1625 dev->poll_controller = rtl8169_netpoll;
1626#endif
1627
1628 tp->intr_mask = 0xffff;
1629 tp->pci_dev = pdev;
1630 tp->mmio_addr = ioaddr;
0e485150
FR		 1631 tp->align = cfg->align;
1632 tp->hw_start = cfg->hw_start;
1633 tp->intr_event = cfg->intr_event;
1634 tp->napi_event = cfg->napi_event;
1da177e4 1635
2efa53f3
FR		 1636 init_timer(&tp->timer);
1637 tp->timer.data = (unsigned long) dev;
1638 tp->timer.function = rtl8169_phy_timer;
1639
1da177e4
LT		 1640 spin_lock_init(&tp->lock);
1641
1642 rc = register_netdev(dev);
4ff96fa6
FR		 1643 if (rc < 0)
1644 goto err_out_unmap_5;
1da177e4
LT		 1645
1646 pci_set_drvdata(pdev, dev);
1647
b57b7e5a 1648 if (netif_msg_probe(tp)) {
96b9709c
FR		 1649 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1650
b57b7e5a
SH		 1651 printk(KERN_INFO "%s: %s at 0x%lx, "
1652 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1653 "XID %08x IRQ %d\n",
b57b7e5a 1654 dev->name,
bcf0bf90 1655 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1656 dev->base_addr,
1657 dev->dev_addr[0], dev->dev_addr[1],
1658 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1659 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1660 }
1da177e4 1661
4ff96fa6 1662 rtl8169_init_phy(dev, tp);
1da177e4 1663
4ff96fa6
FR		 1664out:
1665 return rc;
1da177e4 1666
4ff96fa6
FR		 1667err_out_unmap_5:
1668 iounmap(ioaddr);
1669err_out_free_res_4:
1670 pci_release_regions(pdev);
1671err_out_mwi_3:
1672 pci_clear_mwi(pdev);
1673err_out_disable_2:
1674 pci_disable_device(pdev);
1675err_out_free_dev_1:
1676 free_netdev(dev);
1677 goto out;
1da177e4
LT		 1678}
1679
07d3f51f 1680static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1681{
1682 struct net_device *dev = pci_get_drvdata(pdev);
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684
eb2a021c
FR		 1685 flush_scheduled_work();
1686
1da177e4
LT		 1687 unregister_netdev(dev);
1688 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1689 pci_set_drvdata(pdev, NULL);
1690}
1691
1da177e4
LT		 1692static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1693 struct net_device *dev)
1694{
1695 unsigned int mtu = dev->mtu;
1696
1697 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1698}
1699
1700static int rtl8169_open(struct net_device *dev)
1701{
1702 struct rtl8169_private *tp = netdev_priv(dev);
1703 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1704 int retval = -ENOMEM;
1da177e4 1705
1da177e4 1706
99f252b0 1707 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1708
1709 /*
1710 * Rx and Tx desscriptors needs 256 bytes alignment.
1711 * pci_alloc_consistent provides more.
1712 */
1713 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1714 &tp->TxPhyAddr);
1715 if (!tp->TxDescArray)
99f252b0 1716 goto out;
1da177e4
LT		 1717
1718 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1719 &tp->RxPhyAddr);
1720 if (!tp->RxDescArray)
99f252b0 1721 goto err_free_tx_0;
1da177e4
LT		 1722
1723 retval = rtl8169_init_ring(dev);
1724 if (retval < 0)
99f252b0 1725 goto err_free_rx_1;
1da177e4 1726
c4028958 1727 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1728
99f252b0
FR		 1729 smp_mb();
1730
1731 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1732 dev->name, dev);
1733 if (retval < 0)
1734 goto err_release_ring_2;
1735
07ce4064 1736 rtl_hw_start(dev);
1da177e4
LT		 1737
1738 rtl8169_request_timer(dev);
1739
1740 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1741out:
1742 return retval;
1743
99f252b0
FR		 1744err_release_ring_2:
1745 rtl8169_rx_clear(tp);
1746err_free_rx_1:
1da177e4
LT		 1747 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1748 tp->RxPhyAddr);
99f252b0 1749err_free_tx_0:
1da177e4
LT		 1750 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1751 tp->TxPhyAddr);
1da177e4
LT		 1752 goto out;
1753}
1754
1755static void rtl8169_hw_reset(void __iomem *ioaddr)
1756{
1757 /* Disable interrupts */
1758 rtl8169_irq_mask_and_ack(ioaddr);
1759
1760 /* Reset the chipset */
1761 RTL_W8(ChipCmd, CmdReset);
1762
1763 /* PCI commit */
1764 RTL_R8(ChipCmd);
1765}
1766
7f796d83 1767static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1768{
1769 void __iomem *ioaddr = tp->mmio_addr;
1770 u32 cfg = rtl8169_rx_config;
1771
1772 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1773 RTL_W32(RxConfig, cfg);
1774
1775 /* Set DMA burst size and Interframe Gap Time */
1776 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1777 (InterFrameGap << TxInterFrameGapShift));
1778}
1779
07ce4064 1780static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1781{
1782 struct rtl8169_private *tp = netdev_priv(dev);
1783 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1784 unsigned int i;
1da177e4
LT		 1785
1786 /* Soft reset the chip. */
1787 RTL_W8(ChipCmd, CmdReset);
1788
1789 /* Check that the chip has finished the reset. */
07d3f51f 1790 for (i = 0; i < 100; i++) {
1da177e4
LT		 1791 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1792 break;
b518fa8e 1793 msleep_interruptible(1);
1da177e4
LT		 1794 }
1795
07ce4064
FR		 1796 tp->hw_start(dev);
1797
07ce4064
FR		 1798 netif_start_queue(dev);
1799}
1800
1801
7f796d83
FR		 1802static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1803 void __iomem *ioaddr)
1804{
1805 /*
1806 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1807 * register to be written before TxDescAddrLow to work.
1808 * Switching from MMIO to I/O access fixes the issue as well.
1809 */
1810 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1811 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1812 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1813 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1814}
1815
1816static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1817{
1818 u16 cmd;
1819
1820 cmd = RTL_R16(CPlusCmd);
1821 RTL_W16(CPlusCmd, cmd);
1822 return cmd;
1823}
1824
1825static void rtl_set_rx_max_size(void __iomem *ioaddr)
1826{
1827 /* Low hurts. Let's disable the filtering. */
1828 RTL_W16(RxMaxSize, 16383);
1829}
1830
6dccd16b
FR		 1831static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1832{
1833 struct {
1834 u32 mac_version;
1835 u32 clk;
1836 u32 val;
1837 } cfg2_info [] = {
1838 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1839 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1840 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1841 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1842 }, *p = cfg2_info;
1843 unsigned int i;
1844 u32 clk;
1845
1846 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1847 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1848 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1849 RTL_W32(0x7c, p->val);
1850 break;
1851 }
1852 }
1853}
1854
07ce4064
FR		 1855static void rtl_hw_start_8169(struct net_device *dev)
1856{
1857 struct rtl8169_private *tp = netdev_priv(dev);
1858 void __iomem *ioaddr = tp->mmio_addr;
1859 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1860
9cb427b6
FR		 1861 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1862 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1863 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1864 }
1865
1da177e4 1866 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1867 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1868 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1869 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1870 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1871 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1872
1da177e4
LT		 1873 RTL_W8(EarlyTxThres, EarlyTxThld);
1874
7f796d83 1875 rtl_set_rx_max_size(ioaddr);
1da177e4 1876
6dccd16b 1877 rtl_set_rx_tx_config_registers(tp);
1da177e4 1878
7f796d83 1879 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1880
bcf0bf90
FR		 1881 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1882 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1883 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1884 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1885 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1886 }
1887
bcf0bf90
FR		 1888 RTL_W16(CPlusCmd, tp->cp_cmd);
1889
6dccd16b
FR		 1890 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1891
1da177e4
LT		 1892 /*
1893 * Undocumented corner. Supposedly:
1894 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1895 */
1896 RTL_W16(IntrMitigate, 0x0000);
1897
7f796d83 1898 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1899
1da177e4 1900 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1901
1902 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1903 RTL_R8(IntrMask);
1da177e4
LT		 1904
1905 RTL_W32(RxMissed, 0);
1906
07ce4064 1907 rtl_set_rx_mode(dev);
1da177e4
LT		 1908
1909 /* no early-rx interrupts */
1910 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 1911
1912 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 1913 RTL_W16(IntrMask, tp->intr_event);
6dccd16b
FR		 1914
1915 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 1916}
1da177e4 1917
07ce4064
FR		 1918static void rtl_hw_start_8168(struct net_device *dev)
1919{
2dd99530
FR		 1920 struct rtl8169_private *tp = netdev_priv(dev);
1921 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1922 struct pci_dev *pdev = tp->pci_dev;
1923 u8 ctl;
2dd99530
FR		 1924
1925 RTL_W8(Cfg9346, Cfg9346_Unlock);
1926
1927 RTL_W8(EarlyTxThres, EarlyTxThld);
1928
1929 rtl_set_rx_max_size(ioaddr);
1930
0e485150
FR		 1931 rtl_set_rx_tx_config_registers(tp);
1932
1933 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 1934
1935 RTL_W16(CPlusCmd, tp->cp_cmd);
1936
0e485150
FR		 1937 /* Tx performance tweak. */
1938 pci_read_config_byte(pdev, 0x69, &ctl);
1939 ctl = (ctl & ~0x70) | 0x50;
1940 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 1941
0e485150 1942 RTL_W16(IntrMitigate, 0x5151);
2dd99530 1943
0e485150
FR		 1944 /* Work around for RxFIFO overflow. */
1945 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1946 tp->intr_event |= RxFIFOOver | PCSTimeout;
1947 tp->intr_event &= ~RxOverflow;
1948 }
1949
1950 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 1951
1952 RTL_W8(Cfg9346, Cfg9346_Lock);
1953
1954 RTL_R8(IntrMask);
1955
1956 RTL_W32(RxMissed, 0);
1957
1958 rtl_set_rx_mode(dev);
1959
0e485150
FR		 1960 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1961
2dd99530 1962 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 1963
0e485150 1964 RTL_W16(IntrMask, tp->intr_event);
07ce4064 1965}
1da177e4 1966
07ce4064
FR		 1967static void rtl_hw_start_8101(struct net_device *dev)
1968{
cdf1a608
FR		 1969 struct rtl8169_private *tp = netdev_priv(dev);
1970 void __iomem *ioaddr = tp->mmio_addr;
1971 struct pci_dev *pdev = tp->pci_dev;
1972
1973 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1974 pci_write_config_word(pdev, 0x68, 0x00);
1975 pci_write_config_word(pdev, 0x69, 0x08);
1976 }
1977
1978 RTL_W8(Cfg9346, Cfg9346_Unlock);
1979
1980 RTL_W8(EarlyTxThres, EarlyTxThld);
1981
1982 rtl_set_rx_max_size(ioaddr);
1983
1984 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1985
1986 RTL_W16(CPlusCmd, tp->cp_cmd);
1987
1988 RTL_W16(IntrMitigate, 0x0000);
1989
1990 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1991
1992 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1993 rtl_set_rx_tx_config_registers(tp);
1994
1995 RTL_W8(Cfg9346, Cfg9346_Lock);
1996
1997 RTL_R8(IntrMask);
1998
1999 RTL_W32(RxMissed, 0);
2000
2001 rtl_set_rx_mode(dev);
2002
0e485150
FR		 2003 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2004
cdf1a608 2005 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2006
0e485150 2007 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2008}
2009
2010static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2011{
2012 struct rtl8169_private *tp = netdev_priv(dev);
2013 int ret = 0;
2014
2015 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2016 return -EINVAL;
2017
2018 dev->mtu = new_mtu;
2019
2020 if (!netif_running(dev))
2021 goto out;
2022
2023 rtl8169_down(dev);
2024
2025 rtl8169_set_rxbufsize(tp, dev);
2026
2027 ret = rtl8169_init_ring(dev);
2028 if (ret < 0)
2029 goto out;
2030
2031 netif_poll_enable(dev);
2032
07ce4064 2033 rtl_hw_start(dev);
1da177e4
LT		 2034
2035 rtl8169_request_timer(dev);
2036
2037out:
2038 return ret;
2039}
2040
2041static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2042{
2043 desc->addr = 0x0badbadbadbadbadull;
2044 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2045}
2046
2047static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2048 struct sk_buff **sk_buff, struct RxDesc *desc)
2049{
2050 struct pci_dev *pdev = tp->pci_dev;
2051
2052 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2053 PCI_DMA_FROMDEVICE);
2054 dev_kfree_skb(*sk_buff);
2055 *sk_buff = NULL;
2056 rtl8169_make_unusable_by_asic(desc);
2057}
2058
2059static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2060{
2061 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2062
2063 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2064}
2065
2066static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2067 u32 rx_buf_sz)
2068{
2069 desc->addr = cpu_to_le64(mapping);
2070 wmb();
2071 rtl8169_mark_to_asic(desc, rx_buf_sz);
2072}
2073
15d31758
SH		 2074static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2075 struct net_device *dev,
2076 struct RxDesc *desc, int rx_buf_sz,
2077 unsigned int align)
1da177e4
LT		 2078{
2079 struct sk_buff *skb;
2080 dma_addr_t mapping;
e9f63f30 2081 unsigned int pad;
1da177e4 2082
e9f63f30
FR		 2083 pad = align ? align : NET_IP_ALIGN;
2084
2085 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2086 if (!skb)
2087 goto err_out;
2088
e9f63f30 2089 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2090
689be439 2091 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2092 PCI_DMA_FROMDEVICE);
2093
2094 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2095out:
15d31758 2096 return skb;
1da177e4
LT		 2097
2098err_out:
1da177e4
LT		 2099 rtl8169_make_unusable_by_asic(desc);
2100 goto out;
2101}
2102
2103static void rtl8169_rx_clear(struct rtl8169_private *tp)
2104{
07d3f51f 2105 unsigned int i;
1da177e4
LT		 2106
2107 for (i = 0; i < NUM_RX_DESC; i++) {
2108 if (tp->Rx_skbuff[i]) {
2109 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2110 tp->RxDescArray + i);
2111 }
2112 }
2113}
2114
2115static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2116 u32 start, u32 end)
2117{
2118 u32 cur;
5b0384f4 2119
4ae47c2d 2120 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2121 struct sk_buff *skb;
2122 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2123
4ae47c2d
FR		 2124 WARN_ON((s32)(end - cur) < 0);
2125
1da177e4
LT		 2126 if (tp->Rx_skbuff[i])
2127 continue;
bcf0bf90 2128
15d31758
SH		 2129 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2130 tp->RxDescArray + i,
2131 tp->rx_buf_sz, tp->align);
2132 if (!skb)
1da177e4 2133 break;
15d31758
SH		 2134
2135 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2136 }
2137 return cur - start;
2138}
2139
2140static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2141{
2142 desc->opts1 |= cpu_to_le32(RingEnd);
2143}
2144
2145static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2146{
2147 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2148}
2149
2150static int rtl8169_init_ring(struct net_device *dev)
2151{
2152 struct rtl8169_private *tp = netdev_priv(dev);
2153
2154 rtl8169_init_ring_indexes(tp);
2155
2156 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2157 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2158
2159 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2160 goto err_out;
2161
2162 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2163
2164 return 0;
2165
2166err_out:
2167 rtl8169_rx_clear(tp);
2168 return -ENOMEM;
2169}
2170
2171static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2172 struct TxDesc *desc)
2173{
2174 unsigned int len = tx_skb->len;
2175
2176 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2177 desc->opts1 = 0x00;
2178 desc->opts2 = 0x00;
2179 desc->addr = 0x00;
2180 tx_skb->len = 0;
2181}
2182
2183static void rtl8169_tx_clear(struct rtl8169_private *tp)
2184{
2185 unsigned int i;
2186
2187 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2188 unsigned int entry = i % NUM_TX_DESC;
2189 struct ring_info *tx_skb = tp->tx_skb + entry;
2190 unsigned int len = tx_skb->len;
2191
2192 if (len) {
2193 struct sk_buff *skb = tx_skb->skb;
2194
2195 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2196 tp->TxDescArray + entry);
2197 if (skb) {
2198 dev_kfree_skb(skb);
2199 tx_skb->skb = NULL;
2200 }
2201 tp->stats.tx_dropped++;
2202 }
2203 }
2204 tp->cur_tx = tp->dirty_tx = 0;
2205}
2206
c4028958 2207static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2208{
2209 struct rtl8169_private *tp = netdev_priv(dev);
2210
c4028958 2211 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2212 schedule_delayed_work(&tp->task, 4);
2213}
2214
2215static void rtl8169_wait_for_quiescence(struct net_device *dev)
2216{
2217 struct rtl8169_private *tp = netdev_priv(dev);
2218 void __iomem *ioaddr = tp->mmio_addr;
2219
2220 synchronize_irq(dev->irq);
2221
2222 /* Wait for any pending NAPI task to complete */
2223 netif_poll_disable(dev);
2224
2225 rtl8169_irq_mask_and_ack(ioaddr);
2226
2227 netif_poll_enable(dev);
2228}
2229
c4028958 2230static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2231{
c4028958
DH		 2232 struct rtl8169_private *tp =
2233 container_of(work, struct rtl8169_private, task.work);
2234 struct net_device *dev = tp->dev;
1da177e4
LT		 2235 int ret;
2236
eb2a021c
FR		 2237 rtnl_lock();
2238
2239 if (!netif_running(dev))
2240 goto out_unlock;
2241
2242 rtl8169_wait_for_quiescence(dev);
2243 rtl8169_close(dev);
1da177e4
LT		 2244
2245 ret = rtl8169_open(dev);
2246 if (unlikely(ret < 0)) {
07d3f51f
FR		 2247 if (net_ratelimit() && netif_msg_drv(tp)) {
2248 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2249 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2250 }
2251 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2252 }
eb2a021c
FR		 2253
2254out_unlock:
2255 rtnl_unlock();
1da177e4
LT		 2256}
2257
c4028958 2258static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2259{
c4028958
DH		 2260 struct rtl8169_private *tp =
2261 container_of(work, struct rtl8169_private, task.work);
2262 struct net_device *dev = tp->dev;
1da177e4 2263
eb2a021c
FR		 2264 rtnl_lock();
2265
1da177e4 2266 if (!netif_running(dev))
eb2a021c 2267 goto out_unlock;
1da177e4
LT		 2268
2269 rtl8169_wait_for_quiescence(dev);
2270
2271 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2272 rtl8169_tx_clear(tp);
2273
2274 if (tp->dirty_rx == tp->cur_rx) {
2275 rtl8169_init_ring_indexes(tp);
07ce4064 2276 rtl_hw_start(dev);
1da177e4
LT		 2277 netif_wake_queue(dev);
2278 } else {
07d3f51f
FR		 2279 if (net_ratelimit() && netif_msg_intr(tp)) {
2280 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2281 dev->name);
1da177e4
LT		 2282 }
2283 rtl8169_schedule_work(dev, rtl8169_reset_task);
2284 }
eb2a021c
FR		 2285
2286out_unlock:
2287 rtnl_unlock();
1da177e4
LT		 2288}
2289
2290static void rtl8169_tx_timeout(struct net_device *dev)
2291{
2292 struct rtl8169_private *tp = netdev_priv(dev);
2293
2294 rtl8169_hw_reset(tp->mmio_addr);
2295
2296 /* Let's wait a bit while any (async) irq lands on */
2297 rtl8169_schedule_work(dev, rtl8169_reset_task);
2298}
2299
2300static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2301 u32 opts1)
2302{
2303 struct skb_shared_info *info = skb_shinfo(skb);
2304 unsigned int cur_frag, entry;
2305 struct TxDesc *txd;
2306
2307 entry = tp->cur_tx;
2308 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2309 skb_frag_t *frag = info->frags + cur_frag;
2310 dma_addr_t mapping;
2311 u32 status, len;
2312 void *addr;
2313
2314 entry = (entry + 1) % NUM_TX_DESC;
2315
2316 txd = tp->TxDescArray + entry;
2317 len = frag->size;
2318 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2319 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2320
2321 /* anti gcc 2.95.3 bugware (sic) */
2322 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2323
2324 txd->opts1 = cpu_to_le32(status);
2325 txd->addr = cpu_to_le64(mapping);
2326
2327 tp->tx_skb[entry].len = len;
2328 }
2329
2330 if (cur_frag) {
2331 tp->tx_skb[entry].skb = skb;
2332 txd->opts1 |= cpu_to_le32(LastFrag);
2333 }
2334
2335 return cur_frag;
2336}
2337
2338static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2339{
2340 if (dev->features & NETIF_F_TSO) {
7967168c 2341 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2342
2343 if (mss)
2344 return LargeSend | ((mss & MSSMask) << MSSShift);
2345 }
84fa7933 2346 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2347 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2348
2349 if (ip->protocol == IPPROTO_TCP)
2350 return IPCS | TCPCS;
2351 else if (ip->protocol == IPPROTO_UDP)
2352 return IPCS | UDPCS;
2353 WARN_ON(1); /* we need a WARN() */
2354 }
2355 return 0;
2356}
2357
2358static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2359{
2360 struct rtl8169_private *tp = netdev_priv(dev);
2361 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2362 struct TxDesc *txd = tp->TxDescArray + entry;
2363 void __iomem *ioaddr = tp->mmio_addr;
2364 dma_addr_t mapping;
2365 u32 status, len;
2366 u32 opts1;
188f4af0 2367 int ret = NETDEV_TX_OK;
5b0384f4 2368
1da177e4 2369 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2370 if (netif_msg_drv(tp)) {
2371 printk(KERN_ERR
2372 "%s: BUG! Tx Ring full when queue awake!\n",
2373 dev->name);
2374 }
1da177e4
LT		 2375 goto err_stop;
2376 }
2377
2378 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2379 goto err_stop;
2380
2381 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2382
2383 frags = rtl8169_xmit_frags(tp, skb, opts1);
2384 if (frags) {
2385 len = skb_headlen(skb);
2386 opts1 |= FirstFrag;
2387 } else {
2388 len = skb->len;
2389
2390 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2391 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2392 goto err_update_stats;
2393 len = ETH_ZLEN;
2394 }
2395
2396 opts1 |= FirstFrag | LastFrag;
2397 tp->tx_skb[entry].skb = skb;
2398 }
2399
2400 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2401
2402 tp->tx_skb[entry].len = len;
2403 txd->addr = cpu_to_le64(mapping);
2404 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2405
2406 wmb();
2407
2408 /* anti gcc 2.95.3 bugware (sic) */
2409 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2410 txd->opts1 = cpu_to_le32(status);
2411
2412 dev->trans_start = jiffies;
2413
2414 tp->cur_tx += frags + 1;
2415
2416 smp_wmb();
2417
275391a4 2418 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2419
2420 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2421 netif_stop_queue(dev);
2422 smp_rmb();
2423 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2424 netif_wake_queue(dev);
2425 }
2426
2427out:
2428 return ret;
2429
2430err_stop:
2431 netif_stop_queue(dev);
188f4af0 2432 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2433err_update_stats:
2434 tp->stats.tx_dropped++;
2435 goto out;
2436}
2437
2438static void rtl8169_pcierr_interrupt(struct net_device *dev)
2439{
2440 struct rtl8169_private *tp = netdev_priv(dev);
2441 struct pci_dev *pdev = tp->pci_dev;
2442 void __iomem *ioaddr = tp->mmio_addr;
2443 u16 pci_status, pci_cmd;
2444
2445 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2446 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2447
b57b7e5a
SH		 2448 if (netif_msg_intr(tp)) {
2449 printk(KERN_ERR
2450 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2451 dev->name, pci_cmd, pci_status);
2452 }
1da177e4
LT		 2453
2454 /*
2455 * The recovery sequence below admits a very elaborated explanation:
2456 * - it seems to work;
d03902b8
FR		 2457 * - I did not see what else could be done;
2458 * - it makes iop3xx happy.
1da177e4
LT		 2459 *
2460 * Feel free to adjust to your needs.
2461 */
a27993f3 2462 if (pdev->broken_parity_status)
d03902b8
FR		 2463 pci_cmd &= ~PCI_COMMAND_PARITY;
2464 else
2465 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2466
2467 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2468
2469 pci_write_config_word(pdev, PCI_STATUS,
2470 pci_status & (PCI_STATUS_DETECTED_PARITY |
2471 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2472 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2473
2474 /* The infamous DAC f*ckup only happens at boot time */
2475 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2476 if (netif_msg_intr(tp))
2477 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2478 tp->cp_cmd &= ~PCIDAC;
2479 RTL_W16(CPlusCmd, tp->cp_cmd);
2480 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2481 }
2482
2483 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2484
2485 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2486}
2487
07d3f51f
FR		 2488static void rtl8169_tx_interrupt(struct net_device *dev,
2489 struct rtl8169_private *tp,
2490 void __iomem *ioaddr)
1da177e4
LT		 2491{
2492 unsigned int dirty_tx, tx_left;
2493
1da177e4
LT		 2494 dirty_tx = tp->dirty_tx;
2495 smp_rmb();
2496 tx_left = tp->cur_tx - dirty_tx;
2497
2498 while (tx_left > 0) {
2499 unsigned int entry = dirty_tx % NUM_TX_DESC;
2500 struct ring_info *tx_skb = tp->tx_skb + entry;
2501 u32 len = tx_skb->len;
2502 u32 status;
2503
2504 rmb();
2505 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2506 if (status & DescOwn)
2507 break;
2508
2509 tp->stats.tx_bytes += len;
2510 tp->stats.tx_packets++;
2511
2512 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2513
2514 if (status & LastFrag) {
2515 dev_kfree_skb_irq(tx_skb->skb);
2516 tx_skb->skb = NULL;
2517 }
2518 dirty_tx++;
2519 tx_left--;
2520 }
2521
2522 if (tp->dirty_tx != dirty_tx) {
2523 tp->dirty_tx = dirty_tx;
2524 smp_wmb();
2525 if (netif_queue_stopped(dev) &&
2526 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2527 netif_wake_queue(dev);
2528 }
2529 }
2530}
2531
126fa4b9
FR		 2532static inline int rtl8169_fragmented_frame(u32 status)
2533{
2534 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2535}
2536
1da177e4
LT		 2537static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2538{
2539 u32 opts1 = le32_to_cpu(desc->opts1);
2540 u32 status = opts1 & RxProtoMask;
2541
2542 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2543 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2544 ((status == RxProtoIP) && !(opts1 & IPFail)))
2545 skb->ip_summed = CHECKSUM_UNNECESSARY;
2546 else
2547 skb->ip_summed = CHECKSUM_NONE;
2548}
2549
07d3f51f
FR		 2550static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2551 struct rtl8169_private *tp, int pkt_size,
2552 dma_addr_t addr)
1da177e4 2553{
b449655f
SH		 2554 struct sk_buff *skb;
2555 bool done = false;
1da177e4 2556
b449655f
SH		 2557 if (pkt_size >= rx_copybreak)
2558 goto out;
1da177e4 2559
07d3f51f 2560 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2561 if (!skb)
2562 goto out;
2563
07d3f51f
FR		 2564 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2565 PCI_DMA_FROMDEVICE);
86402234 2566 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2567 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2568 *sk_buff = skb;
2569 done = true;
2570out:
2571 return done;
1da177e4
LT		 2572}
2573
07d3f51f
FR		 2574static int rtl8169_rx_interrupt(struct net_device *dev,
2575 struct rtl8169_private *tp,
2576 void __iomem *ioaddr)
1da177e4
LT		 2577{
2578 unsigned int cur_rx, rx_left;
2579 unsigned int delta, count;
2580
1da177e4
LT		 2581 cur_rx = tp->cur_rx;
2582 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2583 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2584
4dcb7d33 2585 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2586 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2587 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2588 u32 status;
2589
2590 rmb();
126fa4b9 2591 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2592
2593 if (status & DescOwn)
2594 break;
4dcb7d33 2595 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2596 if (netif_msg_rx_err(tp)) {
2597 printk(KERN_INFO
2598 "%s: Rx ERROR. status = %08x\n",
2599 dev->name, status);
2600 }
1da177e4
LT		 2601 tp->stats.rx_errors++;
2602 if (status & (RxRWT | RxRUNT))
2603 tp->stats.rx_length_errors++;
2604 if (status & RxCRC)
2605 tp->stats.rx_crc_errors++;
9dccf611
FR		 2606 if (status & RxFOVF) {
2607 rtl8169_schedule_work(dev, rtl8169_reset_task);
2608 tp->stats.rx_fifo_errors++;
2609 }
126fa4b9 2610 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2611 } else {
1da177e4 2612 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2613 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2614 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2615 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2616
126fa4b9
FR		 2617 /*
2618 * The driver does not support incoming fragmented
2619 * frames. They are seen as a symptom of over-mtu
2620 * sized frames.
2621 */
2622 if (unlikely(rtl8169_fragmented_frame(status))) {
2623 tp->stats.rx_dropped++;
2624 tp->stats.rx_length_errors++;
2625 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2626 continue;
126fa4b9
FR		 2627 }
2628
1da177e4 2629 rtl8169_rx_csum(skb, desc);
bcf0bf90 2630
07d3f51f 2631 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2632 pci_dma_sync_single_for_device(pdev, addr,
2633 pkt_size, PCI_DMA_FROMDEVICE);
2634 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2635 } else {
2636 pci_unmap_single(pdev, addr, pkt_size,
2637 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2638 tp->Rx_skbuff[entry] = NULL;
2639 }
2640
1da177e4
LT		 2641 skb_put(skb, pkt_size);
2642 skb->protocol = eth_type_trans(skb, dev);
2643
2644 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2645 rtl8169_rx_skb(skb);
2646
2647 dev->last_rx = jiffies;
2648 tp->stats.rx_bytes += pkt_size;
2649 tp->stats.rx_packets++;
2650 }
6dccd16b
FR		 2651
2652 /* Work around for AMD plateform. */
2653 if ((desc->opts2 & 0xfffe000) &&
2654 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2655 desc->opts2 = 0;
2656 cur_rx++;
2657 }
1da177e4
LT		 2658 }
2659
2660 count = cur_rx - tp->cur_rx;
2661 tp->cur_rx = cur_rx;
2662
2663 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2664 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2665 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2666 tp->dirty_rx += delta;
2667
2668 /*
2669 * FIXME: until there is periodic timer to try and refill the ring,
2670 * a temporary shortage may definitely kill the Rx process.
2671 * - disable the asic to try and avoid an overflow and kick it again
2672 * after refill ?
2673 * - how do others driver handle this condition (Uh oh...).
2674 */
b57b7e5a 2675 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2676 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2677
2678 return count;
2679}
2680
07d3f51f 2681static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2682{
07d3f51f 2683 struct net_device *dev = dev_instance;
1da177e4
LT		 2684 struct rtl8169_private *tp = netdev_priv(dev);
2685 int boguscnt = max_interrupt_work;
2686 void __iomem *ioaddr = tp->mmio_addr;
2687 int status;
2688 int handled = 0;
2689
2690 do {
2691 status = RTL_R16(IntrStatus);
2692
2693 /* hotplug/major error/no more work/shared irq */
2694 if ((status == 0xFFFF) || !status)
2695 break;
2696
2697 handled = 1;
2698
2699 if (unlikely(!netif_running(dev))) {
2700 rtl8169_asic_down(ioaddr);
2701 goto out;
2702 }
2703
2704 status &= tp->intr_mask;
2705 RTL_W16(IntrStatus,
2706 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2707
0e485150
FR		 2708 if (!(status & tp->intr_event))
2709 break;
2710
2711 /* Work around for rx fifo overflow */
2712 if (unlikely(status & RxFIFOOver) &&
2713 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2714 netif_stop_queue(dev);
2715 rtl8169_tx_timeout(dev);
1da177e4 2716 break;
0e485150 2717 }
1da177e4
LT		 2718
2719 if (unlikely(status & SYSErr)) {
2720 rtl8169_pcierr_interrupt(dev);
2721 break;
2722 }
2723
2724 if (status & LinkChg)
2725 rtl8169_check_link_status(dev, tp, ioaddr);
2726
2727#ifdef CONFIG_R8169_NAPI
0e485150
FR		 2728 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2729 tp->intr_mask = ~tp->napi_event;
1da177e4
LT		 2730
2731 if (likely(netif_rx_schedule_prep(dev)))
2732 __netif_rx_schedule(dev);
b57b7e5a 2733 else if (netif_msg_intr(tp)) {
1da177e4 2734 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2735 dev->name, status);
1da177e4
LT		 2736 }
2737 break;
2738#else
2739 /* Rx interrupt */
07d3f51f 2740 if (status & (RxOK | RxOverflow | RxFIFOOver))
1da177e4 2741 rtl8169_rx_interrupt(dev, tp, ioaddr);
07d3f51f 2742
1da177e4
LT		 2743 /* Tx interrupt */
2744 if (status & (TxOK | TxErr))
2745 rtl8169_tx_interrupt(dev, tp, ioaddr);
2746#endif
2747
2748 boguscnt--;
2749 } while (boguscnt > 0);
2750
2751 if (boguscnt <= 0) {
7c8b2eb4 2752 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2753 printk(KERN_WARNING
2754 "%s: Too much work at interrupt!\n", dev->name);
2755 }
1da177e4
LT		 2756 /* Clear all interrupt sources. */
2757 RTL_W16(IntrStatus, 0xffff);
2758 }
2759out:
2760 return IRQ_RETVAL(handled);
2761}
2762
2763#ifdef CONFIG_R8169_NAPI
2764static int rtl8169_poll(struct net_device *dev, int *budget)
2765{
2766 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2767 struct rtl8169_private *tp = netdev_priv(dev);
2768 void __iomem *ioaddr = tp->mmio_addr;
2769
2770 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2771 rtl8169_tx_interrupt(dev, tp, ioaddr);
2772
2773 *budget -= work_done;
2774 dev->quota -= work_done;
2775
2776 if (work_done < work_to_do) {
2777 netif_rx_complete(dev);
2778 tp->intr_mask = 0xffff;
2779 /*
2780 * 20040426: the barrier is not strictly required but the
2781 * behavior of the irq handler could be less predictable
2782 * without it. Btw, the lack of flush for the posted pci
2783 * write is safe - FR
2784 */
2785 smp_wmb();
0e485150 2786 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2787 }
2788
2789 return (work_done >= work_to_do);
2790}
2791#endif
2792
2793static void rtl8169_down(struct net_device *dev)
2794{
2795 struct rtl8169_private *tp = netdev_priv(dev);
2796 void __iomem *ioaddr = tp->mmio_addr;
2797 unsigned int poll_locked = 0;
733b736c 2798 unsigned int intrmask;
1da177e4
LT		 2799
2800 rtl8169_delete_timer(dev);
2801
2802 netif_stop_queue(dev);
2803
1da177e4
LT		 2804core_down:
2805 spin_lock_irq(&tp->lock);
2806
2807 rtl8169_asic_down(ioaddr);
2808
2809 /* Update the error counts. */
2810 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2811 RTL_W32(RxMissed, 0);
2812
2813 spin_unlock_irq(&tp->lock);
2814
2815 synchronize_irq(dev->irq);
2816
2817 if (!poll_locked) {
2818 netif_poll_disable(dev);
2819 poll_locked++;
2820 }
2821
2822 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2823 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2824
2825 /*
2826 * And now for the 50k$ question: are IRQ disabled or not ?
2827 *
2828 * Two paths lead here:
2829 * 1) dev->close
2830 * -> netif_running() is available to sync the current code and the
2831 * IRQ handler. See rtl8169_interrupt for details.
2832 * 2) dev->change_mtu
2833 * -> rtl8169_poll can not be issued again and re-enable the
2834 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2835 *
2836 * No loop if hotpluged or major error (0xffff).
1da177e4 2837 */
733b736c
AP		 2838 intrmask = RTL_R16(IntrMask);
2839 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2840 goto core_down;
2841
2842 rtl8169_tx_clear(tp);
2843
2844 rtl8169_rx_clear(tp);
2845}
2846
2847static int rtl8169_close(struct net_device *dev)
2848{
2849 struct rtl8169_private *tp = netdev_priv(dev);
2850 struct pci_dev *pdev = tp->pci_dev;
2851
2852 rtl8169_down(dev);
2853
2854 free_irq(dev->irq, dev);
2855
2856 netif_poll_enable(dev);
2857
2858 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2859 tp->RxPhyAddr);
2860 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2861 tp->TxPhyAddr);
2862 tp->TxDescArray = NULL;
2863 tp->RxDescArray = NULL;
2864
2865 return 0;
2866}
2867
07ce4064 2868static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2869{
2870 struct rtl8169_private *tp = netdev_priv(dev);
2871 void __iomem *ioaddr = tp->mmio_addr;
2872 unsigned long flags;
2873 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2874 int rx_mode;
1da177e4
LT		 2875 u32 tmp = 0;
2876
2877 if (dev->flags & IFF_PROMISC) {
2878 /* Unconditionally log net taps. */
b57b7e5a
SH		 2879 if (netif_msg_link(tp)) {
2880 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2881 dev->name);
2882 }
1da177e4
LT		 2883 rx_mode =
2884 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2885 AcceptAllPhys;
2886 mc_filter[1] = mc_filter[0] = 0xffffffff;
2887 } else if ((dev->mc_count > multicast_filter_limit)
2888 || (dev->flags & IFF_ALLMULTI)) {
2889 /* Too many to filter perfectly -- accept all multicasts. */
2890 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2891 mc_filter[1] = mc_filter[0] = 0xffffffff;
2892 } else {
2893 struct dev_mc_list *mclist;
07d3f51f
FR		 2894 unsigned int i;
2895
1da177e4
LT		 2896 rx_mode = AcceptBroadcast | AcceptMyPhys;
2897 mc_filter[1] = mc_filter[0] = 0;
2898 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2899 i++, mclist = mclist->next) {
2900 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2901 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2902 rx_mode |= AcceptMulticast;
2903 }
2904 }
2905
2906 spin_lock_irqsave(&tp->lock, flags);
2907
2908 tmp = rtl8169_rx_config | rx_mode |
2909 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2910
bcf0bf90
FR		 2911 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2912 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2913 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2914 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2915 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2916 mc_filter[0] = 0xffffffff;
2917 mc_filter[1] = 0xffffffff;
2918 }
2919
1da177e4
LT		 2920 RTL_W32(RxConfig, tmp);
2921 RTL_W32(MAR0 + 0, mc_filter[0]);
2922 RTL_W32(MAR0 + 4, mc_filter[1]);
2923
2924 spin_unlock_irqrestore(&tp->lock, flags);
2925}
2926
2927/**
2928 * rtl8169_get_stats - Get rtl8169 read/write statistics
2929 * @dev: The Ethernet Device to get statistics for
2930 *
2931 * Get TX/RX statistics for rtl8169
2932 */
2933static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2934{
2935 struct rtl8169_private *tp = netdev_priv(dev);
2936 void __iomem *ioaddr = tp->mmio_addr;
2937 unsigned long flags;
2938
2939 if (netif_running(dev)) {
2940 spin_lock_irqsave(&tp->lock, flags);
2941 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2942 RTL_W32(RxMissed, 0);
2943 spin_unlock_irqrestore(&tp->lock, flags);
2944 }
5b0384f4 2945
1da177e4
LT		 2946 return &tp->stats;
2947}
2948
5d06a99f
FR		 2949#ifdef CONFIG_PM
2950
2951static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2952{
2953 struct net_device *dev = pci_get_drvdata(pdev);
2954 struct rtl8169_private *tp = netdev_priv(dev);
2955 void __iomem *ioaddr = tp->mmio_addr;
2956
2957 if (!netif_running(dev))
1371fa6d 2958 goto out_pci_suspend;
5d06a99f
FR		 2959
2960 netif_device_detach(dev);
2961 netif_stop_queue(dev);
2962
2963 spin_lock_irq(&tp->lock);
2964
2965 rtl8169_asic_down(ioaddr);
2966
2967 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2968 RTL_W32(RxMissed, 0);
2969
2970 spin_unlock_irq(&tp->lock);
2971
1371fa6d 2972out_pci_suspend:
5d06a99f 2973 pci_save_state(pdev);
61a4dcc2 2974 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 2975 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 2976
5d06a99f
FR		 2977 return 0;
2978}
2979
2980static int rtl8169_resume(struct pci_dev *pdev)
2981{
2982 struct net_device *dev = pci_get_drvdata(pdev);
2983
1371fa6d
FR		 2984 pci_set_power_state(pdev, PCI_D0);
2985 pci_restore_state(pdev);
2986 pci_enable_wake(pdev, PCI_D0, 0);
2987
5d06a99f
FR		 2988 if (!netif_running(dev))
2989 goto out;
2990
2991 netif_device_attach(dev);
2992
5d06a99f
FR		 2993 rtl8169_schedule_work(dev, rtl8169_reset_task);
2994out:
2995 return 0;
2996}
2997
2998#endif /* CONFIG_PM */
2999
1da177e4
LT		 3000static struct pci_driver rtl8169_pci_driver = {
3001 .name = MODULENAME,
3002 .id_table = rtl8169_pci_tbl,
3003 .probe = rtl8169_init_one,
3004 .remove = __devexit_p(rtl8169_remove_one),
3005#ifdef CONFIG_PM
3006 .suspend = rtl8169_suspend,
3007 .resume = rtl8169_resume,
3008#endif
3009};
3010
07d3f51f 3011static int __init rtl8169_init_module(void)
1da177e4 3012{
29917620 3013 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3014}
3015
07d3f51f 3016static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3017{
3018 pci_unregister_driver(&rtl8169_pci_driver);
3019}
3020
3021module_init(rtl8169_init_module);
3022module_exit(rtl8169_cleanup_module);
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