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r8169: update the phy init for the 8168C
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
06fa7358
JP		 47#define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 49#else
50#define assert(expr) do {} while (0)
51#define dprintk(fmt, args...) do {} while (0)
52#endif /* RTL8169_DEBUG */
53
b57b7e5a 54#define R8169_MSG_DEFAULT \
f0e837d9 55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 56
1da177e4
LT		 57#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60#ifdef CONFIG_R8169_NAPI
61#define rtl8169_rx_skb netif_receive_skb
0b50f81d 62#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 63#define rtl8169_rx_quota(count, quota) min(count, quota)
64#else
65#define rtl8169_rx_skb netif_rx
0b50f81d 66#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 67#define rtl8169_rx_quota(count, quota) count
68#endif
69
1da177e4 70/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 71static const int max_interrupt_work = 20;
1da177e4
LT		 72
73/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 75static const int multicast_filter_limit = 32;
1da177e4
LT		 76
77/* MAC address length */
78#define MAC_ADDR_LEN 6
79
80#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 83#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 84#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87
88#define R8169_REGS_SIZE 256
89#define R8169_NAPI_WEIGHT 64
90#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92#define RX_BUF_SIZE 1536 /* Rx Buffer size */
93#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95
96#define RTL8169_TX_TIMEOUT (6*HZ)
97#define RTL8169_PHY_TIMEOUT (10*HZ)
98
99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
105#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
106
107enum mac_version {
ba6eb6ee
FR		 108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
118 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
119 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
120 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
121 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
122 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
123 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 124};
125
1da177e4
LT		 126#define _R(NAME,MAC,MASK) \
127 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128
3c6bee1d 129static const struct {
1da177e4
LT		 130 const char *name;
131 u8 mac_version;
132 u32 RxConfigMask; /* Clears the bits supported by this chip */
133} rtl_chip_info[] = {
ba6eb6ee
FR		 134 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 144 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
147 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 150};
151#undef _R
152
bcf0bf90
FR		 153enum cfg_version {
154 RTL_CFG_0 = 0x00,
155 RTL_CFG_1,
156 RTL_CFG_2
157};
158
07ce4064
FR		 159static void rtl_hw_start_8169(struct net_device *);
160static void rtl_hw_start_8168(struct net_device *);
161static void rtl_hw_start_8101(struct net_device *);
162
1da177e4 163static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 170 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 171 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
172 { PCI_VENDOR_ID_LINKSYS, 0x1032,
173 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 174 {0,},
175};
176
177MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179static int rx_copybreak = 200;
180static int use_dac;
b57b7e5a
SH		 181static struct {
182 u32 msg_enable;
183} debug = { -1 };
1da177e4 184
07d3f51f
FR		 185enum rtl_registers {
186 MAC0 = 0, /* Ethernet hardware address. */
773d2021 187 MAC4 = 4,
07d3f51f
FR		 188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
195 FLASH = 0x30,
196 ERSR = 0x36,
197 ChipCmd = 0x37,
198 TxPoll = 0x38,
199 IntrMask = 0x3c,
200 IntrStatus = 0x3e,
201 TxConfig = 0x40,
202 RxConfig = 0x44,
203 RxMissed = 0x4c,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
208 Config3 = 0x54,
209 Config4 = 0x55,
210 Config5 = 0x56,
211 MultiIntr = 0x5c,
212 PHYAR = 0x60,
213 TBICSR = 0x64,
214 TBI_ANAR = 0x68,
215 TBI_LPAR = 0x6a,
216 PHYstatus = 0x6c,
217 RxMaxSize = 0xda,
218 CPlusCmd = 0xe0,
219 IntrMitigate = 0xe2,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
222 EarlyTxThres = 0xec,
223 FuncEvent = 0xf0,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
1da177e4
LT		 227};
228
07d3f51f 229enum rtl_register_content {
1da177e4 230 /* InterruptStatusBits */
07d3f51f
FR		 231 SYSErr = 0x8000,
232 PCSTimeout = 0x4000,
233 SWInt = 0x0100,
234 TxDescUnavail = 0x0080,
235 RxFIFOOver = 0x0040,
236 LinkChg = 0x0020,
237 RxOverflow = 0x0010,
238 TxErr = 0x0008,
239 TxOK = 0x0004,
240 RxErr = 0x0002,
241 RxOK = 0x0001,
1da177e4
LT		 242
243 /* RxStatusDesc */
9dccf611
FR		 244 RxFOVF = (1 << 23),
245 RxRWT = (1 << 22),
246 RxRES = (1 << 21),
247 RxRUNT = (1 << 20),
248 RxCRC = (1 << 19),
1da177e4
LT		 249
250 /* ChipCmdBits */
07d3f51f
FR		 251 CmdReset = 0x10,
252 CmdRxEnb = 0x08,
253 CmdTxEnb = 0x04,
254 RxBufEmpty = 0x01,
1da177e4 255
275391a4
FR		 256 /* TXPoll register p.5 */
257 HPQ = 0x80, /* Poll cmd on the high prio queue */
258 NPQ = 0x40, /* Poll cmd on the low prio queue */
259 FSWInt = 0x01, /* Forced software interrupt */
260
1da177e4 261 /* Cfg9346Bits */
07d3f51f
FR		 262 Cfg9346_Lock = 0x00,
263 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 264
265 /* rx_mode_bits */
07d3f51f
FR		 266 AcceptErr = 0x20,
267 AcceptRunt = 0x10,
268 AcceptBroadcast = 0x08,
269 AcceptMulticast = 0x04,
270 AcceptMyPhys = 0x02,
271 AcceptAllPhys = 0x01,
1da177e4
LT		 272
273 /* RxConfigBits */
07d3f51f
FR		 274 RxCfgFIFOShift = 13,
275 RxCfgDMAShift = 8,
1da177e4
LT		 276
277 /* TxConfigBits */
278 TxInterFrameGapShift = 24,
279 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
280
5d06a99f 281 /* Config1 register p.24 */
fbac58fc 282 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 283 PMEnable = (1 << 0), /* Power Management Enable */
284
6dccd16b
FR		 285 /* Config2 register p. 25 */
286 PCI_Clock_66MHz = 0x01,
287 PCI_Clock_33MHz = 0x00,
288
61a4dcc2
FR		 289 /* Config3 register p.25 */
290 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
291 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
292
5d06a99f 293 /* Config5 register p.27 */
61a4dcc2
FR		 294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
299
1da177e4
LT		 300 /* TBICSR p.28 */
301 TBIReset = 0x80000000,
302 TBILoopback = 0x40000000,
303 TBINwEnable = 0x20000000,
304 TBINwRestart = 0x10000000,
305 TBILinkOk = 0x02000000,
306 TBINwComplete = 0x01000000,
307
308 /* CPlusCmd p.31 */
0e485150 309 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 310 RxVlan = (1 << 6),
311 RxChkSum = (1 << 5),
312 PCIDAC = (1 << 4),
313 PCIMulRW = (1 << 3),
0e485150
FR		 314 INTT_0 = 0x0000, // 8168
315 INTT_1 = 0x0001, // 8168
316 INTT_2 = 0x0002, // 8168
317 INTT_3 = 0x0003, // 8168
1da177e4
LT		 318
319 /* rtl8169_PHYstatus */
07d3f51f
FR		 320 TBI_Enable = 0x80,
321 TxFlowCtrl = 0x40,
322 RxFlowCtrl = 0x20,
323 _1000bpsF = 0x10,
324 _100bps = 0x08,
325 _10bps = 0x04,
326 LinkStatus = 0x02,
327 FullDup = 0x01,
1da177e4 328
1da177e4 329 /* _TBICSRBit */
07d3f51f 330 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 331
332 /* DumpCounterCommand */
07d3f51f 333 CounterDump = 0x8,
1da177e4
LT		 334};
335
07d3f51f 336enum desc_status_bit {
1da177e4
LT		 337 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
338 RingEnd = (1 << 30), /* End of descriptor ring */
339 FirstFrag = (1 << 29), /* First segment of a packet */
340 LastFrag = (1 << 28), /* Final segment of a packet */
341
342 /* Tx private */
343 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
344 MSSShift = 16, /* MSS value position */
345 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
346 IPCS = (1 << 18), /* Calculate IP checksum */
347 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
348 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
349 TxVlanTag = (1 << 17), /* Add VLAN tag */
350
351 /* Rx private */
352 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
353 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
354
355#define RxProtoUDP (PID1)
356#define RxProtoTCP (PID0)
357#define RxProtoIP (PID1 | PID0)
358#define RxProtoMask RxProtoIP
359
360 IPFail = (1 << 16), /* IP checksum failed */
361 UDPFail = (1 << 15), /* UDP/IP checksum failed */
362 TCPFail = (1 << 14), /* TCP/IP checksum failed */
363 RxVlanTag = (1 << 16), /* VLAN tag available */
364};
365
366#define RsvdMask 0x3fffc000
367
368struct TxDesc {
6cccd6e7
REB		 369 __le32 opts1;
370 __le32 opts2;
371 __le64 addr;
1da177e4
LT		 372};
373
374struct RxDesc {
6cccd6e7
REB		 375 __le32 opts1;
376 __le32 opts2;
377 __le64 addr;
1da177e4
LT		 378};
379
380struct ring_info {
381 struct sk_buff *skb;
382 u32 len;
383 u8 __pad[sizeof(void *) - sizeof(u32)];
384};
385
f23e7fda
FR		 386enum features {
387 RTL_FEATURE_WOL = (1 << 0),
fbac58fc 388 RTL_FEATURE_MSI = (1 << 1),
f23e7fda
FR		 389};
390
1da177e4
LT		 391struct rtl8169_private {
392 void __iomem *mmio_addr; /* memory map physical address */
393 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 394 struct net_device *dev;
bea3348e 395 struct napi_struct napi;
1da177e4 396 spinlock_t lock; /* spin lock flag */
b57b7e5a 397 u32 msg_enable;
1da177e4
LT		 398 int chipset;
399 int mac_version;
1da177e4
LT		 400 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
401 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
402 u32 dirty_rx;
403 u32 dirty_tx;
404 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
405 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
406 dma_addr_t TxPhyAddr;
407 dma_addr_t RxPhyAddr;
408 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
409 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 410 unsigned align;
1da177e4
LT		 411 unsigned rx_buf_sz;
412 struct timer_list timer;
413 u16 cp_cmd;
0e485150
FR		 414 u16 intr_event;
415 u16 napi_event;
1da177e4
LT		 416 u16 intr_mask;
417 int phy_auto_nego_reg;
418 int phy_1000_ctrl_reg;
419#ifdef CONFIG_R8169_VLAN
420 struct vlan_group *vlgrp;
421#endif
422 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
423 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
424 void (*phy_reset_enable)(void __iomem *);
07ce4064 425 void (*hw_start)(struct net_device *);
1da177e4
LT		 426 unsigned int (*phy_reset_pending)(void __iomem *);
427 unsigned int (*link_ok)(void __iomem *);
c4028958 428 struct delayed_work task;
f23e7fda 429 unsigned features;
1da177e4
LT		 430};
431
979b6c13 432MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 433MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 434module_param(rx_copybreak, int, 0);
1b7efd58 435MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 436module_param(use_dac, int, 0);
437MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 438module_param_named(debug, debug.msg_enable, int, 0);
439MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 440MODULE_LICENSE("GPL");
441MODULE_VERSION(RTL8169_VERSION);
442
443static int rtl8169_open(struct net_device *dev);
444static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 445static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 446static int rtl8169_init_ring(struct net_device *dev);
07ce4064 447static void rtl_hw_start(struct net_device *dev);
1da177e4 448static int rtl8169_close(struct net_device *dev);
07ce4064 449static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 450static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 451static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 452static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 453 void __iomem *, u32 budget);
4dcb7d33 454static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 455static void rtl8169_down(struct net_device *dev);
99f252b0 456static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 457
458#ifdef CONFIG_R8169_NAPI
bea3348e 459static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 460#endif
461
1da177e4 462static const unsigned int rtl8169_rx_config =
5b0384f4 463 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 464
07d3f51f 465static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 466{
467 int i;
468
07d3f51f 469 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 470
2371408c 471 for (i = 20; i > 0; i--) {
07d3f51f
FR		 472 /*
473 * Check if the RTL8169 has completed writing to the specified
474 * MII register.
475 */
5b0384f4 476 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 477 break;
2371408c 478 udelay(25);
1da177e4
LT		 479 }
480}
481
07d3f51f 482static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 483{
484 int i, value = -1;
485
07d3f51f 486 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 487
2371408c 488 for (i = 20; i > 0; i--) {
07d3f51f
FR		 489 /*
490 * Check if the RTL8169 has completed retrieving data from
491 * the specified MII register.
492 */
1da177e4
LT		 493 if (RTL_R32(PHYAR) & 0x80000000) {
494 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
495 break;
496 }
2371408c 497 udelay(25);
1da177e4
LT		 498 }
499 return value;
500}
501
502static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
503{
504 RTL_W16(IntrMask, 0x0000);
505
506 RTL_W16(IntrStatus, 0xffff);
507}
508
509static void rtl8169_asic_down(void __iomem *ioaddr)
510{
511 RTL_W8(ChipCmd, 0x00);
512 rtl8169_irq_mask_and_ack(ioaddr);
513 RTL_R16(CPlusCmd);
514}
515
516static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
517{
518 return RTL_R32(TBICSR) & TBIReset;
519}
520
521static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
522{
64e4bfb4 523 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 524}
525
526static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
527{
528 return RTL_R32(TBICSR) & TBILinkOk;
529}
530
531static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
532{
533 return RTL_R8(PHYstatus) & LinkStatus;
534}
535
536static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
537{
538 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
539}
540
541static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
542{
543 unsigned int val;
544
9e0db8ef
FR		 545 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
546 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 547}
548
549static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 550 struct rtl8169_private *tp,
551 void __iomem *ioaddr)
1da177e4
LT		 552{
553 unsigned long flags;
554
555 spin_lock_irqsave(&tp->lock, flags);
556 if (tp->link_ok(ioaddr)) {
557 netif_carrier_on(dev);
b57b7e5a
SH		 558 if (netif_msg_ifup(tp))
559 printk(KERN_INFO PFX "%s: link up\n", dev->name);
560 } else {
561 if (netif_msg_ifdown(tp))
562 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 563 netif_carrier_off(dev);
b57b7e5a 564 }
1da177e4
LT		 565 spin_unlock_irqrestore(&tp->lock, flags);
566}
567
61a4dcc2
FR		 568static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
569{
570 struct rtl8169_private *tp = netdev_priv(dev);
571 void __iomem *ioaddr = tp->mmio_addr;
572 u8 options;
573
574 wol->wolopts = 0;
575
576#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
577 wol->supported = WAKE_ANY;
578
579 spin_lock_irq(&tp->lock);
580
581 options = RTL_R8(Config1);
582 if (!(options & PMEnable))
583 goto out_unlock;
584
585 options = RTL_R8(Config3);
586 if (options & LinkUp)
587 wol->wolopts |= WAKE_PHY;
588 if (options & MagicPacket)
589 wol->wolopts |= WAKE_MAGIC;
590
591 options = RTL_R8(Config5);
592 if (options & UWF)
593 wol->wolopts |= WAKE_UCAST;
594 if (options & BWF)
5b0384f4 595 wol->wolopts |= WAKE_BCAST;
61a4dcc2 596 if (options & MWF)
5b0384f4 597 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 598
599out_unlock:
600 spin_unlock_irq(&tp->lock);
601}
602
603static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
604{
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 607 unsigned int i;
61a4dcc2
FR		 608 static struct {
609 u32 opt;
610 u16 reg;
611 u8 mask;
612 } cfg[] = {
613 { WAKE_ANY, Config1, PMEnable },
614 { WAKE_PHY, Config3, LinkUp },
615 { WAKE_MAGIC, Config3, MagicPacket },
616 { WAKE_UCAST, Config5, UWF },
617 { WAKE_BCAST, Config5, BWF },
618 { WAKE_MCAST, Config5, MWF },
619 { WAKE_ANY, Config5, LanWake }
620 };
621
622 spin_lock_irq(&tp->lock);
623
624 RTL_W8(Cfg9346, Cfg9346_Unlock);
625
626 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
627 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
628 if (wol->wolopts & cfg[i].opt)
629 options |= cfg[i].mask;
630 RTL_W8(cfg[i].reg, options);
631 }
632
633 RTL_W8(Cfg9346, Cfg9346_Lock);
634
f23e7fda
FR		 635 if (wol->wolopts)
636 tp->features |= RTL_FEATURE_WOL;
637 else
638 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 639
640 spin_unlock_irq(&tp->lock);
641
642 return 0;
643}
644
1da177e4
LT		 645static void rtl8169_get_drvinfo(struct net_device *dev,
646 struct ethtool_drvinfo *info)
647{
648 struct rtl8169_private *tp = netdev_priv(dev);
649
650 strcpy(info->driver, MODULENAME);
651 strcpy(info->version, RTL8169_VERSION);
652 strcpy(info->bus_info, pci_name(tp->pci_dev));
653}
654
655static int rtl8169_get_regs_len(struct net_device *dev)
656{
657 return R8169_REGS_SIZE;
658}
659
660static int rtl8169_set_speed_tbi(struct net_device *dev,
661 u8 autoneg, u16 speed, u8 duplex)
662{
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
665 int ret = 0;
666 u32 reg;
667
668 reg = RTL_R32(TBICSR);
669 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
670 (duplex == DUPLEX_FULL)) {
671 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
672 } else if (autoneg == AUTONEG_ENABLE)
673 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
674 else {
b57b7e5a
SH		 675 if (netif_msg_link(tp)) {
676 printk(KERN_WARNING "%s: "
677 "incorrect speed setting refused in TBI mode\n",
678 dev->name);
679 }
1da177e4
LT		 680 ret = -EOPNOTSUPP;
681 }
682
683 return ret;
684}
685
686static int rtl8169_set_speed_xmii(struct net_device *dev,
687 u8 autoneg, u16 speed, u8 duplex)
688{
689 struct rtl8169_private *tp = netdev_priv(dev);
690 void __iomem *ioaddr = tp->mmio_addr;
691 int auto_nego, giga_ctrl;
692
64e4bfb4
FR		 693 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
694 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
695 ADVERTISE_100HALF | ADVERTISE_100FULL);
696 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 698
699 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 700 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
701 ADVERTISE_100HALF | ADVERTISE_100FULL);
702 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 703 } else {
704 if (speed == SPEED_10)
64e4bfb4 705 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 706 else if (speed == SPEED_100)
64e4bfb4 707 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 708 else if (speed == SPEED_1000)
64e4bfb4 709 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 710
711 if (duplex == DUPLEX_HALF)
64e4bfb4 712 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 713
714 if (duplex == DUPLEX_FULL)
64e4bfb4 715 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 716
717 /* This tweak comes straight from Realtek's driver. */
718 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 719 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
720 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 721 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 722 }
723 }
724
725 /* The 8100e/8101e do Fast Ethernet only. */
726 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 728 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
729 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 730 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 731 netif_msg_link(tp)) {
732 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
733 dev->name);
734 }
64e4bfb4 735 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 736 }
737
623a1593
FR		 738 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
739
e3cf0cc0
FR		 740 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
741 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 742 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
743 mdio_write(ioaddr, 0x1f, 0x0000);
744 mdio_write(ioaddr, 0x0e, 0x0000);
745 }
746
1da177e4
LT		 747 tp->phy_auto_nego_reg = auto_nego;
748 tp->phy_1000_ctrl_reg = giga_ctrl;
749
64e4bfb4
FR		 750 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
751 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
752 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 753 return 0;
754}
755
756static int rtl8169_set_speed(struct net_device *dev,
757 u8 autoneg, u16 speed, u8 duplex)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 int ret;
761
762 ret = tp->set_speed(dev, autoneg, speed, duplex);
763
64e4bfb4 764 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 765 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
766
767 return ret;
768}
769
770static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773 unsigned long flags;
774 int ret;
775
776 spin_lock_irqsave(&tp->lock, flags);
777 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
778 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 779
1da177e4
LT		 780 return ret;
781}
782
783static u32 rtl8169_get_rx_csum(struct net_device *dev)
784{
785 struct rtl8169_private *tp = netdev_priv(dev);
786
787 return tp->cp_cmd & RxChkSum;
788}
789
790static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
791{
792 struct rtl8169_private *tp = netdev_priv(dev);
793 void __iomem *ioaddr = tp->mmio_addr;
794 unsigned long flags;
795
796 spin_lock_irqsave(&tp->lock, flags);
797
798 if (data)
799 tp->cp_cmd |= RxChkSum;
800 else
801 tp->cp_cmd &= ~RxChkSum;
802
803 RTL_W16(CPlusCmd, tp->cp_cmd);
804 RTL_R16(CPlusCmd);
805
806 spin_unlock_irqrestore(&tp->lock, flags);
807
808 return 0;
809}
810
811#ifdef CONFIG_R8169_VLAN
812
813static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
814 struct sk_buff *skb)
815{
816 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
817 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
818}
819
820static void rtl8169_vlan_rx_register(struct net_device *dev,
821 struct vlan_group *grp)
822{
823 struct rtl8169_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->mmio_addr;
825 unsigned long flags;
826
827 spin_lock_irqsave(&tp->lock, flags);
828 tp->vlgrp = grp;
829 if (tp->vlgrp)
830 tp->cp_cmd |= RxVlan;
831 else
832 tp->cp_cmd &= ~RxVlan;
833 RTL_W16(CPlusCmd, tp->cp_cmd);
834 RTL_R16(CPlusCmd);
835 spin_unlock_irqrestore(&tp->lock, flags);
836}
837
1da177e4
LT		 838static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
839 struct sk_buff *skb)
840{
841 u32 opts2 = le32_to_cpu(desc->opts2);
842 int ret;
843
844 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 845 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 846 ret = 0;
847 } else
848 ret = -1;
849 desc->opts2 = 0;
850 return ret;
851}
852
853#else /* !CONFIG_R8169_VLAN */
854
855static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
856 struct sk_buff *skb)
857{
858 return 0;
859}
860
861static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
862 struct sk_buff *skb)
863{
864 return -1;
865}
866
867#endif
868
869static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 u32 status;
874
875 cmd->supported =
876 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
877 cmd->port = PORT_FIBRE;
878 cmd->transceiver = XCVR_INTERNAL;
879
880 status = RTL_R32(TBICSR);
881 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
882 cmd->autoneg = !!(status & TBINwEnable);
883
884 cmd->speed = SPEED_1000;
885 cmd->duplex = DUPLEX_FULL; /* Always set */
886}
887
888static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
889{
890 struct rtl8169_private *tp = netdev_priv(dev);
891 void __iomem *ioaddr = tp->mmio_addr;
892 u8 status;
893
894 cmd->supported = SUPPORTED_10baseT_Half |
895 SUPPORTED_10baseT_Full |
896 SUPPORTED_100baseT_Half |
897 SUPPORTED_100baseT_Full |
898 SUPPORTED_1000baseT_Full |
899 SUPPORTED_Autoneg |
5b0384f4 900 SUPPORTED_TP;
1da177e4
LT		 901
902 cmd->autoneg = 1;
903 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
904
64e4bfb4 905 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 906 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 907 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 908 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 909 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 910 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 911 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 912 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 913 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 914 cmd->advertising |= ADVERTISED_1000baseT_Full;
915
916 status = RTL_R8(PHYstatus);
917
918 if (status & _1000bpsF)
919 cmd->speed = SPEED_1000;
920 else if (status & _100bps)
921 cmd->speed = SPEED_100;
922 else if (status & _10bps)
923 cmd->speed = SPEED_10;
924
623a1593
FR		 925 if (status & TxFlowCtrl)
926 cmd->advertising |= ADVERTISED_Asym_Pause;
927 if (status & RxFlowCtrl)
928 cmd->advertising |= ADVERTISED_Pause;
929
1da177e4
LT		 930 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
931 DUPLEX_FULL : DUPLEX_HALF;
932}
933
934static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
935{
936 struct rtl8169_private *tp = netdev_priv(dev);
937 unsigned long flags;
938
939 spin_lock_irqsave(&tp->lock, flags);
940
941 tp->get_settings(dev, cmd);
942
943 spin_unlock_irqrestore(&tp->lock, flags);
944 return 0;
945}
946
947static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
948 void *p)
949{
5b0384f4
FR		 950 struct rtl8169_private *tp = netdev_priv(dev);
951 unsigned long flags;
1da177e4 952
5b0384f4
FR		 953 if (regs->len > R8169_REGS_SIZE)
954 regs->len = R8169_REGS_SIZE;
1da177e4 955
5b0384f4
FR		 956 spin_lock_irqsave(&tp->lock, flags);
957 memcpy_fromio(p, tp->mmio_addr, regs->len);
958 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 959}
960
b57b7e5a
SH		 961static u32 rtl8169_get_msglevel(struct net_device *dev)
962{
963 struct rtl8169_private *tp = netdev_priv(dev);
964
965 return tp->msg_enable;
966}
967
968static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
969{
970 struct rtl8169_private *tp = netdev_priv(dev);
971
972 tp->msg_enable = value;
973}
974
d4a3a0fc
SH		 975static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
976 "tx_packets",
977 "rx_packets",
978 "tx_errors",
979 "rx_errors",
980 "rx_missed",
981 "align_errors",
982 "tx_single_collisions",
983 "tx_multi_collisions",
984 "unicast",
985 "broadcast",
986 "multicast",
987 "tx_aborted",
988 "tx_underrun",
989};
990
991struct rtl8169_counters {
b1eab701
AV		 992 __le64 tx_packets;
993 __le64 rx_packets;
994 __le64 tx_errors;
995 __le32 rx_errors;
996 __le16 rx_missed;
997 __le16 align_errors;
998 __le32 tx_one_collision;
999 __le32 tx_multi_collision;
1000 __le64 rx_unicast;
1001 __le64 rx_broadcast;
1002 __le32 rx_multicast;
1003 __le16 tx_aborted;
1004 __le16 tx_underun;
d4a3a0fc
SH		 1005};
1006
b9f2c044 1007static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1008{
b9f2c044
JG		 1009 switch (sset) {
1010 case ETH_SS_STATS:
1011 return ARRAY_SIZE(rtl8169_gstrings);
1012 default:
1013 return -EOPNOTSUPP;
1014 }
d4a3a0fc
SH		 1015}
1016
1017static void rtl8169_get_ethtool_stats(struct net_device *dev,
1018 struct ethtool_stats *stats, u64 *data)
1019{
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->mmio_addr;
1022 struct rtl8169_counters *counters;
1023 dma_addr_t paddr;
1024 u32 cmd;
1025
1026 ASSERT_RTNL();
1027
1028 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1029 if (!counters)
1030 return;
1031
1032 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1033 cmd = (u64)paddr & DMA_32BIT_MASK;
1034 RTL_W32(CounterAddrLow, cmd);
1035 RTL_W32(CounterAddrLow, cmd | CounterDump);
1036
1037 while (RTL_R32(CounterAddrLow) & CounterDump) {
1038 if (msleep_interruptible(1))
1039 break;
1040 }
1041
1042 RTL_W32(CounterAddrLow, 0);
1043 RTL_W32(CounterAddrHigh, 0);
1044
5b0384f4 1045 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1046 data[1] = le64_to_cpu(counters->rx_packets);
1047 data[2] = le64_to_cpu(counters->tx_errors);
1048 data[3] = le32_to_cpu(counters->rx_errors);
1049 data[4] = le16_to_cpu(counters->rx_missed);
1050 data[5] = le16_to_cpu(counters->align_errors);
1051 data[6] = le32_to_cpu(counters->tx_one_collision);
1052 data[7] = le32_to_cpu(counters->tx_multi_collision);
1053 data[8] = le64_to_cpu(counters->rx_unicast);
1054 data[9] = le64_to_cpu(counters->rx_broadcast);
1055 data[10] = le32_to_cpu(counters->rx_multicast);
1056 data[11] = le16_to_cpu(counters->tx_aborted);
1057 data[12] = le16_to_cpu(counters->tx_underun);
1058
1059 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1060}
1061
1062static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1063{
1064 switch(stringset) {
1065 case ETH_SS_STATS:
1066 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1067 break;
1068 }
1069}
1070
7282d491 1071static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1072 .get_drvinfo = rtl8169_get_drvinfo,
1073 .get_regs_len = rtl8169_get_regs_len,
1074 .get_link = ethtool_op_get_link,
1075 .get_settings = rtl8169_get_settings,
1076 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1077 .get_msglevel = rtl8169_get_msglevel,
1078 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1079 .get_rx_csum = rtl8169_get_rx_csum,
1080 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1081 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1082 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1083 .set_tso = ethtool_op_set_tso,
1084 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1085 .get_wol = rtl8169_get_wol,
1086 .set_wol = rtl8169_set_wol,
d4a3a0fc 1087 .get_strings = rtl8169_get_strings,
b9f2c044 1088 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1089 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1090};
1091
07d3f51f
FR		 1092static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1093 int bitnum, int bitval)
1da177e4
LT		 1094{
1095 int val;
1096
1097 val = mdio_read(ioaddr, reg);
1098 val = (bitval == 1) ?
1099 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1100 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1101}
1102
07d3f51f
FR		 1103static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1104 void __iomem *ioaddr)
1da177e4 1105{
0e485150
FR		 1106 /*
1107 * The driver currently handles the 8168Bf and the 8168Be identically
1108 * but they can be identified more specifically through the test below
1109 * if needed:
1110 *
1111 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1112 *
1113 * Same thing for the 8101Eb and the 8101Ec:
1114 *
1115 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1116 */
1da177e4
LT		 1117 const struct {
1118 u32 mask;
e3cf0cc0 1119 u32 val;
1da177e4
LT		 1120 int mac_version;
1121 } mac_info[] = {
e3cf0cc0
FR		 1122 /* 8168B family. */
1123 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1124 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1125 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1126 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1127
1128 /* 8168B family. */
1129 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1130 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1131 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1132 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1133
1134 /* 8101 family. */
1135 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1136 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1138 /* FIXME: where did these entries come from ? -- FR */
1139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1141
1142 /* 8110 family. */
1143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1149
1150 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1151 }, *p = mac_info;
1152 u32 reg;
1153
e3cf0cc0
FR		 1154 reg = RTL_R32(TxConfig);
1155 while ((reg & p->mask) != p->val)
1da177e4
LT		 1156 p++;
1157 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1158
1159 if (p->mask == 0x00000000) {
1160 struct pci_dev *pdev = tp->pci_dev;
1161
1162 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1163 }
1da177e4
LT		 1164}
1165
1166static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1167{
bcf0bf90 1168 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1169}
1170
867763c1
FR		 1171struct phy_reg {
1172 u16 reg;
1173 u16 val;
1174};
1175
1176static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1177{
1178 while (len-- > 0) {
1179 mdio_write(ioaddr, regs->reg, regs->val);
1180 regs++;
1181 }
1182}
1183
5615d9f1 1184static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1185{
1da177e4
LT		 1186 struct {
1187 u16 regs[5]; /* Beware of bit-sign propagation */
1188 } phy_magic[5] = { {
1189 { 0x0000, //w 4 15 12 0
1190 0x00a1, //w 3 15 0 00a1
1191 0x0008, //w 2 15 0 0008
1192 0x1020, //w 1 15 0 1020
1193 0x1000 } },{ //w 0 15 0 1000
1194 { 0x7000, //w 4 15 12 7
1195 0xff41, //w 3 15 0 ff41
1196 0xde60, //w 2 15 0 de60
1197 0x0140, //w 1 15 0 0140
1198 0x0077 } },{ //w 0 15 0 0077
1199 { 0xa000, //w 4 15 12 a
1200 0xdf01, //w 3 15 0 df01
1201 0xdf20, //w 2 15 0 df20
1202 0xff95, //w 1 15 0 ff95
1203 0xfa00 } },{ //w 0 15 0 fa00
1204 { 0xb000, //w 4 15 12 b
1205 0xff41, //w 3 15 0 ff41
1206 0xde20, //w 2 15 0 de20
1207 0x0140, //w 1 15 0 0140
1208 0x00bb } },{ //w 0 15 0 00bb
1209 { 0xf000, //w 4 15 12 f
1210 0xdf01, //w 3 15 0 df01
1211 0xdf20, //w 2 15 0 df20
1212 0xff95, //w 1 15 0 ff95
1213 0xbf00 } //w 0 15 0 bf00
1214 }
1215 }, *p = phy_magic;
07d3f51f 1216 unsigned int i;
1da177e4 1217
a441d7b6
FR		 1218 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1219 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1220 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1221 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1222
1223 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1224 int val, pos = 4;
1225
1226 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1227 mdio_write(ioaddr, pos, val);
1228 while (--pos >= 0)
1229 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1230 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1231 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1232 }
a441d7b6 1233 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1234}
1235
5615d9f1
FR		 1236static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1237{
a441d7b6
FR		 1238 struct phy_reg phy_reg_init[] = {
1239 { 0x1f, 0x0002 },
1240 { 0x01, 0x90d0 },
1241 { 0x1f, 0x0000 }
1242 };
1243
1244 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1245}
1246
867763c1
FR		 1247static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1248{
1249 struct phy_reg phy_reg_init[] = {
1250 { 0x1f, 0x0000 },
1251 { 0x1d, 0x0f00 },
1252 { 0x1f, 0x0002 },
1253 { 0x0c, 0x1ec8 },
1254 { 0x1f, 0x0000 }
1255 };
1256
1257 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1258}
1259
1260static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1261{
1262 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1263 { 0x1f, 0x0001 },
1264 { 0x12, 0x2300 },
867763c1
FR		 1265 { 0x1f, 0x0002 },
1266 { 0x00, 0x88d4 },
1267 { 0x01, 0x82b1 },
1268 { 0x03, 0x7002 },
1269 { 0x08, 0x9e30 },
1270 { 0x09, 0x01f0 },
1271 { 0x0a, 0x5500 },
1272 { 0x0c, 0x00c8 },
1273 { 0x1f, 0x0003 },
1274 { 0x12, 0xc096 },
1275 { 0x16, 0x000a },
1276 { 0x1f, 0x0000 }
1277 };
1278
1279 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1280}
1281
5615d9f1
FR		 1282static void rtl_hw_phy_config(struct net_device *dev)
1283{
1284 struct rtl8169_private *tp = netdev_priv(dev);
1285 void __iomem *ioaddr = tp->mmio_addr;
1286
1287 rtl8169_print_mac_version(tp);
1288
1289 switch (tp->mac_version) {
1290 case RTL_GIGA_MAC_VER_01:
1291 break;
1292 case RTL_GIGA_MAC_VER_02:
1293 case RTL_GIGA_MAC_VER_03:
1294 rtl8169s_hw_phy_config(ioaddr);
1295 break;
1296 case RTL_GIGA_MAC_VER_04:
1297 rtl8169sb_hw_phy_config(ioaddr);
1298 break;
867763c1
FR		 1299 case RTL_GIGA_MAC_VER_18:
1300 rtl8168cp_hw_phy_config(ioaddr);
1301 break;
1302 case RTL_GIGA_MAC_VER_19:
1303 rtl8168c_hw_phy_config(ioaddr);
1304 break;
5615d9f1
FR		 1305 default:
1306 break;
1307 }
1308}
1309
1da177e4
LT		 1310static void rtl8169_phy_timer(unsigned long __opaque)
1311{
1312 struct net_device *dev = (struct net_device *)__opaque;
1313 struct rtl8169_private *tp = netdev_priv(dev);
1314 struct timer_list *timer = &tp->timer;
1315 void __iomem *ioaddr = tp->mmio_addr;
1316 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1317
bcf0bf90 1318 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1319
64e4bfb4 1320 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1321 return;
1322
1323 spin_lock_irq(&tp->lock);
1324
1325 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1326 /*
1da177e4
LT		 1327 * A busy loop could burn quite a few cycles on nowadays CPU.
1328 * Let's delay the execution of the timer for a few ticks.
1329 */
1330 timeout = HZ/10;
1331 goto out_mod_timer;
1332 }
1333
1334 if (tp->link_ok(ioaddr))
1335 goto out_unlock;
1336
b57b7e5a
SH		 1337 if (netif_msg_link(tp))
1338 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1339
1340 tp->phy_reset_enable(ioaddr);
1341
1342out_mod_timer:
1343 mod_timer(timer, jiffies + timeout);
1344out_unlock:
1345 spin_unlock_irq(&tp->lock);
1346}
1347
1348static inline void rtl8169_delete_timer(struct net_device *dev)
1349{
1350 struct rtl8169_private *tp = netdev_priv(dev);
1351 struct timer_list *timer = &tp->timer;
1352
e179bb7b 1353 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1354 return;
1355
1356 del_timer_sync(timer);
1357}
1358
1359static inline void rtl8169_request_timer(struct net_device *dev)
1360{
1361 struct rtl8169_private *tp = netdev_priv(dev);
1362 struct timer_list *timer = &tp->timer;
1363
e179bb7b 1364 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1365 return;
1366
2efa53f3 1367 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1368}
1369
1370#ifdef CONFIG_NET_POLL_CONTROLLER
1371/*
1372 * Polling 'interrupt' - used by things like netconsole to send skbs
1373 * without having to re-enable interrupts. It's not called while
1374 * the interrupt routine is executing.
1375 */
1376static void rtl8169_netpoll(struct net_device *dev)
1377{
1378 struct rtl8169_private *tp = netdev_priv(dev);
1379 struct pci_dev *pdev = tp->pci_dev;
1380
1381 disable_irq(pdev->irq);
7d12e780 1382 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1383 enable_irq(pdev->irq);
1384}
1385#endif
1386
1387static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1388 void __iomem *ioaddr)
1389{
1390 iounmap(ioaddr);
1391 pci_release_regions(pdev);
1392 pci_disable_device(pdev);
1393 free_netdev(dev);
1394}
1395
bf793295
FR		 1396static void rtl8169_phy_reset(struct net_device *dev,
1397 struct rtl8169_private *tp)
1398{
1399 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1400 unsigned int i;
bf793295
FR		 1401
1402 tp->phy_reset_enable(ioaddr);
1403 for (i = 0; i < 100; i++) {
1404 if (!tp->phy_reset_pending(ioaddr))
1405 return;
1406 msleep(1);
1407 }
1408 if (netif_msg_link(tp))
1409 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1410}
1411
4ff96fa6
FR		 1412static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1413{
1414 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1415
5615d9f1 1416 rtl_hw_phy_config(dev);
4ff96fa6
FR		 1417
1418 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1419 RTL_W8(0x82, 0x01);
1420
6dccd16b
FR		 1421 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1422
1423 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1424 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1425
bcf0bf90 1426 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1427 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1428 RTL_W8(0x82, 0x01);
1429 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1430 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1431 }
1432
bf793295
FR		 1433 rtl8169_phy_reset(dev, tp);
1434
901dda2b
FR		 1435 /*
1436 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1437 * only 8101. Don't panic.
1438 */
1439 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1440
1441 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1442 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1443}
1444
773d2021
FR		 1445static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1446{
1447 void __iomem *ioaddr = tp->mmio_addr;
1448 u32 high;
1449 u32 low;
1450
1451 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1452 high = addr[4] | (addr[5] << 8);
1453
1454 spin_lock_irq(&tp->lock);
1455
1456 RTL_W8(Cfg9346, Cfg9346_Unlock);
1457 RTL_W32(MAC0, low);
1458 RTL_W32(MAC4, high);
1459 RTL_W8(Cfg9346, Cfg9346_Lock);
1460
1461 spin_unlock_irq(&tp->lock);
1462}
1463
1464static int rtl_set_mac_address(struct net_device *dev, void *p)
1465{
1466 struct rtl8169_private *tp = netdev_priv(dev);
1467 struct sockaddr *addr = p;
1468
1469 if (!is_valid_ether_addr(addr->sa_data))
1470 return -EADDRNOTAVAIL;
1471
1472 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1473
1474 rtl_rar_set(tp, dev->dev_addr);
1475
1476 return 0;
1477}
1478
5f787a1a
FR		 1479static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1480{
1481 struct rtl8169_private *tp = netdev_priv(dev);
1482 struct mii_ioctl_data *data = if_mii(ifr);
1483
1484 if (!netif_running(dev))
1485 return -ENODEV;
1486
1487 switch (cmd) {
1488 case SIOCGMIIPHY:
1489 data->phy_id = 32; /* Internal PHY */
1490 return 0;
1491
1492 case SIOCGMIIREG:
1493 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1494 return 0;
1495
1496 case SIOCSMIIREG:
1497 if (!capable(CAP_NET_ADMIN))
1498 return -EPERM;
1499 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1500 return 0;
1501 }
1502 return -EOPNOTSUPP;
1503}
1504
0e485150
FR		 1505static const struct rtl_cfg_info {
1506 void (*hw_start)(struct net_device *);
1507 unsigned int region;
1508 unsigned int align;
1509 u16 intr_event;
1510 u16 napi_event;
fbac58fc 1511 unsigned msi;
0e485150
FR		 1512} rtl_cfg_infos [] = {
1513 [RTL_CFG_0] = {
1514 .hw_start = rtl_hw_start_8169,
1515 .region = 1,
e9f63f30 1516 .align = 0,
0e485150
FR		 1517 .intr_event = SYSErr | LinkChg | RxOverflow |
1518 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1519 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1520 .msi = 0
0e485150
FR		 1521 },
1522 [RTL_CFG_1] = {
1523 .hw_start = rtl_hw_start_8168,
1524 .region = 2,
1525 .align = 8,
1526 .intr_event = SYSErr | LinkChg | RxOverflow |
1527 TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1528 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1529 .msi = RTL_FEATURE_MSI
0e485150
FR		 1530 },
1531 [RTL_CFG_2] = {
1532 .hw_start = rtl_hw_start_8101,
1533 .region = 2,
1534 .align = 8,
1535 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1536 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1537 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1538 .msi = RTL_FEATURE_MSI
0e485150
FR		 1539 }
1540};
1541
fbac58fc
FR		 1542/* Cfg9346_Unlock assumed. */
1543static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1544 const struct rtl_cfg_info *cfg)
1545{
1546 unsigned msi = 0;
1547 u8 cfg2;
1548
1549 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1550 if (cfg->msi) {
1551 if (pci_enable_msi(pdev)) {
1552 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1553 } else {
1554 cfg2 |= MSIEnable;
1555 msi = RTL_FEATURE_MSI;
1556 }
1557 }
1558 RTL_W8(Config2, cfg2);
1559 return msi;
1560}
1561
1562static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1563{
1564 if (tp->features & RTL_FEATURE_MSI) {
1565 pci_disable_msi(pdev);
1566 tp->features &= ~RTL_FEATURE_MSI;
1567 }
1568}
1569
1da177e4 1570static int __devinit
4ff96fa6 1571rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1572{
0e485150
FR		 1573 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1574 const unsigned int region = cfg->region;
1da177e4 1575 struct rtl8169_private *tp;
4ff96fa6
FR		 1576 struct net_device *dev;
1577 void __iomem *ioaddr;
07d3f51f
FR		 1578 unsigned int i;
1579 int rc;
1da177e4 1580
4ff96fa6
FR		 1581 if (netif_msg_drv(&debug)) {
1582 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1583 MODULENAME, RTL8169_VERSION);
1584 }
1da177e4 1585
1da177e4 1586 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1587 if (!dev) {
b57b7e5a 1588 if (netif_msg_drv(&debug))
9b91cf9d 1589 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1590 rc = -ENOMEM;
1591 goto out;
1da177e4
LT		 1592 }
1593
1da177e4
LT		 1594 SET_NETDEV_DEV(dev, &pdev->dev);
1595 tp = netdev_priv(dev);
c4028958 1596 tp->dev = dev;
b57b7e5a 1597 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1598
1599 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1600 rc = pci_enable_device(pdev);
b57b7e5a 1601 if (rc < 0) {
2e8a538d 1602 if (netif_msg_probe(tp))
9b91cf9d 1603 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1604 goto err_out_free_dev_1;
1da177e4
LT		 1605 }
1606
1607 rc = pci_set_mwi(pdev);
1608 if (rc < 0)
4ff96fa6 1609 goto err_out_disable_2;
1da177e4 1610
1da177e4 1611 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1612 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1613 if (netif_msg_probe(tp)) {
9b91cf9d 1614 dev_err(&pdev->dev,
bcf0bf90
FR		 1615 "region #%d not an MMIO resource, aborting\n",
1616 region);
4ff96fa6 1617 }
1da177e4 1618 rc = -ENODEV;
4ff96fa6 1619 goto err_out_mwi_3;
1da177e4 1620 }
4ff96fa6 1621
1da177e4 1622 /* check for weird/broken PCI region reporting */
bcf0bf90 1623 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1624 if (netif_msg_probe(tp)) {
9b91cf9d 1625 dev_err(&pdev->dev,
4ff96fa6
FR		 1626 "Invalid PCI region size(s), aborting\n");
1627 }
1da177e4 1628 rc = -ENODEV;
4ff96fa6 1629 goto err_out_mwi_3;
1da177e4
LT		 1630 }
1631
1632 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1633 if (rc < 0) {
2e8a538d 1634 if (netif_msg_probe(tp))
9b91cf9d 1635 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1636 goto err_out_mwi_3;
1da177e4
LT		 1637 }
1638
1639 tp->cp_cmd = PCIMulRW | RxChkSum;
1640
1641 if ((sizeof(dma_addr_t) > 4) &&
1642 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1643 tp->cp_cmd |= PCIDAC;
1644 dev->features |= NETIF_F_HIGHDMA;
1645 } else {
1646 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1647 if (rc < 0) {
4ff96fa6 1648 if (netif_msg_probe(tp)) {
9b91cf9d 1649 dev_err(&pdev->dev,
4ff96fa6
FR		 1650 "DMA configuration failed.\n");
1651 }
1652 goto err_out_free_res_4;
1da177e4
LT		 1653 }
1654 }
1655
1656 pci_set_master(pdev);
1657
1658 /* ioremap MMIO region */
bcf0bf90 1659 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1660 if (!ioaddr) {
b57b7e5a 1661 if (netif_msg_probe(tp))
9b91cf9d 1662 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1663 rc = -EIO;
4ff96fa6 1664 goto err_out_free_res_4;
1da177e4
LT		 1665 }
1666
1667 /* Unneeded ? Don't mess with Mrs. Murphy. */
1668 rtl8169_irq_mask_and_ack(ioaddr);
1669
1670 /* Soft reset the chip. */
1671 RTL_W8(ChipCmd, CmdReset);
1672
1673 /* Check that the chip has finished the reset. */
07d3f51f 1674 for (i = 0; i < 100; i++) {
1da177e4
LT		 1675 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1676 break;
b518fa8e 1677 msleep_interruptible(1);
1da177e4
LT		 1678 }
1679
1680 /* Identify chip attached to board */
1681 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1682
1683 rtl8169_print_mac_version(tp);
1da177e4
LT		 1684
1685 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1686 if (tp->mac_version == rtl_chip_info[i].mac_version)
1687 break;
1688 }
1689 if (i < 0) {
1690 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1691 if (netif_msg_probe(tp)) {
2e8a538d 1692 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1693 "unknown chip version, assuming %s\n",
1694 rtl_chip_info[0].name);
b57b7e5a 1695 }
1da177e4
LT		 1696 i++;
1697 }
1698 tp->chipset = i;
1699
5d06a99f
FR		 1700 RTL_W8(Cfg9346, Cfg9346_Unlock);
1701 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1702 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1703 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1704 RTL_W8(Cfg9346, Cfg9346_Lock);
1705
1da177e4
LT		 1706 if (RTL_R8(PHYstatus) & TBI_Enable) {
1707 tp->set_speed = rtl8169_set_speed_tbi;
1708 tp->get_settings = rtl8169_gset_tbi;
1709 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1710 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1711 tp->link_ok = rtl8169_tbi_link_ok;
1712
64e4bfb4 1713 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1714 } else {
1715 tp->set_speed = rtl8169_set_speed_xmii;
1716 tp->get_settings = rtl8169_gset_xmii;
1717 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1718 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1719 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1720
1721 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1722 }
1723
1724 /* Get MAC address. FIXME: read EEPROM */
1725 for (i = 0; i < MAC_ADDR_LEN; i++)
1726 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1727 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1728
1729 dev->open = rtl8169_open;
1730 dev->hard_start_xmit = rtl8169_start_xmit;
1731 dev->get_stats = rtl8169_get_stats;
1732 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1733 dev->stop = rtl8169_close;
1734 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1735 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1736 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1737 dev->irq = pdev->irq;
1738 dev->base_addr = (unsigned long) ioaddr;
1739 dev->change_mtu = rtl8169_change_mtu;
773d2021 1740 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1741
1742#ifdef CONFIG_R8169_NAPI
bea3348e 1743 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1744#endif
1745
1746#ifdef CONFIG_R8169_VLAN
1747 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1748 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1749#endif
1750
1751#ifdef CONFIG_NET_POLL_CONTROLLER
1752 dev->poll_controller = rtl8169_netpoll;
1753#endif
1754
1755 tp->intr_mask = 0xffff;
1756 tp->pci_dev = pdev;
1757 tp->mmio_addr = ioaddr;
0e485150
FR		 1758 tp->align = cfg->align;
1759 tp->hw_start = cfg->hw_start;
1760 tp->intr_event = cfg->intr_event;
1761 tp->napi_event = cfg->napi_event;
1da177e4 1762
2efa53f3
FR		 1763 init_timer(&tp->timer);
1764 tp->timer.data = (unsigned long) dev;
1765 tp->timer.function = rtl8169_phy_timer;
1766
1da177e4
LT		 1767 spin_lock_init(&tp->lock);
1768
1769 rc = register_netdev(dev);
4ff96fa6 1770 if (rc < 0)
fbac58fc 1771 goto err_out_msi_5;
1da177e4
LT		 1772
1773 pci_set_drvdata(pdev, dev);
1774
b57b7e5a 1775 if (netif_msg_probe(tp)) {
96b9709c
FR		 1776 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1777
b57b7e5a
SH		 1778 printk(KERN_INFO "%s: %s at 0x%lx, "
1779 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1780 "XID %08x IRQ %d\n",
b57b7e5a 1781 dev->name,
bcf0bf90 1782 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1783 dev->base_addr,
1784 dev->dev_addr[0], dev->dev_addr[1],
1785 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1786 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1787 }
1da177e4 1788
4ff96fa6 1789 rtl8169_init_phy(dev, tp);
1da177e4 1790
4ff96fa6
FR		 1791out:
1792 return rc;
1da177e4 1793
fbac58fc
FR		 1794err_out_msi_5:
1795 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1796 iounmap(ioaddr);
1797err_out_free_res_4:
1798 pci_release_regions(pdev);
1799err_out_mwi_3:
1800 pci_clear_mwi(pdev);
1801err_out_disable_2:
1802 pci_disable_device(pdev);
1803err_out_free_dev_1:
1804 free_netdev(dev);
1805 goto out;
1da177e4
LT		 1806}
1807
07d3f51f 1808static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1809{
1810 struct net_device *dev = pci_get_drvdata(pdev);
1811 struct rtl8169_private *tp = netdev_priv(dev);
1812
eb2a021c
FR		 1813 flush_scheduled_work();
1814
1da177e4 1815 unregister_netdev(dev);
fbac58fc 1816 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1817 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1818 pci_set_drvdata(pdev, NULL);
1819}
1820
1da177e4
LT		 1821static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1822 struct net_device *dev)
1823{
1824 unsigned int mtu = dev->mtu;
1825
1826 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1827}
1828
1829static int rtl8169_open(struct net_device *dev)
1830{
1831 struct rtl8169_private *tp = netdev_priv(dev);
1832 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1833 int retval = -ENOMEM;
1da177e4 1834
1da177e4 1835
99f252b0 1836 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1837
1838 /*
1839 * Rx and Tx desscriptors needs 256 bytes alignment.
1840 * pci_alloc_consistent provides more.
1841 */
1842 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1843 &tp->TxPhyAddr);
1844 if (!tp->TxDescArray)
99f252b0 1845 goto out;
1da177e4
LT		 1846
1847 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1848 &tp->RxPhyAddr);
1849 if (!tp->RxDescArray)
99f252b0 1850 goto err_free_tx_0;
1da177e4
LT		 1851
1852 retval = rtl8169_init_ring(dev);
1853 if (retval < 0)
99f252b0 1854 goto err_free_rx_1;
1da177e4 1855
c4028958 1856 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1857
99f252b0
FR		 1858 smp_mb();
1859
fbac58fc
FR		 1860 retval = request_irq(dev->irq, rtl8169_interrupt,
1861 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1862 dev->name, dev);
1863 if (retval < 0)
1864 goto err_release_ring_2;
1865
bea3348e
SH		 1866#ifdef CONFIG_R8169_NAPI
1867 napi_enable(&tp->napi);
1868#endif
1869
07ce4064 1870 rtl_hw_start(dev);
1da177e4
LT		 1871
1872 rtl8169_request_timer(dev);
1873
1874 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1875out:
1876 return retval;
1877
99f252b0
FR		 1878err_release_ring_2:
1879 rtl8169_rx_clear(tp);
1880err_free_rx_1:
1da177e4
LT		 1881 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1882 tp->RxPhyAddr);
99f252b0 1883err_free_tx_0:
1da177e4
LT		 1884 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1885 tp->TxPhyAddr);
1da177e4
LT		 1886 goto out;
1887}
1888
1889static void rtl8169_hw_reset(void __iomem *ioaddr)
1890{
1891 /* Disable interrupts */
1892 rtl8169_irq_mask_and_ack(ioaddr);
1893
1894 /* Reset the chipset */
1895 RTL_W8(ChipCmd, CmdReset);
1896
1897 /* PCI commit */
1898 RTL_R8(ChipCmd);
1899}
1900
7f796d83 1901static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1902{
1903 void __iomem *ioaddr = tp->mmio_addr;
1904 u32 cfg = rtl8169_rx_config;
1905
1906 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1907 RTL_W32(RxConfig, cfg);
1908
1909 /* Set DMA burst size and Interframe Gap Time */
1910 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1911 (InterFrameGap << TxInterFrameGapShift));
1912}
1913
07ce4064 1914static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1915{
1916 struct rtl8169_private *tp = netdev_priv(dev);
1917 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1918 unsigned int i;
1da177e4
LT		 1919
1920 /* Soft reset the chip. */
1921 RTL_W8(ChipCmd, CmdReset);
1922
1923 /* Check that the chip has finished the reset. */
07d3f51f 1924 for (i = 0; i < 100; i++) {
1da177e4
LT		 1925 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1926 break;
b518fa8e 1927 msleep_interruptible(1);
1da177e4
LT		 1928 }
1929
07ce4064
FR		 1930 tp->hw_start(dev);
1931
07ce4064
FR		 1932 netif_start_queue(dev);
1933}
1934
1935
7f796d83
FR		 1936static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1937 void __iomem *ioaddr)
1938{
1939 /*
1940 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1941 * register to be written before TxDescAddrLow to work.
1942 * Switching from MMIO to I/O access fixes the issue as well.
1943 */
1944 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1945 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1946 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1947 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1948}
1949
1950static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1951{
1952 u16 cmd;
1953
1954 cmd = RTL_R16(CPlusCmd);
1955 RTL_W16(CPlusCmd, cmd);
1956 return cmd;
1957}
1958
1959static void rtl_set_rx_max_size(void __iomem *ioaddr)
1960{
1961 /* Low hurts. Let's disable the filtering. */
1962 RTL_W16(RxMaxSize, 16383);
1963}
1964
6dccd16b
FR		 1965static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1966{
1967 struct {
1968 u32 mac_version;
1969 u32 clk;
1970 u32 val;
1971 } cfg2_info [] = {
1972 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1973 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1974 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1975 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1976 }, *p = cfg2_info;
1977 unsigned int i;
1978 u32 clk;
1979
1980 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1981 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1982 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1983 RTL_W32(0x7c, p->val);
1984 break;
1985 }
1986 }
1987}
1988
07ce4064
FR		 1989static void rtl_hw_start_8169(struct net_device *dev)
1990{
1991 struct rtl8169_private *tp = netdev_priv(dev);
1992 void __iomem *ioaddr = tp->mmio_addr;
1993 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1994
9cb427b6
FR		 1995 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1996 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1997 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1998 }
1999
1da177e4 2000 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2001 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2002 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2003 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2004 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2005 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2006
1da177e4
LT		 2007 RTL_W8(EarlyTxThres, EarlyTxThld);
2008
7f796d83 2009 rtl_set_rx_max_size(ioaddr);
1da177e4 2010
c946b304
FR		 2011 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2012 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2013 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2014 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2015 rtl_set_rx_tx_config_registers(tp);
1da177e4 2016
7f796d83 2017 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2018
bcf0bf90
FR		 2019 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2020 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2021 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2022 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2023 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2024 }
2025
bcf0bf90
FR		 2026 RTL_W16(CPlusCmd, tp->cp_cmd);
2027
6dccd16b
FR		 2028 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2029
1da177e4
LT		 2030 /*
2031 * Undocumented corner. Supposedly:
2032 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2033 */
2034 RTL_W16(IntrMitigate, 0x0000);
2035
7f796d83 2036 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2037
c946b304
FR		 2038 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2039 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2040 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2041 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2042 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2043 rtl_set_rx_tx_config_registers(tp);
2044 }
2045
1da177e4 2046 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2047
2048 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2049 RTL_R8(IntrMask);
1da177e4
LT		 2050
2051 RTL_W32(RxMissed, 0);
2052
07ce4064 2053 rtl_set_rx_mode(dev);
1da177e4
LT		 2054
2055 /* no early-rx interrupts */
2056 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2057
2058 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2059 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2060}
1da177e4 2061
07ce4064
FR		 2062static void rtl_hw_start_8168(struct net_device *dev)
2063{
2dd99530
FR		 2064 struct rtl8169_private *tp = netdev_priv(dev);
2065 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2066 struct pci_dev *pdev = tp->pci_dev;
2067 u8 ctl;
2dd99530
FR		 2068
2069 RTL_W8(Cfg9346, Cfg9346_Unlock);
2070
2071 RTL_W8(EarlyTxThres, EarlyTxThld);
2072
2073 rtl_set_rx_max_size(ioaddr);
2074
0e485150
FR		 2075 rtl_set_rx_tx_config_registers(tp);
2076
2077 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2078
2079 RTL_W16(CPlusCmd, tp->cp_cmd);
2080
0e485150
FR		 2081 /* Tx performance tweak. */
2082 pci_read_config_byte(pdev, 0x69, &ctl);
2083 ctl = (ctl & ~0x70) | 0x50;
2084 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2085
0e485150 2086 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2087
0e485150
FR		 2088 /* Work around for RxFIFO overflow. */
2089 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2090 tp->intr_event |= RxFIFOOver | PCSTimeout;
2091 tp->intr_event &= ~RxOverflow;
2092 }
2093
2094 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2095
2096 RTL_W8(Cfg9346, Cfg9346_Lock);
2097
2098 RTL_R8(IntrMask);
2099
2100 RTL_W32(RxMissed, 0);
2101
2102 rtl_set_rx_mode(dev);
2103
0e485150
FR		 2104 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2105
2dd99530 2106 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2107
0e485150 2108 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2109}
1da177e4 2110
07ce4064
FR		 2111static void rtl_hw_start_8101(struct net_device *dev)
2112{
cdf1a608
FR		 2113 struct rtl8169_private *tp = netdev_priv(dev);
2114 void __iomem *ioaddr = tp->mmio_addr;
2115 struct pci_dev *pdev = tp->pci_dev;
2116
e3cf0cc0
FR		 2117 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2118 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
cdf1a608
FR		 2119 pci_write_config_word(pdev, 0x68, 0x00);
2120 pci_write_config_word(pdev, 0x69, 0x08);
2121 }
2122
2123 RTL_W8(Cfg9346, Cfg9346_Unlock);
2124
2125 RTL_W8(EarlyTxThres, EarlyTxThld);
2126
2127 rtl_set_rx_max_size(ioaddr);
2128
2129 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2130
2131 RTL_W16(CPlusCmd, tp->cp_cmd);
2132
2133 RTL_W16(IntrMitigate, 0x0000);
2134
2135 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2136
2137 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2138 rtl_set_rx_tx_config_registers(tp);
2139
2140 RTL_W8(Cfg9346, Cfg9346_Lock);
2141
2142 RTL_R8(IntrMask);
2143
2144 RTL_W32(RxMissed, 0);
2145
2146 rtl_set_rx_mode(dev);
2147
0e485150
FR		 2148 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2149
cdf1a608 2150 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2151
0e485150 2152 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2153}
2154
2155static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2156{
2157 struct rtl8169_private *tp = netdev_priv(dev);
2158 int ret = 0;
2159
2160 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2161 return -EINVAL;
2162
2163 dev->mtu = new_mtu;
2164
2165 if (!netif_running(dev))
2166 goto out;
2167
2168 rtl8169_down(dev);
2169
2170 rtl8169_set_rxbufsize(tp, dev);
2171
2172 ret = rtl8169_init_ring(dev);
2173 if (ret < 0)
2174 goto out;
2175
bea3348e
SH		 2176#ifdef CONFIG_R8169_NAPI
2177 napi_enable(&tp->napi);
2178#endif
1da177e4 2179
07ce4064 2180 rtl_hw_start(dev);
1da177e4
LT		 2181
2182 rtl8169_request_timer(dev);
2183
2184out:
2185 return ret;
2186}
2187
2188static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2189{
2190 desc->addr = 0x0badbadbadbadbadull;
2191 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2192}
2193
2194static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2195 struct sk_buff **sk_buff, struct RxDesc *desc)
2196{
2197 struct pci_dev *pdev = tp->pci_dev;
2198
2199 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2200 PCI_DMA_FROMDEVICE);
2201 dev_kfree_skb(*sk_buff);
2202 *sk_buff = NULL;
2203 rtl8169_make_unusable_by_asic(desc);
2204}
2205
2206static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2207{
2208 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2209
2210 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2211}
2212
2213static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2214 u32 rx_buf_sz)
2215{
2216 desc->addr = cpu_to_le64(mapping);
2217 wmb();
2218 rtl8169_mark_to_asic(desc, rx_buf_sz);
2219}
2220
15d31758
SH		 2221static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2222 struct net_device *dev,
2223 struct RxDesc *desc, int rx_buf_sz,
2224 unsigned int align)
1da177e4
LT		 2225{
2226 struct sk_buff *skb;
2227 dma_addr_t mapping;
e9f63f30 2228 unsigned int pad;
1da177e4 2229
e9f63f30
FR		 2230 pad = align ? align : NET_IP_ALIGN;
2231
2232 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2233 if (!skb)
2234 goto err_out;
2235
e9f63f30 2236 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2237
689be439 2238 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2239 PCI_DMA_FROMDEVICE);
2240
2241 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2242out:
15d31758 2243 return skb;
1da177e4
LT		 2244
2245err_out:
1da177e4
LT		 2246 rtl8169_make_unusable_by_asic(desc);
2247 goto out;
2248}
2249
2250static void rtl8169_rx_clear(struct rtl8169_private *tp)
2251{
07d3f51f 2252 unsigned int i;
1da177e4
LT		 2253
2254 for (i = 0; i < NUM_RX_DESC; i++) {
2255 if (tp->Rx_skbuff[i]) {
2256 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2257 tp->RxDescArray + i);
2258 }
2259 }
2260}
2261
2262static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2263 u32 start, u32 end)
2264{
2265 u32 cur;
5b0384f4 2266
4ae47c2d 2267 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2268 struct sk_buff *skb;
2269 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2270
4ae47c2d
FR		 2271 WARN_ON((s32)(end - cur) < 0);
2272
1da177e4
LT		 2273 if (tp->Rx_skbuff[i])
2274 continue;
bcf0bf90 2275
15d31758
SH		 2276 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2277 tp->RxDescArray + i,
2278 tp->rx_buf_sz, tp->align);
2279 if (!skb)
1da177e4 2280 break;
15d31758
SH		 2281
2282 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2283 }
2284 return cur - start;
2285}
2286
2287static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2288{
2289 desc->opts1 |= cpu_to_le32(RingEnd);
2290}
2291
2292static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2293{
2294 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2295}
2296
2297static int rtl8169_init_ring(struct net_device *dev)
2298{
2299 struct rtl8169_private *tp = netdev_priv(dev);
2300
2301 rtl8169_init_ring_indexes(tp);
2302
2303 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2304 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2305
2306 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2307 goto err_out;
2308
2309 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2310
2311 return 0;
2312
2313err_out:
2314 rtl8169_rx_clear(tp);
2315 return -ENOMEM;
2316}
2317
2318static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2319 struct TxDesc *desc)
2320{
2321 unsigned int len = tx_skb->len;
2322
2323 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2324 desc->opts1 = 0x00;
2325 desc->opts2 = 0x00;
2326 desc->addr = 0x00;
2327 tx_skb->len = 0;
2328}
2329
2330static void rtl8169_tx_clear(struct rtl8169_private *tp)
2331{
2332 unsigned int i;
2333
2334 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2335 unsigned int entry = i % NUM_TX_DESC;
2336 struct ring_info *tx_skb = tp->tx_skb + entry;
2337 unsigned int len = tx_skb->len;
2338
2339 if (len) {
2340 struct sk_buff *skb = tx_skb->skb;
2341
2342 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2343 tp->TxDescArray + entry);
2344 if (skb) {
2345 dev_kfree_skb(skb);
2346 tx_skb->skb = NULL;
2347 }
cebf8cc7 2348 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2349 }
2350 }
2351 tp->cur_tx = tp->dirty_tx = 0;
2352}
2353
c4028958 2354static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2355{
2356 struct rtl8169_private *tp = netdev_priv(dev);
2357
c4028958 2358 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2359 schedule_delayed_work(&tp->task, 4);
2360}
2361
2362static void rtl8169_wait_for_quiescence(struct net_device *dev)
2363{
2364 struct rtl8169_private *tp = netdev_priv(dev);
2365 void __iomem *ioaddr = tp->mmio_addr;
2366
2367 synchronize_irq(dev->irq);
2368
2369 /* Wait for any pending NAPI task to complete */
bea3348e
SH		 2370#ifdef CONFIG_R8169_NAPI
2371 napi_disable(&tp->napi);
2372#endif
1da177e4
LT		 2373
2374 rtl8169_irq_mask_and_ack(ioaddr);
2375
bea3348e
SH		 2376#ifdef CONFIG_R8169_NAPI
2377 napi_enable(&tp->napi);
2378#endif
1da177e4
LT		 2379}
2380
c4028958 2381static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2382{
c4028958
DH		 2383 struct rtl8169_private *tp =
2384 container_of(work, struct rtl8169_private, task.work);
2385 struct net_device *dev = tp->dev;
1da177e4
LT		 2386 int ret;
2387
eb2a021c
FR		 2388 rtnl_lock();
2389
2390 if (!netif_running(dev))
2391 goto out_unlock;
2392
2393 rtl8169_wait_for_quiescence(dev);
2394 rtl8169_close(dev);
1da177e4
LT		 2395
2396 ret = rtl8169_open(dev);
2397 if (unlikely(ret < 0)) {
07d3f51f 2398 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2399 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2400 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2401 }
2402 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2403 }
eb2a021c
FR		 2404
2405out_unlock:
2406 rtnl_unlock();
1da177e4
LT		 2407}
2408
c4028958 2409static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2410{
c4028958
DH		 2411 struct rtl8169_private *tp =
2412 container_of(work, struct rtl8169_private, task.work);
2413 struct net_device *dev = tp->dev;
1da177e4 2414
eb2a021c
FR		 2415 rtnl_lock();
2416
1da177e4 2417 if (!netif_running(dev))
eb2a021c 2418 goto out_unlock;
1da177e4
LT		 2419
2420 rtl8169_wait_for_quiescence(dev);
2421
bea3348e 2422 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2423 rtl8169_tx_clear(tp);
2424
2425 if (tp->dirty_rx == tp->cur_rx) {
2426 rtl8169_init_ring_indexes(tp);
07ce4064 2427 rtl_hw_start(dev);
1da177e4 2428 netif_wake_queue(dev);
cebf8cc7 2429 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2430 } else {
07d3f51f 2431 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2432 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2433 dev->name);
1da177e4
LT		 2434 }
2435 rtl8169_schedule_work(dev, rtl8169_reset_task);
2436 }
eb2a021c
FR		 2437
2438out_unlock:
2439 rtnl_unlock();
1da177e4
LT		 2440}
2441
2442static void rtl8169_tx_timeout(struct net_device *dev)
2443{
2444 struct rtl8169_private *tp = netdev_priv(dev);
2445
2446 rtl8169_hw_reset(tp->mmio_addr);
2447
2448 /* Let's wait a bit while any (async) irq lands on */
2449 rtl8169_schedule_work(dev, rtl8169_reset_task);
2450}
2451
2452static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2453 u32 opts1)
2454{
2455 struct skb_shared_info *info = skb_shinfo(skb);
2456 unsigned int cur_frag, entry;
a6343afb 2457 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2458
2459 entry = tp->cur_tx;
2460 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2461 skb_frag_t *frag = info->frags + cur_frag;
2462 dma_addr_t mapping;
2463 u32 status, len;
2464 void *addr;
2465
2466 entry = (entry + 1) % NUM_TX_DESC;
2467
2468 txd = tp->TxDescArray + entry;
2469 len = frag->size;
2470 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2471 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2472
2473 /* anti gcc 2.95.3 bugware (sic) */
2474 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2475
2476 txd->opts1 = cpu_to_le32(status);
2477 txd->addr = cpu_to_le64(mapping);
2478
2479 tp->tx_skb[entry].len = len;
2480 }
2481
2482 if (cur_frag) {
2483 tp->tx_skb[entry].skb = skb;
2484 txd->opts1 |= cpu_to_le32(LastFrag);
2485 }
2486
2487 return cur_frag;
2488}
2489
2490static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2491{
2492 if (dev->features & NETIF_F_TSO) {
7967168c 2493 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2494
2495 if (mss)
2496 return LargeSend | ((mss & MSSMask) << MSSShift);
2497 }
84fa7933 2498 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2499 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2500
2501 if (ip->protocol == IPPROTO_TCP)
2502 return IPCS | TCPCS;
2503 else if (ip->protocol == IPPROTO_UDP)
2504 return IPCS | UDPCS;
2505 WARN_ON(1); /* we need a WARN() */
2506 }
2507 return 0;
2508}
2509
2510static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2511{
2512 struct rtl8169_private *tp = netdev_priv(dev);
2513 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2514 struct TxDesc *txd = tp->TxDescArray + entry;
2515 void __iomem *ioaddr = tp->mmio_addr;
2516 dma_addr_t mapping;
2517 u32 status, len;
2518 u32 opts1;
188f4af0 2519 int ret = NETDEV_TX_OK;
5b0384f4 2520
1da177e4 2521 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2522 if (netif_msg_drv(tp)) {
2523 printk(KERN_ERR
2524 "%s: BUG! Tx Ring full when queue awake!\n",
2525 dev->name);
2526 }
1da177e4
LT		 2527 goto err_stop;
2528 }
2529
2530 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2531 goto err_stop;
2532
2533 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2534
2535 frags = rtl8169_xmit_frags(tp, skb, opts1);
2536 if (frags) {
2537 len = skb_headlen(skb);
2538 opts1 |= FirstFrag;
2539 } else {
2540 len = skb->len;
2541
2542 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2543 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2544 goto err_update_stats;
2545 len = ETH_ZLEN;
2546 }
2547
2548 opts1 |= FirstFrag | LastFrag;
2549 tp->tx_skb[entry].skb = skb;
2550 }
2551
2552 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2553
2554 tp->tx_skb[entry].len = len;
2555 txd->addr = cpu_to_le64(mapping);
2556 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2557
2558 wmb();
2559
2560 /* anti gcc 2.95.3 bugware (sic) */
2561 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2562 txd->opts1 = cpu_to_le32(status);
2563
2564 dev->trans_start = jiffies;
2565
2566 tp->cur_tx += frags + 1;
2567
2568 smp_wmb();
2569
275391a4 2570 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2571
2572 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2573 netif_stop_queue(dev);
2574 smp_rmb();
2575 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2576 netif_wake_queue(dev);
2577 }
2578
2579out:
2580 return ret;
2581
2582err_stop:
2583 netif_stop_queue(dev);
188f4af0 2584 ret = NETDEV_TX_BUSY;
1da177e4 2585err_update_stats:
cebf8cc7 2586 dev->stats.tx_dropped++;
1da177e4
LT		 2587 goto out;
2588}
2589
2590static void rtl8169_pcierr_interrupt(struct net_device *dev)
2591{
2592 struct rtl8169_private *tp = netdev_priv(dev);
2593 struct pci_dev *pdev = tp->pci_dev;
2594 void __iomem *ioaddr = tp->mmio_addr;
2595 u16 pci_status, pci_cmd;
2596
2597 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2598 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2599
b57b7e5a
SH		 2600 if (netif_msg_intr(tp)) {
2601 printk(KERN_ERR
2602 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2603 dev->name, pci_cmd, pci_status);
2604 }
1da177e4
LT		 2605
2606 /*
2607 * The recovery sequence below admits a very elaborated explanation:
2608 * - it seems to work;
d03902b8
FR		 2609 * - I did not see what else could be done;
2610 * - it makes iop3xx happy.
1da177e4
LT		 2611 *
2612 * Feel free to adjust to your needs.
2613 */
a27993f3 2614 if (pdev->broken_parity_status)
d03902b8
FR		 2615 pci_cmd &= ~PCI_COMMAND_PARITY;
2616 else
2617 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2618
2619 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2620
2621 pci_write_config_word(pdev, PCI_STATUS,
2622 pci_status & (PCI_STATUS_DETECTED_PARITY |
2623 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2624 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2625
2626 /* The infamous DAC f*ckup only happens at boot time */
2627 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2628 if (netif_msg_intr(tp))
2629 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2630 tp->cp_cmd &= ~PCIDAC;
2631 RTL_W16(CPlusCmd, tp->cp_cmd);
2632 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2633 }
2634
2635 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2636
2637 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2638}
2639
07d3f51f
FR		 2640static void rtl8169_tx_interrupt(struct net_device *dev,
2641 struct rtl8169_private *tp,
2642 void __iomem *ioaddr)
1da177e4
LT		 2643{
2644 unsigned int dirty_tx, tx_left;
2645
1da177e4
LT		 2646 dirty_tx = tp->dirty_tx;
2647 smp_rmb();
2648 tx_left = tp->cur_tx - dirty_tx;
2649
2650 while (tx_left > 0) {
2651 unsigned int entry = dirty_tx % NUM_TX_DESC;
2652 struct ring_info *tx_skb = tp->tx_skb + entry;
2653 u32 len = tx_skb->len;
2654 u32 status;
2655
2656 rmb();
2657 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2658 if (status & DescOwn)
2659 break;
2660
cebf8cc7
FR		 2661 dev->stats.tx_bytes += len;
2662 dev->stats.tx_packets++;
1da177e4
LT		 2663
2664 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2665
2666 if (status & LastFrag) {
2667 dev_kfree_skb_irq(tx_skb->skb);
2668 tx_skb->skb = NULL;
2669 }
2670 dirty_tx++;
2671 tx_left--;
2672 }
2673
2674 if (tp->dirty_tx != dirty_tx) {
2675 tp->dirty_tx = dirty_tx;
2676 smp_wmb();
2677 if (netif_queue_stopped(dev) &&
2678 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2679 netif_wake_queue(dev);
2680 }
d78ae2dc
FR		 2681 /*
2682 * 8168 hack: TxPoll requests are lost when the Tx packets are
2683 * too close. Let's kick an extra TxPoll request when a burst
2684 * of start_xmit activity is detected (if it is not detected,
2685 * it is slow enough). -- FR
2686 */
2687 smp_rmb();
2688 if (tp->cur_tx != dirty_tx)
2689 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2690 }
2691}
2692
126fa4b9
FR		 2693static inline int rtl8169_fragmented_frame(u32 status)
2694{
2695 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2696}
2697
1da177e4
LT		 2698static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2699{
2700 u32 opts1 = le32_to_cpu(desc->opts1);
2701 u32 status = opts1 & RxProtoMask;
2702
2703 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2704 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2705 ((status == RxProtoIP) && !(opts1 & IPFail)))
2706 skb->ip_summed = CHECKSUM_UNNECESSARY;
2707 else
2708 skb->ip_summed = CHECKSUM_NONE;
2709}
2710
07d3f51f
FR		 2711static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2712 struct rtl8169_private *tp, int pkt_size,
2713 dma_addr_t addr)
1da177e4 2714{
b449655f
SH		 2715 struct sk_buff *skb;
2716 bool done = false;
1da177e4 2717
b449655f
SH		 2718 if (pkt_size >= rx_copybreak)
2719 goto out;
1da177e4 2720
07d3f51f 2721 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2722 if (!skb)
2723 goto out;
2724
07d3f51f
FR		 2725 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2726 PCI_DMA_FROMDEVICE);
86402234 2727 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2728 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2729 *sk_buff = skb;
2730 done = true;
2731out:
2732 return done;
1da177e4
LT		 2733}
2734
07d3f51f
FR		 2735static int rtl8169_rx_interrupt(struct net_device *dev,
2736 struct rtl8169_private *tp,
bea3348e 2737 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2738{
2739 unsigned int cur_rx, rx_left;
2740 unsigned int delta, count;
2741
1da177e4
LT		 2742 cur_rx = tp->cur_rx;
2743 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
bea3348e 2744 rx_left = rtl8169_rx_quota(rx_left, budget);
1da177e4 2745
4dcb7d33 2746 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2747 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2748 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2749 u32 status;
2750
2751 rmb();
126fa4b9 2752 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2753
2754 if (status & DescOwn)
2755 break;
4dcb7d33 2756 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2757 if (netif_msg_rx_err(tp)) {
2758 printk(KERN_INFO
2759 "%s: Rx ERROR. status = %08x\n",
2760 dev->name, status);
2761 }
cebf8cc7 2762 dev->stats.rx_errors++;
1da177e4 2763 if (status & (RxRWT | RxRUNT))
cebf8cc7 2764 dev->stats.rx_length_errors++;
1da177e4 2765 if (status & RxCRC)
cebf8cc7 2766 dev->stats.rx_crc_errors++;
9dccf611
FR		 2767 if (status & RxFOVF) {
2768 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2769 dev->stats.rx_fifo_errors++;
9dccf611 2770 }
126fa4b9 2771 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2772 } else {
1da177e4 2773 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2774 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2775 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2776 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2777
126fa4b9
FR		 2778 /*
2779 * The driver does not support incoming fragmented
2780 * frames. They are seen as a symptom of over-mtu
2781 * sized frames.
2782 */
2783 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2784 dev->stats.rx_dropped++;
2785 dev->stats.rx_length_errors++;
126fa4b9 2786 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2787 continue;
126fa4b9
FR		 2788 }
2789
1da177e4 2790 rtl8169_rx_csum(skb, desc);
bcf0bf90 2791
07d3f51f 2792 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2793 pci_dma_sync_single_for_device(pdev, addr,
2794 pkt_size, PCI_DMA_FROMDEVICE);
2795 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2796 } else {
2797 pci_unmap_single(pdev, addr, pkt_size,
2798 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2799 tp->Rx_skbuff[entry] = NULL;
2800 }
2801
1da177e4
LT		 2802 skb_put(skb, pkt_size);
2803 skb->protocol = eth_type_trans(skb, dev);
2804
2805 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2806 rtl8169_rx_skb(skb);
2807
2808 dev->last_rx = jiffies;
cebf8cc7
FR		 2809 dev->stats.rx_bytes += pkt_size;
2810 dev->stats.rx_packets++;
1da177e4 2811 }
6dccd16b
FR		 2812
2813 /* Work around for AMD plateform. */
2814 if ((desc->opts2 & 0xfffe000) &&
2815 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2816 desc->opts2 = 0;
2817 cur_rx++;
2818 }
1da177e4
LT		 2819 }
2820
2821 count = cur_rx - tp->cur_rx;
2822 tp->cur_rx = cur_rx;
2823
2824 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2825 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2826 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2827 tp->dirty_rx += delta;
2828
2829 /*
2830 * FIXME: until there is periodic timer to try and refill the ring,
2831 * a temporary shortage may definitely kill the Rx process.
2832 * - disable the asic to try and avoid an overflow and kick it again
2833 * after refill ?
2834 * - how do others driver handle this condition (Uh oh...).
2835 */
b57b7e5a 2836 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2837 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2838
2839 return count;
2840}
2841
07d3f51f 2842static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2843{
07d3f51f 2844 struct net_device *dev = dev_instance;
1da177e4
LT		 2845 struct rtl8169_private *tp = netdev_priv(dev);
2846 int boguscnt = max_interrupt_work;
2847 void __iomem *ioaddr = tp->mmio_addr;
2848 int status;
2849 int handled = 0;
2850
2851 do {
2852 status = RTL_R16(IntrStatus);
2853
2854 /* hotplug/major error/no more work/shared irq */
2855 if ((status == 0xFFFF) || !status)
2856 break;
2857
2858 handled = 1;
2859
2860 if (unlikely(!netif_running(dev))) {
2861 rtl8169_asic_down(ioaddr);
2862 goto out;
2863 }
2864
2865 status &= tp->intr_mask;
2866 RTL_W16(IntrStatus,
2867 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2868
0e485150
FR		 2869 if (!(status & tp->intr_event))
2870 break;
2871
2872 /* Work around for rx fifo overflow */
2873 if (unlikely(status & RxFIFOOver) &&
2874 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2875 netif_stop_queue(dev);
2876 rtl8169_tx_timeout(dev);
1da177e4 2877 break;
0e485150 2878 }
1da177e4
LT		 2879
2880 if (unlikely(status & SYSErr)) {
2881 rtl8169_pcierr_interrupt(dev);
2882 break;
2883 }
2884
2885 if (status & LinkChg)
2886 rtl8169_check_link_status(dev, tp, ioaddr);
2887
2888#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2889 if (status & tp->napi_event) {
2890 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2891 tp->intr_mask = ~tp->napi_event;
2892
bea3348e
SH		 2893 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2894 __netif_rx_schedule(dev, &tp->napi);
313b0305
FR		 2895 else if (netif_msg_intr(tp)) {
2896 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2897 dev->name, status);
2898 }
1da177e4
LT		 2899 }
2900 break;
2901#else
2902 /* Rx interrupt */
07d3f51f 2903 if (status & (RxOK | RxOverflow | RxFIFOOver))
bea3348e 2904 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
07d3f51f 2905
1da177e4
LT		 2906 /* Tx interrupt */
2907 if (status & (TxOK | TxErr))
2908 rtl8169_tx_interrupt(dev, tp, ioaddr);
2909#endif
2910
2911 boguscnt--;
2912 } while (boguscnt > 0);
2913
2914 if (boguscnt <= 0) {
7c8b2eb4 2915 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2916 printk(KERN_WARNING
2917 "%s: Too much work at interrupt!\n", dev->name);
2918 }
1da177e4
LT		 2919 /* Clear all interrupt sources. */
2920 RTL_W16(IntrStatus, 0xffff);
2921 }
2922out:
2923 return IRQ_RETVAL(handled);
2924}
2925
2926#ifdef CONFIG_R8169_NAPI
bea3348e 2927static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2928{
bea3348e
SH		 2929 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2930 struct net_device *dev = tp->dev;
1da177e4 2931 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2932 int work_done;
1da177e4 2933
bea3348e 2934 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2935 rtl8169_tx_interrupt(dev, tp, ioaddr);
2936
bea3348e
SH		 2937 if (work_done < budget) {
2938 netif_rx_complete(dev, napi);
1da177e4
LT		 2939 tp->intr_mask = 0xffff;
2940 /*
2941 * 20040426: the barrier is not strictly required but the
2942 * behavior of the irq handler could be less predictable
2943 * without it. Btw, the lack of flush for the posted pci
2944 * write is safe - FR
2945 */
2946 smp_wmb();
0e485150 2947 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2948 }
2949
bea3348e 2950 return work_done;
1da177e4
LT		 2951}
2952#endif
2953
2954static void rtl8169_down(struct net_device *dev)
2955{
2956 struct rtl8169_private *tp = netdev_priv(dev);
2957 void __iomem *ioaddr = tp->mmio_addr;
2958 unsigned int poll_locked = 0;
733b736c 2959 unsigned int intrmask;
1da177e4
LT		 2960
2961 rtl8169_delete_timer(dev);
2962
2963 netif_stop_queue(dev);
2964
1da177e4
LT		 2965core_down:
2966 spin_lock_irq(&tp->lock);
2967
2968 rtl8169_asic_down(ioaddr);
2969
2970 /* Update the error counts. */
cebf8cc7 2971 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 2972 RTL_W32(RxMissed, 0);
2973
2974 spin_unlock_irq(&tp->lock);
2975
2976 synchronize_irq(dev->irq);
2977
2978 if (!poll_locked) {
bea3348e 2979 napi_disable(&tp->napi);
1da177e4
LT		 2980 poll_locked++;
2981 }
2982
2983 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2984 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2985
2986 /*
2987 * And now for the 50k$ question: are IRQ disabled or not ?
2988 *
2989 * Two paths lead here:
2990 * 1) dev->close
2991 * -> netif_running() is available to sync the current code and the
2992 * IRQ handler. See rtl8169_interrupt for details.
2993 * 2) dev->change_mtu
2994 * -> rtl8169_poll can not be issued again and re-enable the
2995 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2996 *
2997 * No loop if hotpluged or major error (0xffff).
1da177e4 2998 */
733b736c
AP		 2999 intrmask = RTL_R16(IntrMask);
3000 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3001 goto core_down;
3002
3003 rtl8169_tx_clear(tp);
3004
3005 rtl8169_rx_clear(tp);
3006}
3007
3008static int rtl8169_close(struct net_device *dev)
3009{
3010 struct rtl8169_private *tp = netdev_priv(dev);
3011 struct pci_dev *pdev = tp->pci_dev;
3012
3013 rtl8169_down(dev);
3014
3015 free_irq(dev->irq, dev);
3016
1da177e4
LT		 3017 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3018 tp->RxPhyAddr);
3019 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3020 tp->TxPhyAddr);
3021 tp->TxDescArray = NULL;
3022 tp->RxDescArray = NULL;
3023
3024 return 0;
3025}
3026
07ce4064 3027static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3028{
3029 struct rtl8169_private *tp = netdev_priv(dev);
3030 void __iomem *ioaddr = tp->mmio_addr;
3031 unsigned long flags;
3032 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3033 int rx_mode;
1da177e4
LT		 3034 u32 tmp = 0;
3035
3036 if (dev->flags & IFF_PROMISC) {
3037 /* Unconditionally log net taps. */
b57b7e5a
SH		 3038 if (netif_msg_link(tp)) {
3039 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3040 dev->name);
3041 }
1da177e4
LT		 3042 rx_mode =
3043 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3044 AcceptAllPhys;
3045 mc_filter[1] = mc_filter[0] = 0xffffffff;
3046 } else if ((dev->mc_count > multicast_filter_limit)
3047 || (dev->flags & IFF_ALLMULTI)) {
3048 /* Too many to filter perfectly -- accept all multicasts. */
3049 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3050 mc_filter[1] = mc_filter[0] = 0xffffffff;
3051 } else {
3052 struct dev_mc_list *mclist;
07d3f51f
FR		 3053 unsigned int i;
3054
1da177e4
LT		 3055 rx_mode = AcceptBroadcast | AcceptMyPhys;
3056 mc_filter[1] = mc_filter[0] = 0;
3057 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3058 i++, mclist = mclist->next) {
3059 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3060 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3061 rx_mode |= AcceptMulticast;
3062 }
3063 }
3064
3065 spin_lock_irqsave(&tp->lock, flags);
3066
3067 tmp = rtl8169_rx_config | rx_mode |
3068 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3069
bcf0bf90
FR		 3070 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3071 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3072 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3073 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 3074 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3075 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3076 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
bcf0bf90
FR		 3077 mc_filter[0] = 0xffffffff;
3078 mc_filter[1] = 0xffffffff;
3079 }
3080
1da177e4
LT		 3081 RTL_W32(MAR0 + 0, mc_filter[0]);
3082 RTL_W32(MAR0 + 4, mc_filter[1]);
3083
57a9f236
FR		 3084 RTL_W32(RxConfig, tmp);
3085
1da177e4
LT		 3086 spin_unlock_irqrestore(&tp->lock, flags);
3087}
3088
3089/**
3090 * rtl8169_get_stats - Get rtl8169 read/write statistics
3091 * @dev: The Ethernet Device to get statistics for
3092 *
3093 * Get TX/RX statistics for rtl8169
3094 */
3095static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3096{
3097 struct rtl8169_private *tp = netdev_priv(dev);
3098 void __iomem *ioaddr = tp->mmio_addr;
3099 unsigned long flags;
3100
3101 if (netif_running(dev)) {
3102 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3103 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3104 RTL_W32(RxMissed, 0);
3105 spin_unlock_irqrestore(&tp->lock, flags);
3106 }
5b0384f4 3107
cebf8cc7 3108 return &dev->stats;
1da177e4
LT		 3109}
3110
5d06a99f
FR		 3111#ifdef CONFIG_PM
3112
3113static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3114{
3115 struct net_device *dev = pci_get_drvdata(pdev);
3116 struct rtl8169_private *tp = netdev_priv(dev);
3117 void __iomem *ioaddr = tp->mmio_addr;
3118
3119 if (!netif_running(dev))
1371fa6d 3120 goto out_pci_suspend;
5d06a99f
FR		 3121
3122 netif_device_detach(dev);
3123 netif_stop_queue(dev);
3124
3125 spin_lock_irq(&tp->lock);
3126
3127 rtl8169_asic_down(ioaddr);
3128
cebf8cc7 3129 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3130 RTL_W32(RxMissed, 0);
3131
3132 spin_unlock_irq(&tp->lock);
3133
1371fa6d 3134out_pci_suspend:
5d06a99f 3135 pci_save_state(pdev);
f23e7fda
FR		 3136 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3137 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3138 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3139
5d06a99f
FR		 3140 return 0;
3141}
3142
3143static int rtl8169_resume(struct pci_dev *pdev)
3144{
3145 struct net_device *dev = pci_get_drvdata(pdev);
3146
1371fa6d
FR		 3147 pci_set_power_state(pdev, PCI_D0);
3148 pci_restore_state(pdev);
3149 pci_enable_wake(pdev, PCI_D0, 0);
3150
5d06a99f
FR		 3151 if (!netif_running(dev))
3152 goto out;
3153
3154 netif_device_attach(dev);
3155
5d06a99f
FR		 3156 rtl8169_schedule_work(dev, rtl8169_reset_task);
3157out:
3158 return 0;
3159}
3160
3161#endif /* CONFIG_PM */
3162
1da177e4
LT		 3163static struct pci_driver rtl8169_pci_driver = {
3164 .name = MODULENAME,
3165 .id_table = rtl8169_pci_tbl,
3166 .probe = rtl8169_init_one,
3167 .remove = __devexit_p(rtl8169_remove_one),
3168#ifdef CONFIG_PM
3169 .suspend = rtl8169_suspend,
3170 .resume = rtl8169_resume,
3171#endif
3172};
3173
07d3f51f 3174static int __init rtl8169_init_module(void)
1da177e4 3175{
29917620 3176 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3177}
3178
07d3f51f 3179static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3180{
3181 pci_unregister_driver(&rtl8169_pci_driver);
3182}
3183
3184module_init(rtl8169_init_module);
3185module_exit(rtl8169_cleanup_module);
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