]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/r8169.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: phy init for the 8169sce
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4
LT		 54/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 56static const int multicast_filter_limit = 32;
1da177e4
LT		 57
58/* MAC address length */
59#define MAC_ADDR_LEN 6
60
9c14ceaf 61#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 62#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 65#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 66#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_NAPI_WEIGHT 64
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77#define RTL8169_TX_TIMEOUT (6*HZ)
78#define RTL8169_PHY_TIMEOUT (10*HZ)
79
ea8dbdd1 80#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 82#define RTL_EEPROM_SIG_ADDR 0x0000
83
1da177e4
LT		 84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
f21b75e9 93 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9
FR		 117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
1da177e4
LT		 119};
120
1da177e4
LT		 121#define _R(NAME,MAC,MASK) \
122 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
123
3c6bee1d 124static const struct {
1da177e4
LT		 125 const char *name;
126 u8 mac_version;
127 u32 RxConfigMask; /* Clears the bits supported by this chip */
128} rtl_chip_info[] = {
ba6eb6ee
FR		 129 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
130 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
131 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
132 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 134 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 135 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
137 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 143 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
146 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 151 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9
FR		 152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
153 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
1da177e4
LT		 154};
155#undef _R
156
bcf0bf90
FR		 157enum cfg_version {
158 RTL_CFG_0 = 0x00,
159 RTL_CFG_1,
160 RTL_CFG_2
161};
162
07ce4064
FR		 163static void rtl_hw_start_8169(struct net_device *);
164static void rtl_hw_start_8168(struct net_device *);
165static void rtl_hw_start_8101(struct net_device *);
166
1da177e4 167static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 174 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 175 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
176 { PCI_VENDOR_ID_LINKSYS, 0x1032,
177 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 178 { 0x0001, 0x8168,
179 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 180 {0,},
181};
182
183MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
184
185static int rx_copybreak = 200;
186static int use_dac;
b57b7e5a
SH		 187static struct {
188 u32 msg_enable;
189} debug = { -1 };
1da177e4 190
07d3f51f
FR		 191enum rtl_registers {
192 MAC0 = 0, /* Ethernet hardware address. */
773d2021 193 MAC4 = 4,
07d3f51f
FR		 194 MAR0 = 8, /* Multicast filter. */
195 CounterAddrLow = 0x10,
196 CounterAddrHigh = 0x14,
197 TxDescStartAddrLow = 0x20,
198 TxDescStartAddrHigh = 0x24,
199 TxHDescStartAddrLow = 0x28,
200 TxHDescStartAddrHigh = 0x2c,
201 FLASH = 0x30,
202 ERSR = 0x36,
203 ChipCmd = 0x37,
204 TxPoll = 0x38,
205 IntrMask = 0x3c,
206 IntrStatus = 0x3e,
207 TxConfig = 0x40,
208 RxConfig = 0x44,
209 RxMissed = 0x4c,
210 Cfg9346 = 0x50,
211 Config0 = 0x51,
212 Config1 = 0x52,
213 Config2 = 0x53,
214 Config3 = 0x54,
215 Config4 = 0x55,
216 Config5 = 0x56,
217 MultiIntr = 0x5c,
218 PHYAR = 0x60,
07d3f51f
FR		 219 PHYstatus = 0x6c,
220 RxMaxSize = 0xda,
221 CPlusCmd = 0xe0,
222 IntrMitigate = 0xe2,
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 EarlyTxThres = 0xec,
226 FuncEvent = 0xf0,
227 FuncEventMask = 0xf4,
228 FuncPresetState = 0xf8,
229 FuncForceEvent = 0xfc,
1da177e4
LT		 230};
231
f162a5d1
FR		 232enum rtl8110_registers {
233 TBICSR = 0x64,
234 TBI_ANAR = 0x68,
235 TBI_LPAR = 0x6a,
236};
237
238enum rtl8168_8101_registers {
239 CSIDR = 0x64,
240 CSIAR = 0x68,
241#define CSIAR_FLAG 0x80000000
242#define CSIAR_WRITE_CMD 0x80000000
243#define CSIAR_BYTE_ENABLE 0x0f
244#define CSIAR_BYTE_ENABLE_SHIFT 12
245#define CSIAR_ADDR_MASK 0x0fff
246
247 EPHYAR = 0x80,
248#define EPHYAR_FLAG 0x80000000
249#define EPHYAR_WRITE_CMD 0x80000000
250#define EPHYAR_REG_MASK 0x1f
251#define EPHYAR_REG_SHIFT 16
252#define EPHYAR_DATA_MASK 0xffff
253 DBG_REG = 0xd1,
254#define FIX_NAK_1 (1 << 4)
255#define FIX_NAK_2 (1 << 3)
256};
257
07d3f51f 258enum rtl_register_content {
1da177e4 259 /* InterruptStatusBits */
07d3f51f
FR		 260 SYSErr = 0x8000,
261 PCSTimeout = 0x4000,
262 SWInt = 0x0100,
263 TxDescUnavail = 0x0080,
264 RxFIFOOver = 0x0040,
265 LinkChg = 0x0020,
266 RxOverflow = 0x0010,
267 TxErr = 0x0008,
268 TxOK = 0x0004,
269 RxErr = 0x0002,
270 RxOK = 0x0001,
1da177e4
LT		 271
272 /* RxStatusDesc */
9dccf611
FR		 273 RxFOVF = (1 << 23),
274 RxRWT = (1 << 22),
275 RxRES = (1 << 21),
276 RxRUNT = (1 << 20),
277 RxCRC = (1 << 19),
1da177e4
LT		 278
279 /* ChipCmdBits */
07d3f51f
FR		 280 CmdReset = 0x10,
281 CmdRxEnb = 0x08,
282 CmdTxEnb = 0x04,
283 RxBufEmpty = 0x01,
1da177e4 284
275391a4
FR		 285 /* TXPoll register p.5 */
286 HPQ = 0x80, /* Poll cmd on the high prio queue */
287 NPQ = 0x40, /* Poll cmd on the low prio queue */
288 FSWInt = 0x01, /* Forced software interrupt */
289
1da177e4 290 /* Cfg9346Bits */
07d3f51f
FR		 291 Cfg9346_Lock = 0x00,
292 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 293
294 /* rx_mode_bits */
07d3f51f
FR		 295 AcceptErr = 0x20,
296 AcceptRunt = 0x10,
297 AcceptBroadcast = 0x08,
298 AcceptMulticast = 0x04,
299 AcceptMyPhys = 0x02,
300 AcceptAllPhys = 0x01,
1da177e4
LT		 301
302 /* RxConfigBits */
07d3f51f
FR		 303 RxCfgFIFOShift = 13,
304 RxCfgDMAShift = 8,
1da177e4
LT		 305
306 /* TxConfigBits */
307 TxInterFrameGapShift = 24,
308 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
309
5d06a99f 310 /* Config1 register p.24 */
f162a5d1
FR		 311 LEDS1 = (1 << 7),
312 LEDS0 = (1 << 6),
fbac58fc 313 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 314 Speed_down = (1 << 4),
315 MEMMAP = (1 << 3),
316 IOMAP = (1 << 2),
317 VPD = (1 << 1),
5d06a99f
FR		 318 PMEnable = (1 << 0), /* Power Management Enable */
319
6dccd16b
FR		 320 /* Config2 register p. 25 */
321 PCI_Clock_66MHz = 0x01,
322 PCI_Clock_33MHz = 0x00,
323
61a4dcc2
FR		 324 /* Config3 register p.25 */
325 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
326 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 327 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 328
5d06a99f 329 /* Config5 register p.27 */
61a4dcc2
FR		 330 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF = (1 << 5), /* Accept Multicast wakeup frame */
332 UWF = (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 334 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
335
1da177e4
LT		 336 /* TBICSR p.28 */
337 TBIReset = 0x80000000,
338 TBILoopback = 0x40000000,
339 TBINwEnable = 0x20000000,
340 TBINwRestart = 0x10000000,
341 TBILinkOk = 0x02000000,
342 TBINwComplete = 0x01000000,
343
344 /* CPlusCmd p.31 */
f162a5d1
FR		 345 EnableBist = (1 << 15), // 8168 8101
346 Mac_dbgo_oe = (1 << 14), // 8168 8101
347 Normal_mode = (1 << 13), // unused
348 Force_half_dup = (1 << 12), // 8168 8101
349 Force_rxflow_en = (1 << 11), // 8168 8101
350 Force_txflow_en = (1 << 10), // 8168 8101
351 Cxpl_dbg_sel = (1 << 9), // 8168 8101
352 ASF = (1 << 8), // 8168 8101
353 PktCntrDisable = (1 << 7), // 8168 8101
354 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 355 RxVlan = (1 << 6),
356 RxChkSum = (1 << 5),
357 PCIDAC = (1 << 4),
358 PCIMulRW = (1 << 3),
0e485150
FR		 359 INTT_0 = 0x0000, // 8168
360 INTT_1 = 0x0001, // 8168
361 INTT_2 = 0x0002, // 8168
362 INTT_3 = 0x0003, // 8168
1da177e4
LT		 363
364 /* rtl8169_PHYstatus */
07d3f51f
FR		 365 TBI_Enable = 0x80,
366 TxFlowCtrl = 0x40,
367 RxFlowCtrl = 0x20,
368 _1000bpsF = 0x10,
369 _100bps = 0x08,
370 _10bps = 0x04,
371 LinkStatus = 0x02,
372 FullDup = 0x01,
1da177e4 373
1da177e4 374 /* _TBICSRBit */
07d3f51f 375 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 376
377 /* DumpCounterCommand */
07d3f51f 378 CounterDump = 0x8,
1da177e4
LT		 379};
380
07d3f51f 381enum desc_status_bit {
1da177e4
LT		 382 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd = (1 << 30), /* End of descriptor ring */
384 FirstFrag = (1 << 29), /* First segment of a packet */
385 LastFrag = (1 << 28), /* Final segment of a packet */
386
387 /* Tx private */
388 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift = 16, /* MSS value position */
390 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS = (1 << 18), /* Calculate IP checksum */
392 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag = (1 << 17), /* Add VLAN tag */
395
396 /* Rx private */
397 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
398 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
399
400#define RxProtoUDP (PID1)
401#define RxProtoTCP (PID0)
402#define RxProtoIP (PID1 | PID0)
403#define RxProtoMask RxProtoIP
404
405 IPFail = (1 << 16), /* IP checksum failed */
406 UDPFail = (1 << 15), /* UDP/IP checksum failed */
407 TCPFail = (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag = (1 << 16), /* VLAN tag available */
409};
410
411#define RsvdMask 0x3fffc000
412
413struct TxDesc {
6cccd6e7
REB		 414 __le32 opts1;
415 __le32 opts2;
416 __le64 addr;
1da177e4
LT		 417};
418
419struct RxDesc {
6cccd6e7
REB		 420 __le32 opts1;
421 __le32 opts2;
422 __le64 addr;
1da177e4
LT		 423};
424
425struct ring_info {
426 struct sk_buff *skb;
427 u32 len;
428 u8 __pad[sizeof(void *) - sizeof(u32)];
429};
430
f23e7fda 431enum features {
ccdffb9a
FR		 432 RTL_FEATURE_WOL = (1 << 0),
433 RTL_FEATURE_MSI = (1 << 1),
434 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 435};
436
355423d0
IV		 437struct rtl8169_counters {
438 __le64 tx_packets;
439 __le64 rx_packets;
440 __le64 tx_errors;
441 __le32 rx_errors;
442 __le16 rx_missed;
443 __le16 align_errors;
444 __le32 tx_one_collision;
445 __le32 tx_multi_collision;
446 __le64 rx_unicast;
447 __le64 rx_broadcast;
448 __le32 rx_multicast;
449 __le16 tx_aborted;
450 __le16 tx_underun;
451};
452
1da177e4
LT		 453struct rtl8169_private {
454 void __iomem *mmio_addr; /* memory map physical address */
455 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 456 struct net_device *dev;
bea3348e 457 struct napi_struct napi;
1da177e4 458 spinlock_t lock; /* spin lock flag */
b57b7e5a 459 u32 msg_enable;
1da177e4
LT		 460 int chipset;
461 int mac_version;
1da177e4
LT		 462 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
463 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
464 u32 dirty_rx;
465 u32 dirty_tx;
466 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
467 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
468 dma_addr_t TxPhyAddr;
469 dma_addr_t RxPhyAddr;
470 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
471 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 472 unsigned align;
1da177e4
LT		 473 unsigned rx_buf_sz;
474 struct timer_list timer;
475 u16 cp_cmd;
0e485150
FR		 476 u16 intr_event;
477 u16 napi_event;
1da177e4 478 u16 intr_mask;
1da177e4
LT		 479 int phy_1000_ctrl_reg;
480#ifdef CONFIG_R8169_VLAN
481 struct vlan_group *vlgrp;
482#endif
483 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 484 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 485 void (*phy_reset_enable)(void __iomem *);
07ce4064 486 void (*hw_start)(struct net_device *);
1da177e4
LT		 487 unsigned int (*phy_reset_pending)(void __iomem *);
488 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 489 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 490 int pcie_cap;
c4028958 491 struct delayed_work task;
f23e7fda 492 unsigned features;
ccdffb9a
FR		 493
494 struct mii_if_info mii;
355423d0 495 struct rtl8169_counters counters;
1da177e4
LT		 496};
497
979b6c13 498MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 499MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 500module_param(rx_copybreak, int, 0);
1b7efd58 501MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 502module_param(use_dac, int, 0);
503MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 504module_param_named(debug, debug.msg_enable, int, 0);
505MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 506MODULE_LICENSE("GPL");
507MODULE_VERSION(RTL8169_VERSION);
508
509static int rtl8169_open(struct net_device *dev);
510static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 511static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 512static int rtl8169_init_ring(struct net_device *dev);
07ce4064 513static void rtl_hw_start(struct net_device *dev);
1da177e4 514static int rtl8169_close(struct net_device *dev);
07ce4064 515static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 516static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 517static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 518static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 519 void __iomem *, u32 budget);
4dcb7d33 520static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 521static void rtl8169_down(struct net_device *dev);
99f252b0 522static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 523static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 524
1da177e4 525static const unsigned int rtl8169_rx_config =
5b0384f4 526 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 527
07d3f51f 528static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 529{
530 int i;
531
a6baf3af 532 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 533
2371408c 534 for (i = 20; i > 0; i--) {
07d3f51f
FR		 535 /*
536 * Check if the RTL8169 has completed writing to the specified
537 * MII register.
538 */
5b0384f4 539 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 540 break;
2371408c 541 udelay(25);
1da177e4
LT		 542 }
543}
544
07d3f51f 545static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 546{
547 int i, value = -1;
548
a6baf3af 549 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 550
2371408c 551 for (i = 20; i > 0; i--) {
07d3f51f
FR		 552 /*
553 * Check if the RTL8169 has completed retrieving data from
554 * the specified MII register.
555 */
1da177e4 556 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 557 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 558 break;
559 }
2371408c 560 udelay(25);
1da177e4
LT		 561 }
562 return value;
563}
564
dacf8154
FR		 565static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
566{
567 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
568}
569
ccdffb9a
FR		 570static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
571 int val)
572{
573 struct rtl8169_private *tp = netdev_priv(dev);
574 void __iomem *ioaddr = tp->mmio_addr;
575
576 mdio_write(ioaddr, location, val);
577}
578
579static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
580{
581 struct rtl8169_private *tp = netdev_priv(dev);
582 void __iomem *ioaddr = tp->mmio_addr;
583
584 return mdio_read(ioaddr, location);
585}
586
dacf8154
FR		 587static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
588{
589 unsigned int i;
590
591 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
592 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
593
594 for (i = 0; i < 100; i++) {
595 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
596 break;
597 udelay(10);
598 }
599}
600
601static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
602{
603 u16 value = 0xffff;
604 unsigned int i;
605
606 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
607
608 for (i = 0; i < 100; i++) {
609 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
610 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
611 break;
612 }
613 udelay(10);
614 }
615
616 return value;
617}
618
619static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
620{
621 unsigned int i;
622
623 RTL_W32(CSIDR, value);
624 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
625 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
626
627 for (i = 0; i < 100; i++) {
628 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
629 break;
630 udelay(10);
631 }
632}
633
634static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
635{
636 u32 value = ~0x00;
637 unsigned int i;
638
639 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
640 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
641
642 for (i = 0; i < 100; i++) {
643 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
644 value = RTL_R32(CSIDR);
645 break;
646 }
647 udelay(10);
648 }
649
650 return value;
651}
652
1da177e4
LT		 653static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
654{
655 RTL_W16(IntrMask, 0x0000);
656
657 RTL_W16(IntrStatus, 0xffff);
658}
659
660static void rtl8169_asic_down(void __iomem *ioaddr)
661{
662 RTL_W8(ChipCmd, 0x00);
663 rtl8169_irq_mask_and_ack(ioaddr);
664 RTL_R16(CPlusCmd);
665}
666
667static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
668{
669 return RTL_R32(TBICSR) & TBIReset;
670}
671
672static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
673{
64e4bfb4 674 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 675}
676
677static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
678{
679 return RTL_R32(TBICSR) & TBILinkOk;
680}
681
682static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
683{
684 return RTL_R8(PHYstatus) & LinkStatus;
685}
686
687static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
688{
689 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
690}
691
692static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
693{
694 unsigned int val;
695
9e0db8ef
FR		 696 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
697 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 698}
699
700static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 701 struct rtl8169_private *tp,
702 void __iomem *ioaddr)
1da177e4
LT		 703{
704 unsigned long flags;
705
706 spin_lock_irqsave(&tp->lock, flags);
707 if (tp->link_ok(ioaddr)) {
708 netif_carrier_on(dev);
b57b7e5a
SH		 709 if (netif_msg_ifup(tp))
710 printk(KERN_INFO PFX "%s: link up\n", dev->name);
711 } else {
712 if (netif_msg_ifdown(tp))
713 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 714 netif_carrier_off(dev);
b57b7e5a 715 }
1da177e4
LT		 716 spin_unlock_irqrestore(&tp->lock, flags);
717}
718
61a4dcc2
FR		 719static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
720{
721 struct rtl8169_private *tp = netdev_priv(dev);
722 void __iomem *ioaddr = tp->mmio_addr;
723 u8 options;
724
725 wol->wolopts = 0;
726
727#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
728 wol->supported = WAKE_ANY;
729
730 spin_lock_irq(&tp->lock);
731
732 options = RTL_R8(Config1);
733 if (!(options & PMEnable))
734 goto out_unlock;
735
736 options = RTL_R8(Config3);
737 if (options & LinkUp)
738 wol->wolopts |= WAKE_PHY;
739 if (options & MagicPacket)
740 wol->wolopts |= WAKE_MAGIC;
741
742 options = RTL_R8(Config5);
743 if (options & UWF)
744 wol->wolopts |= WAKE_UCAST;
745 if (options & BWF)
5b0384f4 746 wol->wolopts |= WAKE_BCAST;
61a4dcc2 747 if (options & MWF)
5b0384f4 748 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 749
750out_unlock:
751 spin_unlock_irq(&tp->lock);
752}
753
754static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
755{
756 struct rtl8169_private *tp = netdev_priv(dev);
757 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 758 unsigned int i;
61a4dcc2
FR		 759 static struct {
760 u32 opt;
761 u16 reg;
762 u8 mask;
763 } cfg[] = {
764 { WAKE_ANY, Config1, PMEnable },
765 { WAKE_PHY, Config3, LinkUp },
766 { WAKE_MAGIC, Config3, MagicPacket },
767 { WAKE_UCAST, Config5, UWF },
768 { WAKE_BCAST, Config5, BWF },
769 { WAKE_MCAST, Config5, MWF },
770 { WAKE_ANY, Config5, LanWake }
771 };
772
773 spin_lock_irq(&tp->lock);
774
775 RTL_W8(Cfg9346, Cfg9346_Unlock);
776
777 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
778 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
779 if (wol->wolopts & cfg[i].opt)
780 options |= cfg[i].mask;
781 RTL_W8(cfg[i].reg, options);
782 }
783
784 RTL_W8(Cfg9346, Cfg9346_Lock);
785
f23e7fda
FR		 786 if (wol->wolopts)
787 tp->features |= RTL_FEATURE_WOL;
788 else
789 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 790 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 791
792 spin_unlock_irq(&tp->lock);
793
794 return 0;
795}
796
1da177e4
LT		 797static void rtl8169_get_drvinfo(struct net_device *dev,
798 struct ethtool_drvinfo *info)
799{
800 struct rtl8169_private *tp = netdev_priv(dev);
801
802 strcpy(info->driver, MODULENAME);
803 strcpy(info->version, RTL8169_VERSION);
804 strcpy(info->bus_info, pci_name(tp->pci_dev));
805}
806
807static int rtl8169_get_regs_len(struct net_device *dev)
808{
809 return R8169_REGS_SIZE;
810}
811
812static int rtl8169_set_speed_tbi(struct net_device *dev,
813 u8 autoneg, u16 speed, u8 duplex)
814{
815 struct rtl8169_private *tp = netdev_priv(dev);
816 void __iomem *ioaddr = tp->mmio_addr;
817 int ret = 0;
818 u32 reg;
819
820 reg = RTL_R32(TBICSR);
821 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
822 (duplex == DUPLEX_FULL)) {
823 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
824 } else if (autoneg == AUTONEG_ENABLE)
825 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
826 else {
b57b7e5a
SH		 827 if (netif_msg_link(tp)) {
828 printk(KERN_WARNING "%s: "
829 "incorrect speed setting refused in TBI mode\n",
830 dev->name);
831 }
1da177e4
LT		 832 ret = -EOPNOTSUPP;
833 }
834
835 return ret;
836}
837
838static int rtl8169_set_speed_xmii(struct net_device *dev,
839 u8 autoneg, u16 speed, u8 duplex)
840{
841 struct rtl8169_private *tp = netdev_priv(dev);
842 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 843 int giga_ctrl, bmcr;
1da177e4
LT		 844
845 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 846 int auto_nego;
847
848 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 849 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
850 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 851 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 852
3577aa1b 853 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
854 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 855
3577aa1b 856 /* The 8100e/8101e/8102e do Fast Ethernet only. */
857 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
858 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
859 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
860 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
861 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
862 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
863 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
864 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
865 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
866 } else if (netif_msg_link(tp)) {
bcf0bf90
FR		 867 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
868 dev->name);
869 }
1da177e4 870
3577aa1b 871 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
872
873 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
874 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
875 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
876 /*
877 * Wake up the PHY.
878 * Vendor specific (0x1f) and reserved (0x0e) MII
879 * registers.
880 */
881 mdio_write(ioaddr, 0x1f, 0x0000);
882 mdio_write(ioaddr, 0x0e, 0x0000);
883 }
884
885 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
886 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
887 } else {
888 giga_ctrl = 0;
889
890 if (speed == SPEED_10)
891 bmcr = 0;
892 else if (speed == SPEED_100)
893 bmcr = BMCR_SPEED100;
894 else
895 return -EINVAL;
896
897 if (duplex == DUPLEX_FULL)
898 bmcr |= BMCR_FULLDPLX;
623a1593 899
2584fbc3 900 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 901 }
902
1da177e4
LT		 903 tp->phy_1000_ctrl_reg = giga_ctrl;
904
3577aa1b 905 mdio_write(ioaddr, MII_BMCR, bmcr);
906
907 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
908 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
909 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
910 mdio_write(ioaddr, 0x17, 0x2138);
911 mdio_write(ioaddr, 0x0e, 0x0260);
912 } else {
913 mdio_write(ioaddr, 0x17, 0x2108);
914 mdio_write(ioaddr, 0x0e, 0x0000);
915 }
916 }
917
1da177e4
LT		 918 return 0;
919}
920
921static int rtl8169_set_speed(struct net_device *dev,
922 u8 autoneg, u16 speed, u8 duplex)
923{
924 struct rtl8169_private *tp = netdev_priv(dev);
925 int ret;
926
927 ret = tp->set_speed(dev, autoneg, speed, duplex);
928
64e4bfb4 929 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 930 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
931
932 return ret;
933}
934
935static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
936{
937 struct rtl8169_private *tp = netdev_priv(dev);
938 unsigned long flags;
939 int ret;
940
941 spin_lock_irqsave(&tp->lock, flags);
942 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
943 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 944
1da177e4
LT		 945 return ret;
946}
947
948static u32 rtl8169_get_rx_csum(struct net_device *dev)
949{
950 struct rtl8169_private *tp = netdev_priv(dev);
951
952 return tp->cp_cmd & RxChkSum;
953}
954
955static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
956{
957 struct rtl8169_private *tp = netdev_priv(dev);
958 void __iomem *ioaddr = tp->mmio_addr;
959 unsigned long flags;
960
961 spin_lock_irqsave(&tp->lock, flags);
962
963 if (data)
964 tp->cp_cmd |= RxChkSum;
965 else
966 tp->cp_cmd &= ~RxChkSum;
967
968 RTL_W16(CPlusCmd, tp->cp_cmd);
969 RTL_R16(CPlusCmd);
970
971 spin_unlock_irqrestore(&tp->lock, flags);
972
973 return 0;
974}
975
976#ifdef CONFIG_R8169_VLAN
977
978static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
979 struct sk_buff *skb)
980{
981 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
982 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
983}
984
985static void rtl8169_vlan_rx_register(struct net_device *dev,
986 struct vlan_group *grp)
987{
988 struct rtl8169_private *tp = netdev_priv(dev);
989 void __iomem *ioaddr = tp->mmio_addr;
990 unsigned long flags;
991
992 spin_lock_irqsave(&tp->lock, flags);
993 tp->vlgrp = grp;
994 if (tp->vlgrp)
995 tp->cp_cmd |= RxVlan;
996 else
997 tp->cp_cmd &= ~RxVlan;
998 RTL_W16(CPlusCmd, tp->cp_cmd);
999 RTL_R16(CPlusCmd);
1000 spin_unlock_irqrestore(&tp->lock, flags);
1001}
1002
1da177e4
LT		 1003static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1004 struct sk_buff *skb)
1005{
1006 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1007 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1008 int ret;
1009
865c652d
FR		 1010 if (vlgrp && (opts2 & RxVlanTag)) {
1011 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1012 ret = 0;
1013 } else
1014 ret = -1;
1015 desc->opts2 = 0;
1016 return ret;
1017}
1018
1019#else /* !CONFIG_R8169_VLAN */
1020
1021static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1022 struct sk_buff *skb)
1023{
1024 return 0;
1025}
1026
1027static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1028 struct sk_buff *skb)
1029{
1030 return -1;
1031}
1032
1033#endif
1034
ccdffb9a 1035static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1036{
1037 struct rtl8169_private *tp = netdev_priv(dev);
1038 void __iomem *ioaddr = tp->mmio_addr;
1039 u32 status;
1040
1041 cmd->supported =
1042 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1043 cmd->port = PORT_FIBRE;
1044 cmd->transceiver = XCVR_INTERNAL;
1045
1046 status = RTL_R32(TBICSR);
1047 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1048 cmd->autoneg = !!(status & TBINwEnable);
1049
1050 cmd->speed = SPEED_1000;
1051 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1052
1053 return 0;
1da177e4
LT		 1054}
1055
ccdffb9a 1056static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1057{
1058 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1059
1060 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1061}
1062
1063static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1064{
1065 struct rtl8169_private *tp = netdev_priv(dev);
1066 unsigned long flags;
ccdffb9a 1067 int rc;
1da177e4
LT		 1068
1069 spin_lock_irqsave(&tp->lock, flags);
1070
ccdffb9a 1071 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1072
1073 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1074 return rc;
1da177e4
LT		 1075}
1076
1077static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1078 void *p)
1079{
5b0384f4
FR		 1080 struct rtl8169_private *tp = netdev_priv(dev);
1081 unsigned long flags;
1da177e4 1082
5b0384f4
FR		 1083 if (regs->len > R8169_REGS_SIZE)
1084 regs->len = R8169_REGS_SIZE;
1da177e4 1085
5b0384f4
FR		 1086 spin_lock_irqsave(&tp->lock, flags);
1087 memcpy_fromio(p, tp->mmio_addr, regs->len);
1088 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1089}
1090
b57b7e5a
SH		 1091static u32 rtl8169_get_msglevel(struct net_device *dev)
1092{
1093 struct rtl8169_private *tp = netdev_priv(dev);
1094
1095 return tp->msg_enable;
1096}
1097
1098static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1099{
1100 struct rtl8169_private *tp = netdev_priv(dev);
1101
1102 tp->msg_enable = value;
1103}
1104
d4a3a0fc
SH		 1105static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1106 "tx_packets",
1107 "rx_packets",
1108 "tx_errors",
1109 "rx_errors",
1110 "rx_missed",
1111 "align_errors",
1112 "tx_single_collisions",
1113 "tx_multi_collisions",
1114 "unicast",
1115 "broadcast",
1116 "multicast",
1117 "tx_aborted",
1118 "tx_underrun",
1119};
1120
b9f2c044 1121static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1122{
b9f2c044
JG		 1123 switch (sset) {
1124 case ETH_SS_STATS:
1125 return ARRAY_SIZE(rtl8169_gstrings);
1126 default:
1127 return -EOPNOTSUPP;
1128 }
d4a3a0fc
SH		 1129}
1130
355423d0 1131static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1132{
1133 struct rtl8169_private *tp = netdev_priv(dev);
1134 void __iomem *ioaddr = tp->mmio_addr;
1135 struct rtl8169_counters *counters;
1136 dma_addr_t paddr;
1137 u32 cmd;
355423d0 1138 int wait = 1000;
d4a3a0fc 1139
355423d0
IV		 1140 /*
1141 * Some chips are unable to dump tally counters when the receiver
1142 * is disabled.
1143 */
1144 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1145 return;
d4a3a0fc
SH		 1146
1147 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1148 if (!counters)
1149 return;
1150
1151 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1152 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1153 RTL_W32(CounterAddrLow, cmd);
1154 RTL_W32(CounterAddrLow, cmd | CounterDump);
1155
355423d0
IV		 1156 while (wait--) {
1157 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1158 /* copy updated counters */
1159 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1160 break;
355423d0
IV		 1161 }
1162 udelay(10);
d4a3a0fc
SH		 1163 }
1164
1165 RTL_W32(CounterAddrLow, 0);
1166 RTL_W32(CounterAddrHigh, 0);
1167
d4a3a0fc
SH		 1168 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1169}
1170
355423d0
IV		 1171static void rtl8169_get_ethtool_stats(struct net_device *dev,
1172 struct ethtool_stats *stats, u64 *data)
1173{
1174 struct rtl8169_private *tp = netdev_priv(dev);
1175
1176 ASSERT_RTNL();
1177
1178 rtl8169_update_counters(dev);
1179
1180 data[0] = le64_to_cpu(tp->counters.tx_packets);
1181 data[1] = le64_to_cpu(tp->counters.rx_packets);
1182 data[2] = le64_to_cpu(tp->counters.tx_errors);
1183 data[3] = le32_to_cpu(tp->counters.rx_errors);
1184 data[4] = le16_to_cpu(tp->counters.rx_missed);
1185 data[5] = le16_to_cpu(tp->counters.align_errors);
1186 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1187 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1188 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1189 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1190 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1191 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1192 data[12] = le16_to_cpu(tp->counters.tx_underun);
1193}
1194
d4a3a0fc
SH		 1195static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1196{
1197 switch(stringset) {
1198 case ETH_SS_STATS:
1199 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1200 break;
1201 }
1202}
1203
7282d491 1204static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1205 .get_drvinfo = rtl8169_get_drvinfo,
1206 .get_regs_len = rtl8169_get_regs_len,
1207 .get_link = ethtool_op_get_link,
1208 .get_settings = rtl8169_get_settings,
1209 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1210 .get_msglevel = rtl8169_get_msglevel,
1211 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1212 .get_rx_csum = rtl8169_get_rx_csum,
1213 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1214 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1215 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1216 .set_tso = ethtool_op_set_tso,
1217 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1218 .get_wol = rtl8169_get_wol,
1219 .set_wol = rtl8169_set_wol,
d4a3a0fc 1220 .get_strings = rtl8169_get_strings,
b9f2c044 1221 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1222 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1223};
1224
07d3f51f
FR		 1225static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1226 int bitnum, int bitval)
1da177e4
LT		 1227{
1228 int val;
1229
1230 val = mdio_read(ioaddr, reg);
1231 val = (bitval == 1) ?
1232 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1233 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1234}
1235
07d3f51f
FR		 1236static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1237 void __iomem *ioaddr)
1da177e4 1238{
0e485150
FR		 1239 /*
1240 * The driver currently handles the 8168Bf and the 8168Be identically
1241 * but they can be identified more specifically through the test below
1242 * if needed:
1243 *
1244 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1245 *
1246 * Same thing for the 8101Eb and the 8101Ec:
1247 *
1248 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1249 */
1da177e4
LT		 1250 const struct {
1251 u32 mask;
e3cf0cc0 1252 u32 val;
1da177e4
LT		 1253 int mac_version;
1254 } mac_info[] = {
5b538df9
FR		 1255 /* 8168D family. */
1256 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1257
ef808d50 1258 /* 8168C family. */
7f3e3d3a 1259 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1260 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1261 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1262 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1263 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1264 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1265 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1266 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1267 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1268
1269 /* 8168B family. */
1270 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1271 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1272 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1273 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1274
1275 /* 8101 family. */
2857ffb7
FR		 1276 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1277 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1278 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1279 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1280 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1281 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1282 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1283 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1284 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1285 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1286 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1287 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1288 /* FIXME: where did these entries come from ? -- FR */
1289 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1290 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1291
1292 /* 8110 family. */
1293 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1294 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1295 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1296 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1297 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1298 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1299
f21b75e9
JD		 1300 /* Catch-all */
1301 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1302 }, *p = mac_info;
1303 u32 reg;
1304
e3cf0cc0
FR		 1305 reg = RTL_R32(TxConfig);
1306 while ((reg & p->mask) != p->val)
1da177e4
LT		 1307 p++;
1308 tp->mac_version = p->mac_version;
1309}
1310
1311static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1312{
bcf0bf90 1313 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1314}
1315
867763c1
FR		 1316struct phy_reg {
1317 u16 reg;
1318 u16 val;
1319};
1320
1321static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1322{
1323 while (len-- > 0) {
1324 mdio_write(ioaddr, regs->reg, regs->val);
1325 regs++;
1326 }
1327}
1328
5615d9f1 1329static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1330{
1da177e4
LT		 1331 struct {
1332 u16 regs[5]; /* Beware of bit-sign propagation */
1333 } phy_magic[5] = { {
1334 { 0x0000, //w 4 15 12 0
1335 0x00a1, //w 3 15 0 00a1
1336 0x0008, //w 2 15 0 0008
1337 0x1020, //w 1 15 0 1020
1338 0x1000 } },{ //w 0 15 0 1000
1339 { 0x7000, //w 4 15 12 7
1340 0xff41, //w 3 15 0 ff41
1341 0xde60, //w 2 15 0 de60
1342 0x0140, //w 1 15 0 0140
1343 0x0077 } },{ //w 0 15 0 0077
1344 { 0xa000, //w 4 15 12 a
1345 0xdf01, //w 3 15 0 df01
1346 0xdf20, //w 2 15 0 df20
1347 0xff95, //w 1 15 0 ff95
1348 0xfa00 } },{ //w 0 15 0 fa00
1349 { 0xb000, //w 4 15 12 b
1350 0xff41, //w 3 15 0 ff41
1351 0xde20, //w 2 15 0 de20
1352 0x0140, //w 1 15 0 0140
1353 0x00bb } },{ //w 0 15 0 00bb
1354 { 0xf000, //w 4 15 12 f
1355 0xdf01, //w 3 15 0 df01
1356 0xdf20, //w 2 15 0 df20
1357 0xff95, //w 1 15 0 ff95
1358 0xbf00 } //w 0 15 0 bf00
1359 }
1360 }, *p = phy_magic;
07d3f51f 1361 unsigned int i;
1da177e4 1362
a441d7b6
FR		 1363 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1364 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1365 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1366 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1367
1368 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1369 int val, pos = 4;
1370
1371 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1372 mdio_write(ioaddr, pos, val);
1373 while (--pos >= 0)
1374 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1375 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1376 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1377 }
a441d7b6 1378 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1379}
1380
5615d9f1
FR		 1381static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1382{
a441d7b6
FR		 1383 struct phy_reg phy_reg_init[] = {
1384 { 0x1f, 0x0002 },
1385 { 0x01, 0x90d0 },
1386 { 0x1f, 0x0000 }
1387 };
1388
1389 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1390}
1391
8c7006aa 1392static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1393{
1394 struct phy_reg phy_reg_init[] = {
1395 { 0x1f, 0x0001 },
1396 { 0x04, 0x0000 },
1397 { 0x03, 0x00a1 },
1398 { 0x02, 0x0008 },
1399 { 0x01, 0x0120 },
1400 { 0x00, 0x1000 },
1401 { 0x04, 0x0800 },
1402 { 0x04, 0x9000 },
1403 { 0x03, 0x802f },
1404 { 0x02, 0x4f02 },
1405 { 0x01, 0x0409 },
1406 { 0x00, 0xf099 },
1407 { 0x04, 0x9800 },
1408 { 0x04, 0xa000 },
1409 { 0x03, 0xdf01 },
1410 { 0x02, 0xdf20 },
1411 { 0x01, 0xff95 },
1412 { 0x00, 0xba00 },
1413 { 0x04, 0xa800 },
1414 { 0x04, 0xf000 },
1415 { 0x03, 0xdf01 },
1416 { 0x02, 0xdf20 },
1417 { 0x01, 0x101a },
1418 { 0x00, 0xa0ff },
1419 { 0x04, 0xf800 },
1420 { 0x04, 0x0000 },
1421 { 0x1f, 0x0000 },
1422
1423 { 0x1f, 0x0001 },
1424 { 0x0b, 0x8480 },
1425 { 0x1f, 0x0000 },
1426
1427 { 0x1f, 0x0001 },
1428 { 0x18, 0x67c7 },
1429 { 0x04, 0x2000 },
1430 { 0x03, 0x002f },
1431 { 0x02, 0x4360 },
1432 { 0x01, 0x0109 },
1433 { 0x00, 0x3022 },
1434 { 0x04, 0x2800 },
1435 { 0x1f, 0x0000 },
1436
1437 { 0x1f, 0x0001 },
1438 { 0x17, 0x0cc0 },
1439 { 0x1f, 0x0000 }
1440 };
1441
1442 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1443}
1444
236b8082
FR		 1445static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1446{
1447 struct phy_reg phy_reg_init[] = {
1448 { 0x10, 0xf41b },
1449 { 0x1f, 0x0000 }
1450 };
1451
1452 mdio_write(ioaddr, 0x1f, 0x0001);
1453 mdio_patch(ioaddr, 0x16, 1 << 0);
1454
1455 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1456}
1457
1458static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1459{
1460 struct phy_reg phy_reg_init[] = {
1461 { 0x1f, 0x0001 },
1462 { 0x10, 0xf41b },
1463 { 0x1f, 0x0000 }
1464 };
1465
1466 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1467}
1468
ef3386f0 1469static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1470{
1471 struct phy_reg phy_reg_init[] = {
1472 { 0x1f, 0x0000 },
1473 { 0x1d, 0x0f00 },
1474 { 0x1f, 0x0002 },
1475 { 0x0c, 0x1ec8 },
1476 { 0x1f, 0x0000 }
1477 };
1478
1479 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1480}
1481
ef3386f0
FR		 1482static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1483{
1484 struct phy_reg phy_reg_init[] = {
1485 { 0x1f, 0x0001 },
1486 { 0x1d, 0x3d98 },
1487 { 0x1f, 0x0000 }
1488 };
1489
1490 mdio_write(ioaddr, 0x1f, 0x0000);
1491 mdio_patch(ioaddr, 0x14, 1 << 5);
1492 mdio_patch(ioaddr, 0x0d, 1 << 5);
1493
1494 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1495}
1496
219a1e9d 1497static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1498{
1499 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1500 { 0x1f, 0x0001 },
1501 { 0x12, 0x2300 },
867763c1
FR		 1502 { 0x1f, 0x0002 },
1503 { 0x00, 0x88d4 },
1504 { 0x01, 0x82b1 },
1505 { 0x03, 0x7002 },
1506 { 0x08, 0x9e30 },
1507 { 0x09, 0x01f0 },
1508 { 0x0a, 0x5500 },
1509 { 0x0c, 0x00c8 },
1510 { 0x1f, 0x0003 },
1511 { 0x12, 0xc096 },
1512 { 0x16, 0x000a },
f50d4275
FR		 1513 { 0x1f, 0x0000 },
1514 { 0x1f, 0x0000 },
1515 { 0x09, 0x2000 },
1516 { 0x09, 0x0000 }
867763c1
FR		 1517 };
1518
1519 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1520
1521 mdio_patch(ioaddr, 0x14, 1 << 5);
1522 mdio_patch(ioaddr, 0x0d, 1 << 5);
1523 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1524}
1525
219a1e9d 1526static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1527{
1528 struct phy_reg phy_reg_init[] = {
f50d4275 1529 { 0x1f, 0x0001 },
7da97ec9 1530 { 0x12, 0x2300 },
f50d4275
FR		 1531 { 0x03, 0x802f },
1532 { 0x02, 0x4f02 },
1533 { 0x01, 0x0409 },
1534 { 0x00, 0xf099 },
1535 { 0x04, 0x9800 },
1536 { 0x04, 0x9000 },
1537 { 0x1d, 0x3d98 },
7da97ec9
FR		 1538 { 0x1f, 0x0002 },
1539 { 0x0c, 0x7eb8 },
f50d4275
FR		 1540 { 0x06, 0x0761 },
1541 { 0x1f, 0x0003 },
1542 { 0x16, 0x0f0a },
7da97ec9
FR		 1543 { 0x1f, 0x0000 }
1544 };
1545
1546 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1547
1548 mdio_patch(ioaddr, 0x16, 1 << 0);
1549 mdio_patch(ioaddr, 0x14, 1 << 5);
1550 mdio_patch(ioaddr, 0x0d, 1 << 5);
1551 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1552}
1553
197ff761
FR		 1554static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1555{
1556 struct phy_reg phy_reg_init[] = {
1557 { 0x1f, 0x0001 },
1558 { 0x12, 0x2300 },
1559 { 0x1d, 0x3d98 },
1560 { 0x1f, 0x0002 },
1561 { 0x0c, 0x7eb8 },
1562 { 0x06, 0x5461 },
1563 { 0x1f, 0x0003 },
1564 { 0x16, 0x0f0a },
1565 { 0x1f, 0x0000 }
1566 };
1567
1568 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1569
1570 mdio_patch(ioaddr, 0x16, 1 << 0);
1571 mdio_patch(ioaddr, 0x14, 1 << 5);
1572 mdio_patch(ioaddr, 0x0d, 1 << 5);
1573 mdio_write(ioaddr, 0x1f, 0x0000);
1574}
1575
6fb07058
FR		 1576static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1577{
1578 rtl8168c_3_hw_phy_config(ioaddr);
1579}
1580
5b538df9
FR		 1581static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1582{
1583 struct phy_reg phy_reg_init_0[] = {
1584 { 0x1f, 0x0001 },
1585 { 0x09, 0x2770 },
1586 { 0x08, 0x04d0 },
1587 { 0x0b, 0xad15 },
1588 { 0x0c, 0x5bf0 },
1589 { 0x1c, 0xf101 },
1590 { 0x1f, 0x0003 },
1591 { 0x14, 0x94d7 },
1592 { 0x12, 0xf4d6 },
1593 { 0x09, 0xca0f },
1594 { 0x1f, 0x0002 },
1595 { 0x0b, 0x0b10 },
1596 { 0x0c, 0xd1f7 },
1597 { 0x1f, 0x0002 },
1598 { 0x06, 0x5461 },
1599 { 0x1f, 0x0002 },
1600 { 0x05, 0x6662 },
1601 { 0x1f, 0x0000 },
1602 { 0x14, 0x0060 },
1603 { 0x1f, 0x0000 },
1604 { 0x0d, 0xf8a0 },
1605 { 0x1f, 0x0005 },
1606 { 0x05, 0xffc2 }
1607 };
1608
1609 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1610
1611 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1612 struct phy_reg phy_reg_init_1[] = {
1613 { 0x1f, 0x0005 },
1614 { 0x01, 0x0300 },
1615 { 0x1f, 0x0000 },
1616 { 0x11, 0x401c },
1617 { 0x16, 0x4100 },
1618 { 0x1f, 0x0005 },
1619 { 0x07, 0x0010 },
1620 { 0x05, 0x83dc },
1621 { 0x06, 0x087d },
1622 { 0x05, 0x8300 },
1623 { 0x06, 0x0101 },
1624 { 0x06, 0x05f8 },
1625 { 0x06, 0xf9fa },
1626 { 0x06, 0xfbef },
1627 { 0x06, 0x79e2 },
1628 { 0x06, 0x835f },
1629 { 0x06, 0xe0f8 },
1630 { 0x06, 0x9ae1 },
1631 { 0x06, 0xf89b },
1632 { 0x06, 0xef31 },
1633 { 0x06, 0x3b65 },
1634 { 0x06, 0xaa07 },
1635 { 0x06, 0x81e4 },
1636 { 0x06, 0xf89a },
1637 { 0x06, 0xe5f8 },
1638 { 0x06, 0x9baf },
1639 { 0x06, 0x06ae },
1640 { 0x05, 0x83dc },
1641 { 0x06, 0x8300 },
1642 };
1643
1644 rtl_phy_write(ioaddr, phy_reg_init_1,
1645 ARRAY_SIZE(phy_reg_init_1));
1646 }
1647
1648 mdio_write(ioaddr, 0x1f, 0x0000);
1649}
1650
2857ffb7
FR		 1651static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1652{
1653 struct phy_reg phy_reg_init[] = {
1654 { 0x1f, 0x0003 },
1655 { 0x08, 0x441d },
1656 { 0x01, 0x9100 },
1657 { 0x1f, 0x0000 }
1658 };
1659
1660 mdio_write(ioaddr, 0x1f, 0x0000);
1661 mdio_patch(ioaddr, 0x11, 1 << 12);
1662 mdio_patch(ioaddr, 0x19, 1 << 13);
1663
1664 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1665}
1666
5615d9f1
FR		 1667static void rtl_hw_phy_config(struct net_device *dev)
1668{
1669 struct rtl8169_private *tp = netdev_priv(dev);
1670 void __iomem *ioaddr = tp->mmio_addr;
1671
1672 rtl8169_print_mac_version(tp);
1673
1674 switch (tp->mac_version) {
1675 case RTL_GIGA_MAC_VER_01:
1676 break;
1677 case RTL_GIGA_MAC_VER_02:
1678 case RTL_GIGA_MAC_VER_03:
1679 rtl8169s_hw_phy_config(ioaddr);
1680 break;
1681 case RTL_GIGA_MAC_VER_04:
1682 rtl8169sb_hw_phy_config(ioaddr);
1683 break;
8c7006aa 1684 case RTL_GIGA_MAC_VER_06:
1685 rtl8169sce_hw_phy_config(ioaddr);
1686 break;
2857ffb7
FR		 1687 case RTL_GIGA_MAC_VER_07:
1688 case RTL_GIGA_MAC_VER_08:
1689 case RTL_GIGA_MAC_VER_09:
1690 rtl8102e_hw_phy_config(ioaddr);
1691 break;
236b8082
FR		 1692 case RTL_GIGA_MAC_VER_11:
1693 rtl8168bb_hw_phy_config(ioaddr);
1694 break;
1695 case RTL_GIGA_MAC_VER_12:
1696 rtl8168bef_hw_phy_config(ioaddr);
1697 break;
1698 case RTL_GIGA_MAC_VER_17:
1699 rtl8168bef_hw_phy_config(ioaddr);
1700 break;
867763c1 1701 case RTL_GIGA_MAC_VER_18:
ef3386f0 1702 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1703 break;
1704 case RTL_GIGA_MAC_VER_19:
219a1e9d 1705 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1706 break;
7da97ec9 1707 case RTL_GIGA_MAC_VER_20:
219a1e9d 1708 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1709 break;
197ff761
FR		 1710 case RTL_GIGA_MAC_VER_21:
1711 rtl8168c_3_hw_phy_config(ioaddr);
1712 break;
6fb07058
FR		 1713 case RTL_GIGA_MAC_VER_22:
1714 rtl8168c_4_hw_phy_config(ioaddr);
1715 break;
ef3386f0 1716 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 1717 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 1718 rtl8168cp_2_hw_phy_config(ioaddr);
1719 break;
5b538df9
FR		 1720 case RTL_GIGA_MAC_VER_25:
1721 rtl8168d_hw_phy_config(ioaddr);
1722 break;
ef3386f0 1723
5615d9f1
FR		 1724 default:
1725 break;
1726 }
1727}
1728
1da177e4
LT		 1729static void rtl8169_phy_timer(unsigned long __opaque)
1730{
1731 struct net_device *dev = (struct net_device *)__opaque;
1732 struct rtl8169_private *tp = netdev_priv(dev);
1733 struct timer_list *timer = &tp->timer;
1734 void __iomem *ioaddr = tp->mmio_addr;
1735 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1736
bcf0bf90 1737 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1738
64e4bfb4 1739 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1740 return;
1741
1742 spin_lock_irq(&tp->lock);
1743
1744 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1745 /*
1da177e4
LT		 1746 * A busy loop could burn quite a few cycles on nowadays CPU.
1747 * Let's delay the execution of the timer for a few ticks.
1748 */
1749 timeout = HZ/10;
1750 goto out_mod_timer;
1751 }
1752
1753 if (tp->link_ok(ioaddr))
1754 goto out_unlock;
1755
b57b7e5a
SH		 1756 if (netif_msg_link(tp))
1757 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1758
1759 tp->phy_reset_enable(ioaddr);
1760
1761out_mod_timer:
1762 mod_timer(timer, jiffies + timeout);
1763out_unlock:
1764 spin_unlock_irq(&tp->lock);
1765}
1766
1767static inline void rtl8169_delete_timer(struct net_device *dev)
1768{
1769 struct rtl8169_private *tp = netdev_priv(dev);
1770 struct timer_list *timer = &tp->timer;
1771
e179bb7b 1772 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1773 return;
1774
1775 del_timer_sync(timer);
1776}
1777
1778static inline void rtl8169_request_timer(struct net_device *dev)
1779{
1780 struct rtl8169_private *tp = netdev_priv(dev);
1781 struct timer_list *timer = &tp->timer;
1782
e179bb7b 1783 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1784 return;
1785
2efa53f3 1786 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1787}
1788
1789#ifdef CONFIG_NET_POLL_CONTROLLER
1790/*
1791 * Polling 'interrupt' - used by things like netconsole to send skbs
1792 * without having to re-enable interrupts. It's not called while
1793 * the interrupt routine is executing.
1794 */
1795static void rtl8169_netpoll(struct net_device *dev)
1796{
1797 struct rtl8169_private *tp = netdev_priv(dev);
1798 struct pci_dev *pdev = tp->pci_dev;
1799
1800 disable_irq(pdev->irq);
7d12e780 1801 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1802 enable_irq(pdev->irq);
1803}
1804#endif
1805
1806static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1807 void __iomem *ioaddr)
1808{
1809 iounmap(ioaddr);
1810 pci_release_regions(pdev);
1811 pci_disable_device(pdev);
1812 free_netdev(dev);
1813}
1814
bf793295
FR		 1815static void rtl8169_phy_reset(struct net_device *dev,
1816 struct rtl8169_private *tp)
1817{
1818 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1819 unsigned int i;
bf793295
FR		 1820
1821 tp->phy_reset_enable(ioaddr);
1822 for (i = 0; i < 100; i++) {
1823 if (!tp->phy_reset_pending(ioaddr))
1824 return;
1825 msleep(1);
1826 }
1827 if (netif_msg_link(tp))
1828 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1829}
1830
4ff96fa6
FR		 1831static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1832{
1833 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1834
5615d9f1 1835 rtl_hw_phy_config(dev);
4ff96fa6 1836
77332894
MS		 1837 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1838 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1839 RTL_W8(0x82, 0x01);
1840 }
4ff96fa6 1841
6dccd16b
FR		 1842 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1843
1844 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1845 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1846
bcf0bf90 1847 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1848 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1849 RTL_W8(0x82, 0x01);
1850 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1851 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1852 }
1853
bf793295
FR		 1854 rtl8169_phy_reset(dev, tp);
1855
901dda2b
FR		 1856 /*
1857 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1858 * only 8101. Don't panic.
1859 */
1860 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1861
1862 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1863 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1864}
1865
773d2021
FR		 1866static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1867{
1868 void __iomem *ioaddr = tp->mmio_addr;
1869 u32 high;
1870 u32 low;
1871
1872 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1873 high = addr[4] | (addr[5] << 8);
1874
1875 spin_lock_irq(&tp->lock);
1876
1877 RTL_W8(Cfg9346, Cfg9346_Unlock);
1878 RTL_W32(MAC0, low);
1879 RTL_W32(MAC4, high);
1880 RTL_W8(Cfg9346, Cfg9346_Lock);
1881
1882 spin_unlock_irq(&tp->lock);
1883}
1884
1885static int rtl_set_mac_address(struct net_device *dev, void *p)
1886{
1887 struct rtl8169_private *tp = netdev_priv(dev);
1888 struct sockaddr *addr = p;
1889
1890 if (!is_valid_ether_addr(addr->sa_data))
1891 return -EADDRNOTAVAIL;
1892
1893 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1894
1895 rtl_rar_set(tp, dev->dev_addr);
1896
1897 return 0;
1898}
1899
5f787a1a
FR		 1900static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1901{
1902 struct rtl8169_private *tp = netdev_priv(dev);
1903 struct mii_ioctl_data *data = if_mii(ifr);
1904
8b4ab28d
FR		 1905 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1906}
5f787a1a 1907
8b4ab28d
FR		 1908static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1909{
5f787a1a
FR		 1910 switch (cmd) {
1911 case SIOCGMIIPHY:
1912 data->phy_id = 32; /* Internal PHY */
1913 return 0;
1914
1915 case SIOCGMIIREG:
1916 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1917 return 0;
1918
1919 case SIOCSMIIREG:
1920 if (!capable(CAP_NET_ADMIN))
1921 return -EPERM;
1922 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1923 return 0;
1924 }
1925 return -EOPNOTSUPP;
1926}
1927
8b4ab28d
FR		 1928static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1929{
1930 return -EOPNOTSUPP;
1931}
1932
0e485150
FR		 1933static const struct rtl_cfg_info {
1934 void (*hw_start)(struct net_device *);
1935 unsigned int region;
1936 unsigned int align;
1937 u16 intr_event;
1938 u16 napi_event;
ccdffb9a 1939 unsigned features;
f21b75e9 1940 u8 default_ver;
0e485150
FR		 1941} rtl_cfg_infos [] = {
1942 [RTL_CFG_0] = {
1943 .hw_start = rtl_hw_start_8169,
1944 .region = 1,
e9f63f30 1945 .align = 0,
0e485150
FR		 1946 .intr_event = SYSErr | LinkChg | RxOverflow |
1947 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1948 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 1949 .features = RTL_FEATURE_GMII,
1950 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 1951 },
1952 [RTL_CFG_1] = {
1953 .hw_start = rtl_hw_start_8168,
1954 .region = 2,
1955 .align = 8,
1956 .intr_event = SYSErr | LinkChg | RxOverflow |
1957 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1958 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 1959 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
1960 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 1961 },
1962 [RTL_CFG_2] = {
1963 .hw_start = rtl_hw_start_8101,
1964 .region = 2,
1965 .align = 8,
1966 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1967 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1968 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 1969 .features = RTL_FEATURE_MSI,
1970 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 1971 }
1972};
1973
fbac58fc
FR		 1974/* Cfg9346_Unlock assumed. */
1975static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1976 const struct rtl_cfg_info *cfg)
1977{
1978 unsigned msi = 0;
1979 u8 cfg2;
1980
1981 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1982 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1983 if (pci_enable_msi(pdev)) {
1984 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1985 } else {
1986 cfg2 |= MSIEnable;
1987 msi = RTL_FEATURE_MSI;
1988 }
1989 }
1990 RTL_W8(Config2, cfg2);
1991 return msi;
1992}
1993
1994static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1995{
1996 if (tp->features & RTL_FEATURE_MSI) {
1997 pci_disable_msi(pdev);
1998 tp->features &= ~RTL_FEATURE_MSI;
1999 }
2000}
2001
8b4ab28d
FR		 2002static const struct net_device_ops rtl8169_netdev_ops = {
2003 .ndo_open = rtl8169_open,
2004 .ndo_stop = rtl8169_close,
2005 .ndo_get_stats = rtl8169_get_stats,
00829823 2006 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2007 .ndo_tx_timeout = rtl8169_tx_timeout,
2008 .ndo_validate_addr = eth_validate_addr,
2009 .ndo_change_mtu = rtl8169_change_mtu,
2010 .ndo_set_mac_address = rtl_set_mac_address,
2011 .ndo_do_ioctl = rtl8169_ioctl,
2012 .ndo_set_multicast_list = rtl_set_rx_mode,
2013#ifdef CONFIG_R8169_VLAN
2014 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2015#endif
2016#ifdef CONFIG_NET_POLL_CONTROLLER
2017 .ndo_poll_controller = rtl8169_netpoll,
2018#endif
2019
2020};
2021
1da177e4 2022static int __devinit
4ff96fa6 2023rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2024{
0e485150
FR		 2025 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2026 const unsigned int region = cfg->region;
1da177e4 2027 struct rtl8169_private *tp;
ccdffb9a 2028 struct mii_if_info *mii;
4ff96fa6
FR		 2029 struct net_device *dev;
2030 void __iomem *ioaddr;
07d3f51f
FR		 2031 unsigned int i;
2032 int rc;
1da177e4 2033
4ff96fa6
FR		 2034 if (netif_msg_drv(&debug)) {
2035 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2036 MODULENAME, RTL8169_VERSION);
2037 }
1da177e4 2038
1da177e4 2039 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2040 if (!dev) {
b57b7e5a 2041 if (netif_msg_drv(&debug))
9b91cf9d 2042 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2043 rc = -ENOMEM;
2044 goto out;
1da177e4
LT		 2045 }
2046
1da177e4 2047 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2048 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2049 tp = netdev_priv(dev);
c4028958 2050 tp->dev = dev;
21e197f2 2051 tp->pci_dev = pdev;
b57b7e5a 2052 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2053
ccdffb9a
FR		 2054 mii = &tp->mii;
2055 mii->dev = dev;
2056 mii->mdio_read = rtl_mdio_read;
2057 mii->mdio_write = rtl_mdio_write;
2058 mii->phy_id_mask = 0x1f;
2059 mii->reg_num_mask = 0x1f;
2060 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2061
1da177e4
LT		 2062 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2063 rc = pci_enable_device(pdev);
b57b7e5a 2064 if (rc < 0) {
2e8a538d 2065 if (netif_msg_probe(tp))
9b91cf9d 2066 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 2067 goto err_out_free_dev_1;
1da177e4
LT		 2068 }
2069
2070 rc = pci_set_mwi(pdev);
2071 if (rc < 0)
4ff96fa6 2072 goto err_out_disable_2;
1da177e4 2073
1da177e4 2074 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2075 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 2076 if (netif_msg_probe(tp)) {
9b91cf9d 2077 dev_err(&pdev->dev,
bcf0bf90
FR		 2078 "region #%d not an MMIO resource, aborting\n",
2079 region);
4ff96fa6 2080 }
1da177e4 2081 rc = -ENODEV;
4ff96fa6 2082 goto err_out_mwi_3;
1da177e4 2083 }
4ff96fa6 2084
1da177e4 2085 /* check for weird/broken PCI region reporting */
bcf0bf90 2086 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 2087 if (netif_msg_probe(tp)) {
9b91cf9d 2088 dev_err(&pdev->dev,
4ff96fa6
FR		 2089 "Invalid PCI region size(s), aborting\n");
2090 }
1da177e4 2091 rc = -ENODEV;
4ff96fa6 2092 goto err_out_mwi_3;
1da177e4
LT		 2093 }
2094
2095 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2096 if (rc < 0) {
2e8a538d 2097 if (netif_msg_probe(tp))
9b91cf9d 2098 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 2099 goto err_out_mwi_3;
1da177e4
LT		 2100 }
2101
2102 tp->cp_cmd = PCIMulRW | RxChkSum;
2103
2104 if ((sizeof(dma_addr_t) > 4) &&
6a35528a 2105 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2106 tp->cp_cmd |= PCIDAC;
2107 dev->features |= NETIF_F_HIGHDMA;
2108 } else {
284901a9 2109 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2110 if (rc < 0) {
4ff96fa6 2111 if (netif_msg_probe(tp)) {
9b91cf9d 2112 dev_err(&pdev->dev,
4ff96fa6
FR		 2113 "DMA configuration failed.\n");
2114 }
2115 goto err_out_free_res_4;
1da177e4
LT		 2116 }
2117 }
2118
1da177e4 2119 /* ioremap MMIO region */
bcf0bf90 2120 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2121 if (!ioaddr) {
b57b7e5a 2122 if (netif_msg_probe(tp))
9b91cf9d 2123 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2124 rc = -EIO;
4ff96fa6 2125 goto err_out_free_res_4;
1da177e4
LT		 2126 }
2127
9c14ceaf
FR		 2128 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2129 if (!tp->pcie_cap && netif_msg_probe(tp))
2130 dev_info(&pdev->dev, "no PCI Express capability\n");
2131
d78ad8cb 2132 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2133
2134 /* Soft reset the chip. */
2135 RTL_W8(ChipCmd, CmdReset);
2136
2137 /* Check that the chip has finished the reset. */
07d3f51f 2138 for (i = 0; i < 100; i++) {
1da177e4
LT		 2139 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2140 break;
b518fa8e 2141 msleep_interruptible(1);
1da177e4
LT		 2142 }
2143
d78ad8cb
KW		 2144 RTL_W16(IntrStatus, 0xffff);
2145
ca52efd5 2146 pci_set_master(pdev);
2147
1da177e4
LT		 2148 /* Identify chip attached to board */
2149 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 2150
f21b75e9
JD		 2151 /* Use appropriate default if unknown */
2152 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2153 if (netif_msg_probe(tp)) {
2154 dev_notice(&pdev->dev,
2155 "unknown MAC, using family default\n");
2156 }
2157 tp->mac_version = cfg->default_ver;
2158 }
2159
1da177e4 2160 rtl8169_print_mac_version(tp);
1da177e4 2161
cee60c37 2162 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2163 if (tp->mac_version == rtl_chip_info[i].mac_version)
2164 break;
2165 }
cee60c37 2166 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 2167 dev_err(&pdev->dev,
2168 "driver bug, MAC version not found in rtl_chip_info\n");
2169 goto err_out_msi_5;
1da177e4
LT		 2170 }
2171 tp->chipset = i;
2172
5d06a99f
FR		 2173 RTL_W8(Cfg9346, Cfg9346_Unlock);
2174 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2175 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2176 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2177 tp->features |= RTL_FEATURE_WOL;
2178 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2179 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2180 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2181 RTL_W8(Cfg9346, Cfg9346_Lock);
2182
66ec5d4f
FR		 2183 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2184 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2185 tp->set_speed = rtl8169_set_speed_tbi;
2186 tp->get_settings = rtl8169_gset_tbi;
2187 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2188 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2189 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2190 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2191
64e4bfb4 2192 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2193 } else {
2194 tp->set_speed = rtl8169_set_speed_xmii;
2195 tp->get_settings = rtl8169_gset_xmii;
2196 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2197 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2198 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2199 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2200 }
2201
df58ef51
FR		 2202 spin_lock_init(&tp->lock);
2203
738e1e69
PV		 2204 tp->mmio_addr = ioaddr;
2205
7bf6bf48 2206 /* Get MAC address */
1da177e4
LT		 2207 for (i = 0; i < MAC_ADDR_LEN; i++)
2208 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2209 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2210
1da177e4 2211 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2212 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2213 dev->irq = pdev->irq;
2214 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2215
bea3348e 2216 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2217
2218#ifdef CONFIG_R8169_VLAN
2219 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 2220#endif
2221
2222 tp->intr_mask = 0xffff;
0e485150
FR		 2223 tp->align = cfg->align;
2224 tp->hw_start = cfg->hw_start;
2225 tp->intr_event = cfg->intr_event;
2226 tp->napi_event = cfg->napi_event;
1da177e4 2227
2efa53f3
FR		 2228 init_timer(&tp->timer);
2229 tp->timer.data = (unsigned long) dev;
2230 tp->timer.function = rtl8169_phy_timer;
2231
1da177e4 2232 rc = register_netdev(dev);
4ff96fa6 2233 if (rc < 0)
fbac58fc 2234 goto err_out_msi_5;
1da177e4
LT		 2235
2236 pci_set_drvdata(pdev, dev);
2237
b57b7e5a 2238 if (netif_msg_probe(tp)) {
21d57363 2239 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
96b9709c 2240
b57b7e5a
SH		 2241 printk(KERN_INFO "%s: %s at 0x%lx, "
2242 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2243 "XID %08x IRQ %d\n",
b57b7e5a 2244 dev->name,
bcf0bf90 2245 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2246 dev->base_addr,
2247 dev->dev_addr[0], dev->dev_addr[1],
2248 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2249 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2250 }
1da177e4 2251
4ff96fa6 2252 rtl8169_init_phy(dev, tp);
8b76ab39 2253 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2254
4ff96fa6
FR		 2255out:
2256 return rc;
1da177e4 2257
fbac58fc
FR		 2258err_out_msi_5:
2259 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2260 iounmap(ioaddr);
2261err_out_free_res_4:
2262 pci_release_regions(pdev);
2263err_out_mwi_3:
2264 pci_clear_mwi(pdev);
2265err_out_disable_2:
2266 pci_disable_device(pdev);
2267err_out_free_dev_1:
2268 free_netdev(dev);
2269 goto out;
1da177e4
LT		 2270}
2271
07d3f51f 2272static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2273{
2274 struct net_device *dev = pci_get_drvdata(pdev);
2275 struct rtl8169_private *tp = netdev_priv(dev);
2276
eb2a021c
FR		 2277 flush_scheduled_work();
2278
1da177e4 2279 unregister_netdev(dev);
fbac58fc 2280 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2281 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2282 pci_set_drvdata(pdev, NULL);
2283}
2284
1da177e4
LT		 2285static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2286 struct net_device *dev)
2287{
2288 unsigned int mtu = dev->mtu;
2289
2290 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2291}
2292
2293static int rtl8169_open(struct net_device *dev)
2294{
2295 struct rtl8169_private *tp = netdev_priv(dev);
2296 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2297 int retval = -ENOMEM;
1da177e4 2298
1da177e4 2299
99f252b0 2300 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2301
2302 /*
2303 * Rx and Tx desscriptors needs 256 bytes alignment.
2304 * pci_alloc_consistent provides more.
2305 */
2306 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2307 &tp->TxPhyAddr);
2308 if (!tp->TxDescArray)
99f252b0 2309 goto out;
1da177e4
LT		 2310
2311 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2312 &tp->RxPhyAddr);
2313 if (!tp->RxDescArray)
99f252b0 2314 goto err_free_tx_0;
1da177e4
LT		 2315
2316 retval = rtl8169_init_ring(dev);
2317 if (retval < 0)
99f252b0 2318 goto err_free_rx_1;
1da177e4 2319
c4028958 2320 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2321
99f252b0
FR		 2322 smp_mb();
2323
fbac58fc
FR		 2324 retval = request_irq(dev->irq, rtl8169_interrupt,
2325 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2326 dev->name, dev);
2327 if (retval < 0)
2328 goto err_release_ring_2;
2329
bea3348e 2330 napi_enable(&tp->napi);
bea3348e 2331
07ce4064 2332 rtl_hw_start(dev);
1da177e4
LT		 2333
2334 rtl8169_request_timer(dev);
2335
2336 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2337out:
2338 return retval;
2339
99f252b0
FR		 2340err_release_ring_2:
2341 rtl8169_rx_clear(tp);
2342err_free_rx_1:
1da177e4
LT		 2343 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2344 tp->RxPhyAddr);
99f252b0 2345err_free_tx_0:
1da177e4
LT		 2346 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2347 tp->TxPhyAddr);
1da177e4
LT		 2348 goto out;
2349}
2350
2351static void rtl8169_hw_reset(void __iomem *ioaddr)
2352{
2353 /* Disable interrupts */
2354 rtl8169_irq_mask_and_ack(ioaddr);
2355
2356 /* Reset the chipset */
2357 RTL_W8(ChipCmd, CmdReset);
2358
2359 /* PCI commit */
2360 RTL_R8(ChipCmd);
2361}
2362
7f796d83 2363static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2364{
2365 void __iomem *ioaddr = tp->mmio_addr;
2366 u32 cfg = rtl8169_rx_config;
2367
2368 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2369 RTL_W32(RxConfig, cfg);
2370
2371 /* Set DMA burst size and Interframe Gap Time */
2372 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2373 (InterFrameGap << TxInterFrameGapShift));
2374}
2375
07ce4064 2376static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2377{
2378 struct rtl8169_private *tp = netdev_priv(dev);
2379 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2380 unsigned int i;
1da177e4
LT		 2381
2382 /* Soft reset the chip. */
2383 RTL_W8(ChipCmd, CmdReset);
2384
2385 /* Check that the chip has finished the reset. */
07d3f51f 2386 for (i = 0; i < 100; i++) {
1da177e4
LT		 2387 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2388 break;
b518fa8e 2389 msleep_interruptible(1);
1da177e4
LT		 2390 }
2391
07ce4064
FR		 2392 tp->hw_start(dev);
2393
07ce4064
FR		 2394 netif_start_queue(dev);
2395}
2396
2397
7f796d83
FR		 2398static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2399 void __iomem *ioaddr)
2400{
2401 /*
2402 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2403 * register to be written before TxDescAddrLow to work.
2404 * Switching from MMIO to I/O access fixes the issue as well.
2405 */
2406 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 2407 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 2408 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 2409 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2410}
2411
2412static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2413{
2414 u16 cmd;
2415
2416 cmd = RTL_R16(CPlusCmd);
2417 RTL_W16(CPlusCmd, cmd);
2418 return cmd;
2419}
2420
fdd7b4c3 2421static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 2422{
2423 /* Low hurts. Let's disable the filtering. */
fdd7b4c3 2424 RTL_W16(RxMaxSize, rx_buf_sz);
7f796d83
FR		 2425}
2426
6dccd16b
FR		 2427static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2428{
2429 struct {
2430 u32 mac_version;
2431 u32 clk;
2432 u32 val;
2433 } cfg2_info [] = {
2434 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2435 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2436 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2437 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2438 }, *p = cfg2_info;
2439 unsigned int i;
2440 u32 clk;
2441
2442 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2443 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2444 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2445 RTL_W32(0x7c, p->val);
2446 break;
2447 }
2448 }
2449}
2450
07ce4064
FR		 2451static void rtl_hw_start_8169(struct net_device *dev)
2452{
2453 struct rtl8169_private *tp = netdev_priv(dev);
2454 void __iomem *ioaddr = tp->mmio_addr;
2455 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2456
9cb427b6
FR		 2457 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2458 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2459 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2460 }
2461
1da177e4 2462 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2463 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2464 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2465 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2466 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2467 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2468
1da177e4
LT		 2469 RTL_W8(EarlyTxThres, EarlyTxThld);
2470
fdd7b4c3 2471 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 2472
c946b304
FR		 2473 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2474 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2475 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2476 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2477 rtl_set_rx_tx_config_registers(tp);
1da177e4 2478
7f796d83 2479 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2480
bcf0bf90
FR		 2481 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2482 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2483 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2484 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2485 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2486 }
2487
bcf0bf90
FR		 2488 RTL_W16(CPlusCmd, tp->cp_cmd);
2489
6dccd16b
FR		 2490 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2491
1da177e4
LT		 2492 /*
2493 * Undocumented corner. Supposedly:
2494 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2495 */
2496 RTL_W16(IntrMitigate, 0x0000);
2497
7f796d83 2498 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2499
c946b304
FR		 2500 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2501 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2502 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2503 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2504 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2505 rtl_set_rx_tx_config_registers(tp);
2506 }
2507
1da177e4 2508 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2509
2510 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2511 RTL_R8(IntrMask);
1da177e4
LT		 2512
2513 RTL_W32(RxMissed, 0);
2514
07ce4064 2515 rtl_set_rx_mode(dev);
1da177e4
LT		 2516
2517 /* no early-rx interrupts */
2518 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2519
2520 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2521 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2522}
1da177e4 2523
9c14ceaf 2524static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2525{
9c14ceaf
FR		 2526 struct net_device *dev = pci_get_drvdata(pdev);
2527 struct rtl8169_private *tp = netdev_priv(dev);
2528 int cap = tp->pcie_cap;
2529
2530 if (cap) {
2531 u16 ctl;
458a9f61 2532
9c14ceaf
FR		 2533 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2534 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2535 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2536 }
458a9f61
FR		 2537}
2538
dacf8154
FR		 2539static void rtl_csi_access_enable(void __iomem *ioaddr)
2540{
2541 u32 csi;
2542
2543 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2544 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2545}
2546
2547struct ephy_info {
2548 unsigned int offset;
2549 u16 mask;
2550 u16 bits;
2551};
2552
2553static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2554{
2555 u16 w;
2556
2557 while (len-- > 0) {
2558 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2559 rtl_ephy_write(ioaddr, e->offset, w);
2560 e++;
2561 }
2562}
2563
b726e493
FR		 2564static void rtl_disable_clock_request(struct pci_dev *pdev)
2565{
2566 struct net_device *dev = pci_get_drvdata(pdev);
2567 struct rtl8169_private *tp = netdev_priv(dev);
2568 int cap = tp->pcie_cap;
2569
2570 if (cap) {
2571 u16 ctl;
2572
2573 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2574 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2575 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2576 }
2577}
2578
2579#define R8168_CPCMD_QUIRK_MASK (\
2580 EnableBist | \
2581 Mac_dbgo_oe | \
2582 Force_half_dup | \
2583 Force_rxflow_en | \
2584 Force_txflow_en | \
2585 Cxpl_dbg_sel | \
2586 ASF | \
2587 PktCntrDisable | \
2588 Mac_dbgo_sel)
2589
219a1e9d
FR		 2590static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2591{
b726e493
FR		 2592 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2593
2594 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2595
2e68ae44
FR		 2596 rtl_tx_performance_tweak(pdev,
2597 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2598}
2599
2600static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2601{
2602 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2603
2604 RTL_W8(EarlyTxThres, EarlyTxThld);
2605
2606 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2607}
2608
2609static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2610{
b726e493
FR		 2611 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2612
2613 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2614
219a1e9d 2615 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2616
2617 rtl_disable_clock_request(pdev);
2618
2619 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2620}
2621
ef3386f0 2622static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2623{
b726e493
FR		 2624 static struct ephy_info e_info_8168cp[] = {
2625 { 0x01, 0, 0x0001 },
2626 { 0x02, 0x0800, 0x1000 },
2627 { 0x03, 0, 0x0042 },
2628 { 0x06, 0x0080, 0x0000 },
2629 { 0x07, 0, 0x2000 }
2630 };
2631
2632 rtl_csi_access_enable(ioaddr);
2633
2634 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2635
219a1e9d
FR		 2636 __rtl_hw_start_8168cp(ioaddr, pdev);
2637}
2638
ef3386f0
FR		 2639static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2640{
2641 rtl_csi_access_enable(ioaddr);
2642
2643 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2644
2645 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2646
2647 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2648}
2649
7f3e3d3a
FR		 2650static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2651{
2652 rtl_csi_access_enable(ioaddr);
2653
2654 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2655
2656 /* Magic. */
2657 RTL_W8(DBG_REG, 0x20);
2658
2659 RTL_W8(EarlyTxThres, EarlyTxThld);
2660
2661 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2662
2663 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2664}
2665
219a1e9d
FR		 2666static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2667{
b726e493
FR		 2668 static struct ephy_info e_info_8168c_1[] = {
2669 { 0x02, 0x0800, 0x1000 },
2670 { 0x03, 0, 0x0002 },
2671 { 0x06, 0x0080, 0x0000 }
2672 };
2673
2674 rtl_csi_access_enable(ioaddr);
2675
2676 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2677
2678 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2679
219a1e9d
FR		 2680 __rtl_hw_start_8168cp(ioaddr, pdev);
2681}
2682
2683static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2684{
b726e493
FR		 2685 static struct ephy_info e_info_8168c_2[] = {
2686 { 0x01, 0, 0x0001 },
2687 { 0x03, 0x0400, 0x0220 }
2688 };
2689
2690 rtl_csi_access_enable(ioaddr);
2691
2692 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2693
219a1e9d
FR		 2694 __rtl_hw_start_8168cp(ioaddr, pdev);
2695}
2696
197ff761
FR		 2697static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2698{
2699 rtl_hw_start_8168c_2(ioaddr, pdev);
2700}
2701
6fb07058
FR		 2702static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2703{
2704 rtl_csi_access_enable(ioaddr);
2705
2706 __rtl_hw_start_8168cp(ioaddr, pdev);
2707}
2708
5b538df9
FR		 2709static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2710{
2711 rtl_csi_access_enable(ioaddr);
2712
2713 rtl_disable_clock_request(pdev);
2714
2715 RTL_W8(EarlyTxThres, EarlyTxThld);
2716
2717 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2718
2719 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2720}
2721
07ce4064
FR		 2722static void rtl_hw_start_8168(struct net_device *dev)
2723{
2dd99530
FR		 2724 struct rtl8169_private *tp = netdev_priv(dev);
2725 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2726 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2727
2728 RTL_W8(Cfg9346, Cfg9346_Unlock);
2729
2730 RTL_W8(EarlyTxThres, EarlyTxThld);
2731
fdd7b4c3 2732 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 2733
0e485150 2734 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2735
2736 RTL_W16(CPlusCmd, tp->cp_cmd);
2737
0e485150 2738 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2739
0e485150
FR		 2740 /* Work around for RxFIFO overflow. */
2741 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2742 tp->intr_event |= RxFIFOOver | PCSTimeout;
2743 tp->intr_event &= ~RxOverflow;
2744 }
2745
2746 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2747
b8363901
FR		 2748 rtl_set_rx_mode(dev);
2749
2750 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2751 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2752
2753 RTL_R8(IntrMask);
2754
219a1e9d
FR		 2755 switch (tp->mac_version) {
2756 case RTL_GIGA_MAC_VER_11:
2757 rtl_hw_start_8168bb(ioaddr, pdev);
2758 break;
2759
2760 case RTL_GIGA_MAC_VER_12:
2761 case RTL_GIGA_MAC_VER_17:
2762 rtl_hw_start_8168bef(ioaddr, pdev);
2763 break;
2764
2765 case RTL_GIGA_MAC_VER_18:
ef3386f0 2766 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2767 break;
2768
2769 case RTL_GIGA_MAC_VER_19:
2770 rtl_hw_start_8168c_1(ioaddr, pdev);
2771 break;
2772
2773 case RTL_GIGA_MAC_VER_20:
2774 rtl_hw_start_8168c_2(ioaddr, pdev);
2775 break;
2776
197ff761
FR		 2777 case RTL_GIGA_MAC_VER_21:
2778 rtl_hw_start_8168c_3(ioaddr, pdev);
2779 break;
2780
6fb07058
FR		 2781 case RTL_GIGA_MAC_VER_22:
2782 rtl_hw_start_8168c_4(ioaddr, pdev);
2783 break;
2784
ef3386f0
FR		 2785 case RTL_GIGA_MAC_VER_23:
2786 rtl_hw_start_8168cp_2(ioaddr, pdev);
2787 break;
2788
7f3e3d3a
FR		 2789 case RTL_GIGA_MAC_VER_24:
2790 rtl_hw_start_8168cp_3(ioaddr, pdev);
2791 break;
2792
5b538df9
FR		 2793 case RTL_GIGA_MAC_VER_25:
2794 rtl_hw_start_8168d(ioaddr, pdev);
2795 break;
2796
219a1e9d
FR		 2797 default:
2798 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2799 dev->name, tp->mac_version);
2800 break;
2801 }
2dd99530 2802
0e485150
FR		 2803 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2804
b8363901
FR		 2805 RTL_W8(Cfg9346, Cfg9346_Lock);
2806
2dd99530 2807 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2808
0e485150 2809 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2810}
1da177e4 2811
2857ffb7
FR		 2812#define R810X_CPCMD_QUIRK_MASK (\
2813 EnableBist | \
2814 Mac_dbgo_oe | \
2815 Force_half_dup | \
5edcc537 2816 Force_rxflow_en | \
2857ffb7
FR		 2817 Force_txflow_en | \
2818 Cxpl_dbg_sel | \
2819 ASF | \
2820 PktCntrDisable | \
2821 PCIDAC | \
2822 PCIMulRW)
2823
2824static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2825{
2826 static struct ephy_info e_info_8102e_1[] = {
2827 { 0x01, 0, 0x6e65 },
2828 { 0x02, 0, 0x091f },
2829 { 0x03, 0, 0xc2f9 },
2830 { 0x06, 0, 0xafb5 },
2831 { 0x07, 0, 0x0e00 },
2832 { 0x19, 0, 0xec80 },
2833 { 0x01, 0, 0x2e65 },
2834 { 0x01, 0, 0x6e65 }
2835 };
2836 u8 cfg1;
2837
2838 rtl_csi_access_enable(ioaddr);
2839
2840 RTL_W8(DBG_REG, FIX_NAK_1);
2841
2842 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2843
2844 RTL_W8(Config1,
2845 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2846 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2847
2848 cfg1 = RTL_R8(Config1);
2849 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2850 RTL_W8(Config1, cfg1 & ~LEDS0);
2851
2852 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2853
2854 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2855}
2856
2857static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2858{
2859 rtl_csi_access_enable(ioaddr);
2860
2861 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2862
2863 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2864 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2865
2866 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2867}
2868
2869static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2870{
2871 rtl_hw_start_8102e_2(ioaddr, pdev);
2872
2873 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2874}
2875
07ce4064
FR		 2876static void rtl_hw_start_8101(struct net_device *dev)
2877{
cdf1a608
FR		 2878 struct rtl8169_private *tp = netdev_priv(dev);
2879 void __iomem *ioaddr = tp->mmio_addr;
2880 struct pci_dev *pdev = tp->pci_dev;
2881
e3cf0cc0
FR		 2882 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2883 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2884 int cap = tp->pcie_cap;
2885
2886 if (cap) {
2887 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2888 PCI_EXP_DEVCTL_NOSNOOP_EN);
2889 }
cdf1a608
FR		 2890 }
2891
2857ffb7
FR		 2892 switch (tp->mac_version) {
2893 case RTL_GIGA_MAC_VER_07:
2894 rtl_hw_start_8102e_1(ioaddr, pdev);
2895 break;
2896
2897 case RTL_GIGA_MAC_VER_08:
2898 rtl_hw_start_8102e_3(ioaddr, pdev);
2899 break;
2900
2901 case RTL_GIGA_MAC_VER_09:
2902 rtl_hw_start_8102e_2(ioaddr, pdev);
2903 break;
cdf1a608
FR		 2904 }
2905
2906 RTL_W8(Cfg9346, Cfg9346_Unlock);
2907
2908 RTL_W8(EarlyTxThres, EarlyTxThld);
2909
fdd7b4c3 2910 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 2911
2912 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2913
2914 RTL_W16(CPlusCmd, tp->cp_cmd);
2915
2916 RTL_W16(IntrMitigate, 0x0000);
2917
2918 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2919
2920 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2921 rtl_set_rx_tx_config_registers(tp);
2922
2923 RTL_W8(Cfg9346, Cfg9346_Lock);
2924
2925 RTL_R8(IntrMask);
2926
cdf1a608
FR		 2927 rtl_set_rx_mode(dev);
2928
0e485150
FR		 2929 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2930
cdf1a608 2931 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2932
0e485150 2933 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2934}
2935
2936static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2937{
2938 struct rtl8169_private *tp = netdev_priv(dev);
2939 int ret = 0;
2940
2941 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2942 return -EINVAL;
2943
2944 dev->mtu = new_mtu;
2945
2946 if (!netif_running(dev))
2947 goto out;
2948
2949 rtl8169_down(dev);
2950
2951 rtl8169_set_rxbufsize(tp, dev);
2952
2953 ret = rtl8169_init_ring(dev);
2954 if (ret < 0)
2955 goto out;
2956
bea3348e 2957 napi_enable(&tp->napi);
1da177e4 2958
07ce4064 2959 rtl_hw_start(dev);
1da177e4
LT		 2960
2961 rtl8169_request_timer(dev);
2962
2963out:
2964 return ret;
2965}
2966
2967static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2968{
95e0918d 2969 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2970 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2971}
2972
2973static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2974 struct sk_buff **sk_buff, struct RxDesc *desc)
2975{
2976 struct pci_dev *pdev = tp->pci_dev;
2977
2978 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2979 PCI_DMA_FROMDEVICE);
2980 dev_kfree_skb(*sk_buff);
2981 *sk_buff = NULL;
2982 rtl8169_make_unusable_by_asic(desc);
2983}
2984
2985static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2986{
2987 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2988
2989 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2990}
2991
2992static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2993 u32 rx_buf_sz)
2994{
2995 desc->addr = cpu_to_le64(mapping);
2996 wmb();
2997 rtl8169_mark_to_asic(desc, rx_buf_sz);
2998}
2999
15d31758
SH		 3000static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3001 struct net_device *dev,
3002 struct RxDesc *desc, int rx_buf_sz,
3003 unsigned int align)
1da177e4
LT		 3004{
3005 struct sk_buff *skb;
3006 dma_addr_t mapping;
e9f63f30 3007 unsigned int pad;
1da177e4 3008
e9f63f30
FR		 3009 pad = align ? align : NET_IP_ALIGN;
3010
3011 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3012 if (!skb)
3013 goto err_out;
3014
e9f63f30 3015 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3016
689be439 3017 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3018 PCI_DMA_FROMDEVICE);
3019
3020 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3021out:
15d31758 3022 return skb;
1da177e4
LT		 3023
3024err_out:
1da177e4
LT		 3025 rtl8169_make_unusable_by_asic(desc);
3026 goto out;
3027}
3028
3029static void rtl8169_rx_clear(struct rtl8169_private *tp)
3030{
07d3f51f 3031 unsigned int i;
1da177e4
LT		 3032
3033 for (i = 0; i < NUM_RX_DESC; i++) {
3034 if (tp->Rx_skbuff[i]) {
3035 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3036 tp->RxDescArray + i);
3037 }
3038 }
3039}
3040
3041static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3042 u32 start, u32 end)
3043{
3044 u32 cur;
5b0384f4 3045
4ae47c2d 3046 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 3047 struct sk_buff *skb;
3048 unsigned int i = cur % NUM_RX_DESC;
1da177e4 3049
4ae47c2d
FR		 3050 WARN_ON((s32)(end - cur) < 0);
3051
1da177e4
LT		 3052 if (tp->Rx_skbuff[i])
3053 continue;
bcf0bf90 3054
15d31758
SH		 3055 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3056 tp->RxDescArray + i,
3057 tp->rx_buf_sz, tp->align);
3058 if (!skb)
1da177e4 3059 break;
15d31758
SH		 3060
3061 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 3062 }
3063 return cur - start;
3064}
3065
3066static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3067{
3068 desc->opts1 |= cpu_to_le32(RingEnd);
3069}
3070
3071static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3072{
3073 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3074}
3075
3076static int rtl8169_init_ring(struct net_device *dev)
3077{
3078 struct rtl8169_private *tp = netdev_priv(dev);
3079
3080 rtl8169_init_ring_indexes(tp);
3081
3082 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3083 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3084
3085 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3086 goto err_out;
3087
3088 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3089
3090 return 0;
3091
3092err_out:
3093 rtl8169_rx_clear(tp);
3094 return -ENOMEM;
3095}
3096
3097static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3098 struct TxDesc *desc)
3099{
3100 unsigned int len = tx_skb->len;
3101
3102 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3103 desc->opts1 = 0x00;
3104 desc->opts2 = 0x00;
3105 desc->addr = 0x00;
3106 tx_skb->len = 0;
3107}
3108
3109static void rtl8169_tx_clear(struct rtl8169_private *tp)
3110{
3111 unsigned int i;
3112
3113 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3114 unsigned int entry = i % NUM_TX_DESC;
3115 struct ring_info *tx_skb = tp->tx_skb + entry;
3116 unsigned int len = tx_skb->len;
3117
3118 if (len) {
3119 struct sk_buff *skb = tx_skb->skb;
3120
3121 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3122 tp->TxDescArray + entry);
3123 if (skb) {
3124 dev_kfree_skb(skb);
3125 tx_skb->skb = NULL;
3126 }
cebf8cc7 3127 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3128 }
3129 }
3130 tp->cur_tx = tp->dirty_tx = 0;
3131}
3132
c4028958 3133static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3134{
3135 struct rtl8169_private *tp = netdev_priv(dev);
3136
c4028958 3137 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3138 schedule_delayed_work(&tp->task, 4);
3139}
3140
3141static void rtl8169_wait_for_quiescence(struct net_device *dev)
3142{
3143 struct rtl8169_private *tp = netdev_priv(dev);
3144 void __iomem *ioaddr = tp->mmio_addr;
3145
3146 synchronize_irq(dev->irq);
3147
3148 /* Wait for any pending NAPI task to complete */
bea3348e 3149 napi_disable(&tp->napi);
1da177e4
LT		 3150
3151 rtl8169_irq_mask_and_ack(ioaddr);
3152
d1d08d12
DM		 3153 tp->intr_mask = 0xffff;
3154 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3155 napi_enable(&tp->napi);
1da177e4
LT		 3156}
3157
c4028958 3158static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3159{
c4028958
DH		 3160 struct rtl8169_private *tp =
3161 container_of(work, struct rtl8169_private, task.work);
3162 struct net_device *dev = tp->dev;
1da177e4
LT		 3163 int ret;
3164
eb2a021c
FR		 3165 rtnl_lock();
3166
3167 if (!netif_running(dev))
3168 goto out_unlock;
3169
3170 rtl8169_wait_for_quiescence(dev);
3171 rtl8169_close(dev);
1da177e4
LT		 3172
3173 ret = rtl8169_open(dev);
3174 if (unlikely(ret < 0)) {
07d3f51f 3175 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3176 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3177 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3178 }
3179 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3180 }
eb2a021c
FR		 3181
3182out_unlock:
3183 rtnl_unlock();
1da177e4
LT		 3184}
3185
c4028958 3186static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3187{
c4028958
DH		 3188 struct rtl8169_private *tp =
3189 container_of(work, struct rtl8169_private, task.work);
3190 struct net_device *dev = tp->dev;
1da177e4 3191
eb2a021c
FR		 3192 rtnl_lock();
3193
1da177e4 3194 if (!netif_running(dev))
eb2a021c 3195 goto out_unlock;
1da177e4
LT		 3196
3197 rtl8169_wait_for_quiescence(dev);
3198
bea3348e 3199 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3200 rtl8169_tx_clear(tp);
3201
3202 if (tp->dirty_rx == tp->cur_rx) {
3203 rtl8169_init_ring_indexes(tp);
07ce4064 3204 rtl_hw_start(dev);
1da177e4 3205 netif_wake_queue(dev);
cebf8cc7 3206 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3207 } else {
07d3f51f 3208 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3209 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3210 dev->name);
1da177e4
LT		 3211 }
3212 rtl8169_schedule_work(dev, rtl8169_reset_task);
3213 }
eb2a021c
FR		 3214
3215out_unlock:
3216 rtnl_unlock();
1da177e4
LT		 3217}
3218
3219static void rtl8169_tx_timeout(struct net_device *dev)
3220{
3221 struct rtl8169_private *tp = netdev_priv(dev);
3222
3223 rtl8169_hw_reset(tp->mmio_addr);
3224
3225 /* Let's wait a bit while any (async) irq lands on */
3226 rtl8169_schedule_work(dev, rtl8169_reset_task);
3227}
3228
3229static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3230 u32 opts1)
3231{
3232 struct skb_shared_info *info = skb_shinfo(skb);
3233 unsigned int cur_frag, entry;
a6343afb 3234 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3235
3236 entry = tp->cur_tx;
3237 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3238 skb_frag_t *frag = info->frags + cur_frag;
3239 dma_addr_t mapping;
3240 u32 status, len;
3241 void *addr;
3242
3243 entry = (entry + 1) % NUM_TX_DESC;
3244
3245 txd = tp->TxDescArray + entry;
3246 len = frag->size;
3247 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3248 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3249
3250 /* anti gcc 2.95.3 bugware (sic) */
3251 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3252
3253 txd->opts1 = cpu_to_le32(status);
3254 txd->addr = cpu_to_le64(mapping);
3255
3256 tp->tx_skb[entry].len = len;
3257 }
3258
3259 if (cur_frag) {
3260 tp->tx_skb[entry].skb = skb;
3261 txd->opts1 |= cpu_to_le32(LastFrag);
3262 }
3263
3264 return cur_frag;
3265}
3266
3267static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3268{
3269 if (dev->features & NETIF_F_TSO) {
7967168c 3270 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3271
3272 if (mss)
3273 return LargeSend | ((mss & MSSMask) << MSSShift);
3274 }
84fa7933 3275 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3276 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3277
3278 if (ip->protocol == IPPROTO_TCP)
3279 return IPCS | TCPCS;
3280 else if (ip->protocol == IPPROTO_UDP)
3281 return IPCS | UDPCS;
3282 WARN_ON(1); /* we need a WARN() */
3283 }
3284 return 0;
3285}
3286
3287static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3288{
3289 struct rtl8169_private *tp = netdev_priv(dev);
3290 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3291 struct TxDesc *txd = tp->TxDescArray + entry;
3292 void __iomem *ioaddr = tp->mmio_addr;
3293 dma_addr_t mapping;
3294 u32 status, len;
3295 u32 opts1;
188f4af0 3296 int ret = NETDEV_TX_OK;
5b0384f4 3297
1da177e4 3298 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3299 if (netif_msg_drv(tp)) {
3300 printk(KERN_ERR
3301 "%s: BUG! Tx Ring full when queue awake!\n",
3302 dev->name);
3303 }
1da177e4
LT		 3304 goto err_stop;
3305 }
3306
3307 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3308 goto err_stop;
3309
3310 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3311
3312 frags = rtl8169_xmit_frags(tp, skb, opts1);
3313 if (frags) {
3314 len = skb_headlen(skb);
3315 opts1 |= FirstFrag;
3316 } else {
3317 len = skb->len;
1da177e4
LT		 3318 opts1 |= FirstFrag | LastFrag;
3319 tp->tx_skb[entry].skb = skb;
3320 }
3321
3322 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3323
3324 tp->tx_skb[entry].len = len;
3325 txd->addr = cpu_to_le64(mapping);
3326 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3327
3328 wmb();
3329
3330 /* anti gcc 2.95.3 bugware (sic) */
3331 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3332 txd->opts1 = cpu_to_le32(status);
3333
1da177e4
LT		 3334 tp->cur_tx += frags + 1;
3335
3336 smp_wmb();
3337
275391a4 3338 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3339
3340 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3341 netif_stop_queue(dev);
3342 smp_rmb();
3343 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3344 netif_wake_queue(dev);
3345 }
3346
3347out:
3348 return ret;
3349
3350err_stop:
3351 netif_stop_queue(dev);
188f4af0 3352 ret = NETDEV_TX_BUSY;
cebf8cc7 3353 dev->stats.tx_dropped++;
1da177e4
LT		 3354 goto out;
3355}
3356
3357static void rtl8169_pcierr_interrupt(struct net_device *dev)
3358{
3359 struct rtl8169_private *tp = netdev_priv(dev);
3360 struct pci_dev *pdev = tp->pci_dev;
3361 void __iomem *ioaddr = tp->mmio_addr;
3362 u16 pci_status, pci_cmd;
3363
3364 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3365 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3366
b57b7e5a
SH		 3367 if (netif_msg_intr(tp)) {
3368 printk(KERN_ERR
3369 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3370 dev->name, pci_cmd, pci_status);
3371 }
1da177e4
LT		 3372
3373 /*
3374 * The recovery sequence below admits a very elaborated explanation:
3375 * - it seems to work;
d03902b8
FR		 3376 * - I did not see what else could be done;
3377 * - it makes iop3xx happy.
1da177e4
LT		 3378 *
3379 * Feel free to adjust to your needs.
3380 */
a27993f3 3381 if (pdev->broken_parity_status)
d03902b8
FR		 3382 pci_cmd &= ~PCI_COMMAND_PARITY;
3383 else
3384 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3385
3386 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3387
3388 pci_write_config_word(pdev, PCI_STATUS,
3389 pci_status & (PCI_STATUS_DETECTED_PARITY |
3390 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3391 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3392
3393 /* The infamous DAC f*ckup only happens at boot time */
3394 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3395 if (netif_msg_intr(tp))
3396 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3397 tp->cp_cmd &= ~PCIDAC;
3398 RTL_W16(CPlusCmd, tp->cp_cmd);
3399 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3400 }
3401
3402 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3403
3404 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3405}
3406
07d3f51f
FR		 3407static void rtl8169_tx_interrupt(struct net_device *dev,
3408 struct rtl8169_private *tp,
3409 void __iomem *ioaddr)
1da177e4
LT		 3410{
3411 unsigned int dirty_tx, tx_left;
3412
1da177e4
LT		 3413 dirty_tx = tp->dirty_tx;
3414 smp_rmb();
3415 tx_left = tp->cur_tx - dirty_tx;
3416
3417 while (tx_left > 0) {
3418 unsigned int entry = dirty_tx % NUM_TX_DESC;
3419 struct ring_info *tx_skb = tp->tx_skb + entry;
3420 u32 len = tx_skb->len;
3421 u32 status;
3422
3423 rmb();
3424 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3425 if (status & DescOwn)
3426 break;
3427
cebf8cc7
FR		 3428 dev->stats.tx_bytes += len;
3429 dev->stats.tx_packets++;
1da177e4
LT		 3430
3431 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3432
3433 if (status & LastFrag) {
87433bfc 3434 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 3435 tx_skb->skb = NULL;
3436 }
3437 dirty_tx++;
3438 tx_left--;
3439 }
3440
3441 if (tp->dirty_tx != dirty_tx) {
3442 tp->dirty_tx = dirty_tx;
3443 smp_wmb();
3444 if (netif_queue_stopped(dev) &&
3445 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3446 netif_wake_queue(dev);
3447 }
d78ae2dc
FR		 3448 /*
3449 * 8168 hack: TxPoll requests are lost when the Tx packets are
3450 * too close. Let's kick an extra TxPoll request when a burst
3451 * of start_xmit activity is detected (if it is not detected,
3452 * it is slow enough). -- FR
3453 */
3454 smp_rmb();
3455 if (tp->cur_tx != dirty_tx)
3456 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3457 }
3458}
3459
126fa4b9
FR		 3460static inline int rtl8169_fragmented_frame(u32 status)
3461{
3462 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3463}
3464
1da177e4
LT		 3465static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3466{
3467 u32 opts1 = le32_to_cpu(desc->opts1);
3468 u32 status = opts1 & RxProtoMask;
3469
3470 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3471 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3472 ((status == RxProtoIP) && !(opts1 & IPFail)))
3473 skb->ip_summed = CHECKSUM_UNNECESSARY;
3474 else
3475 skb->ip_summed = CHECKSUM_NONE;
3476}
3477
07d3f51f
FR		 3478static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3479 struct rtl8169_private *tp, int pkt_size,
3480 dma_addr_t addr)
1da177e4 3481{
b449655f
SH		 3482 struct sk_buff *skb;
3483 bool done = false;
1da177e4 3484
b449655f
SH		 3485 if (pkt_size >= rx_copybreak)
3486 goto out;
1da177e4 3487
07d3f51f 3488 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3489 if (!skb)
3490 goto out;
3491
07d3f51f
FR		 3492 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3493 PCI_DMA_FROMDEVICE);
86402234 3494 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3495 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3496 *sk_buff = skb;
3497 done = true;
3498out:
3499 return done;
1da177e4
LT		 3500}
3501
07d3f51f
FR		 3502static int rtl8169_rx_interrupt(struct net_device *dev,
3503 struct rtl8169_private *tp,
bea3348e 3504 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3505{
3506 unsigned int cur_rx, rx_left;
3507 unsigned int delta, count;
3508
1da177e4
LT		 3509 cur_rx = tp->cur_rx;
3510 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3511 rx_left = min(rx_left, budget);
1da177e4 3512
4dcb7d33 3513 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3514 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3515 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3516 u32 status;
3517
3518 rmb();
126fa4b9 3519 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3520
3521 if (status & DescOwn)
3522 break;
4dcb7d33 3523 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3524 if (netif_msg_rx_err(tp)) {
3525 printk(KERN_INFO
3526 "%s: Rx ERROR. status = %08x\n",
3527 dev->name, status);
3528 }
cebf8cc7 3529 dev->stats.rx_errors++;
1da177e4 3530 if (status & (RxRWT | RxRUNT))
cebf8cc7 3531 dev->stats.rx_length_errors++;
1da177e4 3532 if (status & RxCRC)
cebf8cc7 3533 dev->stats.rx_crc_errors++;
9dccf611
FR		 3534 if (status & RxFOVF) {
3535 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3536 dev->stats.rx_fifo_errors++;
9dccf611 3537 }
126fa4b9 3538 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3539 } else {
1da177e4 3540 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3541 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3542 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3543 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3544
126fa4b9
FR		 3545 /*
3546 * The driver does not support incoming fragmented
3547 * frames. They are seen as a symptom of over-mtu
3548 * sized frames.
3549 */
3550 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3551 dev->stats.rx_dropped++;
3552 dev->stats.rx_length_errors++;
126fa4b9 3553 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3554 continue;
126fa4b9
FR		 3555 }
3556
1da177e4 3557 rtl8169_rx_csum(skb, desc);
bcf0bf90 3558
07d3f51f 3559 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3560 pci_dma_sync_single_for_device(pdev, addr,
3561 pkt_size, PCI_DMA_FROMDEVICE);
3562 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3563 } else {
a866bbf6 3564 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3565 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3566 tp->Rx_skbuff[entry] = NULL;
3567 }
3568
1da177e4
LT		 3569 skb_put(skb, pkt_size);
3570 skb->protocol = eth_type_trans(skb, dev);
3571
3572 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3573 netif_receive_skb(skb);
1da177e4 3574
cebf8cc7
FR		 3575 dev->stats.rx_bytes += pkt_size;
3576 dev->stats.rx_packets++;
1da177e4 3577 }
6dccd16b
FR		 3578
3579 /* Work around for AMD plateform. */
95e0918d 3580 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3581 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3582 desc->opts2 = 0;
3583 cur_rx++;
3584 }
1da177e4
LT		 3585 }
3586
3587 count = cur_rx - tp->cur_rx;
3588 tp->cur_rx = cur_rx;
3589
3590 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3591 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3592 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3593 tp->dirty_rx += delta;
3594
3595 /*
3596 * FIXME: until there is periodic timer to try and refill the ring,
3597 * a temporary shortage may definitely kill the Rx process.
3598 * - disable the asic to try and avoid an overflow and kick it again
3599 * after refill ?
3600 * - how do others driver handle this condition (Uh oh...).
3601 */
b57b7e5a 3602 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3603 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3604
3605 return count;
3606}
3607
07d3f51f 3608static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3609{
07d3f51f 3610 struct net_device *dev = dev_instance;
1da177e4 3611 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3612 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3613 int handled = 0;
865c652d 3614 int status;
1da177e4 3615
f11a377b
DD		 3616 /* loop handling interrupts until we have no new ones or
3617 * we hit a invalid/hotplug case.
3618 */
865c652d 3619 status = RTL_R16(IntrStatus);
f11a377b
DD		 3620 while (status && status != 0xffff) {
3621 handled = 1;
1da177e4 3622
f11a377b
DD		 3623 /* Handle all of the error cases first. These will reset
3624 * the chip, so just exit the loop.
3625 */
3626 if (unlikely(!netif_running(dev))) {
3627 rtl8169_asic_down(ioaddr);
3628 break;
3629 }
1da177e4 3630
f11a377b
DD		 3631 /* Work around for rx fifo overflow */
3632 if (unlikely(status & RxFIFOOver) &&
3633 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3634 netif_stop_queue(dev);
3635 rtl8169_tx_timeout(dev);
3636 break;
3637 }
1da177e4 3638
f11a377b
DD		 3639 if (unlikely(status & SYSErr)) {
3640 rtl8169_pcierr_interrupt(dev);
3641 break;
3642 }
1da177e4 3643
f11a377b
DD		 3644 if (status & LinkChg)
3645 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 3646
f11a377b
DD		 3647 /* We need to see the lastest version of tp->intr_mask to
3648 * avoid ignoring an MSI interrupt and having to wait for
3649 * another event which may never come.
3650 */
3651 smp_rmb();
3652 if (status & tp->intr_mask & tp->napi_event) {
3653 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3654 tp->intr_mask = ~tp->napi_event;
3655
3656 if (likely(napi_schedule_prep(&tp->napi)))
3657 __napi_schedule(&tp->napi);
3658 else if (netif_msg_intr(tp)) {
3659 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3660 dev->name, status);
3661 }
3662 }
1da177e4 3663
f11a377b
DD		 3664 /* We only get a new MSI interrupt when all active irq
3665 * sources on the chip have been acknowledged. So, ack
3666 * everything we've seen and check if new sources have become
3667 * active to avoid blocking all interrupts from the chip.
3668 */
3669 RTL_W16(IntrStatus,
3670 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3671 status = RTL_R16(IntrStatus);
865c652d 3672 }
1da177e4 3673
1da177e4
LT		 3674 return IRQ_RETVAL(handled);
3675}
3676
bea3348e 3677static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3678{
bea3348e
SH		 3679 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3680 struct net_device *dev = tp->dev;
1da177e4 3681 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3682 int work_done;
1da177e4 3683
bea3348e 3684 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3685 rtl8169_tx_interrupt(dev, tp, ioaddr);
3686
bea3348e 3687 if (work_done < budget) {
288379f0 3688 napi_complete(napi);
f11a377b
DD		 3689
3690 /* We need for force the visibility of tp->intr_mask
3691 * for other CPUs, as we can loose an MSI interrupt
3692 * and potentially wait for a retransmit timeout if we don't.
3693 * The posted write to IntrMask is safe, as it will
3694 * eventually make it to the chip and we won't loose anything
3695 * until it does.
1da177e4 3696 */
f11a377b 3697 tp->intr_mask = 0xffff;
1da177e4 3698 smp_wmb();
0e485150 3699 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3700 }
3701
bea3348e 3702 return work_done;
1da177e4 3703}
1da177e4 3704
523a6094
FR		 3705static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3706{
3707 struct rtl8169_private *tp = netdev_priv(dev);
3708
3709 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3710 return;
3711
3712 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3713 RTL_W32(RxMissed, 0);
3714}
3715
1da177e4
LT		 3716static void rtl8169_down(struct net_device *dev)
3717{
3718 struct rtl8169_private *tp = netdev_priv(dev);
3719 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3720 unsigned int intrmask;
1da177e4
LT		 3721
3722 rtl8169_delete_timer(dev);
3723
3724 netif_stop_queue(dev);
3725
93dd79e8 3726 napi_disable(&tp->napi);
93dd79e8 3727
1da177e4
LT		 3728core_down:
3729 spin_lock_irq(&tp->lock);
3730
3731 rtl8169_asic_down(ioaddr);
3732
523a6094 3733 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3734
3735 spin_unlock_irq(&tp->lock);
3736
3737 synchronize_irq(dev->irq);
3738
1da177e4 3739 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3740 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3741
3742 /*
3743 * And now for the 50k$ question: are IRQ disabled or not ?
3744 *
3745 * Two paths lead here:
3746 * 1) dev->close
3747 * -> netif_running() is available to sync the current code and the
3748 * IRQ handler. See rtl8169_interrupt for details.
3749 * 2) dev->change_mtu
3750 * -> rtl8169_poll can not be issued again and re-enable the
3751 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3752 *
3753 * No loop if hotpluged or major error (0xffff).
1da177e4 3754 */
733b736c
AP		 3755 intrmask = RTL_R16(IntrMask);
3756 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3757 goto core_down;
3758
3759 rtl8169_tx_clear(tp);
3760
3761 rtl8169_rx_clear(tp);
3762}
3763
3764static int rtl8169_close(struct net_device *dev)
3765{
3766 struct rtl8169_private *tp = netdev_priv(dev);
3767 struct pci_dev *pdev = tp->pci_dev;
3768
355423d0
IV		 3769 /* update counters before going down */
3770 rtl8169_update_counters(dev);
3771
1da177e4
LT		 3772 rtl8169_down(dev);
3773
3774 free_irq(dev->irq, dev);
3775
1da177e4
LT		 3776 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3777 tp->RxPhyAddr);
3778 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3779 tp->TxPhyAddr);
3780 tp->TxDescArray = NULL;
3781 tp->RxDescArray = NULL;
3782
3783 return 0;
3784}
3785
07ce4064 3786static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3787{
3788 struct rtl8169_private *tp = netdev_priv(dev);
3789 void __iomem *ioaddr = tp->mmio_addr;
3790 unsigned long flags;
3791 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3792 int rx_mode;
1da177e4
LT		 3793 u32 tmp = 0;
3794
3795 if (dev->flags & IFF_PROMISC) {
3796 /* Unconditionally log net taps. */
b57b7e5a
SH		 3797 if (netif_msg_link(tp)) {
3798 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3799 dev->name);
3800 }
1da177e4
LT		 3801 rx_mode =
3802 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3803 AcceptAllPhys;
3804 mc_filter[1] = mc_filter[0] = 0xffffffff;
3805 } else if ((dev->mc_count > multicast_filter_limit)
3806 || (dev->flags & IFF_ALLMULTI)) {
3807 /* Too many to filter perfectly -- accept all multicasts. */
3808 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3809 mc_filter[1] = mc_filter[0] = 0xffffffff;
3810 } else {
3811 struct dev_mc_list *mclist;
07d3f51f
FR		 3812 unsigned int i;
3813
1da177e4
LT		 3814 rx_mode = AcceptBroadcast | AcceptMyPhys;
3815 mc_filter[1] = mc_filter[0] = 0;
3816 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3817 i++, mclist = mclist->next) {
3818 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3819 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3820 rx_mode |= AcceptMulticast;
3821 }
3822 }
3823
3824 spin_lock_irqsave(&tp->lock, flags);
3825
3826 tmp = rtl8169_rx_config | rx_mode |
3827 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3828
f887cce8 3829 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3830 u32 data = mc_filter[0];
3831
3832 mc_filter[0] = swab32(mc_filter[1]);
3833 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3834 }
3835
1da177e4
LT		 3836 RTL_W32(MAR0 + 0, mc_filter[0]);
3837 RTL_W32(MAR0 + 4, mc_filter[1]);
3838
57a9f236
FR		 3839 RTL_W32(RxConfig, tmp);
3840
1da177e4
LT		 3841 spin_unlock_irqrestore(&tp->lock, flags);
3842}
3843
3844/**
3845 * rtl8169_get_stats - Get rtl8169 read/write statistics
3846 * @dev: The Ethernet Device to get statistics for
3847 *
3848 * Get TX/RX statistics for rtl8169
3849 */
3850static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3851{
3852 struct rtl8169_private *tp = netdev_priv(dev);
3853 void __iomem *ioaddr = tp->mmio_addr;
3854 unsigned long flags;
3855
3856 if (netif_running(dev)) {
3857 spin_lock_irqsave(&tp->lock, flags);
523a6094 3858 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3859 spin_unlock_irqrestore(&tp->lock, flags);
3860 }
5b0384f4 3861
cebf8cc7 3862 return &dev->stats;
1da177e4
LT		 3863}
3864
861ab440 3865static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 3866{
5d06a99f 3867 if (!netif_running(dev))
861ab440 3868 return;
5d06a99f
FR		 3869
3870 netif_device_detach(dev);
3871 netif_stop_queue(dev);
861ab440
RW		 3872}
3873
3874#ifdef CONFIG_PM
3875
3876static int rtl8169_suspend(struct device *device)
3877{
3878 struct pci_dev *pdev = to_pci_dev(device);
3879 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 3880
861ab440 3881 rtl8169_net_suspend(dev);
1371fa6d 3882
5d06a99f
FR		 3883 return 0;
3884}
3885
861ab440 3886static int rtl8169_resume(struct device *device)
5d06a99f 3887{
861ab440 3888 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 3889 struct net_device *dev = pci_get_drvdata(pdev);
3890
3891 if (!netif_running(dev))
3892 goto out;
3893
3894 netif_device_attach(dev);
3895
5d06a99f
FR		 3896 rtl8169_schedule_work(dev, rtl8169_reset_task);
3897out:
3898 return 0;
3899}
3900
861ab440
RW		 3901static struct dev_pm_ops rtl8169_pm_ops = {
3902 .suspend = rtl8169_suspend,
3903 .resume = rtl8169_resume,
3904 .freeze = rtl8169_suspend,
3905 .thaw = rtl8169_resume,
3906 .poweroff = rtl8169_suspend,
3907 .restore = rtl8169_resume,
3908};
3909
3910#define RTL8169_PM_OPS (&rtl8169_pm_ops)
3911
3912#else /* !CONFIG_PM */
3913
3914#define RTL8169_PM_OPS NULL
3915
3916#endif /* !CONFIG_PM */
3917
1765f95d
FR		 3918static void rtl_shutdown(struct pci_dev *pdev)
3919{
861ab440 3920 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 3921 struct rtl8169_private *tp = netdev_priv(dev);
3922 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 3923
3924 rtl8169_net_suspend(dev);
1765f95d 3925
4bb3f522 3926 spin_lock_irq(&tp->lock);
3927
3928 rtl8169_asic_down(ioaddr);
3929
3930 spin_unlock_irq(&tp->lock);
3931
861ab440 3932 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 3933 /* WoL fails with some 8168 when the receiver is disabled. */
3934 if (tp->features & RTL_FEATURE_WOL) {
3935 pci_clear_master(pdev);
3936
3937 RTL_W8(ChipCmd, CmdRxEnb);
3938 /* PCI commit */
3939 RTL_R8(ChipCmd);
3940 }
3941
861ab440
RW		 3942 pci_wake_from_d3(pdev, true);
3943 pci_set_power_state(pdev, PCI_D3hot);
3944 }
3945}
5d06a99f 3946
1da177e4
LT		 3947static struct pci_driver rtl8169_pci_driver = {
3948 .name = MODULENAME,
3949 .id_table = rtl8169_pci_tbl,
3950 .probe = rtl8169_init_one,
3951 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 3952 .shutdown = rtl_shutdown,
861ab440 3953 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 3954};
3955
07d3f51f 3956static int __init rtl8169_init_module(void)
1da177e4 3957{
29917620 3958 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3959}
3960
07d3f51f 3961static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3962{
3963 pci_unregister_driver(&rtl8169_pci_driver);
3964}
3965
3966module_init(rtl8169_init_module);
3967module_exit(rtl8169_cleanup_module);
Clone of davem's net-next-2.6 tree