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r8169: add a new 8168cp flavor
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 113 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0
FR		 114 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
115 RTL_GIGA_MAC_VER_23 = 0x17 // 8168CP
1da177e4
LT		 116};
117
1da177e4
LT		 118#define _R(NAME,MAC,MASK) \
119 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
120
3c6bee1d 121static const struct {
1da177e4
LT		 122 const char *name;
123 u8 mac_version;
124 u32 RxConfigMask; /* Clears the bits supported by this chip */
125} rtl_chip_info[] = {
ba6eb6ee
FR		 126 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
127 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
128 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
129 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
130 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 131 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 132 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
133 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
134 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 136 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
137 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
139 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 140 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
143 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
144 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 145 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0
FR		 147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880) // PCI-E
1da177e4
LT		 149};
150#undef _R
151
bcf0bf90
FR		 152enum cfg_version {
153 RTL_CFG_0 = 0x00,
154 RTL_CFG_1,
155 RTL_CFG_2
156};
157
07ce4064
FR		 158static void rtl_hw_start_8169(struct net_device *);
159static void rtl_hw_start_8168(struct net_device *);
160static void rtl_hw_start_8101(struct net_device *);
161
1da177e4 162static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 169 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 170 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032,
172 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 173 { 0x0001, 0x8168,
174 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 175 {0,},
176};
177
178MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
179
180static int rx_copybreak = 200;
181static int use_dac;
b57b7e5a
SH		 182static struct {
183 u32 msg_enable;
184} debug = { -1 };
1da177e4 185
07d3f51f
FR		 186enum rtl_registers {
187 MAC0 = 0, /* Ethernet hardware address. */
773d2021 188 MAC4 = 4,
07d3f51f
FR		 189 MAR0 = 8, /* Multicast filter. */
190 CounterAddrLow = 0x10,
191 CounterAddrHigh = 0x14,
192 TxDescStartAddrLow = 0x20,
193 TxDescStartAddrHigh = 0x24,
194 TxHDescStartAddrLow = 0x28,
195 TxHDescStartAddrHigh = 0x2c,
196 FLASH = 0x30,
197 ERSR = 0x36,
198 ChipCmd = 0x37,
199 TxPoll = 0x38,
200 IntrMask = 0x3c,
201 IntrStatus = 0x3e,
202 TxConfig = 0x40,
203 RxConfig = 0x44,
204 RxMissed = 0x4c,
205 Cfg9346 = 0x50,
206 Config0 = 0x51,
207 Config1 = 0x52,
208 Config2 = 0x53,
209 Config3 = 0x54,
210 Config4 = 0x55,
211 Config5 = 0x56,
212 MultiIntr = 0x5c,
213 PHYAR = 0x60,
07d3f51f
FR		 214 PHYstatus = 0x6c,
215 RxMaxSize = 0xda,
216 CPlusCmd = 0xe0,
217 IntrMitigate = 0xe2,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
220 EarlyTxThres = 0xec,
221 FuncEvent = 0xf0,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
1da177e4
LT		 225};
226
f162a5d1
FR		 227enum rtl8110_registers {
228 TBICSR = 0x64,
229 TBI_ANAR = 0x68,
230 TBI_LPAR = 0x6a,
231};
232
233enum rtl8168_8101_registers {
234 CSIDR = 0x64,
235 CSIAR = 0x68,
236#define CSIAR_FLAG 0x80000000
237#define CSIAR_WRITE_CMD 0x80000000
238#define CSIAR_BYTE_ENABLE 0x0f
239#define CSIAR_BYTE_ENABLE_SHIFT 12
240#define CSIAR_ADDR_MASK 0x0fff
241
242 EPHYAR = 0x80,
243#define EPHYAR_FLAG 0x80000000
244#define EPHYAR_WRITE_CMD 0x80000000
245#define EPHYAR_REG_MASK 0x1f
246#define EPHYAR_REG_SHIFT 16
247#define EPHYAR_DATA_MASK 0xffff
248 DBG_REG = 0xd1,
249#define FIX_NAK_1 (1 << 4)
250#define FIX_NAK_2 (1 << 3)
251};
252
07d3f51f 253enum rtl_register_content {
1da177e4 254 /* InterruptStatusBits */
07d3f51f
FR		 255 SYSErr = 0x8000,
256 PCSTimeout = 0x4000,
257 SWInt = 0x0100,
258 TxDescUnavail = 0x0080,
259 RxFIFOOver = 0x0040,
260 LinkChg = 0x0020,
261 RxOverflow = 0x0010,
262 TxErr = 0x0008,
263 TxOK = 0x0004,
264 RxErr = 0x0002,
265 RxOK = 0x0001,
1da177e4
LT		 266
267 /* RxStatusDesc */
9dccf611
FR		 268 RxFOVF = (1 << 23),
269 RxRWT = (1 << 22),
270 RxRES = (1 << 21),
271 RxRUNT = (1 << 20),
272 RxCRC = (1 << 19),
1da177e4
LT		 273
274 /* ChipCmdBits */
07d3f51f
FR		 275 CmdReset = 0x10,
276 CmdRxEnb = 0x08,
277 CmdTxEnb = 0x04,
278 RxBufEmpty = 0x01,
1da177e4 279
275391a4
FR		 280 /* TXPoll register p.5 */
281 HPQ = 0x80, /* Poll cmd on the high prio queue */
282 NPQ = 0x40, /* Poll cmd on the low prio queue */
283 FSWInt = 0x01, /* Forced software interrupt */
284
1da177e4 285 /* Cfg9346Bits */
07d3f51f
FR		 286 Cfg9346_Lock = 0x00,
287 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 288
289 /* rx_mode_bits */
07d3f51f
FR		 290 AcceptErr = 0x20,
291 AcceptRunt = 0x10,
292 AcceptBroadcast = 0x08,
293 AcceptMulticast = 0x04,
294 AcceptMyPhys = 0x02,
295 AcceptAllPhys = 0x01,
1da177e4
LT		 296
297 /* RxConfigBits */
07d3f51f
FR		 298 RxCfgFIFOShift = 13,
299 RxCfgDMAShift = 8,
1da177e4
LT		 300
301 /* TxConfigBits */
302 TxInterFrameGapShift = 24,
303 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
304
5d06a99f 305 /* Config1 register p.24 */
f162a5d1
FR		 306 LEDS1 = (1 << 7),
307 LEDS0 = (1 << 6),
fbac58fc 308 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 309 Speed_down = (1 << 4),
310 MEMMAP = (1 << 3),
311 IOMAP = (1 << 2),
312 VPD = (1 << 1),
5d06a99f
FR		 313 PMEnable = (1 << 0), /* Power Management Enable */
314
6dccd16b
FR		 315 /* Config2 register p. 25 */
316 PCI_Clock_66MHz = 0x01,
317 PCI_Clock_33MHz = 0x00,
318
61a4dcc2
FR		 319 /* Config3 register p.25 */
320 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
321 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 322 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 323
5d06a99f 324 /* Config5 register p.27 */
61a4dcc2
FR		 325 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
326 MWF = (1 << 5), /* Accept Multicast wakeup frame */
327 UWF = (1 << 4), /* Accept Unicast wakeup frame */
328 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 329 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
330
1da177e4
LT		 331 /* TBICSR p.28 */
332 TBIReset = 0x80000000,
333 TBILoopback = 0x40000000,
334 TBINwEnable = 0x20000000,
335 TBINwRestart = 0x10000000,
336 TBILinkOk = 0x02000000,
337 TBINwComplete = 0x01000000,
338
339 /* CPlusCmd p.31 */
f162a5d1
FR		 340 EnableBist = (1 << 15), // 8168 8101
341 Mac_dbgo_oe = (1 << 14), // 8168 8101
342 Normal_mode = (1 << 13), // unused
343 Force_half_dup = (1 << 12), // 8168 8101
344 Force_rxflow_en = (1 << 11), // 8168 8101
345 Force_txflow_en = (1 << 10), // 8168 8101
346 Cxpl_dbg_sel = (1 << 9), // 8168 8101
347 ASF = (1 << 8), // 8168 8101
348 PktCntrDisable = (1 << 7), // 8168 8101
349 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 350 RxVlan = (1 << 6),
351 RxChkSum = (1 << 5),
352 PCIDAC = (1 << 4),
353 PCIMulRW = (1 << 3),
0e485150
FR		 354 INTT_0 = 0x0000, // 8168
355 INTT_1 = 0x0001, // 8168
356 INTT_2 = 0x0002, // 8168
357 INTT_3 = 0x0003, // 8168
1da177e4
LT		 358
359 /* rtl8169_PHYstatus */
07d3f51f
FR		 360 TBI_Enable = 0x80,
361 TxFlowCtrl = 0x40,
362 RxFlowCtrl = 0x20,
363 _1000bpsF = 0x10,
364 _100bps = 0x08,
365 _10bps = 0x04,
366 LinkStatus = 0x02,
367 FullDup = 0x01,
1da177e4 368
1da177e4 369 /* _TBICSRBit */
07d3f51f 370 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 371
372 /* DumpCounterCommand */
07d3f51f 373 CounterDump = 0x8,
1da177e4
LT		 374};
375
07d3f51f 376enum desc_status_bit {
1da177e4
LT		 377 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
378 RingEnd = (1 << 30), /* End of descriptor ring */
379 FirstFrag = (1 << 29), /* First segment of a packet */
380 LastFrag = (1 << 28), /* Final segment of a packet */
381
382 /* Tx private */
383 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
384 MSSShift = 16, /* MSS value position */
385 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
386 IPCS = (1 << 18), /* Calculate IP checksum */
387 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
388 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
389 TxVlanTag = (1 << 17), /* Add VLAN tag */
390
391 /* Rx private */
392 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
393 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
394
395#define RxProtoUDP (PID1)
396#define RxProtoTCP (PID0)
397#define RxProtoIP (PID1 | PID0)
398#define RxProtoMask RxProtoIP
399
400 IPFail = (1 << 16), /* IP checksum failed */
401 UDPFail = (1 << 15), /* UDP/IP checksum failed */
402 TCPFail = (1 << 14), /* TCP/IP checksum failed */
403 RxVlanTag = (1 << 16), /* VLAN tag available */
404};
405
406#define RsvdMask 0x3fffc000
407
408struct TxDesc {
6cccd6e7
REB		 409 __le32 opts1;
410 __le32 opts2;
411 __le64 addr;
1da177e4
LT		 412};
413
414struct RxDesc {
6cccd6e7
REB		 415 __le32 opts1;
416 __le32 opts2;
417 __le64 addr;
1da177e4
LT		 418};
419
420struct ring_info {
421 struct sk_buff *skb;
422 u32 len;
423 u8 __pad[sizeof(void *) - sizeof(u32)];
424};
425
f23e7fda 426enum features {
ccdffb9a
FR		 427 RTL_FEATURE_WOL = (1 << 0),
428 RTL_FEATURE_MSI = (1 << 1),
429 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 430};
431
1da177e4
LT		 432struct rtl8169_private {
433 void __iomem *mmio_addr; /* memory map physical address */
434 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 435 struct net_device *dev;
bea3348e 436 struct napi_struct napi;
1da177e4 437 spinlock_t lock; /* spin lock flag */
b57b7e5a 438 u32 msg_enable;
1da177e4
LT		 439 int chipset;
440 int mac_version;
1da177e4
LT		 441 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
442 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
443 u32 dirty_rx;
444 u32 dirty_tx;
445 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
446 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
447 dma_addr_t TxPhyAddr;
448 dma_addr_t RxPhyAddr;
449 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
450 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 451 unsigned align;
1da177e4
LT		 452 unsigned rx_buf_sz;
453 struct timer_list timer;
454 u16 cp_cmd;
0e485150
FR		 455 u16 intr_event;
456 u16 napi_event;
1da177e4
LT		 457 u16 intr_mask;
458 int phy_auto_nego_reg;
459 int phy_1000_ctrl_reg;
460#ifdef CONFIG_R8169_VLAN
461 struct vlan_group *vlgrp;
462#endif
463 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 464 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 465 void (*phy_reset_enable)(void __iomem *);
07ce4064 466 void (*hw_start)(struct net_device *);
1da177e4
LT		 467 unsigned int (*phy_reset_pending)(void __iomem *);
468 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 469 int pcie_cap;
c4028958 470 struct delayed_work task;
f23e7fda 471 unsigned features;
ccdffb9a
FR		 472
473 struct mii_if_info mii;
1da177e4
LT		 474};
475
979b6c13 476MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 477MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 478module_param(rx_copybreak, int, 0);
1b7efd58 479MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 480module_param(use_dac, int, 0);
481MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 482module_param_named(debug, debug.msg_enable, int, 0);
483MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 484MODULE_LICENSE("GPL");
485MODULE_VERSION(RTL8169_VERSION);
486
487static int rtl8169_open(struct net_device *dev);
488static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 489static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 490static int rtl8169_init_ring(struct net_device *dev);
07ce4064 491static void rtl_hw_start(struct net_device *dev);
1da177e4 492static int rtl8169_close(struct net_device *dev);
07ce4064 493static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 494static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 495static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 496static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 497 void __iomem *, u32 budget);
4dcb7d33 498static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 499static void rtl8169_down(struct net_device *dev);
99f252b0 500static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 501static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 502
1da177e4 503static const unsigned int rtl8169_rx_config =
5b0384f4 504 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 505
07d3f51f 506static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 507{
508 int i;
509
a6baf3af 510 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 511
2371408c 512 for (i = 20; i > 0; i--) {
07d3f51f
FR		 513 /*
514 * Check if the RTL8169 has completed writing to the specified
515 * MII register.
516 */
5b0384f4 517 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 518 break;
2371408c 519 udelay(25);
1da177e4
LT		 520 }
521}
522
07d3f51f 523static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 524{
525 int i, value = -1;
526
a6baf3af 527 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 528
2371408c 529 for (i = 20; i > 0; i--) {
07d3f51f
FR		 530 /*
531 * Check if the RTL8169 has completed retrieving data from
532 * the specified MII register.
533 */
1da177e4 534 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 535 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 536 break;
537 }
2371408c 538 udelay(25);
1da177e4
LT		 539 }
540 return value;
541}
542
dacf8154
FR		 543static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
544{
545 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
546}
547
ccdffb9a
FR		 548static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
549 int val)
550{
551 struct rtl8169_private *tp = netdev_priv(dev);
552 void __iomem *ioaddr = tp->mmio_addr;
553
554 mdio_write(ioaddr, location, val);
555}
556
557static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
558{
559 struct rtl8169_private *tp = netdev_priv(dev);
560 void __iomem *ioaddr = tp->mmio_addr;
561
562 return mdio_read(ioaddr, location);
563}
564
dacf8154
FR		 565static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
566{
567 unsigned int i;
568
569 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
570 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
571
572 for (i = 0; i < 100; i++) {
573 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
574 break;
575 udelay(10);
576 }
577}
578
579static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
580{
581 u16 value = 0xffff;
582 unsigned int i;
583
584 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
585
586 for (i = 0; i < 100; i++) {
587 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
588 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
589 break;
590 }
591 udelay(10);
592 }
593
594 return value;
595}
596
597static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
598{
599 unsigned int i;
600
601 RTL_W32(CSIDR, value);
602 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
603 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
604
605 for (i = 0; i < 100; i++) {
606 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
607 break;
608 udelay(10);
609 }
610}
611
612static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
613{
614 u32 value = ~0x00;
615 unsigned int i;
616
617 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
618 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
619
620 for (i = 0; i < 100; i++) {
621 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
622 value = RTL_R32(CSIDR);
623 break;
624 }
625 udelay(10);
626 }
627
628 return value;
629}
630
1da177e4
LT		 631static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
632{
633 RTL_W16(IntrMask, 0x0000);
634
635 RTL_W16(IntrStatus, 0xffff);
636}
637
638static void rtl8169_asic_down(void __iomem *ioaddr)
639{
640 RTL_W8(ChipCmd, 0x00);
641 rtl8169_irq_mask_and_ack(ioaddr);
642 RTL_R16(CPlusCmd);
643}
644
645static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
646{
647 return RTL_R32(TBICSR) & TBIReset;
648}
649
650static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
651{
64e4bfb4 652 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 653}
654
655static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
656{
657 return RTL_R32(TBICSR) & TBILinkOk;
658}
659
660static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
661{
662 return RTL_R8(PHYstatus) & LinkStatus;
663}
664
665static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
666{
667 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
668}
669
670static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
671{
672 unsigned int val;
673
9e0db8ef
FR		 674 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
675 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 676}
677
678static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 679 struct rtl8169_private *tp,
680 void __iomem *ioaddr)
1da177e4
LT		 681{
682 unsigned long flags;
683
684 spin_lock_irqsave(&tp->lock, flags);
685 if (tp->link_ok(ioaddr)) {
686 netif_carrier_on(dev);
b57b7e5a
SH		 687 if (netif_msg_ifup(tp))
688 printk(KERN_INFO PFX "%s: link up\n", dev->name);
689 } else {
690 if (netif_msg_ifdown(tp))
691 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 692 netif_carrier_off(dev);
b57b7e5a 693 }
1da177e4
LT		 694 spin_unlock_irqrestore(&tp->lock, flags);
695}
696
61a4dcc2
FR		 697static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
698{
699 struct rtl8169_private *tp = netdev_priv(dev);
700 void __iomem *ioaddr = tp->mmio_addr;
701 u8 options;
702
703 wol->wolopts = 0;
704
705#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
706 wol->supported = WAKE_ANY;
707
708 spin_lock_irq(&tp->lock);
709
710 options = RTL_R8(Config1);
711 if (!(options & PMEnable))
712 goto out_unlock;
713
714 options = RTL_R8(Config3);
715 if (options & LinkUp)
716 wol->wolopts |= WAKE_PHY;
717 if (options & MagicPacket)
718 wol->wolopts |= WAKE_MAGIC;
719
720 options = RTL_R8(Config5);
721 if (options & UWF)
722 wol->wolopts |= WAKE_UCAST;
723 if (options & BWF)
5b0384f4 724 wol->wolopts |= WAKE_BCAST;
61a4dcc2 725 if (options & MWF)
5b0384f4 726 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 727
728out_unlock:
729 spin_unlock_irq(&tp->lock);
730}
731
732static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
733{
734 struct rtl8169_private *tp = netdev_priv(dev);
735 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 736 unsigned int i;
61a4dcc2
FR		 737 static struct {
738 u32 opt;
739 u16 reg;
740 u8 mask;
741 } cfg[] = {
742 { WAKE_ANY, Config1, PMEnable },
743 { WAKE_PHY, Config3, LinkUp },
744 { WAKE_MAGIC, Config3, MagicPacket },
745 { WAKE_UCAST, Config5, UWF },
746 { WAKE_BCAST, Config5, BWF },
747 { WAKE_MCAST, Config5, MWF },
748 { WAKE_ANY, Config5, LanWake }
749 };
750
751 spin_lock_irq(&tp->lock);
752
753 RTL_W8(Cfg9346, Cfg9346_Unlock);
754
755 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
756 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
757 if (wol->wolopts & cfg[i].opt)
758 options |= cfg[i].mask;
759 RTL_W8(cfg[i].reg, options);
760 }
761
762 RTL_W8(Cfg9346, Cfg9346_Lock);
763
f23e7fda
FR		 764 if (wol->wolopts)
765 tp->features |= RTL_FEATURE_WOL;
766 else
767 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 768 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 769
770 spin_unlock_irq(&tp->lock);
771
772 return 0;
773}
774
1da177e4
LT		 775static void rtl8169_get_drvinfo(struct net_device *dev,
776 struct ethtool_drvinfo *info)
777{
778 struct rtl8169_private *tp = netdev_priv(dev);
779
780 strcpy(info->driver, MODULENAME);
781 strcpy(info->version, RTL8169_VERSION);
782 strcpy(info->bus_info, pci_name(tp->pci_dev));
783}
784
785static int rtl8169_get_regs_len(struct net_device *dev)
786{
787 return R8169_REGS_SIZE;
788}
789
790static int rtl8169_set_speed_tbi(struct net_device *dev,
791 u8 autoneg, u16 speed, u8 duplex)
792{
793 struct rtl8169_private *tp = netdev_priv(dev);
794 void __iomem *ioaddr = tp->mmio_addr;
795 int ret = 0;
796 u32 reg;
797
798 reg = RTL_R32(TBICSR);
799 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
800 (duplex == DUPLEX_FULL)) {
801 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
802 } else if (autoneg == AUTONEG_ENABLE)
803 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
804 else {
b57b7e5a
SH		 805 if (netif_msg_link(tp)) {
806 printk(KERN_WARNING "%s: "
807 "incorrect speed setting refused in TBI mode\n",
808 dev->name);
809 }
1da177e4
LT		 810 ret = -EOPNOTSUPP;
811 }
812
813 return ret;
814}
815
816static int rtl8169_set_speed_xmii(struct net_device *dev,
817 u8 autoneg, u16 speed, u8 duplex)
818{
819 struct rtl8169_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->mmio_addr;
821 int auto_nego, giga_ctrl;
822
64e4bfb4
FR		 823 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
824 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
825 ADVERTISE_100HALF | ADVERTISE_100FULL);
826 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
827 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 828
829 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 830 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
831 ADVERTISE_100HALF | ADVERTISE_100FULL);
832 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 833 } else {
834 if (speed == SPEED_10)
64e4bfb4 835 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 836 else if (speed == SPEED_100)
64e4bfb4 837 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 838 else if (speed == SPEED_1000)
64e4bfb4 839 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 840
841 if (duplex == DUPLEX_HALF)
64e4bfb4 842 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 843
844 if (duplex == DUPLEX_FULL)
64e4bfb4 845 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 846
847 /* This tweak comes straight from Realtek's driver. */
848 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 849 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
850 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 851 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 852 }
853 }
854
2857ffb7
FR		 855 /* The 8100e/8101e/8102e do Fast Ethernet only. */
856 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
858 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
859 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
860 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 861 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 862 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
863 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 864 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 865 netif_msg_link(tp)) {
866 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
867 dev->name);
868 }
64e4bfb4 869 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 870 }
871
623a1593
FR		 872 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
873
a2de6b89
FR		 874 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
875 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
876 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
877 /*
878 * Wake up the PHY.
879 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
880 */
2584fbc3
RS		 881 mdio_write(ioaddr, 0x1f, 0x0000);
882 mdio_write(ioaddr, 0x0e, 0x0000);
883 }
884
1da177e4
LT		 885 tp->phy_auto_nego_reg = auto_nego;
886 tp->phy_1000_ctrl_reg = giga_ctrl;
887
64e4bfb4
FR		 888 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
889 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
890 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 891 return 0;
892}
893
894static int rtl8169_set_speed(struct net_device *dev,
895 u8 autoneg, u16 speed, u8 duplex)
896{
897 struct rtl8169_private *tp = netdev_priv(dev);
898 int ret;
899
900 ret = tp->set_speed(dev, autoneg, speed, duplex);
901
64e4bfb4 902 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 903 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
904
905 return ret;
906}
907
908static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
909{
910 struct rtl8169_private *tp = netdev_priv(dev);
911 unsigned long flags;
912 int ret;
913
914 spin_lock_irqsave(&tp->lock, flags);
915 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
916 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 917
1da177e4
LT		 918 return ret;
919}
920
921static u32 rtl8169_get_rx_csum(struct net_device *dev)
922{
923 struct rtl8169_private *tp = netdev_priv(dev);
924
925 return tp->cp_cmd & RxChkSum;
926}
927
928static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
929{
930 struct rtl8169_private *tp = netdev_priv(dev);
931 void __iomem *ioaddr = tp->mmio_addr;
932 unsigned long flags;
933
934 spin_lock_irqsave(&tp->lock, flags);
935
936 if (data)
937 tp->cp_cmd |= RxChkSum;
938 else
939 tp->cp_cmd &= ~RxChkSum;
940
941 RTL_W16(CPlusCmd, tp->cp_cmd);
942 RTL_R16(CPlusCmd);
943
944 spin_unlock_irqrestore(&tp->lock, flags);
945
946 return 0;
947}
948
949#ifdef CONFIG_R8169_VLAN
950
951static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
952 struct sk_buff *skb)
953{
954 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
955 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
956}
957
958static void rtl8169_vlan_rx_register(struct net_device *dev,
959 struct vlan_group *grp)
960{
961 struct rtl8169_private *tp = netdev_priv(dev);
962 void __iomem *ioaddr = tp->mmio_addr;
963 unsigned long flags;
964
965 spin_lock_irqsave(&tp->lock, flags);
966 tp->vlgrp = grp;
967 if (tp->vlgrp)
968 tp->cp_cmd |= RxVlan;
969 else
970 tp->cp_cmd &= ~RxVlan;
971 RTL_W16(CPlusCmd, tp->cp_cmd);
972 RTL_R16(CPlusCmd);
973 spin_unlock_irqrestore(&tp->lock, flags);
974}
975
1da177e4
LT		 976static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
977 struct sk_buff *skb)
978{
979 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 980 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 981 int ret;
982
865c652d
FR		 983 if (vlgrp && (opts2 & RxVlanTag)) {
984 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 985 ret = 0;
986 } else
987 ret = -1;
988 desc->opts2 = 0;
989 return ret;
990}
991
992#else /* !CONFIG_R8169_VLAN */
993
994static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
995 struct sk_buff *skb)
996{
997 return 0;
998}
999
1000static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1001 struct sk_buff *skb)
1002{
1003 return -1;
1004}
1005
1006#endif
1007
ccdffb9a 1008static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1009{
1010 struct rtl8169_private *tp = netdev_priv(dev);
1011 void __iomem *ioaddr = tp->mmio_addr;
1012 u32 status;
1013
1014 cmd->supported =
1015 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1016 cmd->port = PORT_FIBRE;
1017 cmd->transceiver = XCVR_INTERNAL;
1018
1019 status = RTL_R32(TBICSR);
1020 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1021 cmd->autoneg = !!(status & TBINwEnable);
1022
1023 cmd->speed = SPEED_1000;
1024 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1025
1026 return 0;
1da177e4
LT		 1027}
1028
ccdffb9a 1029static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1030{
1031 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1032
1033 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1034}
1035
1036static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1037{
1038 struct rtl8169_private *tp = netdev_priv(dev);
1039 unsigned long flags;
ccdffb9a 1040 int rc;
1da177e4
LT		 1041
1042 spin_lock_irqsave(&tp->lock, flags);
1043
ccdffb9a 1044 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1045
1046 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1047 return rc;
1da177e4
LT		 1048}
1049
1050static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1051 void *p)
1052{
5b0384f4
FR		 1053 struct rtl8169_private *tp = netdev_priv(dev);
1054 unsigned long flags;
1da177e4 1055
5b0384f4
FR		 1056 if (regs->len > R8169_REGS_SIZE)
1057 regs->len = R8169_REGS_SIZE;
1da177e4 1058
5b0384f4
FR		 1059 spin_lock_irqsave(&tp->lock, flags);
1060 memcpy_fromio(p, tp->mmio_addr, regs->len);
1061 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1062}
1063
b57b7e5a
SH		 1064static u32 rtl8169_get_msglevel(struct net_device *dev)
1065{
1066 struct rtl8169_private *tp = netdev_priv(dev);
1067
1068 return tp->msg_enable;
1069}
1070
1071static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1072{
1073 struct rtl8169_private *tp = netdev_priv(dev);
1074
1075 tp->msg_enable = value;
1076}
1077
d4a3a0fc
SH		 1078static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1079 "tx_packets",
1080 "rx_packets",
1081 "tx_errors",
1082 "rx_errors",
1083 "rx_missed",
1084 "align_errors",
1085 "tx_single_collisions",
1086 "tx_multi_collisions",
1087 "unicast",
1088 "broadcast",
1089 "multicast",
1090 "tx_aborted",
1091 "tx_underrun",
1092};
1093
1094struct rtl8169_counters {
b1eab701
AV		 1095 __le64 tx_packets;
1096 __le64 rx_packets;
1097 __le64 tx_errors;
1098 __le32 rx_errors;
1099 __le16 rx_missed;
1100 __le16 align_errors;
1101 __le32 tx_one_collision;
1102 __le32 tx_multi_collision;
1103 __le64 rx_unicast;
1104 __le64 rx_broadcast;
1105 __le32 rx_multicast;
1106 __le16 tx_aborted;
1107 __le16 tx_underun;
d4a3a0fc
SH		 1108};
1109
b9f2c044 1110static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1111{
b9f2c044
JG		 1112 switch (sset) {
1113 case ETH_SS_STATS:
1114 return ARRAY_SIZE(rtl8169_gstrings);
1115 default:
1116 return -EOPNOTSUPP;
1117 }
d4a3a0fc
SH		 1118}
1119
1120static void rtl8169_get_ethtool_stats(struct net_device *dev,
1121 struct ethtool_stats *stats, u64 *data)
1122{
1123 struct rtl8169_private *tp = netdev_priv(dev);
1124 void __iomem *ioaddr = tp->mmio_addr;
1125 struct rtl8169_counters *counters;
1126 dma_addr_t paddr;
1127 u32 cmd;
1128
1129 ASSERT_RTNL();
1130
1131 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1132 if (!counters)
1133 return;
1134
1135 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1136 cmd = (u64)paddr & DMA_32BIT_MASK;
1137 RTL_W32(CounterAddrLow, cmd);
1138 RTL_W32(CounterAddrLow, cmd | CounterDump);
1139
1140 while (RTL_R32(CounterAddrLow) & CounterDump) {
1141 if (msleep_interruptible(1))
1142 break;
1143 }
1144
1145 RTL_W32(CounterAddrLow, 0);
1146 RTL_W32(CounterAddrHigh, 0);
1147
5b0384f4 1148 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1149 data[1] = le64_to_cpu(counters->rx_packets);
1150 data[2] = le64_to_cpu(counters->tx_errors);
1151 data[3] = le32_to_cpu(counters->rx_errors);
1152 data[4] = le16_to_cpu(counters->rx_missed);
1153 data[5] = le16_to_cpu(counters->align_errors);
1154 data[6] = le32_to_cpu(counters->tx_one_collision);
1155 data[7] = le32_to_cpu(counters->tx_multi_collision);
1156 data[8] = le64_to_cpu(counters->rx_unicast);
1157 data[9] = le64_to_cpu(counters->rx_broadcast);
1158 data[10] = le32_to_cpu(counters->rx_multicast);
1159 data[11] = le16_to_cpu(counters->tx_aborted);
1160 data[12] = le16_to_cpu(counters->tx_underun);
1161
1162 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1163}
1164
1165static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1166{
1167 switch(stringset) {
1168 case ETH_SS_STATS:
1169 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1170 break;
1171 }
1172}
1173
7282d491 1174static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1175 .get_drvinfo = rtl8169_get_drvinfo,
1176 .get_regs_len = rtl8169_get_regs_len,
1177 .get_link = ethtool_op_get_link,
1178 .get_settings = rtl8169_get_settings,
1179 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1180 .get_msglevel = rtl8169_get_msglevel,
1181 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1182 .get_rx_csum = rtl8169_get_rx_csum,
1183 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1184 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1185 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1186 .set_tso = ethtool_op_set_tso,
1187 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1188 .get_wol = rtl8169_get_wol,
1189 .set_wol = rtl8169_set_wol,
d4a3a0fc 1190 .get_strings = rtl8169_get_strings,
b9f2c044 1191 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1192 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1193};
1194
07d3f51f
FR		 1195static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1196 int bitnum, int bitval)
1da177e4
LT		 1197{
1198 int val;
1199
1200 val = mdio_read(ioaddr, reg);
1201 val = (bitval == 1) ?
1202 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1203 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1204}
1205
07d3f51f
FR		 1206static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1207 void __iomem *ioaddr)
1da177e4 1208{
0e485150
FR		 1209 /*
1210 * The driver currently handles the 8168Bf and the 8168Be identically
1211 * but they can be identified more specifically through the test below
1212 * if needed:
1213 *
1214 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1215 *
1216 * Same thing for the 8101Eb and the 8101Ec:
1217 *
1218 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1219 */
1da177e4
LT		 1220 const struct {
1221 u32 mask;
e3cf0cc0 1222 u32 val;
1da177e4
LT		 1223 int mac_version;
1224 } mac_info[] = {
e3cf0cc0 1225 /* 8168B family. */
ef3386f0 1226 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
e3cf0cc0
FR		 1227 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1228 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1229 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1230 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1231 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1232 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1233
1234 /* 8168B family. */
1235 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1236 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1237 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1238 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1239
1240 /* 8101 family. */
2857ffb7
FR		 1241 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1242 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1243 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1244 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1245 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1246 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1247 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1248 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1249 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1250 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1251 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1252 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1253 /* FIXME: where did these entries come from ? -- FR */
1254 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1255 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1256
1257 /* 8110 family. */
1258 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1259 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1260 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1261 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1262 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1263 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1264
1265 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1266 }, *p = mac_info;
1267 u32 reg;
1268
e3cf0cc0
FR		 1269 reg = RTL_R32(TxConfig);
1270 while ((reg & p->mask) != p->val)
1da177e4
LT		 1271 p++;
1272 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1273
1274 if (p->mask == 0x00000000) {
1275 struct pci_dev *pdev = tp->pci_dev;
1276
1277 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1278 }
1da177e4
LT		 1279}
1280
1281static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1282{
bcf0bf90 1283 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1284}
1285
867763c1
FR		 1286struct phy_reg {
1287 u16 reg;
1288 u16 val;
1289};
1290
1291static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1292{
1293 while (len-- > 0) {
1294 mdio_write(ioaddr, regs->reg, regs->val);
1295 regs++;
1296 }
1297}
1298
5615d9f1 1299static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1300{
1da177e4
LT		 1301 struct {
1302 u16 regs[5]; /* Beware of bit-sign propagation */
1303 } phy_magic[5] = { {
1304 { 0x0000, //w 4 15 12 0
1305 0x00a1, //w 3 15 0 00a1
1306 0x0008, //w 2 15 0 0008
1307 0x1020, //w 1 15 0 1020
1308 0x1000 } },{ //w 0 15 0 1000
1309 { 0x7000, //w 4 15 12 7
1310 0xff41, //w 3 15 0 ff41
1311 0xde60, //w 2 15 0 de60
1312 0x0140, //w 1 15 0 0140
1313 0x0077 } },{ //w 0 15 0 0077
1314 { 0xa000, //w 4 15 12 a
1315 0xdf01, //w 3 15 0 df01
1316 0xdf20, //w 2 15 0 df20
1317 0xff95, //w 1 15 0 ff95
1318 0xfa00 } },{ //w 0 15 0 fa00
1319 { 0xb000, //w 4 15 12 b
1320 0xff41, //w 3 15 0 ff41
1321 0xde20, //w 2 15 0 de20
1322 0x0140, //w 1 15 0 0140
1323 0x00bb } },{ //w 0 15 0 00bb
1324 { 0xf000, //w 4 15 12 f
1325 0xdf01, //w 3 15 0 df01
1326 0xdf20, //w 2 15 0 df20
1327 0xff95, //w 1 15 0 ff95
1328 0xbf00 } //w 0 15 0 bf00
1329 }
1330 }, *p = phy_magic;
07d3f51f 1331 unsigned int i;
1da177e4 1332
a441d7b6
FR		 1333 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1334 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1335 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1336 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1337
1338 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1339 int val, pos = 4;
1340
1341 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1342 mdio_write(ioaddr, pos, val);
1343 while (--pos >= 0)
1344 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1345 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1346 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1347 }
a441d7b6 1348 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1349}
1350
5615d9f1
FR		 1351static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1352{
a441d7b6
FR		 1353 struct phy_reg phy_reg_init[] = {
1354 { 0x1f, 0x0002 },
1355 { 0x01, 0x90d0 },
1356 { 0x1f, 0x0000 }
1357 };
1358
1359 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1360}
1361
236b8082
FR		 1362static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1363{
1364 struct phy_reg phy_reg_init[] = {
1365 { 0x10, 0xf41b },
1366 { 0x1f, 0x0000 }
1367 };
1368
1369 mdio_write(ioaddr, 0x1f, 0x0001);
1370 mdio_patch(ioaddr, 0x16, 1 << 0);
1371
1372 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1373}
1374
1375static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1376{
1377 struct phy_reg phy_reg_init[] = {
1378 { 0x1f, 0x0001 },
1379 { 0x10, 0xf41b },
1380 { 0x1f, 0x0000 }
1381 };
1382
1383 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1384}
1385
ef3386f0 1386static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1387{
1388 struct phy_reg phy_reg_init[] = {
1389 { 0x1f, 0x0000 },
1390 { 0x1d, 0x0f00 },
1391 { 0x1f, 0x0002 },
1392 { 0x0c, 0x1ec8 },
1393 { 0x1f, 0x0000 }
1394 };
1395
1396 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1397}
1398
ef3386f0
FR		 1399static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1400{
1401 struct phy_reg phy_reg_init[] = {
1402 { 0x1f, 0x0001 },
1403 { 0x1d, 0x3d98 },
1404 { 0x1f, 0x0000 }
1405 };
1406
1407 mdio_write(ioaddr, 0x1f, 0x0000);
1408 mdio_patch(ioaddr, 0x14, 1 << 5);
1409 mdio_patch(ioaddr, 0x0d, 1 << 5);
1410
1411 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1412}
1413
219a1e9d 1414static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1415{
1416 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1417 { 0x1f, 0x0001 },
1418 { 0x12, 0x2300 },
867763c1
FR		 1419 { 0x1f, 0x0002 },
1420 { 0x00, 0x88d4 },
1421 { 0x01, 0x82b1 },
1422 { 0x03, 0x7002 },
1423 { 0x08, 0x9e30 },
1424 { 0x09, 0x01f0 },
1425 { 0x0a, 0x5500 },
1426 { 0x0c, 0x00c8 },
1427 { 0x1f, 0x0003 },
1428 { 0x12, 0xc096 },
1429 { 0x16, 0x000a },
f50d4275
FR		 1430 { 0x1f, 0x0000 },
1431 { 0x1f, 0x0000 },
1432 { 0x09, 0x2000 },
1433 { 0x09, 0x0000 }
867763c1
FR		 1434 };
1435
1436 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1437
1438 mdio_patch(ioaddr, 0x14, 1 << 5);
1439 mdio_patch(ioaddr, 0x0d, 1 << 5);
1440 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1441}
1442
219a1e9d 1443static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1444{
1445 struct phy_reg phy_reg_init[] = {
f50d4275 1446 { 0x1f, 0x0001 },
7da97ec9 1447 { 0x12, 0x2300 },
f50d4275
FR		 1448 { 0x03, 0x802f },
1449 { 0x02, 0x4f02 },
1450 { 0x01, 0x0409 },
1451 { 0x00, 0xf099 },
1452 { 0x04, 0x9800 },
1453 { 0x04, 0x9000 },
1454 { 0x1d, 0x3d98 },
7da97ec9
FR		 1455 { 0x1f, 0x0002 },
1456 { 0x0c, 0x7eb8 },
f50d4275
FR		 1457 { 0x06, 0x0761 },
1458 { 0x1f, 0x0003 },
1459 { 0x16, 0x0f0a },
7da97ec9
FR		 1460 { 0x1f, 0x0000 }
1461 };
1462
1463 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1464
1465 mdio_patch(ioaddr, 0x16, 1 << 0);
1466 mdio_patch(ioaddr, 0x14, 1 << 5);
1467 mdio_patch(ioaddr, 0x0d, 1 << 5);
1468 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1469}
1470
197ff761
FR		 1471static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1472{
1473 struct phy_reg phy_reg_init[] = {
1474 { 0x1f, 0x0001 },
1475 { 0x12, 0x2300 },
1476 { 0x1d, 0x3d98 },
1477 { 0x1f, 0x0002 },
1478 { 0x0c, 0x7eb8 },
1479 { 0x06, 0x5461 },
1480 { 0x1f, 0x0003 },
1481 { 0x16, 0x0f0a },
1482 { 0x1f, 0x0000 }
1483 };
1484
1485 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1486
1487 mdio_patch(ioaddr, 0x16, 1 << 0);
1488 mdio_patch(ioaddr, 0x14, 1 << 5);
1489 mdio_patch(ioaddr, 0x0d, 1 << 5);
1490 mdio_write(ioaddr, 0x1f, 0x0000);
1491}
1492
6fb07058
FR		 1493static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1494{
1495 rtl8168c_3_hw_phy_config(ioaddr);
1496}
1497
2857ffb7
FR		 1498static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1499{
1500 struct phy_reg phy_reg_init[] = {
1501 { 0x1f, 0x0003 },
1502 { 0x08, 0x441d },
1503 { 0x01, 0x9100 },
1504 { 0x1f, 0x0000 }
1505 };
1506
1507 mdio_write(ioaddr, 0x1f, 0x0000);
1508 mdio_patch(ioaddr, 0x11, 1 << 12);
1509 mdio_patch(ioaddr, 0x19, 1 << 13);
1510
1511 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1512}
1513
5615d9f1
FR		 1514static void rtl_hw_phy_config(struct net_device *dev)
1515{
1516 struct rtl8169_private *tp = netdev_priv(dev);
1517 void __iomem *ioaddr = tp->mmio_addr;
1518
1519 rtl8169_print_mac_version(tp);
1520
1521 switch (tp->mac_version) {
1522 case RTL_GIGA_MAC_VER_01:
1523 break;
1524 case RTL_GIGA_MAC_VER_02:
1525 case RTL_GIGA_MAC_VER_03:
1526 rtl8169s_hw_phy_config(ioaddr);
1527 break;
1528 case RTL_GIGA_MAC_VER_04:
1529 rtl8169sb_hw_phy_config(ioaddr);
1530 break;
2857ffb7
FR		 1531 case RTL_GIGA_MAC_VER_07:
1532 case RTL_GIGA_MAC_VER_08:
1533 case RTL_GIGA_MAC_VER_09:
1534 rtl8102e_hw_phy_config(ioaddr);
1535 break;
236b8082
FR		 1536 case RTL_GIGA_MAC_VER_11:
1537 rtl8168bb_hw_phy_config(ioaddr);
1538 break;
1539 case RTL_GIGA_MAC_VER_12:
1540 rtl8168bef_hw_phy_config(ioaddr);
1541 break;
1542 case RTL_GIGA_MAC_VER_17:
1543 rtl8168bef_hw_phy_config(ioaddr);
1544 break;
867763c1 1545 case RTL_GIGA_MAC_VER_18:
ef3386f0 1546 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1547 break;
1548 case RTL_GIGA_MAC_VER_19:
219a1e9d 1549 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1550 break;
7da97ec9 1551 case RTL_GIGA_MAC_VER_20:
219a1e9d 1552 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1553 break;
197ff761
FR		 1554 case RTL_GIGA_MAC_VER_21:
1555 rtl8168c_3_hw_phy_config(ioaddr);
1556 break;
6fb07058
FR		 1557 case RTL_GIGA_MAC_VER_22:
1558 rtl8168c_4_hw_phy_config(ioaddr);
1559 break;
ef3386f0
FR		 1560 case RTL_GIGA_MAC_VER_23:
1561 rtl8168cp_2_hw_phy_config(ioaddr);
1562 break;
1563
5615d9f1
FR		 1564 default:
1565 break;
1566 }
1567}
1568
1da177e4
LT		 1569static void rtl8169_phy_timer(unsigned long __opaque)
1570{
1571 struct net_device *dev = (struct net_device *)__opaque;
1572 struct rtl8169_private *tp = netdev_priv(dev);
1573 struct timer_list *timer = &tp->timer;
1574 void __iomem *ioaddr = tp->mmio_addr;
1575 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1576
bcf0bf90 1577 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1578
64e4bfb4 1579 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1580 return;
1581
1582 spin_lock_irq(&tp->lock);
1583
1584 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1585 /*
1da177e4
LT		 1586 * A busy loop could burn quite a few cycles on nowadays CPU.
1587 * Let's delay the execution of the timer for a few ticks.
1588 */
1589 timeout = HZ/10;
1590 goto out_mod_timer;
1591 }
1592
1593 if (tp->link_ok(ioaddr))
1594 goto out_unlock;
1595
b57b7e5a
SH		 1596 if (netif_msg_link(tp))
1597 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1598
1599 tp->phy_reset_enable(ioaddr);
1600
1601out_mod_timer:
1602 mod_timer(timer, jiffies + timeout);
1603out_unlock:
1604 spin_unlock_irq(&tp->lock);
1605}
1606
1607static inline void rtl8169_delete_timer(struct net_device *dev)
1608{
1609 struct rtl8169_private *tp = netdev_priv(dev);
1610 struct timer_list *timer = &tp->timer;
1611
e179bb7b 1612 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1613 return;
1614
1615 del_timer_sync(timer);
1616}
1617
1618static inline void rtl8169_request_timer(struct net_device *dev)
1619{
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 struct timer_list *timer = &tp->timer;
1622
e179bb7b 1623 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1624 return;
1625
2efa53f3 1626 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1627}
1628
1629#ifdef CONFIG_NET_POLL_CONTROLLER
1630/*
1631 * Polling 'interrupt' - used by things like netconsole to send skbs
1632 * without having to re-enable interrupts. It's not called while
1633 * the interrupt routine is executing.
1634 */
1635static void rtl8169_netpoll(struct net_device *dev)
1636{
1637 struct rtl8169_private *tp = netdev_priv(dev);
1638 struct pci_dev *pdev = tp->pci_dev;
1639
1640 disable_irq(pdev->irq);
7d12e780 1641 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1642 enable_irq(pdev->irq);
1643}
1644#endif
1645
1646static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1647 void __iomem *ioaddr)
1648{
1649 iounmap(ioaddr);
1650 pci_release_regions(pdev);
1651 pci_disable_device(pdev);
1652 free_netdev(dev);
1653}
1654
bf793295
FR		 1655static void rtl8169_phy_reset(struct net_device *dev,
1656 struct rtl8169_private *tp)
1657{
1658 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1659 unsigned int i;
bf793295
FR		 1660
1661 tp->phy_reset_enable(ioaddr);
1662 for (i = 0; i < 100; i++) {
1663 if (!tp->phy_reset_pending(ioaddr))
1664 return;
1665 msleep(1);
1666 }
1667 if (netif_msg_link(tp))
1668 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1669}
1670
4ff96fa6
FR		 1671static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1672{
1673 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1674
5615d9f1 1675 rtl_hw_phy_config(dev);
4ff96fa6 1676
77332894
MS		 1677 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1678 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1679 RTL_W8(0x82, 0x01);
1680 }
4ff96fa6 1681
6dccd16b
FR		 1682 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1683
1684 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1685 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1686
bcf0bf90 1687 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1688 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1689 RTL_W8(0x82, 0x01);
1690 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1691 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1692 }
1693
bf793295
FR		 1694 rtl8169_phy_reset(dev, tp);
1695
901dda2b
FR		 1696 /*
1697 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1698 * only 8101. Don't panic.
1699 */
1700 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1701
1702 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1703 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1704}
1705
773d2021
FR		 1706static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1707{
1708 void __iomem *ioaddr = tp->mmio_addr;
1709 u32 high;
1710 u32 low;
1711
1712 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1713 high = addr[4] | (addr[5] << 8);
1714
1715 spin_lock_irq(&tp->lock);
1716
1717 RTL_W8(Cfg9346, Cfg9346_Unlock);
1718 RTL_W32(MAC0, low);
1719 RTL_W32(MAC4, high);
1720 RTL_W8(Cfg9346, Cfg9346_Lock);
1721
1722 spin_unlock_irq(&tp->lock);
1723}
1724
1725static int rtl_set_mac_address(struct net_device *dev, void *p)
1726{
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728 struct sockaddr *addr = p;
1729
1730 if (!is_valid_ether_addr(addr->sa_data))
1731 return -EADDRNOTAVAIL;
1732
1733 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1734
1735 rtl_rar_set(tp, dev->dev_addr);
1736
1737 return 0;
1738}
1739
5f787a1a
FR		 1740static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1741{
1742 struct rtl8169_private *tp = netdev_priv(dev);
1743 struct mii_ioctl_data *data = if_mii(ifr);
1744
1745 if (!netif_running(dev))
1746 return -ENODEV;
1747
1748 switch (cmd) {
1749 case SIOCGMIIPHY:
1750 data->phy_id = 32; /* Internal PHY */
1751 return 0;
1752
1753 case SIOCGMIIREG:
1754 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1755 return 0;
1756
1757 case SIOCSMIIREG:
1758 if (!capable(CAP_NET_ADMIN))
1759 return -EPERM;
1760 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1761 return 0;
1762 }
1763 return -EOPNOTSUPP;
1764}
1765
0e485150
FR		 1766static const struct rtl_cfg_info {
1767 void (*hw_start)(struct net_device *);
1768 unsigned int region;
1769 unsigned int align;
1770 u16 intr_event;
1771 u16 napi_event;
ccdffb9a 1772 unsigned features;
0e485150
FR		 1773} rtl_cfg_infos [] = {
1774 [RTL_CFG_0] = {
1775 .hw_start = rtl_hw_start_8169,
1776 .region = 1,
e9f63f30 1777 .align = 0,
0e485150
FR		 1778 .intr_event = SYSErr | LinkChg | RxOverflow |
1779 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1780 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1781 .features = RTL_FEATURE_GMII
0e485150
FR		 1782 },
1783 [RTL_CFG_1] = {
1784 .hw_start = rtl_hw_start_8168,
1785 .region = 2,
1786 .align = 8,
1787 .intr_event = SYSErr | LinkChg | RxOverflow |
1788 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1789 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1790 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1791 },
1792 [RTL_CFG_2] = {
1793 .hw_start = rtl_hw_start_8101,
1794 .region = 2,
1795 .align = 8,
1796 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1797 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1798 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1799 .features = RTL_FEATURE_MSI
0e485150
FR		 1800 }
1801};
1802
fbac58fc
FR		 1803/* Cfg9346_Unlock assumed. */
1804static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1805 const struct rtl_cfg_info *cfg)
1806{
1807 unsigned msi = 0;
1808 u8 cfg2;
1809
1810 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1811 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1812 if (pci_enable_msi(pdev)) {
1813 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1814 } else {
1815 cfg2 |= MSIEnable;
1816 msi = RTL_FEATURE_MSI;
1817 }
1818 }
1819 RTL_W8(Config2, cfg2);
1820 return msi;
1821}
1822
1823static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1824{
1825 if (tp->features & RTL_FEATURE_MSI) {
1826 pci_disable_msi(pdev);
1827 tp->features &= ~RTL_FEATURE_MSI;
1828 }
1829}
1830
7bf6bf48
IV		 1831static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1832{
1833 int ret, count = 100;
1834 u16 status = 0;
1835 u32 value;
1836
1837 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1838 if (ret < 0)
1839 return ret;
1840
1841 do {
1842 udelay(10);
1843 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1844 if (ret < 0)
1845 return ret;
1846 } while (!(status & PCI_VPD_ADDR_F) && --count);
1847
1848 if (!(status & PCI_VPD_ADDR_F))
1849 return -ETIMEDOUT;
1850
1851 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1852 if (ret < 0)
1853 return ret;
1854
1855 *val = cpu_to_le32(value);
1856
1857 return 0;
1858}
1859
1860static void rtl_init_mac_address(struct rtl8169_private *tp,
1861 void __iomem *ioaddr)
1862{
1863 struct pci_dev *pdev = tp->pci_dev;
1864 u8 cfg1;
1865 int vpd_cap;
1866 u8 mac[8];
1867 DECLARE_MAC_BUF(buf);
1868
1869 cfg1 = RTL_R8(Config1);
1870 if (!(cfg1 & VPD)) {
1871 dprintk("VPD access not enabled, enabling\n");
1872 RTL_W8(Cfg9346, Cfg9346_Unlock);
1873 RTL_W8(Config1, cfg1 | VPD);
1874 RTL_W8(Cfg9346, Cfg9346_Lock);
1875 }
1876
1877 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1878 if (!vpd_cap)
1879 return;
1880
1881 /* MAC address is stored in EEPROM at offset 0x0e
1882 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1883 * address as defined in the PCI 2.2 Specifications, but the VPD data
1884 * is always consecutive 4-byte data starting from the VPD address
1885 * specified."
1886 */
1887 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1888 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1889 dprintk("Reading MAC address from EEPROM failed\n");
1890 return;
1891 }
1892
1893 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1894
1895 /* Write MAC address */
1896 rtl_rar_set(tp, mac);
1897}
1898
1da177e4 1899static int __devinit
4ff96fa6 1900rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1901{
0e485150
FR		 1902 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1903 const unsigned int region = cfg->region;
1da177e4 1904 struct rtl8169_private *tp;
ccdffb9a 1905 struct mii_if_info *mii;
4ff96fa6
FR		 1906 struct net_device *dev;
1907 void __iomem *ioaddr;
07d3f51f
FR		 1908 unsigned int i;
1909 int rc;
1da177e4 1910
4ff96fa6
FR		 1911 if (netif_msg_drv(&debug)) {
1912 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1913 MODULENAME, RTL8169_VERSION);
1914 }
1da177e4 1915
1da177e4 1916 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1917 if (!dev) {
b57b7e5a 1918 if (netif_msg_drv(&debug))
9b91cf9d 1919 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1920 rc = -ENOMEM;
1921 goto out;
1da177e4
LT		 1922 }
1923
1da177e4
LT		 1924 SET_NETDEV_DEV(dev, &pdev->dev);
1925 tp = netdev_priv(dev);
c4028958 1926 tp->dev = dev;
21e197f2 1927 tp->pci_dev = pdev;
b57b7e5a 1928 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1929
ccdffb9a
FR		 1930 mii = &tp->mii;
1931 mii->dev = dev;
1932 mii->mdio_read = rtl_mdio_read;
1933 mii->mdio_write = rtl_mdio_write;
1934 mii->phy_id_mask = 0x1f;
1935 mii->reg_num_mask = 0x1f;
1936 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1937
1da177e4
LT		 1938 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1939 rc = pci_enable_device(pdev);
b57b7e5a 1940 if (rc < 0) {
2e8a538d 1941 if (netif_msg_probe(tp))
9b91cf9d 1942 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1943 goto err_out_free_dev_1;
1da177e4
LT		 1944 }
1945
1946 rc = pci_set_mwi(pdev);
1947 if (rc < 0)
4ff96fa6 1948 goto err_out_disable_2;
1da177e4 1949
1da177e4 1950 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1951 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1952 if (netif_msg_probe(tp)) {
9b91cf9d 1953 dev_err(&pdev->dev,
bcf0bf90
FR		 1954 "region #%d not an MMIO resource, aborting\n",
1955 region);
4ff96fa6 1956 }
1da177e4 1957 rc = -ENODEV;
4ff96fa6 1958 goto err_out_mwi_3;
1da177e4 1959 }
4ff96fa6 1960
1da177e4 1961 /* check for weird/broken PCI region reporting */
bcf0bf90 1962 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1963 if (netif_msg_probe(tp)) {
9b91cf9d 1964 dev_err(&pdev->dev,
4ff96fa6
FR		 1965 "Invalid PCI region size(s), aborting\n");
1966 }
1da177e4 1967 rc = -ENODEV;
4ff96fa6 1968 goto err_out_mwi_3;
1da177e4
LT		 1969 }
1970
1971 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1972 if (rc < 0) {
2e8a538d 1973 if (netif_msg_probe(tp))
9b91cf9d 1974 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1975 goto err_out_mwi_3;
1da177e4
LT		 1976 }
1977
1978 tp->cp_cmd = PCIMulRW | RxChkSum;
1979
1980 if ((sizeof(dma_addr_t) > 4) &&
1981 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1982 tp->cp_cmd |= PCIDAC;
1983 dev->features |= NETIF_F_HIGHDMA;
1984 } else {
1985 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1986 if (rc < 0) {
4ff96fa6 1987 if (netif_msg_probe(tp)) {
9b91cf9d 1988 dev_err(&pdev->dev,
4ff96fa6
FR		 1989 "DMA configuration failed.\n");
1990 }
1991 goto err_out_free_res_4;
1da177e4
LT		 1992 }
1993 }
1994
1995 pci_set_master(pdev);
1996
1997 /* ioremap MMIO region */
bcf0bf90 1998 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1999 if (!ioaddr) {
b57b7e5a 2000 if (netif_msg_probe(tp))
9b91cf9d 2001 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2002 rc = -EIO;
4ff96fa6 2003 goto err_out_free_res_4;
1da177e4
LT		 2004 }
2005
9c14ceaf
FR		 2006 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2007 if (!tp->pcie_cap && netif_msg_probe(tp))
2008 dev_info(&pdev->dev, "no PCI Express capability\n");
2009
1da177e4
LT		 2010 /* Unneeded ? Don't mess with Mrs. Murphy. */
2011 rtl8169_irq_mask_and_ack(ioaddr);
2012
2013 /* Soft reset the chip. */
2014 RTL_W8(ChipCmd, CmdReset);
2015
2016 /* Check that the chip has finished the reset. */
07d3f51f 2017 for (i = 0; i < 100; i++) {
1da177e4
LT		 2018 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2019 break;
b518fa8e 2020 msleep_interruptible(1);
1da177e4
LT		 2021 }
2022
2023 /* Identify chip attached to board */
2024 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 2025
2026 rtl8169_print_mac_version(tp);
1da177e4 2027
cee60c37 2028 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2029 if (tp->mac_version == rtl_chip_info[i].mac_version)
2030 break;
2031 }
cee60c37 2032 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 2033 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 2034 if (netif_msg_probe(tp)) {
2e8a538d 2035 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 2036 "unknown chip version, assuming %s\n",
2037 rtl_chip_info[0].name);
b57b7e5a 2038 }
cee60c37 2039 i = 0;
1da177e4
LT		 2040 }
2041 tp->chipset = i;
2042
5d06a99f
FR		 2043 RTL_W8(Cfg9346, Cfg9346_Unlock);
2044 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2045 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2046 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2047 tp->features |= RTL_FEATURE_WOL;
2048 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2049 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2050 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2051 RTL_W8(Cfg9346, Cfg9346_Lock);
2052
66ec5d4f
FR		 2053 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2054 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2055 tp->set_speed = rtl8169_set_speed_tbi;
2056 tp->get_settings = rtl8169_gset_tbi;
2057 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2058 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2059 tp->link_ok = rtl8169_tbi_link_ok;
2060
64e4bfb4 2061 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2062 } else {
2063 tp->set_speed = rtl8169_set_speed_xmii;
2064 tp->get_settings = rtl8169_gset_xmii;
2065 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2066 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2067 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 2068
2069 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 2070 }
2071
df58ef51
FR		 2072 spin_lock_init(&tp->lock);
2073
7bf6bf48
IV		 2074 rtl_init_mac_address(tp, ioaddr);
2075
2076 /* Get MAC address */
1da177e4
LT		 2077 for (i = 0; i < MAC_ADDR_LEN; i++)
2078 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2079 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 2080
2081 dev->open = rtl8169_open;
2082 dev->hard_start_xmit = rtl8169_start_xmit;
2083 dev->get_stats = rtl8169_get_stats;
2084 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2085 dev->stop = rtl8169_close;
2086 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 2087 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 2088 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2089 dev->irq = pdev->irq;
2090 dev->base_addr = (unsigned long) ioaddr;
2091 dev->change_mtu = rtl8169_change_mtu;
773d2021 2092 dev->set_mac_address = rtl_set_mac_address;
1da177e4 2093
bea3348e 2094 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2095
2096#ifdef CONFIG_R8169_VLAN
2097 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2098 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 2099#endif
2100
2101#ifdef CONFIG_NET_POLL_CONTROLLER
2102 dev->poll_controller = rtl8169_netpoll;
2103#endif
2104
2105 tp->intr_mask = 0xffff;
1da177e4 2106 tp->mmio_addr = ioaddr;
0e485150
FR		 2107 tp->align = cfg->align;
2108 tp->hw_start = cfg->hw_start;
2109 tp->intr_event = cfg->intr_event;
2110 tp->napi_event = cfg->napi_event;
1da177e4 2111
2efa53f3
FR		 2112 init_timer(&tp->timer);
2113 tp->timer.data = (unsigned long) dev;
2114 tp->timer.function = rtl8169_phy_timer;
2115
1da177e4 2116 rc = register_netdev(dev);
4ff96fa6 2117 if (rc < 0)
fbac58fc 2118 goto err_out_msi_5;
1da177e4
LT		 2119
2120 pci_set_drvdata(pdev, dev);
2121
b57b7e5a 2122 if (netif_msg_probe(tp)) {
96b9709c
FR		 2123 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2124
b57b7e5a
SH		 2125 printk(KERN_INFO "%s: %s at 0x%lx, "
2126 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2127 "XID %08x IRQ %d\n",
b57b7e5a 2128 dev->name,
bcf0bf90 2129 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2130 dev->base_addr,
2131 dev->dev_addr[0], dev->dev_addr[1],
2132 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2133 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2134 }
1da177e4 2135
4ff96fa6 2136 rtl8169_init_phy(dev, tp);
8b76ab39 2137 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2138
4ff96fa6
FR		 2139out:
2140 return rc;
1da177e4 2141
fbac58fc
FR		 2142err_out_msi_5:
2143 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2144 iounmap(ioaddr);
2145err_out_free_res_4:
2146 pci_release_regions(pdev);
2147err_out_mwi_3:
2148 pci_clear_mwi(pdev);
2149err_out_disable_2:
2150 pci_disable_device(pdev);
2151err_out_free_dev_1:
2152 free_netdev(dev);
2153 goto out;
1da177e4
LT		 2154}
2155
07d3f51f 2156static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2157{
2158 struct net_device *dev = pci_get_drvdata(pdev);
2159 struct rtl8169_private *tp = netdev_priv(dev);
2160
eb2a021c
FR		 2161 flush_scheduled_work();
2162
1da177e4 2163 unregister_netdev(dev);
fbac58fc 2164 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2165 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2166 pci_set_drvdata(pdev, NULL);
2167}
2168
1da177e4
LT		 2169static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2170 struct net_device *dev)
2171{
2172 unsigned int mtu = dev->mtu;
2173
2174 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2175}
2176
2177static int rtl8169_open(struct net_device *dev)
2178{
2179 struct rtl8169_private *tp = netdev_priv(dev);
2180 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2181 int retval = -ENOMEM;
1da177e4 2182
1da177e4 2183
99f252b0 2184 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2185
2186 /*
2187 * Rx and Tx desscriptors needs 256 bytes alignment.
2188 * pci_alloc_consistent provides more.
2189 */
2190 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2191 &tp->TxPhyAddr);
2192 if (!tp->TxDescArray)
99f252b0 2193 goto out;
1da177e4
LT		 2194
2195 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2196 &tp->RxPhyAddr);
2197 if (!tp->RxDescArray)
99f252b0 2198 goto err_free_tx_0;
1da177e4
LT		 2199
2200 retval = rtl8169_init_ring(dev);
2201 if (retval < 0)
99f252b0 2202 goto err_free_rx_1;
1da177e4 2203
c4028958 2204 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2205
99f252b0
FR		 2206 smp_mb();
2207
fbac58fc
FR		 2208 retval = request_irq(dev->irq, rtl8169_interrupt,
2209 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2210 dev->name, dev);
2211 if (retval < 0)
2212 goto err_release_ring_2;
2213
bea3348e 2214 napi_enable(&tp->napi);
bea3348e 2215
07ce4064 2216 rtl_hw_start(dev);
1da177e4
LT		 2217
2218 rtl8169_request_timer(dev);
2219
2220 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2221out:
2222 return retval;
2223
99f252b0
FR		 2224err_release_ring_2:
2225 rtl8169_rx_clear(tp);
2226err_free_rx_1:
1da177e4
LT		 2227 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2228 tp->RxPhyAddr);
99f252b0 2229err_free_tx_0:
1da177e4
LT		 2230 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2231 tp->TxPhyAddr);
1da177e4
LT		 2232 goto out;
2233}
2234
2235static void rtl8169_hw_reset(void __iomem *ioaddr)
2236{
2237 /* Disable interrupts */
2238 rtl8169_irq_mask_and_ack(ioaddr);
2239
2240 /* Reset the chipset */
2241 RTL_W8(ChipCmd, CmdReset);
2242
2243 /* PCI commit */
2244 RTL_R8(ChipCmd);
2245}
2246
7f796d83 2247static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2248{
2249 void __iomem *ioaddr = tp->mmio_addr;
2250 u32 cfg = rtl8169_rx_config;
2251
2252 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2253 RTL_W32(RxConfig, cfg);
2254
2255 /* Set DMA burst size and Interframe Gap Time */
2256 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2257 (InterFrameGap << TxInterFrameGapShift));
2258}
2259
07ce4064 2260static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2261{
2262 struct rtl8169_private *tp = netdev_priv(dev);
2263 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2264 unsigned int i;
1da177e4
LT		 2265
2266 /* Soft reset the chip. */
2267 RTL_W8(ChipCmd, CmdReset);
2268
2269 /* Check that the chip has finished the reset. */
07d3f51f 2270 for (i = 0; i < 100; i++) {
1da177e4
LT		 2271 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2272 break;
b518fa8e 2273 msleep_interruptible(1);
1da177e4
LT		 2274 }
2275
07ce4064
FR		 2276 tp->hw_start(dev);
2277
07ce4064
FR		 2278 netif_start_queue(dev);
2279}
2280
2281
7f796d83
FR		 2282static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2283 void __iomem *ioaddr)
2284{
2285 /*
2286 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2287 * register to be written before TxDescAddrLow to work.
2288 * Switching from MMIO to I/O access fixes the issue as well.
2289 */
2290 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2291 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2292 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2293 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2294}
2295
2296static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2297{
2298 u16 cmd;
2299
2300 cmd = RTL_R16(CPlusCmd);
2301 RTL_W16(CPlusCmd, cmd);
2302 return cmd;
2303}
2304
2305static void rtl_set_rx_max_size(void __iomem *ioaddr)
2306{
2307 /* Low hurts. Let's disable the filtering. */
2308 RTL_W16(RxMaxSize, 16383);
2309}
2310
6dccd16b
FR		 2311static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2312{
2313 struct {
2314 u32 mac_version;
2315 u32 clk;
2316 u32 val;
2317 } cfg2_info [] = {
2318 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2319 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2320 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2321 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2322 }, *p = cfg2_info;
2323 unsigned int i;
2324 u32 clk;
2325
2326 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2327 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2328 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2329 RTL_W32(0x7c, p->val);
2330 break;
2331 }
2332 }
2333}
2334
07ce4064
FR		 2335static void rtl_hw_start_8169(struct net_device *dev)
2336{
2337 struct rtl8169_private *tp = netdev_priv(dev);
2338 void __iomem *ioaddr = tp->mmio_addr;
2339 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2340
9cb427b6
FR		 2341 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2342 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2343 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2344 }
2345
1da177e4 2346 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2347 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2348 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2349 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2350 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2351 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2352
1da177e4
LT		 2353 RTL_W8(EarlyTxThres, EarlyTxThld);
2354
7f796d83 2355 rtl_set_rx_max_size(ioaddr);
1da177e4 2356
c946b304
FR		 2357 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2358 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2359 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2360 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2361 rtl_set_rx_tx_config_registers(tp);
1da177e4 2362
7f796d83 2363 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2364
bcf0bf90
FR		 2365 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2366 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2367 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2368 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2369 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2370 }
2371
bcf0bf90
FR		 2372 RTL_W16(CPlusCmd, tp->cp_cmd);
2373
6dccd16b
FR		 2374 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2375
1da177e4
LT		 2376 /*
2377 * Undocumented corner. Supposedly:
2378 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2379 */
2380 RTL_W16(IntrMitigate, 0x0000);
2381
7f796d83 2382 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2383
c946b304
FR		 2384 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2385 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2386 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2387 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2388 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2389 rtl_set_rx_tx_config_registers(tp);
2390 }
2391
1da177e4 2392 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2393
2394 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2395 RTL_R8(IntrMask);
1da177e4
LT		 2396
2397 RTL_W32(RxMissed, 0);
2398
07ce4064 2399 rtl_set_rx_mode(dev);
1da177e4
LT		 2400
2401 /* no early-rx interrupts */
2402 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2403
2404 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2405 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2406}
1da177e4 2407
9c14ceaf 2408static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2409{
9c14ceaf
FR		 2410 struct net_device *dev = pci_get_drvdata(pdev);
2411 struct rtl8169_private *tp = netdev_priv(dev);
2412 int cap = tp->pcie_cap;
2413
2414 if (cap) {
2415 u16 ctl;
458a9f61 2416
9c14ceaf
FR		 2417 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2418 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2419 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2420 }
458a9f61
FR		 2421}
2422
dacf8154
FR		 2423static void rtl_csi_access_enable(void __iomem *ioaddr)
2424{
2425 u32 csi;
2426
2427 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2428 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2429}
2430
2431struct ephy_info {
2432 unsigned int offset;
2433 u16 mask;
2434 u16 bits;
2435};
2436
2437static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2438{
2439 u16 w;
2440
2441 while (len-- > 0) {
2442 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2443 rtl_ephy_write(ioaddr, e->offset, w);
2444 e++;
2445 }
2446}
2447
b726e493
FR		 2448static void rtl_disable_clock_request(struct pci_dev *pdev)
2449{
2450 struct net_device *dev = pci_get_drvdata(pdev);
2451 struct rtl8169_private *tp = netdev_priv(dev);
2452 int cap = tp->pcie_cap;
2453
2454 if (cap) {
2455 u16 ctl;
2456
2457 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2458 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2459 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2460 }
2461}
2462
2463#define R8168_CPCMD_QUIRK_MASK (\
2464 EnableBist | \
2465 Mac_dbgo_oe | \
2466 Force_half_dup | \
2467 Force_rxflow_en | \
2468 Force_txflow_en | \
2469 Cxpl_dbg_sel | \
2470 ASF | \
2471 PktCntrDisable | \
2472 Mac_dbgo_sel)
2473
219a1e9d
FR		 2474static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2475{
b726e493
FR		 2476 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2477
2478 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2479
2e68ae44
FR		 2480 rtl_tx_performance_tweak(pdev,
2481 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2482}
2483
2484static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2485{
2486 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2487
2488 RTL_W8(EarlyTxThres, EarlyTxThld);
2489
2490 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2491}
2492
2493static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2494{
b726e493
FR		 2495 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2496
2497 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2498
219a1e9d 2499 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2500
2501 rtl_disable_clock_request(pdev);
2502
2503 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2504}
2505
ef3386f0 2506static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2507{
b726e493
FR		 2508 static struct ephy_info e_info_8168cp[] = {
2509 { 0x01, 0, 0x0001 },
2510 { 0x02, 0x0800, 0x1000 },
2511 { 0x03, 0, 0x0042 },
2512 { 0x06, 0x0080, 0x0000 },
2513 { 0x07, 0, 0x2000 }
2514 };
2515
2516 rtl_csi_access_enable(ioaddr);
2517
2518 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2519
219a1e9d
FR		 2520 __rtl_hw_start_8168cp(ioaddr, pdev);
2521}
2522
ef3386f0
FR		 2523static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2524{
2525 rtl_csi_access_enable(ioaddr);
2526
2527 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2528
2529 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2530
2531 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2532}
2533
219a1e9d
FR		 2534static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2535{
b726e493
FR		 2536 static struct ephy_info e_info_8168c_1[] = {
2537 { 0x02, 0x0800, 0x1000 },
2538 { 0x03, 0, 0x0002 },
2539 { 0x06, 0x0080, 0x0000 }
2540 };
2541
2542 rtl_csi_access_enable(ioaddr);
2543
2544 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2545
2546 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2547
219a1e9d
FR		 2548 __rtl_hw_start_8168cp(ioaddr, pdev);
2549}
2550
2551static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2552{
b726e493
FR		 2553 static struct ephy_info e_info_8168c_2[] = {
2554 { 0x01, 0, 0x0001 },
2555 { 0x03, 0x0400, 0x0220 }
2556 };
2557
2558 rtl_csi_access_enable(ioaddr);
2559
2560 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2561
219a1e9d
FR		 2562 __rtl_hw_start_8168cp(ioaddr, pdev);
2563}
2564
197ff761
FR		 2565static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2566{
2567 rtl_hw_start_8168c_2(ioaddr, pdev);
2568}
2569
6fb07058
FR		 2570static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2571{
2572 rtl_csi_access_enable(ioaddr);
2573
2574 __rtl_hw_start_8168cp(ioaddr, pdev);
2575}
2576
07ce4064
FR		 2577static void rtl_hw_start_8168(struct net_device *dev)
2578{
2dd99530
FR		 2579 struct rtl8169_private *tp = netdev_priv(dev);
2580 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2581 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2582
2583 RTL_W8(Cfg9346, Cfg9346_Unlock);
2584
2585 RTL_W8(EarlyTxThres, EarlyTxThld);
2586
2587 rtl_set_rx_max_size(ioaddr);
2588
0e485150 2589 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2590
2591 RTL_W16(CPlusCmd, tp->cp_cmd);
2592
0e485150 2593 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2594
0e485150
FR		 2595 /* Work around for RxFIFO overflow. */
2596 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2597 tp->intr_event |= RxFIFOOver | PCSTimeout;
2598 tp->intr_event &= ~RxOverflow;
2599 }
2600
2601 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2602
b8363901
FR		 2603 rtl_set_rx_mode(dev);
2604
2605 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2606 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2607
2608 RTL_R8(IntrMask);
2609
219a1e9d
FR		 2610 switch (tp->mac_version) {
2611 case RTL_GIGA_MAC_VER_11:
2612 rtl_hw_start_8168bb(ioaddr, pdev);
2613 break;
2614
2615 case RTL_GIGA_MAC_VER_12:
2616 case RTL_GIGA_MAC_VER_17:
2617 rtl_hw_start_8168bef(ioaddr, pdev);
2618 break;
2619
2620 case RTL_GIGA_MAC_VER_18:
ef3386f0 2621 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2622 break;
2623
2624 case RTL_GIGA_MAC_VER_19:
2625 rtl_hw_start_8168c_1(ioaddr, pdev);
2626 break;
2627
2628 case RTL_GIGA_MAC_VER_20:
2629 rtl_hw_start_8168c_2(ioaddr, pdev);
2630 break;
2631
197ff761
FR		 2632 case RTL_GIGA_MAC_VER_21:
2633 rtl_hw_start_8168c_3(ioaddr, pdev);
2634 break;
2635
6fb07058
FR		 2636 case RTL_GIGA_MAC_VER_22:
2637 rtl_hw_start_8168c_4(ioaddr, pdev);
2638 break;
2639
ef3386f0
FR		 2640 case RTL_GIGA_MAC_VER_23:
2641 rtl_hw_start_8168cp_2(ioaddr, pdev);
2642 break;
2643
219a1e9d
FR		 2644 default:
2645 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2646 dev->name, tp->mac_version);
2647 break;
2648 }
2dd99530 2649
0e485150
FR		 2650 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2651
b8363901
FR		 2652 RTL_W8(Cfg9346, Cfg9346_Lock);
2653
2dd99530 2654 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2655
0e485150 2656 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2657}
1da177e4 2658
2857ffb7
FR		 2659#define R810X_CPCMD_QUIRK_MASK (\
2660 EnableBist | \
2661 Mac_dbgo_oe | \
2662 Force_half_dup | \
2663 Force_half_dup | \
2664 Force_txflow_en | \
2665 Cxpl_dbg_sel | \
2666 ASF | \
2667 PktCntrDisable | \
2668 PCIDAC | \
2669 PCIMulRW)
2670
2671static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2672{
2673 static struct ephy_info e_info_8102e_1[] = {
2674 { 0x01, 0, 0x6e65 },
2675 { 0x02, 0, 0x091f },
2676 { 0x03, 0, 0xc2f9 },
2677 { 0x06, 0, 0xafb5 },
2678 { 0x07, 0, 0x0e00 },
2679 { 0x19, 0, 0xec80 },
2680 { 0x01, 0, 0x2e65 },
2681 { 0x01, 0, 0x6e65 }
2682 };
2683 u8 cfg1;
2684
2685 rtl_csi_access_enable(ioaddr);
2686
2687 RTL_W8(DBG_REG, FIX_NAK_1);
2688
2689 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2690
2691 RTL_W8(Config1,
2692 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2693 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2694
2695 cfg1 = RTL_R8(Config1);
2696 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2697 RTL_W8(Config1, cfg1 & ~LEDS0);
2698
2699 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2700
2701 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2702}
2703
2704static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2705{
2706 rtl_csi_access_enable(ioaddr);
2707
2708 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2709
2710 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2711 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2712
2713 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2714}
2715
2716static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2717{
2718 rtl_hw_start_8102e_2(ioaddr, pdev);
2719
2720 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2721}
2722
07ce4064
FR		 2723static void rtl_hw_start_8101(struct net_device *dev)
2724{
cdf1a608
FR		 2725 struct rtl8169_private *tp = netdev_priv(dev);
2726 void __iomem *ioaddr = tp->mmio_addr;
2727 struct pci_dev *pdev = tp->pci_dev;
2728
e3cf0cc0
FR		 2729 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2730 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2731 int cap = tp->pcie_cap;
2732
2733 if (cap) {
2734 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2735 PCI_EXP_DEVCTL_NOSNOOP_EN);
2736 }
cdf1a608
FR		 2737 }
2738
2857ffb7
FR		 2739 switch (tp->mac_version) {
2740 case RTL_GIGA_MAC_VER_07:
2741 rtl_hw_start_8102e_1(ioaddr, pdev);
2742 break;
2743
2744 case RTL_GIGA_MAC_VER_08:
2745 rtl_hw_start_8102e_3(ioaddr, pdev);
2746 break;
2747
2748 case RTL_GIGA_MAC_VER_09:
2749 rtl_hw_start_8102e_2(ioaddr, pdev);
2750 break;
cdf1a608
FR		 2751 }
2752
2753 RTL_W8(Cfg9346, Cfg9346_Unlock);
2754
2755 RTL_W8(EarlyTxThres, EarlyTxThld);
2756
2757 rtl_set_rx_max_size(ioaddr);
2758
2759 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2760
2761 RTL_W16(CPlusCmd, tp->cp_cmd);
2762
2763 RTL_W16(IntrMitigate, 0x0000);
2764
2765 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2766
2767 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2768 rtl_set_rx_tx_config_registers(tp);
2769
2770 RTL_W8(Cfg9346, Cfg9346_Lock);
2771
2772 RTL_R8(IntrMask);
2773
cdf1a608
FR		 2774 rtl_set_rx_mode(dev);
2775
0e485150
FR		 2776 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2777
cdf1a608 2778 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2779
0e485150 2780 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2781}
2782
2783static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2784{
2785 struct rtl8169_private *tp = netdev_priv(dev);
2786 int ret = 0;
2787
2788 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2789 return -EINVAL;
2790
2791 dev->mtu = new_mtu;
2792
2793 if (!netif_running(dev))
2794 goto out;
2795
2796 rtl8169_down(dev);
2797
2798 rtl8169_set_rxbufsize(tp, dev);
2799
2800 ret = rtl8169_init_ring(dev);
2801 if (ret < 0)
2802 goto out;
2803
bea3348e 2804 napi_enable(&tp->napi);
1da177e4 2805
07ce4064 2806 rtl_hw_start(dev);
1da177e4
LT		 2807
2808 rtl8169_request_timer(dev);
2809
2810out:
2811 return ret;
2812}
2813
2814static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2815{
95e0918d 2816 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2817 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2818}
2819
2820static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2821 struct sk_buff **sk_buff, struct RxDesc *desc)
2822{
2823 struct pci_dev *pdev = tp->pci_dev;
2824
2825 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2826 PCI_DMA_FROMDEVICE);
2827 dev_kfree_skb(*sk_buff);
2828 *sk_buff = NULL;
2829 rtl8169_make_unusable_by_asic(desc);
2830}
2831
2832static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2833{
2834 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2835
2836 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2837}
2838
2839static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2840 u32 rx_buf_sz)
2841{
2842 desc->addr = cpu_to_le64(mapping);
2843 wmb();
2844 rtl8169_mark_to_asic(desc, rx_buf_sz);
2845}
2846
15d31758
SH		 2847static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2848 struct net_device *dev,
2849 struct RxDesc *desc, int rx_buf_sz,
2850 unsigned int align)
1da177e4
LT		 2851{
2852 struct sk_buff *skb;
2853 dma_addr_t mapping;
e9f63f30 2854 unsigned int pad;
1da177e4 2855
e9f63f30
FR		 2856 pad = align ? align : NET_IP_ALIGN;
2857
2858 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2859 if (!skb)
2860 goto err_out;
2861
e9f63f30 2862 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2863
689be439 2864 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2865 PCI_DMA_FROMDEVICE);
2866
2867 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2868out:
15d31758 2869 return skb;
1da177e4
LT		 2870
2871err_out:
1da177e4
LT		 2872 rtl8169_make_unusable_by_asic(desc);
2873 goto out;
2874}
2875
2876static void rtl8169_rx_clear(struct rtl8169_private *tp)
2877{
07d3f51f 2878 unsigned int i;
1da177e4
LT		 2879
2880 for (i = 0; i < NUM_RX_DESC; i++) {
2881 if (tp->Rx_skbuff[i]) {
2882 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2883 tp->RxDescArray + i);
2884 }
2885 }
2886}
2887
2888static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2889 u32 start, u32 end)
2890{
2891 u32 cur;
5b0384f4 2892
4ae47c2d 2893 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2894 struct sk_buff *skb;
2895 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2896
4ae47c2d
FR		 2897 WARN_ON((s32)(end - cur) < 0);
2898
1da177e4
LT		 2899 if (tp->Rx_skbuff[i])
2900 continue;
bcf0bf90 2901
15d31758
SH		 2902 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2903 tp->RxDescArray + i,
2904 tp->rx_buf_sz, tp->align);
2905 if (!skb)
1da177e4 2906 break;
15d31758
SH		 2907
2908 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2909 }
2910 return cur - start;
2911}
2912
2913static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2914{
2915 desc->opts1 |= cpu_to_le32(RingEnd);
2916}
2917
2918static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2919{
2920 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2921}
2922
2923static int rtl8169_init_ring(struct net_device *dev)
2924{
2925 struct rtl8169_private *tp = netdev_priv(dev);
2926
2927 rtl8169_init_ring_indexes(tp);
2928
2929 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2930 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2931
2932 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2933 goto err_out;
2934
2935 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2936
2937 return 0;
2938
2939err_out:
2940 rtl8169_rx_clear(tp);
2941 return -ENOMEM;
2942}
2943
2944static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2945 struct TxDesc *desc)
2946{
2947 unsigned int len = tx_skb->len;
2948
2949 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2950 desc->opts1 = 0x00;
2951 desc->opts2 = 0x00;
2952 desc->addr = 0x00;
2953 tx_skb->len = 0;
2954}
2955
2956static void rtl8169_tx_clear(struct rtl8169_private *tp)
2957{
2958 unsigned int i;
2959
2960 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2961 unsigned int entry = i % NUM_TX_DESC;
2962 struct ring_info *tx_skb = tp->tx_skb + entry;
2963 unsigned int len = tx_skb->len;
2964
2965 if (len) {
2966 struct sk_buff *skb = tx_skb->skb;
2967
2968 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2969 tp->TxDescArray + entry);
2970 if (skb) {
2971 dev_kfree_skb(skb);
2972 tx_skb->skb = NULL;
2973 }
cebf8cc7 2974 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2975 }
2976 }
2977 tp->cur_tx = tp->dirty_tx = 0;
2978}
2979
c4028958 2980static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2981{
2982 struct rtl8169_private *tp = netdev_priv(dev);
2983
c4028958 2984 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2985 schedule_delayed_work(&tp->task, 4);
2986}
2987
2988static void rtl8169_wait_for_quiescence(struct net_device *dev)
2989{
2990 struct rtl8169_private *tp = netdev_priv(dev);
2991 void __iomem *ioaddr = tp->mmio_addr;
2992
2993 synchronize_irq(dev->irq);
2994
2995 /* Wait for any pending NAPI task to complete */
bea3348e 2996 napi_disable(&tp->napi);
1da177e4
LT		 2997
2998 rtl8169_irq_mask_and_ack(ioaddr);
2999
d1d08d12
DM		 3000 tp->intr_mask = 0xffff;
3001 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3002 napi_enable(&tp->napi);
1da177e4
LT		 3003}
3004
c4028958 3005static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3006{
c4028958
DH		 3007 struct rtl8169_private *tp =
3008 container_of(work, struct rtl8169_private, task.work);
3009 struct net_device *dev = tp->dev;
1da177e4
LT		 3010 int ret;
3011
eb2a021c
FR		 3012 rtnl_lock();
3013
3014 if (!netif_running(dev))
3015 goto out_unlock;
3016
3017 rtl8169_wait_for_quiescence(dev);
3018 rtl8169_close(dev);
1da177e4
LT		 3019
3020 ret = rtl8169_open(dev);
3021 if (unlikely(ret < 0)) {
07d3f51f 3022 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3023 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3024 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3025 }
3026 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3027 }
eb2a021c
FR		 3028
3029out_unlock:
3030 rtnl_unlock();
1da177e4
LT		 3031}
3032
c4028958 3033static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3034{
c4028958
DH		 3035 struct rtl8169_private *tp =
3036 container_of(work, struct rtl8169_private, task.work);
3037 struct net_device *dev = tp->dev;
1da177e4 3038
eb2a021c
FR		 3039 rtnl_lock();
3040
1da177e4 3041 if (!netif_running(dev))
eb2a021c 3042 goto out_unlock;
1da177e4
LT		 3043
3044 rtl8169_wait_for_quiescence(dev);
3045
bea3348e 3046 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3047 rtl8169_tx_clear(tp);
3048
3049 if (tp->dirty_rx == tp->cur_rx) {
3050 rtl8169_init_ring_indexes(tp);
07ce4064 3051 rtl_hw_start(dev);
1da177e4 3052 netif_wake_queue(dev);
cebf8cc7 3053 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3054 } else {
07d3f51f 3055 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3056 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3057 dev->name);
1da177e4
LT		 3058 }
3059 rtl8169_schedule_work(dev, rtl8169_reset_task);
3060 }
eb2a021c
FR		 3061
3062out_unlock:
3063 rtnl_unlock();
1da177e4
LT		 3064}
3065
3066static void rtl8169_tx_timeout(struct net_device *dev)
3067{
3068 struct rtl8169_private *tp = netdev_priv(dev);
3069
3070 rtl8169_hw_reset(tp->mmio_addr);
3071
3072 /* Let's wait a bit while any (async) irq lands on */
3073 rtl8169_schedule_work(dev, rtl8169_reset_task);
3074}
3075
3076static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3077 u32 opts1)
3078{
3079 struct skb_shared_info *info = skb_shinfo(skb);
3080 unsigned int cur_frag, entry;
a6343afb 3081 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3082
3083 entry = tp->cur_tx;
3084 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3085 skb_frag_t *frag = info->frags + cur_frag;
3086 dma_addr_t mapping;
3087 u32 status, len;
3088 void *addr;
3089
3090 entry = (entry + 1) % NUM_TX_DESC;
3091
3092 txd = tp->TxDescArray + entry;
3093 len = frag->size;
3094 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3095 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3096
3097 /* anti gcc 2.95.3 bugware (sic) */
3098 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3099
3100 txd->opts1 = cpu_to_le32(status);
3101 txd->addr = cpu_to_le64(mapping);
3102
3103 tp->tx_skb[entry].len = len;
3104 }
3105
3106 if (cur_frag) {
3107 tp->tx_skb[entry].skb = skb;
3108 txd->opts1 |= cpu_to_le32(LastFrag);
3109 }
3110
3111 return cur_frag;
3112}
3113
3114static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3115{
3116 if (dev->features & NETIF_F_TSO) {
7967168c 3117 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3118
3119 if (mss)
3120 return LargeSend | ((mss & MSSMask) << MSSShift);
3121 }
84fa7933 3122 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3123 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3124
3125 if (ip->protocol == IPPROTO_TCP)
3126 return IPCS | TCPCS;
3127 else if (ip->protocol == IPPROTO_UDP)
3128 return IPCS | UDPCS;
3129 WARN_ON(1); /* we need a WARN() */
3130 }
3131 return 0;
3132}
3133
3134static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3135{
3136 struct rtl8169_private *tp = netdev_priv(dev);
3137 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3138 struct TxDesc *txd = tp->TxDescArray + entry;
3139 void __iomem *ioaddr = tp->mmio_addr;
3140 dma_addr_t mapping;
3141 u32 status, len;
3142 u32 opts1;
188f4af0 3143 int ret = NETDEV_TX_OK;
5b0384f4 3144
1da177e4 3145 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3146 if (netif_msg_drv(tp)) {
3147 printk(KERN_ERR
3148 "%s: BUG! Tx Ring full when queue awake!\n",
3149 dev->name);
3150 }
1da177e4
LT		 3151 goto err_stop;
3152 }
3153
3154 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3155 goto err_stop;
3156
3157 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3158
3159 frags = rtl8169_xmit_frags(tp, skb, opts1);
3160 if (frags) {
3161 len = skb_headlen(skb);
3162 opts1 |= FirstFrag;
3163 } else {
3164 len = skb->len;
3165
3166 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 3167 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 3168 goto err_update_stats;
3169 len = ETH_ZLEN;
3170 }
3171
3172 opts1 |= FirstFrag | LastFrag;
3173 tp->tx_skb[entry].skb = skb;
3174 }
3175
3176 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3177
3178 tp->tx_skb[entry].len = len;
3179 txd->addr = cpu_to_le64(mapping);
3180 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3181
3182 wmb();
3183
3184 /* anti gcc 2.95.3 bugware (sic) */
3185 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3186 txd->opts1 = cpu_to_le32(status);
3187
3188 dev->trans_start = jiffies;
3189
3190 tp->cur_tx += frags + 1;
3191
3192 smp_wmb();
3193
275391a4 3194 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3195
3196 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3197 netif_stop_queue(dev);
3198 smp_rmb();
3199 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3200 netif_wake_queue(dev);
3201 }
3202
3203out:
3204 return ret;
3205
3206err_stop:
3207 netif_stop_queue(dev);
188f4af0 3208 ret = NETDEV_TX_BUSY;
1da177e4 3209err_update_stats:
cebf8cc7 3210 dev->stats.tx_dropped++;
1da177e4
LT		 3211 goto out;
3212}
3213
3214static void rtl8169_pcierr_interrupt(struct net_device *dev)
3215{
3216 struct rtl8169_private *tp = netdev_priv(dev);
3217 struct pci_dev *pdev = tp->pci_dev;
3218 void __iomem *ioaddr = tp->mmio_addr;
3219 u16 pci_status, pci_cmd;
3220
3221 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3222 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3223
b57b7e5a
SH		 3224 if (netif_msg_intr(tp)) {
3225 printk(KERN_ERR
3226 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3227 dev->name, pci_cmd, pci_status);
3228 }
1da177e4
LT		 3229
3230 /*
3231 * The recovery sequence below admits a very elaborated explanation:
3232 * - it seems to work;
d03902b8
FR		 3233 * - I did not see what else could be done;
3234 * - it makes iop3xx happy.
1da177e4
LT		 3235 *
3236 * Feel free to adjust to your needs.
3237 */
a27993f3 3238 if (pdev->broken_parity_status)
d03902b8
FR		 3239 pci_cmd &= ~PCI_COMMAND_PARITY;
3240 else
3241 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3242
3243 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3244
3245 pci_write_config_word(pdev, PCI_STATUS,
3246 pci_status & (PCI_STATUS_DETECTED_PARITY |
3247 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3248 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3249
3250 /* The infamous DAC f*ckup only happens at boot time */
3251 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3252 if (netif_msg_intr(tp))
3253 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3254 tp->cp_cmd &= ~PCIDAC;
3255 RTL_W16(CPlusCmd, tp->cp_cmd);
3256 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3257 }
3258
3259 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3260
3261 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3262}
3263
07d3f51f
FR		 3264static void rtl8169_tx_interrupt(struct net_device *dev,
3265 struct rtl8169_private *tp,
3266 void __iomem *ioaddr)
1da177e4
LT		 3267{
3268 unsigned int dirty_tx, tx_left;
3269
1da177e4
LT		 3270 dirty_tx = tp->dirty_tx;
3271 smp_rmb();
3272 tx_left = tp->cur_tx - dirty_tx;
3273
3274 while (tx_left > 0) {
3275 unsigned int entry = dirty_tx % NUM_TX_DESC;
3276 struct ring_info *tx_skb = tp->tx_skb + entry;
3277 u32 len = tx_skb->len;
3278 u32 status;
3279
3280 rmb();
3281 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3282 if (status & DescOwn)
3283 break;
3284
cebf8cc7
FR		 3285 dev->stats.tx_bytes += len;
3286 dev->stats.tx_packets++;
1da177e4
LT		 3287
3288 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3289
3290 if (status & LastFrag) {
3291 dev_kfree_skb_irq(tx_skb->skb);
3292 tx_skb->skb = NULL;
3293 }
3294 dirty_tx++;
3295 tx_left--;
3296 }
3297
3298 if (tp->dirty_tx != dirty_tx) {
3299 tp->dirty_tx = dirty_tx;
3300 smp_wmb();
3301 if (netif_queue_stopped(dev) &&
3302 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3303 netif_wake_queue(dev);
3304 }
d78ae2dc
FR		 3305 /*
3306 * 8168 hack: TxPoll requests are lost when the Tx packets are
3307 * too close. Let's kick an extra TxPoll request when a burst
3308 * of start_xmit activity is detected (if it is not detected,
3309 * it is slow enough). -- FR
3310 */
3311 smp_rmb();
3312 if (tp->cur_tx != dirty_tx)
3313 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3314 }
3315}
3316
126fa4b9
FR		 3317static inline int rtl8169_fragmented_frame(u32 status)
3318{
3319 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3320}
3321
1da177e4
LT		 3322static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3323{
3324 u32 opts1 = le32_to_cpu(desc->opts1);
3325 u32 status = opts1 & RxProtoMask;
3326
3327 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3328 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3329 ((status == RxProtoIP) && !(opts1 & IPFail)))
3330 skb->ip_summed = CHECKSUM_UNNECESSARY;
3331 else
3332 skb->ip_summed = CHECKSUM_NONE;
3333}
3334
07d3f51f
FR		 3335static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3336 struct rtl8169_private *tp, int pkt_size,
3337 dma_addr_t addr)
1da177e4 3338{
b449655f
SH		 3339 struct sk_buff *skb;
3340 bool done = false;
1da177e4 3341
b449655f
SH		 3342 if (pkt_size >= rx_copybreak)
3343 goto out;
1da177e4 3344
07d3f51f 3345 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3346 if (!skb)
3347 goto out;
3348
07d3f51f
FR		 3349 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3350 PCI_DMA_FROMDEVICE);
86402234 3351 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3352 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3353 *sk_buff = skb;
3354 done = true;
3355out:
3356 return done;
1da177e4
LT		 3357}
3358
07d3f51f
FR		 3359static int rtl8169_rx_interrupt(struct net_device *dev,
3360 struct rtl8169_private *tp,
bea3348e 3361 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3362{
3363 unsigned int cur_rx, rx_left;
3364 unsigned int delta, count;
3365
1da177e4
LT		 3366 cur_rx = tp->cur_rx;
3367 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3368 rx_left = min(rx_left, budget);
1da177e4 3369
4dcb7d33 3370 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3371 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3372 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3373 u32 status;
3374
3375 rmb();
126fa4b9 3376 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3377
3378 if (status & DescOwn)
3379 break;
4dcb7d33 3380 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3381 if (netif_msg_rx_err(tp)) {
3382 printk(KERN_INFO
3383 "%s: Rx ERROR. status = %08x\n",
3384 dev->name, status);
3385 }
cebf8cc7 3386 dev->stats.rx_errors++;
1da177e4 3387 if (status & (RxRWT | RxRUNT))
cebf8cc7 3388 dev->stats.rx_length_errors++;
1da177e4 3389 if (status & RxCRC)
cebf8cc7 3390 dev->stats.rx_crc_errors++;
9dccf611
FR		 3391 if (status & RxFOVF) {
3392 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3393 dev->stats.rx_fifo_errors++;
9dccf611 3394 }
126fa4b9 3395 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3396 } else {
1da177e4 3397 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3398 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3399 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3400 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3401
126fa4b9
FR		 3402 /*
3403 * The driver does not support incoming fragmented
3404 * frames. They are seen as a symptom of over-mtu
3405 * sized frames.
3406 */
3407 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3408 dev->stats.rx_dropped++;
3409 dev->stats.rx_length_errors++;
126fa4b9 3410 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3411 continue;
126fa4b9
FR		 3412 }
3413
1da177e4 3414 rtl8169_rx_csum(skb, desc);
bcf0bf90 3415
07d3f51f 3416 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3417 pci_dma_sync_single_for_device(pdev, addr,
3418 pkt_size, PCI_DMA_FROMDEVICE);
3419 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3420 } else {
a866bbf6 3421 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3422 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3423 tp->Rx_skbuff[entry] = NULL;
3424 }
3425
1da177e4
LT		 3426 skb_put(skb, pkt_size);
3427 skb->protocol = eth_type_trans(skb, dev);
3428
3429 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3430 netif_receive_skb(skb);
1da177e4
LT		 3431
3432 dev->last_rx = jiffies;
cebf8cc7
FR		 3433 dev->stats.rx_bytes += pkt_size;
3434 dev->stats.rx_packets++;
1da177e4 3435 }
6dccd16b
FR		 3436
3437 /* Work around for AMD plateform. */
95e0918d 3438 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3439 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3440 desc->opts2 = 0;
3441 cur_rx++;
3442 }
1da177e4
LT		 3443 }
3444
3445 count = cur_rx - tp->cur_rx;
3446 tp->cur_rx = cur_rx;
3447
3448 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3449 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3450 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3451 tp->dirty_rx += delta;
3452
3453 /*
3454 * FIXME: until there is periodic timer to try and refill the ring,
3455 * a temporary shortage may definitely kill the Rx process.
3456 * - disable the asic to try and avoid an overflow and kick it again
3457 * after refill ?
3458 * - how do others driver handle this condition (Uh oh...).
3459 */
b57b7e5a 3460 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3461 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3462
3463 return count;
3464}
3465
07d3f51f 3466static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3467{
07d3f51f 3468 struct net_device *dev = dev_instance;
1da177e4 3469 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3470 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3471 int handled = 0;
865c652d 3472 int status;
1da177e4 3473
865c652d 3474 status = RTL_R16(IntrStatus);
1da177e4 3475
865c652d
FR		 3476 /* hotplug/major error/no more work/shared irq */
3477 if ((status == 0xffff) || !status)
3478 goto out;
1da177e4 3479
865c652d 3480 handled = 1;
1da177e4 3481
865c652d
FR		 3482 if (unlikely(!netif_running(dev))) {
3483 rtl8169_asic_down(ioaddr);
3484 goto out;
3485 }
1da177e4 3486
865c652d
FR		 3487 status &= tp->intr_mask;
3488 RTL_W16(IntrStatus,
3489 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3490
865c652d
FR		 3491 if (!(status & tp->intr_event))
3492 goto out;
0e485150 3493
865c652d
FR		 3494 /* Work around for rx fifo overflow */
3495 if (unlikely(status & RxFIFOOver) &&
3496 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3497 netif_stop_queue(dev);
3498 rtl8169_tx_timeout(dev);
3499 goto out;
3500 }
1da177e4 3501
865c652d
FR		 3502 if (unlikely(status & SYSErr)) {
3503 rtl8169_pcierr_interrupt(dev);
3504 goto out;
3505 }
1da177e4 3506
865c652d
FR		 3507 if (status & LinkChg)
3508 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3509
865c652d
FR		 3510 if (status & tp->napi_event) {
3511 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3512 tp->intr_mask = ~tp->napi_event;
313b0305 3513
bea3348e
SH		 3514 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3515 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 3516 else if (netif_msg_intr(tp)) {
3517 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3518 dev->name, status);
b57b7e5a 3519 }
1da177e4
LT		 3520 }
3521out:
3522 return IRQ_RETVAL(handled);
3523}
3524
bea3348e 3525static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3526{
bea3348e
SH		 3527 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3528 struct net_device *dev = tp->dev;
1da177e4 3529 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3530 int work_done;
1da177e4 3531
bea3348e 3532 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3533 rtl8169_tx_interrupt(dev, tp, ioaddr);
3534
bea3348e
SH		 3535 if (work_done < budget) {
3536 netif_rx_complete(dev, napi);
1da177e4
LT		 3537 tp->intr_mask = 0xffff;
3538 /*
3539 * 20040426: the barrier is not strictly required but the
3540 * behavior of the irq handler could be less predictable
3541 * without it. Btw, the lack of flush for the posted pci
3542 * write is safe - FR
3543 */
3544 smp_wmb();
0e485150 3545 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3546 }
3547
bea3348e 3548 return work_done;
1da177e4 3549}
1da177e4 3550
523a6094
FR		 3551static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3552{
3553 struct rtl8169_private *tp = netdev_priv(dev);
3554
3555 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3556 return;
3557
3558 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3559 RTL_W32(RxMissed, 0);
3560}
3561
1da177e4
LT		 3562static void rtl8169_down(struct net_device *dev)
3563{
3564 struct rtl8169_private *tp = netdev_priv(dev);
3565 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3566 unsigned int intrmask;
1da177e4
LT		 3567
3568 rtl8169_delete_timer(dev);
3569
3570 netif_stop_queue(dev);
3571
93dd79e8 3572 napi_disable(&tp->napi);
93dd79e8 3573
1da177e4
LT		 3574core_down:
3575 spin_lock_irq(&tp->lock);
3576
3577 rtl8169_asic_down(ioaddr);
3578
523a6094 3579 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3580
3581 spin_unlock_irq(&tp->lock);
3582
3583 synchronize_irq(dev->irq);
3584
1da177e4 3585 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3586 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3587
3588 /*
3589 * And now for the 50k$ question: are IRQ disabled or not ?
3590 *
3591 * Two paths lead here:
3592 * 1) dev->close
3593 * -> netif_running() is available to sync the current code and the
3594 * IRQ handler. See rtl8169_interrupt for details.
3595 * 2) dev->change_mtu
3596 * -> rtl8169_poll can not be issued again and re-enable the
3597 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3598 *
3599 * No loop if hotpluged or major error (0xffff).
1da177e4 3600 */
733b736c
AP		 3601 intrmask = RTL_R16(IntrMask);
3602 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3603 goto core_down;
3604
3605 rtl8169_tx_clear(tp);
3606
3607 rtl8169_rx_clear(tp);
3608}
3609
3610static int rtl8169_close(struct net_device *dev)
3611{
3612 struct rtl8169_private *tp = netdev_priv(dev);
3613 struct pci_dev *pdev = tp->pci_dev;
3614
3615 rtl8169_down(dev);
3616
3617 free_irq(dev->irq, dev);
3618
1da177e4
LT		 3619 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3620 tp->RxPhyAddr);
3621 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3622 tp->TxPhyAddr);
3623 tp->TxDescArray = NULL;
3624 tp->RxDescArray = NULL;
3625
3626 return 0;
3627}
3628
07ce4064 3629static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3630{
3631 struct rtl8169_private *tp = netdev_priv(dev);
3632 void __iomem *ioaddr = tp->mmio_addr;
3633 unsigned long flags;
3634 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3635 int rx_mode;
1da177e4
LT		 3636 u32 tmp = 0;
3637
3638 if (dev->flags & IFF_PROMISC) {
3639 /* Unconditionally log net taps. */
b57b7e5a
SH		 3640 if (netif_msg_link(tp)) {
3641 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3642 dev->name);
3643 }
1da177e4
LT		 3644 rx_mode =
3645 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3646 AcceptAllPhys;
3647 mc_filter[1] = mc_filter[0] = 0xffffffff;
3648 } else if ((dev->mc_count > multicast_filter_limit)
3649 || (dev->flags & IFF_ALLMULTI)) {
3650 /* Too many to filter perfectly -- accept all multicasts. */
3651 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3652 mc_filter[1] = mc_filter[0] = 0xffffffff;
3653 } else {
3654 struct dev_mc_list *mclist;
07d3f51f
FR		 3655 unsigned int i;
3656
1da177e4
LT		 3657 rx_mode = AcceptBroadcast | AcceptMyPhys;
3658 mc_filter[1] = mc_filter[0] = 0;
3659 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3660 i++, mclist = mclist->next) {
3661 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3662 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3663 rx_mode |= AcceptMulticast;
3664 }
3665 }
3666
3667 spin_lock_irqsave(&tp->lock, flags);
3668
3669 tmp = rtl8169_rx_config | rx_mode |
3670 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3671
f887cce8 3672 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3673 u32 data = mc_filter[0];
3674
3675 mc_filter[0] = swab32(mc_filter[1]);
3676 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3677 }
3678
1da177e4
LT		 3679 RTL_W32(MAR0 + 0, mc_filter[0]);
3680 RTL_W32(MAR0 + 4, mc_filter[1]);
3681
57a9f236
FR		 3682 RTL_W32(RxConfig, tmp);
3683
1da177e4
LT		 3684 spin_unlock_irqrestore(&tp->lock, flags);
3685}
3686
3687/**
3688 * rtl8169_get_stats - Get rtl8169 read/write statistics
3689 * @dev: The Ethernet Device to get statistics for
3690 *
3691 * Get TX/RX statistics for rtl8169
3692 */
3693static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3694{
3695 struct rtl8169_private *tp = netdev_priv(dev);
3696 void __iomem *ioaddr = tp->mmio_addr;
3697 unsigned long flags;
3698
3699 if (netif_running(dev)) {
3700 spin_lock_irqsave(&tp->lock, flags);
523a6094 3701 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3702 spin_unlock_irqrestore(&tp->lock, flags);
3703 }
5b0384f4 3704
cebf8cc7 3705 return &dev->stats;
1da177e4
LT		 3706}
3707
5d06a99f
FR		 3708#ifdef CONFIG_PM
3709
3710static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3711{
3712 struct net_device *dev = pci_get_drvdata(pdev);
3713 struct rtl8169_private *tp = netdev_priv(dev);
3714 void __iomem *ioaddr = tp->mmio_addr;
3715
3716 if (!netif_running(dev))
1371fa6d 3717 goto out_pci_suspend;
5d06a99f
FR		 3718
3719 netif_device_detach(dev);
3720 netif_stop_queue(dev);
3721
3722 spin_lock_irq(&tp->lock);
3723
3724 rtl8169_asic_down(ioaddr);
3725
523a6094 3726 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3727
3728 spin_unlock_irq(&tp->lock);
3729
1371fa6d 3730out_pci_suspend:
5d06a99f 3731 pci_save_state(pdev);
f23e7fda
FR		 3732 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3733 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3734 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3735
5d06a99f
FR		 3736 return 0;
3737}
3738
3739static int rtl8169_resume(struct pci_dev *pdev)
3740{
3741 struct net_device *dev = pci_get_drvdata(pdev);
3742
1371fa6d
FR		 3743 pci_set_power_state(pdev, PCI_D0);
3744 pci_restore_state(pdev);
3745 pci_enable_wake(pdev, PCI_D0, 0);
3746
5d06a99f
FR		 3747 if (!netif_running(dev))
3748 goto out;
3749
3750 netif_device_attach(dev);
3751
5d06a99f
FR		 3752 rtl8169_schedule_work(dev, rtl8169_reset_task);
3753out:
3754 return 0;
3755}
3756
3757#endif /* CONFIG_PM */
3758
1da177e4
LT		 3759static struct pci_driver rtl8169_pci_driver = {
3760 .name = MODULENAME,
3761 .id_table = rtl8169_pci_tbl,
3762 .probe = rtl8169_init_one,
3763 .remove = __devexit_p(rtl8169_remove_one),
3764#ifdef CONFIG_PM
3765 .suspend = rtl8169_suspend,
3766 .resume = rtl8169_resume,
3767#endif
3768};
3769
07d3f51f 3770static int __init rtl8169_init_module(void)
1da177e4 3771{
29917620 3772 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3773}
3774
07d3f51f 3775static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3776{
3777 pci_unregister_driver(&rtl8169_pci_driver);
3778}
3779
3780module_init(rtl8169_init_module);
3781module_exit(rtl8169_cleanup_module);
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