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r8169: add hw start helpers for the 8168 and the 8101
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 99 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 100 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
101 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
102 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
103 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
104 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
105 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
106 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
107 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
108 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 109};
110
1da177e4
LT		 111#define _R(NAME,MAC,MASK) \
112 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
113
3c6bee1d 114static const struct {
1da177e4
LT		 115 const char *name;
116 u8 mac_version;
117 u32 RxConfigMask; /* Clears the bits supported by this chip */
118} rtl_chip_info[] = {
ba6eb6ee
FR		 119 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
120 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
121 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
122 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 124 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
126 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
127 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
128 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 129 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
130 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
131 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
132 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
134 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 135};
136#undef _R
137
bcf0bf90
FR		 138enum cfg_version {
139 RTL_CFG_0 = 0x00,
140 RTL_CFG_1,
141 RTL_CFG_2
142};
143
07ce4064
FR		 144static void rtl_hw_start_8169(struct net_device *);
145static void rtl_hw_start_8168(struct net_device *);
146static void rtl_hw_start_8101(struct net_device *);
147
1da177e4 148static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 153 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
154 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 155 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 156 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
157 { PCI_VENDOR_ID_LINKSYS, 0x1032,
158 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 159 { 0x0001, 0x8168,
160 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 161 {0,},
162};
163
164MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
165
166static int rx_copybreak = 200;
167static int use_dac;
b57b7e5a
SH		 168static struct {
169 u32 msg_enable;
170} debug = { -1 };
1da177e4 171
07d3f51f
FR		 172enum rtl_registers {
173 MAC0 = 0, /* Ethernet hardware address. */
773d2021 174 MAC4 = 4,
07d3f51f
FR		 175 MAR0 = 8, /* Multicast filter. */
176 CounterAddrLow = 0x10,
177 CounterAddrHigh = 0x14,
178 TxDescStartAddrLow = 0x20,
179 TxDescStartAddrHigh = 0x24,
180 TxHDescStartAddrLow = 0x28,
181 TxHDescStartAddrHigh = 0x2c,
182 FLASH = 0x30,
183 ERSR = 0x36,
184 ChipCmd = 0x37,
185 TxPoll = 0x38,
186 IntrMask = 0x3c,
187 IntrStatus = 0x3e,
188 TxConfig = 0x40,
189 RxConfig = 0x44,
190 RxMissed = 0x4c,
191 Cfg9346 = 0x50,
192 Config0 = 0x51,
193 Config1 = 0x52,
194 Config2 = 0x53,
195 Config3 = 0x54,
196 Config4 = 0x55,
197 Config5 = 0x56,
198 MultiIntr = 0x5c,
199 PHYAR = 0x60,
07d3f51f
FR		 200 PHYstatus = 0x6c,
201 RxMaxSize = 0xda,
202 CPlusCmd = 0xe0,
203 IntrMitigate = 0xe2,
204 RxDescAddrLow = 0xe4,
205 RxDescAddrHigh = 0xe8,
206 EarlyTxThres = 0xec,
207 FuncEvent = 0xf0,
208 FuncEventMask = 0xf4,
209 FuncPresetState = 0xf8,
210 FuncForceEvent = 0xfc,
1da177e4
LT		 211};
212
f162a5d1
FR		 213enum rtl8110_registers {
214 TBICSR = 0x64,
215 TBI_ANAR = 0x68,
216 TBI_LPAR = 0x6a,
217};
218
219enum rtl8168_8101_registers {
220 CSIDR = 0x64,
221 CSIAR = 0x68,
222#define CSIAR_FLAG 0x80000000
223#define CSIAR_WRITE_CMD 0x80000000
224#define CSIAR_BYTE_ENABLE 0x0f
225#define CSIAR_BYTE_ENABLE_SHIFT 12
226#define CSIAR_ADDR_MASK 0x0fff
227
228 EPHYAR = 0x80,
229#define EPHYAR_FLAG 0x80000000
230#define EPHYAR_WRITE_CMD 0x80000000
231#define EPHYAR_REG_MASK 0x1f
232#define EPHYAR_REG_SHIFT 16
233#define EPHYAR_DATA_MASK 0xffff
234 DBG_REG = 0xd1,
235#define FIX_NAK_1 (1 << 4)
236#define FIX_NAK_2 (1 << 3)
237};
238
07d3f51f 239enum rtl_register_content {
1da177e4 240 /* InterruptStatusBits */
07d3f51f
FR		 241 SYSErr = 0x8000,
242 PCSTimeout = 0x4000,
243 SWInt = 0x0100,
244 TxDescUnavail = 0x0080,
245 RxFIFOOver = 0x0040,
246 LinkChg = 0x0020,
247 RxOverflow = 0x0010,
248 TxErr = 0x0008,
249 TxOK = 0x0004,
250 RxErr = 0x0002,
251 RxOK = 0x0001,
1da177e4
LT		 252
253 /* RxStatusDesc */
9dccf611
FR		 254 RxFOVF = (1 << 23),
255 RxRWT = (1 << 22),
256 RxRES = (1 << 21),
257 RxRUNT = (1 << 20),
258 RxCRC = (1 << 19),
1da177e4
LT		 259
260 /* ChipCmdBits */
07d3f51f
FR		 261 CmdReset = 0x10,
262 CmdRxEnb = 0x08,
263 CmdTxEnb = 0x04,
264 RxBufEmpty = 0x01,
1da177e4 265
275391a4
FR		 266 /* TXPoll register p.5 */
267 HPQ = 0x80, /* Poll cmd on the high prio queue */
268 NPQ = 0x40, /* Poll cmd on the low prio queue */
269 FSWInt = 0x01, /* Forced software interrupt */
270
1da177e4 271 /* Cfg9346Bits */
07d3f51f
FR		 272 Cfg9346_Lock = 0x00,
273 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 274
275 /* rx_mode_bits */
07d3f51f
FR		 276 AcceptErr = 0x20,
277 AcceptRunt = 0x10,
278 AcceptBroadcast = 0x08,
279 AcceptMulticast = 0x04,
280 AcceptMyPhys = 0x02,
281 AcceptAllPhys = 0x01,
1da177e4
LT		 282
283 /* RxConfigBits */
07d3f51f
FR		 284 RxCfgFIFOShift = 13,
285 RxCfgDMAShift = 8,
1da177e4
LT		 286
287 /* TxConfigBits */
288 TxInterFrameGapShift = 24,
289 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
290
5d06a99f 291 /* Config1 register p.24 */
f162a5d1
FR		 292 LEDS1 = (1 << 7),
293 LEDS0 = (1 << 6),
fbac58fc 294 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 295 Speed_down = (1 << 4),
296 MEMMAP = (1 << 3),
297 IOMAP = (1 << 2),
298 VPD = (1 << 1),
5d06a99f
FR		 299 PMEnable = (1 << 0), /* Power Management Enable */
300
6dccd16b
FR		 301 /* Config2 register p. 25 */
302 PCI_Clock_66MHz = 0x01,
303 PCI_Clock_33MHz = 0x00,
304
61a4dcc2
FR		 305 /* Config3 register p.25 */
306 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
307 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 308 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 309
5d06a99f 310 /* Config5 register p.27 */
61a4dcc2
FR		 311 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
312 MWF = (1 << 5), /* Accept Multicast wakeup frame */
313 UWF = (1 << 4), /* Accept Unicast wakeup frame */
314 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 315 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
316
1da177e4
LT		 317 /* TBICSR p.28 */
318 TBIReset = 0x80000000,
319 TBILoopback = 0x40000000,
320 TBINwEnable = 0x20000000,
321 TBINwRestart = 0x10000000,
322 TBILinkOk = 0x02000000,
323 TBINwComplete = 0x01000000,
324
325 /* CPlusCmd p.31 */
f162a5d1
FR		 326 EnableBist = (1 << 15), // 8168 8101
327 Mac_dbgo_oe = (1 << 14), // 8168 8101
328 Normal_mode = (1 << 13), // unused
329 Force_half_dup = (1 << 12), // 8168 8101
330 Force_rxflow_en = (1 << 11), // 8168 8101
331 Force_txflow_en = (1 << 10), // 8168 8101
332 Cxpl_dbg_sel = (1 << 9), // 8168 8101
333 ASF = (1 << 8), // 8168 8101
334 PktCntrDisable = (1 << 7), // 8168 8101
335 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 336 RxVlan = (1 << 6),
337 RxChkSum = (1 << 5),
338 PCIDAC = (1 << 4),
339 PCIMulRW = (1 << 3),
0e485150
FR		 340 INTT_0 = 0x0000, // 8168
341 INTT_1 = 0x0001, // 8168
342 INTT_2 = 0x0002, // 8168
343 INTT_3 = 0x0003, // 8168
1da177e4
LT		 344
345 /* rtl8169_PHYstatus */
07d3f51f
FR		 346 TBI_Enable = 0x80,
347 TxFlowCtrl = 0x40,
348 RxFlowCtrl = 0x20,
349 _1000bpsF = 0x10,
350 _100bps = 0x08,
351 _10bps = 0x04,
352 LinkStatus = 0x02,
353 FullDup = 0x01,
1da177e4 354
1da177e4 355 /* _TBICSRBit */
07d3f51f 356 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 357
358 /* DumpCounterCommand */
07d3f51f 359 CounterDump = 0x8,
1da177e4
LT		 360};
361
07d3f51f 362enum desc_status_bit {
1da177e4
LT		 363 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
364 RingEnd = (1 << 30), /* End of descriptor ring */
365 FirstFrag = (1 << 29), /* First segment of a packet */
366 LastFrag = (1 << 28), /* Final segment of a packet */
367
368 /* Tx private */
369 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
370 MSSShift = 16, /* MSS value position */
371 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
372 IPCS = (1 << 18), /* Calculate IP checksum */
373 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
374 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
375 TxVlanTag = (1 << 17), /* Add VLAN tag */
376
377 /* Rx private */
378 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
379 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
380
381#define RxProtoUDP (PID1)
382#define RxProtoTCP (PID0)
383#define RxProtoIP (PID1 | PID0)
384#define RxProtoMask RxProtoIP
385
386 IPFail = (1 << 16), /* IP checksum failed */
387 UDPFail = (1 << 15), /* UDP/IP checksum failed */
388 TCPFail = (1 << 14), /* TCP/IP checksum failed */
389 RxVlanTag = (1 << 16), /* VLAN tag available */
390};
391
392#define RsvdMask 0x3fffc000
393
394struct TxDesc {
6cccd6e7
REB		 395 __le32 opts1;
396 __le32 opts2;
397 __le64 addr;
1da177e4
LT		 398};
399
400struct RxDesc {
6cccd6e7
REB		 401 __le32 opts1;
402 __le32 opts2;
403 __le64 addr;
1da177e4
LT		 404};
405
406struct ring_info {
407 struct sk_buff *skb;
408 u32 len;
409 u8 __pad[sizeof(void *) - sizeof(u32)];
410};
411
f23e7fda 412enum features {
ccdffb9a
FR		 413 RTL_FEATURE_WOL = (1 << 0),
414 RTL_FEATURE_MSI = (1 << 1),
415 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 416};
417
1da177e4
LT		 418struct rtl8169_private {
419 void __iomem *mmio_addr; /* memory map physical address */
420 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 421 struct net_device *dev;
bea3348e 422 struct napi_struct napi;
1da177e4 423 spinlock_t lock; /* spin lock flag */
b57b7e5a 424 u32 msg_enable;
1da177e4
LT		 425 int chipset;
426 int mac_version;
1da177e4
LT		 427 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
428 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
429 u32 dirty_rx;
430 u32 dirty_tx;
431 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
432 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
433 dma_addr_t TxPhyAddr;
434 dma_addr_t RxPhyAddr;
435 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
436 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 437 unsigned align;
1da177e4
LT		 438 unsigned rx_buf_sz;
439 struct timer_list timer;
440 u16 cp_cmd;
0e485150
FR		 441 u16 intr_event;
442 u16 napi_event;
1da177e4
LT		 443 u16 intr_mask;
444 int phy_auto_nego_reg;
445 int phy_1000_ctrl_reg;
446#ifdef CONFIG_R8169_VLAN
447 struct vlan_group *vlgrp;
448#endif
449 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 450 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 451 void (*phy_reset_enable)(void __iomem *);
07ce4064 452 void (*hw_start)(struct net_device *);
1da177e4
LT		 453 unsigned int (*phy_reset_pending)(void __iomem *);
454 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 455 int pcie_cap;
c4028958 456 struct delayed_work task;
f23e7fda 457 unsigned features;
ccdffb9a
FR		 458
459 struct mii_if_info mii;
1da177e4
LT		 460};
461
979b6c13 462MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 463MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 464module_param(rx_copybreak, int, 0);
1b7efd58 465MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 466module_param(use_dac, int, 0);
467MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 468module_param_named(debug, debug.msg_enable, int, 0);
469MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 470MODULE_LICENSE("GPL");
471MODULE_VERSION(RTL8169_VERSION);
472
473static int rtl8169_open(struct net_device *dev);
474static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 475static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 476static int rtl8169_init_ring(struct net_device *dev);
07ce4064 477static void rtl_hw_start(struct net_device *dev);
1da177e4 478static int rtl8169_close(struct net_device *dev);
07ce4064 479static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 480static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 481static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 482static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 483 void __iomem *, u32 budget);
4dcb7d33 484static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 485static void rtl8169_down(struct net_device *dev);
99f252b0 486static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 487static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 488
1da177e4 489static const unsigned int rtl8169_rx_config =
5b0384f4 490 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 491
07d3f51f 492static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 493{
494 int i;
495
a6baf3af 496 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 497
2371408c 498 for (i = 20; i > 0; i--) {
07d3f51f
FR		 499 /*
500 * Check if the RTL8169 has completed writing to the specified
501 * MII register.
502 */
5b0384f4 503 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 504 break;
2371408c 505 udelay(25);
1da177e4
LT		 506 }
507}
508
07d3f51f 509static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 510{
511 int i, value = -1;
512
a6baf3af 513 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 514
2371408c 515 for (i = 20; i > 0; i--) {
07d3f51f
FR		 516 /*
517 * Check if the RTL8169 has completed retrieving data from
518 * the specified MII register.
519 */
1da177e4 520 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 521 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 522 break;
523 }
2371408c 524 udelay(25);
1da177e4
LT		 525 }
526 return value;
527}
528
dacf8154
FR		 529static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
530{
531 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
532}
533
ccdffb9a
FR		 534static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
535 int val)
536{
537 struct rtl8169_private *tp = netdev_priv(dev);
538 void __iomem *ioaddr = tp->mmio_addr;
539
540 mdio_write(ioaddr, location, val);
541}
542
543static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
544{
545 struct rtl8169_private *tp = netdev_priv(dev);
546 void __iomem *ioaddr = tp->mmio_addr;
547
548 return mdio_read(ioaddr, location);
549}
550
dacf8154
FR		 551static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
552{
553 unsigned int i;
554
555 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
556 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
557
558 for (i = 0; i < 100; i++) {
559 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
560 break;
561 udelay(10);
562 }
563}
564
565static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
566{
567 u16 value = 0xffff;
568 unsigned int i;
569
570 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
571
572 for (i = 0; i < 100; i++) {
573 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
574 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
575 break;
576 }
577 udelay(10);
578 }
579
580 return value;
581}
582
583static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
584{
585 unsigned int i;
586
587 RTL_W32(CSIDR, value);
588 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
589 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
590
591 for (i = 0; i < 100; i++) {
592 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
593 break;
594 udelay(10);
595 }
596}
597
598static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
599{
600 u32 value = ~0x00;
601 unsigned int i;
602
603 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
604 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
605
606 for (i = 0; i < 100; i++) {
607 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
608 value = RTL_R32(CSIDR);
609 break;
610 }
611 udelay(10);
612 }
613
614 return value;
615}
616
1da177e4
LT		 617static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
618{
619 RTL_W16(IntrMask, 0x0000);
620
621 RTL_W16(IntrStatus, 0xffff);
622}
623
624static void rtl8169_asic_down(void __iomem *ioaddr)
625{
626 RTL_W8(ChipCmd, 0x00);
627 rtl8169_irq_mask_and_ack(ioaddr);
628 RTL_R16(CPlusCmd);
629}
630
631static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
632{
633 return RTL_R32(TBICSR) & TBIReset;
634}
635
636static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
637{
64e4bfb4 638 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 639}
640
641static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
642{
643 return RTL_R32(TBICSR) & TBILinkOk;
644}
645
646static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
647{
648 return RTL_R8(PHYstatus) & LinkStatus;
649}
650
651static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
652{
653 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
654}
655
656static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
657{
658 unsigned int val;
659
9e0db8ef
FR		 660 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
661 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 662}
663
664static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 665 struct rtl8169_private *tp,
666 void __iomem *ioaddr)
1da177e4
LT		 667{
668 unsigned long flags;
669
670 spin_lock_irqsave(&tp->lock, flags);
671 if (tp->link_ok(ioaddr)) {
672 netif_carrier_on(dev);
b57b7e5a
SH		 673 if (netif_msg_ifup(tp))
674 printk(KERN_INFO PFX "%s: link up\n", dev->name);
675 } else {
676 if (netif_msg_ifdown(tp))
677 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 678 netif_carrier_off(dev);
b57b7e5a 679 }
1da177e4
LT		 680 spin_unlock_irqrestore(&tp->lock, flags);
681}
682
61a4dcc2
FR		 683static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
684{
685 struct rtl8169_private *tp = netdev_priv(dev);
686 void __iomem *ioaddr = tp->mmio_addr;
687 u8 options;
688
689 wol->wolopts = 0;
690
691#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
692 wol->supported = WAKE_ANY;
693
694 spin_lock_irq(&tp->lock);
695
696 options = RTL_R8(Config1);
697 if (!(options & PMEnable))
698 goto out_unlock;
699
700 options = RTL_R8(Config3);
701 if (options & LinkUp)
702 wol->wolopts |= WAKE_PHY;
703 if (options & MagicPacket)
704 wol->wolopts |= WAKE_MAGIC;
705
706 options = RTL_R8(Config5);
707 if (options & UWF)
708 wol->wolopts |= WAKE_UCAST;
709 if (options & BWF)
5b0384f4 710 wol->wolopts |= WAKE_BCAST;
61a4dcc2 711 if (options & MWF)
5b0384f4 712 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 713
714out_unlock:
715 spin_unlock_irq(&tp->lock);
716}
717
718static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
719{
720 struct rtl8169_private *tp = netdev_priv(dev);
721 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 722 unsigned int i;
61a4dcc2
FR		 723 static struct {
724 u32 opt;
725 u16 reg;
726 u8 mask;
727 } cfg[] = {
728 { WAKE_ANY, Config1, PMEnable },
729 { WAKE_PHY, Config3, LinkUp },
730 { WAKE_MAGIC, Config3, MagicPacket },
731 { WAKE_UCAST, Config5, UWF },
732 { WAKE_BCAST, Config5, BWF },
733 { WAKE_MCAST, Config5, MWF },
734 { WAKE_ANY, Config5, LanWake }
735 };
736
737 spin_lock_irq(&tp->lock);
738
739 RTL_W8(Cfg9346, Cfg9346_Unlock);
740
741 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
742 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
743 if (wol->wolopts & cfg[i].opt)
744 options |= cfg[i].mask;
745 RTL_W8(cfg[i].reg, options);
746 }
747
748 RTL_W8(Cfg9346, Cfg9346_Lock);
749
f23e7fda
FR		 750 if (wol->wolopts)
751 tp->features |= RTL_FEATURE_WOL;
752 else
753 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 754
755 spin_unlock_irq(&tp->lock);
756
757 return 0;
758}
759
1da177e4
LT		 760static void rtl8169_get_drvinfo(struct net_device *dev,
761 struct ethtool_drvinfo *info)
762{
763 struct rtl8169_private *tp = netdev_priv(dev);
764
765 strcpy(info->driver, MODULENAME);
766 strcpy(info->version, RTL8169_VERSION);
767 strcpy(info->bus_info, pci_name(tp->pci_dev));
768}
769
770static int rtl8169_get_regs_len(struct net_device *dev)
771{
772 return R8169_REGS_SIZE;
773}
774
775static int rtl8169_set_speed_tbi(struct net_device *dev,
776 u8 autoneg, u16 speed, u8 duplex)
777{
778 struct rtl8169_private *tp = netdev_priv(dev);
779 void __iomem *ioaddr = tp->mmio_addr;
780 int ret = 0;
781 u32 reg;
782
783 reg = RTL_R32(TBICSR);
784 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
785 (duplex == DUPLEX_FULL)) {
786 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
787 } else if (autoneg == AUTONEG_ENABLE)
788 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
789 else {
b57b7e5a
SH		 790 if (netif_msg_link(tp)) {
791 printk(KERN_WARNING "%s: "
792 "incorrect speed setting refused in TBI mode\n",
793 dev->name);
794 }
1da177e4
LT		 795 ret = -EOPNOTSUPP;
796 }
797
798 return ret;
799}
800
801static int rtl8169_set_speed_xmii(struct net_device *dev,
802 u8 autoneg, u16 speed, u8 duplex)
803{
804 struct rtl8169_private *tp = netdev_priv(dev);
805 void __iomem *ioaddr = tp->mmio_addr;
806 int auto_nego, giga_ctrl;
807
64e4bfb4
FR		 808 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
809 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
810 ADVERTISE_100HALF | ADVERTISE_100FULL);
811 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
812 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 813
814 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 815 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
816 ADVERTISE_100HALF | ADVERTISE_100FULL);
817 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 818 } else {
819 if (speed == SPEED_10)
64e4bfb4 820 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 821 else if (speed == SPEED_100)
64e4bfb4 822 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 823 else if (speed == SPEED_1000)
64e4bfb4 824 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 825
826 if (duplex == DUPLEX_HALF)
64e4bfb4 827 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 828
829 if (duplex == DUPLEX_FULL)
64e4bfb4 830 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 831
832 /* This tweak comes straight from Realtek's driver. */
833 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 834 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
835 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 836 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 837 }
838 }
839
840 /* The 8100e/8101e do Fast Ethernet only. */
841 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
842 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 843 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
844 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 845 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 846 netif_msg_link(tp)) {
847 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
848 dev->name);
849 }
64e4bfb4 850 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 851 }
852
623a1593
FR		 853 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
854
e3cf0cc0
FR		 855 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
856 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 857 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
858 mdio_write(ioaddr, 0x1f, 0x0000);
859 mdio_write(ioaddr, 0x0e, 0x0000);
860 }
861
1da177e4
LT		 862 tp->phy_auto_nego_reg = auto_nego;
863 tp->phy_1000_ctrl_reg = giga_ctrl;
864
64e4bfb4
FR		 865 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
866 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
867 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 868 return 0;
869}
870
871static int rtl8169_set_speed(struct net_device *dev,
872 u8 autoneg, u16 speed, u8 duplex)
873{
874 struct rtl8169_private *tp = netdev_priv(dev);
875 int ret;
876
877 ret = tp->set_speed(dev, autoneg, speed, duplex);
878
64e4bfb4 879 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 880 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
881
882 return ret;
883}
884
885static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
886{
887 struct rtl8169_private *tp = netdev_priv(dev);
888 unsigned long flags;
889 int ret;
890
891 spin_lock_irqsave(&tp->lock, flags);
892 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
893 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 894
1da177e4
LT		 895 return ret;
896}
897
898static u32 rtl8169_get_rx_csum(struct net_device *dev)
899{
900 struct rtl8169_private *tp = netdev_priv(dev);
901
902 return tp->cp_cmd & RxChkSum;
903}
904
905static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
906{
907 struct rtl8169_private *tp = netdev_priv(dev);
908 void __iomem *ioaddr = tp->mmio_addr;
909 unsigned long flags;
910
911 spin_lock_irqsave(&tp->lock, flags);
912
913 if (data)
914 tp->cp_cmd |= RxChkSum;
915 else
916 tp->cp_cmd &= ~RxChkSum;
917
918 RTL_W16(CPlusCmd, tp->cp_cmd);
919 RTL_R16(CPlusCmd);
920
921 spin_unlock_irqrestore(&tp->lock, flags);
922
923 return 0;
924}
925
926#ifdef CONFIG_R8169_VLAN
927
928static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
929 struct sk_buff *skb)
930{
931 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
932 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
933}
934
935static void rtl8169_vlan_rx_register(struct net_device *dev,
936 struct vlan_group *grp)
937{
938 struct rtl8169_private *tp = netdev_priv(dev);
939 void __iomem *ioaddr = tp->mmio_addr;
940 unsigned long flags;
941
942 spin_lock_irqsave(&tp->lock, flags);
943 tp->vlgrp = grp;
944 if (tp->vlgrp)
945 tp->cp_cmd |= RxVlan;
946 else
947 tp->cp_cmd &= ~RxVlan;
948 RTL_W16(CPlusCmd, tp->cp_cmd);
949 RTL_R16(CPlusCmd);
950 spin_unlock_irqrestore(&tp->lock, flags);
951}
952
1da177e4
LT		 953static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
954 struct sk_buff *skb)
955{
956 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 957 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 958 int ret;
959
865c652d
FR		 960 if (vlgrp && (opts2 & RxVlanTag)) {
961 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 962 ret = 0;
963 } else
964 ret = -1;
965 desc->opts2 = 0;
966 return ret;
967}
968
969#else /* !CONFIG_R8169_VLAN */
970
971static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
972 struct sk_buff *skb)
973{
974 return 0;
975}
976
977static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
978 struct sk_buff *skb)
979{
980 return -1;
981}
982
983#endif
984
ccdffb9a 985static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 986{
987 struct rtl8169_private *tp = netdev_priv(dev);
988 void __iomem *ioaddr = tp->mmio_addr;
989 u32 status;
990
991 cmd->supported =
992 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
993 cmd->port = PORT_FIBRE;
994 cmd->transceiver = XCVR_INTERNAL;
995
996 status = RTL_R32(TBICSR);
997 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
998 cmd->autoneg = !!(status & TBINwEnable);
999
1000 cmd->speed = SPEED_1000;
1001 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1002
1003 return 0;
1da177e4
LT		 1004}
1005
ccdffb9a 1006static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1007{
1008 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1009
1010 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1011}
1012
1013static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1014{
1015 struct rtl8169_private *tp = netdev_priv(dev);
1016 unsigned long flags;
ccdffb9a 1017 int rc;
1da177e4
LT		 1018
1019 spin_lock_irqsave(&tp->lock, flags);
1020
ccdffb9a 1021 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1022
1023 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1024 return rc;
1da177e4
LT		 1025}
1026
1027static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1028 void *p)
1029{
5b0384f4
FR		 1030 struct rtl8169_private *tp = netdev_priv(dev);
1031 unsigned long flags;
1da177e4 1032
5b0384f4
FR		 1033 if (regs->len > R8169_REGS_SIZE)
1034 regs->len = R8169_REGS_SIZE;
1da177e4 1035
5b0384f4
FR		 1036 spin_lock_irqsave(&tp->lock, flags);
1037 memcpy_fromio(p, tp->mmio_addr, regs->len);
1038 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1039}
1040
b57b7e5a
SH		 1041static u32 rtl8169_get_msglevel(struct net_device *dev)
1042{
1043 struct rtl8169_private *tp = netdev_priv(dev);
1044
1045 return tp->msg_enable;
1046}
1047
1048static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1049{
1050 struct rtl8169_private *tp = netdev_priv(dev);
1051
1052 tp->msg_enable = value;
1053}
1054
d4a3a0fc
SH		 1055static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1056 "tx_packets",
1057 "rx_packets",
1058 "tx_errors",
1059 "rx_errors",
1060 "rx_missed",
1061 "align_errors",
1062 "tx_single_collisions",
1063 "tx_multi_collisions",
1064 "unicast",
1065 "broadcast",
1066 "multicast",
1067 "tx_aborted",
1068 "tx_underrun",
1069};
1070
1071struct rtl8169_counters {
b1eab701
AV		 1072 __le64 tx_packets;
1073 __le64 rx_packets;
1074 __le64 tx_errors;
1075 __le32 rx_errors;
1076 __le16 rx_missed;
1077 __le16 align_errors;
1078 __le32 tx_one_collision;
1079 __le32 tx_multi_collision;
1080 __le64 rx_unicast;
1081 __le64 rx_broadcast;
1082 __le32 rx_multicast;
1083 __le16 tx_aborted;
1084 __le16 tx_underun;
d4a3a0fc
SH		 1085};
1086
b9f2c044 1087static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1088{
b9f2c044
JG		 1089 switch (sset) {
1090 case ETH_SS_STATS:
1091 return ARRAY_SIZE(rtl8169_gstrings);
1092 default:
1093 return -EOPNOTSUPP;
1094 }
d4a3a0fc
SH		 1095}
1096
1097static void rtl8169_get_ethtool_stats(struct net_device *dev,
1098 struct ethtool_stats *stats, u64 *data)
1099{
1100 struct rtl8169_private *tp = netdev_priv(dev);
1101 void __iomem *ioaddr = tp->mmio_addr;
1102 struct rtl8169_counters *counters;
1103 dma_addr_t paddr;
1104 u32 cmd;
1105
1106 ASSERT_RTNL();
1107
1108 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1109 if (!counters)
1110 return;
1111
1112 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1113 cmd = (u64)paddr & DMA_32BIT_MASK;
1114 RTL_W32(CounterAddrLow, cmd);
1115 RTL_W32(CounterAddrLow, cmd | CounterDump);
1116
1117 while (RTL_R32(CounterAddrLow) & CounterDump) {
1118 if (msleep_interruptible(1))
1119 break;
1120 }
1121
1122 RTL_W32(CounterAddrLow, 0);
1123 RTL_W32(CounterAddrHigh, 0);
1124
5b0384f4 1125 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1126 data[1] = le64_to_cpu(counters->rx_packets);
1127 data[2] = le64_to_cpu(counters->tx_errors);
1128 data[3] = le32_to_cpu(counters->rx_errors);
1129 data[4] = le16_to_cpu(counters->rx_missed);
1130 data[5] = le16_to_cpu(counters->align_errors);
1131 data[6] = le32_to_cpu(counters->tx_one_collision);
1132 data[7] = le32_to_cpu(counters->tx_multi_collision);
1133 data[8] = le64_to_cpu(counters->rx_unicast);
1134 data[9] = le64_to_cpu(counters->rx_broadcast);
1135 data[10] = le32_to_cpu(counters->rx_multicast);
1136 data[11] = le16_to_cpu(counters->tx_aborted);
1137 data[12] = le16_to_cpu(counters->tx_underun);
1138
1139 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1140}
1141
1142static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1143{
1144 switch(stringset) {
1145 case ETH_SS_STATS:
1146 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1147 break;
1148 }
1149}
1150
7282d491 1151static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1152 .get_drvinfo = rtl8169_get_drvinfo,
1153 .get_regs_len = rtl8169_get_regs_len,
1154 .get_link = ethtool_op_get_link,
1155 .get_settings = rtl8169_get_settings,
1156 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1157 .get_msglevel = rtl8169_get_msglevel,
1158 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1159 .get_rx_csum = rtl8169_get_rx_csum,
1160 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1161 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1162 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1163 .set_tso = ethtool_op_set_tso,
1164 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1165 .get_wol = rtl8169_get_wol,
1166 .set_wol = rtl8169_set_wol,
d4a3a0fc 1167 .get_strings = rtl8169_get_strings,
b9f2c044 1168 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1169 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1170};
1171
07d3f51f
FR		 1172static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1173 int bitnum, int bitval)
1da177e4
LT		 1174{
1175 int val;
1176
1177 val = mdio_read(ioaddr, reg);
1178 val = (bitval == 1) ?
1179 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1180 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1181}
1182
07d3f51f
FR		 1183static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1184 void __iomem *ioaddr)
1da177e4 1185{
0e485150
FR		 1186 /*
1187 * The driver currently handles the 8168Bf and the 8168Be identically
1188 * but they can be identified more specifically through the test below
1189 * if needed:
1190 *
1191 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1192 *
1193 * Same thing for the 8101Eb and the 8101Ec:
1194 *
1195 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1196 */
1da177e4
LT		 1197 const struct {
1198 u32 mask;
e3cf0cc0 1199 u32 val;
1da177e4
LT		 1200 int mac_version;
1201 } mac_info[] = {
e3cf0cc0
FR		 1202 /* 8168B family. */
1203 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1204 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1205 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1206 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1207
1208 /* 8168B family. */
1209 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1210 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1211 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1212 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1213
1214 /* 8101 family. */
1215 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1216 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1217 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1218 /* FIXME: where did these entries come from ? -- FR */
1219 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1220 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1221
1222 /* 8110 family. */
1223 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1224 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1225 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1226 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1227 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1228 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1229
1230 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1231 }, *p = mac_info;
1232 u32 reg;
1233
e3cf0cc0
FR		 1234 reg = RTL_R32(TxConfig);
1235 while ((reg & p->mask) != p->val)
1da177e4
LT		 1236 p++;
1237 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1238
1239 if (p->mask == 0x00000000) {
1240 struct pci_dev *pdev = tp->pci_dev;
1241
1242 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1243 }
1da177e4
LT		 1244}
1245
1246static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1247{
bcf0bf90 1248 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1249}
1250
867763c1
FR		 1251struct phy_reg {
1252 u16 reg;
1253 u16 val;
1254};
1255
1256static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1257{
1258 while (len-- > 0) {
1259 mdio_write(ioaddr, regs->reg, regs->val);
1260 regs++;
1261 }
1262}
1263
5615d9f1 1264static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1265{
1da177e4
LT		 1266 struct {
1267 u16 regs[5]; /* Beware of bit-sign propagation */
1268 } phy_magic[5] = { {
1269 { 0x0000, //w 4 15 12 0
1270 0x00a1, //w 3 15 0 00a1
1271 0x0008, //w 2 15 0 0008
1272 0x1020, //w 1 15 0 1020
1273 0x1000 } },{ //w 0 15 0 1000
1274 { 0x7000, //w 4 15 12 7
1275 0xff41, //w 3 15 0 ff41
1276 0xde60, //w 2 15 0 de60
1277 0x0140, //w 1 15 0 0140
1278 0x0077 } },{ //w 0 15 0 0077
1279 { 0xa000, //w 4 15 12 a
1280 0xdf01, //w 3 15 0 df01
1281 0xdf20, //w 2 15 0 df20
1282 0xff95, //w 1 15 0 ff95
1283 0xfa00 } },{ //w 0 15 0 fa00
1284 { 0xb000, //w 4 15 12 b
1285 0xff41, //w 3 15 0 ff41
1286 0xde20, //w 2 15 0 de20
1287 0x0140, //w 1 15 0 0140
1288 0x00bb } },{ //w 0 15 0 00bb
1289 { 0xf000, //w 4 15 12 f
1290 0xdf01, //w 3 15 0 df01
1291 0xdf20, //w 2 15 0 df20
1292 0xff95, //w 1 15 0 ff95
1293 0xbf00 } //w 0 15 0 bf00
1294 }
1295 }, *p = phy_magic;
07d3f51f 1296 unsigned int i;
1da177e4 1297
a441d7b6
FR		 1298 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1299 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1300 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1301 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1302
1303 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1304 int val, pos = 4;
1305
1306 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1307 mdio_write(ioaddr, pos, val);
1308 while (--pos >= 0)
1309 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1310 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1311 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1312 }
a441d7b6 1313 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1314}
1315
5615d9f1
FR		 1316static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1317{
a441d7b6
FR		 1318 struct phy_reg phy_reg_init[] = {
1319 { 0x1f, 0x0002 },
1320 { 0x01, 0x90d0 },
1321 { 0x1f, 0x0000 }
1322 };
1323
1324 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1325}
1326
867763c1
FR		 1327static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1328{
1329 struct phy_reg phy_reg_init[] = {
1330 { 0x1f, 0x0000 },
1331 { 0x1d, 0x0f00 },
1332 { 0x1f, 0x0002 },
1333 { 0x0c, 0x1ec8 },
1334 { 0x1f, 0x0000 }
1335 };
1336
1337 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1338}
1339
1340static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1341{
1342 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1343 { 0x1f, 0x0001 },
1344 { 0x12, 0x2300 },
867763c1
FR		 1345 { 0x1f, 0x0002 },
1346 { 0x00, 0x88d4 },
1347 { 0x01, 0x82b1 },
1348 { 0x03, 0x7002 },
1349 { 0x08, 0x9e30 },
1350 { 0x09, 0x01f0 },
1351 { 0x0a, 0x5500 },
1352 { 0x0c, 0x00c8 },
1353 { 0x1f, 0x0003 },
1354 { 0x12, 0xc096 },
1355 { 0x16, 0x000a },
1356 { 0x1f, 0x0000 }
1357 };
1358
1359 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1360}
1361
7da97ec9
FR		 1362static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1363{
1364 struct phy_reg phy_reg_init[] = {
1365 { 0x1f, 0x0000 },
1366 { 0x12, 0x2300 },
1367 { 0x1f, 0x0003 },
1368 { 0x16, 0x0f0a },
1369 { 0x1f, 0x0000 },
1370 { 0x1f, 0x0002 },
1371 { 0x0c, 0x7eb8 },
1372 { 0x1f, 0x0000 }
1373 };
1374
1375 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1376}
1377
5615d9f1
FR		 1378static void rtl_hw_phy_config(struct net_device *dev)
1379{
1380 struct rtl8169_private *tp = netdev_priv(dev);
1381 void __iomem *ioaddr = tp->mmio_addr;
1382
1383 rtl8169_print_mac_version(tp);
1384
1385 switch (tp->mac_version) {
1386 case RTL_GIGA_MAC_VER_01:
1387 break;
1388 case RTL_GIGA_MAC_VER_02:
1389 case RTL_GIGA_MAC_VER_03:
1390 rtl8169s_hw_phy_config(ioaddr);
1391 break;
1392 case RTL_GIGA_MAC_VER_04:
1393 rtl8169sb_hw_phy_config(ioaddr);
1394 break;
867763c1
FR		 1395 case RTL_GIGA_MAC_VER_18:
1396 rtl8168cp_hw_phy_config(ioaddr);
1397 break;
1398 case RTL_GIGA_MAC_VER_19:
1399 rtl8168c_hw_phy_config(ioaddr);
1400 break;
7da97ec9
FR		 1401 case RTL_GIGA_MAC_VER_20:
1402 rtl8168cx_hw_phy_config(ioaddr);
1403 break;
5615d9f1
FR		 1404 default:
1405 break;
1406 }
1407}
1408
1da177e4
LT		 1409static void rtl8169_phy_timer(unsigned long __opaque)
1410{
1411 struct net_device *dev = (struct net_device *)__opaque;
1412 struct rtl8169_private *tp = netdev_priv(dev);
1413 struct timer_list *timer = &tp->timer;
1414 void __iomem *ioaddr = tp->mmio_addr;
1415 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1416
bcf0bf90 1417 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1418
64e4bfb4 1419 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1420 return;
1421
1422 spin_lock_irq(&tp->lock);
1423
1424 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1425 /*
1da177e4
LT		 1426 * A busy loop could burn quite a few cycles on nowadays CPU.
1427 * Let's delay the execution of the timer for a few ticks.
1428 */
1429 timeout = HZ/10;
1430 goto out_mod_timer;
1431 }
1432
1433 if (tp->link_ok(ioaddr))
1434 goto out_unlock;
1435
b57b7e5a
SH		 1436 if (netif_msg_link(tp))
1437 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1438
1439 tp->phy_reset_enable(ioaddr);
1440
1441out_mod_timer:
1442 mod_timer(timer, jiffies + timeout);
1443out_unlock:
1444 spin_unlock_irq(&tp->lock);
1445}
1446
1447static inline void rtl8169_delete_timer(struct net_device *dev)
1448{
1449 struct rtl8169_private *tp = netdev_priv(dev);
1450 struct timer_list *timer = &tp->timer;
1451
e179bb7b 1452 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1453 return;
1454
1455 del_timer_sync(timer);
1456}
1457
1458static inline void rtl8169_request_timer(struct net_device *dev)
1459{
1460 struct rtl8169_private *tp = netdev_priv(dev);
1461 struct timer_list *timer = &tp->timer;
1462
e179bb7b 1463 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1464 return;
1465
2efa53f3 1466 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1467}
1468
1469#ifdef CONFIG_NET_POLL_CONTROLLER
1470/*
1471 * Polling 'interrupt' - used by things like netconsole to send skbs
1472 * without having to re-enable interrupts. It's not called while
1473 * the interrupt routine is executing.
1474 */
1475static void rtl8169_netpoll(struct net_device *dev)
1476{
1477 struct rtl8169_private *tp = netdev_priv(dev);
1478 struct pci_dev *pdev = tp->pci_dev;
1479
1480 disable_irq(pdev->irq);
7d12e780 1481 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1482 enable_irq(pdev->irq);
1483}
1484#endif
1485
1486static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1487 void __iomem *ioaddr)
1488{
1489 iounmap(ioaddr);
1490 pci_release_regions(pdev);
1491 pci_disable_device(pdev);
1492 free_netdev(dev);
1493}
1494
bf793295
FR		 1495static void rtl8169_phy_reset(struct net_device *dev,
1496 struct rtl8169_private *tp)
1497{
1498 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1499 unsigned int i;
bf793295
FR		 1500
1501 tp->phy_reset_enable(ioaddr);
1502 for (i = 0; i < 100; i++) {
1503 if (!tp->phy_reset_pending(ioaddr))
1504 return;
1505 msleep(1);
1506 }
1507 if (netif_msg_link(tp))
1508 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1509}
1510
4ff96fa6
FR		 1511static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1512{
1513 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1514
5615d9f1 1515 rtl_hw_phy_config(dev);
4ff96fa6 1516
77332894
MS		 1517 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1518 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1519 RTL_W8(0x82, 0x01);
1520 }
4ff96fa6 1521
6dccd16b
FR		 1522 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1523
1524 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1525 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1526
bcf0bf90 1527 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1528 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1529 RTL_W8(0x82, 0x01);
1530 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1531 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1532 }
1533
bf793295
FR		 1534 rtl8169_phy_reset(dev, tp);
1535
901dda2b
FR		 1536 /*
1537 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1538 * only 8101. Don't panic.
1539 */
1540 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1541
1542 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1543 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1544}
1545
773d2021
FR		 1546static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1547{
1548 void __iomem *ioaddr = tp->mmio_addr;
1549 u32 high;
1550 u32 low;
1551
1552 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1553 high = addr[4] | (addr[5] << 8);
1554
1555 spin_lock_irq(&tp->lock);
1556
1557 RTL_W8(Cfg9346, Cfg9346_Unlock);
1558 RTL_W32(MAC0, low);
1559 RTL_W32(MAC4, high);
1560 RTL_W8(Cfg9346, Cfg9346_Lock);
1561
1562 spin_unlock_irq(&tp->lock);
1563}
1564
1565static int rtl_set_mac_address(struct net_device *dev, void *p)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 struct sockaddr *addr = p;
1569
1570 if (!is_valid_ether_addr(addr->sa_data))
1571 return -EADDRNOTAVAIL;
1572
1573 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1574
1575 rtl_rar_set(tp, dev->dev_addr);
1576
1577 return 0;
1578}
1579
5f787a1a
FR		 1580static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1581{
1582 struct rtl8169_private *tp = netdev_priv(dev);
1583 struct mii_ioctl_data *data = if_mii(ifr);
1584
1585 if (!netif_running(dev))
1586 return -ENODEV;
1587
1588 switch (cmd) {
1589 case SIOCGMIIPHY:
1590 data->phy_id = 32; /* Internal PHY */
1591 return 0;
1592
1593 case SIOCGMIIREG:
1594 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1595 return 0;
1596
1597 case SIOCSMIIREG:
1598 if (!capable(CAP_NET_ADMIN))
1599 return -EPERM;
1600 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1601 return 0;
1602 }
1603 return -EOPNOTSUPP;
1604}
1605
0e485150
FR		 1606static const struct rtl_cfg_info {
1607 void (*hw_start)(struct net_device *);
1608 unsigned int region;
1609 unsigned int align;
1610 u16 intr_event;
1611 u16 napi_event;
ccdffb9a 1612 unsigned features;
0e485150
FR		 1613} rtl_cfg_infos [] = {
1614 [RTL_CFG_0] = {
1615 .hw_start = rtl_hw_start_8169,
1616 .region = 1,
e9f63f30 1617 .align = 0,
0e485150
FR		 1618 .intr_event = SYSErr | LinkChg | RxOverflow |
1619 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1620 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1621 .features = RTL_FEATURE_GMII
0e485150
FR		 1622 },
1623 [RTL_CFG_1] = {
1624 .hw_start = rtl_hw_start_8168,
1625 .region = 2,
1626 .align = 8,
1627 .intr_event = SYSErr | LinkChg | RxOverflow |
1628 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1629 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1630 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1631 },
1632 [RTL_CFG_2] = {
1633 .hw_start = rtl_hw_start_8101,
1634 .region = 2,
1635 .align = 8,
1636 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1637 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1638 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1639 .features = RTL_FEATURE_MSI
0e485150
FR		 1640 }
1641};
1642
fbac58fc
FR		 1643/* Cfg9346_Unlock assumed. */
1644static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1645 const struct rtl_cfg_info *cfg)
1646{
1647 unsigned msi = 0;
1648 u8 cfg2;
1649
1650 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1651 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1652 if (pci_enable_msi(pdev)) {
1653 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1654 } else {
1655 cfg2 |= MSIEnable;
1656 msi = RTL_FEATURE_MSI;
1657 }
1658 }
1659 RTL_W8(Config2, cfg2);
1660 return msi;
1661}
1662
1663static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1664{
1665 if (tp->features & RTL_FEATURE_MSI) {
1666 pci_disable_msi(pdev);
1667 tp->features &= ~RTL_FEATURE_MSI;
1668 }
1669}
1670
1da177e4 1671static int __devinit
4ff96fa6 1672rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1673{
0e485150
FR		 1674 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1675 const unsigned int region = cfg->region;
1da177e4 1676 struct rtl8169_private *tp;
ccdffb9a 1677 struct mii_if_info *mii;
4ff96fa6
FR		 1678 struct net_device *dev;
1679 void __iomem *ioaddr;
07d3f51f
FR		 1680 unsigned int i;
1681 int rc;
1da177e4 1682
4ff96fa6
FR		 1683 if (netif_msg_drv(&debug)) {
1684 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1685 MODULENAME, RTL8169_VERSION);
1686 }
1da177e4 1687
1da177e4 1688 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1689 if (!dev) {
b57b7e5a 1690 if (netif_msg_drv(&debug))
9b91cf9d 1691 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1692 rc = -ENOMEM;
1693 goto out;
1da177e4
LT		 1694 }
1695
1da177e4
LT		 1696 SET_NETDEV_DEV(dev, &pdev->dev);
1697 tp = netdev_priv(dev);
c4028958 1698 tp->dev = dev;
21e197f2 1699 tp->pci_dev = pdev;
b57b7e5a 1700 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1701
ccdffb9a
FR		 1702 mii = &tp->mii;
1703 mii->dev = dev;
1704 mii->mdio_read = rtl_mdio_read;
1705 mii->mdio_write = rtl_mdio_write;
1706 mii->phy_id_mask = 0x1f;
1707 mii->reg_num_mask = 0x1f;
1708 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1709
1da177e4
LT		 1710 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1711 rc = pci_enable_device(pdev);
b57b7e5a 1712 if (rc < 0) {
2e8a538d 1713 if (netif_msg_probe(tp))
9b91cf9d 1714 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1715 goto err_out_free_dev_1;
1da177e4
LT		 1716 }
1717
1718 rc = pci_set_mwi(pdev);
1719 if (rc < 0)
4ff96fa6 1720 goto err_out_disable_2;
1da177e4 1721
1da177e4 1722 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1723 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1724 if (netif_msg_probe(tp)) {
9b91cf9d 1725 dev_err(&pdev->dev,
bcf0bf90
FR		 1726 "region #%d not an MMIO resource, aborting\n",
1727 region);
4ff96fa6 1728 }
1da177e4 1729 rc = -ENODEV;
4ff96fa6 1730 goto err_out_mwi_3;
1da177e4 1731 }
4ff96fa6 1732
1da177e4 1733 /* check for weird/broken PCI region reporting */
bcf0bf90 1734 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1735 if (netif_msg_probe(tp)) {
9b91cf9d 1736 dev_err(&pdev->dev,
4ff96fa6
FR		 1737 "Invalid PCI region size(s), aborting\n");
1738 }
1da177e4 1739 rc = -ENODEV;
4ff96fa6 1740 goto err_out_mwi_3;
1da177e4
LT		 1741 }
1742
1743 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1744 if (rc < 0) {
2e8a538d 1745 if (netif_msg_probe(tp))
9b91cf9d 1746 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1747 goto err_out_mwi_3;
1da177e4
LT		 1748 }
1749
1750 tp->cp_cmd = PCIMulRW | RxChkSum;
1751
1752 if ((sizeof(dma_addr_t) > 4) &&
1753 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1754 tp->cp_cmd |= PCIDAC;
1755 dev->features |= NETIF_F_HIGHDMA;
1756 } else {
1757 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1758 if (rc < 0) {
4ff96fa6 1759 if (netif_msg_probe(tp)) {
9b91cf9d 1760 dev_err(&pdev->dev,
4ff96fa6
FR		 1761 "DMA configuration failed.\n");
1762 }
1763 goto err_out_free_res_4;
1da177e4
LT		 1764 }
1765 }
1766
1767 pci_set_master(pdev);
1768
1769 /* ioremap MMIO region */
bcf0bf90 1770 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1771 if (!ioaddr) {
b57b7e5a 1772 if (netif_msg_probe(tp))
9b91cf9d 1773 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1774 rc = -EIO;
4ff96fa6 1775 goto err_out_free_res_4;
1da177e4
LT		 1776 }
1777
9c14ceaf
FR		 1778 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1779 if (!tp->pcie_cap && netif_msg_probe(tp))
1780 dev_info(&pdev->dev, "no PCI Express capability\n");
1781
1da177e4
LT		 1782 /* Unneeded ? Don't mess with Mrs. Murphy. */
1783 rtl8169_irq_mask_and_ack(ioaddr);
1784
1785 /* Soft reset the chip. */
1786 RTL_W8(ChipCmd, CmdReset);
1787
1788 /* Check that the chip has finished the reset. */
07d3f51f 1789 for (i = 0; i < 100; i++) {
1da177e4
LT		 1790 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1791 break;
b518fa8e 1792 msleep_interruptible(1);
1da177e4
LT		 1793 }
1794
1795 /* Identify chip attached to board */
1796 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1797
1798 rtl8169_print_mac_version(tp);
1da177e4 1799
cee60c37 1800 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 1801 if (tp->mac_version == rtl_chip_info[i].mac_version)
1802 break;
1803 }
cee60c37 1804 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 1805 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1806 if (netif_msg_probe(tp)) {
2e8a538d 1807 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1808 "unknown chip version, assuming %s\n",
1809 rtl_chip_info[0].name);
b57b7e5a 1810 }
cee60c37 1811 i = 0;
1da177e4
LT		 1812 }
1813 tp->chipset = i;
1814
5d06a99f
FR		 1815 RTL_W8(Cfg9346, Cfg9346_Unlock);
1816 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1817 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1818 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1819 RTL_W8(Cfg9346, Cfg9346_Lock);
1820
66ec5d4f
FR		 1821 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1822 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 1823 tp->set_speed = rtl8169_set_speed_tbi;
1824 tp->get_settings = rtl8169_gset_tbi;
1825 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1826 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1827 tp->link_ok = rtl8169_tbi_link_ok;
1828
64e4bfb4 1829 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1830 } else {
1831 tp->set_speed = rtl8169_set_speed_xmii;
1832 tp->get_settings = rtl8169_gset_xmii;
1833 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1834 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1835 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1836
1837 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1838 }
1839
1840 /* Get MAC address. FIXME: read EEPROM */
1841 for (i = 0; i < MAC_ADDR_LEN; i++)
1842 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1843 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1844
1845 dev->open = rtl8169_open;
1846 dev->hard_start_xmit = rtl8169_start_xmit;
1847 dev->get_stats = rtl8169_get_stats;
1848 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1849 dev->stop = rtl8169_close;
1850 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1851 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1852 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1853 dev->irq = pdev->irq;
1854 dev->base_addr = (unsigned long) ioaddr;
1855 dev->change_mtu = rtl8169_change_mtu;
773d2021 1856 dev->set_mac_address = rtl_set_mac_address;
1da177e4 1857
bea3348e 1858 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1859
1860#ifdef CONFIG_R8169_VLAN
1861 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1862 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1863#endif
1864
1865#ifdef CONFIG_NET_POLL_CONTROLLER
1866 dev->poll_controller = rtl8169_netpoll;
1867#endif
1868
1869 tp->intr_mask = 0xffff;
1da177e4 1870 tp->mmio_addr = ioaddr;
0e485150
FR		 1871 tp->align = cfg->align;
1872 tp->hw_start = cfg->hw_start;
1873 tp->intr_event = cfg->intr_event;
1874 tp->napi_event = cfg->napi_event;
1da177e4 1875
2efa53f3
FR		 1876 init_timer(&tp->timer);
1877 tp->timer.data = (unsigned long) dev;
1878 tp->timer.function = rtl8169_phy_timer;
1879
1da177e4
LT		 1880 spin_lock_init(&tp->lock);
1881
1882 rc = register_netdev(dev);
4ff96fa6 1883 if (rc < 0)
fbac58fc 1884 goto err_out_msi_5;
1da177e4
LT		 1885
1886 pci_set_drvdata(pdev, dev);
1887
b57b7e5a 1888 if (netif_msg_probe(tp)) {
96b9709c
FR		 1889 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1890
b57b7e5a
SH		 1891 printk(KERN_INFO "%s: %s at 0x%lx, "
1892 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1893 "XID %08x IRQ %d\n",
b57b7e5a 1894 dev->name,
bcf0bf90 1895 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1896 dev->base_addr,
1897 dev->dev_addr[0], dev->dev_addr[1],
1898 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1899 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1900 }
1da177e4 1901
4ff96fa6 1902 rtl8169_init_phy(dev, tp);
1da177e4 1903
4ff96fa6
FR		 1904out:
1905 return rc;
1da177e4 1906
fbac58fc
FR		 1907err_out_msi_5:
1908 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1909 iounmap(ioaddr);
1910err_out_free_res_4:
1911 pci_release_regions(pdev);
1912err_out_mwi_3:
1913 pci_clear_mwi(pdev);
1914err_out_disable_2:
1915 pci_disable_device(pdev);
1916err_out_free_dev_1:
1917 free_netdev(dev);
1918 goto out;
1da177e4
LT		 1919}
1920
07d3f51f 1921static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1922{
1923 struct net_device *dev = pci_get_drvdata(pdev);
1924 struct rtl8169_private *tp = netdev_priv(dev);
1925
eb2a021c
FR		 1926 flush_scheduled_work();
1927
1da177e4 1928 unregister_netdev(dev);
fbac58fc 1929 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1930 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1931 pci_set_drvdata(pdev, NULL);
1932}
1933
1da177e4
LT		 1934static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1935 struct net_device *dev)
1936{
1937 unsigned int mtu = dev->mtu;
1938
1939 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1940}
1941
1942static int rtl8169_open(struct net_device *dev)
1943{
1944 struct rtl8169_private *tp = netdev_priv(dev);
1945 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1946 int retval = -ENOMEM;
1da177e4 1947
1da177e4 1948
99f252b0 1949 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1950
1951 /*
1952 * Rx and Tx desscriptors needs 256 bytes alignment.
1953 * pci_alloc_consistent provides more.
1954 */
1955 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1956 &tp->TxPhyAddr);
1957 if (!tp->TxDescArray)
99f252b0 1958 goto out;
1da177e4
LT		 1959
1960 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1961 &tp->RxPhyAddr);
1962 if (!tp->RxDescArray)
99f252b0 1963 goto err_free_tx_0;
1da177e4
LT		 1964
1965 retval = rtl8169_init_ring(dev);
1966 if (retval < 0)
99f252b0 1967 goto err_free_rx_1;
1da177e4 1968
c4028958 1969 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1970
99f252b0
FR		 1971 smp_mb();
1972
fbac58fc
FR		 1973 retval = request_irq(dev->irq, rtl8169_interrupt,
1974 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1975 dev->name, dev);
1976 if (retval < 0)
1977 goto err_release_ring_2;
1978
bea3348e 1979 napi_enable(&tp->napi);
bea3348e 1980
07ce4064 1981 rtl_hw_start(dev);
1da177e4
LT		 1982
1983 rtl8169_request_timer(dev);
1984
1985 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1986out:
1987 return retval;
1988
99f252b0
FR		 1989err_release_ring_2:
1990 rtl8169_rx_clear(tp);
1991err_free_rx_1:
1da177e4
LT		 1992 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1993 tp->RxPhyAddr);
99f252b0 1994err_free_tx_0:
1da177e4
LT		 1995 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1996 tp->TxPhyAddr);
1da177e4
LT		 1997 goto out;
1998}
1999
2000static void rtl8169_hw_reset(void __iomem *ioaddr)
2001{
2002 /* Disable interrupts */
2003 rtl8169_irq_mask_and_ack(ioaddr);
2004
2005 /* Reset the chipset */
2006 RTL_W8(ChipCmd, CmdReset);
2007
2008 /* PCI commit */
2009 RTL_R8(ChipCmd);
2010}
2011
7f796d83 2012static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2013{
2014 void __iomem *ioaddr = tp->mmio_addr;
2015 u32 cfg = rtl8169_rx_config;
2016
2017 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2018 RTL_W32(RxConfig, cfg);
2019
2020 /* Set DMA burst size and Interframe Gap Time */
2021 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2022 (InterFrameGap << TxInterFrameGapShift));
2023}
2024
07ce4064 2025static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2026{
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2029 unsigned int i;
1da177e4
LT		 2030
2031 /* Soft reset the chip. */
2032 RTL_W8(ChipCmd, CmdReset);
2033
2034 /* Check that the chip has finished the reset. */
07d3f51f 2035 for (i = 0; i < 100; i++) {
1da177e4
LT		 2036 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2037 break;
b518fa8e 2038 msleep_interruptible(1);
1da177e4
LT		 2039 }
2040
07ce4064
FR		 2041 tp->hw_start(dev);
2042
07ce4064
FR		 2043 netif_start_queue(dev);
2044}
2045
2046
7f796d83
FR		 2047static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2048 void __iomem *ioaddr)
2049{
2050 /*
2051 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2052 * register to be written before TxDescAddrLow to work.
2053 * Switching from MMIO to I/O access fixes the issue as well.
2054 */
2055 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2056 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2057 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2058 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2059}
2060
2061static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2062{
2063 u16 cmd;
2064
2065 cmd = RTL_R16(CPlusCmd);
2066 RTL_W16(CPlusCmd, cmd);
2067 return cmd;
2068}
2069
2070static void rtl_set_rx_max_size(void __iomem *ioaddr)
2071{
2072 /* Low hurts. Let's disable the filtering. */
2073 RTL_W16(RxMaxSize, 16383);
2074}
2075
6dccd16b
FR		 2076static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2077{
2078 struct {
2079 u32 mac_version;
2080 u32 clk;
2081 u32 val;
2082 } cfg2_info [] = {
2083 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2084 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2085 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2086 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2087 }, *p = cfg2_info;
2088 unsigned int i;
2089 u32 clk;
2090
2091 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2092 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2093 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2094 RTL_W32(0x7c, p->val);
2095 break;
2096 }
2097 }
2098}
2099
07ce4064
FR		 2100static void rtl_hw_start_8169(struct net_device *dev)
2101{
2102 struct rtl8169_private *tp = netdev_priv(dev);
2103 void __iomem *ioaddr = tp->mmio_addr;
2104 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2105
9cb427b6
FR		 2106 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2107 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2108 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2109 }
2110
1da177e4 2111 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2112 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2113 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2114 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2115 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2116 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2117
1da177e4
LT		 2118 RTL_W8(EarlyTxThres, EarlyTxThld);
2119
7f796d83 2120 rtl_set_rx_max_size(ioaddr);
1da177e4 2121
c946b304
FR		 2122 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2123 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2124 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2125 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2126 rtl_set_rx_tx_config_registers(tp);
1da177e4 2127
7f796d83 2128 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2129
bcf0bf90
FR		 2130 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2131 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2132 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2133 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2134 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2135 }
2136
bcf0bf90
FR		 2137 RTL_W16(CPlusCmd, tp->cp_cmd);
2138
6dccd16b
FR		 2139 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2140
1da177e4
LT		 2141 /*
2142 * Undocumented corner. Supposedly:
2143 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2144 */
2145 RTL_W16(IntrMitigate, 0x0000);
2146
7f796d83 2147 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2148
c946b304
FR		 2149 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2150 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2151 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2152 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2153 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2154 rtl_set_rx_tx_config_registers(tp);
2155 }
2156
1da177e4 2157 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2158
2159 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2160 RTL_R8(IntrMask);
1da177e4
LT		 2161
2162 RTL_W32(RxMissed, 0);
2163
07ce4064 2164 rtl_set_rx_mode(dev);
1da177e4
LT		 2165
2166 /* no early-rx interrupts */
2167 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2168
2169 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2170 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2171}
1da177e4 2172
9c14ceaf 2173static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2174{
9c14ceaf
FR		 2175 struct net_device *dev = pci_get_drvdata(pdev);
2176 struct rtl8169_private *tp = netdev_priv(dev);
2177 int cap = tp->pcie_cap;
2178
2179 if (cap) {
2180 u16 ctl;
458a9f61 2181
9c14ceaf
FR		 2182 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2183 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2184 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2185 }
458a9f61
FR		 2186}
2187
dacf8154
FR		 2188static void rtl_csi_access_enable(void __iomem *ioaddr)
2189{
2190 u32 csi;
2191
2192 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2193 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2194}
2195
2196struct ephy_info {
2197 unsigned int offset;
2198 u16 mask;
2199 u16 bits;
2200};
2201
2202static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2203{
2204 u16 w;
2205
2206 while (len-- > 0) {
2207 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2208 rtl_ephy_write(ioaddr, e->offset, w);
2209 e++;
2210 }
2211}
2212
07ce4064
FR		 2213static void rtl_hw_start_8168(struct net_device *dev)
2214{
2dd99530
FR		 2215 struct rtl8169_private *tp = netdev_priv(dev);
2216 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2217 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2218
2219 RTL_W8(Cfg9346, Cfg9346_Unlock);
2220
2221 RTL_W8(EarlyTxThres, EarlyTxThld);
2222
2223 rtl_set_rx_max_size(ioaddr);
2224
0e485150
FR		 2225 rtl_set_rx_tx_config_registers(tp);
2226
2227 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2228
2229 RTL_W16(CPlusCmd, tp->cp_cmd);
2230
9c14ceaf 2231 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2dd99530 2232
0e485150 2233 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2234
0e485150
FR		 2235 /* Work around for RxFIFO overflow. */
2236 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2237 tp->intr_event |= RxFIFOOver | PCSTimeout;
2238 tp->intr_event &= ~RxOverflow;
2239 }
2240
2241 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2242
2243 RTL_W8(Cfg9346, Cfg9346_Lock);
2244
2245 RTL_R8(IntrMask);
2246
2247 RTL_W32(RxMissed, 0);
2248
2249 rtl_set_rx_mode(dev);
2250
0e485150
FR		 2251 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2252
2dd99530 2253 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2254
0e485150 2255 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2256}
1da177e4 2257
07ce4064
FR		 2258static void rtl_hw_start_8101(struct net_device *dev)
2259{
cdf1a608
FR		 2260 struct rtl8169_private *tp = netdev_priv(dev);
2261 void __iomem *ioaddr = tp->mmio_addr;
2262 struct pci_dev *pdev = tp->pci_dev;
2263
e3cf0cc0
FR		 2264 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2265 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2266 int cap = tp->pcie_cap;
2267
2268 if (cap) {
2269 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2270 PCI_EXP_DEVCTL_NOSNOOP_EN);
2271 }
cdf1a608
FR		 2272 }
2273
2274 RTL_W8(Cfg9346, Cfg9346_Unlock);
2275
2276 RTL_W8(EarlyTxThres, EarlyTxThld);
2277
2278 rtl_set_rx_max_size(ioaddr);
2279
2280 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2281
2282 RTL_W16(CPlusCmd, tp->cp_cmd);
2283
2284 RTL_W16(IntrMitigate, 0x0000);
2285
2286 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2287
2288 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2289 rtl_set_rx_tx_config_registers(tp);
2290
2291 RTL_W8(Cfg9346, Cfg9346_Lock);
2292
2293 RTL_R8(IntrMask);
2294
2295 RTL_W32(RxMissed, 0);
2296
2297 rtl_set_rx_mode(dev);
2298
0e485150
FR		 2299 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2300
cdf1a608 2301 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2302
0e485150 2303 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2304}
2305
2306static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2307{
2308 struct rtl8169_private *tp = netdev_priv(dev);
2309 int ret = 0;
2310
2311 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2312 return -EINVAL;
2313
2314 dev->mtu = new_mtu;
2315
2316 if (!netif_running(dev))
2317 goto out;
2318
2319 rtl8169_down(dev);
2320
2321 rtl8169_set_rxbufsize(tp, dev);
2322
2323 ret = rtl8169_init_ring(dev);
2324 if (ret < 0)
2325 goto out;
2326
bea3348e 2327 napi_enable(&tp->napi);
1da177e4 2328
07ce4064 2329 rtl_hw_start(dev);
1da177e4
LT		 2330
2331 rtl8169_request_timer(dev);
2332
2333out:
2334 return ret;
2335}
2336
2337static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2338{
95e0918d 2339 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2340 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2341}
2342
2343static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2344 struct sk_buff **sk_buff, struct RxDesc *desc)
2345{
2346 struct pci_dev *pdev = tp->pci_dev;
2347
2348 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2349 PCI_DMA_FROMDEVICE);
2350 dev_kfree_skb(*sk_buff);
2351 *sk_buff = NULL;
2352 rtl8169_make_unusable_by_asic(desc);
2353}
2354
2355static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2356{
2357 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2358
2359 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2360}
2361
2362static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2363 u32 rx_buf_sz)
2364{
2365 desc->addr = cpu_to_le64(mapping);
2366 wmb();
2367 rtl8169_mark_to_asic(desc, rx_buf_sz);
2368}
2369
15d31758
SH		 2370static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2371 struct net_device *dev,
2372 struct RxDesc *desc, int rx_buf_sz,
2373 unsigned int align)
1da177e4
LT		 2374{
2375 struct sk_buff *skb;
2376 dma_addr_t mapping;
e9f63f30 2377 unsigned int pad;
1da177e4 2378
e9f63f30
FR		 2379 pad = align ? align : NET_IP_ALIGN;
2380
2381 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2382 if (!skb)
2383 goto err_out;
2384
e9f63f30 2385 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2386
689be439 2387 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2388 PCI_DMA_FROMDEVICE);
2389
2390 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2391out:
15d31758 2392 return skb;
1da177e4
LT		 2393
2394err_out:
1da177e4
LT		 2395 rtl8169_make_unusable_by_asic(desc);
2396 goto out;
2397}
2398
2399static void rtl8169_rx_clear(struct rtl8169_private *tp)
2400{
07d3f51f 2401 unsigned int i;
1da177e4
LT		 2402
2403 for (i = 0; i < NUM_RX_DESC; i++) {
2404 if (tp->Rx_skbuff[i]) {
2405 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2406 tp->RxDescArray + i);
2407 }
2408 }
2409}
2410
2411static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2412 u32 start, u32 end)
2413{
2414 u32 cur;
5b0384f4 2415
4ae47c2d 2416 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2417 struct sk_buff *skb;
2418 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2419
4ae47c2d
FR		 2420 WARN_ON((s32)(end - cur) < 0);
2421
1da177e4
LT		 2422 if (tp->Rx_skbuff[i])
2423 continue;
bcf0bf90 2424
15d31758
SH		 2425 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2426 tp->RxDescArray + i,
2427 tp->rx_buf_sz, tp->align);
2428 if (!skb)
1da177e4 2429 break;
15d31758
SH		 2430
2431 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2432 }
2433 return cur - start;
2434}
2435
2436static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2437{
2438 desc->opts1 |= cpu_to_le32(RingEnd);
2439}
2440
2441static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2442{
2443 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2444}
2445
2446static int rtl8169_init_ring(struct net_device *dev)
2447{
2448 struct rtl8169_private *tp = netdev_priv(dev);
2449
2450 rtl8169_init_ring_indexes(tp);
2451
2452 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2453 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2454
2455 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2456 goto err_out;
2457
2458 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2459
2460 return 0;
2461
2462err_out:
2463 rtl8169_rx_clear(tp);
2464 return -ENOMEM;
2465}
2466
2467static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2468 struct TxDesc *desc)
2469{
2470 unsigned int len = tx_skb->len;
2471
2472 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2473 desc->opts1 = 0x00;
2474 desc->opts2 = 0x00;
2475 desc->addr = 0x00;
2476 tx_skb->len = 0;
2477}
2478
2479static void rtl8169_tx_clear(struct rtl8169_private *tp)
2480{
2481 unsigned int i;
2482
2483 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2484 unsigned int entry = i % NUM_TX_DESC;
2485 struct ring_info *tx_skb = tp->tx_skb + entry;
2486 unsigned int len = tx_skb->len;
2487
2488 if (len) {
2489 struct sk_buff *skb = tx_skb->skb;
2490
2491 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2492 tp->TxDescArray + entry);
2493 if (skb) {
2494 dev_kfree_skb(skb);
2495 tx_skb->skb = NULL;
2496 }
cebf8cc7 2497 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2498 }
2499 }
2500 tp->cur_tx = tp->dirty_tx = 0;
2501}
2502
c4028958 2503static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2504{
2505 struct rtl8169_private *tp = netdev_priv(dev);
2506
c4028958 2507 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2508 schedule_delayed_work(&tp->task, 4);
2509}
2510
2511static void rtl8169_wait_for_quiescence(struct net_device *dev)
2512{
2513 struct rtl8169_private *tp = netdev_priv(dev);
2514 void __iomem *ioaddr = tp->mmio_addr;
2515
2516 synchronize_irq(dev->irq);
2517
2518 /* Wait for any pending NAPI task to complete */
bea3348e 2519 napi_disable(&tp->napi);
1da177e4
LT		 2520
2521 rtl8169_irq_mask_and_ack(ioaddr);
2522
d1d08d12
DM		 2523 tp->intr_mask = 0xffff;
2524 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2525 napi_enable(&tp->napi);
1da177e4
LT		 2526}
2527
c4028958 2528static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2529{
c4028958
DH		 2530 struct rtl8169_private *tp =
2531 container_of(work, struct rtl8169_private, task.work);
2532 struct net_device *dev = tp->dev;
1da177e4
LT		 2533 int ret;
2534
eb2a021c
FR		 2535 rtnl_lock();
2536
2537 if (!netif_running(dev))
2538 goto out_unlock;
2539
2540 rtl8169_wait_for_quiescence(dev);
2541 rtl8169_close(dev);
1da177e4
LT		 2542
2543 ret = rtl8169_open(dev);
2544 if (unlikely(ret < 0)) {
07d3f51f 2545 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2546 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2547 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2548 }
2549 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2550 }
eb2a021c
FR		 2551
2552out_unlock:
2553 rtnl_unlock();
1da177e4
LT		 2554}
2555
c4028958 2556static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2557{
c4028958
DH		 2558 struct rtl8169_private *tp =
2559 container_of(work, struct rtl8169_private, task.work);
2560 struct net_device *dev = tp->dev;
1da177e4 2561
eb2a021c
FR		 2562 rtnl_lock();
2563
1da177e4 2564 if (!netif_running(dev))
eb2a021c 2565 goto out_unlock;
1da177e4
LT		 2566
2567 rtl8169_wait_for_quiescence(dev);
2568
bea3348e 2569 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2570 rtl8169_tx_clear(tp);
2571
2572 if (tp->dirty_rx == tp->cur_rx) {
2573 rtl8169_init_ring_indexes(tp);
07ce4064 2574 rtl_hw_start(dev);
1da177e4 2575 netif_wake_queue(dev);
cebf8cc7 2576 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2577 } else {
07d3f51f 2578 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2579 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2580 dev->name);
1da177e4
LT		 2581 }
2582 rtl8169_schedule_work(dev, rtl8169_reset_task);
2583 }
eb2a021c
FR		 2584
2585out_unlock:
2586 rtnl_unlock();
1da177e4
LT		 2587}
2588
2589static void rtl8169_tx_timeout(struct net_device *dev)
2590{
2591 struct rtl8169_private *tp = netdev_priv(dev);
2592
2593 rtl8169_hw_reset(tp->mmio_addr);
2594
2595 /* Let's wait a bit while any (async) irq lands on */
2596 rtl8169_schedule_work(dev, rtl8169_reset_task);
2597}
2598
2599static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2600 u32 opts1)
2601{
2602 struct skb_shared_info *info = skb_shinfo(skb);
2603 unsigned int cur_frag, entry;
a6343afb 2604 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2605
2606 entry = tp->cur_tx;
2607 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2608 skb_frag_t *frag = info->frags + cur_frag;
2609 dma_addr_t mapping;
2610 u32 status, len;
2611 void *addr;
2612
2613 entry = (entry + 1) % NUM_TX_DESC;
2614
2615 txd = tp->TxDescArray + entry;
2616 len = frag->size;
2617 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2618 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2619
2620 /* anti gcc 2.95.3 bugware (sic) */
2621 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2622
2623 txd->opts1 = cpu_to_le32(status);
2624 txd->addr = cpu_to_le64(mapping);
2625
2626 tp->tx_skb[entry].len = len;
2627 }
2628
2629 if (cur_frag) {
2630 tp->tx_skb[entry].skb = skb;
2631 txd->opts1 |= cpu_to_le32(LastFrag);
2632 }
2633
2634 return cur_frag;
2635}
2636
2637static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2638{
2639 if (dev->features & NETIF_F_TSO) {
7967168c 2640 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2641
2642 if (mss)
2643 return LargeSend | ((mss & MSSMask) << MSSShift);
2644 }
84fa7933 2645 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2646 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2647
2648 if (ip->protocol == IPPROTO_TCP)
2649 return IPCS | TCPCS;
2650 else if (ip->protocol == IPPROTO_UDP)
2651 return IPCS | UDPCS;
2652 WARN_ON(1); /* we need a WARN() */
2653 }
2654 return 0;
2655}
2656
2657static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2658{
2659 struct rtl8169_private *tp = netdev_priv(dev);
2660 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2661 struct TxDesc *txd = tp->TxDescArray + entry;
2662 void __iomem *ioaddr = tp->mmio_addr;
2663 dma_addr_t mapping;
2664 u32 status, len;
2665 u32 opts1;
188f4af0 2666 int ret = NETDEV_TX_OK;
5b0384f4 2667
1da177e4 2668 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2669 if (netif_msg_drv(tp)) {
2670 printk(KERN_ERR
2671 "%s: BUG! Tx Ring full when queue awake!\n",
2672 dev->name);
2673 }
1da177e4
LT		 2674 goto err_stop;
2675 }
2676
2677 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2678 goto err_stop;
2679
2680 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2681
2682 frags = rtl8169_xmit_frags(tp, skb, opts1);
2683 if (frags) {
2684 len = skb_headlen(skb);
2685 opts1 |= FirstFrag;
2686 } else {
2687 len = skb->len;
2688
2689 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2690 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2691 goto err_update_stats;
2692 len = ETH_ZLEN;
2693 }
2694
2695 opts1 |= FirstFrag | LastFrag;
2696 tp->tx_skb[entry].skb = skb;
2697 }
2698
2699 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2700
2701 tp->tx_skb[entry].len = len;
2702 txd->addr = cpu_to_le64(mapping);
2703 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2704
2705 wmb();
2706
2707 /* anti gcc 2.95.3 bugware (sic) */
2708 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2709 txd->opts1 = cpu_to_le32(status);
2710
2711 dev->trans_start = jiffies;
2712
2713 tp->cur_tx += frags + 1;
2714
2715 smp_wmb();
2716
275391a4 2717 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2718
2719 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2720 netif_stop_queue(dev);
2721 smp_rmb();
2722 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2723 netif_wake_queue(dev);
2724 }
2725
2726out:
2727 return ret;
2728
2729err_stop:
2730 netif_stop_queue(dev);
188f4af0 2731 ret = NETDEV_TX_BUSY;
1da177e4 2732err_update_stats:
cebf8cc7 2733 dev->stats.tx_dropped++;
1da177e4
LT		 2734 goto out;
2735}
2736
2737static void rtl8169_pcierr_interrupt(struct net_device *dev)
2738{
2739 struct rtl8169_private *tp = netdev_priv(dev);
2740 struct pci_dev *pdev = tp->pci_dev;
2741 void __iomem *ioaddr = tp->mmio_addr;
2742 u16 pci_status, pci_cmd;
2743
2744 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2745 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2746
b57b7e5a
SH		 2747 if (netif_msg_intr(tp)) {
2748 printk(KERN_ERR
2749 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2750 dev->name, pci_cmd, pci_status);
2751 }
1da177e4
LT		 2752
2753 /*
2754 * The recovery sequence below admits a very elaborated explanation:
2755 * - it seems to work;
d03902b8
FR		 2756 * - I did not see what else could be done;
2757 * - it makes iop3xx happy.
1da177e4
LT		 2758 *
2759 * Feel free to adjust to your needs.
2760 */
a27993f3 2761 if (pdev->broken_parity_status)
d03902b8
FR		 2762 pci_cmd &= ~PCI_COMMAND_PARITY;
2763 else
2764 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2765
2766 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2767
2768 pci_write_config_word(pdev, PCI_STATUS,
2769 pci_status & (PCI_STATUS_DETECTED_PARITY |
2770 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2771 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2772
2773 /* The infamous DAC f*ckup only happens at boot time */
2774 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2775 if (netif_msg_intr(tp))
2776 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2777 tp->cp_cmd &= ~PCIDAC;
2778 RTL_W16(CPlusCmd, tp->cp_cmd);
2779 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2780 }
2781
2782 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2783
2784 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2785}
2786
07d3f51f
FR		 2787static void rtl8169_tx_interrupt(struct net_device *dev,
2788 struct rtl8169_private *tp,
2789 void __iomem *ioaddr)
1da177e4
LT		 2790{
2791 unsigned int dirty_tx, tx_left;
2792
1da177e4
LT		 2793 dirty_tx = tp->dirty_tx;
2794 smp_rmb();
2795 tx_left = tp->cur_tx - dirty_tx;
2796
2797 while (tx_left > 0) {
2798 unsigned int entry = dirty_tx % NUM_TX_DESC;
2799 struct ring_info *tx_skb = tp->tx_skb + entry;
2800 u32 len = tx_skb->len;
2801 u32 status;
2802
2803 rmb();
2804 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2805 if (status & DescOwn)
2806 break;
2807
cebf8cc7
FR		 2808 dev->stats.tx_bytes += len;
2809 dev->stats.tx_packets++;
1da177e4
LT		 2810
2811 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2812
2813 if (status & LastFrag) {
2814 dev_kfree_skb_irq(tx_skb->skb);
2815 tx_skb->skb = NULL;
2816 }
2817 dirty_tx++;
2818 tx_left--;
2819 }
2820
2821 if (tp->dirty_tx != dirty_tx) {
2822 tp->dirty_tx = dirty_tx;
2823 smp_wmb();
2824 if (netif_queue_stopped(dev) &&
2825 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2826 netif_wake_queue(dev);
2827 }
d78ae2dc
FR		 2828 /*
2829 * 8168 hack: TxPoll requests are lost when the Tx packets are
2830 * too close. Let's kick an extra TxPoll request when a burst
2831 * of start_xmit activity is detected (if it is not detected,
2832 * it is slow enough). -- FR
2833 */
2834 smp_rmb();
2835 if (tp->cur_tx != dirty_tx)
2836 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2837 }
2838}
2839
126fa4b9
FR		 2840static inline int rtl8169_fragmented_frame(u32 status)
2841{
2842 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2843}
2844
1da177e4
LT		 2845static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2846{
2847 u32 opts1 = le32_to_cpu(desc->opts1);
2848 u32 status = opts1 & RxProtoMask;
2849
2850 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2851 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2852 ((status == RxProtoIP) && !(opts1 & IPFail)))
2853 skb->ip_summed = CHECKSUM_UNNECESSARY;
2854 else
2855 skb->ip_summed = CHECKSUM_NONE;
2856}
2857
07d3f51f
FR		 2858static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2859 struct rtl8169_private *tp, int pkt_size,
2860 dma_addr_t addr)
1da177e4 2861{
b449655f
SH		 2862 struct sk_buff *skb;
2863 bool done = false;
1da177e4 2864
b449655f
SH		 2865 if (pkt_size >= rx_copybreak)
2866 goto out;
1da177e4 2867
07d3f51f 2868 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2869 if (!skb)
2870 goto out;
2871
07d3f51f
FR		 2872 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2873 PCI_DMA_FROMDEVICE);
86402234 2874 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2875 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2876 *sk_buff = skb;
2877 done = true;
2878out:
2879 return done;
1da177e4
LT		 2880}
2881
07d3f51f
FR		 2882static int rtl8169_rx_interrupt(struct net_device *dev,
2883 struct rtl8169_private *tp,
bea3348e 2884 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2885{
2886 unsigned int cur_rx, rx_left;
2887 unsigned int delta, count;
2888
1da177e4
LT		 2889 cur_rx = tp->cur_rx;
2890 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 2891 rx_left = min(rx_left, budget);
1da177e4 2892
4dcb7d33 2893 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2894 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2895 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2896 u32 status;
2897
2898 rmb();
126fa4b9 2899 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2900
2901 if (status & DescOwn)
2902 break;
4dcb7d33 2903 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2904 if (netif_msg_rx_err(tp)) {
2905 printk(KERN_INFO
2906 "%s: Rx ERROR. status = %08x\n",
2907 dev->name, status);
2908 }
cebf8cc7 2909 dev->stats.rx_errors++;
1da177e4 2910 if (status & (RxRWT | RxRUNT))
cebf8cc7 2911 dev->stats.rx_length_errors++;
1da177e4 2912 if (status & RxCRC)
cebf8cc7 2913 dev->stats.rx_crc_errors++;
9dccf611
FR		 2914 if (status & RxFOVF) {
2915 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2916 dev->stats.rx_fifo_errors++;
9dccf611 2917 }
126fa4b9 2918 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2919 } else {
1da177e4 2920 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2921 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2922 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2923 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2924
126fa4b9
FR		 2925 /*
2926 * The driver does not support incoming fragmented
2927 * frames. They are seen as a symptom of over-mtu
2928 * sized frames.
2929 */
2930 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2931 dev->stats.rx_dropped++;
2932 dev->stats.rx_length_errors++;
126fa4b9 2933 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2934 continue;
126fa4b9
FR		 2935 }
2936
1da177e4 2937 rtl8169_rx_csum(skb, desc);
bcf0bf90 2938
07d3f51f 2939 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2940 pci_dma_sync_single_for_device(pdev, addr,
2941 pkt_size, PCI_DMA_FROMDEVICE);
2942 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2943 } else {
2944 pci_unmap_single(pdev, addr, pkt_size,
2945 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2946 tp->Rx_skbuff[entry] = NULL;
2947 }
2948
1da177e4
LT		 2949 skb_put(skb, pkt_size);
2950 skb->protocol = eth_type_trans(skb, dev);
2951
2952 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 2953 netif_receive_skb(skb);
1da177e4
LT		 2954
2955 dev->last_rx = jiffies;
cebf8cc7
FR		 2956 dev->stats.rx_bytes += pkt_size;
2957 dev->stats.rx_packets++;
1da177e4 2958 }
6dccd16b
FR		 2959
2960 /* Work around for AMD plateform. */
95e0918d 2961 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 2962 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2963 desc->opts2 = 0;
2964 cur_rx++;
2965 }
1da177e4
LT		 2966 }
2967
2968 count = cur_rx - tp->cur_rx;
2969 tp->cur_rx = cur_rx;
2970
2971 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2972 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2973 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2974 tp->dirty_rx += delta;
2975
2976 /*
2977 * FIXME: until there is periodic timer to try and refill the ring,
2978 * a temporary shortage may definitely kill the Rx process.
2979 * - disable the asic to try and avoid an overflow and kick it again
2980 * after refill ?
2981 * - how do others driver handle this condition (Uh oh...).
2982 */
b57b7e5a 2983 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2984 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2985
2986 return count;
2987}
2988
07d3f51f 2989static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2990{
07d3f51f 2991 struct net_device *dev = dev_instance;
1da177e4 2992 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 2993 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 2994 int handled = 0;
865c652d 2995 int status;
1da177e4 2996
865c652d 2997 status = RTL_R16(IntrStatus);
1da177e4 2998
865c652d
FR		 2999 /* hotplug/major error/no more work/shared irq */
3000 if ((status == 0xffff) || !status)
3001 goto out;
1da177e4 3002
865c652d 3003 handled = 1;
1da177e4 3004
865c652d
FR		 3005 if (unlikely(!netif_running(dev))) {
3006 rtl8169_asic_down(ioaddr);
3007 goto out;
3008 }
1da177e4 3009
865c652d
FR		 3010 status &= tp->intr_mask;
3011 RTL_W16(IntrStatus,
3012 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3013
865c652d
FR		 3014 if (!(status & tp->intr_event))
3015 goto out;
0e485150 3016
865c652d
FR		 3017 /* Work around for rx fifo overflow */
3018 if (unlikely(status & RxFIFOOver) &&
3019 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3020 netif_stop_queue(dev);
3021 rtl8169_tx_timeout(dev);
3022 goto out;
3023 }
1da177e4 3024
865c652d
FR		 3025 if (unlikely(status & SYSErr)) {
3026 rtl8169_pcierr_interrupt(dev);
3027 goto out;
3028 }
1da177e4 3029
865c652d
FR		 3030 if (status & LinkChg)
3031 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3032
865c652d
FR		 3033 if (status & tp->napi_event) {
3034 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3035 tp->intr_mask = ~tp->napi_event;
313b0305 3036
bea3348e
SH		 3037 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3038 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 3039 else if (netif_msg_intr(tp)) {
3040 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3041 dev->name, status);
b57b7e5a 3042 }
1da177e4
LT		 3043 }
3044out:
3045 return IRQ_RETVAL(handled);
3046}
3047
bea3348e 3048static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3049{
bea3348e
SH		 3050 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3051 struct net_device *dev = tp->dev;
1da177e4 3052 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3053 int work_done;
1da177e4 3054
bea3348e 3055 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3056 rtl8169_tx_interrupt(dev, tp, ioaddr);
3057
bea3348e
SH		 3058 if (work_done < budget) {
3059 netif_rx_complete(dev, napi);
1da177e4
LT		 3060 tp->intr_mask = 0xffff;
3061 /*
3062 * 20040426: the barrier is not strictly required but the
3063 * behavior of the irq handler could be less predictable
3064 * without it. Btw, the lack of flush for the posted pci
3065 * write is safe - FR
3066 */
3067 smp_wmb();
0e485150 3068 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3069 }
3070
bea3348e 3071 return work_done;
1da177e4 3072}
1da177e4
LT		 3073
3074static void rtl8169_down(struct net_device *dev)
3075{
3076 struct rtl8169_private *tp = netdev_priv(dev);
3077 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3078 unsigned int intrmask;
1da177e4
LT		 3079
3080 rtl8169_delete_timer(dev);
3081
3082 netif_stop_queue(dev);
3083
93dd79e8 3084 napi_disable(&tp->napi);
93dd79e8 3085
1da177e4
LT		 3086core_down:
3087 spin_lock_irq(&tp->lock);
3088
3089 rtl8169_asic_down(ioaddr);
3090
3091 /* Update the error counts. */
cebf8cc7 3092 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3093 RTL_W32(RxMissed, 0);
3094
3095 spin_unlock_irq(&tp->lock);
3096
3097 synchronize_irq(dev->irq);
3098
1da177e4 3099 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3100 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3101
3102 /*
3103 * And now for the 50k$ question: are IRQ disabled or not ?
3104 *
3105 * Two paths lead here:
3106 * 1) dev->close
3107 * -> netif_running() is available to sync the current code and the
3108 * IRQ handler. See rtl8169_interrupt for details.
3109 * 2) dev->change_mtu
3110 * -> rtl8169_poll can not be issued again and re-enable the
3111 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3112 *
3113 * No loop if hotpluged or major error (0xffff).
1da177e4 3114 */
733b736c
AP		 3115 intrmask = RTL_R16(IntrMask);
3116 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3117 goto core_down;
3118
3119 rtl8169_tx_clear(tp);
3120
3121 rtl8169_rx_clear(tp);
3122}
3123
3124static int rtl8169_close(struct net_device *dev)
3125{
3126 struct rtl8169_private *tp = netdev_priv(dev);
3127 struct pci_dev *pdev = tp->pci_dev;
3128
3129 rtl8169_down(dev);
3130
3131 free_irq(dev->irq, dev);
3132
1da177e4
LT		 3133 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3134 tp->RxPhyAddr);
3135 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3136 tp->TxPhyAddr);
3137 tp->TxDescArray = NULL;
3138 tp->RxDescArray = NULL;
3139
3140 return 0;
3141}
3142
07ce4064 3143static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3144{
3145 struct rtl8169_private *tp = netdev_priv(dev);
3146 void __iomem *ioaddr = tp->mmio_addr;
3147 unsigned long flags;
3148 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3149 int rx_mode;
1da177e4
LT		 3150 u32 tmp = 0;
3151
3152 if (dev->flags & IFF_PROMISC) {
3153 /* Unconditionally log net taps. */
b57b7e5a
SH		 3154 if (netif_msg_link(tp)) {
3155 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3156 dev->name);
3157 }
1da177e4
LT		 3158 rx_mode =
3159 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3160 AcceptAllPhys;
3161 mc_filter[1] = mc_filter[0] = 0xffffffff;
3162 } else if ((dev->mc_count > multicast_filter_limit)
3163 || (dev->flags & IFF_ALLMULTI)) {
3164 /* Too many to filter perfectly -- accept all multicasts. */
3165 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3166 mc_filter[1] = mc_filter[0] = 0xffffffff;
3167 } else {
3168 struct dev_mc_list *mclist;
07d3f51f
FR		 3169 unsigned int i;
3170
1da177e4
LT		 3171 rx_mode = AcceptBroadcast | AcceptMyPhys;
3172 mc_filter[1] = mc_filter[0] = 0;
3173 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3174 i++, mclist = mclist->next) {
3175 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3176 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3177 rx_mode |= AcceptMulticast;
3178 }
3179 }
3180
3181 spin_lock_irqsave(&tp->lock, flags);
3182
3183 tmp = rtl8169_rx_config | rx_mode |
3184 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3185
f887cce8 3186 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3187 u32 data = mc_filter[0];
3188
3189 mc_filter[0] = swab32(mc_filter[1]);
3190 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3191 }
3192
1da177e4
LT		 3193 RTL_W32(MAR0 + 0, mc_filter[0]);
3194 RTL_W32(MAR0 + 4, mc_filter[1]);
3195
57a9f236
FR		 3196 RTL_W32(RxConfig, tmp);
3197
1da177e4
LT		 3198 spin_unlock_irqrestore(&tp->lock, flags);
3199}
3200
3201/**
3202 * rtl8169_get_stats - Get rtl8169 read/write statistics
3203 * @dev: The Ethernet Device to get statistics for
3204 *
3205 * Get TX/RX statistics for rtl8169
3206 */
3207static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3208{
3209 struct rtl8169_private *tp = netdev_priv(dev);
3210 void __iomem *ioaddr = tp->mmio_addr;
3211 unsigned long flags;
3212
3213 if (netif_running(dev)) {
3214 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3215 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3216 RTL_W32(RxMissed, 0);
3217 spin_unlock_irqrestore(&tp->lock, flags);
3218 }
5b0384f4 3219
cebf8cc7 3220 return &dev->stats;
1da177e4
LT		 3221}
3222
5d06a99f
FR		 3223#ifdef CONFIG_PM
3224
3225static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3226{
3227 struct net_device *dev = pci_get_drvdata(pdev);
3228 struct rtl8169_private *tp = netdev_priv(dev);
3229 void __iomem *ioaddr = tp->mmio_addr;
3230
3231 if (!netif_running(dev))
1371fa6d 3232 goto out_pci_suspend;
5d06a99f
FR		 3233
3234 netif_device_detach(dev);
3235 netif_stop_queue(dev);
3236
3237 spin_lock_irq(&tp->lock);
3238
3239 rtl8169_asic_down(ioaddr);
3240
cebf8cc7 3241 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3242 RTL_W32(RxMissed, 0);
3243
3244 spin_unlock_irq(&tp->lock);
3245
1371fa6d 3246out_pci_suspend:
5d06a99f 3247 pci_save_state(pdev);
f23e7fda
FR		 3248 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3249 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3250 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3251
5d06a99f
FR		 3252 return 0;
3253}
3254
3255static int rtl8169_resume(struct pci_dev *pdev)
3256{
3257 struct net_device *dev = pci_get_drvdata(pdev);
3258
1371fa6d
FR		 3259 pci_set_power_state(pdev, PCI_D0);
3260 pci_restore_state(pdev);
3261 pci_enable_wake(pdev, PCI_D0, 0);
3262
5d06a99f
FR		 3263 if (!netif_running(dev))
3264 goto out;
3265
3266 netif_device_attach(dev);
3267
5d06a99f
FR		 3268 rtl8169_schedule_work(dev, rtl8169_reset_task);
3269out:
3270 return 0;
3271}
3272
3273#endif /* CONFIG_PM */
3274
1da177e4
LT		 3275static struct pci_driver rtl8169_pci_driver = {
3276 .name = MODULENAME,
3277 .id_table = rtl8169_pci_tbl,
3278 .probe = rtl8169_init_one,
3279 .remove = __devexit_p(rtl8169_remove_one),
3280#ifdef CONFIG_PM
3281 .suspend = rtl8169_suspend,
3282 .resume = rtl8169_resume,
3283#endif
3284};
3285
07d3f51f 3286static int __init rtl8169_init_module(void)
1da177e4 3287{
29917620 3288 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3289}
3290
07d3f51f 3291static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3292{
3293 pci_unregister_driver(&rtl8169_pci_driver);
3294}
3295
3296module_init(rtl8169_init_module);
3297module_exit(rtl8169_cleanup_module);
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