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r8169: shuffle some registers handling around (8168 operation only)
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 113};
114
1da177e4
LT		 115#define _R(NAME,MAC,MASK) \
116 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
117
3c6bee1d 118static const struct {
1da177e4
LT		 119 const char *name;
120 u8 mac_version;
121 u32 RxConfigMask; /* Clears the bits supported by this chip */
122} rtl_chip_info[] = {
ba6eb6ee
FR		 123 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
124 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
125 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
126 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
127 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 129 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
130 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
131 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
132 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 133 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
136 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 137 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
139 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
140 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
141 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
142 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 143};
144#undef _R
145
bcf0bf90
FR		 146enum cfg_version {
147 RTL_CFG_0 = 0x00,
148 RTL_CFG_1,
149 RTL_CFG_2
150};
151
07ce4064
FR		 152static void rtl_hw_start_8169(struct net_device *);
153static void rtl_hw_start_8168(struct net_device *);
154static void rtl_hw_start_8101(struct net_device *);
155
1da177e4 156static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 157 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 158 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 159 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 160 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
162 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 163 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 164 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
165 { PCI_VENDOR_ID_LINKSYS, 0x1032,
166 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 167 { 0x0001, 0x8168,
168 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 169 {0,},
170};
171
172MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
173
174static int rx_copybreak = 200;
175static int use_dac;
b57b7e5a
SH		 176static struct {
177 u32 msg_enable;
178} debug = { -1 };
1da177e4 179
07d3f51f
FR		 180enum rtl_registers {
181 MAC0 = 0, /* Ethernet hardware address. */
773d2021 182 MAC4 = 4,
07d3f51f
FR		 183 MAR0 = 8, /* Multicast filter. */
184 CounterAddrLow = 0x10,
185 CounterAddrHigh = 0x14,
186 TxDescStartAddrLow = 0x20,
187 TxDescStartAddrHigh = 0x24,
188 TxHDescStartAddrLow = 0x28,
189 TxHDescStartAddrHigh = 0x2c,
190 FLASH = 0x30,
191 ERSR = 0x36,
192 ChipCmd = 0x37,
193 TxPoll = 0x38,
194 IntrMask = 0x3c,
195 IntrStatus = 0x3e,
196 TxConfig = 0x40,
197 RxConfig = 0x44,
198 RxMissed = 0x4c,
199 Cfg9346 = 0x50,
200 Config0 = 0x51,
201 Config1 = 0x52,
202 Config2 = 0x53,
203 Config3 = 0x54,
204 Config4 = 0x55,
205 Config5 = 0x56,
206 MultiIntr = 0x5c,
207 PHYAR = 0x60,
07d3f51f
FR		 208 PHYstatus = 0x6c,
209 RxMaxSize = 0xda,
210 CPlusCmd = 0xe0,
211 IntrMitigate = 0xe2,
212 RxDescAddrLow = 0xe4,
213 RxDescAddrHigh = 0xe8,
214 EarlyTxThres = 0xec,
215 FuncEvent = 0xf0,
216 FuncEventMask = 0xf4,
217 FuncPresetState = 0xf8,
218 FuncForceEvent = 0xfc,
1da177e4
LT		 219};
220
f162a5d1
FR		 221enum rtl8110_registers {
222 TBICSR = 0x64,
223 TBI_ANAR = 0x68,
224 TBI_LPAR = 0x6a,
225};
226
227enum rtl8168_8101_registers {
228 CSIDR = 0x64,
229 CSIAR = 0x68,
230#define CSIAR_FLAG 0x80000000
231#define CSIAR_WRITE_CMD 0x80000000
232#define CSIAR_BYTE_ENABLE 0x0f
233#define CSIAR_BYTE_ENABLE_SHIFT 12
234#define CSIAR_ADDR_MASK 0x0fff
235
236 EPHYAR = 0x80,
237#define EPHYAR_FLAG 0x80000000
238#define EPHYAR_WRITE_CMD 0x80000000
239#define EPHYAR_REG_MASK 0x1f
240#define EPHYAR_REG_SHIFT 16
241#define EPHYAR_DATA_MASK 0xffff
242 DBG_REG = 0xd1,
243#define FIX_NAK_1 (1 << 4)
244#define FIX_NAK_2 (1 << 3)
245};
246
07d3f51f 247enum rtl_register_content {
1da177e4 248 /* InterruptStatusBits */
07d3f51f
FR		 249 SYSErr = 0x8000,
250 PCSTimeout = 0x4000,
251 SWInt = 0x0100,
252 TxDescUnavail = 0x0080,
253 RxFIFOOver = 0x0040,
254 LinkChg = 0x0020,
255 RxOverflow = 0x0010,
256 TxErr = 0x0008,
257 TxOK = 0x0004,
258 RxErr = 0x0002,
259 RxOK = 0x0001,
1da177e4
LT		 260
261 /* RxStatusDesc */
9dccf611
FR		 262 RxFOVF = (1 << 23),
263 RxRWT = (1 << 22),
264 RxRES = (1 << 21),
265 RxRUNT = (1 << 20),
266 RxCRC = (1 << 19),
1da177e4
LT		 267
268 /* ChipCmdBits */
07d3f51f
FR		 269 CmdReset = 0x10,
270 CmdRxEnb = 0x08,
271 CmdTxEnb = 0x04,
272 RxBufEmpty = 0x01,
1da177e4 273
275391a4
FR		 274 /* TXPoll register p.5 */
275 HPQ = 0x80, /* Poll cmd on the high prio queue */
276 NPQ = 0x40, /* Poll cmd on the low prio queue */
277 FSWInt = 0x01, /* Forced software interrupt */
278
1da177e4 279 /* Cfg9346Bits */
07d3f51f
FR		 280 Cfg9346_Lock = 0x00,
281 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 282
283 /* rx_mode_bits */
07d3f51f
FR		 284 AcceptErr = 0x20,
285 AcceptRunt = 0x10,
286 AcceptBroadcast = 0x08,
287 AcceptMulticast = 0x04,
288 AcceptMyPhys = 0x02,
289 AcceptAllPhys = 0x01,
1da177e4
LT		 290
291 /* RxConfigBits */
07d3f51f
FR		 292 RxCfgFIFOShift = 13,
293 RxCfgDMAShift = 8,
1da177e4
LT		 294
295 /* TxConfigBits */
296 TxInterFrameGapShift = 24,
297 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
298
5d06a99f 299 /* Config1 register p.24 */
f162a5d1
FR		 300 LEDS1 = (1 << 7),
301 LEDS0 = (1 << 6),
fbac58fc 302 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 303 Speed_down = (1 << 4),
304 MEMMAP = (1 << 3),
305 IOMAP = (1 << 2),
306 VPD = (1 << 1),
5d06a99f
FR		 307 PMEnable = (1 << 0), /* Power Management Enable */
308
6dccd16b
FR		 309 /* Config2 register p. 25 */
310 PCI_Clock_66MHz = 0x01,
311 PCI_Clock_33MHz = 0x00,
312
61a4dcc2
FR		 313 /* Config3 register p.25 */
314 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
315 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 316 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 317
5d06a99f 318 /* Config5 register p.27 */
61a4dcc2
FR		 319 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
320 MWF = (1 << 5), /* Accept Multicast wakeup frame */
321 UWF = (1 << 4), /* Accept Unicast wakeup frame */
322 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 323 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
324
1da177e4
LT		 325 /* TBICSR p.28 */
326 TBIReset = 0x80000000,
327 TBILoopback = 0x40000000,
328 TBINwEnable = 0x20000000,
329 TBINwRestart = 0x10000000,
330 TBILinkOk = 0x02000000,
331 TBINwComplete = 0x01000000,
332
333 /* CPlusCmd p.31 */
f162a5d1
FR		 334 EnableBist = (1 << 15), // 8168 8101
335 Mac_dbgo_oe = (1 << 14), // 8168 8101
336 Normal_mode = (1 << 13), // unused
337 Force_half_dup = (1 << 12), // 8168 8101
338 Force_rxflow_en = (1 << 11), // 8168 8101
339 Force_txflow_en = (1 << 10), // 8168 8101
340 Cxpl_dbg_sel = (1 << 9), // 8168 8101
341 ASF = (1 << 8), // 8168 8101
342 PktCntrDisable = (1 << 7), // 8168 8101
343 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 344 RxVlan = (1 << 6),
345 RxChkSum = (1 << 5),
346 PCIDAC = (1 << 4),
347 PCIMulRW = (1 << 3),
0e485150
FR		 348 INTT_0 = 0x0000, // 8168
349 INTT_1 = 0x0001, // 8168
350 INTT_2 = 0x0002, // 8168
351 INTT_3 = 0x0003, // 8168
1da177e4
LT		 352
353 /* rtl8169_PHYstatus */
07d3f51f
FR		 354 TBI_Enable = 0x80,
355 TxFlowCtrl = 0x40,
356 RxFlowCtrl = 0x20,
357 _1000bpsF = 0x10,
358 _100bps = 0x08,
359 _10bps = 0x04,
360 LinkStatus = 0x02,
361 FullDup = 0x01,
1da177e4 362
1da177e4 363 /* _TBICSRBit */
07d3f51f 364 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 365
366 /* DumpCounterCommand */
07d3f51f 367 CounterDump = 0x8,
1da177e4
LT		 368};
369
07d3f51f 370enum desc_status_bit {
1da177e4
LT		 371 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
372 RingEnd = (1 << 30), /* End of descriptor ring */
373 FirstFrag = (1 << 29), /* First segment of a packet */
374 LastFrag = (1 << 28), /* Final segment of a packet */
375
376 /* Tx private */
377 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
378 MSSShift = 16, /* MSS value position */
379 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
380 IPCS = (1 << 18), /* Calculate IP checksum */
381 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
382 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
383 TxVlanTag = (1 << 17), /* Add VLAN tag */
384
385 /* Rx private */
386 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
387 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
388
389#define RxProtoUDP (PID1)
390#define RxProtoTCP (PID0)
391#define RxProtoIP (PID1 | PID0)
392#define RxProtoMask RxProtoIP
393
394 IPFail = (1 << 16), /* IP checksum failed */
395 UDPFail = (1 << 15), /* UDP/IP checksum failed */
396 TCPFail = (1 << 14), /* TCP/IP checksum failed */
397 RxVlanTag = (1 << 16), /* VLAN tag available */
398};
399
400#define RsvdMask 0x3fffc000
401
402struct TxDesc {
6cccd6e7
REB		 403 __le32 opts1;
404 __le32 opts2;
405 __le64 addr;
1da177e4
LT		 406};
407
408struct RxDesc {
6cccd6e7
REB		 409 __le32 opts1;
410 __le32 opts2;
411 __le64 addr;
1da177e4
LT		 412};
413
414struct ring_info {
415 struct sk_buff *skb;
416 u32 len;
417 u8 __pad[sizeof(void *) - sizeof(u32)];
418};
419
f23e7fda 420enum features {
ccdffb9a
FR		 421 RTL_FEATURE_WOL = (1 << 0),
422 RTL_FEATURE_MSI = (1 << 1),
423 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 424};
425
1da177e4
LT		 426struct rtl8169_private {
427 void __iomem *mmio_addr; /* memory map physical address */
428 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 429 struct net_device *dev;
bea3348e 430 struct napi_struct napi;
1da177e4 431 spinlock_t lock; /* spin lock flag */
b57b7e5a 432 u32 msg_enable;
1da177e4
LT		 433 int chipset;
434 int mac_version;
1da177e4
LT		 435 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
436 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
437 u32 dirty_rx;
438 u32 dirty_tx;
439 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
440 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
441 dma_addr_t TxPhyAddr;
442 dma_addr_t RxPhyAddr;
443 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
444 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 445 unsigned align;
1da177e4
LT		 446 unsigned rx_buf_sz;
447 struct timer_list timer;
448 u16 cp_cmd;
0e485150
FR		 449 u16 intr_event;
450 u16 napi_event;
1da177e4
LT		 451 u16 intr_mask;
452 int phy_auto_nego_reg;
453 int phy_1000_ctrl_reg;
454#ifdef CONFIG_R8169_VLAN
455 struct vlan_group *vlgrp;
456#endif
457 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 458 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 459 void (*phy_reset_enable)(void __iomem *);
07ce4064 460 void (*hw_start)(struct net_device *);
1da177e4
LT		 461 unsigned int (*phy_reset_pending)(void __iomem *);
462 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 463 int pcie_cap;
c4028958 464 struct delayed_work task;
f23e7fda 465 unsigned features;
ccdffb9a
FR		 466
467 struct mii_if_info mii;
1da177e4
LT		 468};
469
979b6c13 470MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 471MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 472module_param(rx_copybreak, int, 0);
1b7efd58 473MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 474module_param(use_dac, int, 0);
475MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 476module_param_named(debug, debug.msg_enable, int, 0);
477MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 478MODULE_LICENSE("GPL");
479MODULE_VERSION(RTL8169_VERSION);
480
481static int rtl8169_open(struct net_device *dev);
482static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 483static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 484static int rtl8169_init_ring(struct net_device *dev);
07ce4064 485static void rtl_hw_start(struct net_device *dev);
1da177e4 486static int rtl8169_close(struct net_device *dev);
07ce4064 487static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 488static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 489static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 490static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 491 void __iomem *, u32 budget);
4dcb7d33 492static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 493static void rtl8169_down(struct net_device *dev);
99f252b0 494static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 495static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 496
1da177e4 497static const unsigned int rtl8169_rx_config =
5b0384f4 498 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 499
07d3f51f 500static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 501{
502 int i;
503
a6baf3af 504 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 505
2371408c 506 for (i = 20; i > 0; i--) {
07d3f51f
FR		 507 /*
508 * Check if the RTL8169 has completed writing to the specified
509 * MII register.
510 */
5b0384f4 511 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 512 break;
2371408c 513 udelay(25);
1da177e4
LT		 514 }
515}
516
07d3f51f 517static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 518{
519 int i, value = -1;
520
a6baf3af 521 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 522
2371408c 523 for (i = 20; i > 0; i--) {
07d3f51f
FR		 524 /*
525 * Check if the RTL8169 has completed retrieving data from
526 * the specified MII register.
527 */
1da177e4 528 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 529 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 530 break;
531 }
2371408c 532 udelay(25);
1da177e4
LT		 533 }
534 return value;
535}
536
dacf8154
FR		 537static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
538{
539 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
540}
541
ccdffb9a
FR		 542static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
543 int val)
544{
545 struct rtl8169_private *tp = netdev_priv(dev);
546 void __iomem *ioaddr = tp->mmio_addr;
547
548 mdio_write(ioaddr, location, val);
549}
550
551static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
552{
553 struct rtl8169_private *tp = netdev_priv(dev);
554 void __iomem *ioaddr = tp->mmio_addr;
555
556 return mdio_read(ioaddr, location);
557}
558
dacf8154
FR		 559static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
560{
561 unsigned int i;
562
563 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
564 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
565
566 for (i = 0; i < 100; i++) {
567 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
568 break;
569 udelay(10);
570 }
571}
572
573static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
574{
575 u16 value = 0xffff;
576 unsigned int i;
577
578 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
579
580 for (i = 0; i < 100; i++) {
581 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
582 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
583 break;
584 }
585 udelay(10);
586 }
587
588 return value;
589}
590
591static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
592{
593 unsigned int i;
594
595 RTL_W32(CSIDR, value);
596 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
597 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
598
599 for (i = 0; i < 100; i++) {
600 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
601 break;
602 udelay(10);
603 }
604}
605
606static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
607{
608 u32 value = ~0x00;
609 unsigned int i;
610
611 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
612 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
613
614 for (i = 0; i < 100; i++) {
615 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
616 value = RTL_R32(CSIDR);
617 break;
618 }
619 udelay(10);
620 }
621
622 return value;
623}
624
1da177e4
LT		 625static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
626{
627 RTL_W16(IntrMask, 0x0000);
628
629 RTL_W16(IntrStatus, 0xffff);
630}
631
632static void rtl8169_asic_down(void __iomem *ioaddr)
633{
634 RTL_W8(ChipCmd, 0x00);
635 rtl8169_irq_mask_and_ack(ioaddr);
636 RTL_R16(CPlusCmd);
637}
638
639static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
640{
641 return RTL_R32(TBICSR) & TBIReset;
642}
643
644static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
645{
64e4bfb4 646 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 647}
648
649static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
650{
651 return RTL_R32(TBICSR) & TBILinkOk;
652}
653
654static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
655{
656 return RTL_R8(PHYstatus) & LinkStatus;
657}
658
659static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
660{
661 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
662}
663
664static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
665{
666 unsigned int val;
667
9e0db8ef
FR		 668 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
669 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 670}
671
672static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 673 struct rtl8169_private *tp,
674 void __iomem *ioaddr)
1da177e4
LT		 675{
676 unsigned long flags;
677
678 spin_lock_irqsave(&tp->lock, flags);
679 if (tp->link_ok(ioaddr)) {
680 netif_carrier_on(dev);
b57b7e5a
SH		 681 if (netif_msg_ifup(tp))
682 printk(KERN_INFO PFX "%s: link up\n", dev->name);
683 } else {
684 if (netif_msg_ifdown(tp))
685 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 686 netif_carrier_off(dev);
b57b7e5a 687 }
1da177e4
LT		 688 spin_unlock_irqrestore(&tp->lock, flags);
689}
690
61a4dcc2
FR		 691static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
692{
693 struct rtl8169_private *tp = netdev_priv(dev);
694 void __iomem *ioaddr = tp->mmio_addr;
695 u8 options;
696
697 wol->wolopts = 0;
698
699#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700 wol->supported = WAKE_ANY;
701
702 spin_lock_irq(&tp->lock);
703
704 options = RTL_R8(Config1);
705 if (!(options & PMEnable))
706 goto out_unlock;
707
708 options = RTL_R8(Config3);
709 if (options & LinkUp)
710 wol->wolopts |= WAKE_PHY;
711 if (options & MagicPacket)
712 wol->wolopts |= WAKE_MAGIC;
713
714 options = RTL_R8(Config5);
715 if (options & UWF)
716 wol->wolopts |= WAKE_UCAST;
717 if (options & BWF)
5b0384f4 718 wol->wolopts |= WAKE_BCAST;
61a4dcc2 719 if (options & MWF)
5b0384f4 720 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 721
722out_unlock:
723 spin_unlock_irq(&tp->lock);
724}
725
726static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
727{
728 struct rtl8169_private *tp = netdev_priv(dev);
729 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 730 unsigned int i;
61a4dcc2
FR		 731 static struct {
732 u32 opt;
733 u16 reg;
734 u8 mask;
735 } cfg[] = {
736 { WAKE_ANY, Config1, PMEnable },
737 { WAKE_PHY, Config3, LinkUp },
738 { WAKE_MAGIC, Config3, MagicPacket },
739 { WAKE_UCAST, Config5, UWF },
740 { WAKE_BCAST, Config5, BWF },
741 { WAKE_MCAST, Config5, MWF },
742 { WAKE_ANY, Config5, LanWake }
743 };
744
745 spin_lock_irq(&tp->lock);
746
747 RTL_W8(Cfg9346, Cfg9346_Unlock);
748
749 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
750 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
751 if (wol->wolopts & cfg[i].opt)
752 options |= cfg[i].mask;
753 RTL_W8(cfg[i].reg, options);
754 }
755
756 RTL_W8(Cfg9346, Cfg9346_Lock);
757
f23e7fda
FR		 758 if (wol->wolopts)
759 tp->features |= RTL_FEATURE_WOL;
760 else
761 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 762 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 763
764 spin_unlock_irq(&tp->lock);
765
766 return 0;
767}
768
1da177e4
LT		 769static void rtl8169_get_drvinfo(struct net_device *dev,
770 struct ethtool_drvinfo *info)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773
774 strcpy(info->driver, MODULENAME);
775 strcpy(info->version, RTL8169_VERSION);
776 strcpy(info->bus_info, pci_name(tp->pci_dev));
777}
778
779static int rtl8169_get_regs_len(struct net_device *dev)
780{
781 return R8169_REGS_SIZE;
782}
783
784static int rtl8169_set_speed_tbi(struct net_device *dev,
785 u8 autoneg, u16 speed, u8 duplex)
786{
787 struct rtl8169_private *tp = netdev_priv(dev);
788 void __iomem *ioaddr = tp->mmio_addr;
789 int ret = 0;
790 u32 reg;
791
792 reg = RTL_R32(TBICSR);
793 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
794 (duplex == DUPLEX_FULL)) {
795 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
796 } else if (autoneg == AUTONEG_ENABLE)
797 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
798 else {
b57b7e5a
SH		 799 if (netif_msg_link(tp)) {
800 printk(KERN_WARNING "%s: "
801 "incorrect speed setting refused in TBI mode\n",
802 dev->name);
803 }
1da177e4
LT		 804 ret = -EOPNOTSUPP;
805 }
806
807 return ret;
808}
809
810static int rtl8169_set_speed_xmii(struct net_device *dev,
811 u8 autoneg, u16 speed, u8 duplex)
812{
813 struct rtl8169_private *tp = netdev_priv(dev);
814 void __iomem *ioaddr = tp->mmio_addr;
815 int auto_nego, giga_ctrl;
816
64e4bfb4
FR		 817 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
818 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
819 ADVERTISE_100HALF | ADVERTISE_100FULL);
820 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
821 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 822
823 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 824 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
825 ADVERTISE_100HALF | ADVERTISE_100FULL);
826 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 827 } else {
828 if (speed == SPEED_10)
64e4bfb4 829 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 830 else if (speed == SPEED_100)
64e4bfb4 831 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 832 else if (speed == SPEED_1000)
64e4bfb4 833 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 834
835 if (duplex == DUPLEX_HALF)
64e4bfb4 836 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 837
838 if (duplex == DUPLEX_FULL)
64e4bfb4 839 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 840
841 /* This tweak comes straight from Realtek's driver. */
842 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 843 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
844 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 845 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 846 }
847 }
848
2857ffb7
FR		 849 /* The 8100e/8101e/8102e do Fast Ethernet only. */
850 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
851 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
852 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
853 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
854 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 855 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 856 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 858 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 859 netif_msg_link(tp)) {
860 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
861 dev->name);
862 }
64e4bfb4 863 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 864 }
865
623a1593
FR		 866 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
867
a2de6b89
FR		 868 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
869 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
870 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
871 /*
872 * Wake up the PHY.
873 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
874 */
2584fbc3
RS		 875 mdio_write(ioaddr, 0x1f, 0x0000);
876 mdio_write(ioaddr, 0x0e, 0x0000);
877 }
878
1da177e4
LT		 879 tp->phy_auto_nego_reg = auto_nego;
880 tp->phy_1000_ctrl_reg = giga_ctrl;
881
64e4bfb4
FR		 882 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
883 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
884 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 885 return 0;
886}
887
888static int rtl8169_set_speed(struct net_device *dev,
889 u8 autoneg, u16 speed, u8 duplex)
890{
891 struct rtl8169_private *tp = netdev_priv(dev);
892 int ret;
893
894 ret = tp->set_speed(dev, autoneg, speed, duplex);
895
64e4bfb4 896 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 897 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
898
899 return ret;
900}
901
902static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
903{
904 struct rtl8169_private *tp = netdev_priv(dev);
905 unsigned long flags;
906 int ret;
907
908 spin_lock_irqsave(&tp->lock, flags);
909 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
910 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 911
1da177e4
LT		 912 return ret;
913}
914
915static u32 rtl8169_get_rx_csum(struct net_device *dev)
916{
917 struct rtl8169_private *tp = netdev_priv(dev);
918
919 return tp->cp_cmd & RxChkSum;
920}
921
922static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
923{
924 struct rtl8169_private *tp = netdev_priv(dev);
925 void __iomem *ioaddr = tp->mmio_addr;
926 unsigned long flags;
927
928 spin_lock_irqsave(&tp->lock, flags);
929
930 if (data)
931 tp->cp_cmd |= RxChkSum;
932 else
933 tp->cp_cmd &= ~RxChkSum;
934
935 RTL_W16(CPlusCmd, tp->cp_cmd);
936 RTL_R16(CPlusCmd);
937
938 spin_unlock_irqrestore(&tp->lock, flags);
939
940 return 0;
941}
942
943#ifdef CONFIG_R8169_VLAN
944
945static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
946 struct sk_buff *skb)
947{
948 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
949 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
950}
951
952static void rtl8169_vlan_rx_register(struct net_device *dev,
953 struct vlan_group *grp)
954{
955 struct rtl8169_private *tp = netdev_priv(dev);
956 void __iomem *ioaddr = tp->mmio_addr;
957 unsigned long flags;
958
959 spin_lock_irqsave(&tp->lock, flags);
960 tp->vlgrp = grp;
961 if (tp->vlgrp)
962 tp->cp_cmd |= RxVlan;
963 else
964 tp->cp_cmd &= ~RxVlan;
965 RTL_W16(CPlusCmd, tp->cp_cmd);
966 RTL_R16(CPlusCmd);
967 spin_unlock_irqrestore(&tp->lock, flags);
968}
969
1da177e4
LT		 970static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
971 struct sk_buff *skb)
972{
973 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 974 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 975 int ret;
976
865c652d
FR		 977 if (vlgrp && (opts2 & RxVlanTag)) {
978 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 979 ret = 0;
980 } else
981 ret = -1;
982 desc->opts2 = 0;
983 return ret;
984}
985
986#else /* !CONFIG_R8169_VLAN */
987
988static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
989 struct sk_buff *skb)
990{
991 return 0;
992}
993
994static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
995 struct sk_buff *skb)
996{
997 return -1;
998}
999
1000#endif
1001
ccdffb9a 1002static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1003{
1004 struct rtl8169_private *tp = netdev_priv(dev);
1005 void __iomem *ioaddr = tp->mmio_addr;
1006 u32 status;
1007
1008 cmd->supported =
1009 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1010 cmd->port = PORT_FIBRE;
1011 cmd->transceiver = XCVR_INTERNAL;
1012
1013 status = RTL_R32(TBICSR);
1014 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1015 cmd->autoneg = !!(status & TBINwEnable);
1016
1017 cmd->speed = SPEED_1000;
1018 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1019
1020 return 0;
1da177e4
LT		 1021}
1022
ccdffb9a 1023static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1024{
1025 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1026
1027 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1028}
1029
1030static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1031{
1032 struct rtl8169_private *tp = netdev_priv(dev);
1033 unsigned long flags;
ccdffb9a 1034 int rc;
1da177e4
LT		 1035
1036 spin_lock_irqsave(&tp->lock, flags);
1037
ccdffb9a 1038 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1039
1040 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1041 return rc;
1da177e4
LT		 1042}
1043
1044static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1045 void *p)
1046{
5b0384f4
FR		 1047 struct rtl8169_private *tp = netdev_priv(dev);
1048 unsigned long flags;
1da177e4 1049
5b0384f4
FR		 1050 if (regs->len > R8169_REGS_SIZE)
1051 regs->len = R8169_REGS_SIZE;
1da177e4 1052
5b0384f4
FR		 1053 spin_lock_irqsave(&tp->lock, flags);
1054 memcpy_fromio(p, tp->mmio_addr, regs->len);
1055 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1056}
1057
b57b7e5a
SH		 1058static u32 rtl8169_get_msglevel(struct net_device *dev)
1059{
1060 struct rtl8169_private *tp = netdev_priv(dev);
1061
1062 return tp->msg_enable;
1063}
1064
1065static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1066{
1067 struct rtl8169_private *tp = netdev_priv(dev);
1068
1069 tp->msg_enable = value;
1070}
1071
d4a3a0fc
SH		 1072static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1073 "tx_packets",
1074 "rx_packets",
1075 "tx_errors",
1076 "rx_errors",
1077 "rx_missed",
1078 "align_errors",
1079 "tx_single_collisions",
1080 "tx_multi_collisions",
1081 "unicast",
1082 "broadcast",
1083 "multicast",
1084 "tx_aborted",
1085 "tx_underrun",
1086};
1087
1088struct rtl8169_counters {
b1eab701
AV		 1089 __le64 tx_packets;
1090 __le64 rx_packets;
1091 __le64 tx_errors;
1092 __le32 rx_errors;
1093 __le16 rx_missed;
1094 __le16 align_errors;
1095 __le32 tx_one_collision;
1096 __le32 tx_multi_collision;
1097 __le64 rx_unicast;
1098 __le64 rx_broadcast;
1099 __le32 rx_multicast;
1100 __le16 tx_aborted;
1101 __le16 tx_underun;
d4a3a0fc
SH		 1102};
1103
b9f2c044 1104static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1105{
b9f2c044
JG		 1106 switch (sset) {
1107 case ETH_SS_STATS:
1108 return ARRAY_SIZE(rtl8169_gstrings);
1109 default:
1110 return -EOPNOTSUPP;
1111 }
d4a3a0fc
SH		 1112}
1113
1114static void rtl8169_get_ethtool_stats(struct net_device *dev,
1115 struct ethtool_stats *stats, u64 *data)
1116{
1117 struct rtl8169_private *tp = netdev_priv(dev);
1118 void __iomem *ioaddr = tp->mmio_addr;
1119 struct rtl8169_counters *counters;
1120 dma_addr_t paddr;
1121 u32 cmd;
1122
1123 ASSERT_RTNL();
1124
1125 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1126 if (!counters)
1127 return;
1128
1129 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1130 cmd = (u64)paddr & DMA_32BIT_MASK;
1131 RTL_W32(CounterAddrLow, cmd);
1132 RTL_W32(CounterAddrLow, cmd | CounterDump);
1133
1134 while (RTL_R32(CounterAddrLow) & CounterDump) {
1135 if (msleep_interruptible(1))
1136 break;
1137 }
1138
1139 RTL_W32(CounterAddrLow, 0);
1140 RTL_W32(CounterAddrHigh, 0);
1141
5b0384f4 1142 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1143 data[1] = le64_to_cpu(counters->rx_packets);
1144 data[2] = le64_to_cpu(counters->tx_errors);
1145 data[3] = le32_to_cpu(counters->rx_errors);
1146 data[4] = le16_to_cpu(counters->rx_missed);
1147 data[5] = le16_to_cpu(counters->align_errors);
1148 data[6] = le32_to_cpu(counters->tx_one_collision);
1149 data[7] = le32_to_cpu(counters->tx_multi_collision);
1150 data[8] = le64_to_cpu(counters->rx_unicast);
1151 data[9] = le64_to_cpu(counters->rx_broadcast);
1152 data[10] = le32_to_cpu(counters->rx_multicast);
1153 data[11] = le16_to_cpu(counters->tx_aborted);
1154 data[12] = le16_to_cpu(counters->tx_underun);
1155
1156 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1157}
1158
1159static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1160{
1161 switch(stringset) {
1162 case ETH_SS_STATS:
1163 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1164 break;
1165 }
1166}
1167
7282d491 1168static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1169 .get_drvinfo = rtl8169_get_drvinfo,
1170 .get_regs_len = rtl8169_get_regs_len,
1171 .get_link = ethtool_op_get_link,
1172 .get_settings = rtl8169_get_settings,
1173 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1174 .get_msglevel = rtl8169_get_msglevel,
1175 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1176 .get_rx_csum = rtl8169_get_rx_csum,
1177 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1178 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1179 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1180 .set_tso = ethtool_op_set_tso,
1181 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1182 .get_wol = rtl8169_get_wol,
1183 .set_wol = rtl8169_set_wol,
d4a3a0fc 1184 .get_strings = rtl8169_get_strings,
b9f2c044 1185 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1186 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1187};
1188
07d3f51f
FR		 1189static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1190 int bitnum, int bitval)
1da177e4
LT		 1191{
1192 int val;
1193
1194 val = mdio_read(ioaddr, reg);
1195 val = (bitval == 1) ?
1196 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1197 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1198}
1199
07d3f51f
FR		 1200static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1201 void __iomem *ioaddr)
1da177e4 1202{
0e485150
FR		 1203 /*
1204 * The driver currently handles the 8168Bf and the 8168Be identically
1205 * but they can be identified more specifically through the test below
1206 * if needed:
1207 *
1208 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1209 *
1210 * Same thing for the 8101Eb and the 8101Ec:
1211 *
1212 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1213 */
1da177e4
LT		 1214 const struct {
1215 u32 mask;
e3cf0cc0 1216 u32 val;
1da177e4
LT		 1217 int mac_version;
1218 } mac_info[] = {
e3cf0cc0
FR		 1219 /* 8168B family. */
1220 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1221 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1222 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1223 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1224
1225 /* 8168B family. */
1226 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1227 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1228 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1229 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1230
1231 /* 8101 family. */
2857ffb7
FR		 1232 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1233 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1234 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1235 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1236 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1237 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1238 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1239 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1240 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1241 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1242 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1243 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1244 /* FIXME: where did these entries come from ? -- FR */
1245 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1246 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1247
1248 /* 8110 family. */
1249 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1250 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1251 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1252 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1253 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1254 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1255
1256 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1257 }, *p = mac_info;
1258 u32 reg;
1259
e3cf0cc0
FR		 1260 reg = RTL_R32(TxConfig);
1261 while ((reg & p->mask) != p->val)
1da177e4
LT		 1262 p++;
1263 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1264
1265 if (p->mask == 0x00000000) {
1266 struct pci_dev *pdev = tp->pci_dev;
1267
1268 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1269 }
1da177e4
LT		 1270}
1271
1272static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1273{
bcf0bf90 1274 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1275}
1276
867763c1
FR		 1277struct phy_reg {
1278 u16 reg;
1279 u16 val;
1280};
1281
1282static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1283{
1284 while (len-- > 0) {
1285 mdio_write(ioaddr, regs->reg, regs->val);
1286 regs++;
1287 }
1288}
1289
5615d9f1 1290static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1291{
1da177e4
LT		 1292 struct {
1293 u16 regs[5]; /* Beware of bit-sign propagation */
1294 } phy_magic[5] = { {
1295 { 0x0000, //w 4 15 12 0
1296 0x00a1, //w 3 15 0 00a1
1297 0x0008, //w 2 15 0 0008
1298 0x1020, //w 1 15 0 1020
1299 0x1000 } },{ //w 0 15 0 1000
1300 { 0x7000, //w 4 15 12 7
1301 0xff41, //w 3 15 0 ff41
1302 0xde60, //w 2 15 0 de60
1303 0x0140, //w 1 15 0 0140
1304 0x0077 } },{ //w 0 15 0 0077
1305 { 0xa000, //w 4 15 12 a
1306 0xdf01, //w 3 15 0 df01
1307 0xdf20, //w 2 15 0 df20
1308 0xff95, //w 1 15 0 ff95
1309 0xfa00 } },{ //w 0 15 0 fa00
1310 { 0xb000, //w 4 15 12 b
1311 0xff41, //w 3 15 0 ff41
1312 0xde20, //w 2 15 0 de20
1313 0x0140, //w 1 15 0 0140
1314 0x00bb } },{ //w 0 15 0 00bb
1315 { 0xf000, //w 4 15 12 f
1316 0xdf01, //w 3 15 0 df01
1317 0xdf20, //w 2 15 0 df20
1318 0xff95, //w 1 15 0 ff95
1319 0xbf00 } //w 0 15 0 bf00
1320 }
1321 }, *p = phy_magic;
07d3f51f 1322 unsigned int i;
1da177e4 1323
a441d7b6
FR		 1324 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1325 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1326 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1327 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1328
1329 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1330 int val, pos = 4;
1331
1332 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1333 mdio_write(ioaddr, pos, val);
1334 while (--pos >= 0)
1335 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1336 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1337 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1338 }
a441d7b6 1339 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1340}
1341
5615d9f1
FR		 1342static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1343{
a441d7b6
FR		 1344 struct phy_reg phy_reg_init[] = {
1345 { 0x1f, 0x0002 },
1346 { 0x01, 0x90d0 },
1347 { 0x1f, 0x0000 }
1348 };
1349
1350 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1351}
1352
236b8082
FR		 1353static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1354{
1355 struct phy_reg phy_reg_init[] = {
1356 { 0x10, 0xf41b },
1357 { 0x1f, 0x0000 }
1358 };
1359
1360 mdio_write(ioaddr, 0x1f, 0x0001);
1361 mdio_patch(ioaddr, 0x16, 1 << 0);
1362
1363 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1364}
1365
1366static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1367{
1368 struct phy_reg phy_reg_init[] = {
1369 { 0x1f, 0x0001 },
1370 { 0x10, 0xf41b },
1371 { 0x1f, 0x0000 }
1372 };
1373
1374 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1375}
1376
867763c1
FR		 1377static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1378{
1379 struct phy_reg phy_reg_init[] = {
1380 { 0x1f, 0x0000 },
1381 { 0x1d, 0x0f00 },
1382 { 0x1f, 0x0002 },
1383 { 0x0c, 0x1ec8 },
1384 { 0x1f, 0x0000 }
1385 };
1386
1387 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1388}
1389
1390static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1391{
1392 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1393 { 0x1f, 0x0001 },
1394 { 0x12, 0x2300 },
867763c1
FR		 1395 { 0x1f, 0x0002 },
1396 { 0x00, 0x88d4 },
1397 { 0x01, 0x82b1 },
1398 { 0x03, 0x7002 },
1399 { 0x08, 0x9e30 },
1400 { 0x09, 0x01f0 },
1401 { 0x0a, 0x5500 },
1402 { 0x0c, 0x00c8 },
1403 { 0x1f, 0x0003 },
1404 { 0x12, 0xc096 },
1405 { 0x16, 0x000a },
f50d4275
FR		 1406 { 0x1f, 0x0000 },
1407 { 0x1f, 0x0000 },
1408 { 0x09, 0x2000 },
1409 { 0x09, 0x0000 }
867763c1
FR		 1410 };
1411
1412 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1413
1414 mdio_patch(ioaddr, 0x14, 1 << 5);
1415 mdio_patch(ioaddr, 0x0d, 1 << 5);
1416 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1417}
1418
7da97ec9
FR		 1419static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1420{
1421 struct phy_reg phy_reg_init[] = {
f50d4275 1422 { 0x1f, 0x0001 },
7da97ec9 1423 { 0x12, 0x2300 },
f50d4275
FR		 1424 { 0x03, 0x802f },
1425 { 0x02, 0x4f02 },
1426 { 0x01, 0x0409 },
1427 { 0x00, 0xf099 },
1428 { 0x04, 0x9800 },
1429 { 0x04, 0x9000 },
1430 { 0x1d, 0x3d98 },
7da97ec9
FR		 1431 { 0x1f, 0x0002 },
1432 { 0x0c, 0x7eb8 },
f50d4275
FR		 1433 { 0x06, 0x0761 },
1434 { 0x1f, 0x0003 },
1435 { 0x16, 0x0f0a },
7da97ec9
FR		 1436 { 0x1f, 0x0000 }
1437 };
1438
1439 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1440
1441 mdio_patch(ioaddr, 0x16, 1 << 0);
1442 mdio_patch(ioaddr, 0x14, 1 << 5);
1443 mdio_patch(ioaddr, 0x0d, 1 << 5);
1444 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1445}
1446
2857ffb7
FR		 1447static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1448{
1449 struct phy_reg phy_reg_init[] = {
1450 { 0x1f, 0x0003 },
1451 { 0x08, 0x441d },
1452 { 0x01, 0x9100 },
1453 { 0x1f, 0x0000 }
1454 };
1455
1456 mdio_write(ioaddr, 0x1f, 0x0000);
1457 mdio_patch(ioaddr, 0x11, 1 << 12);
1458 mdio_patch(ioaddr, 0x19, 1 << 13);
1459
1460 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1461}
1462
5615d9f1
FR		 1463static void rtl_hw_phy_config(struct net_device *dev)
1464{
1465 struct rtl8169_private *tp = netdev_priv(dev);
1466 void __iomem *ioaddr = tp->mmio_addr;
1467
1468 rtl8169_print_mac_version(tp);
1469
1470 switch (tp->mac_version) {
1471 case RTL_GIGA_MAC_VER_01:
1472 break;
1473 case RTL_GIGA_MAC_VER_02:
1474 case RTL_GIGA_MAC_VER_03:
1475 rtl8169s_hw_phy_config(ioaddr);
1476 break;
1477 case RTL_GIGA_MAC_VER_04:
1478 rtl8169sb_hw_phy_config(ioaddr);
1479 break;
2857ffb7
FR		 1480 case RTL_GIGA_MAC_VER_07:
1481 case RTL_GIGA_MAC_VER_08:
1482 case RTL_GIGA_MAC_VER_09:
1483 rtl8102e_hw_phy_config(ioaddr);
1484 break;
236b8082
FR		 1485 case RTL_GIGA_MAC_VER_11:
1486 rtl8168bb_hw_phy_config(ioaddr);
1487 break;
1488 case RTL_GIGA_MAC_VER_12:
1489 rtl8168bef_hw_phy_config(ioaddr);
1490 break;
1491 case RTL_GIGA_MAC_VER_17:
1492 rtl8168bef_hw_phy_config(ioaddr);
1493 break;
867763c1
FR		 1494 case RTL_GIGA_MAC_VER_18:
1495 rtl8168cp_hw_phy_config(ioaddr);
1496 break;
1497 case RTL_GIGA_MAC_VER_19:
1498 rtl8168c_hw_phy_config(ioaddr);
1499 break;
7da97ec9
FR		 1500 case RTL_GIGA_MAC_VER_20:
1501 rtl8168cx_hw_phy_config(ioaddr);
1502 break;
5615d9f1
FR		 1503 default:
1504 break;
1505 }
1506}
1507
1da177e4
LT		 1508static void rtl8169_phy_timer(unsigned long __opaque)
1509{
1510 struct net_device *dev = (struct net_device *)__opaque;
1511 struct rtl8169_private *tp = netdev_priv(dev);
1512 struct timer_list *timer = &tp->timer;
1513 void __iomem *ioaddr = tp->mmio_addr;
1514 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1515
bcf0bf90 1516 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1517
64e4bfb4 1518 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1519 return;
1520
1521 spin_lock_irq(&tp->lock);
1522
1523 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1524 /*
1da177e4
LT		 1525 * A busy loop could burn quite a few cycles on nowadays CPU.
1526 * Let's delay the execution of the timer for a few ticks.
1527 */
1528 timeout = HZ/10;
1529 goto out_mod_timer;
1530 }
1531
1532 if (tp->link_ok(ioaddr))
1533 goto out_unlock;
1534
b57b7e5a
SH		 1535 if (netif_msg_link(tp))
1536 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1537
1538 tp->phy_reset_enable(ioaddr);
1539
1540out_mod_timer:
1541 mod_timer(timer, jiffies + timeout);
1542out_unlock:
1543 spin_unlock_irq(&tp->lock);
1544}
1545
1546static inline void rtl8169_delete_timer(struct net_device *dev)
1547{
1548 struct rtl8169_private *tp = netdev_priv(dev);
1549 struct timer_list *timer = &tp->timer;
1550
e179bb7b 1551 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1552 return;
1553
1554 del_timer_sync(timer);
1555}
1556
1557static inline void rtl8169_request_timer(struct net_device *dev)
1558{
1559 struct rtl8169_private *tp = netdev_priv(dev);
1560 struct timer_list *timer = &tp->timer;
1561
e179bb7b 1562 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1563 return;
1564
2efa53f3 1565 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1566}
1567
1568#ifdef CONFIG_NET_POLL_CONTROLLER
1569/*
1570 * Polling 'interrupt' - used by things like netconsole to send skbs
1571 * without having to re-enable interrupts. It's not called while
1572 * the interrupt routine is executing.
1573 */
1574static void rtl8169_netpoll(struct net_device *dev)
1575{
1576 struct rtl8169_private *tp = netdev_priv(dev);
1577 struct pci_dev *pdev = tp->pci_dev;
1578
1579 disable_irq(pdev->irq);
7d12e780 1580 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1581 enable_irq(pdev->irq);
1582}
1583#endif
1584
1585static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1586 void __iomem *ioaddr)
1587{
1588 iounmap(ioaddr);
1589 pci_release_regions(pdev);
1590 pci_disable_device(pdev);
1591 free_netdev(dev);
1592}
1593
bf793295
FR		 1594static void rtl8169_phy_reset(struct net_device *dev,
1595 struct rtl8169_private *tp)
1596{
1597 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1598 unsigned int i;
bf793295
FR		 1599
1600 tp->phy_reset_enable(ioaddr);
1601 for (i = 0; i < 100; i++) {
1602 if (!tp->phy_reset_pending(ioaddr))
1603 return;
1604 msleep(1);
1605 }
1606 if (netif_msg_link(tp))
1607 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1608}
1609
4ff96fa6
FR		 1610static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1611{
1612 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1613
5615d9f1 1614 rtl_hw_phy_config(dev);
4ff96fa6 1615
77332894
MS		 1616 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1617 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1618 RTL_W8(0x82, 0x01);
1619 }
4ff96fa6 1620
6dccd16b
FR		 1621 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1622
1623 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1624 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1625
bcf0bf90 1626 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1627 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1628 RTL_W8(0x82, 0x01);
1629 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1630 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1631 }
1632
bf793295
FR		 1633 rtl8169_phy_reset(dev, tp);
1634
901dda2b
FR		 1635 /*
1636 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1637 * only 8101. Don't panic.
1638 */
1639 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1640
1641 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1642 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1643}
1644
773d2021
FR		 1645static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1646{
1647 void __iomem *ioaddr = tp->mmio_addr;
1648 u32 high;
1649 u32 low;
1650
1651 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1652 high = addr[4] | (addr[5] << 8);
1653
1654 spin_lock_irq(&tp->lock);
1655
1656 RTL_W8(Cfg9346, Cfg9346_Unlock);
1657 RTL_W32(MAC0, low);
1658 RTL_W32(MAC4, high);
1659 RTL_W8(Cfg9346, Cfg9346_Lock);
1660
1661 spin_unlock_irq(&tp->lock);
1662}
1663
1664static int rtl_set_mac_address(struct net_device *dev, void *p)
1665{
1666 struct rtl8169_private *tp = netdev_priv(dev);
1667 struct sockaddr *addr = p;
1668
1669 if (!is_valid_ether_addr(addr->sa_data))
1670 return -EADDRNOTAVAIL;
1671
1672 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1673
1674 rtl_rar_set(tp, dev->dev_addr);
1675
1676 return 0;
1677}
1678
5f787a1a
FR		 1679static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1680{
1681 struct rtl8169_private *tp = netdev_priv(dev);
1682 struct mii_ioctl_data *data = if_mii(ifr);
1683
1684 if (!netif_running(dev))
1685 return -ENODEV;
1686
1687 switch (cmd) {
1688 case SIOCGMIIPHY:
1689 data->phy_id = 32; /* Internal PHY */
1690 return 0;
1691
1692 case SIOCGMIIREG:
1693 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1694 return 0;
1695
1696 case SIOCSMIIREG:
1697 if (!capable(CAP_NET_ADMIN))
1698 return -EPERM;
1699 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1700 return 0;
1701 }
1702 return -EOPNOTSUPP;
1703}
1704
0e485150
FR		 1705static const struct rtl_cfg_info {
1706 void (*hw_start)(struct net_device *);
1707 unsigned int region;
1708 unsigned int align;
1709 u16 intr_event;
1710 u16 napi_event;
ccdffb9a 1711 unsigned features;
0e485150
FR		 1712} rtl_cfg_infos [] = {
1713 [RTL_CFG_0] = {
1714 .hw_start = rtl_hw_start_8169,
1715 .region = 1,
e9f63f30 1716 .align = 0,
0e485150
FR		 1717 .intr_event = SYSErr | LinkChg | RxOverflow |
1718 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1719 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1720 .features = RTL_FEATURE_GMII
0e485150
FR		 1721 },
1722 [RTL_CFG_1] = {
1723 .hw_start = rtl_hw_start_8168,
1724 .region = 2,
1725 .align = 8,
1726 .intr_event = SYSErr | LinkChg | RxOverflow |
1727 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1728 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1729 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1730 },
1731 [RTL_CFG_2] = {
1732 .hw_start = rtl_hw_start_8101,
1733 .region = 2,
1734 .align = 8,
1735 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1736 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1737 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1738 .features = RTL_FEATURE_MSI
0e485150
FR		 1739 }
1740};
1741
fbac58fc
FR		 1742/* Cfg9346_Unlock assumed. */
1743static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1744 const struct rtl_cfg_info *cfg)
1745{
1746 unsigned msi = 0;
1747 u8 cfg2;
1748
1749 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1750 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1751 if (pci_enable_msi(pdev)) {
1752 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1753 } else {
1754 cfg2 |= MSIEnable;
1755 msi = RTL_FEATURE_MSI;
1756 }
1757 }
1758 RTL_W8(Config2, cfg2);
1759 return msi;
1760}
1761
1762static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1763{
1764 if (tp->features & RTL_FEATURE_MSI) {
1765 pci_disable_msi(pdev);
1766 tp->features &= ~RTL_FEATURE_MSI;
1767 }
1768}
1769
7bf6bf48
IV		 1770static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1771{
1772 int ret, count = 100;
1773 u16 status = 0;
1774 u32 value;
1775
1776 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1777 if (ret < 0)
1778 return ret;
1779
1780 do {
1781 udelay(10);
1782 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1783 if (ret < 0)
1784 return ret;
1785 } while (!(status & PCI_VPD_ADDR_F) && --count);
1786
1787 if (!(status & PCI_VPD_ADDR_F))
1788 return -ETIMEDOUT;
1789
1790 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1791 if (ret < 0)
1792 return ret;
1793
1794 *val = cpu_to_le32(value);
1795
1796 return 0;
1797}
1798
1799static void rtl_init_mac_address(struct rtl8169_private *tp,
1800 void __iomem *ioaddr)
1801{
1802 struct pci_dev *pdev = tp->pci_dev;
1803 u8 cfg1;
1804 int vpd_cap;
1805 u8 mac[8];
1806 DECLARE_MAC_BUF(buf);
1807
1808 cfg1 = RTL_R8(Config1);
1809 if (!(cfg1 & VPD)) {
1810 dprintk("VPD access not enabled, enabling\n");
1811 RTL_W8(Cfg9346, Cfg9346_Unlock);
1812 RTL_W8(Config1, cfg1 | VPD);
1813 RTL_W8(Cfg9346, Cfg9346_Lock);
1814 }
1815
1816 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1817 if (!vpd_cap)
1818 return;
1819
1820 /* MAC address is stored in EEPROM at offset 0x0e
1821 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1822 * address as defined in the PCI 2.2 Specifications, but the VPD data
1823 * is always consecutive 4-byte data starting from the VPD address
1824 * specified."
1825 */
1826 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1827 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1828 dprintk("Reading MAC address from EEPROM failed\n");
1829 return;
1830 }
1831
1832 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1833
1834 /* Write MAC address */
1835 rtl_rar_set(tp, mac);
1836}
1837
1da177e4 1838static int __devinit
4ff96fa6 1839rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1840{
0e485150
FR		 1841 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1842 const unsigned int region = cfg->region;
1da177e4 1843 struct rtl8169_private *tp;
ccdffb9a 1844 struct mii_if_info *mii;
4ff96fa6
FR		 1845 struct net_device *dev;
1846 void __iomem *ioaddr;
07d3f51f
FR		 1847 unsigned int i;
1848 int rc;
1da177e4 1849
4ff96fa6
FR		 1850 if (netif_msg_drv(&debug)) {
1851 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1852 MODULENAME, RTL8169_VERSION);
1853 }
1da177e4 1854
1da177e4 1855 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1856 if (!dev) {
b57b7e5a 1857 if (netif_msg_drv(&debug))
9b91cf9d 1858 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1859 rc = -ENOMEM;
1860 goto out;
1da177e4
LT		 1861 }
1862
1da177e4
LT		 1863 SET_NETDEV_DEV(dev, &pdev->dev);
1864 tp = netdev_priv(dev);
c4028958 1865 tp->dev = dev;
21e197f2 1866 tp->pci_dev = pdev;
b57b7e5a 1867 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1868
ccdffb9a
FR		 1869 mii = &tp->mii;
1870 mii->dev = dev;
1871 mii->mdio_read = rtl_mdio_read;
1872 mii->mdio_write = rtl_mdio_write;
1873 mii->phy_id_mask = 0x1f;
1874 mii->reg_num_mask = 0x1f;
1875 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1876
1da177e4
LT		 1877 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1878 rc = pci_enable_device(pdev);
b57b7e5a 1879 if (rc < 0) {
2e8a538d 1880 if (netif_msg_probe(tp))
9b91cf9d 1881 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1882 goto err_out_free_dev_1;
1da177e4
LT		 1883 }
1884
1885 rc = pci_set_mwi(pdev);
1886 if (rc < 0)
4ff96fa6 1887 goto err_out_disable_2;
1da177e4 1888
1da177e4 1889 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1890 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1891 if (netif_msg_probe(tp)) {
9b91cf9d 1892 dev_err(&pdev->dev,
bcf0bf90
FR		 1893 "region #%d not an MMIO resource, aborting\n",
1894 region);
4ff96fa6 1895 }
1da177e4 1896 rc = -ENODEV;
4ff96fa6 1897 goto err_out_mwi_3;
1da177e4 1898 }
4ff96fa6 1899
1da177e4 1900 /* check for weird/broken PCI region reporting */
bcf0bf90 1901 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1902 if (netif_msg_probe(tp)) {
9b91cf9d 1903 dev_err(&pdev->dev,
4ff96fa6
FR		 1904 "Invalid PCI region size(s), aborting\n");
1905 }
1da177e4 1906 rc = -ENODEV;
4ff96fa6 1907 goto err_out_mwi_3;
1da177e4
LT		 1908 }
1909
1910 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1911 if (rc < 0) {
2e8a538d 1912 if (netif_msg_probe(tp))
9b91cf9d 1913 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1914 goto err_out_mwi_3;
1da177e4
LT		 1915 }
1916
1917 tp->cp_cmd = PCIMulRW | RxChkSum;
1918
1919 if ((sizeof(dma_addr_t) > 4) &&
1920 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1921 tp->cp_cmd |= PCIDAC;
1922 dev->features |= NETIF_F_HIGHDMA;
1923 } else {
1924 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1925 if (rc < 0) {
4ff96fa6 1926 if (netif_msg_probe(tp)) {
9b91cf9d 1927 dev_err(&pdev->dev,
4ff96fa6
FR		 1928 "DMA configuration failed.\n");
1929 }
1930 goto err_out_free_res_4;
1da177e4
LT		 1931 }
1932 }
1933
1934 pci_set_master(pdev);
1935
1936 /* ioremap MMIO region */
bcf0bf90 1937 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1938 if (!ioaddr) {
b57b7e5a 1939 if (netif_msg_probe(tp))
9b91cf9d 1940 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1941 rc = -EIO;
4ff96fa6 1942 goto err_out_free_res_4;
1da177e4
LT		 1943 }
1944
9c14ceaf
FR		 1945 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1946 if (!tp->pcie_cap && netif_msg_probe(tp))
1947 dev_info(&pdev->dev, "no PCI Express capability\n");
1948
1da177e4
LT		 1949 /* Unneeded ? Don't mess with Mrs. Murphy. */
1950 rtl8169_irq_mask_and_ack(ioaddr);
1951
1952 /* Soft reset the chip. */
1953 RTL_W8(ChipCmd, CmdReset);
1954
1955 /* Check that the chip has finished the reset. */
07d3f51f 1956 for (i = 0; i < 100; i++) {
1da177e4
LT		 1957 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1958 break;
b518fa8e 1959 msleep_interruptible(1);
1da177e4
LT		 1960 }
1961
1962 /* Identify chip attached to board */
1963 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1964
1965 rtl8169_print_mac_version(tp);
1da177e4 1966
cee60c37 1967 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 1968 if (tp->mac_version == rtl_chip_info[i].mac_version)
1969 break;
1970 }
cee60c37 1971 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 1972 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1973 if (netif_msg_probe(tp)) {
2e8a538d 1974 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1975 "unknown chip version, assuming %s\n",
1976 rtl_chip_info[0].name);
b57b7e5a 1977 }
cee60c37 1978 i = 0;
1da177e4
LT		 1979 }
1980 tp->chipset = i;
1981
5d06a99f
FR		 1982 RTL_W8(Cfg9346, Cfg9346_Unlock);
1983 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1984 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 1985 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
1986 tp->features |= RTL_FEATURE_WOL;
1987 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
1988 tp->features |= RTL_FEATURE_WOL;
fbac58fc 1989 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1990 RTL_W8(Cfg9346, Cfg9346_Lock);
1991
66ec5d4f
FR		 1992 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1993 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 1994 tp->set_speed = rtl8169_set_speed_tbi;
1995 tp->get_settings = rtl8169_gset_tbi;
1996 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1997 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1998 tp->link_ok = rtl8169_tbi_link_ok;
1999
64e4bfb4 2000 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2001 } else {
2002 tp->set_speed = rtl8169_set_speed_xmii;
2003 tp->get_settings = rtl8169_gset_xmii;
2004 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2005 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2006 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 2007
2008 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 2009 }
2010
df58ef51
FR		 2011 spin_lock_init(&tp->lock);
2012
7bf6bf48
IV		 2013 rtl_init_mac_address(tp, ioaddr);
2014
2015 /* Get MAC address */
1da177e4
LT		 2016 for (i = 0; i < MAC_ADDR_LEN; i++)
2017 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2018 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 2019
2020 dev->open = rtl8169_open;
2021 dev->hard_start_xmit = rtl8169_start_xmit;
2022 dev->get_stats = rtl8169_get_stats;
2023 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2024 dev->stop = rtl8169_close;
2025 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 2026 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 2027 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2028 dev->irq = pdev->irq;
2029 dev->base_addr = (unsigned long) ioaddr;
2030 dev->change_mtu = rtl8169_change_mtu;
773d2021 2031 dev->set_mac_address = rtl_set_mac_address;
1da177e4 2032
bea3348e 2033 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2034
2035#ifdef CONFIG_R8169_VLAN
2036 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2037 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 2038#endif
2039
2040#ifdef CONFIG_NET_POLL_CONTROLLER
2041 dev->poll_controller = rtl8169_netpoll;
2042#endif
2043
2044 tp->intr_mask = 0xffff;
1da177e4 2045 tp->mmio_addr = ioaddr;
0e485150
FR		 2046 tp->align = cfg->align;
2047 tp->hw_start = cfg->hw_start;
2048 tp->intr_event = cfg->intr_event;
2049 tp->napi_event = cfg->napi_event;
1da177e4 2050
2efa53f3
FR		 2051 init_timer(&tp->timer);
2052 tp->timer.data = (unsigned long) dev;
2053 tp->timer.function = rtl8169_phy_timer;
2054
1da177e4 2055 rc = register_netdev(dev);
4ff96fa6 2056 if (rc < 0)
fbac58fc 2057 goto err_out_msi_5;
1da177e4
LT		 2058
2059 pci_set_drvdata(pdev, dev);
2060
b57b7e5a 2061 if (netif_msg_probe(tp)) {
96b9709c
FR		 2062 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2063
b57b7e5a
SH		 2064 printk(KERN_INFO "%s: %s at 0x%lx, "
2065 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2066 "XID %08x IRQ %d\n",
b57b7e5a 2067 dev->name,
bcf0bf90 2068 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2069 dev->base_addr,
2070 dev->dev_addr[0], dev->dev_addr[1],
2071 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2072 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2073 }
1da177e4 2074
4ff96fa6 2075 rtl8169_init_phy(dev, tp);
8b76ab39 2076 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2077
4ff96fa6
FR		 2078out:
2079 return rc;
1da177e4 2080
fbac58fc
FR		 2081err_out_msi_5:
2082 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2083 iounmap(ioaddr);
2084err_out_free_res_4:
2085 pci_release_regions(pdev);
2086err_out_mwi_3:
2087 pci_clear_mwi(pdev);
2088err_out_disable_2:
2089 pci_disable_device(pdev);
2090err_out_free_dev_1:
2091 free_netdev(dev);
2092 goto out;
1da177e4
LT		 2093}
2094
07d3f51f 2095static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2096{
2097 struct net_device *dev = pci_get_drvdata(pdev);
2098 struct rtl8169_private *tp = netdev_priv(dev);
2099
eb2a021c
FR		 2100 flush_scheduled_work();
2101
1da177e4 2102 unregister_netdev(dev);
fbac58fc 2103 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2104 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2105 pci_set_drvdata(pdev, NULL);
2106}
2107
1da177e4
LT		 2108static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2109 struct net_device *dev)
2110{
2111 unsigned int mtu = dev->mtu;
2112
2113 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2114}
2115
2116static int rtl8169_open(struct net_device *dev)
2117{
2118 struct rtl8169_private *tp = netdev_priv(dev);
2119 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2120 int retval = -ENOMEM;
1da177e4 2121
1da177e4 2122
99f252b0 2123 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2124
2125 /*
2126 * Rx and Tx desscriptors needs 256 bytes alignment.
2127 * pci_alloc_consistent provides more.
2128 */
2129 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2130 &tp->TxPhyAddr);
2131 if (!tp->TxDescArray)
99f252b0 2132 goto out;
1da177e4
LT		 2133
2134 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2135 &tp->RxPhyAddr);
2136 if (!tp->RxDescArray)
99f252b0 2137 goto err_free_tx_0;
1da177e4
LT		 2138
2139 retval = rtl8169_init_ring(dev);
2140 if (retval < 0)
99f252b0 2141 goto err_free_rx_1;
1da177e4 2142
c4028958 2143 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2144
99f252b0
FR		 2145 smp_mb();
2146
fbac58fc
FR		 2147 retval = request_irq(dev->irq, rtl8169_interrupt,
2148 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2149 dev->name, dev);
2150 if (retval < 0)
2151 goto err_release_ring_2;
2152
bea3348e 2153 napi_enable(&tp->napi);
bea3348e 2154
07ce4064 2155 rtl_hw_start(dev);
1da177e4
LT		 2156
2157 rtl8169_request_timer(dev);
2158
2159 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2160out:
2161 return retval;
2162
99f252b0
FR		 2163err_release_ring_2:
2164 rtl8169_rx_clear(tp);
2165err_free_rx_1:
1da177e4
LT		 2166 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2167 tp->RxPhyAddr);
99f252b0 2168err_free_tx_0:
1da177e4
LT		 2169 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2170 tp->TxPhyAddr);
1da177e4
LT		 2171 goto out;
2172}
2173
2174static void rtl8169_hw_reset(void __iomem *ioaddr)
2175{
2176 /* Disable interrupts */
2177 rtl8169_irq_mask_and_ack(ioaddr);
2178
2179 /* Reset the chipset */
2180 RTL_W8(ChipCmd, CmdReset);
2181
2182 /* PCI commit */
2183 RTL_R8(ChipCmd);
2184}
2185
7f796d83 2186static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2187{
2188 void __iomem *ioaddr = tp->mmio_addr;
2189 u32 cfg = rtl8169_rx_config;
2190
2191 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2192 RTL_W32(RxConfig, cfg);
2193
2194 /* Set DMA burst size and Interframe Gap Time */
2195 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2196 (InterFrameGap << TxInterFrameGapShift));
2197}
2198
07ce4064 2199static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2200{
2201 struct rtl8169_private *tp = netdev_priv(dev);
2202 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2203 unsigned int i;
1da177e4
LT		 2204
2205 /* Soft reset the chip. */
2206 RTL_W8(ChipCmd, CmdReset);
2207
2208 /* Check that the chip has finished the reset. */
07d3f51f 2209 for (i = 0; i < 100; i++) {
1da177e4
LT		 2210 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2211 break;
b518fa8e 2212 msleep_interruptible(1);
1da177e4
LT		 2213 }
2214
07ce4064
FR		 2215 tp->hw_start(dev);
2216
07ce4064
FR		 2217 netif_start_queue(dev);
2218}
2219
2220
7f796d83
FR		 2221static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2222 void __iomem *ioaddr)
2223{
2224 /*
2225 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2226 * register to be written before TxDescAddrLow to work.
2227 * Switching from MMIO to I/O access fixes the issue as well.
2228 */
2229 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2230 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2231 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2232 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2233}
2234
2235static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2236{
2237 u16 cmd;
2238
2239 cmd = RTL_R16(CPlusCmd);
2240 RTL_W16(CPlusCmd, cmd);
2241 return cmd;
2242}
2243
2244static void rtl_set_rx_max_size(void __iomem *ioaddr)
2245{
2246 /* Low hurts. Let's disable the filtering. */
2247 RTL_W16(RxMaxSize, 16383);
2248}
2249
6dccd16b
FR		 2250static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2251{
2252 struct {
2253 u32 mac_version;
2254 u32 clk;
2255 u32 val;
2256 } cfg2_info [] = {
2257 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2258 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2259 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2260 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2261 }, *p = cfg2_info;
2262 unsigned int i;
2263 u32 clk;
2264
2265 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2266 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2267 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2268 RTL_W32(0x7c, p->val);
2269 break;
2270 }
2271 }
2272}
2273
07ce4064
FR		 2274static void rtl_hw_start_8169(struct net_device *dev)
2275{
2276 struct rtl8169_private *tp = netdev_priv(dev);
2277 void __iomem *ioaddr = tp->mmio_addr;
2278 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2279
9cb427b6
FR		 2280 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2281 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2282 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2283 }
2284
1da177e4 2285 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2286 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2287 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2288 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2289 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2290 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2291
1da177e4
LT		 2292 RTL_W8(EarlyTxThres, EarlyTxThld);
2293
7f796d83 2294 rtl_set_rx_max_size(ioaddr);
1da177e4 2295
c946b304
FR		 2296 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2297 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2298 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2299 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2300 rtl_set_rx_tx_config_registers(tp);
1da177e4 2301
7f796d83 2302 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2303
bcf0bf90
FR		 2304 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2305 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2306 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2307 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2308 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2309 }
2310
bcf0bf90
FR		 2311 RTL_W16(CPlusCmd, tp->cp_cmd);
2312
6dccd16b
FR		 2313 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2314
1da177e4
LT		 2315 /*
2316 * Undocumented corner. Supposedly:
2317 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2318 */
2319 RTL_W16(IntrMitigate, 0x0000);
2320
7f796d83 2321 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2322
c946b304
FR		 2323 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2324 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2325 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2326 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2327 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2328 rtl_set_rx_tx_config_registers(tp);
2329 }
2330
1da177e4 2331 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2332
2333 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2334 RTL_R8(IntrMask);
1da177e4
LT		 2335
2336 RTL_W32(RxMissed, 0);
2337
07ce4064 2338 rtl_set_rx_mode(dev);
1da177e4
LT		 2339
2340 /* no early-rx interrupts */
2341 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2342
2343 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2344 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2345}
1da177e4 2346
9c14ceaf 2347static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2348{
9c14ceaf
FR		 2349 struct net_device *dev = pci_get_drvdata(pdev);
2350 struct rtl8169_private *tp = netdev_priv(dev);
2351 int cap = tp->pcie_cap;
2352
2353 if (cap) {
2354 u16 ctl;
458a9f61 2355
9c14ceaf
FR		 2356 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2357 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2358 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2359 }
458a9f61
FR		 2360}
2361
dacf8154
FR		 2362static void rtl_csi_access_enable(void __iomem *ioaddr)
2363{
2364 u32 csi;
2365
2366 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2367 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2368}
2369
2370struct ephy_info {
2371 unsigned int offset;
2372 u16 mask;
2373 u16 bits;
2374};
2375
2376static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2377{
2378 u16 w;
2379
2380 while (len-- > 0) {
2381 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2382 rtl_ephy_write(ioaddr, e->offset, w);
2383 e++;
2384 }
2385}
2386
07ce4064
FR		 2387static void rtl_hw_start_8168(struct net_device *dev)
2388{
2dd99530
FR		 2389 struct rtl8169_private *tp = netdev_priv(dev);
2390 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2391 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2392
2393 RTL_W8(Cfg9346, Cfg9346_Unlock);
2394
2395 RTL_W8(EarlyTxThres, EarlyTxThld);
2396
2397 rtl_set_rx_max_size(ioaddr);
2398
0e485150 2399 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2400
2401 RTL_W16(CPlusCmd, tp->cp_cmd);
2402
0e485150 2403 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2404
0e485150
FR		 2405 /* Work around for RxFIFO overflow. */
2406 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2407 tp->intr_event |= RxFIFOOver | PCSTimeout;
2408 tp->intr_event &= ~RxOverflow;
2409 }
2410
2411 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2412
b8363901
FR		 2413 rtl_set_rx_mode(dev);
2414
2415 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2416 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2417
2418 RTL_R8(IntrMask);
2419
b8363901 2420 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2dd99530 2421
0e485150
FR		 2422 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2423
b8363901
FR		 2424 RTL_W8(Cfg9346, Cfg9346_Lock);
2425
2dd99530 2426 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2427
0e485150 2428 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2429}
1da177e4 2430
2857ffb7
FR		 2431#define R810X_CPCMD_QUIRK_MASK (\
2432 EnableBist | \
2433 Mac_dbgo_oe | \
2434 Force_half_dup | \
2435 Force_half_dup | \
2436 Force_txflow_en | \
2437 Cxpl_dbg_sel | \
2438 ASF | \
2439 PktCntrDisable | \
2440 PCIDAC | \
2441 PCIMulRW)
2442
2443static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2444{
2445 static struct ephy_info e_info_8102e_1[] = {
2446 { 0x01, 0, 0x6e65 },
2447 { 0x02, 0, 0x091f },
2448 { 0x03, 0, 0xc2f9 },
2449 { 0x06, 0, 0xafb5 },
2450 { 0x07, 0, 0x0e00 },
2451 { 0x19, 0, 0xec80 },
2452 { 0x01, 0, 0x2e65 },
2453 { 0x01, 0, 0x6e65 }
2454 };
2455 u8 cfg1;
2456
2457 rtl_csi_access_enable(ioaddr);
2458
2459 RTL_W8(DBG_REG, FIX_NAK_1);
2460
2461 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2462
2463 RTL_W8(Config1,
2464 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2465 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2466
2467 cfg1 = RTL_R8(Config1);
2468 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2469 RTL_W8(Config1, cfg1 & ~LEDS0);
2470
2471 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2472
2473 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2474}
2475
2476static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2477{
2478 rtl_csi_access_enable(ioaddr);
2479
2480 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2481
2482 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2483 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2484
2485 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2486}
2487
2488static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2489{
2490 rtl_hw_start_8102e_2(ioaddr, pdev);
2491
2492 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2493}
2494
07ce4064
FR		 2495static void rtl_hw_start_8101(struct net_device *dev)
2496{
cdf1a608
FR		 2497 struct rtl8169_private *tp = netdev_priv(dev);
2498 void __iomem *ioaddr = tp->mmio_addr;
2499 struct pci_dev *pdev = tp->pci_dev;
2500
e3cf0cc0
FR		 2501 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2502 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2503 int cap = tp->pcie_cap;
2504
2505 if (cap) {
2506 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2507 PCI_EXP_DEVCTL_NOSNOOP_EN);
2508 }
cdf1a608
FR		 2509 }
2510
2857ffb7
FR		 2511 switch (tp->mac_version) {
2512 case RTL_GIGA_MAC_VER_07:
2513 rtl_hw_start_8102e_1(ioaddr, pdev);
2514 break;
2515
2516 case RTL_GIGA_MAC_VER_08:
2517 rtl_hw_start_8102e_3(ioaddr, pdev);
2518 break;
2519
2520 case RTL_GIGA_MAC_VER_09:
2521 rtl_hw_start_8102e_2(ioaddr, pdev);
2522 break;
cdf1a608
FR		 2523 }
2524
2525 RTL_W8(Cfg9346, Cfg9346_Unlock);
2526
2527 RTL_W8(EarlyTxThres, EarlyTxThld);
2528
2529 rtl_set_rx_max_size(ioaddr);
2530
2531 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2532
2533 RTL_W16(CPlusCmd, tp->cp_cmd);
2534
2535 RTL_W16(IntrMitigate, 0x0000);
2536
2537 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2538
2539 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2540 rtl_set_rx_tx_config_registers(tp);
2541
2542 RTL_W8(Cfg9346, Cfg9346_Lock);
2543
2544 RTL_R8(IntrMask);
2545
cdf1a608
FR		 2546 rtl_set_rx_mode(dev);
2547
0e485150
FR		 2548 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2549
cdf1a608 2550 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2551
0e485150 2552 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2553}
2554
2555static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2556{
2557 struct rtl8169_private *tp = netdev_priv(dev);
2558 int ret = 0;
2559
2560 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2561 return -EINVAL;
2562
2563 dev->mtu = new_mtu;
2564
2565 if (!netif_running(dev))
2566 goto out;
2567
2568 rtl8169_down(dev);
2569
2570 rtl8169_set_rxbufsize(tp, dev);
2571
2572 ret = rtl8169_init_ring(dev);
2573 if (ret < 0)
2574 goto out;
2575
bea3348e 2576 napi_enable(&tp->napi);
1da177e4 2577
07ce4064 2578 rtl_hw_start(dev);
1da177e4
LT		 2579
2580 rtl8169_request_timer(dev);
2581
2582out:
2583 return ret;
2584}
2585
2586static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2587{
95e0918d 2588 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2589 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2590}
2591
2592static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2593 struct sk_buff **sk_buff, struct RxDesc *desc)
2594{
2595 struct pci_dev *pdev = tp->pci_dev;
2596
2597 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2598 PCI_DMA_FROMDEVICE);
2599 dev_kfree_skb(*sk_buff);
2600 *sk_buff = NULL;
2601 rtl8169_make_unusable_by_asic(desc);
2602}
2603
2604static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2605{
2606 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2607
2608 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2609}
2610
2611static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2612 u32 rx_buf_sz)
2613{
2614 desc->addr = cpu_to_le64(mapping);
2615 wmb();
2616 rtl8169_mark_to_asic(desc, rx_buf_sz);
2617}
2618
15d31758
SH		 2619static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2620 struct net_device *dev,
2621 struct RxDesc *desc, int rx_buf_sz,
2622 unsigned int align)
1da177e4
LT		 2623{
2624 struct sk_buff *skb;
2625 dma_addr_t mapping;
e9f63f30 2626 unsigned int pad;
1da177e4 2627
e9f63f30
FR		 2628 pad = align ? align : NET_IP_ALIGN;
2629
2630 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2631 if (!skb)
2632 goto err_out;
2633
e9f63f30 2634 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2635
689be439 2636 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2637 PCI_DMA_FROMDEVICE);
2638
2639 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2640out:
15d31758 2641 return skb;
1da177e4
LT		 2642
2643err_out:
1da177e4
LT		 2644 rtl8169_make_unusable_by_asic(desc);
2645 goto out;
2646}
2647
2648static void rtl8169_rx_clear(struct rtl8169_private *tp)
2649{
07d3f51f 2650 unsigned int i;
1da177e4
LT		 2651
2652 for (i = 0; i < NUM_RX_DESC; i++) {
2653 if (tp->Rx_skbuff[i]) {
2654 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2655 tp->RxDescArray + i);
2656 }
2657 }
2658}
2659
2660static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2661 u32 start, u32 end)
2662{
2663 u32 cur;
5b0384f4 2664
4ae47c2d 2665 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2666 struct sk_buff *skb;
2667 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2668
4ae47c2d
FR		 2669 WARN_ON((s32)(end - cur) < 0);
2670
1da177e4
LT		 2671 if (tp->Rx_skbuff[i])
2672 continue;
bcf0bf90 2673
15d31758
SH		 2674 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2675 tp->RxDescArray + i,
2676 tp->rx_buf_sz, tp->align);
2677 if (!skb)
1da177e4 2678 break;
15d31758
SH		 2679
2680 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2681 }
2682 return cur - start;
2683}
2684
2685static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2686{
2687 desc->opts1 |= cpu_to_le32(RingEnd);
2688}
2689
2690static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2691{
2692 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2693}
2694
2695static int rtl8169_init_ring(struct net_device *dev)
2696{
2697 struct rtl8169_private *tp = netdev_priv(dev);
2698
2699 rtl8169_init_ring_indexes(tp);
2700
2701 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2702 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2703
2704 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2705 goto err_out;
2706
2707 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2708
2709 return 0;
2710
2711err_out:
2712 rtl8169_rx_clear(tp);
2713 return -ENOMEM;
2714}
2715
2716static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2717 struct TxDesc *desc)
2718{
2719 unsigned int len = tx_skb->len;
2720
2721 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2722 desc->opts1 = 0x00;
2723 desc->opts2 = 0x00;
2724 desc->addr = 0x00;
2725 tx_skb->len = 0;
2726}
2727
2728static void rtl8169_tx_clear(struct rtl8169_private *tp)
2729{
2730 unsigned int i;
2731
2732 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2733 unsigned int entry = i % NUM_TX_DESC;
2734 struct ring_info *tx_skb = tp->tx_skb + entry;
2735 unsigned int len = tx_skb->len;
2736
2737 if (len) {
2738 struct sk_buff *skb = tx_skb->skb;
2739
2740 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2741 tp->TxDescArray + entry);
2742 if (skb) {
2743 dev_kfree_skb(skb);
2744 tx_skb->skb = NULL;
2745 }
cebf8cc7 2746 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2747 }
2748 }
2749 tp->cur_tx = tp->dirty_tx = 0;
2750}
2751
c4028958 2752static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2753{
2754 struct rtl8169_private *tp = netdev_priv(dev);
2755
c4028958 2756 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2757 schedule_delayed_work(&tp->task, 4);
2758}
2759
2760static void rtl8169_wait_for_quiescence(struct net_device *dev)
2761{
2762 struct rtl8169_private *tp = netdev_priv(dev);
2763 void __iomem *ioaddr = tp->mmio_addr;
2764
2765 synchronize_irq(dev->irq);
2766
2767 /* Wait for any pending NAPI task to complete */
bea3348e 2768 napi_disable(&tp->napi);
1da177e4
LT		 2769
2770 rtl8169_irq_mask_and_ack(ioaddr);
2771
d1d08d12
DM		 2772 tp->intr_mask = 0xffff;
2773 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2774 napi_enable(&tp->napi);
1da177e4
LT		 2775}
2776
c4028958 2777static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2778{
c4028958
DH		 2779 struct rtl8169_private *tp =
2780 container_of(work, struct rtl8169_private, task.work);
2781 struct net_device *dev = tp->dev;
1da177e4
LT		 2782 int ret;
2783
eb2a021c
FR		 2784 rtnl_lock();
2785
2786 if (!netif_running(dev))
2787 goto out_unlock;
2788
2789 rtl8169_wait_for_quiescence(dev);
2790 rtl8169_close(dev);
1da177e4
LT		 2791
2792 ret = rtl8169_open(dev);
2793 if (unlikely(ret < 0)) {
07d3f51f 2794 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2795 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2796 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2797 }
2798 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2799 }
eb2a021c
FR		 2800
2801out_unlock:
2802 rtnl_unlock();
1da177e4
LT		 2803}
2804
c4028958 2805static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2806{
c4028958
DH		 2807 struct rtl8169_private *tp =
2808 container_of(work, struct rtl8169_private, task.work);
2809 struct net_device *dev = tp->dev;
1da177e4 2810
eb2a021c
FR		 2811 rtnl_lock();
2812
1da177e4 2813 if (!netif_running(dev))
eb2a021c 2814 goto out_unlock;
1da177e4
LT		 2815
2816 rtl8169_wait_for_quiescence(dev);
2817
bea3348e 2818 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2819 rtl8169_tx_clear(tp);
2820
2821 if (tp->dirty_rx == tp->cur_rx) {
2822 rtl8169_init_ring_indexes(tp);
07ce4064 2823 rtl_hw_start(dev);
1da177e4 2824 netif_wake_queue(dev);
cebf8cc7 2825 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2826 } else {
07d3f51f 2827 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2828 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2829 dev->name);
1da177e4
LT		 2830 }
2831 rtl8169_schedule_work(dev, rtl8169_reset_task);
2832 }
eb2a021c
FR		 2833
2834out_unlock:
2835 rtnl_unlock();
1da177e4
LT		 2836}
2837
2838static void rtl8169_tx_timeout(struct net_device *dev)
2839{
2840 struct rtl8169_private *tp = netdev_priv(dev);
2841
2842 rtl8169_hw_reset(tp->mmio_addr);
2843
2844 /* Let's wait a bit while any (async) irq lands on */
2845 rtl8169_schedule_work(dev, rtl8169_reset_task);
2846}
2847
2848static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2849 u32 opts1)
2850{
2851 struct skb_shared_info *info = skb_shinfo(skb);
2852 unsigned int cur_frag, entry;
a6343afb 2853 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2854
2855 entry = tp->cur_tx;
2856 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2857 skb_frag_t *frag = info->frags + cur_frag;
2858 dma_addr_t mapping;
2859 u32 status, len;
2860 void *addr;
2861
2862 entry = (entry + 1) % NUM_TX_DESC;
2863
2864 txd = tp->TxDescArray + entry;
2865 len = frag->size;
2866 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2867 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2868
2869 /* anti gcc 2.95.3 bugware (sic) */
2870 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2871
2872 txd->opts1 = cpu_to_le32(status);
2873 txd->addr = cpu_to_le64(mapping);
2874
2875 tp->tx_skb[entry].len = len;
2876 }
2877
2878 if (cur_frag) {
2879 tp->tx_skb[entry].skb = skb;
2880 txd->opts1 |= cpu_to_le32(LastFrag);
2881 }
2882
2883 return cur_frag;
2884}
2885
2886static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2887{
2888 if (dev->features & NETIF_F_TSO) {
7967168c 2889 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2890
2891 if (mss)
2892 return LargeSend | ((mss & MSSMask) << MSSShift);
2893 }
84fa7933 2894 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2895 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2896
2897 if (ip->protocol == IPPROTO_TCP)
2898 return IPCS | TCPCS;
2899 else if (ip->protocol == IPPROTO_UDP)
2900 return IPCS | UDPCS;
2901 WARN_ON(1); /* we need a WARN() */
2902 }
2903 return 0;
2904}
2905
2906static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2907{
2908 struct rtl8169_private *tp = netdev_priv(dev);
2909 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2910 struct TxDesc *txd = tp->TxDescArray + entry;
2911 void __iomem *ioaddr = tp->mmio_addr;
2912 dma_addr_t mapping;
2913 u32 status, len;
2914 u32 opts1;
188f4af0 2915 int ret = NETDEV_TX_OK;
5b0384f4 2916
1da177e4 2917 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2918 if (netif_msg_drv(tp)) {
2919 printk(KERN_ERR
2920 "%s: BUG! Tx Ring full when queue awake!\n",
2921 dev->name);
2922 }
1da177e4
LT		 2923 goto err_stop;
2924 }
2925
2926 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2927 goto err_stop;
2928
2929 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2930
2931 frags = rtl8169_xmit_frags(tp, skb, opts1);
2932 if (frags) {
2933 len = skb_headlen(skb);
2934 opts1 |= FirstFrag;
2935 } else {
2936 len = skb->len;
2937
2938 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2939 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2940 goto err_update_stats;
2941 len = ETH_ZLEN;
2942 }
2943
2944 opts1 |= FirstFrag | LastFrag;
2945 tp->tx_skb[entry].skb = skb;
2946 }
2947
2948 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2949
2950 tp->tx_skb[entry].len = len;
2951 txd->addr = cpu_to_le64(mapping);
2952 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2953
2954 wmb();
2955
2956 /* anti gcc 2.95.3 bugware (sic) */
2957 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2958 txd->opts1 = cpu_to_le32(status);
2959
2960 dev->trans_start = jiffies;
2961
2962 tp->cur_tx += frags + 1;
2963
2964 smp_wmb();
2965
275391a4 2966 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2967
2968 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2969 netif_stop_queue(dev);
2970 smp_rmb();
2971 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2972 netif_wake_queue(dev);
2973 }
2974
2975out:
2976 return ret;
2977
2978err_stop:
2979 netif_stop_queue(dev);
188f4af0 2980 ret = NETDEV_TX_BUSY;
1da177e4 2981err_update_stats:
cebf8cc7 2982 dev->stats.tx_dropped++;
1da177e4
LT		 2983 goto out;
2984}
2985
2986static void rtl8169_pcierr_interrupt(struct net_device *dev)
2987{
2988 struct rtl8169_private *tp = netdev_priv(dev);
2989 struct pci_dev *pdev = tp->pci_dev;
2990 void __iomem *ioaddr = tp->mmio_addr;
2991 u16 pci_status, pci_cmd;
2992
2993 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2994 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2995
b57b7e5a
SH		 2996 if (netif_msg_intr(tp)) {
2997 printk(KERN_ERR
2998 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2999 dev->name, pci_cmd, pci_status);
3000 }
1da177e4
LT		 3001
3002 /*
3003 * The recovery sequence below admits a very elaborated explanation:
3004 * - it seems to work;
d03902b8
FR		 3005 * - I did not see what else could be done;
3006 * - it makes iop3xx happy.
1da177e4
LT		 3007 *
3008 * Feel free to adjust to your needs.
3009 */
a27993f3 3010 if (pdev->broken_parity_status)
d03902b8
FR		 3011 pci_cmd &= ~PCI_COMMAND_PARITY;
3012 else
3013 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3014
3015 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3016
3017 pci_write_config_word(pdev, PCI_STATUS,
3018 pci_status & (PCI_STATUS_DETECTED_PARITY |
3019 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3020 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3021
3022 /* The infamous DAC f*ckup only happens at boot time */
3023 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3024 if (netif_msg_intr(tp))
3025 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3026 tp->cp_cmd &= ~PCIDAC;
3027 RTL_W16(CPlusCmd, tp->cp_cmd);
3028 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3029 }
3030
3031 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3032
3033 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3034}
3035
07d3f51f
FR		 3036static void rtl8169_tx_interrupt(struct net_device *dev,
3037 struct rtl8169_private *tp,
3038 void __iomem *ioaddr)
1da177e4
LT		 3039{
3040 unsigned int dirty_tx, tx_left;
3041
1da177e4
LT		 3042 dirty_tx = tp->dirty_tx;
3043 smp_rmb();
3044 tx_left = tp->cur_tx - dirty_tx;
3045
3046 while (tx_left > 0) {
3047 unsigned int entry = dirty_tx % NUM_TX_DESC;
3048 struct ring_info *tx_skb = tp->tx_skb + entry;
3049 u32 len = tx_skb->len;
3050 u32 status;
3051
3052 rmb();
3053 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3054 if (status & DescOwn)
3055 break;
3056
cebf8cc7
FR		 3057 dev->stats.tx_bytes += len;
3058 dev->stats.tx_packets++;
1da177e4
LT		 3059
3060 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3061
3062 if (status & LastFrag) {
3063 dev_kfree_skb_irq(tx_skb->skb);
3064 tx_skb->skb = NULL;
3065 }
3066 dirty_tx++;
3067 tx_left--;
3068 }
3069
3070 if (tp->dirty_tx != dirty_tx) {
3071 tp->dirty_tx = dirty_tx;
3072 smp_wmb();
3073 if (netif_queue_stopped(dev) &&
3074 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3075 netif_wake_queue(dev);
3076 }
d78ae2dc
FR		 3077 /*
3078 * 8168 hack: TxPoll requests are lost when the Tx packets are
3079 * too close. Let's kick an extra TxPoll request when a burst
3080 * of start_xmit activity is detected (if it is not detected,
3081 * it is slow enough). -- FR
3082 */
3083 smp_rmb();
3084 if (tp->cur_tx != dirty_tx)
3085 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3086 }
3087}
3088
126fa4b9
FR		 3089static inline int rtl8169_fragmented_frame(u32 status)
3090{
3091 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3092}
3093
1da177e4
LT		 3094static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3095{
3096 u32 opts1 = le32_to_cpu(desc->opts1);
3097 u32 status = opts1 & RxProtoMask;
3098
3099 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3100 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3101 ((status == RxProtoIP) && !(opts1 & IPFail)))
3102 skb->ip_summed = CHECKSUM_UNNECESSARY;
3103 else
3104 skb->ip_summed = CHECKSUM_NONE;
3105}
3106
07d3f51f
FR		 3107static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3108 struct rtl8169_private *tp, int pkt_size,
3109 dma_addr_t addr)
1da177e4 3110{
b449655f
SH		 3111 struct sk_buff *skb;
3112 bool done = false;
1da177e4 3113
b449655f
SH		 3114 if (pkt_size >= rx_copybreak)
3115 goto out;
1da177e4 3116
07d3f51f 3117 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3118 if (!skb)
3119 goto out;
3120
07d3f51f
FR		 3121 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3122 PCI_DMA_FROMDEVICE);
86402234 3123 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3124 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3125 *sk_buff = skb;
3126 done = true;
3127out:
3128 return done;
1da177e4
LT		 3129}
3130
07d3f51f
FR		 3131static int rtl8169_rx_interrupt(struct net_device *dev,
3132 struct rtl8169_private *tp,
bea3348e 3133 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3134{
3135 unsigned int cur_rx, rx_left;
3136 unsigned int delta, count;
3137
1da177e4
LT		 3138 cur_rx = tp->cur_rx;
3139 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3140 rx_left = min(rx_left, budget);
1da177e4 3141
4dcb7d33 3142 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3143 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3144 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3145 u32 status;
3146
3147 rmb();
126fa4b9 3148 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3149
3150 if (status & DescOwn)
3151 break;
4dcb7d33 3152 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3153 if (netif_msg_rx_err(tp)) {
3154 printk(KERN_INFO
3155 "%s: Rx ERROR. status = %08x\n",
3156 dev->name, status);
3157 }
cebf8cc7 3158 dev->stats.rx_errors++;
1da177e4 3159 if (status & (RxRWT | RxRUNT))
cebf8cc7 3160 dev->stats.rx_length_errors++;
1da177e4 3161 if (status & RxCRC)
cebf8cc7 3162 dev->stats.rx_crc_errors++;
9dccf611
FR		 3163 if (status & RxFOVF) {
3164 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3165 dev->stats.rx_fifo_errors++;
9dccf611 3166 }
126fa4b9 3167 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3168 } else {
1da177e4 3169 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3170 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3171 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3172 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3173
126fa4b9
FR		 3174 /*
3175 * The driver does not support incoming fragmented
3176 * frames. They are seen as a symptom of over-mtu
3177 * sized frames.
3178 */
3179 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3180 dev->stats.rx_dropped++;
3181 dev->stats.rx_length_errors++;
126fa4b9 3182 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3183 continue;
126fa4b9
FR		 3184 }
3185
1da177e4 3186 rtl8169_rx_csum(skb, desc);
bcf0bf90 3187
07d3f51f 3188 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3189 pci_dma_sync_single_for_device(pdev, addr,
3190 pkt_size, PCI_DMA_FROMDEVICE);
3191 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3192 } else {
a866bbf6 3193 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3194 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3195 tp->Rx_skbuff[entry] = NULL;
3196 }
3197
1da177e4
LT		 3198 skb_put(skb, pkt_size);
3199 skb->protocol = eth_type_trans(skb, dev);
3200
3201 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3202 netif_receive_skb(skb);
1da177e4
LT		 3203
3204 dev->last_rx = jiffies;
cebf8cc7
FR		 3205 dev->stats.rx_bytes += pkt_size;
3206 dev->stats.rx_packets++;
1da177e4 3207 }
6dccd16b
FR		 3208
3209 /* Work around for AMD plateform. */
95e0918d 3210 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3211 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3212 desc->opts2 = 0;
3213 cur_rx++;
3214 }
1da177e4
LT		 3215 }
3216
3217 count = cur_rx - tp->cur_rx;
3218 tp->cur_rx = cur_rx;
3219
3220 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3221 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3222 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3223 tp->dirty_rx += delta;
3224
3225 /*
3226 * FIXME: until there is periodic timer to try and refill the ring,
3227 * a temporary shortage may definitely kill the Rx process.
3228 * - disable the asic to try and avoid an overflow and kick it again
3229 * after refill ?
3230 * - how do others driver handle this condition (Uh oh...).
3231 */
b57b7e5a 3232 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3233 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3234
3235 return count;
3236}
3237
07d3f51f 3238static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3239{
07d3f51f 3240 struct net_device *dev = dev_instance;
1da177e4 3241 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3242 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3243 int handled = 0;
865c652d 3244 int status;
1da177e4 3245
865c652d 3246 status = RTL_R16(IntrStatus);
1da177e4 3247
865c652d
FR		 3248 /* hotplug/major error/no more work/shared irq */
3249 if ((status == 0xffff) || !status)
3250 goto out;
1da177e4 3251
865c652d 3252 handled = 1;
1da177e4 3253
865c652d
FR		 3254 if (unlikely(!netif_running(dev))) {
3255 rtl8169_asic_down(ioaddr);
3256 goto out;
3257 }
1da177e4 3258
865c652d
FR		 3259 status &= tp->intr_mask;
3260 RTL_W16(IntrStatus,
3261 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3262
865c652d
FR		 3263 if (!(status & tp->intr_event))
3264 goto out;
0e485150 3265
865c652d
FR		 3266 /* Work around for rx fifo overflow */
3267 if (unlikely(status & RxFIFOOver) &&
3268 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3269 netif_stop_queue(dev);
3270 rtl8169_tx_timeout(dev);
3271 goto out;
3272 }
1da177e4 3273
865c652d
FR		 3274 if (unlikely(status & SYSErr)) {
3275 rtl8169_pcierr_interrupt(dev);
3276 goto out;
3277 }
1da177e4 3278
865c652d
FR		 3279 if (status & LinkChg)
3280 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3281
865c652d
FR		 3282 if (status & tp->napi_event) {
3283 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3284 tp->intr_mask = ~tp->napi_event;
313b0305 3285
bea3348e
SH		 3286 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3287 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 3288 else if (netif_msg_intr(tp)) {
3289 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3290 dev->name, status);
b57b7e5a 3291 }
1da177e4
LT		 3292 }
3293out:
3294 return IRQ_RETVAL(handled);
3295}
3296
bea3348e 3297static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3298{
bea3348e
SH		 3299 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3300 struct net_device *dev = tp->dev;
1da177e4 3301 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3302 int work_done;
1da177e4 3303
bea3348e 3304 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3305 rtl8169_tx_interrupt(dev, tp, ioaddr);
3306
bea3348e
SH		 3307 if (work_done < budget) {
3308 netif_rx_complete(dev, napi);
1da177e4
LT		 3309 tp->intr_mask = 0xffff;
3310 /*
3311 * 20040426: the barrier is not strictly required but the
3312 * behavior of the irq handler could be less predictable
3313 * without it. Btw, the lack of flush for the posted pci
3314 * write is safe - FR
3315 */
3316 smp_wmb();
0e485150 3317 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3318 }
3319
bea3348e 3320 return work_done;
1da177e4 3321}
1da177e4 3322
523a6094
FR		 3323static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3324{
3325 struct rtl8169_private *tp = netdev_priv(dev);
3326
3327 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3328 return;
3329
3330 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3331 RTL_W32(RxMissed, 0);
3332}
3333
1da177e4
LT		 3334static void rtl8169_down(struct net_device *dev)
3335{
3336 struct rtl8169_private *tp = netdev_priv(dev);
3337 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3338 unsigned int intrmask;
1da177e4
LT		 3339
3340 rtl8169_delete_timer(dev);
3341
3342 netif_stop_queue(dev);
3343
93dd79e8 3344 napi_disable(&tp->napi);
93dd79e8 3345
1da177e4
LT		 3346core_down:
3347 spin_lock_irq(&tp->lock);
3348
3349 rtl8169_asic_down(ioaddr);
3350
523a6094 3351 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3352
3353 spin_unlock_irq(&tp->lock);
3354
3355 synchronize_irq(dev->irq);
3356
1da177e4 3357 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3358 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3359
3360 /*
3361 * And now for the 50k$ question: are IRQ disabled or not ?
3362 *
3363 * Two paths lead here:
3364 * 1) dev->close
3365 * -> netif_running() is available to sync the current code and the
3366 * IRQ handler. See rtl8169_interrupt for details.
3367 * 2) dev->change_mtu
3368 * -> rtl8169_poll can not be issued again and re-enable the
3369 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3370 *
3371 * No loop if hotpluged or major error (0xffff).
1da177e4 3372 */
733b736c
AP		 3373 intrmask = RTL_R16(IntrMask);
3374 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3375 goto core_down;
3376
3377 rtl8169_tx_clear(tp);
3378
3379 rtl8169_rx_clear(tp);
3380}
3381
3382static int rtl8169_close(struct net_device *dev)
3383{
3384 struct rtl8169_private *tp = netdev_priv(dev);
3385 struct pci_dev *pdev = tp->pci_dev;
3386
3387 rtl8169_down(dev);
3388
3389 free_irq(dev->irq, dev);
3390
1da177e4
LT		 3391 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3392 tp->RxPhyAddr);
3393 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3394 tp->TxPhyAddr);
3395 tp->TxDescArray = NULL;
3396 tp->RxDescArray = NULL;
3397
3398 return 0;
3399}
3400
07ce4064 3401static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3402{
3403 struct rtl8169_private *tp = netdev_priv(dev);
3404 void __iomem *ioaddr = tp->mmio_addr;
3405 unsigned long flags;
3406 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3407 int rx_mode;
1da177e4
LT		 3408 u32 tmp = 0;
3409
3410 if (dev->flags & IFF_PROMISC) {
3411 /* Unconditionally log net taps. */
b57b7e5a
SH		 3412 if (netif_msg_link(tp)) {
3413 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3414 dev->name);
3415 }
1da177e4
LT		 3416 rx_mode =
3417 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3418 AcceptAllPhys;
3419 mc_filter[1] = mc_filter[0] = 0xffffffff;
3420 } else if ((dev->mc_count > multicast_filter_limit)
3421 || (dev->flags & IFF_ALLMULTI)) {
3422 /* Too many to filter perfectly -- accept all multicasts. */
3423 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3424 mc_filter[1] = mc_filter[0] = 0xffffffff;
3425 } else {
3426 struct dev_mc_list *mclist;
07d3f51f
FR		 3427 unsigned int i;
3428
1da177e4
LT		 3429 rx_mode = AcceptBroadcast | AcceptMyPhys;
3430 mc_filter[1] = mc_filter[0] = 0;
3431 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3432 i++, mclist = mclist->next) {
3433 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3434 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3435 rx_mode |= AcceptMulticast;
3436 }
3437 }
3438
3439 spin_lock_irqsave(&tp->lock, flags);
3440
3441 tmp = rtl8169_rx_config | rx_mode |
3442 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3443
f887cce8 3444 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3445 u32 data = mc_filter[0];
3446
3447 mc_filter[0] = swab32(mc_filter[1]);
3448 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3449 }
3450
1da177e4
LT		 3451 RTL_W32(MAR0 + 0, mc_filter[0]);
3452 RTL_W32(MAR0 + 4, mc_filter[1]);
3453
57a9f236
FR		 3454 RTL_W32(RxConfig, tmp);
3455
1da177e4
LT		 3456 spin_unlock_irqrestore(&tp->lock, flags);
3457}
3458
3459/**
3460 * rtl8169_get_stats - Get rtl8169 read/write statistics
3461 * @dev: The Ethernet Device to get statistics for
3462 *
3463 * Get TX/RX statistics for rtl8169
3464 */
3465static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3466{
3467 struct rtl8169_private *tp = netdev_priv(dev);
3468 void __iomem *ioaddr = tp->mmio_addr;
3469 unsigned long flags;
3470
3471 if (netif_running(dev)) {
3472 spin_lock_irqsave(&tp->lock, flags);
523a6094 3473 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3474 spin_unlock_irqrestore(&tp->lock, flags);
3475 }
5b0384f4 3476
cebf8cc7 3477 return &dev->stats;
1da177e4
LT		 3478}
3479
5d06a99f
FR		 3480#ifdef CONFIG_PM
3481
3482static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3483{
3484 struct net_device *dev = pci_get_drvdata(pdev);
3485 struct rtl8169_private *tp = netdev_priv(dev);
3486 void __iomem *ioaddr = tp->mmio_addr;
3487
3488 if (!netif_running(dev))
1371fa6d 3489 goto out_pci_suspend;
5d06a99f
FR		 3490
3491 netif_device_detach(dev);
3492 netif_stop_queue(dev);
3493
3494 spin_lock_irq(&tp->lock);
3495
3496 rtl8169_asic_down(ioaddr);
3497
523a6094 3498 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3499
3500 spin_unlock_irq(&tp->lock);
3501
1371fa6d 3502out_pci_suspend:
5d06a99f 3503 pci_save_state(pdev);
f23e7fda
FR		 3504 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3505 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3506 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3507
5d06a99f
FR		 3508 return 0;
3509}
3510
3511static int rtl8169_resume(struct pci_dev *pdev)
3512{
3513 struct net_device *dev = pci_get_drvdata(pdev);
3514
1371fa6d
FR		 3515 pci_set_power_state(pdev, PCI_D0);
3516 pci_restore_state(pdev);
3517 pci_enable_wake(pdev, PCI_D0, 0);
3518
5d06a99f
FR		 3519 if (!netif_running(dev))
3520 goto out;
3521
3522 netif_device_attach(dev);
3523
5d06a99f
FR		 3524 rtl8169_schedule_work(dev, rtl8169_reset_task);
3525out:
3526 return 0;
3527}
3528
3529#endif /* CONFIG_PM */
3530
1da177e4
LT		 3531static struct pci_driver rtl8169_pci_driver = {
3532 .name = MODULENAME,
3533 .id_table = rtl8169_pci_tbl,
3534 .probe = rtl8169_init_one,
3535 .remove = __devexit_p(rtl8169_remove_one),
3536#ifdef CONFIG_PM
3537 .suspend = rtl8169_suspend,
3538 .resume = rtl8169_resume,
3539#endif
3540};
3541
07d3f51f 3542static int __init rtl8169_init_module(void)
1da177e4 3543{
29917620 3544 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3545}
3546
07d3f51f 3547static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3548{
3549 pci_unregister_driver(&rtl8169_pci_driver);
3550}
3551
3552module_init(rtl8169_init_module);
3553module_exit(rtl8169_cleanup_module);
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