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wireless: convert drivers to netdev_tx_t
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4
LT		 54/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 56static const int multicast_filter_limit = 32;
1da177e4
LT		 57
58/* MAC address length */
59#define MAC_ADDR_LEN 6
60
9c14ceaf 61#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 62#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 65#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 66#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_NAPI_WEIGHT 64
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77#define RTL8169_TX_TIMEOUT (6*HZ)
78#define RTL8169_PHY_TIMEOUT (10*HZ)
79
ea8dbdd1 80#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 82#define RTL_EEPROM_SIG_ADDR 0x0000
83
1da177e4
LT		 84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
f21b75e9 93 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9
FR		 117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
1da177e4
LT		 119};
120
1da177e4
LT		 121#define _R(NAME,MAC,MASK) \
122 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
123
3c6bee1d 124static const struct {
1da177e4
LT		 125 const char *name;
126 u8 mac_version;
127 u32 RxConfigMask; /* Clears the bits supported by this chip */
128} rtl_chip_info[] = {
ba6eb6ee
FR		 129 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
130 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
131 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
132 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 134 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 135 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
137 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 143 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
146 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 151 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9
FR		 152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
153 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
1da177e4
LT		 154};
155#undef _R
156
bcf0bf90
FR		 157enum cfg_version {
158 RTL_CFG_0 = 0x00,
159 RTL_CFG_1,
160 RTL_CFG_2
161};
162
07ce4064
FR		 163static void rtl_hw_start_8169(struct net_device *);
164static void rtl_hw_start_8168(struct net_device *);
165static void rtl_hw_start_8101(struct net_device *);
166
1da177e4 167static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 174 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 175 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
176 { PCI_VENDOR_ID_LINKSYS, 0x1032,
177 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 178 { 0x0001, 0x8168,
179 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 180 {0,},
181};
182
183MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
184
185static int rx_copybreak = 200;
186static int use_dac;
b57b7e5a
SH		 187static struct {
188 u32 msg_enable;
189} debug = { -1 };
1da177e4 190
07d3f51f
FR		 191enum rtl_registers {
192 MAC0 = 0, /* Ethernet hardware address. */
773d2021 193 MAC4 = 4,
07d3f51f
FR		 194 MAR0 = 8, /* Multicast filter. */
195 CounterAddrLow = 0x10,
196 CounterAddrHigh = 0x14,
197 TxDescStartAddrLow = 0x20,
198 TxDescStartAddrHigh = 0x24,
199 TxHDescStartAddrLow = 0x28,
200 TxHDescStartAddrHigh = 0x2c,
201 FLASH = 0x30,
202 ERSR = 0x36,
203 ChipCmd = 0x37,
204 TxPoll = 0x38,
205 IntrMask = 0x3c,
206 IntrStatus = 0x3e,
207 TxConfig = 0x40,
208 RxConfig = 0x44,
209 RxMissed = 0x4c,
210 Cfg9346 = 0x50,
211 Config0 = 0x51,
212 Config1 = 0x52,
213 Config2 = 0x53,
214 Config3 = 0x54,
215 Config4 = 0x55,
216 Config5 = 0x56,
217 MultiIntr = 0x5c,
218 PHYAR = 0x60,
07d3f51f
FR		 219 PHYstatus = 0x6c,
220 RxMaxSize = 0xda,
221 CPlusCmd = 0xe0,
222 IntrMitigate = 0xe2,
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 EarlyTxThres = 0xec,
226 FuncEvent = 0xf0,
227 FuncEventMask = 0xf4,
228 FuncPresetState = 0xf8,
229 FuncForceEvent = 0xfc,
1da177e4
LT		 230};
231
f162a5d1
FR		 232enum rtl8110_registers {
233 TBICSR = 0x64,
234 TBI_ANAR = 0x68,
235 TBI_LPAR = 0x6a,
236};
237
238enum rtl8168_8101_registers {
239 CSIDR = 0x64,
240 CSIAR = 0x68,
241#define CSIAR_FLAG 0x80000000
242#define CSIAR_WRITE_CMD 0x80000000
243#define CSIAR_BYTE_ENABLE 0x0f
244#define CSIAR_BYTE_ENABLE_SHIFT 12
245#define CSIAR_ADDR_MASK 0x0fff
246
247 EPHYAR = 0x80,
248#define EPHYAR_FLAG 0x80000000
249#define EPHYAR_WRITE_CMD 0x80000000
250#define EPHYAR_REG_MASK 0x1f
251#define EPHYAR_REG_SHIFT 16
252#define EPHYAR_DATA_MASK 0xffff
253 DBG_REG = 0xd1,
254#define FIX_NAK_1 (1 << 4)
255#define FIX_NAK_2 (1 << 3)
256};
257
07d3f51f 258enum rtl_register_content {
1da177e4 259 /* InterruptStatusBits */
07d3f51f
FR		 260 SYSErr = 0x8000,
261 PCSTimeout = 0x4000,
262 SWInt = 0x0100,
263 TxDescUnavail = 0x0080,
264 RxFIFOOver = 0x0040,
265 LinkChg = 0x0020,
266 RxOverflow = 0x0010,
267 TxErr = 0x0008,
268 TxOK = 0x0004,
269 RxErr = 0x0002,
270 RxOK = 0x0001,
1da177e4
LT		 271
272 /* RxStatusDesc */
9dccf611
FR		 273 RxFOVF = (1 << 23),
274 RxRWT = (1 << 22),
275 RxRES = (1 << 21),
276 RxRUNT = (1 << 20),
277 RxCRC = (1 << 19),
1da177e4
LT		 278
279 /* ChipCmdBits */
07d3f51f
FR		 280 CmdReset = 0x10,
281 CmdRxEnb = 0x08,
282 CmdTxEnb = 0x04,
283 RxBufEmpty = 0x01,
1da177e4 284
275391a4
FR		 285 /* TXPoll register p.5 */
286 HPQ = 0x80, /* Poll cmd on the high prio queue */
287 NPQ = 0x40, /* Poll cmd on the low prio queue */
288 FSWInt = 0x01, /* Forced software interrupt */
289
1da177e4 290 /* Cfg9346Bits */
07d3f51f
FR		 291 Cfg9346_Lock = 0x00,
292 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 293
294 /* rx_mode_bits */
07d3f51f
FR		 295 AcceptErr = 0x20,
296 AcceptRunt = 0x10,
297 AcceptBroadcast = 0x08,
298 AcceptMulticast = 0x04,
299 AcceptMyPhys = 0x02,
300 AcceptAllPhys = 0x01,
1da177e4
LT		 301
302 /* RxConfigBits */
07d3f51f
FR		 303 RxCfgFIFOShift = 13,
304 RxCfgDMAShift = 8,
1da177e4
LT		 305
306 /* TxConfigBits */
307 TxInterFrameGapShift = 24,
308 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
309
5d06a99f 310 /* Config1 register p.24 */
f162a5d1
FR		 311 LEDS1 = (1 << 7),
312 LEDS0 = (1 << 6),
fbac58fc 313 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 314 Speed_down = (1 << 4),
315 MEMMAP = (1 << 3),
316 IOMAP = (1 << 2),
317 VPD = (1 << 1),
5d06a99f
FR		 318 PMEnable = (1 << 0), /* Power Management Enable */
319
6dccd16b
FR		 320 /* Config2 register p. 25 */
321 PCI_Clock_66MHz = 0x01,
322 PCI_Clock_33MHz = 0x00,
323
61a4dcc2
FR		 324 /* Config3 register p.25 */
325 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
326 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 327 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 328
5d06a99f 329 /* Config5 register p.27 */
61a4dcc2
FR		 330 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF = (1 << 5), /* Accept Multicast wakeup frame */
332 UWF = (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 334 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
335
1da177e4
LT		 336 /* TBICSR p.28 */
337 TBIReset = 0x80000000,
338 TBILoopback = 0x40000000,
339 TBINwEnable = 0x20000000,
340 TBINwRestart = 0x10000000,
341 TBILinkOk = 0x02000000,
342 TBINwComplete = 0x01000000,
343
344 /* CPlusCmd p.31 */
f162a5d1
FR		 345 EnableBist = (1 << 15), // 8168 8101
346 Mac_dbgo_oe = (1 << 14), // 8168 8101
347 Normal_mode = (1 << 13), // unused
348 Force_half_dup = (1 << 12), // 8168 8101
349 Force_rxflow_en = (1 << 11), // 8168 8101
350 Force_txflow_en = (1 << 10), // 8168 8101
351 Cxpl_dbg_sel = (1 << 9), // 8168 8101
352 ASF = (1 << 8), // 8168 8101
353 PktCntrDisable = (1 << 7), // 8168 8101
354 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 355 RxVlan = (1 << 6),
356 RxChkSum = (1 << 5),
357 PCIDAC = (1 << 4),
358 PCIMulRW = (1 << 3),
0e485150
FR		 359 INTT_0 = 0x0000, // 8168
360 INTT_1 = 0x0001, // 8168
361 INTT_2 = 0x0002, // 8168
362 INTT_3 = 0x0003, // 8168
1da177e4
LT		 363
364 /* rtl8169_PHYstatus */
07d3f51f
FR		 365 TBI_Enable = 0x80,
366 TxFlowCtrl = 0x40,
367 RxFlowCtrl = 0x20,
368 _1000bpsF = 0x10,
369 _100bps = 0x08,
370 _10bps = 0x04,
371 LinkStatus = 0x02,
372 FullDup = 0x01,
1da177e4 373
1da177e4 374 /* _TBICSRBit */
07d3f51f 375 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 376
377 /* DumpCounterCommand */
07d3f51f 378 CounterDump = 0x8,
1da177e4
LT		 379};
380
07d3f51f 381enum desc_status_bit {
1da177e4
LT		 382 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd = (1 << 30), /* End of descriptor ring */
384 FirstFrag = (1 << 29), /* First segment of a packet */
385 LastFrag = (1 << 28), /* Final segment of a packet */
386
387 /* Tx private */
388 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift = 16, /* MSS value position */
390 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS = (1 << 18), /* Calculate IP checksum */
392 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag = (1 << 17), /* Add VLAN tag */
395
396 /* Rx private */
397 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
398 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
399
400#define RxProtoUDP (PID1)
401#define RxProtoTCP (PID0)
402#define RxProtoIP (PID1 | PID0)
403#define RxProtoMask RxProtoIP
404
405 IPFail = (1 << 16), /* IP checksum failed */
406 UDPFail = (1 << 15), /* UDP/IP checksum failed */
407 TCPFail = (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag = (1 << 16), /* VLAN tag available */
409};
410
411#define RsvdMask 0x3fffc000
412
413struct TxDesc {
6cccd6e7
REB		 414 __le32 opts1;
415 __le32 opts2;
416 __le64 addr;
1da177e4
LT		 417};
418
419struct RxDesc {
6cccd6e7
REB		 420 __le32 opts1;
421 __le32 opts2;
422 __le64 addr;
1da177e4
LT		 423};
424
425struct ring_info {
426 struct sk_buff *skb;
427 u32 len;
428 u8 __pad[sizeof(void *) - sizeof(u32)];
429};
430
f23e7fda 431enum features {
ccdffb9a
FR		 432 RTL_FEATURE_WOL = (1 << 0),
433 RTL_FEATURE_MSI = (1 << 1),
434 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 435};
436
355423d0
IV		 437struct rtl8169_counters {
438 __le64 tx_packets;
439 __le64 rx_packets;
440 __le64 tx_errors;
441 __le32 rx_errors;
442 __le16 rx_missed;
443 __le16 align_errors;
444 __le32 tx_one_collision;
445 __le32 tx_multi_collision;
446 __le64 rx_unicast;
447 __le64 rx_broadcast;
448 __le32 rx_multicast;
449 __le16 tx_aborted;
450 __le16 tx_underun;
451};
452
1da177e4
LT		 453struct rtl8169_private {
454 void __iomem *mmio_addr; /* memory map physical address */
455 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 456 struct net_device *dev;
bea3348e 457 struct napi_struct napi;
1da177e4 458 spinlock_t lock; /* spin lock flag */
b57b7e5a 459 u32 msg_enable;
1da177e4
LT		 460 int chipset;
461 int mac_version;
1da177e4
LT		 462 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
463 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
464 u32 dirty_rx;
465 u32 dirty_tx;
466 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
467 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
468 dma_addr_t TxPhyAddr;
469 dma_addr_t RxPhyAddr;
470 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
471 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 472 unsigned align;
1da177e4
LT		 473 unsigned rx_buf_sz;
474 struct timer_list timer;
475 u16 cp_cmd;
0e485150
FR		 476 u16 intr_event;
477 u16 napi_event;
1da177e4 478 u16 intr_mask;
1da177e4
LT		 479 int phy_1000_ctrl_reg;
480#ifdef CONFIG_R8169_VLAN
481 struct vlan_group *vlgrp;
482#endif
483 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 484 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 485 void (*phy_reset_enable)(void __iomem *);
07ce4064 486 void (*hw_start)(struct net_device *);
1da177e4
LT		 487 unsigned int (*phy_reset_pending)(void __iomem *);
488 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 489 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 490 int pcie_cap;
c4028958 491 struct delayed_work task;
f23e7fda 492 unsigned features;
ccdffb9a
FR		 493
494 struct mii_if_info mii;
355423d0 495 struct rtl8169_counters counters;
1da177e4
LT		 496};
497
979b6c13 498MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 499MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 500module_param(rx_copybreak, int, 0);
1b7efd58 501MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 502module_param(use_dac, int, 0);
503MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 504module_param_named(debug, debug.msg_enable, int, 0);
505MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 506MODULE_LICENSE("GPL");
507MODULE_VERSION(RTL8169_VERSION);
508
509static int rtl8169_open(struct net_device *dev);
510static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 511static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 512static int rtl8169_init_ring(struct net_device *dev);
07ce4064 513static void rtl_hw_start(struct net_device *dev);
1da177e4 514static int rtl8169_close(struct net_device *dev);
07ce4064 515static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 516static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 517static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 518static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 519 void __iomem *, u32 budget);
4dcb7d33 520static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 521static void rtl8169_down(struct net_device *dev);
99f252b0 522static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 523static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 524
1da177e4 525static const unsigned int rtl8169_rx_config =
5b0384f4 526 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 527
07d3f51f 528static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 529{
530 int i;
531
a6baf3af 532 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 533
2371408c 534 for (i = 20; i > 0; i--) {
07d3f51f
FR		 535 /*
536 * Check if the RTL8169 has completed writing to the specified
537 * MII register.
538 */
5b0384f4 539 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 540 break;
2371408c 541 udelay(25);
1da177e4
LT		 542 }
543}
544
07d3f51f 545static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 546{
547 int i, value = -1;
548
a6baf3af 549 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 550
2371408c 551 for (i = 20; i > 0; i--) {
07d3f51f
FR		 552 /*
553 * Check if the RTL8169 has completed retrieving data from
554 * the specified MII register.
555 */
1da177e4 556 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 557 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 558 break;
559 }
2371408c 560 udelay(25);
1da177e4
LT		 561 }
562 return value;
563}
564
dacf8154
FR		 565static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
566{
567 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
568}
569
ccdffb9a
FR		 570static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
571 int val)
572{
573 struct rtl8169_private *tp = netdev_priv(dev);
574 void __iomem *ioaddr = tp->mmio_addr;
575
576 mdio_write(ioaddr, location, val);
577}
578
579static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
580{
581 struct rtl8169_private *tp = netdev_priv(dev);
582 void __iomem *ioaddr = tp->mmio_addr;
583
584 return mdio_read(ioaddr, location);
585}
586
dacf8154
FR		 587static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
588{
589 unsigned int i;
590
591 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
592 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
593
594 for (i = 0; i < 100; i++) {
595 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
596 break;
597 udelay(10);
598 }
599}
600
601static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
602{
603 u16 value = 0xffff;
604 unsigned int i;
605
606 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
607
608 for (i = 0; i < 100; i++) {
609 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
610 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
611 break;
612 }
613 udelay(10);
614 }
615
616 return value;
617}
618
619static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
620{
621 unsigned int i;
622
623 RTL_W32(CSIDR, value);
624 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
625 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
626
627 for (i = 0; i < 100; i++) {
628 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
629 break;
630 udelay(10);
631 }
632}
633
634static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
635{
636 u32 value = ~0x00;
637 unsigned int i;
638
639 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
640 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
641
642 for (i = 0; i < 100; i++) {
643 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
644 value = RTL_R32(CSIDR);
645 break;
646 }
647 udelay(10);
648 }
649
650 return value;
651}
652
1da177e4
LT		 653static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
654{
655 RTL_W16(IntrMask, 0x0000);
656
657 RTL_W16(IntrStatus, 0xffff);
658}
659
660static void rtl8169_asic_down(void __iomem *ioaddr)
661{
662 RTL_W8(ChipCmd, 0x00);
663 rtl8169_irq_mask_and_ack(ioaddr);
664 RTL_R16(CPlusCmd);
665}
666
667static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
668{
669 return RTL_R32(TBICSR) & TBIReset;
670}
671
672static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
673{
64e4bfb4 674 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 675}
676
677static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
678{
679 return RTL_R32(TBICSR) & TBILinkOk;
680}
681
682static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
683{
684 return RTL_R8(PHYstatus) & LinkStatus;
685}
686
687static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
688{
689 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
690}
691
692static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
693{
694 unsigned int val;
695
9e0db8ef
FR		 696 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
697 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 698}
699
700static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 701 struct rtl8169_private *tp,
702 void __iomem *ioaddr)
1da177e4
LT		 703{
704 unsigned long flags;
705
706 spin_lock_irqsave(&tp->lock, flags);
707 if (tp->link_ok(ioaddr)) {
708 netif_carrier_on(dev);
b57b7e5a
SH		 709 if (netif_msg_ifup(tp))
710 printk(KERN_INFO PFX "%s: link up\n", dev->name);
711 } else {
712 if (netif_msg_ifdown(tp))
713 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 714 netif_carrier_off(dev);
b57b7e5a 715 }
1da177e4
LT		 716 spin_unlock_irqrestore(&tp->lock, flags);
717}
718
61a4dcc2
FR		 719static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
720{
721 struct rtl8169_private *tp = netdev_priv(dev);
722 void __iomem *ioaddr = tp->mmio_addr;
723 u8 options;
724
725 wol->wolopts = 0;
726
727#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
728 wol->supported = WAKE_ANY;
729
730 spin_lock_irq(&tp->lock);
731
732 options = RTL_R8(Config1);
733 if (!(options & PMEnable))
734 goto out_unlock;
735
736 options = RTL_R8(Config3);
737 if (options & LinkUp)
738 wol->wolopts |= WAKE_PHY;
739 if (options & MagicPacket)
740 wol->wolopts |= WAKE_MAGIC;
741
742 options = RTL_R8(Config5);
743 if (options & UWF)
744 wol->wolopts |= WAKE_UCAST;
745 if (options & BWF)
5b0384f4 746 wol->wolopts |= WAKE_BCAST;
61a4dcc2 747 if (options & MWF)
5b0384f4 748 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 749
750out_unlock:
751 spin_unlock_irq(&tp->lock);
752}
753
754static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
755{
756 struct rtl8169_private *tp = netdev_priv(dev);
757 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 758 unsigned int i;
61a4dcc2
FR		 759 static struct {
760 u32 opt;
761 u16 reg;
762 u8 mask;
763 } cfg[] = {
764 { WAKE_ANY, Config1, PMEnable },
765 { WAKE_PHY, Config3, LinkUp },
766 { WAKE_MAGIC, Config3, MagicPacket },
767 { WAKE_UCAST, Config5, UWF },
768 { WAKE_BCAST, Config5, BWF },
769 { WAKE_MCAST, Config5, MWF },
770 { WAKE_ANY, Config5, LanWake }
771 };
772
773 spin_lock_irq(&tp->lock);
774
775 RTL_W8(Cfg9346, Cfg9346_Unlock);
776
777 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
778 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
779 if (wol->wolopts & cfg[i].opt)
780 options |= cfg[i].mask;
781 RTL_W8(cfg[i].reg, options);
782 }
783
784 RTL_W8(Cfg9346, Cfg9346_Lock);
785
f23e7fda
FR		 786 if (wol->wolopts)
787 tp->features |= RTL_FEATURE_WOL;
788 else
789 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 790 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 791
792 spin_unlock_irq(&tp->lock);
793
794 return 0;
795}
796
1da177e4
LT		 797static void rtl8169_get_drvinfo(struct net_device *dev,
798 struct ethtool_drvinfo *info)
799{
800 struct rtl8169_private *tp = netdev_priv(dev);
801
802 strcpy(info->driver, MODULENAME);
803 strcpy(info->version, RTL8169_VERSION);
804 strcpy(info->bus_info, pci_name(tp->pci_dev));
805}
806
807static int rtl8169_get_regs_len(struct net_device *dev)
808{
809 return R8169_REGS_SIZE;
810}
811
812static int rtl8169_set_speed_tbi(struct net_device *dev,
813 u8 autoneg, u16 speed, u8 duplex)
814{
815 struct rtl8169_private *tp = netdev_priv(dev);
816 void __iomem *ioaddr = tp->mmio_addr;
817 int ret = 0;
818 u32 reg;
819
820 reg = RTL_R32(TBICSR);
821 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
822 (duplex == DUPLEX_FULL)) {
823 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
824 } else if (autoneg == AUTONEG_ENABLE)
825 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
826 else {
b57b7e5a
SH		 827 if (netif_msg_link(tp)) {
828 printk(KERN_WARNING "%s: "
829 "incorrect speed setting refused in TBI mode\n",
830 dev->name);
831 }
1da177e4
LT		 832 ret = -EOPNOTSUPP;
833 }
834
835 return ret;
836}
837
838static int rtl8169_set_speed_xmii(struct net_device *dev,
839 u8 autoneg, u16 speed, u8 duplex)
840{
841 struct rtl8169_private *tp = netdev_priv(dev);
842 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 843 int giga_ctrl, bmcr;
1da177e4
LT		 844
845 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 846 int auto_nego;
847
848 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 849 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
850 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 851 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 852
3577aa1b 853 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
854 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 855
3577aa1b 856 /* The 8100e/8101e/8102e do Fast Ethernet only. */
857 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
858 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
859 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
860 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
861 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
862 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
863 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
864 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
865 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
866 } else if (netif_msg_link(tp)) {
bcf0bf90
FR		 867 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
868 dev->name);
869 }
1da177e4 870
3577aa1b 871 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
872
873 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
874 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
875 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
876 /*
877 * Wake up the PHY.
878 * Vendor specific (0x1f) and reserved (0x0e) MII
879 * registers.
880 */
881 mdio_write(ioaddr, 0x1f, 0x0000);
882 mdio_write(ioaddr, 0x0e, 0x0000);
883 }
884
885 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
886 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
887 } else {
888 giga_ctrl = 0;
889
890 if (speed == SPEED_10)
891 bmcr = 0;
892 else if (speed == SPEED_100)
893 bmcr = BMCR_SPEED100;
894 else
895 return -EINVAL;
896
897 if (duplex == DUPLEX_FULL)
898 bmcr |= BMCR_FULLDPLX;
623a1593 899
2584fbc3 900 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 901 }
902
1da177e4
LT		 903 tp->phy_1000_ctrl_reg = giga_ctrl;
904
3577aa1b 905 mdio_write(ioaddr, MII_BMCR, bmcr);
906
907 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
908 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
909 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
910 mdio_write(ioaddr, 0x17, 0x2138);
911 mdio_write(ioaddr, 0x0e, 0x0260);
912 } else {
913 mdio_write(ioaddr, 0x17, 0x2108);
914 mdio_write(ioaddr, 0x0e, 0x0000);
915 }
916 }
917
1da177e4
LT		 918 return 0;
919}
920
921static int rtl8169_set_speed(struct net_device *dev,
922 u8 autoneg, u16 speed, u8 duplex)
923{
924 struct rtl8169_private *tp = netdev_priv(dev);
925 int ret;
926
927 ret = tp->set_speed(dev, autoneg, speed, duplex);
928
64e4bfb4 929 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 930 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
931
932 return ret;
933}
934
935static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
936{
937 struct rtl8169_private *tp = netdev_priv(dev);
938 unsigned long flags;
939 int ret;
940
941 spin_lock_irqsave(&tp->lock, flags);
942 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
943 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 944
1da177e4
LT		 945 return ret;
946}
947
948static u32 rtl8169_get_rx_csum(struct net_device *dev)
949{
950 struct rtl8169_private *tp = netdev_priv(dev);
951
952 return tp->cp_cmd & RxChkSum;
953}
954
955static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
956{
957 struct rtl8169_private *tp = netdev_priv(dev);
958 void __iomem *ioaddr = tp->mmio_addr;
959 unsigned long flags;
960
961 spin_lock_irqsave(&tp->lock, flags);
962
963 if (data)
964 tp->cp_cmd |= RxChkSum;
965 else
966 tp->cp_cmd &= ~RxChkSum;
967
968 RTL_W16(CPlusCmd, tp->cp_cmd);
969 RTL_R16(CPlusCmd);
970
971 spin_unlock_irqrestore(&tp->lock, flags);
972
973 return 0;
974}
975
976#ifdef CONFIG_R8169_VLAN
977
978static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
979 struct sk_buff *skb)
980{
981 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
982 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
983}
984
985static void rtl8169_vlan_rx_register(struct net_device *dev,
986 struct vlan_group *grp)
987{
988 struct rtl8169_private *tp = netdev_priv(dev);
989 void __iomem *ioaddr = tp->mmio_addr;
990 unsigned long flags;
991
992 spin_lock_irqsave(&tp->lock, flags);
993 tp->vlgrp = grp;
994 if (tp->vlgrp)
995 tp->cp_cmd |= RxVlan;
996 else
997 tp->cp_cmd &= ~RxVlan;
998 RTL_W16(CPlusCmd, tp->cp_cmd);
999 RTL_R16(CPlusCmd);
1000 spin_unlock_irqrestore(&tp->lock, flags);
1001}
1002
1da177e4
LT		 1003static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1004 struct sk_buff *skb)
1005{
1006 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1007 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1008 int ret;
1009
865c652d
FR		 1010 if (vlgrp && (opts2 & RxVlanTag)) {
1011 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1012 ret = 0;
1013 } else
1014 ret = -1;
1015 desc->opts2 = 0;
1016 return ret;
1017}
1018
1019#else /* !CONFIG_R8169_VLAN */
1020
1021static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1022 struct sk_buff *skb)
1023{
1024 return 0;
1025}
1026
1027static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1028 struct sk_buff *skb)
1029{
1030 return -1;
1031}
1032
1033#endif
1034
ccdffb9a 1035static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1036{
1037 struct rtl8169_private *tp = netdev_priv(dev);
1038 void __iomem *ioaddr = tp->mmio_addr;
1039 u32 status;
1040
1041 cmd->supported =
1042 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1043 cmd->port = PORT_FIBRE;
1044 cmd->transceiver = XCVR_INTERNAL;
1045
1046 status = RTL_R32(TBICSR);
1047 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1048 cmd->autoneg = !!(status & TBINwEnable);
1049
1050 cmd->speed = SPEED_1000;
1051 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1052
1053 return 0;
1da177e4
LT		 1054}
1055
ccdffb9a 1056static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1057{
1058 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1059
1060 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1061}
1062
1063static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1064{
1065 struct rtl8169_private *tp = netdev_priv(dev);
1066 unsigned long flags;
ccdffb9a 1067 int rc;
1da177e4
LT		 1068
1069 spin_lock_irqsave(&tp->lock, flags);
1070
ccdffb9a 1071 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1072
1073 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1074 return rc;
1da177e4
LT		 1075}
1076
1077static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1078 void *p)
1079{
5b0384f4
FR		 1080 struct rtl8169_private *tp = netdev_priv(dev);
1081 unsigned long flags;
1da177e4 1082
5b0384f4
FR		 1083 if (regs->len > R8169_REGS_SIZE)
1084 regs->len = R8169_REGS_SIZE;
1da177e4 1085
5b0384f4
FR		 1086 spin_lock_irqsave(&tp->lock, flags);
1087 memcpy_fromio(p, tp->mmio_addr, regs->len);
1088 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1089}
1090
b57b7e5a
SH		 1091static u32 rtl8169_get_msglevel(struct net_device *dev)
1092{
1093 struct rtl8169_private *tp = netdev_priv(dev);
1094
1095 return tp->msg_enable;
1096}
1097
1098static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1099{
1100 struct rtl8169_private *tp = netdev_priv(dev);
1101
1102 tp->msg_enable = value;
1103}
1104
d4a3a0fc
SH		 1105static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1106 "tx_packets",
1107 "rx_packets",
1108 "tx_errors",
1109 "rx_errors",
1110 "rx_missed",
1111 "align_errors",
1112 "tx_single_collisions",
1113 "tx_multi_collisions",
1114 "unicast",
1115 "broadcast",
1116 "multicast",
1117 "tx_aborted",
1118 "tx_underrun",
1119};
1120
b9f2c044 1121static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1122{
b9f2c044
JG		 1123 switch (sset) {
1124 case ETH_SS_STATS:
1125 return ARRAY_SIZE(rtl8169_gstrings);
1126 default:
1127 return -EOPNOTSUPP;
1128 }
d4a3a0fc
SH		 1129}
1130
355423d0 1131static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1132{
1133 struct rtl8169_private *tp = netdev_priv(dev);
1134 void __iomem *ioaddr = tp->mmio_addr;
1135 struct rtl8169_counters *counters;
1136 dma_addr_t paddr;
1137 u32 cmd;
355423d0 1138 int wait = 1000;
d4a3a0fc 1139
355423d0
IV		 1140 /*
1141 * Some chips are unable to dump tally counters when the receiver
1142 * is disabled.
1143 */
1144 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1145 return;
d4a3a0fc
SH		 1146
1147 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1148 if (!counters)
1149 return;
1150
1151 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1152 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1153 RTL_W32(CounterAddrLow, cmd);
1154 RTL_W32(CounterAddrLow, cmd | CounterDump);
1155
355423d0
IV		 1156 while (wait--) {
1157 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1158 /* copy updated counters */
1159 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1160 break;
355423d0
IV		 1161 }
1162 udelay(10);
d4a3a0fc
SH		 1163 }
1164
1165 RTL_W32(CounterAddrLow, 0);
1166 RTL_W32(CounterAddrHigh, 0);
1167
d4a3a0fc
SH		 1168 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1169}
1170
355423d0
IV		 1171static void rtl8169_get_ethtool_stats(struct net_device *dev,
1172 struct ethtool_stats *stats, u64 *data)
1173{
1174 struct rtl8169_private *tp = netdev_priv(dev);
1175
1176 ASSERT_RTNL();
1177
1178 rtl8169_update_counters(dev);
1179
1180 data[0] = le64_to_cpu(tp->counters.tx_packets);
1181 data[1] = le64_to_cpu(tp->counters.rx_packets);
1182 data[2] = le64_to_cpu(tp->counters.tx_errors);
1183 data[3] = le32_to_cpu(tp->counters.rx_errors);
1184 data[4] = le16_to_cpu(tp->counters.rx_missed);
1185 data[5] = le16_to_cpu(tp->counters.align_errors);
1186 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1187 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1188 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1189 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1190 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1191 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1192 data[12] = le16_to_cpu(tp->counters.tx_underun);
1193}
1194
d4a3a0fc
SH		 1195static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1196{
1197 switch(stringset) {
1198 case ETH_SS_STATS:
1199 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1200 break;
1201 }
1202}
1203
7282d491 1204static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1205 .get_drvinfo = rtl8169_get_drvinfo,
1206 .get_regs_len = rtl8169_get_regs_len,
1207 .get_link = ethtool_op_get_link,
1208 .get_settings = rtl8169_get_settings,
1209 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1210 .get_msglevel = rtl8169_get_msglevel,
1211 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1212 .get_rx_csum = rtl8169_get_rx_csum,
1213 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1214 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1215 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1216 .set_tso = ethtool_op_set_tso,
1217 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1218 .get_wol = rtl8169_get_wol,
1219 .set_wol = rtl8169_set_wol,
d4a3a0fc 1220 .get_strings = rtl8169_get_strings,
b9f2c044 1221 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1222 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1223};
1224
07d3f51f
FR		 1225static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1226 void __iomem *ioaddr)
1da177e4 1227{
0e485150
FR		 1228 /*
1229 * The driver currently handles the 8168Bf and the 8168Be identically
1230 * but they can be identified more specifically through the test below
1231 * if needed:
1232 *
1233 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1234 *
1235 * Same thing for the 8101Eb and the 8101Ec:
1236 *
1237 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1238 */
1da177e4
LT		 1239 const struct {
1240 u32 mask;
e3cf0cc0 1241 u32 val;
1da177e4
LT		 1242 int mac_version;
1243 } mac_info[] = {
5b538df9
FR		 1244 /* 8168D family. */
1245 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1246
ef808d50 1247 /* 8168C family. */
7f3e3d3a 1248 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1249 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1250 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1251 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1252 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1253 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1254 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1255 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1256 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1257
1258 /* 8168B family. */
1259 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1260 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1261 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1262 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1263
1264 /* 8101 family. */
2857ffb7
FR		 1265 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1266 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1267 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1268 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1269 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1270 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1271 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1272 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1273 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1274 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1275 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1276 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1277 /* FIXME: where did these entries come from ? -- FR */
1278 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1279 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1280
1281 /* 8110 family. */
1282 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1283 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1284 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1285 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1286 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1287 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1288
f21b75e9
JD		 1289 /* Catch-all */
1290 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1291 }, *p = mac_info;
1292 u32 reg;
1293
e3cf0cc0
FR		 1294 reg = RTL_R32(TxConfig);
1295 while ((reg & p->mask) != p->val)
1da177e4
LT		 1296 p++;
1297 tp->mac_version = p->mac_version;
1298}
1299
1300static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1301{
bcf0bf90 1302 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1303}
1304
867763c1
FR		 1305struct phy_reg {
1306 u16 reg;
1307 u16 val;
1308};
1309
1310static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1311{
1312 while (len-- > 0) {
1313 mdio_write(ioaddr, regs->reg, regs->val);
1314 regs++;
1315 }
1316}
1317
5615d9f1 1318static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1319{
0b9b571d 1320 struct phy_reg phy_reg_init[] = {
1321 { 0x1f, 0x0001 },
1322 { 0x06, 0x006e },
1323 { 0x08, 0x0708 },
1324 { 0x15, 0x4000 },
1325 { 0x18, 0x65c7 },
1da177e4 1326
0b9b571d 1327 { 0x1f, 0x0001 },
1328 { 0x03, 0x00a1 },
1329 { 0x02, 0x0008 },
1330 { 0x01, 0x0120 },
1331 { 0x00, 0x1000 },
1332 { 0x04, 0x0800 },
1333 { 0x04, 0x0000 },
1da177e4 1334
0b9b571d 1335 { 0x03, 0xff41 },
1336 { 0x02, 0xdf60 },
1337 { 0x01, 0x0140 },
1338 { 0x00, 0x0077 },
1339 { 0x04, 0x7800 },
1340 { 0x04, 0x7000 },
1341
1342 { 0x03, 0x802f },
1343 { 0x02, 0x4f02 },
1344 { 0x01, 0x0409 },
1345 { 0x00, 0xf0f9 },
1346 { 0x04, 0x9800 },
1347 { 0x04, 0x9000 },
1348
1349 { 0x03, 0xdf01 },
1350 { 0x02, 0xdf20 },
1351 { 0x01, 0xff95 },
1352 { 0x00, 0xba00 },
1353 { 0x04, 0xa800 },
1354 { 0x04, 0xa000 },
1355
1356 { 0x03, 0xff41 },
1357 { 0x02, 0xdf20 },
1358 { 0x01, 0x0140 },
1359 { 0x00, 0x00bb },
1360 { 0x04, 0xb800 },
1361 { 0x04, 0xb000 },
1362
1363 { 0x03, 0xdf41 },
1364 { 0x02, 0xdc60 },
1365 { 0x01, 0x6340 },
1366 { 0x00, 0x007d },
1367 { 0x04, 0xd800 },
1368 { 0x04, 0xd000 },
1369
1370 { 0x03, 0xdf01 },
1371 { 0x02, 0xdf20 },
1372 { 0x01, 0x100a },
1373 { 0x00, 0xa0ff },
1374 { 0x04, 0xf800 },
1375 { 0x04, 0xf000 },
1376
1377 { 0x1f, 0x0000 },
1378 { 0x0b, 0x0000 },
1379 { 0x00, 0x9200 }
1380 };
1da177e4 1381
0b9b571d 1382 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1383}
1384
5615d9f1
FR		 1385static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1386{
a441d7b6
FR		 1387 struct phy_reg phy_reg_init[] = {
1388 { 0x1f, 0x0002 },
1389 { 0x01, 0x90d0 },
1390 { 0x1f, 0x0000 }
1391 };
1392
1393 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1394}
1395
2e955856 1396static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1397 void __iomem *ioaddr)
1398{
1399 struct pci_dev *pdev = tp->pci_dev;
1400 u16 vendor_id, device_id;
1401
1402 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1403 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1404
1405 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1406 return;
1407
1408 mdio_write(ioaddr, 0x1f, 0x0001);
1409 mdio_write(ioaddr, 0x10, 0xf01b);
1410 mdio_write(ioaddr, 0x1f, 0x0000);
1411}
1412
1413static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1414 void __iomem *ioaddr)
1415{
1416 struct phy_reg phy_reg_init[] = {
1417 { 0x1f, 0x0001 },
1418 { 0x04, 0x0000 },
1419 { 0x03, 0x00a1 },
1420 { 0x02, 0x0008 },
1421 { 0x01, 0x0120 },
1422 { 0x00, 0x1000 },
1423 { 0x04, 0x0800 },
1424 { 0x04, 0x9000 },
1425 { 0x03, 0x802f },
1426 { 0x02, 0x4f02 },
1427 { 0x01, 0x0409 },
1428 { 0x00, 0xf099 },
1429 { 0x04, 0x9800 },
1430 { 0x04, 0xa000 },
1431 { 0x03, 0xdf01 },
1432 { 0x02, 0xdf20 },
1433 { 0x01, 0xff95 },
1434 { 0x00, 0xba00 },
1435 { 0x04, 0xa800 },
1436 { 0x04, 0xf000 },
1437 { 0x03, 0xdf01 },
1438 { 0x02, 0xdf20 },
1439 { 0x01, 0x101a },
1440 { 0x00, 0xa0ff },
1441 { 0x04, 0xf800 },
1442 { 0x04, 0x0000 },
1443 { 0x1f, 0x0000 },
1444
1445 { 0x1f, 0x0001 },
1446 { 0x10, 0xf41b },
1447 { 0x14, 0xfb54 },
1448 { 0x18, 0xf5c7 },
1449 { 0x1f, 0x0000 },
1450
1451 { 0x1f, 0x0001 },
1452 { 0x17, 0x0cc0 },
1453 { 0x1f, 0x0000 }
1454 };
1455
1456 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1457
1458 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1459}
1460
8c7006aa 1461static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1462{
1463 struct phy_reg phy_reg_init[] = {
1464 { 0x1f, 0x0001 },
1465 { 0x04, 0x0000 },
1466 { 0x03, 0x00a1 },
1467 { 0x02, 0x0008 },
1468 { 0x01, 0x0120 },
1469 { 0x00, 0x1000 },
1470 { 0x04, 0x0800 },
1471 { 0x04, 0x9000 },
1472 { 0x03, 0x802f },
1473 { 0x02, 0x4f02 },
1474 { 0x01, 0x0409 },
1475 { 0x00, 0xf099 },
1476 { 0x04, 0x9800 },
1477 { 0x04, 0xa000 },
1478 { 0x03, 0xdf01 },
1479 { 0x02, 0xdf20 },
1480 { 0x01, 0xff95 },
1481 { 0x00, 0xba00 },
1482 { 0x04, 0xa800 },
1483 { 0x04, 0xf000 },
1484 { 0x03, 0xdf01 },
1485 { 0x02, 0xdf20 },
1486 { 0x01, 0x101a },
1487 { 0x00, 0xa0ff },
1488 { 0x04, 0xf800 },
1489 { 0x04, 0x0000 },
1490 { 0x1f, 0x0000 },
1491
1492 { 0x1f, 0x0001 },
1493 { 0x0b, 0x8480 },
1494 { 0x1f, 0x0000 },
1495
1496 { 0x1f, 0x0001 },
1497 { 0x18, 0x67c7 },
1498 { 0x04, 0x2000 },
1499 { 0x03, 0x002f },
1500 { 0x02, 0x4360 },
1501 { 0x01, 0x0109 },
1502 { 0x00, 0x3022 },
1503 { 0x04, 0x2800 },
1504 { 0x1f, 0x0000 },
1505
1506 { 0x1f, 0x0001 },
1507 { 0x17, 0x0cc0 },
1508 { 0x1f, 0x0000 }
1509 };
1510
1511 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1512}
1513
236b8082
FR		 1514static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1515{
1516 struct phy_reg phy_reg_init[] = {
1517 { 0x10, 0xf41b },
1518 { 0x1f, 0x0000 }
1519 };
1520
1521 mdio_write(ioaddr, 0x1f, 0x0001);
1522 mdio_patch(ioaddr, 0x16, 1 << 0);
1523
1524 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1525}
1526
1527static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1528{
1529 struct phy_reg phy_reg_init[] = {
1530 { 0x1f, 0x0001 },
1531 { 0x10, 0xf41b },
1532 { 0x1f, 0x0000 }
1533 };
1534
1535 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1536}
1537
ef3386f0 1538static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1539{
1540 struct phy_reg phy_reg_init[] = {
1541 { 0x1f, 0x0000 },
1542 { 0x1d, 0x0f00 },
1543 { 0x1f, 0x0002 },
1544 { 0x0c, 0x1ec8 },
1545 { 0x1f, 0x0000 }
1546 };
1547
1548 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1549}
1550
ef3386f0
FR		 1551static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1552{
1553 struct phy_reg phy_reg_init[] = {
1554 { 0x1f, 0x0001 },
1555 { 0x1d, 0x3d98 },
1556 { 0x1f, 0x0000 }
1557 };
1558
1559 mdio_write(ioaddr, 0x1f, 0x0000);
1560 mdio_patch(ioaddr, 0x14, 1 << 5);
1561 mdio_patch(ioaddr, 0x0d, 1 << 5);
1562
1563 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1564}
1565
219a1e9d 1566static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1567{
1568 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1569 { 0x1f, 0x0001 },
1570 { 0x12, 0x2300 },
867763c1
FR		 1571 { 0x1f, 0x0002 },
1572 { 0x00, 0x88d4 },
1573 { 0x01, 0x82b1 },
1574 { 0x03, 0x7002 },
1575 { 0x08, 0x9e30 },
1576 { 0x09, 0x01f0 },
1577 { 0x0a, 0x5500 },
1578 { 0x0c, 0x00c8 },
1579 { 0x1f, 0x0003 },
1580 { 0x12, 0xc096 },
1581 { 0x16, 0x000a },
f50d4275
FR		 1582 { 0x1f, 0x0000 },
1583 { 0x1f, 0x0000 },
1584 { 0x09, 0x2000 },
1585 { 0x09, 0x0000 }
867763c1
FR		 1586 };
1587
1588 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1589
1590 mdio_patch(ioaddr, 0x14, 1 << 5);
1591 mdio_patch(ioaddr, 0x0d, 1 << 5);
1592 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1593}
1594
219a1e9d 1595static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1596{
1597 struct phy_reg phy_reg_init[] = {
f50d4275 1598 { 0x1f, 0x0001 },
7da97ec9 1599 { 0x12, 0x2300 },
f50d4275
FR		 1600 { 0x03, 0x802f },
1601 { 0x02, 0x4f02 },
1602 { 0x01, 0x0409 },
1603 { 0x00, 0xf099 },
1604 { 0x04, 0x9800 },
1605 { 0x04, 0x9000 },
1606 { 0x1d, 0x3d98 },
7da97ec9
FR		 1607 { 0x1f, 0x0002 },
1608 { 0x0c, 0x7eb8 },
f50d4275
FR		 1609 { 0x06, 0x0761 },
1610 { 0x1f, 0x0003 },
1611 { 0x16, 0x0f0a },
7da97ec9
FR		 1612 { 0x1f, 0x0000 }
1613 };
1614
1615 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1616
1617 mdio_patch(ioaddr, 0x16, 1 << 0);
1618 mdio_patch(ioaddr, 0x14, 1 << 5);
1619 mdio_patch(ioaddr, 0x0d, 1 << 5);
1620 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1621}
1622
197ff761
FR		 1623static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1624{
1625 struct phy_reg phy_reg_init[] = {
1626 { 0x1f, 0x0001 },
1627 { 0x12, 0x2300 },
1628 { 0x1d, 0x3d98 },
1629 { 0x1f, 0x0002 },
1630 { 0x0c, 0x7eb8 },
1631 { 0x06, 0x5461 },
1632 { 0x1f, 0x0003 },
1633 { 0x16, 0x0f0a },
1634 { 0x1f, 0x0000 }
1635 };
1636
1637 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1638
1639 mdio_patch(ioaddr, 0x16, 1 << 0);
1640 mdio_patch(ioaddr, 0x14, 1 << 5);
1641 mdio_patch(ioaddr, 0x0d, 1 << 5);
1642 mdio_write(ioaddr, 0x1f, 0x0000);
1643}
1644
6fb07058
FR		 1645static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1646{
1647 rtl8168c_3_hw_phy_config(ioaddr);
1648}
1649
5b538df9
FR		 1650static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1651{
1652 struct phy_reg phy_reg_init_0[] = {
1653 { 0x1f, 0x0001 },
1654 { 0x09, 0x2770 },
1655 { 0x08, 0x04d0 },
1656 { 0x0b, 0xad15 },
1657 { 0x0c, 0x5bf0 },
1658 { 0x1c, 0xf101 },
1659 { 0x1f, 0x0003 },
1660 { 0x14, 0x94d7 },
1661 { 0x12, 0xf4d6 },
1662 { 0x09, 0xca0f },
1663 { 0x1f, 0x0002 },
1664 { 0x0b, 0x0b10 },
1665 { 0x0c, 0xd1f7 },
1666 { 0x1f, 0x0002 },
1667 { 0x06, 0x5461 },
1668 { 0x1f, 0x0002 },
1669 { 0x05, 0x6662 },
1670 { 0x1f, 0x0000 },
1671 { 0x14, 0x0060 },
1672 { 0x1f, 0x0000 },
1673 { 0x0d, 0xf8a0 },
1674 { 0x1f, 0x0005 },
1675 { 0x05, 0xffc2 }
1676 };
1677
1678 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1679
1680 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1681 struct phy_reg phy_reg_init_1[] = {
1682 { 0x1f, 0x0005 },
1683 { 0x01, 0x0300 },
1684 { 0x1f, 0x0000 },
1685 { 0x11, 0x401c },
1686 { 0x16, 0x4100 },
1687 { 0x1f, 0x0005 },
1688 { 0x07, 0x0010 },
1689 { 0x05, 0x83dc },
1690 { 0x06, 0x087d },
1691 { 0x05, 0x8300 },
1692 { 0x06, 0x0101 },
1693 { 0x06, 0x05f8 },
1694 { 0x06, 0xf9fa },
1695 { 0x06, 0xfbef },
1696 { 0x06, 0x79e2 },
1697 { 0x06, 0x835f },
1698 { 0x06, 0xe0f8 },
1699 { 0x06, 0x9ae1 },
1700 { 0x06, 0xf89b },
1701 { 0x06, 0xef31 },
1702 { 0x06, 0x3b65 },
1703 { 0x06, 0xaa07 },
1704 { 0x06, 0x81e4 },
1705 { 0x06, 0xf89a },
1706 { 0x06, 0xe5f8 },
1707 { 0x06, 0x9baf },
1708 { 0x06, 0x06ae },
1709 { 0x05, 0x83dc },
1710 { 0x06, 0x8300 },
1711 };
1712
1713 rtl_phy_write(ioaddr, phy_reg_init_1,
1714 ARRAY_SIZE(phy_reg_init_1));
1715 }
1716
1717 mdio_write(ioaddr, 0x1f, 0x0000);
1718}
1719
2857ffb7
FR		 1720static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1721{
1722 struct phy_reg phy_reg_init[] = {
1723 { 0x1f, 0x0003 },
1724 { 0x08, 0x441d },
1725 { 0x01, 0x9100 },
1726 { 0x1f, 0x0000 }
1727 };
1728
1729 mdio_write(ioaddr, 0x1f, 0x0000);
1730 mdio_patch(ioaddr, 0x11, 1 << 12);
1731 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 1732 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 1733
1734 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1735}
1736
5615d9f1
FR		 1737static void rtl_hw_phy_config(struct net_device *dev)
1738{
1739 struct rtl8169_private *tp = netdev_priv(dev);
1740 void __iomem *ioaddr = tp->mmio_addr;
1741
1742 rtl8169_print_mac_version(tp);
1743
1744 switch (tp->mac_version) {
1745 case RTL_GIGA_MAC_VER_01:
1746 break;
1747 case RTL_GIGA_MAC_VER_02:
1748 case RTL_GIGA_MAC_VER_03:
1749 rtl8169s_hw_phy_config(ioaddr);
1750 break;
1751 case RTL_GIGA_MAC_VER_04:
1752 rtl8169sb_hw_phy_config(ioaddr);
1753 break;
2e955856 1754 case RTL_GIGA_MAC_VER_05:
1755 rtl8169scd_hw_phy_config(tp, ioaddr);
1756 break;
8c7006aa 1757 case RTL_GIGA_MAC_VER_06:
1758 rtl8169sce_hw_phy_config(ioaddr);
1759 break;
2857ffb7
FR		 1760 case RTL_GIGA_MAC_VER_07:
1761 case RTL_GIGA_MAC_VER_08:
1762 case RTL_GIGA_MAC_VER_09:
1763 rtl8102e_hw_phy_config(ioaddr);
1764 break;
236b8082
FR		 1765 case RTL_GIGA_MAC_VER_11:
1766 rtl8168bb_hw_phy_config(ioaddr);
1767 break;
1768 case RTL_GIGA_MAC_VER_12:
1769 rtl8168bef_hw_phy_config(ioaddr);
1770 break;
1771 case RTL_GIGA_MAC_VER_17:
1772 rtl8168bef_hw_phy_config(ioaddr);
1773 break;
867763c1 1774 case RTL_GIGA_MAC_VER_18:
ef3386f0 1775 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1776 break;
1777 case RTL_GIGA_MAC_VER_19:
219a1e9d 1778 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1779 break;
7da97ec9 1780 case RTL_GIGA_MAC_VER_20:
219a1e9d 1781 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1782 break;
197ff761
FR		 1783 case RTL_GIGA_MAC_VER_21:
1784 rtl8168c_3_hw_phy_config(ioaddr);
1785 break;
6fb07058
FR		 1786 case RTL_GIGA_MAC_VER_22:
1787 rtl8168c_4_hw_phy_config(ioaddr);
1788 break;
ef3386f0 1789 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 1790 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 1791 rtl8168cp_2_hw_phy_config(ioaddr);
1792 break;
5b538df9
FR		 1793 case RTL_GIGA_MAC_VER_25:
1794 rtl8168d_hw_phy_config(ioaddr);
1795 break;
ef3386f0 1796
5615d9f1
FR		 1797 default:
1798 break;
1799 }
1800}
1801
1da177e4
LT		 1802static void rtl8169_phy_timer(unsigned long __opaque)
1803{
1804 struct net_device *dev = (struct net_device *)__opaque;
1805 struct rtl8169_private *tp = netdev_priv(dev);
1806 struct timer_list *timer = &tp->timer;
1807 void __iomem *ioaddr = tp->mmio_addr;
1808 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1809
bcf0bf90 1810 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1811
64e4bfb4 1812 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1813 return;
1814
1815 spin_lock_irq(&tp->lock);
1816
1817 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1818 /*
1da177e4
LT		 1819 * A busy loop could burn quite a few cycles on nowadays CPU.
1820 * Let's delay the execution of the timer for a few ticks.
1821 */
1822 timeout = HZ/10;
1823 goto out_mod_timer;
1824 }
1825
1826 if (tp->link_ok(ioaddr))
1827 goto out_unlock;
1828
b57b7e5a
SH		 1829 if (netif_msg_link(tp))
1830 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1831
1832 tp->phy_reset_enable(ioaddr);
1833
1834out_mod_timer:
1835 mod_timer(timer, jiffies + timeout);
1836out_unlock:
1837 spin_unlock_irq(&tp->lock);
1838}
1839
1840static inline void rtl8169_delete_timer(struct net_device *dev)
1841{
1842 struct rtl8169_private *tp = netdev_priv(dev);
1843 struct timer_list *timer = &tp->timer;
1844
e179bb7b 1845 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1846 return;
1847
1848 del_timer_sync(timer);
1849}
1850
1851static inline void rtl8169_request_timer(struct net_device *dev)
1852{
1853 struct rtl8169_private *tp = netdev_priv(dev);
1854 struct timer_list *timer = &tp->timer;
1855
e179bb7b 1856 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1857 return;
1858
2efa53f3 1859 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1860}
1861
1862#ifdef CONFIG_NET_POLL_CONTROLLER
1863/*
1864 * Polling 'interrupt' - used by things like netconsole to send skbs
1865 * without having to re-enable interrupts. It's not called while
1866 * the interrupt routine is executing.
1867 */
1868static void rtl8169_netpoll(struct net_device *dev)
1869{
1870 struct rtl8169_private *tp = netdev_priv(dev);
1871 struct pci_dev *pdev = tp->pci_dev;
1872
1873 disable_irq(pdev->irq);
7d12e780 1874 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1875 enable_irq(pdev->irq);
1876}
1877#endif
1878
1879static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1880 void __iomem *ioaddr)
1881{
1882 iounmap(ioaddr);
1883 pci_release_regions(pdev);
1884 pci_disable_device(pdev);
1885 free_netdev(dev);
1886}
1887
bf793295
FR		 1888static void rtl8169_phy_reset(struct net_device *dev,
1889 struct rtl8169_private *tp)
1890{
1891 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1892 unsigned int i;
bf793295
FR		 1893
1894 tp->phy_reset_enable(ioaddr);
1895 for (i = 0; i < 100; i++) {
1896 if (!tp->phy_reset_pending(ioaddr))
1897 return;
1898 msleep(1);
1899 }
1900 if (netif_msg_link(tp))
1901 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1902}
1903
4ff96fa6
FR		 1904static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1905{
1906 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1907
5615d9f1 1908 rtl_hw_phy_config(dev);
4ff96fa6 1909
77332894
MS		 1910 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1911 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1912 RTL_W8(0x82, 0x01);
1913 }
4ff96fa6 1914
6dccd16b
FR		 1915 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1916
1917 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1918 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1919
bcf0bf90 1920 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1921 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1922 RTL_W8(0x82, 0x01);
1923 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1924 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1925 }
1926
bf793295
FR		 1927 rtl8169_phy_reset(dev, tp);
1928
901dda2b
FR		 1929 /*
1930 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1931 * only 8101. Don't panic.
1932 */
1933 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1934
1935 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1936 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1937}
1938
773d2021
FR		 1939static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1940{
1941 void __iomem *ioaddr = tp->mmio_addr;
1942 u32 high;
1943 u32 low;
1944
1945 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1946 high = addr[4] | (addr[5] << 8);
1947
1948 spin_lock_irq(&tp->lock);
1949
1950 RTL_W8(Cfg9346, Cfg9346_Unlock);
1951 RTL_W32(MAC0, low);
1952 RTL_W32(MAC4, high);
1953 RTL_W8(Cfg9346, Cfg9346_Lock);
1954
1955 spin_unlock_irq(&tp->lock);
1956}
1957
1958static int rtl_set_mac_address(struct net_device *dev, void *p)
1959{
1960 struct rtl8169_private *tp = netdev_priv(dev);
1961 struct sockaddr *addr = p;
1962
1963 if (!is_valid_ether_addr(addr->sa_data))
1964 return -EADDRNOTAVAIL;
1965
1966 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1967
1968 rtl_rar_set(tp, dev->dev_addr);
1969
1970 return 0;
1971}
1972
5f787a1a
FR		 1973static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1974{
1975 struct rtl8169_private *tp = netdev_priv(dev);
1976 struct mii_ioctl_data *data = if_mii(ifr);
1977
8b4ab28d
FR		 1978 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1979}
5f787a1a 1980
8b4ab28d
FR		 1981static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1982{
5f787a1a
FR		 1983 switch (cmd) {
1984 case SIOCGMIIPHY:
1985 data->phy_id = 32; /* Internal PHY */
1986 return 0;
1987
1988 case SIOCGMIIREG:
1989 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1990 return 0;
1991
1992 case SIOCSMIIREG:
1993 if (!capable(CAP_NET_ADMIN))
1994 return -EPERM;
1995 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1996 return 0;
1997 }
1998 return -EOPNOTSUPP;
1999}
2000
8b4ab28d
FR		 2001static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2002{
2003 return -EOPNOTSUPP;
2004}
2005
0e485150
FR		 2006static const struct rtl_cfg_info {
2007 void (*hw_start)(struct net_device *);
2008 unsigned int region;
2009 unsigned int align;
2010 u16 intr_event;
2011 u16 napi_event;
ccdffb9a 2012 unsigned features;
f21b75e9 2013 u8 default_ver;
0e485150
FR		 2014} rtl_cfg_infos [] = {
2015 [RTL_CFG_0] = {
2016 .hw_start = rtl_hw_start_8169,
2017 .region = 1,
e9f63f30 2018 .align = 0,
0e485150
FR		 2019 .intr_event = SYSErr | LinkChg | RxOverflow |
2020 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2021 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2022 .features = RTL_FEATURE_GMII,
2023 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2024 },
2025 [RTL_CFG_1] = {
2026 .hw_start = rtl_hw_start_8168,
2027 .region = 2,
2028 .align = 8,
2029 .intr_event = SYSErr | LinkChg | RxOverflow |
2030 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2031 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2032 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2033 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2034 },
2035 [RTL_CFG_2] = {
2036 .hw_start = rtl_hw_start_8101,
2037 .region = 2,
2038 .align = 8,
2039 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2040 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2041 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2042 .features = RTL_FEATURE_MSI,
2043 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2044 }
2045};
2046
fbac58fc
FR		 2047/* Cfg9346_Unlock assumed. */
2048static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2049 const struct rtl_cfg_info *cfg)
2050{
2051 unsigned msi = 0;
2052 u8 cfg2;
2053
2054 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2055 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2056 if (pci_enable_msi(pdev)) {
2057 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2058 } else {
2059 cfg2 |= MSIEnable;
2060 msi = RTL_FEATURE_MSI;
2061 }
2062 }
2063 RTL_W8(Config2, cfg2);
2064 return msi;
2065}
2066
2067static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2068{
2069 if (tp->features & RTL_FEATURE_MSI) {
2070 pci_disable_msi(pdev);
2071 tp->features &= ~RTL_FEATURE_MSI;
2072 }
2073}
2074
8b4ab28d
FR		 2075static const struct net_device_ops rtl8169_netdev_ops = {
2076 .ndo_open = rtl8169_open,
2077 .ndo_stop = rtl8169_close,
2078 .ndo_get_stats = rtl8169_get_stats,
00829823 2079 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2080 .ndo_tx_timeout = rtl8169_tx_timeout,
2081 .ndo_validate_addr = eth_validate_addr,
2082 .ndo_change_mtu = rtl8169_change_mtu,
2083 .ndo_set_mac_address = rtl_set_mac_address,
2084 .ndo_do_ioctl = rtl8169_ioctl,
2085 .ndo_set_multicast_list = rtl_set_rx_mode,
2086#ifdef CONFIG_R8169_VLAN
2087 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2088#endif
2089#ifdef CONFIG_NET_POLL_CONTROLLER
2090 .ndo_poll_controller = rtl8169_netpoll,
2091#endif
2092
2093};
2094
1da177e4 2095static int __devinit
4ff96fa6 2096rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2097{
0e485150
FR		 2098 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2099 const unsigned int region = cfg->region;
1da177e4 2100 struct rtl8169_private *tp;
ccdffb9a 2101 struct mii_if_info *mii;
4ff96fa6
FR		 2102 struct net_device *dev;
2103 void __iomem *ioaddr;
07d3f51f
FR		 2104 unsigned int i;
2105 int rc;
1da177e4 2106
4ff96fa6
FR		 2107 if (netif_msg_drv(&debug)) {
2108 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2109 MODULENAME, RTL8169_VERSION);
2110 }
1da177e4 2111
1da177e4 2112 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2113 if (!dev) {
b57b7e5a 2114 if (netif_msg_drv(&debug))
9b91cf9d 2115 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2116 rc = -ENOMEM;
2117 goto out;
1da177e4
LT		 2118 }
2119
1da177e4 2120 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2121 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2122 tp = netdev_priv(dev);
c4028958 2123 tp->dev = dev;
21e197f2 2124 tp->pci_dev = pdev;
b57b7e5a 2125 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2126
ccdffb9a
FR		 2127 mii = &tp->mii;
2128 mii->dev = dev;
2129 mii->mdio_read = rtl_mdio_read;
2130 mii->mdio_write = rtl_mdio_write;
2131 mii->phy_id_mask = 0x1f;
2132 mii->reg_num_mask = 0x1f;
2133 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2134
1da177e4
LT		 2135 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2136 rc = pci_enable_device(pdev);
b57b7e5a 2137 if (rc < 0) {
2e8a538d 2138 if (netif_msg_probe(tp))
9b91cf9d 2139 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 2140 goto err_out_free_dev_1;
1da177e4
LT		 2141 }
2142
2143 rc = pci_set_mwi(pdev);
2144 if (rc < 0)
4ff96fa6 2145 goto err_out_disable_2;
1da177e4 2146
1da177e4 2147 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2148 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 2149 if (netif_msg_probe(tp)) {
9b91cf9d 2150 dev_err(&pdev->dev,
bcf0bf90
FR		 2151 "region #%d not an MMIO resource, aborting\n",
2152 region);
4ff96fa6 2153 }
1da177e4 2154 rc = -ENODEV;
4ff96fa6 2155 goto err_out_mwi_3;
1da177e4 2156 }
4ff96fa6 2157
1da177e4 2158 /* check for weird/broken PCI region reporting */
bcf0bf90 2159 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 2160 if (netif_msg_probe(tp)) {
9b91cf9d 2161 dev_err(&pdev->dev,
4ff96fa6
FR		 2162 "Invalid PCI region size(s), aborting\n");
2163 }
1da177e4 2164 rc = -ENODEV;
4ff96fa6 2165 goto err_out_mwi_3;
1da177e4
LT		 2166 }
2167
2168 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2169 if (rc < 0) {
2e8a538d 2170 if (netif_msg_probe(tp))
9b91cf9d 2171 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 2172 goto err_out_mwi_3;
1da177e4
LT		 2173 }
2174
2175 tp->cp_cmd = PCIMulRW | RxChkSum;
2176
2177 if ((sizeof(dma_addr_t) > 4) &&
6a35528a 2178 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2179 tp->cp_cmd |= PCIDAC;
2180 dev->features |= NETIF_F_HIGHDMA;
2181 } else {
284901a9 2182 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2183 if (rc < 0) {
4ff96fa6 2184 if (netif_msg_probe(tp)) {
9b91cf9d 2185 dev_err(&pdev->dev,
4ff96fa6
FR		 2186 "DMA configuration failed.\n");
2187 }
2188 goto err_out_free_res_4;
1da177e4
LT		 2189 }
2190 }
2191
1da177e4 2192 /* ioremap MMIO region */
bcf0bf90 2193 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2194 if (!ioaddr) {
b57b7e5a 2195 if (netif_msg_probe(tp))
9b91cf9d 2196 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2197 rc = -EIO;
4ff96fa6 2198 goto err_out_free_res_4;
1da177e4
LT		 2199 }
2200
9c14ceaf
FR		 2201 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2202 if (!tp->pcie_cap && netif_msg_probe(tp))
2203 dev_info(&pdev->dev, "no PCI Express capability\n");
2204
d78ad8cb 2205 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2206
2207 /* Soft reset the chip. */
2208 RTL_W8(ChipCmd, CmdReset);
2209
2210 /* Check that the chip has finished the reset. */
07d3f51f 2211 for (i = 0; i < 100; i++) {
1da177e4
LT		 2212 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2213 break;
b518fa8e 2214 msleep_interruptible(1);
1da177e4
LT		 2215 }
2216
d78ad8cb
KW		 2217 RTL_W16(IntrStatus, 0xffff);
2218
ca52efd5 2219 pci_set_master(pdev);
2220
1da177e4
LT		 2221 /* Identify chip attached to board */
2222 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 2223
f21b75e9
JD		 2224 /* Use appropriate default if unknown */
2225 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2226 if (netif_msg_probe(tp)) {
2227 dev_notice(&pdev->dev,
2228 "unknown MAC, using family default\n");
2229 }
2230 tp->mac_version = cfg->default_ver;
2231 }
2232
1da177e4 2233 rtl8169_print_mac_version(tp);
1da177e4 2234
cee60c37 2235 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2236 if (tp->mac_version == rtl_chip_info[i].mac_version)
2237 break;
2238 }
cee60c37 2239 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 2240 dev_err(&pdev->dev,
2241 "driver bug, MAC version not found in rtl_chip_info\n");
2242 goto err_out_msi_5;
1da177e4
LT		 2243 }
2244 tp->chipset = i;
2245
5d06a99f
FR		 2246 RTL_W8(Cfg9346, Cfg9346_Unlock);
2247 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2248 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2249 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2250 tp->features |= RTL_FEATURE_WOL;
2251 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2252 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2253 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2254 RTL_W8(Cfg9346, Cfg9346_Lock);
2255
66ec5d4f
FR		 2256 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2257 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2258 tp->set_speed = rtl8169_set_speed_tbi;
2259 tp->get_settings = rtl8169_gset_tbi;
2260 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2261 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2262 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2263 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2264
64e4bfb4 2265 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2266 } else {
2267 tp->set_speed = rtl8169_set_speed_xmii;
2268 tp->get_settings = rtl8169_gset_xmii;
2269 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2270 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2271 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2272 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2273 }
2274
df58ef51
FR		 2275 spin_lock_init(&tp->lock);
2276
738e1e69
PV		 2277 tp->mmio_addr = ioaddr;
2278
7bf6bf48 2279 /* Get MAC address */
1da177e4
LT		 2280 for (i = 0; i < MAC_ADDR_LEN; i++)
2281 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2282 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2283
1da177e4 2284 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2285 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2286 dev->irq = pdev->irq;
2287 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2288
bea3348e 2289 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2290
2291#ifdef CONFIG_R8169_VLAN
2292 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 2293#endif
2294
2295 tp->intr_mask = 0xffff;
0e485150
FR		 2296 tp->align = cfg->align;
2297 tp->hw_start = cfg->hw_start;
2298 tp->intr_event = cfg->intr_event;
2299 tp->napi_event = cfg->napi_event;
1da177e4 2300
2efa53f3
FR		 2301 init_timer(&tp->timer);
2302 tp->timer.data = (unsigned long) dev;
2303 tp->timer.function = rtl8169_phy_timer;
2304
1da177e4 2305 rc = register_netdev(dev);
4ff96fa6 2306 if (rc < 0)
fbac58fc 2307 goto err_out_msi_5;
1da177e4
LT		 2308
2309 pci_set_drvdata(pdev, dev);
2310
b57b7e5a 2311 if (netif_msg_probe(tp)) {
21d57363 2312 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
96b9709c 2313
b57b7e5a
SH		 2314 printk(KERN_INFO "%s: %s at 0x%lx, "
2315 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2316 "XID %08x IRQ %d\n",
b57b7e5a 2317 dev->name,
bcf0bf90 2318 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2319 dev->base_addr,
2320 dev->dev_addr[0], dev->dev_addr[1],
2321 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2322 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2323 }
1da177e4 2324
4ff96fa6 2325 rtl8169_init_phy(dev, tp);
8b76ab39 2326 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2327
4ff96fa6
FR		 2328out:
2329 return rc;
1da177e4 2330
fbac58fc
FR		 2331err_out_msi_5:
2332 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2333 iounmap(ioaddr);
2334err_out_free_res_4:
2335 pci_release_regions(pdev);
2336err_out_mwi_3:
2337 pci_clear_mwi(pdev);
2338err_out_disable_2:
2339 pci_disable_device(pdev);
2340err_out_free_dev_1:
2341 free_netdev(dev);
2342 goto out;
1da177e4
LT		 2343}
2344
07d3f51f 2345static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2346{
2347 struct net_device *dev = pci_get_drvdata(pdev);
2348 struct rtl8169_private *tp = netdev_priv(dev);
2349
eb2a021c
FR		 2350 flush_scheduled_work();
2351
1da177e4 2352 unregister_netdev(dev);
fbac58fc 2353 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2354 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2355 pci_set_drvdata(pdev, NULL);
2356}
2357
1da177e4
LT		 2358static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2359 struct net_device *dev)
2360{
2361 unsigned int mtu = dev->mtu;
2362
2363 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2364}
2365
2366static int rtl8169_open(struct net_device *dev)
2367{
2368 struct rtl8169_private *tp = netdev_priv(dev);
2369 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2370 int retval = -ENOMEM;
1da177e4 2371
1da177e4 2372
99f252b0 2373 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2374
2375 /*
2376 * Rx and Tx desscriptors needs 256 bytes alignment.
2377 * pci_alloc_consistent provides more.
2378 */
2379 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2380 &tp->TxPhyAddr);
2381 if (!tp->TxDescArray)
99f252b0 2382 goto out;
1da177e4
LT		 2383
2384 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2385 &tp->RxPhyAddr);
2386 if (!tp->RxDescArray)
99f252b0 2387 goto err_free_tx_0;
1da177e4
LT		 2388
2389 retval = rtl8169_init_ring(dev);
2390 if (retval < 0)
99f252b0 2391 goto err_free_rx_1;
1da177e4 2392
c4028958 2393 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2394
99f252b0
FR		 2395 smp_mb();
2396
fbac58fc
FR		 2397 retval = request_irq(dev->irq, rtl8169_interrupt,
2398 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2399 dev->name, dev);
2400 if (retval < 0)
2401 goto err_release_ring_2;
2402
bea3348e 2403 napi_enable(&tp->napi);
bea3348e 2404
07ce4064 2405 rtl_hw_start(dev);
1da177e4
LT		 2406
2407 rtl8169_request_timer(dev);
2408
2409 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2410out:
2411 return retval;
2412
99f252b0
FR		 2413err_release_ring_2:
2414 rtl8169_rx_clear(tp);
2415err_free_rx_1:
1da177e4
LT		 2416 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2417 tp->RxPhyAddr);
99f252b0 2418err_free_tx_0:
1da177e4
LT		 2419 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2420 tp->TxPhyAddr);
1da177e4
LT		 2421 goto out;
2422}
2423
2424static void rtl8169_hw_reset(void __iomem *ioaddr)
2425{
2426 /* Disable interrupts */
2427 rtl8169_irq_mask_and_ack(ioaddr);
2428
2429 /* Reset the chipset */
2430 RTL_W8(ChipCmd, CmdReset);
2431
2432 /* PCI commit */
2433 RTL_R8(ChipCmd);
2434}
2435
7f796d83 2436static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2437{
2438 void __iomem *ioaddr = tp->mmio_addr;
2439 u32 cfg = rtl8169_rx_config;
2440
2441 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2442 RTL_W32(RxConfig, cfg);
2443
2444 /* Set DMA burst size and Interframe Gap Time */
2445 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2446 (InterFrameGap << TxInterFrameGapShift));
2447}
2448
07ce4064 2449static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2450{
2451 struct rtl8169_private *tp = netdev_priv(dev);
2452 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2453 unsigned int i;
1da177e4
LT		 2454
2455 /* Soft reset the chip. */
2456 RTL_W8(ChipCmd, CmdReset);
2457
2458 /* Check that the chip has finished the reset. */
07d3f51f 2459 for (i = 0; i < 100; i++) {
1da177e4
LT		 2460 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2461 break;
b518fa8e 2462 msleep_interruptible(1);
1da177e4
LT		 2463 }
2464
07ce4064
FR		 2465 tp->hw_start(dev);
2466
07ce4064
FR		 2467 netif_start_queue(dev);
2468}
2469
2470
7f796d83
FR		 2471static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2472 void __iomem *ioaddr)
2473{
2474 /*
2475 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2476 * register to be written before TxDescAddrLow to work.
2477 * Switching from MMIO to I/O access fixes the issue as well.
2478 */
2479 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 2480 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 2481 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 2482 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2483}
2484
2485static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2486{
2487 u16 cmd;
2488
2489 cmd = RTL_R16(CPlusCmd);
2490 RTL_W16(CPlusCmd, cmd);
2491 return cmd;
2492}
2493
fdd7b4c3 2494static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 2495{
2496 /* Low hurts. Let's disable the filtering. */
fdd7b4c3 2497 RTL_W16(RxMaxSize, rx_buf_sz);
7f796d83
FR		 2498}
2499
6dccd16b
FR		 2500static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2501{
2502 struct {
2503 u32 mac_version;
2504 u32 clk;
2505 u32 val;
2506 } cfg2_info [] = {
2507 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2508 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2509 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2510 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2511 }, *p = cfg2_info;
2512 unsigned int i;
2513 u32 clk;
2514
2515 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2516 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2517 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2518 RTL_W32(0x7c, p->val);
2519 break;
2520 }
2521 }
2522}
2523
07ce4064
FR		 2524static void rtl_hw_start_8169(struct net_device *dev)
2525{
2526 struct rtl8169_private *tp = netdev_priv(dev);
2527 void __iomem *ioaddr = tp->mmio_addr;
2528 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2529
9cb427b6
FR		 2530 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2531 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2532 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2533 }
2534
1da177e4 2535 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2536 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2537 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2538 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2539 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2540 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2541
1da177e4
LT		 2542 RTL_W8(EarlyTxThres, EarlyTxThld);
2543
fdd7b4c3 2544 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 2545
c946b304
FR		 2546 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2547 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2548 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2549 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2550 rtl_set_rx_tx_config_registers(tp);
1da177e4 2551
7f796d83 2552 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2553
bcf0bf90
FR		 2554 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2555 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2556 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2557 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2558 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2559 }
2560
bcf0bf90
FR		 2561 RTL_W16(CPlusCmd, tp->cp_cmd);
2562
6dccd16b
FR		 2563 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2564
1da177e4
LT		 2565 /*
2566 * Undocumented corner. Supposedly:
2567 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2568 */
2569 RTL_W16(IntrMitigate, 0x0000);
2570
7f796d83 2571 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2572
c946b304
FR		 2573 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2574 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2575 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2576 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2577 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2578 rtl_set_rx_tx_config_registers(tp);
2579 }
2580
1da177e4 2581 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2582
2583 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2584 RTL_R8(IntrMask);
1da177e4
LT		 2585
2586 RTL_W32(RxMissed, 0);
2587
07ce4064 2588 rtl_set_rx_mode(dev);
1da177e4
LT		 2589
2590 /* no early-rx interrupts */
2591 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2592
2593 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2594 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2595}
1da177e4 2596
9c14ceaf 2597static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2598{
9c14ceaf
FR		 2599 struct net_device *dev = pci_get_drvdata(pdev);
2600 struct rtl8169_private *tp = netdev_priv(dev);
2601 int cap = tp->pcie_cap;
2602
2603 if (cap) {
2604 u16 ctl;
458a9f61 2605
9c14ceaf
FR		 2606 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2607 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2608 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2609 }
458a9f61
FR		 2610}
2611
dacf8154
FR		 2612static void rtl_csi_access_enable(void __iomem *ioaddr)
2613{
2614 u32 csi;
2615
2616 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2617 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2618}
2619
2620struct ephy_info {
2621 unsigned int offset;
2622 u16 mask;
2623 u16 bits;
2624};
2625
2626static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2627{
2628 u16 w;
2629
2630 while (len-- > 0) {
2631 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2632 rtl_ephy_write(ioaddr, e->offset, w);
2633 e++;
2634 }
2635}
2636
b726e493
FR		 2637static void rtl_disable_clock_request(struct pci_dev *pdev)
2638{
2639 struct net_device *dev = pci_get_drvdata(pdev);
2640 struct rtl8169_private *tp = netdev_priv(dev);
2641 int cap = tp->pcie_cap;
2642
2643 if (cap) {
2644 u16 ctl;
2645
2646 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2647 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2648 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2649 }
2650}
2651
2652#define R8168_CPCMD_QUIRK_MASK (\
2653 EnableBist | \
2654 Mac_dbgo_oe | \
2655 Force_half_dup | \
2656 Force_rxflow_en | \
2657 Force_txflow_en | \
2658 Cxpl_dbg_sel | \
2659 ASF | \
2660 PktCntrDisable | \
2661 Mac_dbgo_sel)
2662
219a1e9d
FR		 2663static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2664{
b726e493
FR		 2665 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2666
2667 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2668
2e68ae44
FR		 2669 rtl_tx_performance_tweak(pdev,
2670 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2671}
2672
2673static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2674{
2675 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2676
2677 RTL_W8(EarlyTxThres, EarlyTxThld);
2678
2679 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2680}
2681
2682static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2683{
b726e493
FR		 2684 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2685
2686 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2687
219a1e9d 2688 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2689
2690 rtl_disable_clock_request(pdev);
2691
2692 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2693}
2694
ef3386f0 2695static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2696{
b726e493
FR		 2697 static struct ephy_info e_info_8168cp[] = {
2698 { 0x01, 0, 0x0001 },
2699 { 0x02, 0x0800, 0x1000 },
2700 { 0x03, 0, 0x0042 },
2701 { 0x06, 0x0080, 0x0000 },
2702 { 0x07, 0, 0x2000 }
2703 };
2704
2705 rtl_csi_access_enable(ioaddr);
2706
2707 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2708
219a1e9d
FR		 2709 __rtl_hw_start_8168cp(ioaddr, pdev);
2710}
2711
ef3386f0
FR		 2712static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2713{
2714 rtl_csi_access_enable(ioaddr);
2715
2716 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2717
2718 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2719
2720 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2721}
2722
7f3e3d3a
FR		 2723static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2724{
2725 rtl_csi_access_enable(ioaddr);
2726
2727 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2728
2729 /* Magic. */
2730 RTL_W8(DBG_REG, 0x20);
2731
2732 RTL_W8(EarlyTxThres, EarlyTxThld);
2733
2734 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2735
2736 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2737}
2738
219a1e9d
FR		 2739static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2740{
b726e493
FR		 2741 static struct ephy_info e_info_8168c_1[] = {
2742 { 0x02, 0x0800, 0x1000 },
2743 { 0x03, 0, 0x0002 },
2744 { 0x06, 0x0080, 0x0000 }
2745 };
2746
2747 rtl_csi_access_enable(ioaddr);
2748
2749 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2750
2751 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2752
219a1e9d
FR		 2753 __rtl_hw_start_8168cp(ioaddr, pdev);
2754}
2755
2756static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2757{
b726e493
FR		 2758 static struct ephy_info e_info_8168c_2[] = {
2759 { 0x01, 0, 0x0001 },
2760 { 0x03, 0x0400, 0x0220 }
2761 };
2762
2763 rtl_csi_access_enable(ioaddr);
2764
2765 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2766
219a1e9d
FR		 2767 __rtl_hw_start_8168cp(ioaddr, pdev);
2768}
2769
197ff761
FR		 2770static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2771{
2772 rtl_hw_start_8168c_2(ioaddr, pdev);
2773}
2774
6fb07058
FR		 2775static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2776{
2777 rtl_csi_access_enable(ioaddr);
2778
2779 __rtl_hw_start_8168cp(ioaddr, pdev);
2780}
2781
5b538df9
FR		 2782static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2783{
2784 rtl_csi_access_enable(ioaddr);
2785
2786 rtl_disable_clock_request(pdev);
2787
2788 RTL_W8(EarlyTxThres, EarlyTxThld);
2789
2790 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2791
2792 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2793}
2794
07ce4064
FR		 2795static void rtl_hw_start_8168(struct net_device *dev)
2796{
2dd99530
FR		 2797 struct rtl8169_private *tp = netdev_priv(dev);
2798 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2799 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2800
2801 RTL_W8(Cfg9346, Cfg9346_Unlock);
2802
2803 RTL_W8(EarlyTxThres, EarlyTxThld);
2804
fdd7b4c3 2805 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 2806
0e485150 2807 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2808
2809 RTL_W16(CPlusCmd, tp->cp_cmd);
2810
0e485150 2811 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2812
0e485150
FR		 2813 /* Work around for RxFIFO overflow. */
2814 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2815 tp->intr_event |= RxFIFOOver | PCSTimeout;
2816 tp->intr_event &= ~RxOverflow;
2817 }
2818
2819 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2820
b8363901
FR		 2821 rtl_set_rx_mode(dev);
2822
2823 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2824 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2825
2826 RTL_R8(IntrMask);
2827
219a1e9d
FR		 2828 switch (tp->mac_version) {
2829 case RTL_GIGA_MAC_VER_11:
2830 rtl_hw_start_8168bb(ioaddr, pdev);
2831 break;
2832
2833 case RTL_GIGA_MAC_VER_12:
2834 case RTL_GIGA_MAC_VER_17:
2835 rtl_hw_start_8168bef(ioaddr, pdev);
2836 break;
2837
2838 case RTL_GIGA_MAC_VER_18:
ef3386f0 2839 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2840 break;
2841
2842 case RTL_GIGA_MAC_VER_19:
2843 rtl_hw_start_8168c_1(ioaddr, pdev);
2844 break;
2845
2846 case RTL_GIGA_MAC_VER_20:
2847 rtl_hw_start_8168c_2(ioaddr, pdev);
2848 break;
2849
197ff761
FR		 2850 case RTL_GIGA_MAC_VER_21:
2851 rtl_hw_start_8168c_3(ioaddr, pdev);
2852 break;
2853
6fb07058
FR		 2854 case RTL_GIGA_MAC_VER_22:
2855 rtl_hw_start_8168c_4(ioaddr, pdev);
2856 break;
2857
ef3386f0
FR		 2858 case RTL_GIGA_MAC_VER_23:
2859 rtl_hw_start_8168cp_2(ioaddr, pdev);
2860 break;
2861
7f3e3d3a
FR		 2862 case RTL_GIGA_MAC_VER_24:
2863 rtl_hw_start_8168cp_3(ioaddr, pdev);
2864 break;
2865
5b538df9
FR		 2866 case RTL_GIGA_MAC_VER_25:
2867 rtl_hw_start_8168d(ioaddr, pdev);
2868 break;
2869
219a1e9d
FR		 2870 default:
2871 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2872 dev->name, tp->mac_version);
2873 break;
2874 }
2dd99530 2875
0e485150
FR		 2876 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2877
b8363901
FR		 2878 RTL_W8(Cfg9346, Cfg9346_Lock);
2879
2dd99530 2880 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2881
0e485150 2882 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2883}
1da177e4 2884
2857ffb7
FR		 2885#define R810X_CPCMD_QUIRK_MASK (\
2886 EnableBist | \
2887 Mac_dbgo_oe | \
2888 Force_half_dup | \
5edcc537 2889 Force_rxflow_en | \
2857ffb7
FR		 2890 Force_txflow_en | \
2891 Cxpl_dbg_sel | \
2892 ASF | \
2893 PktCntrDisable | \
2894 PCIDAC | \
2895 PCIMulRW)
2896
2897static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2898{
2899 static struct ephy_info e_info_8102e_1[] = {
2900 { 0x01, 0, 0x6e65 },
2901 { 0x02, 0, 0x091f },
2902 { 0x03, 0, 0xc2f9 },
2903 { 0x06, 0, 0xafb5 },
2904 { 0x07, 0, 0x0e00 },
2905 { 0x19, 0, 0xec80 },
2906 { 0x01, 0, 0x2e65 },
2907 { 0x01, 0, 0x6e65 }
2908 };
2909 u8 cfg1;
2910
2911 rtl_csi_access_enable(ioaddr);
2912
2913 RTL_W8(DBG_REG, FIX_NAK_1);
2914
2915 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2916
2917 RTL_W8(Config1,
2918 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2919 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2920
2921 cfg1 = RTL_R8(Config1);
2922 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2923 RTL_W8(Config1, cfg1 & ~LEDS0);
2924
2925 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2926
2927 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2928}
2929
2930static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2931{
2932 rtl_csi_access_enable(ioaddr);
2933
2934 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2935
2936 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2937 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2938
2939 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2940}
2941
2942static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2943{
2944 rtl_hw_start_8102e_2(ioaddr, pdev);
2945
2946 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2947}
2948
07ce4064
FR		 2949static void rtl_hw_start_8101(struct net_device *dev)
2950{
cdf1a608
FR		 2951 struct rtl8169_private *tp = netdev_priv(dev);
2952 void __iomem *ioaddr = tp->mmio_addr;
2953 struct pci_dev *pdev = tp->pci_dev;
2954
e3cf0cc0
FR		 2955 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2956 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2957 int cap = tp->pcie_cap;
2958
2959 if (cap) {
2960 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2961 PCI_EXP_DEVCTL_NOSNOOP_EN);
2962 }
cdf1a608
FR		 2963 }
2964
2857ffb7
FR		 2965 switch (tp->mac_version) {
2966 case RTL_GIGA_MAC_VER_07:
2967 rtl_hw_start_8102e_1(ioaddr, pdev);
2968 break;
2969
2970 case RTL_GIGA_MAC_VER_08:
2971 rtl_hw_start_8102e_3(ioaddr, pdev);
2972 break;
2973
2974 case RTL_GIGA_MAC_VER_09:
2975 rtl_hw_start_8102e_2(ioaddr, pdev);
2976 break;
cdf1a608
FR		 2977 }
2978
2979 RTL_W8(Cfg9346, Cfg9346_Unlock);
2980
2981 RTL_W8(EarlyTxThres, EarlyTxThld);
2982
fdd7b4c3 2983 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 2984
2985 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2986
2987 RTL_W16(CPlusCmd, tp->cp_cmd);
2988
2989 RTL_W16(IntrMitigate, 0x0000);
2990
2991 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2992
2993 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2994 rtl_set_rx_tx_config_registers(tp);
2995
2996 RTL_W8(Cfg9346, Cfg9346_Lock);
2997
2998 RTL_R8(IntrMask);
2999
cdf1a608
FR		 3000 rtl_set_rx_mode(dev);
3001
0e485150
FR		 3002 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3003
cdf1a608 3004 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3005
0e485150 3006 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3007}
3008
3009static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3010{
3011 struct rtl8169_private *tp = netdev_priv(dev);
3012 int ret = 0;
3013
3014 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3015 return -EINVAL;
3016
3017 dev->mtu = new_mtu;
3018
3019 if (!netif_running(dev))
3020 goto out;
3021
3022 rtl8169_down(dev);
3023
3024 rtl8169_set_rxbufsize(tp, dev);
3025
3026 ret = rtl8169_init_ring(dev);
3027 if (ret < 0)
3028 goto out;
3029
bea3348e 3030 napi_enable(&tp->napi);
1da177e4 3031
07ce4064 3032 rtl_hw_start(dev);
1da177e4
LT		 3033
3034 rtl8169_request_timer(dev);
3035
3036out:
3037 return ret;
3038}
3039
3040static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3041{
95e0918d 3042 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3043 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3044}
3045
3046static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3047 struct sk_buff **sk_buff, struct RxDesc *desc)
3048{
3049 struct pci_dev *pdev = tp->pci_dev;
3050
3051 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3052 PCI_DMA_FROMDEVICE);
3053 dev_kfree_skb(*sk_buff);
3054 *sk_buff = NULL;
3055 rtl8169_make_unusable_by_asic(desc);
3056}
3057
3058static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3059{
3060 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3061
3062 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3063}
3064
3065static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3066 u32 rx_buf_sz)
3067{
3068 desc->addr = cpu_to_le64(mapping);
3069 wmb();
3070 rtl8169_mark_to_asic(desc, rx_buf_sz);
3071}
3072
15d31758
SH		 3073static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3074 struct net_device *dev,
3075 struct RxDesc *desc, int rx_buf_sz,
3076 unsigned int align)
1da177e4
LT		 3077{
3078 struct sk_buff *skb;
3079 dma_addr_t mapping;
e9f63f30 3080 unsigned int pad;
1da177e4 3081
e9f63f30
FR		 3082 pad = align ? align : NET_IP_ALIGN;
3083
3084 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3085 if (!skb)
3086 goto err_out;
3087
e9f63f30 3088 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3089
689be439 3090 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3091 PCI_DMA_FROMDEVICE);
3092
3093 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3094out:
15d31758 3095 return skb;
1da177e4
LT		 3096
3097err_out:
1da177e4
LT		 3098 rtl8169_make_unusable_by_asic(desc);
3099 goto out;
3100}
3101
3102static void rtl8169_rx_clear(struct rtl8169_private *tp)
3103{
07d3f51f 3104 unsigned int i;
1da177e4
LT		 3105
3106 for (i = 0; i < NUM_RX_DESC; i++) {
3107 if (tp->Rx_skbuff[i]) {
3108 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3109 tp->RxDescArray + i);
3110 }
3111 }
3112}
3113
3114static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3115 u32 start, u32 end)
3116{
3117 u32 cur;
5b0384f4 3118
4ae47c2d 3119 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 3120 struct sk_buff *skb;
3121 unsigned int i = cur % NUM_RX_DESC;
1da177e4 3122
4ae47c2d
FR		 3123 WARN_ON((s32)(end - cur) < 0);
3124
1da177e4
LT		 3125 if (tp->Rx_skbuff[i])
3126 continue;
bcf0bf90 3127
15d31758
SH		 3128 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3129 tp->RxDescArray + i,
3130 tp->rx_buf_sz, tp->align);
3131 if (!skb)
1da177e4 3132 break;
15d31758
SH		 3133
3134 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 3135 }
3136 return cur - start;
3137}
3138
3139static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3140{
3141 desc->opts1 |= cpu_to_le32(RingEnd);
3142}
3143
3144static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3145{
3146 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3147}
3148
3149static int rtl8169_init_ring(struct net_device *dev)
3150{
3151 struct rtl8169_private *tp = netdev_priv(dev);
3152
3153 rtl8169_init_ring_indexes(tp);
3154
3155 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3156 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3157
3158 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3159 goto err_out;
3160
3161 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3162
3163 return 0;
3164
3165err_out:
3166 rtl8169_rx_clear(tp);
3167 return -ENOMEM;
3168}
3169
3170static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3171 struct TxDesc *desc)
3172{
3173 unsigned int len = tx_skb->len;
3174
3175 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3176 desc->opts1 = 0x00;
3177 desc->opts2 = 0x00;
3178 desc->addr = 0x00;
3179 tx_skb->len = 0;
3180}
3181
3182static void rtl8169_tx_clear(struct rtl8169_private *tp)
3183{
3184 unsigned int i;
3185
3186 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3187 unsigned int entry = i % NUM_TX_DESC;
3188 struct ring_info *tx_skb = tp->tx_skb + entry;
3189 unsigned int len = tx_skb->len;
3190
3191 if (len) {
3192 struct sk_buff *skb = tx_skb->skb;
3193
3194 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3195 tp->TxDescArray + entry);
3196 if (skb) {
3197 dev_kfree_skb(skb);
3198 tx_skb->skb = NULL;
3199 }
cebf8cc7 3200 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3201 }
3202 }
3203 tp->cur_tx = tp->dirty_tx = 0;
3204}
3205
c4028958 3206static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3207{
3208 struct rtl8169_private *tp = netdev_priv(dev);
3209
c4028958 3210 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3211 schedule_delayed_work(&tp->task, 4);
3212}
3213
3214static void rtl8169_wait_for_quiescence(struct net_device *dev)
3215{
3216 struct rtl8169_private *tp = netdev_priv(dev);
3217 void __iomem *ioaddr = tp->mmio_addr;
3218
3219 synchronize_irq(dev->irq);
3220
3221 /* Wait for any pending NAPI task to complete */
bea3348e 3222 napi_disable(&tp->napi);
1da177e4
LT		 3223
3224 rtl8169_irq_mask_and_ack(ioaddr);
3225
d1d08d12
DM		 3226 tp->intr_mask = 0xffff;
3227 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3228 napi_enable(&tp->napi);
1da177e4
LT		 3229}
3230
c4028958 3231static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3232{
c4028958
DH		 3233 struct rtl8169_private *tp =
3234 container_of(work, struct rtl8169_private, task.work);
3235 struct net_device *dev = tp->dev;
1da177e4
LT		 3236 int ret;
3237
eb2a021c
FR		 3238 rtnl_lock();
3239
3240 if (!netif_running(dev))
3241 goto out_unlock;
3242
3243 rtl8169_wait_for_quiescence(dev);
3244 rtl8169_close(dev);
1da177e4
LT		 3245
3246 ret = rtl8169_open(dev);
3247 if (unlikely(ret < 0)) {
07d3f51f 3248 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3249 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3250 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3251 }
3252 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3253 }
eb2a021c
FR		 3254
3255out_unlock:
3256 rtnl_unlock();
1da177e4
LT		 3257}
3258
c4028958 3259static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3260{
c4028958
DH		 3261 struct rtl8169_private *tp =
3262 container_of(work, struct rtl8169_private, task.work);
3263 struct net_device *dev = tp->dev;
1da177e4 3264
eb2a021c
FR		 3265 rtnl_lock();
3266
1da177e4 3267 if (!netif_running(dev))
eb2a021c 3268 goto out_unlock;
1da177e4
LT		 3269
3270 rtl8169_wait_for_quiescence(dev);
3271
bea3348e 3272 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3273 rtl8169_tx_clear(tp);
3274
3275 if (tp->dirty_rx == tp->cur_rx) {
3276 rtl8169_init_ring_indexes(tp);
07ce4064 3277 rtl_hw_start(dev);
1da177e4 3278 netif_wake_queue(dev);
cebf8cc7 3279 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3280 } else {
07d3f51f 3281 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3282 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3283 dev->name);
1da177e4
LT		 3284 }
3285 rtl8169_schedule_work(dev, rtl8169_reset_task);
3286 }
eb2a021c
FR		 3287
3288out_unlock:
3289 rtnl_unlock();
1da177e4
LT		 3290}
3291
3292static void rtl8169_tx_timeout(struct net_device *dev)
3293{
3294 struct rtl8169_private *tp = netdev_priv(dev);
3295
3296 rtl8169_hw_reset(tp->mmio_addr);
3297
3298 /* Let's wait a bit while any (async) irq lands on */
3299 rtl8169_schedule_work(dev, rtl8169_reset_task);
3300}
3301
3302static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3303 u32 opts1)
3304{
3305 struct skb_shared_info *info = skb_shinfo(skb);
3306 unsigned int cur_frag, entry;
a6343afb 3307 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3308
3309 entry = tp->cur_tx;
3310 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3311 skb_frag_t *frag = info->frags + cur_frag;
3312 dma_addr_t mapping;
3313 u32 status, len;
3314 void *addr;
3315
3316 entry = (entry + 1) % NUM_TX_DESC;
3317
3318 txd = tp->TxDescArray + entry;
3319 len = frag->size;
3320 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3321 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3322
3323 /* anti gcc 2.95.3 bugware (sic) */
3324 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3325
3326 txd->opts1 = cpu_to_le32(status);
3327 txd->addr = cpu_to_le64(mapping);
3328
3329 tp->tx_skb[entry].len = len;
3330 }
3331
3332 if (cur_frag) {
3333 tp->tx_skb[entry].skb = skb;
3334 txd->opts1 |= cpu_to_le32(LastFrag);
3335 }
3336
3337 return cur_frag;
3338}
3339
3340static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3341{
3342 if (dev->features & NETIF_F_TSO) {
7967168c 3343 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3344
3345 if (mss)
3346 return LargeSend | ((mss & MSSMask) << MSSShift);
3347 }
84fa7933 3348 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3349 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3350
3351 if (ip->protocol == IPPROTO_TCP)
3352 return IPCS | TCPCS;
3353 else if (ip->protocol == IPPROTO_UDP)
3354 return IPCS | UDPCS;
3355 WARN_ON(1); /* we need a WARN() */
3356 }
3357 return 0;
3358}
3359
3360static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3361{
3362 struct rtl8169_private *tp = netdev_priv(dev);
3363 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3364 struct TxDesc *txd = tp->TxDescArray + entry;
3365 void __iomem *ioaddr = tp->mmio_addr;
3366 dma_addr_t mapping;
3367 u32 status, len;
3368 u32 opts1;
188f4af0 3369 int ret = NETDEV_TX_OK;
5b0384f4 3370
1da177e4 3371 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3372 if (netif_msg_drv(tp)) {
3373 printk(KERN_ERR
3374 "%s: BUG! Tx Ring full when queue awake!\n",
3375 dev->name);
3376 }
1da177e4
LT		 3377 goto err_stop;
3378 }
3379
3380 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3381 goto err_stop;
3382
3383 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3384
3385 frags = rtl8169_xmit_frags(tp, skb, opts1);
3386 if (frags) {
3387 len = skb_headlen(skb);
3388 opts1 |= FirstFrag;
3389 } else {
3390 len = skb->len;
1da177e4
LT		 3391 opts1 |= FirstFrag | LastFrag;
3392 tp->tx_skb[entry].skb = skb;
3393 }
3394
3395 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3396
3397 tp->tx_skb[entry].len = len;
3398 txd->addr = cpu_to_le64(mapping);
3399 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3400
3401 wmb();
3402
3403 /* anti gcc 2.95.3 bugware (sic) */
3404 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3405 txd->opts1 = cpu_to_le32(status);
3406
1da177e4
LT		 3407 tp->cur_tx += frags + 1;
3408
3409 smp_wmb();
3410
275391a4 3411 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3412
3413 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3414 netif_stop_queue(dev);
3415 smp_rmb();
3416 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3417 netif_wake_queue(dev);
3418 }
3419
3420out:
3421 return ret;
3422
3423err_stop:
3424 netif_stop_queue(dev);
188f4af0 3425 ret = NETDEV_TX_BUSY;
cebf8cc7 3426 dev->stats.tx_dropped++;
1da177e4
LT		 3427 goto out;
3428}
3429
3430static void rtl8169_pcierr_interrupt(struct net_device *dev)
3431{
3432 struct rtl8169_private *tp = netdev_priv(dev);
3433 struct pci_dev *pdev = tp->pci_dev;
3434 void __iomem *ioaddr = tp->mmio_addr;
3435 u16 pci_status, pci_cmd;
3436
3437 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3438 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3439
b57b7e5a
SH		 3440 if (netif_msg_intr(tp)) {
3441 printk(KERN_ERR
3442 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3443 dev->name, pci_cmd, pci_status);
3444 }
1da177e4
LT		 3445
3446 /*
3447 * The recovery sequence below admits a very elaborated explanation:
3448 * - it seems to work;
d03902b8
FR		 3449 * - I did not see what else could be done;
3450 * - it makes iop3xx happy.
1da177e4
LT		 3451 *
3452 * Feel free to adjust to your needs.
3453 */
a27993f3 3454 if (pdev->broken_parity_status)
d03902b8
FR		 3455 pci_cmd &= ~PCI_COMMAND_PARITY;
3456 else
3457 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3458
3459 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3460
3461 pci_write_config_word(pdev, PCI_STATUS,
3462 pci_status & (PCI_STATUS_DETECTED_PARITY |
3463 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3464 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3465
3466 /* The infamous DAC f*ckup only happens at boot time */
3467 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3468 if (netif_msg_intr(tp))
3469 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3470 tp->cp_cmd &= ~PCIDAC;
3471 RTL_W16(CPlusCmd, tp->cp_cmd);
3472 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3473 }
3474
3475 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3476
3477 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3478}
3479
07d3f51f
FR		 3480static void rtl8169_tx_interrupt(struct net_device *dev,
3481 struct rtl8169_private *tp,
3482 void __iomem *ioaddr)
1da177e4
LT		 3483{
3484 unsigned int dirty_tx, tx_left;
3485
1da177e4
LT		 3486 dirty_tx = tp->dirty_tx;
3487 smp_rmb();
3488 tx_left = tp->cur_tx - dirty_tx;
3489
3490 while (tx_left > 0) {
3491 unsigned int entry = dirty_tx % NUM_TX_DESC;
3492 struct ring_info *tx_skb = tp->tx_skb + entry;
3493 u32 len = tx_skb->len;
3494 u32 status;
3495
3496 rmb();
3497 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3498 if (status & DescOwn)
3499 break;
3500
cebf8cc7
FR		 3501 dev->stats.tx_bytes += len;
3502 dev->stats.tx_packets++;
1da177e4
LT		 3503
3504 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3505
3506 if (status & LastFrag) {
87433bfc 3507 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 3508 tx_skb->skb = NULL;
3509 }
3510 dirty_tx++;
3511 tx_left--;
3512 }
3513
3514 if (tp->dirty_tx != dirty_tx) {
3515 tp->dirty_tx = dirty_tx;
3516 smp_wmb();
3517 if (netif_queue_stopped(dev) &&
3518 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3519 netif_wake_queue(dev);
3520 }
d78ae2dc
FR		 3521 /*
3522 * 8168 hack: TxPoll requests are lost when the Tx packets are
3523 * too close. Let's kick an extra TxPoll request when a burst
3524 * of start_xmit activity is detected (if it is not detected,
3525 * it is slow enough). -- FR
3526 */
3527 smp_rmb();
3528 if (tp->cur_tx != dirty_tx)
3529 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3530 }
3531}
3532
126fa4b9
FR		 3533static inline int rtl8169_fragmented_frame(u32 status)
3534{
3535 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3536}
3537
1da177e4
LT		 3538static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3539{
3540 u32 opts1 = le32_to_cpu(desc->opts1);
3541 u32 status = opts1 & RxProtoMask;
3542
3543 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3544 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3545 ((status == RxProtoIP) && !(opts1 & IPFail)))
3546 skb->ip_summed = CHECKSUM_UNNECESSARY;
3547 else
3548 skb->ip_summed = CHECKSUM_NONE;
3549}
3550
07d3f51f
FR		 3551static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3552 struct rtl8169_private *tp, int pkt_size,
3553 dma_addr_t addr)
1da177e4 3554{
b449655f
SH		 3555 struct sk_buff *skb;
3556 bool done = false;
1da177e4 3557
b449655f
SH		 3558 if (pkt_size >= rx_copybreak)
3559 goto out;
1da177e4 3560
07d3f51f 3561 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3562 if (!skb)
3563 goto out;
3564
07d3f51f
FR		 3565 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3566 PCI_DMA_FROMDEVICE);
86402234 3567 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3568 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3569 *sk_buff = skb;
3570 done = true;
3571out:
3572 return done;
1da177e4
LT		 3573}
3574
07d3f51f
FR		 3575static int rtl8169_rx_interrupt(struct net_device *dev,
3576 struct rtl8169_private *tp,
bea3348e 3577 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3578{
3579 unsigned int cur_rx, rx_left;
3580 unsigned int delta, count;
3581
1da177e4
LT		 3582 cur_rx = tp->cur_rx;
3583 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3584 rx_left = min(rx_left, budget);
1da177e4 3585
4dcb7d33 3586 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3587 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3588 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3589 u32 status;
3590
3591 rmb();
126fa4b9 3592 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3593
3594 if (status & DescOwn)
3595 break;
4dcb7d33 3596 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3597 if (netif_msg_rx_err(tp)) {
3598 printk(KERN_INFO
3599 "%s: Rx ERROR. status = %08x\n",
3600 dev->name, status);
3601 }
cebf8cc7 3602 dev->stats.rx_errors++;
1da177e4 3603 if (status & (RxRWT | RxRUNT))
cebf8cc7 3604 dev->stats.rx_length_errors++;
1da177e4 3605 if (status & RxCRC)
cebf8cc7 3606 dev->stats.rx_crc_errors++;
9dccf611
FR		 3607 if (status & RxFOVF) {
3608 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3609 dev->stats.rx_fifo_errors++;
9dccf611 3610 }
126fa4b9 3611 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3612 } else {
1da177e4 3613 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3614 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3615 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3616 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3617
126fa4b9
FR		 3618 /*
3619 * The driver does not support incoming fragmented
3620 * frames. They are seen as a symptom of over-mtu
3621 * sized frames.
3622 */
3623 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3624 dev->stats.rx_dropped++;
3625 dev->stats.rx_length_errors++;
126fa4b9 3626 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3627 continue;
126fa4b9
FR		 3628 }
3629
1da177e4 3630 rtl8169_rx_csum(skb, desc);
bcf0bf90 3631
07d3f51f 3632 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3633 pci_dma_sync_single_for_device(pdev, addr,
3634 pkt_size, PCI_DMA_FROMDEVICE);
3635 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3636 } else {
a866bbf6 3637 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3638 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3639 tp->Rx_skbuff[entry] = NULL;
3640 }
3641
1da177e4
LT		 3642 skb_put(skb, pkt_size);
3643 skb->protocol = eth_type_trans(skb, dev);
3644
3645 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3646 netif_receive_skb(skb);
1da177e4 3647
cebf8cc7
FR		 3648 dev->stats.rx_bytes += pkt_size;
3649 dev->stats.rx_packets++;
1da177e4 3650 }
6dccd16b
FR		 3651
3652 /* Work around for AMD plateform. */
95e0918d 3653 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3654 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3655 desc->opts2 = 0;
3656 cur_rx++;
3657 }
1da177e4
LT		 3658 }
3659
3660 count = cur_rx - tp->cur_rx;
3661 tp->cur_rx = cur_rx;
3662
3663 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3664 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3665 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3666 tp->dirty_rx += delta;
3667
3668 /*
3669 * FIXME: until there is periodic timer to try and refill the ring,
3670 * a temporary shortage may definitely kill the Rx process.
3671 * - disable the asic to try and avoid an overflow and kick it again
3672 * after refill ?
3673 * - how do others driver handle this condition (Uh oh...).
3674 */
b57b7e5a 3675 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3676 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3677
3678 return count;
3679}
3680
07d3f51f 3681static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3682{
07d3f51f 3683 struct net_device *dev = dev_instance;
1da177e4 3684 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3685 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3686 int handled = 0;
865c652d 3687 int status;
1da177e4 3688
f11a377b
DD		 3689 /* loop handling interrupts until we have no new ones or
3690 * we hit a invalid/hotplug case.
3691 */
865c652d 3692 status = RTL_R16(IntrStatus);
f11a377b
DD		 3693 while (status && status != 0xffff) {
3694 handled = 1;
1da177e4 3695
f11a377b
DD		 3696 /* Handle all of the error cases first. These will reset
3697 * the chip, so just exit the loop.
3698 */
3699 if (unlikely(!netif_running(dev))) {
3700 rtl8169_asic_down(ioaddr);
3701 break;
3702 }
1da177e4 3703
f11a377b
DD		 3704 /* Work around for rx fifo overflow */
3705 if (unlikely(status & RxFIFOOver) &&
3706 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3707 netif_stop_queue(dev);
3708 rtl8169_tx_timeout(dev);
3709 break;
3710 }
1da177e4 3711
f11a377b
DD		 3712 if (unlikely(status & SYSErr)) {
3713 rtl8169_pcierr_interrupt(dev);
3714 break;
3715 }
1da177e4 3716
f11a377b
DD		 3717 if (status & LinkChg)
3718 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 3719
f11a377b
DD		 3720 /* We need to see the lastest version of tp->intr_mask to
3721 * avoid ignoring an MSI interrupt and having to wait for
3722 * another event which may never come.
3723 */
3724 smp_rmb();
3725 if (status & tp->intr_mask & tp->napi_event) {
3726 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3727 tp->intr_mask = ~tp->napi_event;
3728
3729 if (likely(napi_schedule_prep(&tp->napi)))
3730 __napi_schedule(&tp->napi);
3731 else if (netif_msg_intr(tp)) {
3732 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3733 dev->name, status);
3734 }
3735 }
1da177e4 3736
f11a377b
DD		 3737 /* We only get a new MSI interrupt when all active irq
3738 * sources on the chip have been acknowledged. So, ack
3739 * everything we've seen and check if new sources have become
3740 * active to avoid blocking all interrupts from the chip.
3741 */
3742 RTL_W16(IntrStatus,
3743 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3744 status = RTL_R16(IntrStatus);
865c652d 3745 }
1da177e4 3746
1da177e4
LT		 3747 return IRQ_RETVAL(handled);
3748}
3749
bea3348e 3750static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3751{
bea3348e
SH		 3752 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3753 struct net_device *dev = tp->dev;
1da177e4 3754 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3755 int work_done;
1da177e4 3756
bea3348e 3757 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3758 rtl8169_tx_interrupt(dev, tp, ioaddr);
3759
bea3348e 3760 if (work_done < budget) {
288379f0 3761 napi_complete(napi);
f11a377b
DD		 3762
3763 /* We need for force the visibility of tp->intr_mask
3764 * for other CPUs, as we can loose an MSI interrupt
3765 * and potentially wait for a retransmit timeout if we don't.
3766 * The posted write to IntrMask is safe, as it will
3767 * eventually make it to the chip and we won't loose anything
3768 * until it does.
1da177e4 3769 */
f11a377b 3770 tp->intr_mask = 0xffff;
1da177e4 3771 smp_wmb();
0e485150 3772 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3773 }
3774
bea3348e 3775 return work_done;
1da177e4 3776}
1da177e4 3777
523a6094
FR		 3778static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3779{
3780 struct rtl8169_private *tp = netdev_priv(dev);
3781
3782 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3783 return;
3784
3785 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3786 RTL_W32(RxMissed, 0);
3787}
3788
1da177e4
LT		 3789static void rtl8169_down(struct net_device *dev)
3790{
3791 struct rtl8169_private *tp = netdev_priv(dev);
3792 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3793 unsigned int intrmask;
1da177e4
LT		 3794
3795 rtl8169_delete_timer(dev);
3796
3797 netif_stop_queue(dev);
3798
93dd79e8 3799 napi_disable(&tp->napi);
93dd79e8 3800
1da177e4
LT		 3801core_down:
3802 spin_lock_irq(&tp->lock);
3803
3804 rtl8169_asic_down(ioaddr);
3805
523a6094 3806 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3807
3808 spin_unlock_irq(&tp->lock);
3809
3810 synchronize_irq(dev->irq);
3811
1da177e4 3812 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3813 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3814
3815 /*
3816 * And now for the 50k$ question: are IRQ disabled or not ?
3817 *
3818 * Two paths lead here:
3819 * 1) dev->close
3820 * -> netif_running() is available to sync the current code and the
3821 * IRQ handler. See rtl8169_interrupt for details.
3822 * 2) dev->change_mtu
3823 * -> rtl8169_poll can not be issued again and re-enable the
3824 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3825 *
3826 * No loop if hotpluged or major error (0xffff).
1da177e4 3827 */
733b736c
AP		 3828 intrmask = RTL_R16(IntrMask);
3829 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3830 goto core_down;
3831
3832 rtl8169_tx_clear(tp);
3833
3834 rtl8169_rx_clear(tp);
3835}
3836
3837static int rtl8169_close(struct net_device *dev)
3838{
3839 struct rtl8169_private *tp = netdev_priv(dev);
3840 struct pci_dev *pdev = tp->pci_dev;
3841
355423d0
IV		 3842 /* update counters before going down */
3843 rtl8169_update_counters(dev);
3844
1da177e4
LT		 3845 rtl8169_down(dev);
3846
3847 free_irq(dev->irq, dev);
3848
1da177e4
LT		 3849 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3850 tp->RxPhyAddr);
3851 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3852 tp->TxPhyAddr);
3853 tp->TxDescArray = NULL;
3854 tp->RxDescArray = NULL;
3855
3856 return 0;
3857}
3858
07ce4064 3859static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3860{
3861 struct rtl8169_private *tp = netdev_priv(dev);
3862 void __iomem *ioaddr = tp->mmio_addr;
3863 unsigned long flags;
3864 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3865 int rx_mode;
1da177e4
LT		 3866 u32 tmp = 0;
3867
3868 if (dev->flags & IFF_PROMISC) {
3869 /* Unconditionally log net taps. */
b57b7e5a
SH		 3870 if (netif_msg_link(tp)) {
3871 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3872 dev->name);
3873 }
1da177e4
LT		 3874 rx_mode =
3875 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3876 AcceptAllPhys;
3877 mc_filter[1] = mc_filter[0] = 0xffffffff;
3878 } else if ((dev->mc_count > multicast_filter_limit)
3879 || (dev->flags & IFF_ALLMULTI)) {
3880 /* Too many to filter perfectly -- accept all multicasts. */
3881 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3882 mc_filter[1] = mc_filter[0] = 0xffffffff;
3883 } else {
3884 struct dev_mc_list *mclist;
07d3f51f
FR		 3885 unsigned int i;
3886
1da177e4
LT		 3887 rx_mode = AcceptBroadcast | AcceptMyPhys;
3888 mc_filter[1] = mc_filter[0] = 0;
3889 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3890 i++, mclist = mclist->next) {
3891 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3892 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3893 rx_mode |= AcceptMulticast;
3894 }
3895 }
3896
3897 spin_lock_irqsave(&tp->lock, flags);
3898
3899 tmp = rtl8169_rx_config | rx_mode |
3900 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3901
f887cce8 3902 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3903 u32 data = mc_filter[0];
3904
3905 mc_filter[0] = swab32(mc_filter[1]);
3906 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3907 }
3908
1da177e4
LT		 3909 RTL_W32(MAR0 + 0, mc_filter[0]);
3910 RTL_W32(MAR0 + 4, mc_filter[1]);
3911
57a9f236
FR		 3912 RTL_W32(RxConfig, tmp);
3913
1da177e4
LT		 3914 spin_unlock_irqrestore(&tp->lock, flags);
3915}
3916
3917/**
3918 * rtl8169_get_stats - Get rtl8169 read/write statistics
3919 * @dev: The Ethernet Device to get statistics for
3920 *
3921 * Get TX/RX statistics for rtl8169
3922 */
3923static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3924{
3925 struct rtl8169_private *tp = netdev_priv(dev);
3926 void __iomem *ioaddr = tp->mmio_addr;
3927 unsigned long flags;
3928
3929 if (netif_running(dev)) {
3930 spin_lock_irqsave(&tp->lock, flags);
523a6094 3931 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3932 spin_unlock_irqrestore(&tp->lock, flags);
3933 }
5b0384f4 3934
cebf8cc7 3935 return &dev->stats;
1da177e4
LT		 3936}
3937
861ab440 3938static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 3939{
5d06a99f 3940 if (!netif_running(dev))
861ab440 3941 return;
5d06a99f
FR		 3942
3943 netif_device_detach(dev);
3944 netif_stop_queue(dev);
861ab440
RW		 3945}
3946
3947#ifdef CONFIG_PM
3948
3949static int rtl8169_suspend(struct device *device)
3950{
3951 struct pci_dev *pdev = to_pci_dev(device);
3952 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 3953
861ab440 3954 rtl8169_net_suspend(dev);
1371fa6d 3955
5d06a99f
FR		 3956 return 0;
3957}
3958
861ab440 3959static int rtl8169_resume(struct device *device)
5d06a99f 3960{
861ab440 3961 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 3962 struct net_device *dev = pci_get_drvdata(pdev);
3963
3964 if (!netif_running(dev))
3965 goto out;
3966
3967 netif_device_attach(dev);
3968
5d06a99f
FR		 3969 rtl8169_schedule_work(dev, rtl8169_reset_task);
3970out:
3971 return 0;
3972}
3973
861ab440
RW		 3974static struct dev_pm_ops rtl8169_pm_ops = {
3975 .suspend = rtl8169_suspend,
3976 .resume = rtl8169_resume,
3977 .freeze = rtl8169_suspend,
3978 .thaw = rtl8169_resume,
3979 .poweroff = rtl8169_suspend,
3980 .restore = rtl8169_resume,
3981};
3982
3983#define RTL8169_PM_OPS (&rtl8169_pm_ops)
3984
3985#else /* !CONFIG_PM */
3986
3987#define RTL8169_PM_OPS NULL
3988
3989#endif /* !CONFIG_PM */
3990
1765f95d
FR		 3991static void rtl_shutdown(struct pci_dev *pdev)
3992{
861ab440 3993 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 3994 struct rtl8169_private *tp = netdev_priv(dev);
3995 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 3996
3997 rtl8169_net_suspend(dev);
1765f95d 3998
4bb3f522 3999 spin_lock_irq(&tp->lock);
4000
4001 rtl8169_asic_down(ioaddr);
4002
4003 spin_unlock_irq(&tp->lock);
4004
861ab440 4005 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4006 /* WoL fails with some 8168 when the receiver is disabled. */
4007 if (tp->features & RTL_FEATURE_WOL) {
4008 pci_clear_master(pdev);
4009
4010 RTL_W8(ChipCmd, CmdRxEnb);
4011 /* PCI commit */
4012 RTL_R8(ChipCmd);
4013 }
4014
861ab440
RW		 4015 pci_wake_from_d3(pdev, true);
4016 pci_set_power_state(pdev, PCI_D3hot);
4017 }
4018}
5d06a99f 4019
1da177e4
LT		 4020static struct pci_driver rtl8169_pci_driver = {
4021 .name = MODULENAME,
4022 .id_table = rtl8169_pci_tbl,
4023 .probe = rtl8169_init_one,
4024 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4025 .shutdown = rtl_shutdown,
861ab440 4026 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4027};
4028
07d3f51f 4029static int __init rtl8169_init_module(void)
1da177e4 4030{
29917620 4031 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4032}
4033
07d3f51f 4034static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4035{
4036 pci_unregister_driver(&rtl8169_pci_driver);
4037}
4038
4039module_init(rtl8169_init_module);
4040module_exit(rtl8169_cleanup_module);
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