]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/r8169.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ibmtr: possible Read buffer overflow?
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4
LT		 54/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 56static const int multicast_filter_limit = 32;
1da177e4
LT		 57
58/* MAC address length */
59#define MAC_ADDR_LEN 6
60
9c14ceaf 61#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 62#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 65#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 66#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_NAPI_WEIGHT 64
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77#define RTL8169_TX_TIMEOUT (6*HZ)
78#define RTL8169_PHY_TIMEOUT (10*HZ)
79
ea8dbdd1 80#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 82#define RTL_EEPROM_SIG_ADDR 0x0000
83
1da177e4
LT		 84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
f21b75e9 93 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 121};
122
1da177e4
LT		 123#define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
3c6bee1d 126static const struct {
1da177e4
LT		 127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130} rtl_chip_info[] = {
ba6eb6ee
FR		 131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 158};
159#undef _R
160
bcf0bf90
FR		 161enum cfg_version {
162 RTL_CFG_0 = 0x00,
163 RTL_CFG_1,
164 RTL_CFG_2
165};
166
07ce4064
FR		 167static void rtl_hw_start_8169(struct net_device *);
168static void rtl_hw_start_8168(struct net_device *);
169static void rtl_hw_start_8101(struct net_device *);
170
1da177e4 171static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 182 { 0x0001, 0x8168,
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 184 {0,},
185};
186
187MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
189static int rx_copybreak = 200;
190static int use_dac;
b57b7e5a
SH		 191static struct {
192 u32 msg_enable;
193} debug = { -1 };
1da177e4 194
07d3f51f
FR		 195enum rtl_registers {
196 MAC0 = 0, /* Ethernet hardware address. */
773d2021 197 MAC4 = 4,
07d3f51f
FR		 198 MAR0 = 8, /* Multicast filter. */
199 CounterAddrLow = 0x10,
200 CounterAddrHigh = 0x14,
201 TxDescStartAddrLow = 0x20,
202 TxDescStartAddrHigh = 0x24,
203 TxHDescStartAddrLow = 0x28,
204 TxHDescStartAddrHigh = 0x2c,
205 FLASH = 0x30,
206 ERSR = 0x36,
207 ChipCmd = 0x37,
208 TxPoll = 0x38,
209 IntrMask = 0x3c,
210 IntrStatus = 0x3e,
211 TxConfig = 0x40,
212 RxConfig = 0x44,
213 RxMissed = 0x4c,
214 Cfg9346 = 0x50,
215 Config0 = 0x51,
216 Config1 = 0x52,
217 Config2 = 0x53,
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 MultiIntr = 0x5c,
222 PHYAR = 0x60,
07d3f51f
FR		 223 PHYstatus = 0x6c,
224 RxMaxSize = 0xda,
225 CPlusCmd = 0xe0,
226 IntrMitigate = 0xe2,
227 RxDescAddrLow = 0xe4,
228 RxDescAddrHigh = 0xe8,
229 EarlyTxThres = 0xec,
230 FuncEvent = 0xf0,
231 FuncEventMask = 0xf4,
232 FuncPresetState = 0xf8,
233 FuncForceEvent = 0xfc,
1da177e4
LT		 234};
235
f162a5d1
FR		 236enum rtl8110_registers {
237 TBICSR = 0x64,
238 TBI_ANAR = 0x68,
239 TBI_LPAR = 0x6a,
240};
241
242enum rtl8168_8101_registers {
243 CSIDR = 0x64,
244 CSIAR = 0x68,
245#define CSIAR_FLAG 0x80000000
246#define CSIAR_WRITE_CMD 0x80000000
247#define CSIAR_BYTE_ENABLE 0x0f
248#define CSIAR_BYTE_ENABLE_SHIFT 12
249#define CSIAR_ADDR_MASK 0x0fff
250
251 EPHYAR = 0x80,
252#define EPHYAR_FLAG 0x80000000
253#define EPHYAR_WRITE_CMD 0x80000000
254#define EPHYAR_REG_MASK 0x1f
255#define EPHYAR_REG_SHIFT 16
256#define EPHYAR_DATA_MASK 0xffff
257 DBG_REG = 0xd1,
258#define FIX_NAK_1 (1 << 4)
259#define FIX_NAK_2 (1 << 3)
daf9df6d 260 EFUSEAR = 0xdc,
261#define EFUSEAR_FLAG 0x80000000
262#define EFUSEAR_WRITE_CMD 0x80000000
263#define EFUSEAR_READ_CMD 0x00000000
264#define EFUSEAR_REG_MASK 0x03ff
265#define EFUSEAR_REG_SHIFT 8
266#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 267};
268
07d3f51f 269enum rtl_register_content {
1da177e4 270 /* InterruptStatusBits */
07d3f51f
FR		 271 SYSErr = 0x8000,
272 PCSTimeout = 0x4000,
273 SWInt = 0x0100,
274 TxDescUnavail = 0x0080,
275 RxFIFOOver = 0x0040,
276 LinkChg = 0x0020,
277 RxOverflow = 0x0010,
278 TxErr = 0x0008,
279 TxOK = 0x0004,
280 RxErr = 0x0002,
281 RxOK = 0x0001,
1da177e4
LT		 282
283 /* RxStatusDesc */
9dccf611
FR		 284 RxFOVF = (1 << 23),
285 RxRWT = (1 << 22),
286 RxRES = (1 << 21),
287 RxRUNT = (1 << 20),
288 RxCRC = (1 << 19),
1da177e4
LT		 289
290 /* ChipCmdBits */
07d3f51f
FR		 291 CmdReset = 0x10,
292 CmdRxEnb = 0x08,
293 CmdTxEnb = 0x04,
294 RxBufEmpty = 0x01,
1da177e4 295
275391a4
FR		 296 /* TXPoll register p.5 */
297 HPQ = 0x80, /* Poll cmd on the high prio queue */
298 NPQ = 0x40, /* Poll cmd on the low prio queue */
299 FSWInt = 0x01, /* Forced software interrupt */
300
1da177e4 301 /* Cfg9346Bits */
07d3f51f
FR		 302 Cfg9346_Lock = 0x00,
303 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 304
305 /* rx_mode_bits */
07d3f51f
FR		 306 AcceptErr = 0x20,
307 AcceptRunt = 0x10,
308 AcceptBroadcast = 0x08,
309 AcceptMulticast = 0x04,
310 AcceptMyPhys = 0x02,
311 AcceptAllPhys = 0x01,
1da177e4
LT		 312
313 /* RxConfigBits */
07d3f51f
FR		 314 RxCfgFIFOShift = 13,
315 RxCfgDMAShift = 8,
1da177e4
LT		 316
317 /* TxConfigBits */
318 TxInterFrameGapShift = 24,
319 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
320
5d06a99f 321 /* Config1 register p.24 */
f162a5d1
FR		 322 LEDS1 = (1 << 7),
323 LEDS0 = (1 << 6),
fbac58fc 324 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 325 Speed_down = (1 << 4),
326 MEMMAP = (1 << 3),
327 IOMAP = (1 << 2),
328 VPD = (1 << 1),
5d06a99f
FR		 329 PMEnable = (1 << 0), /* Power Management Enable */
330
6dccd16b
FR		 331 /* Config2 register p. 25 */
332 PCI_Clock_66MHz = 0x01,
333 PCI_Clock_33MHz = 0x00,
334
61a4dcc2
FR		 335 /* Config3 register p.25 */
336 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
337 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 338 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 339
5d06a99f 340 /* Config5 register p.27 */
61a4dcc2
FR		 341 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
342 MWF = (1 << 5), /* Accept Multicast wakeup frame */
343 UWF = (1 << 4), /* Accept Unicast wakeup frame */
344 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 345 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
346
1da177e4
LT		 347 /* TBICSR p.28 */
348 TBIReset = 0x80000000,
349 TBILoopback = 0x40000000,
350 TBINwEnable = 0x20000000,
351 TBINwRestart = 0x10000000,
352 TBILinkOk = 0x02000000,
353 TBINwComplete = 0x01000000,
354
355 /* CPlusCmd p.31 */
f162a5d1
FR		 356 EnableBist = (1 << 15), // 8168 8101
357 Mac_dbgo_oe = (1 << 14), // 8168 8101
358 Normal_mode = (1 << 13), // unused
359 Force_half_dup = (1 << 12), // 8168 8101
360 Force_rxflow_en = (1 << 11), // 8168 8101
361 Force_txflow_en = (1 << 10), // 8168 8101
362 Cxpl_dbg_sel = (1 << 9), // 8168 8101
363 ASF = (1 << 8), // 8168 8101
364 PktCntrDisable = (1 << 7), // 8168 8101
365 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 366 RxVlan = (1 << 6),
367 RxChkSum = (1 << 5),
368 PCIDAC = (1 << 4),
369 PCIMulRW = (1 << 3),
0e485150
FR		 370 INTT_0 = 0x0000, // 8168
371 INTT_1 = 0x0001, // 8168
372 INTT_2 = 0x0002, // 8168
373 INTT_3 = 0x0003, // 8168
1da177e4
LT		 374
375 /* rtl8169_PHYstatus */
07d3f51f
FR		 376 TBI_Enable = 0x80,
377 TxFlowCtrl = 0x40,
378 RxFlowCtrl = 0x20,
379 _1000bpsF = 0x10,
380 _100bps = 0x08,
381 _10bps = 0x04,
382 LinkStatus = 0x02,
383 FullDup = 0x01,
1da177e4 384
1da177e4 385 /* _TBICSRBit */
07d3f51f 386 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 387
388 /* DumpCounterCommand */
07d3f51f 389 CounterDump = 0x8,
1da177e4
LT		 390};
391
07d3f51f 392enum desc_status_bit {
1da177e4
LT		 393 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
394 RingEnd = (1 << 30), /* End of descriptor ring */
395 FirstFrag = (1 << 29), /* First segment of a packet */
396 LastFrag = (1 << 28), /* Final segment of a packet */
397
398 /* Tx private */
399 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
400 MSSShift = 16, /* MSS value position */
401 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
402 IPCS = (1 << 18), /* Calculate IP checksum */
403 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
404 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
405 TxVlanTag = (1 << 17), /* Add VLAN tag */
406
407 /* Rx private */
408 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
409 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
410
411#define RxProtoUDP (PID1)
412#define RxProtoTCP (PID0)
413#define RxProtoIP (PID1 | PID0)
414#define RxProtoMask RxProtoIP
415
416 IPFail = (1 << 16), /* IP checksum failed */
417 UDPFail = (1 << 15), /* UDP/IP checksum failed */
418 TCPFail = (1 << 14), /* TCP/IP checksum failed */
419 RxVlanTag = (1 << 16), /* VLAN tag available */
420};
421
422#define RsvdMask 0x3fffc000
423
424struct TxDesc {
6cccd6e7
REB		 425 __le32 opts1;
426 __le32 opts2;
427 __le64 addr;
1da177e4
LT		 428};
429
430struct RxDesc {
6cccd6e7
REB		 431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
1da177e4
LT		 434};
435
436struct ring_info {
437 struct sk_buff *skb;
438 u32 len;
439 u8 __pad[sizeof(void *) - sizeof(u32)];
440};
441
f23e7fda 442enum features {
ccdffb9a
FR		 443 RTL_FEATURE_WOL = (1 << 0),
444 RTL_FEATURE_MSI = (1 << 1),
445 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 446};
447
355423d0
IV		 448struct rtl8169_counters {
449 __le64 tx_packets;
450 __le64 rx_packets;
451 __le64 tx_errors;
452 __le32 rx_errors;
453 __le16 rx_missed;
454 __le16 align_errors;
455 __le32 tx_one_collision;
456 __le32 tx_multi_collision;
457 __le64 rx_unicast;
458 __le64 rx_broadcast;
459 __le32 rx_multicast;
460 __le16 tx_aborted;
461 __le16 tx_underun;
462};
463
1da177e4
LT		 464struct rtl8169_private {
465 void __iomem *mmio_addr; /* memory map physical address */
466 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 467 struct net_device *dev;
bea3348e 468 struct napi_struct napi;
1da177e4 469 spinlock_t lock; /* spin lock flag */
b57b7e5a 470 u32 msg_enable;
1da177e4
LT		 471 int chipset;
472 int mac_version;
1da177e4
LT		 473 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
474 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
475 u32 dirty_rx;
476 u32 dirty_tx;
477 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
478 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
479 dma_addr_t TxPhyAddr;
480 dma_addr_t RxPhyAddr;
481 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
482 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 483 unsigned align;
1da177e4
LT		 484 unsigned rx_buf_sz;
485 struct timer_list timer;
486 u16 cp_cmd;
0e485150
FR		 487 u16 intr_event;
488 u16 napi_event;
1da177e4 489 u16 intr_mask;
1da177e4
LT		 490 int phy_1000_ctrl_reg;
491#ifdef CONFIG_R8169_VLAN
492 struct vlan_group *vlgrp;
493#endif
494 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 495 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 496 void (*phy_reset_enable)(void __iomem *);
07ce4064 497 void (*hw_start)(struct net_device *);
1da177e4
LT		 498 unsigned int (*phy_reset_pending)(void __iomem *);
499 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 500 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 501 int pcie_cap;
c4028958 502 struct delayed_work task;
f23e7fda 503 unsigned features;
ccdffb9a
FR		 504
505 struct mii_if_info mii;
355423d0 506 struct rtl8169_counters counters;
1da177e4
LT		 507};
508
979b6c13 509MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 510MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 511module_param(rx_copybreak, int, 0);
1b7efd58 512MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 513module_param(use_dac, int, 0);
514MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 515module_param_named(debug, debug.msg_enable, int, 0);
516MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 517MODULE_LICENSE("GPL");
518MODULE_VERSION(RTL8169_VERSION);
519
520static int rtl8169_open(struct net_device *dev);
61357325
SH		 521static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
522 struct net_device *dev);
7d12e780 523static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 524static int rtl8169_init_ring(struct net_device *dev);
07ce4064 525static void rtl_hw_start(struct net_device *dev);
1da177e4 526static int rtl8169_close(struct net_device *dev);
07ce4064 527static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 528static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 529static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 530static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 531 void __iomem *, u32 budget);
4dcb7d33 532static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 533static void rtl8169_down(struct net_device *dev);
99f252b0 534static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 535static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 536
1da177e4 537static const unsigned int rtl8169_rx_config =
5b0384f4 538 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 539
07d3f51f 540static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 541{
542 int i;
543
a6baf3af 544 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 545
2371408c 546 for (i = 20; i > 0; i--) {
07d3f51f
FR		 547 /*
548 * Check if the RTL8169 has completed writing to the specified
549 * MII register.
550 */
5b0384f4 551 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 552 break;
2371408c 553 udelay(25);
1da177e4
LT		 554 }
555}
556
07d3f51f 557static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 558{
559 int i, value = -1;
560
a6baf3af 561 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 562
2371408c 563 for (i = 20; i > 0; i--) {
07d3f51f
FR		 564 /*
565 * Check if the RTL8169 has completed retrieving data from
566 * the specified MII register.
567 */
1da177e4 568 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 569 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 570 break;
571 }
2371408c 572 udelay(25);
1da177e4
LT		 573 }
574 return value;
575}
576
dacf8154
FR		 577static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
578{
579 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
580}
581
daf9df6d 582static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
583{
584 int val;
585
586 val = mdio_read(ioaddr, reg_addr);
587 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
588}
589
ccdffb9a
FR		 590static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
591 int val)
592{
593 struct rtl8169_private *tp = netdev_priv(dev);
594 void __iomem *ioaddr = tp->mmio_addr;
595
596 mdio_write(ioaddr, location, val);
597}
598
599static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
600{
601 struct rtl8169_private *tp = netdev_priv(dev);
602 void __iomem *ioaddr = tp->mmio_addr;
603
604 return mdio_read(ioaddr, location);
605}
606
dacf8154
FR		 607static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
608{
609 unsigned int i;
610
611 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
612 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
613
614 for (i = 0; i < 100; i++) {
615 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
616 break;
617 udelay(10);
618 }
619}
620
621static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
622{
623 u16 value = 0xffff;
624 unsigned int i;
625
626 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
627
628 for (i = 0; i < 100; i++) {
629 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
630 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
631 break;
632 }
633 udelay(10);
634 }
635
636 return value;
637}
638
639static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
640{
641 unsigned int i;
642
643 RTL_W32(CSIDR, value);
644 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
645 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
646
647 for (i = 0; i < 100; i++) {
648 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
649 break;
650 udelay(10);
651 }
652}
653
654static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
655{
656 u32 value = ~0x00;
657 unsigned int i;
658
659 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
660 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
661
662 for (i = 0; i < 100; i++) {
663 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
664 value = RTL_R32(CSIDR);
665 break;
666 }
667 udelay(10);
668 }
669
670 return value;
671}
672
daf9df6d 673static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
674{
675 u8 value = 0xff;
676 unsigned int i;
677
678 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
679
680 for (i = 0; i < 300; i++) {
681 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
682 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
683 break;
684 }
685 udelay(100);
686 }
687
688 return value;
689}
690
1da177e4
LT		 691static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
692{
693 RTL_W16(IntrMask, 0x0000);
694
695 RTL_W16(IntrStatus, 0xffff);
696}
697
698static void rtl8169_asic_down(void __iomem *ioaddr)
699{
700 RTL_W8(ChipCmd, 0x00);
701 rtl8169_irq_mask_and_ack(ioaddr);
702 RTL_R16(CPlusCmd);
703}
704
705static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
706{
707 return RTL_R32(TBICSR) & TBIReset;
708}
709
710static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
711{
64e4bfb4 712 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 713}
714
715static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
716{
717 return RTL_R32(TBICSR) & TBILinkOk;
718}
719
720static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
721{
722 return RTL_R8(PHYstatus) & LinkStatus;
723}
724
725static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
726{
727 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
728}
729
730static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
731{
732 unsigned int val;
733
9e0db8ef
FR		 734 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
735 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 736}
737
738static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 739 struct rtl8169_private *tp,
740 void __iomem *ioaddr)
1da177e4
LT		 741{
742 unsigned long flags;
743
744 spin_lock_irqsave(&tp->lock, flags);
745 if (tp->link_ok(ioaddr)) {
746 netif_carrier_on(dev);
b57b7e5a
SH		 747 if (netif_msg_ifup(tp))
748 printk(KERN_INFO PFX "%s: link up\n", dev->name);
749 } else {
750 if (netif_msg_ifdown(tp))
751 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 752 netif_carrier_off(dev);
b57b7e5a 753 }
1da177e4
LT		 754 spin_unlock_irqrestore(&tp->lock, flags);
755}
756
61a4dcc2
FR		 757static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 void __iomem *ioaddr = tp->mmio_addr;
761 u8 options;
762
763 wol->wolopts = 0;
764
765#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
766 wol->supported = WAKE_ANY;
767
768 spin_lock_irq(&tp->lock);
769
770 options = RTL_R8(Config1);
771 if (!(options & PMEnable))
772 goto out_unlock;
773
774 options = RTL_R8(Config3);
775 if (options & LinkUp)
776 wol->wolopts |= WAKE_PHY;
777 if (options & MagicPacket)
778 wol->wolopts |= WAKE_MAGIC;
779
780 options = RTL_R8(Config5);
781 if (options & UWF)
782 wol->wolopts |= WAKE_UCAST;
783 if (options & BWF)
5b0384f4 784 wol->wolopts |= WAKE_BCAST;
61a4dcc2 785 if (options & MWF)
5b0384f4 786 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 787
788out_unlock:
789 spin_unlock_irq(&tp->lock);
790}
791
792static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
793{
794 struct rtl8169_private *tp = netdev_priv(dev);
795 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 796 unsigned int i;
61a4dcc2
FR		 797 static struct {
798 u32 opt;
799 u16 reg;
800 u8 mask;
801 } cfg[] = {
802 { WAKE_ANY, Config1, PMEnable },
803 { WAKE_PHY, Config3, LinkUp },
804 { WAKE_MAGIC, Config3, MagicPacket },
805 { WAKE_UCAST, Config5, UWF },
806 { WAKE_BCAST, Config5, BWF },
807 { WAKE_MCAST, Config5, MWF },
808 { WAKE_ANY, Config5, LanWake }
809 };
810
811 spin_lock_irq(&tp->lock);
812
813 RTL_W8(Cfg9346, Cfg9346_Unlock);
814
815 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
816 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
817 if (wol->wolopts & cfg[i].opt)
818 options |= cfg[i].mask;
819 RTL_W8(cfg[i].reg, options);
820 }
821
822 RTL_W8(Cfg9346, Cfg9346_Lock);
823
f23e7fda
FR		 824 if (wol->wolopts)
825 tp->features |= RTL_FEATURE_WOL;
826 else
827 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 828 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 829
830 spin_unlock_irq(&tp->lock);
831
832 return 0;
833}
834
1da177e4
LT		 835static void rtl8169_get_drvinfo(struct net_device *dev,
836 struct ethtool_drvinfo *info)
837{
838 struct rtl8169_private *tp = netdev_priv(dev);
839
840 strcpy(info->driver, MODULENAME);
841 strcpy(info->version, RTL8169_VERSION);
842 strcpy(info->bus_info, pci_name(tp->pci_dev));
843}
844
845static int rtl8169_get_regs_len(struct net_device *dev)
846{
847 return R8169_REGS_SIZE;
848}
849
850static int rtl8169_set_speed_tbi(struct net_device *dev,
851 u8 autoneg, u16 speed, u8 duplex)
852{
853 struct rtl8169_private *tp = netdev_priv(dev);
854 void __iomem *ioaddr = tp->mmio_addr;
855 int ret = 0;
856 u32 reg;
857
858 reg = RTL_R32(TBICSR);
859 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
860 (duplex == DUPLEX_FULL)) {
861 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
862 } else if (autoneg == AUTONEG_ENABLE)
863 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
864 else {
b57b7e5a
SH		 865 if (netif_msg_link(tp)) {
866 printk(KERN_WARNING "%s: "
867 "incorrect speed setting refused in TBI mode\n",
868 dev->name);
869 }
1da177e4
LT		 870 ret = -EOPNOTSUPP;
871 }
872
873 return ret;
874}
875
876static int rtl8169_set_speed_xmii(struct net_device *dev,
877 u8 autoneg, u16 speed, u8 duplex)
878{
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 881 int giga_ctrl, bmcr;
1da177e4
LT		 882
883 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 884 int auto_nego;
885
886 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 887 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
888 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 889 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 890
3577aa1b 891 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
892 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 893
3577aa1b 894 /* The 8100e/8101e/8102e do Fast Ethernet only. */
895 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
898 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
899 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
900 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
901 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
902 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
903 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
904 } else if (netif_msg_link(tp)) {
bcf0bf90
FR		 905 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
906 dev->name);
907 }
1da177e4 908
3577aa1b 909 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
910
911 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
912 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
913 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
914 /*
915 * Wake up the PHY.
916 * Vendor specific (0x1f) and reserved (0x0e) MII
917 * registers.
918 */
919 mdio_write(ioaddr, 0x1f, 0x0000);
920 mdio_write(ioaddr, 0x0e, 0x0000);
921 }
922
923 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
924 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
925 } else {
926 giga_ctrl = 0;
927
928 if (speed == SPEED_10)
929 bmcr = 0;
930 else if (speed == SPEED_100)
931 bmcr = BMCR_SPEED100;
932 else
933 return -EINVAL;
934
935 if (duplex == DUPLEX_FULL)
936 bmcr |= BMCR_FULLDPLX;
623a1593 937
2584fbc3 938 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 939 }
940
1da177e4
LT		 941 tp->phy_1000_ctrl_reg = giga_ctrl;
942
3577aa1b 943 mdio_write(ioaddr, MII_BMCR, bmcr);
944
945 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
946 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
947 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
948 mdio_write(ioaddr, 0x17, 0x2138);
949 mdio_write(ioaddr, 0x0e, 0x0260);
950 } else {
951 mdio_write(ioaddr, 0x17, 0x2108);
952 mdio_write(ioaddr, 0x0e, 0x0000);
953 }
954 }
955
1da177e4
LT		 956 return 0;
957}
958
959static int rtl8169_set_speed(struct net_device *dev,
960 u8 autoneg, u16 speed, u8 duplex)
961{
962 struct rtl8169_private *tp = netdev_priv(dev);
963 int ret;
964
965 ret = tp->set_speed(dev, autoneg, speed, duplex);
966
64e4bfb4 967 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 968 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
969
970 return ret;
971}
972
973static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
974{
975 struct rtl8169_private *tp = netdev_priv(dev);
976 unsigned long flags;
977 int ret;
978
979 spin_lock_irqsave(&tp->lock, flags);
980 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
981 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 982
1da177e4
LT		 983 return ret;
984}
985
986static u32 rtl8169_get_rx_csum(struct net_device *dev)
987{
988 struct rtl8169_private *tp = netdev_priv(dev);
989
990 return tp->cp_cmd & RxChkSum;
991}
992
993static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
994{
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
997 unsigned long flags;
998
999 spin_lock_irqsave(&tp->lock, flags);
1000
1001 if (data)
1002 tp->cp_cmd |= RxChkSum;
1003 else
1004 tp->cp_cmd &= ~RxChkSum;
1005
1006 RTL_W16(CPlusCmd, tp->cp_cmd);
1007 RTL_R16(CPlusCmd);
1008
1009 spin_unlock_irqrestore(&tp->lock, flags);
1010
1011 return 0;
1012}
1013
1014#ifdef CONFIG_R8169_VLAN
1015
1016static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1017 struct sk_buff *skb)
1018{
1019 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1020 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1021}
1022
1023static void rtl8169_vlan_rx_register(struct net_device *dev,
1024 struct vlan_group *grp)
1025{
1026 struct rtl8169_private *tp = netdev_priv(dev);
1027 void __iomem *ioaddr = tp->mmio_addr;
1028 unsigned long flags;
1029
1030 spin_lock_irqsave(&tp->lock, flags);
1031 tp->vlgrp = grp;
05af2142
SW		 1032 /*
1033 * Do not disable RxVlan on 8110SCd.
1034 */
1035 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1036 tp->cp_cmd |= RxVlan;
1037 else
1038 tp->cp_cmd &= ~RxVlan;
1039 RTL_W16(CPlusCmd, tp->cp_cmd);
1040 RTL_R16(CPlusCmd);
1041 spin_unlock_irqrestore(&tp->lock, flags);
1042}
1043
1da177e4
LT		 1044static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1045 struct sk_buff *skb)
1046{
1047 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1048 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1049 int ret;
1050
865c652d
FR		 1051 if (vlgrp && (opts2 & RxVlanTag)) {
1052 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1053 ret = 0;
1054 } else
1055 ret = -1;
1056 desc->opts2 = 0;
1057 return ret;
1058}
1059
1060#else /* !CONFIG_R8169_VLAN */
1061
1062static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1063 struct sk_buff *skb)
1064{
1065 return 0;
1066}
1067
1068static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1069 struct sk_buff *skb)
1070{
1071 return -1;
1072}
1073
1074#endif
1075
ccdffb9a 1076static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1077{
1078 struct rtl8169_private *tp = netdev_priv(dev);
1079 void __iomem *ioaddr = tp->mmio_addr;
1080 u32 status;
1081
1082 cmd->supported =
1083 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1084 cmd->port = PORT_FIBRE;
1085 cmd->transceiver = XCVR_INTERNAL;
1086
1087 status = RTL_R32(TBICSR);
1088 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1089 cmd->autoneg = !!(status & TBINwEnable);
1090
1091 cmd->speed = SPEED_1000;
1092 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1093
1094 return 0;
1da177e4
LT		 1095}
1096
ccdffb9a 1097static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1098{
1099 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1100
1101 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1102}
1103
1104static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1105{
1106 struct rtl8169_private *tp = netdev_priv(dev);
1107 unsigned long flags;
ccdffb9a 1108 int rc;
1da177e4
LT		 1109
1110 spin_lock_irqsave(&tp->lock, flags);
1111
ccdffb9a 1112 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1113
1114 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1115 return rc;
1da177e4
LT		 1116}
1117
1118static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1119 void *p)
1120{
5b0384f4
FR		 1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 unsigned long flags;
1da177e4 1123
5b0384f4
FR		 1124 if (regs->len > R8169_REGS_SIZE)
1125 regs->len = R8169_REGS_SIZE;
1da177e4 1126
5b0384f4
FR		 1127 spin_lock_irqsave(&tp->lock, flags);
1128 memcpy_fromio(p, tp->mmio_addr, regs->len);
1129 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1130}
1131
b57b7e5a
SH		 1132static u32 rtl8169_get_msglevel(struct net_device *dev)
1133{
1134 struct rtl8169_private *tp = netdev_priv(dev);
1135
1136 return tp->msg_enable;
1137}
1138
1139static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1140{
1141 struct rtl8169_private *tp = netdev_priv(dev);
1142
1143 tp->msg_enable = value;
1144}
1145
d4a3a0fc
SH		 1146static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1147 "tx_packets",
1148 "rx_packets",
1149 "tx_errors",
1150 "rx_errors",
1151 "rx_missed",
1152 "align_errors",
1153 "tx_single_collisions",
1154 "tx_multi_collisions",
1155 "unicast",
1156 "broadcast",
1157 "multicast",
1158 "tx_aborted",
1159 "tx_underrun",
1160};
1161
b9f2c044 1162static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1163{
b9f2c044
JG		 1164 switch (sset) {
1165 case ETH_SS_STATS:
1166 return ARRAY_SIZE(rtl8169_gstrings);
1167 default:
1168 return -EOPNOTSUPP;
1169 }
d4a3a0fc
SH		 1170}
1171
355423d0 1172static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1173{
1174 struct rtl8169_private *tp = netdev_priv(dev);
1175 void __iomem *ioaddr = tp->mmio_addr;
1176 struct rtl8169_counters *counters;
1177 dma_addr_t paddr;
1178 u32 cmd;
355423d0 1179 int wait = 1000;
d4a3a0fc 1180
355423d0
IV		 1181 /*
1182 * Some chips are unable to dump tally counters when the receiver
1183 * is disabled.
1184 */
1185 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1186 return;
d4a3a0fc
SH		 1187
1188 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1189 if (!counters)
1190 return;
1191
1192 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1193 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1194 RTL_W32(CounterAddrLow, cmd);
1195 RTL_W32(CounterAddrLow, cmd | CounterDump);
1196
355423d0
IV		 1197 while (wait--) {
1198 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1199 /* copy updated counters */
1200 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1201 break;
355423d0
IV		 1202 }
1203 udelay(10);
d4a3a0fc
SH		 1204 }
1205
1206 RTL_W32(CounterAddrLow, 0);
1207 RTL_W32(CounterAddrHigh, 0);
1208
d4a3a0fc
SH		 1209 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1210}
1211
355423d0
IV		 1212static void rtl8169_get_ethtool_stats(struct net_device *dev,
1213 struct ethtool_stats *stats, u64 *data)
1214{
1215 struct rtl8169_private *tp = netdev_priv(dev);
1216
1217 ASSERT_RTNL();
1218
1219 rtl8169_update_counters(dev);
1220
1221 data[0] = le64_to_cpu(tp->counters.tx_packets);
1222 data[1] = le64_to_cpu(tp->counters.rx_packets);
1223 data[2] = le64_to_cpu(tp->counters.tx_errors);
1224 data[3] = le32_to_cpu(tp->counters.rx_errors);
1225 data[4] = le16_to_cpu(tp->counters.rx_missed);
1226 data[5] = le16_to_cpu(tp->counters.align_errors);
1227 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1228 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1229 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1230 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1231 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1232 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1233 data[12] = le16_to_cpu(tp->counters.tx_underun);
1234}
1235
d4a3a0fc
SH		 1236static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1237{
1238 switch(stringset) {
1239 case ETH_SS_STATS:
1240 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1241 break;
1242 }
1243}
1244
7282d491 1245static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1246 .get_drvinfo = rtl8169_get_drvinfo,
1247 .get_regs_len = rtl8169_get_regs_len,
1248 .get_link = ethtool_op_get_link,
1249 .get_settings = rtl8169_get_settings,
1250 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1251 .get_msglevel = rtl8169_get_msglevel,
1252 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1253 .get_rx_csum = rtl8169_get_rx_csum,
1254 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1255 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1256 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1257 .set_tso = ethtool_op_set_tso,
1258 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1259 .get_wol = rtl8169_get_wol,
1260 .set_wol = rtl8169_set_wol,
d4a3a0fc 1261 .get_strings = rtl8169_get_strings,
b9f2c044 1262 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1263 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1264};
1265
07d3f51f
FR		 1266static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1267 void __iomem *ioaddr)
1da177e4 1268{
0e485150
FR		 1269 /*
1270 * The driver currently handles the 8168Bf and the 8168Be identically
1271 * but they can be identified more specifically through the test below
1272 * if needed:
1273 *
1274 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1275 *
1276 * Same thing for the 8101Eb and the 8101Ec:
1277 *
1278 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1279 */
1da177e4
LT		 1280 const struct {
1281 u32 mask;
e3cf0cc0 1282 u32 val;
1da177e4
LT		 1283 int mac_version;
1284 } mac_info[] = {
5b538df9 1285 /* 8168D family. */
daf9df6d 1286 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1287 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1288 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1289 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1290
ef808d50 1291 /* 8168C family. */
7f3e3d3a 1292 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1293 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1294 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1295 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1296 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1297 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1298 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1299 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1300 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1301
1302 /* 8168B family. */
1303 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1304 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1305 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1306 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1307
1308 /* 8101 family. */
2857ffb7
FR		 1309 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1310 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1311 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1312 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1313 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1314 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1315 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1316 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1317 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1318 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1319 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1320 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1321 /* FIXME: where did these entries come from ? -- FR */
1322 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1323 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1324
1325 /* 8110 family. */
1326 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1327 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1328 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1329 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1330 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1331 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1332
f21b75e9
JD		 1333 /* Catch-all */
1334 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1335 }, *p = mac_info;
1336 u32 reg;
1337
e3cf0cc0
FR		 1338 reg = RTL_R32(TxConfig);
1339 while ((reg & p->mask) != p->val)
1da177e4
LT		 1340 p++;
1341 tp->mac_version = p->mac_version;
1342}
1343
1344static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1345{
bcf0bf90 1346 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1347}
1348
867763c1
FR		 1349struct phy_reg {
1350 u16 reg;
1351 u16 val;
1352};
1353
1354static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1355{
1356 while (len-- > 0) {
1357 mdio_write(ioaddr, regs->reg, regs->val);
1358 regs++;
1359 }
1360}
1361
5615d9f1 1362static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1363{
0b9b571d 1364 struct phy_reg phy_reg_init[] = {
1365 { 0x1f, 0x0001 },
1366 { 0x06, 0x006e },
1367 { 0x08, 0x0708 },
1368 { 0x15, 0x4000 },
1369 { 0x18, 0x65c7 },
1da177e4 1370
0b9b571d 1371 { 0x1f, 0x0001 },
1372 { 0x03, 0x00a1 },
1373 { 0x02, 0x0008 },
1374 { 0x01, 0x0120 },
1375 { 0x00, 0x1000 },
1376 { 0x04, 0x0800 },
1377 { 0x04, 0x0000 },
1da177e4 1378
0b9b571d 1379 { 0x03, 0xff41 },
1380 { 0x02, 0xdf60 },
1381 { 0x01, 0x0140 },
1382 { 0x00, 0x0077 },
1383 { 0x04, 0x7800 },
1384 { 0x04, 0x7000 },
1385
1386 { 0x03, 0x802f },
1387 { 0x02, 0x4f02 },
1388 { 0x01, 0x0409 },
1389 { 0x00, 0xf0f9 },
1390 { 0x04, 0x9800 },
1391 { 0x04, 0x9000 },
1392
1393 { 0x03, 0xdf01 },
1394 { 0x02, 0xdf20 },
1395 { 0x01, 0xff95 },
1396 { 0x00, 0xba00 },
1397 { 0x04, 0xa800 },
1398 { 0x04, 0xa000 },
1399
1400 { 0x03, 0xff41 },
1401 { 0x02, 0xdf20 },
1402 { 0x01, 0x0140 },
1403 { 0x00, 0x00bb },
1404 { 0x04, 0xb800 },
1405 { 0x04, 0xb000 },
1406
1407 { 0x03, 0xdf41 },
1408 { 0x02, 0xdc60 },
1409 { 0x01, 0x6340 },
1410 { 0x00, 0x007d },
1411 { 0x04, 0xd800 },
1412 { 0x04, 0xd000 },
1413
1414 { 0x03, 0xdf01 },
1415 { 0x02, 0xdf20 },
1416 { 0x01, 0x100a },
1417 { 0x00, 0xa0ff },
1418 { 0x04, 0xf800 },
1419 { 0x04, 0xf000 },
1420
1421 { 0x1f, 0x0000 },
1422 { 0x0b, 0x0000 },
1423 { 0x00, 0x9200 }
1424 };
1da177e4 1425
0b9b571d 1426 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1427}
1428
5615d9f1
FR		 1429static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1430{
a441d7b6
FR		 1431 struct phy_reg phy_reg_init[] = {
1432 { 0x1f, 0x0002 },
1433 { 0x01, 0x90d0 },
1434 { 0x1f, 0x0000 }
1435 };
1436
1437 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1438}
1439
2e955856 1440static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1441 void __iomem *ioaddr)
1442{
1443 struct pci_dev *pdev = tp->pci_dev;
1444 u16 vendor_id, device_id;
1445
1446 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1447 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1448
1449 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1450 return;
1451
1452 mdio_write(ioaddr, 0x1f, 0x0001);
1453 mdio_write(ioaddr, 0x10, 0xf01b);
1454 mdio_write(ioaddr, 0x1f, 0x0000);
1455}
1456
1457static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1458 void __iomem *ioaddr)
1459{
1460 struct phy_reg phy_reg_init[] = {
1461 { 0x1f, 0x0001 },
1462 { 0x04, 0x0000 },
1463 { 0x03, 0x00a1 },
1464 { 0x02, 0x0008 },
1465 { 0x01, 0x0120 },
1466 { 0x00, 0x1000 },
1467 { 0x04, 0x0800 },
1468 { 0x04, 0x9000 },
1469 { 0x03, 0x802f },
1470 { 0x02, 0x4f02 },
1471 { 0x01, 0x0409 },
1472 { 0x00, 0xf099 },
1473 { 0x04, 0x9800 },
1474 { 0x04, 0xa000 },
1475 { 0x03, 0xdf01 },
1476 { 0x02, 0xdf20 },
1477 { 0x01, 0xff95 },
1478 { 0x00, 0xba00 },
1479 { 0x04, 0xa800 },
1480 { 0x04, 0xf000 },
1481 { 0x03, 0xdf01 },
1482 { 0x02, 0xdf20 },
1483 { 0x01, 0x101a },
1484 { 0x00, 0xa0ff },
1485 { 0x04, 0xf800 },
1486 { 0x04, 0x0000 },
1487 { 0x1f, 0x0000 },
1488
1489 { 0x1f, 0x0001 },
1490 { 0x10, 0xf41b },
1491 { 0x14, 0xfb54 },
1492 { 0x18, 0xf5c7 },
1493 { 0x1f, 0x0000 },
1494
1495 { 0x1f, 0x0001 },
1496 { 0x17, 0x0cc0 },
1497 { 0x1f, 0x0000 }
1498 };
1499
1500 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1501
1502 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1503}
1504
8c7006aa 1505static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1506{
1507 struct phy_reg phy_reg_init[] = {
1508 { 0x1f, 0x0001 },
1509 { 0x04, 0x0000 },
1510 { 0x03, 0x00a1 },
1511 { 0x02, 0x0008 },
1512 { 0x01, 0x0120 },
1513 { 0x00, 0x1000 },
1514 { 0x04, 0x0800 },
1515 { 0x04, 0x9000 },
1516 { 0x03, 0x802f },
1517 { 0x02, 0x4f02 },
1518 { 0x01, 0x0409 },
1519 { 0x00, 0xf099 },
1520 { 0x04, 0x9800 },
1521 { 0x04, 0xa000 },
1522 { 0x03, 0xdf01 },
1523 { 0x02, 0xdf20 },
1524 { 0x01, 0xff95 },
1525 { 0x00, 0xba00 },
1526 { 0x04, 0xa800 },
1527 { 0x04, 0xf000 },
1528 { 0x03, 0xdf01 },
1529 { 0x02, 0xdf20 },
1530 { 0x01, 0x101a },
1531 { 0x00, 0xa0ff },
1532 { 0x04, 0xf800 },
1533 { 0x04, 0x0000 },
1534 { 0x1f, 0x0000 },
1535
1536 { 0x1f, 0x0001 },
1537 { 0x0b, 0x8480 },
1538 { 0x1f, 0x0000 },
1539
1540 { 0x1f, 0x0001 },
1541 { 0x18, 0x67c7 },
1542 { 0x04, 0x2000 },
1543 { 0x03, 0x002f },
1544 { 0x02, 0x4360 },
1545 { 0x01, 0x0109 },
1546 { 0x00, 0x3022 },
1547 { 0x04, 0x2800 },
1548 { 0x1f, 0x0000 },
1549
1550 { 0x1f, 0x0001 },
1551 { 0x17, 0x0cc0 },
1552 { 0x1f, 0x0000 }
1553 };
1554
1555 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1556}
1557
236b8082
FR		 1558static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1559{
1560 struct phy_reg phy_reg_init[] = {
1561 { 0x10, 0xf41b },
1562 { 0x1f, 0x0000 }
1563 };
1564
1565 mdio_write(ioaddr, 0x1f, 0x0001);
1566 mdio_patch(ioaddr, 0x16, 1 << 0);
1567
1568 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1569}
1570
1571static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1572{
1573 struct phy_reg phy_reg_init[] = {
1574 { 0x1f, 0x0001 },
1575 { 0x10, 0xf41b },
1576 { 0x1f, 0x0000 }
1577 };
1578
1579 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1580}
1581
ef3386f0 1582static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1583{
1584 struct phy_reg phy_reg_init[] = {
1585 { 0x1f, 0x0000 },
1586 { 0x1d, 0x0f00 },
1587 { 0x1f, 0x0002 },
1588 { 0x0c, 0x1ec8 },
1589 { 0x1f, 0x0000 }
1590 };
1591
1592 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1593}
1594
ef3386f0
FR		 1595static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1596{
1597 struct phy_reg phy_reg_init[] = {
1598 { 0x1f, 0x0001 },
1599 { 0x1d, 0x3d98 },
1600 { 0x1f, 0x0000 }
1601 };
1602
1603 mdio_write(ioaddr, 0x1f, 0x0000);
1604 mdio_patch(ioaddr, 0x14, 1 << 5);
1605 mdio_patch(ioaddr, 0x0d, 1 << 5);
1606
1607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1608}
1609
219a1e9d 1610static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1611{
1612 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1613 { 0x1f, 0x0001 },
1614 { 0x12, 0x2300 },
867763c1
FR		 1615 { 0x1f, 0x0002 },
1616 { 0x00, 0x88d4 },
1617 { 0x01, 0x82b1 },
1618 { 0x03, 0x7002 },
1619 { 0x08, 0x9e30 },
1620 { 0x09, 0x01f0 },
1621 { 0x0a, 0x5500 },
1622 { 0x0c, 0x00c8 },
1623 { 0x1f, 0x0003 },
1624 { 0x12, 0xc096 },
1625 { 0x16, 0x000a },
f50d4275
FR		 1626 { 0x1f, 0x0000 },
1627 { 0x1f, 0x0000 },
1628 { 0x09, 0x2000 },
1629 { 0x09, 0x0000 }
867763c1
FR		 1630 };
1631
1632 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1633
1634 mdio_patch(ioaddr, 0x14, 1 << 5);
1635 mdio_patch(ioaddr, 0x0d, 1 << 5);
1636 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1637}
1638
219a1e9d 1639static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1640{
1641 struct phy_reg phy_reg_init[] = {
f50d4275 1642 { 0x1f, 0x0001 },
7da97ec9 1643 { 0x12, 0x2300 },
f50d4275
FR		 1644 { 0x03, 0x802f },
1645 { 0x02, 0x4f02 },
1646 { 0x01, 0x0409 },
1647 { 0x00, 0xf099 },
1648 { 0x04, 0x9800 },
1649 { 0x04, 0x9000 },
1650 { 0x1d, 0x3d98 },
7da97ec9
FR		 1651 { 0x1f, 0x0002 },
1652 { 0x0c, 0x7eb8 },
f50d4275
FR		 1653 { 0x06, 0x0761 },
1654 { 0x1f, 0x0003 },
1655 { 0x16, 0x0f0a },
7da97ec9
FR		 1656 { 0x1f, 0x0000 }
1657 };
1658
1659 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1660
1661 mdio_patch(ioaddr, 0x16, 1 << 0);
1662 mdio_patch(ioaddr, 0x14, 1 << 5);
1663 mdio_patch(ioaddr, 0x0d, 1 << 5);
1664 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1665}
1666
197ff761
FR		 1667static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1668{
1669 struct phy_reg phy_reg_init[] = {
1670 { 0x1f, 0x0001 },
1671 { 0x12, 0x2300 },
1672 { 0x1d, 0x3d98 },
1673 { 0x1f, 0x0002 },
1674 { 0x0c, 0x7eb8 },
1675 { 0x06, 0x5461 },
1676 { 0x1f, 0x0003 },
1677 { 0x16, 0x0f0a },
1678 { 0x1f, 0x0000 }
1679 };
1680
1681 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1682
1683 mdio_patch(ioaddr, 0x16, 1 << 0);
1684 mdio_patch(ioaddr, 0x14, 1 << 5);
1685 mdio_patch(ioaddr, 0x0d, 1 << 5);
1686 mdio_write(ioaddr, 0x1f, 0x0000);
1687}
1688
6fb07058
FR		 1689static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1690{
1691 rtl8168c_3_hw_phy_config(ioaddr);
1692}
1693
daf9df6d 1694static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1695{
daf9df6d 1696 static struct phy_reg phy_reg_init_0[] = {
5b538df9 1697 { 0x1f, 0x0001 },
daf9df6d 1698 { 0x06, 0x4064 },
1699 { 0x07, 0x2863 },
1700 { 0x08, 0x059c },
1701 { 0x09, 0x26b4 },
1702 { 0x0a, 0x6a19 },
1703 { 0x0b, 0xdcc8 },
1704 { 0x10, 0xf06d },
1705 { 0x14, 0x7f68 },
1706 { 0x18, 0x7fd9 },
1707 { 0x1c, 0xf0ff },
1708 { 0x1d, 0x3d9c },
5b538df9 1709 { 0x1f, 0x0003 },
daf9df6d 1710 { 0x12, 0xf49f },
1711 { 0x13, 0x070b },
1712 { 0x1a, 0x05ad },
1713 { 0x14, 0x94c0 }
1714 };
1715 static struct phy_reg phy_reg_init_1[] = {
5b538df9 1716 { 0x1f, 0x0002 },
daf9df6d 1717 { 0x06, 0x5561 },
1718 { 0x1f, 0x0005 },
1719 { 0x05, 0x8332 },
1720 { 0x06, 0x5561 }
1721 };
1722 static struct phy_reg phy_reg_init_2[] = {
1723 { 0x1f, 0x0005 },
1724 { 0x05, 0xffc2 },
1725 { 0x1f, 0x0005 },
1726 { 0x05, 0x8000 },
1727 { 0x06, 0xf8f9 },
1728 { 0x06, 0xfaef },
1729 { 0x06, 0x59ee },
1730 { 0x06, 0xf8ea },
1731 { 0x06, 0x00ee },
1732 { 0x06, 0xf8eb },
1733 { 0x06, 0x00e0 },
1734 { 0x06, 0xf87c },
1735 { 0x06, 0xe1f8 },
1736 { 0x06, 0x7d59 },
1737 { 0x06, 0x0fef },
1738 { 0x06, 0x0139 },
1739 { 0x06, 0x029e },
1740 { 0x06, 0x06ef },
1741 { 0x06, 0x1039 },
1742 { 0x06, 0x089f },
1743 { 0x06, 0x2aee },
1744 { 0x06, 0xf8ea },
1745 { 0x06, 0x00ee },
1746 { 0x06, 0xf8eb },
1747 { 0x06, 0x01e0 },
1748 { 0x06, 0xf87c },
1749 { 0x06, 0xe1f8 },
1750 { 0x06, 0x7d58 },
1751 { 0x06, 0x409e },
1752 { 0x06, 0x0f39 },
1753 { 0x06, 0x46aa },
1754 { 0x06, 0x0bbf },
1755 { 0x06, 0x8290 },
1756 { 0x06, 0xd682 },
1757 { 0x06, 0x9802 },
1758 { 0x06, 0x014f },
1759 { 0x06, 0xae09 },
1760 { 0x06, 0xbf82 },
1761 { 0x06, 0x98d6 },
1762 { 0x06, 0x82a0 },
1763 { 0x06, 0x0201 },
1764 { 0x06, 0x4fef },
1765 { 0x06, 0x95fe },
1766 { 0x06, 0xfdfc },
1767 { 0x06, 0x05f8 },
1768 { 0x06, 0xf9fa },
1769 { 0x06, 0xeef8 },
1770 { 0x06, 0xea00 },
1771 { 0x06, 0xeef8 },
1772 { 0x06, 0xeb00 },
1773 { 0x06, 0xe2f8 },
1774 { 0x06, 0x7ce3 },
1775 { 0x06, 0xf87d },
1776 { 0x06, 0xa511 },
1777 { 0x06, 0x1112 },
1778 { 0x06, 0xd240 },
1779 { 0x06, 0xd644 },
1780 { 0x06, 0x4402 },
1781 { 0x06, 0x8217 },
1782 { 0x06, 0xd2a0 },
1783 { 0x06, 0xd6aa },
1784 { 0x06, 0xaa02 },
1785 { 0x06, 0x8217 },
1786 { 0x06, 0xae0f },
1787 { 0x06, 0xa544 },
1788 { 0x06, 0x4402 },
1789 { 0x06, 0xae4d },
1790 { 0x06, 0xa5aa },
1791 { 0x06, 0xaa02 },
1792 { 0x06, 0xae47 },
1793 { 0x06, 0xaf82 },
1794 { 0x06, 0x13ee },
1795 { 0x06, 0x834e },
1796 { 0x06, 0x00ee },
1797 { 0x06, 0x834d },
1798 { 0x06, 0x0fee },
1799 { 0x06, 0x834c },
1800 { 0x06, 0x0fee },
1801 { 0x06, 0x834f },
1802 { 0x06, 0x00ee },
1803 { 0x06, 0x8351 },
1804 { 0x06, 0x00ee },
1805 { 0x06, 0x834a },
1806 { 0x06, 0xffee },
1807 { 0x06, 0x834b },
1808 { 0x06, 0xffe0 },
1809 { 0x06, 0x8330 },
1810 { 0x06, 0xe183 },
1811 { 0x06, 0x3158 },
1812 { 0x06, 0xfee4 },
1813 { 0x06, 0xf88a },
1814 { 0x06, 0xe5f8 },
1815 { 0x06, 0x8be0 },
1816 { 0x06, 0x8332 },
1817 { 0x06, 0xe183 },
1818 { 0x06, 0x3359 },
1819 { 0x06, 0x0fe2 },
1820 { 0x06, 0x834d },
1821 { 0x06, 0x0c24 },
1822 { 0x06, 0x5af0 },
1823 { 0x06, 0x1e12 },
1824 { 0x06, 0xe4f8 },
1825 { 0x06, 0x8ce5 },
1826 { 0x06, 0xf88d },
1827 { 0x06, 0xaf82 },
1828 { 0x06, 0x13e0 },
1829 { 0x06, 0x834f },
1830 { 0x06, 0x10e4 },
1831 { 0x06, 0x834f },
1832 { 0x06, 0xe083 },
1833 { 0x06, 0x4e78 },
1834 { 0x06, 0x009f },
1835 { 0x06, 0x0ae0 },
1836 { 0x06, 0x834f },
1837 { 0x06, 0xa010 },
1838 { 0x06, 0xa5ee },
1839 { 0x06, 0x834e },
1840 { 0x06, 0x01e0 },
1841 { 0x06, 0x834e },
1842 { 0x06, 0x7805 },
1843 { 0x06, 0x9e9a },
1844 { 0x06, 0xe083 },
1845 { 0x06, 0x4e78 },
1846 { 0x06, 0x049e },
1847 { 0x06, 0x10e0 },
1848 { 0x06, 0x834e },
1849 { 0x06, 0x7803 },
1850 { 0x06, 0x9e0f },
1851 { 0x06, 0xe083 },
1852 { 0x06, 0x4e78 },
1853 { 0x06, 0x019e },
1854 { 0x06, 0x05ae },
1855 { 0x06, 0x0caf },
1856 { 0x06, 0x81f8 },
1857 { 0x06, 0xaf81 },
1858 { 0x06, 0xa3af },
1859 { 0x06, 0x81dc },
1860 { 0x06, 0xaf82 },
1861 { 0x06, 0x13ee },
1862 { 0x06, 0x8348 },
1863 { 0x06, 0x00ee },
1864 { 0x06, 0x8349 },
1865 { 0x06, 0x00e0 },
1866 { 0x06, 0x8351 },
1867 { 0x06, 0x10e4 },
1868 { 0x06, 0x8351 },
1869 { 0x06, 0x5801 },
1870 { 0x06, 0x9fea },
1871 { 0x06, 0xd000 },
1872 { 0x06, 0xd180 },
1873 { 0x06, 0x1f66 },
1874 { 0x06, 0xe2f8 },
1875 { 0x06, 0xeae3 },
1876 { 0x06, 0xf8eb },
1877 { 0x06, 0x5af8 },
1878 { 0x06, 0x1e20 },
1879 { 0x06, 0xe6f8 },
1880 { 0x06, 0xeae5 },
1881 { 0x06, 0xf8eb },
1882 { 0x06, 0xd302 },
1883 { 0x06, 0xb3fe },
1884 { 0x06, 0xe2f8 },
1885 { 0x06, 0x7cef },
1886 { 0x06, 0x325b },
1887 { 0x06, 0x80e3 },
1888 { 0x06, 0xf87d },
1889 { 0x06, 0x9e03 },
1890 { 0x06, 0x7dff },
1891 { 0x06, 0xff0d },
1892 { 0x06, 0x581c },
1893 { 0x06, 0x551a },
1894 { 0x06, 0x6511 },
1895 { 0x06, 0xa190 },
1896 { 0x06, 0xd3e2 },
1897 { 0x06, 0x8348 },
1898 { 0x06, 0xe383 },
1899 { 0x06, 0x491b },
1900 { 0x06, 0x56ab },
1901 { 0x06, 0x08ef },
1902 { 0x06, 0x56e6 },
1903 { 0x06, 0x8348 },
1904 { 0x06, 0xe783 },
1905 { 0x06, 0x4910 },
1906 { 0x06, 0xd180 },
1907 { 0x06, 0x1f66 },
1908 { 0x06, 0xa004 },
1909 { 0x06, 0xb9e2 },
1910 { 0x06, 0x8348 },
1911 { 0x06, 0xe383 },
1912 { 0x06, 0x49ef },
1913 { 0x06, 0x65e2 },
1914 { 0x06, 0x834a },
1915 { 0x06, 0xe383 },
1916 { 0x06, 0x4b1b },
1917 { 0x06, 0x56aa },
1918 { 0x06, 0x0eef },
1919 { 0x06, 0x56e6 },
1920 { 0x06, 0x834a },
1921 { 0x06, 0xe783 },
1922 { 0x06, 0x4be2 },
1923 { 0x06, 0x834d },
1924 { 0x06, 0xe683 },
1925 { 0x06, 0x4ce0 },
1926 { 0x06, 0x834d },
1927 { 0x06, 0xa000 },
1928 { 0x06, 0x0caf },
1929 { 0x06, 0x81dc },
1930 { 0x06, 0xe083 },
1931 { 0x06, 0x4d10 },
1932 { 0x06, 0xe483 },
1933 { 0x06, 0x4dae },
1934 { 0x06, 0x0480 },
1935 { 0x06, 0xe483 },
1936 { 0x06, 0x4de0 },
1937 { 0x06, 0x834e },
1938 { 0x06, 0x7803 },
1939 { 0x06, 0x9e0b },
1940 { 0x06, 0xe083 },
1941 { 0x06, 0x4e78 },
1942 { 0x06, 0x049e },
1943 { 0x06, 0x04ee },
1944 { 0x06, 0x834e },
1945 { 0x06, 0x02e0 },
1946 { 0x06, 0x8332 },
1947 { 0x06, 0xe183 },
1948 { 0x06, 0x3359 },
1949 { 0x06, 0x0fe2 },
1950 { 0x06, 0x834d },
1951 { 0x06, 0x0c24 },
1952 { 0x06, 0x5af0 },
1953 { 0x06, 0x1e12 },
1954 { 0x06, 0xe4f8 },
1955 { 0x06, 0x8ce5 },
1956 { 0x06, 0xf88d },
1957 { 0x06, 0xe083 },
1958 { 0x06, 0x30e1 },
1959 { 0x06, 0x8331 },
1960 { 0x06, 0x6801 },
1961 { 0x06, 0xe4f8 },
1962 { 0x06, 0x8ae5 },
1963 { 0x06, 0xf88b },
1964 { 0x06, 0xae37 },
1965 { 0x06, 0xee83 },
1966 { 0x06, 0x4e03 },
1967 { 0x06, 0xe083 },
1968 { 0x06, 0x4ce1 },
1969 { 0x06, 0x834d },
1970 { 0x06, 0x1b01 },
1971 { 0x06, 0x9e04 },
1972 { 0x06, 0xaaa1 },
1973 { 0x06, 0xaea8 },
1974 { 0x06, 0xee83 },
1975 { 0x06, 0x4e04 },
1976 { 0x06, 0xee83 },
1977 { 0x06, 0x4f00 },
1978 { 0x06, 0xaeab },
1979 { 0x06, 0xe083 },
1980 { 0x06, 0x4f78 },
1981 { 0x06, 0x039f },
1982 { 0x06, 0x14ee },
1983 { 0x06, 0x834e },
1984 { 0x06, 0x05d2 },
1985 { 0x06, 0x40d6 },
1986 { 0x06, 0x5554 },
1987 { 0x06, 0x0282 },
1988 { 0x06, 0x17d2 },
1989 { 0x06, 0xa0d6 },
1990 { 0x06, 0xba00 },
1991 { 0x06, 0x0282 },
1992 { 0x06, 0x17fe },
1993 { 0x06, 0xfdfc },
1994 { 0x06, 0x05f8 },
1995 { 0x06, 0xe0f8 },
1996 { 0x06, 0x60e1 },
1997 { 0x06, 0xf861 },
1998 { 0x06, 0x6802 },
1999 { 0x06, 0xe4f8 },
2000 { 0x06, 0x60e5 },
2001 { 0x06, 0xf861 },
2002 { 0x06, 0xe0f8 },
2003 { 0x06, 0x48e1 },
2004 { 0x06, 0xf849 },
2005 { 0x06, 0x580f },
2006 { 0x06, 0x1e02 },
2007 { 0x06, 0xe4f8 },
2008 { 0x06, 0x48e5 },
2009 { 0x06, 0xf849 },
2010 { 0x06, 0xd000 },
2011 { 0x06, 0x0282 },
2012 { 0x06, 0x5bbf },
2013 { 0x06, 0x8350 },
2014 { 0x06, 0xef46 },
2015 { 0x06, 0xdc19 },
2016 { 0x06, 0xddd0 },
2017 { 0x06, 0x0102 },
2018 { 0x06, 0x825b },
2019 { 0x06, 0x0282 },
2020 { 0x06, 0x77e0 },
2021 { 0x06, 0xf860 },
2022 { 0x06, 0xe1f8 },
2023 { 0x06, 0x6158 },
2024 { 0x06, 0xfde4 },
2025 { 0x06, 0xf860 },
2026 { 0x06, 0xe5f8 },
2027 { 0x06, 0x61fc },
2028 { 0x06, 0x04f9 },
2029 { 0x06, 0xfafb },
2030 { 0x06, 0xc6bf },
2031 { 0x06, 0xf840 },
2032 { 0x06, 0xbe83 },
2033 { 0x06, 0x50a0 },
2034 { 0x06, 0x0101 },
2035 { 0x06, 0x071b },
2036 { 0x06, 0x89cf },
2037 { 0x06, 0xd208 },
2038 { 0x06, 0xebdb },
2039 { 0x06, 0x19b2 },
2040 { 0x06, 0xfbff },
2041 { 0x06, 0xfefd },
2042 { 0x06, 0x04f8 },
2043 { 0x06, 0xe0f8 },
2044 { 0x06, 0x48e1 },
2045 { 0x06, 0xf849 },
2046 { 0x06, 0x6808 },
2047 { 0x06, 0xe4f8 },
2048 { 0x06, 0x48e5 },
2049 { 0x06, 0xf849 },
2050 { 0x06, 0x58f7 },
2051 { 0x06, 0xe4f8 },
2052 { 0x06, 0x48e5 },
2053 { 0x06, 0xf849 },
2054 { 0x06, 0xfc04 },
2055 { 0x06, 0x4d20 },
2056 { 0x06, 0x0002 },
2057 { 0x06, 0x4e22 },
2058 { 0x06, 0x0002 },
2059 { 0x06, 0x4ddf },
2060 { 0x06, 0xff01 },
2061 { 0x06, 0x4edd },
2062 { 0x06, 0xff01 },
2063 { 0x05, 0x83d4 },
2064 { 0x06, 0x8000 },
2065 { 0x05, 0x83d8 },
2066 { 0x06, 0x8051 },
2067 { 0x02, 0x6010 },
2068 { 0x03, 0xdc00 },
2069 { 0x05, 0xfff6 },
2070 { 0x06, 0x00fc },
5b538df9 2071 { 0x1f, 0x0000 },
daf9df6d 2072
5b538df9 2073 { 0x1f, 0x0000 },
daf9df6d 2074 { 0x0d, 0xf880 },
2075 { 0x1f, 0x0000 }
2076 };
2077
2078 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2079
2080 mdio_write(ioaddr, 0x1f, 0x0002);
2081 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2082 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2083
2084 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2085
2086 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2087 struct phy_reg phy_reg_init[] = {
2088 { 0x1f, 0x0002 },
2089 { 0x05, 0x669a },
2090 { 0x1f, 0x0005 },
2091 { 0x05, 0x8330 },
2092 { 0x06, 0x669a },
2093 { 0x1f, 0x0002 }
2094 };
2095 int val;
2096
2097 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2098
2099 val = mdio_read(ioaddr, 0x0d);
2100
2101 if ((val & 0x00ff) != 0x006c) {
2102 u32 set[] = {
2103 0x0065, 0x0066, 0x0067, 0x0068,
2104 0x0069, 0x006a, 0x006b, 0x006c
2105 };
2106 int i;
2107
2108 mdio_write(ioaddr, 0x1f, 0x0002);
2109
2110 val &= 0xff00;
2111 for (i = 0; i < ARRAY_SIZE(set); i++)
2112 mdio_write(ioaddr, 0x0d, val | set[i]);
2113 }
2114 } else {
2115 struct phy_reg phy_reg_init[] = {
2116 { 0x1f, 0x0002 },
2117 { 0x05, 0x6662 },
2118 { 0x1f, 0x0005 },
2119 { 0x05, 0x8330 },
2120 { 0x06, 0x6662 }
2121 };
2122
2123 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2124 }
2125
2126 mdio_write(ioaddr, 0x1f, 0x0002);
2127 mdio_patch(ioaddr, 0x0d, 0x0300);
2128 mdio_patch(ioaddr, 0x0f, 0x0010);
2129
2130 mdio_write(ioaddr, 0x1f, 0x0002);
2131 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2132 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2133
2134 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2135}
2136
2137static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2138{
2139 static struct phy_reg phy_reg_init_0[] = {
2140 { 0x1f, 0x0001 },
2141 { 0x06, 0x4064 },
2142 { 0x07, 0x2863 },
2143 { 0x08, 0x059c },
2144 { 0x09, 0x26b4 },
2145 { 0x0a, 0x6a19 },
2146 { 0x0b, 0xdcc8 },
2147 { 0x10, 0xf06d },
2148 { 0x14, 0x7f68 },
2149 { 0x18, 0x7fd9 },
2150 { 0x1c, 0xf0ff },
2151 { 0x1d, 0x3d9c },
2152 { 0x1f, 0x0003 },
2153 { 0x12, 0xf49f },
2154 { 0x13, 0x070b },
2155 { 0x1a, 0x05ad },
2156 { 0x14, 0x94c0 },
2157
2158 { 0x1f, 0x0002 },
2159 { 0x06, 0x5561 },
2160 { 0x1f, 0x0005 },
2161 { 0x05, 0x8332 },
2162 { 0x06, 0x5561 }
2163 };
2164 static struct phy_reg phy_reg_init_1[] = {
2165 { 0x1f, 0x0005 },
2166 { 0x05, 0xffc2 },
5b538df9 2167 { 0x1f, 0x0005 },
daf9df6d 2168 { 0x05, 0x8000 },
2169 { 0x06, 0xf8f9 },
2170 { 0x06, 0xfaee },
2171 { 0x06, 0xf8ea },
2172 { 0x06, 0x00ee },
2173 { 0x06, 0xf8eb },
2174 { 0x06, 0x00e2 },
2175 { 0x06, 0xf87c },
2176 { 0x06, 0xe3f8 },
2177 { 0x06, 0x7da5 },
2178 { 0x06, 0x1111 },
2179 { 0x06, 0x12d2 },
2180 { 0x06, 0x40d6 },
2181 { 0x06, 0x4444 },
2182 { 0x06, 0x0281 },
2183 { 0x06, 0xc6d2 },
2184 { 0x06, 0xa0d6 },
2185 { 0x06, 0xaaaa },
2186 { 0x06, 0x0281 },
2187 { 0x06, 0xc6ae },
2188 { 0x06, 0x0fa5 },
2189 { 0x06, 0x4444 },
2190 { 0x06, 0x02ae },
2191 { 0x06, 0x4da5 },
2192 { 0x06, 0xaaaa },
2193 { 0x06, 0x02ae },
2194 { 0x06, 0x47af },
2195 { 0x06, 0x81c2 },
2196 { 0x06, 0xee83 },
2197 { 0x06, 0x4e00 },
2198 { 0x06, 0xee83 },
2199 { 0x06, 0x4d0f },
2200 { 0x06, 0xee83 },
2201 { 0x06, 0x4c0f },
2202 { 0x06, 0xee83 },
2203 { 0x06, 0x4f00 },
2204 { 0x06, 0xee83 },
2205 { 0x06, 0x5100 },
2206 { 0x06, 0xee83 },
2207 { 0x06, 0x4aff },
2208 { 0x06, 0xee83 },
2209 { 0x06, 0x4bff },
2210 { 0x06, 0xe083 },
2211 { 0x06, 0x30e1 },
2212 { 0x06, 0x8331 },
2213 { 0x06, 0x58fe },
2214 { 0x06, 0xe4f8 },
2215 { 0x06, 0x8ae5 },
2216 { 0x06, 0xf88b },
2217 { 0x06, 0xe083 },
2218 { 0x06, 0x32e1 },
2219 { 0x06, 0x8333 },
2220 { 0x06, 0x590f },
2221 { 0x06, 0xe283 },
2222 { 0x06, 0x4d0c },
2223 { 0x06, 0x245a },
2224 { 0x06, 0xf01e },
2225 { 0x06, 0x12e4 },
2226 { 0x06, 0xf88c },
2227 { 0x06, 0xe5f8 },
2228 { 0x06, 0x8daf },
2229 { 0x06, 0x81c2 },
2230 { 0x06, 0xe083 },
2231 { 0x06, 0x4f10 },
2232 { 0x06, 0xe483 },
2233 { 0x06, 0x4fe0 },
2234 { 0x06, 0x834e },
2235 { 0x06, 0x7800 },
2236 { 0x06, 0x9f0a },
2237 { 0x06, 0xe083 },
2238 { 0x06, 0x4fa0 },
2239 { 0x06, 0x10a5 },
2240 { 0x06, 0xee83 },
2241 { 0x06, 0x4e01 },
2242 { 0x06, 0xe083 },
2243 { 0x06, 0x4e78 },
2244 { 0x06, 0x059e },
2245 { 0x06, 0x9ae0 },
2246 { 0x06, 0x834e },
2247 { 0x06, 0x7804 },
2248 { 0x06, 0x9e10 },
2249 { 0x06, 0xe083 },
2250 { 0x06, 0x4e78 },
2251 { 0x06, 0x039e },
2252 { 0x06, 0x0fe0 },
2253 { 0x06, 0x834e },
2254 { 0x06, 0x7801 },
2255 { 0x06, 0x9e05 },
2256 { 0x06, 0xae0c },
2257 { 0x06, 0xaf81 },
2258 { 0x06, 0xa7af },
2259 { 0x06, 0x8152 },
2260 { 0x06, 0xaf81 },
2261 { 0x06, 0x8baf },
2262 { 0x06, 0x81c2 },
2263 { 0x06, 0xee83 },
2264 { 0x06, 0x4800 },
2265 { 0x06, 0xee83 },
2266 { 0x06, 0x4900 },
2267 { 0x06, 0xe083 },
2268 { 0x06, 0x5110 },
2269 { 0x06, 0xe483 },
2270 { 0x06, 0x5158 },
2271 { 0x06, 0x019f },
2272 { 0x06, 0xead0 },
2273 { 0x06, 0x00d1 },
2274 { 0x06, 0x801f },
2275 { 0x06, 0x66e2 },
2276 { 0x06, 0xf8ea },
2277 { 0x06, 0xe3f8 },
2278 { 0x06, 0xeb5a },
2279 { 0x06, 0xf81e },
2280 { 0x06, 0x20e6 },
2281 { 0x06, 0xf8ea },
2282 { 0x06, 0xe5f8 },
2283 { 0x06, 0xebd3 },
2284 { 0x06, 0x02b3 },
2285 { 0x06, 0xfee2 },
2286 { 0x06, 0xf87c },
2287 { 0x06, 0xef32 },
2288 { 0x06, 0x5b80 },
2289 { 0x06, 0xe3f8 },
2290 { 0x06, 0x7d9e },
2291 { 0x06, 0x037d },
2292 { 0x06, 0xffff },
2293 { 0x06, 0x0d58 },
2294 { 0x06, 0x1c55 },
2295 { 0x06, 0x1a65 },
2296 { 0x06, 0x11a1 },
2297 { 0x06, 0x90d3 },
2298 { 0x06, 0xe283 },
2299 { 0x06, 0x48e3 },
2300 { 0x06, 0x8349 },
2301 { 0x06, 0x1b56 },
2302 { 0x06, 0xab08 },
2303 { 0x06, 0xef56 },
2304 { 0x06, 0xe683 },
2305 { 0x06, 0x48e7 },
2306 { 0x06, 0x8349 },
2307 { 0x06, 0x10d1 },
2308 { 0x06, 0x801f },
2309 { 0x06, 0x66a0 },
2310 { 0x06, 0x04b9 },
2311 { 0x06, 0xe283 },
2312 { 0x06, 0x48e3 },
2313 { 0x06, 0x8349 },
2314 { 0x06, 0xef65 },
2315 { 0x06, 0xe283 },
2316 { 0x06, 0x4ae3 },
2317 { 0x06, 0x834b },
2318 { 0x06, 0x1b56 },
2319 { 0x06, 0xaa0e },
2320 { 0x06, 0xef56 },
2321 { 0x06, 0xe683 },
2322 { 0x06, 0x4ae7 },
2323 { 0x06, 0x834b },
2324 { 0x06, 0xe283 },
2325 { 0x06, 0x4de6 },
2326 { 0x06, 0x834c },
2327 { 0x06, 0xe083 },
2328 { 0x06, 0x4da0 },
2329 { 0x06, 0x000c },
2330 { 0x06, 0xaf81 },
2331 { 0x06, 0x8be0 },
2332 { 0x06, 0x834d },
2333 { 0x06, 0x10e4 },
2334 { 0x06, 0x834d },
2335 { 0x06, 0xae04 },
2336 { 0x06, 0x80e4 },
2337 { 0x06, 0x834d },
2338 { 0x06, 0xe083 },
2339 { 0x06, 0x4e78 },
2340 { 0x06, 0x039e },
2341 { 0x06, 0x0be0 },
2342 { 0x06, 0x834e },
2343 { 0x06, 0x7804 },
2344 { 0x06, 0x9e04 },
2345 { 0x06, 0xee83 },
2346 { 0x06, 0x4e02 },
2347 { 0x06, 0xe083 },
2348 { 0x06, 0x32e1 },
2349 { 0x06, 0x8333 },
2350 { 0x06, 0x590f },
2351 { 0x06, 0xe283 },
2352 { 0x06, 0x4d0c },
2353 { 0x06, 0x245a },
2354 { 0x06, 0xf01e },
2355 { 0x06, 0x12e4 },
2356 { 0x06, 0xf88c },
2357 { 0x06, 0xe5f8 },
2358 { 0x06, 0x8de0 },
2359 { 0x06, 0x8330 },
2360 { 0x06, 0xe183 },
2361 { 0x06, 0x3168 },
2362 { 0x06, 0x01e4 },
2363 { 0x06, 0xf88a },
2364 { 0x06, 0xe5f8 },
2365 { 0x06, 0x8bae },
2366 { 0x06, 0x37ee },
2367 { 0x06, 0x834e },
2368 { 0x06, 0x03e0 },
2369 { 0x06, 0x834c },
2370 { 0x06, 0xe183 },
2371 { 0x06, 0x4d1b },
2372 { 0x06, 0x019e },
2373 { 0x06, 0x04aa },
2374 { 0x06, 0xa1ae },
2375 { 0x06, 0xa8ee },
2376 { 0x06, 0x834e },
2377 { 0x06, 0x04ee },
2378 { 0x06, 0x834f },
2379 { 0x06, 0x00ae },
2380 { 0x06, 0xabe0 },
2381 { 0x06, 0x834f },
2382 { 0x06, 0x7803 },
2383 { 0x06, 0x9f14 },
2384 { 0x06, 0xee83 },
2385 { 0x06, 0x4e05 },
2386 { 0x06, 0xd240 },
2387 { 0x06, 0xd655 },
2388 { 0x06, 0x5402 },
2389 { 0x06, 0x81c6 },
2390 { 0x06, 0xd2a0 },
2391 { 0x06, 0xd6ba },
2392 { 0x06, 0x0002 },
2393 { 0x06, 0x81c6 },
2394 { 0x06, 0xfefd },
2395 { 0x06, 0xfc05 },
2396 { 0x06, 0xf8e0 },
2397 { 0x06, 0xf860 },
2398 { 0x06, 0xe1f8 },
2399 { 0x06, 0x6168 },
2400 { 0x06, 0x02e4 },
2401 { 0x06, 0xf860 },
2402 { 0x06, 0xe5f8 },
2403 { 0x06, 0x61e0 },
2404 { 0x06, 0xf848 },
2405 { 0x06, 0xe1f8 },
2406 { 0x06, 0x4958 },
2407 { 0x06, 0x0f1e },
2408 { 0x06, 0x02e4 },
2409 { 0x06, 0xf848 },
2410 { 0x06, 0xe5f8 },
2411 { 0x06, 0x49d0 },
2412 { 0x06, 0x0002 },
2413 { 0x06, 0x820a },
2414 { 0x06, 0xbf83 },
2415 { 0x06, 0x50ef },
2416 { 0x06, 0x46dc },
2417 { 0x06, 0x19dd },
2418 { 0x06, 0xd001 },
2419 { 0x06, 0x0282 },
2420 { 0x06, 0x0a02 },
2421 { 0x06, 0x8226 },
2422 { 0x06, 0xe0f8 },
2423 { 0x06, 0x60e1 },
2424 { 0x06, 0xf861 },
2425 { 0x06, 0x58fd },
2426 { 0x06, 0xe4f8 },
2427 { 0x06, 0x60e5 },
2428 { 0x06, 0xf861 },
2429 { 0x06, 0xfc04 },
2430 { 0x06, 0xf9fa },
2431 { 0x06, 0xfbc6 },
2432 { 0x06, 0xbff8 },
2433 { 0x06, 0x40be },
2434 { 0x06, 0x8350 },
2435 { 0x06, 0xa001 },
2436 { 0x06, 0x0107 },
2437 { 0x06, 0x1b89 },
2438 { 0x06, 0xcfd2 },
2439 { 0x06, 0x08eb },
2440 { 0x06, 0xdb19 },
2441 { 0x06, 0xb2fb },
2442 { 0x06, 0xfffe },
2443 { 0x06, 0xfd04 },
2444 { 0x06, 0xf8e0 },
2445 { 0x06, 0xf848 },
2446 { 0x06, 0xe1f8 },
2447 { 0x06, 0x4968 },
2448 { 0x06, 0x08e4 },
2449 { 0x06, 0xf848 },
2450 { 0x06, 0xe5f8 },
2451 { 0x06, 0x4958 },
2452 { 0x06, 0xf7e4 },
2453 { 0x06, 0xf848 },
2454 { 0x06, 0xe5f8 },
2455 { 0x06, 0x49fc },
2456 { 0x06, 0x044d },
2457 { 0x06, 0x2000 },
2458 { 0x06, 0x024e },
2459 { 0x06, 0x2200 },
2460 { 0x06, 0x024d },
2461 { 0x06, 0xdfff },
2462 { 0x06, 0x014e },
2463 { 0x06, 0xddff },
2464 { 0x06, 0x0100 },
2465 { 0x05, 0x83d8 },
2466 { 0x06, 0x8000 },
2467 { 0x03, 0xdc00 },
2468 { 0x05, 0xfff6 },
2469 { 0x06, 0x00fc },
2470 { 0x1f, 0x0000 },
2471
2472 { 0x1f, 0x0000 },
2473 { 0x0d, 0xf880 },
2474 { 0x1f, 0x0000 }
5b538df9
FR		 2475 };
2476
2477 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2478
daf9df6d 2479 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2480 struct phy_reg phy_reg_init[] = {
2481 { 0x1f, 0x0002 },
2482 { 0x05, 0x669a },
5b538df9 2483 { 0x1f, 0x0005 },
daf9df6d 2484 { 0x05, 0x8330 },
2485 { 0x06, 0x669a },
2486
2487 { 0x1f, 0x0002 }
2488 };
2489 int val;
2490
2491 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2492
2493 val = mdio_read(ioaddr, 0x0d);
2494 if ((val & 0x00ff) != 0x006c) {
2495 u32 set[] = {
2496 0x0065, 0x0066, 0x0067, 0x0068,
2497 0x0069, 0x006a, 0x006b, 0x006c
2498 };
2499 int i;
2500
2501 mdio_write(ioaddr, 0x1f, 0x0002);
2502
2503 val &= 0xff00;
2504 for (i = 0; i < ARRAY_SIZE(set); i++)
2505 mdio_write(ioaddr, 0x0d, val | set[i]);
2506 }
2507 } else {
2508 struct phy_reg phy_reg_init[] = {
2509 { 0x1f, 0x0002 },
2510 { 0x05, 0x2642 },
5b538df9 2511 { 0x1f, 0x0005 },
daf9df6d 2512 { 0x05, 0x8330 },
2513 { 0x06, 0x2642 }
5b538df9
FR		 2514 };
2515
daf9df6d 2516 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2517 }
2518
daf9df6d 2519 mdio_write(ioaddr, 0x1f, 0x0002);
2520 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2521 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2522
2523 mdio_write(ioaddr, 0x1f, 0x0001);
2524 mdio_write(ioaddr, 0x17, 0x0cc0);
2525
2526 mdio_write(ioaddr, 0x1f, 0x0002);
2527 mdio_patch(ioaddr, 0x0f, 0x0017);
2528
2529 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2530}
2531
2532static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2533{
2534 struct phy_reg phy_reg_init[] = {
2535 { 0x1f, 0x0002 },
2536 { 0x10, 0x0008 },
2537 { 0x0d, 0x006c },
2538
2539 { 0x1f, 0x0000 },
2540 { 0x0d, 0xf880 },
2541
2542 { 0x1f, 0x0001 },
2543 { 0x17, 0x0cc0 },
2544
2545 { 0x1f, 0x0001 },
2546 { 0x0b, 0xa4d8 },
2547 { 0x09, 0x281c },
2548 { 0x07, 0x2883 },
2549 { 0x0a, 0x6b35 },
2550 { 0x1d, 0x3da4 },
2551 { 0x1c, 0xeffd },
2552 { 0x14, 0x7f52 },
2553 { 0x18, 0x7fc6 },
2554 { 0x08, 0x0601 },
2555 { 0x06, 0x4063 },
2556 { 0x10, 0xf074 },
2557 { 0x1f, 0x0003 },
2558 { 0x13, 0x0789 },
2559 { 0x12, 0xf4bd },
2560 { 0x1a, 0x04fd },
2561 { 0x14, 0x84b0 },
2562 { 0x1f, 0x0000 },
2563 { 0x00, 0x9200 },
2564
2565 { 0x1f, 0x0005 },
2566 { 0x01, 0x0340 },
2567 { 0x1f, 0x0001 },
2568 { 0x04, 0x4000 },
2569 { 0x03, 0x1d21 },
2570 { 0x02, 0x0c32 },
2571 { 0x01, 0x0200 },
2572 { 0x00, 0x5554 },
2573 { 0x04, 0x4800 },
2574 { 0x04, 0x4000 },
2575 { 0x04, 0xf000 },
2576 { 0x03, 0xdf01 },
2577 { 0x02, 0xdf20 },
2578 { 0x01, 0x101a },
2579 { 0x00, 0xa0ff },
2580 { 0x04, 0xf800 },
2581 { 0x04, 0xf000 },
2582 { 0x1f, 0x0000 },
2583
2584 { 0x1f, 0x0007 },
2585 { 0x1e, 0x0023 },
2586 { 0x16, 0x0000 },
2587 { 0x1f, 0x0000 }
2588 };
2589
2590 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2591}
2592
2857ffb7
FR		 2593static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2594{
2595 struct phy_reg phy_reg_init[] = {
2596 { 0x1f, 0x0003 },
2597 { 0x08, 0x441d },
2598 { 0x01, 0x9100 },
2599 { 0x1f, 0x0000 }
2600 };
2601
2602 mdio_write(ioaddr, 0x1f, 0x0000);
2603 mdio_patch(ioaddr, 0x11, 1 << 12);
2604 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2605 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2606
2607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2608}
2609
5615d9f1
FR		 2610static void rtl_hw_phy_config(struct net_device *dev)
2611{
2612 struct rtl8169_private *tp = netdev_priv(dev);
2613 void __iomem *ioaddr = tp->mmio_addr;
2614
2615 rtl8169_print_mac_version(tp);
2616
2617 switch (tp->mac_version) {
2618 case RTL_GIGA_MAC_VER_01:
2619 break;
2620 case RTL_GIGA_MAC_VER_02:
2621 case RTL_GIGA_MAC_VER_03:
2622 rtl8169s_hw_phy_config(ioaddr);
2623 break;
2624 case RTL_GIGA_MAC_VER_04:
2625 rtl8169sb_hw_phy_config(ioaddr);
2626 break;
2e955856 2627 case RTL_GIGA_MAC_VER_05:
2628 rtl8169scd_hw_phy_config(tp, ioaddr);
2629 break;
8c7006aa 2630 case RTL_GIGA_MAC_VER_06:
2631 rtl8169sce_hw_phy_config(ioaddr);
2632 break;
2857ffb7
FR		 2633 case RTL_GIGA_MAC_VER_07:
2634 case RTL_GIGA_MAC_VER_08:
2635 case RTL_GIGA_MAC_VER_09:
2636 rtl8102e_hw_phy_config(ioaddr);
2637 break;
236b8082
FR		 2638 case RTL_GIGA_MAC_VER_11:
2639 rtl8168bb_hw_phy_config(ioaddr);
2640 break;
2641 case RTL_GIGA_MAC_VER_12:
2642 rtl8168bef_hw_phy_config(ioaddr);
2643 break;
2644 case RTL_GIGA_MAC_VER_17:
2645 rtl8168bef_hw_phy_config(ioaddr);
2646 break;
867763c1 2647 case RTL_GIGA_MAC_VER_18:
ef3386f0 2648 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2649 break;
2650 case RTL_GIGA_MAC_VER_19:
219a1e9d 2651 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2652 break;
7da97ec9 2653 case RTL_GIGA_MAC_VER_20:
219a1e9d 2654 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2655 break;
197ff761
FR		 2656 case RTL_GIGA_MAC_VER_21:
2657 rtl8168c_3_hw_phy_config(ioaddr);
2658 break;
6fb07058
FR		 2659 case RTL_GIGA_MAC_VER_22:
2660 rtl8168c_4_hw_phy_config(ioaddr);
2661 break;
ef3386f0 2662 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2663 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2664 rtl8168cp_2_hw_phy_config(ioaddr);
2665 break;
5b538df9 2666 case RTL_GIGA_MAC_VER_25:
daf9df6d 2667 rtl8168d_1_hw_phy_config(ioaddr);
2668 break;
2669 case RTL_GIGA_MAC_VER_26:
2670 rtl8168d_2_hw_phy_config(ioaddr);
2671 break;
2672 case RTL_GIGA_MAC_VER_27:
2673 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2674 break;
ef3386f0 2675
5615d9f1
FR		 2676 default:
2677 break;
2678 }
2679}
2680
1da177e4
LT		 2681static void rtl8169_phy_timer(unsigned long __opaque)
2682{
2683 struct net_device *dev = (struct net_device *)__opaque;
2684 struct rtl8169_private *tp = netdev_priv(dev);
2685 struct timer_list *timer = &tp->timer;
2686 void __iomem *ioaddr = tp->mmio_addr;
2687 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2688
bcf0bf90 2689 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2690
64e4bfb4 2691 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2692 return;
2693
2694 spin_lock_irq(&tp->lock);
2695
2696 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2697 /*
1da177e4
LT		 2698 * A busy loop could burn quite a few cycles on nowadays CPU.
2699 * Let's delay the execution of the timer for a few ticks.
2700 */
2701 timeout = HZ/10;
2702 goto out_mod_timer;
2703 }
2704
2705 if (tp->link_ok(ioaddr))
2706 goto out_unlock;
2707
b57b7e5a
SH		 2708 if (netif_msg_link(tp))
2709 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 2710
2711 tp->phy_reset_enable(ioaddr);
2712
2713out_mod_timer:
2714 mod_timer(timer, jiffies + timeout);
2715out_unlock:
2716 spin_unlock_irq(&tp->lock);
2717}
2718
2719static inline void rtl8169_delete_timer(struct net_device *dev)
2720{
2721 struct rtl8169_private *tp = netdev_priv(dev);
2722 struct timer_list *timer = &tp->timer;
2723
e179bb7b 2724 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2725 return;
2726
2727 del_timer_sync(timer);
2728}
2729
2730static inline void rtl8169_request_timer(struct net_device *dev)
2731{
2732 struct rtl8169_private *tp = netdev_priv(dev);
2733 struct timer_list *timer = &tp->timer;
2734
e179bb7b 2735 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2736 return;
2737
2efa53f3 2738 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2739}
2740
2741#ifdef CONFIG_NET_POLL_CONTROLLER
2742/*
2743 * Polling 'interrupt' - used by things like netconsole to send skbs
2744 * without having to re-enable interrupts. It's not called while
2745 * the interrupt routine is executing.
2746 */
2747static void rtl8169_netpoll(struct net_device *dev)
2748{
2749 struct rtl8169_private *tp = netdev_priv(dev);
2750 struct pci_dev *pdev = tp->pci_dev;
2751
2752 disable_irq(pdev->irq);
7d12e780 2753 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2754 enable_irq(pdev->irq);
2755}
2756#endif
2757
2758static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2759 void __iomem *ioaddr)
2760{
2761 iounmap(ioaddr);
2762 pci_release_regions(pdev);
2763 pci_disable_device(pdev);
2764 free_netdev(dev);
2765}
2766
bf793295
FR		 2767static void rtl8169_phy_reset(struct net_device *dev,
2768 struct rtl8169_private *tp)
2769{
2770 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2771 unsigned int i;
bf793295
FR		 2772
2773 tp->phy_reset_enable(ioaddr);
2774 for (i = 0; i < 100; i++) {
2775 if (!tp->phy_reset_pending(ioaddr))
2776 return;
2777 msleep(1);
2778 }
2779 if (netif_msg_link(tp))
2780 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
2781}
2782
4ff96fa6
FR		 2783static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2784{
2785 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2786
5615d9f1 2787 rtl_hw_phy_config(dev);
4ff96fa6 2788
77332894
MS		 2789 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2790 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2791 RTL_W8(0x82, 0x01);
2792 }
4ff96fa6 2793
6dccd16b
FR		 2794 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2795
2796 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2797 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2798
bcf0bf90 2799 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2800 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2801 RTL_W8(0x82, 0x01);
2802 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2803 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2804 }
2805
bf793295
FR		 2806 rtl8169_phy_reset(dev, tp);
2807
901dda2b
FR		 2808 /*
2809 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2810 * only 8101. Don't panic.
2811 */
2812 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 2813
2814 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
2815 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
2816}
2817
773d2021
FR		 2818static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2819{
2820 void __iomem *ioaddr = tp->mmio_addr;
2821 u32 high;
2822 u32 low;
2823
2824 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2825 high = addr[4] | (addr[5] << 8);
2826
2827 spin_lock_irq(&tp->lock);
2828
2829 RTL_W8(Cfg9346, Cfg9346_Unlock);
2830 RTL_W32(MAC0, low);
2831 RTL_W32(MAC4, high);
2832 RTL_W8(Cfg9346, Cfg9346_Lock);
2833
2834 spin_unlock_irq(&tp->lock);
2835}
2836
2837static int rtl_set_mac_address(struct net_device *dev, void *p)
2838{
2839 struct rtl8169_private *tp = netdev_priv(dev);
2840 struct sockaddr *addr = p;
2841
2842 if (!is_valid_ether_addr(addr->sa_data))
2843 return -EADDRNOTAVAIL;
2844
2845 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2846
2847 rtl_rar_set(tp, dev->dev_addr);
2848
2849 return 0;
2850}
2851
5f787a1a
FR		 2852static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2853{
2854 struct rtl8169_private *tp = netdev_priv(dev);
2855 struct mii_ioctl_data *data = if_mii(ifr);
2856
8b4ab28d
FR		 2857 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2858}
5f787a1a 2859
8b4ab28d
FR		 2860static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2861{
5f787a1a
FR		 2862 switch (cmd) {
2863 case SIOCGMIIPHY:
2864 data->phy_id = 32; /* Internal PHY */
2865 return 0;
2866
2867 case SIOCGMIIREG:
2868 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2869 return 0;
2870
2871 case SIOCSMIIREG:
5f787a1a
FR		 2872 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2873 return 0;
2874 }
2875 return -EOPNOTSUPP;
2876}
2877
8b4ab28d
FR		 2878static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2879{
2880 return -EOPNOTSUPP;
2881}
2882
0e485150
FR		 2883static const struct rtl_cfg_info {
2884 void (*hw_start)(struct net_device *);
2885 unsigned int region;
2886 unsigned int align;
2887 u16 intr_event;
2888 u16 napi_event;
ccdffb9a 2889 unsigned features;
f21b75e9 2890 u8 default_ver;
0e485150
FR		 2891} rtl_cfg_infos [] = {
2892 [RTL_CFG_0] = {
2893 .hw_start = rtl_hw_start_8169,
2894 .region = 1,
e9f63f30 2895 .align = 0,
0e485150
FR		 2896 .intr_event = SYSErr | LinkChg | RxOverflow |
2897 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2898 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2899 .features = RTL_FEATURE_GMII,
2900 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2901 },
2902 [RTL_CFG_1] = {
2903 .hw_start = rtl_hw_start_8168,
2904 .region = 2,
2905 .align = 8,
2906 .intr_event = SYSErr | LinkChg | RxOverflow |
2907 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2908 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2909 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2910 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2911 },
2912 [RTL_CFG_2] = {
2913 .hw_start = rtl_hw_start_8101,
2914 .region = 2,
2915 .align = 8,
2916 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2917 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2918 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2919 .features = RTL_FEATURE_MSI,
2920 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2921 }
2922};
2923
fbac58fc
FR		 2924/* Cfg9346_Unlock assumed. */
2925static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2926 const struct rtl_cfg_info *cfg)
2927{
2928 unsigned msi = 0;
2929 u8 cfg2;
2930
2931 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2932 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2933 if (pci_enable_msi(pdev)) {
2934 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2935 } else {
2936 cfg2 |= MSIEnable;
2937 msi = RTL_FEATURE_MSI;
2938 }
2939 }
2940 RTL_W8(Config2, cfg2);
2941 return msi;
2942}
2943
2944static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2945{
2946 if (tp->features & RTL_FEATURE_MSI) {
2947 pci_disable_msi(pdev);
2948 tp->features &= ~RTL_FEATURE_MSI;
2949 }
2950}
2951
8b4ab28d
FR		 2952static const struct net_device_ops rtl8169_netdev_ops = {
2953 .ndo_open = rtl8169_open,
2954 .ndo_stop = rtl8169_close,
2955 .ndo_get_stats = rtl8169_get_stats,
00829823 2956 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2957 .ndo_tx_timeout = rtl8169_tx_timeout,
2958 .ndo_validate_addr = eth_validate_addr,
2959 .ndo_change_mtu = rtl8169_change_mtu,
2960 .ndo_set_mac_address = rtl_set_mac_address,
2961 .ndo_do_ioctl = rtl8169_ioctl,
2962 .ndo_set_multicast_list = rtl_set_rx_mode,
2963#ifdef CONFIG_R8169_VLAN
2964 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2965#endif
2966#ifdef CONFIG_NET_POLL_CONTROLLER
2967 .ndo_poll_controller = rtl8169_netpoll,
2968#endif
2969
2970};
2971
1da177e4 2972static int __devinit
4ff96fa6 2973rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2974{
0e485150
FR		 2975 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2976 const unsigned int region = cfg->region;
1da177e4 2977 struct rtl8169_private *tp;
ccdffb9a 2978 struct mii_if_info *mii;
4ff96fa6
FR		 2979 struct net_device *dev;
2980 void __iomem *ioaddr;
07d3f51f
FR		 2981 unsigned int i;
2982 int rc;
1da177e4 2983
4ff96fa6
FR		 2984 if (netif_msg_drv(&debug)) {
2985 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2986 MODULENAME, RTL8169_VERSION);
2987 }
1da177e4 2988
1da177e4 2989 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2990 if (!dev) {
b57b7e5a 2991 if (netif_msg_drv(&debug))
9b91cf9d 2992 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2993 rc = -ENOMEM;
2994 goto out;
1da177e4
LT		 2995 }
2996
1da177e4 2997 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2998 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2999 tp = netdev_priv(dev);
c4028958 3000 tp->dev = dev;
21e197f2 3001 tp->pci_dev = pdev;
b57b7e5a 3002 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3003
ccdffb9a
FR		 3004 mii = &tp->mii;
3005 mii->dev = dev;
3006 mii->mdio_read = rtl_mdio_read;
3007 mii->mdio_write = rtl_mdio_write;
3008 mii->phy_id_mask = 0x1f;
3009 mii->reg_num_mask = 0x1f;
3010 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3011
1da177e4
LT		 3012 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3013 rc = pci_enable_device(pdev);
b57b7e5a 3014 if (rc < 0) {
2e8a538d 3015 if (netif_msg_probe(tp))
9b91cf9d 3016 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 3017 goto err_out_free_dev_1;
1da177e4
LT		 3018 }
3019
3020 rc = pci_set_mwi(pdev);
3021 if (rc < 0)
4ff96fa6 3022 goto err_out_disable_2;
1da177e4 3023
1da177e4 3024 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3025 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 3026 if (netif_msg_probe(tp)) {
9b91cf9d 3027 dev_err(&pdev->dev,
bcf0bf90
FR		 3028 "region #%d not an MMIO resource, aborting\n",
3029 region);
4ff96fa6 3030 }
1da177e4 3031 rc = -ENODEV;
4ff96fa6 3032 goto err_out_mwi_3;
1da177e4 3033 }
4ff96fa6 3034
1da177e4 3035 /* check for weird/broken PCI region reporting */
bcf0bf90 3036 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 3037 if (netif_msg_probe(tp)) {
9b91cf9d 3038 dev_err(&pdev->dev,
4ff96fa6
FR		 3039 "Invalid PCI region size(s), aborting\n");
3040 }
1da177e4 3041 rc = -ENODEV;
4ff96fa6 3042 goto err_out_mwi_3;
1da177e4
LT		 3043 }
3044
3045 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3046 if (rc < 0) {
2e8a538d 3047 if (netif_msg_probe(tp))
9b91cf9d 3048 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 3049 goto err_out_mwi_3;
1da177e4
LT		 3050 }
3051
3052 tp->cp_cmd = PCIMulRW | RxChkSum;
3053
3054 if ((sizeof(dma_addr_t) > 4) &&
6a35528a 3055 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3056 tp->cp_cmd |= PCIDAC;
3057 dev->features |= NETIF_F_HIGHDMA;
3058 } else {
284901a9 3059 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3060 if (rc < 0) {
4ff96fa6 3061 if (netif_msg_probe(tp)) {
9b91cf9d 3062 dev_err(&pdev->dev,
4ff96fa6
FR		 3063 "DMA configuration failed.\n");
3064 }
3065 goto err_out_free_res_4;
1da177e4
LT		 3066 }
3067 }
3068
1da177e4 3069 /* ioremap MMIO region */
bcf0bf90 3070 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3071 if (!ioaddr) {
b57b7e5a 3072 if (netif_msg_probe(tp))
9b91cf9d 3073 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 3074 rc = -EIO;
4ff96fa6 3075 goto err_out_free_res_4;
1da177e4
LT		 3076 }
3077
9c14ceaf
FR		 3078 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3079 if (!tp->pcie_cap && netif_msg_probe(tp))
3080 dev_info(&pdev->dev, "no PCI Express capability\n");
3081
d78ad8cb 3082 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3083
3084 /* Soft reset the chip. */
3085 RTL_W8(ChipCmd, CmdReset);
3086
3087 /* Check that the chip has finished the reset. */
07d3f51f 3088 for (i = 0; i < 100; i++) {
1da177e4
LT		 3089 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3090 break;
b518fa8e 3091 msleep_interruptible(1);
1da177e4
LT		 3092 }
3093
d78ad8cb
KW		 3094 RTL_W16(IntrStatus, 0xffff);
3095
ca52efd5 3096 pci_set_master(pdev);
3097
1da177e4
LT		 3098 /* Identify chip attached to board */
3099 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3100
f21b75e9
JD		 3101 /* Use appropriate default if unknown */
3102 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3103 if (netif_msg_probe(tp)) {
3104 dev_notice(&pdev->dev,
3105 "unknown MAC, using family default\n");
3106 }
3107 tp->mac_version = cfg->default_ver;
3108 }
3109
1da177e4 3110 rtl8169_print_mac_version(tp);
1da177e4 3111
cee60c37 3112 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3113 if (tp->mac_version == rtl_chip_info[i].mac_version)
3114 break;
3115 }
cee60c37 3116 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3117 dev_err(&pdev->dev,
3118 "driver bug, MAC version not found in rtl_chip_info\n");
3119 goto err_out_msi_5;
1da177e4
LT		 3120 }
3121 tp->chipset = i;
3122
5d06a99f
FR		 3123 RTL_W8(Cfg9346, Cfg9346_Unlock);
3124 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3125 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3126 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3127 tp->features |= RTL_FEATURE_WOL;
3128 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3129 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3130 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3131 RTL_W8(Cfg9346, Cfg9346_Lock);
3132
66ec5d4f
FR		 3133 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3134 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3135 tp->set_speed = rtl8169_set_speed_tbi;
3136 tp->get_settings = rtl8169_gset_tbi;
3137 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3138 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3139 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3140 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3141
64e4bfb4 3142 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3143 } else {
3144 tp->set_speed = rtl8169_set_speed_xmii;
3145 tp->get_settings = rtl8169_gset_xmii;
3146 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3147 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3148 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3149 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3150 }
3151
df58ef51
FR		 3152 spin_lock_init(&tp->lock);
3153
738e1e69
PV		 3154 tp->mmio_addr = ioaddr;
3155
7bf6bf48 3156 /* Get MAC address */
1da177e4
LT		 3157 for (i = 0; i < MAC_ADDR_LEN; i++)
3158 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3159 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3160
1da177e4 3161 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3162 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3163 dev->irq = pdev->irq;
3164 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3165
bea3348e 3166 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3167
3168#ifdef CONFIG_R8169_VLAN
3169 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3170#endif
3171
3172 tp->intr_mask = 0xffff;
0e485150
FR		 3173 tp->align = cfg->align;
3174 tp->hw_start = cfg->hw_start;
3175 tp->intr_event = cfg->intr_event;
3176 tp->napi_event = cfg->napi_event;
1da177e4 3177
2efa53f3
FR		 3178 init_timer(&tp->timer);
3179 tp->timer.data = (unsigned long) dev;
3180 tp->timer.function = rtl8169_phy_timer;
3181
1da177e4 3182 rc = register_netdev(dev);
4ff96fa6 3183 if (rc < 0)
fbac58fc 3184 goto err_out_msi_5;
1da177e4
LT		 3185
3186 pci_set_drvdata(pdev, dev);
3187
b57b7e5a 3188 if (netif_msg_probe(tp)) {
21d57363 3189 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
96b9709c 3190
b57b7e5a
SH		 3191 printk(KERN_INFO "%s: %s at 0x%lx, "
3192 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 3193 "XID %08x IRQ %d\n",
b57b7e5a 3194 dev->name,
bcf0bf90 3195 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 3196 dev->base_addr,
3197 dev->dev_addr[0], dev->dev_addr[1],
3198 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 3199 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 3200 }
1da177e4 3201
4ff96fa6 3202 rtl8169_init_phy(dev, tp);
05af2142
SW		 3203
3204 /*
3205 * Pretend we are using VLANs; This bypasses a nasty bug where
3206 * Interrupts stop flowing on high load on 8110SCd controllers.
3207 */
3208 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3209 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3210
8b76ab39 3211 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3212
4ff96fa6
FR		 3213out:
3214 return rc;
1da177e4 3215
fbac58fc
FR		 3216err_out_msi_5:
3217 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 3218 iounmap(ioaddr);
3219err_out_free_res_4:
3220 pci_release_regions(pdev);
3221err_out_mwi_3:
3222 pci_clear_mwi(pdev);
3223err_out_disable_2:
3224 pci_disable_device(pdev);
3225err_out_free_dev_1:
3226 free_netdev(dev);
3227 goto out;
1da177e4
LT		 3228}
3229
07d3f51f 3230static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3231{
3232 struct net_device *dev = pci_get_drvdata(pdev);
3233 struct rtl8169_private *tp = netdev_priv(dev);
3234
eb2a021c
FR		 3235 flush_scheduled_work();
3236
1da177e4 3237 unregister_netdev(dev);
fbac58fc 3238 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3239 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3240 pci_set_drvdata(pdev, NULL);
3241}
3242
1da177e4
LT		 3243static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3244 struct net_device *dev)
3245{
3246 unsigned int mtu = dev->mtu;
3247
3248 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
3249}
3250
3251static int rtl8169_open(struct net_device *dev)
3252{
3253 struct rtl8169_private *tp = netdev_priv(dev);
3254 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3255 int retval = -ENOMEM;
1da177e4 3256
1da177e4 3257
99f252b0 3258 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 3259
3260 /*
3261 * Rx and Tx desscriptors needs 256 bytes alignment.
3262 * pci_alloc_consistent provides more.
3263 */
3264 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3265 &tp->TxPhyAddr);
3266 if (!tp->TxDescArray)
99f252b0 3267 goto out;
1da177e4
LT		 3268
3269 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3270 &tp->RxPhyAddr);
3271 if (!tp->RxDescArray)
99f252b0 3272 goto err_free_tx_0;
1da177e4
LT		 3273
3274 retval = rtl8169_init_ring(dev);
3275 if (retval < 0)
99f252b0 3276 goto err_free_rx_1;
1da177e4 3277
c4028958 3278 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3279
99f252b0
FR		 3280 smp_mb();
3281
fbac58fc
FR		 3282 retval = request_irq(dev->irq, rtl8169_interrupt,
3283 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3284 dev->name, dev);
3285 if (retval < 0)
3286 goto err_release_ring_2;
3287
bea3348e 3288 napi_enable(&tp->napi);
bea3348e 3289
07ce4064 3290 rtl_hw_start(dev);
1da177e4
LT		 3291
3292 rtl8169_request_timer(dev);
3293
3294 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3295out:
3296 return retval;
3297
99f252b0
FR		 3298err_release_ring_2:
3299 rtl8169_rx_clear(tp);
3300err_free_rx_1:
1da177e4
LT		 3301 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3302 tp->RxPhyAddr);
99f252b0 3303err_free_tx_0:
1da177e4
LT		 3304 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3305 tp->TxPhyAddr);
1da177e4
LT		 3306 goto out;
3307}
3308
3309static void rtl8169_hw_reset(void __iomem *ioaddr)
3310{
3311 /* Disable interrupts */
3312 rtl8169_irq_mask_and_ack(ioaddr);
3313
3314 /* Reset the chipset */
3315 RTL_W8(ChipCmd, CmdReset);
3316
3317 /* PCI commit */
3318 RTL_R8(ChipCmd);
3319}
3320
7f796d83 3321static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3322{
3323 void __iomem *ioaddr = tp->mmio_addr;
3324 u32 cfg = rtl8169_rx_config;
3325
3326 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3327 RTL_W32(RxConfig, cfg);
3328
3329 /* Set DMA burst size and Interframe Gap Time */
3330 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3331 (InterFrameGap << TxInterFrameGapShift));
3332}
3333
07ce4064 3334static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3335{
3336 struct rtl8169_private *tp = netdev_priv(dev);
3337 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3338 unsigned int i;
1da177e4
LT		 3339
3340 /* Soft reset the chip. */
3341 RTL_W8(ChipCmd, CmdReset);
3342
3343 /* Check that the chip has finished the reset. */
07d3f51f 3344 for (i = 0; i < 100; i++) {
1da177e4
LT		 3345 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3346 break;
b518fa8e 3347 msleep_interruptible(1);
1da177e4
LT		 3348 }
3349
07ce4064
FR		 3350 tp->hw_start(dev);
3351
07ce4064
FR		 3352 netif_start_queue(dev);
3353}
3354
3355
7f796d83
FR		 3356static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3357 void __iomem *ioaddr)
3358{
3359 /*
3360 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3361 * register to be written before TxDescAddrLow to work.
3362 * Switching from MMIO to I/O access fixes the issue as well.
3363 */
3364 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3365 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3366 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3367 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3368}
3369
3370static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3371{
3372 u16 cmd;
3373
3374 cmd = RTL_R16(CPlusCmd);
3375 RTL_W16(CPlusCmd, cmd);
3376 return cmd;
3377}
3378
fdd7b4c3 3379static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3380{
3381 /* Low hurts. Let's disable the filtering. */
fdd7b4c3 3382 RTL_W16(RxMaxSize, rx_buf_sz);
7f796d83
FR		 3383}
3384
6dccd16b
FR		 3385static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3386{
3387 struct {
3388 u32 mac_version;
3389 u32 clk;
3390 u32 val;
3391 } cfg2_info [] = {
3392 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3393 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3394 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3395 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3396 }, *p = cfg2_info;
3397 unsigned int i;
3398 u32 clk;
3399
3400 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3401 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3402 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3403 RTL_W32(0x7c, p->val);
3404 break;
3405 }
3406 }
3407}
3408
07ce4064
FR		 3409static void rtl_hw_start_8169(struct net_device *dev)
3410{
3411 struct rtl8169_private *tp = netdev_priv(dev);
3412 void __iomem *ioaddr = tp->mmio_addr;
3413 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3414
9cb427b6
FR		 3415 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3416 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3417 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3418 }
3419
1da177e4 3420 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3421 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3422 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3424 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3425 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3426
1da177e4
LT		 3427 RTL_W8(EarlyTxThres, EarlyTxThld);
3428
fdd7b4c3 3429 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3430
c946b304
FR		 3431 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3432 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3433 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3434 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3435 rtl_set_rx_tx_config_registers(tp);
1da177e4 3436
7f796d83 3437 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3438
bcf0bf90
FR		 3439 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3440 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3441 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3442 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3443 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3444 }
3445
bcf0bf90
FR		 3446 RTL_W16(CPlusCmd, tp->cp_cmd);
3447
6dccd16b
FR		 3448 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3449
1da177e4
LT		 3450 /*
3451 * Undocumented corner. Supposedly:
3452 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3453 */
3454 RTL_W16(IntrMitigate, 0x0000);
3455
7f796d83 3456 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3457
c946b304
FR		 3458 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3459 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3460 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3461 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3462 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3463 rtl_set_rx_tx_config_registers(tp);
3464 }
3465
1da177e4 3466 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3467
3468 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3469 RTL_R8(IntrMask);
1da177e4
LT		 3470
3471 RTL_W32(RxMissed, 0);
3472
07ce4064 3473 rtl_set_rx_mode(dev);
1da177e4
LT		 3474
3475 /* no early-rx interrupts */
3476 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3477
3478 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3479 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3480}
1da177e4 3481
9c14ceaf 3482static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3483{
9c14ceaf
FR		 3484 struct net_device *dev = pci_get_drvdata(pdev);
3485 struct rtl8169_private *tp = netdev_priv(dev);
3486 int cap = tp->pcie_cap;
3487
3488 if (cap) {
3489 u16 ctl;
458a9f61 3490
9c14ceaf
FR		 3491 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3492 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3493 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3494 }
458a9f61
FR		 3495}
3496
dacf8154
FR		 3497static void rtl_csi_access_enable(void __iomem *ioaddr)
3498{
3499 u32 csi;
3500
3501 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3502 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3503}
3504
3505struct ephy_info {
3506 unsigned int offset;
3507 u16 mask;
3508 u16 bits;
3509};
3510
3511static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
3512{
3513 u16 w;
3514
3515 while (len-- > 0) {
3516 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3517 rtl_ephy_write(ioaddr, e->offset, w);
3518 e++;
3519 }
3520}
3521
b726e493
FR		 3522static void rtl_disable_clock_request(struct pci_dev *pdev)
3523{
3524 struct net_device *dev = pci_get_drvdata(pdev);
3525 struct rtl8169_private *tp = netdev_priv(dev);
3526 int cap = tp->pcie_cap;
3527
3528 if (cap) {
3529 u16 ctl;
3530
3531 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3532 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3533 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3534 }
3535}
3536
3537#define R8168_CPCMD_QUIRK_MASK (\
3538 EnableBist | \
3539 Mac_dbgo_oe | \
3540 Force_half_dup | \
3541 Force_rxflow_en | \
3542 Force_txflow_en | \
3543 Cxpl_dbg_sel | \
3544 ASF | \
3545 PktCntrDisable | \
3546 Mac_dbgo_sel)
3547
219a1e9d
FR		 3548static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3549{
b726e493
FR		 3550 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3551
3552 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3553
2e68ae44
FR		 3554 rtl_tx_performance_tweak(pdev,
3555 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3556}
3557
3558static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3559{
3560 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3561
3562 RTL_W8(EarlyTxThres, EarlyTxThld);
3563
3564 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3565}
3566
3567static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3568{
b726e493
FR		 3569 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3570
3571 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3572
219a1e9d 3573 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3574
3575 rtl_disable_clock_request(pdev);
3576
3577 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3578}
3579
ef3386f0 3580static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3581{
b726e493
FR		 3582 static struct ephy_info e_info_8168cp[] = {
3583 { 0x01, 0, 0x0001 },
3584 { 0x02, 0x0800, 0x1000 },
3585 { 0x03, 0, 0x0042 },
3586 { 0x06, 0x0080, 0x0000 },
3587 { 0x07, 0, 0x2000 }
3588 };
3589
3590 rtl_csi_access_enable(ioaddr);
3591
3592 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3593
219a1e9d
FR		 3594 __rtl_hw_start_8168cp(ioaddr, pdev);
3595}
3596
ef3386f0
FR		 3597static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3598{
3599 rtl_csi_access_enable(ioaddr);
3600
3601 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3602
3603 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3604
3605 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3606}
3607
7f3e3d3a
FR		 3608static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3609{
3610 rtl_csi_access_enable(ioaddr);
3611
3612 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3613
3614 /* Magic. */
3615 RTL_W8(DBG_REG, 0x20);
3616
3617 RTL_W8(EarlyTxThres, EarlyTxThld);
3618
3619 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3620
3621 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3622}
3623
219a1e9d
FR		 3624static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3625{
b726e493
FR		 3626 static struct ephy_info e_info_8168c_1[] = {
3627 { 0x02, 0x0800, 0x1000 },
3628 { 0x03, 0, 0x0002 },
3629 { 0x06, 0x0080, 0x0000 }
3630 };
3631
3632 rtl_csi_access_enable(ioaddr);
3633
3634 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3635
3636 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3637
219a1e9d
FR		 3638 __rtl_hw_start_8168cp(ioaddr, pdev);
3639}
3640
3641static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3642{
b726e493
FR		 3643 static struct ephy_info e_info_8168c_2[] = {
3644 { 0x01, 0, 0x0001 },
3645 { 0x03, 0x0400, 0x0220 }
3646 };
3647
3648 rtl_csi_access_enable(ioaddr);
3649
3650 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3651
219a1e9d
FR		 3652 __rtl_hw_start_8168cp(ioaddr, pdev);
3653}
3654
197ff761
FR		 3655static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3656{
3657 rtl_hw_start_8168c_2(ioaddr, pdev);
3658}
3659
6fb07058
FR		 3660static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3661{
3662 rtl_csi_access_enable(ioaddr);
3663
3664 __rtl_hw_start_8168cp(ioaddr, pdev);
3665}
3666
5b538df9
FR		 3667static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3668{
3669 rtl_csi_access_enable(ioaddr);
3670
3671 rtl_disable_clock_request(pdev);
3672
3673 RTL_W8(EarlyTxThres, EarlyTxThld);
3674
3675 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3676
3677 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3678}
3679
07ce4064
FR		 3680static void rtl_hw_start_8168(struct net_device *dev)
3681{
2dd99530
FR		 3682 struct rtl8169_private *tp = netdev_priv(dev);
3683 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3684 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3685
3686 RTL_W8(Cfg9346, Cfg9346_Unlock);
3687
3688 RTL_W8(EarlyTxThres, EarlyTxThld);
3689
fdd7b4c3 3690 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3691
0e485150 3692 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3693
3694 RTL_W16(CPlusCmd, tp->cp_cmd);
3695
0e485150 3696 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3697
0e485150
FR		 3698 /* Work around for RxFIFO overflow. */
3699 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3700 tp->intr_event |= RxFIFOOver | PCSTimeout;
3701 tp->intr_event &= ~RxOverflow;
3702 }
3703
3704 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3705
b8363901
FR		 3706 rtl_set_rx_mode(dev);
3707
3708 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3709 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3710
3711 RTL_R8(IntrMask);
3712
219a1e9d
FR		 3713 switch (tp->mac_version) {
3714 case RTL_GIGA_MAC_VER_11:
3715 rtl_hw_start_8168bb(ioaddr, pdev);
3716 break;
3717
3718 case RTL_GIGA_MAC_VER_12:
3719 case RTL_GIGA_MAC_VER_17:
3720 rtl_hw_start_8168bef(ioaddr, pdev);
3721 break;
3722
3723 case RTL_GIGA_MAC_VER_18:
ef3386f0 3724 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3725 break;
3726
3727 case RTL_GIGA_MAC_VER_19:
3728 rtl_hw_start_8168c_1(ioaddr, pdev);
3729 break;
3730
3731 case RTL_GIGA_MAC_VER_20:
3732 rtl_hw_start_8168c_2(ioaddr, pdev);
3733 break;
3734
197ff761
FR		 3735 case RTL_GIGA_MAC_VER_21:
3736 rtl_hw_start_8168c_3(ioaddr, pdev);
3737 break;
3738
6fb07058
FR		 3739 case RTL_GIGA_MAC_VER_22:
3740 rtl_hw_start_8168c_4(ioaddr, pdev);
3741 break;
3742
ef3386f0
FR		 3743 case RTL_GIGA_MAC_VER_23:
3744 rtl_hw_start_8168cp_2(ioaddr, pdev);
3745 break;
3746
7f3e3d3a
FR		 3747 case RTL_GIGA_MAC_VER_24:
3748 rtl_hw_start_8168cp_3(ioaddr, pdev);
3749 break;
3750
5b538df9 3751 case RTL_GIGA_MAC_VER_25:
daf9df6d 3752 case RTL_GIGA_MAC_VER_26:
3753 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3754 rtl_hw_start_8168d(ioaddr, pdev);
3755 break;
3756
219a1e9d
FR		 3757 default:
3758 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3759 dev->name, tp->mac_version);
3760 break;
3761 }
2dd99530 3762
0e485150
FR		 3763 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3764
b8363901
FR		 3765 RTL_W8(Cfg9346, Cfg9346_Lock);
3766
2dd99530 3767 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3768
0e485150 3769 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3770}
1da177e4 3771
2857ffb7
FR		 3772#define R810X_CPCMD_QUIRK_MASK (\
3773 EnableBist | \
3774 Mac_dbgo_oe | \
3775 Force_half_dup | \
5edcc537 3776 Force_rxflow_en | \
2857ffb7
FR		 3777 Force_txflow_en | \
3778 Cxpl_dbg_sel | \
3779 ASF | \
3780 PktCntrDisable | \
3781 PCIDAC | \
3782 PCIMulRW)
3783
3784static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3785{
3786 static struct ephy_info e_info_8102e_1[] = {
3787 { 0x01, 0, 0x6e65 },
3788 { 0x02, 0, 0x091f },
3789 { 0x03, 0, 0xc2f9 },
3790 { 0x06, 0, 0xafb5 },
3791 { 0x07, 0, 0x0e00 },
3792 { 0x19, 0, 0xec80 },
3793 { 0x01, 0, 0x2e65 },
3794 { 0x01, 0, 0x6e65 }
3795 };
3796 u8 cfg1;
3797
3798 rtl_csi_access_enable(ioaddr);
3799
3800 RTL_W8(DBG_REG, FIX_NAK_1);
3801
3802 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3803
3804 RTL_W8(Config1,
3805 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3806 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3807
3808 cfg1 = RTL_R8(Config1);
3809 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3810 RTL_W8(Config1, cfg1 & ~LEDS0);
3811
3812 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3813
3814 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3815}
3816
3817static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3818{
3819 rtl_csi_access_enable(ioaddr);
3820
3821 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3822
3823 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3824 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3825
3826 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3827}
3828
3829static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3830{
3831 rtl_hw_start_8102e_2(ioaddr, pdev);
3832
3833 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3834}
3835
07ce4064
FR		 3836static void rtl_hw_start_8101(struct net_device *dev)
3837{
cdf1a608
FR		 3838 struct rtl8169_private *tp = netdev_priv(dev);
3839 void __iomem *ioaddr = tp->mmio_addr;
3840 struct pci_dev *pdev = tp->pci_dev;
3841
e3cf0cc0
FR		 3842 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3843 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3844 int cap = tp->pcie_cap;
3845
3846 if (cap) {
3847 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3848 PCI_EXP_DEVCTL_NOSNOOP_EN);
3849 }
cdf1a608
FR		 3850 }
3851
2857ffb7
FR		 3852 switch (tp->mac_version) {
3853 case RTL_GIGA_MAC_VER_07:
3854 rtl_hw_start_8102e_1(ioaddr, pdev);
3855 break;
3856
3857 case RTL_GIGA_MAC_VER_08:
3858 rtl_hw_start_8102e_3(ioaddr, pdev);
3859 break;
3860
3861 case RTL_GIGA_MAC_VER_09:
3862 rtl_hw_start_8102e_2(ioaddr, pdev);
3863 break;
cdf1a608
FR		 3864 }
3865
3866 RTL_W8(Cfg9346, Cfg9346_Unlock);
3867
3868 RTL_W8(EarlyTxThres, EarlyTxThld);
3869
fdd7b4c3 3870 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3871
3872 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3873
3874 RTL_W16(CPlusCmd, tp->cp_cmd);
3875
3876 RTL_W16(IntrMitigate, 0x0000);
3877
3878 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3879
3880 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3881 rtl_set_rx_tx_config_registers(tp);
3882
3883 RTL_W8(Cfg9346, Cfg9346_Lock);
3884
3885 RTL_R8(IntrMask);
3886
cdf1a608
FR		 3887 rtl_set_rx_mode(dev);
3888
0e485150
FR		 3889 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3890
cdf1a608 3891 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3892
0e485150 3893 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3894}
3895
3896static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3897{
3898 struct rtl8169_private *tp = netdev_priv(dev);
3899 int ret = 0;
3900
3901 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3902 return -EINVAL;
3903
3904 dev->mtu = new_mtu;
3905
3906 if (!netif_running(dev))
3907 goto out;
3908
3909 rtl8169_down(dev);
3910
3911 rtl8169_set_rxbufsize(tp, dev);
3912
3913 ret = rtl8169_init_ring(dev);
3914 if (ret < 0)
3915 goto out;
3916
bea3348e 3917 napi_enable(&tp->napi);
1da177e4 3918
07ce4064 3919 rtl_hw_start(dev);
1da177e4
LT		 3920
3921 rtl8169_request_timer(dev);
3922
3923out:
3924 return ret;
3925}
3926
3927static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3928{
95e0918d 3929 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3930 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3931}
3932
3933static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3934 struct sk_buff **sk_buff, struct RxDesc *desc)
3935{
3936 struct pci_dev *pdev = tp->pci_dev;
3937
3938 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3939 PCI_DMA_FROMDEVICE);
3940 dev_kfree_skb(*sk_buff);
3941 *sk_buff = NULL;
3942 rtl8169_make_unusable_by_asic(desc);
3943}
3944
3945static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3946{
3947 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3948
3949 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3950}
3951
3952static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3953 u32 rx_buf_sz)
3954{
3955 desc->addr = cpu_to_le64(mapping);
3956 wmb();
3957 rtl8169_mark_to_asic(desc, rx_buf_sz);
3958}
3959
15d31758
SH		 3960static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3961 struct net_device *dev,
3962 struct RxDesc *desc, int rx_buf_sz,
3963 unsigned int align)
1da177e4
LT		 3964{
3965 struct sk_buff *skb;
3966 dma_addr_t mapping;
e9f63f30 3967 unsigned int pad;
1da177e4 3968
e9f63f30
FR		 3969 pad = align ? align : NET_IP_ALIGN;
3970
3971 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3972 if (!skb)
3973 goto err_out;
3974
e9f63f30 3975 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3976
689be439 3977 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3978 PCI_DMA_FROMDEVICE);
3979
3980 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3981out:
15d31758 3982 return skb;
1da177e4
LT		 3983
3984err_out:
1da177e4
LT		 3985 rtl8169_make_unusable_by_asic(desc);
3986 goto out;
3987}
3988
3989static void rtl8169_rx_clear(struct rtl8169_private *tp)
3990{
07d3f51f 3991 unsigned int i;
1da177e4
LT		 3992
3993 for (i = 0; i < NUM_RX_DESC; i++) {
3994 if (tp->Rx_skbuff[i]) {
3995 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3996 tp->RxDescArray + i);
3997 }
3998 }
3999}
4000
4001static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4002 u32 start, u32 end)
4003{
4004 u32 cur;
5b0384f4 4005
4ae47c2d 4006 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 4007 struct sk_buff *skb;
4008 unsigned int i = cur % NUM_RX_DESC;
1da177e4 4009
4ae47c2d
FR		 4010 WARN_ON((s32)(end - cur) < 0);
4011
1da177e4
LT		 4012 if (tp->Rx_skbuff[i])
4013 continue;
bcf0bf90 4014
15d31758
SH		 4015 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4016 tp->RxDescArray + i,
4017 tp->rx_buf_sz, tp->align);
4018 if (!skb)
1da177e4 4019 break;
15d31758
SH		 4020
4021 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 4022 }
4023 return cur - start;
4024}
4025
4026static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4027{
4028 desc->opts1 |= cpu_to_le32(RingEnd);
4029}
4030
4031static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4032{
4033 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4034}
4035
4036static int rtl8169_init_ring(struct net_device *dev)
4037{
4038 struct rtl8169_private *tp = netdev_priv(dev);
4039
4040 rtl8169_init_ring_indexes(tp);
4041
4042 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4043 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4044
4045 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4046 goto err_out;
4047
4048 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4049
4050 return 0;
4051
4052err_out:
4053 rtl8169_rx_clear(tp);
4054 return -ENOMEM;
4055}
4056
4057static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4058 struct TxDesc *desc)
4059{
4060 unsigned int len = tx_skb->len;
4061
4062 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4063 desc->opts1 = 0x00;
4064 desc->opts2 = 0x00;
4065 desc->addr = 0x00;
4066 tx_skb->len = 0;
4067}
4068
4069static void rtl8169_tx_clear(struct rtl8169_private *tp)
4070{
4071 unsigned int i;
4072
4073 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4074 unsigned int entry = i % NUM_TX_DESC;
4075 struct ring_info *tx_skb = tp->tx_skb + entry;
4076 unsigned int len = tx_skb->len;
4077
4078 if (len) {
4079 struct sk_buff *skb = tx_skb->skb;
4080
4081 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4082 tp->TxDescArray + entry);
4083 if (skb) {
4084 dev_kfree_skb(skb);
4085 tx_skb->skb = NULL;
4086 }
cebf8cc7 4087 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4088 }
4089 }
4090 tp->cur_tx = tp->dirty_tx = 0;
4091}
4092
c4028958 4093static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4094{
4095 struct rtl8169_private *tp = netdev_priv(dev);
4096
c4028958 4097 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4098 schedule_delayed_work(&tp->task, 4);
4099}
4100
4101static void rtl8169_wait_for_quiescence(struct net_device *dev)
4102{
4103 struct rtl8169_private *tp = netdev_priv(dev);
4104 void __iomem *ioaddr = tp->mmio_addr;
4105
4106 synchronize_irq(dev->irq);
4107
4108 /* Wait for any pending NAPI task to complete */
bea3348e 4109 napi_disable(&tp->napi);
1da177e4
LT		 4110
4111 rtl8169_irq_mask_and_ack(ioaddr);
4112
d1d08d12
DM		 4113 tp->intr_mask = 0xffff;
4114 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4115 napi_enable(&tp->napi);
1da177e4
LT		 4116}
4117
c4028958 4118static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4119{
c4028958
DH		 4120 struct rtl8169_private *tp =
4121 container_of(work, struct rtl8169_private, task.work);
4122 struct net_device *dev = tp->dev;
1da177e4
LT		 4123 int ret;
4124
eb2a021c
FR		 4125 rtnl_lock();
4126
4127 if (!netif_running(dev))
4128 goto out_unlock;
4129
4130 rtl8169_wait_for_quiescence(dev);
4131 rtl8169_close(dev);
1da177e4
LT		 4132
4133 ret = rtl8169_open(dev);
4134 if (unlikely(ret < 0)) {
07d3f51f 4135 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 4136 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 4137 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 4138 }
4139 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4140 }
eb2a021c
FR		 4141
4142out_unlock:
4143 rtnl_unlock();
1da177e4
LT		 4144}
4145
c4028958 4146static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4147{
c4028958
DH		 4148 struct rtl8169_private *tp =
4149 container_of(work, struct rtl8169_private, task.work);
4150 struct net_device *dev = tp->dev;
1da177e4 4151
eb2a021c
FR		 4152 rtnl_lock();
4153
1da177e4 4154 if (!netif_running(dev))
eb2a021c 4155 goto out_unlock;
1da177e4
LT		 4156
4157 rtl8169_wait_for_quiescence(dev);
4158
bea3348e 4159 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4160 rtl8169_tx_clear(tp);
4161
4162 if (tp->dirty_rx == tp->cur_rx) {
4163 rtl8169_init_ring_indexes(tp);
07ce4064 4164 rtl_hw_start(dev);
1da177e4 4165 netif_wake_queue(dev);
cebf8cc7 4166 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4167 } else {
07d3f51f 4168 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 4169 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 4170 dev->name);
1da177e4
LT		 4171 }
4172 rtl8169_schedule_work(dev, rtl8169_reset_task);
4173 }
eb2a021c
FR		 4174
4175out_unlock:
4176 rtnl_unlock();
1da177e4
LT		 4177}
4178
4179static void rtl8169_tx_timeout(struct net_device *dev)
4180{
4181 struct rtl8169_private *tp = netdev_priv(dev);
4182
4183 rtl8169_hw_reset(tp->mmio_addr);
4184
4185 /* Let's wait a bit while any (async) irq lands on */
4186 rtl8169_schedule_work(dev, rtl8169_reset_task);
4187}
4188
4189static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4190 u32 opts1)
4191{
4192 struct skb_shared_info *info = skb_shinfo(skb);
4193 unsigned int cur_frag, entry;
a6343afb 4194 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4195
4196 entry = tp->cur_tx;
4197 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4198 skb_frag_t *frag = info->frags + cur_frag;
4199 dma_addr_t mapping;
4200 u32 status, len;
4201 void *addr;
4202
4203 entry = (entry + 1) % NUM_TX_DESC;
4204
4205 txd = tp->TxDescArray + entry;
4206 len = frag->size;
4207 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4208 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4209
4210 /* anti gcc 2.95.3 bugware (sic) */
4211 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4212
4213 txd->opts1 = cpu_to_le32(status);
4214 txd->addr = cpu_to_le64(mapping);
4215
4216 tp->tx_skb[entry].len = len;
4217 }
4218
4219 if (cur_frag) {
4220 tp->tx_skb[entry].skb = skb;
4221 txd->opts1 |= cpu_to_le32(LastFrag);
4222 }
4223
4224 return cur_frag;
4225}
4226
4227static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4228{
4229 if (dev->features & NETIF_F_TSO) {
7967168c 4230 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4231
4232 if (mss)
4233 return LargeSend | ((mss & MSSMask) << MSSShift);
4234 }
84fa7933 4235 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4236 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4237
4238 if (ip->protocol == IPPROTO_TCP)
4239 return IPCS | TCPCS;
4240 else if (ip->protocol == IPPROTO_UDP)
4241 return IPCS | UDPCS;
4242 WARN_ON(1); /* we need a WARN() */
4243 }
4244 return 0;
4245}
4246
61357325
SH		 4247static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4248 struct net_device *dev)
1da177e4
LT		 4249{
4250 struct rtl8169_private *tp = netdev_priv(dev);
4251 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4252 struct TxDesc *txd = tp->TxDescArray + entry;
4253 void __iomem *ioaddr = tp->mmio_addr;
4254 dma_addr_t mapping;
4255 u32 status, len;
4256 u32 opts1;
5b0384f4 4257
1da177e4 4258 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 4259 if (netif_msg_drv(tp)) {
4260 printk(KERN_ERR
4261 "%s: BUG! Tx Ring full when queue awake!\n",
4262 dev->name);
4263 }
1da177e4
LT		 4264 goto err_stop;
4265 }
4266
4267 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4268 goto err_stop;
4269
4270 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4271
4272 frags = rtl8169_xmit_frags(tp, skb, opts1);
4273 if (frags) {
4274 len = skb_headlen(skb);
4275 opts1 |= FirstFrag;
4276 } else {
4277 len = skb->len;
1da177e4
LT		 4278 opts1 |= FirstFrag | LastFrag;
4279 tp->tx_skb[entry].skb = skb;
4280 }
4281
4282 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4283
4284 tp->tx_skb[entry].len = len;
4285 txd->addr = cpu_to_le64(mapping);
4286 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4287
4288 wmb();
4289
4290 /* anti gcc 2.95.3 bugware (sic) */
4291 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4292 txd->opts1 = cpu_to_le32(status);
4293
1da177e4
LT		 4294 tp->cur_tx += frags + 1;
4295
4296 smp_wmb();
4297
275391a4 4298 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4299
4300 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4301 netif_stop_queue(dev);
4302 smp_rmb();
4303 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4304 netif_wake_queue(dev);
4305 }
4306
61357325 4307 return NETDEV_TX_OK;
1da177e4
LT		 4308
4309err_stop:
4310 netif_stop_queue(dev);
cebf8cc7 4311 dev->stats.tx_dropped++;
61357325 4312 return NETDEV_TX_BUSY;
1da177e4
LT		 4313}
4314
4315static void rtl8169_pcierr_interrupt(struct net_device *dev)
4316{
4317 struct rtl8169_private *tp = netdev_priv(dev);
4318 struct pci_dev *pdev = tp->pci_dev;
4319 void __iomem *ioaddr = tp->mmio_addr;
4320 u16 pci_status, pci_cmd;
4321
4322 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4323 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4324
b57b7e5a
SH		 4325 if (netif_msg_intr(tp)) {
4326 printk(KERN_ERR
4327 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4328 dev->name, pci_cmd, pci_status);
4329 }
1da177e4
LT		 4330
4331 /*
4332 * The recovery sequence below admits a very elaborated explanation:
4333 * - it seems to work;
d03902b8
FR		 4334 * - I did not see what else could be done;
4335 * - it makes iop3xx happy.
1da177e4
LT		 4336 *
4337 * Feel free to adjust to your needs.
4338 */
a27993f3 4339 if (pdev->broken_parity_status)
d03902b8
FR		 4340 pci_cmd &= ~PCI_COMMAND_PARITY;
4341 else
4342 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4343
4344 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4345
4346 pci_write_config_word(pdev, PCI_STATUS,
4347 pci_status & (PCI_STATUS_DETECTED_PARITY |
4348 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4349 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4350
4351 /* The infamous DAC f*ckup only happens at boot time */
4352 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 4353 if (netif_msg_intr(tp))
4354 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 4355 tp->cp_cmd &= ~PCIDAC;
4356 RTL_W16(CPlusCmd, tp->cp_cmd);
4357 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4358 }
4359
4360 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4361
4362 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4363}
4364
07d3f51f
FR		 4365static void rtl8169_tx_interrupt(struct net_device *dev,
4366 struct rtl8169_private *tp,
4367 void __iomem *ioaddr)
1da177e4
LT		 4368{
4369 unsigned int dirty_tx, tx_left;
4370
1da177e4
LT		 4371 dirty_tx = tp->dirty_tx;
4372 smp_rmb();
4373 tx_left = tp->cur_tx - dirty_tx;
4374
4375 while (tx_left > 0) {
4376 unsigned int entry = dirty_tx % NUM_TX_DESC;
4377 struct ring_info *tx_skb = tp->tx_skb + entry;
4378 u32 len = tx_skb->len;
4379 u32 status;
4380
4381 rmb();
4382 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4383 if (status & DescOwn)
4384 break;
4385
cebf8cc7
FR		 4386 dev->stats.tx_bytes += len;
4387 dev->stats.tx_packets++;
1da177e4
LT		 4388
4389 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4390
4391 if (status & LastFrag) {
87433bfc 4392 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4393 tx_skb->skb = NULL;
4394 }
4395 dirty_tx++;
4396 tx_left--;
4397 }
4398
4399 if (tp->dirty_tx != dirty_tx) {
4400 tp->dirty_tx = dirty_tx;
4401 smp_wmb();
4402 if (netif_queue_stopped(dev) &&
4403 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4404 netif_wake_queue(dev);
4405 }
d78ae2dc
FR		 4406 /*
4407 * 8168 hack: TxPoll requests are lost when the Tx packets are
4408 * too close. Let's kick an extra TxPoll request when a burst
4409 * of start_xmit activity is detected (if it is not detected,
4410 * it is slow enough). -- FR
4411 */
4412 smp_rmb();
4413 if (tp->cur_tx != dirty_tx)
4414 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4415 }
4416}
4417
126fa4b9
FR		 4418static inline int rtl8169_fragmented_frame(u32 status)
4419{
4420 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4421}
4422
1da177e4
LT		 4423static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4424{
4425 u32 opts1 = le32_to_cpu(desc->opts1);
4426 u32 status = opts1 & RxProtoMask;
4427
4428 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4429 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4430 ((status == RxProtoIP) && !(opts1 & IPFail)))
4431 skb->ip_summed = CHECKSUM_UNNECESSARY;
4432 else
4433 skb->ip_summed = CHECKSUM_NONE;
4434}
4435
07d3f51f
FR		 4436static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4437 struct rtl8169_private *tp, int pkt_size,
4438 dma_addr_t addr)
1da177e4 4439{
b449655f
SH		 4440 struct sk_buff *skb;
4441 bool done = false;
1da177e4 4442
b449655f
SH		 4443 if (pkt_size >= rx_copybreak)
4444 goto out;
1da177e4 4445
07d3f51f 4446 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 4447 if (!skb)
4448 goto out;
4449
07d3f51f
FR		 4450 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4451 PCI_DMA_FROMDEVICE);
86402234 4452 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 4453 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4454 *sk_buff = skb;
4455 done = true;
4456out:
4457 return done;
1da177e4
LT		 4458}
4459
07d3f51f
FR		 4460static int rtl8169_rx_interrupt(struct net_device *dev,
4461 struct rtl8169_private *tp,
bea3348e 4462 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4463{
4464 unsigned int cur_rx, rx_left;
4465 unsigned int delta, count;
4466
1da177e4
LT		 4467 cur_rx = tp->cur_rx;
4468 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4469 rx_left = min(rx_left, budget);
1da177e4 4470
4dcb7d33 4471 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4472 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4473 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4474 u32 status;
4475
4476 rmb();
126fa4b9 4477 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4478
4479 if (status & DescOwn)
4480 break;
4dcb7d33 4481 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 4482 if (netif_msg_rx_err(tp)) {
4483 printk(KERN_INFO
4484 "%s: Rx ERROR. status = %08x\n",
4485 dev->name, status);
4486 }
cebf8cc7 4487 dev->stats.rx_errors++;
1da177e4 4488 if (status & (RxRWT | RxRUNT))
cebf8cc7 4489 dev->stats.rx_length_errors++;
1da177e4 4490 if (status & RxCRC)
cebf8cc7 4491 dev->stats.rx_crc_errors++;
9dccf611
FR		 4492 if (status & RxFOVF) {
4493 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4494 dev->stats.rx_fifo_errors++;
9dccf611 4495 }
126fa4b9 4496 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4497 } else {
1da177e4 4498 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4499 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4500 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4501 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4502
126fa4b9
FR		 4503 /*
4504 * The driver does not support incoming fragmented
4505 * frames. They are seen as a symptom of over-mtu
4506 * sized frames.
4507 */
4508 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4509 dev->stats.rx_dropped++;
4510 dev->stats.rx_length_errors++;
126fa4b9 4511 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4512 continue;
126fa4b9
FR		 4513 }
4514
1da177e4 4515 rtl8169_rx_csum(skb, desc);
bcf0bf90 4516
07d3f51f 4517 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 4518 pci_dma_sync_single_for_device(pdev, addr,
4519 pkt_size, PCI_DMA_FROMDEVICE);
4520 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4521 } else {
a866bbf6 4522 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 4523 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4524 tp->Rx_skbuff[entry] = NULL;
4525 }
4526
1da177e4
LT		 4527 skb_put(skb, pkt_size);
4528 skb->protocol = eth_type_trans(skb, dev);
4529
4530 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 4531 netif_receive_skb(skb);
1da177e4 4532
cebf8cc7
FR		 4533 dev->stats.rx_bytes += pkt_size;
4534 dev->stats.rx_packets++;
1da177e4 4535 }
6dccd16b
FR		 4536
4537 /* Work around for AMD plateform. */
95e0918d 4538 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4539 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4540 desc->opts2 = 0;
4541 cur_rx++;
4542 }
1da177e4
LT		 4543 }
4544
4545 count = cur_rx - tp->cur_rx;
4546 tp->cur_rx = cur_rx;
4547
4548 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 4549 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 4550 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
4551 tp->dirty_rx += delta;
4552
4553 /*
4554 * FIXME: until there is periodic timer to try and refill the ring,
4555 * a temporary shortage may definitely kill the Rx process.
4556 * - disable the asic to try and avoid an overflow and kick it again
4557 * after refill ?
4558 * - how do others driver handle this condition (Uh oh...).
4559 */
b57b7e5a 4560 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 4561 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
4562
4563 return count;
4564}
4565
07d3f51f 4566static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4567{
07d3f51f 4568 struct net_device *dev = dev_instance;
1da177e4 4569 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4570 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4571 int handled = 0;
865c652d 4572 int status;
1da177e4 4573
f11a377b
DD		 4574 /* loop handling interrupts until we have no new ones or
4575 * we hit a invalid/hotplug case.
4576 */
865c652d 4577 status = RTL_R16(IntrStatus);
f11a377b
DD		 4578 while (status && status != 0xffff) {
4579 handled = 1;
1da177e4 4580
f11a377b
DD		 4581 /* Handle all of the error cases first. These will reset
4582 * the chip, so just exit the loop.
4583 */
4584 if (unlikely(!netif_running(dev))) {
4585 rtl8169_asic_down(ioaddr);
4586 break;
4587 }
1da177e4 4588
f11a377b
DD		 4589 /* Work around for rx fifo overflow */
4590 if (unlikely(status & RxFIFOOver) &&
4591 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4592 netif_stop_queue(dev);
4593 rtl8169_tx_timeout(dev);
4594 break;
4595 }
1da177e4 4596
f11a377b
DD		 4597 if (unlikely(status & SYSErr)) {
4598 rtl8169_pcierr_interrupt(dev);
4599 break;
4600 }
1da177e4 4601
f11a377b
DD		 4602 if (status & LinkChg)
4603 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4604
f11a377b
DD		 4605 /* We need to see the lastest version of tp->intr_mask to
4606 * avoid ignoring an MSI interrupt and having to wait for
4607 * another event which may never come.
4608 */
4609 smp_rmb();
4610 if (status & tp->intr_mask & tp->napi_event) {
4611 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4612 tp->intr_mask = ~tp->napi_event;
4613
4614 if (likely(napi_schedule_prep(&tp->napi)))
4615 __napi_schedule(&tp->napi);
4616 else if (netif_msg_intr(tp)) {
4617 printk(KERN_INFO "%s: interrupt %04x in poll\n",
4618 dev->name, status);
4619 }
4620 }
1da177e4 4621
f11a377b
DD		 4622 /* We only get a new MSI interrupt when all active irq
4623 * sources on the chip have been acknowledged. So, ack
4624 * everything we've seen and check if new sources have become
4625 * active to avoid blocking all interrupts from the chip.
4626 */
4627 RTL_W16(IntrStatus,
4628 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4629 status = RTL_R16(IntrStatus);
865c652d 4630 }
1da177e4 4631
1da177e4
LT		 4632 return IRQ_RETVAL(handled);
4633}
4634
bea3348e 4635static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4636{
bea3348e
SH		 4637 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4638 struct net_device *dev = tp->dev;
1da177e4 4639 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4640 int work_done;
1da177e4 4641
bea3348e 4642 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4643 rtl8169_tx_interrupt(dev, tp, ioaddr);
4644
bea3348e 4645 if (work_done < budget) {
288379f0 4646 napi_complete(napi);
f11a377b
DD		 4647
4648 /* We need for force the visibility of tp->intr_mask
4649 * for other CPUs, as we can loose an MSI interrupt
4650 * and potentially wait for a retransmit timeout if we don't.
4651 * The posted write to IntrMask is safe, as it will
4652 * eventually make it to the chip and we won't loose anything
4653 * until it does.
1da177e4 4654 */
f11a377b 4655 tp->intr_mask = 0xffff;
1da177e4 4656 smp_wmb();
0e485150 4657 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4658 }
4659
bea3348e 4660 return work_done;
1da177e4 4661}
1da177e4 4662
523a6094
FR		 4663static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4664{
4665 struct rtl8169_private *tp = netdev_priv(dev);
4666
4667 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4668 return;
4669
4670 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4671 RTL_W32(RxMissed, 0);
4672}
4673
1da177e4
LT		 4674static void rtl8169_down(struct net_device *dev)
4675{
4676 struct rtl8169_private *tp = netdev_priv(dev);
4677 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4678 unsigned int intrmask;
1da177e4
LT		 4679
4680 rtl8169_delete_timer(dev);
4681
4682 netif_stop_queue(dev);
4683
93dd79e8 4684 napi_disable(&tp->napi);
93dd79e8 4685
1da177e4
LT		 4686core_down:
4687 spin_lock_irq(&tp->lock);
4688
4689 rtl8169_asic_down(ioaddr);
4690
523a6094 4691 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4692
4693 spin_unlock_irq(&tp->lock);
4694
4695 synchronize_irq(dev->irq);
4696
1da177e4 4697 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4698 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4699
4700 /*
4701 * And now for the 50k$ question: are IRQ disabled or not ?
4702 *
4703 * Two paths lead here:
4704 * 1) dev->close
4705 * -> netif_running() is available to sync the current code and the
4706 * IRQ handler. See rtl8169_interrupt for details.
4707 * 2) dev->change_mtu
4708 * -> rtl8169_poll can not be issued again and re-enable the
4709 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4710 *
4711 * No loop if hotpluged or major error (0xffff).
1da177e4 4712 */
733b736c
AP		 4713 intrmask = RTL_R16(IntrMask);
4714 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4715 goto core_down;
4716
4717 rtl8169_tx_clear(tp);
4718
4719 rtl8169_rx_clear(tp);
4720}
4721
4722static int rtl8169_close(struct net_device *dev)
4723{
4724 struct rtl8169_private *tp = netdev_priv(dev);
4725 struct pci_dev *pdev = tp->pci_dev;
4726
355423d0
IV		 4727 /* update counters before going down */
4728 rtl8169_update_counters(dev);
4729
1da177e4
LT		 4730 rtl8169_down(dev);
4731
4732 free_irq(dev->irq, dev);
4733
1da177e4
LT		 4734 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4735 tp->RxPhyAddr);
4736 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4737 tp->TxPhyAddr);
4738 tp->TxDescArray = NULL;
4739 tp->RxDescArray = NULL;
4740
4741 return 0;
4742}
4743
07ce4064 4744static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4745{
4746 struct rtl8169_private *tp = netdev_priv(dev);
4747 void __iomem *ioaddr = tp->mmio_addr;
4748 unsigned long flags;
4749 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4750 int rx_mode;
1da177e4
LT		 4751 u32 tmp = 0;
4752
4753 if (dev->flags & IFF_PROMISC) {
4754 /* Unconditionally log net taps. */
b57b7e5a
SH		 4755 if (netif_msg_link(tp)) {
4756 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
4757 dev->name);
4758 }
1da177e4
LT		 4759 rx_mode =
4760 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4761 AcceptAllPhys;
4762 mc_filter[1] = mc_filter[0] = 0xffffffff;
4763 } else if ((dev->mc_count > multicast_filter_limit)
4764 || (dev->flags & IFF_ALLMULTI)) {
4765 /* Too many to filter perfectly -- accept all multicasts. */
4766 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4767 mc_filter[1] = mc_filter[0] = 0xffffffff;
4768 } else {
4769 struct dev_mc_list *mclist;
07d3f51f
FR		 4770 unsigned int i;
4771
1da177e4
LT		 4772 rx_mode = AcceptBroadcast | AcceptMyPhys;
4773 mc_filter[1] = mc_filter[0] = 0;
4774 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
4775 i++, mclist = mclist->next) {
4776 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4777 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4778 rx_mode |= AcceptMulticast;
4779 }
4780 }
4781
4782 spin_lock_irqsave(&tp->lock, flags);
4783
4784 tmp = rtl8169_rx_config | rx_mode |
4785 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4786
f887cce8 4787 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4788 u32 data = mc_filter[0];
4789
4790 mc_filter[0] = swab32(mc_filter[1]);
4791 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4792 }
4793
1da177e4
LT		 4794 RTL_W32(MAR0 + 0, mc_filter[0]);
4795 RTL_W32(MAR0 + 4, mc_filter[1]);
4796
57a9f236
FR		 4797 RTL_W32(RxConfig, tmp);
4798
1da177e4
LT		 4799 spin_unlock_irqrestore(&tp->lock, flags);
4800}
4801
4802/**
4803 * rtl8169_get_stats - Get rtl8169 read/write statistics
4804 * @dev: The Ethernet Device to get statistics for
4805 *
4806 * Get TX/RX statistics for rtl8169
4807 */
4808static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4809{
4810 struct rtl8169_private *tp = netdev_priv(dev);
4811 void __iomem *ioaddr = tp->mmio_addr;
4812 unsigned long flags;
4813
4814 if (netif_running(dev)) {
4815 spin_lock_irqsave(&tp->lock, flags);
523a6094 4816 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4817 spin_unlock_irqrestore(&tp->lock, flags);
4818 }
5b0384f4 4819
cebf8cc7 4820 return &dev->stats;
1da177e4
LT		 4821}
4822
861ab440 4823static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4824{
5d06a99f 4825 if (!netif_running(dev))
861ab440 4826 return;
5d06a99f
FR		 4827
4828 netif_device_detach(dev);
4829 netif_stop_queue(dev);
861ab440
RW		 4830}
4831
4832#ifdef CONFIG_PM
4833
4834static int rtl8169_suspend(struct device *device)
4835{
4836 struct pci_dev *pdev = to_pci_dev(device);
4837 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4838
861ab440 4839 rtl8169_net_suspend(dev);
1371fa6d 4840
5d06a99f
FR		 4841 return 0;
4842}
4843
861ab440 4844static int rtl8169_resume(struct device *device)
5d06a99f 4845{
861ab440 4846 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4847 struct net_device *dev = pci_get_drvdata(pdev);
4848
4849 if (!netif_running(dev))
4850 goto out;
4851
4852 netif_device_attach(dev);
4853
5d06a99f
FR		 4854 rtl8169_schedule_work(dev, rtl8169_reset_task);
4855out:
4856 return 0;
4857}
4858
861ab440
RW		 4859static struct dev_pm_ops rtl8169_pm_ops = {
4860 .suspend = rtl8169_suspend,
4861 .resume = rtl8169_resume,
4862 .freeze = rtl8169_suspend,
4863 .thaw = rtl8169_resume,
4864 .poweroff = rtl8169_suspend,
4865 .restore = rtl8169_resume,
4866};
4867
4868#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4869
4870#else /* !CONFIG_PM */
4871
4872#define RTL8169_PM_OPS NULL
4873
4874#endif /* !CONFIG_PM */
4875
1765f95d
FR		 4876static void rtl_shutdown(struct pci_dev *pdev)
4877{
861ab440 4878 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4879 struct rtl8169_private *tp = netdev_priv(dev);
4880 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4881
4882 rtl8169_net_suspend(dev);
1765f95d 4883
4bb3f522 4884 spin_lock_irq(&tp->lock);
4885
4886 rtl8169_asic_down(ioaddr);
4887
4888 spin_unlock_irq(&tp->lock);
4889
861ab440 4890 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4891 /* WoL fails with some 8168 when the receiver is disabled. */
4892 if (tp->features & RTL_FEATURE_WOL) {
4893 pci_clear_master(pdev);
4894
4895 RTL_W8(ChipCmd, CmdRxEnb);
4896 /* PCI commit */
4897 RTL_R8(ChipCmd);
4898 }
4899
861ab440
RW		 4900 pci_wake_from_d3(pdev, true);
4901 pci_set_power_state(pdev, PCI_D3hot);
4902 }
4903}
5d06a99f 4904
1da177e4
LT		 4905static struct pci_driver rtl8169_pci_driver = {
4906 .name = MODULENAME,
4907 .id_table = rtl8169_pci_tbl,
4908 .probe = rtl8169_init_one,
4909 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4910 .shutdown = rtl_shutdown,
861ab440 4911 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4912};
4913
07d3f51f 4914static int __init rtl8169_init_module(void)
1da177e4 4915{
29917620 4916 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4917}
4918
07d3f51f 4919static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4920{
4921 pci_unregister_driver(&rtl8169_pci_driver);
4922}
4923
4924module_init(rtl8169_init_module);
4925module_exit(rtl8169_cleanup_module);
Clone of davem's net-next-2.6 tree