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ip6mr: fix a typo in ip6mr_for_each_table()
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
1da177e4 27
99f252b0 28#include <asm/system.h>
1da177e4
LT		 29#include <asm/io.h>
30#include <asm/irq.h>
31
865c652d 32#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 33#define MODULENAME "r8169"
34#define PFX MODULENAME ": "
35
36#ifdef RTL8169_DEBUG
37#define assert(expr) \
5b0384f4
FR		 38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 40 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 41 }
06fa7358
JP		 42#define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 44#else
45#define assert(expr) do {} while (0)
46#define dprintk(fmt, args...) do {} while (0)
47#endif /* RTL8169_DEBUG */
48
b57b7e5a 49#define R8169_MSG_DEFAULT \
f0e837d9 50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 51
1da177e4
LT		 52#define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
1da177e4
LT		 55/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 57static const int multicast_filter_limit = 32;
1da177e4
LT		 58
59/* MAC address length */
60#define MAC_ADDR_LEN 6
61
9c14ceaf 62#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 63#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 66#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 67#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
71#define R8169_NAPI_WEIGHT 64
72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74#define RX_BUF_SIZE 1536 /* Rx Buffer size */
75#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78#define RTL8169_TX_TIMEOUT (6*HZ)
79#define RTL8169_PHY_TIMEOUT (10*HZ)
80
ea8dbdd1 81#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 83#define RTL_EEPROM_SIG_ADDR 0x0000
84
1da177e4
LT		 85/* write/read MMIO register */
86#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89#define RTL_R8(reg) readb (ioaddr + (reg))
90#define RTL_R16(reg) readw (ioaddr + (reg))
91#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
92
93enum mac_version {
f21b75e9 94 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 159};
160#undef _R
161
bcf0bf90
FR		 162enum cfg_version {
163 RTL_CFG_0 = 0x00,
164 RTL_CFG_1,
165 RTL_CFG_2
166};
167
07ce4064
FR		 168static void rtl_hw_start_8169(struct net_device *);
169static void rtl_hw_start_8168(struct net_device *);
170static void rtl_hw_start_8101(struct net_device *);
171
a3aa1884 172static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 183 { 0x0001, 0x8168,
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 185 {0,},
186};
187
188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189
c0cd884a
NH		 190/*
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
193 * rtl8169_open()
194 */
195static int rx_copybreak = 16383;
4300e8c7 196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4 200
07d3f51f
FR		 201enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
773d2021 203 MAC4 = 4,
07d3f51f
FR		 204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
07d3f51f
FR		 229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec,
236 FuncEvent = 0xf0,
237 FuncEventMask = 0xf4,
238 FuncPresetState = 0xf8,
239 FuncForceEvent = 0xfc,
1da177e4
LT		 240};
241
f162a5d1
FR		 242enum rtl8110_registers {
243 TBICSR = 0x64,
244 TBI_ANAR = 0x68,
245 TBI_LPAR = 0x6a,
246};
247
248enum rtl8168_8101_registers {
249 CSIDR = 0x64,
250 CSIAR = 0x68,
251#define CSIAR_FLAG 0x80000000
252#define CSIAR_WRITE_CMD 0x80000000
253#define CSIAR_BYTE_ENABLE 0x0f
254#define CSIAR_BYTE_ENABLE_SHIFT 12
255#define CSIAR_ADDR_MASK 0x0fff
256
257 EPHYAR = 0x80,
258#define EPHYAR_FLAG 0x80000000
259#define EPHYAR_WRITE_CMD 0x80000000
260#define EPHYAR_REG_MASK 0x1f
261#define EPHYAR_REG_SHIFT 16
262#define EPHYAR_DATA_MASK 0xffff
263 DBG_REG = 0xd1,
264#define FIX_NAK_1 (1 << 4)
265#define FIX_NAK_2 (1 << 3)
daf9df6d 266 EFUSEAR = 0xdc,
267#define EFUSEAR_FLAG 0x80000000
268#define EFUSEAR_WRITE_CMD 0x80000000
269#define EFUSEAR_READ_CMD 0x00000000
270#define EFUSEAR_REG_MASK 0x03ff
271#define EFUSEAR_REG_SHIFT 8
272#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 273};
274
07d3f51f 275enum rtl_register_content {
1da177e4 276 /* InterruptStatusBits */
07d3f51f
FR		 277 SYSErr = 0x8000,
278 PCSTimeout = 0x4000,
279 SWInt = 0x0100,
280 TxDescUnavail = 0x0080,
281 RxFIFOOver = 0x0040,
282 LinkChg = 0x0020,
283 RxOverflow = 0x0010,
284 TxErr = 0x0008,
285 TxOK = 0x0004,
286 RxErr = 0x0002,
287 RxOK = 0x0001,
1da177e4
LT		 288
289 /* RxStatusDesc */
9dccf611
FR		 290 RxFOVF = (1 << 23),
291 RxRWT = (1 << 22),
292 RxRES = (1 << 21),
293 RxRUNT = (1 << 20),
294 RxCRC = (1 << 19),
1da177e4
LT		 295
296 /* ChipCmdBits */
07d3f51f
FR		 297 CmdReset = 0x10,
298 CmdRxEnb = 0x08,
299 CmdTxEnb = 0x04,
300 RxBufEmpty = 0x01,
1da177e4 301
275391a4
FR		 302 /* TXPoll register p.5 */
303 HPQ = 0x80, /* Poll cmd on the high prio queue */
304 NPQ = 0x40, /* Poll cmd on the low prio queue */
305 FSWInt = 0x01, /* Forced software interrupt */
306
1da177e4 307 /* Cfg9346Bits */
07d3f51f
FR		 308 Cfg9346_Lock = 0x00,
309 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 310
311 /* rx_mode_bits */
07d3f51f
FR		 312 AcceptErr = 0x20,
313 AcceptRunt = 0x10,
314 AcceptBroadcast = 0x08,
315 AcceptMulticast = 0x04,
316 AcceptMyPhys = 0x02,
317 AcceptAllPhys = 0x01,
1da177e4
LT		 318
319 /* RxConfigBits */
07d3f51f
FR		 320 RxCfgFIFOShift = 13,
321 RxCfgDMAShift = 8,
1da177e4
LT		 322
323 /* TxConfigBits */
324 TxInterFrameGapShift = 24,
325 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
326
5d06a99f 327 /* Config1 register p.24 */
f162a5d1
FR		 328 LEDS1 = (1 << 7),
329 LEDS0 = (1 << 6),
fbac58fc 330 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 331 Speed_down = (1 << 4),
332 MEMMAP = (1 << 3),
333 IOMAP = (1 << 2),
334 VPD = (1 << 1),
5d06a99f
FR		 335 PMEnable = (1 << 0), /* Power Management Enable */
336
6dccd16b
FR		 337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz = 0x01,
339 PCI_Clock_33MHz = 0x00,
340
61a4dcc2
FR		 341 /* Config3 register p.25 */
342 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 344 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 345
5d06a99f 346 /* Config5 register p.27 */
61a4dcc2
FR		 347 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF = (1 << 5), /* Accept Multicast wakeup frame */
349 UWF = (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 351 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
352
1da177e4
LT		 353 /* TBICSR p.28 */
354 TBIReset = 0x80000000,
355 TBILoopback = 0x40000000,
356 TBINwEnable = 0x20000000,
357 TBINwRestart = 0x10000000,
358 TBILinkOk = 0x02000000,
359 TBINwComplete = 0x01000000,
360
361 /* CPlusCmd p.31 */
f162a5d1
FR		 362 EnableBist = (1 << 15), // 8168 8101
363 Mac_dbgo_oe = (1 << 14), // 8168 8101
364 Normal_mode = (1 << 13), // unused
365 Force_half_dup = (1 << 12), // 8168 8101
366 Force_rxflow_en = (1 << 11), // 8168 8101
367 Force_txflow_en = (1 << 10), // 8168 8101
368 Cxpl_dbg_sel = (1 << 9), // 8168 8101
369 ASF = (1 << 8), // 8168 8101
370 PktCntrDisable = (1 << 7), // 8168 8101
371 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 372 RxVlan = (1 << 6),
373 RxChkSum = (1 << 5),
374 PCIDAC = (1 << 4),
375 PCIMulRW = (1 << 3),
0e485150
FR		 376 INTT_0 = 0x0000, // 8168
377 INTT_1 = 0x0001, // 8168
378 INTT_2 = 0x0002, // 8168
379 INTT_3 = 0x0003, // 8168
1da177e4
LT		 380
381 /* rtl8169_PHYstatus */
07d3f51f
FR		 382 TBI_Enable = 0x80,
383 TxFlowCtrl = 0x40,
384 RxFlowCtrl = 0x20,
385 _1000bpsF = 0x10,
386 _100bps = 0x08,
387 _10bps = 0x04,
388 LinkStatus = 0x02,
389 FullDup = 0x01,
1da177e4 390
1da177e4 391 /* _TBICSRBit */
07d3f51f 392 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 393
394 /* DumpCounterCommand */
07d3f51f 395 CounterDump = 0x8,
1da177e4
LT		 396};
397
07d3f51f 398enum desc_status_bit {
1da177e4
LT		 399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */
403
404 /* Tx private */
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift = 16, /* MSS value position */
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS = (1 << 18), /* Calculate IP checksum */
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag = (1 << 17), /* Add VLAN tag */
412
413 /* Rx private */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
416
417#define RxProtoUDP (PID1)
418#define RxProtoTCP (PID0)
419#define RxProtoIP (PID1 | PID0)
420#define RxProtoMask RxProtoIP
421
422 IPFail = (1 << 16), /* IP checksum failed */
423 UDPFail = (1 << 15), /* UDP/IP checksum failed */
424 TCPFail = (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag = (1 << 16), /* VLAN tag available */
426};
427
428#define RsvdMask 0x3fffc000
429
430struct TxDesc {
6cccd6e7
REB		 431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
1da177e4
LT		 434};
435
436struct RxDesc {
6cccd6e7
REB		 437 __le32 opts1;
438 __le32 opts2;
439 __le64 addr;
1da177e4
LT		 440};
441
442struct ring_info {
443 struct sk_buff *skb;
444 u32 len;
445 u8 __pad[sizeof(void *) - sizeof(u32)];
446};
447
f23e7fda 448enum features {
ccdffb9a
FR		 449 RTL_FEATURE_WOL = (1 << 0),
450 RTL_FEATURE_MSI = (1 << 1),
451 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 452};
453
355423d0
IV		 454struct rtl8169_counters {
455 __le64 tx_packets;
456 __le64 rx_packets;
457 __le64 tx_errors;
458 __le32 rx_errors;
459 __le16 rx_missed;
460 __le16 align_errors;
461 __le32 tx_one_collision;
462 __le32 tx_multi_collision;
463 __le64 rx_unicast;
464 __le64 rx_broadcast;
465 __le32 rx_multicast;
466 __le16 tx_aborted;
467 __le16 tx_underun;
468};
469
1da177e4
LT		 470struct rtl8169_private {
471 void __iomem *mmio_addr; /* memory map physical address */
472 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 473 struct net_device *dev;
bea3348e 474 struct napi_struct napi;
1da177e4 475 spinlock_t lock; /* spin lock flag */
b57b7e5a 476 u32 msg_enable;
1da177e4
LT		 477 int chipset;
478 int mac_version;
1da177e4
LT		 479 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
481 u32 dirty_rx;
482 u32 dirty_tx;
483 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
484 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr;
486 dma_addr_t RxPhyAddr;
487 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
488 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 489 unsigned align;
1da177e4
LT		 490 unsigned rx_buf_sz;
491 struct timer_list timer;
492 u16 cp_cmd;
0e485150
FR		 493 u16 intr_event;
494 u16 napi_event;
1da177e4 495 u16 intr_mask;
1da177e4
LT		 496 int phy_1000_ctrl_reg;
497#ifdef CONFIG_R8169_VLAN
498 struct vlan_group *vlgrp;
499#endif
500 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 501 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 502 void (*phy_reset_enable)(void __iomem *);
07ce4064 503 void (*hw_start)(struct net_device *);
1da177e4
LT		 504 unsigned int (*phy_reset_pending)(void __iomem *);
505 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 506 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 507 int pcie_cap;
c4028958 508 struct delayed_work task;
f23e7fda 509 unsigned features;
ccdffb9a
FR		 510
511 struct mii_if_info mii;
355423d0 512 struct rtl8169_counters counters;
e1759441 513 u32 saved_wolopts;
1da177e4
LT		 514};
515
979b6c13 516MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 517MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 518module_param(rx_copybreak, int, 0);
1b7efd58 519MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4 520module_param(use_dac, int, 0);
4300e8c7 521MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 522module_param_named(debug, debug.msg_enable, int, 0);
523MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 524MODULE_LICENSE("GPL");
525MODULE_VERSION(RTL8169_VERSION);
526
527static int rtl8169_open(struct net_device *dev);
61357325
SH		 528static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
529 struct net_device *dev);
7d12e780 530static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 531static int rtl8169_init_ring(struct net_device *dev);
07ce4064 532static void rtl_hw_start(struct net_device *dev);
1da177e4 533static int rtl8169_close(struct net_device *dev);
07ce4064 534static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 535static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 536static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 537static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 538 void __iomem *, u32 budget);
4dcb7d33 539static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 540static void rtl8169_down(struct net_device *dev);
99f252b0 541static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 542static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 543
1da177e4 544static const unsigned int rtl8169_rx_config =
5b0384f4 545 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 546
07d3f51f 547static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 548{
549 int i;
550
a6baf3af 551 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 552
2371408c 553 for (i = 20; i > 0; i--) {
07d3f51f
FR		 554 /*
555 * Check if the RTL8169 has completed writing to the specified
556 * MII register.
557 */
5b0384f4 558 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 559 break;
2371408c 560 udelay(25);
1da177e4
LT		 561 }
562}
563
07d3f51f 564static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 565{
566 int i, value = -1;
567
a6baf3af 568 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 569
2371408c 570 for (i = 20; i > 0; i--) {
07d3f51f
FR		 571 /*
572 * Check if the RTL8169 has completed retrieving data from
573 * the specified MII register.
574 */
1da177e4 575 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 576 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 577 break;
578 }
2371408c 579 udelay(25);
1da177e4
LT		 580 }
581 return value;
582}
583
dacf8154
FR		 584static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
585{
586 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
587}
588
daf9df6d 589static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
590{
591 int val;
592
593 val = mdio_read(ioaddr, reg_addr);
594 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
595}
596
ccdffb9a
FR		 597static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
598 int val)
599{
600 struct rtl8169_private *tp = netdev_priv(dev);
601 void __iomem *ioaddr = tp->mmio_addr;
602
603 mdio_write(ioaddr, location, val);
604}
605
606static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
607{
608 struct rtl8169_private *tp = netdev_priv(dev);
609 void __iomem *ioaddr = tp->mmio_addr;
610
611 return mdio_read(ioaddr, location);
612}
613
dacf8154
FR		 614static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
615{
616 unsigned int i;
617
618 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
619 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
620
621 for (i = 0; i < 100; i++) {
622 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
623 break;
624 udelay(10);
625 }
626}
627
628static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
629{
630 u16 value = 0xffff;
631 unsigned int i;
632
633 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
634
635 for (i = 0; i < 100; i++) {
636 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
637 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
638 break;
639 }
640 udelay(10);
641 }
642
643 return value;
644}
645
646static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
647{
648 unsigned int i;
649
650 RTL_W32(CSIDR, value);
651 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
652 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
653
654 for (i = 0; i < 100; i++) {
655 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
656 break;
657 udelay(10);
658 }
659}
660
661static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
662{
663 u32 value = ~0x00;
664 unsigned int i;
665
666 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
667 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
668
669 for (i = 0; i < 100; i++) {
670 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
671 value = RTL_R32(CSIDR);
672 break;
673 }
674 udelay(10);
675 }
676
677 return value;
678}
679
daf9df6d 680static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
681{
682 u8 value = 0xff;
683 unsigned int i;
684
685 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
686
687 for (i = 0; i < 300; i++) {
688 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
689 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
690 break;
691 }
692 udelay(100);
693 }
694
695 return value;
696}
697
1da177e4
LT		 698static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
699{
700 RTL_W16(IntrMask, 0x0000);
701
702 RTL_W16(IntrStatus, 0xffff);
703}
704
705static void rtl8169_asic_down(void __iomem *ioaddr)
706{
707 RTL_W8(ChipCmd, 0x00);
708 rtl8169_irq_mask_and_ack(ioaddr);
709 RTL_R16(CPlusCmd);
710}
711
712static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
713{
714 return RTL_R32(TBICSR) & TBIReset;
715}
716
717static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
718{
64e4bfb4 719 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 720}
721
722static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
723{
724 return RTL_R32(TBICSR) & TBILinkOk;
725}
726
727static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
728{
729 return RTL_R8(PHYstatus) & LinkStatus;
730}
731
732static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
733{
734 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
735}
736
737static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
738{
739 unsigned int val;
740
9e0db8ef
FR		 741 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
742 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 743}
744
745static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 746 struct rtl8169_private *tp,
747 void __iomem *ioaddr)
1da177e4
LT		 748{
749 unsigned long flags;
750
751 spin_lock_irqsave(&tp->lock, flags);
752 if (tp->link_ok(ioaddr)) {
e1759441
RW		 753 /* This is to cancel a scheduled suspend if there's one. */
754 pm_request_resume(&tp->pci_dev->dev);
1da177e4 755 netif_carrier_on(dev);
bf82c189 756 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 757 } else {
1da177e4 758 netif_carrier_off(dev);
bf82c189 759 netif_info(tp, ifdown, dev, "link down\n");
e1759441 760 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 761 }
1da177e4
LT		 762 spin_unlock_irqrestore(&tp->lock, flags);
763}
764
e1759441
RW		 765#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
766
767static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 768{
61a4dcc2
FR		 769 void __iomem *ioaddr = tp->mmio_addr;
770 u8 options;
e1759441 771 u32 wolopts = 0;
61a4dcc2
FR		 772
773 options = RTL_R8(Config1);
774 if (!(options & PMEnable))
e1759441 775 return 0;
61a4dcc2
FR		 776
777 options = RTL_R8(Config3);
778 if (options & LinkUp)
e1759441 779 wolopts |= WAKE_PHY;
61a4dcc2 780 if (options & MagicPacket)
e1759441 781 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 782
783 options = RTL_R8(Config5);
784 if (options & UWF)
e1759441 785 wolopts |= WAKE_UCAST;
61a4dcc2 786 if (options & BWF)
e1759441 787 wolopts |= WAKE_BCAST;
61a4dcc2 788 if (options & MWF)
e1759441 789 wolopts |= WAKE_MCAST;
61a4dcc2 790
e1759441 791 return wolopts;
61a4dcc2
FR		 792}
793
e1759441 794static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 795{
796 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 797
798 spin_lock_irq(&tp->lock);
799
800 wol->supported = WAKE_ANY;
801 wol->wolopts = __rtl8169_get_wol(tp);
802
803 spin_unlock_irq(&tp->lock);
804}
805
806static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
807{
61a4dcc2 808 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 809 unsigned int i;
350f7596 810 static const struct {
61a4dcc2
FR		 811 u32 opt;
812 u16 reg;
813 u8 mask;
814 } cfg[] = {
815 { WAKE_ANY, Config1, PMEnable },
816 { WAKE_PHY, Config3, LinkUp },
817 { WAKE_MAGIC, Config3, MagicPacket },
818 { WAKE_UCAST, Config5, UWF },
819 { WAKE_BCAST, Config5, BWF },
820 { WAKE_MCAST, Config5, MWF },
821 { WAKE_ANY, Config5, LanWake }
822 };
823
61a4dcc2
FR		 824 RTL_W8(Cfg9346, Cfg9346_Unlock);
825
826 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
827 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 828 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 829 options |= cfg[i].mask;
830 RTL_W8(cfg[i].reg, options);
831 }
832
833 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 834}
835
836static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
837{
838 struct rtl8169_private *tp = netdev_priv(dev);
839
840 spin_lock_irq(&tp->lock);
61a4dcc2 841
f23e7fda
FR		 842 if (wol->wolopts)
843 tp->features |= RTL_FEATURE_WOL;
844 else
845 tp->features &= ~RTL_FEATURE_WOL;
e1759441 846 __rtl8169_set_wol(tp, wol->wolopts);
8b76ab39 847 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 848
849 spin_unlock_irq(&tp->lock);
850
851 return 0;
852}
853
1da177e4
LT		 854static void rtl8169_get_drvinfo(struct net_device *dev,
855 struct ethtool_drvinfo *info)
856{
857 struct rtl8169_private *tp = netdev_priv(dev);
858
859 strcpy(info->driver, MODULENAME);
860 strcpy(info->version, RTL8169_VERSION);
861 strcpy(info->bus_info, pci_name(tp->pci_dev));
862}
863
864static int rtl8169_get_regs_len(struct net_device *dev)
865{
866 return R8169_REGS_SIZE;
867}
868
869static int rtl8169_set_speed_tbi(struct net_device *dev,
870 u8 autoneg, u16 speed, u8 duplex)
871{
872 struct rtl8169_private *tp = netdev_priv(dev);
873 void __iomem *ioaddr = tp->mmio_addr;
874 int ret = 0;
875 u32 reg;
876
877 reg = RTL_R32(TBICSR);
878 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
879 (duplex == DUPLEX_FULL)) {
880 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
881 } else if (autoneg == AUTONEG_ENABLE)
882 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
883 else {
bf82c189
JP		 884 netif_warn(tp, link, dev,
885 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 886 ret = -EOPNOTSUPP;
887 }
888
889 return ret;
890}
891
892static int rtl8169_set_speed_xmii(struct net_device *dev,
893 u8 autoneg, u16 speed, u8 duplex)
894{
895 struct rtl8169_private *tp = netdev_priv(dev);
896 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 897 int giga_ctrl, bmcr;
1da177e4
LT		 898
899 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 900 int auto_nego;
901
902 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 903 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
904 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 905 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 906
3577aa1b 907 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
908 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 909
3577aa1b 910 /* The 8100e/8101e/8102e do Fast Ethernet only. */
911 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
912 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
913 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
914 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
915 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
916 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
917 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
918 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
919 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 920 } else {
921 netif_info(tp, link, dev,
922 "PHY does not support 1000Mbps\n");
bcf0bf90 923 }
1da177e4 924
3577aa1b 925 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
926
927 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
928 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
929 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
930 /*
931 * Wake up the PHY.
932 * Vendor specific (0x1f) and reserved (0x0e) MII
933 * registers.
934 */
935 mdio_write(ioaddr, 0x1f, 0x0000);
936 mdio_write(ioaddr, 0x0e, 0x0000);
937 }
938
939 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
940 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
941 } else {
942 giga_ctrl = 0;
943
944 if (speed == SPEED_10)
945 bmcr = 0;
946 else if (speed == SPEED_100)
947 bmcr = BMCR_SPEED100;
948 else
949 return -EINVAL;
950
951 if (duplex == DUPLEX_FULL)
952 bmcr |= BMCR_FULLDPLX;
623a1593 953
2584fbc3 954 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 955 }
956
1da177e4
LT		 957 tp->phy_1000_ctrl_reg = giga_ctrl;
958
3577aa1b 959 mdio_write(ioaddr, MII_BMCR, bmcr);
960
961 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
962 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
963 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
964 mdio_write(ioaddr, 0x17, 0x2138);
965 mdio_write(ioaddr, 0x0e, 0x0260);
966 } else {
967 mdio_write(ioaddr, 0x17, 0x2108);
968 mdio_write(ioaddr, 0x0e, 0x0000);
969 }
970 }
971
1da177e4
LT		 972 return 0;
973}
974
975static int rtl8169_set_speed(struct net_device *dev,
976 u8 autoneg, u16 speed, u8 duplex)
977{
978 struct rtl8169_private *tp = netdev_priv(dev);
979 int ret;
980
981 ret = tp->set_speed(dev, autoneg, speed, duplex);
982
64e4bfb4 983 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 984 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
985
986 return ret;
987}
988
989static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
990{
991 struct rtl8169_private *tp = netdev_priv(dev);
992 unsigned long flags;
993 int ret;
994
995 spin_lock_irqsave(&tp->lock, flags);
996 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
997 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 998
1da177e4
LT		 999 return ret;
1000}
1001
1002static u32 rtl8169_get_rx_csum(struct net_device *dev)
1003{
1004 struct rtl8169_private *tp = netdev_priv(dev);
1005
1006 return tp->cp_cmd & RxChkSum;
1007}
1008
1009static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1010{
1011 struct rtl8169_private *tp = netdev_priv(dev);
1012 void __iomem *ioaddr = tp->mmio_addr;
1013 unsigned long flags;
1014
1015 spin_lock_irqsave(&tp->lock, flags);
1016
1017 if (data)
1018 tp->cp_cmd |= RxChkSum;
1019 else
1020 tp->cp_cmd &= ~RxChkSum;
1021
1022 RTL_W16(CPlusCmd, tp->cp_cmd);
1023 RTL_R16(CPlusCmd);
1024
1025 spin_unlock_irqrestore(&tp->lock, flags);
1026
1027 return 0;
1028}
1029
1030#ifdef CONFIG_R8169_VLAN
1031
1032static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1033 struct sk_buff *skb)
1034{
1035 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1036 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1037}
1038
1039static void rtl8169_vlan_rx_register(struct net_device *dev,
1040 struct vlan_group *grp)
1041{
1042 struct rtl8169_private *tp = netdev_priv(dev);
1043 void __iomem *ioaddr = tp->mmio_addr;
1044 unsigned long flags;
1045
1046 spin_lock_irqsave(&tp->lock, flags);
1047 tp->vlgrp = grp;
05af2142
SW		 1048 /*
1049 * Do not disable RxVlan on 8110SCd.
1050 */
1051 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1052 tp->cp_cmd |= RxVlan;
1053 else
1054 tp->cp_cmd &= ~RxVlan;
1055 RTL_W16(CPlusCmd, tp->cp_cmd);
1056 RTL_R16(CPlusCmd);
1057 spin_unlock_irqrestore(&tp->lock, flags);
1058}
1059
1da177e4 1060static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1061 struct sk_buff *skb, int polling)
1da177e4
LT		 1062{
1063 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1064 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1065 int ret;
1066
865c652d 1067 if (vlgrp && (opts2 & RxVlanTag)) {
630b943c 1068 __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
1da177e4
LT		 1069 ret = 0;
1070 } else
1071 ret = -1;
1072 desc->opts2 = 0;
1073 return ret;
1074}
1075
1076#else /* !CONFIG_R8169_VLAN */
1077
1078static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1079 struct sk_buff *skb)
1080{
1081 return 0;
1082}
1083
1084static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1085 struct sk_buff *skb, int polling)
1da177e4
LT		 1086{
1087 return -1;
1088}
1089
1090#endif
1091
ccdffb9a 1092static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1093{
1094 struct rtl8169_private *tp = netdev_priv(dev);
1095 void __iomem *ioaddr = tp->mmio_addr;
1096 u32 status;
1097
1098 cmd->supported =
1099 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1100 cmd->port = PORT_FIBRE;
1101 cmd->transceiver = XCVR_INTERNAL;
1102
1103 status = RTL_R32(TBICSR);
1104 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1105 cmd->autoneg = !!(status & TBINwEnable);
1106
1107 cmd->speed = SPEED_1000;
1108 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1109
1110 return 0;
1da177e4
LT		 1111}
1112
ccdffb9a 1113static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1114{
1115 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1116
1117 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1118}
1119
1120static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1121{
1122 struct rtl8169_private *tp = netdev_priv(dev);
1123 unsigned long flags;
ccdffb9a 1124 int rc;
1da177e4
LT		 1125
1126 spin_lock_irqsave(&tp->lock, flags);
1127
ccdffb9a 1128 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1129
1130 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1131 return rc;
1da177e4
LT		 1132}
1133
1134static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1135 void *p)
1136{
5b0384f4
FR		 1137 struct rtl8169_private *tp = netdev_priv(dev);
1138 unsigned long flags;
1da177e4 1139
5b0384f4
FR		 1140 if (regs->len > R8169_REGS_SIZE)
1141 regs->len = R8169_REGS_SIZE;
1da177e4 1142
5b0384f4
FR		 1143 spin_lock_irqsave(&tp->lock, flags);
1144 memcpy_fromio(p, tp->mmio_addr, regs->len);
1145 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1146}
1147
b57b7e5a
SH		 1148static u32 rtl8169_get_msglevel(struct net_device *dev)
1149{
1150 struct rtl8169_private *tp = netdev_priv(dev);
1151
1152 return tp->msg_enable;
1153}
1154
1155static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1156{
1157 struct rtl8169_private *tp = netdev_priv(dev);
1158
1159 tp->msg_enable = value;
1160}
1161
d4a3a0fc
SH		 1162static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1163 "tx_packets",
1164 "rx_packets",
1165 "tx_errors",
1166 "rx_errors",
1167 "rx_missed",
1168 "align_errors",
1169 "tx_single_collisions",
1170 "tx_multi_collisions",
1171 "unicast",
1172 "broadcast",
1173 "multicast",
1174 "tx_aborted",
1175 "tx_underrun",
1176};
1177
b9f2c044 1178static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1179{
b9f2c044
JG		 1180 switch (sset) {
1181 case ETH_SS_STATS:
1182 return ARRAY_SIZE(rtl8169_gstrings);
1183 default:
1184 return -EOPNOTSUPP;
1185 }
d4a3a0fc
SH		 1186}
1187
355423d0 1188static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1189{
1190 struct rtl8169_private *tp = netdev_priv(dev);
1191 void __iomem *ioaddr = tp->mmio_addr;
1192 struct rtl8169_counters *counters;
1193 dma_addr_t paddr;
1194 u32 cmd;
355423d0 1195 int wait = 1000;
d4a3a0fc 1196
355423d0
IV		 1197 /*
1198 * Some chips are unable to dump tally counters when the receiver
1199 * is disabled.
1200 */
1201 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1202 return;
d4a3a0fc
SH		 1203
1204 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1205 if (!counters)
1206 return;
1207
1208 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1209 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1210 RTL_W32(CounterAddrLow, cmd);
1211 RTL_W32(CounterAddrLow, cmd | CounterDump);
1212
355423d0
IV		 1213 while (wait--) {
1214 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1215 /* copy updated counters */
1216 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1217 break;
355423d0
IV		 1218 }
1219 udelay(10);
d4a3a0fc
SH		 1220 }
1221
1222 RTL_W32(CounterAddrLow, 0);
1223 RTL_W32(CounterAddrHigh, 0);
1224
d4a3a0fc
SH		 1225 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1226}
1227
355423d0
IV		 1228static void rtl8169_get_ethtool_stats(struct net_device *dev,
1229 struct ethtool_stats *stats, u64 *data)
1230{
1231 struct rtl8169_private *tp = netdev_priv(dev);
1232
1233 ASSERT_RTNL();
1234
1235 rtl8169_update_counters(dev);
1236
1237 data[0] = le64_to_cpu(tp->counters.tx_packets);
1238 data[1] = le64_to_cpu(tp->counters.rx_packets);
1239 data[2] = le64_to_cpu(tp->counters.tx_errors);
1240 data[3] = le32_to_cpu(tp->counters.rx_errors);
1241 data[4] = le16_to_cpu(tp->counters.rx_missed);
1242 data[5] = le16_to_cpu(tp->counters.align_errors);
1243 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1244 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1245 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1246 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1247 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1248 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1249 data[12] = le16_to_cpu(tp->counters.tx_underun);
1250}
1251
d4a3a0fc
SH		 1252static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1253{
1254 switch(stringset) {
1255 case ETH_SS_STATS:
1256 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1257 break;
1258 }
1259}
1260
7282d491 1261static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1262 .get_drvinfo = rtl8169_get_drvinfo,
1263 .get_regs_len = rtl8169_get_regs_len,
1264 .get_link = ethtool_op_get_link,
1265 .get_settings = rtl8169_get_settings,
1266 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1267 .get_msglevel = rtl8169_get_msglevel,
1268 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1269 .get_rx_csum = rtl8169_get_rx_csum,
1270 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1271 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1272 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1273 .set_tso = ethtool_op_set_tso,
1274 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1275 .get_wol = rtl8169_get_wol,
1276 .set_wol = rtl8169_set_wol,
d4a3a0fc 1277 .get_strings = rtl8169_get_strings,
b9f2c044 1278 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1279 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1280};
1281
07d3f51f
FR		 1282static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1283 void __iomem *ioaddr)
1da177e4 1284{
0e485150
FR		 1285 /*
1286 * The driver currently handles the 8168Bf and the 8168Be identically
1287 * but they can be identified more specifically through the test below
1288 * if needed:
1289 *
1290 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1291 *
1292 * Same thing for the 8101Eb and the 8101Ec:
1293 *
1294 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1295 */
350f7596 1296 static const struct {
1da177e4 1297 u32 mask;
e3cf0cc0 1298 u32 val;
1da177e4
LT		 1299 int mac_version;
1300 } mac_info[] = {
5b538df9 1301 /* 8168D family. */
daf9df6d 1302 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1303 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1304 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1305 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1306
ef808d50 1307 /* 8168C family. */
7f3e3d3a 1308 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1309 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1310 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1311 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1312 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1313 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1314 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1315 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1316 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1317
1318 /* 8168B family. */
1319 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1320 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1321 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1322 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1323
1324 /* 8101 family. */
2857ffb7
FR		 1325 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1326 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1327 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1328 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1329 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1330 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1331 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1332 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1333 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1334 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1335 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1336 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1337 /* FIXME: where did these entries come from ? -- FR */
1338 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1339 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1340
1341 /* 8110 family. */
1342 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1343 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1344 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1345 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1346 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1347 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1348
f21b75e9
JD		 1349 /* Catch-all */
1350 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1351 }, *p = mac_info;
1352 u32 reg;
1353
e3cf0cc0
FR		 1354 reg = RTL_R32(TxConfig);
1355 while ((reg & p->mask) != p->val)
1da177e4
LT		 1356 p++;
1357 tp->mac_version = p->mac_version;
1358}
1359
1360static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1361{
bcf0bf90 1362 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1363}
1364
867763c1
FR		 1365struct phy_reg {
1366 u16 reg;
1367 u16 val;
1368};
1369
350f7596 1370static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1371{
1372 while (len-- > 0) {
1373 mdio_write(ioaddr, regs->reg, regs->val);
1374 regs++;
1375 }
1376}
1377
5615d9f1 1378static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1379{
350f7596 1380 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1381 { 0x1f, 0x0001 },
1382 { 0x06, 0x006e },
1383 { 0x08, 0x0708 },
1384 { 0x15, 0x4000 },
1385 { 0x18, 0x65c7 },
1da177e4 1386
0b9b571d 1387 { 0x1f, 0x0001 },
1388 { 0x03, 0x00a1 },
1389 { 0x02, 0x0008 },
1390 { 0x01, 0x0120 },
1391 { 0x00, 0x1000 },
1392 { 0x04, 0x0800 },
1393 { 0x04, 0x0000 },
1da177e4 1394
0b9b571d 1395 { 0x03, 0xff41 },
1396 { 0x02, 0xdf60 },
1397 { 0x01, 0x0140 },
1398 { 0x00, 0x0077 },
1399 { 0x04, 0x7800 },
1400 { 0x04, 0x7000 },
1401
1402 { 0x03, 0x802f },
1403 { 0x02, 0x4f02 },
1404 { 0x01, 0x0409 },
1405 { 0x00, 0xf0f9 },
1406 { 0x04, 0x9800 },
1407 { 0x04, 0x9000 },
1408
1409 { 0x03, 0xdf01 },
1410 { 0x02, 0xdf20 },
1411 { 0x01, 0xff95 },
1412 { 0x00, 0xba00 },
1413 { 0x04, 0xa800 },
1414 { 0x04, 0xa000 },
1415
1416 { 0x03, 0xff41 },
1417 { 0x02, 0xdf20 },
1418 { 0x01, 0x0140 },
1419 { 0x00, 0x00bb },
1420 { 0x04, 0xb800 },
1421 { 0x04, 0xb000 },
1422
1423 { 0x03, 0xdf41 },
1424 { 0x02, 0xdc60 },
1425 { 0x01, 0x6340 },
1426 { 0x00, 0x007d },
1427 { 0x04, 0xd800 },
1428 { 0x04, 0xd000 },
1429
1430 { 0x03, 0xdf01 },
1431 { 0x02, 0xdf20 },
1432 { 0x01, 0x100a },
1433 { 0x00, 0xa0ff },
1434 { 0x04, 0xf800 },
1435 { 0x04, 0xf000 },
1436
1437 { 0x1f, 0x0000 },
1438 { 0x0b, 0x0000 },
1439 { 0x00, 0x9200 }
1440 };
1da177e4 1441
0b9b571d 1442 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1443}
1444
5615d9f1
FR		 1445static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1446{
350f7596 1447 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1448 { 0x1f, 0x0002 },
1449 { 0x01, 0x90d0 },
1450 { 0x1f, 0x0000 }
1451 };
1452
1453 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1454}
1455
2e955856 1456static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1457 void __iomem *ioaddr)
1458{
1459 struct pci_dev *pdev = tp->pci_dev;
1460 u16 vendor_id, device_id;
1461
1462 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1463 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1464
1465 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1466 return;
1467
1468 mdio_write(ioaddr, 0x1f, 0x0001);
1469 mdio_write(ioaddr, 0x10, 0xf01b);
1470 mdio_write(ioaddr, 0x1f, 0x0000);
1471}
1472
1473static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1474 void __iomem *ioaddr)
1475{
350f7596 1476 static const struct phy_reg phy_reg_init[] = {
2e955856 1477 { 0x1f, 0x0001 },
1478 { 0x04, 0x0000 },
1479 { 0x03, 0x00a1 },
1480 { 0x02, 0x0008 },
1481 { 0x01, 0x0120 },
1482 { 0x00, 0x1000 },
1483 { 0x04, 0x0800 },
1484 { 0x04, 0x9000 },
1485 { 0x03, 0x802f },
1486 { 0x02, 0x4f02 },
1487 { 0x01, 0x0409 },
1488 { 0x00, 0xf099 },
1489 { 0x04, 0x9800 },
1490 { 0x04, 0xa000 },
1491 { 0x03, 0xdf01 },
1492 { 0x02, 0xdf20 },
1493 { 0x01, 0xff95 },
1494 { 0x00, 0xba00 },
1495 { 0x04, 0xa800 },
1496 { 0x04, 0xf000 },
1497 { 0x03, 0xdf01 },
1498 { 0x02, 0xdf20 },
1499 { 0x01, 0x101a },
1500 { 0x00, 0xa0ff },
1501 { 0x04, 0xf800 },
1502 { 0x04, 0x0000 },
1503 { 0x1f, 0x0000 },
1504
1505 { 0x1f, 0x0001 },
1506 { 0x10, 0xf41b },
1507 { 0x14, 0xfb54 },
1508 { 0x18, 0xf5c7 },
1509 { 0x1f, 0x0000 },
1510
1511 { 0x1f, 0x0001 },
1512 { 0x17, 0x0cc0 },
1513 { 0x1f, 0x0000 }
1514 };
1515
1516 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1517
1518 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1519}
1520
8c7006aa 1521static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1522{
350f7596 1523 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1524 { 0x1f, 0x0001 },
1525 { 0x04, 0x0000 },
1526 { 0x03, 0x00a1 },
1527 { 0x02, 0x0008 },
1528 { 0x01, 0x0120 },
1529 { 0x00, 0x1000 },
1530 { 0x04, 0x0800 },
1531 { 0x04, 0x9000 },
1532 { 0x03, 0x802f },
1533 { 0x02, 0x4f02 },
1534 { 0x01, 0x0409 },
1535 { 0x00, 0xf099 },
1536 { 0x04, 0x9800 },
1537 { 0x04, 0xa000 },
1538 { 0x03, 0xdf01 },
1539 { 0x02, 0xdf20 },
1540 { 0x01, 0xff95 },
1541 { 0x00, 0xba00 },
1542 { 0x04, 0xa800 },
1543 { 0x04, 0xf000 },
1544 { 0x03, 0xdf01 },
1545 { 0x02, 0xdf20 },
1546 { 0x01, 0x101a },
1547 { 0x00, 0xa0ff },
1548 { 0x04, 0xf800 },
1549 { 0x04, 0x0000 },
1550 { 0x1f, 0x0000 },
1551
1552 { 0x1f, 0x0001 },
1553 { 0x0b, 0x8480 },
1554 { 0x1f, 0x0000 },
1555
1556 { 0x1f, 0x0001 },
1557 { 0x18, 0x67c7 },
1558 { 0x04, 0x2000 },
1559 { 0x03, 0x002f },
1560 { 0x02, 0x4360 },
1561 { 0x01, 0x0109 },
1562 { 0x00, 0x3022 },
1563 { 0x04, 0x2800 },
1564 { 0x1f, 0x0000 },
1565
1566 { 0x1f, 0x0001 },
1567 { 0x17, 0x0cc0 },
1568 { 0x1f, 0x0000 }
1569 };
1570
1571 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1572}
1573
236b8082
FR		 1574static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1575{
350f7596 1576 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1577 { 0x10, 0xf41b },
1578 { 0x1f, 0x0000 }
1579 };
1580
1581 mdio_write(ioaddr, 0x1f, 0x0001);
1582 mdio_patch(ioaddr, 0x16, 1 << 0);
1583
1584 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1585}
1586
1587static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1588{
350f7596 1589 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1590 { 0x1f, 0x0001 },
1591 { 0x10, 0xf41b },
1592 { 0x1f, 0x0000 }
1593 };
1594
1595 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1596}
1597
ef3386f0 1598static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1599{
350f7596 1600 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1601 { 0x1f, 0x0000 },
1602 { 0x1d, 0x0f00 },
1603 { 0x1f, 0x0002 },
1604 { 0x0c, 0x1ec8 },
1605 { 0x1f, 0x0000 }
1606 };
1607
1608 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1609}
1610
ef3386f0
FR		 1611static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1612{
350f7596 1613 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1614 { 0x1f, 0x0001 },
1615 { 0x1d, 0x3d98 },
1616 { 0x1f, 0x0000 }
1617 };
1618
1619 mdio_write(ioaddr, 0x1f, 0x0000);
1620 mdio_patch(ioaddr, 0x14, 1 << 5);
1621 mdio_patch(ioaddr, 0x0d, 1 << 5);
1622
1623 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1624}
1625
219a1e9d 1626static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1627{
350f7596 1628 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1629 { 0x1f, 0x0001 },
1630 { 0x12, 0x2300 },
867763c1
FR		 1631 { 0x1f, 0x0002 },
1632 { 0x00, 0x88d4 },
1633 { 0x01, 0x82b1 },
1634 { 0x03, 0x7002 },
1635 { 0x08, 0x9e30 },
1636 { 0x09, 0x01f0 },
1637 { 0x0a, 0x5500 },
1638 { 0x0c, 0x00c8 },
1639 { 0x1f, 0x0003 },
1640 { 0x12, 0xc096 },
1641 { 0x16, 0x000a },
f50d4275
FR		 1642 { 0x1f, 0x0000 },
1643 { 0x1f, 0x0000 },
1644 { 0x09, 0x2000 },
1645 { 0x09, 0x0000 }
867763c1
FR		 1646 };
1647
1648 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1649
1650 mdio_patch(ioaddr, 0x14, 1 << 5);
1651 mdio_patch(ioaddr, 0x0d, 1 << 5);
1652 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1653}
1654
219a1e9d 1655static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1656{
350f7596 1657 static const struct phy_reg phy_reg_init[] = {
f50d4275 1658 { 0x1f, 0x0001 },
7da97ec9 1659 { 0x12, 0x2300 },
f50d4275
FR		 1660 { 0x03, 0x802f },
1661 { 0x02, 0x4f02 },
1662 { 0x01, 0x0409 },
1663 { 0x00, 0xf099 },
1664 { 0x04, 0x9800 },
1665 { 0x04, 0x9000 },
1666 { 0x1d, 0x3d98 },
7da97ec9
FR		 1667 { 0x1f, 0x0002 },
1668 { 0x0c, 0x7eb8 },
f50d4275
FR		 1669 { 0x06, 0x0761 },
1670 { 0x1f, 0x0003 },
1671 { 0x16, 0x0f0a },
7da97ec9
FR		 1672 { 0x1f, 0x0000 }
1673 };
1674
1675 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1676
1677 mdio_patch(ioaddr, 0x16, 1 << 0);
1678 mdio_patch(ioaddr, 0x14, 1 << 5);
1679 mdio_patch(ioaddr, 0x0d, 1 << 5);
1680 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1681}
1682
197ff761
FR		 1683static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1684{
350f7596 1685 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1686 { 0x1f, 0x0001 },
1687 { 0x12, 0x2300 },
1688 { 0x1d, 0x3d98 },
1689 { 0x1f, 0x0002 },
1690 { 0x0c, 0x7eb8 },
1691 { 0x06, 0x5461 },
1692 { 0x1f, 0x0003 },
1693 { 0x16, 0x0f0a },
1694 { 0x1f, 0x0000 }
1695 };
1696
1697 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1698
1699 mdio_patch(ioaddr, 0x16, 1 << 0);
1700 mdio_patch(ioaddr, 0x14, 1 << 5);
1701 mdio_patch(ioaddr, 0x0d, 1 << 5);
1702 mdio_write(ioaddr, 0x1f, 0x0000);
1703}
1704
6fb07058
FR		 1705static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1706{
1707 rtl8168c_3_hw_phy_config(ioaddr);
1708}
1709
daf9df6d 1710static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1711{
350f7596 1712 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1713 { 0x1f, 0x0001 },
daf9df6d 1714 { 0x06, 0x4064 },
1715 { 0x07, 0x2863 },
1716 { 0x08, 0x059c },
1717 { 0x09, 0x26b4 },
1718 { 0x0a, 0x6a19 },
1719 { 0x0b, 0xdcc8 },
1720 { 0x10, 0xf06d },
1721 { 0x14, 0x7f68 },
1722 { 0x18, 0x7fd9 },
1723 { 0x1c, 0xf0ff },
1724 { 0x1d, 0x3d9c },
5b538df9 1725 { 0x1f, 0x0003 },
daf9df6d 1726 { 0x12, 0xf49f },
1727 { 0x13, 0x070b },
1728 { 0x1a, 0x05ad },
1729 { 0x14, 0x94c0 }
1730 };
350f7596 1731 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1732 { 0x1f, 0x0002 },
daf9df6d 1733 { 0x06, 0x5561 },
1734 { 0x1f, 0x0005 },
1735 { 0x05, 0x8332 },
1736 { 0x06, 0x5561 }
1737 };
350f7596 1738 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1739 { 0x1f, 0x0005 },
1740 { 0x05, 0xffc2 },
1741 { 0x1f, 0x0005 },
1742 { 0x05, 0x8000 },
1743 { 0x06, 0xf8f9 },
1744 { 0x06, 0xfaef },
1745 { 0x06, 0x59ee },
1746 { 0x06, 0xf8ea },
1747 { 0x06, 0x00ee },
1748 { 0x06, 0xf8eb },
1749 { 0x06, 0x00e0 },
1750 { 0x06, 0xf87c },
1751 { 0x06, 0xe1f8 },
1752 { 0x06, 0x7d59 },
1753 { 0x06, 0x0fef },
1754 { 0x06, 0x0139 },
1755 { 0x06, 0x029e },
1756 { 0x06, 0x06ef },
1757 { 0x06, 0x1039 },
1758 { 0x06, 0x089f },
1759 { 0x06, 0x2aee },
1760 { 0x06, 0xf8ea },
1761 { 0x06, 0x00ee },
1762 { 0x06, 0xf8eb },
1763 { 0x06, 0x01e0 },
1764 { 0x06, 0xf87c },
1765 { 0x06, 0xe1f8 },
1766 { 0x06, 0x7d58 },
1767 { 0x06, 0x409e },
1768 { 0x06, 0x0f39 },
1769 { 0x06, 0x46aa },
1770 { 0x06, 0x0bbf },
1771 { 0x06, 0x8290 },
1772 { 0x06, 0xd682 },
1773 { 0x06, 0x9802 },
1774 { 0x06, 0x014f },
1775 { 0x06, 0xae09 },
1776 { 0x06, 0xbf82 },
1777 { 0x06, 0x98d6 },
1778 { 0x06, 0x82a0 },
1779 { 0x06, 0x0201 },
1780 { 0x06, 0x4fef },
1781 { 0x06, 0x95fe },
1782 { 0x06, 0xfdfc },
1783 { 0x06, 0x05f8 },
1784 { 0x06, 0xf9fa },
1785 { 0x06, 0xeef8 },
1786 { 0x06, 0xea00 },
1787 { 0x06, 0xeef8 },
1788 { 0x06, 0xeb00 },
1789 { 0x06, 0xe2f8 },
1790 { 0x06, 0x7ce3 },
1791 { 0x06, 0xf87d },
1792 { 0x06, 0xa511 },
1793 { 0x06, 0x1112 },
1794 { 0x06, 0xd240 },
1795 { 0x06, 0xd644 },
1796 { 0x06, 0x4402 },
1797 { 0x06, 0x8217 },
1798 { 0x06, 0xd2a0 },
1799 { 0x06, 0xd6aa },
1800 { 0x06, 0xaa02 },
1801 { 0x06, 0x8217 },
1802 { 0x06, 0xae0f },
1803 { 0x06, 0xa544 },
1804 { 0x06, 0x4402 },
1805 { 0x06, 0xae4d },
1806 { 0x06, 0xa5aa },
1807 { 0x06, 0xaa02 },
1808 { 0x06, 0xae47 },
1809 { 0x06, 0xaf82 },
1810 { 0x06, 0x13ee },
1811 { 0x06, 0x834e },
1812 { 0x06, 0x00ee },
1813 { 0x06, 0x834d },
1814 { 0x06, 0x0fee },
1815 { 0x06, 0x834c },
1816 { 0x06, 0x0fee },
1817 { 0x06, 0x834f },
1818 { 0x06, 0x00ee },
1819 { 0x06, 0x8351 },
1820 { 0x06, 0x00ee },
1821 { 0x06, 0x834a },
1822 { 0x06, 0xffee },
1823 { 0x06, 0x834b },
1824 { 0x06, 0xffe0 },
1825 { 0x06, 0x8330 },
1826 { 0x06, 0xe183 },
1827 { 0x06, 0x3158 },
1828 { 0x06, 0xfee4 },
1829 { 0x06, 0xf88a },
1830 { 0x06, 0xe5f8 },
1831 { 0x06, 0x8be0 },
1832 { 0x06, 0x8332 },
1833 { 0x06, 0xe183 },
1834 { 0x06, 0x3359 },
1835 { 0x06, 0x0fe2 },
1836 { 0x06, 0x834d },
1837 { 0x06, 0x0c24 },
1838 { 0x06, 0x5af0 },
1839 { 0x06, 0x1e12 },
1840 { 0x06, 0xe4f8 },
1841 { 0x06, 0x8ce5 },
1842 { 0x06, 0xf88d },
1843 { 0x06, 0xaf82 },
1844 { 0x06, 0x13e0 },
1845 { 0x06, 0x834f },
1846 { 0x06, 0x10e4 },
1847 { 0x06, 0x834f },
1848 { 0x06, 0xe083 },
1849 { 0x06, 0x4e78 },
1850 { 0x06, 0x009f },
1851 { 0x06, 0x0ae0 },
1852 { 0x06, 0x834f },
1853 { 0x06, 0xa010 },
1854 { 0x06, 0xa5ee },
1855 { 0x06, 0x834e },
1856 { 0x06, 0x01e0 },
1857 { 0x06, 0x834e },
1858 { 0x06, 0x7805 },
1859 { 0x06, 0x9e9a },
1860 { 0x06, 0xe083 },
1861 { 0x06, 0x4e78 },
1862 { 0x06, 0x049e },
1863 { 0x06, 0x10e0 },
1864 { 0x06, 0x834e },
1865 { 0x06, 0x7803 },
1866 { 0x06, 0x9e0f },
1867 { 0x06, 0xe083 },
1868 { 0x06, 0x4e78 },
1869 { 0x06, 0x019e },
1870 { 0x06, 0x05ae },
1871 { 0x06, 0x0caf },
1872 { 0x06, 0x81f8 },
1873 { 0x06, 0xaf81 },
1874 { 0x06, 0xa3af },
1875 { 0x06, 0x81dc },
1876 { 0x06, 0xaf82 },
1877 { 0x06, 0x13ee },
1878 { 0x06, 0x8348 },
1879 { 0x06, 0x00ee },
1880 { 0x06, 0x8349 },
1881 { 0x06, 0x00e0 },
1882 { 0x06, 0x8351 },
1883 { 0x06, 0x10e4 },
1884 { 0x06, 0x8351 },
1885 { 0x06, 0x5801 },
1886 { 0x06, 0x9fea },
1887 { 0x06, 0xd000 },
1888 { 0x06, 0xd180 },
1889 { 0x06, 0x1f66 },
1890 { 0x06, 0xe2f8 },
1891 { 0x06, 0xeae3 },
1892 { 0x06, 0xf8eb },
1893 { 0x06, 0x5af8 },
1894 { 0x06, 0x1e20 },
1895 { 0x06, 0xe6f8 },
1896 { 0x06, 0xeae5 },
1897 { 0x06, 0xf8eb },
1898 { 0x06, 0xd302 },
1899 { 0x06, 0xb3fe },
1900 { 0x06, 0xe2f8 },
1901 { 0x06, 0x7cef },
1902 { 0x06, 0x325b },
1903 { 0x06, 0x80e3 },
1904 { 0x06, 0xf87d },
1905 { 0x06, 0x9e03 },
1906 { 0x06, 0x7dff },
1907 { 0x06, 0xff0d },
1908 { 0x06, 0x581c },
1909 { 0x06, 0x551a },
1910 { 0x06, 0x6511 },
1911 { 0x06, 0xa190 },
1912 { 0x06, 0xd3e2 },
1913 { 0x06, 0x8348 },
1914 { 0x06, 0xe383 },
1915 { 0x06, 0x491b },
1916 { 0x06, 0x56ab },
1917 { 0x06, 0x08ef },
1918 { 0x06, 0x56e6 },
1919 { 0x06, 0x8348 },
1920 { 0x06, 0xe783 },
1921 { 0x06, 0x4910 },
1922 { 0x06, 0xd180 },
1923 { 0x06, 0x1f66 },
1924 { 0x06, 0xa004 },
1925 { 0x06, 0xb9e2 },
1926 { 0x06, 0x8348 },
1927 { 0x06, 0xe383 },
1928 { 0x06, 0x49ef },
1929 { 0x06, 0x65e2 },
1930 { 0x06, 0x834a },
1931 { 0x06, 0xe383 },
1932 { 0x06, 0x4b1b },
1933 { 0x06, 0x56aa },
1934 { 0x06, 0x0eef },
1935 { 0x06, 0x56e6 },
1936 { 0x06, 0x834a },
1937 { 0x06, 0xe783 },
1938 { 0x06, 0x4be2 },
1939 { 0x06, 0x834d },
1940 { 0x06, 0xe683 },
1941 { 0x06, 0x4ce0 },
1942 { 0x06, 0x834d },
1943 { 0x06, 0xa000 },
1944 { 0x06, 0x0caf },
1945 { 0x06, 0x81dc },
1946 { 0x06, 0xe083 },
1947 { 0x06, 0x4d10 },
1948 { 0x06, 0xe483 },
1949 { 0x06, 0x4dae },
1950 { 0x06, 0x0480 },
1951 { 0x06, 0xe483 },
1952 { 0x06, 0x4de0 },
1953 { 0x06, 0x834e },
1954 { 0x06, 0x7803 },
1955 { 0x06, 0x9e0b },
1956 { 0x06, 0xe083 },
1957 { 0x06, 0x4e78 },
1958 { 0x06, 0x049e },
1959 { 0x06, 0x04ee },
1960 { 0x06, 0x834e },
1961 { 0x06, 0x02e0 },
1962 { 0x06, 0x8332 },
1963 { 0x06, 0xe183 },
1964 { 0x06, 0x3359 },
1965 { 0x06, 0x0fe2 },
1966 { 0x06, 0x834d },
1967 { 0x06, 0x0c24 },
1968 { 0x06, 0x5af0 },
1969 { 0x06, 0x1e12 },
1970 { 0x06, 0xe4f8 },
1971 { 0x06, 0x8ce5 },
1972 { 0x06, 0xf88d },
1973 { 0x06, 0xe083 },
1974 { 0x06, 0x30e1 },
1975 { 0x06, 0x8331 },
1976 { 0x06, 0x6801 },
1977 { 0x06, 0xe4f8 },
1978 { 0x06, 0x8ae5 },
1979 { 0x06, 0xf88b },
1980 { 0x06, 0xae37 },
1981 { 0x06, 0xee83 },
1982 { 0x06, 0x4e03 },
1983 { 0x06, 0xe083 },
1984 { 0x06, 0x4ce1 },
1985 { 0x06, 0x834d },
1986 { 0x06, 0x1b01 },
1987 { 0x06, 0x9e04 },
1988 { 0x06, 0xaaa1 },
1989 { 0x06, 0xaea8 },
1990 { 0x06, 0xee83 },
1991 { 0x06, 0x4e04 },
1992 { 0x06, 0xee83 },
1993 { 0x06, 0x4f00 },
1994 { 0x06, 0xaeab },
1995 { 0x06, 0xe083 },
1996 { 0x06, 0x4f78 },
1997 { 0x06, 0x039f },
1998 { 0x06, 0x14ee },
1999 { 0x06, 0x834e },
2000 { 0x06, 0x05d2 },
2001 { 0x06, 0x40d6 },
2002 { 0x06, 0x5554 },
2003 { 0x06, 0x0282 },
2004 { 0x06, 0x17d2 },
2005 { 0x06, 0xa0d6 },
2006 { 0x06, 0xba00 },
2007 { 0x06, 0x0282 },
2008 { 0x06, 0x17fe },
2009 { 0x06, 0xfdfc },
2010 { 0x06, 0x05f8 },
2011 { 0x06, 0xe0f8 },
2012 { 0x06, 0x60e1 },
2013 { 0x06, 0xf861 },
2014 { 0x06, 0x6802 },
2015 { 0x06, 0xe4f8 },
2016 { 0x06, 0x60e5 },
2017 { 0x06, 0xf861 },
2018 { 0x06, 0xe0f8 },
2019 { 0x06, 0x48e1 },
2020 { 0x06, 0xf849 },
2021 { 0x06, 0x580f },
2022 { 0x06, 0x1e02 },
2023 { 0x06, 0xe4f8 },
2024 { 0x06, 0x48e5 },
2025 { 0x06, 0xf849 },
2026 { 0x06, 0xd000 },
2027 { 0x06, 0x0282 },
2028 { 0x06, 0x5bbf },
2029 { 0x06, 0x8350 },
2030 { 0x06, 0xef46 },
2031 { 0x06, 0xdc19 },
2032 { 0x06, 0xddd0 },
2033 { 0x06, 0x0102 },
2034 { 0x06, 0x825b },
2035 { 0x06, 0x0282 },
2036 { 0x06, 0x77e0 },
2037 { 0x06, 0xf860 },
2038 { 0x06, 0xe1f8 },
2039 { 0x06, 0x6158 },
2040 { 0x06, 0xfde4 },
2041 { 0x06, 0xf860 },
2042 { 0x06, 0xe5f8 },
2043 { 0x06, 0x61fc },
2044 { 0x06, 0x04f9 },
2045 { 0x06, 0xfafb },
2046 { 0x06, 0xc6bf },
2047 { 0x06, 0xf840 },
2048 { 0x06, 0xbe83 },
2049 { 0x06, 0x50a0 },
2050 { 0x06, 0x0101 },
2051 { 0x06, 0x071b },
2052 { 0x06, 0x89cf },
2053 { 0x06, 0xd208 },
2054 { 0x06, 0xebdb },
2055 { 0x06, 0x19b2 },
2056 { 0x06, 0xfbff },
2057 { 0x06, 0xfefd },
2058 { 0x06, 0x04f8 },
2059 { 0x06, 0xe0f8 },
2060 { 0x06, 0x48e1 },
2061 { 0x06, 0xf849 },
2062 { 0x06, 0x6808 },
2063 { 0x06, 0xe4f8 },
2064 { 0x06, 0x48e5 },
2065 { 0x06, 0xf849 },
2066 { 0x06, 0x58f7 },
2067 { 0x06, 0xe4f8 },
2068 { 0x06, 0x48e5 },
2069 { 0x06, 0xf849 },
2070 { 0x06, 0xfc04 },
2071 { 0x06, 0x4d20 },
2072 { 0x06, 0x0002 },
2073 { 0x06, 0x4e22 },
2074 { 0x06, 0x0002 },
2075 { 0x06, 0x4ddf },
2076 { 0x06, 0xff01 },
2077 { 0x06, 0x4edd },
2078 { 0x06, 0xff01 },
2079 { 0x05, 0x83d4 },
2080 { 0x06, 0x8000 },
2081 { 0x05, 0x83d8 },
2082 { 0x06, 0x8051 },
2083 { 0x02, 0x6010 },
2084 { 0x03, 0xdc00 },
2085 { 0x05, 0xfff6 },
2086 { 0x06, 0x00fc },
5b538df9 2087 { 0x1f, 0x0000 },
daf9df6d 2088
5b538df9 2089 { 0x1f, 0x0000 },
daf9df6d 2090 { 0x0d, 0xf880 },
2091 { 0x1f, 0x0000 }
2092 };
2093
2094 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2095
2096 mdio_write(ioaddr, 0x1f, 0x0002);
2097 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2098 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2099
2100 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2101
2102 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2103 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2104 { 0x1f, 0x0002 },
2105 { 0x05, 0x669a },
2106 { 0x1f, 0x0005 },
2107 { 0x05, 0x8330 },
2108 { 0x06, 0x669a },
2109 { 0x1f, 0x0002 }
2110 };
2111 int val;
2112
2113 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2114
2115 val = mdio_read(ioaddr, 0x0d);
2116
2117 if ((val & 0x00ff) != 0x006c) {
350f7596 2118 static const u32 set[] = {
daf9df6d 2119 0x0065, 0x0066, 0x0067, 0x0068,
2120 0x0069, 0x006a, 0x006b, 0x006c
2121 };
2122 int i;
2123
2124 mdio_write(ioaddr, 0x1f, 0x0002);
2125
2126 val &= 0xff00;
2127 for (i = 0; i < ARRAY_SIZE(set); i++)
2128 mdio_write(ioaddr, 0x0d, val | set[i]);
2129 }
2130 } else {
350f7596 2131 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2132 { 0x1f, 0x0002 },
2133 { 0x05, 0x6662 },
2134 { 0x1f, 0x0005 },
2135 { 0x05, 0x8330 },
2136 { 0x06, 0x6662 }
2137 };
2138
2139 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2140 }
2141
2142 mdio_write(ioaddr, 0x1f, 0x0002);
2143 mdio_patch(ioaddr, 0x0d, 0x0300);
2144 mdio_patch(ioaddr, 0x0f, 0x0010);
2145
2146 mdio_write(ioaddr, 0x1f, 0x0002);
2147 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2148 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2149
2150 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2151}
2152
2153static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2154{
350f7596 2155 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2156 { 0x1f, 0x0001 },
2157 { 0x06, 0x4064 },
2158 { 0x07, 0x2863 },
2159 { 0x08, 0x059c },
2160 { 0x09, 0x26b4 },
2161 { 0x0a, 0x6a19 },
2162 { 0x0b, 0xdcc8 },
2163 { 0x10, 0xf06d },
2164 { 0x14, 0x7f68 },
2165 { 0x18, 0x7fd9 },
2166 { 0x1c, 0xf0ff },
2167 { 0x1d, 0x3d9c },
2168 { 0x1f, 0x0003 },
2169 { 0x12, 0xf49f },
2170 { 0x13, 0x070b },
2171 { 0x1a, 0x05ad },
2172 { 0x14, 0x94c0 },
2173
2174 { 0x1f, 0x0002 },
2175 { 0x06, 0x5561 },
2176 { 0x1f, 0x0005 },
2177 { 0x05, 0x8332 },
2178 { 0x06, 0x5561 }
2179 };
350f7596 2180 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2181 { 0x1f, 0x0005 },
2182 { 0x05, 0xffc2 },
5b538df9 2183 { 0x1f, 0x0005 },
daf9df6d 2184 { 0x05, 0x8000 },
2185 { 0x06, 0xf8f9 },
2186 { 0x06, 0xfaee },
2187 { 0x06, 0xf8ea },
2188 { 0x06, 0x00ee },
2189 { 0x06, 0xf8eb },
2190 { 0x06, 0x00e2 },
2191 { 0x06, 0xf87c },
2192 { 0x06, 0xe3f8 },
2193 { 0x06, 0x7da5 },
2194 { 0x06, 0x1111 },
2195 { 0x06, 0x12d2 },
2196 { 0x06, 0x40d6 },
2197 { 0x06, 0x4444 },
2198 { 0x06, 0x0281 },
2199 { 0x06, 0xc6d2 },
2200 { 0x06, 0xa0d6 },
2201 { 0x06, 0xaaaa },
2202 { 0x06, 0x0281 },
2203 { 0x06, 0xc6ae },
2204 { 0x06, 0x0fa5 },
2205 { 0x06, 0x4444 },
2206 { 0x06, 0x02ae },
2207 { 0x06, 0x4da5 },
2208 { 0x06, 0xaaaa },
2209 { 0x06, 0x02ae },
2210 { 0x06, 0x47af },
2211 { 0x06, 0x81c2 },
2212 { 0x06, 0xee83 },
2213 { 0x06, 0x4e00 },
2214 { 0x06, 0xee83 },
2215 { 0x06, 0x4d0f },
2216 { 0x06, 0xee83 },
2217 { 0x06, 0x4c0f },
2218 { 0x06, 0xee83 },
2219 { 0x06, 0x4f00 },
2220 { 0x06, 0xee83 },
2221 { 0x06, 0x5100 },
2222 { 0x06, 0xee83 },
2223 { 0x06, 0x4aff },
2224 { 0x06, 0xee83 },
2225 { 0x06, 0x4bff },
2226 { 0x06, 0xe083 },
2227 { 0x06, 0x30e1 },
2228 { 0x06, 0x8331 },
2229 { 0x06, 0x58fe },
2230 { 0x06, 0xe4f8 },
2231 { 0x06, 0x8ae5 },
2232 { 0x06, 0xf88b },
2233 { 0x06, 0xe083 },
2234 { 0x06, 0x32e1 },
2235 { 0x06, 0x8333 },
2236 { 0x06, 0x590f },
2237 { 0x06, 0xe283 },
2238 { 0x06, 0x4d0c },
2239 { 0x06, 0x245a },
2240 { 0x06, 0xf01e },
2241 { 0x06, 0x12e4 },
2242 { 0x06, 0xf88c },
2243 { 0x06, 0xe5f8 },
2244 { 0x06, 0x8daf },
2245 { 0x06, 0x81c2 },
2246 { 0x06, 0xe083 },
2247 { 0x06, 0x4f10 },
2248 { 0x06, 0xe483 },
2249 { 0x06, 0x4fe0 },
2250 { 0x06, 0x834e },
2251 { 0x06, 0x7800 },
2252 { 0x06, 0x9f0a },
2253 { 0x06, 0xe083 },
2254 { 0x06, 0x4fa0 },
2255 { 0x06, 0x10a5 },
2256 { 0x06, 0xee83 },
2257 { 0x06, 0x4e01 },
2258 { 0x06, 0xe083 },
2259 { 0x06, 0x4e78 },
2260 { 0x06, 0x059e },
2261 { 0x06, 0x9ae0 },
2262 { 0x06, 0x834e },
2263 { 0x06, 0x7804 },
2264 { 0x06, 0x9e10 },
2265 { 0x06, 0xe083 },
2266 { 0x06, 0x4e78 },
2267 { 0x06, 0x039e },
2268 { 0x06, 0x0fe0 },
2269 { 0x06, 0x834e },
2270 { 0x06, 0x7801 },
2271 { 0x06, 0x9e05 },
2272 { 0x06, 0xae0c },
2273 { 0x06, 0xaf81 },
2274 { 0x06, 0xa7af },
2275 { 0x06, 0x8152 },
2276 { 0x06, 0xaf81 },
2277 { 0x06, 0x8baf },
2278 { 0x06, 0x81c2 },
2279 { 0x06, 0xee83 },
2280 { 0x06, 0x4800 },
2281 { 0x06, 0xee83 },
2282 { 0x06, 0x4900 },
2283 { 0x06, 0xe083 },
2284 { 0x06, 0x5110 },
2285 { 0x06, 0xe483 },
2286 { 0x06, 0x5158 },
2287 { 0x06, 0x019f },
2288 { 0x06, 0xead0 },
2289 { 0x06, 0x00d1 },
2290 { 0x06, 0x801f },
2291 { 0x06, 0x66e2 },
2292 { 0x06, 0xf8ea },
2293 { 0x06, 0xe3f8 },
2294 { 0x06, 0xeb5a },
2295 { 0x06, 0xf81e },
2296 { 0x06, 0x20e6 },
2297 { 0x06, 0xf8ea },
2298 { 0x06, 0xe5f8 },
2299 { 0x06, 0xebd3 },
2300 { 0x06, 0x02b3 },
2301 { 0x06, 0xfee2 },
2302 { 0x06, 0xf87c },
2303 { 0x06, 0xef32 },
2304 { 0x06, 0x5b80 },
2305 { 0x06, 0xe3f8 },
2306 { 0x06, 0x7d9e },
2307 { 0x06, 0x037d },
2308 { 0x06, 0xffff },
2309 { 0x06, 0x0d58 },
2310 { 0x06, 0x1c55 },
2311 { 0x06, 0x1a65 },
2312 { 0x06, 0x11a1 },
2313 { 0x06, 0x90d3 },
2314 { 0x06, 0xe283 },
2315 { 0x06, 0x48e3 },
2316 { 0x06, 0x8349 },
2317 { 0x06, 0x1b56 },
2318 { 0x06, 0xab08 },
2319 { 0x06, 0xef56 },
2320 { 0x06, 0xe683 },
2321 { 0x06, 0x48e7 },
2322 { 0x06, 0x8349 },
2323 { 0x06, 0x10d1 },
2324 { 0x06, 0x801f },
2325 { 0x06, 0x66a0 },
2326 { 0x06, 0x04b9 },
2327 { 0x06, 0xe283 },
2328 { 0x06, 0x48e3 },
2329 { 0x06, 0x8349 },
2330 { 0x06, 0xef65 },
2331 { 0x06, 0xe283 },
2332 { 0x06, 0x4ae3 },
2333 { 0x06, 0x834b },
2334 { 0x06, 0x1b56 },
2335 { 0x06, 0xaa0e },
2336 { 0x06, 0xef56 },
2337 { 0x06, 0xe683 },
2338 { 0x06, 0x4ae7 },
2339 { 0x06, 0x834b },
2340 { 0x06, 0xe283 },
2341 { 0x06, 0x4de6 },
2342 { 0x06, 0x834c },
2343 { 0x06, 0xe083 },
2344 { 0x06, 0x4da0 },
2345 { 0x06, 0x000c },
2346 { 0x06, 0xaf81 },
2347 { 0x06, 0x8be0 },
2348 { 0x06, 0x834d },
2349 { 0x06, 0x10e4 },
2350 { 0x06, 0x834d },
2351 { 0x06, 0xae04 },
2352 { 0x06, 0x80e4 },
2353 { 0x06, 0x834d },
2354 { 0x06, 0xe083 },
2355 { 0x06, 0x4e78 },
2356 { 0x06, 0x039e },
2357 { 0x06, 0x0be0 },
2358 { 0x06, 0x834e },
2359 { 0x06, 0x7804 },
2360 { 0x06, 0x9e04 },
2361 { 0x06, 0xee83 },
2362 { 0x06, 0x4e02 },
2363 { 0x06, 0xe083 },
2364 { 0x06, 0x32e1 },
2365 { 0x06, 0x8333 },
2366 { 0x06, 0x590f },
2367 { 0x06, 0xe283 },
2368 { 0x06, 0x4d0c },
2369 { 0x06, 0x245a },
2370 { 0x06, 0xf01e },
2371 { 0x06, 0x12e4 },
2372 { 0x06, 0xf88c },
2373 { 0x06, 0xe5f8 },
2374 { 0x06, 0x8de0 },
2375 { 0x06, 0x8330 },
2376 { 0x06, 0xe183 },
2377 { 0x06, 0x3168 },
2378 { 0x06, 0x01e4 },
2379 { 0x06, 0xf88a },
2380 { 0x06, 0xe5f8 },
2381 { 0x06, 0x8bae },
2382 { 0x06, 0x37ee },
2383 { 0x06, 0x834e },
2384 { 0x06, 0x03e0 },
2385 { 0x06, 0x834c },
2386 { 0x06, 0xe183 },
2387 { 0x06, 0x4d1b },
2388 { 0x06, 0x019e },
2389 { 0x06, 0x04aa },
2390 { 0x06, 0xa1ae },
2391 { 0x06, 0xa8ee },
2392 { 0x06, 0x834e },
2393 { 0x06, 0x04ee },
2394 { 0x06, 0x834f },
2395 { 0x06, 0x00ae },
2396 { 0x06, 0xabe0 },
2397 { 0x06, 0x834f },
2398 { 0x06, 0x7803 },
2399 { 0x06, 0x9f14 },
2400 { 0x06, 0xee83 },
2401 { 0x06, 0x4e05 },
2402 { 0x06, 0xd240 },
2403 { 0x06, 0xd655 },
2404 { 0x06, 0x5402 },
2405 { 0x06, 0x81c6 },
2406 { 0x06, 0xd2a0 },
2407 { 0x06, 0xd6ba },
2408 { 0x06, 0x0002 },
2409 { 0x06, 0x81c6 },
2410 { 0x06, 0xfefd },
2411 { 0x06, 0xfc05 },
2412 { 0x06, 0xf8e0 },
2413 { 0x06, 0xf860 },
2414 { 0x06, 0xe1f8 },
2415 { 0x06, 0x6168 },
2416 { 0x06, 0x02e4 },
2417 { 0x06, 0xf860 },
2418 { 0x06, 0xe5f8 },
2419 { 0x06, 0x61e0 },
2420 { 0x06, 0xf848 },
2421 { 0x06, 0xe1f8 },
2422 { 0x06, 0x4958 },
2423 { 0x06, 0x0f1e },
2424 { 0x06, 0x02e4 },
2425 { 0x06, 0xf848 },
2426 { 0x06, 0xe5f8 },
2427 { 0x06, 0x49d0 },
2428 { 0x06, 0x0002 },
2429 { 0x06, 0x820a },
2430 { 0x06, 0xbf83 },
2431 { 0x06, 0x50ef },
2432 { 0x06, 0x46dc },
2433 { 0x06, 0x19dd },
2434 { 0x06, 0xd001 },
2435 { 0x06, 0x0282 },
2436 { 0x06, 0x0a02 },
2437 { 0x06, 0x8226 },
2438 { 0x06, 0xe0f8 },
2439 { 0x06, 0x60e1 },
2440 { 0x06, 0xf861 },
2441 { 0x06, 0x58fd },
2442 { 0x06, 0xe4f8 },
2443 { 0x06, 0x60e5 },
2444 { 0x06, 0xf861 },
2445 { 0x06, 0xfc04 },
2446 { 0x06, 0xf9fa },
2447 { 0x06, 0xfbc6 },
2448 { 0x06, 0xbff8 },
2449 { 0x06, 0x40be },
2450 { 0x06, 0x8350 },
2451 { 0x06, 0xa001 },
2452 { 0x06, 0x0107 },
2453 { 0x06, 0x1b89 },
2454 { 0x06, 0xcfd2 },
2455 { 0x06, 0x08eb },
2456 { 0x06, 0xdb19 },
2457 { 0x06, 0xb2fb },
2458 { 0x06, 0xfffe },
2459 { 0x06, 0xfd04 },
2460 { 0x06, 0xf8e0 },
2461 { 0x06, 0xf848 },
2462 { 0x06, 0xe1f8 },
2463 { 0x06, 0x4968 },
2464 { 0x06, 0x08e4 },
2465 { 0x06, 0xf848 },
2466 { 0x06, 0xe5f8 },
2467 { 0x06, 0x4958 },
2468 { 0x06, 0xf7e4 },
2469 { 0x06, 0xf848 },
2470 { 0x06, 0xe5f8 },
2471 { 0x06, 0x49fc },
2472 { 0x06, 0x044d },
2473 { 0x06, 0x2000 },
2474 { 0x06, 0x024e },
2475 { 0x06, 0x2200 },
2476 { 0x06, 0x024d },
2477 { 0x06, 0xdfff },
2478 { 0x06, 0x014e },
2479 { 0x06, 0xddff },
2480 { 0x06, 0x0100 },
2481 { 0x05, 0x83d8 },
2482 { 0x06, 0x8000 },
2483 { 0x03, 0xdc00 },
2484 { 0x05, 0xfff6 },
2485 { 0x06, 0x00fc },
2486 { 0x1f, 0x0000 },
2487
2488 { 0x1f, 0x0000 },
2489 { 0x0d, 0xf880 },
2490 { 0x1f, 0x0000 }
5b538df9
FR		 2491 };
2492
2493 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2494
daf9df6d 2495 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2496 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2497 { 0x1f, 0x0002 },
2498 { 0x05, 0x669a },
5b538df9 2499 { 0x1f, 0x0005 },
daf9df6d 2500 { 0x05, 0x8330 },
2501 { 0x06, 0x669a },
2502
2503 { 0x1f, 0x0002 }
2504 };
2505 int val;
2506
2507 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2508
2509 val = mdio_read(ioaddr, 0x0d);
2510 if ((val & 0x00ff) != 0x006c) {
2511 u32 set[] = {
2512 0x0065, 0x0066, 0x0067, 0x0068,
2513 0x0069, 0x006a, 0x006b, 0x006c
2514 };
2515 int i;
2516
2517 mdio_write(ioaddr, 0x1f, 0x0002);
2518
2519 val &= 0xff00;
2520 for (i = 0; i < ARRAY_SIZE(set); i++)
2521 mdio_write(ioaddr, 0x0d, val | set[i]);
2522 }
2523 } else {
350f7596 2524 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2525 { 0x1f, 0x0002 },
2526 { 0x05, 0x2642 },
5b538df9 2527 { 0x1f, 0x0005 },
daf9df6d 2528 { 0x05, 0x8330 },
2529 { 0x06, 0x2642 }
5b538df9
FR		 2530 };
2531
daf9df6d 2532 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2533 }
2534
daf9df6d 2535 mdio_write(ioaddr, 0x1f, 0x0002);
2536 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2537 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2538
2539 mdio_write(ioaddr, 0x1f, 0x0001);
2540 mdio_write(ioaddr, 0x17, 0x0cc0);
2541
2542 mdio_write(ioaddr, 0x1f, 0x0002);
2543 mdio_patch(ioaddr, 0x0f, 0x0017);
2544
2545 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2546}
2547
2548static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2549{
350f7596 2550 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2551 { 0x1f, 0x0002 },
2552 { 0x10, 0x0008 },
2553 { 0x0d, 0x006c },
2554
2555 { 0x1f, 0x0000 },
2556 { 0x0d, 0xf880 },
2557
2558 { 0x1f, 0x0001 },
2559 { 0x17, 0x0cc0 },
2560
2561 { 0x1f, 0x0001 },
2562 { 0x0b, 0xa4d8 },
2563 { 0x09, 0x281c },
2564 { 0x07, 0x2883 },
2565 { 0x0a, 0x6b35 },
2566 { 0x1d, 0x3da4 },
2567 { 0x1c, 0xeffd },
2568 { 0x14, 0x7f52 },
2569 { 0x18, 0x7fc6 },
2570 { 0x08, 0x0601 },
2571 { 0x06, 0x4063 },
2572 { 0x10, 0xf074 },
2573 { 0x1f, 0x0003 },
2574 { 0x13, 0x0789 },
2575 { 0x12, 0xf4bd },
2576 { 0x1a, 0x04fd },
2577 { 0x14, 0x84b0 },
2578 { 0x1f, 0x0000 },
2579 { 0x00, 0x9200 },
2580
2581 { 0x1f, 0x0005 },
2582 { 0x01, 0x0340 },
2583 { 0x1f, 0x0001 },
2584 { 0x04, 0x4000 },
2585 { 0x03, 0x1d21 },
2586 { 0x02, 0x0c32 },
2587 { 0x01, 0x0200 },
2588 { 0x00, 0x5554 },
2589 { 0x04, 0x4800 },
2590 { 0x04, 0x4000 },
2591 { 0x04, 0xf000 },
2592 { 0x03, 0xdf01 },
2593 { 0x02, 0xdf20 },
2594 { 0x01, 0x101a },
2595 { 0x00, 0xa0ff },
2596 { 0x04, 0xf800 },
2597 { 0x04, 0xf000 },
2598 { 0x1f, 0x0000 },
2599
2600 { 0x1f, 0x0007 },
2601 { 0x1e, 0x0023 },
2602 { 0x16, 0x0000 },
2603 { 0x1f, 0x0000 }
2604 };
2605
2606 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2607}
2608
2857ffb7
FR		 2609static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2610{
350f7596 2611 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2612 { 0x1f, 0x0003 },
2613 { 0x08, 0x441d },
2614 { 0x01, 0x9100 },
2615 { 0x1f, 0x0000 }
2616 };
2617
2618 mdio_write(ioaddr, 0x1f, 0x0000);
2619 mdio_patch(ioaddr, 0x11, 1 << 12);
2620 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2621 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2622
2623 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2624}
2625
5615d9f1
FR		 2626static void rtl_hw_phy_config(struct net_device *dev)
2627{
2628 struct rtl8169_private *tp = netdev_priv(dev);
2629 void __iomem *ioaddr = tp->mmio_addr;
2630
2631 rtl8169_print_mac_version(tp);
2632
2633 switch (tp->mac_version) {
2634 case RTL_GIGA_MAC_VER_01:
2635 break;
2636 case RTL_GIGA_MAC_VER_02:
2637 case RTL_GIGA_MAC_VER_03:
2638 rtl8169s_hw_phy_config(ioaddr);
2639 break;
2640 case RTL_GIGA_MAC_VER_04:
2641 rtl8169sb_hw_phy_config(ioaddr);
2642 break;
2e955856 2643 case RTL_GIGA_MAC_VER_05:
2644 rtl8169scd_hw_phy_config(tp, ioaddr);
2645 break;
8c7006aa 2646 case RTL_GIGA_MAC_VER_06:
2647 rtl8169sce_hw_phy_config(ioaddr);
2648 break;
2857ffb7
FR		 2649 case RTL_GIGA_MAC_VER_07:
2650 case RTL_GIGA_MAC_VER_08:
2651 case RTL_GIGA_MAC_VER_09:
2652 rtl8102e_hw_phy_config(ioaddr);
2653 break;
236b8082
FR		 2654 case RTL_GIGA_MAC_VER_11:
2655 rtl8168bb_hw_phy_config(ioaddr);
2656 break;
2657 case RTL_GIGA_MAC_VER_12:
2658 rtl8168bef_hw_phy_config(ioaddr);
2659 break;
2660 case RTL_GIGA_MAC_VER_17:
2661 rtl8168bef_hw_phy_config(ioaddr);
2662 break;
867763c1 2663 case RTL_GIGA_MAC_VER_18:
ef3386f0 2664 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2665 break;
2666 case RTL_GIGA_MAC_VER_19:
219a1e9d 2667 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2668 break;
7da97ec9 2669 case RTL_GIGA_MAC_VER_20:
219a1e9d 2670 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2671 break;
197ff761
FR		 2672 case RTL_GIGA_MAC_VER_21:
2673 rtl8168c_3_hw_phy_config(ioaddr);
2674 break;
6fb07058
FR		 2675 case RTL_GIGA_MAC_VER_22:
2676 rtl8168c_4_hw_phy_config(ioaddr);
2677 break;
ef3386f0 2678 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2679 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2680 rtl8168cp_2_hw_phy_config(ioaddr);
2681 break;
5b538df9 2682 case RTL_GIGA_MAC_VER_25:
daf9df6d 2683 rtl8168d_1_hw_phy_config(ioaddr);
2684 break;
2685 case RTL_GIGA_MAC_VER_26:
2686 rtl8168d_2_hw_phy_config(ioaddr);
2687 break;
2688 case RTL_GIGA_MAC_VER_27:
2689 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2690 break;
ef3386f0 2691
5615d9f1
FR		 2692 default:
2693 break;
2694 }
2695}
2696
1da177e4
LT		 2697static void rtl8169_phy_timer(unsigned long __opaque)
2698{
2699 struct net_device *dev = (struct net_device *)__opaque;
2700 struct rtl8169_private *tp = netdev_priv(dev);
2701 struct timer_list *timer = &tp->timer;
2702 void __iomem *ioaddr = tp->mmio_addr;
2703 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2704
bcf0bf90 2705 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2706
64e4bfb4 2707 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2708 return;
2709
2710 spin_lock_irq(&tp->lock);
2711
2712 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2713 /*
1da177e4
LT		 2714 * A busy loop could burn quite a few cycles on nowadays CPU.
2715 * Let's delay the execution of the timer for a few ticks.
2716 */
2717 timeout = HZ/10;
2718 goto out_mod_timer;
2719 }
2720
2721 if (tp->link_ok(ioaddr))
2722 goto out_unlock;
2723
bf82c189 2724 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2725
2726 tp->phy_reset_enable(ioaddr);
2727
2728out_mod_timer:
2729 mod_timer(timer, jiffies + timeout);
2730out_unlock:
2731 spin_unlock_irq(&tp->lock);
2732}
2733
2734static inline void rtl8169_delete_timer(struct net_device *dev)
2735{
2736 struct rtl8169_private *tp = netdev_priv(dev);
2737 struct timer_list *timer = &tp->timer;
2738
e179bb7b 2739 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2740 return;
2741
2742 del_timer_sync(timer);
2743}
2744
2745static inline void rtl8169_request_timer(struct net_device *dev)
2746{
2747 struct rtl8169_private *tp = netdev_priv(dev);
2748 struct timer_list *timer = &tp->timer;
2749
e179bb7b 2750 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2751 return;
2752
2efa53f3 2753 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2754}
2755
2756#ifdef CONFIG_NET_POLL_CONTROLLER
2757/*
2758 * Polling 'interrupt' - used by things like netconsole to send skbs
2759 * without having to re-enable interrupts. It's not called while
2760 * the interrupt routine is executing.
2761 */
2762static void rtl8169_netpoll(struct net_device *dev)
2763{
2764 struct rtl8169_private *tp = netdev_priv(dev);
2765 struct pci_dev *pdev = tp->pci_dev;
2766
2767 disable_irq(pdev->irq);
7d12e780 2768 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2769 enable_irq(pdev->irq);
2770}
2771#endif
2772
2773static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2774 void __iomem *ioaddr)
2775{
2776 iounmap(ioaddr);
2777 pci_release_regions(pdev);
87aeec76 2778 pci_clear_mwi(pdev);
1da177e4
LT		 2779 pci_disable_device(pdev);
2780 free_netdev(dev);
2781}
2782
bf793295
FR		 2783static void rtl8169_phy_reset(struct net_device *dev,
2784 struct rtl8169_private *tp)
2785{
2786 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2787 unsigned int i;
bf793295
FR		 2788
2789 tp->phy_reset_enable(ioaddr);
2790 for (i = 0; i < 100; i++) {
2791 if (!tp->phy_reset_pending(ioaddr))
2792 return;
2793 msleep(1);
2794 }
bf82c189 2795 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2796}
2797
4ff96fa6
FR		 2798static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2799{
2800 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2801
5615d9f1 2802 rtl_hw_phy_config(dev);
4ff96fa6 2803
77332894
MS		 2804 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2805 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2806 RTL_W8(0x82, 0x01);
2807 }
4ff96fa6 2808
6dccd16b
FR		 2809 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2810
2811 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2812 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2813
bcf0bf90 2814 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2815 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2816 RTL_W8(0x82, 0x01);
2817 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2818 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2819 }
2820
bf793295
FR		 2821 rtl8169_phy_reset(dev, tp);
2822
901dda2b
FR		 2823 /*
2824 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2825 * only 8101. Don't panic.
2826 */
2827 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2828
bf82c189
JP		 2829 if (RTL_R8(PHYstatus) & TBI_Enable)
2830 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2831}
2832
773d2021
FR		 2833static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2834{
2835 void __iomem *ioaddr = tp->mmio_addr;
2836 u32 high;
2837 u32 low;
2838
2839 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2840 high = addr[4] | (addr[5] << 8);
2841
2842 spin_lock_irq(&tp->lock);
2843
2844 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2845
773d2021 2846 RTL_W32(MAC4, high);
908ba2bf 2847 RTL_R32(MAC4);
2848
78f1cd02 2849 RTL_W32(MAC0, low);
908ba2bf 2850 RTL_R32(MAC0);
2851
773d2021
FR		 2852 RTL_W8(Cfg9346, Cfg9346_Lock);
2853
2854 spin_unlock_irq(&tp->lock);
2855}
2856
2857static int rtl_set_mac_address(struct net_device *dev, void *p)
2858{
2859 struct rtl8169_private *tp = netdev_priv(dev);
2860 struct sockaddr *addr = p;
2861
2862 if (!is_valid_ether_addr(addr->sa_data))
2863 return -EADDRNOTAVAIL;
2864
2865 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2866
2867 rtl_rar_set(tp, dev->dev_addr);
2868
2869 return 0;
2870}
2871
5f787a1a
FR		 2872static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2873{
2874 struct rtl8169_private *tp = netdev_priv(dev);
2875 struct mii_ioctl_data *data = if_mii(ifr);
2876
8b4ab28d
FR		 2877 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2878}
5f787a1a 2879
8b4ab28d
FR		 2880static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2881{
5f787a1a
FR		 2882 switch (cmd) {
2883 case SIOCGMIIPHY:
2884 data->phy_id = 32; /* Internal PHY */
2885 return 0;
2886
2887 case SIOCGMIIREG:
2888 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2889 return 0;
2890
2891 case SIOCSMIIREG:
5f787a1a
FR		 2892 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2893 return 0;
2894 }
2895 return -EOPNOTSUPP;
2896}
2897
8b4ab28d
FR		 2898static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2899{
2900 return -EOPNOTSUPP;
2901}
2902
0e485150
FR		 2903static const struct rtl_cfg_info {
2904 void (*hw_start)(struct net_device *);
2905 unsigned int region;
2906 unsigned int align;
2907 u16 intr_event;
2908 u16 napi_event;
ccdffb9a 2909 unsigned features;
f21b75e9 2910 u8 default_ver;
0e485150
FR		 2911} rtl_cfg_infos [] = {
2912 [RTL_CFG_0] = {
2913 .hw_start = rtl_hw_start_8169,
2914 .region = 1,
e9f63f30 2915 .align = 0,
0e485150
FR		 2916 .intr_event = SYSErr | LinkChg | RxOverflow |
2917 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2918 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2919 .features = RTL_FEATURE_GMII,
2920 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2921 },
2922 [RTL_CFG_1] = {
2923 .hw_start = rtl_hw_start_8168,
2924 .region = 2,
2925 .align = 8,
2926 .intr_event = SYSErr | LinkChg | RxOverflow |
2927 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2928 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2929 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2930 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2931 },
2932 [RTL_CFG_2] = {
2933 .hw_start = rtl_hw_start_8101,
2934 .region = 2,
2935 .align = 8,
2936 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2937 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2938 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2939 .features = RTL_FEATURE_MSI,
2940 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2941 }
2942};
2943
fbac58fc
FR		 2944/* Cfg9346_Unlock assumed. */
2945static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2946 const struct rtl_cfg_info *cfg)
2947{
2948 unsigned msi = 0;
2949 u8 cfg2;
2950
2951 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2952 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2953 if (pci_enable_msi(pdev)) {
2954 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2955 } else {
2956 cfg2 |= MSIEnable;
2957 msi = RTL_FEATURE_MSI;
2958 }
2959 }
2960 RTL_W8(Config2, cfg2);
2961 return msi;
2962}
2963
2964static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2965{
2966 if (tp->features & RTL_FEATURE_MSI) {
2967 pci_disable_msi(pdev);
2968 tp->features &= ~RTL_FEATURE_MSI;
2969 }
2970}
2971
8b4ab28d
FR		 2972static const struct net_device_ops rtl8169_netdev_ops = {
2973 .ndo_open = rtl8169_open,
2974 .ndo_stop = rtl8169_close,
2975 .ndo_get_stats = rtl8169_get_stats,
00829823 2976 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2977 .ndo_tx_timeout = rtl8169_tx_timeout,
2978 .ndo_validate_addr = eth_validate_addr,
2979 .ndo_change_mtu = rtl8169_change_mtu,
2980 .ndo_set_mac_address = rtl_set_mac_address,
2981 .ndo_do_ioctl = rtl8169_ioctl,
2982 .ndo_set_multicast_list = rtl_set_rx_mode,
2983#ifdef CONFIG_R8169_VLAN
2984 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2985#endif
2986#ifdef CONFIG_NET_POLL_CONTROLLER
2987 .ndo_poll_controller = rtl8169_netpoll,
2988#endif
2989
2990};
2991
1da177e4 2992static int __devinit
4ff96fa6 2993rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2994{
0e485150
FR		 2995 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2996 const unsigned int region = cfg->region;
1da177e4 2997 struct rtl8169_private *tp;
ccdffb9a 2998 struct mii_if_info *mii;
4ff96fa6
FR		 2999 struct net_device *dev;
3000 void __iomem *ioaddr;
07d3f51f
FR		 3001 unsigned int i;
3002 int rc;
1da177e4 3003
4ff96fa6
FR		 3004 if (netif_msg_drv(&debug)) {
3005 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3006 MODULENAME, RTL8169_VERSION);
3007 }
1da177e4 3008
1da177e4 3009 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3010 if (!dev) {
b57b7e5a 3011 if (netif_msg_drv(&debug))
9b91cf9d 3012 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3013 rc = -ENOMEM;
3014 goto out;
1da177e4
LT		 3015 }
3016
1da177e4 3017 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3018 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3019 tp = netdev_priv(dev);
c4028958 3020 tp->dev = dev;
21e197f2 3021 tp->pci_dev = pdev;
b57b7e5a 3022 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3023
ccdffb9a
FR		 3024 mii = &tp->mii;
3025 mii->dev = dev;
3026 mii->mdio_read = rtl_mdio_read;
3027 mii->mdio_write = rtl_mdio_write;
3028 mii->phy_id_mask = 0x1f;
3029 mii->reg_num_mask = 0x1f;
3030 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3031
1da177e4
LT		 3032 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3033 rc = pci_enable_device(pdev);
b57b7e5a 3034 if (rc < 0) {
bf82c189 3035 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3036 goto err_out_free_dev_1;
1da177e4
LT		 3037 }
3038
87aeec76 3039 if (pci_set_mwi(pdev) < 0)
3040 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3041
1da177e4 3042 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3043 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3044 netif_err(tp, probe, dev,
3045 "region #%d not an MMIO resource, aborting\n",
3046 region);
1da177e4 3047 rc = -ENODEV;
87aeec76 3048 goto err_out_mwi_2;
1da177e4 3049 }
4ff96fa6 3050
1da177e4 3051 /* check for weird/broken PCI region reporting */
bcf0bf90 3052 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3053 netif_err(tp, probe, dev,
3054 "Invalid PCI region size(s), aborting\n");
1da177e4 3055 rc = -ENODEV;
87aeec76 3056 goto err_out_mwi_2;
1da177e4
LT		 3057 }
3058
3059 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3060 if (rc < 0) {
bf82c189 3061 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3062 goto err_out_mwi_2;
1da177e4
LT		 3063 }
3064
3065 tp->cp_cmd = PCIMulRW | RxChkSum;
3066
3067 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3068 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3069 tp->cp_cmd |= PCIDAC;
3070 dev->features |= NETIF_F_HIGHDMA;
3071 } else {
284901a9 3072 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3073 if (rc < 0) {
bf82c189 3074 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3075 goto err_out_free_res_3;
1da177e4
LT		 3076 }
3077 }
3078
1da177e4 3079 /* ioremap MMIO region */
bcf0bf90 3080 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3081 if (!ioaddr) {
bf82c189 3082 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3083 rc = -EIO;
87aeec76 3084 goto err_out_free_res_3;
1da177e4
LT		 3085 }
3086
4300e8c7
DM		 3087 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3088 if (!tp->pcie_cap)
3089 netif_info(tp, probe, dev, "no PCI Express capability\n");
3090
d78ad8cb 3091 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3092
3093 /* Soft reset the chip. */
3094 RTL_W8(ChipCmd, CmdReset);
3095
3096 /* Check that the chip has finished the reset. */
07d3f51f 3097 for (i = 0; i < 100; i++) {
1da177e4
LT		 3098 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3099 break;
b518fa8e 3100 msleep_interruptible(1);
1da177e4
LT		 3101 }
3102
d78ad8cb
KW		 3103 RTL_W16(IntrStatus, 0xffff);
3104
ca52efd5 3105 pci_set_master(pdev);
3106
1da177e4
LT		 3107 /* Identify chip attached to board */
3108 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3109
f21b75e9
JD		 3110 /* Use appropriate default if unknown */
3111 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3112 netif_notice(tp, probe, dev,
3113 "unknown MAC, using family default\n");
f21b75e9
JD		 3114 tp->mac_version = cfg->default_ver;
3115 }
3116
1da177e4 3117 rtl8169_print_mac_version(tp);
1da177e4 3118
cee60c37 3119 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3120 if (tp->mac_version == rtl_chip_info[i].mac_version)
3121 break;
3122 }
cee60c37 3123 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3124 dev_err(&pdev->dev,
3125 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3126 goto err_out_msi_4;
1da177e4
LT		 3127 }
3128 tp->chipset = i;
3129
5d06a99f
FR		 3130 RTL_W8(Cfg9346, Cfg9346_Unlock);
3131 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3132 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3133 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3134 tp->features |= RTL_FEATURE_WOL;
3135 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3136 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3137 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3138 RTL_W8(Cfg9346, Cfg9346_Lock);
3139
66ec5d4f
FR		 3140 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3141 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3142 tp->set_speed = rtl8169_set_speed_tbi;
3143 tp->get_settings = rtl8169_gset_tbi;
3144 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3145 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3146 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3147 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3148
64e4bfb4 3149 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3150 } else {
3151 tp->set_speed = rtl8169_set_speed_xmii;
3152 tp->get_settings = rtl8169_gset_xmii;
3153 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3154 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3155 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3156 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3157 }
3158
df58ef51
FR		 3159 spin_lock_init(&tp->lock);
3160
738e1e69
PV		 3161 tp->mmio_addr = ioaddr;
3162
7bf6bf48 3163 /* Get MAC address */
1da177e4
LT		 3164 for (i = 0; i < MAC_ADDR_LEN; i++)
3165 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3166 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3167
1da177e4 3168 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3169 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3170 dev->irq = pdev->irq;
3171 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3172
bea3348e 3173 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3174
3175#ifdef CONFIG_R8169_VLAN
3176 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3177#endif
3178
3179 tp->intr_mask = 0xffff;
0e485150
FR		 3180 tp->align = cfg->align;
3181 tp->hw_start = cfg->hw_start;
3182 tp->intr_event = cfg->intr_event;
3183 tp->napi_event = cfg->napi_event;
1da177e4 3184
2efa53f3
FR		 3185 init_timer(&tp->timer);
3186 tp->timer.data = (unsigned long) dev;
3187 tp->timer.function = rtl8169_phy_timer;
3188
1da177e4 3189 rc = register_netdev(dev);
4ff96fa6 3190 if (rc < 0)
87aeec76 3191 goto err_out_msi_4;
1da177e4
LT		 3192
3193 pci_set_drvdata(pdev, dev);
3194
bf82c189
JP		 3195 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3196 rtl_chip_info[tp->chipset].name,
3197 dev->base_addr, dev->dev_addr,
3198 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3199
4ff96fa6 3200 rtl8169_init_phy(dev, tp);
05af2142
SW		 3201
3202 /*
3203 * Pretend we are using VLANs; This bypasses a nasty bug where
3204 * Interrupts stop flowing on high load on 8110SCd controllers.
3205 */
3206 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3207 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3208
8b76ab39 3209 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3210
e1759441
RW		 3211 if (pci_dev_run_wake(pdev)) {
3212 pm_runtime_set_active(&pdev->dev);
3213 pm_runtime_enable(&pdev->dev);
3214 }
3215 pm_runtime_idle(&pdev->dev);
3216
4ff96fa6
FR		 3217out:
3218 return rc;
1da177e4 3219
87aeec76 3220err_out_msi_4:
fbac58fc 3221 rtl_disable_msi(pdev, tp);
4ff96fa6 3222 iounmap(ioaddr);
87aeec76 3223err_out_free_res_3:
4ff96fa6 3224 pci_release_regions(pdev);
87aeec76 3225err_out_mwi_2:
4ff96fa6 3226 pci_clear_mwi(pdev);
4ff96fa6
FR		 3227 pci_disable_device(pdev);
3228err_out_free_dev_1:
3229 free_netdev(dev);
3230 goto out;
1da177e4
LT		 3231}
3232
07d3f51f 3233static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3234{
3235 struct net_device *dev = pci_get_drvdata(pdev);
3236 struct rtl8169_private *tp = netdev_priv(dev);
3237
e1759441
RW		 3238 pm_runtime_get_sync(&pdev->dev);
3239
eb2a021c
FR		 3240 flush_scheduled_work();
3241
1da177e4 3242 unregister_netdev(dev);
cc098dc7 3243
e1759441
RW		 3244 if (pci_dev_run_wake(pdev)) {
3245 pm_runtime_disable(&pdev->dev);
3246 pm_runtime_set_suspended(&pdev->dev);
3247 }
3248 pm_runtime_put_noidle(&pdev->dev);
3249
cc098dc7
IV		 3250 /* restore original MAC address */
3251 rtl_rar_set(tp, dev->perm_addr);
3252
fbac58fc 3253 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3254 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3255 pci_set_drvdata(pdev, NULL);
3256}
3257
1da177e4 3258static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
c0cd884a 3259 unsigned int mtu)
1da177e4 3260{
c0cd884a
NH		 3261 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3262
3263 if (max_frame != 16383)
93f4d91d
NH		 3264 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3265 "NIC may lead to frame reception errors!\n");
1da177e4 3266
8812304c 3267 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
1da177e4
LT		 3268}
3269
3270static int rtl8169_open(struct net_device *dev)
3271{
3272 struct rtl8169_private *tp = netdev_priv(dev);
3273 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3274 int retval = -ENOMEM;
1da177e4 3275
e1759441 3276 pm_runtime_get_sync(&pdev->dev);
1da177e4 3277
c0cd884a
NH		 3278 /*
3279 * Note that we use a magic value here, its wierd I know
3280 * its done because, some subset of rtl8169 hardware suffers from
3281 * a problem in which frames received that are longer than
3282 * the size set in RxMaxSize register return garbage sizes
3283 * when received. To avoid this we need to turn off filtering,
3284 * which is done by setting a value of 16383 in the RxMaxSize register
3285 * and allocating 16k frames to handle the largest possible rx value
3286 * thats what the magic math below does.
3287 */
3288 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
1da177e4
LT		 3289
3290 /*
3291 * Rx and Tx desscriptors needs 256 bytes alignment.
3292 * pci_alloc_consistent provides more.
3293 */
3294 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3295 &tp->TxPhyAddr);
3296 if (!tp->TxDescArray)
e1759441 3297 goto err_pm_runtime_put;
1da177e4
LT		 3298
3299 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3300 &tp->RxPhyAddr);
3301 if (!tp->RxDescArray)
99f252b0 3302 goto err_free_tx_0;
1da177e4
LT		 3303
3304 retval = rtl8169_init_ring(dev);
3305 if (retval < 0)
99f252b0 3306 goto err_free_rx_1;
1da177e4 3307
c4028958 3308 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3309
99f252b0
FR		 3310 smp_mb();
3311
fbac58fc
FR		 3312 retval = request_irq(dev->irq, rtl8169_interrupt,
3313 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3314 dev->name, dev);
3315 if (retval < 0)
3316 goto err_release_ring_2;
3317
bea3348e 3318 napi_enable(&tp->napi);
bea3348e 3319
07ce4064 3320 rtl_hw_start(dev);
1da177e4
LT		 3321
3322 rtl8169_request_timer(dev);
3323
e1759441
RW		 3324 tp->saved_wolopts = 0;
3325 pm_runtime_put_noidle(&pdev->dev);
3326
1da177e4
LT		 3327 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3328out:
3329 return retval;
3330
99f252b0
FR		 3331err_release_ring_2:
3332 rtl8169_rx_clear(tp);
3333err_free_rx_1:
1da177e4
LT		 3334 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3335 tp->RxPhyAddr);
e1759441 3336 tp->RxDescArray = NULL;
99f252b0 3337err_free_tx_0:
1da177e4
LT		 3338 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3339 tp->TxPhyAddr);
e1759441
RW		 3340 tp->TxDescArray = NULL;
3341err_pm_runtime_put:
3342 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3343 goto out;
3344}
3345
3346static void rtl8169_hw_reset(void __iomem *ioaddr)
3347{
3348 /* Disable interrupts */
3349 rtl8169_irq_mask_and_ack(ioaddr);
3350
3351 /* Reset the chipset */
3352 RTL_W8(ChipCmd, CmdReset);
3353
3354 /* PCI commit */
3355 RTL_R8(ChipCmd);
3356}
3357
7f796d83 3358static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3359{
3360 void __iomem *ioaddr = tp->mmio_addr;
3361 u32 cfg = rtl8169_rx_config;
3362
3363 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3364 RTL_W32(RxConfig, cfg);
3365
3366 /* Set DMA burst size and Interframe Gap Time */
3367 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3368 (InterFrameGap << TxInterFrameGapShift));
3369}
3370
07ce4064 3371static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3372{
3373 struct rtl8169_private *tp = netdev_priv(dev);
3374 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3375 unsigned int i;
1da177e4
LT		 3376
3377 /* Soft reset the chip. */
3378 RTL_W8(ChipCmd, CmdReset);
3379
3380 /* Check that the chip has finished the reset. */
07d3f51f 3381 for (i = 0; i < 100; i++) {
1da177e4
LT		 3382 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3383 break;
b518fa8e 3384 msleep_interruptible(1);
1da177e4
LT		 3385 }
3386
07ce4064
FR		 3387 tp->hw_start(dev);
3388
07ce4064
FR		 3389 netif_start_queue(dev);
3390}
3391
3392
7f796d83
FR		 3393static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3394 void __iomem *ioaddr)
3395{
3396 /*
3397 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3398 * register to be written before TxDescAddrLow to work.
3399 * Switching from MMIO to I/O access fixes the issue as well.
3400 */
3401 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3402 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3403 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3404 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3405}
3406
3407static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3408{
3409 u16 cmd;
3410
3411 cmd = RTL_R16(CPlusCmd);
3412 RTL_W16(CPlusCmd, cmd);
3413 return cmd;
3414}
3415
fdd7b4c3 3416static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3417{
3418 /* Low hurts. Let's disable the filtering. */
207d6e87 3419 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3420}
3421
6dccd16b
FR		 3422static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3423{
350f7596 3424 static const struct {
6dccd16b
FR		 3425 u32 mac_version;
3426 u32 clk;
3427 u32 val;
3428 } cfg2_info [] = {
3429 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3430 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3431 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3432 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3433 }, *p = cfg2_info;
3434 unsigned int i;
3435 u32 clk;
3436
3437 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3438 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3439 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3440 RTL_W32(0x7c, p->val);
3441 break;
3442 }
3443 }
3444}
3445
07ce4064
FR		 3446static void rtl_hw_start_8169(struct net_device *dev)
3447{
3448 struct rtl8169_private *tp = netdev_priv(dev);
3449 void __iomem *ioaddr = tp->mmio_addr;
3450 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3451
9cb427b6
FR		 3452 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3453 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3454 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3455 }
3456
1da177e4 3457 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3458 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3459 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3460 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3461 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3462 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3463
1da177e4
LT		 3464 RTL_W8(EarlyTxThres, EarlyTxThld);
3465
fdd7b4c3 3466 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3467
c946b304
FR		 3468 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3469 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3470 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3471 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3472 rtl_set_rx_tx_config_registers(tp);
1da177e4 3473
7f796d83 3474 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3475
bcf0bf90
FR		 3476 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3477 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3478 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3479 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3480 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3481 }
3482
bcf0bf90
FR		 3483 RTL_W16(CPlusCmd, tp->cp_cmd);
3484
6dccd16b
FR		 3485 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3486
1da177e4
LT		 3487 /*
3488 * Undocumented corner. Supposedly:
3489 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3490 */
3491 RTL_W16(IntrMitigate, 0x0000);
3492
7f796d83 3493 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3494
c946b304
FR		 3495 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3496 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3497 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3498 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3499 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3500 rtl_set_rx_tx_config_registers(tp);
3501 }
3502
1da177e4 3503 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3504
3505 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3506 RTL_R8(IntrMask);
1da177e4
LT		 3507
3508 RTL_W32(RxMissed, 0);
3509
07ce4064 3510 rtl_set_rx_mode(dev);
1da177e4
LT		 3511
3512 /* no early-rx interrupts */
3513 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3514
3515 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3516 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3517}
1da177e4 3518
9c14ceaf 3519static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3520{
9c14ceaf
FR		 3521 struct net_device *dev = pci_get_drvdata(pdev);
3522 struct rtl8169_private *tp = netdev_priv(dev);
3523 int cap = tp->pcie_cap;
3524
3525 if (cap) {
3526 u16 ctl;
458a9f61 3527
9c14ceaf
FR		 3528 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3529 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3530 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3531 }
458a9f61
FR		 3532}
3533
dacf8154
FR		 3534static void rtl_csi_access_enable(void __iomem *ioaddr)
3535{
3536 u32 csi;
3537
3538 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3539 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3540}
3541
3542struct ephy_info {
3543 unsigned int offset;
3544 u16 mask;
3545 u16 bits;
3546};
3547
350f7596 3548static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3549{
3550 u16 w;
3551
3552 while (len-- > 0) {
3553 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3554 rtl_ephy_write(ioaddr, e->offset, w);
3555 e++;
3556 }
3557}
3558
b726e493
FR		 3559static void rtl_disable_clock_request(struct pci_dev *pdev)
3560{
3561 struct net_device *dev = pci_get_drvdata(pdev);
3562 struct rtl8169_private *tp = netdev_priv(dev);
3563 int cap = tp->pcie_cap;
3564
3565 if (cap) {
3566 u16 ctl;
3567
3568 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3569 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3570 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3571 }
3572}
3573
3574#define R8168_CPCMD_QUIRK_MASK (\
3575 EnableBist | \
3576 Mac_dbgo_oe | \
3577 Force_half_dup | \
3578 Force_rxflow_en | \
3579 Force_txflow_en | \
3580 Cxpl_dbg_sel | \
3581 ASF | \
3582 PktCntrDisable | \
3583 Mac_dbgo_sel)
3584
219a1e9d
FR		 3585static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3586{
b726e493
FR		 3587 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3588
3589 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3590
2e68ae44
FR		 3591 rtl_tx_performance_tweak(pdev,
3592 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3593}
3594
3595static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3596{
3597 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3598
3599 RTL_W8(EarlyTxThres, EarlyTxThld);
3600
3601 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3602}
3603
3604static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3605{
b726e493
FR		 3606 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3607
3608 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3609
219a1e9d 3610 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3611
3612 rtl_disable_clock_request(pdev);
3613
3614 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3615}
3616
ef3386f0 3617static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3618{
350f7596 3619 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3620 { 0x01, 0, 0x0001 },
3621 { 0x02, 0x0800, 0x1000 },
3622 { 0x03, 0, 0x0042 },
3623 { 0x06, 0x0080, 0x0000 },
3624 { 0x07, 0, 0x2000 }
3625 };
3626
3627 rtl_csi_access_enable(ioaddr);
3628
3629 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3630
219a1e9d
FR		 3631 __rtl_hw_start_8168cp(ioaddr, pdev);
3632}
3633
ef3386f0
FR		 3634static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3635{
3636 rtl_csi_access_enable(ioaddr);
3637
3638 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3639
3640 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3641
3642 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3643}
3644
7f3e3d3a
FR		 3645static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3646{
3647 rtl_csi_access_enable(ioaddr);
3648
3649 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3650
3651 /* Magic. */
3652 RTL_W8(DBG_REG, 0x20);
3653
3654 RTL_W8(EarlyTxThres, EarlyTxThld);
3655
3656 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3657
3658 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3659}
3660
219a1e9d
FR		 3661static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3662{
350f7596 3663 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3664 { 0x02, 0x0800, 0x1000 },
3665 { 0x03, 0, 0x0002 },
3666 { 0x06, 0x0080, 0x0000 }
3667 };
3668
3669 rtl_csi_access_enable(ioaddr);
3670
3671 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3672
3673 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3674
219a1e9d
FR		 3675 __rtl_hw_start_8168cp(ioaddr, pdev);
3676}
3677
3678static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3679{
350f7596 3680 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3681 { 0x01, 0, 0x0001 },
3682 { 0x03, 0x0400, 0x0220 }
3683 };
3684
3685 rtl_csi_access_enable(ioaddr);
3686
3687 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3688
219a1e9d
FR		 3689 __rtl_hw_start_8168cp(ioaddr, pdev);
3690}
3691
197ff761
FR		 3692static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3693{
3694 rtl_hw_start_8168c_2(ioaddr, pdev);
3695}
3696
6fb07058
FR		 3697static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3698{
3699 rtl_csi_access_enable(ioaddr);
3700
3701 __rtl_hw_start_8168cp(ioaddr, pdev);
3702}
3703
5b538df9
FR		 3704static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3705{
3706 rtl_csi_access_enable(ioaddr);
3707
3708 rtl_disable_clock_request(pdev);
3709
3710 RTL_W8(EarlyTxThres, EarlyTxThld);
3711
3712 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3713
3714 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3715}
3716
07ce4064
FR		 3717static void rtl_hw_start_8168(struct net_device *dev)
3718{
2dd99530
FR		 3719 struct rtl8169_private *tp = netdev_priv(dev);
3720 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3721 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3722
3723 RTL_W8(Cfg9346, Cfg9346_Unlock);
3724
3725 RTL_W8(EarlyTxThres, EarlyTxThld);
3726
fdd7b4c3 3727 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3728
0e485150 3729 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3730
3731 RTL_W16(CPlusCmd, tp->cp_cmd);
3732
0e485150 3733 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3734
0e485150
FR		 3735 /* Work around for RxFIFO overflow. */
3736 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3737 tp->intr_event |= RxFIFOOver | PCSTimeout;
3738 tp->intr_event &= ~RxOverflow;
3739 }
3740
3741 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3742
b8363901
FR		 3743 rtl_set_rx_mode(dev);
3744
3745 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3746 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3747
3748 RTL_R8(IntrMask);
3749
219a1e9d
FR		 3750 switch (tp->mac_version) {
3751 case RTL_GIGA_MAC_VER_11:
3752 rtl_hw_start_8168bb(ioaddr, pdev);
3753 break;
3754
3755 case RTL_GIGA_MAC_VER_12:
3756 case RTL_GIGA_MAC_VER_17:
3757 rtl_hw_start_8168bef(ioaddr, pdev);
3758 break;
3759
3760 case RTL_GIGA_MAC_VER_18:
ef3386f0 3761 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3762 break;
3763
3764 case RTL_GIGA_MAC_VER_19:
3765 rtl_hw_start_8168c_1(ioaddr, pdev);
3766 break;
3767
3768 case RTL_GIGA_MAC_VER_20:
3769 rtl_hw_start_8168c_2(ioaddr, pdev);
3770 break;
3771
197ff761
FR		 3772 case RTL_GIGA_MAC_VER_21:
3773 rtl_hw_start_8168c_3(ioaddr, pdev);
3774 break;
3775
6fb07058
FR		 3776 case RTL_GIGA_MAC_VER_22:
3777 rtl_hw_start_8168c_4(ioaddr, pdev);
3778 break;
3779
ef3386f0
FR		 3780 case RTL_GIGA_MAC_VER_23:
3781 rtl_hw_start_8168cp_2(ioaddr, pdev);
3782 break;
3783
7f3e3d3a
FR		 3784 case RTL_GIGA_MAC_VER_24:
3785 rtl_hw_start_8168cp_3(ioaddr, pdev);
3786 break;
3787
5b538df9 3788 case RTL_GIGA_MAC_VER_25:
daf9df6d 3789 case RTL_GIGA_MAC_VER_26:
3790 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3791 rtl_hw_start_8168d(ioaddr, pdev);
3792 break;
3793
219a1e9d
FR		 3794 default:
3795 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3796 dev->name, tp->mac_version);
3797 break;
3798 }
2dd99530 3799
0e485150
FR		 3800 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3801
b8363901
FR		 3802 RTL_W8(Cfg9346, Cfg9346_Lock);
3803
2dd99530 3804 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3805
0e485150 3806 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3807}
1da177e4 3808
2857ffb7
FR		 3809#define R810X_CPCMD_QUIRK_MASK (\
3810 EnableBist | \
3811 Mac_dbgo_oe | \
3812 Force_half_dup | \
5edcc537 3813 Force_rxflow_en | \
2857ffb7
FR		 3814 Force_txflow_en | \
3815 Cxpl_dbg_sel | \
3816 ASF | \
3817 PktCntrDisable | \
3818 PCIDAC | \
3819 PCIMulRW)
3820
3821static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3822{
350f7596 3823 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3824 { 0x01, 0, 0x6e65 },
3825 { 0x02, 0, 0x091f },
3826 { 0x03, 0, 0xc2f9 },
3827 { 0x06, 0, 0xafb5 },
3828 { 0x07, 0, 0x0e00 },
3829 { 0x19, 0, 0xec80 },
3830 { 0x01, 0, 0x2e65 },
3831 { 0x01, 0, 0x6e65 }
3832 };
3833 u8 cfg1;
3834
3835 rtl_csi_access_enable(ioaddr);
3836
3837 RTL_W8(DBG_REG, FIX_NAK_1);
3838
3839 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3840
3841 RTL_W8(Config1,
3842 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3843 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3844
3845 cfg1 = RTL_R8(Config1);
3846 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3847 RTL_W8(Config1, cfg1 & ~LEDS0);
3848
3849 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3850
3851 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3852}
3853
3854static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3855{
3856 rtl_csi_access_enable(ioaddr);
3857
3858 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3859
3860 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3861 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3862
3863 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3864}
3865
3866static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3867{
3868 rtl_hw_start_8102e_2(ioaddr, pdev);
3869
3870 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3871}
3872
07ce4064
FR		 3873static void rtl_hw_start_8101(struct net_device *dev)
3874{
cdf1a608
FR		 3875 struct rtl8169_private *tp = netdev_priv(dev);
3876 void __iomem *ioaddr = tp->mmio_addr;
3877 struct pci_dev *pdev = tp->pci_dev;
3878
e3cf0cc0
FR		 3879 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3880 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3881 int cap = tp->pcie_cap;
3882
3883 if (cap) {
3884 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3885 PCI_EXP_DEVCTL_NOSNOOP_EN);
3886 }
cdf1a608
FR		 3887 }
3888
2857ffb7
FR		 3889 switch (tp->mac_version) {
3890 case RTL_GIGA_MAC_VER_07:
3891 rtl_hw_start_8102e_1(ioaddr, pdev);
3892 break;
3893
3894 case RTL_GIGA_MAC_VER_08:
3895 rtl_hw_start_8102e_3(ioaddr, pdev);
3896 break;
3897
3898 case RTL_GIGA_MAC_VER_09:
3899 rtl_hw_start_8102e_2(ioaddr, pdev);
3900 break;
cdf1a608
FR		 3901 }
3902
3903 RTL_W8(Cfg9346, Cfg9346_Unlock);
3904
3905 RTL_W8(EarlyTxThres, EarlyTxThld);
3906
fdd7b4c3 3907 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3908
3909 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3910
3911 RTL_W16(CPlusCmd, tp->cp_cmd);
3912
3913 RTL_W16(IntrMitigate, 0x0000);
3914
3915 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3916
3917 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3918 rtl_set_rx_tx_config_registers(tp);
3919
3920 RTL_W8(Cfg9346, Cfg9346_Lock);
3921
3922 RTL_R8(IntrMask);
3923
cdf1a608
FR		 3924 rtl_set_rx_mode(dev);
3925
0e485150
FR		 3926 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3927
cdf1a608 3928 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3929
0e485150 3930 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3931}
3932
3933static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3934{
3935 struct rtl8169_private *tp = netdev_priv(dev);
3936 int ret = 0;
3937
3938 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3939 return -EINVAL;
3940
3941 dev->mtu = new_mtu;
3942
3943 if (!netif_running(dev))
3944 goto out;
3945
3946 rtl8169_down(dev);
3947
c0cd884a 3948 rtl8169_set_rxbufsize(tp, dev->mtu);
1da177e4
LT		 3949
3950 ret = rtl8169_init_ring(dev);
3951 if (ret < 0)
3952 goto out;
3953
bea3348e 3954 napi_enable(&tp->napi);
1da177e4 3955
07ce4064 3956 rtl_hw_start(dev);
1da177e4
LT		 3957
3958 rtl8169_request_timer(dev);
3959
3960out:
3961 return ret;
3962}
3963
3964static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3965{
95e0918d 3966 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3967 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3968}
3969
3970static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3971 struct sk_buff **sk_buff, struct RxDesc *desc)
3972{
3973 struct pci_dev *pdev = tp->pci_dev;
3974
3975 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3976 PCI_DMA_FROMDEVICE);
3977 dev_kfree_skb(*sk_buff);
3978 *sk_buff = NULL;
3979 rtl8169_make_unusable_by_asic(desc);
3980}
3981
3982static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3983{
3984 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3985
3986 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3987}
3988
3989static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3990 u32 rx_buf_sz)
3991{
3992 desc->addr = cpu_to_le64(mapping);
3993 wmb();
3994 rtl8169_mark_to_asic(desc, rx_buf_sz);
3995}
3996
15d31758
SH		 3997static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3998 struct net_device *dev,
3999 struct RxDesc *desc, int rx_buf_sz,
4000 unsigned int align)
1da177e4
LT		 4001{
4002 struct sk_buff *skb;
4003 dma_addr_t mapping;
e9f63f30 4004 unsigned int pad;
1da177e4 4005
e9f63f30
FR		 4006 pad = align ? align : NET_IP_ALIGN;
4007
4008 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 4009 if (!skb)
4010 goto err_out;
4011
e9f63f30 4012 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 4013
689be439 4014 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 4015 PCI_DMA_FROMDEVICE);
4016
4017 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 4018out:
15d31758 4019 return skb;
1da177e4
LT		 4020
4021err_out:
1da177e4
LT		 4022 rtl8169_make_unusable_by_asic(desc);
4023 goto out;
4024}
4025
4026static void rtl8169_rx_clear(struct rtl8169_private *tp)
4027{
07d3f51f 4028 unsigned int i;
1da177e4
LT		 4029
4030 for (i = 0; i < NUM_RX_DESC; i++) {
4031 if (tp->Rx_skbuff[i]) {
4032 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4033 tp->RxDescArray + i);
4034 }
4035 }
4036}
4037
4038static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4039 u32 start, u32 end)
4040{
4041 u32 cur;
5b0384f4 4042
4ae47c2d 4043 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 4044 struct sk_buff *skb;
4045 unsigned int i = cur % NUM_RX_DESC;
1da177e4 4046
4ae47c2d
FR		 4047 WARN_ON((s32)(end - cur) < 0);
4048
1da177e4
LT		 4049 if (tp->Rx_skbuff[i])
4050 continue;
bcf0bf90 4051
15d31758
SH		 4052 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4053 tp->RxDescArray + i,
4054 tp->rx_buf_sz, tp->align);
4055 if (!skb)
1da177e4 4056 break;
15d31758
SH		 4057
4058 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 4059 }
4060 return cur - start;
4061}
4062
4063static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4064{
4065 desc->opts1 |= cpu_to_le32(RingEnd);
4066}
4067
4068static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4069{
4070 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4071}
4072
4073static int rtl8169_init_ring(struct net_device *dev)
4074{
4075 struct rtl8169_private *tp = netdev_priv(dev);
4076
4077 rtl8169_init_ring_indexes(tp);
4078
4079 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4080 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4081
4082 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4083 goto err_out;
4084
4085 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4086
4087 return 0;
4088
4089err_out:
4090 rtl8169_rx_clear(tp);
4091 return -ENOMEM;
4092}
4093
4094static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4095 struct TxDesc *desc)
4096{
4097 unsigned int len = tx_skb->len;
4098
4099 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4100 desc->opts1 = 0x00;
4101 desc->opts2 = 0x00;
4102 desc->addr = 0x00;
4103 tx_skb->len = 0;
4104}
4105
4106static void rtl8169_tx_clear(struct rtl8169_private *tp)
4107{
4108 unsigned int i;
4109
4110 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4111 unsigned int entry = i % NUM_TX_DESC;
4112 struct ring_info *tx_skb = tp->tx_skb + entry;
4113 unsigned int len = tx_skb->len;
4114
4115 if (len) {
4116 struct sk_buff *skb = tx_skb->skb;
4117
4118 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4119 tp->TxDescArray + entry);
4120 if (skb) {
4121 dev_kfree_skb(skb);
4122 tx_skb->skb = NULL;
4123 }
cebf8cc7 4124 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4125 }
4126 }
4127 tp->cur_tx = tp->dirty_tx = 0;
4128}
4129
c4028958 4130static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4131{
4132 struct rtl8169_private *tp = netdev_priv(dev);
4133
c4028958 4134 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4135 schedule_delayed_work(&tp->task, 4);
4136}
4137
4138static void rtl8169_wait_for_quiescence(struct net_device *dev)
4139{
4140 struct rtl8169_private *tp = netdev_priv(dev);
4141 void __iomem *ioaddr = tp->mmio_addr;
4142
4143 synchronize_irq(dev->irq);
4144
4145 /* Wait for any pending NAPI task to complete */
bea3348e 4146 napi_disable(&tp->napi);
1da177e4
LT		 4147
4148 rtl8169_irq_mask_and_ack(ioaddr);
4149
d1d08d12
DM		 4150 tp->intr_mask = 0xffff;
4151 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4152 napi_enable(&tp->napi);
1da177e4
LT		 4153}
4154
c4028958 4155static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4156{
c4028958
DH		 4157 struct rtl8169_private *tp =
4158 container_of(work, struct rtl8169_private, task.work);
4159 struct net_device *dev = tp->dev;
1da177e4
LT		 4160 int ret;
4161
eb2a021c
FR		 4162 rtnl_lock();
4163
4164 if (!netif_running(dev))
4165 goto out_unlock;
4166
4167 rtl8169_wait_for_quiescence(dev);
4168 rtl8169_close(dev);
1da177e4
LT		 4169
4170 ret = rtl8169_open(dev);
4171 if (unlikely(ret < 0)) {
bf82c189
JP		 4172 if (net_ratelimit())
4173 netif_err(tp, drv, dev,
4174 "reinit failure (status = %d). Rescheduling\n",
4175 ret);
1da177e4
LT		 4176 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4177 }
eb2a021c
FR		 4178
4179out_unlock:
4180 rtnl_unlock();
1da177e4
LT		 4181}
4182
c4028958 4183static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4184{
c4028958
DH		 4185 struct rtl8169_private *tp =
4186 container_of(work, struct rtl8169_private, task.work);
4187 struct net_device *dev = tp->dev;
1da177e4 4188
eb2a021c
FR		 4189 rtnl_lock();
4190
1da177e4 4191 if (!netif_running(dev))
eb2a021c 4192 goto out_unlock;
1da177e4
LT		 4193
4194 rtl8169_wait_for_quiescence(dev);
4195
bea3348e 4196 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4197 rtl8169_tx_clear(tp);
4198
4199 if (tp->dirty_rx == tp->cur_rx) {
4200 rtl8169_init_ring_indexes(tp);
07ce4064 4201 rtl_hw_start(dev);
1da177e4 4202 netif_wake_queue(dev);
cebf8cc7 4203 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4204 } else {
bf82c189
JP		 4205 if (net_ratelimit())
4206 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4207 rtl8169_schedule_work(dev, rtl8169_reset_task);
4208 }
eb2a021c
FR		 4209
4210out_unlock:
4211 rtnl_unlock();
1da177e4
LT		 4212}
4213
4214static void rtl8169_tx_timeout(struct net_device *dev)
4215{
4216 struct rtl8169_private *tp = netdev_priv(dev);
4217
4218 rtl8169_hw_reset(tp->mmio_addr);
4219
4220 /* Let's wait a bit while any (async) irq lands on */
4221 rtl8169_schedule_work(dev, rtl8169_reset_task);
4222}
4223
4224static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4225 u32 opts1)
4226{
4227 struct skb_shared_info *info = skb_shinfo(skb);
4228 unsigned int cur_frag, entry;
a6343afb 4229 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4230
4231 entry = tp->cur_tx;
4232 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4233 skb_frag_t *frag = info->frags + cur_frag;
4234 dma_addr_t mapping;
4235 u32 status, len;
4236 void *addr;
4237
4238 entry = (entry + 1) % NUM_TX_DESC;
4239
4240 txd = tp->TxDescArray + entry;
4241 len = frag->size;
4242 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4243 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4244
4245 /* anti gcc 2.95.3 bugware (sic) */
4246 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4247
4248 txd->opts1 = cpu_to_le32(status);
4249 txd->addr = cpu_to_le64(mapping);
4250
4251 tp->tx_skb[entry].len = len;
4252 }
4253
4254 if (cur_frag) {
4255 tp->tx_skb[entry].skb = skb;
4256 txd->opts1 |= cpu_to_le32(LastFrag);
4257 }
4258
4259 return cur_frag;
4260}
4261
4262static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4263{
4264 if (dev->features & NETIF_F_TSO) {
7967168c 4265 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4266
4267 if (mss)
4268 return LargeSend | ((mss & MSSMask) << MSSShift);
4269 }
84fa7933 4270 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4271 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4272
4273 if (ip->protocol == IPPROTO_TCP)
4274 return IPCS | TCPCS;
4275 else if (ip->protocol == IPPROTO_UDP)
4276 return IPCS | UDPCS;
4277 WARN_ON(1); /* we need a WARN() */
4278 }
4279 return 0;
4280}
4281
61357325
SH		 4282static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4283 struct net_device *dev)
1da177e4
LT		 4284{
4285 struct rtl8169_private *tp = netdev_priv(dev);
4286 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4287 struct TxDesc *txd = tp->TxDescArray + entry;
4288 void __iomem *ioaddr = tp->mmio_addr;
4289 dma_addr_t mapping;
4290 u32 status, len;
4291 u32 opts1;
5b0384f4 4292
1da177e4 4293 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4294 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 4295 goto err_stop;
4296 }
4297
4298 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4299 goto err_stop;
4300
4301 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4302
4303 frags = rtl8169_xmit_frags(tp, skb, opts1);
4304 if (frags) {
4305 len = skb_headlen(skb);
4306 opts1 |= FirstFrag;
4307 } else {
4308 len = skb->len;
1da177e4
LT		 4309 opts1 |= FirstFrag | LastFrag;
4310 tp->tx_skb[entry].skb = skb;
4311 }
4312
4313 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4314
4315 tp->tx_skb[entry].len = len;
4316 txd->addr = cpu_to_le64(mapping);
4317 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4318
4319 wmb();
4320
4321 /* anti gcc 2.95.3 bugware (sic) */
4322 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4323 txd->opts1 = cpu_to_le32(status);
4324
1da177e4
LT		 4325 tp->cur_tx += frags + 1;
4326
4c020a96 4327 wmb();
1da177e4 4328
275391a4 4329 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4330
4331 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4332 netif_stop_queue(dev);
4333 smp_rmb();
4334 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4335 netif_wake_queue(dev);
4336 }
4337
61357325 4338 return NETDEV_TX_OK;
1da177e4
LT		 4339
4340err_stop:
4341 netif_stop_queue(dev);
cebf8cc7 4342 dev->stats.tx_dropped++;
61357325 4343 return NETDEV_TX_BUSY;
1da177e4
LT		 4344}
4345
4346static void rtl8169_pcierr_interrupt(struct net_device *dev)
4347{
4348 struct rtl8169_private *tp = netdev_priv(dev);
4349 struct pci_dev *pdev = tp->pci_dev;
4350 void __iomem *ioaddr = tp->mmio_addr;
4351 u16 pci_status, pci_cmd;
4352
4353 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4354 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4355
bf82c189
JP		 4356 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4357 pci_cmd, pci_status);
1da177e4
LT		 4358
4359 /*
4360 * The recovery sequence below admits a very elaborated explanation:
4361 * - it seems to work;
d03902b8
FR		 4362 * - I did not see what else could be done;
4363 * - it makes iop3xx happy.
1da177e4
LT		 4364 *
4365 * Feel free to adjust to your needs.
4366 */
a27993f3 4367 if (pdev->broken_parity_status)
d03902b8
FR		 4368 pci_cmd &= ~PCI_COMMAND_PARITY;
4369 else
4370 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4371
4372 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4373
4374 pci_write_config_word(pdev, PCI_STATUS,
4375 pci_status & (PCI_STATUS_DETECTED_PARITY |
4376 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4377 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4378
4379 /* The infamous DAC f*ckup only happens at boot time */
4380 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4381 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4382 tp->cp_cmd &= ~PCIDAC;
4383 RTL_W16(CPlusCmd, tp->cp_cmd);
4384 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4385 }
4386
4387 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4388
4389 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4390}
4391
07d3f51f
FR		 4392static void rtl8169_tx_interrupt(struct net_device *dev,
4393 struct rtl8169_private *tp,
4394 void __iomem *ioaddr)
1da177e4
LT		 4395{
4396 unsigned int dirty_tx, tx_left;
4397
1da177e4
LT		 4398 dirty_tx = tp->dirty_tx;
4399 smp_rmb();
4400 tx_left = tp->cur_tx - dirty_tx;
4401
4402 while (tx_left > 0) {
4403 unsigned int entry = dirty_tx % NUM_TX_DESC;
4404 struct ring_info *tx_skb = tp->tx_skb + entry;
4405 u32 len = tx_skb->len;
4406 u32 status;
4407
4408 rmb();
4409 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4410 if (status & DescOwn)
4411 break;
4412
cebf8cc7
FR		 4413 dev->stats.tx_bytes += len;
4414 dev->stats.tx_packets++;
1da177e4
LT		 4415
4416 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4417
4418 if (status & LastFrag) {
87433bfc 4419 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4420 tx_skb->skb = NULL;
4421 }
4422 dirty_tx++;
4423 tx_left--;
4424 }
4425
4426 if (tp->dirty_tx != dirty_tx) {
4427 tp->dirty_tx = dirty_tx;
4428 smp_wmb();
4429 if (netif_queue_stopped(dev) &&
4430 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4431 netif_wake_queue(dev);
4432 }
d78ae2dc
FR		 4433 /*
4434 * 8168 hack: TxPoll requests are lost when the Tx packets are
4435 * too close. Let's kick an extra TxPoll request when a burst
4436 * of start_xmit activity is detected (if it is not detected,
4437 * it is slow enough). -- FR
4438 */
4439 smp_rmb();
4440 if (tp->cur_tx != dirty_tx)
4441 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4442 }
4443}
4444
126fa4b9
FR		 4445static inline int rtl8169_fragmented_frame(u32 status)
4446{
4447 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4448}
4449
1da177e4
LT		 4450static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4451{
4452 u32 opts1 = le32_to_cpu(desc->opts1);
4453 u32 status = opts1 & RxProtoMask;
4454
4455 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4456 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4457 ((status == RxProtoIP) && !(opts1 & IPFail)))
4458 skb->ip_summed = CHECKSUM_UNNECESSARY;
4459 else
4460 skb->ip_summed = CHECKSUM_NONE;
4461}
4462
07d3f51f
FR		 4463static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4464 struct rtl8169_private *tp, int pkt_size,
4465 dma_addr_t addr)
1da177e4 4466{
b449655f
SH		 4467 struct sk_buff *skb;
4468 bool done = false;
1da177e4 4469
b449655f
SH		 4470 if (pkt_size >= rx_copybreak)
4471 goto out;
1da177e4 4472
89d71a66 4473 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
b449655f
SH		 4474 if (!skb)
4475 goto out;
4476
07d3f51f
FR		 4477 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4478 PCI_DMA_FROMDEVICE);
b449655f
SH		 4479 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4480 *sk_buff = skb;
4481 done = true;
4482out:
4483 return done;
1da177e4
LT		 4484}
4485
630b943c
ED		 4486/*
4487 * Warning : rtl8169_rx_interrupt() might be called :
4488 * 1) from NAPI (softirq) context
4489 * (polling = 1 : we should call netif_receive_skb())
4490 * 2) from process context (rtl8169_reset_task())
4491 * (polling = 0 : we must call netif_rx() instead)
4492 */
07d3f51f
FR		 4493static int rtl8169_rx_interrupt(struct net_device *dev,
4494 struct rtl8169_private *tp,
bea3348e 4495 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4496{
4497 unsigned int cur_rx, rx_left;
4498 unsigned int delta, count;
630b943c 4499 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4500
1da177e4
LT		 4501 cur_rx = tp->cur_rx;
4502 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4503 rx_left = min(rx_left, budget);
1da177e4 4504
4dcb7d33 4505 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4506 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4507 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4508 u32 status;
4509
4510 rmb();
126fa4b9 4511 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4512
4513 if (status & DescOwn)
4514 break;
4dcb7d33 4515 if (unlikely(status & RxRES)) {
bf82c189
JP		 4516 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4517 status);
cebf8cc7 4518 dev->stats.rx_errors++;
1da177e4 4519 if (status & (RxRWT | RxRUNT))
cebf8cc7 4520 dev->stats.rx_length_errors++;
1da177e4 4521 if (status & RxCRC)
cebf8cc7 4522 dev->stats.rx_crc_errors++;
9dccf611
FR		 4523 if (status & RxFOVF) {
4524 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4525 dev->stats.rx_fifo_errors++;
9dccf611 4526 }
126fa4b9 4527 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4528 } else {
1da177e4 4529 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4530 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4531 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4532 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4533
126fa4b9
FR		 4534 /*
4535 * The driver does not support incoming fragmented
4536 * frames. They are seen as a symptom of over-mtu
4537 * sized frames.
4538 */
4539 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4540 dev->stats.rx_dropped++;
4541 dev->stats.rx_length_errors++;
126fa4b9 4542 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4543 continue;
126fa4b9
FR		 4544 }
4545
1da177e4 4546 rtl8169_rx_csum(skb, desc);
bcf0bf90 4547
07d3f51f 4548 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 4549 pci_dma_sync_single_for_device(pdev, addr,
4550 pkt_size, PCI_DMA_FROMDEVICE);
4551 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4552 } else {
a866bbf6 4553 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 4554 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4555 tp->Rx_skbuff[entry] = NULL;
4556 }
4557
1da177e4
LT		 4558 skb_put(skb, pkt_size);
4559 skb->protocol = eth_type_trans(skb, dev);
4560
630b943c
ED		 4561 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4562 if (likely(polling))
4563 netif_receive_skb(skb);
4564 else
4565 netif_rx(skb);
4566 }
1da177e4 4567
cebf8cc7
FR		 4568 dev->stats.rx_bytes += pkt_size;
4569 dev->stats.rx_packets++;
1da177e4 4570 }
6dccd16b
FR		 4571
4572 /* Work around for AMD plateform. */
95e0918d 4573 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4574 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4575 desc->opts2 = 0;
4576 cur_rx++;
4577 }
1da177e4
LT		 4578 }
4579
4580 count = cur_rx - tp->cur_rx;
4581 tp->cur_rx = cur_rx;
4582
4583 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
bf82c189
JP		 4584 if (!delta && count)
4585 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
1da177e4
LT		 4586 tp->dirty_rx += delta;
4587
4588 /*
4589 * FIXME: until there is periodic timer to try and refill the ring,
4590 * a temporary shortage may definitely kill the Rx process.
4591 * - disable the asic to try and avoid an overflow and kick it again
4592 * after refill ?
4593 * - how do others driver handle this condition (Uh oh...).
4594 */
bf82c189
JP		 4595 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4596 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
1da177e4
LT		 4597
4598 return count;
4599}
4600
07d3f51f 4601static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4602{
07d3f51f 4603 struct net_device *dev = dev_instance;
1da177e4 4604 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4605 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4606 int handled = 0;
865c652d 4607 int status;
1da177e4 4608
f11a377b
DD		 4609 /* loop handling interrupts until we have no new ones or
4610 * we hit a invalid/hotplug case.
4611 */
865c652d 4612 status = RTL_R16(IntrStatus);
f11a377b
DD		 4613 while (status && status != 0xffff) {
4614 handled = 1;
1da177e4 4615
f11a377b
DD		 4616 /* Handle all of the error cases first. These will reset
4617 * the chip, so just exit the loop.
4618 */
4619 if (unlikely(!netif_running(dev))) {
4620 rtl8169_asic_down(ioaddr);
4621 break;
4622 }
1da177e4 4623
f11a377b
DD		 4624 /* Work around for rx fifo overflow */
4625 if (unlikely(status & RxFIFOOver) &&
4626 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4627 netif_stop_queue(dev);
4628 rtl8169_tx_timeout(dev);
4629 break;
4630 }
1da177e4 4631
f11a377b
DD		 4632 if (unlikely(status & SYSErr)) {
4633 rtl8169_pcierr_interrupt(dev);
4634 break;
4635 }
1da177e4 4636
f11a377b
DD		 4637 if (status & LinkChg)
4638 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4639
f11a377b
DD		 4640 /* We need to see the lastest version of tp->intr_mask to
4641 * avoid ignoring an MSI interrupt and having to wait for
4642 * another event which may never come.
4643 */
4644 smp_rmb();
4645 if (status & tp->intr_mask & tp->napi_event) {
4646 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4647 tp->intr_mask = ~tp->napi_event;
4648
4649 if (likely(napi_schedule_prep(&tp->napi)))
4650 __napi_schedule(&tp->napi);
bf82c189
JP		 4651 else
4652 netif_info(tp, intr, dev,
4653 "interrupt %04x in poll\n", status);
f11a377b 4654 }
1da177e4 4655
f11a377b
DD		 4656 /* We only get a new MSI interrupt when all active irq
4657 * sources on the chip have been acknowledged. So, ack
4658 * everything we've seen and check if new sources have become
4659 * active to avoid blocking all interrupts from the chip.
4660 */
4661 RTL_W16(IntrStatus,
4662 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4663 status = RTL_R16(IntrStatus);
865c652d 4664 }
1da177e4 4665
1da177e4
LT		 4666 return IRQ_RETVAL(handled);
4667}
4668
bea3348e 4669static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4670{
bea3348e
SH		 4671 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4672 struct net_device *dev = tp->dev;
1da177e4 4673 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4674 int work_done;
1da177e4 4675
bea3348e 4676 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4677 rtl8169_tx_interrupt(dev, tp, ioaddr);
4678
bea3348e 4679 if (work_done < budget) {
288379f0 4680 napi_complete(napi);
f11a377b
DD		 4681
4682 /* We need for force the visibility of tp->intr_mask
4683 * for other CPUs, as we can loose an MSI interrupt
4684 * and potentially wait for a retransmit timeout if we don't.
4685 * The posted write to IntrMask is safe, as it will
4686 * eventually make it to the chip and we won't loose anything
4687 * until it does.
1da177e4 4688 */
f11a377b 4689 tp->intr_mask = 0xffff;
4c020a96 4690 wmb();
0e485150 4691 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4692 }
4693
bea3348e 4694 return work_done;
1da177e4 4695}
1da177e4 4696
523a6094
FR		 4697static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4698{
4699 struct rtl8169_private *tp = netdev_priv(dev);
4700
4701 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4702 return;
4703
4704 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4705 RTL_W32(RxMissed, 0);
4706}
4707
1da177e4
LT		 4708static void rtl8169_down(struct net_device *dev)
4709{
4710 struct rtl8169_private *tp = netdev_priv(dev);
4711 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4712 unsigned int intrmask;
1da177e4
LT		 4713
4714 rtl8169_delete_timer(dev);
4715
4716 netif_stop_queue(dev);
4717
93dd79e8 4718 napi_disable(&tp->napi);
93dd79e8 4719
1da177e4
LT		 4720core_down:
4721 spin_lock_irq(&tp->lock);
4722
4723 rtl8169_asic_down(ioaddr);
4724
523a6094 4725 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4726
4727 spin_unlock_irq(&tp->lock);
4728
4729 synchronize_irq(dev->irq);
4730
1da177e4 4731 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4732 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4733
4734 /*
4735 * And now for the 50k$ question: are IRQ disabled or not ?
4736 *
4737 * Two paths lead here:
4738 * 1) dev->close
4739 * -> netif_running() is available to sync the current code and the
4740 * IRQ handler. See rtl8169_interrupt for details.
4741 * 2) dev->change_mtu
4742 * -> rtl8169_poll can not be issued again and re-enable the
4743 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4744 *
4745 * No loop if hotpluged or major error (0xffff).
1da177e4 4746 */
733b736c
AP		 4747 intrmask = RTL_R16(IntrMask);
4748 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4749 goto core_down;
4750
4751 rtl8169_tx_clear(tp);
4752
4753 rtl8169_rx_clear(tp);
4754}
4755
4756static int rtl8169_close(struct net_device *dev)
4757{
4758 struct rtl8169_private *tp = netdev_priv(dev);
4759 struct pci_dev *pdev = tp->pci_dev;
4760
e1759441
RW		 4761 pm_runtime_get_sync(&pdev->dev);
4762
355423d0
IV		 4763 /* update counters before going down */
4764 rtl8169_update_counters(dev);
4765
1da177e4
LT		 4766 rtl8169_down(dev);
4767
4768 free_irq(dev->irq, dev);
4769
1da177e4
LT		 4770 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4771 tp->RxPhyAddr);
4772 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4773 tp->TxPhyAddr);
4774 tp->TxDescArray = NULL;
4775 tp->RxDescArray = NULL;
4776
e1759441
RW		 4777 pm_runtime_put_sync(&pdev->dev);
4778
1da177e4
LT		 4779 return 0;
4780}
4781
07ce4064 4782static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4783{
4784 struct rtl8169_private *tp = netdev_priv(dev);
4785 void __iomem *ioaddr = tp->mmio_addr;
4786 unsigned long flags;
4787 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4788 int rx_mode;
1da177e4
LT		 4789 u32 tmp = 0;
4790
4791 if (dev->flags & IFF_PROMISC) {
4792 /* Unconditionally log net taps. */
bf82c189 4793 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4794 rx_mode =
4795 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4796 AcceptAllPhys;
4797 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4798 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4799 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4800 /* Too many to filter perfectly -- accept all multicasts. */
4801 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4802 mc_filter[1] = mc_filter[0] = 0xffffffff;
4803 } else {
22bedad3 4804 struct netdev_hw_addr *ha;
07d3f51f 4805
1da177e4
LT		 4806 rx_mode = AcceptBroadcast | AcceptMyPhys;
4807 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4808 netdev_for_each_mc_addr(ha, dev) {
4809 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4810 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4811 rx_mode |= AcceptMulticast;
4812 }
4813 }
4814
4815 spin_lock_irqsave(&tp->lock, flags);
4816
4817 tmp = rtl8169_rx_config | rx_mode |
4818 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4819
f887cce8 4820 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4821 u32 data = mc_filter[0];
4822
4823 mc_filter[0] = swab32(mc_filter[1]);
4824 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4825 }
4826
1da177e4 4827 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4828 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4829
57a9f236
FR		 4830 RTL_W32(RxConfig, tmp);
4831
1da177e4
LT		 4832 spin_unlock_irqrestore(&tp->lock, flags);
4833}
4834
4835/**
4836 * rtl8169_get_stats - Get rtl8169 read/write statistics
4837 * @dev: The Ethernet Device to get statistics for
4838 *
4839 * Get TX/RX statistics for rtl8169
4840 */
4841static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4842{
4843 struct rtl8169_private *tp = netdev_priv(dev);
4844 void __iomem *ioaddr = tp->mmio_addr;
4845 unsigned long flags;
4846
4847 if (netif_running(dev)) {
4848 spin_lock_irqsave(&tp->lock, flags);
523a6094 4849 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4850 spin_unlock_irqrestore(&tp->lock, flags);
4851 }
5b0384f4 4852
cebf8cc7 4853 return &dev->stats;
1da177e4
LT		 4854}
4855
861ab440 4856static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4857{
5d06a99f 4858 if (!netif_running(dev))
861ab440 4859 return;
5d06a99f
FR		 4860
4861 netif_device_detach(dev);
4862 netif_stop_queue(dev);
861ab440
RW		 4863}
4864
4865#ifdef CONFIG_PM
4866
4867static int rtl8169_suspend(struct device *device)
4868{
4869 struct pci_dev *pdev = to_pci_dev(device);
4870 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4871
861ab440 4872 rtl8169_net_suspend(dev);
1371fa6d 4873
5d06a99f
FR		 4874 return 0;
4875}
4876
e1759441
RW		 4877static void __rtl8169_resume(struct net_device *dev)
4878{
4879 netif_device_attach(dev);
4880 rtl8169_schedule_work(dev, rtl8169_reset_task);
4881}
4882
861ab440 4883static int rtl8169_resume(struct device *device)
5d06a99f 4884{
861ab440 4885 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4886 struct net_device *dev = pci_get_drvdata(pdev);
4887
e1759441
RW		 4888 if (netif_running(dev))
4889 __rtl8169_resume(dev);
5d06a99f 4890
e1759441
RW		 4891 return 0;
4892}
4893
4894static int rtl8169_runtime_suspend(struct device *device)
4895{
4896 struct pci_dev *pdev = to_pci_dev(device);
4897 struct net_device *dev = pci_get_drvdata(pdev);
4898 struct rtl8169_private *tp = netdev_priv(dev);
4899
4900 if (!tp->TxDescArray)
4901 return 0;
4902
4903 spin_lock_irq(&tp->lock);
4904 tp->saved_wolopts = __rtl8169_get_wol(tp);
4905 __rtl8169_set_wol(tp, WAKE_ANY);
4906 spin_unlock_irq(&tp->lock);
4907
4908 rtl8169_net_suspend(dev);
4909
4910 return 0;
4911}
4912
4913static int rtl8169_runtime_resume(struct device *device)
4914{
4915 struct pci_dev *pdev = to_pci_dev(device);
4916 struct net_device *dev = pci_get_drvdata(pdev);
4917 struct rtl8169_private *tp = netdev_priv(dev);
4918
4919 if (!tp->TxDescArray)
4920 return 0;
4921
4922 spin_lock_irq(&tp->lock);
4923 __rtl8169_set_wol(tp, tp->saved_wolopts);
4924 tp->saved_wolopts = 0;
4925 spin_unlock_irq(&tp->lock);
4926
4927 __rtl8169_resume(dev);
5d06a99f 4928
5d06a99f
FR		 4929 return 0;
4930}
4931
e1759441
RW		 4932static int rtl8169_runtime_idle(struct device *device)
4933{
4934 struct pci_dev *pdev = to_pci_dev(device);
4935 struct net_device *dev = pci_get_drvdata(pdev);
4936 struct rtl8169_private *tp = netdev_priv(dev);
4937
4938 if (!tp->TxDescArray)
4939 return 0;
4940
4941 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4942 return -EBUSY;
4943}
4944
47145210 4945static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4946 .suspend = rtl8169_suspend,
4947 .resume = rtl8169_resume,
4948 .freeze = rtl8169_suspend,
4949 .thaw = rtl8169_resume,
4950 .poweroff = rtl8169_suspend,
4951 .restore = rtl8169_resume,
e1759441
RW		 4952 .runtime_suspend = rtl8169_runtime_suspend,
4953 .runtime_resume = rtl8169_runtime_resume,
4954 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4955};
4956
4957#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4958
4959#else /* !CONFIG_PM */
4960
4961#define RTL8169_PM_OPS NULL
4962
4963#endif /* !CONFIG_PM */
4964
1765f95d
FR		 4965static void rtl_shutdown(struct pci_dev *pdev)
4966{
861ab440 4967 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4968 struct rtl8169_private *tp = netdev_priv(dev);
4969 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4970
4971 rtl8169_net_suspend(dev);
1765f95d 4972
cc098dc7
IV		 4973 /* restore original MAC address */
4974 rtl_rar_set(tp, dev->perm_addr);
4975
4bb3f522 4976 spin_lock_irq(&tp->lock);
4977
4978 rtl8169_asic_down(ioaddr);
4979
4980 spin_unlock_irq(&tp->lock);
4981
861ab440 4982 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4983 /* WoL fails with some 8168 when the receiver is disabled. */
4984 if (tp->features & RTL_FEATURE_WOL) {
4985 pci_clear_master(pdev);
4986
4987 RTL_W8(ChipCmd, CmdRxEnb);
4988 /* PCI commit */
4989 RTL_R8(ChipCmd);
4990 }
4991
861ab440
RW		 4992 pci_wake_from_d3(pdev, true);
4993 pci_set_power_state(pdev, PCI_D3hot);
4994 }
4995}
5d06a99f 4996
1da177e4
LT		 4997static struct pci_driver rtl8169_pci_driver = {
4998 .name = MODULENAME,
4999 .id_table = rtl8169_pci_tbl,
5000 .probe = rtl8169_init_one,
5001 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5002 .shutdown = rtl_shutdown,
861ab440 5003 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5004};
5005
07d3f51f 5006static int __init rtl8169_init_module(void)
1da177e4 5007{
29917620 5008 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5009}
5010
07d3f51f 5011static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5012{
5013 pci_unregister_driver(&rtl8169_pci_driver);
5014}
5015
5016module_init(rtl8169_init_module);
5017module_exit(rtl8169_cleanup_module);
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