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ixgbe: add MAC and PHY support for x540
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
fe15e8e1 62 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 63};
64
65/* ixgbe_pci_tbl - PCI Device ID Table
66 *
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
69 *
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
72 */
a3aa1884 73static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 77 board_82598 },
9a799d71 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 79 board_82598 },
0befdb3e
JB		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 board_82598 },
3845bec0
PWJ		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 board_82598 },
9a799d71 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 85 board_82598 },
8d792cd9
JB		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 board_82598 },
c4900be0
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 board_82598 },
b95f5fcb
JB		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 board_82598 },
c4900be0
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 board_82598 },
2f21bdd3
DS		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 board_82598 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 board_82599 },
1fcf03e6
PWJ		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 board_82599 },
74757d49
DS		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 board_82599 },
e8e26350
PW		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 board_82599 },
38ad1c8e
DS		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 board_82599 },
dbfec662
DS		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 board_82599 },
8911184f
PWJ		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 board_82599 },
119fc60a
MC		 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
113 board_82599 },
312eb931
DS		 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
115 board_82599 },
9a799d71
AK		 116
117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696
JP		 135MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
1cdd1ec8
GR		 146static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
147{
148 struct ixgbe_hw *hw = &adapter->hw;
149 u32 gcr;
150 u32 gpie;
151 u32 vmdctl;
152
153#ifdef CONFIG_PCI_IOV
154 /* disable iov and allow time for transactions to clear */
155 pci_disable_sriov(adapter->pdev);
156#endif
157
158 /* turn off device IOV mode */
159 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
160 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
161 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
162 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
163 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
164 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
165
166 /* set default pool back to 0 */
167 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
168 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
169 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
170
171 /* take a breather then clean up driver data */
172 msleep(100);
e8e9f696
JP		 173
174 kfree(adapter->vfinfo);
1cdd1ec8
GR		 175 adapter->vfinfo = NULL;
176
177 adapter->num_vfs = 0;
178 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
179}
180
dcd79aeb
TI		 181struct ixgbe_reg_info {
182 u32 ofs;
183 char *name;
184};
185
186static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
187
188 /* General Registers */
189 {IXGBE_CTRL, "CTRL"},
190 {IXGBE_STATUS, "STATUS"},
191 {IXGBE_CTRL_EXT, "CTRL_EXT"},
192
193 /* Interrupt Registers */
194 {IXGBE_EICR, "EICR"},
195
196 /* RX Registers */
197 {IXGBE_SRRCTL(0), "SRRCTL"},
198 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
199 {IXGBE_RDLEN(0), "RDLEN"},
200 {IXGBE_RDH(0), "RDH"},
201 {IXGBE_RDT(0), "RDT"},
202 {IXGBE_RXDCTL(0), "RXDCTL"},
203 {IXGBE_RDBAL(0), "RDBAL"},
204 {IXGBE_RDBAH(0), "RDBAH"},
205
206 /* TX Registers */
207 {IXGBE_TDBAL(0), "TDBAL"},
208 {IXGBE_TDBAH(0), "TDBAH"},
209 {IXGBE_TDLEN(0), "TDLEN"},
210 {IXGBE_TDH(0), "TDH"},
211 {IXGBE_TDT(0), "TDT"},
212 {IXGBE_TXDCTL(0), "TXDCTL"},
213
214 /* List Terminator */
215 {}
216};
217
218
219/*
220 * ixgbe_regdump - register printout routine
221 */
222static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
223{
224 int i = 0, j = 0;
225 char rname[16];
226 u32 regs[64];
227
228 switch (reginfo->ofs) {
229 case IXGBE_SRRCTL(0):
230 for (i = 0; i < 64; i++)
231 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
232 break;
233 case IXGBE_DCA_RXCTRL(0):
234 for (i = 0; i < 64; i++)
235 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
236 break;
237 case IXGBE_RDLEN(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
240 break;
241 case IXGBE_RDH(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
244 break;
245 case IXGBE_RDT(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
248 break;
249 case IXGBE_RXDCTL(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
252 break;
253 case IXGBE_RDBAL(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
256 break;
257 case IXGBE_RDBAH(0):
258 for (i = 0; i < 64; i++)
259 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
260 break;
261 case IXGBE_TDBAL(0):
262 for (i = 0; i < 64; i++)
263 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
264 break;
265 case IXGBE_TDBAH(0):
266 for (i = 0; i < 64; i++)
267 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
268 break;
269 case IXGBE_TDLEN(0):
270 for (i = 0; i < 64; i++)
271 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
272 break;
273 case IXGBE_TDH(0):
274 for (i = 0; i < 64; i++)
275 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
276 break;
277 case IXGBE_TDT(0):
278 for (i = 0; i < 64; i++)
279 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
280 break;
281 case IXGBE_TXDCTL(0):
282 for (i = 0; i < 64; i++)
283 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
284 break;
285 default:
c7689578 286 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 287 IXGBE_READ_REG(hw, reginfo->ofs));
288 return;
289 }
290
291 for (i = 0; i < 8; i++) {
292 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 293 pr_err("%-15s", rname);
dcd79aeb 294 for (j = 0; j < 8; j++)
c7689578
JP		 295 pr_cont(" %08x", regs[i*8+j]);
296 pr_cont("\n");
dcd79aeb
TI		 297 }
298
299}
300
301/*
302 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 */
304static void ixgbe_dump(struct ixgbe_adapter *adapter)
305{
306 struct net_device *netdev = adapter->netdev;
307 struct ixgbe_hw *hw = &adapter->hw;
308 struct ixgbe_reg_info *reginfo;
309 int n = 0;
310 struct ixgbe_ring *tx_ring;
311 struct ixgbe_tx_buffer *tx_buffer_info;
312 union ixgbe_adv_tx_desc *tx_desc;
313 struct my_u0 { u64 a; u64 b; } *u0;
314 struct ixgbe_ring *rx_ring;
315 union ixgbe_adv_rx_desc *rx_desc;
316 struct ixgbe_rx_buffer *rx_buffer_info;
317 u32 staterr;
318 int i = 0;
319
320 if (!netif_msg_hw(adapter))
321 return;
322
323 /* Print netdevice Info */
324 if (netdev) {
325 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 326 pr_info("Device Name state "
dcd79aeb 327 "trans_start last_rx\n");
c7689578
JP		 328 pr_info("%-15s %016lX %016lX %016lX\n",
329 netdev->name,
330 netdev->state,
331 netdev->trans_start,
332 netdev->last_rx);
dcd79aeb
TI		 333 }
334
335 /* Print Registers */
336 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 337 pr_info(" Register Name Value\n");
dcd79aeb
TI		 338 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
339 reginfo->name; reginfo++) {
340 ixgbe_regdump(hw, reginfo);
341 }
342
343 /* Print TX Ring Summary */
344 if (!netdev || !netif_running(netdev))
345 goto exit;
346
347 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 348 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 353 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
c7689578
JP		 380 pr_info("------------------------------------\n");
381 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 pr_info("------------------------------------\n");
383 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 388 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
c7689578 391 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
c7689578 402 pr_cont(" NTC/U\n");
dcd79aeb 403 else if (i == tx_ring->next_to_use)
c7689578 404 pr_cont(" NTU\n");
dcd79aeb 405 else if (i == tx_ring->next_to_clean)
c7689578 406 pr_cont(" NTC\n");
dcd79aeb 407 else
c7689578 408 pr_cont("\n");
dcd79aeb
TI		 409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 422 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
c7689578
JP		 425 pr_info("%5d %5X %5X\n",
426 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
c7689578
JP		 457 pr_info("------------------------------------\n");
458 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 pr_info("------------------------------------\n");
460 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
c7689578 463 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 469 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
c7689578 474 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
c7689578 480 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
c7689578 506 pr_cont(" NTU\n");
dcd79aeb 507 else if (i == rx_ring->next_to_clean)
c7689578 508 pr_cont(" NTC\n");
dcd79aeb 509 else
c7689578 510 pr_cont("\n");
dcd79aeb
TI		 511
512 }
513 }
514
515exit:
516 return;
517}
518
5eba3699
AV		 519static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520{
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 527}
528
529static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530{
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 537}
9a799d71 538
e8e26350
PW		 539/*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 548 u8 queue, u8 msix_vector)
9a799d71
AK		 549{
550 u32 ivar, index;
e8e26350
PW		 551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
9a799d71
AK		 586}
587
fe49f04a 588static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 589 u64 qmask)
fe49f04a
AD		 590{
591 u32 mask;
592
bd508178
AD		 593 switch (adapter->hw.mac.type) {
594 case ixgbe_mac_82598EB:
fe49f04a
AD		 595 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 597 break;
598 case ixgbe_mac_82599EB:
fe49f04a
AD		 599 mask = (qmask & 0xFFFFFFFF);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
601 mask = (qmask >> 32);
602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 603 break;
604 default:
605 break;
fe49f04a
AD		 606 }
607}
608
b6ec895e
AD		 609void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
610 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 611{
e5a43549
AD		 612 if (tx_buffer_info->dma) {
613 if (tx_buffer_info->mapped_as_page)
b6ec895e 614 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 615 tx_buffer_info->dma,
616 tx_buffer_info->length,
1b507730 617 DMA_TO_DEVICE);
e5a43549 618 else
b6ec895e 619 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 620 tx_buffer_info->dma,
621 tx_buffer_info->length,
1b507730 622 DMA_TO_DEVICE);
e5a43549
AD		 623 tx_buffer_info->dma = 0;
624 }
9a799d71
AK		 625 if (tx_buffer_info->skb) {
626 dev_kfree_skb_any(tx_buffer_info->skb);
627 tx_buffer_info->skb = NULL;
628 }
44df32c5 629 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 630 /* tx_buffer_info must be completely set up in the transmit path */
631}
632
26f23d82 633/**
c84d324c
JF		 634 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
635 * @adapter: driver private struct
636 * @index: reg idx of queue to query (0-127)
26f23d82 637 *
c84d324c
JF		 638 * Helper function to determine the traffic index for a paticular
639 * register index.
26f23d82 640 *
c84d324c 641 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 642 */
c84d324c 643u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 644{
c84d324c
JF		 645 int tc = -1;
646 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
26f23d82 647
c84d324c
JF		 648 /* if DCB is not enabled the queues have no TC */
649 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
650 return tc;
26f23d82 651
c84d324c
JF		 652 /* check valid range */
653 if (reg_idx >= adapter->hw.mac.max_tx_queues)
654 return tc;
655
656 switch (adapter->hw.mac.type) {
657 case ixgbe_mac_82598EB:
658 tc = reg_idx >> 2;
659 break;
660 default:
661 if (dcb_i != 4 && dcb_i != 8)
6837e895 662 break;
c84d324c
JF		 663
664 /* if VMDq is enabled the lowest order bits determine TC */
665 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
666 IXGBE_FLAG_VMDQ_ENABLED)) {
667 tc = reg_idx & (dcb_i - 1);
668 break;
669 }
670
671 /*
672 * Convert the reg_idx into the correct TC. This bitmask
673 * targets the last full 32 ring traffic class and assigns
674 * it a value of 1. From there the rest of the rings are
675 * based on shifting the mask further up to include the
676 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
677 * will only ever be 8 or 4 and that reg_idx will never
678 * be greater then 128. The code without the power of 2
679 * optimizations would be:
680 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
681 */
682 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
683 tc >>= 9 - (reg_idx >> 5);
684 }
685
686 return tc;
687}
688
689static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
690{
691 struct ixgbe_hw *hw = &adapter->hw;
692 struct ixgbe_hw_stats *hwstats = &adapter->stats;
693 u32 data = 0;
694 u32 xoff[8] = {0};
695 int i;
696
697 if ((hw->fc.current_mode == ixgbe_fc_full) ||
698 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
699 switch (hw->mac.type) {
700 case ixgbe_mac_82598EB:
701 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 702 break;
703 default:
c84d324c
JF		 704 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
705 }
706 hwstats->lxoffrxc += data;
707
708 /* refill credits (no tx hang) if we received xoff */
709 if (!data)
710 return;
711
712 for (i = 0; i < adapter->num_tx_queues; i++)
713 clear_bit(__IXGBE_HANG_CHECK_ARMED,
714 &adapter->tx_ring[i]->state);
715 return;
716 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
717 return;
718
719 /* update stats for each tc, only valid with PFC enabled */
720 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
721 switch (hw->mac.type) {
722 case ixgbe_mac_82598EB:
723 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 724 break;
c84d324c
JF		 725 default:
726 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 727 }
c84d324c
JF		 728 hwstats->pxoffrxc[i] += xoff[i];
729 }
730
731 /* disarm tx queues that have received xoff frames */
732 for (i = 0; i < adapter->num_tx_queues; i++) {
733 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
734 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
735
736 if (xoff[tc])
737 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 738 }
26f23d82
YZ		 739}
740
c84d324c 741static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 742{
c84d324c
JF		 743 return ring->tx_stats.completed;
744}
745
746static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
747{
748 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 749 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 750
c84d324c
JF		 751 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
752 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
753
754 if (head != tail)
755 return (head < tail) ?
756 tail - head : (tail + ring->count - head);
757
758 return 0;
759}
760
761static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
762{
763 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
764 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
765 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
766 bool ret = false;
767
7d637bcc 768 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 769
770 /*
771 * Check for a hung queue, but be thorough. This verifies
772 * that a transmit has been completed since the previous
773 * check AND there is at least one packet pending. The
774 * ARMED bit is set to indicate a potential hang. The
775 * bit is cleared if a pause frame is received to remove
776 * false hang detection due to PFC or 802.3x frames. By
777 * requiring this to fail twice we avoid races with
778 * pfc clearing the ARMED bit and conditions where we
779 * run the check_tx_hang logic with a transmit completion
780 * pending but without time to complete it yet.
781 */
782 if ((tx_done_old == tx_done) && tx_pending) {
783 /* make sure it is true for two checks in a row */
784 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
785 &tx_ring->state);
786 } else {
787 /* update completed stats and continue */
788 tx_ring->tx_stats.tx_done_old = tx_done;
789 /* reset the countdown */
790 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 791 }
792
c84d324c 793 return ret;
9a799d71
AK		 794}
795
b4617240
PW		 796#define IXGBE_MAX_TXD_PWR 14
797#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 798
799/* Tx Descriptors needed, worst case */
800#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
801 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
802#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 803 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 804
e01c31a5
JB		 805static void ixgbe_tx_timeout(struct net_device *netdev);
806
9a799d71
AK		 807/**
808 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 809 * @q_vector: structure containing interrupt and ring information
e01c31a5 810 * @tx_ring: tx ring to clean
9a799d71 811 **/
fe49f04a 812static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 813 struct ixgbe_ring *tx_ring)
9a799d71 814{
fe49f04a 815 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 816 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
817 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 818 unsigned int total_bytes = 0, total_packets = 0;
b953799e 819 u16 i, eop, count = 0;
9a799d71
AK		 820
821 i = tx_ring->next_to_clean;
12207e49 822 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 823 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 824
825 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 826 (count < tx_ring->work_limit)) {
12207e49 827 bool cleaned = false;
2d0bb1c1 828 rmb(); /* read buffer_info after eop_desc */
12207e49 829 for ( ; !cleaned; count++) {
31f05a2d 830 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 831 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 832
833 tx_desc->wb.status = 0;
12207e49 834 cleaned = (i == eop);
9a799d71 835
8ad494b0
AD		 836 i++;
837 if (i == tx_ring->count)
838 i = 0;
e01c31a5 839
8ad494b0
AD		 840 if (cleaned && tx_buffer_info->skb) {
841 total_bytes += tx_buffer_info->bytecount;
842 total_packets += tx_buffer_info->gso_segs;
e092be60 843 }
e01c31a5 844
b6ec895e 845 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 846 tx_buffer_info);
e01c31a5 847 }
12207e49 848
c84d324c 849 tx_ring->tx_stats.completed++;
12207e49 850 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 851 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 852 }
853
9a799d71 854 tx_ring->next_to_clean = i;
b953799e
AD		 855 tx_ring->total_bytes += total_bytes;
856 tx_ring->total_packets += total_packets;
857 u64_stats_update_begin(&tx_ring->syncp);
858 tx_ring->stats.packets += total_packets;
859 tx_ring->stats.bytes += total_bytes;
860 u64_stats_update_end(&tx_ring->syncp);
861
c84d324c
JF		 862 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
863 /* schedule immediate reset if we believe we hung */
864 struct ixgbe_hw *hw = &adapter->hw;
865 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
866 e_err(drv, "Detected Tx Unit Hang\n"
867 " Tx Queue <%d>\n"
868 " TDH, TDT <%x>, <%x>\n"
869 " next_to_use <%x>\n"
870 " next_to_clean <%x>\n"
871 "tx_buffer_info[next_to_clean]\n"
872 " time_stamp <%lx>\n"
873 " jiffies <%lx>\n",
874 tx_ring->queue_index,
875 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
876 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
877 tx_ring->next_to_use, eop,
878 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
879
880 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
881
882 e_info(probe,
883 "tx hang %d detected on queue %d, resetting adapter\n",
884 adapter->tx_timeout_count + 1, tx_ring->queue_index);
885
b953799e 886 /* schedule immediate reset if we believe we hung */
b953799e
AD		 887 ixgbe_tx_timeout(adapter->netdev);
888
889 /* the adapter is about to reset, no point in enabling stuff */
890 return true;
891 }
9a799d71 892
e092be60 893#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 894 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 895 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 896 /* Make sure that anybody stopping the queue after this
897 * sees the new next_to_clean.
898 */
899 smp_mb();
fc77dc3c 900 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 901 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 902 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 903 ++tx_ring->tx_stats.restart_queue;
30eba97a 904 }
e092be60 905 }
9a799d71 906
807540ba 907 return count < tx_ring->work_limit;
9a799d71
AK		 908}
909
5dd2d332 910#ifdef CONFIG_IXGBE_DCA
bd0362dd 911static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 912 struct ixgbe_ring *rx_ring,
913 int cpu)
bd0362dd 914{
33cf09c9 915 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 916 u32 rxctrl;
33cf09c9
AD		 917 u8 reg_idx = rx_ring->reg_idx;
918
919 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
920 switch (hw->mac.type) {
921 case ixgbe_mac_82598EB:
922 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
923 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
924 break;
925 case ixgbe_mac_82599EB:
926 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
927 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
928 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
929 break;
930 default:
931 break;
bd0362dd 932 }
33cf09c9
AD		 933 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
934 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
935 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
936 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
937 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
938 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 939}
940
941static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 942 struct ixgbe_ring *tx_ring,
943 int cpu)
bd0362dd 944{
33cf09c9 945 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 946 u32 txctrl;
33cf09c9
AD		 947 u8 reg_idx = tx_ring->reg_idx;
948
949 switch (hw->mac.type) {
950 case ixgbe_mac_82598EB:
951 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
952 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
953 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
954 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
955 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
956 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
957 break;
958 case ixgbe_mac_82599EB:
959 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
960 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
961 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
962 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
963 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
964 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
965 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
966 break;
967 default:
968 break;
969 }
970}
971
972static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
973{
974 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 975 int cpu = get_cpu();
33cf09c9
AD		 976 long r_idx;
977 int i;
bd0362dd 978
33cf09c9
AD		 979 if (q_vector->cpu == cpu)
980 goto out_no_update;
981
982 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
983 for (i = 0; i < q_vector->txr_count; i++) {
984 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
985 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
986 r_idx + 1);
bd0362dd 987 }
33cf09c9
AD		 988
989 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
990 for (i = 0; i < q_vector->rxr_count; i++) {
991 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
992 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
993 r_idx + 1);
994 }
995
996 q_vector->cpu = cpu;
997out_no_update:
bd0362dd
JC		 998 put_cpu();
999}
1000
1001static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1002{
33cf09c9 1003 int num_q_vectors;
bd0362dd
JC		 1004 int i;
1005
1006 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1007 return;
1008
e35ec126
AD		 1009 /* always use CB2 mode, difference is masked in the CB driver */
1010 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1011
33cf09c9
AD		 1012 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1013 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1014 else
1015 num_q_vectors = 1;
1016
1017 for (i = 0; i < num_q_vectors; i++) {
1018 adapter->q_vector[i]->cpu = -1;
1019 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1020 }
1021}
1022
1023static int __ixgbe_notify_dca(struct device *dev, void *data)
1024{
c60fbb00 1025 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1026 unsigned long event = *(unsigned long *)data;
1027
33cf09c9
AD		 1028 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1029 return 0;
1030
bd0362dd
JC		 1031 switch (event) {
1032 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1033 /* if we're already enabled, don't do it again */
1034 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1035 break;
652f093f 1036 if (dca_add_requester(dev) == 0) {
96b0e0f6 1037 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1038 ixgbe_setup_dca(adapter);
1039 break;
1040 }
1041 /* Fall Through since DCA is disabled. */
1042 case DCA_PROVIDER_REMOVE:
1043 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1044 dca_remove_requester(dev);
1045 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1047 }
1048 break;
1049 }
1050
652f093f 1051 return 0;
bd0362dd
JC		 1052}
1053
5dd2d332 1054#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 1055/**
1056 * ixgbe_receive_skb - Send a completed packet up the stack
1057 * @adapter: board private structure
1058 * @skb: packet to send up
177db6ff
MC		 1059 * @status: hardware indication of status of receive
1060 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1061 * @rx_desc: rx descriptor
9a799d71 1062 **/
78b6f4ce 1063static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1064 struct sk_buff *skb, u8 status,
1065 struct ixgbe_ring *ring,
1066 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1067{
78b6f4ce
HX		 1068 struct ixgbe_adapter *adapter = q_vector->adapter;
1069 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1070 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1071 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1072
f62bbb5e
JG		 1073 if (is_vlan && (tag & VLAN_VID_MASK))
1074 __vlan_hwaccel_put_tag(skb, tag);
1075
1076 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1077 napi_gro_receive(napi, skb);
1078 else
1079 netif_rx(skb);
9a799d71
AK		 1080}
1081
e59bd25d
AV		 1082/**
1083 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1084 * @adapter: address of board private structure
1085 * @status_err: hardware indication of status of receive
1086 * @skb: skb currently being received and modified
1087 **/
9a799d71 1088static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1089 union ixgbe_adv_rx_desc *rx_desc,
1090 struct sk_buff *skb)
9a799d71 1091{
8bae1b2b
DS		 1092 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1093
bc8acf2c 1094 skb_checksum_none_assert(skb);
9a799d71 1095
712744be
JB		 1096 /* Rx csum disabled */
1097 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1098 return;
e59bd25d
AV		 1099
1100 /* if IP and error */
1101 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1102 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1103 adapter->hw_csum_rx_error++;
1104 return;
1105 }
e59bd25d
AV		 1106
1107 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1108 return;
1109
1110 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1111 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1112
1113 /*
1114 * 82599 errata, UDP frames with a 0 checksum can be marked as
1115 * checksum errors.
1116 */
1117 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1118 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1119 return;
1120
e59bd25d
AV		 1121 adapter->hw_csum_rx_error++;
1122 return;
1123 }
1124
9a799d71 1125 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1126 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1127}
1128
84ea2591 1129static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1130{
1131 /*
1132 * Force memory writes to complete before letting h/w
1133 * know there are new descriptors to fetch. (Only
1134 * applicable for weak-ordered memory model archs,
1135 * such as IA-64).
1136 */
1137 wmb();
84ea2591 1138 writel(val, rx_ring->tail);
e8e26350
PW		 1139}
1140
9a799d71
AK		 1141/**
1142 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1143 * @rx_ring: ring to place buffers on
1144 * @cleaned_count: number of buffers to replace
9a799d71 1145 **/
fc77dc3c 1146void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1147{
9a799d71 1148 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1149 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1150 struct sk_buff *skb;
1151 u16 i = rx_ring->next_to_use;
9a799d71 1152
fc77dc3c
AD		 1153 /* do nothing if no valid netdev defined */
1154 if (!rx_ring->netdev)
1155 return;
1156
9a799d71 1157 while (cleaned_count--) {
31f05a2d 1158 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1159 bi = &rx_ring->rx_buffer_info[i];
1160 skb = bi->skb;
9a799d71 1161
d5f398ed 1162 if (!skb) {
fc77dc3c 1163 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1164 rx_ring->rx_buf_len);
9a799d71 1165 if (!skb) {
5b7da515 1166 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1167 goto no_buffers;
1168 }
d716a7d8
AD		 1169 /* initialize queue mapping */
1170 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1171 bi->skb = skb;
d716a7d8 1172 }
9a799d71 1173
d716a7d8 1174 if (!bi->dma) {
b6ec895e 1175 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1176 skb->data,
e8e9f696 1177 rx_ring->rx_buf_len,
1b507730 1178 DMA_FROM_DEVICE);
b6ec895e 1179 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1180 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1181 bi->dma = 0;
1182 goto no_buffers;
1183 }
9a799d71 1184 }
d5f398ed 1185
7d637bcc 1186 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1187 if (!bi->page) {
fc77dc3c 1188 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1189 if (!bi->page) {
5b7da515 1190 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1191 goto no_buffers;
1192 }
1193 }
1194
1195 if (!bi->page_dma) {
1196 /* use a half page if we're re-using */
1197 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1198 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1199 bi->page,
1200 bi->page_offset,
1201 PAGE_SIZE / 2,
1202 DMA_FROM_DEVICE);
b6ec895e 1203 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1204 bi->page_dma)) {
5b7da515 1205 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1206 bi->page_dma = 0;
1207 goto no_buffers;
1208 }
1209 }
1210
1211 /* Refresh the desc even if buffer_addrs didn't change
1212 * because each write-back erases this info. */
3a581073
JB		 1213 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1214 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1215 } else {
3a581073 1216 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1217 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1218 }
1219
1220 i++;
1221 if (i == rx_ring->count)
1222 i = 0;
9a799d71 1223 }
7c6e0a43 1224
9a799d71
AK		 1225no_buffers:
1226 if (rx_ring->next_to_use != i) {
1227 rx_ring->next_to_use = i;
84ea2591 1228 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1229 }
1230}
1231
c267fc16 1232static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1233{
c267fc16
AD		 1234 /* HW will not DMA in data larger than the given buffer, even if it
1235 * parses the (NFS, of course) header to be larger. In that case, it
1236 * fills the header buffer and spills the rest into the page.
1237 */
1238 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1239 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1240 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1241 if (hlen > IXGBE_RX_HDR_SIZE)
1242 hlen = IXGBE_RX_HDR_SIZE;
1243 return hlen;
7c6e0a43
JB		 1244}
1245
f8212f97
AD		 1246/**
1247 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1248 * @skb: pointer to the last skb in the rsc queue
1249 *
1250 * This function changes a queue full of hw rsc buffers into a completed
1251 * packet. It uses the ->prev pointers to find the first packet and then
1252 * turns it into the frag list owner.
1253 **/
aa80175a 1254static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1255{
1256 unsigned int frag_list_size = 0;
aa80175a 1257 unsigned int skb_cnt = 1;
f8212f97
AD		 1258
1259 while (skb->prev) {
1260 struct sk_buff *prev = skb->prev;
1261 frag_list_size += skb->len;
1262 skb->prev = NULL;
1263 skb = prev;
aa80175a 1264 skb_cnt++;
f8212f97
AD		 1265 }
1266
1267 skb_shinfo(skb)->frag_list = skb->next;
1268 skb->next = NULL;
1269 skb->len += frag_list_size;
1270 skb->data_len += frag_list_size;
1271 skb->truesize += frag_list_size;
aa80175a
AD		 1272 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1273
f8212f97
AD		 1274 return skb;
1275}
1276
aa80175a
AD		 1277static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1278{
1279 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1280 IXGBE_RXDADV_RSCCNT_MASK);
1281}
43634e82 1282
c267fc16 1283static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1284 struct ixgbe_ring *rx_ring,
1285 int *work_done, int work_to_do)
9a799d71 1286{
78b6f4ce 1287 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1288 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1289 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1290 struct sk_buff *skb;
d2f4fbe2 1291 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1292 const int current_node = numa_node_id();
3d8fd385
YZ		 1293#ifdef IXGBE_FCOE
1294 int ddp_bytes = 0;
1295#endif /* IXGBE_FCOE */
c267fc16
AD		 1296 u32 staterr;
1297 u16 i;
1298 u16 cleaned_count = 0;
aa80175a 1299 bool pkt_is_rsc = false;
9a799d71
AK		 1300
1301 i = rx_ring->next_to_clean;
31f05a2d 1302 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1303 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1304
1305 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1306 u32 upper_len = 0;
9a799d71 1307
3c945e5b 1308 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1309
c267fc16
AD		 1310 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1311
9a799d71 1312 skb = rx_buffer_info->skb;
9a799d71 1313 rx_buffer_info->skb = NULL;
c267fc16 1314 prefetch(skb->data);
9a799d71 1315
c267fc16 1316 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1317 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1318
1319 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1320 if (rx_buffer_info->dma) {
c267fc16 1321 u16 hlen;
aa80175a 1322 if (pkt_is_rsc &&
c267fc16
AD		 1323 !(staterr & IXGBE_RXD_STAT_EOP) &&
1324 !skb->prev) {
43634e82
MC		 1325 /*
1326 * When HWRSC is enabled, delay unmapping
1327 * of the first packet. It carries the
1328 * header information, HW may still
1329 * access the header after the writeback.
1330 * Only unmap it when EOP is reached
1331 */
e8171aaa 1332 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1333 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1334 } else {
b6ec895e 1335 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1336 rx_buffer_info->dma,
1337 rx_ring->rx_buf_len,
1338 DMA_FROM_DEVICE);
e8171aaa 1339 }
4f57ca6e 1340 rx_buffer_info->dma = 0;
c267fc16
AD		 1341
1342 if (ring_is_ps_enabled(rx_ring)) {
1343 hlen = ixgbe_get_hlen(rx_desc);
1344 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1345 } else {
1346 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1347 }
1348
1349 skb_put(skb, hlen);
1350 } else {
1351 /* assume packet split since header is unmapped */
1352 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1353 }
1354
1355 if (upper_len) {
b6ec895e
AD		 1356 dma_unmap_page(rx_ring->dev,
1357 rx_buffer_info->page_dma,
1358 PAGE_SIZE / 2,
1359 DMA_FROM_DEVICE);
9a799d71
AK		 1360 rx_buffer_info->page_dma = 0;
1361 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1362 rx_buffer_info->page,
1363 rx_buffer_info->page_offset,
1364 upper_len);
762f4c57 1365
c267fc16
AD		 1366 if ((page_count(rx_buffer_info->page) == 1) &&
1367 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1368 get_page(rx_buffer_info->page);
c267fc16
AD		 1369 else
1370 rx_buffer_info->page = NULL;
9a799d71
AK		 1371
1372 skb->len += upper_len;
1373 skb->data_len += upper_len;
1374 skb->truesize += upper_len;
1375 }
1376
1377 i++;
1378 if (i == rx_ring->count)
1379 i = 0;
9a799d71 1380
31f05a2d 1381 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1382 prefetch(next_rxd);
9a799d71 1383 cleaned_count++;
f8212f97 1384
aa80175a 1385 if (pkt_is_rsc) {
f8212f97
AD		 1386 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1387 IXGBE_RXDADV_NEXTP_SHIFT;
1388 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1389 } else {
1390 next_buffer = &rx_ring->rx_buffer_info[i];
1391 }
1392
c267fc16 1393 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1394 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1395 rx_buffer_info->skb = next_buffer->skb;
1396 rx_buffer_info->dma = next_buffer->dma;
1397 next_buffer->skb = skb;
1398 next_buffer->dma = 0;
1399 } else {
1400 skb->next = next_buffer->skb;
1401 skb->next->prev = skb;
1402 }
5b7da515 1403 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1404 goto next_desc;
1405 }
1406
aa80175a
AD		 1407 if (skb->prev) {
1408 skb = ixgbe_transform_rsc_queue(skb);
1409 /* if we got here without RSC the packet is invalid */
1410 if (!pkt_is_rsc) {
1411 __pskb_trim(skb, 0);
1412 rx_buffer_info->skb = skb;
1413 goto next_desc;
1414 }
1415 }
c267fc16
AD		 1416
1417 if (ring_is_rsc_enabled(rx_ring)) {
1418 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1419 dma_unmap_single(rx_ring->dev,
1420 IXGBE_RSC_CB(skb)->dma,
1421 rx_ring->rx_buf_len,
1422 DMA_FROM_DEVICE);
1423 IXGBE_RSC_CB(skb)->dma = 0;
1424 IXGBE_RSC_CB(skb)->delay_unmap = false;
1425 }
aa80175a
AD		 1426 }
1427 if (pkt_is_rsc) {
c267fc16
AD		 1428 if (ring_is_ps_enabled(rx_ring))
1429 rx_ring->rx_stats.rsc_count +=
aa80175a 1430 skb_shinfo(skb)->nr_frags;
c267fc16 1431 else
aa80175a
AD		 1432 rx_ring->rx_stats.rsc_count +=
1433 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1434 rx_ring->rx_stats.rsc_flush++;
1435 }
1436
1437 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1438 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1439 /* trim packet back to size 0 and recycle it */
1440 __pskb_trim(skb, 0);
1441 rx_buffer_info->skb = skb;
9a799d71
AK		 1442 goto next_desc;
1443 }
1444
8bae1b2b 1445 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1446
1447 /* probably a little skewed due to removing CRC */
1448 total_rx_bytes += skb->len;
1449 total_rx_packets++;
1450
fc77dc3c 1451 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1452#ifdef IXGBE_FCOE
1453 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1454 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1455 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1456 if (!ddp_bytes)
332d4a7d 1457 goto next_desc;
3d8fd385 1458 }
332d4a7d 1459#endif /* IXGBE_FCOE */
fdaff1ce 1460 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1461
1462next_desc:
1463 rx_desc->wb.upper.status_error = 0;
1464
c267fc16
AD		 1465 (*work_done)++;
1466 if (*work_done >= work_to_do)
1467 break;
1468
9a799d71
AK		 1469 /* return some buffers to hardware, one at a time is too slow */
1470 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1471 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1472 cleaned_count = 0;
1473 }
1474
1475 /* use prefetched values */
1476 rx_desc = next_rxd;
9a799d71 1477 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1478 }
1479
9a799d71
AK		 1480 rx_ring->next_to_clean = i;
1481 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1482
1483 if (cleaned_count)
fc77dc3c 1484 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1485
3d8fd385
YZ		 1486#ifdef IXGBE_FCOE
1487 /* include DDPed FCoE data */
1488 if (ddp_bytes > 0) {
1489 unsigned int mss;
1490
fc77dc3c 1491 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1492 sizeof(struct fc_frame_header) -
1493 sizeof(struct fcoe_crc_eof);
1494 if (mss > 512)
1495 mss &= ~511;
1496 total_rx_bytes += ddp_bytes;
1497 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1498 }
1499#endif /* IXGBE_FCOE */
1500
f494e8fa
AV		 1501 rx_ring->total_packets += total_rx_packets;
1502 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1503 u64_stats_update_begin(&rx_ring->syncp);
1504 rx_ring->stats.packets += total_rx_packets;
1505 rx_ring->stats.bytes += total_rx_bytes;
1506 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1507}
1508
021230d4 1509static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1510/**
1511 * ixgbe_configure_msix - Configure MSI-X hardware
1512 * @adapter: board private structure
1513 *
1514 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1515 * interrupts.
1516 **/
1517static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1518{
021230d4 1519 struct ixgbe_q_vector *q_vector;
bf29ee6c 1520 int i, q_vectors, v_idx, r_idx;
021230d4 1521 u32 mask;
9a799d71 1522
021230d4 1523 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1524
4df10466
JB		 1525 /*
1526 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1527 * corresponding register.
1528 */
1529 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1530 q_vector = adapter->q_vector[v_idx];
984b3f57 1531 /* XXX for_each_set_bit(...) */
021230d4 1532 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1533 adapter->num_rx_queues);
021230d4
AV		 1534
1535 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1536 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1537 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1538 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1539 adapter->num_rx_queues,
1540 r_idx + 1);
021230d4
AV		 1541 }
1542 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1543 adapter->num_tx_queues);
021230d4
AV		 1544
1545 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1546 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1547 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1548 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1549 adapter->num_tx_queues,
1550 r_idx + 1);
021230d4
AV		 1551 }
1552
021230d4 1553 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1554 /* tx only */
1555 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1556 else if (q_vector->rxr_count)
f7554a2b
NS		 1557 /* rx or mixed */
1558 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1559
fe49f04a 1560 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1561 /* If Flow Director is enabled, set interrupt affinity */
1562 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1563 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1564 /*
1565 * Allocate the affinity_hint cpumask, assign the mask
1566 * for this vector, and set our affinity_hint for
1567 * this irq.
1568 */
1569 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1570 GFP_KERNEL))
1571 return;
1572 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1573 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1574 q_vector->affinity_mask);
1575 }
9a799d71
AK		 1576 }
1577
bd508178
AD		 1578 switch (adapter->hw.mac.type) {
1579 case ixgbe_mac_82598EB:
e8e26350 1580 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1581 v_idx);
bd508178
AD		 1582 break;
1583 case ixgbe_mac_82599EB:
e8e26350 1584 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1585 break;
1586
1587 default:
1588 break;
1589 }
021230d4
AV		 1590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1591
41fb9248 1592 /* set up to autoclear timer, and the vectors */
021230d4 1593 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1594 if (adapter->num_vfs)
1595 mask &= ~(IXGBE_EIMS_OTHER |
1596 IXGBE_EIMS_MAILBOX |
1597 IXGBE_EIMS_LSC);
1598 else
1599 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1601}
1602
f494e8fa
AV		 1603enum latency_range {
1604 lowest_latency = 0,
1605 low_latency = 1,
1606 bulk_latency = 2,
1607 latency_invalid = 255
1608};
1609
1610/**
1611 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1612 * @adapter: pointer to adapter
1613 * @eitr: eitr setting (ints per sec) to give last timeslice
1614 * @itr_setting: current throttle rate in ints/second
1615 * @packets: the number of packets during this measurement interval
1616 * @bytes: the number of bytes during this measurement interval
1617 *
1618 * Stores a new ITR value based on packets and byte
1619 * counts during the last interrupt. The advantage of per interrupt
1620 * computation is faster updates and more accurate ITR for the current
1621 * traffic pattern. Constants in this function were computed
1622 * based on theoretical maximum wire speed and thresholds were set based
1623 * on testing data as well as attempting to minimize response time
1624 * while increasing bulk throughput.
1625 * this functionality is controlled by the InterruptThrottleRate module
1626 * parameter (see ixgbe_param.c)
1627 **/
1628static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1629 u32 eitr, u8 itr_setting,
1630 int packets, int bytes)
f494e8fa
AV		 1631{
1632 unsigned int retval = itr_setting;
1633 u32 timepassed_us;
1634 u64 bytes_perint;
1635
1636 if (packets == 0)
1637 goto update_itr_done;
1638
1639
1640 /* simple throttlerate management
1641 * 0-20MB/s lowest (100000 ints/s)
1642 * 20-100MB/s low (20000 ints/s)
1643 * 100-1249MB/s bulk (8000 ints/s)
1644 */
1645 /* what was last interrupt timeslice? */
1646 timepassed_us = 1000000/eitr;
1647 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1648
1649 switch (itr_setting) {
1650 case lowest_latency:
1651 if (bytes_perint > adapter->eitr_low)
1652 retval = low_latency;
1653 break;
1654 case low_latency:
1655 if (bytes_perint > adapter->eitr_high)
1656 retval = bulk_latency;
1657 else if (bytes_perint <= adapter->eitr_low)
1658 retval = lowest_latency;
1659 break;
1660 case bulk_latency:
1661 if (bytes_perint <= adapter->eitr_high)
1662 retval = low_latency;
1663 break;
1664 }
1665
1666update_itr_done:
1667 return retval;
1668}
1669
509ee935
JB		 1670/**
1671 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1672 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1673 *
1674 * This function is made to be called by ethtool and by the driver
1675 * when it needs to update EITR registers at runtime. Hardware
1676 * specific quirks/differences are taken care of here.
1677 */
fe49f04a 1678void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1679{
fe49f04a 1680 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1681 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1682 int v_idx = q_vector->v_idx;
1683 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1684
bd508178
AD		 1685 switch (adapter->hw.mac.type) {
1686 case ixgbe_mac_82598EB:
509ee935
JB		 1687 /* must write high and low 16 bits to reset counter */
1688 itr_reg |= (itr_reg << 16);
bd508178
AD		 1689 break;
1690 case ixgbe_mac_82599EB:
f8d1dcaf
JB		 1691 /*
1692 * 82599 can support a value of zero, so allow it for
1693 * max interrupt rate, but there is an errata where it can
1694 * not be zero with RSC
1695 */
1696 if (itr_reg == 8 &&
1697 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1698 itr_reg = 0;
1699
509ee935
JB		 1700 /*
1701 * set the WDIS bit to not clear the timer bits and cause an
1702 * immediate assertion of the interrupt
1703 */
1704 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1705 break;
1706 default:
1707 break;
509ee935
JB		 1708 }
1709 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1710}
1711
f494e8fa
AV		 1712static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1713{
1714 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1715 int i, r_idx;
f494e8fa
AV		 1716 u32 new_itr;
1717 u8 current_itr, ret_itr;
f494e8fa
AV		 1718
1719 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1720 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1721 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1722 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1723 q_vector->tx_itr,
1724 tx_ring->total_packets,
1725 tx_ring->total_bytes);
f494e8fa
AV		 1726 /* if the result for this queue would decrease interrupt
1727 * rate for this vector then use that result */
30efa5a3 1728 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1729 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1730 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1731 r_idx + 1);
f494e8fa
AV		 1732 }
1733
1734 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1735 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1736 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1737 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1738 q_vector->rx_itr,
1739 rx_ring->total_packets,
1740 rx_ring->total_bytes);
f494e8fa
AV		 1741 /* if the result for this queue would decrease interrupt
1742 * rate for this vector then use that result */
30efa5a3 1743 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1744 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1745 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1746 r_idx + 1);
f494e8fa
AV		 1747 }
1748
30efa5a3 1749 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1750
1751 switch (current_itr) {
1752 /* counts and packets in update_itr are dependent on these numbers */
1753 case lowest_latency:
1754 new_itr = 100000;
1755 break;
1756 case low_latency:
1757 new_itr = 20000; /* aka hwitr = ~200 */
1758 break;
1759 case bulk_latency:
1760 default:
1761 new_itr = 8000;
1762 break;
1763 }
1764
1765 if (new_itr != q_vector->eitr) {
fe49f04a 1766 /* do an exponential smoothing */
125601bf 1767 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1768
1769 /* save the algorithm value here, not the smoothed one */
1770 q_vector->eitr = new_itr;
fe49f04a
AD		 1771
1772 ixgbe_write_eitr(q_vector);
f494e8fa 1773 }
f494e8fa
AV		 1774}
1775
119fc60a
MC		 1776/**
1777 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1778 * @work: pointer to work_struct containing our data
1779 **/
1780static void ixgbe_check_overtemp_task(struct work_struct *work)
1781{
1782 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1783 struct ixgbe_adapter,
1784 check_overtemp_task);
119fc60a
MC		 1785 struct ixgbe_hw *hw = &adapter->hw;
1786 u32 eicr = adapter->interrupt_event;
1787
7ca647bd
JP		 1788 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1789 return;
1790
1791 switch (hw->device_id) {
1792 case IXGBE_DEV_ID_82599_T3_LOM: {
1793 u32 autoneg;
1794 bool link_up = false;
1795
1796 if (hw->mac.ops.check_link)
1797 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1798
1799 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1800 (eicr & IXGBE_EICR_LSC))
1801 /* Check if this is due to overtemp */
1802 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1803 break;
1804 return;
1805 }
1806 default:
1807 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1808 return;
7ca647bd 1809 break;
119fc60a 1810 }
7ca647bd
JP		 1811 e_crit(drv,
1812 "Network adapter has been stopped because it has over heated. "
1813 "Restart the computer. If the problem persists, "
1814 "power off the system and replace the adapter\n");
1815 /* write to clear the interrupt */
1816 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1817}
1818
0befdb3e
JB		 1819static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1820{
1821 struct ixgbe_hw *hw = &adapter->hw;
1822
1823 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1824 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1825 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1826 /* write to clear the interrupt */
1827 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1828 }
1829}
cf8280ee 1830
e8e26350
PW		 1831static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1832{
1833 struct ixgbe_hw *hw = &adapter->hw;
1834
73c4b7cd
AD		 1835 if (eicr & IXGBE_EICR_GPI_SDP2) {
1836 /* Clear the interrupt */
1837 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1838 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1839 schedule_work(&adapter->sfp_config_module_task);
1840 }
1841
e8e26350
PW		 1842 if (eicr & IXGBE_EICR_GPI_SDP1) {
1843 /* Clear the interrupt */
1844 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
73c4b7cd
AD		 1845 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1846 schedule_work(&adapter->multispeed_fiber_task);
e8e26350
PW		 1847 }
1848}
1849
cf8280ee
JB		 1850static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1851{
1852 struct ixgbe_hw *hw = &adapter->hw;
1853
1854 adapter->lsc_int++;
1855 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1856 adapter->link_check_timeout = jiffies;
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1858 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1859 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1860 schedule_work(&adapter->watchdog_task);
1861 }
1862}
1863
9a799d71
AK		 1864static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1865{
1866 struct net_device *netdev = data;
1867 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1868 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1869 u32 eicr;
1870
1871 /*
1872 * Workaround for Silicon errata. Use clear-by-write instead
1873 * of clear-by-read. Reading with EICS will return the
1874 * interrupt causes without clearing, which later be done
1875 * with the write to EICR.
1876 */
1877 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1878 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1879
cf8280ee
JB		 1880 if (eicr & IXGBE_EICR_LSC)
1881 ixgbe_check_lsc(adapter);
d4f80882 1882
1cdd1ec8
GR		 1883 if (eicr & IXGBE_EICR_MAILBOX)
1884 ixgbe_msg_task(adapter);
1885
bd508178
AD		 1886 switch (hw->mac.type) {
1887 case ixgbe_mac_82599EB:
c4cf55e5
PWJ		 1888 /* Handle Flow Director Full threshold interrupt */
1889 if (eicr & IXGBE_EICR_FLOW_DIR) {
1890 int i;
1891 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1892 /* Disable transmits before FDIR Re-initialization */
1893 netif_tx_stop_all_queues(netdev);
1894 for (i = 0; i < adapter->num_tx_queues; i++) {
1895 struct ixgbe_ring *tx_ring =
e8e9f696 1896 adapter->tx_ring[i];
7d637bcc
AD		 1897 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1898 &tx_ring->state))
c4cf55e5
PWJ		 1899 schedule_work(&adapter->fdir_reinit_task);
1900 }
1901 }
bd508178
AD		 1902 ixgbe_check_sfp_event(adapter, eicr);
1903 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1904 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1905 adapter->interrupt_event = eicr;
1906 schedule_work(&adapter->check_overtemp_task);
1907 }
1908 break;
1909 default:
1910 break;
c4cf55e5 1911 }
bd508178
AD		 1912
1913 ixgbe_check_fan_failure(adapter, eicr);
1914
d4f80882
AV		 1915 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1916 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1917
1918 return IRQ_HANDLED;
1919}
1920
fe49f04a
AD		 1921static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1922 u64 qmask)
1923{
1924 u32 mask;
bd508178 1925 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1926
bd508178
AD		 1927 switch (hw->mac.type) {
1928 case ixgbe_mac_82598EB:
fe49f04a 1929 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1930 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1931 break;
1932 case ixgbe_mac_82599EB:
fe49f04a 1933 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1934 if (mask)
1935 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1936 mask = (qmask >> 32);
bd508178
AD		 1937 if (mask)
1938 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1939 break;
1940 default:
1941 break;
fe49f04a
AD		 1942 }
1943 /* skip the flush */
1944}
1945
1946static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1947 u64 qmask)
fe49f04a
AD		 1948{
1949 u32 mask;
bd508178 1950 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1951
bd508178
AD		 1952 switch (hw->mac.type) {
1953 case ixgbe_mac_82598EB:
fe49f04a 1954 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1955 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1956 break;
1957 case ixgbe_mac_82599EB:
fe49f04a 1958 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1959 if (mask)
1960 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1961 mask = (qmask >> 32);
bd508178
AD		 1962 if (mask)
1963 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1964 break;
1965 default:
1966 break;
fe49f04a
AD		 1967 }
1968 /* skip the flush */
1969}
1970
9a799d71
AK		 1971static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1972{
021230d4
AV		 1973 struct ixgbe_q_vector *q_vector = data;
1974 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1975 struct ixgbe_ring *tx_ring;
021230d4
AV		 1976 int i, r_idx;
1977
1978 if (!q_vector->txr_count)
1979 return IRQ_HANDLED;
1980
1981 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1982 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1983 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1984 tx_ring->total_bytes = 0;
1985 tx_ring->total_packets = 0;
021230d4 1986 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1987 r_idx + 1);
021230d4 1988 }
9a799d71 1989
9b471446 1990 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1991 napi_schedule(&q_vector->napi);
1992
9a799d71
AK		 1993 return IRQ_HANDLED;
1994}
1995
021230d4
AV		 1996/**
1997 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1998 * @irq: unused
1999 * @data: pointer to our q_vector struct for this interrupt vector
2000 **/
9a799d71
AK		 2001static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2002{
021230d4
AV		 2003 struct ixgbe_q_vector *q_vector = data;
2004 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2005 struct ixgbe_ring *rx_ring;
021230d4 2006 int r_idx;
30efa5a3 2007 int i;
021230d4 2008
33cf09c9
AD		 2009#ifdef CONFIG_IXGBE_DCA
2010 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2011 ixgbe_update_dca(q_vector);
2012#endif
2013
021230d4 2014 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2015 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2016 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2017 rx_ring->total_bytes = 0;
2018 rx_ring->total_packets = 0;
2019 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2020 r_idx + 1);
30efa5a3
JB		 2021 }
2022
021230d4
AV		 2023 if (!q_vector->rxr_count)
2024 return IRQ_HANDLED;
2025
9b471446 2026 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2027 napi_schedule(&q_vector->napi);
021230d4
AV		 2028
2029 return IRQ_HANDLED;
2030}
2031
2032static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2033{
91281fd3
AD		 2034 struct ixgbe_q_vector *q_vector = data;
2035 struct ixgbe_adapter *adapter = q_vector->adapter;
2036 struct ixgbe_ring *ring;
2037 int r_idx;
2038 int i;
2039
2040 if (!q_vector->txr_count && !q_vector->rxr_count)
2041 return IRQ_HANDLED;
2042
2043 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2044 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2045 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2046 ring->total_bytes = 0;
2047 ring->total_packets = 0;
2048 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2049 r_idx + 1);
91281fd3
AD		 2050 }
2051
2052 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2053 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2054 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2055 ring->total_bytes = 0;
2056 ring->total_packets = 0;
2057 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2058 r_idx + 1);
91281fd3
AD		 2059 }
2060
9b471446 2061 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2062 napi_schedule(&q_vector->napi);
9a799d71 2063
9a799d71
AK		 2064 return IRQ_HANDLED;
2065}
2066
021230d4
AV		 2067/**
2068 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2069 * @napi: napi struct with our devices info in it
2070 * @budget: amount of work driver is allowed to do this pass, in packets
2071 *
f0848276
JB		 2072 * This function is optimized for cleaning one queue only on a single
2073 * q_vector!!!
021230d4 2074 **/
9a799d71
AK		 2075static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2076{
021230d4 2077 struct ixgbe_q_vector *q_vector =
e8e9f696 2078 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2079 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2080 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2081 int work_done = 0;
021230d4 2082 long r_idx;
9a799d71 2083
5dd2d332 2084#ifdef CONFIG_IXGBE_DCA
bd0362dd 2085 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2086 ixgbe_update_dca(q_vector);
bd0362dd 2087#endif
9a799d71 2088
33cf09c9
AD		 2089 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2090 rx_ring = adapter->rx_ring[r_idx];
2091
78b6f4ce 2092 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2093
021230d4
AV		 2094 /* If all Rx work done, exit the polling mode */
2095 if (work_done < budget) {
288379f0 2096 napi_complete(napi);
f7554a2b 2097 if (adapter->rx_itr_setting & 1)
f494e8fa 2098 ixgbe_set_itr_msix(q_vector);
9a799d71 2099 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2100 ixgbe_irq_enable_queues(adapter,
e8e9f696 2101 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2102 }
2103
2104 return work_done;
2105}
2106
f0848276 2107/**
91281fd3 2108 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2109 * @napi: napi struct with our devices info in it
2110 * @budget: amount of work driver is allowed to do this pass, in packets
2111 *
2112 * This function will clean more than one rx queue associated with a
2113 * q_vector.
2114 **/
91281fd3 2115static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2116{
2117 struct ixgbe_q_vector *q_vector =
e8e9f696 2118 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2119 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2120 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2121 int work_done = 0, i;
2122 long r_idx;
91281fd3
AD		 2123 bool tx_clean_complete = true;
2124
33cf09c9
AD		 2125#ifdef CONFIG_IXGBE_DCA
2126 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2127 ixgbe_update_dca(q_vector);
2128#endif
2129
91281fd3
AD		 2130 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2131 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2132 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2133 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2134 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2135 r_idx + 1);
91281fd3 2136 }
f0848276
JB		 2137
2138 /* attempt to distribute budget to each queue fairly, but don't allow
2139 * the budget to go below 1 because we'll exit polling */
2140 budget /= (q_vector->rxr_count ?: 1);
2141 budget = max(budget, 1);
2142 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2143 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2144 ring = adapter->rx_ring[r_idx];
91281fd3 2145 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2146 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2147 r_idx + 1);
f0848276
JB		 2148 }
2149
2150 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2151 ring = adapter->rx_ring[r_idx];
f0848276 2152 /* If all Rx work done, exit the polling mode */
7f821875 2153 if (work_done < budget) {
288379f0 2154 napi_complete(napi);
f7554a2b 2155 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2156 ixgbe_set_itr_msix(q_vector);
2157 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2158 ixgbe_irq_enable_queues(adapter,
e8e9f696 2159 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2160 return 0;
2161 }
2162
2163 return work_done;
2164}
91281fd3
AD		 2165
2166/**
2167 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2168 * @napi: napi struct with our devices info in it
2169 * @budget: amount of work driver is allowed to do this pass, in packets
2170 *
2171 * This function is optimized for cleaning one queue only on a single
2172 * q_vector!!!
2173 **/
2174static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2175{
2176 struct ixgbe_q_vector *q_vector =
e8e9f696 2177 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2178 struct ixgbe_adapter *adapter = q_vector->adapter;
2179 struct ixgbe_ring *tx_ring = NULL;
2180 int work_done = 0;
2181 long r_idx;
2182
91281fd3
AD		 2183#ifdef CONFIG_IXGBE_DCA
2184 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2185 ixgbe_update_dca(q_vector);
91281fd3
AD		 2186#endif
2187
33cf09c9
AD		 2188 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2189 tx_ring = adapter->tx_ring[r_idx];
2190
91281fd3
AD		 2191 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2192 work_done = budget;
2193
f7554a2b 2194 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2195 if (work_done < budget) {
2196 napi_complete(napi);
f7554a2b 2197 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2198 ixgbe_set_itr_msix(q_vector);
2199 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2200 ixgbe_irq_enable_queues(adapter,
2201 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2202 }
2203
2204 return work_done;
2205}
2206
021230d4 2207static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2208 int r_idx)
021230d4 2209{
7a921c93 2210 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2211 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2212
2213 set_bit(r_idx, q_vector->rxr_idx);
2214 q_vector->rxr_count++;
2274543f 2215 rx_ring->q_vector = q_vector;
021230d4
AV		 2216}
2217
2218static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2219 int t_idx)
021230d4 2220{
7a921c93 2221 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2222 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2223
2224 set_bit(t_idx, q_vector->txr_idx);
2225 q_vector->txr_count++;
2274543f 2226 tx_ring->q_vector = q_vector;
021230d4
AV		 2227}
2228
9a799d71 2229/**
021230d4
AV		 2230 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2231 * @adapter: board private structure to initialize
9a799d71 2232 *
021230d4
AV		 2233 * This function maps descriptor rings to the queue-specific vectors
2234 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2235 * one vector per ring/queue, but on a constrained vector budget, we
2236 * group the rings as "efficiently" as possible. You would add new
2237 * mapping configurations in here.
9a799d71 2238 **/
d0759ebb 2239static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2240{
d0759ebb 2241 int q_vectors;
021230d4
AV		 2242 int v_start = 0;
2243 int rxr_idx = 0, txr_idx = 0;
2244 int rxr_remaining = adapter->num_rx_queues;
2245 int txr_remaining = adapter->num_tx_queues;
2246 int i, j;
2247 int rqpv, tqpv;
2248 int err = 0;
2249
2250 /* No mapping required if MSI-X is disabled. */
2251 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2252 goto out;
9a799d71 2253
d0759ebb
AD		 2254 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2255
021230d4
AV		 2256 /*
2257 * The ideal configuration...
2258 * We have enough vectors to map one per queue.
2259 */
d0759ebb 2260 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2261 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2262 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2263
021230d4
AV		 2264 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2265 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2266
9a799d71 2267 goto out;
021230d4 2268 }
9a799d71 2269
021230d4
AV		 2270 /*
2271 * If we don't have enough vectors for a 1-to-1
2272 * mapping, we'll have to group them so there are
2273 * multiple queues per vector.
2274 */
2275 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2276 for (i = v_start; i < q_vectors; i++) {
2277 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2278 for (j = 0; j < rqpv; j++) {
2279 map_vector_to_rxq(adapter, i, rxr_idx);
2280 rxr_idx++;
2281 rxr_remaining--;
2282 }
d0759ebb 2283 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2284 for (j = 0; j < tqpv; j++) {
2285 map_vector_to_txq(adapter, i, txr_idx);
2286 txr_idx++;
2287 txr_remaining--;
9a799d71 2288 }
9a799d71 2289 }
021230d4
AV		 2290out:
2291 return err;
2292}
2293
2294/**
2295 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2296 * @adapter: board private structure
2297 *
2298 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2299 * interrupts from the kernel.
2300 **/
2301static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2302{
2303 struct net_device *netdev = adapter->netdev;
2304 irqreturn_t (*handler)(int, void *);
2305 int i, vector, q_vectors, err;
e8e9f696 2306 int ri = 0, ti = 0;
021230d4
AV		 2307
2308 /* Decrement for Other and TCP Timer vectors */
2309 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2310
d0759ebb 2311 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2312 if (err)
d0759ebb 2313 return err;
021230d4 2314
d0759ebb
AD		 2315#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2316 ? &ixgbe_msix_clean_many : \
2317 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2318 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2319 NULL)
021230d4 2320 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2321 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2322 handler = SET_HANDLER(q_vector);
cb13fc20 2323
e8e9f696 2324 if (handler == &ixgbe_msix_clean_rx) {
d0759ebb 2325 sprintf(q_vector->name, "%s-%s-%d",
cb13fc20 2326 netdev->name, "rx", ri++);
e8e9f696 2327 } else if (handler == &ixgbe_msix_clean_tx) {
d0759ebb 2328 sprintf(q_vector->name, "%s-%s-%d",
cb13fc20 2329 netdev->name, "tx", ti++);
d0759ebb
AD		 2330 } else if (handler == &ixgbe_msix_clean_many) {
2331 sprintf(q_vector->name, "%s-%s-%d",
32aa77a4
AD		 2332 netdev->name, "TxRx", ri++);
2333 ti++;
d0759ebb
AD		 2334 } else {
2335 /* skip this unused q_vector */
2336 continue;
32aa77a4 2337 }
021230d4 2338 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2339 handler, 0, q_vector->name,
2340 q_vector);
9a799d71 2341 if (err) {
396e799c 2342 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2343 "Error: %d\n", err);
021230d4 2344 goto free_queue_irqs;
9a799d71 2345 }
9a799d71
AK		 2346 }
2347
d0759ebb 2348 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2349 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2350 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2351 if (err) {
396e799c 2352 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2353 goto free_queue_irqs;
9a799d71
AK		 2354 }
2355
9a799d71
AK		 2356 return 0;
2357
021230d4
AV		 2358free_queue_irqs:
2359 for (i = vector - 1; i >= 0; i--)
2360 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2361 adapter->q_vector[i]);
021230d4
AV		 2362 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2363 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2364 kfree(adapter->msix_entries);
2365 adapter->msix_entries = NULL;
9a799d71
AK		 2366 return err;
2367}
2368
f494e8fa
AV		 2369static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2370{
7a921c93 2371 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2372 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2373 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2374 u32 new_itr = q_vector->eitr;
2375 u8 current_itr;
f494e8fa 2376
30efa5a3 2377 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2378 q_vector->tx_itr,
2379 tx_ring->total_packets,
2380 tx_ring->total_bytes);
30efa5a3 2381 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2382 q_vector->rx_itr,
2383 rx_ring->total_packets,
2384 rx_ring->total_bytes);
f494e8fa 2385
30efa5a3 2386 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2387
2388 switch (current_itr) {
2389 /* counts and packets in update_itr are dependent on these numbers */
2390 case lowest_latency:
2391 new_itr = 100000;
2392 break;
2393 case low_latency:
2394 new_itr = 20000; /* aka hwitr = ~200 */
2395 break;
2396 case bulk_latency:
2397 new_itr = 8000;
2398 break;
2399 default:
2400 break;
2401 }
2402
2403 if (new_itr != q_vector->eitr) {
fe49f04a 2404 /* do an exponential smoothing */
125601bf 2405 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2406
125601bf 2407 /* save the algorithm value here */
509ee935 2408 q_vector->eitr = new_itr;
fe49f04a
AD		 2409
2410 ixgbe_write_eitr(q_vector);
f494e8fa 2411 }
f494e8fa
AV		 2412}
2413
79aefa45
AD		 2414/**
2415 * ixgbe_irq_enable - Enable default interrupt generation settings
2416 * @adapter: board private structure
2417 **/
6af3b9eb
ET		 2418static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2419 bool flush)
79aefa45
AD		 2420{
2421 u32 mask;
835462fc
NS		 2422
2423 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2424 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2425 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2426 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2427 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2428 switch (adapter->hw.mac.type) {
2429 case ixgbe_mac_82599EB:
2a41ff81 2430 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2431 mask |= IXGBE_EIMS_GPI_SDP1;
2432 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2433 if (adapter->num_vfs)
2434 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2435 break;
2436 default:
2437 break;
e8e26350 2438 }
c4cf55e5
PWJ		 2439 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2440 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2441 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2442
79aefa45 2443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2444 if (queues)
2445 ixgbe_irq_enable_queues(adapter, ~0);
2446 if (flush)
2447 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2448
2449 if (adapter->num_vfs > 32) {
2450 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2452 }
79aefa45 2453}
021230d4 2454
9a799d71 2455/**
021230d4 2456 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2457 * @irq: interrupt number
2458 * @data: pointer to a network interface device structure
9a799d71
AK		 2459 **/
2460static irqreturn_t ixgbe_intr(int irq, void *data)
2461{
2462 struct net_device *netdev = data;
2463 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2464 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2465 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2466 u32 eicr;
2467
54037505 2468 /*
6af3b9eb 2469 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2470 * before the read of EICR.
2471 */
2472 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2473
021230d4
AV		 2474 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2475 * therefore no explict interrupt disable is necessary */
2476 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2477 if (!eicr) {
6af3b9eb
ET		 2478 /*
2479 * shared interrupt alert!
f47cf66e 2480 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2481 * have disabled interrupts due to EIAM
2482 * finish the workaround of silicon errata on 82598. Unmask
2483 * the interrupt that we masked before the EICR read.
2484 */
2485 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2486 ixgbe_irq_enable(adapter, true, true);
9a799d71 2487 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2488 }
9a799d71 2489
cf8280ee
JB		 2490 if (eicr & IXGBE_EICR_LSC)
2491 ixgbe_check_lsc(adapter);
021230d4 2492
bd508178
AD		 2493 switch (hw->mac.type) {
2494 case ixgbe_mac_82599EB:
e8e26350 2495 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2496 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2497 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2498 adapter->interrupt_event = eicr;
2499 schedule_work(&adapter->check_overtemp_task);
2500 }
2501 break;
2502 default:
2503 break;
2504 }
e8e26350 2505
0befdb3e
JB		 2506 ixgbe_check_fan_failure(adapter, eicr);
2507
7a921c93 2508 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2509 adapter->tx_ring[0]->total_packets = 0;
2510 adapter->tx_ring[0]->total_bytes = 0;
2511 adapter->rx_ring[0]->total_packets = 0;
2512 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2513 /* would disable interrupts here but EIAM disabled it */
7a921c93 2514 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2515 }
2516
6af3b9eb
ET		 2517 /*
2518 * re-enable link(maybe) and non-queue interrupts, no flush.
2519 * ixgbe_poll will re-enable the queue interrupts
2520 */
2521
2522 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2523 ixgbe_irq_enable(adapter, false, false);
2524
9a799d71
AK		 2525 return IRQ_HANDLED;
2526}
2527
021230d4
AV		 2528static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2529{
2530 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2531
2532 for (i = 0; i < q_vectors; i++) {
7a921c93 2533 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2534 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2535 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2536 q_vector->rxr_count = 0;
2537 q_vector->txr_count = 0;
2538 }
2539}
2540
9a799d71
AK		 2541/**
2542 * ixgbe_request_irq - initialize interrupts
2543 * @adapter: board private structure
2544 *
2545 * Attempts to configure interrupts using the best available
2546 * capabilities of the hardware and kernel.
2547 **/
021230d4 2548static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2549{
2550 struct net_device *netdev = adapter->netdev;
021230d4 2551 int err;
9a799d71 2552
021230d4
AV		 2553 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2554 err = ixgbe_request_msix_irqs(adapter);
2555 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2556 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2557 netdev->name, netdev);
021230d4 2558 } else {
a0607fd3 2559 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2560 netdev->name, netdev);
9a799d71
AK		 2561 }
2562
9a799d71 2563 if (err)
396e799c 2564 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2565
9a799d71
AK		 2566 return err;
2567}
2568
2569static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2570{
2571 struct net_device *netdev = adapter->netdev;
2572
2573 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2574 int i, q_vectors;
9a799d71 2575
021230d4
AV		 2576 q_vectors = adapter->num_msix_vectors;
2577
2578 i = q_vectors - 1;
9a799d71 2579 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2580
021230d4
AV		 2581 i--;
2582 for (; i >= 0; i--) {
2583 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2584 adapter->q_vector[i]);
021230d4
AV		 2585 }
2586
2587 ixgbe_reset_q_vectors(adapter);
2588 } else {
2589 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2590 }
2591}
2592
22d5a71b
JB		 2593/**
2594 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2595 * @adapter: board private structure
2596 **/
2597static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2598{
bd508178
AD		 2599 switch (adapter->hw.mac.type) {
2600 case ixgbe_mac_82598EB:
835462fc 2601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2602 break;
2603 case ixgbe_mac_82599EB:
835462fc
NS		 2604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2607 if (adapter->num_vfs > 32)
2608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2609 break;
2610 default:
2611 break;
22d5a71b
JB		 2612 }
2613 IXGBE_WRITE_FLUSH(&adapter->hw);
2614 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2615 int i;
2616 for (i = 0; i < adapter->num_msix_vectors; i++)
2617 synchronize_irq(adapter->msix_entries[i].vector);
2618 } else {
2619 synchronize_irq(adapter->pdev->irq);
2620 }
2621}
2622
9a799d71
AK		 2623/**
2624 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2625 *
2626 **/
2627static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2628{
9a799d71
AK		 2629 struct ixgbe_hw *hw = &adapter->hw;
2630
021230d4 2631 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2632 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2633
e8e26350
PW		 2634 ixgbe_set_ivar(adapter, 0, 0, 0);
2635 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2636
2637 map_vector_to_rxq(adapter, 0, 0);
2638 map_vector_to_txq(adapter, 0, 0);
2639
396e799c 2640 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2641}
2642
43e69bf0
AD		 2643/**
2644 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2645 * @adapter: board private structure
2646 * @ring: structure containing ring specific data
2647 *
2648 * Configure the Tx descriptor ring after a reset.
2649 **/
84418e3b
AD		 2650void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2651 struct ixgbe_ring *ring)
43e69bf0
AD		 2652{
2653 struct ixgbe_hw *hw = &adapter->hw;
2654 u64 tdba = ring->dma;
2f1860b8
AD		 2655 int wait_loop = 10;
2656 u32 txdctl;
bf29ee6c 2657 u8 reg_idx = ring->reg_idx;
43e69bf0 2658
2f1860b8
AD		 2659 /* disable queue to avoid issues while updating state */
2660 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2661 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2662 txdctl & ~IXGBE_TXDCTL_ENABLE);
2663 IXGBE_WRITE_FLUSH(hw);
2664
43e69bf0 2665 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2666 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2667 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2668 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2669 ring->count * sizeof(union ixgbe_adv_tx_desc));
2670 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2671 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2672 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2673
2f1860b8
AD		 2674 /* configure fetching thresholds */
2675 if (adapter->rx_itr_setting == 0) {
2676 /* cannot set wthresh when itr==0 */
2677 txdctl &= ~0x007F0000;
2678 } else {
2679 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2680 txdctl |= (8 << 16);
2681 }
2682 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2683 /* PThresh workaround for Tx hang with DFP enabled. */
2684 txdctl |= 32;
2685 }
2686
2687 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2688 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2689 adapter->atr_sample_rate) {
2690 ring->atr_sample_rate = adapter->atr_sample_rate;
2691 ring->atr_count = 0;
2692 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2693 } else {
2694 ring->atr_sample_rate = 0;
2695 }
2f1860b8 2696
c84d324c
JF		 2697 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2698
2f1860b8
AD		 2699 /* enable queue */
2700 txdctl |= IXGBE_TXDCTL_ENABLE;
2701 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2702
2703 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2704 if (hw->mac.type == ixgbe_mac_82598EB &&
2705 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2706 return;
2707
2708 /* poll to verify queue is enabled */
2709 do {
2710 msleep(1);
2711 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2712 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2713 if (!wait_loop)
2714 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2715}
2716
120ff942
AD		 2717static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2718{
2719 struct ixgbe_hw *hw = &adapter->hw;
2720 u32 rttdcs;
2721 u32 mask;
2722
2723 if (hw->mac.type == ixgbe_mac_82598EB)
2724 return;
2725
2726 /* disable the arbiter while setting MTQC */
2727 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2728 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2729 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2730
2731 /* set transmit pool layout */
2732 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2733 switch (adapter->flags & mask) {
2734
2735 case (IXGBE_FLAG_SRIOV_ENABLED):
2736 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2737 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2738 break;
2739
2740 case (IXGBE_FLAG_DCB_ENABLED):
2741 /* We enable 8 traffic classes, DCB only */
2742 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2743 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2744 break;
2745
2746 default:
2747 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2748 break;
2749 }
2750
2751 /* re-enable the arbiter */
2752 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2753 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2754}
2755
9a799d71 2756/**
3a581073 2757 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2758 * @adapter: board private structure
2759 *
2760 * Configure the Tx unit of the MAC after a reset.
2761 **/
2762static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2763{
2f1860b8
AD		 2764 struct ixgbe_hw *hw = &adapter->hw;
2765 u32 dmatxctl;
43e69bf0 2766 u32 i;
9a799d71 2767
2f1860b8
AD		 2768 ixgbe_setup_mtqc(adapter);
2769
2770 if (hw->mac.type != ixgbe_mac_82598EB) {
2771 /* DMATXCTL.EN must be before Tx queues are enabled */
2772 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2773 dmatxctl |= IXGBE_DMATXCTL_TE;
2774 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2775 }
2776
9a799d71 2777 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2778 for (i = 0; i < adapter->num_tx_queues; i++)
2779 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2780}
2781
e8e26350 2782#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2783
a6616b42 2784static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2785 struct ixgbe_ring *rx_ring)
cc41ac7c 2786{
cc41ac7c 2787 u32 srrctl;
bf29ee6c 2788 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2789
bd508178
AD		 2790 switch (adapter->hw.mac.type) {
2791 case ixgbe_mac_82598EB: {
2792 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2793 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2794 reg_idx = reg_idx & mask;
cc41ac7c 2795 }
bd508178
AD		 2796 break;
2797 case ixgbe_mac_82599EB:
2798 default:
2799 break;
2800 }
2801
bf29ee6c 2802 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2803
2804 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2805 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2806 if (adapter->num_vfs)
2807 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2808
afafd5b0
AD		 2809 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2810 IXGBE_SRRCTL_BSIZEHDR_MASK;
2811
7d637bcc 2812 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2813#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2814 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2815#else
2816 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2817#endif
cc41ac7c 2818 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2819 } else {
afafd5b0
AD		 2820 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2821 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2822 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2823 }
e8e26350 2824
bf29ee6c 2825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2826}
9a799d71 2827
05abb126 2828static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2829{
05abb126
AD		 2830 struct ixgbe_hw *hw = &adapter->hw;
2831 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2832 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2833 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2834 u32 mrqc = 0, reta = 0;
2835 u32 rxcsum;
2836 int i, j;
0cefafad
JB		 2837 int mask;
2838
05abb126
AD		 2839 /* Fill out hash function seeds */
2840 for (i = 0; i < 10; i++)
2841 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2842
2843 /* Fill out redirection table */
2844 for (i = 0, j = 0; i < 128; i++, j++) {
2845 if (j == adapter->ring_feature[RING_F_RSS].indices)
2846 j = 0;
2847 /* reta = 4-byte sliding window of
2848 * 0x00..(indices-1)(indices-1)00..etc. */
2849 reta = (reta << 8) | (j * 0x11);
2850 if ((i & 3) == 3)
2851 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2852 }
0cefafad 2853
05abb126
AD		 2854 /* Disable indicating checksum in descriptor, enables RSS hash */
2855 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2856 rxcsum |= IXGBE_RXCSUM_PCSD;
2857 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2858
2859 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2860 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2861 else
2862 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2863#ifdef CONFIG_IXGBE_DCB
05abb126 2864 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2865#endif
05abb126
AD		 2866 | IXGBE_FLAG_SRIOV_ENABLED
2867 );
0cefafad
JB		 2868
2869 switch (mask) {
2870 case (IXGBE_FLAG_RSS_ENABLED):
2871 mrqc = IXGBE_MRQC_RSSEN;
2872 break;
1cdd1ec8
GR		 2873 case (IXGBE_FLAG_SRIOV_ENABLED):
2874 mrqc = IXGBE_MRQC_VMDQEN;
2875 break;
0cefafad
JB		 2876#ifdef CONFIG_IXGBE_DCB
2877 case (IXGBE_FLAG_DCB_ENABLED):
2878 mrqc = IXGBE_MRQC_RT8TCEN;
2879 break;
2880#endif /* CONFIG_IXGBE_DCB */
2881 default:
2882 break;
2883 }
2884
05abb126
AD		 2885 /* Perform hash on these packet types */
2886 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2887 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2888 | IXGBE_MRQC_RSS_FIELD_IPV6
2889 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2890
2891 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2892}
2893
bb5a9ad2
NS		 2894/**
2895 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2896 * @adapter: address of board private structure
2897 * @index: index of ring to set
bb5a9ad2 2898 **/
7367096a
AD		 2899static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2900 struct ixgbe_ring *ring)
bb5a9ad2 2901{
bb5a9ad2 2902 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2903 u32 rscctrl;
edd2ea55 2904 int rx_buf_len;
bf29ee6c 2905 u8 reg_idx = ring->reg_idx;
7367096a 2906
7d637bcc 2907 if (!ring_is_rsc_enabled(ring))
7367096a 2908 return;
bb5a9ad2 2909
7367096a
AD		 2910 rx_buf_len = ring->rx_buf_len;
2911 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2912 rscctrl |= IXGBE_RSCCTL_RSCEN;
2913 /*
2914 * we must limit the number of descriptors so that the
2915 * total size of max desc * buf_len is not greater
2916 * than 65535
2917 */
7d637bcc 2918 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2919#if (MAX_SKB_FRAGS > 16)
2920 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2921#elif (MAX_SKB_FRAGS > 8)
2922 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2923#elif (MAX_SKB_FRAGS > 4)
2924 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2925#else
2926 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2927#endif
2928 } else {
2929 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2930 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2931 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2932 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2933 else
2934 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2935 }
7367096a 2936 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2937}
2938
9e10e045
AD		 2939/**
2940 * ixgbe_set_uta - Set unicast filter table address
2941 * @adapter: board private structure
2942 *
2943 * The unicast table address is a register array of 32-bit registers.
2944 * The table is meant to be used in a way similar to how the MTA is used
2945 * however due to certain limitations in the hardware it is necessary to
2946 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2947 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2948 **/
2949static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2950{
2951 struct ixgbe_hw *hw = &adapter->hw;
2952 int i;
2953
2954 /* The UTA table only exists on 82599 hardware and newer */
2955 if (hw->mac.type < ixgbe_mac_82599EB)
2956 return;
2957
2958 /* we only need to do this if VMDq is enabled */
2959 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2960 return;
2961
2962 for (i = 0; i < 128; i++)
2963 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2964}
2965
2966#define IXGBE_MAX_RX_DESC_POLL 10
2967static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2968 struct ixgbe_ring *ring)
2969{
2970 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2971 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2972 u32 rxdctl;
bf29ee6c 2973 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2974
2975 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2976 if (hw->mac.type == ixgbe_mac_82598EB &&
2977 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2978 return;
2979
2980 do {
2981 msleep(1);
2982 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2983 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2984
2985 if (!wait_loop) {
2986 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2987 "the polling period\n", reg_idx);
2988 }
2989}
2990
84418e3b
AD		 2991void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2992 struct ixgbe_ring *ring)
acd37177
AD		 2993{
2994 struct ixgbe_hw *hw = &adapter->hw;
2995 u64 rdba = ring->dma;
9e10e045 2996 u32 rxdctl;
bf29ee6c 2997 u8 reg_idx = ring->reg_idx;
acd37177 2998
9e10e045
AD		 2999 /* disable queue to avoid issues while updating state */
3000 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3001 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
3002 rxdctl & ~IXGBE_RXDCTL_ENABLE);
3003 IXGBE_WRITE_FLUSH(hw);
3004
acd37177
AD		 3005 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3006 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3007 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3008 ring->count * sizeof(union ixgbe_adv_rx_desc));
3009 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3010 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3011 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3012
3013 ixgbe_configure_srrctl(adapter, ring);
3014 ixgbe_configure_rscctl(adapter, ring);
3015
3016 if (hw->mac.type == ixgbe_mac_82598EB) {
3017 /*
3018 * enable cache line friendly hardware writes:
3019 * PTHRESH=32 descriptors (half the internal cache),
3020 * this also removes ugly rx_no_buffer_count increment
3021 * HTHRESH=4 descriptors (to minimize latency on fetch)
3022 * WTHRESH=8 burst writeback up to two cache lines
3023 */
3024 rxdctl &= ~0x3FFFFF;
3025 rxdctl |= 0x080420;
3026 }
3027
3028 /* enable receive descriptor ring */
3029 rxdctl |= IXGBE_RXDCTL_ENABLE;
3030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3031
3032 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3033 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3034}
3035
48654521
AD		 3036static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3037{
3038 struct ixgbe_hw *hw = &adapter->hw;
3039 int p;
3040
3041 /* PSRTYPE must be initialized in non 82598 adapters */
3042 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3043 IXGBE_PSRTYPE_UDPHDR |
3044 IXGBE_PSRTYPE_IPV4HDR |
48654521 3045 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3046 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3047
3048 if (hw->mac.type == ixgbe_mac_82598EB)
3049 return;
3050
3051 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3052 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3053
3054 for (p = 0; p < adapter->num_rx_pools; p++)
3055 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3056 psrtype);
3057}
3058
f5b4a52e
AD		 3059static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3060{
3061 struct ixgbe_hw *hw = &adapter->hw;
3062 u32 gcr_ext;
3063 u32 vt_reg_bits;
3064 u32 reg_offset, vf_shift;
3065 u32 vmdctl;
3066
3067 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3068 return;
3069
3070 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3071 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3072 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3073 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3074
3075 vf_shift = adapter->num_vfs % 32;
3076 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3077
3078 /* Enable only the PF's pool for Tx/Rx */
3079 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3080 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3081 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3082 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3083 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3084
3085 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3086 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3087
3088 /*
3089 * Set up VF register offsets for selected VT Mode,
3090 * i.e. 32 or 64 VFs for SR-IOV
3091 */
3092 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3093 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3094 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3095 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3096
3097 /* enable Tx loopback for VF/PF communication */
3098 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3099}
3100
477de6ed 3101static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3102{
9a799d71
AK		 3103 struct ixgbe_hw *hw = &adapter->hw;
3104 struct net_device *netdev = adapter->netdev;
3105 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3106 int rx_buf_len;
477de6ed
AD		 3107 struct ixgbe_ring *rx_ring;
3108 int i;
3109 u32 mhadd, hlreg0;
48654521 3110
9a799d71 3111 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 3112 /* Do not use packet split if we're in SR-IOV Mode */
3113 if (!adapter->num_vfs)
3114 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3115
3116 /* Set the RX buffer length according to the mode */
3117 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3118 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3119 } else {
0c19d6af 3120 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3121 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3122 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3123 else
477de6ed 3124 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3125 }
3126
63f39bd1 3127#ifdef IXGBE_FCOE
477de6ed
AD		 3128 /* adjust max frame to be able to do baby jumbo for FCoE */
3129 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3130 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3131 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3132
477de6ed
AD		 3133#endif /* IXGBE_FCOE */
3134 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3135 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3136 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3137 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3138
3139 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3140 }
3141
3142 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3143 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3144 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3145 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3146
0cefafad
JB		 3147 /*
3148 * Setup the HW Rx Head and Tail Descriptor Pointers and
3149 * the Base and Length of the Rx Descriptor Ring
3150 */
9a799d71 3151 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3152 rx_ring = adapter->rx_ring[i];
a6616b42 3153 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3154
6e455b89 3155 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3156 set_ring_ps_enabled(rx_ring);
3157 else
3158 clear_ring_ps_enabled(rx_ring);
3159
3160 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3161 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3162 else
7d637bcc 3163 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3164
63f39bd1 3165#ifdef IXGBE_FCOE
e8e9f696 3166 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3167 struct ixgbe_ring_feature *f;
3168 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3169 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3170 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3171 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3172 rx_ring->rx_buf_len =
e8e9f696 3173 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3174 } else if (!ring_is_rsc_enabled(rx_ring) &&
3175 !ring_is_ps_enabled(rx_ring)) {
3176 rx_ring->rx_buf_len =
3177 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3178 }
63f39bd1 3179 }
63f39bd1 3180#endif /* IXGBE_FCOE */
477de6ed 3181 }
477de6ed
AD		 3182}
3183
7367096a
AD		 3184static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3185{
3186 struct ixgbe_hw *hw = &adapter->hw;
3187 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3188
3189 switch (hw->mac.type) {
3190 case ixgbe_mac_82598EB:
3191 /*
3192 * For VMDq support of different descriptor types or
3193 * buffer sizes through the use of multiple SRRCTL
3194 * registers, RDRXCTL.MVMEN must be set to 1
3195 *
3196 * also, the manual doesn't mention it clearly but DCA hints
3197 * will only use queue 0's tags unless this bit is set. Side
3198 * effects of setting this bit are only that SRRCTL must be
3199 * fully programmed [0..15]
3200 */
3201 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3202 break;
3203 case ixgbe_mac_82599EB:
3204 /* Disable RSC for ACK packets */
3205 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3206 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3207 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3208 /* hardware requires some bits to be set by default */
3209 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3210 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3211 break;
3212 default:
3213 /* We should do nothing since we don't know this hardware */
3214 return;
3215 }
3216
3217 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3218}
3219
477de6ed
AD		 3220/**
3221 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3222 * @adapter: board private structure
3223 *
3224 * Configure the Rx unit of the MAC after a reset.
3225 **/
3226static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3227{
3228 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3229 int i;
3230 u32 rxctrl;
477de6ed
AD		 3231
3232 /* disable receives while setting up the descriptors */
3233 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3234 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3235
3236 ixgbe_setup_psrtype(adapter);
7367096a 3237 ixgbe_setup_rdrxctl(adapter);
477de6ed 3238
9e10e045 3239 /* Program registers for the distribution of queues */
f5b4a52e 3240 ixgbe_setup_mrqc(adapter);
f5b4a52e 3241
9e10e045
AD		 3242 ixgbe_set_uta(adapter);
3243
477de6ed
AD		 3244 /* set_rx_buffer_len must be called before ring initialization */
3245 ixgbe_set_rx_buffer_len(adapter);
3246
3247 /*
3248 * Setup the HW Rx Head and Tail Descriptor Pointers and
3249 * the Base and Length of the Rx Descriptor Ring
3250 */
9e10e045
AD		 3251 for (i = 0; i < adapter->num_rx_queues; i++)
3252 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3253
9e10e045
AD		 3254 /* disable drop enable for 82598 parts */
3255 if (hw->mac.type == ixgbe_mac_82598EB)
3256 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3257
3258 /* enable all receives */
3259 rxctrl |= IXGBE_RXCTRL_RXEN;
3260 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3261}
3262
068c89b0
DS		 3263static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3264{
3265 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3266 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3267 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3268
3269 /* add VID to filter table */
1ada1b1b 3270 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3271 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3272}
3273
3274static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3275{
3276 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3277 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3278 int pool_ndx = adapter->num_vfs;
068c89b0 3279
068c89b0 3280 /* remove VID from filter table */
1ada1b1b 3281 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3282 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3283}
3284
5f6c0181
JB		 3285/**
3286 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3287 * @adapter: driver data
3288 */
3289static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3290{
3291 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3292 u32 vlnctrl;
3293
3294 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3295 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3296 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3297}
3298
3299/**
3300 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3301 * @adapter: driver data
3302 */
3303static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3304{
3305 struct ixgbe_hw *hw = &adapter->hw;
3306 u32 vlnctrl;
3307
3308 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3309 vlnctrl |= IXGBE_VLNCTRL_VFE;
3310 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3311 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3312}
3313
3314/**
3315 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3316 * @adapter: driver data
3317 */
3318static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3319{
3320 struct ixgbe_hw *hw = &adapter->hw;
3321 u32 vlnctrl;
5f6c0181
JB		 3322 int i, j;
3323
3324 switch (hw->mac.type) {
3325 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3326 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3327 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3328 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3329 break;
3330 case ixgbe_mac_82599EB:
5f6c0181
JB		 3331 for (i = 0; i < adapter->num_rx_queues; i++) {
3332 j = adapter->rx_ring[i]->reg_idx;
3333 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3334 vlnctrl &= ~IXGBE_RXDCTL_VME;
3335 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3336 }
3337 break;
3338 default:
3339 break;
3340 }
3341}
3342
3343/**
f62bbb5e 3344 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3345 * @adapter: driver data
3346 */
f62bbb5e 3347static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3348{
3349 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3350 u32 vlnctrl;
5f6c0181
JB		 3351 int i, j;
3352
3353 switch (hw->mac.type) {
3354 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3355 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3356 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3357 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3358 break;
3359 case ixgbe_mac_82599EB:
5f6c0181
JB		 3360 for (i = 0; i < adapter->num_rx_queues; i++) {
3361 j = adapter->rx_ring[i]->reg_idx;
3362 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3363 vlnctrl |= IXGBE_RXDCTL_VME;
3364 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3365 }
3366 break;
3367 default:
3368 break;
3369 }
3370}
3371
9a799d71
AK		 3372static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3373{
f62bbb5e 3374 u16 vid;
9a799d71 3375
f62bbb5e
JG		 3376 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3377
3378 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3379 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3380}
3381
2850062a
AD		 3382/**
3383 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3384 * @netdev: network interface device structure
3385 *
3386 * Writes unicast address list to the RAR table.
3387 * Returns: -ENOMEM on failure/insufficient address space
3388 * 0 on no addresses written
3389 * X on writing X addresses to the RAR table
3390 **/
3391static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3392{
3393 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 unsigned int vfn = adapter->num_vfs;
3396 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3397 int count = 0;
3398
3399 /* return ENOMEM indicating insufficient memory for addresses */
3400 if (netdev_uc_count(netdev) > rar_entries)
3401 return -ENOMEM;
3402
3403 if (!netdev_uc_empty(netdev) && rar_entries) {
3404 struct netdev_hw_addr *ha;
3405 /* return error if we do not support writing to RAR table */
3406 if (!hw->mac.ops.set_rar)
3407 return -ENOMEM;
3408
3409 netdev_for_each_uc_addr(ha, netdev) {
3410 if (!rar_entries)
3411 break;
3412 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3413 vfn, IXGBE_RAH_AV);
3414 count++;
3415 }
3416 }
3417 /* write the addresses in reverse order to avoid write combining */
3418 for (; rar_entries > 0 ; rar_entries--)
3419 hw->mac.ops.clear_rar(hw, rar_entries);
3420
3421 return count;
3422}
3423
9a799d71 3424/**
2c5645cf 3425 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3426 * @netdev: network interface device structure
3427 *
2c5645cf
CL		 3428 * The set_rx_method entry point is called whenever the unicast/multicast
3429 * address list or the network interface flags are updated. This routine is
3430 * responsible for configuring the hardware for proper unicast, multicast and
3431 * promiscuous mode.
9a799d71 3432 **/
7f870475 3433void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3434{
3435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3436 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3437 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3438 int count;
9a799d71
AK		 3439
3440 /* Check for Promiscuous and All Multicast modes */
3441
3442 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3443
f5dc442b
AD		 3444 /* set all bits that we expect to always be set */
3445 fctrl |= IXGBE_FCTRL_BAM;
3446 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3447 fctrl |= IXGBE_FCTRL_PMCF;
3448
2850062a
AD		 3449 /* clear the bits we are changing the status of */
3450 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3451
9a799d71 3452 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3453 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3454 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3455 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3456 /* don't hardware filter vlans in promisc mode */
3457 ixgbe_vlan_filter_disable(adapter);
9a799d71 3458 } else {
746b9f02
PM		 3459 if (netdev->flags & IFF_ALLMULTI) {
3460 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3461 vmolr |= IXGBE_VMOLR_MPE;
3462 } else {
3463 /*
3464 * Write addresses to the MTA, if the attempt fails
3465 * then we should just turn on promiscous mode so
3466 * that we can at least receive multicast traffic
3467 */
3468 hw->mac.ops.update_mc_addr_list(hw, netdev);
3469 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3470 }
5f6c0181 3471 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3472 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3473 /*
3474 * Write addresses to available RAR registers, if there is not
3475 * sufficient space to store all the addresses then enable
3476 * unicast promiscous mode
3477 */
3478 count = ixgbe_write_uc_addr_list(netdev);
3479 if (count < 0) {
3480 fctrl |= IXGBE_FCTRL_UPE;
3481 vmolr |= IXGBE_VMOLR_ROPE;
3482 }
9a799d71
AK		 3483 }
3484
2850062a 3485 if (adapter->num_vfs) {
1cdd1ec8 3486 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3487 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3488 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3489 IXGBE_VMOLR_ROPE);
3490 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3491 }
3492
3493 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3494
3495 if (netdev->features & NETIF_F_HW_VLAN_RX)
3496 ixgbe_vlan_strip_enable(adapter);
3497 else
3498 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3499}
3500
021230d4
AV		 3501static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3502{
3503 int q_idx;
3504 struct ixgbe_q_vector *q_vector;
3505 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3506
3507 /* legacy and MSI only use one vector */
3508 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3509 q_vectors = 1;
3510
3511 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3512 struct napi_struct *napi;
7a921c93 3513 q_vector = adapter->q_vector[q_idx];
f0848276 3514 napi = &q_vector->napi;
91281fd3
AD		 3515 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3516 if (!q_vector->rxr_count || !q_vector->txr_count) {
3517 if (q_vector->txr_count == 1)
3518 napi->poll = &ixgbe_clean_txonly;
3519 else if (q_vector->rxr_count == 1)
3520 napi->poll = &ixgbe_clean_rxonly;
3521 }
3522 }
f0848276
JB		 3523
3524 napi_enable(napi);
021230d4
AV		 3525 }
3526}
3527
3528static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3529{
3530 int q_idx;
3531 struct ixgbe_q_vector *q_vector;
3532 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3533
3534 /* legacy and MSI only use one vector */
3535 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3536 q_vectors = 1;
3537
3538 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3539 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3540 napi_disable(&q_vector->napi);
3541 }
3542}
3543
7a6b6f51 3544#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3545/*
3546 * ixgbe_configure_dcb - Configure DCB hardware
3547 * @adapter: ixgbe adapter struct
3548 *
3549 * This is called by the driver on open to configure the DCB hardware.
3550 * This is also called by the gennetlink interface when reconfiguring
3551 * the DCB state.
3552 */
3553static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3554{
3555 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3556 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3557
67ebd791
AD		 3558 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3559 if (hw->mac.type == ixgbe_mac_82598EB)
3560 netif_set_gso_max_size(adapter->netdev, 65536);
3561 return;
3562 }
3563
3564 if (hw->mac.type == ixgbe_mac_82598EB)
3565 netif_set_gso_max_size(adapter->netdev, 32768);
3566
9806307a
JF		 3567#ifdef CONFIG_FCOE
3568 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3569 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3570#endif
3571
80ab193d 3572 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3573 DCB_TX_CONFIG);
80ab193d 3574 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3575 DCB_RX_CONFIG);
2f90b865 3576
2f90b865 3577 /* Enable VLAN tag insert/strip */
f62bbb5e 3578 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3579
2f90b865 3580 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3581
3582 /* reconfigure the hardware */
3583 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
2f90b865
AD		 3584}
3585
3586#endif
9a799d71
AK		 3587static void ixgbe_configure(struct ixgbe_adapter *adapter)
3588{
3589 struct net_device *netdev = adapter->netdev;
c4cf55e5 3590 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3591 int i;
3592
7a6b6f51 3593#ifdef CONFIG_IXGBE_DCB
67ebd791 3594 ixgbe_configure_dcb(adapter);
2f90b865 3595#endif
9a799d71 3596
f62bbb5e
JG		 3597 ixgbe_set_rx_mode(netdev);
3598 ixgbe_restore_vlan(adapter);
3599
eacd73f7
YZ		 3600#ifdef IXGBE_FCOE
3601 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3602 ixgbe_configure_fcoe(adapter);
3603
3604#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3605 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3606 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3607 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3608 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3609 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3610 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3611 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3612 }
933d41f1 3613 ixgbe_configure_virtualization(adapter);
c4cf55e5 3614
9a799d71
AK		 3615 ixgbe_configure_tx(adapter);
3616 ixgbe_configure_rx(adapter);
9a799d71
AK		 3617}
3618
e8e26350
PW		 3619static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3620{
3621 switch (hw->phy.type) {
3622 case ixgbe_phy_sfp_avago:
3623 case ixgbe_phy_sfp_ftl:
3624 case ixgbe_phy_sfp_intel:
3625 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3626 case ixgbe_phy_sfp_passive_tyco:
3627 case ixgbe_phy_sfp_passive_unknown:
3628 case ixgbe_phy_sfp_active_unknown:
3629 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3630 return true;
3631 default:
3632 return false;
3633 }
3634}
3635
0ecc061d 3636/**
e8e26350
PW		 3637 * ixgbe_sfp_link_config - set up SFP+ link
3638 * @adapter: pointer to private adapter struct
3639 **/
3640static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3641{
3642 struct ixgbe_hw *hw = &adapter->hw;
3643
3644 if (hw->phy.multispeed_fiber) {
3645 /*
3646 * In multispeed fiber setups, the device may not have
3647 * had a physical connection when the driver loaded.
3648 * If that's the case, the initial link configuration
3649 * couldn't get the MAC into 10G or 1G mode, so we'll
3650 * never have a link status change interrupt fire.
3651 * We need to try and force an autonegotiation
3652 * session, then bring up link.
3653 */
3654 hw->mac.ops.setup_sfp(hw);
3655 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3656 schedule_work(&adapter->multispeed_fiber_task);
3657 } else {
3658 /*
3659 * Direct Attach Cu and non-multispeed fiber modules
3660 * still need to be configured properly prior to
3661 * attempting link.
3662 */
3663 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3664 schedule_work(&adapter->sfp_config_module_task);
3665 }
3666}
3667
3668/**
3669 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3670 * @hw: pointer to private hardware struct
3671 *
3672 * Returns 0 on success, negative on failure
3673 **/
e8e26350 3674static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3675{
3676 u32 autoneg;
8620a103 3677 bool negotiation, link_up = false;
0ecc061d
PWJ		 3678 u32 ret = IXGBE_ERR_LINK_SETUP;
3679
3680 if (hw->mac.ops.check_link)
3681 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3682
3683 if (ret)
3684 goto link_cfg_out;
3685
3686 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3687 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3688 &negotiation);
0ecc061d
PWJ		 3689 if (ret)
3690 goto link_cfg_out;
3691
8620a103
MC		 3692 if (hw->mac.ops.setup_link)
3693 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3694link_cfg_out:
3695 return ret;
3696}
3697
a34bcfff 3698static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3699{
9a799d71 3700 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3701 u32 gpie = 0;
9a799d71 3702
9b471446 3703 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3704 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3705 IXGBE_GPIE_OCD;
3706 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3707 /*
3708 * use EIAM to auto-mask when MSI-X interrupt is asserted
3709 * this saves a register write for every interrupt
3710 */
3711 switch (hw->mac.type) {
3712 case ixgbe_mac_82598EB:
3713 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3714 break;
3715 default:
3716 case ixgbe_mac_82599EB:
3717 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3718 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3719 break;
3720 }
3721 } else {
021230d4
AV		 3722 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3723 * specifically only auto mask tx and rx interrupts */
3724 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3725 }
9a799d71 3726
a34bcfff
AD		 3727 /* XXX: to interrupt immediately for EICS writes, enable this */
3728 /* gpie |= IXGBE_GPIE_EIMEN; */
3729
3730 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3731 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3732 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3733 }
3734
a34bcfff
AD		 3735 /* Enable fan failure interrupt */
3736 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3737 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3738
a34bcfff 3739 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3740 gpie |= IXGBE_SDP1_GPIEN;
3741 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3742
3743 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3744}
3745
3746static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3747{
3748 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3749 int err;
a34bcfff
AD		 3750 u32 ctrl_ext;
3751
3752 ixgbe_get_hw_control(adapter);
3753 ixgbe_setup_gpie(adapter);
e8e26350 3754
9a799d71
AK		 3755 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3756 ixgbe_configure_msix(adapter);
3757 else
3758 ixgbe_configure_msi_and_legacy(adapter);
3759
61fac744 3760 /* enable the optics */
e3de4b7b 3761 if (hw->phy.multispeed_fiber && hw->mac.ops.enable_tx_laser)
61fac744
PW		 3762 hw->mac.ops.enable_tx_laser(hw);
3763
9a799d71 3764 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3765 ixgbe_napi_enable_all(adapter);
3766
73c4b7cd
AD		 3767 if (ixgbe_is_sfp(hw)) {
3768 ixgbe_sfp_link_config(adapter);
3769 } else {
3770 err = ixgbe_non_sfp_link_config(hw);
3771 if (err)
3772 e_err(probe, "link_config FAILED %d\n", err);
3773 }
3774
021230d4
AV		 3775 /* clear any pending interrupts, may auto mask */
3776 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3777 ixgbe_irq_enable(adapter, true, true);
9a799d71 3778
bf069c97
DS		 3779 /*
3780 * If this adapter has a fan, check to see if we had a failure
3781 * before we enabled the interrupt.
3782 */
3783 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3784 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3785 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3786 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3787 }
3788
e8e26350
PW		 3789 /*
3790 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3791 * arrived before interrupts were enabled but after probe. Such
3792 * devices wouldn't have their type identified yet. We need to
3793 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3794 * If we're not hot-pluggable SFP+, we just need to configure link
3795 * and bring it up.
3796 */
73c4b7cd
AD		 3797 if (hw->phy.type == ixgbe_phy_unknown)
3798 schedule_work(&adapter->sfp_config_module_task);
0ecc061d 3799
1da100bb 3800 /* enable transmits */
477de6ed 3801 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3802
9a799d71
AK		 3803 /* bring the link up in the watchdog, this could race with our first
3804 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3805 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3806 adapter->link_check_timeout = jiffies;
9a799d71 3807 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3808
3809 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3810 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3811 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3812 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3813
9a799d71
AK		 3814 return 0;
3815}
3816
d4f80882
AV		 3817void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3818{
3819 WARN_ON(in_interrupt());
3820 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3821 msleep(1);
3822 ixgbe_down(adapter);
5809a1ae
GR		 3823 /*
3824 * If SR-IOV enabled then wait a bit before bringing the adapter
3825 * back up to give the VFs time to respond to the reset. The
3826 * two second wait is based upon the watchdog timer cycle in
3827 * the VF driver.
3828 */
3829 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3830 msleep(2000);
d4f80882
AV		 3831 ixgbe_up(adapter);
3832 clear_bit(__IXGBE_RESETTING, &adapter->state);
3833}
3834
9a799d71
AK		 3835int ixgbe_up(struct ixgbe_adapter *adapter)
3836{
3837 /* hardware has been reset, we need to reload some things */
3838 ixgbe_configure(adapter);
3839
3840 return ixgbe_up_complete(adapter);
3841}
3842
3843void ixgbe_reset(struct ixgbe_adapter *adapter)
3844{
c44ade9e 3845 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3846 int err;
3847
3848 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3849 switch (err) {
3850 case 0:
3851 case IXGBE_ERR_SFP_NOT_PRESENT:
3852 break;
3853 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3854 e_dev_err("master disable timed out\n");
da4dd0f7 3855 break;
794caeb2
PWJ		 3856 case IXGBE_ERR_EEPROM_VERSION:
3857 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3858 e_dev_warn("This device is a pre-production adapter/LOM. "
3859 "Please be aware there may be issuesassociated with "
3860 "your hardware. If you are experiencing problems "
3861 "please contact your Intel or hardware "
3862 "representative who provided you with this "
3863 "hardware.\n");
794caeb2 3864 break;
da4dd0f7 3865 default:
849c4542 3866 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3867 }
9a799d71
AK		 3868
3869 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3870 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3871 IXGBE_RAH_AV);
9a799d71
AK		 3872}
3873
9a799d71
AK		 3874/**
3875 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3876 * @rx_ring: ring to free buffers from
3877 **/
b6ec895e 3878static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3879{
b6ec895e 3880 struct device *dev = rx_ring->dev;
9a799d71 3881 unsigned long size;
b6ec895e 3882 u16 i;
9a799d71 3883
84418e3b
AD		 3884 /* ring already cleared, nothing to do */
3885 if (!rx_ring->rx_buffer_info)
3886 return;
9a799d71 3887
84418e3b 3888 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3889 for (i = 0; i < rx_ring->count; i++) {
3890 struct ixgbe_rx_buffer *rx_buffer_info;
3891
3892 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3893 if (rx_buffer_info->dma) {
b6ec895e 3894 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3895 rx_ring->rx_buf_len,
1b507730 3896 DMA_FROM_DEVICE);
9a799d71
AK		 3897 rx_buffer_info->dma = 0;
3898 }
3899 if (rx_buffer_info->skb) {
f8212f97 3900 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3901 rx_buffer_info->skb = NULL;
f8212f97
AD		 3902 do {
3903 struct sk_buff *this = skb;
e8171aaa 3904 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3905 dma_unmap_single(dev,
1b507730 3906 IXGBE_RSC_CB(this)->dma,
e8e9f696 3907 rx_ring->rx_buf_len,
1b507730 3908 DMA_FROM_DEVICE);
fd3686a8 3909 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3910 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3911 }
f8212f97
AD		 3912 skb = skb->prev;
3913 dev_kfree_skb(this);
3914 } while (skb);
9a799d71
AK		 3915 }
3916 if (!rx_buffer_info->page)
3917 continue;
4f57ca6e 3918 if (rx_buffer_info->page_dma) {
b6ec895e 3919 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3920 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3921 rx_buffer_info->page_dma = 0;
3922 }
9a799d71
AK		 3923 put_page(rx_buffer_info->page);
3924 rx_buffer_info->page = NULL;
762f4c57 3925 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3926 }
3927
3928 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3929 memset(rx_ring->rx_buffer_info, 0, size);
3930
3931 /* Zero out the descriptor ring */
3932 memset(rx_ring->desc, 0, rx_ring->size);
3933
3934 rx_ring->next_to_clean = 0;
3935 rx_ring->next_to_use = 0;
9a799d71
AK		 3936}
3937
3938/**
3939 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3940 * @tx_ring: ring to be cleaned
3941 **/
b6ec895e 3942static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3943{
3944 struct ixgbe_tx_buffer *tx_buffer_info;
3945 unsigned long size;
b6ec895e 3946 u16 i;
9a799d71 3947
84418e3b
AD		 3948 /* ring already cleared, nothing to do */
3949 if (!tx_ring->tx_buffer_info)
3950 return;
9a799d71 3951
84418e3b 3952 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3953 for (i = 0; i < tx_ring->count; i++) {
3954 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3955 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3956 }
3957
3958 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3959 memset(tx_ring->tx_buffer_info, 0, size);
3960
3961 /* Zero out the descriptor ring */
3962 memset(tx_ring->desc, 0, tx_ring->size);
3963
3964 tx_ring->next_to_use = 0;
3965 tx_ring->next_to_clean = 0;
9a799d71
AK		 3966}
3967
3968/**
021230d4 3969 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3970 * @adapter: board private structure
3971 **/
021230d4 3972static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3973{
3974 int i;
3975
021230d4 3976 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3977 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3978}
3979
3980/**
021230d4 3981 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3982 * @adapter: board private structure
3983 **/
021230d4 3984static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3985{
3986 int i;
3987
021230d4 3988 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3989 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3990}
3991
3992void ixgbe_down(struct ixgbe_adapter *adapter)
3993{
3994 struct net_device *netdev = adapter->netdev;
7f821875 3995 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3996 u32 rxctrl;
7f821875 3997 u32 txdctl;
bf29ee6c 3998 int i;
b25ebfd2 3999 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4000
4001 /* signal that we are down to the interrupt handler */
4002 set_bit(__IXGBE_DOWN, &adapter->state);
4003
767081ad
GR		 4004 /* disable receive for all VFs and wait one second */
4005 if (adapter->num_vfs) {
767081ad
GR		 4006 /* ping all the active vfs to let them know we are going down */
4007 ixgbe_ping_all_vfs(adapter);
581d1aa7 4008
767081ad
GR		 4009 /* Disable all VFTE/VFRE TX/RX */
4010 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4011
4012 /* Mark all the VFs as inactive */
4013 for (i = 0 ; i < adapter->num_vfs; i++)
4014 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4015 }
4016
9a799d71 4017 /* disable receives */
7f821875
JB		 4018 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4019 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4020
7f821875 4021 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 4022 msleep(10);
4023
7f821875
JB		 4024 netif_tx_stop_all_queues(netdev);
4025
0a1f87cb
DS		 4026 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4027 del_timer_sync(&adapter->sfp_timer);
9a799d71 4028 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 4029 cancel_work_sync(&adapter->watchdog_task);
9a799d71 4030
c0dfb90e
JF		 4031 netif_carrier_off(netdev);
4032 netif_tx_disable(netdev);
4033
4034 ixgbe_irq_disable(adapter);
4035
4036 ixgbe_napi_disable_all(adapter);
4037
b25ebfd2
PW		 4038 /* Cleanup the affinity_hint CPU mask memory and callback */
4039 for (i = 0; i < num_q_vectors; i++) {
4040 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4041 /* clear the affinity_mask in the IRQ descriptor */
4042 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4043 /* release the CPU mask memory */
4044 free_cpumask_var(q_vector->affinity_mask);
4045 }
4046
c4cf55e5
PWJ		 4047 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4048 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4049 cancel_work_sync(&adapter->fdir_reinit_task);
4050
119fc60a
MC		 4051 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4052 cancel_work_sync(&adapter->check_overtemp_task);
4053
7f821875
JB		 4054 /* disable transmits in the hardware now that interrupts are off */
4055 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4056 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4057 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4058 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4059 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4060 }
88512539 4061 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4062 switch (hw->mac.type) {
4063 case ixgbe_mac_82599EB:
88512539 4064 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4065 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4066 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4067 break;
4068 default:
4069 break;
4070 }
7f821875 4071
9f756f01 4072 /* power down the optics */
e3de4b7b 4073 if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
9f756f01
JF		 4074 hw->mac.ops.disable_tx_laser(hw);
4075
9a713e7c
PW		 4076 /* clear n-tuple filters that are cached */
4077 ethtool_ntuple_flush(netdev);
4078
6f4a0e45
PL		 4079 if (!pci_channel_offline(adapter->pdev))
4080 ixgbe_reset(adapter);
9a799d71
AK		 4081 ixgbe_clean_all_tx_rings(adapter);
4082 ixgbe_clean_all_rx_rings(adapter);
4083
5dd2d332 4084#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4085 /* since we reset the hardware DCA settings were cleared */
e35ec126 4086 ixgbe_setup_dca(adapter);
96b0e0f6 4087#endif
9a799d71
AK		 4088}
4089
9a799d71 4090/**
021230d4
AV		 4091 * ixgbe_poll - NAPI Rx polling callback
4092 * @napi: structure for representing this polling device
4093 * @budget: how many packets driver is allowed to clean
4094 *
4095 * This function is used for legacy and MSI, NAPI mode
9a799d71 4096 **/
021230d4 4097static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4098{
9a1a69ad 4099 struct ixgbe_q_vector *q_vector =
e8e9f696 4100 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4101 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4102 int tx_clean_complete, work_done = 0;
9a799d71 4103
5dd2d332 4104#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4105 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4106 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4107#endif
4108
4a0b9ca0
PW		 4109 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4110 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4111
9a1a69ad 4112 if (!tx_clean_complete)
d2c7ddd6
DM		 4113 work_done = budget;
4114
53e52c72
DM		 4115 /* If budget not fully consumed, exit the polling mode */
4116 if (work_done < budget) {
288379f0 4117 napi_complete(napi);
f7554a2b 4118 if (adapter->rx_itr_setting & 1)
f494e8fa 4119 ixgbe_set_itr(adapter);
d4f80882 4120 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4121 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4122 }
9a799d71
AK		 4123 return work_done;
4124}
4125
4126/**
4127 * ixgbe_tx_timeout - Respond to a Tx Hang
4128 * @netdev: network interface device structure
4129 **/
4130static void ixgbe_tx_timeout(struct net_device *netdev)
4131{
4132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4133
c84d324c
JF		 4134 adapter->tx_timeout_count++;
4135
9a799d71
AK		 4136 /* Do the reset outside of interrupt context */
4137 schedule_work(&adapter->reset_task);
4138}
4139
4140static void ixgbe_reset_task(struct work_struct *work)
4141{
4142 struct ixgbe_adapter *adapter;
4143 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4144
2f90b865
AD		 4145 /* If we're already down or resetting, just bail */
4146 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4147 test_bit(__IXGBE_RESETTING, &adapter->state))
4148 return;
4149
dcd79aeb
TI		 4150 ixgbe_dump(adapter);
4151 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4152 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4153}
4154
bc97114d
PWJ		 4155#ifdef CONFIG_IXGBE_DCB
4156static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 4157{
bc97114d 4158 bool ret = false;
0cefafad 4159 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 4160
0cefafad
JB		 4161 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4162 return ret;
4163
4164 f->mask = 0x7 << 3;
4165 adapter->num_rx_queues = f->indices;
4166 adapter->num_tx_queues = f->indices;
4167 ret = true;
2f90b865 4168
bc97114d
PWJ		 4169 return ret;
4170}
4171#endif
4172
4df10466
JB		 4173/**
4174 * ixgbe_set_rss_queues: Allocate queues for RSS
4175 * @adapter: board private structure to initialize
4176 *
4177 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4178 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4179 *
4180 **/
bc97114d
PWJ		 4181static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4182{
4183 bool ret = false;
0cefafad 4184 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4185
4186 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4187 f->mask = 0xF;
4188 adapter->num_rx_queues = f->indices;
4189 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4190 ret = true;
4191 } else {
bc97114d 4192 ret = false;
b9804972
JB		 4193 }
4194
bc97114d
PWJ		 4195 return ret;
4196}
4197
c4cf55e5
PWJ		 4198/**
4199 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4200 * @adapter: board private structure to initialize
4201 *
4202 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4203 * to the original CPU that initiated the Tx session. This runs in addition
4204 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4205 * Rx load across CPUs using RSS.
4206 *
4207 **/
e8e9f696 4208static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4209{
4210 bool ret = false;
4211 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4212
4213 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4214 f_fdir->mask = 0;
4215
4216 /* Flow Director must have RSS enabled */
4217 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4218 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4219 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4220 adapter->num_tx_queues = f_fdir->indices;
4221 adapter->num_rx_queues = f_fdir->indices;
4222 ret = true;
4223 } else {
4224 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4225 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4226 }
4227 return ret;
4228}
4229
0331a832
YZ		 4230#ifdef IXGBE_FCOE
4231/**
4232 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4233 * @adapter: board private structure to initialize
4234 *
4235 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4236 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4237 * rx queues out of the max number of rx queues, instead, it is used as the
4238 * index of the first rx queue used by FCoE.
4239 *
4240 **/
4241static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4242{
4243 bool ret = false;
4244 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4245
4246 f->indices = min((int)num_online_cpus(), f->indices);
4247 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4248 adapter->num_rx_queues = 1;
4249 adapter->num_tx_queues = 1;
0331a832
YZ		 4250#ifdef CONFIG_IXGBE_DCB
4251 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4252 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4253 ixgbe_set_dcb_queues(adapter);
4254 }
4255#endif
4256 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4257 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4258 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4259 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4260 ixgbe_set_fdir_queues(adapter);
4261 else
4262 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4263 }
4264 /* adding FCoE rx rings to the end */
4265 f->mask = adapter->num_rx_queues;
4266 adapter->num_rx_queues += f->indices;
8de8b2e6 4267 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4268
4269 ret = true;
4270 }
4271
4272 return ret;
4273}
4274
4275#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4276/**
4277 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4278 * @adapter: board private structure to initialize
4279 *
4280 * IOV doesn't actually use anything, so just NAK the
4281 * request for now and let the other queue routines
4282 * figure out what to do.
4283 */
4284static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4285{
4286 return false;
4287}
4288
4df10466
JB		 4289/*
4290 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4291 * @adapter: board private structure to initialize
4292 *
4293 * This is the top level queue allocation routine. The order here is very
4294 * important, starting with the "most" number of features turned on at once,
4295 * and ending with the smallest set of features. This way large combinations
4296 * can be allocated if they're turned on, and smaller combinations are the
4297 * fallthrough conditions.
4298 *
4299 **/
847f53ff 4300static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4301{
1cdd1ec8
GR		 4302 /* Start with base case */
4303 adapter->num_rx_queues = 1;
4304 adapter->num_tx_queues = 1;
4305 adapter->num_rx_pools = adapter->num_rx_queues;
4306 adapter->num_rx_queues_per_pool = 1;
4307
4308 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4309 goto done;
1cdd1ec8 4310
0331a832
YZ		 4311#ifdef IXGBE_FCOE
4312 if (ixgbe_set_fcoe_queues(adapter))
4313 goto done;
4314
4315#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4316#ifdef CONFIG_IXGBE_DCB
4317 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4318 goto done;
bc97114d
PWJ		 4319
4320#endif
c4cf55e5
PWJ		 4321 if (ixgbe_set_fdir_queues(adapter))
4322 goto done;
4323
bc97114d 4324 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4325 goto done;
4326
4327 /* fallback to base case */
4328 adapter->num_rx_queues = 1;
4329 adapter->num_tx_queues = 1;
4330
4331done:
847f53ff 4332 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4333 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4334 return netif_set_real_num_rx_queues(adapter->netdev,
4335 adapter->num_rx_queues);
b9804972
JB		 4336}
4337
021230d4 4338static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4339 int vectors)
021230d4
AV		 4340{
4341 int err, vector_threshold;
4342
4343 /* We'll want at least 3 (vector_threshold):
4344 * 1) TxQ[0] Cleanup
4345 * 2) RxQ[0] Cleanup
4346 * 3) Other (Link Status Change, etc.)
4347 * 4) TCP Timer (optional)
4348 */
4349 vector_threshold = MIN_MSIX_COUNT;
4350
4351 /* The more we get, the more we will assign to Tx/Rx Cleanup
4352 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4353 * Right now, we simply care about how many we'll get; we'll
4354 * set them up later while requesting irq's.
4355 */
4356 while (vectors >= vector_threshold) {
4357 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4358 vectors);
021230d4
AV		 4359 if (!err) /* Success in acquiring all requested vectors. */
4360 break;
4361 else if (err < 0)
4362 vectors = 0; /* Nasty failure, quit now */
4363 else /* err == number of vectors we should try again with */
4364 vectors = err;
4365 }
4366
4367 if (vectors < vector_threshold) {
4368 /* Can't allocate enough MSI-X interrupts? Oh well.
4369 * This just means we'll go with either a single MSI
4370 * vector or fall back to legacy interrupts.
4371 */
849c4542
ET		 4372 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4373 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4374 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4375 kfree(adapter->msix_entries);
4376 adapter->msix_entries = NULL;
021230d4
AV		 4377 } else {
4378 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4379 /*
4380 * Adjust for only the vectors we'll use, which is minimum
4381 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4382 * vectors we were allocated.
4383 */
4384 adapter->num_msix_vectors = min(vectors,
e8e9f696 4385 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4386 }
4387}
4388
021230d4 4389/**
bc97114d 4390 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4391 * @adapter: board private structure to initialize
4392 *
bc97114d
PWJ		 4393 * Cache the descriptor ring offsets for RSS to the assigned rings.
4394 *
021230d4 4395 **/
bc97114d 4396static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4397{
bc97114d 4398 int i;
bc97114d 4399
9d6b758f
AD		 4400 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4401 return false;
bc97114d 4402
9d6b758f
AD		 4403 for (i = 0; i < adapter->num_rx_queues; i++)
4404 adapter->rx_ring[i]->reg_idx = i;
4405 for (i = 0; i < adapter->num_tx_queues; i++)
4406 adapter->tx_ring[i]->reg_idx = i;
4407
4408 return true;
bc97114d
PWJ		 4409}
4410
4411#ifdef CONFIG_IXGBE_DCB
4412/**
4413 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4414 * @adapter: board private structure to initialize
4415 *
4416 * Cache the descriptor ring offsets for DCB to the assigned rings.
4417 *
4418 **/
4419static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4420{
4421 int i;
4422 bool ret = false;
4423 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4424
bd508178
AD		 4425 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4426 return false;
f92ef202 4427
bd508178
AD		 4428 /* the number of queues is assumed to be symmetric */
4429 switch (adapter->hw.mac.type) {
4430 case ixgbe_mac_82598EB:
4431 for (i = 0; i < dcb_i; i++) {
4432 adapter->rx_ring[i]->reg_idx = i << 3;
4433 adapter->tx_ring[i]->reg_idx = i << 2;
4434 }
4435 ret = true;
4436 break;
4437 case ixgbe_mac_82599EB:
4438 if (dcb_i == 8) {
4439 /*
4440 * Tx TC0 starts at: descriptor queue 0
4441 * Tx TC1 starts at: descriptor queue 32
4442 * Tx TC2 starts at: descriptor queue 64
4443 * Tx TC3 starts at: descriptor queue 80
4444 * Tx TC4 starts at: descriptor queue 96
4445 * Tx TC5 starts at: descriptor queue 104
4446 * Tx TC6 starts at: descriptor queue 112
4447 * Tx TC7 starts at: descriptor queue 120
4448 *
4449 * Rx TC0-TC7 are offset by 16 queues each
4450 */
4451 for (i = 0; i < 3; i++) {
4452 adapter->tx_ring[i]->reg_idx = i << 5;
4453 adapter->rx_ring[i]->reg_idx = i << 4;
e8e26350 4454 }
bd508178
AD		 4455 for ( ; i < 5; i++) {
4456 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4457 adapter->rx_ring[i]->reg_idx = i << 4;
4458 }
4459 for ( ; i < dcb_i; i++) {
4460 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4461 adapter->rx_ring[i]->reg_idx = i << 4;
4462 }
4463 ret = true;
4464 } else if (dcb_i == 4) {
4465 /*
4466 * Tx TC0 starts at: descriptor queue 0
4467 * Tx TC1 starts at: descriptor queue 64
4468 * Tx TC2 starts at: descriptor queue 96
4469 * Tx TC3 starts at: descriptor queue 112
4470 *
4471 * Rx TC0-TC3 are offset by 32 queues each
4472 */
4473 adapter->tx_ring[0]->reg_idx = 0;
4474 adapter->tx_ring[1]->reg_idx = 64;
4475 adapter->tx_ring[2]->reg_idx = 96;
4476 adapter->tx_ring[3]->reg_idx = 112;
4477 for (i = 0 ; i < dcb_i; i++)
4478 adapter->rx_ring[i]->reg_idx = i << 5;
4479 ret = true;
021230d4 4480 }
bd508178
AD		 4481 break;
4482 default:
4483 break;
021230d4 4484 }
bc97114d
PWJ		 4485 return ret;
4486}
4487#endif
4488
c4cf55e5
PWJ		 4489/**
4490 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4491 * @adapter: board private structure to initialize
4492 *
4493 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4494 *
4495 **/
e8e9f696 4496static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4497{
4498 int i;
4499 bool ret = false;
4500
4501 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4502 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4503 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4504 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4505 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4506 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4507 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4508 ret = true;
4509 }
4510
4511 return ret;
4512}
4513
0331a832
YZ		 4514#ifdef IXGBE_FCOE
4515/**
4516 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4517 * @adapter: board private structure to initialize
4518 *
4519 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4520 *
4521 */
4522static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4523{
0331a832 4524 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4525 int i;
4526 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4527
4528 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4529 return false;
0331a832 4530
0331a832 4531#ifdef CONFIG_IXGBE_DCB
bf29ee6c
AD		 4532 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4533 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
8de8b2e6 4534
bf29ee6c
AD		 4535 ixgbe_cache_ring_dcb(adapter);
4536 /* find out queues in TC for FCoE */
4537 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4538 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4539 /*
4540 * In 82599, the number of Tx queues for each traffic
4541 * class for both 8-TC and 4-TC modes are:
4542 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4543 * 8 TCs: 32 32 16 16 8 8 8 8
4544 * 4 TCs: 64 64 32 32
4545 * We have max 8 queues for FCoE, where 8 the is
4546 * FCoE redirection table size. If TC for FCoE is
4547 * less than or equal to TC3, we have enough queues
4548 * to add max of 8 queues for FCoE, so we start FCoE
4549 * Tx queue from the next one, i.e., reg_idx + 1.
4550 * If TC for FCoE is above TC3, implying 8 TC mode,
4551 * and we need 8 for FCoE, we have to take all queues
4552 * in that traffic class for FCoE.
4553 */
4554 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4555 fcoe_tx_i--;
4556 }
0331a832 4557#endif /* CONFIG_IXGBE_DCB */
bf29ee6c
AD		 4558 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4559 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4560 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4561 ixgbe_cache_ring_fdir(adapter);
4562 else
4563 ixgbe_cache_ring_rss(adapter);
8faa2a78 4564
bf29ee6c
AD		 4565 fcoe_rx_i = f->mask;
4566 fcoe_tx_i = f->mask;
0331a832 4567 }
bf29ee6c
AD		 4568 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4569 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4570 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4571 }
4572 return true;
0331a832
YZ		 4573}
4574
4575#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4576/**
4577 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4578 * @adapter: board private structure to initialize
4579 *
4580 * SR-IOV doesn't use any descriptor rings but changes the default if
4581 * no other mapping is used.
4582 *
4583 */
4584static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4585{
4a0b9ca0
PW		 4586 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4587 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4588 if (adapter->num_vfs)
4589 return true;
4590 else
4591 return false;
4592}
4593
bc97114d
PWJ		 4594/**
4595 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4596 * @adapter: board private structure to initialize
4597 *
4598 * Once we know the feature-set enabled for the device, we'll cache
4599 * the register offset the descriptor ring is assigned to.
4600 *
4601 * Note, the order the various feature calls is important. It must start with
4602 * the "most" features enabled at the same time, then trickle down to the
4603 * least amount of features turned on at once.
4604 **/
4605static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4606{
4607 /* start with default case */
4a0b9ca0
PW		 4608 adapter->rx_ring[0]->reg_idx = 0;
4609 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4610
1cdd1ec8
GR		 4611 if (ixgbe_cache_ring_sriov(adapter))
4612 return;
4613
0331a832
YZ		 4614#ifdef IXGBE_FCOE
4615 if (ixgbe_cache_ring_fcoe(adapter))
4616 return;
4617
4618#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4619#ifdef CONFIG_IXGBE_DCB
4620 if (ixgbe_cache_ring_dcb(adapter))
4621 return;
4622
4623#endif
c4cf55e5
PWJ		 4624 if (ixgbe_cache_ring_fdir(adapter))
4625 return;
4626
bc97114d
PWJ		 4627 if (ixgbe_cache_ring_rss(adapter))
4628 return;
021230d4
AV		 4629}
4630
9a799d71
AK		 4631/**
4632 * ixgbe_alloc_queues - Allocate memory for all rings
4633 * @adapter: board private structure to initialize
4634 *
4635 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4636 * number of queues at compile-time. The polling_netdev array is
4637 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4638 **/
2f90b865 4639static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4640{
4641 int i;
b6ec895e 4642 int rx_count;
4a0b9ca0 4643 int orig_node = adapter->node;
9a799d71 4644
021230d4 4645 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4646 struct ixgbe_ring *ring = adapter->tx_ring[i];
4647 if (orig_node == -1) {
4648 int cur_node = next_online_node(adapter->node);
4649 if (cur_node == MAX_NUMNODES)
4650 cur_node = first_online_node;
4651 adapter->node = cur_node;
4652 }
4653 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4654 adapter->node);
4a0b9ca0
PW		 4655 if (!ring)
4656 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4657 if (!ring)
4658 goto err_tx_ring_allocation;
4659 ring->count = adapter->tx_ring_count;
4660 ring->queue_index = i;
b6ec895e 4661 ring->dev = &adapter->pdev->dev;
fc77dc3c 4662 ring->netdev = adapter->netdev;
4a0b9ca0
PW		 4663 ring->numa_node = adapter->node;
4664
4665 adapter->tx_ring[i] = ring;
021230d4 4666 }
b9804972 4667
4a0b9ca0
PW		 4668 /* Restore the adapter's original node */
4669 adapter->node = orig_node;
4670
b6ec895e 4671 rx_count = adapter->rx_ring_count;
9a799d71 4672 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4673 struct ixgbe_ring *ring = adapter->rx_ring[i];
4674 if (orig_node == -1) {
4675 int cur_node = next_online_node(adapter->node);
4676 if (cur_node == MAX_NUMNODES)
4677 cur_node = first_online_node;
4678 adapter->node = cur_node;
4679 }
4680 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4681 adapter->node);
4a0b9ca0
PW		 4682 if (!ring)
4683 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4684 if (!ring)
4685 goto err_rx_ring_allocation;
b6ec895e 4686 ring->count = rx_count;
4a0b9ca0 4687 ring->queue_index = i;
b6ec895e 4688 ring->dev = &adapter->pdev->dev;
fc77dc3c 4689 ring->netdev = adapter->netdev;
4a0b9ca0
PW		 4690 ring->numa_node = adapter->node;
4691
4692 adapter->rx_ring[i] = ring;
021230d4
AV		 4693 }
4694
4a0b9ca0
PW		 4695 /* Restore the adapter's original node */
4696 adapter->node = orig_node;
4697
021230d4
AV		 4698 ixgbe_cache_ring_register(adapter);
4699
4700 return 0;
4701
4702err_rx_ring_allocation:
4a0b9ca0
PW		 4703 for (i = 0; i < adapter->num_tx_queues; i++)
4704 kfree(adapter->tx_ring[i]);
021230d4
AV		 4705err_tx_ring_allocation:
4706 return -ENOMEM;
4707}
4708
4709/**
4710 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4711 * @adapter: board private structure to initialize
4712 *
4713 * Attempt to configure the interrupts using the best available
4714 * capabilities of the hardware and the kernel.
4715 **/
feea6a57 4716static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4717{
8be0e467 4718 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4719 int err = 0;
4720 int vector, v_budget;
4721
4722 /*
4723 * It's easy to be greedy for MSI-X vectors, but it really
4724 * doesn't do us much good if we have a lot more vectors
4725 * than CPU's. So let's be conservative and only ask for
342bde1b 4726 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4727 */
4728 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4729 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4730
4731 /*
4732 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4733 * hw.mac->max_msix_vectors vectors. With features
4734 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4735 * descriptor queues supported by our device. Thus, we cap it off in
4736 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4737 */
8be0e467 4738 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4739
4740 /* A failure in MSI-X entry allocation isn't fatal, but it does
4741 * mean we disable MSI-X capabilities of the adapter. */
4742 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4743 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4744 if (adapter->msix_entries) {
4745 for (vector = 0; vector < v_budget; vector++)
4746 adapter->msix_entries[vector].entry = vector;
021230d4 4747
7a921c93 4748 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4749
7a921c93
AD		 4750 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4751 goto out;
4752 }
26d27844 4753
7a921c93
AD		 4754 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4755 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4756 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4757 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4758 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4759 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4760 ixgbe_disable_sriov(adapter);
4761
847f53ff
BH		 4762 err = ixgbe_set_num_queues(adapter);
4763 if (err)
4764 return err;
021230d4 4765
021230d4
AV		 4766 err = pci_enable_msi(adapter->pdev);
4767 if (!err) {
4768 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4769 } else {
849c4542
ET		 4770 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4771 "Unable to allocate MSI interrupt, "
4772 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4773 /* reset err */
4774 err = 0;
4775 }
4776
4777out:
021230d4
AV		 4778 return err;
4779}
4780
7a921c93
AD		 4781/**
4782 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4783 * @adapter: board private structure to initialize
4784 *
4785 * We allocate one q_vector per queue interrupt. If allocation fails we
4786 * return -ENOMEM.
4787 **/
4788static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4789{
4790 int q_idx, num_q_vectors;
4791 struct ixgbe_q_vector *q_vector;
4792 int napi_vectors;
4793 int (*poll)(struct napi_struct *, int);
4794
4795 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4796 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4797 napi_vectors = adapter->num_rx_queues;
91281fd3 4798 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4799 } else {
4800 num_q_vectors = 1;
4801 napi_vectors = 1;
4802 poll = &ixgbe_poll;
4803 }
4804
4805 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4806 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4807 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4808 if (!q_vector)
4809 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4810 GFP_KERNEL);
7a921c93
AD		 4811 if (!q_vector)
4812 goto err_out;
4813 q_vector->adapter = adapter;
f7554a2b
NS		 4814 if (q_vector->txr_count && !q_vector->rxr_count)
4815 q_vector->eitr = adapter->tx_eitr_param;
4816 else
4817 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4818 q_vector->v_idx = q_idx;
91281fd3 4819 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4820 adapter->q_vector[q_idx] = q_vector;
4821 }
4822
4823 return 0;
4824
4825err_out:
4826 while (q_idx) {
4827 q_idx--;
4828 q_vector = adapter->q_vector[q_idx];
4829 netif_napi_del(&q_vector->napi);
4830 kfree(q_vector);
4831 adapter->q_vector[q_idx] = NULL;
4832 }
4833 return -ENOMEM;
4834}
4835
4836/**
4837 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4838 * @adapter: board private structure to initialize
4839 *
4840 * This function frees the memory allocated to the q_vectors. In addition if
4841 * NAPI is enabled it will delete any references to the NAPI struct prior
4842 * to freeing the q_vector.
4843 **/
4844static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4845{
4846 int q_idx, num_q_vectors;
7a921c93 4847
91281fd3 4848 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4849 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4850 else
7a921c93 4851 num_q_vectors = 1;
7a921c93
AD		 4852
4853 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4854 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4855 adapter->q_vector[q_idx] = NULL;
91281fd3 4856 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4857 kfree(q_vector);
4858 }
4859}
4860
7b25cdba 4861static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4862{
4863 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4864 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4865 pci_disable_msix(adapter->pdev);
4866 kfree(adapter->msix_entries);
4867 adapter->msix_entries = NULL;
4868 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4869 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4870 pci_disable_msi(adapter->pdev);
4871 }
021230d4
AV		 4872}
4873
4874/**
4875 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4876 * @adapter: board private structure to initialize
4877 *
4878 * We determine which interrupt scheme to use based on...
4879 * - Kernel support (MSI, MSI-X)
4880 * - which can be user-defined (via MODULE_PARAM)
4881 * - Hardware queue count (num_*_queues)
4882 * - defined by miscellaneous hardware support/features (RSS, etc.)
4883 **/
2f90b865 4884int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4885{
4886 int err;
4887
4888 /* Number of supported queues */
847f53ff
BH		 4889 err = ixgbe_set_num_queues(adapter);
4890 if (err)
4891 return err;
021230d4 4892
021230d4
AV		 4893 err = ixgbe_set_interrupt_capability(adapter);
4894 if (err) {
849c4542 4895 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4896 goto err_set_interrupt;
9a799d71
AK		 4897 }
4898
7a921c93
AD		 4899 err = ixgbe_alloc_q_vectors(adapter);
4900 if (err) {
849c4542 4901 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4902 goto err_alloc_q_vectors;
4903 }
4904
4905 err = ixgbe_alloc_queues(adapter);
4906 if (err) {
849c4542 4907 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4908 goto err_alloc_queues;
4909 }
4910
849c4542 4911 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4912 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4913 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4914
4915 set_bit(__IXGBE_DOWN, &adapter->state);
4916
9a799d71 4917 return 0;
021230d4 4918
7a921c93
AD		 4919err_alloc_queues:
4920 ixgbe_free_q_vectors(adapter);
4921err_alloc_q_vectors:
4922 ixgbe_reset_interrupt_capability(adapter);
021230d4 4923err_set_interrupt:
7a921c93
AD		 4924 return err;
4925}
4926
1a51502b
ED		 4927static void ring_free_rcu(struct rcu_head *head)
4928{
4929 kfree(container_of(head, struct ixgbe_ring, rcu));
4930}
4931
7a921c93
AD		 4932/**
4933 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4934 * @adapter: board private structure to clear interrupt scheme on
4935 *
4936 * We go through and clear interrupt specific resources and reset the structure
4937 * to pre-load conditions
4938 **/
4939void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4940{
4a0b9ca0
PW		 4941 int i;
4942
4943 for (i = 0; i < adapter->num_tx_queues; i++) {
4944 kfree(adapter->tx_ring[i]);
4945 adapter->tx_ring[i] = NULL;
4946 }
4947 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4948 struct ixgbe_ring *ring = adapter->rx_ring[i];
4949
4950 /* ixgbe_get_stats64() might access this ring, we must wait
4951 * a grace period before freeing it.
4952 */
4953 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 4954 adapter->rx_ring[i] = NULL;
4955 }
7a921c93
AD		 4956
4957 ixgbe_free_q_vectors(adapter);
4958 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4959}
4960
c4900be0
DS		 4961/**
4962 * ixgbe_sfp_timer - worker thread to find a missing module
4963 * @data: pointer to our adapter struct
4964 **/
4965static void ixgbe_sfp_timer(unsigned long data)
4966{
4967 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4968
4df10466
JB		 4969 /*
4970 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4971 * delays that sfp+ detection requires
4972 */
4973 schedule_work(&adapter->sfp_task);
4974}
4975
4976/**
4977 * ixgbe_sfp_task - worker thread to find a missing module
4978 * @work: pointer to work_struct containing our data
4979 **/
4980static void ixgbe_sfp_task(struct work_struct *work)
4981{
4982 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4983 struct ixgbe_adapter,
4984 sfp_task);
c4900be0
DS		 4985 struct ixgbe_hw *hw = &adapter->hw;
4986
4987 if ((hw->phy.type == ixgbe_phy_nl) &&
4988 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4989 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4990 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4991 goto reschedule;
4992 ret = hw->phy.ops.reset(hw);
4993 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4994 e_dev_err("failed to initialize because an unsupported "
4995 "SFP+ module type was detected.\n");
4996 e_dev_err("Reload the driver after installing a "
4997 "supported module.\n");
c4900be0
DS		 4998 unregister_netdev(adapter->netdev);
4999 } else {
396e799c 5000 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 5001 }
5002 /* don't need this routine any more */
5003 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5004 }
5005 return;
5006reschedule:
5007 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5008 mod_timer(&adapter->sfp_timer,
e8e9f696 5009 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 5010}
5011
9a799d71
AK		 5012/**
5013 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5014 * @adapter: board private structure to initialize
5015 *
5016 * ixgbe_sw_init initializes the Adapter private data structure.
5017 * Fields are initialized based on PCI device information and
5018 * OS network device settings (MTU size).
5019 **/
5020static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5021{
5022 struct ixgbe_hw *hw = &adapter->hw;
5023 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5024 struct net_device *dev = adapter->netdev;
021230d4 5025 unsigned int rss;
7a6b6f51 5026#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5027 int j;
5028 struct tc_configuration *tc;
5029#endif
16b61beb 5030 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5031
c44ade9e
JB		 5032 /* PCI config space info */
5033
5034 hw->vendor_id = pdev->vendor;
5035 hw->device_id = pdev->device;
5036 hw->revision_id = pdev->revision;
5037 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5038 hw->subsystem_device_id = pdev->subsystem_device;
5039
021230d4
AV		 5040 /* Set capability flags */
5041 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5042 adapter->ring_feature[RING_F_RSS].indices = rss;
5043 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5044 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5045 switch (hw->mac.type) {
5046 case ixgbe_mac_82598EB:
bf069c97
DS		 5047 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5048 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5049 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5050 break;
5051 case ixgbe_mac_82599EB:
e8e26350 5052 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5053 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5054 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5055 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5056 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 5057 if (dev->features & NETIF_F_NTUPLE) {
5058 /* Flow Director perfect filter enabled */
5059 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5060 adapter->atr_sample_rate = 0;
5061 spin_lock_init(&adapter->fdir_perfect_lock);
5062 } else {
5063 /* Flow Director hash filters enabled */
5064 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5065 adapter->atr_sample_rate = 20;
5066 }
c4cf55e5 5067 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5068 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5069 adapter->fdir_pballoc = 0;
eacd73f7 5070#ifdef IXGBE_FCOE
0d551589
YZ		 5071 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5072 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5073 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5074#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5075 /* Default traffic class to use for FCoE */
5076 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5077 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5078#endif
eacd73f7 5079#endif /* IXGBE_FCOE */
bd508178
AD		 5080 break;
5081 default:
5082 break;
f8212f97 5083 }
2f90b865 5084
7a6b6f51 5085#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5086 /* Configure DCB traffic classes */
5087 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5088 tc = &adapter->dcb_cfg.tc_config[j];
5089 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5090 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5091 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5092 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5093 tc->dcb_pfc = pfc_disabled;
5094 }
5095 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5096 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5097 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5098 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 5099 adapter->dcb_cfg.round_robin_enable = false;
5100 adapter->dcb_set_bitmap = 0x00;
5101 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 5102 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 5103
5104#endif
9a799d71
AK		 5105
5106 /* default flow control settings */
cd7664f6 5107 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5108 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5109#ifdef CONFIG_DCB
5110 adapter->last_lfc_mode = hw->fc.current_mode;
5111#endif
16b61beb
JF		 5112 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5113 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5114 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5115 hw->fc.send_xon = true;
71fd570b 5116 hw->fc.disable_fc_autoneg = false;
9a799d71 5117
30efa5a3 5118 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5119 adapter->rx_itr_setting = 1;
5120 adapter->rx_eitr_param = 20000;
5121 adapter->tx_itr_setting = 1;
5122 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5123
5124 /* set defaults for eitr in MegaBytes */
5125 adapter->eitr_low = 10;
5126 adapter->eitr_high = 20;
5127
5128 /* set default ring sizes */
5129 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5130 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5131
9a799d71 5132 /* initialize eeprom parameters */
c44ade9e 5133 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5134 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5135 return -EIO;
5136 }
5137
021230d4 5138 /* enable rx csum by default */
9a799d71
AK		 5139 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5140
1a6c14a2
JB		 5141 /* get assigned NUMA node */
5142 adapter->node = dev_to_node(&pdev->dev);
5143
9a799d71
AK		 5144 set_bit(__IXGBE_DOWN, &adapter->state);
5145
5146 return 0;
5147}
5148
5149/**
5150 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5151 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5152 *
5153 * Return 0 on success, negative on failure
5154 **/
b6ec895e 5155int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5156{
b6ec895e 5157 struct device *dev = tx_ring->dev;
9a799d71
AK		 5158 int size;
5159
3a581073 5160 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 5161 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 5162 if (!tx_ring->tx_buffer_info)
5163 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 5164 if (!tx_ring->tx_buffer_info)
5165 goto err;
3a581073 5166 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 5167
5168 /* round up to nearest 4K */
12207e49 5169 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5170 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5171
b6ec895e 5172 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5173 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5174 if (!tx_ring->desc)
5175 goto err;
9a799d71 5176
3a581073
JB		 5177 tx_ring->next_to_use = 0;
5178 tx_ring->next_to_clean = 0;
5179 tx_ring->work_limit = tx_ring->count;
9a799d71 5180 return 0;
e01c31a5
JB		 5181
5182err:
5183 vfree(tx_ring->tx_buffer_info);
5184 tx_ring->tx_buffer_info = NULL;
b6ec895e 5185 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5186 return -ENOMEM;
9a799d71
AK		 5187}
5188
69888674
AD		 5189/**
5190 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5191 * @adapter: board private structure
5192 *
5193 * If this function returns with an error, then it's possible one or
5194 * more of the rings is populated (while the rest are not). It is the
5195 * callers duty to clean those orphaned rings.
5196 *
5197 * Return 0 on success, negative on failure
5198 **/
5199static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5200{
5201 int i, err = 0;
5202
5203 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5204 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5205 if (!err)
5206 continue;
396e799c 5207 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5208 break;
5209 }
5210
5211 return err;
5212}
5213
9a799d71
AK		 5214/**
5215 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5216 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5217 *
5218 * Returns 0 on success, negative on failure
5219 **/
b6ec895e 5220int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5221{
b6ec895e 5222 struct device *dev = rx_ring->dev;
021230d4 5223 int size;
9a799d71 5224
3a581073 5225 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
b6ec895e 5226 rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
1a6c14a2
JB		 5227 if (!rx_ring->rx_buffer_info)
5228 rx_ring->rx_buffer_info = vmalloc(size);
b6ec895e
AD		 5229 if (!rx_ring->rx_buffer_info)
5230 goto err;
3a581073 5231 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5232
9a799d71 5233 /* Round up to nearest 4K */
3a581073
JB		 5234 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5235 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5236
b6ec895e 5237 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5238 &rx_ring->dma, GFP_KERNEL);
9a799d71 5239
b6ec895e
AD		 5240 if (!rx_ring->desc)
5241 goto err;
9a799d71 5242
3a581073
JB		 5243 rx_ring->next_to_clean = 0;
5244 rx_ring->next_to_use = 0;
9a799d71
AK		 5245
5246 return 0;
b6ec895e
AD		 5247err:
5248 vfree(rx_ring->rx_buffer_info);
5249 rx_ring->rx_buffer_info = NULL;
5250 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5251 return -ENOMEM;
9a799d71
AK		 5252}
5253
69888674
AD		 5254/**
5255 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5256 * @adapter: board private structure
5257 *
5258 * If this function returns with an error, then it's possible one or
5259 * more of the rings is populated (while the rest are not). It is the
5260 * callers duty to clean those orphaned rings.
5261 *
5262 * Return 0 on success, negative on failure
5263 **/
69888674
AD		 5264static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5265{
5266 int i, err = 0;
5267
5268 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5269 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5270 if (!err)
5271 continue;
396e799c 5272 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5273 break;
5274 }
5275
5276 return err;
5277}
5278
9a799d71
AK		 5279/**
5280 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5281 * @tx_ring: Tx descriptor ring for a specific queue
5282 *
5283 * Free all transmit software resources
5284 **/
b6ec895e 5285void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5286{
b6ec895e 5287 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5288
5289 vfree(tx_ring->tx_buffer_info);
5290 tx_ring->tx_buffer_info = NULL;
5291
b6ec895e
AD		 5292 /* if not set, then don't free */
5293 if (!tx_ring->desc)
5294 return;
5295
5296 dma_free_coherent(tx_ring->dev, tx_ring->size,
5297 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5298
5299 tx_ring->desc = NULL;
5300}
5301
5302/**
5303 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5304 * @adapter: board private structure
5305 *
5306 * Free all transmit software resources
5307 **/
5308static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5309{
5310 int i;
5311
5312 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5313 if (adapter->tx_ring[i]->desc)
b6ec895e 5314 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5315}
5316
5317/**
b4617240 5318 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5319 * @rx_ring: ring to clean the resources from
5320 *
5321 * Free all receive software resources
5322 **/
b6ec895e 5323void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5324{
b6ec895e 5325 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5326
5327 vfree(rx_ring->rx_buffer_info);
5328 rx_ring->rx_buffer_info = NULL;
5329
b6ec895e
AD		 5330 /* if not set, then don't free */
5331 if (!rx_ring->desc)
5332 return;
5333
5334 dma_free_coherent(rx_ring->dev, rx_ring->size,
5335 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5336
5337 rx_ring->desc = NULL;
5338}
5339
5340/**
5341 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5342 * @adapter: board private structure
5343 *
5344 * Free all receive software resources
5345 **/
5346static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5347{
5348 int i;
5349
5350 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5351 if (adapter->rx_ring[i]->desc)
b6ec895e 5352 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5353}
5354
9a799d71
AK		 5355/**
5356 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5357 * @netdev: network interface device structure
5358 * @new_mtu: new value for maximum frame size
5359 *
5360 * Returns 0 on success, negative on failure
5361 **/
5362static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5363{
5364 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5365 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5366 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5367
42c783c5
JB		 5368 /* MTU < 68 is an error and causes problems on some kernels */
5369 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5370 return -EINVAL;
5371
396e799c 5372 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5373 /* must set new MTU before calling down or up */
9a799d71
AK		 5374 netdev->mtu = new_mtu;
5375
16b61beb
JF		 5376 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5377 hw->fc.low_water = FC_LOW_WATER(max_frame);
5378
d4f80882
AV		 5379 if (netif_running(netdev))
5380 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5381
5382 return 0;
5383}
5384
5385/**
5386 * ixgbe_open - Called when a network interface is made active
5387 * @netdev: network interface device structure
5388 *
5389 * Returns 0 on success, negative value on failure
5390 *
5391 * The open entry point is called when a network interface is made
5392 * active by the system (IFF_UP). At this point all resources needed
5393 * for transmit and receive operations are allocated, the interrupt
5394 * handler is registered with the OS, the watchdog timer is started,
5395 * and the stack is notified that the interface is ready.
5396 **/
5397static int ixgbe_open(struct net_device *netdev)
5398{
5399 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5400 int err;
4bebfaa5
AK		 5401
5402 /* disallow open during test */
5403 if (test_bit(__IXGBE_TESTING, &adapter->state))
5404 return -EBUSY;
9a799d71 5405
54386467
JB		 5406 netif_carrier_off(netdev);
5407
9a799d71
AK		 5408 /* allocate transmit descriptors */
5409 err = ixgbe_setup_all_tx_resources(adapter);
5410 if (err)
5411 goto err_setup_tx;
5412
9a799d71
AK		 5413 /* allocate receive descriptors */
5414 err = ixgbe_setup_all_rx_resources(adapter);
5415 if (err)
5416 goto err_setup_rx;
5417
5418 ixgbe_configure(adapter);
5419
021230d4 5420 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5421 if (err)
5422 goto err_req_irq;
5423
9a799d71
AK		 5424 err = ixgbe_up_complete(adapter);
5425 if (err)
5426 goto err_up;
5427
d55b53ff
JK		 5428 netif_tx_start_all_queues(netdev);
5429
9a799d71
AK		 5430 return 0;
5431
5432err_up:
5eba3699 5433 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5434 ixgbe_free_irq(adapter);
5435err_req_irq:
9a799d71 5436err_setup_rx:
a20a1199 5437 ixgbe_free_all_rx_resources(adapter);
9a799d71 5438err_setup_tx:
a20a1199 5439 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5440 ixgbe_reset(adapter);
5441
5442 return err;
5443}
5444
5445/**
5446 * ixgbe_close - Disables a network interface
5447 * @netdev: network interface device structure
5448 *
5449 * Returns 0, this is not allowed to fail
5450 *
5451 * The close entry point is called when an interface is de-activated
5452 * by the OS. The hardware is still under the drivers control, but
5453 * needs to be disabled. A global MAC reset is issued to stop the
5454 * hardware, and all transmit and receive resources are freed.
5455 **/
5456static int ixgbe_close(struct net_device *netdev)
5457{
5458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5459
5460 ixgbe_down(adapter);
5461 ixgbe_free_irq(adapter);
5462
5463 ixgbe_free_all_tx_resources(adapter);
5464 ixgbe_free_all_rx_resources(adapter);
5465
5eba3699 5466 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5467
5468 return 0;
5469}
5470
b3c8b4ba
AD		 5471#ifdef CONFIG_PM
5472static int ixgbe_resume(struct pci_dev *pdev)
5473{
c60fbb00
AD		 5474 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5475 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5476 u32 err;
5477
5478 pci_set_power_state(pdev, PCI_D0);
5479 pci_restore_state(pdev);
656ab817
DS		 5480 /*
5481 * pci_restore_state clears dev->state_saved so call
5482 * pci_save_state to restore it.
5483 */
5484 pci_save_state(pdev);
9ce77666 5485
5486 err = pci_enable_device_mem(pdev);
b3c8b4ba 5487 if (err) {
849c4542 5488 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5489 return err;
5490 }
5491 pci_set_master(pdev);
5492
dd4d8ca6 5493 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5494
5495 err = ixgbe_init_interrupt_scheme(adapter);
5496 if (err) {
849c4542 5497 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5498 return err;
5499 }
5500
b3c8b4ba
AD		 5501 ixgbe_reset(adapter);
5502
495dce12
WJP		 5503 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5504
b3c8b4ba 5505 if (netif_running(netdev)) {
c60fbb00 5506 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5507 if (err)
5508 return err;
5509 }
5510
5511 netif_device_attach(netdev);
5512
5513 return 0;
5514}
b3c8b4ba 5515#endif /* CONFIG_PM */
9d8d05ae
RW		 5516
5517static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5518{
c60fbb00
AD		 5519 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5520 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5521 struct ixgbe_hw *hw = &adapter->hw;
5522 u32 ctrl, fctrl;
5523 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5524#ifdef CONFIG_PM
5525 int retval = 0;
5526#endif
5527
5528 netif_device_detach(netdev);
5529
5530 if (netif_running(netdev)) {
5531 ixgbe_down(adapter);
5532 ixgbe_free_irq(adapter);
5533 ixgbe_free_all_tx_resources(adapter);
5534 ixgbe_free_all_rx_resources(adapter);
5535 }
b3c8b4ba 5536
5f5ae6fc
AD		 5537 ixgbe_clear_interrupt_scheme(adapter);
5538
b3c8b4ba
AD		 5539#ifdef CONFIG_PM
5540 retval = pci_save_state(pdev);
5541 if (retval)
5542 return retval;
4df10466 5543
b3c8b4ba 5544#endif
e8e26350
PW		 5545 if (wufc) {
5546 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5547
e8e26350
PW		 5548 /* turn on all-multi mode if wake on multicast is enabled */
5549 if (wufc & IXGBE_WUFC_MC) {
5550 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5551 fctrl |= IXGBE_FCTRL_MPE;
5552 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5553 }
5554
5555 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5556 ctrl |= IXGBE_CTRL_GIO_DIS;
5557 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5558
5559 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5560 } else {
5561 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5562 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5563 }
5564
bd508178
AD		 5565 switch (hw->mac.type) {
5566 case ixgbe_mac_82598EB:
dd4d8ca6 5567 pci_wake_from_d3(pdev, false);
bd508178
AD		 5568 break;
5569 case ixgbe_mac_82599EB:
5570 pci_wake_from_d3(pdev, !!wufc);
5571 break;
5572 default:
5573 break;
5574 }
b3c8b4ba 5575
9d8d05ae
RW		 5576 *enable_wake = !!wufc;
5577
b3c8b4ba
AD		 5578 ixgbe_release_hw_control(adapter);
5579
5580 pci_disable_device(pdev);
5581
9d8d05ae
RW		 5582 return 0;
5583}
5584
5585#ifdef CONFIG_PM
5586static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5587{
5588 int retval;
5589 bool wake;
5590
5591 retval = __ixgbe_shutdown(pdev, &wake);
5592 if (retval)
5593 return retval;
5594
5595 if (wake) {
5596 pci_prepare_to_sleep(pdev);
5597 } else {
5598 pci_wake_from_d3(pdev, false);
5599 pci_set_power_state(pdev, PCI_D3hot);
5600 }
b3c8b4ba
AD		 5601
5602 return 0;
5603}
9d8d05ae 5604#endif /* CONFIG_PM */
b3c8b4ba
AD		 5605
5606static void ixgbe_shutdown(struct pci_dev *pdev)
5607{
9d8d05ae
RW		 5608 bool wake;
5609
5610 __ixgbe_shutdown(pdev, &wake);
5611
5612 if (system_state == SYSTEM_POWER_OFF) {
5613 pci_wake_from_d3(pdev, wake);
5614 pci_set_power_state(pdev, PCI_D3hot);
5615 }
b3c8b4ba
AD		 5616}
5617
9a799d71
AK		 5618/**
5619 * ixgbe_update_stats - Update the board statistics counters.
5620 * @adapter: board private structure
5621 **/
5622void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5623{
2d86f139 5624 struct net_device *netdev = adapter->netdev;
9a799d71 5625 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5626 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5627 u64 total_mpc = 0;
5628 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5629 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5630 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5631 u64 bytes = 0, packets = 0;
9a799d71 5632
d08935c2
DS		 5633 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5634 test_bit(__IXGBE_RESETTING, &adapter->state))
5635 return;
5636
94b982b2 5637 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5638 u64 rsc_count = 0;
94b982b2 5639 u64 rsc_flush = 0;
d51019a4
PW		 5640 for (i = 0; i < 16; i++)
5641 adapter->hw_rx_no_dma_resources +=
7ca647bd 5642 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5643 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5644 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5645 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5646 }
5647 adapter->rsc_total_count = rsc_count;
5648 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5649 }
5650
5b7da515
AD		 5651 for (i = 0; i < adapter->num_rx_queues; i++) {
5652 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5653 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5654 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5655 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5656 bytes += rx_ring->stats.bytes;
5657 packets += rx_ring->stats.packets;
5658 }
5659 adapter->non_eop_descs = non_eop_descs;
5660 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5661 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5662 netdev->stats.rx_bytes = bytes;
5663 netdev->stats.rx_packets = packets;
5664
5665 bytes = 0;
5666 packets = 0;
7ca3bc58 5667 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5668 for (i = 0; i < adapter->num_tx_queues; i++) {
5669 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5670 restart_queue += tx_ring->tx_stats.restart_queue;
5671 tx_busy += tx_ring->tx_stats.tx_busy;
5672 bytes += tx_ring->stats.bytes;
5673 packets += tx_ring->stats.packets;
5674 }
eb985f09 5675 adapter->restart_queue = restart_queue;
5b7da515
AD		 5676 adapter->tx_busy = tx_busy;
5677 netdev->stats.tx_bytes = bytes;
5678 netdev->stats.tx_packets = packets;
7ca3bc58 5679
7ca647bd 5680 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5681 for (i = 0; i < 8; i++) {
5682 /* for packet buffers not used, the register should read 0 */
5683 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5684 missed_rx += mpc;
7ca647bd
JP		 5685 hwstats->mpc[i] += mpc;
5686 total_mpc += hwstats->mpc[i];
e8e26350 5687 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5688 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5689 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5690 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5691 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5692 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5693 switch (hw->mac.type) {
5694 case ixgbe_mac_82598EB:
7ca647bd
JP		 5695 hwstats->pxonrxc[i] +=
5696 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5697 break;
5698 case ixgbe_mac_82599EB:
5699 hwstats->pxonrxc[i] +=
5700 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5701 break;
5702 default:
5703 break;
e8e26350 5704 }
7ca647bd
JP		 5705 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5706 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5707 }
7ca647bd 5708 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5709 /* work around hardware counting issue */
7ca647bd 5710 hwstats->gprc -= missed_rx;
6f11eef7 5711
c84d324c
JF		 5712 ixgbe_update_xoff_received(adapter);
5713
6f11eef7 5714 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5715 switch (hw->mac.type) {
5716 case ixgbe_mac_82598EB:
5717 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5718 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5719 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5720 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5721 break;
5722 case ixgbe_mac_82599EB:
7ca647bd 5723 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5724 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5725 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5726 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5727 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5728 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5729 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5730 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5731 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5732#ifdef IXGBE_FCOE
7ca647bd
JP		 5733 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5734 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5735 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5736 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5737 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5738 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5739#endif /* IXGBE_FCOE */
bd508178
AD		 5740 break;
5741 default:
5742 break;
e8e26350 5743 }
9a799d71 5744 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5745 hwstats->bprc += bprc;
5746 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5747 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5748 hwstats->mprc -= bprc;
5749 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5750 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5751 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5752 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5753 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5754 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5755 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5756 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5757 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5758 hwstats->lxontxc += lxon;
6f11eef7 5759 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5760 hwstats->lxofftxc += lxoff;
5761 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5762 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5763 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5764 /*
5765 * 82598 errata - tx of flow control packets is included in tx counters
5766 */
5767 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5768 hwstats->gptc -= xon_off_tot;
5769 hwstats->mptc -= xon_off_tot;
5770 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5771 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5772 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5773 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5774 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5775 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5776 hwstats->ptc64 -= xon_off_tot;
5777 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5778 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5779 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5780 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5781 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5782 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5783
5784 /* Fill out the OS statistics structure */
7ca647bd 5785 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5786
5787 /* Rx Errors */
7ca647bd 5788 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5789 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5790 netdev->stats.rx_length_errors = hwstats->rlec;
5791 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5792 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5793}
5794
5795/**
5796 * ixgbe_watchdog - Timer Call-back
5797 * @data: pointer to adapter cast into an unsigned long
5798 **/
5799static void ixgbe_watchdog(unsigned long data)
5800{
5801 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5802 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5803 u64 eics = 0;
5804 int i;
cf8280ee 5805
fe49f04a
AD		 5806 /*
5807 * Do the watchdog outside of interrupt context due to the lovely
5808 * delays that some of the newer hardware requires
5809 */
22d5a71b 5810
fe49f04a
AD		 5811 if (test_bit(__IXGBE_DOWN, &adapter->state))
5812 goto watchdog_short_circuit;
22d5a71b 5813
fe49f04a
AD		 5814 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5815 /*
5816 * for legacy and MSI interrupts don't set any bits
5817 * that are enabled for EIAM, because this operation
5818 * would set *both* EIMS and EICS for any bit in EIAM
5819 */
5820 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5821 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5822 goto watchdog_reschedule;
5823 }
5824
5825 /* get one bit for every active tx/rx interrupt vector */
5826 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5827 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5828 if (qv->rxr_count || qv->txr_count)
5829 eics |= ((u64)1 << i);
cf8280ee 5830 }
9a799d71 5831
fe49f04a
AD		 5832 /* Cause software interrupt to ensure rx rings are cleaned */
5833 ixgbe_irq_rearm_queues(adapter, eics);
5834
5835watchdog_reschedule:
5836 /* Reset the timer */
5837 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5838
5839watchdog_short_circuit:
cf8280ee
JB		 5840 schedule_work(&adapter->watchdog_task);
5841}
5842
e8e26350
PW		 5843/**
5844 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5845 * @work: pointer to work_struct containing our data
5846 **/
5847static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5848{
5849 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5850 struct ixgbe_adapter,
5851 multispeed_fiber_task);
e8e26350
PW		 5852 struct ixgbe_hw *hw = &adapter->hw;
5853 u32 autoneg;
8620a103 5854 bool negotiation;
e8e26350
PW		 5855
5856 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5857 autoneg = hw->phy.autoneg_advertised;
5858 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5859 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5860 hw->mac.autotry_restart = false;
8620a103
MC		 5861 if (hw->mac.ops.setup_link)
5862 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5863 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5864 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5865}
5866
5867/**
5868 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5869 * @work: pointer to work_struct containing our data
5870 **/
5871static void ixgbe_sfp_config_module_task(struct work_struct *work)
5872{
5873 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5874 struct ixgbe_adapter,
5875 sfp_config_module_task);
e8e26350
PW		 5876 struct ixgbe_hw *hw = &adapter->hw;
5877 u32 err;
5878
5879 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5880
5881 /* Time for electrical oscillations to settle down */
5882 msleep(100);
e8e26350 5883 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5884
e8e26350 5885 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5886 e_dev_err("failed to initialize because an unsupported SFP+ "
5887 "module type was detected.\n");
5888 e_dev_err("Reload the driver after installing a supported "
5889 "module.\n");
63d6e1d8 5890 unregister_netdev(adapter->netdev);
e8e26350
PW		 5891 return;
5892 }
5893 hw->mac.ops.setup_sfp(hw);
5894
8d1c3c07 5895 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5896 /* This will also work for DA Twinax connections */
5897 schedule_work(&adapter->multispeed_fiber_task);
5898 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5899}
5900
c4cf55e5
PWJ		 5901/**
5902 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5903 * @work: pointer to work_struct containing our data
5904 **/
5905static void ixgbe_fdir_reinit_task(struct work_struct *work)
5906{
5907 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5908 struct ixgbe_adapter,
5909 fdir_reinit_task);
c4cf55e5
PWJ		 5910 struct ixgbe_hw *hw = &adapter->hw;
5911 int i;
5912
5913 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5914 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 5915 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5916 &(adapter->tx_ring[i]->state));
c4cf55e5 5917 } else {
396e799c 5918 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5919 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5920 }
5921 /* Done FDIR Re-initialization, enable transmits */
5922 netif_tx_start_all_queues(adapter->netdev);
5923}
5924
10eec955
JF		 5925static DEFINE_MUTEX(ixgbe_watchdog_lock);
5926
cf8280ee 5927/**
69888674
AD		 5928 * ixgbe_watchdog_task - worker thread to bring link up
5929 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5930 **/
5931static void ixgbe_watchdog_task(struct work_struct *work)
5932{
5933 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5934 struct ixgbe_adapter,
5935 watchdog_task);
cf8280ee
JB		 5936 struct net_device *netdev = adapter->netdev;
5937 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5938 u32 link_speed;
5939 bool link_up;
bc59fcda
NS		 5940 int i;
5941 struct ixgbe_ring *tx_ring;
5942 int some_tx_pending = 0;
cf8280ee 5943
10eec955
JF		 5944 mutex_lock(&ixgbe_watchdog_lock);
5945
5946 link_up = adapter->link_up;
5947 link_speed = adapter->link_speed;
cf8280ee
JB		 5948
5949 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5950 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5951 if (link_up) {
5952#ifdef CONFIG_DCB
5953 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5954 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5955 hw->mac.ops.fc_enable(hw, i);
264857b8 5956 } else {
620fa036 5957 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5958 }
5959#else
620fa036 5960 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5961#endif
5962 }
5963
cf8280ee
JB		 5964 if (link_up ||
5965 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5966 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5967 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5968 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5969 }
5970 adapter->link_up = link_up;
5971 adapter->link_speed = link_speed;
5972 }
9a799d71
AK		 5973
5974 if (link_up) {
5975 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5976 bool flow_rx, flow_tx;
5977
bd508178
AD		 5978 switch (hw->mac.type) {
5979 case ixgbe_mac_82598EB: {
e8e26350
PW		 5980 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5981 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5982 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5983 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350 5984 }
bd508178
AD		 5985 break;
5986 case ixgbe_mac_82599EB: {
5987 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5988 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5989 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5990 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5991 }
5992 break;
5993 default:
5994 flow_tx = false;
5995 flow_rx = false;
5996 break;
5997 }
e8e26350 5998
396e799c 5999 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 6000 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 6001 "10 Gbps" :
6002 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6003 "1 Gbps" : "unknown speed")),
e8e26350 6004 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 6005 (flow_rx ? "RX" :
6006 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 6007
6008 netif_carrier_on(netdev);
9a799d71
AK		 6009 } else {
6010 /* Force detection of hung controller */
7d637bcc
AD		 6011 for (i = 0; i < adapter->num_tx_queues; i++) {
6012 tx_ring = adapter->tx_ring[i];
6013 set_check_for_tx_hang(tx_ring);
6014 }
9a799d71
AK		 6015 }
6016 } else {
cf8280ee
JB		 6017 adapter->link_up = false;
6018 adapter->link_speed = 0;
9a799d71 6019 if (netif_carrier_ok(netdev)) {
396e799c 6020 e_info(drv, "NIC Link is Down\n");
9a799d71 6021 netif_carrier_off(netdev);
9a799d71
AK		 6022 }
6023 }
6024
bc59fcda
NS		 6025 if (!netif_carrier_ok(netdev)) {
6026 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 6027 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6028 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6029 some_tx_pending = 1;
6030 break;
6031 }
6032 }
6033
6034 if (some_tx_pending) {
6035 /* We've lost link, so the controller stops DMA,
6036 * but we've got queued Tx work that's never going
6037 * to get done, so reset controller to flush Tx.
6038 * (Do the reset outside of interrupt context).
6039 */
6040 schedule_work(&adapter->reset_task);
6041 }
6042 }
6043
9a799d71 6044 ixgbe_update_stats(adapter);
10eec955 6045 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 6046}
6047
9a799d71 6048static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6049 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6050 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6051{
6052 struct ixgbe_adv_tx_context_desc *context_desc;
6053 unsigned int i;
6054 int err;
6055 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6056 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6057 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6058
6059 if (skb_is_gso(skb)) {
6060 if (skb_header_cloned(skb)) {
6061 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6062 if (err)
6063 return err;
6064 }
6065 l4len = tcp_hdrlen(skb);
6066 *hdr_len += l4len;
6067
5e09a105 6068 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6069 struct iphdr *iph = ip_hdr(skb);
6070 iph->tot_len = 0;
6071 iph->check = 0;
6072 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6073 iph->daddr, 0,
6074 IPPROTO_TCP,
6075 0);
8e1e8a47 6076 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6077 ipv6_hdr(skb)->payload_len = 0;
6078 tcp_hdr(skb)->check =
6079 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6080 &ipv6_hdr(skb)->daddr,
6081 0, IPPROTO_TCP, 0);
9a799d71
AK		 6082 }
6083
6084 i = tx_ring->next_to_use;
6085
6086 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6087 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6088
6089 /* VLAN MACLEN IPLEN */
6090 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6091 vlan_macip_lens |=
6092 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6093 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6094 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6095 *hdr_len += skb_network_offset(skb);
6096 vlan_macip_lens |=
6097 (skb_transport_header(skb) - skb_network_header(skb));
6098 *hdr_len +=
6099 (skb_transport_header(skb) - skb_network_header(skb));
6100 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6101 context_desc->seqnum_seed = 0;
6102
6103 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6104 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6105 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6106
5e09a105 6107 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6108 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6109 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6110 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6111
6112 /* MSS L4LEN IDX */
9f8cdf4f 6113 mss_l4len_idx =
9a799d71
AK		 6114 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6115 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6116 /* use index 1 for TSO */
6117 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6118 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6119
6120 tx_buffer_info->time_stamp = jiffies;
6121 tx_buffer_info->next_to_watch = i;
6122
6123 i++;
6124 if (i == tx_ring->count)
6125 i = 0;
6126 tx_ring->next_to_use = i;
6127
6128 return true;
6129 }
6130 return false;
6131}
6132
5e09a105
HZ		 6133static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6134 __be16 protocol)
7ca647bd
JP		 6135{
6136 u32 rtn = 0;
7ca647bd
JP		 6137
6138 switch (protocol) {
6139 case cpu_to_be16(ETH_P_IP):
6140 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6141 switch (ip_hdr(skb)->protocol) {
6142 case IPPROTO_TCP:
6143 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6144 break;
6145 case IPPROTO_SCTP:
6146 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6147 break;
6148 }
6149 break;
6150 case cpu_to_be16(ETH_P_IPV6):
6151 /* XXX what about other V6 headers?? */
6152 switch (ipv6_hdr(skb)->nexthdr) {
6153 case IPPROTO_TCP:
6154 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6155 break;
6156 case IPPROTO_SCTP:
6157 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6158 break;
6159 }
6160 break;
6161 default:
6162 if (unlikely(net_ratelimit()))
6163 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6164 protocol);
7ca647bd
JP		 6165 break;
6166 }
6167
6168 return rtn;
6169}
6170
9a799d71 6171static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6172 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6173 struct sk_buff *skb, u32 tx_flags,
6174 __be16 protocol)
9a799d71
AK		 6175{
6176 struct ixgbe_adv_tx_context_desc *context_desc;
6177 unsigned int i;
6178 struct ixgbe_tx_buffer *tx_buffer_info;
6179 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6180
6181 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6182 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6183 i = tx_ring->next_to_use;
6184 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6185 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6186
6187 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6188 vlan_macip_lens |=
6189 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6190 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6191 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6192 if (skb->ip_summed == CHECKSUM_PARTIAL)
6193 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6194 skb_network_header(skb));
9a799d71
AK		 6195
6196 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6197 context_desc->seqnum_seed = 0;
6198
6199 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6200 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6201
7ca647bd 6202 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6203 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6204
6205 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6206 /* use index zero for tx checksum offload */
9a799d71
AK		 6207 context_desc->mss_l4len_idx = 0;
6208
6209 tx_buffer_info->time_stamp = jiffies;
6210 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6211
9a799d71
AK		 6212 i++;
6213 if (i == tx_ring->count)
6214 i = 0;
6215 tx_ring->next_to_use = i;
6216
6217 return true;
6218 }
9f8cdf4f 6219
9a799d71
AK		 6220 return false;
6221}
6222
6223static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6224 struct ixgbe_ring *tx_ring,
6225 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6226 unsigned int first, const u8 hdr_len)
9a799d71 6227{
b6ec895e 6228 struct device *dev = tx_ring->dev;
9a799d71 6229 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6230 unsigned int len;
6231 unsigned int total = skb->len;
9a799d71
AK		 6232 unsigned int offset = 0, size, count = 0, i;
6233 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6234 unsigned int f;
8ad494b0
AD		 6235 unsigned int bytecount = skb->len;
6236 u16 gso_segs = 1;
9a799d71
AK		 6237
6238 i = tx_ring->next_to_use;
6239
eacd73f7
YZ		 6240 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6241 /* excluding fcoe_crc_eof for FCoE */
6242 total -= sizeof(struct fcoe_crc_eof);
6243
6244 len = min(skb_headlen(skb), total);
9a799d71
AK		 6245 while (len) {
6246 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6247 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6248
6249 tx_buffer_info->length = size;
e5a43549 6250 tx_buffer_info->mapped_as_page = false;
b6ec895e 6251 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6252 skb->data + offset,
1b507730 6253 size, DMA_TO_DEVICE);
b6ec895e 6254 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6255 goto dma_error;
9a799d71
AK		 6256 tx_buffer_info->time_stamp = jiffies;
6257 tx_buffer_info->next_to_watch = i;
6258
6259 len -= size;
eacd73f7 6260 total -= size;
9a799d71
AK		 6261 offset += size;
6262 count++;
44df32c5
AD		 6263
6264 if (len) {
6265 i++;
6266 if (i == tx_ring->count)
6267 i = 0;
6268 }
9a799d71
AK		 6269 }
6270
6271 for (f = 0; f < nr_frags; f++) {
6272 struct skb_frag_struct *frag;
6273
6274 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6275 len = min((unsigned int)frag->size, total);
e5a43549 6276 offset = frag->page_offset;
9a799d71
AK		 6277
6278 while (len) {
44df32c5
AD		 6279 i++;
6280 if (i == tx_ring->count)
6281 i = 0;
6282
9a799d71
AK		 6283 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6284 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6285
6286 tx_buffer_info->length = size;
b6ec895e 6287 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6288 frag->page,
6289 offset, size,
1b507730 6290 DMA_TO_DEVICE);
e5a43549 6291 tx_buffer_info->mapped_as_page = true;
b6ec895e 6292 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6293 goto dma_error;
9a799d71
AK		 6294 tx_buffer_info->time_stamp = jiffies;
6295 tx_buffer_info->next_to_watch = i;
6296
6297 len -= size;
eacd73f7 6298 total -= size;
9a799d71
AK		 6299 offset += size;
6300 count++;
9a799d71 6301 }
eacd73f7
YZ		 6302 if (total == 0)
6303 break;
9a799d71 6304 }
44df32c5 6305
8ad494b0
AD		 6306 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6307 gso_segs = skb_shinfo(skb)->gso_segs;
6308#ifdef IXGBE_FCOE
6309 /* adjust for FCoE Sequence Offload */
6310 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6311 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6312 skb_shinfo(skb)->gso_size);
6313#endif /* IXGBE_FCOE */
6314 bytecount += (gso_segs - 1) * hdr_len;
6315
6316 /* multiply data chunks by size of headers */
6317 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6318 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6319 tx_ring->tx_buffer_info[i].skb = skb;
6320 tx_ring->tx_buffer_info[first].next_to_watch = i;
6321
e5a43549
AD		 6322 return count;
6323
6324dma_error:
849c4542 6325 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6326
6327 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6328 tx_buffer_info->dma = 0;
6329 tx_buffer_info->time_stamp = 0;
6330 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6331 if (count)
6332 count--;
e5a43549
AD		 6333
6334 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6335 while (count--) {
e8e9f696 6336 if (i == 0)
e5a43549 6337 i += tx_ring->count;
c1fa347f 6338 i--;
e5a43549 6339 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6340 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6341 }
6342
e44d38e1 6343 return 0;
9a799d71
AK		 6344}
6345
84ea2591 6346static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6347 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6348{
6349 union ixgbe_adv_tx_desc *tx_desc = NULL;
6350 struct ixgbe_tx_buffer *tx_buffer_info;
6351 u32 olinfo_status = 0, cmd_type_len = 0;
6352 unsigned int i;
6353 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6354
6355 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6356
6357 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6358
6359 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6360 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6361
6362 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6363 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6364
6365 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6366 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6367
4eeae6fd
PW		 6368 /* use index 1 context for tso */
6369 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6370 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6371 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6372 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6373
6374 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6375 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6376 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6377
eacd73f7
YZ		 6378 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6379 olinfo_status |= IXGBE_ADVTXD_CC;
6380 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6381 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6382 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6383 }
6384
9a799d71
AK		 6385 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6386
6387 i = tx_ring->next_to_use;
6388 while (count--) {
6389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6390 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6391 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6392 tx_desc->read.cmd_type_len =
e8e9f696 6393 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6394 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6395 i++;
6396 if (i == tx_ring->count)
6397 i = 0;
6398 }
6399
6400 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6401
6402 /*
6403 * Force memory writes to complete before letting h/w
6404 * know there are new descriptors to fetch. (Only
6405 * applicable for weak-ordered memory model archs,
6406 * such as IA-64).
6407 */
6408 wmb();
6409
6410 tx_ring->next_to_use = i;
84ea2591 6411 writel(i, tx_ring->tail);
9a799d71
AK		 6412}
6413
c4cf55e5 6414static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
ee9e0f0b 6415 u8 queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6416{
c4cf55e5 6417 struct ixgbe_atr_input atr_input;
c4cf55e5
PWJ		 6418 struct iphdr *iph = ip_hdr(skb);
6419 struct ethhdr *eth = (struct ethhdr *)skb->data;
ee9e0f0b
AD		 6420 struct tcphdr *th;
6421 u16 vlan_id;
c4cf55e5 6422
ee9e0f0b
AD		 6423 /* Right now, we support IPv4 w/ TCP only */
6424 if (protocol != htons(ETH_P_IP) ||
6425 iph->protocol != IPPROTO_TCP)
d3ead241 6426 return;
c4cf55e5
PWJ		 6427
6428 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6429
6430 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6431 IXGBE_TX_FLAGS_VLAN_SHIFT;
ee9e0f0b
AD		 6432
6433 th = tcp_hdr(skb);
c4cf55e5
PWJ		 6434
6435 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
ee9e0f0b
AD		 6436 ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6437 ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6438 ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6439 ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
c4cf55e5 6440 /* src and dst are inverted, think how the receiver sees them */
ee9e0f0b
AD		 6441 ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6442 ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
c4cf55e5
PWJ		 6443
6444 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6445 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6446}
6447
fc77dc3c 6448static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6449{
fc77dc3c 6450 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6451 /* Herbert's original patch had:
6452 * smp_mb__after_netif_stop_queue();
6453 * but since that doesn't exist yet, just open code it. */
6454 smp_mb();
6455
6456 /* We need to check again in a case another CPU has just
6457 * made room available. */
6458 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6459 return -EBUSY;
6460
6461 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6462 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6463 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6464 return 0;
6465}
6466
fc77dc3c 6467static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6468{
6469 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6470 return 0;
fc77dc3c 6471 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6472}
6473
09a3b1f8
SH		 6474static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6475{
6476 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6477 int txq = smp_processor_id();
56075a98 6478#ifdef IXGBE_FCOE
5e09a105
HZ		 6479 __be16 protocol;
6480
6481 protocol = vlan_get_protocol(skb);
6482
6483 if ((protocol == htons(ETH_P_FCOE)) ||
6484 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6485 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6486 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6487 txq += adapter->ring_feature[RING_F_FCOE].mask;
6488 return txq;
4bc091d8 6489#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6490 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6491 txq = adapter->fcoe.up;
6492 return txq;
4bc091d8 6493#endif
56075a98
JF		 6494 }
6495 }
6496#endif
6497
fdd3d631
KK		 6498 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6499 while (unlikely(txq >= dev->real_num_tx_queues))
6500 txq -= dev->real_num_tx_queues;
5f715823 6501 return txq;
fdd3d631 6502 }
c4cf55e5 6503
2ea186ae
JF		 6504 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6505 if (skb->priority == TC_PRIO_CONTROL)
6506 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6507 else
6508 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6509 >> 13;
6510 return txq;
6511 }
09a3b1f8
SH		 6512
6513 return skb_tx_hash(dev, skb);
6514}
6515
fc77dc3c 6516netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6517 struct ixgbe_adapter *adapter,
6518 struct ixgbe_ring *tx_ring)
9a799d71 6519{
fc77dc3c 6520 struct net_device *netdev = tx_ring->netdev;
60d51134 6521 struct netdev_queue *txq;
9a799d71
AK		 6522 unsigned int first;
6523 unsigned int tx_flags = 0;
30eba97a 6524 u8 hdr_len = 0;
5f715823 6525 int tso;
9a799d71
AK		 6526 int count = 0;
6527 unsigned int f;
5e09a105
HZ		 6528 __be16 protocol;
6529
6530 protocol = vlan_get_protocol(skb);
9f8cdf4f 6531
eab6d18d 6532 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6533 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6534 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6535 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6536 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6537 }
6538 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6539 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6540 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6541 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6542 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6543 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6544 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6545 }
eacd73f7 6546
09ad1cc0 6547#ifdef IXGBE_FCOE
56075a98
JF		 6548 /* for FCoE with DCB, we force the priority to what
6549 * was specified by the switch */
6550 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6551 (protocol == htons(ETH_P_FCOE) ||
6552 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6553#ifdef CONFIG_IXGBE_DCB
6554 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6555 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6556 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6557 tx_flags |= ((adapter->fcoe.up << 13)
6558 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6559 }
6560#endif
ca77cd59 6561 /* flag for FCoE offloads */
5e09a105 6562 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6563 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6564 }
ca77cd59
RL		 6565#endif
6566
eacd73f7 6567 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6568 if (skb_is_gso(skb) ||
6569 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6570 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6571 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6572 count++;
6573
9f8cdf4f
JB		 6574 count += TXD_USE_COUNT(skb_headlen(skb));
6575 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6576 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6577
fc77dc3c 6578 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6579 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6580 return NETDEV_TX_BUSY;
6581 }
9a799d71 6582
9a799d71 6583 first = tx_ring->next_to_use;
eacd73f7
YZ		 6584 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6585#ifdef IXGBE_FCOE
6586 /* setup tx offload for FCoE */
6587 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6588 if (tso < 0) {
6589 dev_kfree_skb_any(skb);
6590 return NETDEV_TX_OK;
6591 }
6592 if (tso)
6593 tx_flags |= IXGBE_TX_FLAGS_FSO;
6594#endif /* IXGBE_FCOE */
6595 } else {
5e09a105 6596 if (protocol == htons(ETH_P_IP))
eacd73f7 6597 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6598 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6599 protocol);
eacd73f7
YZ		 6600 if (tso < 0) {
6601 dev_kfree_skb_any(skb);
6602 return NETDEV_TX_OK;
6603 }
9a799d71 6604
eacd73f7
YZ		 6605 if (tso)
6606 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6607 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6608 protocol) &&
eacd73f7
YZ		 6609 (skb->ip_summed == CHECKSUM_PARTIAL))
6610 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6611 }
9a799d71 6612
8ad494b0 6613 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6614 if (count) {
c4cf55e5
PWJ		 6615 /* add the ATR filter if ATR is on */
6616 if (tx_ring->atr_sample_rate) {
6617 ++tx_ring->atr_count;
6618 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
7d637bcc
AD		 6619 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6620 &tx_ring->state)) {
c4cf55e5 6621 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6622 tx_flags, protocol);
c4cf55e5
PWJ		 6623 tx_ring->atr_count = 0;
6624 }
6625 }
60d51134
ED		 6626 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6627 txq->tx_bytes += skb->len;
6628 txq->tx_packets++;
84ea2591 6629 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6630 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6631
44df32c5
AD		 6632 } else {
6633 dev_kfree_skb_any(skb);
6634 tx_ring->tx_buffer_info[first].time_stamp = 0;
6635 tx_ring->next_to_use = first;
6636 }
9a799d71
AK		 6637
6638 return NETDEV_TX_OK;
6639}
6640
84418e3b
AD		 6641static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6642{
6643 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6644 struct ixgbe_ring *tx_ring;
6645
6646 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6647 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6648}
6649
9a799d71
AK		 6650/**
6651 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6652 * @netdev: network interface device structure
6653 * @p: pointer to an address structure
6654 *
6655 * Returns 0 on success, negative on failure
6656 **/
6657static int ixgbe_set_mac(struct net_device *netdev, void *p)
6658{
6659 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6660 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6661 struct sockaddr *addr = p;
6662
6663 if (!is_valid_ether_addr(addr->sa_data))
6664 return -EADDRNOTAVAIL;
6665
6666 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6667 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6668
1cdd1ec8
GR		 6669 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6670 IXGBE_RAH_AV);
9a799d71
AK		 6671
6672 return 0;
6673}
6674
6b73e10d
BH		 6675static int
6676ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6677{
6678 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6679 struct ixgbe_hw *hw = &adapter->hw;
6680 u16 value;
6681 int rc;
6682
6683 if (prtad != hw->phy.mdio.prtad)
6684 return -EINVAL;
6685 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6686 if (!rc)
6687 rc = value;
6688 return rc;
6689}
6690
6691static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6692 u16 addr, u16 value)
6693{
6694 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6695 struct ixgbe_hw *hw = &adapter->hw;
6696
6697 if (prtad != hw->phy.mdio.prtad)
6698 return -EINVAL;
6699 return hw->phy.ops.write_reg(hw, addr, devad, value);
6700}
6701
6702static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6703{
6704 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6705
6706 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6707}
6708
0365e6e4
PW		 6709/**
6710 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6711 * netdev->dev_addrs
0365e6e4
PW		 6712 * @netdev: network interface device structure
6713 *
6714 * Returns non-zero on failure
6715 **/
6716static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6717{
6718 int err = 0;
6719 struct ixgbe_adapter *adapter = netdev_priv(dev);
6720 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6721
6722 if (is_valid_ether_addr(mac->san_addr)) {
6723 rtnl_lock();
6724 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6725 rtnl_unlock();
6726 }
6727 return err;
6728}
6729
6730/**
6731 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6732 * netdev->dev_addrs
0365e6e4
PW		 6733 * @netdev: network interface device structure
6734 *
6735 * Returns non-zero on failure
6736 **/
6737static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6738{
6739 int err = 0;
6740 struct ixgbe_adapter *adapter = netdev_priv(dev);
6741 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6742
6743 if (is_valid_ether_addr(mac->san_addr)) {
6744 rtnl_lock();
6745 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6746 rtnl_unlock();
6747 }
6748 return err;
6749}
6750
9a799d71
AK		 6751#ifdef CONFIG_NET_POLL_CONTROLLER
6752/*
6753 * Polling 'interrupt' - used by things like netconsole to send skbs
6754 * without having to re-enable interrupts. It's not called while
6755 * the interrupt routine is executing.
6756 */
6757static void ixgbe_netpoll(struct net_device *netdev)
6758{
6759 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6760 int i;
9a799d71 6761
1a647bd2
AD		 6762 /* if interface is down do nothing */
6763 if (test_bit(__IXGBE_DOWN, &adapter->state))
6764 return;
6765
9a799d71 6766 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6767 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6768 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6769 for (i = 0; i < num_q_vectors; i++) {
6770 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6771 ixgbe_msix_clean_many(0, q_vector);
6772 }
6773 } else {
6774 ixgbe_intr(adapter->pdev->irq, netdev);
6775 }
9a799d71 6776 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6777}
6778#endif
6779
de1036b1
ED		 6780static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6781 struct rtnl_link_stats64 *stats)
6782{
6783 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6784 int i;
6785
6786 /* accurate rx/tx bytes/packets stats */
6787 dev_txq_stats_fold(netdev, stats);
1a51502b 6788 rcu_read_lock();
de1036b1 6789 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6790 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6791 u64 bytes, packets;
6792 unsigned int start;
6793
1a51502b
ED		 6794 if (ring) {
6795 do {
6796 start = u64_stats_fetch_begin_bh(&ring->syncp);
6797 packets = ring->stats.packets;
6798 bytes = ring->stats.bytes;
6799 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6800 stats->rx_packets += packets;
6801 stats->rx_bytes += bytes;
6802 }
de1036b1 6803 }
1a51502b 6804 rcu_read_unlock();
de1036b1
ED		 6805 /* following stats updated by ixgbe_watchdog_task() */
6806 stats->multicast = netdev->stats.multicast;
6807 stats->rx_errors = netdev->stats.rx_errors;
6808 stats->rx_length_errors = netdev->stats.rx_length_errors;
6809 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6810 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6811 return stats;
6812}
6813
6814
0edc3527 6815static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6816 .ndo_open = ixgbe_open,
0edc3527 6817 .ndo_stop = ixgbe_close,
00829823 6818 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6819 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6820 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6821 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6822 .ndo_validate_addr = eth_validate_addr,
6823 .ndo_set_mac_address = ixgbe_set_mac,
6824 .ndo_change_mtu = ixgbe_change_mtu,
6825 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6826 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6827 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6828 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6829 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6830 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6831 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6832 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6833 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6834#ifdef CONFIG_NET_POLL_CONTROLLER
6835 .ndo_poll_controller = ixgbe_netpoll,
6836#endif
332d4a7d
YZ		 6837#ifdef IXGBE_FCOE
6838 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6839 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6840 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6841 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6842 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6843#endif /* IXGBE_FCOE */
0edc3527
SH		 6844};
6845
1cdd1ec8
GR		 6846static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6847 const struct ixgbe_info *ii)
6848{
6849#ifdef CONFIG_PCI_IOV
6850 struct ixgbe_hw *hw = &adapter->hw;
6851 int err;
6852
6853 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6854 return;
6855
6856 /* The 82599 supports up to 64 VFs per physical function
6857 * but this implementation limits allocation to 63 so that
6858 * basic networking resources are still available to the
6859 * physical function
6860 */
6861 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6862 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6863 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6864 if (err) {
396e799c 6865 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6866 goto err_novfs;
6867 }
6868 /* If call to enable VFs succeeded then allocate memory
6869 * for per VF control structures.
6870 */
6871 adapter->vfinfo =
6872 kcalloc(adapter->num_vfs,
6873 sizeof(struct vf_data_storage), GFP_KERNEL);
6874 if (adapter->vfinfo) {
6875 /* Now that we're sure SR-IOV is enabled
6876 * and memory allocated set up the mailbox parameters
6877 */
6878 ixgbe_init_mbx_params_pf(hw);
6879 memcpy(&hw->mbx.ops, ii->mbx_ops,
6880 sizeof(hw->mbx.ops));
6881
6882 /* Disable RSC when in SR-IOV mode */
6883 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6884 IXGBE_FLAG2_RSC_ENABLED);
6885 return;
6886 }
6887
6888 /* Oh oh */
396e799c
ET		 6889 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6890 "SRIOV disabled\n");
1cdd1ec8
GR		 6891 pci_disable_sriov(adapter->pdev);
6892
6893err_novfs:
6894 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6895 adapter->num_vfs = 0;
6896#endif /* CONFIG_PCI_IOV */
6897}
6898
9a799d71
AK		 6899/**
6900 * ixgbe_probe - Device Initialization Routine
6901 * @pdev: PCI device information struct
6902 * @ent: entry in ixgbe_pci_tbl
6903 *
6904 * Returns 0 on success, negative on failure
6905 *
6906 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6907 * The OS initialization, configuring of the adapter private structure,
6908 * and a hardware reset occur.
6909 **/
6910static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6911 const struct pci_device_id *ent)
9a799d71
AK		 6912{
6913 struct net_device *netdev;
6914 struct ixgbe_adapter *adapter = NULL;
6915 struct ixgbe_hw *hw;
6916 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6917 static int cards_found;
6918 int i, err, pci_using_dac;
c85a2618 6919 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6920#ifdef IXGBE_FCOE
6921 u16 device_caps;
6922#endif
c44ade9e 6923 u32 part_num, eec;
9a799d71 6924
bded64a7
AG		 6925 /* Catch broken hardware that put the wrong VF device ID in
6926 * the PCIe SR-IOV capability.
6927 */
6928 if (pdev->is_virtfn) {
6929 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6930 pci_name(pdev), pdev->vendor, pdev->device);
6931 return -EINVAL;
6932 }
6933
9ce77666 6934 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6935 if (err)
6936 return err;
6937
1b507730
NN		 6938 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6939 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6940 pci_using_dac = 1;
6941 } else {
1b507730 6942 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6943 if (err) {
1b507730
NN		 6944 err = dma_set_coherent_mask(&pdev->dev,
6945 DMA_BIT_MASK(32));
9a799d71 6946 if (err) {
b8bc0421
DC		 6947 dev_err(&pdev->dev,
6948 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6949 goto err_dma;
6950 }
6951 }
6952 pci_using_dac = 0;
6953 }
6954
9ce77666 6955 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6956 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6957 if (err) {
b8bc0421
DC		 6958 dev_err(&pdev->dev,
6959 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6960 goto err_pci_reg;
6961 }
6962
19d5afd4 6963 pci_enable_pcie_error_reporting(pdev);
6fabd715 6964
9a799d71 6965 pci_set_master(pdev);
fb3b27bc 6966 pci_save_state(pdev);
9a799d71 6967
c85a2618
JF		 6968 if (ii->mac == ixgbe_mac_82598EB)
6969 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6970 else
6971 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6972
6973 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6974#ifdef IXGBE_FCOE
6975 indices += min_t(unsigned int, num_possible_cpus(),
6976 IXGBE_MAX_FCOE_INDICES);
6977#endif
c85a2618 6978 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6979 if (!netdev) {
6980 err = -ENOMEM;
6981 goto err_alloc_etherdev;
6982 }
6983
9a799d71
AK		 6984 SET_NETDEV_DEV(netdev, &pdev->dev);
6985
9a799d71 6986 adapter = netdev_priv(netdev);
c60fbb00 6987 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 6988
6989 adapter->netdev = netdev;
6990 adapter->pdev = pdev;
6991 hw = &adapter->hw;
6992 hw->back = adapter;
6993 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6994
05857980 6995 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6996 pci_resource_len(pdev, 0));
9a799d71
AK		 6997 if (!hw->hw_addr) {
6998 err = -EIO;
6999 goto err_ioremap;
7000 }
7001
7002 for (i = 1; i <= 5; i++) {
7003 if (pci_resource_len(pdev, i) == 0)
7004 continue;
7005 }
7006
0edc3527 7007 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7008 ixgbe_set_ethtool_ops(netdev);
9a799d71 7009 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 7010 strcpy(netdev->name, pci_name(pdev));
7011
9a799d71
AK		 7012 adapter->bd_number = cards_found;
7013
9a799d71
AK		 7014 /* Setup hw api */
7015 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7016 hw->mac.type = ii->mac;
9a799d71 7017
c44ade9e
JB		 7018 /* EEPROM */
7019 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7020 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7021 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7022 if (!(eec & (1 << 8)))
7023 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7024
7025 /* PHY */
7026 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7027 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7028 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7029 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7030 hw->phy.mdio.mmds = 0;
7031 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7032 hw->phy.mdio.dev = netdev;
7033 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7034 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 7035
7036 /* set up this timer and work struct before calling get_invariants
7037 * which might start the timer
7038 */
7039 init_timer(&adapter->sfp_timer);
c061b18d 7040 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 7041 adapter->sfp_timer.data = (unsigned long) adapter;
7042
7043 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 7044
e8e26350
PW		 7045 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7046 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7047
7048 /* a new SFP+ module arrival, called from GPI SDP2 context */
7049 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 7050 ixgbe_sfp_config_module_task);
e8e26350 7051
8ca783ab 7052 ii->get_invariants(hw);
9a799d71
AK		 7053
7054 /* setup the private structure */
7055 err = ixgbe_sw_init(adapter);
7056 if (err)
7057 goto err_sw_init;
7058
e86bff0e
DS		 7059 /* Make it possible the adapter to be woken up via WOL */
7060 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7061 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7062
bf069c97
DS		 7063 /*
7064 * If there is a fan on this device and it has failed log the
7065 * failure.
7066 */
7067 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7068 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7069 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7070 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7071 }
7072
c44ade9e 7073 /* reset_hw fills in the perm_addr as well */
119fc60a 7074 hw->phy.reset_if_overtemp = true;
c44ade9e 7075 err = hw->mac.ops.reset_hw(hw);
119fc60a 7076 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7077 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7078 hw->mac.type == ixgbe_mac_82598EB) {
7079 /*
7080 * Start a kernel thread to watch for a module to arrive.
7081 * Only do this for 82598, since 82599 will generate
7082 * interrupts on module arrival.
7083 */
7084 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7085 mod_timer(&adapter->sfp_timer,
7086 round_jiffies(jiffies + (2 * HZ)));
7087 err = 0;
7088 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 7089 e_dev_err("failed to initialize because an unsupported SFP+ "
7090 "module type was detected.\n");
7091 e_dev_err("Reload the driver after installing a supported "
7092 "module.\n");
04f165ef
PW		 7093 goto err_sw_init;
7094 } else if (err) {
849c4542 7095 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7096 goto err_sw_init;
7097 }
7098
1cdd1ec8
GR		 7099 ixgbe_probe_vf(adapter, ii);
7100
396e799c 7101 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7102 NETIF_F_IP_CSUM |
7103 NETIF_F_HW_VLAN_TX |
7104 NETIF_F_HW_VLAN_RX |
7105 NETIF_F_HW_VLAN_FILTER;
9a799d71 7106
e9990a9c 7107 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7108 netdev->features |= NETIF_F_TSO;
9a799d71 7109 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7110 netdev->features |= NETIF_F_GRO;
ad31c402 7111
45a5ead0
JB		 7112 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7113 netdev->features |= NETIF_F_SCTP_CSUM;
7114
ad31c402
JK		 7115 netdev->vlan_features |= NETIF_F_TSO;
7116 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7117 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7118 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7119 netdev->vlan_features |= NETIF_F_SG;
7120
1cdd1ec8
GR		 7121 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7122 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7123 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 7124 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7125 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7126
7a6b6f51 7127#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7128 netdev->dcbnl_ops = &dcbnl_ops;
7129#endif
7130
eacd73f7 7131#ifdef IXGBE_FCOE
0d551589 7132 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7133 if (hw->mac.ops.get_device_caps) {
7134 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7135 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7136 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7137 }
7138 }
5e09d7f6
YZ		 7139 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7140 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7141 netdev->vlan_features |= NETIF_F_FSO;
7142 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7143 }
eacd73f7 7144#endif /* IXGBE_FCOE */
7b872a55 7145 if (pci_using_dac) {
9a799d71 7146 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7147 netdev->vlan_features |= NETIF_F_HIGHDMA;
7148 }
9a799d71 7149
0c19d6af 7150 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7151 netdev->features |= NETIF_F_LRO;
7152
9a799d71 7153 /* make sure the EEPROM is good */
c44ade9e 7154 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7155 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7156 err = -EIO;
7157 goto err_eeprom;
7158 }
7159
7160 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7161 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7162
c44ade9e 7163 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7164 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7165 err = -EIO;
7166 goto err_eeprom;
7167 }
7168
61fac744 7169 /* power down the optics */
e3de4b7b 7170 if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
61fac744
PW		 7171 hw->mac.ops.disable_tx_laser(hw);
7172
9a799d71 7173 init_timer(&adapter->watchdog_timer);
c061b18d 7174 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7175 adapter->watchdog_timer.data = (unsigned long)adapter;
7176
7177 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7178 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7179
021230d4
AV		 7180 err = ixgbe_init_interrupt_scheme(adapter);
7181 if (err)
7182 goto err_sw_init;
9a799d71 7183
e8e26350 7184 switch (pdev->device) {
50d6c681
AD		 7185 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7186 /* All except this subdevice support WOL */
7187 if (pdev->subsystem_device ==
7188 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
7189 adapter->wol = 0;
7190 break;
7191 }
e8e26350 7192 case IXGBE_DEV_ID_82599_KX4:
495dce12 7193 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7194 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7195 break;
7196 default:
7197 adapter->wol = 0;
7198 break;
7199 }
e8e26350
PW		 7200 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7201
04f165ef
PW		 7202 /* pick up the PCI bus settings for reporting later */
7203 hw->mac.ops.get_bus_info(hw);
7204
9a799d71 7205 /* print bus type/speed/width info */
849c4542 7206 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 7207 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7208 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7209 "Unknown"),
7210 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7211 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7212 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7213 "Unknown"),
7214 netdev->dev_addr);
c44ade9e 7215 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 7216 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 7217 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7218 "PBA No: %06x-%03x\n",
7219 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7220 (part_num >> 8), (part_num & 0xff));
e8e26350 7221 else
849c4542
ET		 7222 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7223 hw->mac.type, hw->phy.type,
7224 (part_num >> 8), (part_num & 0xff));
9a799d71 7225
e8e26350 7226 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7227 e_dev_warn("PCI-Express bandwidth available for this card is "
7228 "not sufficient for optimal performance.\n");
7229 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7230 "is required.\n");
0c254d86
AK		 7231 }
7232
34b0368c
PWJ		 7233 /* save off EEPROM version number */
7234 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7235
9a799d71 7236 /* reset the hardware with the new settings */
794caeb2 7237 err = hw->mac.ops.start_hw(hw);
c44ade9e 7238
794caeb2
PWJ		 7239 if (err == IXGBE_ERR_EEPROM_VERSION) {
7240 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7241 e_dev_warn("This device is a pre-production adapter/LOM. "
7242 "Please be aware there may be issues associated "
7243 "with your hardware. If you are experiencing "
7244 "problems please contact your Intel or hardware "
7245 "representative who provided you with this "
7246 "hardware.\n");
794caeb2 7247 }
9a799d71
AK		 7248 strcpy(netdev->name, "eth%d");
7249 err = register_netdev(netdev);
7250 if (err)
7251 goto err_register;
7252
54386467
JB		 7253 /* carrier off reporting is important to ethtool even BEFORE open */
7254 netif_carrier_off(netdev);
7255
c4cf55e5
PWJ		 7256 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7257 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7258 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7259
119fc60a 7260 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7261 INIT_WORK(&adapter->check_overtemp_task,
7262 ixgbe_check_overtemp_task);
5dd2d332 7263#ifdef CONFIG_IXGBE_DCA
652f093f 7264 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7265 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7266 ixgbe_setup_dca(adapter);
7267 }
7268#endif
1cdd1ec8 7269 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7270 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7271 for (i = 0; i < adapter->num_vfs; i++)
7272 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7273 }
7274
0365e6e4
PW		 7275 /* add san mac addr to netdev */
7276 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7277
849c4542 7278 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7279 cards_found++;
7280 return 0;
7281
7282err_register:
5eba3699 7283 ixgbe_release_hw_control(adapter);
7a921c93 7284 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7285err_sw_init:
7286err_eeprom:
1cdd1ec8
GR		 7287 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7288 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7289 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7290 del_timer_sync(&adapter->sfp_timer);
7291 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7292 cancel_work_sync(&adapter->multispeed_fiber_task);
7293 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7294 iounmap(hw->hw_addr);
7295err_ioremap:
7296 free_netdev(netdev);
7297err_alloc_etherdev:
e8e9f696
JP		 7298 pci_release_selected_regions(pdev,
7299 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7300err_pci_reg:
7301err_dma:
7302 pci_disable_device(pdev);
7303 return err;
7304}
7305
7306/**
7307 * ixgbe_remove - Device Removal Routine
7308 * @pdev: PCI device information struct
7309 *
7310 * ixgbe_remove is called by the PCI subsystem to alert the driver
7311 * that it should release a PCI device. The could be caused by a
7312 * Hot-Plug event, or because the driver is going to be removed from
7313 * memory.
7314 **/
7315static void __devexit ixgbe_remove(struct pci_dev *pdev)
7316{
c60fbb00
AD		 7317 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7318 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7319
7320 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7321 /* clear the module not found bit to make sure the worker won't
7322 * reschedule
7323 */
7324 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7325 del_timer_sync(&adapter->watchdog_timer);
7326
c4900be0
DS		 7327 del_timer_sync(&adapter->sfp_timer);
7328 cancel_work_sync(&adapter->watchdog_task);
7329 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7330 cancel_work_sync(&adapter->multispeed_fiber_task);
7331 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7332 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7333 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7334 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7335 flush_scheduled_work();
7336
5dd2d332 7337#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7338 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7339 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7340 dca_remove_requester(&pdev->dev);
7341 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7342 }
7343
7344#endif
332d4a7d
YZ		 7345#ifdef IXGBE_FCOE
7346 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7347 ixgbe_cleanup_fcoe(adapter);
7348
7349#endif /* IXGBE_FCOE */
0365e6e4
PW		 7350
7351 /* remove the added san mac */
7352 ixgbe_del_sanmac_netdev(netdev);
7353
c4900be0
DS		 7354 if (netdev->reg_state == NETREG_REGISTERED)
7355 unregister_netdev(netdev);
9a799d71 7356
1cdd1ec8
GR		 7357 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7358 ixgbe_disable_sriov(adapter);
7359
7a921c93 7360 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7361
021230d4 7362 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7363
7364 iounmap(adapter->hw.hw_addr);
9ce77666 7365 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7366 IORESOURCE_MEM));
9a799d71 7367
849c4542 7368 e_dev_info("complete\n");
021230d4 7369
9a799d71
AK		 7370 free_netdev(netdev);
7371
19d5afd4 7372 pci_disable_pcie_error_reporting(pdev);
6fabd715 7373
9a799d71
AK		 7374 pci_disable_device(pdev);
7375}
7376
7377/**
7378 * ixgbe_io_error_detected - called when PCI error is detected
7379 * @pdev: Pointer to PCI device
7380 * @state: The current pci connection state
7381 *
7382 * This function is called after a PCI bus error affecting
7383 * this device has been detected.
7384 */
7385static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7386 pci_channel_state_t state)
9a799d71 7387{
c60fbb00
AD		 7388 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7389 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7390
7391 netif_device_detach(netdev);
7392
3044b8d1
BL		 7393 if (state == pci_channel_io_perm_failure)
7394 return PCI_ERS_RESULT_DISCONNECT;
7395
9a799d71
AK		 7396 if (netif_running(netdev))
7397 ixgbe_down(adapter);
7398 pci_disable_device(pdev);
7399
b4617240 7400 /* Request a slot reset. */
9a799d71
AK		 7401 return PCI_ERS_RESULT_NEED_RESET;
7402}
7403
7404/**
7405 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7406 * @pdev: Pointer to PCI device
7407 *
7408 * Restart the card from scratch, as if from a cold-boot.
7409 */
7410static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7411{
c60fbb00 7412 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7413 pci_ers_result_t result;
7414 int err;
9a799d71 7415
9ce77666 7416 if (pci_enable_device_mem(pdev)) {
396e799c 7417 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7418 result = PCI_ERS_RESULT_DISCONNECT;
7419 } else {
7420 pci_set_master(pdev);
7421 pci_restore_state(pdev);
c0e1f68b 7422 pci_save_state(pdev);
9a799d71 7423
dd4d8ca6 7424 pci_wake_from_d3(pdev, false);
9a799d71 7425
6fabd715 7426 ixgbe_reset(adapter);
88512539 7427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7428 result = PCI_ERS_RESULT_RECOVERED;
7429 }
7430
7431 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7432 if (err) {
849c4542
ET		 7433 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7434 "failed 0x%0x\n", err);
6fabd715
PWJ		 7435 /* non-fatal, continue */
7436 }
9a799d71 7437
6fabd715 7438 return result;
9a799d71
AK		 7439}
7440
7441/**
7442 * ixgbe_io_resume - called when traffic can start flowing again.
7443 * @pdev: Pointer to PCI device
7444 *
7445 * This callback is called when the error recovery driver tells us that
7446 * its OK to resume normal operation.
7447 */
7448static void ixgbe_io_resume(struct pci_dev *pdev)
7449{
c60fbb00
AD		 7450 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7451 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7452
7453 if (netif_running(netdev)) {
7454 if (ixgbe_up(adapter)) {
396e799c 7455 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7456 return;
7457 }
7458 }
7459
7460 netif_device_attach(netdev);
9a799d71
AK		 7461}
7462
7463static struct pci_error_handlers ixgbe_err_handler = {
7464 .error_detected = ixgbe_io_error_detected,
7465 .slot_reset = ixgbe_io_slot_reset,
7466 .resume = ixgbe_io_resume,
7467};
7468
7469static struct pci_driver ixgbe_driver = {
7470 .name = ixgbe_driver_name,
7471 .id_table = ixgbe_pci_tbl,
7472 .probe = ixgbe_probe,
7473 .remove = __devexit_p(ixgbe_remove),
7474#ifdef CONFIG_PM
7475 .suspend = ixgbe_suspend,
7476 .resume = ixgbe_resume,
7477#endif
7478 .shutdown = ixgbe_shutdown,
7479 .err_handler = &ixgbe_err_handler
7480};
7481
7482/**
7483 * ixgbe_init_module - Driver Registration Routine
7484 *
7485 * ixgbe_init_module is the first routine called when the driver is
7486 * loaded. All it does is register with the PCI subsystem.
7487 **/
7488static int __init ixgbe_init_module(void)
7489{
7490 int ret;
c7689578 7491 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7492 pr_info("%s\n", ixgbe_copyright);
9a799d71 7493
5dd2d332 7494#ifdef CONFIG_IXGBE_DCA
bd0362dd 7495 dca_register_notify(&dca_notifier);
bd0362dd 7496#endif
5dd2d332 7497
9a799d71
AK		 7498 ret = pci_register_driver(&ixgbe_driver);
7499 return ret;
7500}
b4617240 7501
9a799d71
AK		 7502module_init(ixgbe_init_module);
7503
7504/**
7505 * ixgbe_exit_module - Driver Exit Cleanup Routine
7506 *
7507 * ixgbe_exit_module is called just before the driver is removed
7508 * from memory.
7509 **/
7510static void __exit ixgbe_exit_module(void)
7511{
5dd2d332 7512#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7513 dca_unregister_notify(&dca_notifier);
7514#endif
9a799d71 7515 pci_unregister_driver(&ixgbe_driver);
1a51502b 7516 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7517}
bd0362dd 7518
5dd2d332 7519#ifdef CONFIG_IXGBE_DCA
bd0362dd 7520static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7521 void *p)
bd0362dd
JC		 7522{
7523 int ret_val;
7524
7525 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7526 __ixgbe_notify_dca);
bd0362dd
JC		 7527
7528 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7529}
b453368d 7530
5dd2d332 7531#endif /* CONFIG_IXGBE_DCA */
849c4542 7532
b453368d 7533/**
849c4542 7534 * ixgbe_get_hw_dev return device
b453368d
AD		 7535 * used by hardware layer to print debugging information
7536 **/
849c4542 7537struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7538{
7539 struct ixgbe_adapter *adapter = hw->back;
849c4542 7540 return adapter->netdev;
b453368d 7541}
bd0362dd 7542
9a799d71
AK		 7543module_exit(ixgbe_exit_module);
7544
7545/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree