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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 | 38 | #include <linux/ipv6.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
9a799d71 AK |
40 | #include <net/checksum.h> |
41 | #include <net/ip6_checksum.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/if_vlan.h> | |
eacd73f7 | 44 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
45 | |
46 | #include "ixgbe.h" | |
47 | #include "ixgbe_common.h" | |
ee5f784a | 48 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 49 | #include "ixgbe_sriov.h" |
9a799d71 AK |
50 | |
51 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 52 | static const char ixgbe_driver_string[] = |
e8e9f696 | 53 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 54 | |
99faf68e | 55 | #define DRV_VERSION "2.0.84-k2" |
9c8eb720 | 56 | const char ixgbe_driver_version[] = DRV_VERSION; |
8c47eaa7 | 57 | static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; |
9a799d71 AK |
58 | |
59 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 60 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 61 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
62 | }; |
63 | ||
64 | /* ixgbe_pci_tbl - PCI Device ID Table | |
65 | * | |
66 | * Wildcard entries (PCI_ANY_ID) should come last | |
67 | * Last entry must be all 0s | |
68 | * | |
69 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
70 | * Class, Class Mask, private data (not used) } | |
71 | */ | |
a3aa1884 | 72 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
74 | board_82598 }, | |
9a799d71 | 75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 76 | board_82598 }, |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 78 | board_82598 }, |
0befdb3e JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
80 | board_82598 }, | |
3845bec0 PWJ |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
82 | board_82598 }, | |
9a799d71 | 83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 84 | board_82598 }, |
8d792cd9 JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
88 | board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
90 | board_82598 }, | |
b95f5fcb JB |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
92 | board_82598 }, | |
c4900be0 DS |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
94 | board_82598 }, | |
2f21bdd3 DS |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
96 | board_82598 }, | |
e8e26350 PW |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
98 | board_82599 }, | |
1fcf03e6 PWJ |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
100 | board_82599 }, | |
74757d49 DS |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
102 | board_82599 }, | |
e8e26350 PW |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
104 | board_82599 }, | |
38ad1c8e DS |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
106 | board_82599 }, | |
dbfec662 DS |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
108 | board_82599 }, | |
8911184f PWJ |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
110 | board_82599 }, | |
119fc60a MC |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), |
112 | board_82599 }, | |
312eb931 DS |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
114 | board_82599 }, | |
9a799d71 AK |
115 | |
116 | /* required last entry */ | |
117 | {0, } | |
118 | }; | |
119 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
120 | ||
5dd2d332 | 121 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 122 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 123 | void *p); |
bd0362dd JC |
124 | static struct notifier_block dca_notifier = { |
125 | .notifier_call = ixgbe_notify_dca, | |
126 | .next = NULL, | |
127 | .priority = 0 | |
128 | }; | |
129 | #endif | |
130 | ||
1cdd1ec8 GR |
131 | #ifdef CONFIG_PCI_IOV |
132 | static unsigned int max_vfs; | |
133 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
134 | MODULE_PARM_DESC(max_vfs, |
135 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
136 | #endif /* CONFIG_PCI_IOV */ |
137 | ||
9a799d71 AK |
138 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
139 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
140 | MODULE_LICENSE("GPL"); | |
141 | MODULE_VERSION(DRV_VERSION); | |
142 | ||
143 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
144 | ||
1cdd1ec8 GR |
145 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
146 | { | |
147 | struct ixgbe_hw *hw = &adapter->hw; | |
148 | u32 gcr; | |
149 | u32 gpie; | |
150 | u32 vmdctl; | |
151 | ||
152 | #ifdef CONFIG_PCI_IOV | |
153 | /* disable iov and allow time for transactions to clear */ | |
154 | pci_disable_sriov(adapter->pdev); | |
155 | #endif | |
156 | ||
157 | /* turn off device IOV mode */ | |
158 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
159 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
160 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
161 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
162 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
163 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
164 | ||
165 | /* set default pool back to 0 */ | |
166 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
167 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
168 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
169 | ||
170 | /* take a breather then clean up driver data */ | |
171 | msleep(100); | |
e8e9f696 JP |
172 | |
173 | kfree(adapter->vfinfo); | |
1cdd1ec8 GR |
174 | adapter->vfinfo = NULL; |
175 | ||
176 | adapter->num_vfs = 0; | |
177 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
178 | } | |
179 | ||
dcd79aeb TI |
180 | struct ixgbe_reg_info { |
181 | u32 ofs; | |
182 | char *name; | |
183 | }; | |
184 | ||
185 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
186 | ||
187 | /* General Registers */ | |
188 | {IXGBE_CTRL, "CTRL"}, | |
189 | {IXGBE_STATUS, "STATUS"}, | |
190 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
191 | ||
192 | /* Interrupt Registers */ | |
193 | {IXGBE_EICR, "EICR"}, | |
194 | ||
195 | /* RX Registers */ | |
196 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
197 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
198 | {IXGBE_RDLEN(0), "RDLEN"}, | |
199 | {IXGBE_RDH(0), "RDH"}, | |
200 | {IXGBE_RDT(0), "RDT"}, | |
201 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
202 | {IXGBE_RDBAL(0), "RDBAL"}, | |
203 | {IXGBE_RDBAH(0), "RDBAH"}, | |
204 | ||
205 | /* TX Registers */ | |
206 | {IXGBE_TDBAL(0), "TDBAL"}, | |
207 | {IXGBE_TDBAH(0), "TDBAH"}, | |
208 | {IXGBE_TDLEN(0), "TDLEN"}, | |
209 | {IXGBE_TDH(0), "TDH"}, | |
210 | {IXGBE_TDT(0), "TDT"}, | |
211 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
212 | ||
213 | /* List Terminator */ | |
214 | {} | |
215 | }; | |
216 | ||
217 | ||
218 | /* | |
219 | * ixgbe_regdump - register printout routine | |
220 | */ | |
221 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
222 | { | |
223 | int i = 0, j = 0; | |
224 | char rname[16]; | |
225 | u32 regs[64]; | |
226 | ||
227 | switch (reginfo->ofs) { | |
228 | case IXGBE_SRRCTL(0): | |
229 | for (i = 0; i < 64; i++) | |
230 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
231 | break; | |
232 | case IXGBE_DCA_RXCTRL(0): | |
233 | for (i = 0; i < 64; i++) | |
234 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
235 | break; | |
236 | case IXGBE_RDLEN(0): | |
237 | for (i = 0; i < 64; i++) | |
238 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
239 | break; | |
240 | case IXGBE_RDH(0): | |
241 | for (i = 0; i < 64; i++) | |
242 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
243 | break; | |
244 | case IXGBE_RDT(0): | |
245 | for (i = 0; i < 64; i++) | |
246 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
247 | break; | |
248 | case IXGBE_RXDCTL(0): | |
249 | for (i = 0; i < 64; i++) | |
250 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
251 | break; | |
252 | case IXGBE_RDBAL(0): | |
253 | for (i = 0; i < 64; i++) | |
254 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
255 | break; | |
256 | case IXGBE_RDBAH(0): | |
257 | for (i = 0; i < 64; i++) | |
258 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
259 | break; | |
260 | case IXGBE_TDBAL(0): | |
261 | for (i = 0; i < 64; i++) | |
262 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
263 | break; | |
264 | case IXGBE_TDBAH(0): | |
265 | for (i = 0; i < 64; i++) | |
266 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
267 | break; | |
268 | case IXGBE_TDLEN(0): | |
269 | for (i = 0; i < 64; i++) | |
270 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
271 | break; | |
272 | case IXGBE_TDH(0): | |
273 | for (i = 0; i < 64; i++) | |
274 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
275 | break; | |
276 | case IXGBE_TDT(0): | |
277 | for (i = 0; i < 64; i++) | |
278 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
279 | break; | |
280 | case IXGBE_TXDCTL(0): | |
281 | for (i = 0; i < 64; i++) | |
282 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
283 | break; | |
284 | default: | |
c7689578 | 285 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
286 | IXGBE_READ_REG(hw, reginfo->ofs)); |
287 | return; | |
288 | } | |
289 | ||
290 | for (i = 0; i < 8; i++) { | |
291 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 292 | pr_err("%-15s", rname); |
dcd79aeb | 293 | for (j = 0; j < 8; j++) |
c7689578 JP |
294 | pr_cont(" %08x", regs[i*8+j]); |
295 | pr_cont("\n"); | |
dcd79aeb TI |
296 | } |
297 | ||
298 | } | |
299 | ||
300 | /* | |
301 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
302 | */ | |
303 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
304 | { | |
305 | struct net_device *netdev = adapter->netdev; | |
306 | struct ixgbe_hw *hw = &adapter->hw; | |
307 | struct ixgbe_reg_info *reginfo; | |
308 | int n = 0; | |
309 | struct ixgbe_ring *tx_ring; | |
310 | struct ixgbe_tx_buffer *tx_buffer_info; | |
311 | union ixgbe_adv_tx_desc *tx_desc; | |
312 | struct my_u0 { u64 a; u64 b; } *u0; | |
313 | struct ixgbe_ring *rx_ring; | |
314 | union ixgbe_adv_rx_desc *rx_desc; | |
315 | struct ixgbe_rx_buffer *rx_buffer_info; | |
316 | u32 staterr; | |
317 | int i = 0; | |
318 | ||
319 | if (!netif_msg_hw(adapter)) | |
320 | return; | |
321 | ||
322 | /* Print netdevice Info */ | |
323 | if (netdev) { | |
324 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 325 | pr_info("Device Name state " |
dcd79aeb | 326 | "trans_start last_rx\n"); |
c7689578 JP |
327 | pr_info("%-15s %016lX %016lX %016lX\n", |
328 | netdev->name, | |
329 | netdev->state, | |
330 | netdev->trans_start, | |
331 | netdev->last_rx); | |
dcd79aeb TI |
332 | } |
333 | ||
334 | /* Print Registers */ | |
335 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 336 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
337 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
338 | reginfo->name; reginfo++) { | |
339 | ixgbe_regdump(hw, reginfo); | |
340 | } | |
341 | ||
342 | /* Print TX Ring Summary */ | |
343 | if (!netdev || !netif_running(netdev)) | |
344 | goto exit; | |
345 | ||
346 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 347 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
348 | for (n = 0; n < adapter->num_tx_queues; n++) { |
349 | tx_ring = adapter->tx_ring[n]; | |
350 | tx_buffer_info = | |
351 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
c7689578 | 352 | pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", |
dcd79aeb TI |
353 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
354 | (u64)tx_buffer_info->dma, | |
355 | tx_buffer_info->length, | |
356 | tx_buffer_info->next_to_watch, | |
357 | (u64)tx_buffer_info->time_stamp); | |
358 | } | |
359 | ||
360 | /* Print TX Rings */ | |
361 | if (!netif_msg_tx_done(adapter)) | |
362 | goto rx_ring_summary; | |
363 | ||
364 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
365 | ||
366 | /* Transmit Descriptor Formats | |
367 | * | |
368 | * Advanced Transmit Descriptor | |
369 | * +--------------------------------------------------------------+ | |
370 | * 0 | Buffer Address [63:0] | | |
371 | * +--------------------------------------------------------------+ | |
372 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
373 | * +--------------------------------------------------------------+ | |
374 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
375 | */ | |
376 | ||
377 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
378 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
379 | pr_info("------------------------------------\n"); |
380 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
381 | pr_info("------------------------------------\n"); | |
382 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
383 | "[PlPOIdStDDt Ln] [bi->dma ] " |
384 | "leng ntw timestamp bi->skb\n"); | |
385 | ||
386 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
31f05a2d | 387 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
dcd79aeb TI |
388 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
389 | u0 = (struct my_u0 *)tx_desc; | |
c7689578 | 390 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
dcd79aeb TI |
391 | " %04X %3X %016llX %p", i, |
392 | le64_to_cpu(u0->a), | |
393 | le64_to_cpu(u0->b), | |
394 | (u64)tx_buffer_info->dma, | |
395 | tx_buffer_info->length, | |
396 | tx_buffer_info->next_to_watch, | |
397 | (u64)tx_buffer_info->time_stamp, | |
398 | tx_buffer_info->skb); | |
399 | if (i == tx_ring->next_to_use && | |
400 | i == tx_ring->next_to_clean) | |
c7689578 | 401 | pr_cont(" NTC/U\n"); |
dcd79aeb | 402 | else if (i == tx_ring->next_to_use) |
c7689578 | 403 | pr_cont(" NTU\n"); |
dcd79aeb | 404 | else if (i == tx_ring->next_to_clean) |
c7689578 | 405 | pr_cont(" NTC\n"); |
dcd79aeb | 406 | else |
c7689578 | 407 | pr_cont("\n"); |
dcd79aeb TI |
408 | |
409 | if (netif_msg_pktdata(adapter) && | |
410 | tx_buffer_info->dma != 0) | |
411 | print_hex_dump(KERN_INFO, "", | |
412 | DUMP_PREFIX_ADDRESS, 16, 1, | |
413 | phys_to_virt(tx_buffer_info->dma), | |
414 | tx_buffer_info->length, true); | |
415 | } | |
416 | } | |
417 | ||
418 | /* Print RX Rings Summary */ | |
419 | rx_ring_summary: | |
420 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 421 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
422 | for (n = 0; n < adapter->num_rx_queues; n++) { |
423 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
424 | pr_info("%5d %5X %5X\n", |
425 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
426 | } |
427 | ||
428 | /* Print RX Rings */ | |
429 | if (!netif_msg_rx_status(adapter)) | |
430 | goto exit; | |
431 | ||
432 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
433 | ||
434 | /* Advanced Receive Descriptor (Read) Format | |
435 | * 63 1 0 | |
436 | * +-----------------------------------------------------+ | |
437 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
438 | * +----------------------------------------------+------+ | |
439 | * 8 | Header Buffer Address [63:1] | DD | | |
440 | * +-----------------------------------------------------+ | |
441 | * | |
442 | * | |
443 | * Advanced Receive Descriptor (Write-Back) Format | |
444 | * | |
445 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
446 | * +------------------------------------------------------+ | |
447 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
448 | * | Checksum Ident | | | | Type | Type | | |
449 | * +------------------------------------------------------+ | |
450 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
451 | * +------------------------------------------------------+ | |
452 | * 63 48 47 32 31 20 19 0 | |
453 | */ | |
454 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
455 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
456 | pr_info("------------------------------------\n"); |
457 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
458 | pr_info("------------------------------------\n"); | |
459 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
460 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
461 | "<-- Adv Rx Read format\n"); | |
c7689578 | 462 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
463 | "[vl er S cks ln] ---------------- [bi->skb] " |
464 | "<-- Adv Rx Write-Back format\n"); | |
465 | ||
466 | for (i = 0; i < rx_ring->count; i++) { | |
467 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
31f05a2d | 468 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
dcd79aeb TI |
469 | u0 = (struct my_u0 *)rx_desc; |
470 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
471 | if (staterr & IXGBE_RXD_STAT_DD) { | |
472 | /* Descriptor Done */ | |
c7689578 | 473 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
474 | "%016llX ---------------- %p", i, |
475 | le64_to_cpu(u0->a), | |
476 | le64_to_cpu(u0->b), | |
477 | rx_buffer_info->skb); | |
478 | } else { | |
c7689578 | 479 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
480 | "%016llX %016llX %p", i, |
481 | le64_to_cpu(u0->a), | |
482 | le64_to_cpu(u0->b), | |
483 | (u64)rx_buffer_info->dma, | |
484 | rx_buffer_info->skb); | |
485 | ||
486 | if (netif_msg_pktdata(adapter)) { | |
487 | print_hex_dump(KERN_INFO, "", | |
488 | DUMP_PREFIX_ADDRESS, 16, 1, | |
489 | phys_to_virt(rx_buffer_info->dma), | |
490 | rx_ring->rx_buf_len, true); | |
491 | ||
492 | if (rx_ring->rx_buf_len | |
493 | < IXGBE_RXBUFFER_2048) | |
494 | print_hex_dump(KERN_INFO, "", | |
495 | DUMP_PREFIX_ADDRESS, 16, 1, | |
496 | phys_to_virt( | |
497 | rx_buffer_info->page_dma + | |
498 | rx_buffer_info->page_offset | |
499 | ), | |
500 | PAGE_SIZE/2, true); | |
501 | } | |
502 | } | |
503 | ||
504 | if (i == rx_ring->next_to_use) | |
c7689578 | 505 | pr_cont(" NTU\n"); |
dcd79aeb | 506 | else if (i == rx_ring->next_to_clean) |
c7689578 | 507 | pr_cont(" NTC\n"); |
dcd79aeb | 508 | else |
c7689578 | 509 | pr_cont("\n"); |
dcd79aeb TI |
510 | |
511 | } | |
512 | } | |
513 | ||
514 | exit: | |
515 | return; | |
516 | } | |
517 | ||
5eba3699 AV |
518 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
519 | { | |
520 | u32 ctrl_ext; | |
521 | ||
522 | /* Let firmware take over control of h/w */ | |
523 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
524 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 525 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
526 | } |
527 | ||
528 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
529 | { | |
530 | u32 ctrl_ext; | |
531 | ||
532 | /* Let firmware know the driver has taken over */ | |
533 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
534 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 535 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 536 | } |
9a799d71 | 537 | |
e8e26350 PW |
538 | /* |
539 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
540 | * @adapter: pointer to adapter struct | |
541 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
542 | * @queue: queue to map the corresponding interrupt to | |
543 | * @msix_vector: the vector to map to the corresponding queue | |
544 | * | |
545 | */ | |
546 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 547 | u8 queue, u8 msix_vector) |
9a799d71 AK |
548 | { |
549 | u32 ivar, index; | |
e8e26350 PW |
550 | struct ixgbe_hw *hw = &adapter->hw; |
551 | switch (hw->mac.type) { | |
552 | case ixgbe_mac_82598EB: | |
553 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
554 | if (direction == -1) | |
555 | direction = 0; | |
556 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
557 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
558 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
559 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
560 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
561 | break; | |
562 | case ixgbe_mac_82599EB: | |
563 | if (direction == -1) { | |
564 | /* other causes */ | |
565 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
566 | index = ((queue & 1) * 8); | |
567 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
568 | ivar &= ~(0xFF << index); | |
569 | ivar |= (msix_vector << index); | |
570 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
571 | break; | |
572 | } else { | |
573 | /* tx or rx causes */ | |
574 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
575 | index = ((16 * (queue & 1)) + (8 * direction)); | |
576 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
577 | ivar &= ~(0xFF << index); | |
578 | ivar |= (msix_vector << index); | |
579 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
580 | break; | |
581 | } | |
582 | default: | |
583 | break; | |
584 | } | |
9a799d71 AK |
585 | } |
586 | ||
fe49f04a | 587 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 588 | u64 qmask) |
fe49f04a AD |
589 | { |
590 | u32 mask; | |
591 | ||
592 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
593 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
594 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
595 | } else { | |
596 | mask = (qmask & 0xFFFFFFFF); | |
597 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
598 | mask = (qmask >> 32); | |
599 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
600 | } | |
601 | } | |
602 | ||
84418e3b | 603 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
e8e9f696 JP |
604 | struct ixgbe_tx_buffer |
605 | *tx_buffer_info) | |
9a799d71 | 606 | { |
e5a43549 AD |
607 | if (tx_buffer_info->dma) { |
608 | if (tx_buffer_info->mapped_as_page) | |
1b507730 | 609 | dma_unmap_page(&adapter->pdev->dev, |
e5a43549 AD |
610 | tx_buffer_info->dma, |
611 | tx_buffer_info->length, | |
1b507730 | 612 | DMA_TO_DEVICE); |
e5a43549 | 613 | else |
1b507730 | 614 | dma_unmap_single(&adapter->pdev->dev, |
e5a43549 AD |
615 | tx_buffer_info->dma, |
616 | tx_buffer_info->length, | |
1b507730 | 617 | DMA_TO_DEVICE); |
e5a43549 AD |
618 | tx_buffer_info->dma = 0; |
619 | } | |
9a799d71 AK |
620 | if (tx_buffer_info->skb) { |
621 | dev_kfree_skb_any(tx_buffer_info->skb); | |
622 | tx_buffer_info->skb = NULL; | |
623 | } | |
44df32c5 | 624 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
625 | /* tx_buffer_info must be completely set up in the transmit path */ |
626 | } | |
627 | ||
26f23d82 | 628 | /** |
7483d9dd | 629 | * ixgbe_tx_xon_state - check the tx ring xon state |
26f23d82 YZ |
630 | * @adapter: the ixgbe adapter |
631 | * @tx_ring: the corresponding tx_ring | |
632 | * | |
633 | * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the | |
634 | * corresponding TC of this tx_ring when checking TFCS. | |
635 | * | |
7483d9dd | 636 | * Returns : true if in xon state (currently not paused) |
26f23d82 | 637 | */ |
7483d9dd | 638 | static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter, |
e8e9f696 | 639 | struct ixgbe_ring *tx_ring) |
26f23d82 | 640 | { |
26f23d82 YZ |
641 | u32 txoff = IXGBE_TFCS_TXOFF; |
642 | ||
643 | #ifdef CONFIG_IXGBE_DCB | |
ca739481 | 644 | if (adapter->dcb_cfg.pfc_mode_enable) { |
30b76832 | 645 | int tc; |
26f23d82 YZ |
646 | int reg_idx = tx_ring->reg_idx; |
647 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
648 | ||
6837e895 PW |
649 | switch (adapter->hw.mac.type) { |
650 | case ixgbe_mac_82598EB: | |
26f23d82 YZ |
651 | tc = reg_idx >> 2; |
652 | txoff = IXGBE_TFCS_TXOFF0; | |
6837e895 PW |
653 | break; |
654 | case ixgbe_mac_82599EB: | |
26f23d82 YZ |
655 | tc = 0; |
656 | txoff = IXGBE_TFCS_TXOFF; | |
657 | if (dcb_i == 8) { | |
658 | /* TC0, TC1 */ | |
659 | tc = reg_idx >> 5; | |
660 | if (tc == 2) /* TC2, TC3 */ | |
661 | tc += (reg_idx - 64) >> 4; | |
662 | else if (tc == 3) /* TC4, TC5, TC6, TC7 */ | |
663 | tc += 1 + ((reg_idx - 96) >> 3); | |
664 | } else if (dcb_i == 4) { | |
665 | /* TC0, TC1 */ | |
666 | tc = reg_idx >> 6; | |
667 | if (tc == 1) { | |
668 | tc += (reg_idx - 64) >> 5; | |
669 | if (tc == 2) /* TC2, TC3 */ | |
670 | tc += (reg_idx - 96) >> 4; | |
671 | } | |
672 | } | |
6837e895 PW |
673 | break; |
674 | default: | |
675 | tc = 0; | |
26f23d82 YZ |
676 | } |
677 | txoff <<= tc; | |
678 | } | |
679 | #endif | |
680 | return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff; | |
681 | } | |
682 | ||
9a799d71 | 683 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, |
e8e9f696 JP |
684 | struct ixgbe_ring *tx_ring, |
685 | unsigned int eop) | |
9a799d71 | 686 | { |
e01c31a5 | 687 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 688 | |
9a799d71 | 689 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 690 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 691 | adapter->detect_tx_hung = false; |
44df32c5 | 692 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 | 693 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
7483d9dd | 694 | ixgbe_tx_xon_state(adapter, tx_ring)) { |
9a799d71 | 695 | /* detected Tx unit hang */ |
e01c31a5 | 696 | union ixgbe_adv_tx_desc *tx_desc; |
31f05a2d | 697 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
396e799c | 698 | e_err(drv, "Detected Tx Unit Hang\n" |
849c4542 ET |
699 | " Tx Queue <%d>\n" |
700 | " TDH, TDT <%x>, <%x>\n" | |
701 | " next_to_use <%x>\n" | |
702 | " next_to_clean <%x>\n" | |
703 | "tx_buffer_info[next_to_clean]\n" | |
704 | " time_stamp <%lx>\n" | |
705 | " jiffies <%lx>\n", | |
706 | tx_ring->queue_index, | |
84ea2591 AD |
707 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), |
708 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
849c4542 ET |
709 | tx_ring->next_to_use, eop, |
710 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
711 | return true; |
712 | } | |
713 | ||
714 | return false; | |
715 | } | |
716 | ||
b4617240 PW |
717 | #define IXGBE_MAX_TXD_PWR 14 |
718 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
719 | |
720 | /* Tx Descriptors needed, worst case */ | |
721 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
722 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
723 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 724 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 725 | |
e01c31a5 JB |
726 | static void ixgbe_tx_timeout(struct net_device *netdev); |
727 | ||
9a799d71 AK |
728 | /** |
729 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 730 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 731 | * @tx_ring: tx ring to clean |
9a799d71 | 732 | **/ |
fe49f04a | 733 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 734 | struct ixgbe_ring *tx_ring) |
9a799d71 | 735 | { |
fe49f04a | 736 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 737 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
738 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
739 | struct ixgbe_tx_buffer *tx_buffer_info; | |
740 | unsigned int i, eop, count = 0; | |
e01c31a5 | 741 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
742 | |
743 | i = tx_ring->next_to_clean; | |
12207e49 | 744 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 745 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
746 | |
747 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 748 | (count < tx_ring->work_limit)) { |
12207e49 | 749 | bool cleaned = false; |
2d0bb1c1 | 750 | rmb(); /* read buffer_info after eop_desc */ |
12207e49 | 751 | for ( ; !cleaned; count++) { |
31f05a2d | 752 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 | 753 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
8ad494b0 AD |
754 | |
755 | tx_desc->wb.status = 0; | |
12207e49 | 756 | cleaned = (i == eop); |
9a799d71 | 757 | |
8ad494b0 AD |
758 | i++; |
759 | if (i == tx_ring->count) | |
760 | i = 0; | |
e01c31a5 | 761 | |
8ad494b0 AD |
762 | if (cleaned && tx_buffer_info->skb) { |
763 | total_bytes += tx_buffer_info->bytecount; | |
764 | total_packets += tx_buffer_info->gso_segs; | |
e092be60 | 765 | } |
e01c31a5 | 766 | |
9a799d71 | 767 | ixgbe_unmap_and_free_tx_resource(adapter, |
e8e9f696 | 768 | tx_buffer_info); |
e01c31a5 | 769 | } |
12207e49 PWJ |
770 | |
771 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
31f05a2d | 772 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
773 | } |
774 | ||
9a799d71 AK |
775 | tx_ring->next_to_clean = i; |
776 | ||
e092be60 | 777 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 | 778 | if (unlikely(count && netif_carrier_ok(netdev) && |
e8e9f696 | 779 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
780 | /* Make sure that anybody stopping the queue after this |
781 | * sees the new next_to_clean. | |
782 | */ | |
783 | smp_mb(); | |
30eba97a AV |
784 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
785 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
786 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
7ca3bc58 | 787 | ++tx_ring->restart_queue; |
30eba97a | 788 | } |
e092be60 | 789 | } |
9a799d71 | 790 | |
e01c31a5 JB |
791 | if (adapter->detect_tx_hung) { |
792 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
793 | /* schedule immediate reset if we believe we hung */ | |
396e799c ET |
794 | e_info(probe, "tx hang %d detected, resetting " |
795 | "adapter\n", adapter->tx_timeout_count + 1); | |
e01c31a5 JB |
796 | ixgbe_tx_timeout(adapter->netdev); |
797 | } | |
798 | } | |
9a799d71 | 799 | |
e01c31a5 | 800 | /* re-arm the interrupt */ |
fe49f04a AD |
801 | if (count >= tx_ring->work_limit) |
802 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 803 | |
e01c31a5 JB |
804 | tx_ring->total_bytes += total_bytes; |
805 | tx_ring->total_packets += total_packets; | |
de1036b1 | 806 | u64_stats_update_begin(&tx_ring->syncp); |
e01c31a5 | 807 | tx_ring->stats.packets += total_packets; |
12207e49 | 808 | tx_ring->stats.bytes += total_bytes; |
de1036b1 | 809 | u64_stats_update_end(&tx_ring->syncp); |
807540ba | 810 | return count < tx_ring->work_limit; |
9a799d71 AK |
811 | } |
812 | ||
5dd2d332 | 813 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 814 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
e8e9f696 | 815 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
816 | { |
817 | u32 rxctrl; | |
818 | int cpu = get_cpu(); | |
4a0b9ca0 | 819 | int q = rx_ring->reg_idx; |
bd0362dd | 820 | |
3a581073 | 821 | if (rx_ring->cpu != cpu) { |
bd0362dd | 822 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
823 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
824 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
825 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
826 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
827 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
828 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
e8e9f696 | 829 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); |
e8e26350 | 830 | } |
bd0362dd JC |
831 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
832 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
833 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
834 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e9f696 | 835 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 836 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 837 | rx_ring->cpu = cpu; |
bd0362dd JC |
838 | } |
839 | put_cpu(); | |
840 | } | |
841 | ||
842 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
e8e9f696 | 843 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
844 | { |
845 | u32 txctrl; | |
846 | int cpu = get_cpu(); | |
4a0b9ca0 | 847 | int q = tx_ring->reg_idx; |
ee5f784a | 848 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 849 | |
3a581073 | 850 | if (tx_ring->cpu != cpu) { |
e8e26350 | 851 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
ee5f784a | 852 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
853 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; |
854 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
ee5f784a DS |
855 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
856 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
e8e26350 | 857 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 858 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q)); |
e8e26350 PW |
859 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; |
860 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
e8e9f696 | 861 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); |
ee5f784a DS |
862 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
863 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl); | |
e8e26350 | 864 | } |
3a581073 | 865 | tx_ring->cpu = cpu; |
bd0362dd JC |
866 | } |
867 | put_cpu(); | |
868 | } | |
869 | ||
870 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
871 | { | |
872 | int i; | |
873 | ||
874 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
875 | return; | |
876 | ||
e35ec126 AD |
877 | /* always use CB2 mode, difference is masked in the CB driver */ |
878 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
879 | ||
bd0362dd | 880 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
881 | adapter->tx_ring[i]->cpu = -1; |
882 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]); | |
bd0362dd JC |
883 | } |
884 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 PW |
885 | adapter->rx_ring[i]->cpu = -1; |
886 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]); | |
bd0362dd JC |
887 | } |
888 | } | |
889 | ||
890 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
891 | { | |
892 | struct net_device *netdev = dev_get_drvdata(dev); | |
893 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
894 | unsigned long event = *(unsigned long *)data; | |
895 | ||
896 | switch (event) { | |
897 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
898 | /* if we're already enabled, don't do it again */ |
899 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
900 | break; | |
652f093f | 901 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 902 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
903 | ixgbe_setup_dca(adapter); |
904 | break; | |
905 | } | |
906 | /* Fall Through since DCA is disabled. */ | |
907 | case DCA_PROVIDER_REMOVE: | |
908 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
909 | dca_remove_requester(dev); | |
910 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
911 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
912 | } | |
913 | break; | |
914 | } | |
915 | ||
652f093f | 916 | return 0; |
bd0362dd JC |
917 | } |
918 | ||
5dd2d332 | 919 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
920 | /** |
921 | * ixgbe_receive_skb - Send a completed packet up the stack | |
922 | * @adapter: board private structure | |
923 | * @skb: packet to send up | |
177db6ff MC |
924 | * @status: hardware indication of status of receive |
925 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
926 | * @rx_desc: rx descriptor | |
9a799d71 | 927 | **/ |
78b6f4ce | 928 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
929 | struct sk_buff *skb, u8 status, |
930 | struct ixgbe_ring *ring, | |
931 | union ixgbe_adv_rx_desc *rx_desc) | |
9a799d71 | 932 | { |
78b6f4ce HX |
933 | struct ixgbe_adapter *adapter = q_vector->adapter; |
934 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
935 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
936 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 937 | |
f62bbb5e JG |
938 | if (is_vlan && (tag & VLAN_VID_MASK)) |
939 | __vlan_hwaccel_put_tag(skb, tag); | |
940 | ||
941 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
942 | napi_gro_receive(napi, skb); | |
943 | else | |
944 | netif_rx(skb); | |
9a799d71 AK |
945 | } |
946 | ||
e59bd25d AV |
947 | /** |
948 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
949 | * @adapter: address of board private structure | |
950 | * @status_err: hardware indication of status of receive | |
951 | * @skb: skb currently being received and modified | |
952 | **/ | |
9a799d71 | 953 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
954 | union ixgbe_adv_rx_desc *rx_desc, |
955 | struct sk_buff *skb) | |
9a799d71 | 956 | { |
8bae1b2b DS |
957 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
958 | ||
bc8acf2c | 959 | skb_checksum_none_assert(skb); |
9a799d71 | 960 | |
712744be JB |
961 | /* Rx csum disabled */ |
962 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 963 | return; |
e59bd25d AV |
964 | |
965 | /* if IP and error */ | |
966 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
967 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
968 | adapter->hw_csum_rx_error++; |
969 | return; | |
970 | } | |
e59bd25d AV |
971 | |
972 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
973 | return; | |
974 | ||
975 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
976 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
977 | ||
978 | /* | |
979 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
980 | * checksum errors. | |
981 | */ | |
982 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
983 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
984 | return; | |
985 | ||
e59bd25d AV |
986 | adapter->hw_csum_rx_error++; |
987 | return; | |
988 | } | |
989 | ||
9a799d71 | 990 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 991 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
992 | } |
993 | ||
84ea2591 | 994 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 PW |
995 | { |
996 | /* | |
997 | * Force memory writes to complete before letting h/w | |
998 | * know there are new descriptors to fetch. (Only | |
999 | * applicable for weak-ordered memory model archs, | |
1000 | * such as IA-64). | |
1001 | */ | |
1002 | wmb(); | |
84ea2591 | 1003 | writel(val, rx_ring->tail); |
e8e26350 PW |
1004 | } |
1005 | ||
9a799d71 AK |
1006 | /** |
1007 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
1008 | * @adapter: address of board private structure | |
1009 | **/ | |
84418e3b | 1010 | void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, |
e8e9f696 | 1011 | struct ixgbe_ring *rx_ring, |
d5f398ed | 1012 | u16 cleaned_count) |
9a799d71 | 1013 | { |
9a799d71 AK |
1014 | struct pci_dev *pdev = adapter->pdev; |
1015 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 1016 | struct ixgbe_rx_buffer *bi; |
d5f398ed AD |
1017 | struct sk_buff *skb; |
1018 | u16 i = rx_ring->next_to_use; | |
9a799d71 AK |
1019 | |
1020 | while (cleaned_count--) { | |
31f05a2d | 1021 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
d5f398ed AD |
1022 | bi = &rx_ring->rx_buffer_info[i]; |
1023 | skb = bi->skb; | |
9a799d71 | 1024 | |
d5f398ed AD |
1025 | if (!skb) { |
1026 | skb = netdev_alloc_skb_ip_align(adapter->netdev, | |
1027 | rx_ring->rx_buf_len); | |
9a799d71 AK |
1028 | if (!skb) { |
1029 | adapter->alloc_rx_buff_failed++; | |
1030 | goto no_buffers; | |
1031 | } | |
d716a7d8 AD |
1032 | /* initialize queue mapping */ |
1033 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
d5f398ed | 1034 | bi->skb = skb; |
d716a7d8 | 1035 | } |
9a799d71 | 1036 | |
d716a7d8 AD |
1037 | if (!bi->dma) { |
1038 | bi->dma = dma_map_single(&pdev->dev, | |
d5f398ed | 1039 | skb->data, |
e8e9f696 | 1040 | rx_ring->rx_buf_len, |
1b507730 | 1041 | DMA_FROM_DEVICE); |
d5f398ed AD |
1042 | if (dma_mapping_error(&pdev->dev, bi->dma)) { |
1043 | adapter->alloc_rx_buff_failed++; | |
1044 | bi->dma = 0; | |
1045 | goto no_buffers; | |
1046 | } | |
9a799d71 | 1047 | } |
d5f398ed | 1048 | |
6e455b89 | 1049 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
d5f398ed AD |
1050 | if (!bi->page) { |
1051 | bi->page = netdev_alloc_page(adapter->netdev); | |
1052 | if (!bi->page) { | |
1053 | adapter->alloc_rx_page_failed++; | |
1054 | goto no_buffers; | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | if (!bi->page_dma) { | |
1059 | /* use a half page if we're re-using */ | |
1060 | bi->page_offset ^= PAGE_SIZE / 2; | |
1061 | bi->page_dma = dma_map_page(&pdev->dev, | |
1062 | bi->page, | |
1063 | bi->page_offset, | |
1064 | PAGE_SIZE / 2, | |
1065 | DMA_FROM_DEVICE); | |
1066 | if (dma_mapping_error(&pdev->dev, | |
1067 | bi->page_dma)) { | |
1068 | adapter->alloc_rx_page_failed++; | |
1069 | bi->page_dma = 0; | |
1070 | goto no_buffers; | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | /* Refresh the desc even if buffer_addrs didn't change | |
1075 | * because each write-back erases this info. */ | |
3a581073 JB |
1076 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
1077 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 1078 | } else { |
3a581073 | 1079 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
84418e3b | 1080 | rx_desc->read.hdr_addr = 0; |
9a799d71 AK |
1081 | } |
1082 | ||
1083 | i++; | |
1084 | if (i == rx_ring->count) | |
1085 | i = 0; | |
9a799d71 | 1086 | } |
7c6e0a43 | 1087 | |
9a799d71 AK |
1088 | no_buffers: |
1089 | if (rx_ring->next_to_use != i) { | |
1090 | rx_ring->next_to_use = i; | |
84ea2591 | 1091 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1092 | } |
1093 | } | |
1094 | ||
7c6e0a43 JB |
1095 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
1096 | { | |
1097 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
1098 | } | |
1099 | ||
1100 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
1101 | { | |
1102 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1103 | } | |
1104 | ||
f8212f97 AD |
1105 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
1106 | { | |
1107 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
e8e9f696 JP |
1108 | IXGBE_RXDADV_RSCCNT_MASK) >> |
1109 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
f8212f97 AD |
1110 | } |
1111 | ||
1112 | /** | |
1113 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
1114 | * @skb: pointer to the last skb in the rsc queue | |
94b982b2 | 1115 | * @count: pointer to number of packets coalesced in this context |
f8212f97 AD |
1116 | * |
1117 | * This function changes a queue full of hw rsc buffers into a completed | |
1118 | * packet. It uses the ->prev pointers to find the first packet and then | |
1119 | * turns it into the frag list owner. | |
1120 | **/ | |
94b982b2 | 1121 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb, |
e8e9f696 | 1122 | u64 *count) |
f8212f97 AD |
1123 | { |
1124 | unsigned int frag_list_size = 0; | |
1125 | ||
1126 | while (skb->prev) { | |
1127 | struct sk_buff *prev = skb->prev; | |
1128 | frag_list_size += skb->len; | |
1129 | skb->prev = NULL; | |
1130 | skb = prev; | |
94b982b2 | 1131 | *count += 1; |
f8212f97 AD |
1132 | } |
1133 | ||
1134 | skb_shinfo(skb)->frag_list = skb->next; | |
1135 | skb->next = NULL; | |
1136 | skb->len += frag_list_size; | |
1137 | skb->data_len += frag_list_size; | |
1138 | skb->truesize += frag_list_size; | |
1139 | return skb; | |
1140 | } | |
1141 | ||
43634e82 MC |
1142 | struct ixgbe_rsc_cb { |
1143 | dma_addr_t dma; | |
e8171aaa | 1144 | bool delay_unmap; |
43634e82 MC |
1145 | }; |
1146 | ||
1147 | #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) | |
1148 | ||
78b6f4ce | 1149 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1150 | struct ixgbe_ring *rx_ring, |
1151 | int *work_done, int work_to_do) | |
9a799d71 | 1152 | { |
78b6f4ce | 1153 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
1154 | struct pci_dev *pdev = adapter->pdev; |
1155 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
1156 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
1157 | struct sk_buff *skb; | |
f8212f97 | 1158 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 1159 | u32 len, staterr; |
177db6ff MC |
1160 | u16 hdr_info; |
1161 | bool cleaned = false; | |
9a799d71 | 1162 | int cleaned_count = 0; |
d2f4fbe2 | 1163 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3d8fd385 YZ |
1164 | #ifdef IXGBE_FCOE |
1165 | int ddp_bytes = 0; | |
1166 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
1167 | |
1168 | i = rx_ring->next_to_clean; | |
31f05a2d | 1169 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 AK |
1170 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
1171 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
1172 | |
1173 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 1174 | u32 upper_len = 0; |
9a799d71 AK |
1175 | if (*work_done >= work_to_do) |
1176 | break; | |
1177 | (*work_done)++; | |
1178 | ||
3c945e5b | 1179 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
6e455b89 | 1180 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
7c6e0a43 JB |
1181 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
1182 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 1183 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 | 1184 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); |
0b746e08 SN |
1185 | if ((len > IXGBE_RX_HDR_SIZE) || |
1186 | (upper_len && !(hdr_info & IXGBE_RXDADV_SPH))) | |
1187 | len = IXGBE_RX_HDR_SIZE; | |
7c6e0a43 | 1188 | } else { |
9a799d71 | 1189 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 1190 | } |
9a799d71 AK |
1191 | |
1192 | cleaned = true; | |
1193 | skb = rx_buffer_info->skb; | |
7ca3bc58 | 1194 | prefetch(skb->data); |
9a799d71 AK |
1195 | rx_buffer_info->skb = NULL; |
1196 | ||
21fa4e66 | 1197 | if (rx_buffer_info->dma) { |
43634e82 MC |
1198 | if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
1199 | (!(staterr & IXGBE_RXD_STAT_EOP)) && | |
e8171aaa | 1200 | (!(skb->prev))) { |
43634e82 MC |
1201 | /* |
1202 | * When HWRSC is enabled, delay unmapping | |
1203 | * of the first packet. It carries the | |
1204 | * header information, HW may still | |
1205 | * access the header after the writeback. | |
1206 | * Only unmap it when EOP is reached | |
1207 | */ | |
e8171aaa | 1208 | IXGBE_RSC_CB(skb)->delay_unmap = true; |
43634e82 | 1209 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; |
e8171aaa | 1210 | } else { |
1b507730 | 1211 | dma_unmap_single(&pdev->dev, |
e8e9f696 JP |
1212 | rx_buffer_info->dma, |
1213 | rx_ring->rx_buf_len, | |
1214 | DMA_FROM_DEVICE); | |
e8171aaa | 1215 | } |
4f57ca6e | 1216 | rx_buffer_info->dma = 0; |
9a799d71 AK |
1217 | skb_put(skb, len); |
1218 | } | |
1219 | ||
1220 | if (upper_len) { | |
1b507730 NN |
1221 | dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma, |
1222 | PAGE_SIZE / 2, DMA_FROM_DEVICE); | |
9a799d71 AK |
1223 | rx_buffer_info->page_dma = 0; |
1224 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
e8e9f696 JP |
1225 | rx_buffer_info->page, |
1226 | rx_buffer_info->page_offset, | |
1227 | upper_len); | |
762f4c57 JB |
1228 | |
1229 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
1230 | (page_count(rx_buffer_info->page) != 1)) | |
1231 | rx_buffer_info->page = NULL; | |
1232 | else | |
1233 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
1234 | |
1235 | skb->len += upper_len; | |
1236 | skb->data_len += upper_len; | |
1237 | skb->truesize += upper_len; | |
1238 | } | |
1239 | ||
1240 | i++; | |
1241 | if (i == rx_ring->count) | |
1242 | i = 0; | |
9a799d71 | 1243 | |
31f05a2d | 1244 | next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1245 | prefetch(next_rxd); |
9a799d71 | 1246 | cleaned_count++; |
f8212f97 | 1247 | |
0c19d6af | 1248 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
1249 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
1250 | ||
1251 | if (rsc_count) { | |
1252 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
1253 | IXGBE_RXDADV_NEXTP_SHIFT; | |
1254 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
1255 | } else { |
1256 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
1257 | } | |
1258 | ||
9a799d71 | 1259 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 | 1260 | if (skb->prev) |
e8e9f696 JP |
1261 | skb = ixgbe_transform_rsc_queue(skb, |
1262 | &(rx_ring->rsc_count)); | |
94b982b2 | 1263 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
e8171aaa | 1264 | if (IXGBE_RSC_CB(skb)->delay_unmap) { |
1b507730 NN |
1265 | dma_unmap_single(&pdev->dev, |
1266 | IXGBE_RSC_CB(skb)->dma, | |
e8e9f696 | 1267 | rx_ring->rx_buf_len, |
1b507730 | 1268 | DMA_FROM_DEVICE); |
fd3686a8 | 1269 | IXGBE_RSC_CB(skb)->dma = 0; |
e8171aaa | 1270 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 1271 | } |
94b982b2 | 1272 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) |
e8e9f696 JP |
1273 | rx_ring->rsc_count += |
1274 | skb_shinfo(skb)->nr_frags; | |
94b982b2 MC |
1275 | else |
1276 | rx_ring->rsc_count++; | |
1277 | rx_ring->rsc_flush++; | |
1278 | } | |
de1036b1 | 1279 | u64_stats_update_begin(&rx_ring->syncp); |
9a799d71 AK |
1280 | rx_ring->stats.packets++; |
1281 | rx_ring->stats.bytes += skb->len; | |
de1036b1 | 1282 | u64_stats_update_end(&rx_ring->syncp); |
9a799d71 | 1283 | } else { |
6e455b89 | 1284 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
f8212f97 AD |
1285 | rx_buffer_info->skb = next_buffer->skb; |
1286 | rx_buffer_info->dma = next_buffer->dma; | |
1287 | next_buffer->skb = skb; | |
1288 | next_buffer->dma = 0; | |
1289 | } else { | |
1290 | skb->next = next_buffer->skb; | |
1291 | skb->next->prev = skb; | |
1292 | } | |
7ca3bc58 | 1293 | rx_ring->non_eop_descs++; |
9a799d71 AK |
1294 | goto next_desc; |
1295 | } | |
1296 | ||
1297 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
1298 | dev_kfree_skb_irq(skb); | |
1299 | goto next_desc; | |
1300 | } | |
1301 | ||
8bae1b2b | 1302 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
1303 | |
1304 | /* probably a little skewed due to removing CRC */ | |
1305 | total_rx_bytes += skb->len; | |
1306 | total_rx_packets++; | |
1307 | ||
74ce8dd2 | 1308 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
1309 | #ifdef IXGBE_FCOE |
1310 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
1311 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
1312 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
1313 | if (!ddp_bytes) | |
332d4a7d | 1314 | goto next_desc; |
3d8fd385 | 1315 | } |
332d4a7d | 1316 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 1317 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
1318 | |
1319 | next_desc: | |
1320 | rx_desc->wb.upper.status_error = 0; | |
1321 | ||
1322 | /* return some buffers to hardware, one at a time is too slow */ | |
1323 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1324 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1325 | cleaned_count = 0; | |
1326 | } | |
1327 | ||
1328 | /* use prefetched values */ | |
1329 | rx_desc = next_rxd; | |
f8212f97 | 1330 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
1331 | |
1332 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
1333 | } |
1334 | ||
9a799d71 AK |
1335 | rx_ring->next_to_clean = i; |
1336 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1337 | ||
1338 | if (cleaned_count) | |
1339 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1340 | ||
3d8fd385 YZ |
1341 | #ifdef IXGBE_FCOE |
1342 | /* include DDPed FCoE data */ | |
1343 | if (ddp_bytes > 0) { | |
1344 | unsigned int mss; | |
1345 | ||
1346 | mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) - | |
1347 | sizeof(struct fc_frame_header) - | |
1348 | sizeof(struct fcoe_crc_eof); | |
1349 | if (mss > 512) | |
1350 | mss &= ~511; | |
1351 | total_rx_bytes += ddp_bytes; | |
1352 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1353 | } | |
1354 | #endif /* IXGBE_FCOE */ | |
1355 | ||
f494e8fa AV |
1356 | rx_ring->total_packets += total_rx_packets; |
1357 | rx_ring->total_bytes += total_rx_bytes; | |
f494e8fa | 1358 | |
9a799d71 AK |
1359 | return cleaned; |
1360 | } | |
1361 | ||
021230d4 | 1362 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1363 | /** |
1364 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1365 | * @adapter: board private structure | |
1366 | * | |
1367 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1368 | * interrupts. | |
1369 | **/ | |
1370 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1371 | { | |
021230d4 AV |
1372 | struct ixgbe_q_vector *q_vector; |
1373 | int i, j, q_vectors, v_idx, r_idx; | |
1374 | u32 mask; | |
9a799d71 | 1375 | |
021230d4 | 1376 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1377 | |
4df10466 JB |
1378 | /* |
1379 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1380 | * corresponding register. |
1381 | */ | |
1382 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1383 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1384 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1385 | r_idx = find_first_bit(q_vector->rxr_idx, |
e8e9f696 | 1386 | adapter->num_rx_queues); |
021230d4 AV |
1387 | |
1388 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1389 | j = adapter->rx_ring[r_idx]->reg_idx; |
e8e26350 | 1390 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 1391 | r_idx = find_next_bit(q_vector->rxr_idx, |
e8e9f696 JP |
1392 | adapter->num_rx_queues, |
1393 | r_idx + 1); | |
021230d4 AV |
1394 | } |
1395 | r_idx = find_first_bit(q_vector->txr_idx, | |
e8e9f696 | 1396 | adapter->num_tx_queues); |
021230d4 AV |
1397 | |
1398 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1399 | j = adapter->tx_ring[r_idx]->reg_idx; |
e8e26350 | 1400 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 1401 | r_idx = find_next_bit(q_vector->txr_idx, |
e8e9f696 JP |
1402 | adapter->num_tx_queues, |
1403 | r_idx + 1); | |
021230d4 AV |
1404 | } |
1405 | ||
021230d4 | 1406 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1407 | /* tx only */ |
1408 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1409 | else if (q_vector->rxr_count) |
f7554a2b NS |
1410 | /* rx or mixed */ |
1411 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1412 | |
fe49f04a | 1413 | ixgbe_write_eitr(q_vector); |
b25ebfd2 PW |
1414 | /* If Flow Director is enabled, set interrupt affinity */ |
1415 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
1416 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
1417 | /* | |
1418 | * Allocate the affinity_hint cpumask, assign the mask | |
1419 | * for this vector, and set our affinity_hint for | |
1420 | * this irq. | |
1421 | */ | |
1422 | if (!alloc_cpumask_var(&q_vector->affinity_mask, | |
1423 | GFP_KERNEL)) | |
1424 | return; | |
1425 | cpumask_set_cpu(v_idx, q_vector->affinity_mask); | |
1426 | irq_set_affinity_hint(adapter->msix_entries[v_idx].vector, | |
1427 | q_vector->affinity_mask); | |
1428 | } | |
9a799d71 AK |
1429 | } |
1430 | ||
e8e26350 PW |
1431 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1432 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
e8e9f696 | 1433 | v_idx); |
e8e26350 PW |
1434 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
1435 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
1436 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1437 | ||
41fb9248 | 1438 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1439 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1440 | if (adapter->num_vfs) |
1441 | mask &= ~(IXGBE_EIMS_OTHER | | |
1442 | IXGBE_EIMS_MAILBOX | | |
1443 | IXGBE_EIMS_LSC); | |
1444 | else | |
1445 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1446 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1447 | } |
1448 | ||
f494e8fa AV |
1449 | enum latency_range { |
1450 | lowest_latency = 0, | |
1451 | low_latency = 1, | |
1452 | bulk_latency = 2, | |
1453 | latency_invalid = 255 | |
1454 | }; | |
1455 | ||
1456 | /** | |
1457 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1458 | * @adapter: pointer to adapter | |
1459 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1460 | * @itr_setting: current throttle rate in ints/second | |
1461 | * @packets: the number of packets during this measurement interval | |
1462 | * @bytes: the number of bytes during this measurement interval | |
1463 | * | |
1464 | * Stores a new ITR value based on packets and byte | |
1465 | * counts during the last interrupt. The advantage of per interrupt | |
1466 | * computation is faster updates and more accurate ITR for the current | |
1467 | * traffic pattern. Constants in this function were computed | |
1468 | * based on theoretical maximum wire speed and thresholds were set based | |
1469 | * on testing data as well as attempting to minimize response time | |
1470 | * while increasing bulk throughput. | |
1471 | * this functionality is controlled by the InterruptThrottleRate module | |
1472 | * parameter (see ixgbe_param.c) | |
1473 | **/ | |
1474 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
1475 | u32 eitr, u8 itr_setting, |
1476 | int packets, int bytes) | |
f494e8fa AV |
1477 | { |
1478 | unsigned int retval = itr_setting; | |
1479 | u32 timepassed_us; | |
1480 | u64 bytes_perint; | |
1481 | ||
1482 | if (packets == 0) | |
1483 | goto update_itr_done; | |
1484 | ||
1485 | ||
1486 | /* simple throttlerate management | |
1487 | * 0-20MB/s lowest (100000 ints/s) | |
1488 | * 20-100MB/s low (20000 ints/s) | |
1489 | * 100-1249MB/s bulk (8000 ints/s) | |
1490 | */ | |
1491 | /* what was last interrupt timeslice? */ | |
1492 | timepassed_us = 1000000/eitr; | |
1493 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1494 | ||
1495 | switch (itr_setting) { | |
1496 | case lowest_latency: | |
1497 | if (bytes_perint > adapter->eitr_low) | |
1498 | retval = low_latency; | |
1499 | break; | |
1500 | case low_latency: | |
1501 | if (bytes_perint > adapter->eitr_high) | |
1502 | retval = bulk_latency; | |
1503 | else if (bytes_perint <= adapter->eitr_low) | |
1504 | retval = lowest_latency; | |
1505 | break; | |
1506 | case bulk_latency: | |
1507 | if (bytes_perint <= adapter->eitr_high) | |
1508 | retval = low_latency; | |
1509 | break; | |
1510 | } | |
1511 | ||
1512 | update_itr_done: | |
1513 | return retval; | |
1514 | } | |
1515 | ||
509ee935 JB |
1516 | /** |
1517 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1518 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1519 | * |
1520 | * This function is made to be called by ethtool and by the driver | |
1521 | * when it needs to update EITR registers at runtime. Hardware | |
1522 | * specific quirks/differences are taken care of here. | |
1523 | */ | |
fe49f04a | 1524 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1525 | { |
fe49f04a | 1526 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1527 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1528 | int v_idx = q_vector->v_idx; |
1529 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1530 | ||
509ee935 JB |
1531 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1532 | /* must write high and low 16 bits to reset counter */ | |
1533 | itr_reg |= (itr_reg << 16); | |
1534 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
f8d1dcaf JB |
1535 | /* |
1536 | * 82599 can support a value of zero, so allow it for | |
1537 | * max interrupt rate, but there is an errata where it can | |
1538 | * not be zero with RSC | |
1539 | */ | |
1540 | if (itr_reg == 8 && | |
1541 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
1542 | itr_reg = 0; | |
1543 | ||
509ee935 JB |
1544 | /* |
1545 | * set the WDIS bit to not clear the timer bits and cause an | |
1546 | * immediate assertion of the interrupt | |
1547 | */ | |
1548 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1549 | } | |
1550 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1551 | } | |
1552 | ||
f494e8fa AV |
1553 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1554 | { | |
1555 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
1556 | u32 new_itr; |
1557 | u8 current_itr, ret_itr; | |
fe49f04a | 1558 | int i, r_idx; |
f494e8fa AV |
1559 | struct ixgbe_ring *rx_ring, *tx_ring; |
1560 | ||
1561 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1562 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1563 | tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1564 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1565 | q_vector->tx_itr, |
1566 | tx_ring->total_packets, | |
1567 | tx_ring->total_bytes); | |
f494e8fa AV |
1568 | /* if the result for this queue would decrease interrupt |
1569 | * rate for this vector then use that result */ | |
30efa5a3 | 1570 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
e8e9f696 | 1571 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1572 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 1573 | r_idx + 1); |
f494e8fa AV |
1574 | } |
1575 | ||
1576 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1577 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1578 | rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1579 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1580 | q_vector->rx_itr, |
1581 | rx_ring->total_packets, | |
1582 | rx_ring->total_bytes); | |
f494e8fa AV |
1583 | /* if the result for this queue would decrease interrupt |
1584 | * rate for this vector then use that result */ | |
30efa5a3 | 1585 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
e8e9f696 | 1586 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1587 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 1588 | r_idx + 1); |
f494e8fa AV |
1589 | } |
1590 | ||
30efa5a3 | 1591 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1592 | |
1593 | switch (current_itr) { | |
1594 | /* counts and packets in update_itr are dependent on these numbers */ | |
1595 | case lowest_latency: | |
1596 | new_itr = 100000; | |
1597 | break; | |
1598 | case low_latency: | |
1599 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1600 | break; | |
1601 | case bulk_latency: | |
1602 | default: | |
1603 | new_itr = 8000; | |
1604 | break; | |
1605 | } | |
1606 | ||
1607 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1608 | /* do an exponential smoothing */ |
1609 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1610 | |
1611 | /* save the algorithm value here, not the smoothed one */ | |
1612 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1613 | |
1614 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1615 | } |
f494e8fa AV |
1616 | } |
1617 | ||
119fc60a MC |
1618 | /** |
1619 | * ixgbe_check_overtemp_task - worker thread to check over tempurature | |
1620 | * @work: pointer to work_struct containing our data | |
1621 | **/ | |
1622 | static void ixgbe_check_overtemp_task(struct work_struct *work) | |
1623 | { | |
1624 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
1625 | struct ixgbe_adapter, |
1626 | check_overtemp_task); | |
119fc60a MC |
1627 | struct ixgbe_hw *hw = &adapter->hw; |
1628 | u32 eicr = adapter->interrupt_event; | |
1629 | ||
7ca647bd JP |
1630 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) |
1631 | return; | |
1632 | ||
1633 | switch (hw->device_id) { | |
1634 | case IXGBE_DEV_ID_82599_T3_LOM: { | |
1635 | u32 autoneg; | |
1636 | bool link_up = false; | |
1637 | ||
1638 | if (hw->mac.ops.check_link) | |
1639 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
1640 | ||
1641 | if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) || | |
1642 | (eicr & IXGBE_EICR_LSC)) | |
1643 | /* Check if this is due to overtemp */ | |
1644 | if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP) | |
1645 | break; | |
1646 | return; | |
1647 | } | |
1648 | default: | |
1649 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 1650 | return; |
7ca647bd | 1651 | break; |
119fc60a | 1652 | } |
7ca647bd JP |
1653 | e_crit(drv, |
1654 | "Network adapter has been stopped because it has over heated. " | |
1655 | "Restart the computer. If the problem persists, " | |
1656 | "power off the system and replace the adapter\n"); | |
1657 | /* write to clear the interrupt */ | |
1658 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0); | |
119fc60a MC |
1659 | } |
1660 | ||
0befdb3e JB |
1661 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1662 | { | |
1663 | struct ixgbe_hw *hw = &adapter->hw; | |
1664 | ||
1665 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1666 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 1667 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
1668 | /* write to clear the interrupt */ |
1669 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1670 | } | |
1671 | } | |
cf8280ee | 1672 | |
e8e26350 PW |
1673 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1674 | { | |
1675 | struct ixgbe_hw *hw = &adapter->hw; | |
1676 | ||
1677 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1678 | /* Clear the interrupt */ | |
1679 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1680 | schedule_work(&adapter->multispeed_fiber_task); | |
1681 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1682 | /* Clear the interrupt */ | |
1683 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1684 | schedule_work(&adapter->sfp_config_module_task); | |
1685 | } else { | |
1686 | /* Interrupt isn't for us... */ | |
1687 | return; | |
1688 | } | |
1689 | } | |
1690 | ||
cf8280ee JB |
1691 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1692 | { | |
1693 | struct ixgbe_hw *hw = &adapter->hw; | |
1694 | ||
1695 | adapter->lsc_int++; | |
1696 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1697 | adapter->link_check_timeout = jiffies; | |
1698 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1699 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1700 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1701 | schedule_work(&adapter->watchdog_task); |
1702 | } | |
1703 | } | |
1704 | ||
9a799d71 AK |
1705 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1706 | { | |
1707 | struct net_device *netdev = data; | |
1708 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1709 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1710 | u32 eicr; |
1711 | ||
1712 | /* | |
1713 | * Workaround for Silicon errata. Use clear-by-write instead | |
1714 | * of clear-by-read. Reading with EICS will return the | |
1715 | * interrupt causes without clearing, which later be done | |
1716 | * with the write to EICR. | |
1717 | */ | |
1718 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1719 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1720 | |
cf8280ee JB |
1721 | if (eicr & IXGBE_EICR_LSC) |
1722 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1723 | |
1cdd1ec8 GR |
1724 | if (eicr & IXGBE_EICR_MAILBOX) |
1725 | ixgbe_msg_task(adapter); | |
1726 | ||
e8e26350 PW |
1727 | if (hw->mac.type == ixgbe_mac_82598EB) |
1728 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1729 | |
c4cf55e5 | 1730 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1731 | ixgbe_check_sfp_event(adapter, eicr); |
119fc60a MC |
1732 | adapter->interrupt_event = eicr; |
1733 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && | |
1734 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) | |
1735 | schedule_work(&adapter->check_overtemp_task); | |
c4cf55e5 PWJ |
1736 | |
1737 | /* Handle Flow Director Full threshold interrupt */ | |
1738 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1739 | int i; | |
1740 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1741 | /* Disable transmits before FDIR Re-initialization */ | |
1742 | netif_tx_stop_all_queues(netdev); | |
1743 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1744 | struct ixgbe_ring *tx_ring = | |
e8e9f696 | 1745 | adapter->tx_ring[i]; |
c4cf55e5 | 1746 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, |
e8e9f696 | 1747 | &tx_ring->reinit_state)) |
c4cf55e5 PWJ |
1748 | schedule_work(&adapter->fdir_reinit_task); |
1749 | } | |
1750 | } | |
1751 | } | |
d4f80882 AV |
1752 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1753 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1754 | |
1755 | return IRQ_HANDLED; | |
1756 | } | |
1757 | ||
fe49f04a AD |
1758 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1759 | u64 qmask) | |
1760 | { | |
1761 | u32 mask; | |
1762 | ||
1763 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1764 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1765 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1766 | } else { | |
1767 | mask = (qmask & 0xFFFFFFFF); | |
1768 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1769 | mask = (qmask >> 32); | |
1770 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1771 | } | |
1772 | /* skip the flush */ | |
1773 | } | |
1774 | ||
1775 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 1776 | u64 qmask) |
fe49f04a AD |
1777 | { |
1778 | u32 mask; | |
1779 | ||
1780 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1781 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1782 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1783 | } else { | |
1784 | mask = (qmask & 0xFFFFFFFF); | |
1785 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1786 | mask = (qmask >> 32); | |
1787 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1788 | } | |
1789 | /* skip the flush */ | |
1790 | } | |
1791 | ||
9a799d71 AK |
1792 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1793 | { | |
021230d4 AV |
1794 | struct ixgbe_q_vector *q_vector = data; |
1795 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1796 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1797 | int i, r_idx; |
1798 | ||
1799 | if (!q_vector->txr_count) | |
1800 | return IRQ_HANDLED; | |
1801 | ||
1802 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1803 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1804 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
1805 | tx_ring->total_bytes = 0; |
1806 | tx_ring->total_packets = 0; | |
021230d4 | 1807 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 1808 | r_idx + 1); |
021230d4 | 1809 | } |
9a799d71 | 1810 | |
9b471446 | 1811 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
1812 | napi_schedule(&q_vector->napi); |
1813 | ||
9a799d71 AK |
1814 | return IRQ_HANDLED; |
1815 | } | |
1816 | ||
021230d4 AV |
1817 | /** |
1818 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1819 | * @irq: unused | |
1820 | * @data: pointer to our q_vector struct for this interrupt vector | |
1821 | **/ | |
9a799d71 AK |
1822 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1823 | { | |
021230d4 AV |
1824 | struct ixgbe_q_vector *q_vector = data; |
1825 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1826 | struct ixgbe_ring *rx_ring; |
021230d4 | 1827 | int r_idx; |
30efa5a3 | 1828 | int i; |
021230d4 AV |
1829 | |
1830 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 | 1831 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 1832 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
1833 | rx_ring->total_bytes = 0; |
1834 | rx_ring->total_packets = 0; | |
1835 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 1836 | r_idx + 1); |
30efa5a3 JB |
1837 | } |
1838 | ||
021230d4 AV |
1839 | if (!q_vector->rxr_count) |
1840 | return IRQ_HANDLED; | |
1841 | ||
021230d4 | 1842 | /* disable interrupts on this vector only */ |
9b471446 | 1843 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 1844 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1845 | |
1846 | return IRQ_HANDLED; | |
1847 | } | |
1848 | ||
1849 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1850 | { | |
91281fd3 AD |
1851 | struct ixgbe_q_vector *q_vector = data; |
1852 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1853 | struct ixgbe_ring *ring; | |
1854 | int r_idx; | |
1855 | int i; | |
1856 | ||
1857 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1858 | return IRQ_HANDLED; | |
1859 | ||
1860 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1861 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1862 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1863 | ring->total_bytes = 0; |
1864 | ring->total_packets = 0; | |
1865 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 1866 | r_idx + 1); |
91281fd3 AD |
1867 | } |
1868 | ||
1869 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1870 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1871 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
1872 | ring->total_bytes = 0; |
1873 | ring->total_packets = 0; | |
1874 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 1875 | r_idx + 1); |
91281fd3 AD |
1876 | } |
1877 | ||
9b471446 | 1878 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 1879 | napi_schedule(&q_vector->napi); |
9a799d71 | 1880 | |
9a799d71 AK |
1881 | return IRQ_HANDLED; |
1882 | } | |
1883 | ||
021230d4 AV |
1884 | /** |
1885 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1886 | * @napi: napi struct with our devices info in it | |
1887 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1888 | * | |
f0848276 JB |
1889 | * This function is optimized for cleaning one queue only on a single |
1890 | * q_vector!!! | |
021230d4 | 1891 | **/ |
9a799d71 AK |
1892 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1893 | { | |
021230d4 | 1894 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 1895 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1896 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1897 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1898 | int work_done = 0; |
021230d4 | 1899 | long r_idx; |
9a799d71 | 1900 | |
021230d4 | 1901 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
4a0b9ca0 | 1902 | rx_ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1903 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1904 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1905 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1906 | #endif |
9a799d71 | 1907 | |
78b6f4ce | 1908 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1909 | |
021230d4 AV |
1910 | /* If all Rx work done, exit the polling mode */ |
1911 | if (work_done < budget) { | |
288379f0 | 1912 | napi_complete(napi); |
f7554a2b | 1913 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 1914 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1915 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a | 1916 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 1917 | ((u64)1 << q_vector->v_idx)); |
9a799d71 AK |
1918 | } |
1919 | ||
1920 | return work_done; | |
1921 | } | |
1922 | ||
f0848276 | 1923 | /** |
91281fd3 | 1924 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1925 | * @napi: napi struct with our devices info in it |
1926 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1927 | * | |
1928 | * This function will clean more than one rx queue associated with a | |
1929 | * q_vector. | |
1930 | **/ | |
91281fd3 | 1931 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1932 | { |
1933 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 1934 | container_of(napi, struct ixgbe_q_vector, napi); |
f0848276 | 1935 | struct ixgbe_adapter *adapter = q_vector->adapter; |
91281fd3 | 1936 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1937 | int work_done = 0, i; |
1938 | long r_idx; | |
91281fd3 AD |
1939 | bool tx_clean_complete = true; |
1940 | ||
1941 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1942 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1943 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1944 | #ifdef CONFIG_IXGBE_DCA |
1945 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1946 | ixgbe_update_tx_dca(adapter, ring); | |
1947 | #endif | |
1948 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1949 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 1950 | r_idx + 1); |
91281fd3 | 1951 | } |
f0848276 JB |
1952 | |
1953 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1954 | * the budget to go below 1 because we'll exit polling */ | |
1955 | budget /= (q_vector->rxr_count ?: 1); | |
1956 | budget = max(budget, 1); | |
1957 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1958 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1959 | ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1960 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1961 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1962 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1963 | #endif |
91281fd3 | 1964 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 | 1965 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 1966 | r_idx + 1); |
f0848276 JB |
1967 | } |
1968 | ||
1969 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 1970 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 1971 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1972 | if (work_done < budget) { |
288379f0 | 1973 | napi_complete(napi); |
f7554a2b | 1974 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
1975 | ixgbe_set_itr_msix(q_vector); |
1976 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a | 1977 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 1978 | ((u64)1 << q_vector->v_idx)); |
f0848276 JB |
1979 | return 0; |
1980 | } | |
1981 | ||
1982 | return work_done; | |
1983 | } | |
91281fd3 AD |
1984 | |
1985 | /** | |
1986 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1987 | * @napi: napi struct with our devices info in it | |
1988 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1989 | * | |
1990 | * This function is optimized for cleaning one queue only on a single | |
1991 | * q_vector!!! | |
1992 | **/ | |
1993 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1994 | { | |
1995 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 1996 | container_of(napi, struct ixgbe_q_vector, napi); |
91281fd3 AD |
1997 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1998 | struct ixgbe_ring *tx_ring = NULL; | |
1999 | int work_done = 0; | |
2000 | long r_idx; | |
2001 | ||
2002 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
4a0b9ca0 | 2003 | tx_ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2004 | #ifdef CONFIG_IXGBE_DCA |
2005 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2006 | ixgbe_update_tx_dca(adapter, tx_ring); | |
2007 | #endif | |
2008 | ||
2009 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
2010 | work_done = budget; | |
2011 | ||
f7554a2b | 2012 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
2013 | if (work_done < budget) { |
2014 | napi_complete(napi); | |
f7554a2b | 2015 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
2016 | ixgbe_set_itr_msix(q_vector); |
2017 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
e8e9f696 JP |
2018 | ixgbe_irq_enable_queues(adapter, |
2019 | ((u64)1 << q_vector->v_idx)); | |
91281fd3 AD |
2020 | } |
2021 | ||
2022 | return work_done; | |
2023 | } | |
2024 | ||
021230d4 | 2025 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
e8e9f696 | 2026 | int r_idx) |
021230d4 | 2027 | { |
7a921c93 AD |
2028 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2029 | ||
2030 | set_bit(r_idx, q_vector->rxr_idx); | |
2031 | q_vector->rxr_count++; | |
021230d4 AV |
2032 | } |
2033 | ||
2034 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
e8e9f696 | 2035 | int t_idx) |
021230d4 | 2036 | { |
7a921c93 AD |
2037 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2038 | ||
2039 | set_bit(t_idx, q_vector->txr_idx); | |
2040 | q_vector->txr_count++; | |
021230d4 AV |
2041 | } |
2042 | ||
9a799d71 | 2043 | /** |
021230d4 AV |
2044 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
2045 | * @adapter: board private structure to initialize | |
2046 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 2047 | * |
021230d4 AV |
2048 | * This function maps descriptor rings to the queue-specific vectors |
2049 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
2050 | * one vector per ring/queue, but on a constrained vector budget, we | |
2051 | * group the rings as "efficiently" as possible. You would add new | |
2052 | * mapping configurations in here. | |
9a799d71 | 2053 | **/ |
021230d4 | 2054 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 2055 | int vectors) |
021230d4 AV |
2056 | { |
2057 | int v_start = 0; | |
2058 | int rxr_idx = 0, txr_idx = 0; | |
2059 | int rxr_remaining = adapter->num_rx_queues; | |
2060 | int txr_remaining = adapter->num_tx_queues; | |
2061 | int i, j; | |
2062 | int rqpv, tqpv; | |
2063 | int err = 0; | |
2064 | ||
2065 | /* No mapping required if MSI-X is disabled. */ | |
2066 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2067 | goto out; | |
9a799d71 | 2068 | |
021230d4 AV |
2069 | /* |
2070 | * The ideal configuration... | |
2071 | * We have enough vectors to map one per queue. | |
2072 | */ | |
2073 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
2074 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
2075 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 2076 | |
021230d4 AV |
2077 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
2078 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 2079 | |
9a799d71 | 2080 | goto out; |
021230d4 | 2081 | } |
9a799d71 | 2082 | |
021230d4 AV |
2083 | /* |
2084 | * If we don't have enough vectors for a 1-to-1 | |
2085 | * mapping, we'll have to group them so there are | |
2086 | * multiple queues per vector. | |
2087 | */ | |
2088 | /* Re-adjusting *qpv takes care of the remainder. */ | |
2089 | for (i = v_start; i < vectors; i++) { | |
2090 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
2091 | for (j = 0; j < rqpv; j++) { | |
2092 | map_vector_to_rxq(adapter, i, rxr_idx); | |
2093 | rxr_idx++; | |
2094 | rxr_remaining--; | |
2095 | } | |
2096 | } | |
2097 | for (i = v_start; i < vectors; i++) { | |
2098 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
2099 | for (j = 0; j < tqpv; j++) { | |
2100 | map_vector_to_txq(adapter, i, txr_idx); | |
2101 | txr_idx++; | |
2102 | txr_remaining--; | |
9a799d71 | 2103 | } |
9a799d71 AK |
2104 | } |
2105 | ||
021230d4 AV |
2106 | out: |
2107 | return err; | |
2108 | } | |
2109 | ||
2110 | /** | |
2111 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2112 | * @adapter: board private structure | |
2113 | * | |
2114 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2115 | * interrupts from the kernel. | |
2116 | **/ | |
2117 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2118 | { | |
2119 | struct net_device *netdev = adapter->netdev; | |
2120 | irqreturn_t (*handler)(int, void *); | |
2121 | int i, vector, q_vectors, err; | |
e8e9f696 | 2122 | int ri = 0, ti = 0; |
021230d4 AV |
2123 | |
2124 | /* Decrement for Other and TCP Timer vectors */ | |
2125 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2126 | ||
2127 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
2128 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
2129 | if (err) | |
2130 | goto out; | |
2131 | ||
2132 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
e8e9f696 JP |
2133 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
2134 | &ixgbe_msix_clean_many) | |
021230d4 | 2135 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 2136 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 | 2137 | |
e8e9f696 | 2138 | if (handler == &ixgbe_msix_clean_rx) { |
cb13fc20 RO |
2139 | sprintf(adapter->name[vector], "%s-%s-%d", |
2140 | netdev->name, "rx", ri++); | |
e8e9f696 | 2141 | } else if (handler == &ixgbe_msix_clean_tx) { |
cb13fc20 RO |
2142 | sprintf(adapter->name[vector], "%s-%s-%d", |
2143 | netdev->name, "tx", ti++); | |
e8e9f696 | 2144 | } else |
cb13fc20 RO |
2145 | sprintf(adapter->name[vector], "%s-%s-%d", |
2146 | netdev->name, "TxRx", vector); | |
2147 | ||
021230d4 | 2148 | err = request_irq(adapter->msix_entries[vector].vector, |
e8e9f696 JP |
2149 | handler, 0, adapter->name[vector], |
2150 | adapter->q_vector[vector]); | |
9a799d71 | 2151 | if (err) { |
396e799c | 2152 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2153 | "Error: %d\n", err); |
021230d4 | 2154 | goto free_queue_irqs; |
9a799d71 | 2155 | } |
9a799d71 AK |
2156 | } |
2157 | ||
021230d4 AV |
2158 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
2159 | err = request_irq(adapter->msix_entries[vector].vector, | |
e8e9f696 | 2160 | ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 | 2161 | if (err) { |
396e799c | 2162 | e_err(probe, "request_irq for msix_lsc failed: %d\n", err); |
021230d4 | 2163 | goto free_queue_irqs; |
9a799d71 AK |
2164 | } |
2165 | ||
9a799d71 AK |
2166 | return 0; |
2167 | ||
021230d4 AV |
2168 | free_queue_irqs: |
2169 | for (i = vector - 1; i >= 0; i--) | |
2170 | free_irq(adapter->msix_entries[--vector].vector, | |
e8e9f696 | 2171 | adapter->q_vector[i]); |
021230d4 AV |
2172 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2173 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2174 | kfree(adapter->msix_entries); |
2175 | adapter->msix_entries = NULL; | |
021230d4 | 2176 | out: |
9a799d71 AK |
2177 | return err; |
2178 | } | |
2179 | ||
f494e8fa AV |
2180 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
2181 | { | |
7a921c93 | 2182 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
2183 | u8 current_itr; |
2184 | u32 new_itr = q_vector->eitr; | |
4a0b9ca0 PW |
2185 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
2186 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
f494e8fa | 2187 | |
30efa5a3 | 2188 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2189 | q_vector->tx_itr, |
2190 | tx_ring->total_packets, | |
2191 | tx_ring->total_bytes); | |
30efa5a3 | 2192 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2193 | q_vector->rx_itr, |
2194 | rx_ring->total_packets, | |
2195 | rx_ring->total_bytes); | |
f494e8fa | 2196 | |
30efa5a3 | 2197 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
2198 | |
2199 | switch (current_itr) { | |
2200 | /* counts and packets in update_itr are dependent on these numbers */ | |
2201 | case lowest_latency: | |
2202 | new_itr = 100000; | |
2203 | break; | |
2204 | case low_latency: | |
2205 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2206 | break; | |
2207 | case bulk_latency: | |
2208 | new_itr = 8000; | |
2209 | break; | |
2210 | default: | |
2211 | break; | |
2212 | } | |
2213 | ||
2214 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
2215 | /* do an exponential smoothing */ |
2216 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
2217 | |
2218 | /* save the algorithm value here, not the smoothed one */ | |
2219 | q_vector->eitr = new_itr; | |
fe49f04a AD |
2220 | |
2221 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2222 | } |
f494e8fa AV |
2223 | } |
2224 | ||
79aefa45 AD |
2225 | /** |
2226 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
2227 | * @adapter: board private structure | |
2228 | **/ | |
6af3b9eb ET |
2229 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2230 | bool flush) | |
79aefa45 AD |
2231 | { |
2232 | u32 mask; | |
835462fc NS |
2233 | |
2234 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
119fc60a MC |
2235 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
2236 | mask |= IXGBE_EIMS_GPI_SDP0; | |
6ab33d51 DM |
2237 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2238 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 2239 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 2240 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
2241 | mask |= IXGBE_EIMS_GPI_SDP1; |
2242 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
2243 | if (adapter->num_vfs) |
2244 | mask |= IXGBE_EIMS_MAILBOX; | |
e8e26350 | 2245 | } |
c4cf55e5 PWJ |
2246 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2247 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2248 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 2249 | |
79aefa45 | 2250 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
6af3b9eb ET |
2251 | if (queues) |
2252 | ixgbe_irq_enable_queues(adapter, ~0); | |
2253 | if (flush) | |
2254 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1cdd1ec8 GR |
2255 | |
2256 | if (adapter->num_vfs > 32) { | |
2257 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
2258 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
2259 | } | |
79aefa45 | 2260 | } |
021230d4 | 2261 | |
9a799d71 | 2262 | /** |
021230d4 | 2263 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2264 | * @irq: interrupt number |
2265 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2266 | **/ |
2267 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2268 | { | |
2269 | struct net_device *netdev = data; | |
2270 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2271 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 2272 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2273 | u32 eicr; |
2274 | ||
54037505 | 2275 | /* |
6af3b9eb | 2276 | * Workaround for silicon errata on 82598. Mask the interrupts |
54037505 DS |
2277 | * before the read of EICR. |
2278 | */ | |
2279 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2280 | ||
021230d4 AV |
2281 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
2282 | * therefore no explict interrupt disable is necessary */ | |
2283 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e | 2284 | if (!eicr) { |
6af3b9eb ET |
2285 | /* |
2286 | * shared interrupt alert! | |
f47cf66e | 2287 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2288 | * have disabled interrupts due to EIAM |
2289 | * finish the workaround of silicon errata on 82598. Unmask | |
2290 | * the interrupt that we masked before the EICR read. | |
2291 | */ | |
2292 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2293 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2294 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2295 | } |
9a799d71 | 2296 | |
cf8280ee JB |
2297 | if (eicr & IXGBE_EICR_LSC) |
2298 | ixgbe_check_lsc(adapter); | |
021230d4 | 2299 | |
e8e26350 PW |
2300 | if (hw->mac.type == ixgbe_mac_82599EB) |
2301 | ixgbe_check_sfp_event(adapter, eicr); | |
2302 | ||
0befdb3e | 2303 | ixgbe_check_fan_failure(adapter, eicr); |
119fc60a MC |
2304 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2305 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) | |
2306 | schedule_work(&adapter->check_overtemp_task); | |
0befdb3e | 2307 | |
7a921c93 | 2308 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
2309 | adapter->tx_ring[0]->total_packets = 0; |
2310 | adapter->tx_ring[0]->total_bytes = 0; | |
2311 | adapter->rx_ring[0]->total_packets = 0; | |
2312 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 2313 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 2314 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
2315 | } |
2316 | ||
6af3b9eb ET |
2317 | /* |
2318 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2319 | * ixgbe_poll will re-enable the queue interrupts | |
2320 | */ | |
2321 | ||
2322 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2323 | ixgbe_irq_enable(adapter, false, false); | |
2324 | ||
9a799d71 AK |
2325 | return IRQ_HANDLED; |
2326 | } | |
2327 | ||
021230d4 AV |
2328 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
2329 | { | |
2330 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2331 | ||
2332 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 2333 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
2334 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
2335 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
2336 | q_vector->rxr_count = 0; | |
2337 | q_vector->txr_count = 0; | |
2338 | } | |
2339 | } | |
2340 | ||
9a799d71 AK |
2341 | /** |
2342 | * ixgbe_request_irq - initialize interrupts | |
2343 | * @adapter: board private structure | |
2344 | * | |
2345 | * Attempts to configure interrupts using the best available | |
2346 | * capabilities of the hardware and kernel. | |
2347 | **/ | |
021230d4 | 2348 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2349 | { |
2350 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2351 | int err; |
9a799d71 | 2352 | |
021230d4 AV |
2353 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2354 | err = ixgbe_request_msix_irqs(adapter); | |
2355 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 2356 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
e8e9f696 | 2357 | netdev->name, netdev); |
021230d4 | 2358 | } else { |
a0607fd3 | 2359 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
e8e9f696 | 2360 | netdev->name, netdev); |
9a799d71 AK |
2361 | } |
2362 | ||
9a799d71 | 2363 | if (err) |
396e799c | 2364 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2365 | |
9a799d71 AK |
2366 | return err; |
2367 | } | |
2368 | ||
2369 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2370 | { | |
2371 | struct net_device *netdev = adapter->netdev; | |
2372 | ||
2373 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 2374 | int i, q_vectors; |
9a799d71 | 2375 | |
021230d4 AV |
2376 | q_vectors = adapter->num_msix_vectors; |
2377 | ||
2378 | i = q_vectors - 1; | |
9a799d71 | 2379 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 2380 | |
021230d4 AV |
2381 | i--; |
2382 | for (; i >= 0; i--) { | |
2383 | free_irq(adapter->msix_entries[i].vector, | |
e8e9f696 | 2384 | adapter->q_vector[i]); |
021230d4 AV |
2385 | } |
2386 | ||
2387 | ixgbe_reset_q_vectors(adapter); | |
2388 | } else { | |
2389 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
2390 | } |
2391 | } | |
2392 | ||
22d5a71b JB |
2393 | /** |
2394 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2395 | * @adapter: board private structure | |
2396 | **/ | |
2397 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2398 | { | |
835462fc NS |
2399 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2400 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
2401 | } else { | |
2402 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
2403 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2404 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
2405 | if (adapter->num_vfs > 32) |
2406 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
22d5a71b JB |
2407 | } |
2408 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2409 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2410 | int i; | |
2411 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2412 | synchronize_irq(adapter->msix_entries[i].vector); | |
2413 | } else { | |
2414 | synchronize_irq(adapter->pdev->irq); | |
2415 | } | |
2416 | } | |
2417 | ||
9a799d71 AK |
2418 | /** |
2419 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2420 | * | |
2421 | **/ | |
2422 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2423 | { | |
9a799d71 AK |
2424 | struct ixgbe_hw *hw = &adapter->hw; |
2425 | ||
021230d4 | 2426 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
e8e9f696 | 2427 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2428 | |
e8e26350 PW |
2429 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2430 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2431 | |
2432 | map_vector_to_rxq(adapter, 0, 0); | |
2433 | map_vector_to_txq(adapter, 0, 0); | |
2434 | ||
396e799c | 2435 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2436 | } |
2437 | ||
43e69bf0 AD |
2438 | /** |
2439 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2440 | * @adapter: board private structure | |
2441 | * @ring: structure containing ring specific data | |
2442 | * | |
2443 | * Configure the Tx descriptor ring after a reset. | |
2444 | **/ | |
84418e3b AD |
2445 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2446 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2447 | { |
2448 | struct ixgbe_hw *hw = &adapter->hw; | |
2449 | u64 tdba = ring->dma; | |
2f1860b8 AD |
2450 | int wait_loop = 10; |
2451 | u32 txdctl; | |
43e69bf0 AD |
2452 | u16 reg_idx = ring->reg_idx; |
2453 | ||
2f1860b8 AD |
2454 | /* disable queue to avoid issues while updating state */ |
2455 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
2456 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), | |
2457 | txdctl & ~IXGBE_TXDCTL_ENABLE); | |
2458 | IXGBE_WRITE_FLUSH(hw); | |
2459 | ||
43e69bf0 | 2460 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2461 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2462 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2463 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2464 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2465 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2466 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2467 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2468 | |
2f1860b8 AD |
2469 | /* configure fetching thresholds */ |
2470 | if (adapter->rx_itr_setting == 0) { | |
2471 | /* cannot set wthresh when itr==0 */ | |
2472 | txdctl &= ~0x007F0000; | |
2473 | } else { | |
2474 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ | |
2475 | txdctl |= (8 << 16); | |
2476 | } | |
2477 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2478 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2479 | txdctl |= 32; | |
2480 | } | |
2481 | ||
2482 | /* reinitialize flowdirector state */ | |
2483 | set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state); | |
2484 | ||
2485 | /* enable queue */ | |
2486 | txdctl |= IXGBE_TXDCTL_ENABLE; | |
2487 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); | |
2488 | ||
2489 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2490 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2491 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2492 | return; | |
2493 | ||
2494 | /* poll to verify queue is enabled */ | |
2495 | do { | |
2496 | msleep(1); | |
2497 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
2498 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2499 | if (!wait_loop) | |
2500 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2501 | } |
2502 | ||
120ff942 AD |
2503 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2504 | { | |
2505 | struct ixgbe_hw *hw = &adapter->hw; | |
2506 | u32 rttdcs; | |
2507 | u32 mask; | |
2508 | ||
2509 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2510 | return; | |
2511 | ||
2512 | /* disable the arbiter while setting MTQC */ | |
2513 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2514 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2515 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2516 | ||
2517 | /* set transmit pool layout */ | |
2518 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2519 | switch (adapter->flags & mask) { | |
2520 | ||
2521 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2522 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2523 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2524 | break; | |
2525 | ||
2526 | case (IXGBE_FLAG_DCB_ENABLED): | |
2527 | /* We enable 8 traffic classes, DCB only */ | |
2528 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2529 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
2530 | break; | |
2531 | ||
2532 | default: | |
2533 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); | |
2534 | break; | |
2535 | } | |
2536 | ||
2537 | /* re-enable the arbiter */ | |
2538 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2539 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2540 | } | |
2541 | ||
9a799d71 | 2542 | /** |
3a581073 | 2543 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2544 | * @adapter: board private structure |
2545 | * | |
2546 | * Configure the Tx unit of the MAC after a reset. | |
2547 | **/ | |
2548 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2549 | { | |
2f1860b8 AD |
2550 | struct ixgbe_hw *hw = &adapter->hw; |
2551 | u32 dmatxctl; | |
43e69bf0 | 2552 | u32 i; |
9a799d71 | 2553 | |
2f1860b8 AD |
2554 | ixgbe_setup_mtqc(adapter); |
2555 | ||
2556 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2557 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2558 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2559 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2560 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2561 | } | |
2562 | ||
9a799d71 | 2563 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2564 | for (i = 0; i < adapter->num_tx_queues; i++) |
2565 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2566 | } |
2567 | ||
e8e26350 | 2568 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2569 | |
a6616b42 | 2570 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2571 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2572 | { |
cc41ac7c | 2573 | u32 srrctl; |
a6616b42 | 2574 | int index; |
0cefafad | 2575 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 2576 | |
a6616b42 YZ |
2577 | index = rx_ring->reg_idx; |
2578 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2579 | unsigned long mask; | |
0cefafad | 2580 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb | 2581 | index = index & mask; |
cc41ac7c | 2582 | } |
cc41ac7c JB |
2583 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); |
2584 | ||
2585 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2586 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2587 | if (adapter->num_vfs) |
2588 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2589 | |
afafd5b0 AD |
2590 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2591 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2592 | ||
6e455b89 | 2593 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
afafd5b0 AD |
2594 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2595 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2596 | #else | |
2597 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2598 | #endif | |
cc41ac7c | 2599 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2600 | } else { |
afafd5b0 AD |
2601 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2602 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2603 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2604 | } |
e8e26350 | 2605 | |
cc41ac7c JB |
2606 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
2607 | } | |
9a799d71 | 2608 | |
05abb126 | 2609 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2610 | { |
05abb126 AD |
2611 | struct ixgbe_hw *hw = &adapter->hw; |
2612 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2613 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2614 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2615 | u32 mrqc = 0, reta = 0; |
2616 | u32 rxcsum; | |
2617 | int i, j; | |
0cefafad JB |
2618 | int mask; |
2619 | ||
05abb126 AD |
2620 | /* Fill out hash function seeds */ |
2621 | for (i = 0; i < 10; i++) | |
2622 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2623 | ||
2624 | /* Fill out redirection table */ | |
2625 | for (i = 0, j = 0; i < 128; i++, j++) { | |
2626 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2627 | j = 0; | |
2628 | /* reta = 4-byte sliding window of | |
2629 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2630 | reta = (reta << 8) | (j * 0x11); | |
2631 | if ((i & 3) == 3) | |
2632 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2633 | } | |
0cefafad | 2634 | |
05abb126 AD |
2635 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2636 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2637 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2638 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2639 | ||
2640 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
2641 | mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED; | |
2642 | else | |
2643 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
0cefafad | 2644 | #ifdef CONFIG_IXGBE_DCB |
05abb126 | 2645 | | IXGBE_FLAG_DCB_ENABLED |
0cefafad | 2646 | #endif |
05abb126 AD |
2647 | | IXGBE_FLAG_SRIOV_ENABLED |
2648 | ); | |
0cefafad JB |
2649 | |
2650 | switch (mask) { | |
2651 | case (IXGBE_FLAG_RSS_ENABLED): | |
2652 | mrqc = IXGBE_MRQC_RSSEN; | |
2653 | break; | |
1cdd1ec8 GR |
2654 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2655 | mrqc = IXGBE_MRQC_VMDQEN; | |
2656 | break; | |
0cefafad JB |
2657 | #ifdef CONFIG_IXGBE_DCB |
2658 | case (IXGBE_FLAG_DCB_ENABLED): | |
2659 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2660 | break; | |
2661 | #endif /* CONFIG_IXGBE_DCB */ | |
2662 | default: | |
2663 | break; | |
2664 | } | |
2665 | ||
05abb126 AD |
2666 | /* Perform hash on these packet types */ |
2667 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2668 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2669 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2670 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2671 | ||
2672 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
2673 | } |
2674 | ||
bb5a9ad2 NS |
2675 | /** |
2676 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2677 | * @adapter: address of board private structure | |
2678 | * @index: index of ring to set | |
bb5a9ad2 | 2679 | **/ |
7367096a AD |
2680 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
2681 | struct ixgbe_ring *ring) | |
bb5a9ad2 | 2682 | { |
bb5a9ad2 | 2683 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2684 | u32 rscctrl; |
edd2ea55 | 2685 | int rx_buf_len; |
7367096a AD |
2686 | u16 reg_idx = ring->reg_idx; |
2687 | ||
2688 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
2689 | return; | |
bb5a9ad2 | 2690 | |
7367096a AD |
2691 | rx_buf_len = ring->rx_buf_len; |
2692 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
bb5a9ad2 NS |
2693 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2694 | /* | |
2695 | * we must limit the number of descriptors so that the | |
2696 | * total size of max desc * buf_len is not greater | |
2697 | * than 65535 | |
2698 | */ | |
7367096a | 2699 | if (ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
bb5a9ad2 NS |
2700 | #if (MAX_SKB_FRAGS > 16) |
2701 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2702 | #elif (MAX_SKB_FRAGS > 8) | |
2703 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2704 | #elif (MAX_SKB_FRAGS > 4) | |
2705 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2706 | #else | |
2707 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2708 | #endif | |
2709 | } else { | |
2710 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2711 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2712 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2713 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2714 | else | |
2715 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2716 | } | |
7367096a | 2717 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2718 | } |
2719 | ||
9e10e045 AD |
2720 | /** |
2721 | * ixgbe_set_uta - Set unicast filter table address | |
2722 | * @adapter: board private structure | |
2723 | * | |
2724 | * The unicast table address is a register array of 32-bit registers. | |
2725 | * The table is meant to be used in a way similar to how the MTA is used | |
2726 | * however due to certain limitations in the hardware it is necessary to | |
2727 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2728 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2729 | **/ | |
2730 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2731 | { | |
2732 | struct ixgbe_hw *hw = &adapter->hw; | |
2733 | int i; | |
2734 | ||
2735 | /* The UTA table only exists on 82599 hardware and newer */ | |
2736 | if (hw->mac.type < ixgbe_mac_82599EB) | |
2737 | return; | |
2738 | ||
2739 | /* we only need to do this if VMDq is enabled */ | |
2740 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2741 | return; | |
2742 | ||
2743 | for (i = 0; i < 128; i++) | |
2744 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
2745 | } | |
2746 | ||
2747 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
2748 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2749 | struct ixgbe_ring *ring) | |
2750 | { | |
2751 | struct ixgbe_hw *hw = &adapter->hw; | |
2752 | int reg_idx = ring->reg_idx; | |
2753 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
2754 | u32 rxdctl; | |
2755 | ||
2756 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2757 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2758 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2759 | return; | |
2760 | ||
2761 | do { | |
2762 | msleep(1); | |
2763 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2764 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2765 | ||
2766 | if (!wait_loop) { | |
2767 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
2768 | "the polling period\n", reg_idx); | |
2769 | } | |
2770 | } | |
2771 | ||
84418e3b AD |
2772 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
2773 | struct ixgbe_ring *ring) | |
acd37177 AD |
2774 | { |
2775 | struct ixgbe_hw *hw = &adapter->hw; | |
2776 | u64 rdba = ring->dma; | |
9e10e045 | 2777 | u32 rxdctl; |
acd37177 AD |
2778 | u16 reg_idx = ring->reg_idx; |
2779 | ||
9e10e045 AD |
2780 | /* disable queue to avoid issues while updating state */ |
2781 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2782 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), | |
2783 | rxdctl & ~IXGBE_RXDCTL_ENABLE); | |
2784 | IXGBE_WRITE_FLUSH(hw); | |
2785 | ||
acd37177 AD |
2786 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
2787 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
2788 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
2789 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
2790 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
2791 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 2792 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
2793 | |
2794 | ixgbe_configure_srrctl(adapter, ring); | |
2795 | ixgbe_configure_rscctl(adapter, ring); | |
2796 | ||
2797 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
2798 | /* | |
2799 | * enable cache line friendly hardware writes: | |
2800 | * PTHRESH=32 descriptors (half the internal cache), | |
2801 | * this also removes ugly rx_no_buffer_count increment | |
2802 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
2803 | * WTHRESH=8 burst writeback up to two cache lines | |
2804 | */ | |
2805 | rxdctl &= ~0x3FFFFF; | |
2806 | rxdctl |= 0x080420; | |
2807 | } | |
2808 | ||
2809 | /* enable receive descriptor ring */ | |
2810 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
2811 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2812 | ||
2813 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
2814 | ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring)); | |
acd37177 AD |
2815 | } |
2816 | ||
48654521 AD |
2817 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
2818 | { | |
2819 | struct ixgbe_hw *hw = &adapter->hw; | |
2820 | int p; | |
2821 | ||
2822 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
2823 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
2824 | IXGBE_PSRTYPE_UDPHDR | |
2825 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 2826 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 2827 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
2828 | |
2829 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2830 | return; | |
2831 | ||
2832 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
2833 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
2834 | ||
2835 | for (p = 0; p < adapter->num_rx_pools; p++) | |
2836 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
2837 | psrtype); | |
2838 | } | |
2839 | ||
f5b4a52e AD |
2840 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
2841 | { | |
2842 | struct ixgbe_hw *hw = &adapter->hw; | |
2843 | u32 gcr_ext; | |
2844 | u32 vt_reg_bits; | |
2845 | u32 reg_offset, vf_shift; | |
2846 | u32 vmdctl; | |
2847 | ||
2848 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2849 | return; | |
2850 | ||
2851 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
2852 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
2853 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
2854 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
2855 | ||
2856 | vf_shift = adapter->num_vfs % 32; | |
2857 | reg_offset = (adapter->num_vfs > 32) ? 1 : 0; | |
2858 | ||
2859 | /* Enable only the PF's pool for Tx/Rx */ | |
2860 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
2861 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
2862 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
2863 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
2864 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
2865 | ||
2866 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
2867 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
2868 | ||
2869 | /* | |
2870 | * Set up VF register offsets for selected VT Mode, | |
2871 | * i.e. 32 or 64 VFs for SR-IOV | |
2872 | */ | |
2873 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
2874 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
2875 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
2876 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
2877 | ||
2878 | /* enable Tx loopback for VF/PF communication */ | |
2879 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
2880 | } | |
2881 | ||
477de6ed | 2882 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 2883 | { |
9a799d71 AK |
2884 | struct ixgbe_hw *hw = &adapter->hw; |
2885 | struct net_device *netdev = adapter->netdev; | |
2886 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
7c6e0a43 | 2887 | int rx_buf_len; |
477de6ed AD |
2888 | struct ixgbe_ring *rx_ring; |
2889 | int i; | |
2890 | u32 mhadd, hlreg0; | |
48654521 | 2891 | |
9a799d71 | 2892 | /* Decide whether to use packet split mode or not */ |
1cdd1ec8 GR |
2893 | /* Do not use packet split if we're in SR-IOV Mode */ |
2894 | if (!adapter->num_vfs) | |
2895 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
2896 | |
2897 | /* Set the RX buffer length according to the mode */ | |
2898 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 2899 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 | 2900 | } else { |
0c19d6af | 2901 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 2902 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 2903 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 2904 | else |
477de6ed | 2905 | rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024); |
9a799d71 AK |
2906 | } |
2907 | ||
63f39bd1 | 2908 | #ifdef IXGBE_FCOE |
477de6ed AD |
2909 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
2910 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
2911 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
2912 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 2913 | |
477de6ed AD |
2914 | #endif /* IXGBE_FCOE */ |
2915 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
2916 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
2917 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2918 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2919 | ||
2920 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2921 | } | |
2922 | ||
2923 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2924 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
2925 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
2926 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 2927 | |
0cefafad JB |
2928 | /* |
2929 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2930 | * the Base and Length of the Rx Descriptor Ring | |
2931 | */ | |
9a799d71 | 2932 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 2933 | rx_ring = adapter->rx_ring[i]; |
a6616b42 | 2934 | rx_ring->rx_buf_len = rx_buf_len; |
cc41ac7c | 2935 | |
6e455b89 YZ |
2936 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
2937 | rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED; | |
1b3ff02e PWJ |
2938 | else |
2939 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
cc41ac7c | 2940 | |
63f39bd1 | 2941 | #ifdef IXGBE_FCOE |
e8e9f696 | 2942 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
2943 | struct ixgbe_ring_feature *f; |
2944 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 YZ |
2945 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
2946 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
2947 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
2948 | rx_ring->rx_buf_len = | |
e8e9f696 | 2949 | IXGBE_FCOE_JUMBO_FRAME_SIZE; |
6e455b89 | 2950 | } |
63f39bd1 | 2951 | } |
63f39bd1 | 2952 | #endif /* IXGBE_FCOE */ |
477de6ed AD |
2953 | } |
2954 | ||
2955 | } | |
2956 | ||
7367096a AD |
2957 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
2958 | { | |
2959 | struct ixgbe_hw *hw = &adapter->hw; | |
2960 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2961 | ||
2962 | switch (hw->mac.type) { | |
2963 | case ixgbe_mac_82598EB: | |
2964 | /* | |
2965 | * For VMDq support of different descriptor types or | |
2966 | * buffer sizes through the use of multiple SRRCTL | |
2967 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2968 | * | |
2969 | * also, the manual doesn't mention it clearly but DCA hints | |
2970 | * will only use queue 0's tags unless this bit is set. Side | |
2971 | * effects of setting this bit are only that SRRCTL must be | |
2972 | * fully programmed [0..15] | |
2973 | */ | |
2974 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2975 | break; | |
2976 | case ixgbe_mac_82599EB: | |
2977 | /* Disable RSC for ACK packets */ | |
2978 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2979 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2980 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
2981 | /* hardware requires some bits to be set by default */ | |
2982 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
2983 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
2984 | break; | |
2985 | default: | |
2986 | /* We should do nothing since we don't know this hardware */ | |
2987 | return; | |
2988 | } | |
2989 | ||
2990 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2991 | } | |
2992 | ||
477de6ed AD |
2993 | /** |
2994 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
2995 | * @adapter: board private structure | |
2996 | * | |
2997 | * Configure the Rx unit of the MAC after a reset. | |
2998 | **/ | |
2999 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3000 | { | |
3001 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3002 | int i; |
3003 | u32 rxctrl; | |
477de6ed AD |
3004 | |
3005 | /* disable receives while setting up the descriptors */ | |
3006 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3007 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3008 | ||
3009 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3010 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3011 | |
9e10e045 | 3012 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3013 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3014 | |
9e10e045 AD |
3015 | ixgbe_set_uta(adapter); |
3016 | ||
477de6ed AD |
3017 | /* set_rx_buffer_len must be called before ring initialization */ |
3018 | ixgbe_set_rx_buffer_len(adapter); | |
3019 | ||
3020 | /* | |
3021 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3022 | * the Base and Length of the Rx Descriptor Ring | |
3023 | */ | |
9e10e045 AD |
3024 | for (i = 0; i < adapter->num_rx_queues; i++) |
3025 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3026 | |
9e10e045 AD |
3027 | /* disable drop enable for 82598 parts */ |
3028 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3029 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3030 | ||
3031 | /* enable all receives */ | |
3032 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3033 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3034 | } |
3035 | ||
068c89b0 DS |
3036 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
3037 | { | |
3038 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3039 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3040 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3041 | |
3042 | /* add VID to filter table */ | |
1ada1b1b | 3043 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3044 | set_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3045 | } |
3046 | ||
3047 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
3048 | { | |
3049 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3050 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3051 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3052 | |
068c89b0 | 3053 | /* remove VID from filter table */ |
1ada1b1b | 3054 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3055 | clear_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3056 | } |
3057 | ||
5f6c0181 JB |
3058 | /** |
3059 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3060 | * @adapter: driver data | |
3061 | */ | |
3062 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3063 | { | |
3064 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3065 | u32 vlnctrl; |
3066 | ||
3067 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3068 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3069 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3070 | } | |
3071 | ||
3072 | /** | |
3073 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3074 | * @adapter: driver data | |
3075 | */ | |
3076 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3077 | { | |
3078 | struct ixgbe_hw *hw = &adapter->hw; | |
3079 | u32 vlnctrl; | |
3080 | ||
3081 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3082 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3083 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3084 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3085 | } | |
3086 | ||
3087 | /** | |
3088 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3089 | * @adapter: driver data | |
3090 | */ | |
3091 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3092 | { | |
3093 | struct ixgbe_hw *hw = &adapter->hw; | |
3094 | u32 vlnctrl; | |
5f6c0181 JB |
3095 | int i, j; |
3096 | ||
3097 | switch (hw->mac.type) { | |
3098 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3099 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3100 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3101 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3102 | break; | |
3103 | case ixgbe_mac_82599EB: | |
5f6c0181 JB |
3104 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3105 | j = adapter->rx_ring[i]->reg_idx; | |
3106 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3107 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3108 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3109 | } | |
3110 | break; | |
3111 | default: | |
3112 | break; | |
3113 | } | |
3114 | } | |
3115 | ||
3116 | /** | |
f62bbb5e | 3117 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3118 | * @adapter: driver data |
3119 | */ | |
f62bbb5e | 3120 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3121 | { |
3122 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3123 | u32 vlnctrl; |
5f6c0181 JB |
3124 | int i, j; |
3125 | ||
3126 | switch (hw->mac.type) { | |
3127 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3128 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3129 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3130 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3131 | break; | |
3132 | case ixgbe_mac_82599EB: | |
5f6c0181 JB |
3133 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3134 | j = adapter->rx_ring[i]->reg_idx; | |
3135 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3136 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3137 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3138 | } | |
3139 | break; | |
3140 | default: | |
3141 | break; | |
3142 | } | |
3143 | } | |
3144 | ||
9a799d71 AK |
3145 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3146 | { | |
f62bbb5e | 3147 | u16 vid; |
9a799d71 | 3148 | |
f62bbb5e JG |
3149 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3150 | ||
3151 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3152 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3153 | } |
3154 | ||
2850062a AD |
3155 | /** |
3156 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3157 | * @netdev: network interface device structure | |
3158 | * | |
3159 | * Writes unicast address list to the RAR table. | |
3160 | * Returns: -ENOMEM on failure/insufficient address space | |
3161 | * 0 on no addresses written | |
3162 | * X on writing X addresses to the RAR table | |
3163 | **/ | |
3164 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3165 | { | |
3166 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3167 | struct ixgbe_hw *hw = &adapter->hw; | |
3168 | unsigned int vfn = adapter->num_vfs; | |
3169 | unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1); | |
3170 | int count = 0; | |
3171 | ||
3172 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3173 | if (netdev_uc_count(netdev) > rar_entries) | |
3174 | return -ENOMEM; | |
3175 | ||
3176 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3177 | struct netdev_hw_addr *ha; | |
3178 | /* return error if we do not support writing to RAR table */ | |
3179 | if (!hw->mac.ops.set_rar) | |
3180 | return -ENOMEM; | |
3181 | ||
3182 | netdev_for_each_uc_addr(ha, netdev) { | |
3183 | if (!rar_entries) | |
3184 | break; | |
3185 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3186 | vfn, IXGBE_RAH_AV); | |
3187 | count++; | |
3188 | } | |
3189 | } | |
3190 | /* write the addresses in reverse order to avoid write combining */ | |
3191 | for (; rar_entries > 0 ; rar_entries--) | |
3192 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3193 | ||
3194 | return count; | |
3195 | } | |
3196 | ||
9a799d71 | 3197 | /** |
2c5645cf | 3198 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3199 | * @netdev: network interface device structure |
3200 | * | |
2c5645cf CL |
3201 | * The set_rx_method entry point is called whenever the unicast/multicast |
3202 | * address list or the network interface flags are updated. This routine is | |
3203 | * responsible for configuring the hardware for proper unicast, multicast and | |
3204 | * promiscuous mode. | |
9a799d71 | 3205 | **/ |
7f870475 | 3206 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3207 | { |
3208 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3209 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3210 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3211 | int count; | |
9a799d71 AK |
3212 | |
3213 | /* Check for Promiscuous and All Multicast modes */ | |
3214 | ||
3215 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3216 | ||
f5dc442b AD |
3217 | /* set all bits that we expect to always be set */ |
3218 | fctrl |= IXGBE_FCTRL_BAM; | |
3219 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3220 | fctrl |= IXGBE_FCTRL_PMCF; | |
3221 | ||
2850062a AD |
3222 | /* clear the bits we are changing the status of */ |
3223 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3224 | ||
9a799d71 | 3225 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3226 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3227 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3228 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3229 | /* don't hardware filter vlans in promisc mode */ |
3230 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3231 | } else { |
746b9f02 PM |
3232 | if (netdev->flags & IFF_ALLMULTI) { |
3233 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3234 | vmolr |= IXGBE_VMOLR_MPE; |
3235 | } else { | |
3236 | /* | |
3237 | * Write addresses to the MTA, if the attempt fails | |
3238 | * then we should just turn on promiscous mode so | |
3239 | * that we can at least receive multicast traffic | |
3240 | */ | |
3241 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3242 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3243 | } |
5f6c0181 | 3244 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3245 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3246 | /* |
3247 | * Write addresses to available RAR registers, if there is not | |
3248 | * sufficient space to store all the addresses then enable | |
3249 | * unicast promiscous mode | |
3250 | */ | |
3251 | count = ixgbe_write_uc_addr_list(netdev); | |
3252 | if (count < 0) { | |
3253 | fctrl |= IXGBE_FCTRL_UPE; | |
3254 | vmolr |= IXGBE_VMOLR_ROPE; | |
3255 | } | |
9a799d71 AK |
3256 | } |
3257 | ||
2850062a | 3258 | if (adapter->num_vfs) { |
1cdd1ec8 | 3259 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3260 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3261 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3262 | IXGBE_VMOLR_ROPE); | |
3263 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3264 | } | |
3265 | ||
3266 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
f62bbb5e JG |
3267 | |
3268 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3269 | ixgbe_vlan_strip_enable(adapter); | |
3270 | else | |
3271 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3272 | } |
3273 | ||
021230d4 AV |
3274 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3275 | { | |
3276 | int q_idx; | |
3277 | struct ixgbe_q_vector *q_vector; | |
3278 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3279 | ||
3280 | /* legacy and MSI only use one vector */ | |
3281 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3282 | q_vectors = 1; | |
3283 | ||
3284 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 3285 | struct napi_struct *napi; |
7a921c93 | 3286 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 3287 | napi = &q_vector->napi; |
91281fd3 AD |
3288 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3289 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
3290 | if (q_vector->txr_count == 1) | |
3291 | napi->poll = &ixgbe_clean_txonly; | |
3292 | else if (q_vector->rxr_count == 1) | |
3293 | napi->poll = &ixgbe_clean_rxonly; | |
3294 | } | |
3295 | } | |
f0848276 JB |
3296 | |
3297 | napi_enable(napi); | |
021230d4 AV |
3298 | } |
3299 | } | |
3300 | ||
3301 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3302 | { | |
3303 | int q_idx; | |
3304 | struct ixgbe_q_vector *q_vector; | |
3305 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3306 | ||
3307 | /* legacy and MSI only use one vector */ | |
3308 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3309 | q_vectors = 1; | |
3310 | ||
3311 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3312 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3313 | napi_disable(&q_vector->napi); |
3314 | } | |
3315 | } | |
3316 | ||
7a6b6f51 | 3317 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3318 | /* |
3319 | * ixgbe_configure_dcb - Configure DCB hardware | |
3320 | * @adapter: ixgbe adapter struct | |
3321 | * | |
3322 | * This is called by the driver on open to configure the DCB hardware. | |
3323 | * This is also called by the gennetlink interface when reconfiguring | |
3324 | * the DCB state. | |
3325 | */ | |
3326 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3327 | { | |
3328 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3329 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
5f6c0181 | 3330 | u32 txdctl; |
2f90b865 AD |
3331 | int i, j; |
3332 | ||
67ebd791 AD |
3333 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3334 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3335 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3336 | return; | |
3337 | } | |
3338 | ||
3339 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3340 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3341 | ||
9806307a JF |
3342 | #ifdef CONFIG_FCOE |
3343 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) | |
3344 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
3345 | #endif | |
3346 | ||
80ab193d | 3347 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
9806307a | 3348 | DCB_TX_CONFIG); |
80ab193d | 3349 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
9806307a | 3350 | DCB_RX_CONFIG); |
2f90b865 AD |
3351 | |
3352 | /* reconfigure the hardware */ | |
3353 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
3354 | ||
3355 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3356 | j = adapter->tx_ring[i]->reg_idx; |
2f90b865 AD |
3357 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
3358 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
3359 | txdctl |= 32; | |
3360 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
3361 | } | |
3362 | /* Enable VLAN tag insert/strip */ | |
f62bbb5e | 3363 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3364 | |
2f90b865 AD |
3365 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
3366 | } | |
3367 | ||
3368 | #endif | |
9a799d71 AK |
3369 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3370 | { | |
3371 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 3372 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3373 | int i; |
3374 | ||
7a6b6f51 | 3375 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3376 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3377 | #endif |
9a799d71 | 3378 | |
f62bbb5e JG |
3379 | ixgbe_set_rx_mode(netdev); |
3380 | ixgbe_restore_vlan(adapter); | |
3381 | ||
eacd73f7 YZ |
3382 | #ifdef IXGBE_FCOE |
3383 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3384 | ixgbe_configure_fcoe(adapter); | |
3385 | ||
3386 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
3387 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
3388 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 3389 | adapter->tx_ring[i]->atr_sample_rate = |
e8e9f696 | 3390 | adapter->atr_sample_rate; |
c4cf55e5 PWJ |
3391 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); |
3392 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
3393 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
3394 | } | |
933d41f1 | 3395 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3396 | |
9a799d71 AK |
3397 | ixgbe_configure_tx(adapter); |
3398 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3399 | } |
3400 | ||
e8e26350 PW |
3401 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3402 | { | |
3403 | switch (hw->phy.type) { | |
3404 | case ixgbe_phy_sfp_avago: | |
3405 | case ixgbe_phy_sfp_ftl: | |
3406 | case ixgbe_phy_sfp_intel: | |
3407 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3408 | case ixgbe_phy_sfp_passive_tyco: |
3409 | case ixgbe_phy_sfp_passive_unknown: | |
3410 | case ixgbe_phy_sfp_active_unknown: | |
3411 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 PW |
3412 | return true; |
3413 | default: | |
3414 | return false; | |
3415 | } | |
3416 | } | |
3417 | ||
0ecc061d | 3418 | /** |
e8e26350 PW |
3419 | * ixgbe_sfp_link_config - set up SFP+ link |
3420 | * @adapter: pointer to private adapter struct | |
3421 | **/ | |
3422 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3423 | { | |
3424 | struct ixgbe_hw *hw = &adapter->hw; | |
3425 | ||
3426 | if (hw->phy.multispeed_fiber) { | |
3427 | /* | |
3428 | * In multispeed fiber setups, the device may not have | |
3429 | * had a physical connection when the driver loaded. | |
3430 | * If that's the case, the initial link configuration | |
3431 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
3432 | * never have a link status change interrupt fire. | |
3433 | * We need to try and force an autonegotiation | |
3434 | * session, then bring up link. | |
3435 | */ | |
3436 | hw->mac.ops.setup_sfp(hw); | |
3437 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
3438 | schedule_work(&adapter->multispeed_fiber_task); | |
3439 | } else { | |
3440 | /* | |
3441 | * Direct Attach Cu and non-multispeed fiber modules | |
3442 | * still need to be configured properly prior to | |
3443 | * attempting link. | |
3444 | */ | |
3445 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
3446 | schedule_work(&adapter->sfp_config_module_task); | |
3447 | } | |
3448 | } | |
3449 | ||
3450 | /** | |
3451 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3452 | * @hw: pointer to private hardware struct |
3453 | * | |
3454 | * Returns 0 on success, negative on failure | |
3455 | **/ | |
e8e26350 | 3456 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3457 | { |
3458 | u32 autoneg; | |
8620a103 | 3459 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3460 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3461 | ||
3462 | if (hw->mac.ops.check_link) | |
3463 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3464 | ||
3465 | if (ret) | |
3466 | goto link_cfg_out; | |
3467 | ||
3468 | if (hw->mac.ops.get_link_capabilities) | |
e8e9f696 JP |
3469 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3470 | &negotiation); | |
0ecc061d PWJ |
3471 | if (ret) |
3472 | goto link_cfg_out; | |
3473 | ||
8620a103 MC |
3474 | if (hw->mac.ops.setup_link) |
3475 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3476 | link_cfg_out: |
3477 | return ret; | |
3478 | } | |
3479 | ||
a34bcfff | 3480 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3481 | { |
9a799d71 | 3482 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3483 | u32 gpie = 0; |
9a799d71 | 3484 | |
9b471446 | 3485 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3486 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3487 | IXGBE_GPIE_OCD; | |
3488 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3489 | /* |
3490 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3491 | * this saves a register write for every interrupt | |
3492 | */ | |
3493 | switch (hw->mac.type) { | |
3494 | case ixgbe_mac_82598EB: | |
3495 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3496 | break; | |
3497 | default: | |
3498 | case ixgbe_mac_82599EB: | |
3499 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); | |
3500 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3501 | break; | |
3502 | } | |
3503 | } else { | |
021230d4 AV |
3504 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3505 | * specifically only auto mask tx and rx interrupts */ | |
3506 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3507 | } | |
9a799d71 | 3508 | |
a34bcfff AD |
3509 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3510 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3511 | ||
3512 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3513 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3514 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3515 | } |
3516 | ||
a34bcfff AD |
3517 | /* Enable fan failure interrupt */ |
3518 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3519 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3520 | |
a34bcfff | 3521 | if (hw->mac.type == ixgbe_mac_82599EB) |
e8e26350 PW |
3522 | gpie |= IXGBE_SDP1_GPIEN; |
3523 | gpie |= IXGBE_SDP2_GPIEN; | |
a34bcfff AD |
3524 | |
3525 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3526 | } | |
3527 | ||
3528 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
3529 | { | |
3530 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3531 | int err; |
a34bcfff AD |
3532 | u32 ctrl_ext; |
3533 | ||
3534 | ixgbe_get_hw_control(adapter); | |
3535 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3536 | |
9a799d71 AK |
3537 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3538 | ixgbe_configure_msix(adapter); | |
3539 | else | |
3540 | ixgbe_configure_msi_and_legacy(adapter); | |
3541 | ||
61fac744 PW |
3542 | /* enable the optics */ |
3543 | if (hw->phy.multispeed_fiber) | |
3544 | hw->mac.ops.enable_tx_laser(hw); | |
3545 | ||
9a799d71 | 3546 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3547 | ixgbe_napi_enable_all(adapter); |
3548 | ||
3549 | /* clear any pending interrupts, may auto mask */ | |
3550 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3551 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3552 | |
bf069c97 DS |
3553 | /* |
3554 | * If this adapter has a fan, check to see if we had a failure | |
3555 | * before we enabled the interrupt. | |
3556 | */ | |
3557 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3558 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3559 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3560 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3561 | } |
3562 | ||
e8e26350 PW |
3563 | /* |
3564 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
3565 | * arrived before interrupts were enabled but after probe. Such |
3566 | * devices wouldn't have their type identified yet. We need to | |
3567 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
3568 | * If we're not hot-pluggable SFP+, we just need to configure link |
3569 | * and bring it up. | |
3570 | */ | |
19343de2 DS |
3571 | if (hw->phy.type == ixgbe_phy_unknown) { |
3572 | err = hw->phy.ops.identify(hw); | |
3573 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
5da43c1a DS |
3574 | /* |
3575 | * Take the device down and schedule the sfp tasklet | |
3576 | * which will unregister_netdev and log it. | |
3577 | */ | |
19343de2 | 3578 | ixgbe_down(adapter); |
5da43c1a | 3579 | schedule_work(&adapter->sfp_config_module_task); |
19343de2 DS |
3580 | return err; |
3581 | } | |
e8e26350 PW |
3582 | } |
3583 | ||
3584 | if (ixgbe_is_sfp(hw)) { | |
3585 | ixgbe_sfp_link_config(adapter); | |
3586 | } else { | |
3587 | err = ixgbe_non_sfp_link_config(hw); | |
3588 | if (err) | |
396e799c | 3589 | e_err(probe, "link_config FAILED %d\n", err); |
e8e26350 | 3590 | } |
0ecc061d | 3591 | |
1da100bb | 3592 | /* enable transmits */ |
477de6ed | 3593 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3594 | |
9a799d71 AK |
3595 | /* bring the link up in the watchdog, this could race with our first |
3596 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3597 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3598 | adapter->link_check_timeout = jiffies; | |
9a799d71 | 3599 | mod_timer(&adapter->watchdog_timer, jiffies); |
c9205697 GR |
3600 | |
3601 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3602 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3603 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3604 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3605 | ||
9a799d71 AK |
3606 | return 0; |
3607 | } | |
3608 | ||
d4f80882 AV |
3609 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3610 | { | |
3611 | WARN_ON(in_interrupt()); | |
3612 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
3613 | msleep(1); | |
3614 | ixgbe_down(adapter); | |
5809a1ae GR |
3615 | /* |
3616 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3617 | * back up to give the VFs time to respond to the reset. The | |
3618 | * two second wait is based upon the watchdog timer cycle in | |
3619 | * the VF driver. | |
3620 | */ | |
3621 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3622 | msleep(2000); | |
d4f80882 AV |
3623 | ixgbe_up(adapter); |
3624 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3625 | } | |
3626 | ||
9a799d71 AK |
3627 | int ixgbe_up(struct ixgbe_adapter *adapter) |
3628 | { | |
3629 | /* hardware has been reset, we need to reload some things */ | |
3630 | ixgbe_configure(adapter); | |
3631 | ||
3632 | return ixgbe_up_complete(adapter); | |
3633 | } | |
3634 | ||
3635 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3636 | { | |
c44ade9e | 3637 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3638 | int err; |
3639 | ||
3640 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
3641 | switch (err) { |
3642 | case 0: | |
3643 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
3644 | break; | |
3645 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 3646 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 3647 | break; |
794caeb2 PWJ |
3648 | case IXGBE_ERR_EEPROM_VERSION: |
3649 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
3650 | e_dev_warn("This device is a pre-production adapter/LOM. " |
3651 | "Please be aware there may be issuesassociated with " | |
3652 | "your hardware. If you are experiencing problems " | |
3653 | "please contact your Intel or hardware " | |
3654 | "representative who provided you with this " | |
3655 | "hardware.\n"); | |
794caeb2 | 3656 | break; |
da4dd0f7 | 3657 | default: |
849c4542 | 3658 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 3659 | } |
9a799d71 AK |
3660 | |
3661 | /* reprogram the RAR[0] in case user changed it. */ | |
1cdd1ec8 GR |
3662 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3663 | IXGBE_RAH_AV); | |
9a799d71 AK |
3664 | } |
3665 | ||
9a799d71 AK |
3666 | /** |
3667 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
3668 | * @adapter: board private structure | |
3669 | * @rx_ring: ring to free buffers from | |
3670 | **/ | |
3671 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
e8e9f696 | 3672 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3673 | { |
3674 | struct pci_dev *pdev = adapter->pdev; | |
3675 | unsigned long size; | |
3676 | unsigned int i; | |
3677 | ||
84418e3b AD |
3678 | /* ring already cleared, nothing to do */ |
3679 | if (!rx_ring->rx_buffer_info) | |
3680 | return; | |
9a799d71 | 3681 | |
84418e3b | 3682 | /* Free all the Rx ring sk_buffs */ |
9a799d71 AK |
3683 | for (i = 0; i < rx_ring->count; i++) { |
3684 | struct ixgbe_rx_buffer *rx_buffer_info; | |
3685 | ||
3686 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
3687 | if (rx_buffer_info->dma) { | |
1b507730 | 3688 | dma_unmap_single(&pdev->dev, rx_buffer_info->dma, |
e8e9f696 | 3689 | rx_ring->rx_buf_len, |
1b507730 | 3690 | DMA_FROM_DEVICE); |
9a799d71 AK |
3691 | rx_buffer_info->dma = 0; |
3692 | } | |
3693 | if (rx_buffer_info->skb) { | |
f8212f97 | 3694 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 3695 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
3696 | do { |
3697 | struct sk_buff *this = skb; | |
e8171aaa | 3698 | if (IXGBE_RSC_CB(this)->delay_unmap) { |
1b507730 NN |
3699 | dma_unmap_single(&pdev->dev, |
3700 | IXGBE_RSC_CB(this)->dma, | |
e8e9f696 | 3701 | rx_ring->rx_buf_len, |
1b507730 | 3702 | DMA_FROM_DEVICE); |
fd3686a8 | 3703 | IXGBE_RSC_CB(this)->dma = 0; |
e8171aaa | 3704 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 3705 | } |
f8212f97 AD |
3706 | skb = skb->prev; |
3707 | dev_kfree_skb(this); | |
3708 | } while (skb); | |
9a799d71 AK |
3709 | } |
3710 | if (!rx_buffer_info->page) | |
3711 | continue; | |
4f57ca6e | 3712 | if (rx_buffer_info->page_dma) { |
1b507730 NN |
3713 | dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma, |
3714 | PAGE_SIZE / 2, DMA_FROM_DEVICE); | |
4f57ca6e JB |
3715 | rx_buffer_info->page_dma = 0; |
3716 | } | |
9a799d71 AK |
3717 | put_page(rx_buffer_info->page); |
3718 | rx_buffer_info->page = NULL; | |
762f4c57 | 3719 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
3720 | } |
3721 | ||
3722 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
3723 | memset(rx_ring->rx_buffer_info, 0, size); | |
3724 | ||
3725 | /* Zero out the descriptor ring */ | |
3726 | memset(rx_ring->desc, 0, rx_ring->size); | |
3727 | ||
3728 | rx_ring->next_to_clean = 0; | |
3729 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3730 | } |
3731 | ||
3732 | /** | |
3733 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
3734 | * @adapter: board private structure | |
3735 | * @tx_ring: ring to be cleaned | |
3736 | **/ | |
3737 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
e8e9f696 | 3738 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3739 | { |
3740 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3741 | unsigned long size; | |
3742 | unsigned int i; | |
3743 | ||
84418e3b AD |
3744 | /* ring already cleared, nothing to do */ |
3745 | if (!tx_ring->tx_buffer_info) | |
3746 | return; | |
9a799d71 | 3747 | |
84418e3b | 3748 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
3749 | for (i = 0; i < tx_ring->count; i++) { |
3750 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3751 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
3752 | } | |
3753 | ||
3754 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
3755 | memset(tx_ring->tx_buffer_info, 0, size); | |
3756 | ||
3757 | /* Zero out the descriptor ring */ | |
3758 | memset(tx_ring->desc, 0, tx_ring->size); | |
3759 | ||
3760 | tx_ring->next_to_use = 0; | |
3761 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
3762 | } |
3763 | ||
3764 | /** | |
021230d4 | 3765 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
3766 | * @adapter: board private structure |
3767 | **/ | |
021230d4 | 3768 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3769 | { |
3770 | int i; | |
3771 | ||
021230d4 | 3772 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 3773 | ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]); |
9a799d71 AK |
3774 | } |
3775 | ||
3776 | /** | |
021230d4 | 3777 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
3778 | * @adapter: board private structure |
3779 | **/ | |
021230d4 | 3780 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3781 | { |
3782 | int i; | |
3783 | ||
021230d4 | 3784 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3785 | ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]); |
9a799d71 AK |
3786 | } |
3787 | ||
3788 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
3789 | { | |
3790 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 3791 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 3792 | u32 rxctrl; |
7f821875 JB |
3793 | u32 txdctl; |
3794 | int i, j; | |
b25ebfd2 | 3795 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 AK |
3796 | |
3797 | /* signal that we are down to the interrupt handler */ | |
3798 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3799 | ||
767081ad GR |
3800 | /* disable receive for all VFs and wait one second */ |
3801 | if (adapter->num_vfs) { | |
767081ad GR |
3802 | /* ping all the active vfs to let them know we are going down */ |
3803 | ixgbe_ping_all_vfs(adapter); | |
581d1aa7 | 3804 | |
767081ad GR |
3805 | /* Disable all VFTE/VFRE TX/RX */ |
3806 | ixgbe_disable_tx_rx(adapter); | |
581d1aa7 GR |
3807 | |
3808 | /* Mark all the VFs as inactive */ | |
3809 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3810 | adapter->vfinfo[i].clear_to_send = 0; | |
767081ad GR |
3811 | } |
3812 | ||
9a799d71 | 3813 | /* disable receives */ |
7f821875 JB |
3814 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
3815 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 3816 | |
7f821875 | 3817 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
3818 | msleep(10); |
3819 | ||
7f821875 JB |
3820 | netif_tx_stop_all_queues(netdev); |
3821 | ||
0a1f87cb DS |
3822 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
3823 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 3824 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 3825 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 3826 | |
c0dfb90e JF |
3827 | netif_carrier_off(netdev); |
3828 | netif_tx_disable(netdev); | |
3829 | ||
3830 | ixgbe_irq_disable(adapter); | |
3831 | ||
3832 | ixgbe_napi_disable_all(adapter); | |
3833 | ||
b25ebfd2 PW |
3834 | /* Cleanup the affinity_hint CPU mask memory and callback */ |
3835 | for (i = 0; i < num_q_vectors; i++) { | |
3836 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
3837 | /* clear the affinity_mask in the IRQ descriptor */ | |
3838 | irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL); | |
3839 | /* release the CPU mask memory */ | |
3840 | free_cpumask_var(q_vector->affinity_mask); | |
3841 | } | |
3842 | ||
c4cf55e5 PWJ |
3843 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
3844 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
3845 | cancel_work_sync(&adapter->fdir_reinit_task); | |
3846 | ||
119fc60a MC |
3847 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
3848 | cancel_work_sync(&adapter->check_overtemp_task); | |
3849 | ||
7f821875 JB |
3850 | /* disable transmits in the hardware now that interrupts are off */ |
3851 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3852 | j = adapter->tx_ring[i]->reg_idx; |
7f821875 JB |
3853 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
3854 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
e8e9f696 | 3855 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); |
7f821875 | 3856 | } |
88512539 PW |
3857 | /* Disable the Tx DMA engine on 82599 */ |
3858 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3859 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
e8e9f696 JP |
3860 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
3861 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 3862 | |
9f756f01 JF |
3863 | /* power down the optics */ |
3864 | if (hw->phy.multispeed_fiber) | |
3865 | hw->mac.ops.disable_tx_laser(hw); | |
3866 | ||
9a713e7c PW |
3867 | /* clear n-tuple filters that are cached */ |
3868 | ethtool_ntuple_flush(netdev); | |
3869 | ||
6f4a0e45 PL |
3870 | if (!pci_channel_offline(adapter->pdev)) |
3871 | ixgbe_reset(adapter); | |
9a799d71 AK |
3872 | ixgbe_clean_all_tx_rings(adapter); |
3873 | ixgbe_clean_all_rx_rings(adapter); | |
3874 | ||
5dd2d332 | 3875 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 3876 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 3877 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 3878 | #endif |
9a799d71 AK |
3879 | } |
3880 | ||
9a799d71 | 3881 | /** |
021230d4 AV |
3882 | * ixgbe_poll - NAPI Rx polling callback |
3883 | * @napi: structure for representing this polling device | |
3884 | * @budget: how many packets driver is allowed to clean | |
3885 | * | |
3886 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 3887 | **/ |
021230d4 | 3888 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 3889 | { |
9a1a69ad | 3890 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 3891 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 3892 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 3893 | int tx_clean_complete, work_done = 0; |
9a799d71 | 3894 | |
5dd2d332 | 3895 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 3896 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4a0b9ca0 PW |
3897 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]); |
3898 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]); | |
bd0362dd JC |
3899 | } |
3900 | #endif | |
3901 | ||
4a0b9ca0 PW |
3902 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
3903 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 3904 | |
9a1a69ad | 3905 | if (!tx_clean_complete) |
d2c7ddd6 DM |
3906 | work_done = budget; |
3907 | ||
53e52c72 DM |
3908 | /* If budget not fully consumed, exit the polling mode */ |
3909 | if (work_done < budget) { | |
288379f0 | 3910 | napi_complete(napi); |
f7554a2b | 3911 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 3912 | ixgbe_set_itr(adapter); |
d4f80882 | 3913 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 3914 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 3915 | } |
9a799d71 AK |
3916 | return work_done; |
3917 | } | |
3918 | ||
3919 | /** | |
3920 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
3921 | * @netdev: network interface device structure | |
3922 | **/ | |
3923 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3924 | { | |
3925 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3926 | ||
3927 | /* Do the reset outside of interrupt context */ | |
3928 | schedule_work(&adapter->reset_task); | |
3929 | } | |
3930 | ||
3931 | static void ixgbe_reset_task(struct work_struct *work) | |
3932 | { | |
3933 | struct ixgbe_adapter *adapter; | |
3934 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
3935 | ||
2f90b865 AD |
3936 | /* If we're already down or resetting, just bail */ |
3937 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
3938 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
3939 | return; | |
3940 | ||
9a799d71 AK |
3941 | adapter->tx_timeout_count++; |
3942 | ||
dcd79aeb TI |
3943 | ixgbe_dump(adapter); |
3944 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
d4f80882 | 3945 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
3946 | } |
3947 | ||
bc97114d PWJ |
3948 | #ifdef CONFIG_IXGBE_DCB |
3949 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 3950 | { |
bc97114d | 3951 | bool ret = false; |
0cefafad | 3952 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 3953 | |
0cefafad JB |
3954 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
3955 | return ret; | |
3956 | ||
3957 | f->mask = 0x7 << 3; | |
3958 | adapter->num_rx_queues = f->indices; | |
3959 | adapter->num_tx_queues = f->indices; | |
3960 | ret = true; | |
2f90b865 | 3961 | |
bc97114d PWJ |
3962 | return ret; |
3963 | } | |
3964 | #endif | |
3965 | ||
4df10466 JB |
3966 | /** |
3967 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3968 | * @adapter: board private structure to initialize | |
3969 | * | |
3970 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3971 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3972 | * | |
3973 | **/ | |
bc97114d PWJ |
3974 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3975 | { | |
3976 | bool ret = false; | |
0cefafad | 3977 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3978 | |
3979 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3980 | f->mask = 0xF; |
3981 | adapter->num_rx_queues = f->indices; | |
3982 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3983 | ret = true; |
3984 | } else { | |
bc97114d | 3985 | ret = false; |
b9804972 JB |
3986 | } |
3987 | ||
bc97114d PWJ |
3988 | return ret; |
3989 | } | |
3990 | ||
c4cf55e5 PWJ |
3991 | /** |
3992 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3993 | * @adapter: board private structure to initialize | |
3994 | * | |
3995 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3996 | * to the original CPU that initiated the Tx session. This runs in addition | |
3997 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3998 | * Rx load across CPUs using RSS. | |
3999 | * | |
4000 | **/ | |
e8e9f696 | 4001 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4002 | { |
4003 | bool ret = false; | |
4004 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4005 | ||
4006 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
4007 | f_fdir->mask = 0; | |
4008 | ||
4009 | /* Flow Director must have RSS enabled */ | |
4010 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4011 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
4012 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
4013 | adapter->num_tx_queues = f_fdir->indices; | |
4014 | adapter->num_rx_queues = f_fdir->indices; | |
4015 | ret = true; | |
4016 | } else { | |
4017 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4018 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4019 | } | |
4020 | return ret; | |
4021 | } | |
4022 | ||
0331a832 YZ |
4023 | #ifdef IXGBE_FCOE |
4024 | /** | |
4025 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4026 | * @adapter: board private structure to initialize | |
4027 | * | |
4028 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4029 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4030 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4031 | * index of the first rx queue used by FCoE. | |
4032 | * | |
4033 | **/ | |
4034 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4035 | { | |
4036 | bool ret = false; | |
4037 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
4038 | ||
4039 | f->indices = min((int)num_online_cpus(), f->indices); | |
4040 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
8de8b2e6 YZ |
4041 | adapter->num_rx_queues = 1; |
4042 | adapter->num_tx_queues = 1; | |
0331a832 YZ |
4043 | #ifdef CONFIG_IXGBE_DCB |
4044 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
396e799c | 4045 | e_info(probe, "FCoE enabled with DCB\n"); |
0331a832 YZ |
4046 | ixgbe_set_dcb_queues(adapter); |
4047 | } | |
4048 | #endif | |
4049 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
396e799c | 4050 | e_info(probe, "FCoE enabled with RSS\n"); |
8faa2a78 YZ |
4051 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
4052 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4053 | ixgbe_set_fdir_queues(adapter); | |
4054 | else | |
4055 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
4056 | } |
4057 | /* adding FCoE rx rings to the end */ | |
4058 | f->mask = adapter->num_rx_queues; | |
4059 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 4060 | adapter->num_tx_queues += f->indices; |
0331a832 YZ |
4061 | |
4062 | ret = true; | |
4063 | } | |
4064 | ||
4065 | return ret; | |
4066 | } | |
4067 | ||
4068 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4069 | /** |
4070 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4071 | * @adapter: board private structure to initialize | |
4072 | * | |
4073 | * IOV doesn't actually use anything, so just NAK the | |
4074 | * request for now and let the other queue routines | |
4075 | * figure out what to do. | |
4076 | */ | |
4077 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4078 | { | |
4079 | return false; | |
4080 | } | |
4081 | ||
4df10466 JB |
4082 | /* |
4083 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
4084 | * @adapter: board private structure to initialize | |
4085 | * | |
4086 | * This is the top level queue allocation routine. The order here is very | |
4087 | * important, starting with the "most" number of features turned on at once, | |
4088 | * and ending with the smallest set of features. This way large combinations | |
4089 | * can be allocated if they're turned on, and smaller combinations are the | |
4090 | * fallthrough conditions. | |
4091 | * | |
4092 | **/ | |
847f53ff | 4093 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4094 | { |
1cdd1ec8 GR |
4095 | /* Start with base case */ |
4096 | adapter->num_rx_queues = 1; | |
4097 | adapter->num_tx_queues = 1; | |
4098 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4099 | adapter->num_rx_queues_per_pool = 1; | |
4100 | ||
4101 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4102 | goto done; |
1cdd1ec8 | 4103 | |
0331a832 YZ |
4104 | #ifdef IXGBE_FCOE |
4105 | if (ixgbe_set_fcoe_queues(adapter)) | |
4106 | goto done; | |
4107 | ||
4108 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
4109 | #ifdef CONFIG_IXGBE_DCB |
4110 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4111 | goto done; |
bc97114d PWJ |
4112 | |
4113 | #endif | |
c4cf55e5 PWJ |
4114 | if (ixgbe_set_fdir_queues(adapter)) |
4115 | goto done; | |
4116 | ||
bc97114d | 4117 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4118 | goto done; |
4119 | ||
4120 | /* fallback to base case */ | |
4121 | adapter->num_rx_queues = 1; | |
4122 | adapter->num_tx_queues = 1; | |
4123 | ||
4124 | done: | |
847f53ff | 4125 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4126 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4127 | return netif_set_real_num_rx_queues(adapter->netdev, |
4128 | adapter->num_rx_queues); | |
b9804972 JB |
4129 | } |
4130 | ||
021230d4 | 4131 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4132 | int vectors) |
021230d4 AV |
4133 | { |
4134 | int err, vector_threshold; | |
4135 | ||
4136 | /* We'll want at least 3 (vector_threshold): | |
4137 | * 1) TxQ[0] Cleanup | |
4138 | * 2) RxQ[0] Cleanup | |
4139 | * 3) Other (Link Status Change, etc.) | |
4140 | * 4) TCP Timer (optional) | |
4141 | */ | |
4142 | vector_threshold = MIN_MSIX_COUNT; | |
4143 | ||
4144 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
4145 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
4146 | * Right now, we simply care about how many we'll get; we'll | |
4147 | * set them up later while requesting irq's. | |
4148 | */ | |
4149 | while (vectors >= vector_threshold) { | |
4150 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4151 | vectors); |
021230d4 AV |
4152 | if (!err) /* Success in acquiring all requested vectors. */ |
4153 | break; | |
4154 | else if (err < 0) | |
4155 | vectors = 0; /* Nasty failure, quit now */ | |
4156 | else /* err == number of vectors we should try again with */ | |
4157 | vectors = err; | |
4158 | } | |
4159 | ||
4160 | if (vectors < vector_threshold) { | |
4161 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4162 | * This just means we'll go with either a single MSI | |
4163 | * vector or fall back to legacy interrupts. | |
4164 | */ | |
849c4542 ET |
4165 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4166 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4167 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4168 | kfree(adapter->msix_entries); | |
4169 | adapter->msix_entries = NULL; | |
021230d4 AV |
4170 | } else { |
4171 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4172 | /* |
4173 | * Adjust for only the vectors we'll use, which is minimum | |
4174 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4175 | * vectors we were allocated. | |
4176 | */ | |
4177 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4178 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4179 | } |
4180 | } | |
4181 | ||
021230d4 | 4182 | /** |
bc97114d | 4183 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4184 | * @adapter: board private structure to initialize |
4185 | * | |
bc97114d PWJ |
4186 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4187 | * | |
021230d4 | 4188 | **/ |
bc97114d | 4189 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4190 | { |
bc97114d PWJ |
4191 | int i; |
4192 | bool ret = false; | |
4193 | ||
4194 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
4195 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4196 | adapter->rx_ring[i]->reg_idx = i; |
bc97114d | 4197 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4198 | adapter->tx_ring[i]->reg_idx = i; |
bc97114d PWJ |
4199 | ret = true; |
4200 | } else { | |
4201 | ret = false; | |
4202 | } | |
4203 | ||
4204 | return ret; | |
4205 | } | |
4206 | ||
4207 | #ifdef CONFIG_IXGBE_DCB | |
4208 | /** | |
4209 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4210 | * @adapter: board private structure to initialize | |
4211 | * | |
4212 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4213 | * | |
4214 | **/ | |
4215 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4216 | { | |
4217 | int i; | |
4218 | bool ret = false; | |
4219 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
4220 | ||
4221 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4222 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
4223 | /* the number of queues is assumed to be symmetric */ |
4224 | for (i = 0; i < dcb_i; i++) { | |
4a0b9ca0 PW |
4225 | adapter->rx_ring[i]->reg_idx = i << 3; |
4226 | adapter->tx_ring[i]->reg_idx = i << 2; | |
2f90b865 | 4227 | } |
bc97114d | 4228 | ret = true; |
e8e26350 | 4229 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
4230 | if (dcb_i == 8) { |
4231 | /* | |
4232 | * Tx TC0 starts at: descriptor queue 0 | |
4233 | * Tx TC1 starts at: descriptor queue 32 | |
4234 | * Tx TC2 starts at: descriptor queue 64 | |
4235 | * Tx TC3 starts at: descriptor queue 80 | |
4236 | * Tx TC4 starts at: descriptor queue 96 | |
4237 | * Tx TC5 starts at: descriptor queue 104 | |
4238 | * Tx TC6 starts at: descriptor queue 112 | |
4239 | * Tx TC7 starts at: descriptor queue 120 | |
4240 | * | |
4241 | * Rx TC0-TC7 are offset by 16 queues each | |
4242 | */ | |
4243 | for (i = 0; i < 3; i++) { | |
4a0b9ca0 PW |
4244 | adapter->tx_ring[i]->reg_idx = i << 5; |
4245 | adapter->rx_ring[i]->reg_idx = i << 4; | |
f92ef202 PW |
4246 | } |
4247 | for ( ; i < 5; i++) { | |
4a0b9ca0 | 4248 | adapter->tx_ring[i]->reg_idx = |
e8e9f696 | 4249 | ((i + 2) << 4); |
4a0b9ca0 | 4250 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
4251 | } |
4252 | for ( ; i < dcb_i; i++) { | |
4a0b9ca0 | 4253 | adapter->tx_ring[i]->reg_idx = |
e8e9f696 | 4254 | ((i + 8) << 3); |
4a0b9ca0 | 4255 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
4256 | } |
4257 | ||
4258 | ret = true; | |
4259 | } else if (dcb_i == 4) { | |
4260 | /* | |
4261 | * Tx TC0 starts at: descriptor queue 0 | |
4262 | * Tx TC1 starts at: descriptor queue 64 | |
4263 | * Tx TC2 starts at: descriptor queue 96 | |
4264 | * Tx TC3 starts at: descriptor queue 112 | |
4265 | * | |
4266 | * Rx TC0-TC3 are offset by 32 queues each | |
4267 | */ | |
4a0b9ca0 PW |
4268 | adapter->tx_ring[0]->reg_idx = 0; |
4269 | adapter->tx_ring[1]->reg_idx = 64; | |
4270 | adapter->tx_ring[2]->reg_idx = 96; | |
4271 | adapter->tx_ring[3]->reg_idx = 112; | |
f92ef202 | 4272 | for (i = 0 ; i < dcb_i; i++) |
4a0b9ca0 | 4273 | adapter->rx_ring[i]->reg_idx = i << 5; |
f92ef202 PW |
4274 | |
4275 | ret = true; | |
4276 | } else { | |
4277 | ret = false; | |
e8e26350 | 4278 | } |
bc97114d PWJ |
4279 | } else { |
4280 | ret = false; | |
021230d4 | 4281 | } |
bc97114d PWJ |
4282 | } else { |
4283 | ret = false; | |
021230d4 | 4284 | } |
bc97114d PWJ |
4285 | |
4286 | return ret; | |
4287 | } | |
4288 | #endif | |
4289 | ||
c4cf55e5 PWJ |
4290 | /** |
4291 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4292 | * @adapter: board private structure to initialize | |
4293 | * | |
4294 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4295 | * | |
4296 | **/ | |
e8e9f696 | 4297 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4298 | { |
4299 | int i; | |
4300 | bool ret = false; | |
4301 | ||
4302 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4303 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4304 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
4305 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4306 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4307 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4308 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4309 | ret = true; |
4310 | } | |
4311 | ||
4312 | return ret; | |
4313 | } | |
4314 | ||
0331a832 YZ |
4315 | #ifdef IXGBE_FCOE |
4316 | /** | |
4317 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4318 | * @adapter: board private structure to initialize | |
4319 | * | |
4320 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4321 | * | |
4322 | */ | |
4323 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4324 | { | |
8de8b2e6 | 4325 | int i, fcoe_rx_i = 0, fcoe_tx_i = 0; |
0331a832 YZ |
4326 | bool ret = false; |
4327 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
4328 | ||
4329 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
4330 | #ifdef CONFIG_IXGBE_DCB | |
4331 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 YZ |
4332 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
4333 | ||
0331a832 | 4334 | ixgbe_cache_ring_dcb(adapter); |
8de8b2e6 | 4335 | /* find out queues in TC for FCoE */ |
4a0b9ca0 PW |
4336 | fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1; |
4337 | fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1; | |
8de8b2e6 YZ |
4338 | /* |
4339 | * In 82599, the number of Tx queues for each traffic | |
4340 | * class for both 8-TC and 4-TC modes are: | |
4341 | * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 | |
4342 | * 8 TCs: 32 32 16 16 8 8 8 8 | |
4343 | * 4 TCs: 64 64 32 32 | |
4344 | * We have max 8 queues for FCoE, where 8 the is | |
4345 | * FCoE redirection table size. If TC for FCoE is | |
4346 | * less than or equal to TC3, we have enough queues | |
4347 | * to add max of 8 queues for FCoE, so we start FCoE | |
4348 | * tx descriptor from the next one, i.e., reg_idx + 1. | |
4349 | * If TC for FCoE is above TC3, implying 8 TC mode, | |
4350 | * and we need 8 for FCoE, we have to take all queues | |
4351 | * in that traffic class for FCoE. | |
4352 | */ | |
4353 | if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3)) | |
4354 | fcoe_tx_i--; | |
0331a832 YZ |
4355 | } |
4356 | #endif /* CONFIG_IXGBE_DCB */ | |
4357 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8faa2a78 YZ |
4358 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
4359 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4360 | ixgbe_cache_ring_fdir(adapter); | |
4361 | else | |
4362 | ixgbe_cache_ring_rss(adapter); | |
4363 | ||
8de8b2e6 YZ |
4364 | fcoe_rx_i = f->mask; |
4365 | fcoe_tx_i = f->mask; | |
4366 | } | |
4367 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { | |
4a0b9ca0 PW |
4368 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; |
4369 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
0331a832 | 4370 | } |
0331a832 YZ |
4371 | ret = true; |
4372 | } | |
4373 | return ret; | |
4374 | } | |
4375 | ||
4376 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4377 | /** |
4378 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4379 | * @adapter: board private structure to initialize | |
4380 | * | |
4381 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4382 | * no other mapping is used. | |
4383 | * | |
4384 | */ | |
4385 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4386 | { | |
4a0b9ca0 PW |
4387 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4388 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4389 | if (adapter->num_vfs) |
4390 | return true; | |
4391 | else | |
4392 | return false; | |
4393 | } | |
4394 | ||
bc97114d PWJ |
4395 | /** |
4396 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4397 | * @adapter: board private structure to initialize | |
4398 | * | |
4399 | * Once we know the feature-set enabled for the device, we'll cache | |
4400 | * the register offset the descriptor ring is assigned to. | |
4401 | * | |
4402 | * Note, the order the various feature calls is important. It must start with | |
4403 | * the "most" features enabled at the same time, then trickle down to the | |
4404 | * least amount of features turned on at once. | |
4405 | **/ | |
4406 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4407 | { | |
4408 | /* start with default case */ | |
4a0b9ca0 PW |
4409 | adapter->rx_ring[0]->reg_idx = 0; |
4410 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4411 | |
1cdd1ec8 GR |
4412 | if (ixgbe_cache_ring_sriov(adapter)) |
4413 | return; | |
4414 | ||
0331a832 YZ |
4415 | #ifdef IXGBE_FCOE |
4416 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4417 | return; | |
4418 | ||
4419 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
4420 | #ifdef CONFIG_IXGBE_DCB |
4421 | if (ixgbe_cache_ring_dcb(adapter)) | |
4422 | return; | |
4423 | ||
4424 | #endif | |
c4cf55e5 PWJ |
4425 | if (ixgbe_cache_ring_fdir(adapter)) |
4426 | return; | |
4427 | ||
bc97114d PWJ |
4428 | if (ixgbe_cache_ring_rss(adapter)) |
4429 | return; | |
021230d4 AV |
4430 | } |
4431 | ||
9a799d71 AK |
4432 | /** |
4433 | * ixgbe_alloc_queues - Allocate memory for all rings | |
4434 | * @adapter: board private structure to initialize | |
4435 | * | |
4436 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
4437 | * number of queues at compile-time. The polling_netdev array is |
4438 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 4439 | **/ |
2f90b865 | 4440 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4441 | { |
4442 | int i; | |
4a0b9ca0 | 4443 | int orig_node = adapter->node; |
9a799d71 | 4444 | |
021230d4 | 4445 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
4446 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
4447 | if (orig_node == -1) { | |
4448 | int cur_node = next_online_node(adapter->node); | |
4449 | if (cur_node == MAX_NUMNODES) | |
4450 | cur_node = first_online_node; | |
4451 | adapter->node = cur_node; | |
4452 | } | |
4453 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
e8e9f696 | 4454 | adapter->node); |
4a0b9ca0 PW |
4455 | if (!ring) |
4456 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
4457 | if (!ring) | |
4458 | goto err_tx_ring_allocation; | |
4459 | ring->count = adapter->tx_ring_count; | |
4460 | ring->queue_index = i; | |
4461 | ring->numa_node = adapter->node; | |
4462 | ||
4463 | adapter->tx_ring[i] = ring; | |
021230d4 | 4464 | } |
b9804972 | 4465 | |
4a0b9ca0 PW |
4466 | /* Restore the adapter's original node */ |
4467 | adapter->node = orig_node; | |
4468 | ||
9a799d71 | 4469 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
4470 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4471 | if (orig_node == -1) { | |
4472 | int cur_node = next_online_node(adapter->node); | |
4473 | if (cur_node == MAX_NUMNODES) | |
4474 | cur_node = first_online_node; | |
4475 | adapter->node = cur_node; | |
4476 | } | |
4477 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
e8e9f696 | 4478 | adapter->node); |
4a0b9ca0 PW |
4479 | if (!ring) |
4480 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
4481 | if (!ring) | |
4482 | goto err_rx_ring_allocation; | |
4483 | ring->count = adapter->rx_ring_count; | |
4484 | ring->queue_index = i; | |
4485 | ring->numa_node = adapter->node; | |
4486 | ||
4487 | adapter->rx_ring[i] = ring; | |
021230d4 AV |
4488 | } |
4489 | ||
4a0b9ca0 PW |
4490 | /* Restore the adapter's original node */ |
4491 | adapter->node = orig_node; | |
4492 | ||
021230d4 AV |
4493 | ixgbe_cache_ring_register(adapter); |
4494 | ||
4495 | return 0; | |
4496 | ||
4497 | err_rx_ring_allocation: | |
4a0b9ca0 PW |
4498 | for (i = 0; i < adapter->num_tx_queues; i++) |
4499 | kfree(adapter->tx_ring[i]); | |
021230d4 AV |
4500 | err_tx_ring_allocation: |
4501 | return -ENOMEM; | |
4502 | } | |
4503 | ||
4504 | /** | |
4505 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4506 | * @adapter: board private structure to initialize | |
4507 | * | |
4508 | * Attempt to configure the interrupts using the best available | |
4509 | * capabilities of the hardware and the kernel. | |
4510 | **/ | |
feea6a57 | 4511 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4512 | { |
8be0e467 | 4513 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4514 | int err = 0; |
4515 | int vector, v_budget; | |
4516 | ||
4517 | /* | |
4518 | * It's easy to be greedy for MSI-X vectors, but it really | |
4519 | * doesn't do us much good if we have a lot more vectors | |
4520 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4521 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
4522 | */ |
4523 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
e8e9f696 | 4524 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
4525 | |
4526 | /* | |
4527 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4528 | * hw.mac->max_msix_vectors vectors. With features |
4529 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4530 | * descriptor queues supported by our device. Thus, we cap it off in | |
4531 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4532 | */ |
8be0e467 | 4533 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
4534 | |
4535 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4536 | * mean we disable MSI-X capabilities of the adapter. */ | |
4537 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4538 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4539 | if (adapter->msix_entries) { |
4540 | for (vector = 0; vector < v_budget; vector++) | |
4541 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4542 | |
7a921c93 | 4543 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4544 | |
7a921c93 AD |
4545 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4546 | goto out; | |
4547 | } | |
26d27844 | 4548 | |
7a921c93 AD |
4549 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4550 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
4551 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
4552 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4553 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
4554 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4555 | ixgbe_disable_sriov(adapter); | |
4556 | ||
847f53ff BH |
4557 | err = ixgbe_set_num_queues(adapter); |
4558 | if (err) | |
4559 | return err; | |
021230d4 | 4560 | |
021230d4 AV |
4561 | err = pci_enable_msi(adapter->pdev); |
4562 | if (!err) { | |
4563 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4564 | } else { | |
849c4542 ET |
4565 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4566 | "Unable to allocate MSI interrupt, " | |
4567 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
4568 | /* reset err */ |
4569 | err = 0; | |
4570 | } | |
4571 | ||
4572 | out: | |
021230d4 AV |
4573 | return err; |
4574 | } | |
4575 | ||
7a921c93 AD |
4576 | /** |
4577 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4578 | * @adapter: board private structure to initialize | |
4579 | * | |
4580 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4581 | * return -ENOMEM. | |
4582 | **/ | |
4583 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4584 | { | |
4585 | int q_idx, num_q_vectors; | |
4586 | struct ixgbe_q_vector *q_vector; | |
4587 | int napi_vectors; | |
4588 | int (*poll)(struct napi_struct *, int); | |
4589 | ||
4590 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4591 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
4592 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 4593 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
4594 | } else { |
4595 | num_q_vectors = 1; | |
4596 | napi_vectors = 1; | |
4597 | poll = &ixgbe_poll; | |
4598 | } | |
4599 | ||
4600 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 | 4601 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
e8e9f696 | 4602 | GFP_KERNEL, adapter->node); |
1a6c14a2 JB |
4603 | if (!q_vector) |
4604 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
e8e9f696 | 4605 | GFP_KERNEL); |
7a921c93 AD |
4606 | if (!q_vector) |
4607 | goto err_out; | |
4608 | q_vector->adapter = adapter; | |
f7554a2b NS |
4609 | if (q_vector->txr_count && !q_vector->rxr_count) |
4610 | q_vector->eitr = adapter->tx_eitr_param; | |
4611 | else | |
4612 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 4613 | q_vector->v_idx = q_idx; |
91281fd3 | 4614 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
4615 | adapter->q_vector[q_idx] = q_vector; |
4616 | } | |
4617 | ||
4618 | return 0; | |
4619 | ||
4620 | err_out: | |
4621 | while (q_idx) { | |
4622 | q_idx--; | |
4623 | q_vector = adapter->q_vector[q_idx]; | |
4624 | netif_napi_del(&q_vector->napi); | |
4625 | kfree(q_vector); | |
4626 | adapter->q_vector[q_idx] = NULL; | |
4627 | } | |
4628 | return -ENOMEM; | |
4629 | } | |
4630 | ||
4631 | /** | |
4632 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
4633 | * @adapter: board private structure to initialize | |
4634 | * | |
4635 | * This function frees the memory allocated to the q_vectors. In addition if | |
4636 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4637 | * to freeing the q_vector. | |
4638 | **/ | |
4639 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
4640 | { | |
4641 | int q_idx, num_q_vectors; | |
7a921c93 | 4642 | |
91281fd3 | 4643 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4644 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 4645 | else |
7a921c93 | 4646 | num_q_vectors = 1; |
7a921c93 AD |
4647 | |
4648 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
4649 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 4650 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 4651 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
4652 | kfree(q_vector); |
4653 | } | |
4654 | } | |
4655 | ||
7b25cdba | 4656 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
4657 | { |
4658 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4659 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4660 | pci_disable_msix(adapter->pdev); | |
4661 | kfree(adapter->msix_entries); | |
4662 | adapter->msix_entries = NULL; | |
4663 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
4664 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
4665 | pci_disable_msi(adapter->pdev); | |
4666 | } | |
021230d4 AV |
4667 | } |
4668 | ||
4669 | /** | |
4670 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
4671 | * @adapter: board private structure to initialize | |
4672 | * | |
4673 | * We determine which interrupt scheme to use based on... | |
4674 | * - Kernel support (MSI, MSI-X) | |
4675 | * - which can be user-defined (via MODULE_PARAM) | |
4676 | * - Hardware queue count (num_*_queues) | |
4677 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
4678 | **/ | |
2f90b865 | 4679 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
4680 | { |
4681 | int err; | |
4682 | ||
4683 | /* Number of supported queues */ | |
847f53ff BH |
4684 | err = ixgbe_set_num_queues(adapter); |
4685 | if (err) | |
4686 | return err; | |
021230d4 | 4687 | |
021230d4 AV |
4688 | err = ixgbe_set_interrupt_capability(adapter); |
4689 | if (err) { | |
849c4542 | 4690 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 4691 | goto err_set_interrupt; |
9a799d71 AK |
4692 | } |
4693 | ||
7a921c93 AD |
4694 | err = ixgbe_alloc_q_vectors(adapter); |
4695 | if (err) { | |
849c4542 | 4696 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
4697 | goto err_alloc_q_vectors; |
4698 | } | |
4699 | ||
4700 | err = ixgbe_alloc_queues(adapter); | |
4701 | if (err) { | |
849c4542 | 4702 | e_dev_err("Unable to allocate memory for queues\n"); |
7a921c93 AD |
4703 | goto err_alloc_queues; |
4704 | } | |
4705 | ||
849c4542 | 4706 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
4707 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
4708 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
4709 | |
4710 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4711 | ||
9a799d71 | 4712 | return 0; |
021230d4 | 4713 | |
7a921c93 AD |
4714 | err_alloc_queues: |
4715 | ixgbe_free_q_vectors(adapter); | |
4716 | err_alloc_q_vectors: | |
4717 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 4718 | err_set_interrupt: |
7a921c93 AD |
4719 | return err; |
4720 | } | |
4721 | ||
1a51502b ED |
4722 | static void ring_free_rcu(struct rcu_head *head) |
4723 | { | |
4724 | kfree(container_of(head, struct ixgbe_ring, rcu)); | |
4725 | } | |
4726 | ||
7a921c93 AD |
4727 | /** |
4728 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4729 | * @adapter: board private structure to clear interrupt scheme on | |
4730 | * | |
4731 | * We go through and clear interrupt specific resources and reset the structure | |
4732 | * to pre-load conditions | |
4733 | **/ | |
4734 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
4735 | { | |
4a0b9ca0 PW |
4736 | int i; |
4737 | ||
4738 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4739 | kfree(adapter->tx_ring[i]); | |
4740 | adapter->tx_ring[i] = NULL; | |
4741 | } | |
4742 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1a51502b ED |
4743 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4744 | ||
4745 | /* ixgbe_get_stats64() might access this ring, we must wait | |
4746 | * a grace period before freeing it. | |
4747 | */ | |
4748 | call_rcu(&ring->rcu, ring_free_rcu); | |
4a0b9ca0 PW |
4749 | adapter->rx_ring[i] = NULL; |
4750 | } | |
7a921c93 AD |
4751 | |
4752 | ixgbe_free_q_vectors(adapter); | |
4753 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
4754 | } |
4755 | ||
c4900be0 DS |
4756 | /** |
4757 | * ixgbe_sfp_timer - worker thread to find a missing module | |
4758 | * @data: pointer to our adapter struct | |
4759 | **/ | |
4760 | static void ixgbe_sfp_timer(unsigned long data) | |
4761 | { | |
4762 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
4763 | ||
4df10466 JB |
4764 | /* |
4765 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
4766 | * delays that sfp+ detection requires |
4767 | */ | |
4768 | schedule_work(&adapter->sfp_task); | |
4769 | } | |
4770 | ||
4771 | /** | |
4772 | * ixgbe_sfp_task - worker thread to find a missing module | |
4773 | * @work: pointer to work_struct containing our data | |
4774 | **/ | |
4775 | static void ixgbe_sfp_task(struct work_struct *work) | |
4776 | { | |
4777 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
4778 | struct ixgbe_adapter, |
4779 | sfp_task); | |
c4900be0 DS |
4780 | struct ixgbe_hw *hw = &adapter->hw; |
4781 | ||
4782 | if ((hw->phy.type == ixgbe_phy_nl) && | |
4783 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
4784 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 4785 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
4786 | goto reschedule; |
4787 | ret = hw->phy.ops.reset(hw); | |
4788 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
849c4542 ET |
4789 | e_dev_err("failed to initialize because an unsupported " |
4790 | "SFP+ module type was detected.\n"); | |
4791 | e_dev_err("Reload the driver after installing a " | |
4792 | "supported module.\n"); | |
c4900be0 DS |
4793 | unregister_netdev(adapter->netdev); |
4794 | } else { | |
396e799c | 4795 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); |
c4900be0 DS |
4796 | } |
4797 | /* don't need this routine any more */ | |
4798 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4799 | } | |
4800 | return; | |
4801 | reschedule: | |
4802 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
4803 | mod_timer(&adapter->sfp_timer, | |
e8e9f696 | 4804 | round_jiffies(jiffies + (2 * HZ))); |
c4900be0 DS |
4805 | } |
4806 | ||
9a799d71 AK |
4807 | /** |
4808 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4809 | * @adapter: board private structure to initialize | |
4810 | * | |
4811 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4812 | * Fields are initialized based on PCI device information and | |
4813 | * OS network device settings (MTU size). | |
4814 | **/ | |
4815 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4816 | { | |
4817 | struct ixgbe_hw *hw = &adapter->hw; | |
4818 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 4819 | struct net_device *dev = adapter->netdev; |
021230d4 | 4820 | unsigned int rss; |
7a6b6f51 | 4821 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4822 | int j; |
4823 | struct tc_configuration *tc; | |
4824 | #endif | |
16b61beb | 4825 | int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 4826 | |
c44ade9e JB |
4827 | /* PCI config space info */ |
4828 | ||
4829 | hw->vendor_id = pdev->vendor; | |
4830 | hw->device_id = pdev->device; | |
4831 | hw->revision_id = pdev->revision; | |
4832 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4833 | hw->subsystem_device_id = pdev->subsystem_device; | |
4834 | ||
021230d4 AV |
4835 | /* Set capability flags */ |
4836 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
4837 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
4838 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 4839 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
4840 | if (hw->mac.type == ixgbe_mac_82598EB) { |
4841 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
4842 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4843 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 4844 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 4845 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4846 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4847 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4848 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4849 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
9a713e7c PW |
4850 | if (dev->features & NETIF_F_NTUPLE) { |
4851 | /* Flow Director perfect filter enabled */ | |
4852 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4853 | adapter->atr_sample_rate = 0; | |
4854 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4855 | } else { | |
4856 | /* Flow Director hash filters enabled */ | |
4857 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4858 | adapter->atr_sample_rate = 20; | |
4859 | } | |
c4cf55e5 | 4860 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 4861 | IXGBE_MAX_FDIR_INDICES; |
c4cf55e5 | 4862 | adapter->fdir_pballoc = 0; |
eacd73f7 | 4863 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4864 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4865 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4866 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4867 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
4868 | /* Default traffic class to use for FCoE */ |
4869 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
56075a98 | 4870 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4871 | #endif |
eacd73f7 | 4872 | #endif /* IXGBE_FCOE */ |
f8212f97 | 4873 | } |
2f90b865 | 4874 | |
7a6b6f51 | 4875 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4876 | /* Configure DCB traffic classes */ |
4877 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4878 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4879 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4880 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4881 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4882 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4883 | tc->dcb_pfc = pfc_disabled; | |
4884 | } | |
4885 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
4886 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
4887 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 4888 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
4889 | adapter->dcb_cfg.round_robin_enable = false; |
4890 | adapter->dcb_set_bitmap = 0x00; | |
4891 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
e8e9f696 | 4892 | adapter->ring_feature[RING_F_DCB].indices); |
2f90b865 AD |
4893 | |
4894 | #endif | |
9a799d71 AK |
4895 | |
4896 | /* default flow control settings */ | |
cd7664f6 | 4897 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4898 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4899 | #ifdef CONFIG_DCB |
4900 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4901 | #endif | |
16b61beb JF |
4902 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
4903 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
2b9ade93 JB |
4904 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4905 | hw->fc.send_xon = true; | |
71fd570b | 4906 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4907 | |
30efa5a3 | 4908 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
4909 | adapter->rx_itr_setting = 1; |
4910 | adapter->rx_eitr_param = 20000; | |
4911 | adapter->tx_itr_setting = 1; | |
4912 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
4913 | |
4914 | /* set defaults for eitr in MegaBytes */ | |
4915 | adapter->eitr_low = 10; | |
4916 | adapter->eitr_high = 20; | |
4917 | ||
4918 | /* set default ring sizes */ | |
4919 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4920 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4921 | ||
9a799d71 | 4922 | /* initialize eeprom parameters */ |
c44ade9e | 4923 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4924 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4925 | return -EIO; |
4926 | } | |
4927 | ||
021230d4 | 4928 | /* enable rx csum by default */ |
9a799d71 AK |
4929 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
4930 | ||
1a6c14a2 JB |
4931 | /* get assigned NUMA node */ |
4932 | adapter->node = dev_to_node(&pdev->dev); | |
4933 | ||
9a799d71 AK |
4934 | set_bit(__IXGBE_DOWN, &adapter->state); |
4935 | ||
4936 | return 0; | |
4937 | } | |
4938 | ||
4939 | /** | |
4940 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
4941 | * @adapter: board private structure | |
3a581073 | 4942 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4943 | * |
4944 | * Return 0 on success, negative on failure | |
4945 | **/ | |
4946 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e8e9f696 | 4947 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4948 | { |
4949 | struct pci_dev *pdev = adapter->pdev; | |
4950 | int size; | |
4951 | ||
3a581073 | 4952 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4a0b9ca0 | 4953 | tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node); |
1a6c14a2 JB |
4954 | if (!tx_ring->tx_buffer_info) |
4955 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
4956 | if (!tx_ring->tx_buffer_info) |
4957 | goto err; | |
3a581073 | 4958 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
4959 | |
4960 | /* round up to nearest 4K */ | |
12207e49 | 4961 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4962 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4963 | |
1b507730 NN |
4964 | tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, |
4965 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4966 | if (!tx_ring->desc) |
4967 | goto err; | |
9a799d71 | 4968 | |
3a581073 JB |
4969 | tx_ring->next_to_use = 0; |
4970 | tx_ring->next_to_clean = 0; | |
4971 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 4972 | return 0; |
e01c31a5 JB |
4973 | |
4974 | err: | |
4975 | vfree(tx_ring->tx_buffer_info); | |
4976 | tx_ring->tx_buffer_info = NULL; | |
396e799c | 4977 | e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4978 | return -ENOMEM; |
9a799d71 AK |
4979 | } |
4980 | ||
69888674 AD |
4981 | /** |
4982 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4983 | * @adapter: board private structure | |
4984 | * | |
4985 | * If this function returns with an error, then it's possible one or | |
4986 | * more of the rings is populated (while the rest are not). It is the | |
4987 | * callers duty to clean those orphaned rings. | |
4988 | * | |
4989 | * Return 0 on success, negative on failure | |
4990 | **/ | |
4991 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4992 | { | |
4993 | int i, err = 0; | |
4994 | ||
4995 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 4996 | err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]); |
69888674 AD |
4997 | if (!err) |
4998 | continue; | |
396e799c | 4999 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
5000 | break; |
5001 | } | |
5002 | ||
5003 | return err; | |
5004 | } | |
5005 | ||
9a799d71 AK |
5006 | /** |
5007 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
5008 | * @adapter: board private structure | |
3a581073 | 5009 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5010 | * |
5011 | * Returns 0 on success, negative on failure | |
5012 | **/ | |
5013 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
e8e9f696 | 5014 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
5015 | { |
5016 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 5017 | int size; |
9a799d71 | 5018 | |
3a581073 | 5019 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
1a6c14a2 JB |
5020 | rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node); |
5021 | if (!rx_ring->rx_buffer_info) | |
5022 | rx_ring->rx_buffer_info = vmalloc(size); | |
3a581073 | 5023 | if (!rx_ring->rx_buffer_info) { |
396e799c ET |
5024 | e_err(probe, "vmalloc allocation failed for the Rx " |
5025 | "descriptor ring\n"); | |
177db6ff | 5026 | goto alloc_failed; |
9a799d71 | 5027 | } |
3a581073 | 5028 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 5029 | |
9a799d71 | 5030 | /* Round up to nearest 4K */ |
3a581073 JB |
5031 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5032 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5033 | |
1b507730 NN |
5034 | rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, |
5035 | &rx_ring->dma, GFP_KERNEL); | |
9a799d71 | 5036 | |
3a581073 | 5037 | if (!rx_ring->desc) { |
396e799c ET |
5038 | e_err(probe, "Memory allocation failed for the Rx " |
5039 | "descriptor ring\n"); | |
3a581073 | 5040 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 5041 | goto alloc_failed; |
9a799d71 AK |
5042 | } |
5043 | ||
3a581073 JB |
5044 | rx_ring->next_to_clean = 0; |
5045 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5046 | |
5047 | return 0; | |
177db6ff MC |
5048 | |
5049 | alloc_failed: | |
177db6ff | 5050 | return -ENOMEM; |
9a799d71 AK |
5051 | } |
5052 | ||
69888674 AD |
5053 | /** |
5054 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5055 | * @adapter: board private structure | |
5056 | * | |
5057 | * If this function returns with an error, then it's possible one or | |
5058 | * more of the rings is populated (while the rest are not). It is the | |
5059 | * callers duty to clean those orphaned rings. | |
5060 | * | |
5061 | * Return 0 on success, negative on failure | |
5062 | **/ | |
5063 | ||
5064 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
5065 | { | |
5066 | int i, err = 0; | |
5067 | ||
5068 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 | 5069 | err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); |
69888674 AD |
5070 | if (!err) |
5071 | continue; | |
396e799c | 5072 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5073 | break; |
5074 | } | |
5075 | ||
5076 | return err; | |
5077 | } | |
5078 | ||
9a799d71 AK |
5079 | /** |
5080 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
5081 | * @adapter: board private structure | |
5082 | * @tx_ring: Tx descriptor ring for a specific queue | |
5083 | * | |
5084 | * Free all transmit software resources | |
5085 | **/ | |
c431f97e | 5086 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
e8e9f696 | 5087 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
5088 | { |
5089 | struct pci_dev *pdev = adapter->pdev; | |
5090 | ||
5091 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
5092 | ||
5093 | vfree(tx_ring->tx_buffer_info); | |
5094 | tx_ring->tx_buffer_info = NULL; | |
5095 | ||
1b507730 NN |
5096 | dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, |
5097 | tx_ring->dma); | |
9a799d71 AK |
5098 | |
5099 | tx_ring->desc = NULL; | |
5100 | } | |
5101 | ||
5102 | /** | |
5103 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5104 | * @adapter: board private structure | |
5105 | * | |
5106 | * Free all transmit software resources | |
5107 | **/ | |
5108 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5109 | { | |
5110 | int i; | |
5111 | ||
5112 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 PW |
5113 | if (adapter->tx_ring[i]->desc) |
5114 | ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
5115 | } |
5116 | ||
5117 | /** | |
b4617240 | 5118 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5119 | * @adapter: board private structure |
5120 | * @rx_ring: ring to clean the resources from | |
5121 | * | |
5122 | * Free all receive software resources | |
5123 | **/ | |
c431f97e | 5124 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
e8e9f696 | 5125 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
5126 | { |
5127 | struct pci_dev *pdev = adapter->pdev; | |
5128 | ||
5129 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
5130 | ||
5131 | vfree(rx_ring->rx_buffer_info); | |
5132 | rx_ring->rx_buffer_info = NULL; | |
5133 | ||
1b507730 NN |
5134 | dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, |
5135 | rx_ring->dma); | |
9a799d71 AK |
5136 | |
5137 | rx_ring->desc = NULL; | |
5138 | } | |
5139 | ||
5140 | /** | |
5141 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5142 | * @adapter: board private structure | |
5143 | * | |
5144 | * Free all receive software resources | |
5145 | **/ | |
5146 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5147 | { | |
5148 | int i; | |
5149 | ||
5150 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
5151 | if (adapter->rx_ring[i]->desc) |
5152 | ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]); | |
9a799d71 AK |
5153 | } |
5154 | ||
9a799d71 AK |
5155 | /** |
5156 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5157 | * @netdev: network interface device structure | |
5158 | * @new_mtu: new value for maximum frame size | |
5159 | * | |
5160 | * Returns 0 on success, negative on failure | |
5161 | **/ | |
5162 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5163 | { | |
5164 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
16b61beb | 5165 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5166 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
5167 | ||
42c783c5 JB |
5168 | /* MTU < 68 is an error and causes problems on some kernels */ |
5169 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
5170 | return -EINVAL; |
5171 | ||
396e799c | 5172 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
021230d4 | 5173 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5174 | netdev->mtu = new_mtu; |
5175 | ||
16b61beb JF |
5176 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5177 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
5178 | ||
d4f80882 AV |
5179 | if (netif_running(netdev)) |
5180 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5181 | |
5182 | return 0; | |
5183 | } | |
5184 | ||
5185 | /** | |
5186 | * ixgbe_open - Called when a network interface is made active | |
5187 | * @netdev: network interface device structure | |
5188 | * | |
5189 | * Returns 0 on success, negative value on failure | |
5190 | * | |
5191 | * The open entry point is called when a network interface is made | |
5192 | * active by the system (IFF_UP). At this point all resources needed | |
5193 | * for transmit and receive operations are allocated, the interrupt | |
5194 | * handler is registered with the OS, the watchdog timer is started, | |
5195 | * and the stack is notified that the interface is ready. | |
5196 | **/ | |
5197 | static int ixgbe_open(struct net_device *netdev) | |
5198 | { | |
5199 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5200 | int err; | |
4bebfaa5 AK |
5201 | |
5202 | /* disallow open during test */ | |
5203 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5204 | return -EBUSY; | |
9a799d71 | 5205 | |
54386467 JB |
5206 | netif_carrier_off(netdev); |
5207 | ||
9a799d71 AK |
5208 | /* allocate transmit descriptors */ |
5209 | err = ixgbe_setup_all_tx_resources(adapter); | |
5210 | if (err) | |
5211 | goto err_setup_tx; | |
5212 | ||
9a799d71 AK |
5213 | /* allocate receive descriptors */ |
5214 | err = ixgbe_setup_all_rx_resources(adapter); | |
5215 | if (err) | |
5216 | goto err_setup_rx; | |
5217 | ||
5218 | ixgbe_configure(adapter); | |
5219 | ||
021230d4 | 5220 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5221 | if (err) |
5222 | goto err_req_irq; | |
5223 | ||
9a799d71 AK |
5224 | err = ixgbe_up_complete(adapter); |
5225 | if (err) | |
5226 | goto err_up; | |
5227 | ||
d55b53ff JK |
5228 | netif_tx_start_all_queues(netdev); |
5229 | ||
9a799d71 AK |
5230 | return 0; |
5231 | ||
5232 | err_up: | |
5eba3699 | 5233 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5234 | ixgbe_free_irq(adapter); |
5235 | err_req_irq: | |
9a799d71 | 5236 | err_setup_rx: |
a20a1199 | 5237 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5238 | err_setup_tx: |
a20a1199 | 5239 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5240 | ixgbe_reset(adapter); |
5241 | ||
5242 | return err; | |
5243 | } | |
5244 | ||
5245 | /** | |
5246 | * ixgbe_close - Disables a network interface | |
5247 | * @netdev: network interface device structure | |
5248 | * | |
5249 | * Returns 0, this is not allowed to fail | |
5250 | * | |
5251 | * The close entry point is called when an interface is de-activated | |
5252 | * by the OS. The hardware is still under the drivers control, but | |
5253 | * needs to be disabled. A global MAC reset is issued to stop the | |
5254 | * hardware, and all transmit and receive resources are freed. | |
5255 | **/ | |
5256 | static int ixgbe_close(struct net_device *netdev) | |
5257 | { | |
5258 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5259 | |
5260 | ixgbe_down(adapter); | |
5261 | ixgbe_free_irq(adapter); | |
5262 | ||
5263 | ixgbe_free_all_tx_resources(adapter); | |
5264 | ixgbe_free_all_rx_resources(adapter); | |
5265 | ||
5eba3699 | 5266 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5267 | |
5268 | return 0; | |
5269 | } | |
5270 | ||
b3c8b4ba AD |
5271 | #ifdef CONFIG_PM |
5272 | static int ixgbe_resume(struct pci_dev *pdev) | |
5273 | { | |
5274 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5275 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5276 | u32 err; | |
5277 | ||
5278 | pci_set_power_state(pdev, PCI_D0); | |
5279 | pci_restore_state(pdev); | |
656ab817 DS |
5280 | /* |
5281 | * pci_restore_state clears dev->state_saved so call | |
5282 | * pci_save_state to restore it. | |
5283 | */ | |
5284 | pci_save_state(pdev); | |
9ce77666 | 5285 | |
5286 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5287 | if (err) { |
849c4542 | 5288 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5289 | return err; |
5290 | } | |
5291 | pci_set_master(pdev); | |
5292 | ||
dd4d8ca6 | 5293 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5294 | |
5295 | err = ixgbe_init_interrupt_scheme(adapter); | |
5296 | if (err) { | |
849c4542 | 5297 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5298 | return err; |
5299 | } | |
5300 | ||
b3c8b4ba AD |
5301 | ixgbe_reset(adapter); |
5302 | ||
495dce12 WJP |
5303 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5304 | ||
b3c8b4ba AD |
5305 | if (netif_running(netdev)) { |
5306 | err = ixgbe_open(adapter->netdev); | |
5307 | if (err) | |
5308 | return err; | |
5309 | } | |
5310 | ||
5311 | netif_device_attach(netdev); | |
5312 | ||
5313 | return 0; | |
5314 | } | |
b3c8b4ba | 5315 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5316 | |
5317 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
5318 | { |
5319 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5320 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
5321 | struct ixgbe_hw *hw = &adapter->hw; |
5322 | u32 ctrl, fctrl; | |
5323 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5324 | #ifdef CONFIG_PM |
5325 | int retval = 0; | |
5326 | #endif | |
5327 | ||
5328 | netif_device_detach(netdev); | |
5329 | ||
5330 | if (netif_running(netdev)) { | |
5331 | ixgbe_down(adapter); | |
5332 | ixgbe_free_irq(adapter); | |
5333 | ixgbe_free_all_tx_resources(adapter); | |
5334 | ixgbe_free_all_rx_resources(adapter); | |
5335 | } | |
b3c8b4ba AD |
5336 | |
5337 | #ifdef CONFIG_PM | |
5338 | retval = pci_save_state(pdev); | |
5339 | if (retval) | |
5340 | return retval; | |
4df10466 | 5341 | |
b3c8b4ba | 5342 | #endif |
e8e26350 PW |
5343 | if (wufc) { |
5344 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5345 | |
e8e26350 PW |
5346 | /* turn on all-multi mode if wake on multicast is enabled */ |
5347 | if (wufc & IXGBE_WUFC_MC) { | |
5348 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5349 | fctrl |= IXGBE_FCTRL_MPE; | |
5350 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5351 | } | |
5352 | ||
5353 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5354 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5355 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5356 | ||
5357 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5358 | } else { | |
5359 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5360 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5361 | } | |
5362 | ||
dd4d8ca6 DS |
5363 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
5364 | pci_wake_from_d3(pdev, true); | |
5365 | else | |
5366 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 5367 | |
9d8d05ae RW |
5368 | *enable_wake = !!wufc; |
5369 | ||
fa378134 AG |
5370 | ixgbe_clear_interrupt_scheme(adapter); |
5371 | ||
b3c8b4ba AD |
5372 | ixgbe_release_hw_control(adapter); |
5373 | ||
5374 | pci_disable_device(pdev); | |
5375 | ||
9d8d05ae RW |
5376 | return 0; |
5377 | } | |
5378 | ||
5379 | #ifdef CONFIG_PM | |
5380 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5381 | { | |
5382 | int retval; | |
5383 | bool wake; | |
5384 | ||
5385 | retval = __ixgbe_shutdown(pdev, &wake); | |
5386 | if (retval) | |
5387 | return retval; | |
5388 | ||
5389 | if (wake) { | |
5390 | pci_prepare_to_sleep(pdev); | |
5391 | } else { | |
5392 | pci_wake_from_d3(pdev, false); | |
5393 | pci_set_power_state(pdev, PCI_D3hot); | |
5394 | } | |
b3c8b4ba AD |
5395 | |
5396 | return 0; | |
5397 | } | |
9d8d05ae | 5398 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5399 | |
5400 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5401 | { | |
9d8d05ae RW |
5402 | bool wake; |
5403 | ||
5404 | __ixgbe_shutdown(pdev, &wake); | |
5405 | ||
5406 | if (system_state == SYSTEM_POWER_OFF) { | |
5407 | pci_wake_from_d3(pdev, wake); | |
5408 | pci_set_power_state(pdev, PCI_D3hot); | |
5409 | } | |
b3c8b4ba AD |
5410 | } |
5411 | ||
9a799d71 AK |
5412 | /** |
5413 | * ixgbe_update_stats - Update the board statistics counters. | |
5414 | * @adapter: board private structure | |
5415 | **/ | |
5416 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5417 | { | |
2d86f139 | 5418 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5419 | struct ixgbe_hw *hw = &adapter->hw; |
6f11eef7 AV |
5420 | u64 total_mpc = 0; |
5421 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
eb985f09 | 5422 | u64 non_eop_descs = 0, restart_queue = 0; |
7ca647bd | 5423 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
9a799d71 | 5424 | |
d08935c2 DS |
5425 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5426 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5427 | return; | |
5428 | ||
94b982b2 | 5429 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5430 | u64 rsc_count = 0; |
94b982b2 | 5431 | u64 rsc_flush = 0; |
d51019a4 PW |
5432 | for (i = 0; i < 16; i++) |
5433 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5434 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5435 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
5436 | rsc_count += adapter->rx_ring[i]->rsc_count; |
5437 | rsc_flush += adapter->rx_ring[i]->rsc_flush; | |
94b982b2 MC |
5438 | } |
5439 | adapter->rsc_total_count = rsc_count; | |
5440 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5441 | } |
5442 | ||
7ca3bc58 JB |
5443 | /* gather some stats to the adapter struct that are per queue */ |
5444 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5445 | restart_queue += adapter->tx_ring[i]->restart_queue; |
eb985f09 | 5446 | adapter->restart_queue = restart_queue; |
7ca3bc58 JB |
5447 | |
5448 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5449 | non_eop_descs += adapter->rx_ring[i]->non_eop_descs; |
eb985f09 | 5450 | adapter->non_eop_descs = non_eop_descs; |
7ca3bc58 | 5451 | |
7ca647bd | 5452 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
5453 | for (i = 0; i < 8; i++) { |
5454 | /* for packet buffers not used, the register should read 0 */ | |
5455 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5456 | missed_rx += mpc; | |
7ca647bd JP |
5457 | hwstats->mpc[i] += mpc; |
5458 | total_mpc += hwstats->mpc[i]; | |
e8e26350 | 5459 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5460 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5461 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5462 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5463 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5464 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 | 5465 | if (hw->mac.type == ixgbe_mac_82599EB) { |
7ca647bd JP |
5466 | hwstats->pxonrxc[i] += |
5467 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
5468 | hwstats->pxoffrxc[i] += | |
5469 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
5470 | hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 | 5471 | } else { |
7ca647bd JP |
5472 | hwstats->pxonrxc[i] += |
5473 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
5474 | hwstats->pxoffrxc[i] += | |
5475 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
e8e26350 | 5476 | } |
7ca647bd JP |
5477 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5478 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
6f11eef7 | 5479 | } |
7ca647bd | 5480 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5481 | /* work around hardware counting issue */ |
7ca647bd | 5482 | hwstats->gprc -= missed_rx; |
6f11eef7 AV |
5483 | |
5484 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 | 5485 | if (hw->mac.type == ixgbe_mac_82599EB) { |
aad71918 | 5486 | u64 tmp; |
7ca647bd | 5487 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
e8e9f696 JP |
5488 | tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; |
5489 | /* 4 high bits of GORC */ | |
7ca647bd JP |
5490 | hwstats->gorc += (tmp << 32); |
5491 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
e8e9f696 JP |
5492 | tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; |
5493 | /* 4 high bits of GOTC */ | |
7ca647bd JP |
5494 | hwstats->gotc += (tmp << 32); |
5495 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
e8e9f696 | 5496 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd JP |
5497 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
5498 | hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
5499 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); | |
5500 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5501 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5502 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5503 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5504 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5505 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5506 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5507 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
6d45522c | 5508 | #endif /* IXGBE_FCOE */ |
e8e26350 | 5509 | } else { |
7ca647bd JP |
5510 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); |
5511 | hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
5512 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
5513 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5514 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
e8e26350 | 5515 | } |
9a799d71 | 5516 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5517 | hwstats->bprc += bprc; |
5518 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5519 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5520 | hwstats->mprc -= bprc; |
5521 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5522 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5523 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5524 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5525 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5526 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5527 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5528 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5529 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5530 | hwstats->lxontxc += lxon; |
6f11eef7 | 5531 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd JP |
5532 | hwstats->lxofftxc += lxoff; |
5533 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5534 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
5535 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5536 | /* |
5537 | * 82598 errata - tx of flow control packets is included in tx counters | |
5538 | */ | |
5539 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5540 | hwstats->gptc -= xon_off_tot; |
5541 | hwstats->mptc -= xon_off_tot; | |
5542 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5543 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5544 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5545 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5546 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5547 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5548 | hwstats->ptc64 -= xon_off_tot; | |
5549 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5550 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5551 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5552 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5553 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5554 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5555 | |
5556 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5557 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5558 | |
5559 | /* Rx Errors */ | |
7ca647bd | 5560 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5561 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5562 | netdev->stats.rx_length_errors = hwstats->rlec; |
5563 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5564 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5565 | } |
5566 | ||
5567 | /** | |
5568 | * ixgbe_watchdog - Timer Call-back | |
5569 | * @data: pointer to adapter cast into an unsigned long | |
5570 | **/ | |
5571 | static void ixgbe_watchdog(unsigned long data) | |
5572 | { | |
5573 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 5574 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5575 | u64 eics = 0; |
5576 | int i; | |
cf8280ee | 5577 | |
fe49f04a AD |
5578 | /* |
5579 | * Do the watchdog outside of interrupt context due to the lovely | |
5580 | * delays that some of the newer hardware requires | |
5581 | */ | |
22d5a71b | 5582 | |
fe49f04a AD |
5583 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
5584 | goto watchdog_short_circuit; | |
22d5a71b | 5585 | |
fe49f04a AD |
5586 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5587 | /* | |
5588 | * for legacy and MSI interrupts don't set any bits | |
5589 | * that are enabled for EIAM, because this operation | |
5590 | * would set *both* EIMS and EICS for any bit in EIAM | |
5591 | */ | |
5592 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5593 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
5594 | goto watchdog_reschedule; | |
5595 | } | |
5596 | ||
5597 | /* get one bit for every active tx/rx interrupt vector */ | |
5598 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5599 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
5600 | if (qv->rxr_count || qv->txr_count) | |
5601 | eics |= ((u64)1 << i); | |
cf8280ee | 5602 | } |
9a799d71 | 5603 | |
fe49f04a AD |
5604 | /* Cause software interrupt to ensure rx rings are cleaned */ |
5605 | ixgbe_irq_rearm_queues(adapter, eics); | |
5606 | ||
5607 | watchdog_reschedule: | |
5608 | /* Reset the timer */ | |
5609 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
5610 | ||
5611 | watchdog_short_circuit: | |
cf8280ee JB |
5612 | schedule_work(&adapter->watchdog_task); |
5613 | } | |
5614 | ||
e8e26350 PW |
5615 | /** |
5616 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
5617 | * @work: pointer to work_struct containing our data | |
5618 | **/ | |
5619 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
5620 | { | |
5621 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5622 | struct ixgbe_adapter, |
5623 | multispeed_fiber_task); | |
e8e26350 PW |
5624 | struct ixgbe_hw *hw = &adapter->hw; |
5625 | u32 autoneg; | |
8620a103 | 5626 | bool negotiation; |
e8e26350 PW |
5627 | |
5628 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
5629 | autoneg = hw->phy.autoneg_advertised; |
5630 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 | 5631 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
1097cd17 | 5632 | hw->mac.autotry_restart = false; |
8620a103 MC |
5633 | if (hw->mac.ops.setup_link) |
5634 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
5635 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5636 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
5637 | } | |
5638 | ||
5639 | /** | |
5640 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
5641 | * @work: pointer to work_struct containing our data | |
5642 | **/ | |
5643 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
5644 | { | |
5645 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5646 | struct ixgbe_adapter, |
5647 | sfp_config_module_task); | |
e8e26350 PW |
5648 | struct ixgbe_hw *hw = &adapter->hw; |
5649 | u32 err; | |
5650 | ||
5651 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
5652 | |
5653 | /* Time for electrical oscillations to settle down */ | |
5654 | msleep(100); | |
e8e26350 | 5655 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 5656 | |
e8e26350 | 5657 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
849c4542 ET |
5658 | e_dev_err("failed to initialize because an unsupported SFP+ " |
5659 | "module type was detected.\n"); | |
5660 | e_dev_err("Reload the driver after installing a supported " | |
5661 | "module.\n"); | |
63d6e1d8 | 5662 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
5663 | return; |
5664 | } | |
5665 | hw->mac.ops.setup_sfp(hw); | |
5666 | ||
8d1c3c07 | 5667 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
5668 | /* This will also work for DA Twinax connections */ |
5669 | schedule_work(&adapter->multispeed_fiber_task); | |
5670 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
5671 | } | |
5672 | ||
c4cf55e5 PWJ |
5673 | /** |
5674 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
5675 | * @work: pointer to work_struct containing our data | |
5676 | **/ | |
5677 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
5678 | { | |
5679 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5680 | struct ixgbe_adapter, |
5681 | fdir_reinit_task); | |
c4cf55e5 PWJ |
5682 | struct ixgbe_hw *hw = &adapter->hw; |
5683 | int i; | |
5684 | ||
5685 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
5686 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5687 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
e8e9f696 | 5688 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 | 5689 | } else { |
396e799c | 5690 | e_err(probe, "failed to finish FDIR re-initialization, " |
849c4542 | 5691 | "ignored adding FDIR ATR filters\n"); |
c4cf55e5 PWJ |
5692 | } |
5693 | /* Done FDIR Re-initialization, enable transmits */ | |
5694 | netif_tx_start_all_queues(adapter->netdev); | |
5695 | } | |
5696 | ||
10eec955 JF |
5697 | static DEFINE_MUTEX(ixgbe_watchdog_lock); |
5698 | ||
cf8280ee | 5699 | /** |
69888674 AD |
5700 | * ixgbe_watchdog_task - worker thread to bring link up |
5701 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
5702 | **/ |
5703 | static void ixgbe_watchdog_task(struct work_struct *work) | |
5704 | { | |
5705 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5706 | struct ixgbe_adapter, |
5707 | watchdog_task); | |
cf8280ee JB |
5708 | struct net_device *netdev = adapter->netdev; |
5709 | struct ixgbe_hw *hw = &adapter->hw; | |
10eec955 JF |
5710 | u32 link_speed; |
5711 | bool link_up; | |
bc59fcda NS |
5712 | int i; |
5713 | struct ixgbe_ring *tx_ring; | |
5714 | int some_tx_pending = 0; | |
cf8280ee | 5715 | |
10eec955 JF |
5716 | mutex_lock(&ixgbe_watchdog_lock); |
5717 | ||
5718 | link_up = adapter->link_up; | |
5719 | link_speed = adapter->link_speed; | |
cf8280ee JB |
5720 | |
5721 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
5722 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
5723 | if (link_up) { |
5724 | #ifdef CONFIG_DCB | |
5725 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5726 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 5727 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 5728 | } else { |
620fa036 | 5729 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5730 | } |
5731 | #else | |
620fa036 | 5732 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5733 | #endif |
5734 | } | |
5735 | ||
cf8280ee JB |
5736 | if (link_up || |
5737 | time_after(jiffies, (adapter->link_check_timeout + | |
e8e9f696 | 5738 | IXGBE_TRY_LINK_TIMEOUT))) { |
cf8280ee | 5739 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 5740 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
5741 | } |
5742 | adapter->link_up = link_up; | |
5743 | adapter->link_speed = link_speed; | |
5744 | } | |
9a799d71 AK |
5745 | |
5746 | if (link_up) { | |
5747 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
5748 | bool flow_rx, flow_tx; |
5749 | ||
5750 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
5751 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5752 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
078788b6 PWJ |
5753 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); |
5754 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
e8e26350 PW |
5755 | } else { |
5756 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5757 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
5758 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
5759 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 PW |
5760 | } |
5761 | ||
396e799c | 5762 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
a46e534b | 5763 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? |
849c4542 ET |
5764 | "10 Gbps" : |
5765 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5766 | "1 Gbps" : "unknown speed")), | |
e8e26350 | 5767 | ((flow_rx && flow_tx) ? "RX/TX" : |
849c4542 ET |
5768 | (flow_rx ? "RX" : |
5769 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
5770 | |
5771 | netif_carrier_on(netdev); | |
9a799d71 AK |
5772 | } else { |
5773 | /* Force detection of hung controller */ | |
5774 | adapter->detect_tx_hung = true; | |
5775 | } | |
5776 | } else { | |
cf8280ee JB |
5777 | adapter->link_up = false; |
5778 | adapter->link_speed = 0; | |
9a799d71 | 5779 | if (netif_carrier_ok(netdev)) { |
396e799c | 5780 | e_info(drv, "NIC Link is Down\n"); |
9a799d71 | 5781 | netif_carrier_off(netdev); |
9a799d71 AK |
5782 | } |
5783 | } | |
5784 | ||
bc59fcda NS |
5785 | if (!netif_carrier_ok(netdev)) { |
5786 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 5787 | tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5788 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5789 | some_tx_pending = 1; | |
5790 | break; | |
5791 | } | |
5792 | } | |
5793 | ||
5794 | if (some_tx_pending) { | |
5795 | /* We've lost link, so the controller stops DMA, | |
5796 | * but we've got queued Tx work that's never going | |
5797 | * to get done, so reset controller to flush Tx. | |
5798 | * (Do the reset outside of interrupt context). | |
5799 | */ | |
5800 | schedule_work(&adapter->reset_task); | |
5801 | } | |
5802 | } | |
5803 | ||
9a799d71 | 5804 | ixgbe_update_stats(adapter); |
10eec955 | 5805 | mutex_unlock(&ixgbe_watchdog_lock); |
9a799d71 AK |
5806 | } |
5807 | ||
9a799d71 | 5808 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
e8e9f696 | 5809 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5e09a105 | 5810 | u32 tx_flags, u8 *hdr_len, __be16 protocol) |
9a799d71 AK |
5811 | { |
5812 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5813 | unsigned int i; | |
5814 | int err; | |
5815 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
5816 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
5817 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
5818 | |
5819 | if (skb_is_gso(skb)) { | |
5820 | if (skb_header_cloned(skb)) { | |
5821 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
5822 | if (err) | |
5823 | return err; | |
5824 | } | |
5825 | l4len = tcp_hdrlen(skb); | |
5826 | *hdr_len += l4len; | |
5827 | ||
5e09a105 | 5828 | if (protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
5829 | struct iphdr *iph = ip_hdr(skb); |
5830 | iph->tot_len = 0; | |
5831 | iph->check = 0; | |
5832 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
e8e9f696 JP |
5833 | iph->daddr, 0, |
5834 | IPPROTO_TCP, | |
5835 | 0); | |
8e1e8a47 | 5836 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
5837 | ipv6_hdr(skb)->payload_len = 0; |
5838 | tcp_hdr(skb)->check = | |
5839 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
e8e9f696 JP |
5840 | &ipv6_hdr(skb)->daddr, |
5841 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
5842 | } |
5843 | ||
5844 | i = tx_ring->next_to_use; | |
5845 | ||
5846 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 5847 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
5848 | |
5849 | /* VLAN MACLEN IPLEN */ | |
5850 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5851 | vlan_macip_lens |= | |
5852 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5853 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
e8e9f696 | 5854 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5855 | *hdr_len += skb_network_offset(skb); |
5856 | vlan_macip_lens |= | |
5857 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5858 | *hdr_len += | |
5859 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5860 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5861 | context_desc->seqnum_seed = 0; | |
5862 | ||
5863 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 5864 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
e8e9f696 | 5865 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 5866 | |
5e09a105 | 5867 | if (protocol == htons(ETH_P_IP)) |
9a799d71 AK |
5868 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
5869 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5870 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
5871 | ||
5872 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 5873 | mss_l4len_idx = |
9a799d71 AK |
5874 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
5875 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
5876 | /* use index 1 for TSO */ |
5877 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5878 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
5879 | ||
5880 | tx_buffer_info->time_stamp = jiffies; | |
5881 | tx_buffer_info->next_to_watch = i; | |
5882 | ||
5883 | i++; | |
5884 | if (i == tx_ring->count) | |
5885 | i = 0; | |
5886 | tx_ring->next_to_use = i; | |
5887 | ||
5888 | return true; | |
5889 | } | |
5890 | return false; | |
5891 | } | |
5892 | ||
5e09a105 HZ |
5893 | static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
5894 | __be16 protocol) | |
7ca647bd JP |
5895 | { |
5896 | u32 rtn = 0; | |
7ca647bd JP |
5897 | |
5898 | switch (protocol) { | |
5899 | case cpu_to_be16(ETH_P_IP): | |
5900 | rtn |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5901 | switch (ip_hdr(skb)->protocol) { | |
5902 | case IPPROTO_TCP: | |
5903 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5904 | break; | |
5905 | case IPPROTO_SCTP: | |
5906 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
5907 | break; | |
5908 | } | |
5909 | break; | |
5910 | case cpu_to_be16(ETH_P_IPV6): | |
5911 | /* XXX what about other V6 headers?? */ | |
5912 | switch (ipv6_hdr(skb)->nexthdr) { | |
5913 | case IPPROTO_TCP: | |
5914 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5915 | break; | |
5916 | case IPPROTO_SCTP: | |
5917 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
5918 | break; | |
5919 | } | |
5920 | break; | |
5921 | default: | |
5922 | if (unlikely(net_ratelimit())) | |
5923 | e_warn(probe, "partial checksum but proto=%x!\n", | |
5e09a105 | 5924 | protocol); |
7ca647bd JP |
5925 | break; |
5926 | } | |
5927 | ||
5928 | return rtn; | |
5929 | } | |
5930 | ||
9a799d71 | 5931 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, |
e8e9f696 | 5932 | struct ixgbe_ring *tx_ring, |
5e09a105 HZ |
5933 | struct sk_buff *skb, u32 tx_flags, |
5934 | __be16 protocol) | |
9a799d71 AK |
5935 | { |
5936 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5937 | unsigned int i; | |
5938 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5939 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
5940 | ||
5941 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
5942 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
5943 | i = tx_ring->next_to_use; | |
5944 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 5945 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
5946 | |
5947 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5948 | vlan_macip_lens |= | |
5949 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5950 | vlan_macip_lens |= (skb_network_offset(skb) << | |
e8e9f696 | 5951 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5952 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5953 | vlan_macip_lens |= (skb_transport_header(skb) - | |
e8e9f696 | 5954 | skb_network_header(skb)); |
9a799d71 AK |
5955 | |
5956 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5957 | context_desc->seqnum_seed = 0; | |
5958 | ||
5959 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
e8e9f696 | 5960 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 5961 | |
7ca647bd | 5962 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5e09a105 | 5963 | type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol); |
9a799d71 AK |
5964 | |
5965 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 5966 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
5967 | context_desc->mss_l4len_idx = 0; |
5968 | ||
5969 | tx_buffer_info->time_stamp = jiffies; | |
5970 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 5971 | |
9a799d71 AK |
5972 | i++; |
5973 | if (i == tx_ring->count) | |
5974 | i = 0; | |
5975 | tx_ring->next_to_use = i; | |
5976 | ||
5977 | return true; | |
5978 | } | |
9f8cdf4f | 5979 | |
9a799d71 AK |
5980 | return false; |
5981 | } | |
5982 | ||
5983 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
5984 | struct ixgbe_ring *tx_ring, |
5985 | struct sk_buff *skb, u32 tx_flags, | |
8ad494b0 | 5986 | unsigned int first, const u8 hdr_len) |
9a799d71 | 5987 | { |
e5a43549 | 5988 | struct pci_dev *pdev = adapter->pdev; |
9a799d71 | 5989 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
5990 | unsigned int len; |
5991 | unsigned int total = skb->len; | |
9a799d71 AK |
5992 | unsigned int offset = 0, size, count = 0, i; |
5993 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
5994 | unsigned int f; | |
8ad494b0 AD |
5995 | unsigned int bytecount = skb->len; |
5996 | u16 gso_segs = 1; | |
9a799d71 AK |
5997 | |
5998 | i = tx_ring->next_to_use; | |
5999 | ||
eacd73f7 YZ |
6000 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
6001 | /* excluding fcoe_crc_eof for FCoE */ | |
6002 | total -= sizeof(struct fcoe_crc_eof); | |
6003 | ||
6004 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
6005 | while (len) { |
6006 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
6007 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6008 | ||
6009 | tx_buffer_info->length = size; | |
e5a43549 | 6010 | tx_buffer_info->mapped_as_page = false; |
1b507730 | 6011 | tx_buffer_info->dma = dma_map_single(&pdev->dev, |
e5a43549 | 6012 | skb->data + offset, |
1b507730 NN |
6013 | size, DMA_TO_DEVICE); |
6014 | if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma)) | |
e5a43549 | 6015 | goto dma_error; |
9a799d71 AK |
6016 | tx_buffer_info->time_stamp = jiffies; |
6017 | tx_buffer_info->next_to_watch = i; | |
6018 | ||
6019 | len -= size; | |
eacd73f7 | 6020 | total -= size; |
9a799d71 AK |
6021 | offset += size; |
6022 | count++; | |
44df32c5 AD |
6023 | |
6024 | if (len) { | |
6025 | i++; | |
6026 | if (i == tx_ring->count) | |
6027 | i = 0; | |
6028 | } | |
9a799d71 AK |
6029 | } |
6030 | ||
6031 | for (f = 0; f < nr_frags; f++) { | |
6032 | struct skb_frag_struct *frag; | |
6033 | ||
6034 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 6035 | len = min((unsigned int)frag->size, total); |
e5a43549 | 6036 | offset = frag->page_offset; |
9a799d71 AK |
6037 | |
6038 | while (len) { | |
44df32c5 AD |
6039 | i++; |
6040 | if (i == tx_ring->count) | |
6041 | i = 0; | |
6042 | ||
9a799d71 AK |
6043 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
6044 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6045 | ||
6046 | tx_buffer_info->length = size; | |
1b507730 | 6047 | tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev, |
e5a43549 AD |
6048 | frag->page, |
6049 | offset, size, | |
1b507730 | 6050 | DMA_TO_DEVICE); |
e5a43549 | 6051 | tx_buffer_info->mapped_as_page = true; |
1b507730 | 6052 | if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma)) |
e5a43549 | 6053 | goto dma_error; |
9a799d71 AK |
6054 | tx_buffer_info->time_stamp = jiffies; |
6055 | tx_buffer_info->next_to_watch = i; | |
6056 | ||
6057 | len -= size; | |
eacd73f7 | 6058 | total -= size; |
9a799d71 AK |
6059 | offset += size; |
6060 | count++; | |
9a799d71 | 6061 | } |
eacd73f7 YZ |
6062 | if (total == 0) |
6063 | break; | |
9a799d71 | 6064 | } |
44df32c5 | 6065 | |
8ad494b0 AD |
6066 | if (tx_flags & IXGBE_TX_FLAGS_TSO) |
6067 | gso_segs = skb_shinfo(skb)->gso_segs; | |
6068 | #ifdef IXGBE_FCOE | |
6069 | /* adjust for FCoE Sequence Offload */ | |
6070 | else if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6071 | gso_segs = DIV_ROUND_UP(skb->len - hdr_len, | |
6072 | skb_shinfo(skb)->gso_size); | |
6073 | #endif /* IXGBE_FCOE */ | |
6074 | bytecount += (gso_segs - 1) * hdr_len; | |
6075 | ||
6076 | /* multiply data chunks by size of headers */ | |
6077 | tx_ring->tx_buffer_info[i].bytecount = bytecount; | |
6078 | tx_ring->tx_buffer_info[i].gso_segs = gso_segs; | |
9a799d71 AK |
6079 | tx_ring->tx_buffer_info[i].skb = skb; |
6080 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
6081 | ||
e5a43549 AD |
6082 | return count; |
6083 | ||
6084 | dma_error: | |
849c4542 | 6085 | e_dev_err("TX DMA map failed\n"); |
e5a43549 AD |
6086 | |
6087 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
6088 | tx_buffer_info->dma = 0; | |
6089 | tx_buffer_info->time_stamp = 0; | |
6090 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
6091 | if (count) |
6092 | count--; | |
e5a43549 AD |
6093 | |
6094 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f | 6095 | while (count--) { |
e8e9f696 | 6096 | if (i == 0) |
e5a43549 | 6097 | i += tx_ring->count; |
c1fa347f | 6098 | i--; |
e5a43549 AD |
6099 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
6100 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
6101 | } | |
6102 | ||
e44d38e1 | 6103 | return 0; |
9a799d71 AK |
6104 | } |
6105 | ||
84ea2591 | 6106 | static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring, |
e8e9f696 | 6107 | int tx_flags, int count, u32 paylen, u8 hdr_len) |
9a799d71 AK |
6108 | { |
6109 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
6110 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6111 | u32 olinfo_status = 0, cmd_type_len = 0; | |
6112 | unsigned int i; | |
6113 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
6114 | ||
6115 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
6116 | ||
6117 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
6118 | ||
6119 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6120 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
6121 | ||
6122 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
6123 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6124 | ||
6125 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6126 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6127 | |
4eeae6fd PW |
6128 | /* use index 1 context for tso */ |
6129 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6130 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
6131 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
e8e9f696 | 6132 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
6133 | |
6134 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6135 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6136 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6137 | |
eacd73f7 YZ |
6138 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6139 | olinfo_status |= IXGBE_ADVTXD_CC; | |
6140 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
6141 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6142 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6143 | } | |
6144 | ||
9a799d71 AK |
6145 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
6146 | ||
6147 | i = tx_ring->next_to_use; | |
6148 | while (count--) { | |
6149 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6150 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 AK |
6151 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); |
6152 | tx_desc->read.cmd_type_len = | |
e8e9f696 | 6153 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 6154 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
6155 | i++; |
6156 | if (i == tx_ring->count) | |
6157 | i = 0; | |
6158 | } | |
6159 | ||
6160 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
6161 | ||
6162 | /* | |
6163 | * Force memory writes to complete before letting h/w | |
6164 | * know there are new descriptors to fetch. (Only | |
6165 | * applicable for weak-ordered memory model archs, | |
6166 | * such as IA-64). | |
6167 | */ | |
6168 | wmb(); | |
6169 | ||
6170 | tx_ring->next_to_use = i; | |
84ea2591 | 6171 | writel(i, tx_ring->tail); |
9a799d71 AK |
6172 | } |
6173 | ||
c4cf55e5 | 6174 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
5e09a105 | 6175 | int queue, u32 tx_flags, __be16 protocol) |
c4cf55e5 | 6176 | { |
c4cf55e5 PWJ |
6177 | struct ixgbe_atr_input atr_input; |
6178 | struct tcphdr *th; | |
c4cf55e5 PWJ |
6179 | struct iphdr *iph = ip_hdr(skb); |
6180 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
6181 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
6182 | u32 src_ipv4_addr, dst_ipv4_addr; | |
6183 | u8 l4type = 0; | |
6184 | ||
d3ead241 | 6185 | /* Right now, we support IPv4 only */ |
5e09a105 | 6186 | if (protocol != htons(ETH_P_IP)) |
d3ead241 | 6187 | return; |
c4cf55e5 PWJ |
6188 | /* check if we're UDP or TCP */ |
6189 | if (iph->protocol == IPPROTO_TCP) { | |
6190 | th = tcp_hdr(skb); | |
6191 | src_port = th->source; | |
6192 | dst_port = th->dest; | |
6193 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
6194 | /* l4type IPv4 type is 0, no need to assign */ | |
c4cf55e5 PWJ |
6195 | } else { |
6196 | /* Unsupported L4 header, just bail here */ | |
6197 | return; | |
6198 | } | |
6199 | ||
6200 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
6201 | ||
6202 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
e8e9f696 | 6203 | IXGBE_TX_FLAGS_VLAN_SHIFT; |
c4cf55e5 PWJ |
6204 | src_ipv4_addr = iph->saddr; |
6205 | dst_ipv4_addr = iph->daddr; | |
6206 | flex_bytes = eth->h_proto; | |
6207 | ||
6208 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
6209 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
6210 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
6211 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
6212 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
6213 | /* src and dst are inverted, think how the receiver sees them */ | |
6214 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
6215 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
6216 | ||
6217 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
6218 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
6219 | } | |
6220 | ||
e092be60 | 6221 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
e8e9f696 | 6222 | struct ixgbe_ring *tx_ring, int size) |
e092be60 | 6223 | { |
30eba97a | 6224 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
6225 | /* Herbert's original patch had: |
6226 | * smp_mb__after_netif_stop_queue(); | |
6227 | * but since that doesn't exist yet, just open code it. */ | |
6228 | smp_mb(); | |
6229 | ||
6230 | /* We need to check again in a case another CPU has just | |
6231 | * made room available. */ | |
6232 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
6233 | return -EBUSY; | |
6234 | ||
6235 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 6236 | netif_start_subqueue(netdev, tx_ring->queue_index); |
7ca3bc58 | 6237 | ++tx_ring->restart_queue; |
e092be60 AV |
6238 | return 0; |
6239 | } | |
6240 | ||
6241 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
e8e9f696 | 6242 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
6243 | { |
6244 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
6245 | return 0; | |
6246 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
6247 | } | |
6248 | ||
09a3b1f8 SH |
6249 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6250 | { | |
6251 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 6252 | int txq = smp_processor_id(); |
56075a98 | 6253 | #ifdef IXGBE_FCOE |
5e09a105 HZ |
6254 | __be16 protocol; |
6255 | ||
6256 | protocol = vlan_get_protocol(skb); | |
6257 | ||
6258 | if ((protocol == htons(ETH_P_FCOE)) || | |
6259 | (protocol == htons(ETH_P_FIP))) { | |
56075a98 JF |
6260 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
6261 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6262 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6263 | return txq; | |
4bc091d8 | 6264 | #ifdef CONFIG_IXGBE_DCB |
56075a98 JF |
6265 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6266 | txq = adapter->fcoe.up; | |
6267 | return txq; | |
4bc091d8 | 6268 | #endif |
56075a98 JF |
6269 | } |
6270 | } | |
6271 | #endif | |
6272 | ||
fdd3d631 KK |
6273 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6274 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6275 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6276 | return txq; |
fdd3d631 | 6277 | } |
c4cf55e5 | 6278 | |
2ea186ae JF |
6279 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6280 | if (skb->priority == TC_PRIO_CONTROL) | |
6281 | txq = adapter->ring_feature[RING_F_DCB].indices-1; | |
6282 | else | |
6283 | txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) | |
6284 | >> 13; | |
6285 | return txq; | |
6286 | } | |
09a3b1f8 SH |
6287 | |
6288 | return skb_tx_hash(dev, skb); | |
6289 | } | |
6290 | ||
84418e3b AD |
6291 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev, |
6292 | struct ixgbe_adapter *adapter, | |
6293 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6294 | { |
60d51134 | 6295 | struct netdev_queue *txq; |
9a799d71 AK |
6296 | unsigned int first; |
6297 | unsigned int tx_flags = 0; | |
30eba97a | 6298 | u8 hdr_len = 0; |
5f715823 | 6299 | int tso; |
9a799d71 AK |
6300 | int count = 0; |
6301 | unsigned int f; | |
5e09a105 HZ |
6302 | __be16 protocol; |
6303 | ||
6304 | protocol = vlan_get_protocol(skb); | |
9f8cdf4f | 6305 | |
eab6d18d | 6306 | if (vlan_tx_tag_present(skb)) { |
9f8cdf4f | 6307 | tx_flags |= vlan_tx_tag_get(skb); |
2f90b865 AD |
6308 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6309 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5f715823 | 6310 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
2f90b865 AD |
6311 | } |
6312 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6313 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
33c66bd1 JF |
6314 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED && |
6315 | skb->priority != TC_PRIO_CONTROL) { | |
2ea186ae JF |
6316 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
6317 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6318 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 6319 | } |
eacd73f7 | 6320 | |
09ad1cc0 | 6321 | #ifdef IXGBE_FCOE |
56075a98 JF |
6322 | /* for FCoE with DCB, we force the priority to what |
6323 | * was specified by the switch */ | |
6324 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED && | |
5e09a105 HZ |
6325 | (protocol == htons(ETH_P_FCOE) || |
6326 | protocol == htons(ETH_P_FIP))) { | |
4bc091d8 JF |
6327 | #ifdef CONFIG_IXGBE_DCB |
6328 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6329 | tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK | |
6330 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6331 | tx_flags |= ((adapter->fcoe.up << 13) | |
6332 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6333 | } | |
6334 | #endif | |
ca77cd59 | 6335 | /* flag for FCoE offloads */ |
5e09a105 | 6336 | if (protocol == htons(ETH_P_FCOE)) |
ca77cd59 | 6337 | tx_flags |= IXGBE_TX_FLAGS_FCOE; |
09ad1cc0 | 6338 | } |
ca77cd59 RL |
6339 | #endif |
6340 | ||
eacd73f7 | 6341 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
6342 | if (skb_is_gso(skb) || |
6343 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
6344 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
6345 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
6346 | count++; |
6347 | ||
9f8cdf4f JB |
6348 | count += TXD_USE_COUNT(skb_headlen(skb)); |
6349 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
6350 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
6351 | ||
e092be60 | 6352 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 6353 | adapter->tx_busy++; |
9a799d71 AK |
6354 | return NETDEV_TX_BUSY; |
6355 | } | |
9a799d71 | 6356 | |
9a799d71 | 6357 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
6358 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6359 | #ifdef IXGBE_FCOE | |
6360 | /* setup tx offload for FCoE */ | |
6361 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
6362 | if (tso < 0) { | |
6363 | dev_kfree_skb_any(skb); | |
6364 | return NETDEV_TX_OK; | |
6365 | } | |
6366 | if (tso) | |
6367 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
6368 | #endif /* IXGBE_FCOE */ | |
6369 | } else { | |
5e09a105 | 6370 | if (protocol == htons(ETH_P_IP)) |
eacd73f7 | 6371 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
5e09a105 HZ |
6372 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len, |
6373 | protocol); | |
eacd73f7 YZ |
6374 | if (tso < 0) { |
6375 | dev_kfree_skb_any(skb); | |
6376 | return NETDEV_TX_OK; | |
6377 | } | |
9a799d71 | 6378 | |
eacd73f7 YZ |
6379 | if (tso) |
6380 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5e09a105 HZ |
6381 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags, |
6382 | protocol) && | |
eacd73f7 YZ |
6383 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
6384 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
6385 | } | |
9a799d71 | 6386 | |
8ad494b0 | 6387 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len); |
44df32c5 | 6388 | if (count) { |
c4cf55e5 PWJ |
6389 | /* add the ATR filter if ATR is on */ |
6390 | if (tx_ring->atr_sample_rate) { | |
6391 | ++tx_ring->atr_count; | |
6392 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
e8e9f696 JP |
6393 | test_bit(__IXGBE_FDIR_INIT_DONE, |
6394 | &tx_ring->reinit_state)) { | |
c4cf55e5 | 6395 | ixgbe_atr(adapter, skb, tx_ring->queue_index, |
5e09a105 | 6396 | tx_flags, protocol); |
c4cf55e5 PWJ |
6397 | tx_ring->atr_count = 0; |
6398 | } | |
6399 | } | |
60d51134 ED |
6400 | txq = netdev_get_tx_queue(netdev, tx_ring->queue_index); |
6401 | txq->tx_bytes += skb->len; | |
6402 | txq->tx_packets++; | |
84ea2591 | 6403 | ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len); |
44df32c5 | 6404 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 6405 | |
44df32c5 AD |
6406 | } else { |
6407 | dev_kfree_skb_any(skb); | |
6408 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
6409 | tx_ring->next_to_use = first; | |
6410 | } | |
9a799d71 AK |
6411 | |
6412 | return NETDEV_TX_OK; | |
6413 | } | |
6414 | ||
84418e3b AD |
6415 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
6416 | { | |
6417 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6418 | struct ixgbe_ring *tx_ring; | |
6419 | ||
6420 | tx_ring = adapter->tx_ring[skb->queue_mapping]; | |
6421 | return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring); | |
6422 | } | |
6423 | ||
9a799d71 AK |
6424 | /** |
6425 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6426 | * @netdev: network interface device structure | |
6427 | * @p: pointer to an address structure | |
6428 | * | |
6429 | * Returns 0 on success, negative on failure | |
6430 | **/ | |
6431 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6432 | { | |
6433 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6434 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6435 | struct sockaddr *addr = p; |
6436 | ||
6437 | if (!is_valid_ether_addr(addr->sa_data)) | |
6438 | return -EADDRNOTAVAIL; | |
6439 | ||
6440 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6441 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6442 | |
1cdd1ec8 GR |
6443 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6444 | IXGBE_RAH_AV); | |
9a799d71 AK |
6445 | |
6446 | return 0; | |
6447 | } | |
6448 | ||
6b73e10d BH |
6449 | static int |
6450 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6451 | { | |
6452 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6453 | struct ixgbe_hw *hw = &adapter->hw; | |
6454 | u16 value; | |
6455 | int rc; | |
6456 | ||
6457 | if (prtad != hw->phy.mdio.prtad) | |
6458 | return -EINVAL; | |
6459 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6460 | if (!rc) | |
6461 | rc = value; | |
6462 | return rc; | |
6463 | } | |
6464 | ||
6465 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6466 | u16 addr, u16 value) | |
6467 | { | |
6468 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6469 | struct ixgbe_hw *hw = &adapter->hw; | |
6470 | ||
6471 | if (prtad != hw->phy.mdio.prtad) | |
6472 | return -EINVAL; | |
6473 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6474 | } | |
6475 | ||
6476 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6477 | { | |
6478 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6479 | ||
6480 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6481 | } | |
6482 | ||
0365e6e4 PW |
6483 | /** |
6484 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6485 | * netdev->dev_addrs |
0365e6e4 PW |
6486 | * @netdev: network interface device structure |
6487 | * | |
6488 | * Returns non-zero on failure | |
6489 | **/ | |
6490 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6491 | { | |
6492 | int err = 0; | |
6493 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6494 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6495 | ||
6496 | if (is_valid_ether_addr(mac->san_addr)) { | |
6497 | rtnl_lock(); | |
6498 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6499 | rtnl_unlock(); | |
6500 | } | |
6501 | return err; | |
6502 | } | |
6503 | ||
6504 | /** | |
6505 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6506 | * netdev->dev_addrs |
0365e6e4 PW |
6507 | * @netdev: network interface device structure |
6508 | * | |
6509 | * Returns non-zero on failure | |
6510 | **/ | |
6511 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6512 | { | |
6513 | int err = 0; | |
6514 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6515 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6516 | ||
6517 | if (is_valid_ether_addr(mac->san_addr)) { | |
6518 | rtnl_lock(); | |
6519 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6520 | rtnl_unlock(); | |
6521 | } | |
6522 | return err; | |
6523 | } | |
6524 | ||
9a799d71 AK |
6525 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6526 | /* | |
6527 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6528 | * without having to re-enable interrupts. It's not called while | |
6529 | * the interrupt routine is executing. | |
6530 | */ | |
6531 | static void ixgbe_netpoll(struct net_device *netdev) | |
6532 | { | |
6533 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6534 | int i; |
9a799d71 | 6535 | |
1a647bd2 AD |
6536 | /* if interface is down do nothing */ |
6537 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6538 | return; | |
6539 | ||
9a799d71 | 6540 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6541 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6542 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6543 | for (i = 0; i < num_q_vectors; i++) { | |
6544 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
6545 | ixgbe_msix_clean_many(0, q_vector); | |
6546 | } | |
6547 | } else { | |
6548 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6549 | } | |
9a799d71 | 6550 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
6551 | } |
6552 | #endif | |
6553 | ||
de1036b1 ED |
6554 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6555 | struct rtnl_link_stats64 *stats) | |
6556 | { | |
6557 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6558 | int i; | |
6559 | ||
6560 | /* accurate rx/tx bytes/packets stats */ | |
6561 | dev_txq_stats_fold(netdev, stats); | |
1a51502b | 6562 | rcu_read_lock(); |
de1036b1 | 6563 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6564 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6565 | u64 bytes, packets; |
6566 | unsigned int start; | |
6567 | ||
1a51502b ED |
6568 | if (ring) { |
6569 | do { | |
6570 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6571 | packets = ring->stats.packets; | |
6572 | bytes = ring->stats.bytes; | |
6573 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6574 | stats->rx_packets += packets; | |
6575 | stats->rx_bytes += bytes; | |
6576 | } | |
de1036b1 | 6577 | } |
1a51502b | 6578 | rcu_read_unlock(); |
de1036b1 ED |
6579 | /* following stats updated by ixgbe_watchdog_task() */ |
6580 | stats->multicast = netdev->stats.multicast; | |
6581 | stats->rx_errors = netdev->stats.rx_errors; | |
6582 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6583 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6584 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6585 | return stats; | |
6586 | } | |
6587 | ||
6588 | ||
0edc3527 | 6589 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6590 | .ndo_open = ixgbe_open, |
0edc3527 | 6591 | .ndo_stop = ixgbe_close, |
00829823 | 6592 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6593 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 6594 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6595 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
6596 | .ndo_validate_addr = eth_validate_addr, | |
6597 | .ndo_set_mac_address = ixgbe_set_mac, | |
6598 | .ndo_change_mtu = ixgbe_change_mtu, | |
6599 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6600 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6601 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6602 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6603 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6604 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6605 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
6606 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, | |
de1036b1 | 6607 | .ndo_get_stats64 = ixgbe_get_stats64, |
0edc3527 SH |
6608 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6609 | .ndo_poll_controller = ixgbe_netpoll, | |
6610 | #endif | |
332d4a7d YZ |
6611 | #ifdef IXGBE_FCOE |
6612 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
6613 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
8450ff8c YZ |
6614 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6615 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6616 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 6617 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
6618 | }; |
6619 | ||
1cdd1ec8 GR |
6620 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
6621 | const struct ixgbe_info *ii) | |
6622 | { | |
6623 | #ifdef CONFIG_PCI_IOV | |
6624 | struct ixgbe_hw *hw = &adapter->hw; | |
6625 | int err; | |
6626 | ||
6627 | if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs) | |
6628 | return; | |
6629 | ||
6630 | /* The 82599 supports up to 64 VFs per physical function | |
6631 | * but this implementation limits allocation to 63 so that | |
6632 | * basic networking resources are still available to the | |
6633 | * physical function | |
6634 | */ | |
6635 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
6636 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
6637 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
6638 | if (err) { | |
396e799c | 6639 | e_err(probe, "Failed to enable PCI sriov: %d\n", err); |
1cdd1ec8 GR |
6640 | goto err_novfs; |
6641 | } | |
6642 | /* If call to enable VFs succeeded then allocate memory | |
6643 | * for per VF control structures. | |
6644 | */ | |
6645 | adapter->vfinfo = | |
6646 | kcalloc(adapter->num_vfs, | |
6647 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
6648 | if (adapter->vfinfo) { | |
6649 | /* Now that we're sure SR-IOV is enabled | |
6650 | * and memory allocated set up the mailbox parameters | |
6651 | */ | |
6652 | ixgbe_init_mbx_params_pf(hw); | |
6653 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
6654 | sizeof(hw->mbx.ops)); | |
6655 | ||
6656 | /* Disable RSC when in SR-IOV mode */ | |
6657 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
6658 | IXGBE_FLAG2_RSC_ENABLED); | |
6659 | return; | |
6660 | } | |
6661 | ||
6662 | /* Oh oh */ | |
396e799c ET |
6663 | e_err(probe, "Unable to allocate memory for VF Data Storage - " |
6664 | "SRIOV disabled\n"); | |
1cdd1ec8 GR |
6665 | pci_disable_sriov(adapter->pdev); |
6666 | ||
6667 | err_novfs: | |
6668 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
6669 | adapter->num_vfs = 0; | |
6670 | #endif /* CONFIG_PCI_IOV */ | |
6671 | } | |
6672 | ||
9a799d71 AK |
6673 | /** |
6674 | * ixgbe_probe - Device Initialization Routine | |
6675 | * @pdev: PCI device information struct | |
6676 | * @ent: entry in ixgbe_pci_tbl | |
6677 | * | |
6678 | * Returns 0 on success, negative on failure | |
6679 | * | |
6680 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6681 | * The OS initialization, configuring of the adapter private structure, | |
6682 | * and a hardware reset occur. | |
6683 | **/ | |
6684 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 6685 | const struct pci_device_id *ent) |
9a799d71 AK |
6686 | { |
6687 | struct net_device *netdev; | |
6688 | struct ixgbe_adapter *adapter = NULL; | |
6689 | struct ixgbe_hw *hw; | |
6690 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
6691 | static int cards_found; |
6692 | int i, err, pci_using_dac; | |
c85a2618 | 6693 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
6694 | #ifdef IXGBE_FCOE |
6695 | u16 device_caps; | |
6696 | #endif | |
c44ade9e | 6697 | u32 part_num, eec; |
9a799d71 | 6698 | |
bded64a7 AG |
6699 | /* Catch broken hardware that put the wrong VF device ID in |
6700 | * the PCIe SR-IOV capability. | |
6701 | */ | |
6702 | if (pdev->is_virtfn) { | |
6703 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
6704 | pci_name(pdev), pdev->vendor, pdev->device); | |
6705 | return -EINVAL; | |
6706 | } | |
6707 | ||
9ce77666 | 6708 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
6709 | if (err) |
6710 | return err; | |
6711 | ||
1b507730 NN |
6712 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
6713 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
6714 | pci_using_dac = 1; |
6715 | } else { | |
1b507730 | 6716 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 6717 | if (err) { |
1b507730 NN |
6718 | err = dma_set_coherent_mask(&pdev->dev, |
6719 | DMA_BIT_MASK(32)); | |
9a799d71 | 6720 | if (err) { |
b8bc0421 DC |
6721 | dev_err(&pdev->dev, |
6722 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
6723 | goto err_dma; |
6724 | } | |
6725 | } | |
6726 | pci_using_dac = 0; | |
6727 | } | |
6728 | ||
9ce77666 | 6729 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 6730 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 6731 | if (err) { |
b8bc0421 DC |
6732 | dev_err(&pdev->dev, |
6733 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
6734 | goto err_pci_reg; |
6735 | } | |
6736 | ||
19d5afd4 | 6737 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 6738 | |
9a799d71 | 6739 | pci_set_master(pdev); |
fb3b27bc | 6740 | pci_save_state(pdev); |
9a799d71 | 6741 | |
c85a2618 JF |
6742 | if (ii->mac == ixgbe_mac_82598EB) |
6743 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
6744 | else | |
6745 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
6746 | ||
6747 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); | |
6748 | #ifdef IXGBE_FCOE | |
6749 | indices += min_t(unsigned int, num_possible_cpus(), | |
6750 | IXGBE_MAX_FCOE_INDICES); | |
6751 | #endif | |
c85a2618 | 6752 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
6753 | if (!netdev) { |
6754 | err = -ENOMEM; | |
6755 | goto err_alloc_etherdev; | |
6756 | } | |
6757 | ||
9a799d71 AK |
6758 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6759 | ||
6760 | pci_set_drvdata(pdev, netdev); | |
6761 | adapter = netdev_priv(netdev); | |
6762 | ||
6763 | adapter->netdev = netdev; | |
6764 | adapter->pdev = pdev; | |
6765 | hw = &adapter->hw; | |
6766 | hw->back = adapter; | |
6767 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
6768 | ||
05857980 | 6769 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 6770 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
6771 | if (!hw->hw_addr) { |
6772 | err = -EIO; | |
6773 | goto err_ioremap; | |
6774 | } | |
6775 | ||
6776 | for (i = 1; i <= 5; i++) { | |
6777 | if (pci_resource_len(pdev, i) == 0) | |
6778 | continue; | |
6779 | } | |
6780 | ||
0edc3527 | 6781 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 6782 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 6783 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
6784 | strcpy(netdev->name, pci_name(pdev)); |
6785 | ||
9a799d71 AK |
6786 | adapter->bd_number = cards_found; |
6787 | ||
9a799d71 AK |
6788 | /* Setup hw api */ |
6789 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 6790 | hw->mac.type = ii->mac; |
9a799d71 | 6791 | |
c44ade9e JB |
6792 | /* EEPROM */ |
6793 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
6794 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
6795 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
6796 | if (!(eec & (1 << 8))) | |
6797 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
6798 | ||
6799 | /* PHY */ | |
6800 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 6801 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
6802 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
6803 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
6804 | hw->phy.mdio.mmds = 0; | |
6805 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
6806 | hw->phy.mdio.dev = netdev; | |
6807 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
6808 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
6809 | |
6810 | /* set up this timer and work struct before calling get_invariants | |
6811 | * which might start the timer | |
6812 | */ | |
6813 | init_timer(&adapter->sfp_timer); | |
c061b18d | 6814 | adapter->sfp_timer.function = ixgbe_sfp_timer; |
c4900be0 DS |
6815 | adapter->sfp_timer.data = (unsigned long) adapter; |
6816 | ||
6817 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 6818 | |
e8e26350 PW |
6819 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
6820 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
6821 | ||
6822 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
6823 | INIT_WORK(&adapter->sfp_config_module_task, | |
e8e9f696 | 6824 | ixgbe_sfp_config_module_task); |
e8e26350 | 6825 | |
8ca783ab | 6826 | ii->get_invariants(hw); |
9a799d71 AK |
6827 | |
6828 | /* setup the private structure */ | |
6829 | err = ixgbe_sw_init(adapter); | |
6830 | if (err) | |
6831 | goto err_sw_init; | |
6832 | ||
e86bff0e DS |
6833 | /* Make it possible the adapter to be woken up via WOL */ |
6834 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
6835 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); | |
6836 | ||
bf069c97 DS |
6837 | /* |
6838 | * If there is a fan on this device and it has failed log the | |
6839 | * failure. | |
6840 | */ | |
6841 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
6842 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
6843 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 6844 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
6845 | } |
6846 | ||
c44ade9e | 6847 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 6848 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 6849 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 6850 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
6851 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
6852 | hw->mac.type == ixgbe_mac_82598EB) { | |
6853 | /* | |
6854 | * Start a kernel thread to watch for a module to arrive. | |
6855 | * Only do this for 82598, since 82599 will generate | |
6856 | * interrupts on module arrival. | |
6857 | */ | |
6858 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
6859 | mod_timer(&adapter->sfp_timer, | |
6860 | round_jiffies(jiffies + (2 * HZ))); | |
6861 | err = 0; | |
6862 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
849c4542 ET |
6863 | e_dev_err("failed to initialize because an unsupported SFP+ " |
6864 | "module type was detected.\n"); | |
6865 | e_dev_err("Reload the driver after installing a supported " | |
6866 | "module.\n"); | |
04f165ef PW |
6867 | goto err_sw_init; |
6868 | } else if (err) { | |
849c4542 | 6869 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
6870 | goto err_sw_init; |
6871 | } | |
6872 | ||
1cdd1ec8 GR |
6873 | ixgbe_probe_vf(adapter, ii); |
6874 | ||
396e799c | 6875 | netdev->features = NETIF_F_SG | |
e8e9f696 JP |
6876 | NETIF_F_IP_CSUM | |
6877 | NETIF_F_HW_VLAN_TX | | |
6878 | NETIF_F_HW_VLAN_RX | | |
6879 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 6880 | |
e9990a9c | 6881 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 6882 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 6883 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 6884 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 6885 | |
45a5ead0 JB |
6886 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
6887 | netdev->features |= NETIF_F_SCTP_CSUM; | |
6888 | ||
ad31c402 JK |
6889 | netdev->vlan_features |= NETIF_F_TSO; |
6890 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 6891 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 6892 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
6893 | netdev->vlan_features |= NETIF_F_SG; |
6894 | ||
1cdd1ec8 GR |
6895 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6896 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
6897 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 AD |
6898 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
6899 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
6900 | ||
7a6b6f51 | 6901 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
6902 | netdev->dcbnl_ops = &dcbnl_ops; |
6903 | #endif | |
6904 | ||
eacd73f7 | 6905 | #ifdef IXGBE_FCOE |
0d551589 | 6906 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
6907 | if (hw->mac.ops.get_device_caps) { |
6908 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
6909 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
6910 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
6911 | } |
6912 | } | |
5e09d7f6 YZ |
6913 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
6914 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
6915 | netdev->vlan_features |= NETIF_F_FSO; | |
6916 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
6917 | } | |
eacd73f7 | 6918 | #endif /* IXGBE_FCOE */ |
7b872a55 | 6919 | if (pci_using_dac) { |
9a799d71 | 6920 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
6921 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
6922 | } | |
9a799d71 | 6923 | |
0c19d6af | 6924 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
6925 | netdev->features |= NETIF_F_LRO; |
6926 | ||
9a799d71 | 6927 | /* make sure the EEPROM is good */ |
c44ade9e | 6928 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 6929 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 AK |
6930 | err = -EIO; |
6931 | goto err_eeprom; | |
6932 | } | |
6933 | ||
6934 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
6935 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
6936 | ||
c44ade9e | 6937 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 6938 | e_dev_err("invalid MAC address\n"); |
9a799d71 AK |
6939 | err = -EIO; |
6940 | goto err_eeprom; | |
6941 | } | |
6942 | ||
61fac744 PW |
6943 | /* power down the optics */ |
6944 | if (hw->phy.multispeed_fiber) | |
6945 | hw->mac.ops.disable_tx_laser(hw); | |
6946 | ||
9a799d71 | 6947 | init_timer(&adapter->watchdog_timer); |
c061b18d | 6948 | adapter->watchdog_timer.function = ixgbe_watchdog; |
9a799d71 AK |
6949 | adapter->watchdog_timer.data = (unsigned long)adapter; |
6950 | ||
6951 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 6952 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 6953 | |
021230d4 AV |
6954 | err = ixgbe_init_interrupt_scheme(adapter); |
6955 | if (err) | |
6956 | goto err_sw_init; | |
9a799d71 | 6957 | |
e8e26350 PW |
6958 | switch (pdev->device) { |
6959 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 | 6960 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
e8e9f696 | 6961 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); |
e8e26350 PW |
6962 | break; |
6963 | default: | |
6964 | adapter->wol = 0; | |
6965 | break; | |
6966 | } | |
e8e26350 PW |
6967 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
6968 | ||
04f165ef PW |
6969 | /* pick up the PCI bus settings for reporting later */ |
6970 | hw->mac.ops.get_bus_info(hw); | |
6971 | ||
9a799d71 | 6972 | /* print bus type/speed/width info */ |
849c4542 | 6973 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
e8e9f696 JP |
6974 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" : |
6975 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" : | |
6976 | "Unknown"), | |
6977 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
6978 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
6979 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
6980 | "Unknown"), | |
6981 | netdev->dev_addr); | |
c44ade9e | 6982 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 | 6983 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
849c4542 ET |
6984 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, " |
6985 | "PBA No: %06x-%03x\n", | |
6986 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
6987 | (part_num >> 8), (part_num & 0xff)); | |
e8e26350 | 6988 | else |
849c4542 ET |
6989 | e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n", |
6990 | hw->mac.type, hw->phy.type, | |
6991 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 6992 | |
e8e26350 | 6993 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
6994 | e_dev_warn("PCI-Express bandwidth available for this card is " |
6995 | "not sufficient for optimal performance.\n"); | |
6996 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
6997 | "is required.\n"); | |
0c254d86 AK |
6998 | } |
6999 | ||
34b0368c PWJ |
7000 | /* save off EEPROM version number */ |
7001 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
7002 | ||
9a799d71 | 7003 | /* reset the hardware with the new settings */ |
794caeb2 | 7004 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 7005 | |
794caeb2 PWJ |
7006 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7007 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7008 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7009 | "Please be aware there may be issues associated " | |
7010 | "with your hardware. If you are experiencing " | |
7011 | "problems please contact your Intel or hardware " | |
7012 | "representative who provided you with this " | |
7013 | "hardware.\n"); | |
794caeb2 | 7014 | } |
9a799d71 AK |
7015 | strcpy(netdev->name, "eth%d"); |
7016 | err = register_netdev(netdev); | |
7017 | if (err) | |
7018 | goto err_register; | |
7019 | ||
54386467 JB |
7020 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7021 | netif_carrier_off(netdev); | |
7022 | ||
c4cf55e5 PWJ |
7023 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
7024 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
7025 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
7026 | ||
119fc60a | 7027 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
e8e9f696 JP |
7028 | INIT_WORK(&adapter->check_overtemp_task, |
7029 | ixgbe_check_overtemp_task); | |
5dd2d332 | 7030 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7031 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7032 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7033 | ixgbe_setup_dca(adapter); |
7034 | } | |
7035 | #endif | |
1cdd1ec8 | 7036 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7037 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7038 | for (i = 0; i < adapter->num_vfs; i++) |
7039 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7040 | } | |
7041 | ||
0365e6e4 PW |
7042 | /* add san mac addr to netdev */ |
7043 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7044 | |
849c4542 | 7045 | e_dev_info("Intel(R) 10 Gigabit Network Connection\n"); |
9a799d71 AK |
7046 | cards_found++; |
7047 | return 0; | |
7048 | ||
7049 | err_register: | |
5eba3699 | 7050 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7051 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
7052 | err_sw_init: |
7053 | err_eeprom: | |
1cdd1ec8 GR |
7054 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7055 | ixgbe_disable_sriov(adapter); | |
c4900be0 DS |
7056 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
7057 | del_timer_sync(&adapter->sfp_timer); | |
7058 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
7059 | cancel_work_sync(&adapter->multispeed_fiber_task); |
7060 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
7061 | iounmap(hw->hw_addr); |
7062 | err_ioremap: | |
7063 | free_netdev(netdev); | |
7064 | err_alloc_etherdev: | |
e8e9f696 JP |
7065 | pci_release_selected_regions(pdev, |
7066 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7067 | err_pci_reg: |
7068 | err_dma: | |
7069 | pci_disable_device(pdev); | |
7070 | return err; | |
7071 | } | |
7072 | ||
7073 | /** | |
7074 | * ixgbe_remove - Device Removal Routine | |
7075 | * @pdev: PCI device information struct | |
7076 | * | |
7077 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7078 | * that it should release a PCI device. The could be caused by a | |
7079 | * Hot-Plug event, or because the driver is going to be removed from | |
7080 | * memory. | |
7081 | **/ | |
7082 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7083 | { | |
7084 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7085 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7086 | ||
7087 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
7088 | /* clear the module not found bit to make sure the worker won't |
7089 | * reschedule | |
7090 | */ | |
7091 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
7092 | del_timer_sync(&adapter->watchdog_timer); |
7093 | ||
c4900be0 DS |
7094 | del_timer_sync(&adapter->sfp_timer); |
7095 | cancel_work_sync(&adapter->watchdog_task); | |
7096 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
7097 | cancel_work_sync(&adapter->multispeed_fiber_task); |
7098 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
7099 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
7100 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
7101 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
7102 | flush_scheduled_work(); |
7103 | ||
5dd2d332 | 7104 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7105 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7106 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7107 | dca_remove_requester(&pdev->dev); | |
7108 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7109 | } | |
7110 | ||
7111 | #endif | |
332d4a7d YZ |
7112 | #ifdef IXGBE_FCOE |
7113 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7114 | ixgbe_cleanup_fcoe(adapter); | |
7115 | ||
7116 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7117 | |
7118 | /* remove the added san mac */ | |
7119 | ixgbe_del_sanmac_netdev(netdev); | |
7120 | ||
c4900be0 DS |
7121 | if (netdev->reg_state == NETREG_REGISTERED) |
7122 | unregister_netdev(netdev); | |
9a799d71 | 7123 | |
1cdd1ec8 GR |
7124 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7125 | ixgbe_disable_sriov(adapter); | |
7126 | ||
7a921c93 | 7127 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7128 | |
021230d4 | 7129 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
7130 | |
7131 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 7132 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7133 | IORESOURCE_MEM)); |
9a799d71 | 7134 | |
849c4542 | 7135 | e_dev_info("complete\n"); |
021230d4 | 7136 | |
9a799d71 AK |
7137 | free_netdev(netdev); |
7138 | ||
19d5afd4 | 7139 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7140 | |
9a799d71 AK |
7141 | pci_disable_device(pdev); |
7142 | } | |
7143 | ||
7144 | /** | |
7145 | * ixgbe_io_error_detected - called when PCI error is detected | |
7146 | * @pdev: Pointer to PCI device | |
7147 | * @state: The current pci connection state | |
7148 | * | |
7149 | * This function is called after a PCI bus error affecting | |
7150 | * this device has been detected. | |
7151 | */ | |
7152 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7153 | pci_channel_state_t state) |
9a799d71 AK |
7154 | { |
7155 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 7156 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
7157 | |
7158 | netif_device_detach(netdev); | |
7159 | ||
3044b8d1 BL |
7160 | if (state == pci_channel_io_perm_failure) |
7161 | return PCI_ERS_RESULT_DISCONNECT; | |
7162 | ||
9a799d71 AK |
7163 | if (netif_running(netdev)) |
7164 | ixgbe_down(adapter); | |
7165 | pci_disable_device(pdev); | |
7166 | ||
b4617240 | 7167 | /* Request a slot reset. */ |
9a799d71 AK |
7168 | return PCI_ERS_RESULT_NEED_RESET; |
7169 | } | |
7170 | ||
7171 | /** | |
7172 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7173 | * @pdev: Pointer to PCI device | |
7174 | * | |
7175 | * Restart the card from scratch, as if from a cold-boot. | |
7176 | */ | |
7177 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7178 | { | |
7179 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 7180 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
7181 | pci_ers_result_t result; |
7182 | int err; | |
9a799d71 | 7183 | |
9ce77666 | 7184 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7185 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7186 | result = PCI_ERS_RESULT_DISCONNECT; |
7187 | } else { | |
7188 | pci_set_master(pdev); | |
7189 | pci_restore_state(pdev); | |
c0e1f68b | 7190 | pci_save_state(pdev); |
9a799d71 | 7191 | |
dd4d8ca6 | 7192 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7193 | |
6fabd715 | 7194 | ixgbe_reset(adapter); |
88512539 | 7195 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7196 | result = PCI_ERS_RESULT_RECOVERED; |
7197 | } | |
7198 | ||
7199 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7200 | if (err) { | |
849c4542 ET |
7201 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7202 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7203 | /* non-fatal, continue */ |
7204 | } | |
9a799d71 | 7205 | |
6fabd715 | 7206 | return result; |
9a799d71 AK |
7207 | } |
7208 | ||
7209 | /** | |
7210 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7211 | * @pdev: Pointer to PCI device | |
7212 | * | |
7213 | * This callback is called when the error recovery driver tells us that | |
7214 | * its OK to resume normal operation. | |
7215 | */ | |
7216 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7217 | { | |
7218 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 7219 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
7220 | |
7221 | if (netif_running(netdev)) { | |
7222 | if (ixgbe_up(adapter)) { | |
396e799c | 7223 | e_info(probe, "ixgbe_up failed after reset\n"); |
9a799d71 AK |
7224 | return; |
7225 | } | |
7226 | } | |
7227 | ||
7228 | netif_device_attach(netdev); | |
9a799d71 AK |
7229 | } |
7230 | ||
7231 | static struct pci_error_handlers ixgbe_err_handler = { | |
7232 | .error_detected = ixgbe_io_error_detected, | |
7233 | .slot_reset = ixgbe_io_slot_reset, | |
7234 | .resume = ixgbe_io_resume, | |
7235 | }; | |
7236 | ||
7237 | static struct pci_driver ixgbe_driver = { | |
7238 | .name = ixgbe_driver_name, | |
7239 | .id_table = ixgbe_pci_tbl, | |
7240 | .probe = ixgbe_probe, | |
7241 | .remove = __devexit_p(ixgbe_remove), | |
7242 | #ifdef CONFIG_PM | |
7243 | .suspend = ixgbe_suspend, | |
7244 | .resume = ixgbe_resume, | |
7245 | #endif | |
7246 | .shutdown = ixgbe_shutdown, | |
7247 | .err_handler = &ixgbe_err_handler | |
7248 | }; | |
7249 | ||
7250 | /** | |
7251 | * ixgbe_init_module - Driver Registration Routine | |
7252 | * | |
7253 | * ixgbe_init_module is the first routine called when the driver is | |
7254 | * loaded. All it does is register with the PCI subsystem. | |
7255 | **/ | |
7256 | static int __init ixgbe_init_module(void) | |
7257 | { | |
7258 | int ret; | |
c7689578 | 7259 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7260 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7261 | |
5dd2d332 | 7262 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7263 | dca_register_notify(&dca_notifier); |
bd0362dd | 7264 | #endif |
5dd2d332 | 7265 | |
9a799d71 AK |
7266 | ret = pci_register_driver(&ixgbe_driver); |
7267 | return ret; | |
7268 | } | |
b4617240 | 7269 | |
9a799d71 AK |
7270 | module_init(ixgbe_init_module); |
7271 | ||
7272 | /** | |
7273 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7274 | * | |
7275 | * ixgbe_exit_module is called just before the driver is removed | |
7276 | * from memory. | |
7277 | **/ | |
7278 | static void __exit ixgbe_exit_module(void) | |
7279 | { | |
5dd2d332 | 7280 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7281 | dca_unregister_notify(&dca_notifier); |
7282 | #endif | |
9a799d71 | 7283 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7284 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7285 | } |
bd0362dd | 7286 | |
5dd2d332 | 7287 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7288 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7289 | void *p) |
bd0362dd JC |
7290 | { |
7291 | int ret_val; | |
7292 | ||
7293 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7294 | __ixgbe_notify_dca); |
bd0362dd JC |
7295 | |
7296 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7297 | } | |
b453368d | 7298 | |
5dd2d332 | 7299 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7300 | |
b453368d | 7301 | /** |
849c4542 | 7302 | * ixgbe_get_hw_dev return device |
b453368d AD |
7303 | * used by hardware layer to print debugging information |
7304 | **/ | |
849c4542 | 7305 | struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw) |
b453368d AD |
7306 | { |
7307 | struct ixgbe_adapter *adapter = hw->back; | |
849c4542 | 7308 | return adapter->netdev; |
b453368d | 7309 | } |
bd0362dd | 7310 | |
9a799d71 AK |
7311 | module_exit(ixgbe_exit_module); |
7312 | ||
7313 | /* ixgbe_main.c */ |