]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/ixgbe/ixgbe_main.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: Move max frame size and Rx buffer length configuration into a function
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
134MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515exit:
516 return;
517}
518
5eba3699
AV		 519static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520{
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 527}
528
529static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530{
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 537}
9a799d71 538
e8e26350
PW		 539/*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
9a799d71
AK		 549{
550 u32 ivar, index;
e8e26350
PW		 551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
9a799d71
AK		 586}
587
fe49f04a
AD		 588static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590{
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602}
603
9a799d71 604static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
9a799d71 607{
e5a43549
AD		 608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
1b507730 610 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 611 tx_buffer_info->dma,
612 tx_buffer_info->length,
1b507730 613 DMA_TO_DEVICE);
e5a43549 614 else
1b507730 615 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 616 tx_buffer_info->dma,
617 tx_buffer_info->length,
1b507730 618 DMA_TO_DEVICE);
e5a43549
AD		 619 tx_buffer_info->dma = 0;
620 }
9a799d71
AK		 621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
44df32c5 625 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 626 /* tx_buffer_info must be completely set up in the transmit path */
627}
628
26f23d82 629/**
7483d9dd 630 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
7483d9dd 637 * Returns : true if in xon state (currently not paused)
26f23d82 638 */
7483d9dd 639static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
26f23d82
YZ		 640 struct ixgbe_ring *tx_ring)
641{
26f23d82
YZ		 642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644#ifdef CONFIG_IXGBE_DCB
ca739481 645 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 646 int tc;
26f23d82
YZ		 647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
6837e895
PW		 650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
26f23d82
YZ		 652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 654 break;
655 case ixgbe_mac_82599EB:
26f23d82
YZ		 656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
6837e895
PW		 674 break;
675 default:
676 tc = 0;
26f23d82
YZ		 677 }
678 txoff <<= tc;
679 }
680#endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682}
683
9a799d71 684static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
9a799d71 687{
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
9a799d71 690 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 691 * check with the clearing of time_stamp and movement of eop */
9a799d71 692 adapter->detect_tx_hung = false;
44df32c5 693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 695 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 696 /* detected Tx unit hang */
e01c31a5
JB		 697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
396e799c 699 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 712 return true;
713 }
714
715 return false;
716}
717
b4617240
PW		 718#define IXGBE_MAX_TXD_PWR 14
719#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 720
721/* Tx Descriptors needed, worst case */
722#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 726
e01c31a5
JB		 727static void ixgbe_tx_timeout(struct net_device *netdev);
728
9a799d71
AK		 729/**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 731 * @q_vector: structure containing interrupt and ring information
e01c31a5 732 * @tx_ring: tx ring to clean
9a799d71 733 **/
fe49f04a 734static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 735 struct ixgbe_ring *tx_ring)
9a799d71 736{
fe49f04a 737 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 738 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
e01c31a5 742 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 743
744 i = tx_ring->next_to_clean;
12207e49
PWJ		 745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 749 (count < tx_ring->work_limit)) {
12207e49 750 bool cleaned = false;
2d0bb1c1 751 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
9a799d71
AK		 754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 756 cleaned = (i == eop);
e01c31a5 757 skb = tx_buffer_info->skb;
9a799d71 758
12207e49 759 if (cleaned && skb) {
e092be60 760 unsigned int segs, bytecount;
3d8fd385 761 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 762
763 /* gso_segs is currently only valid for tcp */
e092be60 764 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 765#ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776#endif /* IXGBE_FCOE */
e092be60 777 /* multiply data chunks by size of headers */
3d8fd385 778 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 779 total_packets += segs;
780 total_bytes += bytecount;
e092be60 781 }
e01c31a5 782
9a799d71 783 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 784 tx_buffer_info);
9a799d71 785
12207e49
PWJ		 786 tx_desc->wb.status = 0;
787
9a799d71
AK		 788 i++;
789 if (i == tx_ring->count)
790 i = 0;
e01c31a5 791 }
12207e49
PWJ		 792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
795 }
796
9a799d71
AK		 797 tx_ring->next_to_clean = i;
798
e092be60 799#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
30eba97a
AV		 806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 809 ++tx_ring->restart_queue;
30eba97a 810 }
e092be60 811 }
9a799d71 812
e01c31a5
JB		 813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
396e799c
ET		 816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
9a799d71 821
e01c31a5 822 /* re-arm the interrupt */
fe49f04a
AD		 823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 825
e01c31a5
JB		 826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
e01c31a5 828 tx_ring->stats.packets += total_packets;
12207e49 829 tx_ring->stats.bytes += total_bytes;
9a1a69ad 830 return (count < tx_ring->work_limit);
9a799d71
AK		 831}
832
5dd2d332 833#ifdef CONFIG_IXGBE_DCA
bd0362dd 834static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 835 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 836{
837 u32 rxctrl;
838 int cpu = get_cpu();
4a0b9ca0 839 int q = rx_ring->reg_idx;
bd0362dd 840
3a581073 841 if (rx_ring->cpu != cpu) {
bd0362dd 842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
bd0362dd
JC		 851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 857 rx_ring->cpu = cpu;
bd0362dd
JC		 858 }
859 put_cpu();
860}
861
862static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 863 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 864{
865 u32 txctrl;
866 int cpu = get_cpu();
4a0b9ca0 867 int q = tx_ring->reg_idx;
ee5f784a 868 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 869
3a581073 870 if (tx_ring->cpu != cpu) {
e8e26350 871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 884 }
3a581073 885 tx_ring->cpu = cpu;
bd0362dd
JC		 886 }
887 put_cpu();
888}
889
890static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891{
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
e35ec126
AD		 897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
bd0362dd 900 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 907 }
908}
909
910static int __ixgbe_notify_dca(struct device *dev, void *data)
911{
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
652f093f 921 if (dca_add_requester(dev) == 0) {
96b0e0f6 922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
652f093f 936 return 0;
bd0362dd
JC		 937}
938
5dd2d332 939#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 940/**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
177db6ff
MC		 944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
9a799d71 947 **/
78b6f4ce 948static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 949 struct sk_buff *skb, u8 status,
fdaff1ce 950 struct ixgbe_ring *ring,
177db6ff 951 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 952{
78b6f4ce
HX		 953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 957
182ff8df 958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 961 else
78b6f4ce 962 napi_gro_receive(napi, skb);
177db6ff 963 } else {
8a62babf 964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
966 else
967 netif_rx(skb);
9a799d71
AK		 968 }
969}
970
e59bd25d
AV		 971/**
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
976 **/
9a799d71 977static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 978 union ixgbe_adv_rx_desc *rx_desc,
979 struct sk_buff *skb)
9a799d71 980{
8bae1b2b
DS		 981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
982
9a799d71
AK		 983 skb->ip_summed = CHECKSUM_NONE;
984
712744be
JB		 985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 987 return;
e59bd25d
AV		 988
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 992 adapter->hw_csum_rx_error++;
993 return;
994 }
e59bd25d
AV		 995
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
997 return;
998
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002 /*
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 * checksum errors.
1005 */
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008 return;
1009
e59bd25d
AV		 1010 adapter->hw_csum_rx_error++;
1011 return;
1012 }
1013
9a799d71 1014 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1016}
1017
e8e26350
PW		 1018static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1020{
1021 /*
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1025 * such as IA-64).
1026 */
1027 wmb();
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029}
1030
9a799d71
AK		 1031/**
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1034 **/
1035static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 1036 struct ixgbe_ring *rx_ring,
1037 int cleaned_count)
9a799d71 1038{
d716a7d8 1039 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1042 struct ixgbe_rx_buffer *bi;
9a799d71 1043 unsigned int i;
d716a7d8 1044 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1045
1046 i = rx_ring->next_to_use;
3a581073 1047 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1048
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
762f4c57 1052 if (!bi->page_dma &&
6e455b89 1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1054 if (!bi->page) {
d716a7d8 1055 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1056 if (!bi->page) {
1057 adapter->alloc_rx_page_failed++;
1058 goto no_buffers;
1059 }
1060 bi->page_offset = 0;
1061 } else {
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1064 }
762f4c57 1065
1b507730 1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 1067 bi->page_offset,
1068 (PAGE_SIZE / 2),
1b507730 1069 DMA_FROM_DEVICE);
9a799d71
AK		 1070 }
1071
3a581073 1072 if (!bi->skb) {
d716a7d8
AD		 1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074 bufsz);
1075 bi->skb = skb;
9a799d71
AK		 1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
d716a7d8
AD		 1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1083 }
9a799d71 1084
d716a7d8
AD		 1085 if (!bi->dma) {
1086 bi->dma = dma_map_single(&pdev->dev,
1087 bi->skb->data,
4f57ca6e 1088 rx_ring->rx_buf_len,
1b507730 1089 DMA_FROM_DEVICE);
9a799d71
AK		 1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
6e455b89 1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1096 } else {
3a581073 1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
3a581073 1103 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1104 }
7c6e0a43 1105
9a799d71
AK		 1106no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
e8e26350 1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1113 }
1114}
1115
7c6e0a43
JB		 1116static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117{
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119}
1120
1121static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122{
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124}
1125
f8212f97
AD		 1126static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127{
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131}
1132
1133/**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
94b982b2 1136 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
94b982b2
MC		 1142static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
f8212f97
AD		 1144{
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
94b982b2 1152 *count += 1;
f8212f97
AD		 1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161}
1162
43634e82
MC		 1163struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
e8171aaa 1165 bool delay_unmap;
43634e82
MC		 1166};
1167
1168#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
78b6f4ce 1170static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
9a799d71 1173{
78b6f4ce 1174 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1175 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
f8212f97 1180 unsigned int i, rsc_count = 0;
7c6e0a43 1181 u32 len, staterr;
177db6ff
MC		 1182 u16 hdr_info;
1183 bool cleaned = false;
9a799d71 1184 int cleaned_count = 0;
d2f4fbe2 1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1186#ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188#endif /* IXGBE_FCOE */
9a799d71
AK		 1189
1190 i = rx_ring->next_to_clean;
9a799d71
AK		 1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1196 u32 upper_len = 0;
9a799d71
AK		 1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
3c945e5b 1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1210 } else {
9a799d71 1211 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1212 }
9a799d71
AK		 1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
7ca3bc58 1216 prefetch(skb->data);
9a799d71
AK		 1217 rx_buffer_info->skb = NULL;
1218
21fa4e66 1219 if (rx_buffer_info->dma) {
43634e82
MC		 1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1222 (!(skb->prev))) {
43634e82
MC		 1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
e8171aaa 1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1232 } else {
1b507730 1233 dma_unmap_single(&pdev->dev,
e8171aaa 1234 rx_buffer_info->dma,
43634e82 1235 rx_ring->rx_buf_len,
e8171aaa
MC		 1236 DMA_FROM_DEVICE);
1237 }
4f57ca6e 1238 rx_buffer_info->dma = 0;
9a799d71
AK		 1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1b507730
NN		 1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
9a799d71
AK		 1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
9a799d71
AK		 1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
9a799d71 1268 cleaned_count++;
f8212f97 1269
0c19d6af 1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
9a799d71 1281 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1282 if (skb->prev)
94b982b2
MC		 1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
43634e82 1288 rx_ring->rx_buf_len,
1b507730 1289 DMA_FROM_DEVICE);
fd3686a8 1290 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1292 }
94b982b2
MC		 1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
9a799d71
AK		 1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
6e455b89 1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
7ca3bc58 1311 rx_ring->non_eop_descs++;
9a799d71
AK		 1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
8bae1b2b 1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
74ce8dd2 1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1327#ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
332d4a7d 1332 goto next_desc;
3d8fd385 1333 }
332d4a7d 1334#endif /* IXGBE_FCOE */
fdaff1ce 1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1336
1337next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
f8212f97 1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1351 }
1352
9a799d71
AK		 1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
3d8fd385
YZ		 1359#ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372#endif /* IXGBE_FCOE */
1373
f494e8fa
AV		 1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1378
9a799d71
AK		 1379 return cleaned;
1380}
1381
021230d4 1382static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1383/**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391{
021230d4
AV		 1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
9a799d71 1395
021230d4 1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1397
4df10466
JB		 1398 /*
1399 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1403 q_vector = adapter->q_vector[v_idx];
984b3f57 1404 /* XXX for_each_set_bit(...) */
021230d4 1405 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1406 adapter->num_rx_queues);
021230d4
AV		 1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1409 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1411 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1412 adapter->num_rx_queues,
1413 r_idx + 1);
021230d4
AV		 1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1416 adapter->num_tx_queues);
021230d4
AV		 1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1419 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1421 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1422 adapter->num_tx_queues,
1423 r_idx + 1);
021230d4
AV		 1424 }
1425
021230d4 1426 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1429 else if (q_vector->rxr_count)
f7554a2b
NS		 1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1432
fe49f04a 1433 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1434 }
1435
e8e26350
PW		 1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438 v_idx);
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
41fb9248 1443 /* set up to autoclear timer, and the vectors */
021230d4 1444 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1448 IXGBE_EIMS_LSC);
1449 else
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1452}
1453
f494e8fa
AV		 1454enum latency_range {
1455 lowest_latency = 0,
1456 low_latency = 1,
1457 bulk_latency = 2,
1458 latency_invalid = 255
1459};
1460
1461/**
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1468 *
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1478 **/
1479static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
f494e8fa
AV		 1482{
1483 unsigned int retval = itr_setting;
1484 u32 timepassed_us;
1485 u64 bytes_perint;
1486
1487 if (packets == 0)
1488 goto update_itr_done;
1489
1490
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1495 */
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1504 break;
1505 case low_latency:
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1510 break;
1511 case bulk_latency:
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1514 break;
1515 }
1516
1517update_itr_done:
1518 return retval;
1519}
1520
509ee935
JB		 1521/**
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1523 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1524 *
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1528 */
fe49f04a 1529void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1530{
fe49f04a 1531 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1532 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
509ee935
JB		 1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1540 /*
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1544 */
1545 if (itr_reg == 8 &&
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547 itr_reg = 0;
1548
509ee935
JB		 1549 /*
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1552 */
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554 }
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556}
1557
f494e8fa
AV		 1558static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559{
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1561 u32 new_itr;
1562 u8 current_itr, ret_itr;
fe49f04a 1563 int i, r_idx;
f494e8fa
AV		 1564 struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1568 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1570 q_vector->tx_itr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
f494e8fa
AV		 1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
30efa5a3 1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1576 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1578 r_idx + 1);
f494e8fa
AV		 1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1583 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1585 q_vector->rx_itr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
f494e8fa
AV		 1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
30efa5a3 1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1591 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1593 r_idx + 1);
f494e8fa
AV		 1594 }
1595
30efa5a3 1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1597
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1601 new_itr = 100000;
1602 break;
1603 case low_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1605 break;
1606 case bulk_latency:
1607 default:
1608 new_itr = 8000;
1609 break;
1610 }
1611
1612 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1615
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
fe49f04a
AD		 1618
1619 ixgbe_write_eitr(q_vector);
f494e8fa 1620 }
f494e8fa
AV		 1621}
1622
119fc60a
MC		 1623/**
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1626 **/
1627static void ixgbe_check_overtemp_task(struct work_struct *work)
1628{
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1634
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1638 u32 autoneg;
1639 bool link_up = false;
1640
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648 break;
1649 }
1650 return;
1651 default:
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653 return;
1654 break;
1655 }
396e799c
ET		 1656 e_crit(drv, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
849c4542
ET		 1658 "persists, power off the system and replace the "
1659 "adapter\n");
119fc60a
MC		 1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662 }
1663}
1664
0befdb3e
JB		 1665static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666{
1667 struct ixgbe_hw *hw = &adapter->hw;
1668
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1671 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674 }
1675}
cf8280ee 1676
e8e26350
PW		 1677static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678{
1679 struct ixgbe_hw *hw = &adapter->hw;
1680
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1689 } else {
1690 /* Interrupt isn't for us... */
1691 return;
1692 }
1693}
1694
cf8280ee
JB		 1695static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696{
1697 struct ixgbe_hw *hw = &adapter->hw;
1698
1699 adapter->lsc_int++;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1704 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1705 schedule_work(&adapter->watchdog_task);
1706 }
1707}
1708
9a799d71
AK		 1709static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710{
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1714 u32 eicr;
1715
1716 /*
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1721 */
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1724
cf8280ee
JB		 1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
d4f80882 1727
1cdd1ec8
GR		 1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1730
e8e26350
PW		 1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1733
c4cf55e5 1734 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1735 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1740
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743 int i;
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
4a0b9ca0 1749 adapter->tx_ring[i];
c4cf55e5
PWJ		 1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1753 }
1754 }
1755 }
d4f80882
AV		 1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1758
1759 return IRQ_HANDLED;
1760}
1761
fe49f04a
AD		 1762static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763 u64 qmask)
1764{
1765 u32 mask;
1766
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770 } else {
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775 }
1776 /* skip the flush */
1777}
1778
1779static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780 u64 qmask)
1781{
1782 u32 mask;
1783
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787 } else {
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792 }
1793 /* skip the flush */
1794}
1795
9a799d71
AK		 1796static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797{
021230d4
AV		 1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1800 struct ixgbe_ring *tx_ring;
021230d4
AV		 1801 int i, r_idx;
1802
1803 if (!q_vector->txr_count)
1804 return IRQ_HANDLED;
1805
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1808 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
021230d4 1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1812 r_idx + 1);
021230d4 1813 }
9a799d71 1814
9b471446 1815 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1816 napi_schedule(&q_vector->napi);
1817
9a799d71
AK		 1818 return IRQ_HANDLED;
1819}
1820
021230d4
AV		 1821/**
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @irq: unused
1824 * @data: pointer to our q_vector struct for this interrupt vector
1825 **/
9a799d71
AK		 1826static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827{
021230d4
AV		 1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1830 struct ixgbe_ring *rx_ring;
021230d4 1831 int r_idx;
30efa5a3 1832 int i;
021230d4
AV		 1833
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1835 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1836 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840 r_idx + 1);
1841 }
1842
021230d4
AV		 1843 if (!q_vector->rxr_count)
1844 return IRQ_HANDLED;
1845
021230d4 1846 /* disable interrupts on this vector only */
9b471446 1847 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1848 napi_schedule(&q_vector->napi);
021230d4
AV		 1849
1850 return IRQ_HANDLED;
1851}
1852
1853static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854{
91281fd3
AD		 1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1858 int r_idx;
1859 int i;
1860
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1862 return IRQ_HANDLED;
1863
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1866 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870 r_idx + 1);
1871 }
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1875 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
9b471446 1882 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1883 napi_schedule(&q_vector->napi);
9a799d71 1884
9a799d71
AK		 1885 return IRQ_HANDLED;
1886}
1887
021230d4
AV		 1888/**
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1892 *
f0848276
JB		 1893 * This function is optimized for cleaning one queue only on a single
1894 * q_vector!!!
021230d4 1895 **/
9a799d71
AK		 1896static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897{
021230d4 1898 struct ixgbe_q_vector *q_vector =
b4617240 1899 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1900 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1901 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1902 int work_done = 0;
021230d4 1903 long r_idx;
9a799d71 1904
021230d4 1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1906 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1907#ifdef CONFIG_IXGBE_DCA
bd0362dd 1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1909 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1910#endif
9a799d71 1911
78b6f4ce 1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1913
021230d4
AV		 1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
288379f0 1916 napi_complete(napi);
f7554a2b 1917 if (adapter->rx_itr_setting & 1)
f494e8fa 1918 ixgbe_set_itr_msix(q_vector);
9a799d71 1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1922 }
1923
1924 return work_done;
1925}
1926
f0848276 1927/**
91281fd3 1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1931 *
1932 * This function will clean more than one rx queue associated with a
1933 * q_vector.
1934 **/
91281fd3 1935static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1936{
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1940 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1941 int work_done = 0, i;
1942 long r_idx;
91281fd3
AD		 1943 bool tx_clean_complete = true;
1944
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1947 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1948#ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1951#endif
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954 r_idx + 1);
1955 }
f0848276
JB		 1956
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1963 ring = adapter->rx_ring[r_idx];
5dd2d332 1964#ifdef CONFIG_IXGBE_DCA
f0848276 1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1966 ixgbe_update_rx_dca(adapter, ring);
f0848276 1967#endif
91281fd3 1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970 r_idx + 1);
1971 }
1972
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1974 ring = adapter->rx_ring[r_idx];
f0848276 1975 /* If all Rx work done, exit the polling mode */
7f821875 1976 if (work_done < budget) {
288379f0 1977 napi_complete(napi);
f7554a2b 1978 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1983 return 0;
1984 }
1985
1986 return work_done;
1987}
91281fd3
AD		 1988
1989/**
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1993 *
1994 * This function is optimized for cleaning one queue only on a single
1995 * q_vector!!!
1996 **/
1997static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998{
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2003 int work_done = 0;
2004 long r_idx;
2005
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2007 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2008#ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2011#endif
2012
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014 work_done = budget;
2015
f7554a2b 2016 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2017 if (work_done < budget) {
2018 napi_complete(napi);
f7554a2b 2019 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023 }
2024
2025 return work_done;
2026}
2027
021230d4 2028static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 2029 int r_idx)
021230d4 2030{
7a921c93
AD		 2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
021230d4
AV		 2035}
2036
2037static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 2038 int t_idx)
021230d4 2039{
7a921c93
AD		 2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
021230d4
AV		 2044}
2045
9a799d71 2046/**
021230d4
AV		 2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
9a799d71 2050 *
021230d4
AV		 2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
9a799d71 2056 **/
021230d4 2057static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 2058 int vectors)
021230d4
AV		 2059{
2060 int v_start = 0;
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2064 int i, j;
2065 int rqpv, tqpv;
2066 int err = 0;
2067
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070 goto out;
9a799d71 2071
021230d4
AV		 2072 /*
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2075 */
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2079
021230d4
AV		 2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2082
9a799d71 2083 goto out;
021230d4 2084 }
9a799d71 2085
021230d4
AV		 2086 /*
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2090 */
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2096 rxr_idx++;
2097 rxr_remaining--;
2098 }
2099 }
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2104 txr_idx++;
2105 txr_remaining--;
9a799d71 2106 }
9a799d71
AK		 2107 }
2108
021230d4
AV		 2109out:
2110 return err;
2111}
2112
2113/**
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2116 *
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2119 **/
2120static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121{
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
cb13fc20 2125 int ri=0, ti=0;
021230d4
AV		 2126
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132 if (err)
2133 goto out;
2134
2135#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
021230d4 2138 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2139 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 2140
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2144 }
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2148 }
2149 else
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2152
021230d4 2153 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 2154 handler, 0, adapter->name[vector],
7a921c93 2155 adapter->q_vector[vector]);
9a799d71 2156 if (err) {
396e799c 2157 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2158 "Error: %d\n", err);
021230d4 2159 goto free_queue_irqs;
9a799d71 2160 }
9a799d71
AK		 2161 }
2162
021230d4
AV		 2163 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2165 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2166 if (err) {
396e799c 2167 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2168 goto free_queue_irqs;
9a799d71
AK		 2169 }
2170
9a799d71
AK		 2171 return 0;
2172
021230d4
AV		 2173free_queue_irqs:
2174 for (i = vector - 1; i >= 0; i--)
2175 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 2176 adapter->q_vector[i]);
021230d4
AV		 2177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2179 kfree(adapter->msix_entries);
2180 adapter->msix_entries = NULL;
021230d4 2181out:
9a799d71
AK		 2182 return err;
2183}
2184
f494e8fa
AV		 2185static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186{
7a921c93 2187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2188 u8 current_itr;
2189 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2190 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2192
30efa5a3 2193 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2194 q_vector->tx_itr,
2195 tx_ring->total_packets,
2196 tx_ring->total_bytes);
30efa5a3 2197 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2198 q_vector->rx_itr,
2199 rx_ring->total_packets,
2200 rx_ring->total_bytes);
f494e8fa 2201
30efa5a3 2202 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2203
2204 switch (current_itr) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency:
2207 new_itr = 100000;
2208 break;
2209 case low_latency:
2210 new_itr = 20000; /* aka hwitr = ~200 */
2211 break;
2212 case bulk_latency:
2213 new_itr = 8000;
2214 break;
2215 default:
2216 break;
2217 }
2218
2219 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2220 /* do an exponential smoothing */
2221 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2222
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector->eitr = new_itr;
fe49f04a
AD		 2225
2226 ixgbe_write_eitr(q_vector);
f494e8fa 2227 }
f494e8fa
AV		 2228}
2229
79aefa45
AD		 2230/**
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2233 **/
2234static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235{
2236 u32 mask;
835462fc
NS		 2237
2238 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2239 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2241 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2243 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2244 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2245 mask |= IXGBE_EIMS_GPI_SDP1;
2246 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2247 if (adapter->num_vfs)
2248 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2249 }
c4cf55e5
PWJ		 2250 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2253
79aefa45 2254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2255 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2256 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2257
2258 if (adapter->num_vfs > 32) {
2259 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261 }
79aefa45 2262}
021230d4 2263
9a799d71 2264/**
021230d4 2265 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
9a799d71
AK		 2268 **/
2269static irqreturn_t ixgbe_intr(int irq, void *data)
2270{
2271 struct net_device *netdev = data;
2272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2274 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2275 u32 eicr;
2276
54037505
DS		 2277 /*
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2280 */
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
021230d4
AV		 2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2286 if (!eicr) {
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter);
9a799d71 2291 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2292 }
9a799d71 2293
cf8280ee
JB		 2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
021230d4 2296
e8e26350
PW		 2297 if (hw->mac.type == ixgbe_mac_82599EB)
2298 ixgbe_check_sfp_event(adapter, eicr);
2299
0befdb3e 2300 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2301 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2304
7a921c93 2305 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2306 adapter->tx_ring[0]->total_packets = 0;
2307 adapter->tx_ring[0]->total_bytes = 0;
2308 adapter->rx_ring[0]->total_packets = 0;
2309 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2310 /* would disable interrupts here but EIAM disabled it */
7a921c93 2311 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2312 }
2313
2314 return IRQ_HANDLED;
2315}
2316
021230d4
AV		 2317static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318{
2319 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321 for (i = 0; i < q_vectors; i++) {
7a921c93 2322 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2323 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325 q_vector->rxr_count = 0;
2326 q_vector->txr_count = 0;
2327 }
2328}
2329
9a799d71
AK		 2330/**
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2333 *
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2336 **/
021230d4 2337static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2338{
2339 struct net_device *netdev = adapter->netdev;
021230d4 2340 int err;
9a799d71 2341
021230d4
AV		 2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 err = ixgbe_request_msix_irqs(adapter);
2344 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2345 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 2346 netdev->name, netdev);
021230d4 2347 } else {
a0607fd3 2348 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 2349 netdev->name, netdev);
9a799d71
AK		 2350 }
2351
9a799d71 2352 if (err)
396e799c 2353 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2354
9a799d71
AK		 2355 return err;
2356}
2357
2358static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359{
2360 struct net_device *netdev = adapter->netdev;
2361
2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2363 int i, q_vectors;
9a799d71 2364
021230d4
AV		 2365 q_vectors = adapter->num_msix_vectors;
2366
2367 i = q_vectors - 1;
9a799d71 2368 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2369
021230d4
AV		 2370 i--;
2371 for (; i >= 0; i--) {
2372 free_irq(adapter->msix_entries[i].vector,
7a921c93 2373 adapter->q_vector[i]);
021230d4
AV		 2374 }
2375
2376 ixgbe_reset_q_vectors(adapter);
2377 } else {
2378 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2379 }
2380}
2381
22d5a71b
JB		 2382/**
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2385 **/
2386static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387{
835462fc
NS		 2388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390 } else {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2394 if (adapter->num_vfs > 32)
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2396 }
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
2398 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399 int i;
2400 for (i = 0; i < adapter->num_msix_vectors; i++)
2401 synchronize_irq(adapter->msix_entries[i].vector);
2402 } else {
2403 synchronize_irq(adapter->pdev->irq);
2404 }
2405}
2406
9a799d71
AK		 2407/**
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409 *
2410 **/
2411static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412{
9a799d71
AK		 2413 struct ixgbe_hw *hw = &adapter->hw;
2414
021230d4 2415 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2416 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2417
e8e26350
PW		 2418 ixgbe_set_ivar(adapter, 0, 0, 0);
2419 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2420
2421 map_vector_to_rxq(adapter, 0, 0);
2422 map_vector_to_txq(adapter, 0, 0);
2423
396e799c 2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2425}
2426
43e69bf0
AD		 2427/**
2428 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429 * @adapter: board private structure
2430 * @ring: structure containing ring specific data
2431 *
2432 * Configure the Tx descriptor ring after a reset.
2433 **/
2434 static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435 struct ixgbe_ring *ring)
2436{
2437 struct ixgbe_hw *hw = &adapter->hw;
2438 u64 tdba = ring->dma;
2439 u16 reg_idx = ring->reg_idx;
2440
2441 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2442 (tdba & DMA_BIT_MASK(32)));
2443 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2444 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2445 ring->count * sizeof(union ixgbe_adv_tx_desc));
2446 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2447 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2448 ring->head = IXGBE_TDH(reg_idx);
2449 ring->tail = IXGBE_TDT(reg_idx);
2450
2451}
2452
120ff942
AD		 2453static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2454{
2455 struct ixgbe_hw *hw = &adapter->hw;
2456 u32 rttdcs;
2457 u32 mask;
2458
2459 if (hw->mac.type == ixgbe_mac_82598EB)
2460 return;
2461
2462 /* disable the arbiter while setting MTQC */
2463 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2464 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2465 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2466
2467 /* set transmit pool layout */
2468 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2469 switch (adapter->flags & mask) {
2470
2471 case (IXGBE_FLAG_SRIOV_ENABLED):
2472 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2473 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2474 break;
2475
2476 case (IXGBE_FLAG_DCB_ENABLED):
2477 /* We enable 8 traffic classes, DCB only */
2478 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2479 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2480 break;
2481
2482 default:
2483 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2484 break;
2485 }
2486
2487 /* re-enable the arbiter */
2488 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2489 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2490}
2491
9a799d71 2492/**
3a581073 2493 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2494 * @adapter: board private structure
2495 *
2496 * Configure the Tx unit of the MAC after a reset.
2497 **/
2498static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2499{
43e69bf0 2500 u32 i;
9a799d71
AK		 2501
2502 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2503 for (i = 0; i < adapter->num_tx_queues; i++)
2504 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
ee5f784a 2505
120ff942 2506 ixgbe_setup_mtqc(adapter);
9a799d71
AK		 2507}
2508
e8e26350 2509#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2510
a6616b42
YZ		 2511static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2512 struct ixgbe_ring *rx_ring)
cc41ac7c 2513{
cc41ac7c 2514 u32 srrctl;
a6616b42 2515 int index;
0cefafad 2516 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2517
a6616b42
YZ		 2518 index = rx_ring->reg_idx;
2519 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2520 unsigned long mask;
0cefafad 2521 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2522 index = index & mask;
cc41ac7c 2523 }
cc41ac7c
JB		 2524 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2525
2526 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2527 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2528
afafd5b0
AD		 2529 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2530 IXGBE_SRRCTL_BSIZEHDR_MASK;
2531
6e455b89 2532 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2533#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535#else
2536 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537#endif
cc41ac7c 2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2539 } else {
afafd5b0
AD		 2540 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2541 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2542 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2543 }
e8e26350 2544
cc41ac7c
JB		 2545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2546}
9a799d71 2547
05abb126 2548static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2549{
05abb126
AD		 2550 struct ixgbe_hw *hw = &adapter->hw;
2551 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554 u32 mrqc = 0, reta = 0;
2555 u32 rxcsum;
2556 int i, j;
0cefafad
JB		 2557 int mask;
2558
05abb126
AD		 2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
2565 if (j == adapter->ring_feature[RING_F_RSS].indices)
2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
0cefafad 2573
05abb126
AD		 2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2580 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2581 else
2582 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2583#ifdef CONFIG_IXGBE_DCB
05abb126 2584 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2585#endif
05abb126
AD		 2586 | IXGBE_FLAG_SRIOV_ENABLED
2587 );
0cefafad
JB		 2588
2589 switch (mask) {
2590 case (IXGBE_FLAG_RSS_ENABLED):
2591 mrqc = IXGBE_MRQC_RSSEN;
2592 break;
1cdd1ec8
GR		 2593 case (IXGBE_FLAG_SRIOV_ENABLED):
2594 mrqc = IXGBE_MRQC_VMDQEN;
2595 break;
0cefafad
JB		 2596#ifdef CONFIG_IXGBE_DCB
2597 case (IXGBE_FLAG_DCB_ENABLED):
2598 mrqc = IXGBE_MRQC_RT8TCEN;
2599 break;
2600#endif /* CONFIG_IXGBE_DCB */
2601 default:
2602 break;
2603 }
2604
05abb126
AD		 2605 /* Perform hash on these packet types */
2606 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608 | IXGBE_MRQC_RSS_FIELD_IPV6
2609 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2612}
2613
bb5a9ad2
NS		 2614/**
2615 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616 * @adapter: address of board private structure
2617 * @index: index of ring to set
bb5a9ad2 2618 **/
edd2ea55 2619static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2620{
2621 struct ixgbe_ring *rx_ring;
2622 struct ixgbe_hw *hw = &adapter->hw;
2623 int j;
2624 u32 rscctrl;
edd2ea55 2625 int rx_buf_len;
bb5a9ad2 2626
4a0b9ca0 2627 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2628 j = rx_ring->reg_idx;
edd2ea55 2629 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2630 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2631 rscctrl |= IXGBE_RSCCTL_RSCEN;
2632 /*
2633 * we must limit the number of descriptors so that the
2634 * total size of max desc * buf_len is not greater
2635 * than 65535
2636 */
2637 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2638#if (MAX_SKB_FRAGS > 16)
2639 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2640#elif (MAX_SKB_FRAGS > 8)
2641 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2642#elif (MAX_SKB_FRAGS > 4)
2643 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2644#else
2645 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2646#endif
2647 } else {
2648 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2649 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2650 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2651 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2652 else
2653 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2654 }
2655 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2656}
2657
acd37177
AD		 2658static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2659 struct ixgbe_ring *ring)
2660{
2661 struct ixgbe_hw *hw = &adapter->hw;
2662 u64 rdba = ring->dma;
2663 u16 reg_idx = ring->reg_idx;
2664
2665 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2666 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2667 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2668 ring->count * sizeof(union ixgbe_adv_rx_desc));
2669 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2670 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2671 ring->head = IXGBE_RDH(reg_idx);
2672 ring->tail = IXGBE_RDT(reg_idx);
2673}
2674
48654521
AD		 2675static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2676{
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 int p;
2679
2680 /* PSRTYPE must be initialized in non 82598 adapters */
2681 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2682 IXGBE_PSRTYPE_UDPHDR |
2683 IXGBE_PSRTYPE_IPV4HDR |
2684 IXGBE_PSRTYPE_L2HDR |
2685 IXGBE_PSRTYPE_IPV6HDR;
2686
2687 if (hw->mac.type == ixgbe_mac_82598EB)
2688 return;
2689
2690 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2691 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2692
2693 for (p = 0; p < adapter->num_rx_pools; p++)
2694 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2695 psrtype);
2696}
2697
477de6ed 2698static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2699{
9a799d71
AK		 2700 struct ixgbe_hw *hw = &adapter->hw;
2701 struct net_device *netdev = adapter->netdev;
2702 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2703 int rx_buf_len;
477de6ed
AD		 2704 struct ixgbe_ring *rx_ring;
2705 int i;
2706 u32 mhadd, hlreg0;
48654521 2707
9a799d71 2708 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2709 /* Do not use packet split if we're in SR-IOV Mode */
2710 if (!adapter->num_vfs)
2711 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2712
2713 /* Set the RX buffer length according to the mode */
2714 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2715 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2716 } else {
0c19d6af 2717 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2718 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2719 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2720 else
477de6ed 2721 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2722 }
2723
63f39bd1 2724#ifdef IXGBE_FCOE
477de6ed
AD		 2725 /* adjust max frame to be able to do baby jumbo for FCoE */
2726 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2727 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2728 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2729
477de6ed
AD		 2730#endif /* IXGBE_FCOE */
2731 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2732 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2733 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2734 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2735
2736 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2737 }
2738
2739 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2740 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2741 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2742 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2743
0cefafad
JB		 2744 /*
2745 * Setup the HW Rx Head and Tail Descriptor Pointers and
2746 * the Base and Length of the Rx Descriptor Ring
2747 */
9a799d71 2748 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2749 rx_ring = adapter->rx_ring[i];
a6616b42 2750 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2751
6e455b89
YZ		 2752 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2753 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2754 else
2755 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2756
63f39bd1 2757#ifdef IXGBE_FCOE
477de6ed
AD		 2758 if (netdev->features & NETIF_F_FCOE_MTU)
2759 {
63f39bd1
YZ		 2760 struct ixgbe_ring_feature *f;
2761 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2762 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2763 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2764 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2765 rx_ring->rx_buf_len =
2766 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2767 }
63f39bd1 2768 }
63f39bd1 2769#endif /* IXGBE_FCOE */
477de6ed
AD		 2770 }
2771
2772}
2773
2774/**
2775 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2776 * @adapter: board private structure
2777 *
2778 * Configure the Rx unit of the MAC after a reset.
2779 **/
2780static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2781{
2782 struct ixgbe_hw *hw = &adapter->hw;
2783 struct ixgbe_ring *rx_ring;
2784 int i;
2785 u32 rxctrl;
2786 u32 gcr_ext;
2787 u32 rdrxctl;
2788
2789 /* disable receives while setting up the descriptors */
2790 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2791 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2792
2793 ixgbe_setup_psrtype(adapter);
2794
2795 /* set_rx_buffer_len must be called before ring initialization */
2796 ixgbe_set_rx_buffer_len(adapter);
2797
2798 /*
2799 * Setup the HW Rx Head and Tail Descriptor Pointers and
2800 * the Base and Length of the Rx Descriptor Ring
2801 */
2802 for (i = 0; i < adapter->num_rx_queues; i++) {
2803 rx_ring = adapter->rx_ring[i];
acd37177 2804 ixgbe_configure_rx_ring(adapter, rx_ring);
a6616b42 2805 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2806 }
2807
e8e26350
PW		 2808 if (hw->mac.type == ixgbe_mac_82598EB) {
2809 /*
2810 * For VMDq support of different descriptor types or
2811 * buffer sizes through the use of multiple SRRCTL
2812 * registers, RDRXCTL.MVMEN must be set to 1
2813 *
2814 * also, the manual doesn't mention it clearly but DCA hints
2815 * will only use queue 0's tags unless this bit is set. Side
2816 * effects of setting this bit are only that SRRCTL must be
2817 * fully programmed [0..15]
2818 */
2a41ff81
JB		 2819 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2820 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2821 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2822 }
177db6ff 2823
1cdd1ec8
GR		 2824 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2825 u32 vt_reg_bits;
2826 u32 reg_offset, vf_shift;
2827 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2828 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2829 | IXGBE_VT_CTL_REPLEN;
2830 vt_reg_bits |= (adapter->num_vfs <<
2831 IXGBE_VT_CTL_POOL_SHIFT);
2832 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2833 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2834
2835 vf_shift = adapter->num_vfs % 32;
2836 reg_offset = adapter->num_vfs / 32;
2837 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2838 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2839 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2840 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2841 /* Enable only the PF's pool for Tx/Rx */
2842 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2843 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2844 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
1cdd1ec8
GR		 2845 }
2846
e8e26350 2847 /* Program MRQC for the distribution of queues */
05abb126 2848 ixgbe_setup_mrqc(adapter);
9a799d71 2849
1cdd1ec8 2850 if (adapter->num_vfs) {
1cdd1ec8
GR		 2851 /* Map PF MAC address in RAR Entry 0 to first pool
2852 * following VFs */
2853 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2854
2855 /* Set up VF register offsets for selected VT Mode, i.e.
2856 * 64 VFs for SR-IOV */
826437d3
AD		 2857 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2858 gcr_ext |= IXGBE_GCR_EXT_SRIOV;
2859 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
1cdd1ec8
GR		 2860 }
2861
e8e26350
PW		 2862 if (hw->mac.type == ixgbe_mac_82599EB) {
2863 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2864 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2865 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2866 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2867 }
f8212f97 2868
0c19d6af 2869 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2870 /* Enable 82599 HW-RSC */
bb5a9ad2 2871 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2872 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2873
f8212f97
AD		 2874 /* Disable RSC for ACK packets */
2875 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2876 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2877 }
9a799d71
AK		 2878}
2879
068c89b0
DS		 2880static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2881{
2882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2883 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2884 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2885
2886 /* add VID to filter table */
1ada1b1b 2887 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2888}
2889
2890static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2891{
2892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2893 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2894 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2895
2896 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2897 ixgbe_irq_disable(adapter);
2898
2899 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2900
2901 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2902 ixgbe_irq_enable(adapter);
2903
2904 /* remove VID from filter table */
1ada1b1b 2905 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2906}
2907
5f6c0181
JB		 2908/**
2909 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2910 * @adapter: driver data
2911 */
2912static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2913{
2914 struct ixgbe_hw *hw = &adapter->hw;
2915 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2916 int i, j;
2917
2918 switch (hw->mac.type) {
2919 case ixgbe_mac_82598EB:
38e0bd98
YZ		 2920 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2921#ifdef CONFIG_IXGBE_DCB
2922 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2923 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2924#endif
5f6c0181
JB		 2925 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2926 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2927 break;
2928 case ixgbe_mac_82599EB:
2929 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2930 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2931 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 2932#ifdef CONFIG_IXGBE_DCB
2933 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2934 break;
2935#endif
5f6c0181
JB		 2936 for (i = 0; i < adapter->num_rx_queues; i++) {
2937 j = adapter->rx_ring[i]->reg_idx;
2938 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2939 vlnctrl &= ~IXGBE_RXDCTL_VME;
2940 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2941 }
2942 break;
2943 default:
2944 break;
2945 }
2946}
2947
2948/**
2949 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2950 * @adapter: driver data
2951 */
2952static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2953{
2954 struct ixgbe_hw *hw = &adapter->hw;
2955 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2956 int i, j;
2957
2958 switch (hw->mac.type) {
2959 case ixgbe_mac_82598EB:
2960 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2961 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2962 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2963 break;
2964 case ixgbe_mac_82599EB:
2965 vlnctrl |= IXGBE_VLNCTRL_VFE;
2966 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2967 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2968 for (i = 0; i < adapter->num_rx_queues; i++) {
2969 j = adapter->rx_ring[i]->reg_idx;
2970 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2971 vlnctrl |= IXGBE_RXDCTL_VME;
2972 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2973 }
2974 break;
2975 default:
2976 break;
2977 }
2978}
2979
9a799d71 2980static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2981 struct vlan_group *grp)
9a799d71
AK		 2982{
2983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2984
d4f80882
AV		 2985 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2986 ixgbe_irq_disable(adapter);
9a799d71
AK		 2987 adapter->vlgrp = grp;
2988
2f90b865
AD		 2989 /*
2990 * For a DCB driver, always enable VLAN tag stripping so we can
2991 * still receive traffic from a DCB-enabled host even if we're
2992 * not in DCB mode.
2993 */
5f6c0181 2994 ixgbe_vlan_filter_enable(adapter);
dc63d377 2995
e8e26350 2996 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2997
d4f80882
AV		 2998 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2999 ixgbe_irq_enable(adapter);
9a799d71
AK		 3000}
3001
9a799d71
AK		 3002static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3003{
3004 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3005
3006 if (adapter->vlgrp) {
3007 u16 vid;
3008 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3009 if (!vlan_group_get_device(adapter->vlgrp, vid))
3010 continue;
3011 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3012 }
3013 }
3014}
3015
2850062a
AD		 3016/**
3017 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3018 * @netdev: network interface device structure
3019 *
3020 * Writes unicast address list to the RAR table.
3021 * Returns: -ENOMEM on failure/insufficient address space
3022 * 0 on no addresses written
3023 * X on writing X addresses to the RAR table
3024 **/
3025static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3026{
3027 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3028 struct ixgbe_hw *hw = &adapter->hw;
3029 unsigned int vfn = adapter->num_vfs;
3030 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3031 int count = 0;
3032
3033 /* return ENOMEM indicating insufficient memory for addresses */
3034 if (netdev_uc_count(netdev) > rar_entries)
3035 return -ENOMEM;
3036
3037 if (!netdev_uc_empty(netdev) && rar_entries) {
3038 struct netdev_hw_addr *ha;
3039 /* return error if we do not support writing to RAR table */
3040 if (!hw->mac.ops.set_rar)
3041 return -ENOMEM;
3042
3043 netdev_for_each_uc_addr(ha, netdev) {
3044 if (!rar_entries)
3045 break;
3046 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3047 vfn, IXGBE_RAH_AV);
3048 count++;
3049 }
3050 }
3051 /* write the addresses in reverse order to avoid write combining */
3052 for (; rar_entries > 0 ; rar_entries--)
3053 hw->mac.ops.clear_rar(hw, rar_entries);
3054
3055 return count;
3056}
3057
9a799d71 3058/**
2c5645cf 3059 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3060 * @netdev: network interface device structure
3061 *
2c5645cf
CL		 3062 * The set_rx_method entry point is called whenever the unicast/multicast
3063 * address list or the network interface flags are updated. This routine is
3064 * responsible for configuring the hardware for proper unicast, multicast and
3065 * promiscuous mode.
9a799d71 3066 **/
7f870475 3067void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3068{
3069 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3070 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3071 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3072 int count;
9a799d71
AK		 3073
3074 /* Check for Promiscuous and All Multicast modes */
3075
3076 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3077
f5dc442b
AD		 3078 /* set all bits that we expect to always be set */
3079 fctrl |= IXGBE_FCTRL_BAM;
3080 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3081 fctrl |= IXGBE_FCTRL_PMCF;
3082
2850062a
AD		 3083 /* clear the bits we are changing the status of */
3084 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3085
9a799d71 3086 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3087 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3088 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3089 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3090 /* don't hardware filter vlans in promisc mode */
3091 ixgbe_vlan_filter_disable(adapter);
9a799d71 3092 } else {
746b9f02
PM		 3093 if (netdev->flags & IFF_ALLMULTI) {
3094 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3095 vmolr |= IXGBE_VMOLR_MPE;
3096 } else {
3097 /*
3098 * Write addresses to the MTA, if the attempt fails
3099 * then we should just turn on promiscous mode so
3100 * that we can at least receive multicast traffic
3101 */
3102 hw->mac.ops.update_mc_addr_list(hw, netdev);
3103 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3104 }
5f6c0181 3105 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3106 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3107 /*
3108 * Write addresses to available RAR registers, if there is not
3109 * sufficient space to store all the addresses then enable
3110 * unicast promiscous mode
3111 */
3112 count = ixgbe_write_uc_addr_list(netdev);
3113 if (count < 0) {
3114 fctrl |= IXGBE_FCTRL_UPE;
3115 vmolr |= IXGBE_VMOLR_ROPE;
3116 }
9a799d71
AK		 3117 }
3118
2850062a 3119 if (adapter->num_vfs) {
1cdd1ec8 3120 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3121 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3122 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3123 IXGBE_VMOLR_ROPE);
3124 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3125 }
3126
3127 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
9a799d71
AK		 3128}
3129
021230d4
AV		 3130static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3131{
3132 int q_idx;
3133 struct ixgbe_q_vector *q_vector;
3134 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3135
3136 /* legacy and MSI only use one vector */
3137 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3138 q_vectors = 1;
3139
3140 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3141 struct napi_struct *napi;
7a921c93 3142 q_vector = adapter->q_vector[q_idx];
f0848276 3143 napi = &q_vector->napi;
91281fd3
AD		 3144 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3145 if (!q_vector->rxr_count || !q_vector->txr_count) {
3146 if (q_vector->txr_count == 1)
3147 napi->poll = &ixgbe_clean_txonly;
3148 else if (q_vector->rxr_count == 1)
3149 napi->poll = &ixgbe_clean_rxonly;
3150 }
3151 }
f0848276
JB		 3152
3153 napi_enable(napi);
021230d4
AV		 3154 }
3155}
3156
3157static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3158{
3159 int q_idx;
3160 struct ixgbe_q_vector *q_vector;
3161 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3162
3163 /* legacy and MSI only use one vector */
3164 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3165 q_vectors = 1;
3166
3167 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3168 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3169 napi_disable(&q_vector->napi);
3170 }
3171}
3172
7a6b6f51 3173#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3174/*
3175 * ixgbe_configure_dcb - Configure DCB hardware
3176 * @adapter: ixgbe adapter struct
3177 *
3178 * This is called by the driver on open to configure the DCB hardware.
3179 * This is also called by the gennetlink interface when reconfiguring
3180 * the DCB state.
3181 */
3182static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3183{
3184 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3185 u32 txdctl;
2f90b865
AD		 3186 int i, j;
3187
67ebd791
AD		 3188 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3189 if (hw->mac.type == ixgbe_mac_82598EB)
3190 netif_set_gso_max_size(adapter->netdev, 65536);
3191 return;
3192 }
3193
3194 if (hw->mac.type == ixgbe_mac_82598EB)
3195 netif_set_gso_max_size(adapter->netdev, 32768);
3196
2f90b865
AD		 3197 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3198 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3199 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3200
3201 /* reconfigure the hardware */
3202 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3203
3204 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3205 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3206 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3207 /* PThresh workaround for Tx hang with DFP enabled. */
3208 txdctl |= 32;
3209 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3210 }
3211 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3212 ixgbe_vlan_filter_enable(adapter);
3213
2f90b865
AD		 3214 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3215}
3216
3217#endif
9a799d71
AK		 3218static void ixgbe_configure(struct ixgbe_adapter *adapter)
3219{
3220 struct net_device *netdev = adapter->netdev;
c4cf55e5 3221 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3222 int i;
3223
2c5645cf 3224 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3225
3226 ixgbe_restore_vlan(adapter);
7a6b6f51 3227#ifdef CONFIG_IXGBE_DCB
67ebd791 3228 ixgbe_configure_dcb(adapter);
2f90b865 3229#endif
9a799d71 3230
eacd73f7
YZ		 3231#ifdef IXGBE_FCOE
3232 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3233 ixgbe_configure_fcoe(adapter);
3234
3235#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3236 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3237 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3238 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 3239 adapter->atr_sample_rate;
3240 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3241 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3242 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3243 }
3244
9a799d71
AK		 3245 ixgbe_configure_tx(adapter);
3246 ixgbe_configure_rx(adapter);
3247 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 3248 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3249 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 3250}
3251
e8e26350
PW		 3252static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3253{
3254 switch (hw->phy.type) {
3255 case ixgbe_phy_sfp_avago:
3256 case ixgbe_phy_sfp_ftl:
3257 case ixgbe_phy_sfp_intel:
3258 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3259 case ixgbe_phy_sfp_passive_tyco:
3260 case ixgbe_phy_sfp_passive_unknown:
3261 case ixgbe_phy_sfp_active_unknown:
3262 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3263 return true;
3264 default:
3265 return false;
3266 }
3267}
3268
0ecc061d 3269/**
e8e26350
PW		 3270 * ixgbe_sfp_link_config - set up SFP+ link
3271 * @adapter: pointer to private adapter struct
3272 **/
3273static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3274{
3275 struct ixgbe_hw *hw = &adapter->hw;
3276
3277 if (hw->phy.multispeed_fiber) {
3278 /*
3279 * In multispeed fiber setups, the device may not have
3280 * had a physical connection when the driver loaded.
3281 * If that's the case, the initial link configuration
3282 * couldn't get the MAC into 10G or 1G mode, so we'll
3283 * never have a link status change interrupt fire.
3284 * We need to try and force an autonegotiation
3285 * session, then bring up link.
3286 */
3287 hw->mac.ops.setup_sfp(hw);
3288 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3289 schedule_work(&adapter->multispeed_fiber_task);
3290 } else {
3291 /*
3292 * Direct Attach Cu and non-multispeed fiber modules
3293 * still need to be configured properly prior to
3294 * attempting link.
3295 */
3296 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3297 schedule_work(&adapter->sfp_config_module_task);
3298 }
3299}
3300
3301/**
3302 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3303 * @hw: pointer to private hardware struct
3304 *
3305 * Returns 0 on success, negative on failure
3306 **/
e8e26350 3307static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3308{
3309 u32 autoneg;
8620a103 3310 bool negotiation, link_up = false;
0ecc061d
PWJ		 3311 u32 ret = IXGBE_ERR_LINK_SETUP;
3312
3313 if (hw->mac.ops.check_link)
3314 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3315
3316 if (ret)
3317 goto link_cfg_out;
3318
3319 if (hw->mac.ops.get_link_capabilities)
8620a103 3320 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 3321 if (ret)
3322 goto link_cfg_out;
3323
8620a103
MC		 3324 if (hw->mac.ops.setup_link)
3325 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3326link_cfg_out:
3327 return ret;
3328}
3329
e8e26350
PW		 3330#define IXGBE_MAX_RX_DESC_POLL 10
3331static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3332 int rxr)
3333{
4a0b9ca0 3334 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 3335 int k;
3336
3337 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3338 if (IXGBE_READ_REG(&adapter->hw,
3339 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3340 break;
3341 else
3342 msleep(1);
3343 }
3344 if (k >= IXGBE_MAX_RX_DESC_POLL) {
396e799c 3345 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
849c4542 3346 "the polling period\n", rxr);
e8e26350 3347 }
4a0b9ca0
PW		 3348 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3349 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 3350}
3351
9a799d71
AK		 3352static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3353{
9a799d71 3354 struct ixgbe_hw *hw = &adapter->hw;
021230d4 3355 int i, j = 0;
e8e26350 3356 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 3357 int err;
477de6ed 3358 u32 txdctl, rxdctl;
e8e26350 3359 u32 dmatxctl;
021230d4 3360 u32 gpie;
c9205697 3361 u32 ctrl_ext;
9a799d71 3362
5eba3699
AV		 3363 ixgbe_get_hw_control(adapter);
3364
021230d4
AV		 3365 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3366 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 3367 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3368 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 3369 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 3370 } else {
3371 /* MSI only */
021230d4 3372 gpie = 0;
9a799d71 3373 }
1cdd1ec8
GR		 3374 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3375 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3376 gpie |= IXGBE_GPIE_VTMODE_64;
3377 }
021230d4
AV		 3378 /* XXX: to interrupt immediately for EICS writes, enable this */
3379 /* gpie |= IXGBE_GPIE_EIMEN; */
3380 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 3381 }
3382
9b471446
JB		 3383 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3384 /*
3385 * use EIAM to auto-mask when MSI-X interrupt is asserted
3386 * this saves a register write for every interrupt
3387 */
3388 switch (hw->mac.type) {
3389 case ixgbe_mac_82598EB:
3390 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3391 break;
3392 default:
3393 case ixgbe_mac_82599EB:
3394 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3395 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3396 break;
3397 }
3398 } else {
021230d4
AV		 3399 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3400 * specifically only auto mask tx and rx interrupts */
3401 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3402 }
9a799d71 3403
119fc60a
MC		 3404 /* Enable Thermal over heat sensor interrupt */
3405 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3406 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3407 gpie |= IXGBE_SDP0_GPIEN;
3408 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3409 }
3410
0befdb3e
JB		 3411 /* Enable fan failure interrupt if media type is copper */
3412 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3413 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3414 gpie |= IXGBE_SDP1_GPIEN;
3415 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3416 }
3417
e8e26350
PW		 3418 if (hw->mac.type == ixgbe_mac_82599EB) {
3419 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3420 gpie |= IXGBE_SDP1_GPIEN;
3421 gpie |= IXGBE_SDP2_GPIEN;
3422 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3423 }
3424
179b4096
AD		 3425 if (hw->mac.type == ixgbe_mac_82599EB) {
3426 /* DMATXCTL.EN must be set after all Tx queue config is done */
3427 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3428 dmatxctl |= IXGBE_DMATXCTL_TE;
3429 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3430 }
9a799d71 3431 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3432 j = adapter->tx_ring[i]->reg_idx;
021230d4 3433 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 3434 if (adapter->rx_itr_setting == 0) {
3435 /* cannot set wthresh when itr==0 */
3436 txdctl &= ~0x007F0000;
3437 } else {
3438 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3439 txdctl |= (8 << 16);
3440 }
9a799d71 3441 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 3442 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 3443 if (hw->mac.type == ixgbe_mac_82599EB) {
3444 int wait_loop = 10;
3445 /* poll for Tx Enable ready */
3446 do {
3447 msleep(1);
3448 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3449 } while (--wait_loop &&
3450 !(txdctl & IXGBE_TXDCTL_ENABLE));
3451 if (!wait_loop)
396e799c 3452 e_err(drv, "Could not enable Tx Queue %d\n", j);
1cdd1ec8 3453 }
9a799d71
AK		 3454 }
3455
e8e26350 3456 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 3457 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 3458 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3459 /* enable PTHRESH=32 descriptors (half the internal cache)
3460 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3461 * this also removes a pesky rx_no_buffer_count increment */
3462 rxdctl |= 0x0020;
9a799d71 3463 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 3464 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 3465 if (hw->mac.type == ixgbe_mac_82599EB)
3466 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 3467 }
3468 /* enable all receives */
3469 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 3470 if (hw->mac.type == ixgbe_mac_82598EB)
3471 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3472 else
3473 rxdctl |= IXGBE_RXCTRL_RXEN;
3474 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3475
3476 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3477 ixgbe_configure_msix(adapter);
3478 else
3479 ixgbe_configure_msi_and_legacy(adapter);
3480
61fac744
PW		 3481 /* enable the optics */
3482 if (hw->phy.multispeed_fiber)
3483 hw->mac.ops.enable_tx_laser(hw);
3484
9a799d71 3485 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3486 ixgbe_napi_enable_all(adapter);
3487
3488 /* clear any pending interrupts, may auto mask */
3489 IXGBE_READ_REG(hw, IXGBE_EICR);
3490
9a799d71
AK		 3491 ixgbe_irq_enable(adapter);
3492
bf069c97
DS		 3493 /*
3494 * If this adapter has a fan, check to see if we had a failure
3495 * before we enabled the interrupt.
3496 */
3497 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3498 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3499 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3500 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3501 }
3502
e8e26350
PW		 3503 /*
3504 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3505 * arrived before interrupts were enabled but after probe. Such
3506 * devices wouldn't have their type identified yet. We need to
3507 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3508 * If we're not hot-pluggable SFP+, we just need to configure link
3509 * and bring it up.
3510 */
19343de2
DS		 3511 if (hw->phy.type == ixgbe_phy_unknown) {
3512 err = hw->phy.ops.identify(hw);
3513 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3514 /*
3515 * Take the device down and schedule the sfp tasklet
3516 * which will unregister_netdev and log it.
3517 */
19343de2 3518 ixgbe_down(adapter);
5da43c1a 3519 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3520 return err;
3521 }
e8e26350
PW		 3522 }
3523
3524 if (ixgbe_is_sfp(hw)) {
3525 ixgbe_sfp_link_config(adapter);
3526 } else {
3527 err = ixgbe_non_sfp_link_config(hw);
3528 if (err)
396e799c 3529 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3530 }
0ecc061d 3531
c4cf55e5
PWJ		 3532 for (i = 0; i < adapter->num_tx_queues; i++)
3533 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3534 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3535
1da100bb 3536 /* enable transmits */
477de6ed 3537 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3538
9a799d71
AK		 3539 /* bring the link up in the watchdog, this could race with our first
3540 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3541 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3542 adapter->link_check_timeout = jiffies;
9a799d71 3543 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3544
3545 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3546 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3547 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3548 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3549
9a799d71
AK		 3550 return 0;
3551}
3552
d4f80882
AV		 3553void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3554{
3555 WARN_ON(in_interrupt());
3556 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3557 msleep(1);
3558 ixgbe_down(adapter);
5809a1ae
GR		 3559 /*
3560 * If SR-IOV enabled then wait a bit before bringing the adapter
3561 * back up to give the VFs time to respond to the reset. The
3562 * two second wait is based upon the watchdog timer cycle in
3563 * the VF driver.
3564 */
3565 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3566 msleep(2000);
d4f80882
AV		 3567 ixgbe_up(adapter);
3568 clear_bit(__IXGBE_RESETTING, &adapter->state);
3569}
3570
9a799d71
AK		 3571int ixgbe_up(struct ixgbe_adapter *adapter)
3572{
3573 /* hardware has been reset, we need to reload some things */
3574 ixgbe_configure(adapter);
3575
3576 return ixgbe_up_complete(adapter);
3577}
3578
3579void ixgbe_reset(struct ixgbe_adapter *adapter)
3580{
c44ade9e 3581 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3582 int err;
3583
3584 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3585 switch (err) {
3586 case 0:
3587 case IXGBE_ERR_SFP_NOT_PRESENT:
3588 break;
3589 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3590 e_dev_err("master disable timed out\n");
da4dd0f7 3591 break;
794caeb2
PWJ		 3592 case IXGBE_ERR_EEPROM_VERSION:
3593 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3594 e_dev_warn("This device is a pre-production adapter/LOM. "
3595 "Please be aware there may be issuesassociated with "
3596 "your hardware. If you are experiencing problems "
3597 "please contact your Intel or hardware "
3598 "representative who provided you with this "
3599 "hardware.\n");
794caeb2 3600 break;
da4dd0f7 3601 default:
849c4542 3602 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3603 }
9a799d71
AK		 3604
3605 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3606 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3607 IXGBE_RAH_AV);
9a799d71
AK		 3608}
3609
9a799d71
AK		 3610/**
3611 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3612 * @adapter: board private structure
3613 * @rx_ring: ring to free buffers from
3614 **/
3615static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3616 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3617{
3618 struct pci_dev *pdev = adapter->pdev;
3619 unsigned long size;
3620 unsigned int i;
3621
3622 /* Free all the Rx ring sk_buffs */
3623
3624 for (i = 0; i < rx_ring->count; i++) {
3625 struct ixgbe_rx_buffer *rx_buffer_info;
3626
3627 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3628 if (rx_buffer_info->dma) {
1b507730 3629 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3630 rx_ring->rx_buf_len,
1b507730 3631 DMA_FROM_DEVICE);
9a799d71
AK		 3632 rx_buffer_info->dma = 0;
3633 }
3634 if (rx_buffer_info->skb) {
f8212f97 3635 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3636 rx_buffer_info->skb = NULL;
f8212f97
AD		 3637 do {
3638 struct sk_buff *this = skb;
e8171aaa 3639 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3640 dma_unmap_single(&pdev->dev,
3641 IXGBE_RSC_CB(this)->dma,
43634e82 3642 rx_ring->rx_buf_len,
1b507730 3643 DMA_FROM_DEVICE);
fd3686a8 3644 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3645 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3646 }
f8212f97
AD		 3647 skb = skb->prev;
3648 dev_kfree_skb(this);
3649 } while (skb);
9a799d71
AK		 3650 }
3651 if (!rx_buffer_info->page)
3652 continue;
4f57ca6e 3653 if (rx_buffer_info->page_dma) {
1b507730
NN		 3654 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3655 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3656 rx_buffer_info->page_dma = 0;
3657 }
9a799d71
AK		 3658 put_page(rx_buffer_info->page);
3659 rx_buffer_info->page = NULL;
762f4c57 3660 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3661 }
3662
3663 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3664 memset(rx_ring->rx_buffer_info, 0, size);
3665
3666 /* Zero out the descriptor ring */
3667 memset(rx_ring->desc, 0, rx_ring->size);
3668
3669 rx_ring->next_to_clean = 0;
3670 rx_ring->next_to_use = 0;
3671
9891ca7c
JB		 3672 if (rx_ring->head)
3673 writel(0, adapter->hw.hw_addr + rx_ring->head);
3674 if (rx_ring->tail)
3675 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3676}
3677
3678/**
3679 * ixgbe_clean_tx_ring - Free Tx Buffers
3680 * @adapter: board private structure
3681 * @tx_ring: ring to be cleaned
3682 **/
3683static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3684 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3685{
3686 struct ixgbe_tx_buffer *tx_buffer_info;
3687 unsigned long size;
3688 unsigned int i;
3689
3690 /* Free all the Tx ring sk_buffs */
3691
3692 for (i = 0; i < tx_ring->count; i++) {
3693 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3694 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3695 }
3696
3697 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3698 memset(tx_ring->tx_buffer_info, 0, size);
3699
3700 /* Zero out the descriptor ring */
3701 memset(tx_ring->desc, 0, tx_ring->size);
3702
3703 tx_ring->next_to_use = 0;
3704 tx_ring->next_to_clean = 0;
3705
9891ca7c
JB		 3706 if (tx_ring->head)
3707 writel(0, adapter->hw.hw_addr + tx_ring->head);
3708 if (tx_ring->tail)
3709 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3710}
3711
3712/**
021230d4 3713 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3714 * @adapter: board private structure
3715 **/
021230d4 3716static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3717{
3718 int i;
3719
021230d4 3720 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3721 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3722}
3723
3724/**
021230d4 3725 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3726 * @adapter: board private structure
3727 **/
021230d4 3728static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3729{
3730 int i;
3731
021230d4 3732 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3733 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3734}
3735
3736void ixgbe_down(struct ixgbe_adapter *adapter)
3737{
3738 struct net_device *netdev = adapter->netdev;
7f821875 3739 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3740 u32 rxctrl;
7f821875
JB		 3741 u32 txdctl;
3742 int i, j;
9a799d71
AK		 3743
3744 /* signal that we are down to the interrupt handler */
3745 set_bit(__IXGBE_DOWN, &adapter->state);
3746
767081ad
GR		 3747 /* disable receive for all VFs and wait one second */
3748 if (adapter->num_vfs) {
767081ad
GR		 3749 /* ping all the active vfs to let them know we are going down */
3750 ixgbe_ping_all_vfs(adapter);
581d1aa7 3751
767081ad
GR		 3752 /* Disable all VFTE/VFRE TX/RX */
3753 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3754
3755 /* Mark all the VFs as inactive */
3756 for (i = 0 ; i < adapter->num_vfs; i++)
3757 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3758 }
3759
9a799d71 3760 /* disable receives */
7f821875
JB		 3761 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3762 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3763
7f821875 3764 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3765 msleep(10);
3766
7f821875
JB		 3767 netif_tx_stop_all_queues(netdev);
3768
0a1f87cb
DS		 3769 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3770 del_timer_sync(&adapter->sfp_timer);
9a799d71 3771 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3772 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3773
c0dfb90e
JF		 3774 netif_carrier_off(netdev);
3775 netif_tx_disable(netdev);
3776
3777 ixgbe_irq_disable(adapter);
3778
3779 ixgbe_napi_disable_all(adapter);
3780
c4cf55e5
PWJ		 3781 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3782 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3783 cancel_work_sync(&adapter->fdir_reinit_task);
3784
119fc60a
MC		 3785 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3786 cancel_work_sync(&adapter->check_overtemp_task);
3787
7f821875
JB		 3788 /* disable transmits in the hardware now that interrupts are off */
3789 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3790 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3791 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3792 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3793 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3794 }
88512539
PW		 3795 /* Disable the Tx DMA engine on 82599 */
3796 if (hw->mac.type == ixgbe_mac_82599EB)
3797 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3798 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3799 ~IXGBE_DMATXCTL_TE));
7f821875 3800
9f756f01
JF		 3801 /* power down the optics */
3802 if (hw->phy.multispeed_fiber)
3803 hw->mac.ops.disable_tx_laser(hw);
3804
9a713e7c
PW		 3805 /* clear n-tuple filters that are cached */
3806 ethtool_ntuple_flush(netdev);
3807
6f4a0e45
PL		 3808 if (!pci_channel_offline(adapter->pdev))
3809 ixgbe_reset(adapter);
9a799d71
AK		 3810 ixgbe_clean_all_tx_rings(adapter);
3811 ixgbe_clean_all_rx_rings(adapter);
3812
5dd2d332 3813#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3814 /* since we reset the hardware DCA settings were cleared */
e35ec126 3815 ixgbe_setup_dca(adapter);
96b0e0f6 3816#endif
9a799d71
AK		 3817}
3818
9a799d71 3819/**
021230d4
AV		 3820 * ixgbe_poll - NAPI Rx polling callback
3821 * @napi: structure for representing this polling device
3822 * @budget: how many packets driver is allowed to clean
3823 *
3824 * This function is used for legacy and MSI, NAPI mode
9a799d71 3825 **/
021230d4 3826static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3827{
9a1a69ad
JB		 3828 struct ixgbe_q_vector *q_vector =
3829 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3830 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3831 int tx_clean_complete, work_done = 0;
9a799d71 3832
5dd2d332 3833#ifdef CONFIG_IXGBE_DCA
bd0362dd 3834 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3835 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3836 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3837 }
3838#endif
3839
4a0b9ca0
PW		 3840 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3841 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3842
9a1a69ad 3843 if (!tx_clean_complete)
d2c7ddd6
DM		 3844 work_done = budget;
3845
53e52c72
DM		 3846 /* If budget not fully consumed, exit the polling mode */
3847 if (work_done < budget) {
288379f0 3848 napi_complete(napi);
f7554a2b 3849 if (adapter->rx_itr_setting & 1)
f494e8fa 3850 ixgbe_set_itr(adapter);
d4f80882 3851 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3852 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3853 }
9a799d71
AK		 3854 return work_done;
3855}
3856
3857/**
3858 * ixgbe_tx_timeout - Respond to a Tx Hang
3859 * @netdev: network interface device structure
3860 **/
3861static void ixgbe_tx_timeout(struct net_device *netdev)
3862{
3863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3864
3865 /* Do the reset outside of interrupt context */
3866 schedule_work(&adapter->reset_task);
3867}
3868
3869static void ixgbe_reset_task(struct work_struct *work)
3870{
3871 struct ixgbe_adapter *adapter;
3872 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3873
2f90b865
AD		 3874 /* If we're already down or resetting, just bail */
3875 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3876 test_bit(__IXGBE_RESETTING, &adapter->state))
3877 return;
3878
9a799d71
AK		 3879 adapter->tx_timeout_count++;
3880
dcd79aeb
TI		 3881 ixgbe_dump(adapter);
3882 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3883 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3884}
3885
bc97114d
PWJ		 3886#ifdef CONFIG_IXGBE_DCB
3887static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3888{
bc97114d 3889 bool ret = false;
0cefafad 3890 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3891
0cefafad
JB		 3892 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3893 return ret;
3894
3895 f->mask = 0x7 << 3;
3896 adapter->num_rx_queues = f->indices;
3897 adapter->num_tx_queues = f->indices;
3898 ret = true;
2f90b865 3899
bc97114d
PWJ		 3900 return ret;
3901}
3902#endif
3903
4df10466
JB		 3904/**
3905 * ixgbe_set_rss_queues: Allocate queues for RSS
3906 * @adapter: board private structure to initialize
3907 *
3908 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3909 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3910 *
3911 **/
bc97114d
PWJ		 3912static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3913{
3914 bool ret = false;
0cefafad 3915 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3916
3917 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3918 f->mask = 0xF;
3919 adapter->num_rx_queues = f->indices;
3920 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3921 ret = true;
3922 } else {
bc97114d 3923 ret = false;
b9804972
JB		 3924 }
3925
bc97114d
PWJ		 3926 return ret;
3927}
3928
c4cf55e5
PWJ		 3929/**
3930 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3931 * @adapter: board private structure to initialize
3932 *
3933 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3934 * to the original CPU that initiated the Tx session. This runs in addition
3935 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3936 * Rx load across CPUs using RSS.
3937 *
3938 **/
3939static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3940{
3941 bool ret = false;
3942 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3943
3944 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3945 f_fdir->mask = 0;
3946
3947 /* Flow Director must have RSS enabled */
3948 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3949 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3950 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3951 adapter->num_tx_queues = f_fdir->indices;
3952 adapter->num_rx_queues = f_fdir->indices;
3953 ret = true;
3954 } else {
3955 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3956 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3957 }
3958 return ret;
3959}
3960
0331a832
YZ		 3961#ifdef IXGBE_FCOE
3962/**
3963 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3964 * @adapter: board private structure to initialize
3965 *
3966 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3967 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3968 * rx queues out of the max number of rx queues, instead, it is used as the
3969 * index of the first rx queue used by FCoE.
3970 *
3971 **/
3972static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3973{
3974 bool ret = false;
3975 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3976
3977 f->indices = min((int)num_online_cpus(), f->indices);
3978 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3979 adapter->num_rx_queues = 1;
3980 adapter->num_tx_queues = 1;
0331a832
YZ		 3981#ifdef CONFIG_IXGBE_DCB
3982 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 3983 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 3984 ixgbe_set_dcb_queues(adapter);
3985 }
3986#endif
3987 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 3988 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3989 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3990 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3991 ixgbe_set_fdir_queues(adapter);
3992 else
3993 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3994 }
3995 /* adding FCoE rx rings to the end */
3996 f->mask = adapter->num_rx_queues;
3997 adapter->num_rx_queues += f->indices;
8de8b2e6 3998 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3999
4000 ret = true;
4001 }
4002
4003 return ret;
4004}
4005
4006#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4007/**
4008 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4009 * @adapter: board private structure to initialize
4010 *
4011 * IOV doesn't actually use anything, so just NAK the
4012 * request for now and let the other queue routines
4013 * figure out what to do.
4014 */
4015static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4016{
4017 return false;
4018}
4019
4df10466
JB		 4020/*
4021 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4022 * @adapter: board private structure to initialize
4023 *
4024 * This is the top level queue allocation routine. The order here is very
4025 * important, starting with the "most" number of features turned on at once,
4026 * and ending with the smallest set of features. This way large combinations
4027 * can be allocated if they're turned on, and smaller combinations are the
4028 * fallthrough conditions.
4029 *
4030 **/
bc97114d
PWJ		 4031static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4032{
1cdd1ec8
GR		 4033 /* Start with base case */
4034 adapter->num_rx_queues = 1;
4035 adapter->num_tx_queues = 1;
4036 adapter->num_rx_pools = adapter->num_rx_queues;
4037 adapter->num_rx_queues_per_pool = 1;
4038
4039 if (ixgbe_set_sriov_queues(adapter))
4040 return;
4041
0331a832
YZ		 4042#ifdef IXGBE_FCOE
4043 if (ixgbe_set_fcoe_queues(adapter))
4044 goto done;
4045
4046#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4047#ifdef CONFIG_IXGBE_DCB
4048 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4049 goto done;
bc97114d
PWJ		 4050
4051#endif
c4cf55e5
PWJ		 4052 if (ixgbe_set_fdir_queues(adapter))
4053 goto done;
4054
bc97114d 4055 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4056 goto done;
4057
4058 /* fallback to base case */
4059 adapter->num_rx_queues = 1;
4060 adapter->num_tx_queues = 1;
4061
4062done:
4063 /* Notify the stack of the (possibly) reduced Tx Queue count. */
f0796d5c 4064 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
b9804972
JB		 4065}
4066
021230d4 4067static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 4068 int vectors)
021230d4
AV		 4069{
4070 int err, vector_threshold;
4071
4072 /* We'll want at least 3 (vector_threshold):
4073 * 1) TxQ[0] Cleanup
4074 * 2) RxQ[0] Cleanup
4075 * 3) Other (Link Status Change, etc.)
4076 * 4) TCP Timer (optional)
4077 */
4078 vector_threshold = MIN_MSIX_COUNT;
4079
4080 /* The more we get, the more we will assign to Tx/Rx Cleanup
4081 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4082 * Right now, we simply care about how many we'll get; we'll
4083 * set them up later while requesting irq's.
4084 */
4085 while (vectors >= vector_threshold) {
4086 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 4087 vectors);
021230d4
AV		 4088 if (!err) /* Success in acquiring all requested vectors. */
4089 break;
4090 else if (err < 0)
4091 vectors = 0; /* Nasty failure, quit now */
4092 else /* err == number of vectors we should try again with */
4093 vectors = err;
4094 }
4095
4096 if (vectors < vector_threshold) {
4097 /* Can't allocate enough MSI-X interrupts? Oh well.
4098 * This just means we'll go with either a single MSI
4099 * vector or fall back to legacy interrupts.
4100 */
849c4542
ET		 4101 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4102 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4103 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4104 kfree(adapter->msix_entries);
4105 adapter->msix_entries = NULL;
021230d4
AV		 4106 } else {
4107 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4108 /*
4109 * Adjust for only the vectors we'll use, which is minimum
4110 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4111 * vectors we were allocated.
4112 */
4113 adapter->num_msix_vectors = min(vectors,
4114 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4115 }
4116}
4117
021230d4 4118/**
bc97114d 4119 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4120 * @adapter: board private structure to initialize
4121 *
bc97114d
PWJ		 4122 * Cache the descriptor ring offsets for RSS to the assigned rings.
4123 *
021230d4 4124 **/
bc97114d 4125static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4126{
bc97114d
PWJ		 4127 int i;
4128 bool ret = false;
4129
4130 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4131 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4132 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4133 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4134 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4135 ret = true;
4136 } else {
4137 ret = false;
4138 }
4139
4140 return ret;
4141}
4142
4143#ifdef CONFIG_IXGBE_DCB
4144/**
4145 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4146 * @adapter: board private structure to initialize
4147 *
4148 * Cache the descriptor ring offsets for DCB to the assigned rings.
4149 *
4150 **/
4151static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4152{
4153 int i;
4154 bool ret = false;
4155 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4156
4157 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4158 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4159 /* the number of queues is assumed to be symmetric */
4160 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4161 adapter->rx_ring[i]->reg_idx = i << 3;
4162 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4163 }
bc97114d 4164 ret = true;
e8e26350 4165 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4166 if (dcb_i == 8) {
4167 /*
4168 * Tx TC0 starts at: descriptor queue 0
4169 * Tx TC1 starts at: descriptor queue 32
4170 * Tx TC2 starts at: descriptor queue 64
4171 * Tx TC3 starts at: descriptor queue 80
4172 * Tx TC4 starts at: descriptor queue 96
4173 * Tx TC5 starts at: descriptor queue 104
4174 * Tx TC6 starts at: descriptor queue 112
4175 * Tx TC7 starts at: descriptor queue 120
4176 *
4177 * Rx TC0-TC7 are offset by 16 queues each
4178 */
4179 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4180 adapter->tx_ring[i]->reg_idx = i << 5;
4181 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4182 }
4183 for ( ; i < 5; i++) {
4a0b9ca0 4184 adapter->tx_ring[i]->reg_idx =
f92ef202 4185 ((i + 2) << 4);
4a0b9ca0 4186 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4187 }
4188 for ( ; i < dcb_i; i++) {
4a0b9ca0 4189 adapter->tx_ring[i]->reg_idx =
f92ef202 4190 ((i + 8) << 3);
4a0b9ca0 4191 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4192 }
4193
4194 ret = true;
4195 } else if (dcb_i == 4) {
4196 /*
4197 * Tx TC0 starts at: descriptor queue 0
4198 * Tx TC1 starts at: descriptor queue 64
4199 * Tx TC2 starts at: descriptor queue 96
4200 * Tx TC3 starts at: descriptor queue 112
4201 *
4202 * Rx TC0-TC3 are offset by 32 queues each
4203 */
4a0b9ca0
PW		 4204 adapter->tx_ring[0]->reg_idx = 0;
4205 adapter->tx_ring[1]->reg_idx = 64;
4206 adapter->tx_ring[2]->reg_idx = 96;
4207 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4208 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4209 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4210
4211 ret = true;
4212 } else {
4213 ret = false;
e8e26350 4214 }
bc97114d
PWJ		 4215 } else {
4216 ret = false;
021230d4 4217 }
bc97114d
PWJ		 4218 } else {
4219 ret = false;
021230d4 4220 }
bc97114d
PWJ		 4221
4222 return ret;
4223}
4224#endif
4225
c4cf55e5
PWJ		 4226/**
4227 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4228 * @adapter: board private structure to initialize
4229 *
4230 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4231 *
4232 **/
4233static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4234{
4235 int i;
4236 bool ret = false;
4237
4238 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4239 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4240 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4241 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4242 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4243 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4244 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4245 ret = true;
4246 }
4247
4248 return ret;
4249}
4250
0331a832
YZ		 4251#ifdef IXGBE_FCOE
4252/**
4253 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4254 * @adapter: board private structure to initialize
4255 *
4256 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4257 *
4258 */
4259static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4260{
8de8b2e6 4261 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4262 bool ret = false;
4263 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4264
4265 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4266#ifdef CONFIG_IXGBE_DCB
4267 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4268 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4269
0331a832 4270 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4271 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4272 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4273 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4274 /*
4275 * In 82599, the number of Tx queues for each traffic
4276 * class for both 8-TC and 4-TC modes are:
4277 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4278 * 8 TCs: 32 32 16 16 8 8 8 8
4279 * 4 TCs: 64 64 32 32
4280 * We have max 8 queues for FCoE, where 8 the is
4281 * FCoE redirection table size. If TC for FCoE is
4282 * less than or equal to TC3, we have enough queues
4283 * to add max of 8 queues for FCoE, so we start FCoE
4284 * tx descriptor from the next one, i.e., reg_idx + 1.
4285 * If TC for FCoE is above TC3, implying 8 TC mode,
4286 * and we need 8 for FCoE, we have to take all queues
4287 * in that traffic class for FCoE.
4288 */
4289 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4290 fcoe_tx_i--;
0331a832
YZ		 4291 }
4292#endif /* CONFIG_IXGBE_DCB */
4293 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4294 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4295 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4296 ixgbe_cache_ring_fdir(adapter);
4297 else
4298 ixgbe_cache_ring_rss(adapter);
4299
8de8b2e6
YZ		 4300 fcoe_rx_i = f->mask;
4301 fcoe_tx_i = f->mask;
4302 }
4303 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4304 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4305 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4306 }
0331a832
YZ		 4307 ret = true;
4308 }
4309 return ret;
4310}
4311
4312#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4313/**
4314 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4315 * @adapter: board private structure to initialize
4316 *
4317 * SR-IOV doesn't use any descriptor rings but changes the default if
4318 * no other mapping is used.
4319 *
4320 */
4321static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4322{
4a0b9ca0
PW		 4323 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4324 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4325 if (adapter->num_vfs)
4326 return true;
4327 else
4328 return false;
4329}
4330
bc97114d
PWJ		 4331/**
4332 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4333 * @adapter: board private structure to initialize
4334 *
4335 * Once we know the feature-set enabled for the device, we'll cache
4336 * the register offset the descriptor ring is assigned to.
4337 *
4338 * Note, the order the various feature calls is important. It must start with
4339 * the "most" features enabled at the same time, then trickle down to the
4340 * least amount of features turned on at once.
4341 **/
4342static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4343{
4344 /* start with default case */
4a0b9ca0
PW		 4345 adapter->rx_ring[0]->reg_idx = 0;
4346 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4347
1cdd1ec8
GR		 4348 if (ixgbe_cache_ring_sriov(adapter))
4349 return;
4350
0331a832
YZ		 4351#ifdef IXGBE_FCOE
4352 if (ixgbe_cache_ring_fcoe(adapter))
4353 return;
4354
4355#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4356#ifdef CONFIG_IXGBE_DCB
4357 if (ixgbe_cache_ring_dcb(adapter))
4358 return;
4359
4360#endif
c4cf55e5
PWJ		 4361 if (ixgbe_cache_ring_fdir(adapter))
4362 return;
4363
bc97114d
PWJ		 4364 if (ixgbe_cache_ring_rss(adapter))
4365 return;
021230d4
AV		 4366}
4367
9a799d71
AK		 4368/**
4369 * ixgbe_alloc_queues - Allocate memory for all rings
4370 * @adapter: board private structure to initialize
4371 *
4372 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4373 * number of queues at compile-time. The polling_netdev array is
4374 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4375 **/
2f90b865 4376static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4377{
4378 int i;
4a0b9ca0 4379 int orig_node = adapter->node;
9a799d71 4380
021230d4 4381 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4382 struct ixgbe_ring *ring = adapter->tx_ring[i];
4383 if (orig_node == -1) {
4384 int cur_node = next_online_node(adapter->node);
4385 if (cur_node == MAX_NUMNODES)
4386 cur_node = first_online_node;
4387 adapter->node = cur_node;
4388 }
4389 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4390 adapter->node);
4391 if (!ring)
4392 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4393 if (!ring)
4394 goto err_tx_ring_allocation;
4395 ring->count = adapter->tx_ring_count;
4396 ring->queue_index = i;
4397 ring->numa_node = adapter->node;
4398
4399 adapter->tx_ring[i] = ring;
021230d4 4400 }
b9804972 4401
4a0b9ca0
PW		 4402 /* Restore the adapter's original node */
4403 adapter->node = orig_node;
4404
9a799d71 4405 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4406 struct ixgbe_ring *ring = adapter->rx_ring[i];
4407 if (orig_node == -1) {
4408 int cur_node = next_online_node(adapter->node);
4409 if (cur_node == MAX_NUMNODES)
4410 cur_node = first_online_node;
4411 adapter->node = cur_node;
4412 }
4413 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4414 adapter->node);
4415 if (!ring)
4416 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4417 if (!ring)
4418 goto err_rx_ring_allocation;
4419 ring->count = adapter->rx_ring_count;
4420 ring->queue_index = i;
4421 ring->numa_node = adapter->node;
4422
4423 adapter->rx_ring[i] = ring;
021230d4
AV		 4424 }
4425
4a0b9ca0
PW		 4426 /* Restore the adapter's original node */
4427 adapter->node = orig_node;
4428
021230d4
AV		 4429 ixgbe_cache_ring_register(adapter);
4430
4431 return 0;
4432
4433err_rx_ring_allocation:
4a0b9ca0
PW		 4434 for (i = 0; i < adapter->num_tx_queues; i++)
4435 kfree(adapter->tx_ring[i]);
021230d4
AV		 4436err_tx_ring_allocation:
4437 return -ENOMEM;
4438}
4439
4440/**
4441 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4442 * @adapter: board private structure to initialize
4443 *
4444 * Attempt to configure the interrupts using the best available
4445 * capabilities of the hardware and the kernel.
4446 **/
feea6a57 4447static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4448{
8be0e467 4449 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4450 int err = 0;
4451 int vector, v_budget;
4452
4453 /*
4454 * It's easy to be greedy for MSI-X vectors, but it really
4455 * doesn't do us much good if we have a lot more vectors
4456 * than CPU's. So let's be conservative and only ask for
342bde1b 4457 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4458 */
4459 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 4460 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4461
4462 /*
4463 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4464 * hw.mac->max_msix_vectors vectors. With features
4465 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4466 * descriptor queues supported by our device. Thus, we cap it off in
4467 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4468 */
8be0e467 4469 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4470
4471 /* A failure in MSI-X entry allocation isn't fatal, but it does
4472 * mean we disable MSI-X capabilities of the adapter. */
4473 adapter->msix_entries = kcalloc(v_budget,
b4617240 4474 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4475 if (adapter->msix_entries) {
4476 for (vector = 0; vector < v_budget; vector++)
4477 adapter->msix_entries[vector].entry = vector;
021230d4 4478
7a921c93 4479 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4480
7a921c93
AD		 4481 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4482 goto out;
4483 }
26d27844 4484
7a921c93
AD		 4485 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4486 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4487 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4488 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4489 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4490 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4491 ixgbe_disable_sriov(adapter);
4492
7a921c93 4493 ixgbe_set_num_queues(adapter);
021230d4 4494
021230d4
AV		 4495 err = pci_enable_msi(adapter->pdev);
4496 if (!err) {
4497 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4498 } else {
849c4542
ET		 4499 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4500 "Unable to allocate MSI interrupt, "
4501 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4502 /* reset err */
4503 err = 0;
4504 }
4505
4506out:
021230d4
AV		 4507 return err;
4508}
4509
7a921c93
AD		 4510/**
4511 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4512 * @adapter: board private structure to initialize
4513 *
4514 * We allocate one q_vector per queue interrupt. If allocation fails we
4515 * return -ENOMEM.
4516 **/
4517static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4518{
4519 int q_idx, num_q_vectors;
4520 struct ixgbe_q_vector *q_vector;
4521 int napi_vectors;
4522 int (*poll)(struct napi_struct *, int);
4523
4524 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4525 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4526 napi_vectors = adapter->num_rx_queues;
91281fd3 4527 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4528 } else {
4529 num_q_vectors = 1;
4530 napi_vectors = 1;
4531 poll = &ixgbe_poll;
4532 }
4533
4534 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4535 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4536 GFP_KERNEL, adapter->node);
4537 if (!q_vector)
4538 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4539 GFP_KERNEL);
7a921c93
AD		 4540 if (!q_vector)
4541 goto err_out;
4542 q_vector->adapter = adapter;
f7554a2b
NS		 4543 if (q_vector->txr_count && !q_vector->rxr_count)
4544 q_vector->eitr = adapter->tx_eitr_param;
4545 else
4546 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4547 q_vector->v_idx = q_idx;
91281fd3 4548 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4549 adapter->q_vector[q_idx] = q_vector;
4550 }
4551
4552 return 0;
4553
4554err_out:
4555 while (q_idx) {
4556 q_idx--;
4557 q_vector = adapter->q_vector[q_idx];
4558 netif_napi_del(&q_vector->napi);
4559 kfree(q_vector);
4560 adapter->q_vector[q_idx] = NULL;
4561 }
4562 return -ENOMEM;
4563}
4564
4565/**
4566 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4567 * @adapter: board private structure to initialize
4568 *
4569 * This function frees the memory allocated to the q_vectors. In addition if
4570 * NAPI is enabled it will delete any references to the NAPI struct prior
4571 * to freeing the q_vector.
4572 **/
4573static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4574{
4575 int q_idx, num_q_vectors;
7a921c93 4576
91281fd3 4577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4578 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4579 else
7a921c93 4580 num_q_vectors = 1;
7a921c93
AD		 4581
4582 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4583 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4584 adapter->q_vector[q_idx] = NULL;
91281fd3 4585 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4586 kfree(q_vector);
4587 }
4588}
4589
7b25cdba 4590static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4591{
4592 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4593 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4594 pci_disable_msix(adapter->pdev);
4595 kfree(adapter->msix_entries);
4596 adapter->msix_entries = NULL;
4597 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4598 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4599 pci_disable_msi(adapter->pdev);
4600 }
021230d4
AV		 4601}
4602
4603/**
4604 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4605 * @adapter: board private structure to initialize
4606 *
4607 * We determine which interrupt scheme to use based on...
4608 * - Kernel support (MSI, MSI-X)
4609 * - which can be user-defined (via MODULE_PARAM)
4610 * - Hardware queue count (num_*_queues)
4611 * - defined by miscellaneous hardware support/features (RSS, etc.)
4612 **/
2f90b865 4613int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4614{
4615 int err;
4616
4617 /* Number of supported queues */
4618 ixgbe_set_num_queues(adapter);
4619
021230d4
AV		 4620 err = ixgbe_set_interrupt_capability(adapter);
4621 if (err) {
849c4542 4622 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4623 goto err_set_interrupt;
9a799d71
AK		 4624 }
4625
7a921c93
AD		 4626 err = ixgbe_alloc_q_vectors(adapter);
4627 if (err) {
849c4542 4628 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4629 goto err_alloc_q_vectors;
4630 }
4631
4632 err = ixgbe_alloc_queues(adapter);
4633 if (err) {
849c4542 4634 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4635 goto err_alloc_queues;
4636 }
4637
849c4542 4638 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4639 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4640 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4641
4642 set_bit(__IXGBE_DOWN, &adapter->state);
4643
9a799d71 4644 return 0;
021230d4 4645
7a921c93
AD		 4646err_alloc_queues:
4647 ixgbe_free_q_vectors(adapter);
4648err_alloc_q_vectors:
4649 ixgbe_reset_interrupt_capability(adapter);
021230d4 4650err_set_interrupt:
7a921c93
AD		 4651 return err;
4652}
4653
4654/**
4655 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4656 * @adapter: board private structure to clear interrupt scheme on
4657 *
4658 * We go through and clear interrupt specific resources and reset the structure
4659 * to pre-load conditions
4660 **/
4661void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4662{
4a0b9ca0
PW		 4663 int i;
4664
4665 for (i = 0; i < adapter->num_tx_queues; i++) {
4666 kfree(adapter->tx_ring[i]);
4667 adapter->tx_ring[i] = NULL;
4668 }
4669 for (i = 0; i < adapter->num_rx_queues; i++) {
4670 kfree(adapter->rx_ring[i]);
4671 adapter->rx_ring[i] = NULL;
4672 }
7a921c93
AD		 4673
4674 ixgbe_free_q_vectors(adapter);
4675 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4676}
4677
c4900be0
DS		 4678/**
4679 * ixgbe_sfp_timer - worker thread to find a missing module
4680 * @data: pointer to our adapter struct
4681 **/
4682static void ixgbe_sfp_timer(unsigned long data)
4683{
4684 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4685
4df10466
JB		 4686 /*
4687 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4688 * delays that sfp+ detection requires
4689 */
4690 schedule_work(&adapter->sfp_task);
4691}
4692
4693/**
4694 * ixgbe_sfp_task - worker thread to find a missing module
4695 * @work: pointer to work_struct containing our data
4696 **/
4697static void ixgbe_sfp_task(struct work_struct *work)
4698{
4699 struct ixgbe_adapter *adapter = container_of(work,
4700 struct ixgbe_adapter,
4701 sfp_task);
4702 struct ixgbe_hw *hw = &adapter->hw;
4703
4704 if ((hw->phy.type == ixgbe_phy_nl) &&
4705 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4706 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4707 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4708 goto reschedule;
4709 ret = hw->phy.ops.reset(hw);
4710 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4711 e_dev_err("failed to initialize because an unsupported "
4712 "SFP+ module type was detected.\n");
4713 e_dev_err("Reload the driver after installing a "
4714 "supported module.\n");
c4900be0
DS		 4715 unregister_netdev(adapter->netdev);
4716 } else {
396e799c 4717 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4718 }
4719 /* don't need this routine any more */
4720 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4721 }
4722 return;
4723reschedule:
4724 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4725 mod_timer(&adapter->sfp_timer,
4726 round_jiffies(jiffies + (2 * HZ)));
4727}
4728
9a799d71
AK		 4729/**
4730 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4731 * @adapter: board private structure to initialize
4732 *
4733 * ixgbe_sw_init initializes the Adapter private data structure.
4734 * Fields are initialized based on PCI device information and
4735 * OS network device settings (MTU size).
4736 **/
4737static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4738{
4739 struct ixgbe_hw *hw = &adapter->hw;
4740 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4741 struct net_device *dev = adapter->netdev;
021230d4 4742 unsigned int rss;
7a6b6f51 4743#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4744 int j;
4745 struct tc_configuration *tc;
4746#endif
021230d4 4747
c44ade9e
JB		 4748 /* PCI config space info */
4749
4750 hw->vendor_id = pdev->vendor;
4751 hw->device_id = pdev->device;
4752 hw->revision_id = pdev->revision;
4753 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4754 hw->subsystem_device_id = pdev->subsystem_device;
4755
021230d4
AV		 4756 /* Set capability flags */
4757 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4758 adapter->ring_feature[RING_F_RSS].indices = rss;
4759 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4760 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4761 if (hw->mac.type == ixgbe_mac_82598EB) {
4762 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4763 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4764 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4765 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4766 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4767 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4768 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4769 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4770 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4771 if (dev->features & NETIF_F_NTUPLE) {
4772 /* Flow Director perfect filter enabled */
4773 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4774 adapter->atr_sample_rate = 0;
4775 spin_lock_init(&adapter->fdir_perfect_lock);
4776 } else {
4777 /* Flow Director hash filters enabled */
4778 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4779 adapter->atr_sample_rate = 20;
4780 }
c4cf55e5
PWJ		 4781 adapter->ring_feature[RING_F_FDIR].indices =
4782 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4783 adapter->fdir_pballoc = 0;
eacd73f7 4784#ifdef IXGBE_FCOE
0d551589
YZ		 4785 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4786 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4787 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4788#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4789 /* Default traffic class to use for FCoE */
4790 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4791 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4792#endif
eacd73f7 4793#endif /* IXGBE_FCOE */
f8212f97 4794 }
2f90b865 4795
7a6b6f51 4796#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4797 /* Configure DCB traffic classes */
4798 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4799 tc = &adapter->dcb_cfg.tc_config[j];
4800 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4801 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4802 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4803 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4804 tc->dcb_pfc = pfc_disabled;
4805 }
4806 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4807 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4808 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4809 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4810 adapter->dcb_cfg.round_robin_enable = false;
4811 adapter->dcb_set_bitmap = 0x00;
4812 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4813 adapter->ring_feature[RING_F_DCB].indices);
4814
4815#endif
9a799d71
AK		 4816
4817 /* default flow control settings */
cd7664f6 4818 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4819 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4820#ifdef CONFIG_DCB
4821 adapter->last_lfc_mode = hw->fc.current_mode;
4822#endif
2b9ade93
JB		 4823 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4824 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4825 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4826 hw->fc.send_xon = true;
71fd570b 4827 hw->fc.disable_fc_autoneg = false;
9a799d71 4828
30efa5a3 4829 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4830 adapter->rx_itr_setting = 1;
4831 adapter->rx_eitr_param = 20000;
4832 adapter->tx_itr_setting = 1;
4833 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4834
4835 /* set defaults for eitr in MegaBytes */
4836 adapter->eitr_low = 10;
4837 adapter->eitr_high = 20;
4838
4839 /* set default ring sizes */
4840 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4841 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4842
9a799d71 4843 /* initialize eeprom parameters */
c44ade9e 4844 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4845 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4846 return -EIO;
4847 }
4848
021230d4 4849 /* enable rx csum by default */
9a799d71
AK		 4850 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4851
1a6c14a2
JB		 4852 /* get assigned NUMA node */
4853 adapter->node = dev_to_node(&pdev->dev);
4854
9a799d71
AK		 4855 set_bit(__IXGBE_DOWN, &adapter->state);
4856
4857 return 0;
4858}
4859
4860/**
4861 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4862 * @adapter: board private structure
3a581073 4863 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4864 *
4865 * Return 0 on success, negative on failure
4866 **/
4867int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4868 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4869{
4870 struct pci_dev *pdev = adapter->pdev;
4871 int size;
4872
3a581073 4873 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4874 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4875 if (!tx_ring->tx_buffer_info)
4876 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4877 if (!tx_ring->tx_buffer_info)
4878 goto err;
3a581073 4879 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4880
4881 /* round up to nearest 4K */
12207e49 4882 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4883 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4884
1b507730
NN		 4885 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4886 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4887 if (!tx_ring->desc)
4888 goto err;
9a799d71 4889
3a581073
JB		 4890 tx_ring->next_to_use = 0;
4891 tx_ring->next_to_clean = 0;
4892 tx_ring->work_limit = tx_ring->count;
9a799d71 4893 return 0;
e01c31a5
JB		 4894
4895err:
4896 vfree(tx_ring->tx_buffer_info);
4897 tx_ring->tx_buffer_info = NULL;
396e799c 4898 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4899 return -ENOMEM;
9a799d71
AK		 4900}
4901
69888674
AD		 4902/**
4903 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4904 * @adapter: board private structure
4905 *
4906 * If this function returns with an error, then it's possible one or
4907 * more of the rings is populated (while the rest are not). It is the
4908 * callers duty to clean those orphaned rings.
4909 *
4910 * Return 0 on success, negative on failure
4911 **/
4912static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4913{
4914 int i, err = 0;
4915
4916 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4917 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4918 if (!err)
4919 continue;
396e799c 4920 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4921 break;
4922 }
4923
4924 return err;
4925}
4926
9a799d71
AK		 4927/**
4928 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4929 * @adapter: board private structure
3a581073 4930 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4931 *
4932 * Returns 0 on success, negative on failure
4933 **/
4934int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4935 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4936{
4937 struct pci_dev *pdev = adapter->pdev;
021230d4 4938 int size;
9a799d71 4939
3a581073 4940 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4941 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4942 if (!rx_ring->rx_buffer_info)
4943 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4944 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 4945 e_err(probe, "vmalloc allocation failed for the Rx "
4946 "descriptor ring\n");
177db6ff 4947 goto alloc_failed;
9a799d71 4948 }
3a581073 4949 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4950
9a799d71 4951 /* Round up to nearest 4K */
3a581073
JB		 4952 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4953 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4954
1b507730
NN		 4955 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4956 &rx_ring->dma, GFP_KERNEL);
9a799d71 4957
3a581073 4958 if (!rx_ring->desc) {
396e799c
ET		 4959 e_err(probe, "Memory allocation failed for the Rx "
4960 "descriptor ring\n");
3a581073 4961 vfree(rx_ring->rx_buffer_info);
177db6ff 4962 goto alloc_failed;
9a799d71
AK		 4963 }
4964
3a581073
JB		 4965 rx_ring->next_to_clean = 0;
4966 rx_ring->next_to_use = 0;
9a799d71
AK		 4967
4968 return 0;
177db6ff
MC		 4969
4970alloc_failed:
177db6ff 4971 return -ENOMEM;
9a799d71
AK		 4972}
4973
69888674
AD		 4974/**
4975 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4976 * @adapter: board private structure
4977 *
4978 * If this function returns with an error, then it's possible one or
4979 * more of the rings is populated (while the rest are not). It is the
4980 * callers duty to clean those orphaned rings.
4981 *
4982 * Return 0 on success, negative on failure
4983 **/
4984
4985static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4986{
4987 int i, err = 0;
4988
4989 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4990 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4991 if (!err)
4992 continue;
396e799c 4993 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 4994 break;
4995 }
4996
4997 return err;
4998}
4999
9a799d71
AK		 5000/**
5001 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5002 * @adapter: board private structure
5003 * @tx_ring: Tx descriptor ring for a specific queue
5004 *
5005 * Free all transmit software resources
5006 **/
c431f97e
JB		 5007void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5008 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5009{
5010 struct pci_dev *pdev = adapter->pdev;
5011
5012 ixgbe_clean_tx_ring(adapter, tx_ring);
5013
5014 vfree(tx_ring->tx_buffer_info);
5015 tx_ring->tx_buffer_info = NULL;
5016
1b507730
NN		 5017 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5018 tx_ring->dma);
9a799d71
AK		 5019
5020 tx_ring->desc = NULL;
5021}
5022
5023/**
5024 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5025 * @adapter: board private structure
5026 *
5027 * Free all transmit software resources
5028 **/
5029static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5030{
5031 int i;
5032
5033 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5034 if (adapter->tx_ring[i]->desc)
5035 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5036}
5037
5038/**
b4617240 5039 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5040 * @adapter: board private structure
5041 * @rx_ring: ring to clean the resources from
5042 *
5043 * Free all receive software resources
5044 **/
c431f97e
JB		 5045void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5046 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5047{
5048 struct pci_dev *pdev = adapter->pdev;
5049
5050 ixgbe_clean_rx_ring(adapter, rx_ring);
5051
5052 vfree(rx_ring->rx_buffer_info);
5053 rx_ring->rx_buffer_info = NULL;
5054
1b507730
NN		 5055 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5056 rx_ring->dma);
9a799d71
AK		 5057
5058 rx_ring->desc = NULL;
5059}
5060
5061/**
5062 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5063 * @adapter: board private structure
5064 *
5065 * Free all receive software resources
5066 **/
5067static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5068{
5069 int i;
5070
5071 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5072 if (adapter->rx_ring[i]->desc)
5073 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5074}
5075
9a799d71
AK		 5076/**
5077 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5078 * @netdev: network interface device structure
5079 * @new_mtu: new value for maximum frame size
5080 *
5081 * Returns 0 on success, negative on failure
5082 **/
5083static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5084{
5085 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5086 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5087
42c783c5
JB		 5088 /* MTU < 68 is an error and causes problems on some kernels */
5089 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5090 return -EINVAL;
5091
396e799c 5092 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5093 /* must set new MTU before calling down or up */
9a799d71
AK		 5094 netdev->mtu = new_mtu;
5095
d4f80882
AV		 5096 if (netif_running(netdev))
5097 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5098
5099 return 0;
5100}
5101
5102/**
5103 * ixgbe_open - Called when a network interface is made active
5104 * @netdev: network interface device structure
5105 *
5106 * Returns 0 on success, negative value on failure
5107 *
5108 * The open entry point is called when a network interface is made
5109 * active by the system (IFF_UP). At this point all resources needed
5110 * for transmit and receive operations are allocated, the interrupt
5111 * handler is registered with the OS, the watchdog timer is started,
5112 * and the stack is notified that the interface is ready.
5113 **/
5114static int ixgbe_open(struct net_device *netdev)
5115{
5116 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5117 int err;
4bebfaa5
AK		 5118
5119 /* disallow open during test */
5120 if (test_bit(__IXGBE_TESTING, &adapter->state))
5121 return -EBUSY;
9a799d71 5122
54386467
JB		 5123 netif_carrier_off(netdev);
5124
9a799d71
AK		 5125 /* allocate transmit descriptors */
5126 err = ixgbe_setup_all_tx_resources(adapter);
5127 if (err)
5128 goto err_setup_tx;
5129
9a799d71
AK		 5130 /* allocate receive descriptors */
5131 err = ixgbe_setup_all_rx_resources(adapter);
5132 if (err)
5133 goto err_setup_rx;
5134
5135 ixgbe_configure(adapter);
5136
021230d4 5137 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5138 if (err)
5139 goto err_req_irq;
5140
9a799d71
AK		 5141 err = ixgbe_up_complete(adapter);
5142 if (err)
5143 goto err_up;
5144
d55b53ff
JK		 5145 netif_tx_start_all_queues(netdev);
5146
9a799d71
AK		 5147 return 0;
5148
5149err_up:
5eba3699 5150 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5151 ixgbe_free_irq(adapter);
5152err_req_irq:
9a799d71 5153err_setup_rx:
a20a1199 5154 ixgbe_free_all_rx_resources(adapter);
9a799d71 5155err_setup_tx:
a20a1199 5156 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5157 ixgbe_reset(adapter);
5158
5159 return err;
5160}
5161
5162/**
5163 * ixgbe_close - Disables a network interface
5164 * @netdev: network interface device structure
5165 *
5166 * Returns 0, this is not allowed to fail
5167 *
5168 * The close entry point is called when an interface is de-activated
5169 * by the OS. The hardware is still under the drivers control, but
5170 * needs to be disabled. A global MAC reset is issued to stop the
5171 * hardware, and all transmit and receive resources are freed.
5172 **/
5173static int ixgbe_close(struct net_device *netdev)
5174{
5175 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5176
5177 ixgbe_down(adapter);
5178 ixgbe_free_irq(adapter);
5179
5180 ixgbe_free_all_tx_resources(adapter);
5181 ixgbe_free_all_rx_resources(adapter);
5182
5eba3699 5183 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5184
5185 return 0;
5186}
5187
b3c8b4ba
AD		 5188#ifdef CONFIG_PM
5189static int ixgbe_resume(struct pci_dev *pdev)
5190{
5191 struct net_device *netdev = pci_get_drvdata(pdev);
5192 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5193 u32 err;
5194
5195 pci_set_power_state(pdev, PCI_D0);
5196 pci_restore_state(pdev);
656ab817
DS		 5197 /*
5198 * pci_restore_state clears dev->state_saved so call
5199 * pci_save_state to restore it.
5200 */
5201 pci_save_state(pdev);
9ce77666 5202
5203 err = pci_enable_device_mem(pdev);
b3c8b4ba 5204 if (err) {
849c4542 5205 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5206 return err;
5207 }
5208 pci_set_master(pdev);
5209
dd4d8ca6 5210 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5211
5212 err = ixgbe_init_interrupt_scheme(adapter);
5213 if (err) {
849c4542 5214 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5215 return err;
5216 }
5217
b3c8b4ba
AD		 5218 ixgbe_reset(adapter);
5219
495dce12
WJP		 5220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5221
b3c8b4ba
AD		 5222 if (netif_running(netdev)) {
5223 err = ixgbe_open(adapter->netdev);
5224 if (err)
5225 return err;
5226 }
5227
5228 netif_device_attach(netdev);
5229
5230 return 0;
5231}
b3c8b4ba 5232#endif /* CONFIG_PM */
9d8d05ae
RW		 5233
5234static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5235{
5236 struct net_device *netdev = pci_get_drvdata(pdev);
5237 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5238 struct ixgbe_hw *hw = &adapter->hw;
5239 u32 ctrl, fctrl;
5240 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5241#ifdef CONFIG_PM
5242 int retval = 0;
5243#endif
5244
5245 netif_device_detach(netdev);
5246
5247 if (netif_running(netdev)) {
5248 ixgbe_down(adapter);
5249 ixgbe_free_irq(adapter);
5250 ixgbe_free_all_tx_resources(adapter);
5251 ixgbe_free_all_rx_resources(adapter);
5252 }
b3c8b4ba
AD		 5253
5254#ifdef CONFIG_PM
5255 retval = pci_save_state(pdev);
5256 if (retval)
5257 return retval;
4df10466 5258
b3c8b4ba 5259#endif
e8e26350
PW		 5260 if (wufc) {
5261 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5262
e8e26350
PW		 5263 /* turn on all-multi mode if wake on multicast is enabled */
5264 if (wufc & IXGBE_WUFC_MC) {
5265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5266 fctrl |= IXGBE_FCTRL_MPE;
5267 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5268 }
5269
5270 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5271 ctrl |= IXGBE_CTRL_GIO_DIS;
5272 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5273
5274 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5275 } else {
5276 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5277 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5278 }
5279
dd4d8ca6
DS		 5280 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5281 pci_wake_from_d3(pdev, true);
5282 else
5283 pci_wake_from_d3(pdev, false);
b3c8b4ba 5284
9d8d05ae
RW		 5285 *enable_wake = !!wufc;
5286
fa378134
AG		 5287 ixgbe_clear_interrupt_scheme(adapter);
5288
b3c8b4ba
AD		 5289 ixgbe_release_hw_control(adapter);
5290
5291 pci_disable_device(pdev);
5292
9d8d05ae
RW		 5293 return 0;
5294}
5295
5296#ifdef CONFIG_PM
5297static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5298{
5299 int retval;
5300 bool wake;
5301
5302 retval = __ixgbe_shutdown(pdev, &wake);
5303 if (retval)
5304 return retval;
5305
5306 if (wake) {
5307 pci_prepare_to_sleep(pdev);
5308 } else {
5309 pci_wake_from_d3(pdev, false);
5310 pci_set_power_state(pdev, PCI_D3hot);
5311 }
b3c8b4ba
AD		 5312
5313 return 0;
5314}
9d8d05ae 5315#endif /* CONFIG_PM */
b3c8b4ba
AD		 5316
5317static void ixgbe_shutdown(struct pci_dev *pdev)
5318{
9d8d05ae
RW		 5319 bool wake;
5320
5321 __ixgbe_shutdown(pdev, &wake);
5322
5323 if (system_state == SYSTEM_POWER_OFF) {
5324 pci_wake_from_d3(pdev, wake);
5325 pci_set_power_state(pdev, PCI_D3hot);
5326 }
b3c8b4ba
AD		 5327}
5328
9a799d71
AK		 5329/**
5330 * ixgbe_update_stats - Update the board statistics counters.
5331 * @adapter: board private structure
5332 **/
5333void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5334{
2d86f139 5335 struct net_device *netdev = adapter->netdev;
9a799d71 5336 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5337 u64 total_mpc = 0;
5338 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5339 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5340
d08935c2
DS		 5341 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5342 test_bit(__IXGBE_RESETTING, &adapter->state))
5343 return;
5344
94b982b2 5345 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5346 u64 rsc_count = 0;
94b982b2 5347 u64 rsc_flush = 0;
d51019a4
PW		 5348 for (i = 0; i < 16; i++)
5349 adapter->hw_rx_no_dma_resources +=
5350 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5351 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5352 rsc_count += adapter->rx_ring[i]->rsc_count;
5353 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5354 }
5355 adapter->rsc_total_count = rsc_count;
5356 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5357 }
5358
7ca3bc58
JB		 5359 /* gather some stats to the adapter struct that are per queue */
5360 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5361 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5362 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5363
5364 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5365 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5366 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5367
9a799d71 5368 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5369 for (i = 0; i < 8; i++) {
5370 /* for packet buffers not used, the register should read 0 */
5371 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5372 missed_rx += mpc;
5373 adapter->stats.mpc[i] += mpc;
5374 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5375 if (hw->mac.type == ixgbe_mac_82598EB)
5376 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5377 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5378 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5379 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5380 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5381 if (hw->mac.type == ixgbe_mac_82599EB) {
5382 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5383 IXGBE_PXONRXCNT(i));
5384 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5385 IXGBE_PXOFFRXCNT(i));
5386 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5387 } else {
5388 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5389 IXGBE_PXONRXC(i));
5390 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5391 IXGBE_PXOFFRXC(i));
5392 }
2f90b865
AD		 5393 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5394 IXGBE_PXONTXC(i));
2f90b865 5395 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 5396 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5397 }
5398 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5399 /* work around hardware counting issue */
5400 adapter->stats.gprc -= missed_rx;
5401
5402 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5403 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5404 u64 tmp;
e8e26350 5405 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 5406 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5407 adapter->stats.gorc += (tmp << 32);
e8e26350 5408 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 5409 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5410 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 5411 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5412 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5413 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5414 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5415 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5416 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5417#ifdef IXGBE_FCOE
5418 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5419 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5420 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5421 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5422 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5423 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5424#endif /* IXGBE_FCOE */
e8e26350
PW		 5425 } else {
5426 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5427 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5428 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5429 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5430 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5431 }
9a799d71
AK		 5432 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5433 adapter->stats.bprc += bprc;
5434 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5435 if (hw->mac.type == ixgbe_mac_82598EB)
5436 adapter->stats.mprc -= bprc;
9a799d71
AK		 5437 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5438 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5439 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5440 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5441 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5442 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5443 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5444 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5445 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5446 adapter->stats.lxontxc += lxon;
5447 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5448 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5449 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5450 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5451 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5452 /*
5453 * 82598 errata - tx of flow control packets is included in tx counters
5454 */
5455 xon_off_tot = lxon + lxoff;
5456 adapter->stats.gptc -= xon_off_tot;
5457 adapter->stats.mptc -= xon_off_tot;
5458 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5459 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5460 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5461 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5462 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5463 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5464 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5465 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5466 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5467 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5468 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5469 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5470 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5471
5472 /* Fill out the OS statistics structure */
2d86f139 5473 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5474
5475 /* Rx Errors */
2d86f139 5476 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5477 adapter->stats.rlec;
2d86f139
AK		 5478 netdev->stats.rx_dropped = 0;
5479 netdev->stats.rx_length_errors = adapter->stats.rlec;
5480 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5481 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5482}
5483
5484/**
5485 * ixgbe_watchdog - Timer Call-back
5486 * @data: pointer to adapter cast into an unsigned long
5487 **/
5488static void ixgbe_watchdog(unsigned long data)
5489{
5490 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5491 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5492 u64 eics = 0;
5493 int i;
cf8280ee 5494
fe49f04a
AD		 5495 /*
5496 * Do the watchdog outside of interrupt context due to the lovely
5497 * delays that some of the newer hardware requires
5498 */
22d5a71b 5499
fe49f04a
AD		 5500 if (test_bit(__IXGBE_DOWN, &adapter->state))
5501 goto watchdog_short_circuit;
22d5a71b 5502
fe49f04a
AD		 5503 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5504 /*
5505 * for legacy and MSI interrupts don't set any bits
5506 * that are enabled for EIAM, because this operation
5507 * would set *both* EIMS and EICS for any bit in EIAM
5508 */
5509 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5510 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5511 goto watchdog_reschedule;
5512 }
5513
5514 /* get one bit for every active tx/rx interrupt vector */
5515 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5516 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5517 if (qv->rxr_count || qv->txr_count)
5518 eics |= ((u64)1 << i);
cf8280ee 5519 }
9a799d71 5520
fe49f04a
AD		 5521 /* Cause software interrupt to ensure rx rings are cleaned */
5522 ixgbe_irq_rearm_queues(adapter, eics);
5523
5524watchdog_reschedule:
5525 /* Reset the timer */
5526 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5527
5528watchdog_short_circuit:
cf8280ee
JB		 5529 schedule_work(&adapter->watchdog_task);
5530}
5531
e8e26350
PW		 5532/**
5533 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5534 * @work: pointer to work_struct containing our data
5535 **/
5536static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5537{
5538 struct ixgbe_adapter *adapter = container_of(work,
5539 struct ixgbe_adapter,
5540 multispeed_fiber_task);
5541 struct ixgbe_hw *hw = &adapter->hw;
5542 u32 autoneg;
8620a103 5543 bool negotiation;
e8e26350
PW		 5544
5545 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5546 autoneg = hw->phy.autoneg_advertised;
5547 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5548 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5549 hw->mac.autotry_restart = false;
8620a103
MC		 5550 if (hw->mac.ops.setup_link)
5551 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5552 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5553 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5554}
5555
5556/**
5557 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5558 * @work: pointer to work_struct containing our data
5559 **/
5560static void ixgbe_sfp_config_module_task(struct work_struct *work)
5561{
5562 struct ixgbe_adapter *adapter = container_of(work,
5563 struct ixgbe_adapter,
5564 sfp_config_module_task);
5565 struct ixgbe_hw *hw = &adapter->hw;
5566 u32 err;
5567
5568 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5569
5570 /* Time for electrical oscillations to settle down */
5571 msleep(100);
e8e26350 5572 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5573
e8e26350 5574 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5575 e_dev_err("failed to initialize because an unsupported SFP+ "
5576 "module type was detected.\n");
5577 e_dev_err("Reload the driver after installing a supported "
5578 "module.\n");
63d6e1d8 5579 unregister_netdev(adapter->netdev);
e8e26350
PW		 5580 return;
5581 }
5582 hw->mac.ops.setup_sfp(hw);
5583
8d1c3c07 5584 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5585 /* This will also work for DA Twinax connections */
5586 schedule_work(&adapter->multispeed_fiber_task);
5587 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5588}
5589
c4cf55e5
PWJ		 5590/**
5591 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5592 * @work: pointer to work_struct containing our data
5593 **/
5594static void ixgbe_fdir_reinit_task(struct work_struct *work)
5595{
5596 struct ixgbe_adapter *adapter = container_of(work,
5597 struct ixgbe_adapter,
5598 fdir_reinit_task);
5599 struct ixgbe_hw *hw = &adapter->hw;
5600 int i;
5601
5602 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5603 for (i = 0; i < adapter->num_tx_queues; i++)
5604 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5605 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5606 } else {
396e799c 5607 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5608 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5609 }
5610 /* Done FDIR Re-initialization, enable transmits */
5611 netif_tx_start_all_queues(adapter->netdev);
5612}
5613
10eec955
JF		 5614static DEFINE_MUTEX(ixgbe_watchdog_lock);
5615
cf8280ee 5616/**
69888674
AD		 5617 * ixgbe_watchdog_task - worker thread to bring link up
5618 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5619 **/
5620static void ixgbe_watchdog_task(struct work_struct *work)
5621{
5622 struct ixgbe_adapter *adapter = container_of(work,
5623 struct ixgbe_adapter,
5624 watchdog_task);
5625 struct net_device *netdev = adapter->netdev;
5626 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5627 u32 link_speed;
5628 bool link_up;
bc59fcda
NS		 5629 int i;
5630 struct ixgbe_ring *tx_ring;
5631 int some_tx_pending = 0;
cf8280ee 5632
10eec955
JF		 5633 mutex_lock(&ixgbe_watchdog_lock);
5634
5635 link_up = adapter->link_up;
5636 link_speed = adapter->link_speed;
cf8280ee
JB		 5637
5638 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5639 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5640 if (link_up) {
5641#ifdef CONFIG_DCB
5642 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5643 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5644 hw->mac.ops.fc_enable(hw, i);
264857b8 5645 } else {
620fa036 5646 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5647 }
5648#else
620fa036 5649 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5650#endif
5651 }
5652
cf8280ee
JB		 5653 if (link_up ||
5654 time_after(jiffies, (adapter->link_check_timeout +
5655 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5656 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5657 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5658 }
5659 adapter->link_up = link_up;
5660 adapter->link_speed = link_speed;
5661 }
9a799d71
AK		 5662
5663 if (link_up) {
5664 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5665 bool flow_rx, flow_tx;
5666
5667 if (hw->mac.type == ixgbe_mac_82599EB) {
5668 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5669 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5670 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5671 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5672 } else {
5673 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5674 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5675 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5676 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5677 }
5678
396e799c 5679 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5680 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5681 "10 Gbps" :
5682 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5683 "1 Gbps" : "unknown speed")),
e8e26350 5684 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5685 (flow_rx ? "RX" :
5686 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5687
5688 netif_carrier_on(netdev);
9a799d71
AK		 5689 } else {
5690 /* Force detection of hung controller */
5691 adapter->detect_tx_hung = true;
5692 }
5693 } else {
cf8280ee
JB		 5694 adapter->link_up = false;
5695 adapter->link_speed = 0;
9a799d71 5696 if (netif_carrier_ok(netdev)) {
396e799c 5697 e_info(drv, "NIC Link is Down\n");
9a799d71 5698 netif_carrier_off(netdev);
9a799d71
AK		 5699 }
5700 }
5701
bc59fcda
NS		 5702 if (!netif_carrier_ok(netdev)) {
5703 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5704 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5705 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5706 some_tx_pending = 1;
5707 break;
5708 }
5709 }
5710
5711 if (some_tx_pending) {
5712 /* We've lost link, so the controller stops DMA,
5713 * but we've got queued Tx work that's never going
5714 * to get done, so reset controller to flush Tx.
5715 * (Do the reset outside of interrupt context).
5716 */
5717 schedule_work(&adapter->reset_task);
5718 }
5719 }
5720
9a799d71 5721 ixgbe_update_stats(adapter);
10eec955 5722 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5723}
5724
9a799d71 5725static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5726 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5727 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5728{
5729 struct ixgbe_adv_tx_context_desc *context_desc;
5730 unsigned int i;
5731 int err;
5732 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5733 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5734 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5735
5736 if (skb_is_gso(skb)) {
5737 if (skb_header_cloned(skb)) {
5738 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5739 if (err)
5740 return err;
5741 }
5742 l4len = tcp_hdrlen(skb);
5743 *hdr_len += l4len;
5744
8327d000 5745 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5746 struct iphdr *iph = ip_hdr(skb);
5747 iph->tot_len = 0;
5748 iph->check = 0;
5749 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5750 iph->daddr, 0,
5751 IPPROTO_TCP,
5752 0);
8e1e8a47 5753 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5754 ipv6_hdr(skb)->payload_len = 0;
5755 tcp_hdr(skb)->check =
5756 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5757 &ipv6_hdr(skb)->daddr,
5758 0, IPPROTO_TCP, 0);
9a799d71
AK		 5759 }
5760
5761 i = tx_ring->next_to_use;
5762
5763 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5764 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5765
5766 /* VLAN MACLEN IPLEN */
5767 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5768 vlan_macip_lens |=
5769 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5770 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5771 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5772 *hdr_len += skb_network_offset(skb);
5773 vlan_macip_lens |=
5774 (skb_transport_header(skb) - skb_network_header(skb));
5775 *hdr_len +=
5776 (skb_transport_header(skb) - skb_network_header(skb));
5777 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5778 context_desc->seqnum_seed = 0;
5779
5780 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5781 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5782 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5783
8327d000 5784 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5785 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5786 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5787 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5788
5789 /* MSS L4LEN IDX */
9f8cdf4f 5790 mss_l4len_idx =
9a799d71
AK		 5791 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5792 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5793 /* use index 1 for TSO */
5794 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5795 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5796
5797 tx_buffer_info->time_stamp = jiffies;
5798 tx_buffer_info->next_to_watch = i;
5799
5800 i++;
5801 if (i == tx_ring->count)
5802 i = 0;
5803 tx_ring->next_to_use = i;
5804
5805 return true;
5806 }
5807 return false;
5808}
5809
5810static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5811 struct ixgbe_ring *tx_ring,
5812 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5813{
5814 struct ixgbe_adv_tx_context_desc *context_desc;
5815 unsigned int i;
5816 struct ixgbe_tx_buffer *tx_buffer_info;
5817 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5818
5819 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5820 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5821 i = tx_ring->next_to_use;
5822 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5823 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5824
5825 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5826 vlan_macip_lens |=
5827 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5828 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5829 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5830 if (skb->ip_summed == CHECKSUM_PARTIAL)
5831 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5832 skb_network_header(skb));
9a799d71
AK		 5833
5834 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5835 context_desc->seqnum_seed = 0;
5836
5837 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5838 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5839
5840 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5841 __be16 protocol;
5842
5843 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5844 const struct vlan_ethhdr *vhdr =
5845 (const struct vlan_ethhdr *)skb->data;
5846
5847 protocol = vhdr->h_vlan_encapsulated_proto;
5848 } else {
5849 protocol = skb->protocol;
5850 }
5851
5852 switch (protocol) {
09640e63 5853 case cpu_to_be16(ETH_P_IP):
9a799d71 5854 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5855 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5856 type_tucmd_mlhl |=
b4617240 5857 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5858 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5859 type_tucmd_mlhl |=
5860 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5861 break;
09640e63 5862 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5863 /* XXX what about other V6 headers?? */
5864 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5865 type_tucmd_mlhl |=
b4617240 5866 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5867 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5868 type_tucmd_mlhl |=
5869 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5870 break;
41825d71
AK		 5871 default:
5872 if (unlikely(net_ratelimit())) {
396e799c
ET		 5873 e_warn(probe, "partial checksum "
5874 "but proto=%x!\n",
5875 skb->protocol);
41825d71
AK		 5876 }
5877 break;
5878 }
9a799d71
AK		 5879 }
5880
5881 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5882 /* use index zero for tx checksum offload */
9a799d71
AK		 5883 context_desc->mss_l4len_idx = 0;
5884
5885 tx_buffer_info->time_stamp = jiffies;
5886 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5887
9a799d71
AK		 5888 i++;
5889 if (i == tx_ring->count)
5890 i = 0;
5891 tx_ring->next_to_use = i;
5892
5893 return true;
5894 }
9f8cdf4f 5895
9a799d71
AK		 5896 return false;
5897}
5898
5899static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5900 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5901 struct sk_buff *skb, u32 tx_flags,
5902 unsigned int first)
9a799d71 5903{
e5a43549 5904 struct pci_dev *pdev = adapter->pdev;
9a799d71 5905 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5906 unsigned int len;
5907 unsigned int total = skb->len;
9a799d71
AK		 5908 unsigned int offset = 0, size, count = 0, i;
5909 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5910 unsigned int f;
9a799d71
AK		 5911
5912 i = tx_ring->next_to_use;
5913
eacd73f7
YZ		 5914 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5915 /* excluding fcoe_crc_eof for FCoE */
5916 total -= sizeof(struct fcoe_crc_eof);
5917
5918 len = min(skb_headlen(skb), total);
9a799d71
AK		 5919 while (len) {
5920 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5921 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5922
5923 tx_buffer_info->length = size;
e5a43549 5924 tx_buffer_info->mapped_as_page = false;
1b507730 5925 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5926 skb->data + offset,
1b507730
NN		 5927 size, DMA_TO_DEVICE);
5928 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5929 goto dma_error;
9a799d71
AK		 5930 tx_buffer_info->time_stamp = jiffies;
5931 tx_buffer_info->next_to_watch = i;
5932
5933 len -= size;
eacd73f7 5934 total -= size;
9a799d71
AK		 5935 offset += size;
5936 count++;
44df32c5
AD		 5937
5938 if (len) {
5939 i++;
5940 if (i == tx_ring->count)
5941 i = 0;
5942 }
9a799d71
AK		 5943 }
5944
5945 for (f = 0; f < nr_frags; f++) {
5946 struct skb_frag_struct *frag;
5947
5948 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5949 len = min((unsigned int)frag->size, total);
e5a43549 5950 offset = frag->page_offset;
9a799d71
AK		 5951
5952 while (len) {
44df32c5
AD		 5953 i++;
5954 if (i == tx_ring->count)
5955 i = 0;
5956
9a799d71
AK		 5957 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5958 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5959
5960 tx_buffer_info->length = size;
1b507730 5961 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5962 frag->page,
5963 offset, size,
1b507730 5964 DMA_TO_DEVICE);
e5a43549 5965 tx_buffer_info->mapped_as_page = true;
1b507730 5966 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5967 goto dma_error;
9a799d71
AK		 5968 tx_buffer_info->time_stamp = jiffies;
5969 tx_buffer_info->next_to_watch = i;
5970
5971 len -= size;
eacd73f7 5972 total -= size;
9a799d71
AK		 5973 offset += size;
5974 count++;
9a799d71 5975 }
eacd73f7
YZ		 5976 if (total == 0)
5977 break;
9a799d71 5978 }
44df32c5 5979
9a799d71
AK		 5980 tx_ring->tx_buffer_info[i].skb = skb;
5981 tx_ring->tx_buffer_info[first].next_to_watch = i;
5982
e5a43549
AD		 5983 return count;
5984
5985dma_error:
849c4542 5986 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 5987
5988 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5989 tx_buffer_info->dma = 0;
5990 tx_buffer_info->time_stamp = 0;
5991 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5992 if (count)
5993 count--;
e5a43549
AD		 5994
5995 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5996 while (count--) {
5997 if (i==0)
e5a43549 5998 i += tx_ring->count;
c1fa347f 5999 i--;
e5a43549
AD		 6000 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6001 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6002 }
6003
e44d38e1 6004 return 0;
9a799d71
AK		 6005}
6006
6007static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 6008 struct ixgbe_ring *tx_ring,
6009 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6010{
6011 union ixgbe_adv_tx_desc *tx_desc = NULL;
6012 struct ixgbe_tx_buffer *tx_buffer_info;
6013 u32 olinfo_status = 0, cmd_type_len = 0;
6014 unsigned int i;
6015 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6016
6017 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6018
6019 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6020
6021 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6022 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6023
6024 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6025 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6026
6027 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6028 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6029
4eeae6fd
PW		 6030 /* use index 1 context for tso */
6031 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6032 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6033 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 6034 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6035
6036 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6037 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6038 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6039
eacd73f7
YZ		 6040 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6041 olinfo_status |= IXGBE_ADVTXD_CC;
6042 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6043 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6044 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6045 }
6046
9a799d71
AK		 6047 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6048
6049 i = tx_ring->next_to_use;
6050 while (count--) {
6051 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6052 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6053 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6054 tx_desc->read.cmd_type_len =
b4617240 6055 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6056 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6057 i++;
6058 if (i == tx_ring->count)
6059 i = 0;
6060 }
6061
6062 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6063
6064 /*
6065 * Force memory writes to complete before letting h/w
6066 * know there are new descriptors to fetch. (Only
6067 * applicable for weak-ordered memory model archs,
6068 * such as IA-64).
6069 */
6070 wmb();
6071
6072 tx_ring->next_to_use = i;
6073 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6074}
6075
c4cf55e5
PWJ		 6076static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6077 int queue, u32 tx_flags)
6078{
c4cf55e5
PWJ		 6079 struct ixgbe_atr_input atr_input;
6080 struct tcphdr *th;
c4cf55e5
PWJ		 6081 struct iphdr *iph = ip_hdr(skb);
6082 struct ethhdr *eth = (struct ethhdr *)skb->data;
6083 u16 vlan_id, src_port, dst_port, flex_bytes;
6084 u32 src_ipv4_addr, dst_ipv4_addr;
6085 u8 l4type = 0;
6086
d3ead241
GG		 6087 /* Right now, we support IPv4 only */
6088 if (skb->protocol != htons(ETH_P_IP))
6089 return;
c4cf55e5
PWJ		 6090 /* check if we're UDP or TCP */
6091 if (iph->protocol == IPPROTO_TCP) {
6092 th = tcp_hdr(skb);
6093 src_port = th->source;
6094 dst_port = th->dest;
6095 l4type |= IXGBE_ATR_L4TYPE_TCP;
6096 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6097 } else {
6098 /* Unsupported L4 header, just bail here */
6099 return;
6100 }
6101
6102 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6103
6104 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6105 IXGBE_TX_FLAGS_VLAN_SHIFT;
6106 src_ipv4_addr = iph->saddr;
6107 dst_ipv4_addr = iph->daddr;
6108 flex_bytes = eth->h_proto;
6109
6110 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6111 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6112 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6113 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6114 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6115 /* src and dst are inverted, think how the receiver sees them */
6116 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6117 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6118
6119 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6120 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6121}
6122
e092be60 6123static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6124 struct ixgbe_ring *tx_ring, int size)
e092be60 6125{
30eba97a 6126 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6127 /* Herbert's original patch had:
6128 * smp_mb__after_netif_stop_queue();
6129 * but since that doesn't exist yet, just open code it. */
6130 smp_mb();
6131
6132 /* We need to check again in a case another CPU has just
6133 * made room available. */
6134 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6135 return -EBUSY;
6136
6137 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6138 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6139 ++tx_ring->restart_queue;
e092be60
AV		 6140 return 0;
6141}
6142
6143static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6144 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6145{
6146 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6147 return 0;
6148 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6149}
6150
09a3b1f8
SH		 6151static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6152{
6153 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6154 int txq = smp_processor_id();
09a3b1f8 6155
56075a98
JF		 6156#ifdef IXGBE_FCOE
6157 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6158 (skb->protocol == htons(ETH_P_FIP))) {
6159 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6160 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6161 txq += adapter->ring_feature[RING_F_FCOE].mask;
6162 return txq;
4bc091d8 6163#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6164 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6165 txq = adapter->fcoe.up;
6166 return txq;
4bc091d8 6167#endif
56075a98
JF		 6168 }
6169 }
6170#endif
6171
fdd3d631
KK		 6172 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6173 while (unlikely(txq >= dev->real_num_tx_queues))
6174 txq -= dev->real_num_tx_queues;
5f715823 6175 return txq;
fdd3d631 6176 }
c4cf55e5 6177
2ea186ae
JF		 6178 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6179 if (skb->priority == TC_PRIO_CONTROL)
6180 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6181 else
6182 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6183 >> 13;
6184 return txq;
6185 }
09a3b1f8
SH		 6186
6187 return skb_tx_hash(dev, skb);
6188}
6189
3b29a56d
SH		 6190static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6191 struct net_device *netdev)
9a799d71
AK		 6192{
6193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6194 struct ixgbe_ring *tx_ring;
60d51134 6195 struct netdev_queue *txq;
9a799d71
AK		 6196 unsigned int first;
6197 unsigned int tx_flags = 0;
30eba97a 6198 u8 hdr_len = 0;
5f715823 6199 int tso;
9a799d71
AK		 6200 int count = 0;
6201 unsigned int f;
9f8cdf4f 6202
9f8cdf4f
JB		 6203 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6204 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6205 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6206 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6207 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6208 }
6209 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6210 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6211 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6212 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6213 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6214 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6215 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6216 }
eacd73f7 6217
4a0b9ca0 6218 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 6219
09ad1cc0 6220#ifdef IXGBE_FCOE
56075a98
JF		 6221 /* for FCoE with DCB, we force the priority to what
6222 * was specified by the switch */
6223 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6224 (skb->protocol == htons(ETH_P_FCOE) ||
6225 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6226#ifdef CONFIG_IXGBE_DCB
6227 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6228 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6229 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6230 tx_flags |= ((adapter->fcoe.up << 13)
6231 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6232 }
6233#endif
ca77cd59
RL		 6234 /* flag for FCoE offloads */
6235 if (skb->protocol == htons(ETH_P_FCOE))
6236 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6237 }
ca77cd59
RL		 6238#endif
6239
eacd73f7 6240 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6241 if (skb_is_gso(skb) ||
6242 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6243 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6244 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6245 count++;
6246
9f8cdf4f
JB		 6247 count += TXD_USE_COUNT(skb_headlen(skb));
6248 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6249 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6250
e092be60 6251 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6252 adapter->tx_busy++;
9a799d71
AK		 6253 return NETDEV_TX_BUSY;
6254 }
9a799d71 6255
9a799d71 6256 first = tx_ring->next_to_use;
eacd73f7
YZ		 6257 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6258#ifdef IXGBE_FCOE
6259 /* setup tx offload for FCoE */
6260 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6261 if (tso < 0) {
6262 dev_kfree_skb_any(skb);
6263 return NETDEV_TX_OK;
6264 }
6265 if (tso)
6266 tx_flags |= IXGBE_TX_FLAGS_FSO;
6267#endif /* IXGBE_FCOE */
6268 } else {
6269 if (skb->protocol == htons(ETH_P_IP))
6270 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6271 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6272 if (tso < 0) {
6273 dev_kfree_skb_any(skb);
6274 return NETDEV_TX_OK;
6275 }
9a799d71 6276
eacd73f7
YZ		 6277 if (tso)
6278 tx_flags |= IXGBE_TX_FLAGS_TSO;
6279 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6280 (skb->ip_summed == CHECKSUM_PARTIAL))
6281 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6282 }
9a799d71 6283
eacd73f7 6284 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6285 if (count) {
c4cf55e5
PWJ		 6286 /* add the ATR filter if ATR is on */
6287 if (tx_ring->atr_sample_rate) {
6288 ++tx_ring->atr_count;
6289 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6290 test_bit(__IXGBE_FDIR_INIT_DONE,
6291 &tx_ring->reinit_state)) {
6292 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6293 tx_flags);
6294 tx_ring->atr_count = 0;
6295 }
6296 }
60d51134
ED		 6297 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6298 txq->tx_bytes += skb->len;
6299 txq->tx_packets++;
44df32c5
AD		 6300 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6301 hdr_len);
44df32c5 6302 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6303
44df32c5
AD		 6304 } else {
6305 dev_kfree_skb_any(skb);
6306 tx_ring->tx_buffer_info[first].time_stamp = 0;
6307 tx_ring->next_to_use = first;
6308 }
9a799d71
AK		 6309
6310 return NETDEV_TX_OK;
6311}
6312
9a799d71
AK		 6313/**
6314 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6315 * @netdev: network interface device structure
6316 * @p: pointer to an address structure
6317 *
6318 * Returns 0 on success, negative on failure
6319 **/
6320static int ixgbe_set_mac(struct net_device *netdev, void *p)
6321{
6322 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6323 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6324 struct sockaddr *addr = p;
6325
6326 if (!is_valid_ether_addr(addr->sa_data))
6327 return -EADDRNOTAVAIL;
6328
6329 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6330 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6331
1cdd1ec8
GR		 6332 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6333 IXGBE_RAH_AV);
9a799d71
AK		 6334
6335 return 0;
6336}
6337
6b73e10d
BH		 6338static int
6339ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6340{
6341 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6342 struct ixgbe_hw *hw = &adapter->hw;
6343 u16 value;
6344 int rc;
6345
6346 if (prtad != hw->phy.mdio.prtad)
6347 return -EINVAL;
6348 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6349 if (!rc)
6350 rc = value;
6351 return rc;
6352}
6353
6354static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6355 u16 addr, u16 value)
6356{
6357 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6358 struct ixgbe_hw *hw = &adapter->hw;
6359
6360 if (prtad != hw->phy.mdio.prtad)
6361 return -EINVAL;
6362 return hw->phy.ops.write_reg(hw, addr, devad, value);
6363}
6364
6365static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6366{
6367 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6368
6369 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6370}
6371
0365e6e4
PW		 6372/**
6373 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6374 * netdev->dev_addrs
0365e6e4
PW		 6375 * @netdev: network interface device structure
6376 *
6377 * Returns non-zero on failure
6378 **/
6379static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6380{
6381 int err = 0;
6382 struct ixgbe_adapter *adapter = netdev_priv(dev);
6383 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6384
6385 if (is_valid_ether_addr(mac->san_addr)) {
6386 rtnl_lock();
6387 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6388 rtnl_unlock();
6389 }
6390 return err;
6391}
6392
6393/**
6394 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6395 * netdev->dev_addrs
0365e6e4
PW		 6396 * @netdev: network interface device structure
6397 *
6398 * Returns non-zero on failure
6399 **/
6400static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6401{
6402 int err = 0;
6403 struct ixgbe_adapter *adapter = netdev_priv(dev);
6404 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6405
6406 if (is_valid_ether_addr(mac->san_addr)) {
6407 rtnl_lock();
6408 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6409 rtnl_unlock();
6410 }
6411 return err;
6412}
6413
9a799d71
AK		 6414#ifdef CONFIG_NET_POLL_CONTROLLER
6415/*
6416 * Polling 'interrupt' - used by things like netconsole to send skbs
6417 * without having to re-enable interrupts. It's not called while
6418 * the interrupt routine is executing.
6419 */
6420static void ixgbe_netpoll(struct net_device *netdev)
6421{
6422 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6423 int i;
9a799d71 6424
1a647bd2
AD		 6425 /* if interface is down do nothing */
6426 if (test_bit(__IXGBE_DOWN, &adapter->state))
6427 return;
6428
9a799d71 6429 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6430 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6431 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6432 for (i = 0; i < num_q_vectors; i++) {
6433 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6434 ixgbe_msix_clean_many(0, q_vector);
6435 }
6436 } else {
6437 ixgbe_intr(adapter->pdev->irq, netdev);
6438 }
9a799d71 6439 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6440}
6441#endif
6442
0edc3527
SH		 6443static const struct net_device_ops ixgbe_netdev_ops = {
6444 .ndo_open = ixgbe_open,
6445 .ndo_stop = ixgbe_close,
00829823 6446 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6447 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6448 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6449 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6450 .ndo_validate_addr = eth_validate_addr,
6451 .ndo_set_mac_address = ixgbe_set_mac,
6452 .ndo_change_mtu = ixgbe_change_mtu,
6453 .ndo_tx_timeout = ixgbe_tx_timeout,
6454 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6455 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6456 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6457 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6458 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6459 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6460 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6461 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6462#ifdef CONFIG_NET_POLL_CONTROLLER
6463 .ndo_poll_controller = ixgbe_netpoll,
6464#endif
332d4a7d
YZ		 6465#ifdef IXGBE_FCOE
6466 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6467 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6468 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6469 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6470 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6471#endif /* IXGBE_FCOE */
0edc3527
SH		 6472};
6473
1cdd1ec8
GR		 6474static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6475 const struct ixgbe_info *ii)
6476{
6477#ifdef CONFIG_PCI_IOV
6478 struct ixgbe_hw *hw = &adapter->hw;
6479 int err;
6480
6481 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6482 return;
6483
6484 /* The 82599 supports up to 64 VFs per physical function
6485 * but this implementation limits allocation to 63 so that
6486 * basic networking resources are still available to the
6487 * physical function
6488 */
6489 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6490 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6491 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6492 if (err) {
396e799c 6493 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6494 goto err_novfs;
6495 }
6496 /* If call to enable VFs succeeded then allocate memory
6497 * for per VF control structures.
6498 */
6499 adapter->vfinfo =
6500 kcalloc(adapter->num_vfs,
6501 sizeof(struct vf_data_storage), GFP_KERNEL);
6502 if (adapter->vfinfo) {
6503 /* Now that we're sure SR-IOV is enabled
6504 * and memory allocated set up the mailbox parameters
6505 */
6506 ixgbe_init_mbx_params_pf(hw);
6507 memcpy(&hw->mbx.ops, ii->mbx_ops,
6508 sizeof(hw->mbx.ops));
6509
6510 /* Disable RSC when in SR-IOV mode */
6511 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6512 IXGBE_FLAG2_RSC_ENABLED);
6513 return;
6514 }
6515
6516 /* Oh oh */
396e799c
ET		 6517 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6518 "SRIOV disabled\n");
1cdd1ec8
GR		 6519 pci_disable_sriov(adapter->pdev);
6520
6521err_novfs:
6522 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6523 adapter->num_vfs = 0;
6524#endif /* CONFIG_PCI_IOV */
6525}
6526
9a799d71
AK		 6527/**
6528 * ixgbe_probe - Device Initialization Routine
6529 * @pdev: PCI device information struct
6530 * @ent: entry in ixgbe_pci_tbl
6531 *
6532 * Returns 0 on success, negative on failure
6533 *
6534 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6535 * The OS initialization, configuring of the adapter private structure,
6536 * and a hardware reset occur.
6537 **/
6538static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6539 const struct pci_device_id *ent)
9a799d71
AK		 6540{
6541 struct net_device *netdev;
6542 struct ixgbe_adapter *adapter = NULL;
6543 struct ixgbe_hw *hw;
6544 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6545 static int cards_found;
6546 int i, err, pci_using_dac;
c85a2618 6547 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6548#ifdef IXGBE_FCOE
6549 u16 device_caps;
6550#endif
c44ade9e 6551 u32 part_num, eec;
9a799d71 6552
bded64a7
AG		 6553 /* Catch broken hardware that put the wrong VF device ID in
6554 * the PCIe SR-IOV capability.
6555 */
6556 if (pdev->is_virtfn) {
6557 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6558 pci_name(pdev), pdev->vendor, pdev->device);
6559 return -EINVAL;
6560 }
6561
9ce77666 6562 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6563 if (err)
6564 return err;
6565
1b507730
NN		 6566 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6567 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6568 pci_using_dac = 1;
6569 } else {
1b507730 6570 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6571 if (err) {
1b507730
NN		 6572 err = dma_set_coherent_mask(&pdev->dev,
6573 DMA_BIT_MASK(32));
9a799d71 6574 if (err) {
b8bc0421
DC		 6575 dev_err(&pdev->dev,
6576 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6577 goto err_dma;
6578 }
6579 }
6580 pci_using_dac = 0;
6581 }
6582
9ce77666 6583 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6584 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6585 if (err) {
b8bc0421
DC		 6586 dev_err(&pdev->dev,
6587 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6588 goto err_pci_reg;
6589 }
6590
19d5afd4 6591 pci_enable_pcie_error_reporting(pdev);
6fabd715 6592
9a799d71 6593 pci_set_master(pdev);
fb3b27bc 6594 pci_save_state(pdev);
9a799d71 6595
c85a2618
JF		 6596 if (ii->mac == ixgbe_mac_82598EB)
6597 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6598 else
6599 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6600
6601 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6602#ifdef IXGBE_FCOE
6603 indices += min_t(unsigned int, num_possible_cpus(),
6604 IXGBE_MAX_FCOE_INDICES);
6605#endif
c85a2618 6606 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6607 if (!netdev) {
6608 err = -ENOMEM;
6609 goto err_alloc_etherdev;
6610 }
6611
9a799d71
AK		 6612 SET_NETDEV_DEV(netdev, &pdev->dev);
6613
6614 pci_set_drvdata(pdev, netdev);
6615 adapter = netdev_priv(netdev);
6616
6617 adapter->netdev = netdev;
6618 adapter->pdev = pdev;
6619 hw = &adapter->hw;
6620 hw->back = adapter;
6621 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6622
05857980
JK		 6623 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6624 pci_resource_len(pdev, 0));
9a799d71
AK		 6625 if (!hw->hw_addr) {
6626 err = -EIO;
6627 goto err_ioremap;
6628 }
6629
6630 for (i = 1; i <= 5; i++) {
6631 if (pci_resource_len(pdev, i) == 0)
6632 continue;
6633 }
6634
0edc3527 6635 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6636 ixgbe_set_ethtool_ops(netdev);
9a799d71 6637 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6638 strcpy(netdev->name, pci_name(pdev));
6639
9a799d71
AK		 6640 adapter->bd_number = cards_found;
6641
9a799d71
AK		 6642 /* Setup hw api */
6643 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6644 hw->mac.type = ii->mac;
9a799d71 6645
c44ade9e
JB		 6646 /* EEPROM */
6647 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6648 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6649 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6650 if (!(eec & (1 << 8)))
6651 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6652
6653 /* PHY */
6654 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6655 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6656 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6657 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6658 hw->phy.mdio.mmds = 0;
6659 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6660 hw->phy.mdio.dev = netdev;
6661 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6662 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6663
6664 /* set up this timer and work struct before calling get_invariants
6665 * which might start the timer
6666 */
6667 init_timer(&adapter->sfp_timer);
6668 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6669 adapter->sfp_timer.data = (unsigned long) adapter;
6670
6671 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6672
e8e26350
PW		 6673 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6674 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6675
6676 /* a new SFP+ module arrival, called from GPI SDP2 context */
6677 INIT_WORK(&adapter->sfp_config_module_task,
6678 ixgbe_sfp_config_module_task);
6679
8ca783ab 6680 ii->get_invariants(hw);
9a799d71
AK		 6681
6682 /* setup the private structure */
6683 err = ixgbe_sw_init(adapter);
6684 if (err)
6685 goto err_sw_init;
6686
e86bff0e
DS		 6687 /* Make it possible the adapter to be woken up via WOL */
6688 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6689 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6690
bf069c97
DS		 6691 /*
6692 * If there is a fan on this device and it has failed log the
6693 * failure.
6694 */
6695 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6696 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6697 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6698 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6699 }
6700
c44ade9e 6701 /* reset_hw fills in the perm_addr as well */
119fc60a 6702 hw->phy.reset_if_overtemp = true;
c44ade9e 6703 err = hw->mac.ops.reset_hw(hw);
119fc60a 6704 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6705 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6706 hw->mac.type == ixgbe_mac_82598EB) {
6707 /*
6708 * Start a kernel thread to watch for a module to arrive.
6709 * Only do this for 82598, since 82599 will generate
6710 * interrupts on module arrival.
6711 */
6712 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6713 mod_timer(&adapter->sfp_timer,
6714 round_jiffies(jiffies + (2 * HZ)));
6715 err = 0;
6716 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6717 e_dev_err("failed to initialize because an unsupported SFP+ "
6718 "module type was detected.\n");
6719 e_dev_err("Reload the driver after installing a supported "
6720 "module.\n");
04f165ef
PW		 6721 goto err_sw_init;
6722 } else if (err) {
849c4542 6723 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6724 goto err_sw_init;
6725 }
6726
1cdd1ec8
GR		 6727 ixgbe_probe_vf(adapter, ii);
6728
396e799c 6729 netdev->features = NETIF_F_SG |
b4617240
PW		 6730 NETIF_F_IP_CSUM |
6731 NETIF_F_HW_VLAN_TX |
6732 NETIF_F_HW_VLAN_RX |
6733 NETIF_F_HW_VLAN_FILTER;
9a799d71 6734
e9990a9c 6735 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6736 netdev->features |= NETIF_F_TSO;
9a799d71 6737 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6738 netdev->features |= NETIF_F_GRO;
ad31c402 6739
45a5ead0
JB		 6740 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6741 netdev->features |= NETIF_F_SCTP_CSUM;
6742
ad31c402
JK		 6743 netdev->vlan_features |= NETIF_F_TSO;
6744 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6745 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6746 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6747 netdev->vlan_features |= NETIF_F_SG;
6748
1cdd1ec8
GR		 6749 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6750 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6751 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6752 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6753 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6754
7a6b6f51 6755#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6756 netdev->dcbnl_ops = &dcbnl_ops;
6757#endif
6758
eacd73f7 6759#ifdef IXGBE_FCOE
0d551589 6760 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6761 if (hw->mac.ops.get_device_caps) {
6762 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6763 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6764 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6765 }
6766 }
5e09d7f6
YZ		 6767 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6768 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6769 netdev->vlan_features |= NETIF_F_FSO;
6770 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6771 }
eacd73f7 6772#endif /* IXGBE_FCOE */
9a799d71
AK		 6773 if (pci_using_dac)
6774 netdev->features |= NETIF_F_HIGHDMA;
6775
0c19d6af 6776 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6777 netdev->features |= NETIF_F_LRO;
6778
9a799d71 6779 /* make sure the EEPROM is good */
c44ade9e 6780 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6781 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6782 err = -EIO;
6783 goto err_eeprom;
6784 }
6785
6786 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6787 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6788
c44ade9e 6789 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6790 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6791 err = -EIO;
6792 goto err_eeprom;
6793 }
6794
61fac744
PW		 6795 /* power down the optics */
6796 if (hw->phy.multispeed_fiber)
6797 hw->mac.ops.disable_tx_laser(hw);
6798
9a799d71
AK		 6799 init_timer(&adapter->watchdog_timer);
6800 adapter->watchdog_timer.function = &ixgbe_watchdog;
6801 adapter->watchdog_timer.data = (unsigned long)adapter;
6802
6803 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6804 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6805
021230d4
AV		 6806 err = ixgbe_init_interrupt_scheme(adapter);
6807 if (err)
6808 goto err_sw_init;
9a799d71 6809
e8e26350
PW		 6810 switch (pdev->device) {
6811 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6812 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6813 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6814 break;
6815 default:
6816 adapter->wol = 0;
6817 break;
6818 }
e8e26350
PW		 6819 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6820
04f165ef
PW		 6821 /* pick up the PCI bus settings for reporting later */
6822 hw->mac.ops.get_bus_info(hw);
6823
9a799d71 6824 /* print bus type/speed/width info */
849c4542 6825 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6826 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6827 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6828 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6829 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6830 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6831 "Unknown"),
7c510e4b 6832 netdev->dev_addr);
c44ade9e 6833 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6834 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6835 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6836 "PBA No: %06x-%03x\n",
6837 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6838 (part_num >> 8), (part_num & 0xff));
e8e26350 6839 else
849c4542
ET		 6840 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6841 hw->mac.type, hw->phy.type,
6842 (part_num >> 8), (part_num & 0xff));
9a799d71 6843
e8e26350 6844 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6845 e_dev_warn("PCI-Express bandwidth available for this card is "
6846 "not sufficient for optimal performance.\n");
6847 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6848 "is required.\n");
0c254d86
AK		 6849 }
6850
34b0368c
PWJ		 6851 /* save off EEPROM version number */
6852 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6853
9a799d71 6854 /* reset the hardware with the new settings */
794caeb2 6855 err = hw->mac.ops.start_hw(hw);
c44ade9e 6856
794caeb2
PWJ		 6857 if (err == IXGBE_ERR_EEPROM_VERSION) {
6858 /* We are running on a pre-production device, log a warning */
849c4542
ET		 6859 e_dev_warn("This device is a pre-production adapter/LOM. "
6860 "Please be aware there may be issues associated "
6861 "with your hardware. If you are experiencing "
6862 "problems please contact your Intel or hardware "
6863 "representative who provided you with this "
6864 "hardware.\n");
794caeb2 6865 }
9a799d71
AK		 6866 strcpy(netdev->name, "eth%d");
6867 err = register_netdev(netdev);
6868 if (err)
6869 goto err_register;
6870
54386467
JB		 6871 /* carrier off reporting is important to ethtool even BEFORE open */
6872 netif_carrier_off(netdev);
6873
c4cf55e5
PWJ		 6874 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6875 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6876 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6877
119fc60a
MC		 6878 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6879 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
5dd2d332 6880#ifdef CONFIG_IXGBE_DCA
652f093f 6881 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6882 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6883 ixgbe_setup_dca(adapter);
6884 }
6885#endif
1cdd1ec8 6886 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 6887 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 6888 for (i = 0; i < adapter->num_vfs; i++)
6889 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6890 }
6891
0365e6e4
PW		 6892 /* add san mac addr to netdev */
6893 ixgbe_add_sanmac_netdev(netdev);
9a799d71 6894
849c4542 6895 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 6896 cards_found++;
6897 return 0;
6898
6899err_register:
5eba3699 6900 ixgbe_release_hw_control(adapter);
7a921c93 6901 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6902err_sw_init:
6903err_eeprom:
1cdd1ec8
GR		 6904 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6905 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6906 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6907 del_timer_sync(&adapter->sfp_timer);
6908 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6909 cancel_work_sync(&adapter->multispeed_fiber_task);
6910 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6911 iounmap(hw->hw_addr);
6912err_ioremap:
6913 free_netdev(netdev);
6914err_alloc_etherdev:
9ce77666 6915 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6916 IORESOURCE_MEM));
9a799d71
AK		 6917err_pci_reg:
6918err_dma:
6919 pci_disable_device(pdev);
6920 return err;
6921}
6922
6923/**
6924 * ixgbe_remove - Device Removal Routine
6925 * @pdev: PCI device information struct
6926 *
6927 * ixgbe_remove is called by the PCI subsystem to alert the driver
6928 * that it should release a PCI device. The could be caused by a
6929 * Hot-Plug event, or because the driver is going to be removed from
6930 * memory.
6931 **/
6932static void __devexit ixgbe_remove(struct pci_dev *pdev)
6933{
6934 struct net_device *netdev = pci_get_drvdata(pdev);
6935 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6936
6937 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6938 /* clear the module not found bit to make sure the worker won't
6939 * reschedule
6940 */
6941 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6942 del_timer_sync(&adapter->watchdog_timer);
6943
c4900be0
DS		 6944 del_timer_sync(&adapter->sfp_timer);
6945 cancel_work_sync(&adapter->watchdog_task);
6946 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6947 cancel_work_sync(&adapter->multispeed_fiber_task);
6948 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6949 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6950 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6951 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6952 flush_scheduled_work();
6953
5dd2d332 6954#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6955 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6956 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6957 dca_remove_requester(&pdev->dev);
6958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6959 }
6960
6961#endif
332d4a7d
YZ		 6962#ifdef IXGBE_FCOE
6963 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6964 ixgbe_cleanup_fcoe(adapter);
6965
6966#endif /* IXGBE_FCOE */
0365e6e4
PW		 6967
6968 /* remove the added san mac */
6969 ixgbe_del_sanmac_netdev(netdev);
6970
c4900be0
DS		 6971 if (netdev->reg_state == NETREG_REGISTERED)
6972 unregister_netdev(netdev);
9a799d71 6973
1cdd1ec8
GR		 6974 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6975 ixgbe_disable_sriov(adapter);
6976
7a921c93 6977 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6978
021230d4 6979 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6980
6981 iounmap(adapter->hw.hw_addr);
9ce77666 6982 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6983 IORESOURCE_MEM));
9a799d71 6984
849c4542 6985 e_dev_info("complete\n");
021230d4 6986
9a799d71
AK		 6987 free_netdev(netdev);
6988
19d5afd4 6989 pci_disable_pcie_error_reporting(pdev);
6fabd715 6990
9a799d71
AK		 6991 pci_disable_device(pdev);
6992}
6993
6994/**
6995 * ixgbe_io_error_detected - called when PCI error is detected
6996 * @pdev: Pointer to PCI device
6997 * @state: The current pci connection state
6998 *
6999 * This function is called after a PCI bus error affecting
7000 * this device has been detected.
7001 */
7002static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 7003 pci_channel_state_t state)
9a799d71
AK		 7004{
7005 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7007
7008 netif_device_detach(netdev);
7009
3044b8d1
BL		 7010 if (state == pci_channel_io_perm_failure)
7011 return PCI_ERS_RESULT_DISCONNECT;
7012
9a799d71
AK		 7013 if (netif_running(netdev))
7014 ixgbe_down(adapter);
7015 pci_disable_device(pdev);
7016
b4617240 7017 /* Request a slot reset. */
9a799d71
AK		 7018 return PCI_ERS_RESULT_NEED_RESET;
7019}
7020
7021/**
7022 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7023 * @pdev: Pointer to PCI device
7024 *
7025 * Restart the card from scratch, as if from a cold-boot.
7026 */
7027static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7028{
7029 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7030 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7031 pci_ers_result_t result;
7032 int err;
9a799d71 7033
9ce77666 7034 if (pci_enable_device_mem(pdev)) {
396e799c 7035 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7036 result = PCI_ERS_RESULT_DISCONNECT;
7037 } else {
7038 pci_set_master(pdev);
7039 pci_restore_state(pdev);
c0e1f68b 7040 pci_save_state(pdev);
9a799d71 7041
dd4d8ca6 7042 pci_wake_from_d3(pdev, false);
9a799d71 7043
6fabd715 7044 ixgbe_reset(adapter);
88512539 7045 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7046 result = PCI_ERS_RESULT_RECOVERED;
7047 }
7048
7049 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7050 if (err) {
849c4542
ET		 7051 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7052 "failed 0x%0x\n", err);
6fabd715
PWJ		 7053 /* non-fatal, continue */
7054 }
9a799d71 7055
6fabd715 7056 return result;
9a799d71
AK		 7057}
7058
7059/**
7060 * ixgbe_io_resume - called when traffic can start flowing again.
7061 * @pdev: Pointer to PCI device
7062 *
7063 * This callback is called when the error recovery driver tells us that
7064 * its OK to resume normal operation.
7065 */
7066static void ixgbe_io_resume(struct pci_dev *pdev)
7067{
7068 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7069 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7070
7071 if (netif_running(netdev)) {
7072 if (ixgbe_up(adapter)) {
396e799c 7073 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7074 return;
7075 }
7076 }
7077
7078 netif_device_attach(netdev);
9a799d71
AK		 7079}
7080
7081static struct pci_error_handlers ixgbe_err_handler = {
7082 .error_detected = ixgbe_io_error_detected,
7083 .slot_reset = ixgbe_io_slot_reset,
7084 .resume = ixgbe_io_resume,
7085};
7086
7087static struct pci_driver ixgbe_driver = {
7088 .name = ixgbe_driver_name,
7089 .id_table = ixgbe_pci_tbl,
7090 .probe = ixgbe_probe,
7091 .remove = __devexit_p(ixgbe_remove),
7092#ifdef CONFIG_PM
7093 .suspend = ixgbe_suspend,
7094 .resume = ixgbe_resume,
7095#endif
7096 .shutdown = ixgbe_shutdown,
7097 .err_handler = &ixgbe_err_handler
7098};
7099
7100/**
7101 * ixgbe_init_module - Driver Registration Routine
7102 *
7103 * ixgbe_init_module is the first routine called when the driver is
7104 * loaded. All it does is register with the PCI subsystem.
7105 **/
7106static int __init ixgbe_init_module(void)
7107{
7108 int ret;
849c4542
ET		 7109 pr_info("%s - version %s\n", ixgbe_driver_string,
7110 ixgbe_driver_version);
7111 pr_info("%s\n", ixgbe_copyright);
9a799d71 7112
5dd2d332 7113#ifdef CONFIG_IXGBE_DCA
bd0362dd 7114 dca_register_notify(&dca_notifier);
bd0362dd 7115#endif
5dd2d332 7116
9a799d71
AK		 7117 ret = pci_register_driver(&ixgbe_driver);
7118 return ret;
7119}
b4617240 7120
9a799d71
AK		 7121module_init(ixgbe_init_module);
7122
7123/**
7124 * ixgbe_exit_module - Driver Exit Cleanup Routine
7125 *
7126 * ixgbe_exit_module is called just before the driver is removed
7127 * from memory.
7128 **/
7129static void __exit ixgbe_exit_module(void)
7130{
5dd2d332 7131#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7132 dca_unregister_notify(&dca_notifier);
7133#endif
9a799d71
AK		 7134 pci_unregister_driver(&ixgbe_driver);
7135}
bd0362dd 7136
5dd2d332 7137#ifdef CONFIG_IXGBE_DCA
bd0362dd 7138static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 7139 void *p)
bd0362dd
JC		 7140{
7141 int ret_val;
7142
7143 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 7144 __ixgbe_notify_dca);
bd0362dd
JC		 7145
7146 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7147}
b453368d 7148
5dd2d332 7149#endif /* CONFIG_IXGBE_DCA */
849c4542 7150
b453368d 7151/**
849c4542 7152 * ixgbe_get_hw_dev return device
b453368d
AD		 7153 * used by hardware layer to print debugging information
7154 **/
849c4542 7155struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7156{
7157 struct ixgbe_adapter *adapter = hw->back;
849c4542 7158 return adapter->netdev;
b453368d 7159}
bd0362dd 7160
9a799d71
AK		 7161module_exit(ixgbe_exit_module);
7162
7163/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree