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9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
8d792cd9 51#define DRV_VERSION "1.3.18-k4"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
bd0362dd
JC		 83#ifdef CONFIG_DCA
84static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
85 void *p);
86static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90};
91#endif
92
9a799d71
AK		 93MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
98#define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
5eba3699
AV		 100static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
108}
109
110static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
118}
9a799d71
AK		 119
120#ifdef DEBUG
121/**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126{
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130}
131#endif
132
133static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
134 u8 msix_vector)
135{
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144}
145
146static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
149{
150 if (tx_buffer_info->dma) {
151 pci_unmap_page(adapter->pdev,
152 tx_buffer_info->dma,
153 tx_buffer_info->length, PCI_DMA_TODEVICE);
154 tx_buffer_info->dma = 0;
155 }
156 if (tx_buffer_info->skb) {
157 dev_kfree_skb_any(tx_buffer_info->skb);
158 tx_buffer_info->skb = NULL;
159 }
160 /* tx_buffer_info must be completely set up in the transmit path */
161}
162
163static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
164 struct ixgbe_ring *tx_ring,
165 unsigned int eop,
166 union ixgbe_adv_tx_desc *eop_desc)
167{
168 /* Detect a transmit hang in hardware, this serializes the
169 * check with the clearing of time_stamp and movement of i */
170 adapter->detect_tx_hung = false;
171 if (tx_ring->tx_buffer_info[eop].dma &&
172 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
173 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
174 /* detected Tx unit hang */
175 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
176 " TDH <%x>\n"
177 " TDT <%x>\n"
178 " next_to_use <%x>\n"
179 " next_to_clean <%x>\n"
180 "tx_buffer_info[next_to_clean]\n"
181 " time_stamp <%lx>\n"
182 " next_to_watch <%x>\n"
183 " jiffies <%lx>\n"
184 " next_to_watch.status <%x>\n",
185 readl(adapter->hw.hw_addr + tx_ring->head),
186 readl(adapter->hw.hw_addr + tx_ring->tail),
187 tx_ring->next_to_use,
188 tx_ring->next_to_clean,
189 tx_ring->tx_buffer_info[eop].time_stamp,
190 eop, jiffies, eop_desc->wb.status);
191 return true;
192 }
193
194 return false;
195}
196
e092be60
AV		 197#define IXGBE_MAX_TXD_PWR 14
198#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
199
200/* Tx Descriptors needed, worst case */
201#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
202 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
203#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
204 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
205
9a799d71
AK		 206/**
207 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
208 * @adapter: board private structure
209 **/
210static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
211 struct ixgbe_ring *tx_ring)
212{
213 struct net_device *netdev = adapter->netdev;
214 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
215 struct ixgbe_tx_buffer *tx_buffer_info;
216 unsigned int i, eop;
217 bool cleaned = false;
e092be60 218 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
9a799d71
AK		 219
220 i = tx_ring->next_to_clean;
221 eop = tx_ring->tx_buffer_info[i].next_to_watch;
222 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
223 while (eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) {
e092be60
AV		 224 cleaned = false;
225 while (!cleaned) {
9a799d71
AK		 226 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
227 tx_buffer_info = &tx_ring->tx_buffer_info[i];
228 cleaned = (i == eop);
229
230 tx_ring->stats.bytes += tx_buffer_info->length;
e092be60
AV		 231 if (cleaned) {
232 struct sk_buff *skb = tx_buffer_info->skb;
e092be60
AV		 233 unsigned int segs, bytecount;
234 segs = skb_shinfo(skb)->gso_segs ?: 1;
235 /* multiply data chunks by size of headers */
236 bytecount = ((segs - 1) * skb_headlen(skb)) +
237 skb->len;
238 total_tx_packets += segs;
239 total_tx_bytes += bytecount;
e092be60 240 }
9a799d71
AK		 241 ixgbe_unmap_and_free_tx_resource(adapter,
242 tx_buffer_info);
243 tx_desc->wb.status = 0;
244
245 i++;
246 if (i == tx_ring->count)
247 i = 0;
248 }
249
250 tx_ring->stats.packets++;
251
252 eop = tx_ring->tx_buffer_info[i].next_to_watch;
253 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
254
255 /* weight of a sort for tx, avoid endless transmit cleanup */
e092be60 256 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 257 break;
258 }
259
260 tx_ring->next_to_clean = i;
261
e092be60
AV		 262#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
263 if (total_tx_packets && netif_carrier_ok(netdev) &&
264 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
265 /* Make sure that anybody stopping the queue after this
266 * sees the new next_to_clean.
267 */
268 smp_mb();
30eba97a
AV		 269 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
270 !test_bit(__IXGBE_DOWN, &adapter->state)) {
271 netif_wake_subqueue(netdev, tx_ring->queue_index);
272 adapter->restart_queue++;
273 }
e092be60 274 }
9a799d71
AK		 275
276 if (adapter->detect_tx_hung)
277 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
30eba97a 278 netif_stop_subqueue(netdev, tx_ring->queue_index);
9a799d71 279
e092be60 280 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
282
f494e8fa
AV		 283 tx_ring->total_bytes += total_tx_bytes;
284 tx_ring->total_packets += total_tx_packets;
d2f4fbe2
AV		 285 adapter->net_stats.tx_bytes += total_tx_bytes;
286 adapter->net_stats.tx_packets += total_tx_packets;
e092be60 287 cleaned = total_tx_packets ? true : false;
9a799d71
AK		 288 return cleaned;
289}
290
bd0362dd
JC		 291#ifdef CONFIG_DCA
292static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
293 struct ixgbe_ring *rxr)
294{
295 u32 rxctrl;
296 int cpu = get_cpu();
297 int q = rxr - adapter->rx_ring;
298
299 if (rxr->cpu != cpu) {
300 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
301 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
302 rxctrl |= dca_get_tag(cpu);
303 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
304 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
305 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
306 rxr->cpu = cpu;
307 }
308 put_cpu();
309}
310
311static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
312 struct ixgbe_ring *txr)
313{
314 u32 txctrl;
315 int cpu = get_cpu();
316 int q = txr - adapter->tx_ring;
317
318 if (txr->cpu != cpu) {
319 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
320 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
321 txctrl |= dca_get_tag(cpu);
322 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
324 txr->cpu = cpu;
325 }
326 put_cpu();
327}
328
329static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
330{
331 int i;
332
333 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
334 return;
335
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 adapter->tx_ring[i].cpu = -1;
338 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
339 }
340 for (i = 0; i < adapter->num_rx_queues; i++) {
341 adapter->rx_ring[i].cpu = -1;
342 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
343 }
344}
345
346static int __ixgbe_notify_dca(struct device *dev, void *data)
347{
348 struct net_device *netdev = dev_get_drvdata(dev);
349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
350 unsigned long event = *(unsigned long *)data;
351
352 switch (event) {
353 case DCA_PROVIDER_ADD:
354 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
355 /* Always use CB2 mode, difference is masked
356 * in the CB driver. */
357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 358 if (dca_add_requester(dev) == 0) {
bd0362dd
JC		 359 ixgbe_setup_dca(adapter);
360 break;
361 }
362 /* Fall Through since DCA is disabled. */
363 case DCA_PROVIDER_REMOVE:
364 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
365 dca_remove_requester(dev);
366 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
368 }
369 break;
370 }
371
652f093f 372 return 0;
bd0362dd
JC		 373}
374
375#endif /* CONFIG_DCA */
9a799d71
AK		 376/**
377 * ixgbe_receive_skb - Send a completed packet up the stack
378 * @adapter: board private structure
379 * @skb: packet to send up
177db6ff
MC		 380 * @status: hardware indication of status of receive
381 * @rx_ring: rx descriptor ring (for a specific queue) to setup
382 * @rx_desc: rx descriptor
9a799d71
AK		 383 **/
384static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
177db6ff
MC		 385 struct sk_buff *skb, u8 status,
386 struct ixgbe_ring *ring,
387 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 388{
177db6ff
MC		 389 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
390 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 391
177db6ff
MC		 392 if (adapter->netdev->features & NETIF_F_LRO &&
393 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 394 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 395 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
396 adapter->vlgrp, tag,
397 rx_desc);
9a799d71 398 else
177db6ff
MC		 399 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
400 ring->lro_used = true;
401 } else {
402 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
403 if (adapter->vlgrp && is_vlan)
404 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
405 else
406 netif_receive_skb(skb);
407 } else {
408 if (adapter->vlgrp && is_vlan)
409 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
410 else
411 netif_rx(skb);
412 }
9a799d71
AK		 413 }
414}
415
e59bd25d
AV		 416/**
417 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
418 * @adapter: address of board private structure
419 * @status_err: hardware indication of status of receive
420 * @skb: skb currently being received and modified
421 **/
9a799d71 422static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 423 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 424{
425 skb->ip_summed = CHECKSUM_NONE;
426
712744be
JB		 427 /* Rx csum disabled */
428 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 429 return;
e59bd25d
AV		 430
431 /* if IP and error */
432 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
433 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 434 adapter->hw_csum_rx_error++;
435 return;
436 }
e59bd25d
AV		 437
438 if (!(status_err & IXGBE_RXD_STAT_L4CS))
439 return;
440
441 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
442 adapter->hw_csum_rx_error++;
443 return;
444 }
445
9a799d71 446 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 447 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 448 adapter->hw_csum_rx_good++;
449}
450
451/**
452 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
453 * @adapter: address of board private structure
454 **/
455static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
456 struct ixgbe_ring *rx_ring,
457 int cleaned_count)
458{
459 struct net_device *netdev = adapter->netdev;
460 struct pci_dev *pdev = adapter->pdev;
461 union ixgbe_adv_rx_desc *rx_desc;
462 struct ixgbe_rx_buffer *rx_buffer_info;
463 struct sk_buff *skb;
464 unsigned int i;
465 unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
466
467 i = rx_ring->next_to_use;
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469
470 while (cleaned_count--) {
471 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
472
473 if (!rx_buffer_info->page &&
474 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
475 rx_buffer_info->page = alloc_page(GFP_ATOMIC);
476 if (!rx_buffer_info->page) {
477 adapter->alloc_rx_page_failed++;
478 goto no_buffers;
479 }
480 rx_buffer_info->page_dma =
481 pci_map_page(pdev, rx_buffer_info->page,
482 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
483 }
484
485 if (!rx_buffer_info->skb) {
486 skb = netdev_alloc_skb(netdev, bufsz);
487
488 if (!skb) {
489 adapter->alloc_rx_buff_failed++;
490 goto no_buffers;
491 }
492
493 /*
494 * Make buffer alignment 2 beyond a 16 byte boundary
495 * this will result in a 16 byte aligned IP header after
496 * the 14 byte MAC header is removed
497 */
498 skb_reserve(skb, NET_IP_ALIGN);
499
500 rx_buffer_info->skb = skb;
501 rx_buffer_info->dma = pci_map_single(pdev, skb->data,
502 bufsz,
503 PCI_DMA_FROMDEVICE);
504 }
505 /* Refresh the desc even if buffer_addrs didn't change because
506 * each write-back erases this info. */
507 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
508 rx_desc->read.pkt_addr =
509 cpu_to_le64(rx_buffer_info->page_dma);
510 rx_desc->read.hdr_addr =
511 cpu_to_le64(rx_buffer_info->dma);
512 } else {
513 rx_desc->read.pkt_addr =
514 cpu_to_le64(rx_buffer_info->dma);
515 }
516
517 i++;
518 if (i == rx_ring->count)
519 i = 0;
520 rx_buffer_info = &rx_ring->rx_buffer_info[i];
521 }
522no_buffers:
523 if (rx_ring->next_to_use != i) {
524 rx_ring->next_to_use = i;
525 if (i-- == 0)
526 i = (rx_ring->count - 1);
527
528 /*
529 * Force memory writes to complete before letting h/w
530 * know there are new descriptors to fetch. (Only
531 * applicable for weak-ordered memory model archs,
532 * such as IA-64).
533 */
534 wmb();
535 writel(i, adapter->hw.hw_addr + rx_ring->tail);
536 }
537}
538
539static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
540 struct ixgbe_ring *rx_ring,
541 int *work_done, int work_to_do)
542{
543 struct net_device *netdev = adapter->netdev;
544 struct pci_dev *pdev = adapter->pdev;
545 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
546 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
547 struct sk_buff *skb;
548 unsigned int i;
549 u32 upper_len, len, staterr;
177db6ff
MC		 550 u16 hdr_info;
551 bool cleaned = false;
9a799d71 552 int cleaned_count = 0;
d2f4fbe2 553 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 554
555 i = rx_ring->next_to_clean;
556 upper_len = 0;
557 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
558 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
559 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 560
561 while (staterr & IXGBE_RXD_STAT_DD) {
562 if (*work_done >= work_to_do)
563 break;
564 (*work_done)++;
565
566 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
567 hdr_info =
568 le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
569 len =
570 ((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
571 IXGBE_RXDADV_HDRBUFLEN_SHIFT);
572 if (hdr_info & IXGBE_RXDADV_SPH)
573 adapter->rx_hdr_split++;
574 if (len > IXGBE_RX_HDR_SIZE)
575 len = IXGBE_RX_HDR_SIZE;
576 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
577 } else
578 len = le16_to_cpu(rx_desc->wb.upper.length);
579
580 cleaned = true;
581 skb = rx_buffer_info->skb;
582 prefetch(skb->data - NET_IP_ALIGN);
583 rx_buffer_info->skb = NULL;
584
585 if (len && !skb_shinfo(skb)->nr_frags) {
586 pci_unmap_single(pdev, rx_buffer_info->dma,
587 adapter->rx_buf_len + NET_IP_ALIGN,
588 PCI_DMA_FROMDEVICE);
589 skb_put(skb, len);
590 }
591
592 if (upper_len) {
593 pci_unmap_page(pdev, rx_buffer_info->page_dma,
594 PAGE_SIZE, PCI_DMA_FROMDEVICE);
595 rx_buffer_info->page_dma = 0;
596 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
597 rx_buffer_info->page, 0, upper_len);
598 rx_buffer_info->page = NULL;
599
600 skb->len += upper_len;
601 skb->data_len += upper_len;
602 skb->truesize += upper_len;
603 }
604
605 i++;
606 if (i == rx_ring->count)
607 i = 0;
608 next_buffer = &rx_ring->rx_buffer_info[i];
609
610 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
611 prefetch(next_rxd);
612
613 cleaned_count++;
614 if (staterr & IXGBE_RXD_STAT_EOP) {
615 rx_ring->stats.packets++;
616 rx_ring->stats.bytes += skb->len;
617 } else {
618 rx_buffer_info->skb = next_buffer->skb;
619 rx_buffer_info->dma = next_buffer->dma;
620 next_buffer->skb = skb;
621 adapter->non_eop_descs++;
622 goto next_desc;
623 }
624
625 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
626 dev_kfree_skb_irq(skb);
627 goto next_desc;
628 }
629
630 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 631
632 /* probably a little skewed due to removing CRC */
633 total_rx_bytes += skb->len;
634 total_rx_packets++;
635
9a799d71 636 skb->protocol = eth_type_trans(skb, netdev);
177db6ff 637 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 638 netdev->last_rx = jiffies;
639
640next_desc:
641 rx_desc->wb.upper.status_error = 0;
642
643 /* return some buffers to hardware, one at a time is too slow */
644 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
645 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
646 cleaned_count = 0;
647 }
648
649 /* use prefetched values */
650 rx_desc = next_rxd;
651 rx_buffer_info = next_buffer;
652
653 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 654 }
655
656 if (rx_ring->lro_used) {
657 lro_flush_all(&rx_ring->lro_mgr);
658 rx_ring->lro_used = false;
9a799d71
AK		 659 }
660
661 rx_ring->next_to_clean = i;
662 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
663
664 if (cleaned_count)
665 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
666
d2f4fbe2
AV		 667 adapter->net_stats.rx_bytes += total_rx_bytes;
668 adapter->net_stats.rx_packets += total_rx_packets;
669
f494e8fa
AV		 670 rx_ring->total_packets += total_rx_packets;
671 rx_ring->total_bytes += total_rx_bytes;
672 adapter->net_stats.rx_bytes += total_rx_bytes;
673 adapter->net_stats.rx_packets += total_rx_packets;
674
9a799d71
AK		 675 return cleaned;
676}
677
021230d4 678static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 679/**
680 * ixgbe_configure_msix - Configure MSI-X hardware
681 * @adapter: board private structure
682 *
683 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
684 * interrupts.
685 **/
686static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
687{
021230d4
AV		 688 struct ixgbe_q_vector *q_vector;
689 int i, j, q_vectors, v_idx, r_idx;
690 u32 mask;
9a799d71 691
021230d4 692 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 693
021230d4
AV		 694 /* Populate the IVAR table and set the ITR values to the
695 * corresponding register.
696 */
697 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
698 q_vector = &adapter->q_vector[v_idx];
699 /* XXX for_each_bit(...) */
700 r_idx = find_first_bit(q_vector->rxr_idx,
701 adapter->num_rx_queues);
702
703 for (i = 0; i < q_vector->rxr_count; i++) {
704 j = adapter->rx_ring[r_idx].reg_idx;
705 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
706 r_idx = find_next_bit(q_vector->rxr_idx,
707 adapter->num_rx_queues,
708 r_idx + 1);
709 }
710 r_idx = find_first_bit(q_vector->txr_idx,
711 adapter->num_tx_queues);
712
713 for (i = 0; i < q_vector->txr_count; i++) {
714 j = adapter->tx_ring[r_idx].reg_idx;
715 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
716 r_idx = find_next_bit(q_vector->txr_idx,
717 adapter->num_tx_queues,
718 r_idx + 1);
719 }
720
721 /* if this is a tx only vector use half the irq (tx) rate */
722 if (q_vector->txr_count && !q_vector->rxr_count)
723 q_vector->eitr = adapter->tx_eitr;
724 else
725 /* rx only or mixed */
726 q_vector->eitr = adapter->rx_eitr;
727
728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
729 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 730 }
731
021230d4
AV		 732 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
734
735 /* set up to autoclear timer, lsc, and the vectors */
736 mask = IXGBE_EIMS_ENABLE_MASK;
737 mask &= ~IXGBE_EIMS_OTHER;
738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 739}
740
f494e8fa
AV		 741enum latency_range {
742 lowest_latency = 0,
743 low_latency = 1,
744 bulk_latency = 2,
745 latency_invalid = 255
746};
747
748/**
749 * ixgbe_update_itr - update the dynamic ITR value based on statistics
750 * @adapter: pointer to adapter
751 * @eitr: eitr setting (ints per sec) to give last timeslice
752 * @itr_setting: current throttle rate in ints/second
753 * @packets: the number of packets during this measurement interval
754 * @bytes: the number of bytes during this measurement interval
755 *
756 * Stores a new ITR value based on packets and byte
757 * counts during the last interrupt. The advantage of per interrupt
758 * computation is faster updates and more accurate ITR for the current
759 * traffic pattern. Constants in this function were computed
760 * based on theoretical maximum wire speed and thresholds were set based
761 * on testing data as well as attempting to minimize response time
762 * while increasing bulk throughput.
763 * this functionality is controlled by the InterruptThrottleRate module
764 * parameter (see ixgbe_param.c)
765 **/
766static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
767 u32 eitr, u8 itr_setting,
768 int packets, int bytes)
769{
770 unsigned int retval = itr_setting;
771 u32 timepassed_us;
772 u64 bytes_perint;
773
774 if (packets == 0)
775 goto update_itr_done;
776
777
778 /* simple throttlerate management
779 * 0-20MB/s lowest (100000 ints/s)
780 * 20-100MB/s low (20000 ints/s)
781 * 100-1249MB/s bulk (8000 ints/s)
782 */
783 /* what was last interrupt timeslice? */
784 timepassed_us = 1000000/eitr;
785 bytes_perint = bytes / timepassed_us; /* bytes/usec */
786
787 switch (itr_setting) {
788 case lowest_latency:
789 if (bytes_perint > adapter->eitr_low)
790 retval = low_latency;
791 break;
792 case low_latency:
793 if (bytes_perint > adapter->eitr_high)
794 retval = bulk_latency;
795 else if (bytes_perint <= adapter->eitr_low)
796 retval = lowest_latency;
797 break;
798 case bulk_latency:
799 if (bytes_perint <= adapter->eitr_high)
800 retval = low_latency;
801 break;
802 }
803
804update_itr_done:
805 return retval;
806}
807
808static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
809{
810 struct ixgbe_adapter *adapter = q_vector->adapter;
811 struct ixgbe_hw *hw = &adapter->hw;
812 u32 new_itr;
813 u8 current_itr, ret_itr;
814 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
815 sizeof(struct ixgbe_q_vector);
816 struct ixgbe_ring *rx_ring, *tx_ring;
817
818 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
819 for (i = 0; i < q_vector->txr_count; i++) {
820 tx_ring = &(adapter->tx_ring[r_idx]);
821 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
822 q_vector->tx_eitr,
823 tx_ring->total_packets,
824 tx_ring->total_bytes);
825 /* if the result for this queue would decrease interrupt
826 * rate for this vector then use that result */
827 q_vector->tx_eitr = ((q_vector->tx_eitr > ret_itr) ?
828 q_vector->tx_eitr - 1 : ret_itr);
829 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
830 r_idx + 1);
831 }
832
833 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
834 for (i = 0; i < q_vector->rxr_count; i++) {
835 rx_ring = &(adapter->rx_ring[r_idx]);
836 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
837 q_vector->rx_eitr,
838 rx_ring->total_packets,
839 rx_ring->total_bytes);
840 /* if the result for this queue would decrease interrupt
841 * rate for this vector then use that result */
842 q_vector->rx_eitr = ((q_vector->rx_eitr > ret_itr) ?
843 q_vector->rx_eitr - 1 : ret_itr);
844 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
845 r_idx + 1);
846 }
847
848 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
849
850 switch (current_itr) {
851 /* counts and packets in update_itr are dependent on these numbers */
852 case lowest_latency:
853 new_itr = 100000;
854 break;
855 case low_latency:
856 new_itr = 20000; /* aka hwitr = ~200 */
857 break;
858 case bulk_latency:
859 default:
860 new_itr = 8000;
861 break;
862 }
863
864 if (new_itr != q_vector->eitr) {
865 u32 itr_reg;
866 /* do an exponential smoothing */
867 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
868 q_vector->eitr = new_itr;
869 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
870 /* must write high and low 16 bits to reset counter */
871 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
872 itr_reg);
873 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
874 }
875
876 return;
877}
878
9a799d71
AK		 879static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
880{
881 struct net_device *netdev = data;
882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
883 struct ixgbe_hw *hw = &adapter->hw;
884 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
885
886 if (eicr & IXGBE_EICR_LSC) {
887 adapter->lsc_int++;
888 if (!test_bit(__IXGBE_DOWN, &adapter->state))
889 mod_timer(&adapter->watchdog_timer, jiffies);
890 }
d4f80882
AV		 891
892 if (!test_bit(__IXGBE_DOWN, &adapter->state))
893 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 894
895 return IRQ_HANDLED;
896}
897
898static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
899{
021230d4
AV		 900 struct ixgbe_q_vector *q_vector = data;
901 struct ixgbe_adapter *adapter = q_vector->adapter;
902 struct ixgbe_ring *txr;
903 int i, r_idx;
904
905 if (!q_vector->txr_count)
906 return IRQ_HANDLED;
907
908 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
909 for (i = 0; i < q_vector->txr_count; i++) {
910 txr = &(adapter->tx_ring[r_idx]);
bd0362dd
JC		 911#ifdef CONFIG_DCA
912 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
913 ixgbe_update_tx_dca(adapter, txr);
914#endif
f494e8fa
AV		 915 txr->total_bytes = 0;
916 txr->total_packets = 0;
021230d4
AV		 917 ixgbe_clean_tx_irq(adapter, txr);
918 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
919 r_idx + 1);
920 }
9a799d71 921
9a799d71
AK		 922 return IRQ_HANDLED;
923}
924
021230d4
AV		 925/**
926 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
927 * @irq: unused
928 * @data: pointer to our q_vector struct for this interrupt vector
929 **/
9a799d71
AK		 930static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
931{
021230d4
AV		 932 struct ixgbe_q_vector *q_vector = data;
933 struct ixgbe_adapter *adapter = q_vector->adapter;
934 struct ixgbe_ring *rxr;
935 int r_idx;
936
937 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
938 if (!q_vector->rxr_count)
939 return IRQ_HANDLED;
940
941 rxr = &(adapter->rx_ring[r_idx]);
942 /* disable interrupts on this vector only */
943 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rxr->v_idx);
f494e8fa
AV		 944 rxr->total_bytes = 0;
945 rxr->total_packets = 0;
021230d4
AV		 946 netif_rx_schedule(adapter->netdev, &q_vector->napi);
947
948 return IRQ_HANDLED;
949}
950
951static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
952{
953 ixgbe_msix_clean_rx(irq, data);
954 ixgbe_msix_clean_tx(irq, data);
9a799d71 955
9a799d71
AK		 956 return IRQ_HANDLED;
957}
958
021230d4
AV		 959/**
960 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
961 * @napi: napi struct with our devices info in it
962 * @budget: amount of work driver is allowed to do this pass, in packets
963 *
964 **/
9a799d71
AK		 965static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
966{
021230d4
AV		 967 struct ixgbe_q_vector *q_vector =
968 container_of(napi, struct ixgbe_q_vector, napi);
969 struct ixgbe_adapter *adapter = q_vector->adapter;
970 struct ixgbe_ring *rxr;
9a799d71 971 int work_done = 0;
021230d4 972 long r_idx;
9a799d71 973
021230d4
AV		 974 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
975 rxr = &(adapter->rx_ring[r_idx]);
bd0362dd
JC		 976#ifdef CONFIG_DCA
977 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
978 ixgbe_update_rx_dca(adapter, rxr);
979#endif
9a799d71
AK		 980
981 ixgbe_clean_rx_irq(adapter, rxr, &work_done, budget);
982
021230d4
AV		 983 /* If all Rx work done, exit the polling mode */
984 if (work_done < budget) {
985 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 986 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
987 ixgbe_set_itr_msix(q_vector);
9a799d71 988 if (!test_bit(__IXGBE_DOWN, &adapter->state))
021230d4 989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rxr->v_idx);
9a799d71
AK		 990 }
991
992 return work_done;
993}
994
021230d4
AV		 995static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
996 int r_idx)
997{
998 a->q_vector[v_idx].adapter = a;
999 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1000 a->q_vector[v_idx].rxr_count++;
1001 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1002}
1003
1004static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1005 int r_idx)
1006{
1007 a->q_vector[v_idx].adapter = a;
1008 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1009 a->q_vector[v_idx].txr_count++;
1010 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1011}
1012
9a799d71 1013/**
021230d4
AV		 1014 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1015 * @adapter: board private structure to initialize
1016 * @vectors: allotted vector count for descriptor rings
9a799d71 1017 *
021230d4
AV		 1018 * This function maps descriptor rings to the queue-specific vectors
1019 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1020 * one vector per ring/queue, but on a constrained vector budget, we
1021 * group the rings as "efficiently" as possible. You would add new
1022 * mapping configurations in here.
9a799d71 1023 **/
021230d4
AV		 1024static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1025 int vectors)
1026{
1027 int v_start = 0;
1028 int rxr_idx = 0, txr_idx = 0;
1029 int rxr_remaining = adapter->num_rx_queues;
1030 int txr_remaining = adapter->num_tx_queues;
1031 int i, j;
1032 int rqpv, tqpv;
1033 int err = 0;
1034
1035 /* No mapping required if MSI-X is disabled. */
1036 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1037 goto out;
9a799d71 1038
021230d4
AV		 1039 /*
1040 * The ideal configuration...
1041 * We have enough vectors to map one per queue.
1042 */
1043 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1044 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1045 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1046
021230d4
AV		 1047 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1048 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1049
9a799d71 1050 goto out;
021230d4 1051 }
9a799d71 1052
021230d4
AV		 1053 /*
1054 * If we don't have enough vectors for a 1-to-1
1055 * mapping, we'll have to group them so there are
1056 * multiple queues per vector.
1057 */
1058 /* Re-adjusting *qpv takes care of the remainder. */
1059 for (i = v_start; i < vectors; i++) {
1060 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1061 for (j = 0; j < rqpv; j++) {
1062 map_vector_to_rxq(adapter, i, rxr_idx);
1063 rxr_idx++;
1064 rxr_remaining--;
1065 }
1066 }
1067 for (i = v_start; i < vectors; i++) {
1068 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1069 for (j = 0; j < tqpv; j++) {
1070 map_vector_to_txq(adapter, i, txr_idx);
1071 txr_idx++;
1072 txr_remaining--;
9a799d71 1073 }
9a799d71
AK		 1074 }
1075
021230d4
AV		 1076out:
1077 return err;
1078}
1079
1080/**
1081 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1082 * @adapter: board private structure
1083 *
1084 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1085 * interrupts from the kernel.
1086 **/
1087static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1088{
1089 struct net_device *netdev = adapter->netdev;
1090 irqreturn_t (*handler)(int, void *);
1091 int i, vector, q_vectors, err;
1092
1093 /* Decrement for Other and TCP Timer vectors */
1094 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1095
1096 /* Map the Tx/Rx rings to the vectors we were allotted. */
1097 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1098 if (err)
1099 goto out;
1100
1101#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1102 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1103 &ixgbe_msix_clean_many)
1104 for (vector = 0; vector < q_vectors; vector++) {
1105 handler = SET_HANDLER(&adapter->q_vector[vector]);
1106 sprintf(adapter->name[vector], "%s:v%d-%s",
1107 netdev->name, vector,
1108 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1109 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1110 err = request_irq(adapter->msix_entries[vector].vector,
1111 handler, 0, adapter->name[vector],
1112 &(adapter->q_vector[vector]));
9a799d71
AK		 1113 if (err) {
1114 DPRINTK(PROBE, ERR,
1115 "request_irq failed for MSIX interrupt "
1116 "Error: %d\n", err);
021230d4 1117 goto free_queue_irqs;
9a799d71 1118 }
9a799d71
AK		 1119 }
1120
021230d4
AV		 1121 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1122 err = request_irq(adapter->msix_entries[vector].vector,
1123 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1124 if (err) {
1125 DPRINTK(PROBE, ERR,
1126 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1127 goto free_queue_irqs;
9a799d71
AK		 1128 }
1129
9a799d71
AK		 1130 return 0;
1131
021230d4
AV		 1132free_queue_irqs:
1133 for (i = vector - 1; i >= 0; i--)
1134 free_irq(adapter->msix_entries[--vector].vector,
1135 &(adapter->q_vector[i]));
1136 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1137 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1138 kfree(adapter->msix_entries);
1139 adapter->msix_entries = NULL;
021230d4 1140out:
9a799d71
AK		 1141 return err;
1142}
1143
f494e8fa
AV		 1144static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1145{
1146 struct ixgbe_hw *hw = &adapter->hw;
1147 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1148 u8 current_itr;
1149 u32 new_itr = q_vector->eitr;
1150 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1151 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1152
1153 q_vector->tx_eitr = ixgbe_update_itr(adapter, new_itr,
1154 q_vector->tx_eitr,
1155 tx_ring->total_packets,
1156 tx_ring->total_bytes);
1157 q_vector->rx_eitr = ixgbe_update_itr(adapter, new_itr,
1158 q_vector->rx_eitr,
1159 rx_ring->total_packets,
1160 rx_ring->total_bytes);
1161
1162 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
1163
1164 switch (current_itr) {
1165 /* counts and packets in update_itr are dependent on these numbers */
1166 case lowest_latency:
1167 new_itr = 100000;
1168 break;
1169 case low_latency:
1170 new_itr = 20000; /* aka hwitr = ~200 */
1171 break;
1172 case bulk_latency:
1173 new_itr = 8000;
1174 break;
1175 default:
1176 break;
1177 }
1178
1179 if (new_itr != q_vector->eitr) {
1180 u32 itr_reg;
1181 /* do an exponential smoothing */
1182 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1183 q_vector->eitr = new_itr;
1184 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1185 /* must write high and low 16 bits to reset counter */
1186 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1187 }
1188
1189 return;
1190}
1191
021230d4
AV		 1192static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1193
9a799d71 1194/**
021230d4 1195 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1196 * @irq: interrupt number
1197 * @data: pointer to a network interface device structure
1198 * @pt_regs: CPU registers structure
1199 **/
1200static irqreturn_t ixgbe_intr(int irq, void *data)
1201{
1202 struct net_device *netdev = data;
1203 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1204 struct ixgbe_hw *hw = &adapter->hw;
1205 u32 eicr;
1206
9a799d71 1207
021230d4
AV		 1208 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1209 * therefore no explict interrupt disable is necessary */
1210 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 1211 if (!eicr)
1212 return IRQ_NONE; /* Not our interrupt */
1213
1214 if (eicr & IXGBE_EICR_LSC) {
1215 adapter->lsc_int++;
1216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1217 mod_timer(&adapter->watchdog_timer, jiffies);
1218 }
021230d4
AV		 1219
1220
1221 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1222 adapter->tx_ring[0].total_packets = 0;
1223 adapter->tx_ring[0].total_bytes = 0;
1224 adapter->rx_ring[0].total_packets = 0;
1225 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1226 /* would disable interrupts here but EIAM disabled it */
1227 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1228 }
1229
1230 return IRQ_HANDLED;
1231}
1232
021230d4
AV		 1233static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1234{
1235 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1236
1237 for (i = 0; i < q_vectors; i++) {
1238 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1239 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1240 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1241 q_vector->rxr_count = 0;
1242 q_vector->txr_count = 0;
1243 }
1244}
1245
9a799d71
AK		 1246/**
1247 * ixgbe_request_irq - initialize interrupts
1248 * @adapter: board private structure
1249 *
1250 * Attempts to configure interrupts using the best available
1251 * capabilities of the hardware and kernel.
1252 **/
021230d4 1253static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1254{
1255 struct net_device *netdev = adapter->netdev;
021230d4 1256 int err;
9a799d71 1257
021230d4
AV		 1258 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1259 err = ixgbe_request_msix_irqs(adapter);
1260 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1261 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1262 netdev->name, netdev);
1263 } else {
1264 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1265 netdev->name, netdev);
9a799d71
AK		 1266 }
1267
9a799d71
AK		 1268 if (err)
1269 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1270
9a799d71
AK		 1271 return err;
1272}
1273
1274static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1275{
1276 struct net_device *netdev = adapter->netdev;
1277
1278 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1279 int i, q_vectors;
9a799d71 1280
021230d4
AV		 1281 q_vectors = adapter->num_msix_vectors;
1282
1283 i = q_vectors - 1;
9a799d71 1284 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1285
021230d4
AV		 1286 i--;
1287 for (; i >= 0; i--) {
1288 free_irq(adapter->msix_entries[i].vector,
1289 &(adapter->q_vector[i]));
1290 }
1291
1292 ixgbe_reset_q_vectors(adapter);
1293 } else {
1294 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1295 }
1296}
1297
1298/**
1299 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1300 * @adapter: board private structure
1301 **/
1302static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1303{
9a799d71
AK		 1304 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1305 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1306 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1307 int i;
1308 for (i = 0; i < adapter->num_msix_vectors; i++)
1309 synchronize_irq(adapter->msix_entries[i].vector);
1310 } else {
1311 synchronize_irq(adapter->pdev->irq);
1312 }
9a799d71
AK		 1313}
1314
1315/**
1316 * ixgbe_irq_enable - Enable default interrupt generation settings
1317 * @adapter: board private structure
1318 **/
1319static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1320{
021230d4
AV		 1321 u32 mask;
1322 mask = IXGBE_EIMS_ENABLE_MASK;
1323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1324 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1325}
1326
1327/**
1328 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1329 *
1330 **/
1331static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1332{
9a799d71
AK		 1333 struct ixgbe_hw *hw = &adapter->hw;
1334
021230d4
AV		 1335 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1336 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
9a799d71
AK		 1337
1338 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1339 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1340
1341 map_vector_to_rxq(adapter, 0, 0);
1342 map_vector_to_txq(adapter, 0, 0);
1343
1344 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1345}
1346
1347/**
1348 * ixgbe_configure_tx - Configure 8254x Transmit Unit after Reset
1349 * @adapter: board private structure
1350 *
1351 * Configure the Tx unit of the MAC after a reset.
1352 **/
1353static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1354{
1355 u64 tdba;
1356 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1357 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1358
1359 /* Setup the HW Tx Head and Tail descriptor pointers */
1360 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4 1361 j = adapter->tx_ring[i].reg_idx;
9a799d71
AK		 1362 tdba = adapter->tx_ring[i].dma;
1363 tdlen = adapter->tx_ring[i].count *
021230d4
AV		 1364 sizeof(union ixgbe_adv_tx_desc);
1365 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1366 (tdba & DMA_32BIT_MASK));
1367 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1368 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1369 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1370 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1371 adapter->tx_ring[i].head = IXGBE_TDH(j);
1372 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1373 /* Disable Tx Head Writeback RO bit, since this hoses
1374 * bookkeeping if things aren't delivered in order.
1375 */
1376 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1377 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1378 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
9a799d71 1379 }
9a799d71
AK		 1380}
1381
1382#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1383 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1384
1385#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
177db6ff
MC		 1386/**
1387 * ixgbe_get_skb_hdr - helper function for LRO header processing
1388 * @skb: pointer to sk_buff to be added to LRO packet
1389 * @iphdr: pointer to tcp header structure
1390 * @tcph: pointer to tcp header structure
1391 * @hdr_flags: pointer to header flags
1392 * @priv: private data
1393 **/
1394static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1395 u64 *hdr_flags, void *priv)
1396{
1397 union ixgbe_adv_rx_desc *rx_desc = priv;
1398
1399 /* Verify that this is a valid IPv4 TCP packet */
1400 if (!(rx_desc->wb.lower.lo_dword.pkt_info &
1401 (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)))
1402 return -1;
1403
1404 /* Set network headers */
1405 skb_reset_network_header(skb);
1406 skb_set_transport_header(skb, ip_hdrlen(skb));
1407 *iphdr = ip_hdr(skb);
1408 *tcph = tcp_hdr(skb);
1409 *hdr_flags = LRO_IPV4 | LRO_TCP;
1410 return 0;
1411}
1412
9a799d71
AK		 1413/**
1414 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset
1415 * @adapter: board private structure
1416 *
1417 * Configure the Rx unit of the MAC after a reset.
1418 **/
1419static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1420{
1421 u64 rdba;
1422 struct ixgbe_hw *hw = &adapter->hw;
1423 struct net_device *netdev = adapter->netdev;
1424 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1425 int i, j;
9a799d71
AK		 1426 u32 rdlen, rxctrl, rxcsum;
1427 u32 random[10];
9a799d71 1428 u32 fctrl, hlreg0;
9a799d71 1429 u32 pages;
021230d4 1430 u32 reta = 0, mrqc, srrctl;
9a799d71
AK		 1431
1432 /* Decide whether to use packet split mode or not */
1433 if (netdev->mtu > ETH_DATA_LEN)
1434 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1435 else
1436 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1437
1438 /* Set the RX buffer length according to the mode */
1439 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1440 adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
1441 } else {
1442 if (netdev->mtu <= ETH_DATA_LEN)
1443 adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1444 else
1445 adapter->rx_buf_len = ALIGN(max_frame, 1024);
1446 }
1447
1448 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1449 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1450 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1452
1453 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1454 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1455 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1456 else
1457 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1458 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1459
1460 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1461
1462 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
1463 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1464 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1465
1466 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1467 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1468 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1469 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1470 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1471 IXGBE_SRRCTL_BSIZEHDR_MASK);
1472 } else {
1473 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1474
1475 if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1476 srrctl |=
1477 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1478 else
1479 srrctl |=
1480 adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1481 }
1482 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
1483
1484 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1485 /* disable receives while setting up the descriptors */
1486 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1487 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1488
1489 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1490 * the Base and Length of the Rx Descriptor Ring */
1491 for (i = 0; i < adapter->num_rx_queues; i++) {
1492 rdba = adapter->rx_ring[i].dma;
1493 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
1494 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
1495 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
1496 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
1497 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
1498 adapter->rx_ring[i].head = IXGBE_RDH(i);
1499 adapter->rx_ring[i].tail = IXGBE_RDT(i);
1500 }
1501
177db6ff
MC		 1502 /* Intitial LRO Settings */
1503 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1504 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1505 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1506 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1507 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1508 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1509 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1510 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1511 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1512
021230d4 1513 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1514 /* Fill out redirection table */
021230d4
AV		 1515 for (i = 0, j = 0; i < 128; i++, j++) {
1516 if (j == adapter->ring_feature[RING_F_RSS].indices)
1517 j = 0;
1518 /* reta = 4-byte sliding window of
1519 * 0x00..(indices-1)(indices-1)00..etc. */
1520 reta = (reta << 8) | (j * 0x11);
1521 if ((i & 3) == 3)
1522 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1523 }
1524
1525 /* Fill out hash function seeds */
021230d4
AV		 1526 /* XXX use a random constant here to glue certain flows */
1527 get_random_bytes(&random[0], 40);
9a799d71 1528 for (i = 0; i < 10; i++)
021230d4 1529 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random[i]);
9a799d71
AK		 1530
1531 mrqc = IXGBE_MRQC_RSSEN
1532 /* Perform hash on these packet types */
1533 | IXGBE_MRQC_RSS_FIELD_IPV4
1534 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1535 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1536 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1537 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1538 | IXGBE_MRQC_RSS_FIELD_IPV6
1539 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1540 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1541 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1542 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1543 }
9a799d71 1544
021230d4
AV		 1545 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1546
1547 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1548 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1549 /* Disable indicating checksum in descriptor, enables
1550 * RSS hash */
9a799d71 1551 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1552 }
021230d4
AV		 1553 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1554 /* Enable IPv4 payload checksum for UDP fragments
1555 * if PCSD is not set */
1556 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1557 }
1558
1559 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1560}
1561
1562static void ixgbe_vlan_rx_register(struct net_device *netdev,
1563 struct vlan_group *grp)
1564{
1565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1566 u32 ctrl;
1567
d4f80882
AV		 1568 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1569 ixgbe_irq_disable(adapter);
9a799d71
AK		 1570 adapter->vlgrp = grp;
1571
1572 if (grp) {
1573 /* enable VLAN tag insert/strip */
1574 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1575 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1576 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1578 }
1579
d4f80882
AV		 1580 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1581 ixgbe_irq_enable(adapter);
9a799d71
AK		 1582}
1583
1584static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1585{
1586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1587
1588 /* add VID to filter table */
1589 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1590}
1591
1592static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1593{
1594 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1595
d4f80882
AV		 1596 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1597 ixgbe_irq_disable(adapter);
1598
9a799d71 1599 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1600
1601 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1602 ixgbe_irq_enable(adapter);
9a799d71
AK		 1603
1604 /* remove VID from filter table */
1605 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1606}
1607
1608static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1609{
1610 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1611
1612 if (adapter->vlgrp) {
1613 u16 vid;
1614 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1615 if (!vlan_group_get_device(adapter->vlgrp, vid))
1616 continue;
1617 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1618 }
1619 }
1620}
1621
1622/**
1623 * ixgbe_set_multi - Multicast and Promiscuous mode set
1624 * @netdev: network interface device structure
1625 *
1626 * The set_multi entry point is called whenever the multicast address
1627 * list or the network interface flags are updated. This routine is
1628 * responsible for configuring the hardware for proper multicast,
1629 * promiscuous mode, and all-multi behavior.
1630 **/
1631static void ixgbe_set_multi(struct net_device *netdev)
1632{
1633 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1634 struct ixgbe_hw *hw = &adapter->hw;
1635 struct dev_mc_list *mc_ptr;
1636 u8 *mta_list;
3d01625a 1637 u32 fctrl, vlnctrl;
9a799d71
AK		 1638 int i;
1639
1640 /* Check for Promiscuous and All Multicast modes */
1641
1642 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1643 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1644
1645 if (netdev->flags & IFF_PROMISC) {
1646 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1647 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1648 } else {
746b9f02
PM		 1649 if (netdev->flags & IFF_ALLMULTI) {
1650 fctrl |= IXGBE_FCTRL_MPE;
1651 fctrl &= ~IXGBE_FCTRL_UPE;
1652 } else {
1653 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1654 }
3d01625a 1655 vlnctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 1656 }
1657
1658 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1659 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71
AK		 1660
1661 if (netdev->mc_count) {
1662 mta_list = kcalloc(netdev->mc_count, ETH_ALEN, GFP_ATOMIC);
1663 if (!mta_list)
1664 return;
1665
1666 /* Shared function expects packed array of only addresses. */
1667 mc_ptr = netdev->mc_list;
1668
1669 for (i = 0; i < netdev->mc_count; i++) {
1670 if (!mc_ptr)
1671 break;
1672 memcpy(mta_list + (i * ETH_ALEN), mc_ptr->dmi_addr,
1673 ETH_ALEN);
1674 mc_ptr = mc_ptr->next;
1675 }
1676
1677 ixgbe_update_mc_addr_list(hw, mta_list, i, 0);
1678 kfree(mta_list);
1679 } else {
1680 ixgbe_update_mc_addr_list(hw, NULL, 0, 0);
1681 }
1682
1683}
1684
021230d4
AV		 1685static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1686{
1687 int q_idx;
1688 struct ixgbe_q_vector *q_vector;
1689 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1690
1691 /* legacy and MSI only use one vector */
1692 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1693 q_vectors = 1;
1694
1695 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1696 q_vector = &adapter->q_vector[q_idx];
1697 if (!q_vector->rxr_count)
1698 continue;
1699 napi_enable(&q_vector->napi);
1700 }
1701}
1702
1703static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1704{
1705 int q_idx;
1706 struct ixgbe_q_vector *q_vector;
1707 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1708
1709 /* legacy and MSI only use one vector */
1710 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1711 q_vectors = 1;
1712
1713 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1714 q_vector = &adapter->q_vector[q_idx];
1715 if (!q_vector->rxr_count)
1716 continue;
1717 napi_disable(&q_vector->napi);
1718 }
1719}
1720
9a799d71
AK		 1721static void ixgbe_configure(struct ixgbe_adapter *adapter)
1722{
1723 struct net_device *netdev = adapter->netdev;
1724 int i;
1725
1726 ixgbe_set_multi(netdev);
1727
1728 ixgbe_restore_vlan(adapter);
1729
1730 ixgbe_configure_tx(adapter);
1731 ixgbe_configure_rx(adapter);
1732 for (i = 0; i < adapter->num_rx_queues; i++)
1733 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1734 (adapter->rx_ring[i].count - 1));
1735}
1736
1737static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1738{
1739 struct net_device *netdev = adapter->netdev;
9a799d71 1740 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1741 int i, j = 0;
9a799d71 1742 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1743 u32 txdctl, rxdctl, mhadd;
1744 u32 gpie;
9a799d71 1745
5eba3699
AV		 1746 ixgbe_get_hw_control(adapter);
1747
021230d4
AV		 1748 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1749 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1750 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1751 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1752 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1753 } else {
1754 /* MSI only */
021230d4 1755 gpie = 0;
9a799d71 1756 }
021230d4
AV		 1757 /* XXX: to interrupt immediately for EICS writes, enable this */
1758 /* gpie |= IXGBE_GPIE_EIMEN; */
1759 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1760 }
1761
021230d4
AV		 1762 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1763 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1764 * specifically only auto mask tx and rx interrupts */
1765 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1766 }
9a799d71 1767
021230d4 1768 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1769 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1770 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1771 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1772
1773 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1774 }
1775
1776 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1777 j = adapter->tx_ring[i].reg_idx;
1778 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 1779 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1780 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1781 }
1782
1783 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1784 j = adapter->rx_ring[i].reg_idx;
1785 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1786 /* enable PTHRESH=32 descriptors (half the internal cache)
1787 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1788 * this also removes a pesky rx_no_buffer_count increment */
1789 rxdctl |= 0x0020;
9a799d71 1790 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1792 }
1793 /* enable all receives */
1794 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1795 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1796 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1797
1798 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1799 ixgbe_configure_msix(adapter);
1800 else
1801 ixgbe_configure_msi_and_legacy(adapter);
1802
1803 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1804 ixgbe_napi_enable_all(adapter);
1805
1806 /* clear any pending interrupts, may auto mask */
1807 IXGBE_READ_REG(hw, IXGBE_EICR);
1808
9a799d71
AK		 1809 ixgbe_irq_enable(adapter);
1810
1811 /* bring the link up in the watchdog, this could race with our first
1812 * link up interrupt but shouldn't be a problem */
1813 mod_timer(&adapter->watchdog_timer, jiffies);
1814 return 0;
1815}
1816
d4f80882
AV		 1817void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1818{
1819 WARN_ON(in_interrupt());
1820 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1821 msleep(1);
1822 ixgbe_down(adapter);
1823 ixgbe_up(adapter);
1824 clear_bit(__IXGBE_RESETTING, &adapter->state);
1825}
1826
9a799d71
AK		 1827int ixgbe_up(struct ixgbe_adapter *adapter)
1828{
1829 /* hardware has been reset, we need to reload some things */
1830 ixgbe_configure(adapter);
1831
1832 return ixgbe_up_complete(adapter);
1833}
1834
1835void ixgbe_reset(struct ixgbe_adapter *adapter)
1836{
1837 if (ixgbe_init_hw(&adapter->hw))
1838 DPRINTK(PROBE, ERR, "Hardware Error\n");
1839
1840 /* reprogram the RAR[0] in case user changed it. */
1841 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1842
1843}
1844
1845#ifdef CONFIG_PM
1846static int ixgbe_resume(struct pci_dev *pdev)
1847{
1848 struct net_device *netdev = pci_get_drvdata(pdev);
1849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1850 u32 err;
9a799d71
AK		 1851
1852 pci_set_power_state(pdev, PCI_D0);
1853 pci_restore_state(pdev);
1854 err = pci_enable_device(pdev);
1855 if (err) {
1856 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1857 "suspend\n");
1858 return err;
1859 }
1860 pci_set_master(pdev);
1861
1862 pci_enable_wake(pdev, PCI_D3hot, 0);
1863 pci_enable_wake(pdev, PCI_D3cold, 0);
1864
1865 if (netif_running(netdev)) {
021230d4 1866 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1867 if (err)
1868 return err;
1869 }
1870
1871 ixgbe_reset(adapter);
1872
1873 if (netif_running(netdev))
1874 ixgbe_up(adapter);
1875
1876 netif_device_attach(netdev);
1877
1878 return 0;
1879}
1880#endif
1881
1882/**
1883 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1884 * @adapter: board private structure
1885 * @rx_ring: ring to free buffers from
1886 **/
1887static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1888 struct ixgbe_ring *rx_ring)
1889{
1890 struct pci_dev *pdev = adapter->pdev;
1891 unsigned long size;
1892 unsigned int i;
1893
1894 /* Free all the Rx ring sk_buffs */
1895
1896 for (i = 0; i < rx_ring->count; i++) {
1897 struct ixgbe_rx_buffer *rx_buffer_info;
1898
1899 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1900 if (rx_buffer_info->dma) {
1901 pci_unmap_single(pdev, rx_buffer_info->dma,
1902 adapter->rx_buf_len,
1903 PCI_DMA_FROMDEVICE);
1904 rx_buffer_info->dma = 0;
1905 }
1906 if (rx_buffer_info->skb) {
1907 dev_kfree_skb(rx_buffer_info->skb);
1908 rx_buffer_info->skb = NULL;
1909 }
1910 if (!rx_buffer_info->page)
1911 continue;
1912 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1913 PCI_DMA_FROMDEVICE);
1914 rx_buffer_info->page_dma = 0;
1915
1916 put_page(rx_buffer_info->page);
1917 rx_buffer_info->page = NULL;
1918 }
1919
1920 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1921 memset(rx_ring->rx_buffer_info, 0, size);
1922
1923 /* Zero out the descriptor ring */
1924 memset(rx_ring->desc, 0, rx_ring->size);
1925
1926 rx_ring->next_to_clean = 0;
1927 rx_ring->next_to_use = 0;
1928
1929 writel(0, adapter->hw.hw_addr + rx_ring->head);
1930 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1931}
1932
1933/**
1934 * ixgbe_clean_tx_ring - Free Tx Buffers
1935 * @adapter: board private structure
1936 * @tx_ring: ring to be cleaned
1937 **/
1938static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1939 struct ixgbe_ring *tx_ring)
1940{
1941 struct ixgbe_tx_buffer *tx_buffer_info;
1942 unsigned long size;
1943 unsigned int i;
1944
1945 /* Free all the Tx ring sk_buffs */
1946
1947 for (i = 0; i < tx_ring->count; i++) {
1948 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1949 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1950 }
1951
1952 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1953 memset(tx_ring->tx_buffer_info, 0, size);
1954
1955 /* Zero out the descriptor ring */
1956 memset(tx_ring->desc, 0, tx_ring->size);
1957
1958 tx_ring->next_to_use = 0;
1959 tx_ring->next_to_clean = 0;
1960
1961 writel(0, adapter->hw.hw_addr + tx_ring->head);
1962 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1963}
1964
1965/**
021230d4 1966 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 1967 * @adapter: board private structure
1968 **/
021230d4 1969static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1970{
1971 int i;
1972
021230d4
AV		 1973 for (i = 0; i < adapter->num_rx_queues; i++)
1974 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 1975}
1976
1977/**
021230d4 1978 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 1979 * @adapter: board private structure
1980 **/
021230d4 1981static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1982{
1983 int i;
1984
021230d4
AV		 1985 for (i = 0; i < adapter->num_tx_queues; i++)
1986 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 1987}
1988
1989void ixgbe_down(struct ixgbe_adapter *adapter)
1990{
1991 struct net_device *netdev = adapter->netdev;
1992 u32 rxctrl;
1993
1994 /* signal that we are down to the interrupt handler */
1995 set_bit(__IXGBE_DOWN, &adapter->state);
1996
1997 /* disable receives */
1998 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
2000 rxctrl & ~IXGBE_RXCTRL_RXEN);
2001
2002 netif_tx_disable(netdev);
2003
2004 /* disable transmits in the hardware */
2005
2006 /* flush both disables */
2007 IXGBE_WRITE_FLUSH(&adapter->hw);
2008 msleep(10);
2009
2010 ixgbe_irq_disable(adapter);
2011
021230d4 2012 ixgbe_napi_disable_all(adapter);
9a799d71
AK		 2013 del_timer_sync(&adapter->watchdog_timer);
2014
2015 netif_carrier_off(netdev);
fd2ea0a7 2016 netif_tx_stop_all_queues(netdev);
9a799d71 2017
6f4a0e45
PL		 2018 if (!pci_channel_offline(adapter->pdev))
2019 ixgbe_reset(adapter);
9a799d71
AK		 2020 ixgbe_clean_all_tx_rings(adapter);
2021 ixgbe_clean_all_rx_rings(adapter);
2022
2023}
2024
2025static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2026{
2027 struct net_device *netdev = pci_get_drvdata(pdev);
2028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2029#ifdef CONFIG_PM
2030 int retval = 0;
2031#endif
2032
2033 netif_device_detach(netdev);
2034
2035 if (netif_running(netdev)) {
2036 ixgbe_down(adapter);
2037 ixgbe_free_irq(adapter);
2038 }
2039
2040#ifdef CONFIG_PM
2041 retval = pci_save_state(pdev);
2042 if (retval)
2043 return retval;
2044#endif
2045
2046 pci_enable_wake(pdev, PCI_D3hot, 0);
2047 pci_enable_wake(pdev, PCI_D3cold, 0);
2048
5eba3699
AV		 2049 ixgbe_release_hw_control(adapter);
2050
9a799d71
AK		 2051 pci_disable_device(pdev);
2052
2053 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2054
2055 return 0;
2056}
2057
2058static void ixgbe_shutdown(struct pci_dev *pdev)
2059{
2060 ixgbe_suspend(pdev, PMSG_SUSPEND);
2061}
2062
2063/**
021230d4
AV		 2064 * ixgbe_poll - NAPI Rx polling callback
2065 * @napi: structure for representing this polling device
2066 * @budget: how many packets driver is allowed to clean
2067 *
2068 * This function is used for legacy and MSI, NAPI mode
9a799d71 2069 **/
021230d4 2070static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2071{
021230d4
AV		 2072 struct ixgbe_q_vector *q_vector = container_of(napi,
2073 struct ixgbe_q_vector, napi);
2074 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 2075 int tx_cleaned = 0, work_done = 0;
9a799d71 2076
bd0362dd
JC		 2077#ifdef CONFIG_DCA
2078 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2079 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2080 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2081 }
2082#endif
2083
d2c7ddd6 2084 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2085 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2086
d2c7ddd6
DM		 2087 if (tx_cleaned)
2088 work_done = budget;
2089
53e52c72
DM		 2090 /* If budget not fully consumed, exit the polling mode */
2091 if (work_done < budget) {
021230d4 2092 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 2093 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
2094 ixgbe_set_itr(adapter);
d4f80882
AV		 2095 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2096 ixgbe_irq_enable(adapter);
9a799d71
AK		 2097 }
2098
2099 return work_done;
2100}
2101
2102/**
2103 * ixgbe_tx_timeout - Respond to a Tx Hang
2104 * @netdev: network interface device structure
2105 **/
2106static void ixgbe_tx_timeout(struct net_device *netdev)
2107{
2108 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2109
2110 /* Do the reset outside of interrupt context */
2111 schedule_work(&adapter->reset_task);
2112}
2113
2114static void ixgbe_reset_task(struct work_struct *work)
2115{
2116 struct ixgbe_adapter *adapter;
2117 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2118
2119 adapter->tx_timeout_count++;
2120
d4f80882 2121 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2122}
2123
021230d4
AV		 2124static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2125 int vectors)
2126{
2127 int err, vector_threshold;
2128
2129 /* We'll want at least 3 (vector_threshold):
2130 * 1) TxQ[0] Cleanup
2131 * 2) RxQ[0] Cleanup
2132 * 3) Other (Link Status Change, etc.)
2133 * 4) TCP Timer (optional)
2134 */
2135 vector_threshold = MIN_MSIX_COUNT;
2136
2137 /* The more we get, the more we will assign to Tx/Rx Cleanup
2138 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2139 * Right now, we simply care about how many we'll get; we'll
2140 * set them up later while requesting irq's.
2141 */
2142 while (vectors >= vector_threshold) {
2143 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2144 vectors);
2145 if (!err) /* Success in acquiring all requested vectors. */
2146 break;
2147 else if (err < 0)
2148 vectors = 0; /* Nasty failure, quit now */
2149 else /* err == number of vectors we should try again with */
2150 vectors = err;
2151 }
2152
2153 if (vectors < vector_threshold) {
2154 /* Can't allocate enough MSI-X interrupts? Oh well.
2155 * This just means we'll go with either a single MSI
2156 * vector or fall back to legacy interrupts.
2157 */
2158 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2159 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2160 kfree(adapter->msix_entries);
2161 adapter->msix_entries = NULL;
2162 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2163 adapter->num_tx_queues = 1;
2164 adapter->num_rx_queues = 1;
2165 } else {
2166 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2167 adapter->num_msix_vectors = vectors;
2168 }
2169}
2170
2171static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2172{
2173 int nrq, ntq;
2174 int feature_mask = 0, rss_i, rss_m;
2175
2176 /* Number of supported queues */
2177 switch (adapter->hw.mac.type) {
2178 case ixgbe_mac_82598EB:
2179 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2180 rss_m = 0;
2181 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2182
2183 switch (adapter->flags & feature_mask) {
2184 case (IXGBE_FLAG_RSS_ENABLED):
2185 rss_m = 0xF;
2186 nrq = rss_i;
30eba97a 2187 ntq = rss_i;
021230d4
AV		 2188 break;
2189 case 0:
2190 default:
2191 rss_i = 0;
2192 rss_m = 0;
2193 nrq = 1;
2194 ntq = 1;
2195 break;
2196 }
2197
2198 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2199 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2200 break;
2201 default:
2202 nrq = 1;
2203 ntq = 1;
2204 break;
2205 }
2206
2207 adapter->num_rx_queues = nrq;
2208 adapter->num_tx_queues = ntq;
2209}
2210
2211/**
2212 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2213 * @adapter: board private structure to initialize
2214 *
2215 * Once we know the feature-set enabled for the device, we'll cache
2216 * the register offset the descriptor ring is assigned to.
2217 **/
2218static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2219{
2220 /* TODO: Remove all uses of the indices in the cases where multiple
2221 * features are OR'd together, if the feature set makes sense.
2222 */
2223 int feature_mask = 0, rss_i;
2224 int i, txr_idx, rxr_idx;
2225
2226 /* Number of supported queues */
2227 switch (adapter->hw.mac.type) {
2228 case ixgbe_mac_82598EB:
2229 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2230 txr_idx = 0;
2231 rxr_idx = 0;
2232 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2233 switch (adapter->flags & feature_mask) {
2234 case (IXGBE_FLAG_RSS_ENABLED):
2235 for (i = 0; i < adapter->num_rx_queues; i++)
2236 adapter->rx_ring[i].reg_idx = i;
2237 for (i = 0; i < adapter->num_tx_queues; i++)
2238 adapter->tx_ring[i].reg_idx = i;
2239 break;
2240 case 0:
2241 default:
2242 break;
2243 }
2244 break;
2245 default:
2246 break;
2247 }
2248}
2249
9a799d71
AK		 2250/**
2251 * ixgbe_alloc_queues - Allocate memory for all rings
2252 * @adapter: board private structure to initialize
2253 *
2254 * We allocate one ring per queue at run-time since we don't know the
2255 * number of queues at compile-time. The polling_netdev array is
2256 * intended for Multiqueue, but should work fine with a single queue.
2257 **/
2258static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2259{
2260 int i;
2261
2262 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2263 sizeof(struct ixgbe_ring), GFP_KERNEL);
2264 if (!adapter->tx_ring)
021230d4 2265 goto err_tx_ring_allocation;
9a799d71
AK		 2266
2267 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2268 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2269 if (!adapter->rx_ring)
2270 goto err_rx_ring_allocation;
9a799d71 2271
021230d4
AV		 2272 for (i = 0; i < adapter->num_tx_queues; i++) {
2273 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2274 adapter->tx_ring[i].queue_index = i;
2275 }
9a799d71 2276 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 2277 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 2278 adapter->rx_ring[i].queue_index = i;
2279 }
2280
2281 ixgbe_cache_ring_register(adapter);
2282
2283 return 0;
2284
2285err_rx_ring_allocation:
2286 kfree(adapter->tx_ring);
2287err_tx_ring_allocation:
2288 return -ENOMEM;
2289}
2290
2291/**
2292 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2293 * @adapter: board private structure to initialize
2294 *
2295 * Attempt to configure the interrupts using the best available
2296 * capabilities of the hardware and the kernel.
2297 **/
2298static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2299 *adapter)
2300{
2301 int err = 0;
2302 int vector, v_budget;
2303
2304 /*
2305 * It's easy to be greedy for MSI-X vectors, but it really
2306 * doesn't do us much good if we have a lot more vectors
2307 * than CPU's. So let's be conservative and only ask for
2308 * (roughly) twice the number of vectors as there are CPU's.
2309 */
2310 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2311 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2312
2313 /*
2314 * At the same time, hardware can only support a maximum of
2315 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2316 * we can easily reach upwards of 64 Rx descriptor queues and
2317 * 32 Tx queues. Thus, we cap it off in those rare cases where
2318 * the cpu count also exceeds our vector limit.
2319 */
2320 v_budget = min(v_budget, MAX_MSIX_COUNT);
2321
2322 /* A failure in MSI-X entry allocation isn't fatal, but it does
2323 * mean we disable MSI-X capabilities of the adapter. */
2324 adapter->msix_entries = kcalloc(v_budget,
2325 sizeof(struct msix_entry), GFP_KERNEL);
2326 if (!adapter->msix_entries) {
2327 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2328 ixgbe_set_num_queues(adapter);
2329 kfree(adapter->tx_ring);
2330 kfree(adapter->rx_ring);
2331 err = ixgbe_alloc_queues(adapter);
2332 if (err) {
2333 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2334 "for queues\n");
2335 goto out;
2336 }
2337
2338 goto try_msi;
2339 }
2340
2341 for (vector = 0; vector < v_budget; vector++)
2342 adapter->msix_entries[vector].entry = vector;
2343
2344 ixgbe_acquire_msix_vectors(adapter, v_budget);
2345
2346 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2347 goto out;
2348
2349try_msi:
2350 err = pci_enable_msi(adapter->pdev);
2351 if (!err) {
2352 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2353 } else {
2354 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2355 "falling back to legacy. Error: %d\n", err);
2356 /* reset err */
2357 err = 0;
2358 }
2359
2360out:
30eba97a 2361 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2362 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2363
2364 return err;
2365}
2366
2367static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2368{
2369 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2370 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2371 pci_disable_msix(adapter->pdev);
2372 kfree(adapter->msix_entries);
2373 adapter->msix_entries = NULL;
2374 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2375 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2376 pci_disable_msi(adapter->pdev);
2377 }
2378 return;
2379}
2380
2381/**
2382 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2383 * @adapter: board private structure to initialize
2384 *
2385 * We determine which interrupt scheme to use based on...
2386 * - Kernel support (MSI, MSI-X)
2387 * - which can be user-defined (via MODULE_PARAM)
2388 * - Hardware queue count (num_*_queues)
2389 * - defined by miscellaneous hardware support/features (RSS, etc.)
2390 **/
2391static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2392{
2393 int err;
2394
2395 /* Number of supported queues */
2396 ixgbe_set_num_queues(adapter);
2397
2398 err = ixgbe_alloc_queues(adapter);
2399 if (err) {
2400 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2401 goto err_alloc_queues;
2402 }
2403
2404 err = ixgbe_set_interrupt_capability(adapter);
2405 if (err) {
2406 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2407 goto err_set_interrupt;
9a799d71
AK		 2408 }
2409
021230d4
AV		 2410 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2411 "Tx Queue count = %u\n",
2412 (adapter->num_rx_queues > 1) ? "Enabled" :
2413 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2414
2415 set_bit(__IXGBE_DOWN, &adapter->state);
2416
9a799d71 2417 return 0;
021230d4
AV		 2418
2419err_set_interrupt:
2420 kfree(adapter->tx_ring);
2421 kfree(adapter->rx_ring);
2422err_alloc_queues:
2423 return err;
9a799d71
AK		 2424}
2425
2426/**
2427 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2428 * @adapter: board private structure to initialize
2429 *
2430 * ixgbe_sw_init initializes the Adapter private data structure.
2431 * Fields are initialized based on PCI device information and
2432 * OS network device settings (MTU size).
2433 **/
2434static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2435{
2436 struct ixgbe_hw *hw = &adapter->hw;
2437 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2438 unsigned int rss;
2439
2440 /* Set capability flags */
2441 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2442 adapter->ring_feature[RING_F_RSS].indices = rss;
2443 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71 2444
f494e8fa
AV		 2445 /* Enable Dynamic interrupt throttling by default */
2446 adapter->rx_eitr = 1;
2447 adapter->tx_eitr = 1;
2448
9a799d71
AK		 2449 /* default flow control settings */
2450 hw->fc.original_type = ixgbe_fc_full;
2451 hw->fc.type = ixgbe_fc_full;
2452
021230d4 2453 /* select 10G link by default */
9a799d71
AK		 2454 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2455 if (hw->mac.ops.reset(hw)) {
2456 dev_err(&pdev->dev, "HW Init failed\n");
2457 return -EIO;
2458 }
3957d63d
AK		 2459 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2460 false)) {
9a799d71
AK		 2461 dev_err(&pdev->dev, "Link Speed setup failed\n");
2462 return -EIO;
2463 }
2464
2465 /* initialize eeprom parameters */
2466 if (ixgbe_init_eeprom(hw)) {
2467 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2468 return -EIO;
2469 }
2470
021230d4 2471 /* enable rx csum by default */
9a799d71
AK		 2472 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2473
9a799d71
AK		 2474 set_bit(__IXGBE_DOWN, &adapter->state);
2475
2476 return 0;
2477}
2478
2479/**
2480 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2481 * @adapter: board private structure
2482 * @txdr: tx descriptor ring (for a specific queue) to setup
2483 *
2484 * Return 0 on success, negative on failure
2485 **/
2486int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2487 struct ixgbe_ring *txdr)
2488{
2489 struct pci_dev *pdev = adapter->pdev;
2490 int size;
2491
2492 size = sizeof(struct ixgbe_tx_buffer) * txdr->count;
2493 txdr->tx_buffer_info = vmalloc(size);
2494 if (!txdr->tx_buffer_info) {
2495 DPRINTK(PROBE, ERR,
2496 "Unable to allocate memory for the transmit descriptor ring\n");
2497 return -ENOMEM;
2498 }
2499 memset(txdr->tx_buffer_info, 0, size);
2500
2501 /* round up to nearest 4K */
2502 txdr->size = txdr->count * sizeof(union ixgbe_adv_tx_desc);
2503 txdr->size = ALIGN(txdr->size, 4096);
2504
2505 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2506 if (!txdr->desc) {
2507 vfree(txdr->tx_buffer_info);
2508 DPRINTK(PROBE, ERR,
2509 "Memory allocation failed for the tx desc ring\n");
2510 return -ENOMEM;
2511 }
2512
9a799d71
AK		 2513 txdr->next_to_use = 0;
2514 txdr->next_to_clean = 0;
2515 txdr->work_limit = txdr->count;
9a799d71
AK		 2516
2517 return 0;
2518}
2519
2520/**
2521 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2522 * @adapter: board private structure
2523 * @rxdr: rx descriptor ring (for a specific queue) to setup
2524 *
2525 * Returns 0 on success, negative on failure
2526 **/
2527int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2528 struct ixgbe_ring *rxdr)
2529{
2530 struct pci_dev *pdev = adapter->pdev;
021230d4 2531 int size;
9a799d71 2532
177db6ff
MC		 2533 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
2534 rxdr->lro_mgr.lro_arr = vmalloc(size);
2535 if (!rxdr->lro_mgr.lro_arr)
2536 return -ENOMEM;
2537 memset(rxdr->lro_mgr.lro_arr, 0, size);
2538
9a799d71
AK		 2539 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count;
2540 rxdr->rx_buffer_info = vmalloc(size);
2541 if (!rxdr->rx_buffer_info) {
2542 DPRINTK(PROBE, ERR,
2543 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2544 goto alloc_failed;
9a799d71
AK		 2545 }
2546 memset(rxdr->rx_buffer_info, 0, size);
2547
9a799d71 2548 /* Round up to nearest 4K */
021230d4 2549 rxdr->size = rxdr->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2550 rxdr->size = ALIGN(rxdr->size, 4096);
2551
2552 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2553
2554 if (!rxdr->desc) {
2555 DPRINTK(PROBE, ERR,
2556 "Memory allocation failed for the rx desc ring\n");
2557 vfree(rxdr->rx_buffer_info);
177db6ff 2558 goto alloc_failed;
9a799d71
AK		 2559 }
2560
2561 rxdr->next_to_clean = 0;
2562 rxdr->next_to_use = 0;
9a799d71
AK		 2563
2564 return 0;
177db6ff
MC		 2565
2566alloc_failed:
2567 vfree(rxdr->lro_mgr.lro_arr);
2568 rxdr->lro_mgr.lro_arr = NULL;
2569 return -ENOMEM;
9a799d71
AK		 2570}
2571
2572/**
2573 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2574 * @adapter: board private structure
2575 * @tx_ring: Tx descriptor ring for a specific queue
2576 *
2577 * Free all transmit software resources
2578 **/
2579static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2580 struct ixgbe_ring *tx_ring)
2581{
2582 struct pci_dev *pdev = adapter->pdev;
2583
2584 ixgbe_clean_tx_ring(adapter, tx_ring);
2585
2586 vfree(tx_ring->tx_buffer_info);
2587 tx_ring->tx_buffer_info = NULL;
2588
2589 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2590
2591 tx_ring->desc = NULL;
2592}
2593
2594/**
2595 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2596 * @adapter: board private structure
2597 *
2598 * Free all transmit software resources
2599 **/
2600static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2601{
2602 int i;
2603
2604 for (i = 0; i < adapter->num_tx_queues; i++)
2605 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2606}
2607
2608/**
2609 * ixgbe_free_rx_resources - Free Rx Resources
2610 * @adapter: board private structure
2611 * @rx_ring: ring to clean the resources from
2612 *
2613 * Free all receive software resources
2614 **/
2615static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2616 struct ixgbe_ring *rx_ring)
2617{
2618 struct pci_dev *pdev = adapter->pdev;
2619
177db6ff
MC		 2620 vfree(rx_ring->lro_mgr.lro_arr);
2621 rx_ring->lro_mgr.lro_arr = NULL;
2622
9a799d71
AK		 2623 ixgbe_clean_rx_ring(adapter, rx_ring);
2624
2625 vfree(rx_ring->rx_buffer_info);
2626 rx_ring->rx_buffer_info = NULL;
2627
2628 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2629
2630 rx_ring->desc = NULL;
2631}
2632
2633/**
2634 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2635 * @adapter: board private structure
2636 *
2637 * Free all receive software resources
2638 **/
2639static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2640{
2641 int i;
2642
2643 for (i = 0; i < adapter->num_rx_queues; i++)
2644 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2645}
2646
2647/**
021230d4 2648 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2649 * @adapter: board private structure
2650 *
2651 * If this function returns with an error, then it's possible one or
2652 * more of the rings is populated (while the rest are not). It is the
2653 * callers duty to clean those orphaned rings.
2654 *
2655 * Return 0 on success, negative on failure
2656 **/
2657static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2658{
2659 int i, err = 0;
2660
2661 for (i = 0; i < adapter->num_tx_queues; i++) {
2662 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2663 if (err) {
2664 DPRINTK(PROBE, ERR,
2665 "Allocation for Tx Queue %u failed\n", i);
2666 break;
2667 }
2668 }
2669
2670 return err;
2671}
2672
2673/**
021230d4 2674 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2675 * @adapter: board private structure
2676 *
2677 * If this function returns with an error, then it's possible one or
2678 * more of the rings is populated (while the rest are not). It is the
2679 * callers duty to clean those orphaned rings.
2680 *
2681 * Return 0 on success, negative on failure
2682 **/
2683
2684static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2685{
2686 int i, err = 0;
2687
2688 for (i = 0; i < adapter->num_rx_queues; i++) {
2689 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2690 if (err) {
2691 DPRINTK(PROBE, ERR,
2692 "Allocation for Rx Queue %u failed\n", i);
2693 break;
2694 }
2695 }
2696
2697 return err;
2698}
2699
2700/**
2701 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2702 * @netdev: network interface device structure
2703 * @new_mtu: new value for maximum frame size
2704 *
2705 * Returns 0 on success, negative on failure
2706 **/
2707static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2708{
2709 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2710 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2711
2712 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2713 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2714 return -EINVAL;
2715
021230d4
AV		 2716 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2717 netdev->mtu, new_mtu);
2718 /* must set new MTU before calling down or up */
9a799d71
AK		 2719 netdev->mtu = new_mtu;
2720
d4f80882
AV		 2721 if (netif_running(netdev))
2722 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2723
2724 return 0;
2725}
2726
2727/**
2728 * ixgbe_open - Called when a network interface is made active
2729 * @netdev: network interface device structure
2730 *
2731 * Returns 0 on success, negative value on failure
2732 *
2733 * The open entry point is called when a network interface is made
2734 * active by the system (IFF_UP). At this point all resources needed
2735 * for transmit and receive operations are allocated, the interrupt
2736 * handler is registered with the OS, the watchdog timer is started,
2737 * and the stack is notified that the interface is ready.
2738 **/
2739static int ixgbe_open(struct net_device *netdev)
2740{
2741 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2742 int err;
4bebfaa5
AK		 2743
2744 /* disallow open during test */
2745 if (test_bit(__IXGBE_TESTING, &adapter->state))
2746 return -EBUSY;
9a799d71 2747
9a799d71
AK		 2748 /* allocate transmit descriptors */
2749 err = ixgbe_setup_all_tx_resources(adapter);
2750 if (err)
2751 goto err_setup_tx;
2752
9a799d71
AK		 2753 /* allocate receive descriptors */
2754 err = ixgbe_setup_all_rx_resources(adapter);
2755 if (err)
2756 goto err_setup_rx;
2757
2758 ixgbe_configure(adapter);
2759
021230d4 2760 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2761 if (err)
2762 goto err_req_irq;
2763
9a799d71
AK		 2764 err = ixgbe_up_complete(adapter);
2765 if (err)
2766 goto err_up;
2767
d55b53ff
JK		 2768 netif_tx_start_all_queues(netdev);
2769
9a799d71
AK		 2770 return 0;
2771
2772err_up:
5eba3699 2773 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2774 ixgbe_free_irq(adapter);
2775err_req_irq:
2776 ixgbe_free_all_rx_resources(adapter);
2777err_setup_rx:
2778 ixgbe_free_all_tx_resources(adapter);
2779err_setup_tx:
2780 ixgbe_reset(adapter);
2781
2782 return err;
2783}
2784
2785/**
2786 * ixgbe_close - Disables a network interface
2787 * @netdev: network interface device structure
2788 *
2789 * Returns 0, this is not allowed to fail
2790 *
2791 * The close entry point is called when an interface is de-activated
2792 * by the OS. The hardware is still under the drivers control, but
2793 * needs to be disabled. A global MAC reset is issued to stop the
2794 * hardware, and all transmit and receive resources are freed.
2795 **/
2796static int ixgbe_close(struct net_device *netdev)
2797{
2798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2799
2800 ixgbe_down(adapter);
2801 ixgbe_free_irq(adapter);
2802
2803 ixgbe_free_all_tx_resources(adapter);
2804 ixgbe_free_all_rx_resources(adapter);
2805
5eba3699 2806 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2807
2808 return 0;
2809}
2810
2811/**
2812 * ixgbe_update_stats - Update the board statistics counters.
2813 * @adapter: board private structure
2814 **/
2815void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2816{
2817 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2818 u64 total_mpc = 0;
2819 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2820
2821 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2822 for (i = 0; i < 8; i++) {
2823 /* for packet buffers not used, the register should read 0 */
2824 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2825 missed_rx += mpc;
2826 adapter->stats.mpc[i] += mpc;
2827 total_mpc += adapter->stats.mpc[i];
2828 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2829 }
2830 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2831 /* work around hardware counting issue */
2832 adapter->stats.gprc -= missed_rx;
2833
2834 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2835 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2836 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2837 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2838 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2839 adapter->stats.bprc += bprc;
2840 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2841 adapter->stats.mprc -= bprc;
2842 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2843 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2844 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2845 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2846 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2847 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2848 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 2849 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2850 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 2851 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 2852 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2853 adapter->stats.lxontxc += lxon;
2854 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2855 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 2856 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2857 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 2858 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2859 /*
2860 * 82598 errata - tx of flow control packets is included in tx counters
2861 */
2862 xon_off_tot = lxon + lxoff;
2863 adapter->stats.gptc -= xon_off_tot;
2864 adapter->stats.mptc -= xon_off_tot;
2865 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 2866 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2867 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2868 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 2869 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2870 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 2871 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 2872 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2873 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2874 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2875 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2876 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 2877 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2878
2879 /* Fill out the OS statistics structure */
9a799d71
AK		 2880 adapter->net_stats.multicast = adapter->stats.mprc;
2881
2882 /* Rx Errors */
2883 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2884 adapter->stats.rlec;
2885 adapter->net_stats.rx_dropped = 0;
2886 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2887 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 2888 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 2889}
2890
2891/**
2892 * ixgbe_watchdog - Timer Call-back
2893 * @data: pointer to adapter cast into an unsigned long
2894 **/
2895static void ixgbe_watchdog(unsigned long data)
2896{
2897 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2898 struct net_device *netdev = adapter->netdev;
2899 bool link_up;
2900 u32 link_speed = 0;
2901
3957d63d 2902 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
9a799d71
AK		 2903
2904 if (link_up) {
2905 if (!netif_carrier_ok(netdev)) {
2906 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2907 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2908#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2909#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2910 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2911 "Flow Control: %s\n",
2912 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2913 "10 Gbps" :
2914 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5a059e9d 2915 "1 Gbps" : "unknown speed")),
9a799d71
AK		 2916 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2917 (FLOW_RX ? "RX" :
2918 (FLOW_TX ? "TX" : "None"))));
2919
2920 netif_carrier_on(netdev);
fd2ea0a7 2921 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 2922 } else {
2923 /* Force detection of hung controller */
2924 adapter->detect_tx_hung = true;
2925 }
2926 } else {
2927 if (netif_carrier_ok(netdev)) {
2928 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2929 netif_carrier_off(netdev);
fd2ea0a7 2930 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 2931 }
2932 }
2933
2934 ixgbe_update_stats(adapter);
2935
021230d4
AV		 2936 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2937 /* Cause software interrupt to ensure rx rings are cleaned */
2938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2939 u32 eics =
2940 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
2941 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
2942 } else {
2943 /* for legacy and MSI interrupts don't set any bits that
2944 * are enabled for EIAM, because this operation would
2945 * set *both* EIMS and EICS for any bit in EIAM */
2946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
2947 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
2948 }
2949 /* Reset the timer */
9a799d71
AK		 2950 mod_timer(&adapter->watchdog_timer,
2951 round_jiffies(jiffies + 2 * HZ));
021230d4 2952 }
9a799d71
AK		 2953}
2954
9a799d71
AK		 2955static int ixgbe_tso(struct ixgbe_adapter *adapter,
2956 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
2957 u32 tx_flags, u8 *hdr_len)
2958{
2959 struct ixgbe_adv_tx_context_desc *context_desc;
2960 unsigned int i;
2961 int err;
2962 struct ixgbe_tx_buffer *tx_buffer_info;
2963 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2964 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 2965
2966 if (skb_is_gso(skb)) {
2967 if (skb_header_cloned(skb)) {
2968 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2969 if (err)
2970 return err;
2971 }
2972 l4len = tcp_hdrlen(skb);
2973 *hdr_len += l4len;
2974
8327d000 2975 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 2976 struct iphdr *iph = ip_hdr(skb);
2977 iph->tot_len = 0;
2978 iph->check = 0;
2979 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2980 iph->daddr, 0,
2981 IPPROTO_TCP,
2982 0);
2983 adapter->hw_tso_ctxt++;
2984 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2985 ipv6_hdr(skb)->payload_len = 0;
2986 tcp_hdr(skb)->check =
2987 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2988 &ipv6_hdr(skb)->daddr,
2989 0, IPPROTO_TCP, 0);
2990 adapter->hw_tso6_ctxt++;
2991 }
2992
2993 i = tx_ring->next_to_use;
2994
2995 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2996 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2997
2998 /* VLAN MACLEN IPLEN */
2999 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3000 vlan_macip_lens |=
3001 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3002 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3003 IXGBE_ADVTXD_MACLEN_SHIFT);
3004 *hdr_len += skb_network_offset(skb);
3005 vlan_macip_lens |=
3006 (skb_transport_header(skb) - skb_network_header(skb));
3007 *hdr_len +=
3008 (skb_transport_header(skb) - skb_network_header(skb));
3009 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3010 context_desc->seqnum_seed = 0;
3011
3012 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3013 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3014 IXGBE_ADVTXD_DTYP_CTXT);
3015
8327d000 3016 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3017 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3018 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3019 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3020
3021 /* MSS L4LEN IDX */
3022 mss_l4len_idx |=
3023 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3024 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3025 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3026
3027 tx_buffer_info->time_stamp = jiffies;
3028 tx_buffer_info->next_to_watch = i;
3029
3030 i++;
3031 if (i == tx_ring->count)
3032 i = 0;
3033 tx_ring->next_to_use = i;
3034
3035 return true;
3036 }
3037 return false;
3038}
3039
3040static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3041 struct ixgbe_ring *tx_ring,
3042 struct sk_buff *skb, u32 tx_flags)
3043{
3044 struct ixgbe_adv_tx_context_desc *context_desc;
3045 unsigned int i;
3046 struct ixgbe_tx_buffer *tx_buffer_info;
3047 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3048
3049 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3050 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3051 i = tx_ring->next_to_use;
3052 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3053 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3054
3055 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3056 vlan_macip_lens |=
3057 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3058 vlan_macip_lens |= (skb_network_offset(skb) <<
3059 IXGBE_ADVTXD_MACLEN_SHIFT);
3060 if (skb->ip_summed == CHECKSUM_PARTIAL)
3061 vlan_macip_lens |= (skb_transport_header(skb) -
3062 skb_network_header(skb));
3063
3064 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3065 context_desc->seqnum_seed = 0;
3066
3067 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3068 IXGBE_ADVTXD_DTYP_CTXT);
3069
3070 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3071 switch (skb->protocol) {
3072 case __constant_htons(ETH_P_IP):
9a799d71 3073 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3074 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3075 type_tucmd_mlhl |=
3076 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3077 break;
3078
3079 case __constant_htons(ETH_P_IPV6):
3080 /* XXX what about other V6 headers?? */
3081 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3082 type_tucmd_mlhl |=
3083 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3084 break;
9a799d71 3085
41825d71
AK		 3086 default:
3087 if (unlikely(net_ratelimit())) {
3088 DPRINTK(PROBE, WARNING,
3089 "partial checksum but proto=%x!\n",
3090 skb->protocol);
3091 }
3092 break;
3093 }
9a799d71
AK		 3094 }
3095
3096 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3097 context_desc->mss_l4len_idx = 0;
3098
3099 tx_buffer_info->time_stamp = jiffies;
3100 tx_buffer_info->next_to_watch = i;
3101 adapter->hw_csum_tx_good++;
3102 i++;
3103 if (i == tx_ring->count)
3104 i = 0;
3105 tx_ring->next_to_use = i;
3106
3107 return true;
3108 }
3109 return false;
3110}
3111
3112static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3113 struct ixgbe_ring *tx_ring,
3114 struct sk_buff *skb, unsigned int first)
3115{
3116 struct ixgbe_tx_buffer *tx_buffer_info;
3117 unsigned int len = skb->len;
3118 unsigned int offset = 0, size, count = 0, i;
3119 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3120 unsigned int f;
3121
3122 len -= skb->data_len;
3123
3124 i = tx_ring->next_to_use;
3125
3126 while (len) {
3127 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3128 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3129
3130 tx_buffer_info->length = size;
3131 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3132 skb->data + offset,
3133 size, PCI_DMA_TODEVICE);
3134 tx_buffer_info->time_stamp = jiffies;
3135 tx_buffer_info->next_to_watch = i;
3136
3137 len -= size;
3138 offset += size;
3139 count++;
3140 i++;
3141 if (i == tx_ring->count)
3142 i = 0;
3143 }
3144
3145 for (f = 0; f < nr_frags; f++) {
3146 struct skb_frag_struct *frag;
3147
3148 frag = &skb_shinfo(skb)->frags[f];
3149 len = frag->size;
3150 offset = frag->page_offset;
3151
3152 while (len) {
3153 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3154 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3155
3156 tx_buffer_info->length = size;
3157 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3158 frag->page,
3159 offset,
3160 size, PCI_DMA_TODEVICE);
3161 tx_buffer_info->time_stamp = jiffies;
3162 tx_buffer_info->next_to_watch = i;
3163
3164 len -= size;
3165 offset += size;
3166 count++;
3167 i++;
3168 if (i == tx_ring->count)
3169 i = 0;
3170 }
3171 }
3172 if (i == 0)
3173 i = tx_ring->count - 1;
3174 else
3175 i = i - 1;
3176 tx_ring->tx_buffer_info[i].skb = skb;
3177 tx_ring->tx_buffer_info[first].next_to_watch = i;
3178
3179 return count;
3180}
3181
3182static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3183 struct ixgbe_ring *tx_ring,
3184 int tx_flags, int count, u32 paylen, u8 hdr_len)
3185{
3186 union ixgbe_adv_tx_desc *tx_desc = NULL;
3187 struct ixgbe_tx_buffer *tx_buffer_info;
3188 u32 olinfo_status = 0, cmd_type_len = 0;
3189 unsigned int i;
3190 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3191
3192 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3193
3194 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3195
3196 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3197 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3198
3199 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3200 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3201
3202 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3203 IXGBE_ADVTXD_POPTS_SHIFT;
3204
3205 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3206 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3207 IXGBE_ADVTXD_POPTS_SHIFT;
3208
3209 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3210 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3211 IXGBE_ADVTXD_POPTS_SHIFT;
3212
3213 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3214
3215 i = tx_ring->next_to_use;
3216 while (count--) {
3217 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3218 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3219 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3220 tx_desc->read.cmd_type_len =
3221 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3222 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3223
3224 i++;
3225 if (i == tx_ring->count)
3226 i = 0;
3227 }
3228
3229 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3230
3231 /*
3232 * Force memory writes to complete before letting h/w
3233 * know there are new descriptors to fetch. (Only
3234 * applicable for weak-ordered memory model archs,
3235 * such as IA-64).
3236 */
3237 wmb();
3238
3239 tx_ring->next_to_use = i;
3240 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3241}
3242
e092be60
AV		 3243static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3244 struct ixgbe_ring *tx_ring, int size)
3245{
3246 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3247
30eba97a 3248 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3249 /* Herbert's original patch had:
3250 * smp_mb__after_netif_stop_queue();
3251 * but since that doesn't exist yet, just open code it. */
3252 smp_mb();
3253
3254 /* We need to check again in a case another CPU has just
3255 * made room available. */
3256 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3257 return -EBUSY;
3258
3259 /* A reprieve! - use start_queue because it doesn't call schedule */
30eba97a 3260 netif_wake_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3261 ++adapter->restart_queue;
3262 return 0;
3263}
3264
3265static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3266 struct ixgbe_ring *tx_ring, int size)
3267{
3268 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3269 return 0;
3270 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3271}
3272
3273
9a799d71
AK		 3274static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3275{
3276 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3277 struct ixgbe_ring *tx_ring;
3278 unsigned int len = skb->len;
3279 unsigned int first;
3280 unsigned int tx_flags = 0;
30eba97a
AV		 3281 u8 hdr_len = 0;
3282 int r_idx = 0, tso;
9a799d71
AK		 3283 unsigned int mss = 0;
3284 int count = 0;
3285 unsigned int f;
3286 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3287 len -= skb->data_len;
30eba97a 3288 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3289 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3290
9a799d71
AK		 3291
3292 if (skb->len <= 0) {
3293 dev_kfree_skb(skb);
3294 return NETDEV_TX_OK;
3295 }
3296 mss = skb_shinfo(skb)->gso_size;
3297
3298 if (mss)
3299 count++;
3300 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3301 count++;
3302
3303 count += TXD_USE_COUNT(len);
3304 for (f = 0; f < nr_frags; f++)
3305 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3306
e092be60 3307 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3308 adapter->tx_busy++;
9a799d71
AK		 3309 return NETDEV_TX_BUSY;
3310 }
9a799d71
AK		 3311 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3312 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3313 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3314 }
3315
8327d000 3316 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3317 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3318 first = tx_ring->next_to_use;
3319 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3320 if (tso < 0) {
3321 dev_kfree_skb_any(skb);
3322 return NETDEV_TX_OK;
3323 }
3324
3325 if (tso)
3326 tx_flags |= IXGBE_TX_FLAGS_TSO;
3327 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3328 (skb->ip_summed == CHECKSUM_PARTIAL))
3329 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3330
3331 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3332 ixgbe_tx_map(adapter, tx_ring, skb, first),
3333 skb->len, hdr_len);
3334
3335 netdev->trans_start = jiffies;
3336
e092be60 3337 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3338
3339 return NETDEV_TX_OK;
3340}
3341
3342/**
3343 * ixgbe_get_stats - Get System Network Statistics
3344 * @netdev: network interface device structure
3345 *
3346 * Returns the address of the device statistics structure.
3347 * The statistics are actually updated from the timer callback.
3348 **/
3349static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3350{
3351 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3352
3353 /* only return the current stats */
3354 return &adapter->net_stats;
3355}
3356
3357/**
3358 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3359 * @netdev: network interface device structure
3360 * @p: pointer to an address structure
3361 *
3362 * Returns 0 on success, negative on failure
3363 **/
3364static int ixgbe_set_mac(struct net_device *netdev, void *p)
3365{
3366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3367 struct sockaddr *addr = p;
3368
3369 if (!is_valid_ether_addr(addr->sa_data))
3370 return -EADDRNOTAVAIL;
3371
3372 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3373 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3374
3375 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3376
3377 return 0;
3378}
3379
3380#ifdef CONFIG_NET_POLL_CONTROLLER
3381/*
3382 * Polling 'interrupt' - used by things like netconsole to send skbs
3383 * without having to re-enable interrupts. It's not called while
3384 * the interrupt routine is executing.
3385 */
3386static void ixgbe_netpoll(struct net_device *netdev)
3387{
3388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3389
3390 disable_irq(adapter->pdev->irq);
3391 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3392 ixgbe_intr(adapter->pdev->irq, netdev);
3393 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3394 enable_irq(adapter->pdev->irq);
3395}
3396#endif
3397
021230d4
AV		 3398/**
3399 * ixgbe_napi_add_all - prep napi structs for use
3400 * @adapter: private struct
3401 * helper function to napi_add each possible q_vector->napi
3402 */
3403static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3404{
3405 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3406 int (*poll)(struct napi_struct *, int);
3407
3408 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3409 poll = &ixgbe_clean_rxonly;
3410 } else {
3411 poll = &ixgbe_poll;
3412 /* only one q_vector for legacy modes */
3413 q_vectors = 1;
3414 }
3415
3416 for (i = 0; i < q_vectors; i++) {
3417 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3418 netif_napi_add(adapter->netdev, &q_vector->napi,
3419 (*poll), 64);
3420 }
3421}
3422
9a799d71
AK		 3423/**
3424 * ixgbe_probe - Device Initialization Routine
3425 * @pdev: PCI device information struct
3426 * @ent: entry in ixgbe_pci_tbl
3427 *
3428 * Returns 0 on success, negative on failure
3429 *
3430 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3431 * The OS initialization, configuring of the adapter private structure,
3432 * and a hardware reset occur.
3433 **/
3434static int __devinit ixgbe_probe(struct pci_dev *pdev,
3435 const struct pci_device_id *ent)
3436{
3437 struct net_device *netdev;
3438 struct ixgbe_adapter *adapter = NULL;
3439 struct ixgbe_hw *hw;
3440 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3441 unsigned long mmio_start, mmio_len;
3442 static int cards_found;
3443 int i, err, pci_using_dac;
3444 u16 link_status, link_speed, link_width;
3445 u32 part_num;
3446
3447 err = pci_enable_device(pdev);
3448 if (err)
3449 return err;
3450
3451 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3452 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3453 pci_using_dac = 1;
3454 } else {
3455 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3456 if (err) {
3457 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3458 if (err) {
3459 dev_err(&pdev->dev, "No usable DMA "
3460 "configuration, aborting\n");
3461 goto err_dma;
3462 }
3463 }
3464 pci_using_dac = 0;
3465 }
3466
3467 err = pci_request_regions(pdev, ixgbe_driver_name);
3468 if (err) {
3469 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3470 goto err_pci_reg;
3471 }
3472
3473 pci_set_master(pdev);
fb3b27bc 3474 pci_save_state(pdev);
9a799d71 3475
30eba97a 3476 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3477 if (!netdev) {
3478 err = -ENOMEM;
3479 goto err_alloc_etherdev;
3480 }
3481
9a799d71
AK		 3482 SET_NETDEV_DEV(netdev, &pdev->dev);
3483
3484 pci_set_drvdata(pdev, netdev);
3485 adapter = netdev_priv(netdev);
3486
3487 adapter->netdev = netdev;
3488 adapter->pdev = pdev;
3489 hw = &adapter->hw;
3490 hw->back = adapter;
3491 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3492
3493 mmio_start = pci_resource_start(pdev, 0);
3494 mmio_len = pci_resource_len(pdev, 0);
3495
3496 hw->hw_addr = ioremap(mmio_start, mmio_len);
3497 if (!hw->hw_addr) {
3498 err = -EIO;
3499 goto err_ioremap;
3500 }
3501
3502 for (i = 1; i <= 5; i++) {
3503 if (pci_resource_len(pdev, i) == 0)
3504 continue;
3505 }
3506
3507 netdev->open = &ixgbe_open;
3508 netdev->stop = &ixgbe_close;
3509 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3510 netdev->get_stats = &ixgbe_get_stats;
3511 netdev->set_multicast_list = &ixgbe_set_multi;
3512 netdev->set_mac_address = &ixgbe_set_mac;
3513 netdev->change_mtu = &ixgbe_change_mtu;
3514 ixgbe_set_ethtool_ops(netdev);
3515 netdev->tx_timeout = &ixgbe_tx_timeout;
3516 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3517 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3518 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3519 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3520#ifdef CONFIG_NET_POLL_CONTROLLER
3521 netdev->poll_controller = ixgbe_netpoll;
3522#endif
3523 strcpy(netdev->name, pci_name(pdev));
3524
3525 netdev->mem_start = mmio_start;
3526 netdev->mem_end = mmio_start + mmio_len;
3527
3528 adapter->bd_number = cards_found;
3529
3530 /* PCI config space info */
3531 hw->vendor_id = pdev->vendor;
3532 hw->device_id = pdev->device;
3533 hw->revision_id = pdev->revision;
3534 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3535 hw->subsystem_device_id = pdev->subsystem_device;
3536
3537 /* Setup hw api */
3538 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3539 hw->mac.type = ii->mac;
9a799d71
AK		 3540
3541 err = ii->get_invariants(hw);
3542 if (err)
3543 goto err_hw_init;
3544
3545 /* setup the private structure */
3546 err = ixgbe_sw_init(adapter);
3547 if (err)
3548 goto err_sw_init;
3549
3550 netdev->features = NETIF_F_SG |
3551 NETIF_F_HW_CSUM |
3552 NETIF_F_HW_VLAN_TX |
3553 NETIF_F_HW_VLAN_RX |
3554 NETIF_F_HW_VLAN_FILTER;
3555
177db6ff 3556 netdev->features |= NETIF_F_LRO;
9a799d71 3557 netdev->features |= NETIF_F_TSO;
9a799d71 3558 netdev->features |= NETIF_F_TSO6;
ad31c402
JK		 3559
3560 netdev->vlan_features |= NETIF_F_TSO;
3561 netdev->vlan_features |= NETIF_F_TSO6;
3562 netdev->vlan_features |= NETIF_F_HW_CSUM;
3563 netdev->vlan_features |= NETIF_F_SG;
3564
9a799d71
AK		 3565 if (pci_using_dac)
3566 netdev->features |= NETIF_F_HIGHDMA;
3567
9a799d71
AK		 3568 /* make sure the EEPROM is good */
3569 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3570 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3571 err = -EIO;
3572 goto err_eeprom;
3573 }
3574
3575 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3576 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3577
3578 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3579 err = -EIO;
3580 goto err_eeprom;
3581 }
3582
3583 init_timer(&adapter->watchdog_timer);
3584 adapter->watchdog_timer.function = &ixgbe_watchdog;
3585 adapter->watchdog_timer.data = (unsigned long)adapter;
3586
3587 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3588
3589 /* initialize default flow control settings */
3590 hw->fc.original_type = ixgbe_fc_full;
3591 hw->fc.type = ixgbe_fc_full;
3592 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3593 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3594 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3595
021230d4
AV		 3596 err = ixgbe_init_interrupt_scheme(adapter);
3597 if (err)
3598 goto err_sw_init;
9a799d71
AK		 3599
3600 /* print bus type/speed/width info */
3601 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3602 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3603 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3604 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3605 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3606 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3607 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3608 "Unknown"),
3609 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3610 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3611 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3612 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3613 "Unknown"),
3614 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3615 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3616 ixgbe_read_part_num(hw, &part_num);
3617 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3618 hw->mac.type, hw->phy.type,
3619 (part_num >> 8), (part_num & 0xff));
3620
0c254d86
AK		 3621 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3622 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3623 "this card is not sufficient for optimal "
3624 "performance.\n");
3625 dev_warn(&pdev->dev, "For optimal performance a x8 "
3626 "PCI-Express slot is required.\n");
3627 }
3628
9a799d71
AK		 3629 /* reset the hardware with the new settings */
3630 ixgbe_start_hw(hw);
3631
3632 netif_carrier_off(netdev);
fd2ea0a7 3633 netif_tx_stop_all_queues(netdev);
9a799d71 3634
021230d4
AV		 3635 ixgbe_napi_add_all(adapter);
3636
9a799d71
AK		 3637 strcpy(netdev->name, "eth%d");
3638 err = register_netdev(netdev);
3639 if (err)
3640 goto err_register;
3641
bd0362dd 3642#ifdef CONFIG_DCA
652f093f 3643 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3644 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3645 /* always use CB2 mode, difference is masked
3646 * in the CB driver */
3647 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3648 ixgbe_setup_dca(adapter);
3649 }
3650#endif
9a799d71
AK		 3651
3652 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3653 cards_found++;
3654 return 0;
3655
3656err_register:
5eba3699 3657 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3658err_hw_init:
3659err_sw_init:
021230d4 3660 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3661err_eeprom:
3662 iounmap(hw->hw_addr);
3663err_ioremap:
3664 free_netdev(netdev);
3665err_alloc_etherdev:
3666 pci_release_regions(pdev);
3667err_pci_reg:
3668err_dma:
3669 pci_disable_device(pdev);
3670 return err;
3671}
3672
3673/**
3674 * ixgbe_remove - Device Removal Routine
3675 * @pdev: PCI device information struct
3676 *
3677 * ixgbe_remove is called by the PCI subsystem to alert the driver
3678 * that it should release a PCI device. The could be caused by a
3679 * Hot-Plug event, or because the driver is going to be removed from
3680 * memory.
3681 **/
3682static void __devexit ixgbe_remove(struct pci_dev *pdev)
3683{
3684 struct net_device *netdev = pci_get_drvdata(pdev);
3685 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3686
3687 set_bit(__IXGBE_DOWN, &adapter->state);
3688 del_timer_sync(&adapter->watchdog_timer);
3689
3690 flush_scheduled_work();
3691
bd0362dd
JC		 3692#ifdef CONFIG_DCA
3693 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3694 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3695 dca_remove_requester(&pdev->dev);
3696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3697 }
3698
3699#endif
9a799d71
AK		 3700 unregister_netdev(netdev);
3701
021230d4 3702 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3703
021230d4 3704 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3705
3706 iounmap(adapter->hw.hw_addr);
3707 pci_release_regions(pdev);
3708
021230d4
AV		 3709 DPRINTK(PROBE, INFO, "complete\n");
3710 kfree(adapter->tx_ring);
3711 kfree(adapter->rx_ring);
3712
9a799d71
AK		 3713 free_netdev(netdev);
3714
3715 pci_disable_device(pdev);
3716}
3717
3718/**
3719 * ixgbe_io_error_detected - called when PCI error is detected
3720 * @pdev: Pointer to PCI device
3721 * @state: The current pci connection state
3722 *
3723 * This function is called after a PCI bus error affecting
3724 * this device has been detected.
3725 */
3726static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3727 pci_channel_state_t state)
3728{
3729 struct net_device *netdev = pci_get_drvdata(pdev);
3730 struct ixgbe_adapter *adapter = netdev->priv;
3731
3732 netif_device_detach(netdev);
3733
3734 if (netif_running(netdev))
3735 ixgbe_down(adapter);
3736 pci_disable_device(pdev);
3737
3738 /* Request a slot slot reset. */
3739 return PCI_ERS_RESULT_NEED_RESET;
3740}
3741
3742/**
3743 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3744 * @pdev: Pointer to PCI device
3745 *
3746 * Restart the card from scratch, as if from a cold-boot.
3747 */
3748static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3749{
3750 struct net_device *netdev = pci_get_drvdata(pdev);
3751 struct ixgbe_adapter *adapter = netdev->priv;
3752
3753 if (pci_enable_device(pdev)) {
3754 DPRINTK(PROBE, ERR,
3755 "Cannot re-enable PCI device after reset.\n");
3756 return PCI_ERS_RESULT_DISCONNECT;
3757 }
3758 pci_set_master(pdev);
fb3b27bc 3759 pci_restore_state(pdev);
9a799d71
AK		 3760
3761 pci_enable_wake(pdev, PCI_D3hot, 0);
3762 pci_enable_wake(pdev, PCI_D3cold, 0);
3763
3764 ixgbe_reset(adapter);
3765
3766 return PCI_ERS_RESULT_RECOVERED;
3767}
3768
3769/**
3770 * ixgbe_io_resume - called when traffic can start flowing again.
3771 * @pdev: Pointer to PCI device
3772 *
3773 * This callback is called when the error recovery driver tells us that
3774 * its OK to resume normal operation.
3775 */
3776static void ixgbe_io_resume(struct pci_dev *pdev)
3777{
3778 struct net_device *netdev = pci_get_drvdata(pdev);
3779 struct ixgbe_adapter *adapter = netdev->priv;
3780
3781 if (netif_running(netdev)) {
3782 if (ixgbe_up(adapter)) {
3783 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3784 return;
3785 }
3786 }
3787
3788 netif_device_attach(netdev);
3789
3790}
3791
3792static struct pci_error_handlers ixgbe_err_handler = {
3793 .error_detected = ixgbe_io_error_detected,
3794 .slot_reset = ixgbe_io_slot_reset,
3795 .resume = ixgbe_io_resume,
3796};
3797
3798static struct pci_driver ixgbe_driver = {
3799 .name = ixgbe_driver_name,
3800 .id_table = ixgbe_pci_tbl,
3801 .probe = ixgbe_probe,
3802 .remove = __devexit_p(ixgbe_remove),
3803#ifdef CONFIG_PM
3804 .suspend = ixgbe_suspend,
3805 .resume = ixgbe_resume,
3806#endif
3807 .shutdown = ixgbe_shutdown,
3808 .err_handler = &ixgbe_err_handler
3809};
3810
3811/**
3812 * ixgbe_init_module - Driver Registration Routine
3813 *
3814 * ixgbe_init_module is the first routine called when the driver is
3815 * loaded. All it does is register with the PCI subsystem.
3816 **/
3817static int __init ixgbe_init_module(void)
3818{
3819 int ret;
3820 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3821 ixgbe_driver_string, ixgbe_driver_version);
3822
3823 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3824
bd0362dd
JC		 3825#ifdef CONFIG_DCA
3826 dca_register_notify(&dca_notifier);
3827
3828#endif
9a799d71
AK		 3829 ret = pci_register_driver(&ixgbe_driver);
3830 return ret;
3831}
3832module_init(ixgbe_init_module);
3833
3834/**
3835 * ixgbe_exit_module - Driver Exit Cleanup Routine
3836 *
3837 * ixgbe_exit_module is called just before the driver is removed
3838 * from memory.
3839 **/
3840static void __exit ixgbe_exit_module(void)
3841{
bd0362dd
JC		 3842#ifdef CONFIG_DCA
3843 dca_unregister_notify(&dca_notifier);
3844#endif
9a799d71
AK		 3845 pci_unregister_driver(&ixgbe_driver);
3846}
bd0362dd
JC		 3847
3848#ifdef CONFIG_DCA
3849static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
3850 void *p)
3851{
3852 int ret_val;
3853
3854 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
3855 __ixgbe_notify_dca);
3856
3857 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3858}
3859#endif /* CONFIG_DCA */
3860
9a799d71
AK		 3861module_exit(ixgbe_exit_module);
3862
3863/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree