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igb: add registers etc. printout code just before resetting adapters
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
92eb879f 55#define DRV_VERSION "2.0.62-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
312eb931
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112 board_82599 },
9a799d71
AK		 113
114 /* required last entry */
115 {0, }
116};
117MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
5dd2d332 119#ifdef CONFIG_IXGBE_DCA
bd0362dd 120static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 121 void *p);
bd0362dd
JC		 122static struct notifier_block dca_notifier = {
123 .notifier_call = ixgbe_notify_dca,
124 .next = NULL,
125 .priority = 0
126};
127#endif
128
1cdd1ec8
GR		 129#ifdef CONFIG_PCI_IOV
130static unsigned int max_vfs;
131module_param(max_vfs, uint, 0);
132MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133 "per physical function");
134#endif /* CONFIG_PCI_IOV */
135
9a799d71
AK		 136MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138MODULE_LICENSE("GPL");
139MODULE_VERSION(DRV_VERSION);
140
141#define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
1cdd1ec8
GR		 143static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144{
145 struct ixgbe_hw *hw = &adapter->hw;
146 u32 gcr;
147 u32 gpie;
148 u32 vmdctl;
149
150#ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter->pdev);
153#endif
154
155 /* turn off device IOV mode */
156 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163 /* set default pool back to 0 */
164 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168 /* take a breather then clean up driver data */
169 msleep(100);
170 if (adapter->vfinfo)
171 kfree(adapter->vfinfo);
172 adapter->vfinfo = NULL;
173
174 adapter->num_vfs = 0;
175 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176}
177
5eba3699
AV		 178static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
179{
180 u32 ctrl_ext;
181
182 /* Let firmware take over control of h/w */
183 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 185 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 186}
187
188static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
189{
190 u32 ctrl_ext;
191
192 /* Let firmware know the driver has taken over */
193 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
194 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 195 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 196}
9a799d71 197
e8e26350
PW		 198/*
199 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200 * @adapter: pointer to adapter struct
201 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202 * @queue: queue to map the corresponding interrupt to
203 * @msix_vector: the vector to map to the corresponding queue
204 *
205 */
206static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
207 u8 queue, u8 msix_vector)
9a799d71
AK		 208{
209 u32 ivar, index;
e8e26350
PW		 210 struct ixgbe_hw *hw = &adapter->hw;
211 switch (hw->mac.type) {
212 case ixgbe_mac_82598EB:
213 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
214 if (direction == -1)
215 direction = 0;
216 index = (((direction * 64) + queue) >> 2) & 0x1F;
217 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
218 ivar &= ~(0xFF << (8 * (queue & 0x3)));
219 ivar |= (msix_vector << (8 * (queue & 0x3)));
220 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
221 break;
222 case ixgbe_mac_82599EB:
223 if (direction == -1) {
224 /* other causes */
225 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
226 index = ((queue & 1) * 8);
227 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
228 ivar &= ~(0xFF << index);
229 ivar |= (msix_vector << index);
230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
231 break;
232 } else {
233 /* tx or rx causes */
234 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
235 index = ((16 * (queue & 1)) + (8 * direction));
236 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
237 ivar &= ~(0xFF << index);
238 ivar |= (msix_vector << index);
239 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
240 break;
241 }
242 default:
243 break;
244 }
9a799d71
AK		 245}
246
fe49f04a
AD		 247static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
248 u64 qmask)
249{
250 u32 mask;
251
252 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
253 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
255 } else {
256 mask = (qmask & 0xFFFFFFFF);
257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
258 mask = (qmask >> 32);
259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
260 }
261}
262
9a799d71 263static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 264 struct ixgbe_tx_buffer
265 *tx_buffer_info)
9a799d71 266{
e5a43549
AD		 267 if (tx_buffer_info->dma) {
268 if (tx_buffer_info->mapped_as_page)
1b507730 269 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 270 tx_buffer_info->dma,
271 tx_buffer_info->length,
1b507730 272 DMA_TO_DEVICE);
e5a43549 273 else
1b507730 274 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 275 tx_buffer_info->dma,
276 tx_buffer_info->length,
1b507730 277 DMA_TO_DEVICE);
e5a43549
AD		 278 tx_buffer_info->dma = 0;
279 }
9a799d71
AK		 280 if (tx_buffer_info->skb) {
281 dev_kfree_skb_any(tx_buffer_info->skb);
282 tx_buffer_info->skb = NULL;
283 }
44df32c5 284 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 285 /* tx_buffer_info must be completely set up in the transmit path */
286}
287
26f23d82
YZ		 288/**
289 * ixgbe_tx_is_paused - check if the tx ring is paused
290 * @adapter: the ixgbe adapter
291 * @tx_ring: the corresponding tx_ring
292 *
293 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294 * corresponding TC of this tx_ring when checking TFCS.
295 *
296 * Returns : true if paused
297 */
298static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
299 struct ixgbe_ring *tx_ring)
300{
26f23d82
YZ		 301 u32 txoff = IXGBE_TFCS_TXOFF;
302
303#ifdef CONFIG_IXGBE_DCB
304 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 305 int tc;
26f23d82
YZ		 306 int reg_idx = tx_ring->reg_idx;
307 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
308
6837e895
PW		 309 switch (adapter->hw.mac.type) {
310 case ixgbe_mac_82598EB:
26f23d82
YZ		 311 tc = reg_idx >> 2;
312 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 313 break;
314 case ixgbe_mac_82599EB:
26f23d82
YZ		 315 tc = 0;
316 txoff = IXGBE_TFCS_TXOFF;
317 if (dcb_i == 8) {
318 /* TC0, TC1 */
319 tc = reg_idx >> 5;
320 if (tc == 2) /* TC2, TC3 */
321 tc += (reg_idx - 64) >> 4;
322 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
323 tc += 1 + ((reg_idx - 96) >> 3);
324 } else if (dcb_i == 4) {
325 /* TC0, TC1 */
326 tc = reg_idx >> 6;
327 if (tc == 1) {
328 tc += (reg_idx - 64) >> 5;
329 if (tc == 2) /* TC2, TC3 */
330 tc += (reg_idx - 96) >> 4;
331 }
332 }
6837e895
PW		 333 break;
334 default:
335 tc = 0;
26f23d82
YZ		 336 }
337 txoff <<= tc;
338 }
339#endif
340 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
341}
342
9a799d71 343static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 344 struct ixgbe_ring *tx_ring,
345 unsigned int eop)
9a799d71 346{
e01c31a5 347 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 348
9a799d71 349 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 350 * check with the clearing of time_stamp and movement of eop */
9a799d71 351 adapter->detect_tx_hung = false;
44df32c5 352 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 353 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 354 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 355 /* detected Tx unit hang */
e01c31a5
JB		 356 union ixgbe_adv_tx_desc *tx_desc;
357 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 358 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 359 " Tx Queue <%d>\n"
360 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 361 " next_to_use <%x>\n"
362 " next_to_clean <%x>\n"
363 "tx_buffer_info[next_to_clean]\n"
364 " time_stamp <%lx>\n"
e01c31a5
JB		 365 " jiffies <%lx>\n",
366 tx_ring->queue_index,
44df32c5
AD		 367 IXGBE_READ_REG(hw, tx_ring->head),
368 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 369 tx_ring->next_to_use, eop,
370 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 371 return true;
372 }
373
374 return false;
375}
376
b4617240
PW		 377#define IXGBE_MAX_TXD_PWR 14
378#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 379
380/* Tx Descriptors needed, worst case */
381#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 384 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 385
e01c31a5
JB		 386static void ixgbe_tx_timeout(struct net_device *netdev);
387
9a799d71
AK		 388/**
389 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 390 * @q_vector: structure containing interrupt and ring information
e01c31a5 391 * @tx_ring: tx ring to clean
9a799d71 392 **/
fe49f04a 393static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 394 struct ixgbe_ring *tx_ring)
9a799d71 395{
fe49f04a 396 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 397 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 398 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
399 struct ixgbe_tx_buffer *tx_buffer_info;
400 unsigned int i, eop, count = 0;
e01c31a5 401 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 402
403 i = tx_ring->next_to_clean;
12207e49
PWJ		 404 eop = tx_ring->tx_buffer_info[i].next_to_watch;
405 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
406
407 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 408 (count < tx_ring->work_limit)) {
12207e49
PWJ		 409 bool cleaned = false;
410 for ( ; !cleaned; count++) {
411 struct sk_buff *skb;
9a799d71
AK		 412 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
413 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 414 cleaned = (i == eop);
e01c31a5 415 skb = tx_buffer_info->skb;
9a799d71 416
12207e49 417 if (cleaned && skb) {
e092be60 418 unsigned int segs, bytecount;
3d8fd385 419 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 420
421 /* gso_segs is currently only valid for tcp */
e092be60 422 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 423#ifdef IXGBE_FCOE
424 /* adjust for FCoE Sequence Offload */
425 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
426 && (skb->protocol == htons(ETH_P_FCOE)) &&
427 skb_is_gso(skb)) {
428 hlen = skb_transport_offset(skb) +
429 sizeof(struct fc_frame_header) +
430 sizeof(struct fcoe_crc_eof);
431 segs = DIV_ROUND_UP(skb->len - hlen,
432 skb_shinfo(skb)->gso_size);
433 }
434#endif /* IXGBE_FCOE */
e092be60 435 /* multiply data chunks by size of headers */
3d8fd385 436 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 437 total_packets += segs;
438 total_bytes += bytecount;
e092be60 439 }
e01c31a5 440
9a799d71 441 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 442 tx_buffer_info);
9a799d71 443
12207e49
PWJ		 444 tx_desc->wb.status = 0;
445
9a799d71
AK		 446 i++;
447 if (i == tx_ring->count)
448 i = 0;
e01c31a5 449 }
12207e49
PWJ		 450
451 eop = tx_ring->tx_buffer_info[i].next_to_watch;
452 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
453 }
454
9a799d71
AK		 455 tx_ring->next_to_clean = i;
456
e092be60 457#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 458 if (unlikely(count && netif_carrier_ok(netdev) &&
459 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 460 /* Make sure that anybody stopping the queue after this
461 * sees the new next_to_clean.
462 */
463 smp_mb();
30eba97a
AV		 464 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
465 !test_bit(__IXGBE_DOWN, &adapter->state)) {
466 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 467 ++tx_ring->restart_queue;
30eba97a 468 }
e092be60 469 }
9a799d71 470
e01c31a5
JB		 471 if (adapter->detect_tx_hung) {
472 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
473 /* schedule immediate reset if we believe we hung */
474 DPRINTK(PROBE, INFO,
475 "tx hang %d detected, resetting adapter\n",
476 adapter->tx_timeout_count + 1);
477 ixgbe_tx_timeout(adapter->netdev);
478 }
479 }
9a799d71 480
e01c31a5 481 /* re-arm the interrupt */
fe49f04a
AD		 482 if (count >= tx_ring->work_limit)
483 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 484
e01c31a5
JB		 485 tx_ring->total_bytes += total_bytes;
486 tx_ring->total_packets += total_packets;
e01c31a5 487 tx_ring->stats.packets += total_packets;
12207e49 488 tx_ring->stats.bytes += total_bytes;
9a1a69ad 489 return (count < tx_ring->work_limit);
9a799d71
AK		 490}
491
5dd2d332 492#ifdef CONFIG_IXGBE_DCA
bd0362dd 493static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 494 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 495{
496 u32 rxctrl;
497 int cpu = get_cpu();
4a0b9ca0 498 int q = rx_ring->reg_idx;
bd0362dd 499
3a581073 500 if (rx_ring->cpu != cpu) {
bd0362dd 501 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 502 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
503 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
504 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
505 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
506 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
507 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
508 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
509 }
bd0362dd
JC		 510 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
511 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
513 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 514 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 516 rx_ring->cpu = cpu;
bd0362dd
JC		 517 }
518 put_cpu();
519}
520
521static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 522 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 523{
524 u32 txctrl;
525 int cpu = get_cpu();
4a0b9ca0 526 int q = tx_ring->reg_idx;
ee5f784a 527 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 528
3a581073 529 if (tx_ring->cpu != cpu) {
e8e26350 530 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 531 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 532 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
533 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 534 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
535 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 536 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 537 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 538 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
539 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 540 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
541 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
542 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 543 }
3a581073 544 tx_ring->cpu = cpu;
bd0362dd
JC		 545 }
546 put_cpu();
547}
548
549static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
550{
551 int i;
552
553 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
554 return;
555
e35ec126
AD		 556 /* always use CB2 mode, difference is masked in the CB driver */
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
558
bd0362dd 559 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 560 adapter->tx_ring[i]->cpu = -1;
561 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 562 }
563 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 564 adapter->rx_ring[i]->cpu = -1;
565 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 566 }
567}
568
569static int __ixgbe_notify_dca(struct device *dev, void *data)
570{
571 struct net_device *netdev = dev_get_drvdata(dev);
572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573 unsigned long event = *(unsigned long *)data;
574
575 switch (event) {
576 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 577 /* if we're already enabled, don't do it again */
578 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
579 break;
652f093f 580 if (dca_add_requester(dev) == 0) {
96b0e0f6 581 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 582 ixgbe_setup_dca(adapter);
583 break;
584 }
585 /* Fall Through since DCA is disabled. */
586 case DCA_PROVIDER_REMOVE:
587 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
588 dca_remove_requester(dev);
589 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
591 }
592 break;
593 }
594
652f093f 595 return 0;
bd0362dd
JC		 596}
597
5dd2d332 598#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 599/**
600 * ixgbe_receive_skb - Send a completed packet up the stack
601 * @adapter: board private structure
602 * @skb: packet to send up
177db6ff
MC		 603 * @status: hardware indication of status of receive
604 * @rx_ring: rx descriptor ring (for a specific queue) to setup
605 * @rx_desc: rx descriptor
9a799d71 606 **/
78b6f4ce 607static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 608 struct sk_buff *skb, u8 status,
fdaff1ce 609 struct ixgbe_ring *ring,
177db6ff 610 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 611{
78b6f4ce
HX		 612 struct ixgbe_adapter *adapter = q_vector->adapter;
613 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 614 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
615 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 616
fdaff1ce 617 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 618 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 619 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 620 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 621 else
78b6f4ce 622 napi_gro_receive(napi, skb);
177db6ff 623 } else {
8a62babf 624 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 625 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
626 else
627 netif_rx(skb);
9a799d71
AK		 628 }
629}
630
e59bd25d
AV		 631/**
632 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633 * @adapter: address of board private structure
634 * @status_err: hardware indication of status of receive
635 * @skb: skb currently being received and modified
636 **/
9a799d71 637static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 638 union ixgbe_adv_rx_desc *rx_desc,
639 struct sk_buff *skb)
9a799d71 640{
8bae1b2b
DS		 641 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
642
9a799d71
AK		 643 skb->ip_summed = CHECKSUM_NONE;
644
712744be
JB		 645 /* Rx csum disabled */
646 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 647 return;
e59bd25d
AV		 648
649 /* if IP and error */
650 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
651 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 652 adapter->hw_csum_rx_error++;
653 return;
654 }
e59bd25d
AV		 655
656 if (!(status_err & IXGBE_RXD_STAT_L4CS))
657 return;
658
659 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 660 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
661
662 /*
663 * 82599 errata, UDP frames with a 0 checksum can be marked as
664 * checksum errors.
665 */
666 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
667 (adapter->hw.mac.type == ixgbe_mac_82599EB))
668 return;
669
e59bd25d
AV		 670 adapter->hw_csum_rx_error++;
671 return;
672 }
673
9a799d71 674 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 675 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 676}
677
e8e26350
PW		 678static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
679 struct ixgbe_ring *rx_ring, u32 val)
680{
681 /*
682 * Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
687 wmb();
688 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
689}
690
9a799d71
AK		 691/**
692 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693 * @adapter: address of board private structure
694 **/
695static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 696 struct ixgbe_ring *rx_ring,
697 int cleaned_count)
9a799d71 698{
9a799d71
AK		 699 struct pci_dev *pdev = adapter->pdev;
700 union ixgbe_adv_rx_desc *rx_desc;
3a581073 701 struct ixgbe_rx_buffer *bi;
9a799d71 702 unsigned int i;
9a799d71
AK		 703
704 i = rx_ring->next_to_use;
3a581073 705 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 706
707 while (cleaned_count--) {
708 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
709
762f4c57 710 if (!bi->page_dma &&
6e455b89 711 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 712 if (!bi->page) {
762f4c57
JB		 713 bi->page = alloc_page(GFP_ATOMIC);
714 if (!bi->page) {
715 adapter->alloc_rx_page_failed++;
716 goto no_buffers;
717 }
718 bi->page_offset = 0;
719 } else {
720 /* use a half page if we're re-using */
721 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 722 }
762f4c57 723
1b507730 724 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 725 bi->page_offset,
726 (PAGE_SIZE / 2),
1b507730 727 DMA_FROM_DEVICE);
9a799d71
AK		 728 }
729
3a581073 730 if (!bi->skb) {
5ecc3614 731 struct sk_buff *skb;
7ca3bc58
JB		 732 /* netdev_alloc_skb reserves 32 bytes up front!! */
733 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
734 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 735
736 if (!skb) {
737 adapter->alloc_rx_buff_failed++;
738 goto no_buffers;
739 }
740
7ca3bc58
JB		 741 /* advance the data pointer to the next cache line */
742 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
743 - skb->data));
744
3a581073 745 bi->skb = skb;
1b507730 746 bi->dma = dma_map_single(&pdev->dev, skb->data,
4f57ca6e 747 rx_ring->rx_buf_len,
1b507730 748 DMA_FROM_DEVICE);
9a799d71
AK		 749 }
750 /* Refresh the desc even if buffer_addrs didn't change because
751 * each write-back erases this info. */
6e455b89 752 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 753 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
754 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 755 } else {
3a581073 756 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 757 }
758
759 i++;
760 if (i == rx_ring->count)
761 i = 0;
3a581073 762 bi = &rx_ring->rx_buffer_info[i];
9a799d71 763 }
7c6e0a43 764
9a799d71
AK		 765no_buffers:
766 if (rx_ring->next_to_use != i) {
767 rx_ring->next_to_use = i;
768 if (i-- == 0)
769 i = (rx_ring->count - 1);
770
e8e26350 771 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 772 }
773}
774
7c6e0a43
JB		 775static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
776{
777 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
778}
779
780static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
781{
782 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
783}
784
f8212f97
AD		 785static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
786{
787 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
788 IXGBE_RXDADV_RSCCNT_MASK) >>
789 IXGBE_RXDADV_RSCCNT_SHIFT;
790}
791
792/**
793 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794 * @skb: pointer to the last skb in the rsc queue
94b982b2 795 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 796 *
797 * This function changes a queue full of hw rsc buffers into a completed
798 * packet. It uses the ->prev pointers to find the first packet and then
799 * turns it into the frag list owner.
800 **/
94b982b2
MC		 801static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
802 u64 *count)
f8212f97
AD		 803{
804 unsigned int frag_list_size = 0;
805
806 while (skb->prev) {
807 struct sk_buff *prev = skb->prev;
808 frag_list_size += skb->len;
809 skb->prev = NULL;
810 skb = prev;
94b982b2 811 *count += 1;
f8212f97
AD		 812 }
813
814 skb_shinfo(skb)->frag_list = skb->next;
815 skb->next = NULL;
816 skb->len += frag_list_size;
817 skb->data_len += frag_list_size;
818 skb->truesize += frag_list_size;
819 return skb;
820}
821
43634e82
MC		 822struct ixgbe_rsc_cb {
823 dma_addr_t dma;
824};
825
826#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
827
78b6f4ce 828static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 829 struct ixgbe_ring *rx_ring,
830 int *work_done, int work_to_do)
9a799d71 831{
78b6f4ce 832 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 833 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 834 struct pci_dev *pdev = adapter->pdev;
835 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
836 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
837 struct sk_buff *skb;
f8212f97 838 unsigned int i, rsc_count = 0;
7c6e0a43 839 u32 len, staterr;
177db6ff
MC		 840 u16 hdr_info;
841 bool cleaned = false;
9a799d71 842 int cleaned_count = 0;
d2f4fbe2 843 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 844#ifdef IXGBE_FCOE
845 int ddp_bytes = 0;
846#endif /* IXGBE_FCOE */
9a799d71
AK		 847
848 i = rx_ring->next_to_clean;
9a799d71
AK		 849 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
850 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
851 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 852
853 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 854 u32 upper_len = 0;
9a799d71
AK		 855 if (*work_done >= work_to_do)
856 break;
857 (*work_done)++;
858
3c945e5b 859 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 860 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 861 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
862 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 863 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 864 if (len > IXGBE_RX_HDR_SIZE)
865 len = IXGBE_RX_HDR_SIZE;
866 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 867 } else {
9a799d71 868 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 869 }
9a799d71
AK		 870
871 cleaned = true;
872 skb = rx_buffer_info->skb;
7ca3bc58 873 prefetch(skb->data);
9a799d71
AK		 874 rx_buffer_info->skb = NULL;
875
21fa4e66 876 if (rx_buffer_info->dma) {
43634e82
MC		 877 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
878 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
879 (!(skb->prev)))
880 /*
881 * When HWRSC is enabled, delay unmapping
882 * of the first packet. It carries the
883 * header information, HW may still
884 * access the header after the writeback.
885 * Only unmap it when EOP is reached
886 */
887 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
888 else
1b507730
NN		 889 dma_unmap_single(&pdev->dev,
890 rx_buffer_info->dma,
43634e82 891 rx_ring->rx_buf_len,
1b507730 892 DMA_FROM_DEVICE);
4f57ca6e 893 rx_buffer_info->dma = 0;
9a799d71
AK		 894 skb_put(skb, len);
895 }
896
897 if (upper_len) {
1b507730
NN		 898 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
899 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 900 rx_buffer_info->page_dma = 0;
901 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 902 rx_buffer_info->page,
903 rx_buffer_info->page_offset,
904 upper_len);
905
906 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
907 (page_count(rx_buffer_info->page) != 1))
908 rx_buffer_info->page = NULL;
909 else
910 get_page(rx_buffer_info->page);
9a799d71
AK		 911
912 skb->len += upper_len;
913 skb->data_len += upper_len;
914 skb->truesize += upper_len;
915 }
916
917 i++;
918 if (i == rx_ring->count)
919 i = 0;
9a799d71
AK		 920
921 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
922 prefetch(next_rxd);
9a799d71 923 cleaned_count++;
f8212f97 924
0c19d6af 925 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 926 rsc_count = ixgbe_get_rsc_count(rx_desc);
927
928 if (rsc_count) {
929 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
930 IXGBE_RXDADV_NEXTP_SHIFT;
931 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 932 } else {
933 next_buffer = &rx_ring->rx_buffer_info[i];
934 }
935
9a799d71 936 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 937 if (skb->prev)
94b982b2
MC		 938 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
939 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
fd3686a8 940 if (IXGBE_RSC_CB(skb)->dma) {
1b507730
NN		 941 dma_unmap_single(&pdev->dev,
942 IXGBE_RSC_CB(skb)->dma,
43634e82 943 rx_ring->rx_buf_len,
1b507730 944 DMA_FROM_DEVICE);
fd3686a8
MC		 945 IXGBE_RSC_CB(skb)->dma = 0;
946 }
94b982b2
MC		 947 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
948 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
949 else
950 rx_ring->rsc_count++;
951 rx_ring->rsc_flush++;
952 }
9a799d71
AK		 953 rx_ring->stats.packets++;
954 rx_ring->stats.bytes += skb->len;
955 } else {
6e455b89 956 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 957 rx_buffer_info->skb = next_buffer->skb;
958 rx_buffer_info->dma = next_buffer->dma;
959 next_buffer->skb = skb;
960 next_buffer->dma = 0;
961 } else {
962 skb->next = next_buffer->skb;
963 skb->next->prev = skb;
964 }
7ca3bc58 965 rx_ring->non_eop_descs++;
9a799d71
AK		 966 goto next_desc;
967 }
968
969 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
970 dev_kfree_skb_irq(skb);
971 goto next_desc;
972 }
973
8bae1b2b 974 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 975
976 /* probably a little skewed due to removing CRC */
977 total_rx_bytes += skb->len;
978 total_rx_packets++;
979
74ce8dd2 980 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 981#ifdef IXGBE_FCOE
982 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 983 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
984 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
985 if (!ddp_bytes)
332d4a7d 986 goto next_desc;
3d8fd385 987 }
332d4a7d 988#endif /* IXGBE_FCOE */
fdaff1ce 989 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 990
991next_desc:
992 rx_desc->wb.upper.status_error = 0;
993
994 /* return some buffers to hardware, one at a time is too slow */
995 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
996 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
997 cleaned_count = 0;
998 }
999
1000 /* use prefetched values */
1001 rx_desc = next_rxd;
f8212f97 1002 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1003
1004 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1005 }
1006
9a799d71
AK		 1007 rx_ring->next_to_clean = i;
1008 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1009
1010 if (cleaned_count)
1011 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1012
3d8fd385
YZ		 1013#ifdef IXGBE_FCOE
1014 /* include DDPed FCoE data */
1015 if (ddp_bytes > 0) {
1016 unsigned int mss;
1017
1018 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1019 sizeof(struct fc_frame_header) -
1020 sizeof(struct fcoe_crc_eof);
1021 if (mss > 512)
1022 mss &= ~511;
1023 total_rx_bytes += ddp_bytes;
1024 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1025 }
1026#endif /* IXGBE_FCOE */
1027
f494e8fa
AV		 1028 rx_ring->total_packets += total_rx_packets;
1029 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1030 netdev->stats.rx_bytes += total_rx_bytes;
1031 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1032
9a799d71
AK		 1033 return cleaned;
1034}
1035
021230d4 1036static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1037/**
1038 * ixgbe_configure_msix - Configure MSI-X hardware
1039 * @adapter: board private structure
1040 *
1041 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1042 * interrupts.
1043 **/
1044static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1045{
021230d4
AV		 1046 struct ixgbe_q_vector *q_vector;
1047 int i, j, q_vectors, v_idx, r_idx;
1048 u32 mask;
9a799d71 1049
021230d4 1050 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1051
4df10466
JB		 1052 /*
1053 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1054 * corresponding register.
1055 */
1056 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1057 q_vector = adapter->q_vector[v_idx];
984b3f57 1058 /* XXX for_each_set_bit(...) */
021230d4 1059 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1060 adapter->num_rx_queues);
021230d4
AV		 1061
1062 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1063 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1064 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1065 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1066 adapter->num_rx_queues,
1067 r_idx + 1);
021230d4
AV		 1068 }
1069 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1070 adapter->num_tx_queues);
021230d4
AV		 1071
1072 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1073 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1074 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1075 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1076 adapter->num_tx_queues,
1077 r_idx + 1);
021230d4
AV		 1078 }
1079
021230d4 1080 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1081 /* tx only */
1082 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1083 else if (q_vector->rxr_count)
f7554a2b
NS		 1084 /* rx or mixed */
1085 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1086
fe49f04a 1087 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1088 }
1089
e8e26350
PW		 1090 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1091 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1092 v_idx);
1093 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1094 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1095 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1096
41fb9248 1097 /* set up to autoclear timer, and the vectors */
021230d4 1098 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1099 if (adapter->num_vfs)
1100 mask &= ~(IXGBE_EIMS_OTHER |
1101 IXGBE_EIMS_MAILBOX |
1102 IXGBE_EIMS_LSC);
1103 else
1104 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1106}
1107
f494e8fa
AV		 1108enum latency_range {
1109 lowest_latency = 0,
1110 low_latency = 1,
1111 bulk_latency = 2,
1112 latency_invalid = 255
1113};
1114
1115/**
1116 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1117 * @adapter: pointer to adapter
1118 * @eitr: eitr setting (ints per sec) to give last timeslice
1119 * @itr_setting: current throttle rate in ints/second
1120 * @packets: the number of packets during this measurement interval
1121 * @bytes: the number of bytes during this measurement interval
1122 *
1123 * Stores a new ITR value based on packets and byte
1124 * counts during the last interrupt. The advantage of per interrupt
1125 * computation is faster updates and more accurate ITR for the current
1126 * traffic pattern. Constants in this function were computed
1127 * based on theoretical maximum wire speed and thresholds were set based
1128 * on testing data as well as attempting to minimize response time
1129 * while increasing bulk throughput.
1130 * this functionality is controlled by the InterruptThrottleRate module
1131 * parameter (see ixgbe_param.c)
1132 **/
1133static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1134 u32 eitr, u8 itr_setting,
1135 int packets, int bytes)
f494e8fa
AV		 1136{
1137 unsigned int retval = itr_setting;
1138 u32 timepassed_us;
1139 u64 bytes_perint;
1140
1141 if (packets == 0)
1142 goto update_itr_done;
1143
1144
1145 /* simple throttlerate management
1146 * 0-20MB/s lowest (100000 ints/s)
1147 * 20-100MB/s low (20000 ints/s)
1148 * 100-1249MB/s bulk (8000 ints/s)
1149 */
1150 /* what was last interrupt timeslice? */
1151 timepassed_us = 1000000/eitr;
1152 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1153
1154 switch (itr_setting) {
1155 case lowest_latency:
1156 if (bytes_perint > adapter->eitr_low)
1157 retval = low_latency;
1158 break;
1159 case low_latency:
1160 if (bytes_perint > adapter->eitr_high)
1161 retval = bulk_latency;
1162 else if (bytes_perint <= adapter->eitr_low)
1163 retval = lowest_latency;
1164 break;
1165 case bulk_latency:
1166 if (bytes_perint <= adapter->eitr_high)
1167 retval = low_latency;
1168 break;
1169 }
1170
1171update_itr_done:
1172 return retval;
1173}
1174
509ee935
JB		 1175/**
1176 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1177 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1178 *
1179 * This function is made to be called by ethtool and by the driver
1180 * when it needs to update EITR registers at runtime. Hardware
1181 * specific quirks/differences are taken care of here.
1182 */
fe49f04a 1183void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1184{
fe49f04a 1185 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1186 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1187 int v_idx = q_vector->v_idx;
1188 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1189
509ee935
JB		 1190 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1191 /* must write high and low 16 bits to reset counter */
1192 itr_reg |= (itr_reg << 16);
1193 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1194 /*
1195 * 82599 can support a value of zero, so allow it for
1196 * max interrupt rate, but there is an errata where it can
1197 * not be zero with RSC
1198 */
1199 if (itr_reg == 8 &&
1200 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1201 itr_reg = 0;
1202
509ee935
JB		 1203 /*
1204 * set the WDIS bit to not clear the timer bits and cause an
1205 * immediate assertion of the interrupt
1206 */
1207 itr_reg |= IXGBE_EITR_CNT_WDIS;
1208 }
1209 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1210}
1211
f494e8fa
AV		 1212static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1213{
1214 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1215 u32 new_itr;
1216 u8 current_itr, ret_itr;
fe49f04a 1217 int i, r_idx;
f494e8fa
AV		 1218 struct ixgbe_ring *rx_ring, *tx_ring;
1219
1220 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1221 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1222 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1223 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1224 q_vector->tx_itr,
1225 tx_ring->total_packets,
1226 tx_ring->total_bytes);
f494e8fa
AV		 1227 /* if the result for this queue would decrease interrupt
1228 * rate for this vector then use that result */
30efa5a3 1229 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1230 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1231 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1232 r_idx + 1);
f494e8fa
AV		 1233 }
1234
1235 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1236 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1237 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1238 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1239 q_vector->rx_itr,
1240 rx_ring->total_packets,
1241 rx_ring->total_bytes);
f494e8fa
AV		 1242 /* if the result for this queue would decrease interrupt
1243 * rate for this vector then use that result */
30efa5a3 1244 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1245 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1246 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1247 r_idx + 1);
f494e8fa
AV		 1248 }
1249
30efa5a3 1250 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1251
1252 switch (current_itr) {
1253 /* counts and packets in update_itr are dependent on these numbers */
1254 case lowest_latency:
1255 new_itr = 100000;
1256 break;
1257 case low_latency:
1258 new_itr = 20000; /* aka hwitr = ~200 */
1259 break;
1260 case bulk_latency:
1261 default:
1262 new_itr = 8000;
1263 break;
1264 }
1265
1266 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1267 /* do an exponential smoothing */
1268 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1269
1270 /* save the algorithm value here, not the smoothed one */
1271 q_vector->eitr = new_itr;
fe49f04a
AD		 1272
1273 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1274 }
1275
1276 return;
1277}
1278
0befdb3e
JB		 1279static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1280{
1281 struct ixgbe_hw *hw = &adapter->hw;
1282
1283 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1284 (eicr & IXGBE_EICR_GPI_SDP1)) {
1285 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1286 /* write to clear the interrupt */
1287 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1288 }
1289}
cf8280ee 1290
e8e26350
PW		 1291static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1292{
1293 struct ixgbe_hw *hw = &adapter->hw;
1294
1295 if (eicr & IXGBE_EICR_GPI_SDP1) {
1296 /* Clear the interrupt */
1297 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1298 schedule_work(&adapter->multispeed_fiber_task);
1299 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1300 /* Clear the interrupt */
1301 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1302 schedule_work(&adapter->sfp_config_module_task);
1303 } else {
1304 /* Interrupt isn't for us... */
1305 return;
1306 }
1307}
1308
cf8280ee
JB		 1309static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1310{
1311 struct ixgbe_hw *hw = &adapter->hw;
1312
1313 adapter->lsc_int++;
1314 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1315 adapter->link_check_timeout = jiffies;
1316 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1317 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1318 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1319 schedule_work(&adapter->watchdog_task);
1320 }
1321}
1322
9a799d71
AK		 1323static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1324{
1325 struct net_device *netdev = data;
1326 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1327 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1328 u32 eicr;
1329
1330 /*
1331 * Workaround for Silicon errata. Use clear-by-write instead
1332 * of clear-by-read. Reading with EICS will return the
1333 * interrupt causes without clearing, which later be done
1334 * with the write to EICR.
1335 */
1336 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1337 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1338
cf8280ee
JB		 1339 if (eicr & IXGBE_EICR_LSC)
1340 ixgbe_check_lsc(adapter);
d4f80882 1341
1cdd1ec8
GR		 1342 if (eicr & IXGBE_EICR_MAILBOX)
1343 ixgbe_msg_task(adapter);
1344
e8e26350
PW		 1345 if (hw->mac.type == ixgbe_mac_82598EB)
1346 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1347
c4cf55e5 1348 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1349 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1350
1351 /* Handle Flow Director Full threshold interrupt */
1352 if (eicr & IXGBE_EICR_FLOW_DIR) {
1353 int i;
1354 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1355 /* Disable transmits before FDIR Re-initialization */
1356 netif_tx_stop_all_queues(netdev);
1357 for (i = 0; i < adapter->num_tx_queues; i++) {
1358 struct ixgbe_ring *tx_ring =
4a0b9ca0 1359 adapter->tx_ring[i];
c4cf55e5
PWJ		 1360 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1361 &tx_ring->reinit_state))
1362 schedule_work(&adapter->fdir_reinit_task);
1363 }
1364 }
1365 }
d4f80882
AV		 1366 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1367 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1368
1369 return IRQ_HANDLED;
1370}
1371
fe49f04a
AD		 1372static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1373 u64 qmask)
1374{
1375 u32 mask;
1376
1377 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1378 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1379 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1380 } else {
1381 mask = (qmask & 0xFFFFFFFF);
1382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1383 mask = (qmask >> 32);
1384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1385 }
1386 /* skip the flush */
1387}
1388
1389static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1390 u64 qmask)
1391{
1392 u32 mask;
1393
1394 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1395 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1397 } else {
1398 mask = (qmask & 0xFFFFFFFF);
1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1400 mask = (qmask >> 32);
1401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1402 }
1403 /* skip the flush */
1404}
1405
9a799d71
AK		 1406static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1407{
021230d4
AV		 1408 struct ixgbe_q_vector *q_vector = data;
1409 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1410 struct ixgbe_ring *tx_ring;
021230d4
AV		 1411 int i, r_idx;
1412
1413 if (!q_vector->txr_count)
1414 return IRQ_HANDLED;
1415
1416 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1417 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1418 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1419 tx_ring->total_bytes = 0;
1420 tx_ring->total_packets = 0;
021230d4 1421 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1422 r_idx + 1);
021230d4 1423 }
9a799d71 1424
9b471446 1425 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1426 napi_schedule(&q_vector->napi);
1427
9a799d71
AK		 1428 return IRQ_HANDLED;
1429}
1430
021230d4
AV		 1431/**
1432 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1433 * @irq: unused
1434 * @data: pointer to our q_vector struct for this interrupt vector
1435 **/
9a799d71
AK		 1436static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1437{
021230d4
AV		 1438 struct ixgbe_q_vector *q_vector = data;
1439 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1440 struct ixgbe_ring *rx_ring;
021230d4 1441 int r_idx;
30efa5a3 1442 int i;
021230d4
AV		 1443
1444 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1445 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1446 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1447 rx_ring->total_bytes = 0;
1448 rx_ring->total_packets = 0;
1449 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1450 r_idx + 1);
1451 }
1452
021230d4
AV		 1453 if (!q_vector->rxr_count)
1454 return IRQ_HANDLED;
1455
021230d4 1456 /* disable interrupts on this vector only */
9b471446 1457 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1458 napi_schedule(&q_vector->napi);
021230d4
AV		 1459
1460 return IRQ_HANDLED;
1461}
1462
1463static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1464{
91281fd3
AD		 1465 struct ixgbe_q_vector *q_vector = data;
1466 struct ixgbe_adapter *adapter = q_vector->adapter;
1467 struct ixgbe_ring *ring;
1468 int r_idx;
1469 int i;
1470
1471 if (!q_vector->txr_count && !q_vector->rxr_count)
1472 return IRQ_HANDLED;
1473
1474 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1475 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1476 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1477 ring->total_bytes = 0;
1478 ring->total_packets = 0;
1479 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1480 r_idx + 1);
1481 }
1482
1483 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1484 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1485 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1486 ring->total_bytes = 0;
1487 ring->total_packets = 0;
1488 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1489 r_idx + 1);
1490 }
1491
9b471446 1492 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1493 napi_schedule(&q_vector->napi);
9a799d71 1494
9a799d71
AK		 1495 return IRQ_HANDLED;
1496}
1497
021230d4
AV		 1498/**
1499 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1500 * @napi: napi struct with our devices info in it
1501 * @budget: amount of work driver is allowed to do this pass, in packets
1502 *
f0848276
JB		 1503 * This function is optimized for cleaning one queue only on a single
1504 * q_vector!!!
021230d4 1505 **/
9a799d71
AK		 1506static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1507{
021230d4 1508 struct ixgbe_q_vector *q_vector =
b4617240 1509 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1510 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1511 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1512 int work_done = 0;
021230d4 1513 long r_idx;
9a799d71 1514
021230d4 1515 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1516 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1517#ifdef CONFIG_IXGBE_DCA
bd0362dd 1518 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1519 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1520#endif
9a799d71 1521
78b6f4ce 1522 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1523
021230d4
AV		 1524 /* If all Rx work done, exit the polling mode */
1525 if (work_done < budget) {
288379f0 1526 napi_complete(napi);
f7554a2b 1527 if (adapter->rx_itr_setting & 1)
f494e8fa 1528 ixgbe_set_itr_msix(q_vector);
9a799d71 1529 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1530 ixgbe_irq_enable_queues(adapter,
1531 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1532 }
1533
1534 return work_done;
1535}
1536
f0848276 1537/**
91281fd3 1538 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1539 * @napi: napi struct with our devices info in it
1540 * @budget: amount of work driver is allowed to do this pass, in packets
1541 *
1542 * This function will clean more than one rx queue associated with a
1543 * q_vector.
1544 **/
91281fd3 1545static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1546{
1547 struct ixgbe_q_vector *q_vector =
1548 container_of(napi, struct ixgbe_q_vector, napi);
1549 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1550 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1551 int work_done = 0, i;
1552 long r_idx;
91281fd3
AD		 1553 bool tx_clean_complete = true;
1554
1555 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1556 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1557 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1558#ifdef CONFIG_IXGBE_DCA
1559 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1560 ixgbe_update_tx_dca(adapter, ring);
1561#endif
1562 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1563 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1564 r_idx + 1);
1565 }
f0848276
JB		 1566
1567 /* attempt to distribute budget to each queue fairly, but don't allow
1568 * the budget to go below 1 because we'll exit polling */
1569 budget /= (q_vector->rxr_count ?: 1);
1570 budget = max(budget, 1);
1571 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1572 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1573 ring = adapter->rx_ring[r_idx];
5dd2d332 1574#ifdef CONFIG_IXGBE_DCA
f0848276 1575 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1576 ixgbe_update_rx_dca(adapter, ring);
f0848276 1577#endif
91281fd3 1578 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1579 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1580 r_idx + 1);
1581 }
1582
1583 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1584 ring = adapter->rx_ring[r_idx];
f0848276 1585 /* If all Rx work done, exit the polling mode */
7f821875 1586 if (work_done < budget) {
288379f0 1587 napi_complete(napi);
f7554a2b 1588 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1589 ixgbe_set_itr_msix(q_vector);
1590 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1591 ixgbe_irq_enable_queues(adapter,
1592 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1593 return 0;
1594 }
1595
1596 return work_done;
1597}
91281fd3
AD		 1598
1599/**
1600 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1601 * @napi: napi struct with our devices info in it
1602 * @budget: amount of work driver is allowed to do this pass, in packets
1603 *
1604 * This function is optimized for cleaning one queue only on a single
1605 * q_vector!!!
1606 **/
1607static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1608{
1609 struct ixgbe_q_vector *q_vector =
1610 container_of(napi, struct ixgbe_q_vector, napi);
1611 struct ixgbe_adapter *adapter = q_vector->adapter;
1612 struct ixgbe_ring *tx_ring = NULL;
1613 int work_done = 0;
1614 long r_idx;
1615
1616 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1617 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1618#ifdef CONFIG_IXGBE_DCA
1619 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1620 ixgbe_update_tx_dca(adapter, tx_ring);
1621#endif
1622
1623 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1624 work_done = budget;
1625
f7554a2b 1626 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1627 if (work_done < budget) {
1628 napi_complete(napi);
f7554a2b 1629 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1630 ixgbe_set_itr_msix(q_vector);
1631 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1632 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1633 }
1634
1635 return work_done;
1636}
1637
021230d4 1638static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1639 int r_idx)
021230d4 1640{
7a921c93
AD		 1641 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1642
1643 set_bit(r_idx, q_vector->rxr_idx);
1644 q_vector->rxr_count++;
021230d4
AV		 1645}
1646
1647static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1648 int t_idx)
021230d4 1649{
7a921c93
AD		 1650 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1651
1652 set_bit(t_idx, q_vector->txr_idx);
1653 q_vector->txr_count++;
021230d4
AV		 1654}
1655
9a799d71 1656/**
021230d4
AV		 1657 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1658 * @adapter: board private structure to initialize
1659 * @vectors: allotted vector count for descriptor rings
9a799d71 1660 *
021230d4
AV		 1661 * This function maps descriptor rings to the queue-specific vectors
1662 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1663 * one vector per ring/queue, but on a constrained vector budget, we
1664 * group the rings as "efficiently" as possible. You would add new
1665 * mapping configurations in here.
9a799d71 1666 **/
021230d4 1667static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1668 int vectors)
021230d4
AV		 1669{
1670 int v_start = 0;
1671 int rxr_idx = 0, txr_idx = 0;
1672 int rxr_remaining = adapter->num_rx_queues;
1673 int txr_remaining = adapter->num_tx_queues;
1674 int i, j;
1675 int rqpv, tqpv;
1676 int err = 0;
1677
1678 /* No mapping required if MSI-X is disabled. */
1679 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1680 goto out;
9a799d71 1681
021230d4
AV		 1682 /*
1683 * The ideal configuration...
1684 * We have enough vectors to map one per queue.
1685 */
1686 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1687 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1688 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1689
021230d4
AV		 1690 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1691 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1692
9a799d71 1693 goto out;
021230d4 1694 }
9a799d71 1695
021230d4
AV		 1696 /*
1697 * If we don't have enough vectors for a 1-to-1
1698 * mapping, we'll have to group them so there are
1699 * multiple queues per vector.
1700 */
1701 /* Re-adjusting *qpv takes care of the remainder. */
1702 for (i = v_start; i < vectors; i++) {
1703 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1704 for (j = 0; j < rqpv; j++) {
1705 map_vector_to_rxq(adapter, i, rxr_idx);
1706 rxr_idx++;
1707 rxr_remaining--;
1708 }
1709 }
1710 for (i = v_start; i < vectors; i++) {
1711 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1712 for (j = 0; j < tqpv; j++) {
1713 map_vector_to_txq(adapter, i, txr_idx);
1714 txr_idx++;
1715 txr_remaining--;
9a799d71 1716 }
9a799d71
AK		 1717 }
1718
021230d4
AV		 1719out:
1720 return err;
1721}
1722
1723/**
1724 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1725 * @adapter: board private structure
1726 *
1727 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1728 * interrupts from the kernel.
1729 **/
1730static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1731{
1732 struct net_device *netdev = adapter->netdev;
1733 irqreturn_t (*handler)(int, void *);
1734 int i, vector, q_vectors, err;
cb13fc20 1735 int ri=0, ti=0;
021230d4
AV		 1736
1737 /* Decrement for Other and TCP Timer vectors */
1738 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1739
1740 /* Map the Tx/Rx rings to the vectors we were allotted. */
1741 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1742 if (err)
1743 goto out;
1744
1745#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1746 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1747 &ixgbe_msix_clean_many)
021230d4 1748 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1749 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1750
1751 if(handler == &ixgbe_msix_clean_rx) {
1752 sprintf(adapter->name[vector], "%s-%s-%d",
1753 netdev->name, "rx", ri++);
1754 }
1755 else if(handler == &ixgbe_msix_clean_tx) {
1756 sprintf(adapter->name[vector], "%s-%s-%d",
1757 netdev->name, "tx", ti++);
1758 }
1759 else
1760 sprintf(adapter->name[vector], "%s-%s-%d",
1761 netdev->name, "TxRx", vector);
1762
021230d4 1763 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1764 handler, 0, adapter->name[vector],
7a921c93 1765 adapter->q_vector[vector]);
9a799d71
AK		 1766 if (err) {
1767 DPRINTK(PROBE, ERR,
b4617240
PW		 1768 "request_irq failed for MSIX interrupt "
1769 "Error: %d\n", err);
021230d4 1770 goto free_queue_irqs;
9a799d71 1771 }
9a799d71
AK		 1772 }
1773
021230d4
AV		 1774 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1775 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1776 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1777 if (err) {
1778 DPRINTK(PROBE, ERR,
1779 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1780 goto free_queue_irqs;
9a799d71
AK		 1781 }
1782
9a799d71
AK		 1783 return 0;
1784
021230d4
AV		 1785free_queue_irqs:
1786 for (i = vector - 1; i >= 0; i--)
1787 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1788 adapter->q_vector[i]);
021230d4
AV		 1789 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1790 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1791 kfree(adapter->msix_entries);
1792 adapter->msix_entries = NULL;
021230d4 1793out:
9a799d71
AK		 1794 return err;
1795}
1796
f494e8fa
AV		 1797static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1798{
7a921c93 1799 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1800 u8 current_itr;
1801 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1802 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1803 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1804
30efa5a3 1805 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1806 q_vector->tx_itr,
1807 tx_ring->total_packets,
1808 tx_ring->total_bytes);
30efa5a3 1809 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1810 q_vector->rx_itr,
1811 rx_ring->total_packets,
1812 rx_ring->total_bytes);
f494e8fa 1813
30efa5a3 1814 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1815
1816 switch (current_itr) {
1817 /* counts and packets in update_itr are dependent on these numbers */
1818 case lowest_latency:
1819 new_itr = 100000;
1820 break;
1821 case low_latency:
1822 new_itr = 20000; /* aka hwitr = ~200 */
1823 break;
1824 case bulk_latency:
1825 new_itr = 8000;
1826 break;
1827 default:
1828 break;
1829 }
1830
1831 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1832 /* do an exponential smoothing */
1833 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1834
1835 /* save the algorithm value here, not the smoothed one */
1836 q_vector->eitr = new_itr;
fe49f04a
AD		 1837
1838 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1839 }
1840
1841 return;
1842}
1843
79aefa45
AD		 1844/**
1845 * ixgbe_irq_enable - Enable default interrupt generation settings
1846 * @adapter: board private structure
1847 **/
1848static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1849{
1850 u32 mask;
835462fc
NS		 1851
1852 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1853 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1854 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1855 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1856 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1857 mask |= IXGBE_EIMS_GPI_SDP1;
1858 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1859 if (adapter->num_vfs)
1860 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1861 }
c4cf55e5
PWJ		 1862 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1863 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1864 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1865
79aefa45 1866 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1867 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1868 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1869
1870 if (adapter->num_vfs > 32) {
1871 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1872 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1873 }
79aefa45 1874}
021230d4 1875
9a799d71 1876/**
021230d4 1877 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1878 * @irq: interrupt number
1879 * @data: pointer to a network interface device structure
9a799d71
AK		 1880 **/
1881static irqreturn_t ixgbe_intr(int irq, void *data)
1882{
1883 struct net_device *netdev = data;
1884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1885 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1886 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1887 u32 eicr;
1888
54037505
DS		 1889 /*
1890 * Workaround for silicon errata. Mask the interrupts
1891 * before the read of EICR.
1892 */
1893 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1894
021230d4
AV		 1895 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1896 * therefore no explict interrupt disable is necessary */
1897 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1898 if (!eicr) {
1899 /* shared interrupt alert!
1900 * make sure interrupts are enabled because the read will
1901 * have disabled interrupts due to EIAM */
1902 ixgbe_irq_enable(adapter);
9a799d71 1903 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1904 }
9a799d71 1905
cf8280ee
JB		 1906 if (eicr & IXGBE_EICR_LSC)
1907 ixgbe_check_lsc(adapter);
021230d4 1908
e8e26350
PW		 1909 if (hw->mac.type == ixgbe_mac_82599EB)
1910 ixgbe_check_sfp_event(adapter, eicr);
1911
0befdb3e
JB		 1912 ixgbe_check_fan_failure(adapter, eicr);
1913
7a921c93 1914 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1915 adapter->tx_ring[0]->total_packets = 0;
1916 adapter->tx_ring[0]->total_bytes = 0;
1917 adapter->rx_ring[0]->total_packets = 0;
1918 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1919 /* would disable interrupts here but EIAM disabled it */
7a921c93 1920 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1921 }
1922
1923 return IRQ_HANDLED;
1924}
1925
021230d4
AV		 1926static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1927{
1928 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1929
1930 for (i = 0; i < q_vectors; i++) {
7a921c93 1931 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1932 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1933 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1934 q_vector->rxr_count = 0;
1935 q_vector->txr_count = 0;
1936 }
1937}
1938
9a799d71
AK		 1939/**
1940 * ixgbe_request_irq - initialize interrupts
1941 * @adapter: board private structure
1942 *
1943 * Attempts to configure interrupts using the best available
1944 * capabilities of the hardware and kernel.
1945 **/
021230d4 1946static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1947{
1948 struct net_device *netdev = adapter->netdev;
021230d4 1949 int err;
9a799d71 1950
021230d4
AV		 1951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1952 err = ixgbe_request_msix_irqs(adapter);
1953 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1954 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1955 netdev->name, netdev);
021230d4 1956 } else {
a0607fd3 1957 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1958 netdev->name, netdev);
9a799d71
AK		 1959 }
1960
9a799d71
AK		 1961 if (err)
1962 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1963
9a799d71
AK		 1964 return err;
1965}
1966
1967static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1968{
1969 struct net_device *netdev = adapter->netdev;
1970
1971 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1972 int i, q_vectors;
9a799d71 1973
021230d4
AV		 1974 q_vectors = adapter->num_msix_vectors;
1975
1976 i = q_vectors - 1;
9a799d71 1977 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1978
021230d4
AV		 1979 i--;
1980 for (; i >= 0; i--) {
1981 free_irq(adapter->msix_entries[i].vector,
7a921c93 1982 adapter->q_vector[i]);
021230d4
AV		 1983 }
1984
1985 ixgbe_reset_q_vectors(adapter);
1986 } else {
1987 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1988 }
1989}
1990
22d5a71b
JB		 1991/**
1992 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1993 * @adapter: board private structure
1994 **/
1995static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1996{
835462fc
NS		 1997 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1999 } else {
2000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2001 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2003 if (adapter->num_vfs > 32)
2004 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2005 }
2006 IXGBE_WRITE_FLUSH(&adapter->hw);
2007 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2008 int i;
2009 for (i = 0; i < adapter->num_msix_vectors; i++)
2010 synchronize_irq(adapter->msix_entries[i].vector);
2011 } else {
2012 synchronize_irq(adapter->pdev->irq);
2013 }
2014}
2015
9a799d71
AK		 2016/**
2017 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2018 *
2019 **/
2020static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2021{
9a799d71
AK		 2022 struct ixgbe_hw *hw = &adapter->hw;
2023
021230d4 2024 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2025 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2026
e8e26350
PW		 2027 ixgbe_set_ivar(adapter, 0, 0, 0);
2028 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2029
2030 map_vector_to_rxq(adapter, 0, 0);
2031 map_vector_to_txq(adapter, 0, 0);
2032
2033 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2034}
2035
2036/**
3a581073 2037 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2038 * @adapter: board private structure
2039 *
2040 * Configure the Tx unit of the MAC after a reset.
2041 **/
2042static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2043{
12207e49 2044 u64 tdba;
9a799d71 2045 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2046 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2047
2048 /* Setup the HW Tx Head and Tail descriptor pointers */
2049 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2050 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2051 j = ring->reg_idx;
2052 tdba = ring->dma;
2053 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2054 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2055 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2056 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2057 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2058 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2059 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2060 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2061 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2062 /*
2063 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2064 * bookkeeping if things aren't delivered in order.
2065 */
84f62d4b
PWJ		 2066 switch (hw->mac.type) {
2067 case ixgbe_mac_82598EB:
2068 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2069 break;
2070 case ixgbe_mac_82599EB:
2071 default:
2072 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2073 break;
2074 }
021230d4 2075 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2076 switch (hw->mac.type) {
2077 case ixgbe_mac_82598EB:
2078 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2079 break;
2080 case ixgbe_mac_82599EB:
2081 default:
2082 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2083 break;
2084 }
9a799d71 2085 }
ee5f784a 2086
e8e26350 2087 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2088 u32 rttdcs;
1cdd1ec8 2089 u32 mask;
ee5f784a
DS		 2090
2091 /* disable the arbiter while setting MTQC */
2092 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2093 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2094 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2095
1cdd1ec8
GR		 2096 /* set transmit pool layout */
2097 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2098 switch (adapter->flags & mask) {
2099
2100 case (IXGBE_FLAG_SRIOV_ENABLED):
2101 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2102 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2103 break;
2104
2105 case (IXGBE_FLAG_DCB_ENABLED):
2106 /* We enable 8 traffic classes, DCB only */
2107 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2108 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2109 break;
2110
2111 default:
ee5f784a 2112 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2113 break;
2114 }
ee5f784a
DS		 2115
2116 /* re-eable the arbiter */
2117 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2118 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2119 }
9a799d71
AK		 2120}
2121
e8e26350 2122#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2123
a6616b42
YZ		 2124static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2125 struct ixgbe_ring *rx_ring)
cc41ac7c 2126{
cc41ac7c 2127 u32 srrctl;
a6616b42 2128 int index;
0cefafad 2129 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2130
a6616b42
YZ		 2131 index = rx_ring->reg_idx;
2132 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2133 unsigned long mask;
0cefafad 2134 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2135 index = index & mask;
cc41ac7c 2136 }
cc41ac7c
JB		 2137 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2138
2139 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2140 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2141
afafd5b0
AD		 2142 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2143 IXGBE_SRRCTL_BSIZEHDR_MASK;
2144
6e455b89 2145 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2146#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2147 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2148#else
2149 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2150#endif
cc41ac7c 2151 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2152 } else {
afafd5b0
AD		 2153 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2154 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2155 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2156 }
e8e26350 2157
cc41ac7c
JB		 2158 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2159}
9a799d71 2160
0cefafad
JB		 2161static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2162{
2163 u32 mrqc = 0;
2164 int mask;
2165
2166 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2167 return mrqc;
2168
2169 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2170#ifdef CONFIG_IXGBE_DCB
2171 | IXGBE_FLAG_DCB_ENABLED
2172#endif
1cdd1ec8 2173 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2174 );
2175
2176 switch (mask) {
2177 case (IXGBE_FLAG_RSS_ENABLED):
2178 mrqc = IXGBE_MRQC_RSSEN;
2179 break;
1cdd1ec8
GR		 2180 case (IXGBE_FLAG_SRIOV_ENABLED):
2181 mrqc = IXGBE_MRQC_VMDQEN;
2182 break;
0cefafad
JB		 2183#ifdef CONFIG_IXGBE_DCB
2184 case (IXGBE_FLAG_DCB_ENABLED):
2185 mrqc = IXGBE_MRQC_RT8TCEN;
2186 break;
2187#endif /* CONFIG_IXGBE_DCB */
2188 default:
2189 break;
2190 }
2191
2192 return mrqc;
2193}
2194
bb5a9ad2
NS		 2195/**
2196 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2197 * @adapter: address of board private structure
2198 * @index: index of ring to set
bb5a9ad2 2199 **/
edd2ea55 2200static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2201{
2202 struct ixgbe_ring *rx_ring;
2203 struct ixgbe_hw *hw = &adapter->hw;
2204 int j;
2205 u32 rscctrl;
edd2ea55 2206 int rx_buf_len;
bb5a9ad2 2207
4a0b9ca0 2208 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2209 j = rx_ring->reg_idx;
edd2ea55 2210 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2211 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2212 rscctrl |= IXGBE_RSCCTL_RSCEN;
2213 /*
2214 * we must limit the number of descriptors so that the
2215 * total size of max desc * buf_len is not greater
2216 * than 65535
2217 */
2218 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2219#if (MAX_SKB_FRAGS > 16)
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2221#elif (MAX_SKB_FRAGS > 8)
2222 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2223#elif (MAX_SKB_FRAGS > 4)
2224 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2225#else
2226 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2227#endif
2228 } else {
2229 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2230 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2231 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2232 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2233 else
2234 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2235 }
2236 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2237}
2238
9a799d71 2239/**
3a581073 2240 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2241 * @adapter: board private structure
2242 *
2243 * Configure the Rx unit of the MAC after a reset.
2244 **/
2245static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2246{
2247 u64 rdba;
2248 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2249 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2250 struct net_device *netdev = adapter->netdev;
2251 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2252 int i, j;
9a799d71 2253 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2254 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2255 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2256 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2257 u32 fctrl, hlreg0;
509ee935 2258 u32 reta = 0, mrqc = 0;
cc41ac7c 2259 u32 rdrxctl;
7c6e0a43 2260 int rx_buf_len;
9a799d71
AK		 2261
2262 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2263 /* Do not use packet split if we're in SR-IOV Mode */
2264 if (!adapter->num_vfs)
2265 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2266
2267 /* Set the RX buffer length according to the mode */
2268 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2269 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2270 if (hw->mac.type == ixgbe_mac_82599EB) {
2271 /* PSRTYPE must be initialized in 82599 */
2272 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2273 IXGBE_PSRTYPE_UDPHDR |
2274 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2275 IXGBE_PSRTYPE_IPV6HDR |
2276 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2277 IXGBE_WRITE_REG(hw,
2278 IXGBE_PSRTYPE(adapter->num_vfs),
2279 psrtype);
e8e26350 2280 }
9a799d71 2281 } else {
0c19d6af 2282 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2283 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2284 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2285 else
7c6e0a43 2286 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2287 }
2288
2289 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2290 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2291 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2292 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2293 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2294
2295 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2296 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2297 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2298 else
2299 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2300#ifdef IXGBE_FCOE
f34c5c82 2301 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2302 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2303#endif
9a799d71
AK		 2304 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2305
4a0b9ca0 2306 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2307 /* disable receives while setting up the descriptors */
2308 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2309 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2310
0cefafad
JB		 2311 /*
2312 * Setup the HW Rx Head and Tail Descriptor Pointers and
2313 * the Base and Length of the Rx Descriptor Ring
2314 */
9a799d71 2315 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2316 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2317 rdba = rx_ring->dma;
2318 j = rx_ring->reg_idx;
284901a9 2319 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2320 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2321 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2322 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2323 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2324 rx_ring->head = IXGBE_RDH(j);
2325 rx_ring->tail = IXGBE_RDT(j);
2326 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2327
6e455b89
YZ		 2328 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2329 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2330 else
2331 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2332
63f39bd1 2333#ifdef IXGBE_FCOE
f34c5c82 2334 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2335 struct ixgbe_ring_feature *f;
2336 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2337 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2338 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2339 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2340 rx_ring->rx_buf_len =
2341 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2342 }
63f39bd1
YZ		 2343 }
2344
2345#endif /* IXGBE_FCOE */
a6616b42 2346 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2347 }
2348
e8e26350
PW		 2349 if (hw->mac.type == ixgbe_mac_82598EB) {
2350 /*
2351 * For VMDq support of different descriptor types or
2352 * buffer sizes through the use of multiple SRRCTL
2353 * registers, RDRXCTL.MVMEN must be set to 1
2354 *
2355 * also, the manual doesn't mention it clearly but DCA hints
2356 * will only use queue 0's tags unless this bit is set. Side
2357 * effects of setting this bit are only that SRRCTL must be
2358 * fully programmed [0..15]
2359 */
2a41ff81
JB		 2360 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2361 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2362 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2363 }
177db6ff 2364
1cdd1ec8
GR		 2365 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2366 u32 vt_reg_bits;
2367 u32 reg_offset, vf_shift;
2368 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2369 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2370 | IXGBE_VT_CTL_REPLEN;
2371 vt_reg_bits |= (adapter->num_vfs <<
2372 IXGBE_VT_CTL_POOL_SHIFT);
2373 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2374 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2375
2376 vf_shift = adapter->num_vfs % 32;
2377 reg_offset = adapter->num_vfs / 32;
2378 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2379 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2380 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2381 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2382 /* Enable only the PF's pool for Tx/Rx */
2383 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2384 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2385 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2386 ixgbe_set_vmolr(hw, adapter->num_vfs);
2387 }
2388
e8e26350 2389 /* Program MRQC for the distribution of queues */
0cefafad 2390 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2391
021230d4 2392 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2393 /* Fill out redirection table */
021230d4
AV		 2394 for (i = 0, j = 0; i < 128; i++, j++) {
2395 if (j == adapter->ring_feature[RING_F_RSS].indices)
2396 j = 0;
2397 /* reta = 4-byte sliding window of
2398 * 0x00..(indices-1)(indices-1)00..etc. */
2399 reta = (reta << 8) | (j * 0x11);
2400 if ((i & 3) == 3)
2401 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2402 }
2403
2404 /* Fill out hash function seeds */
2405 for (i = 0; i < 10; i++)
7c6e0a43 2406 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2407
2a41ff81
JB		 2408 if (hw->mac.type == ixgbe_mac_82598EB)
2409 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2410 /* Perform hash on these packet types */
2a41ff81
JB		 2411 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2412 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2413 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2414 | IXGBE_MRQC_RSS_FIELD_IPV6
2415 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2416 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2417 }
2a41ff81 2418 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2419
1cdd1ec8
GR		 2420 if (adapter->num_vfs) {
2421 u32 reg;
2422
2423 /* Map PF MAC address in RAR Entry 0 to first pool
2424 * following VFs */
2425 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2426
2427 /* Set up VF register offsets for selected VT Mode, i.e.
2428 * 64 VFs for SR-IOV */
2429 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2430 reg |= IXGBE_GCR_EXT_SRIOV;
2431 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2432 }
2433
021230d4
AV		 2434 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2435
2436 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2437 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2438 /* Disable indicating checksum in descriptor, enables
2439 * RSS hash */
9a799d71 2440 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2441 }
021230d4
AV		 2442 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2443 /* Enable IPv4 payload checksum for UDP fragments
2444 * if PCSD is not set */
2445 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2446 }
2447
2448 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2449
2450 if (hw->mac.type == ixgbe_mac_82599EB) {
2451 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2452 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2453 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2454 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2455 }
f8212f97 2456
0c19d6af 2457 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2458 /* Enable 82599 HW-RSC */
bb5a9ad2 2459 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2460 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2461
f8212f97
AD		 2462 /* Disable RSC for ACK packets */
2463 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2464 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2465 }
9a799d71
AK		 2466}
2467
068c89b0
DS		 2468static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2469{
2470 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2471 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2472 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2473
2474 /* add VID to filter table */
1ada1b1b 2475 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2476}
2477
2478static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2479{
2480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2482 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2483
2484 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2485 ixgbe_irq_disable(adapter);
2486
2487 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2488
2489 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2490 ixgbe_irq_enable(adapter);
2491
2492 /* remove VID from filter table */
1ada1b1b 2493 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2494}
2495
5f6c0181
JB		 2496/**
2497 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2498 * @adapter: driver data
2499 */
2500static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2501{
2502 struct ixgbe_hw *hw = &adapter->hw;
2503 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2504 int i, j;
2505
2506 switch (hw->mac.type) {
2507 case ixgbe_mac_82598EB:
2508 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2509 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2510 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2511 break;
2512 case ixgbe_mac_82599EB:
2513 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2514 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2515 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2516 for (i = 0; i < adapter->num_rx_queues; i++) {
2517 j = adapter->rx_ring[i]->reg_idx;
2518 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2519 vlnctrl &= ~IXGBE_RXDCTL_VME;
2520 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2521 }
2522 break;
2523 default:
2524 break;
2525 }
2526}
2527
2528/**
2529 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2530 * @adapter: driver data
2531 */
2532static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2533{
2534 struct ixgbe_hw *hw = &adapter->hw;
2535 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2536 int i, j;
2537
2538 switch (hw->mac.type) {
2539 case ixgbe_mac_82598EB:
2540 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2541 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2542 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2543 break;
2544 case ixgbe_mac_82599EB:
2545 vlnctrl |= IXGBE_VLNCTRL_VFE;
2546 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2547 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2548 for (i = 0; i < adapter->num_rx_queues; i++) {
2549 j = adapter->rx_ring[i]->reg_idx;
2550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2551 vlnctrl |= IXGBE_RXDCTL_VME;
2552 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2553 }
2554 break;
2555 default:
2556 break;
2557 }
2558}
2559
9a799d71 2560static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2561 struct vlan_group *grp)
9a799d71
AK		 2562{
2563 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2564
d4f80882
AV		 2565 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2566 ixgbe_irq_disable(adapter);
9a799d71
AK		 2567 adapter->vlgrp = grp;
2568
2f90b865
AD		 2569 /*
2570 * For a DCB driver, always enable VLAN tag stripping so we can
2571 * still receive traffic from a DCB-enabled host even if we're
2572 * not in DCB mode.
2573 */
5f6c0181 2574 ixgbe_vlan_filter_enable(adapter);
dc63d377 2575
e8e26350 2576 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2577
d4f80882
AV		 2578 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2579 ixgbe_irq_enable(adapter);
9a799d71
AK		 2580}
2581
9a799d71
AK		 2582static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2583{
2584 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2585
2586 if (adapter->vlgrp) {
2587 u16 vid;
2588 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2589 if (!vlan_group_get_device(adapter->vlgrp, vid))
2590 continue;
2591 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2592 }
2593 }
2594}
2595
2596/**
2c5645cf 2597 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2598 * @netdev: network interface device structure
2599 *
2c5645cf
CL		 2600 * The set_rx_method entry point is called whenever the unicast/multicast
2601 * address list or the network interface flags are updated. This routine is
2602 * responsible for configuring the hardware for proper unicast, multicast and
2603 * promiscuous mode.
9a799d71 2604 **/
7f870475 2605void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2606{
2607 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2608 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2609 u32 fctrl;
9a799d71
AK		 2610
2611 /* Check for Promiscuous and All Multicast modes */
2612
2613 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2614
2615 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2616 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2617 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
5f6c0181
JB		 2618 /* don't hardware filter vlans in promisc mode */
2619 ixgbe_vlan_filter_disable(adapter);
9a799d71 2620 } else {
746b9f02
PM		 2621 if (netdev->flags & IFF_ALLMULTI) {
2622 fctrl |= IXGBE_FCTRL_MPE;
2623 fctrl &= ~IXGBE_FCTRL_UPE;
2624 } else {
2625 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2626 }
5f6c0181 2627 ixgbe_vlan_filter_enable(adapter);
2c5645cf 2628 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2629 }
2630
2631 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2632
2c5645cf 2633 /* reprogram secondary unicast list */
32e7bfc4 2634 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2635
2c5645cf 2636 /* reprogram multicast list */
2853eb89
JP		 2637 hw->mac.ops.update_mc_addr_list(hw, netdev);
2638
1cdd1ec8
GR		 2639 if (adapter->num_vfs)
2640 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2641}
2642
021230d4
AV		 2643static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2644{
2645 int q_idx;
2646 struct ixgbe_q_vector *q_vector;
2647 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2648
2649 /* legacy and MSI only use one vector */
2650 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2651 q_vectors = 1;
2652
2653 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2654 struct napi_struct *napi;
7a921c93 2655 q_vector = adapter->q_vector[q_idx];
f0848276 2656 napi = &q_vector->napi;
91281fd3
AD		 2657 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2658 if (!q_vector->rxr_count || !q_vector->txr_count) {
2659 if (q_vector->txr_count == 1)
2660 napi->poll = &ixgbe_clean_txonly;
2661 else if (q_vector->rxr_count == 1)
2662 napi->poll = &ixgbe_clean_rxonly;
2663 }
2664 }
f0848276
JB		 2665
2666 napi_enable(napi);
021230d4
AV		 2667 }
2668}
2669
2670static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2671{
2672 int q_idx;
2673 struct ixgbe_q_vector *q_vector;
2674 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2675
2676 /* legacy and MSI only use one vector */
2677 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2678 q_vectors = 1;
2679
2680 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2681 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2682 napi_disable(&q_vector->napi);
2683 }
2684}
2685
7a6b6f51 2686#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2687/*
2688 * ixgbe_configure_dcb - Configure DCB hardware
2689 * @adapter: ixgbe adapter struct
2690 *
2691 * This is called by the driver on open to configure the DCB hardware.
2692 * This is also called by the gennetlink interface when reconfiguring
2693 * the DCB state.
2694 */
2695static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2696{
2697 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2698 u32 txdctl;
2f90b865
AD		 2699 int i, j;
2700
2701 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2702 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2703 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2704
2705 /* reconfigure the hardware */
2706 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2707
2708 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2709 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2710 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2711 /* PThresh workaround for Tx hang with DFP enabled. */
2712 txdctl |= 32;
2713 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2714 }
2715 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 2716 ixgbe_vlan_filter_enable(adapter);
2717
2f90b865
AD		 2718 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2719}
2720
2721#endif
9a799d71
AK		 2722static void ixgbe_configure(struct ixgbe_adapter *adapter)
2723{
2724 struct net_device *netdev = adapter->netdev;
c4cf55e5 2725 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2726 int i;
2727
2c5645cf 2728 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2729
2730 ixgbe_restore_vlan(adapter);
7a6b6f51 2731#ifdef CONFIG_IXGBE_DCB
2f90b865 2732 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2733 if (hw->mac.type == ixgbe_mac_82598EB)
2734 netif_set_gso_max_size(netdev, 32768);
2735 else
2736 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2737 ixgbe_configure_dcb(adapter);
2738 } else {
2739 netif_set_gso_max_size(netdev, 65536);
2740 }
2741#else
2742 netif_set_gso_max_size(netdev, 65536);
2743#endif
9a799d71 2744
eacd73f7
YZ		 2745#ifdef IXGBE_FCOE
2746 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2747 ixgbe_configure_fcoe(adapter);
2748
2749#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2750 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2751 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2752 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2753 adapter->atr_sample_rate;
2754 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2755 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2756 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2757 }
2758
9a799d71
AK		 2759 ixgbe_configure_tx(adapter);
2760 ixgbe_configure_rx(adapter);
2761 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2762 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2763 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2764}
2765
e8e26350
PW		 2766static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2767{
2768 switch (hw->phy.type) {
2769 case ixgbe_phy_sfp_avago:
2770 case ixgbe_phy_sfp_ftl:
2771 case ixgbe_phy_sfp_intel:
2772 case ixgbe_phy_sfp_unknown:
2773 case ixgbe_phy_tw_tyco:
2774 case ixgbe_phy_tw_unknown:
2775 return true;
2776 default:
2777 return false;
2778 }
2779}
2780
0ecc061d 2781/**
e8e26350
PW		 2782 * ixgbe_sfp_link_config - set up SFP+ link
2783 * @adapter: pointer to private adapter struct
2784 **/
2785static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2786{
2787 struct ixgbe_hw *hw = &adapter->hw;
2788
2789 if (hw->phy.multispeed_fiber) {
2790 /*
2791 * In multispeed fiber setups, the device may not have
2792 * had a physical connection when the driver loaded.
2793 * If that's the case, the initial link configuration
2794 * couldn't get the MAC into 10G or 1G mode, so we'll
2795 * never have a link status change interrupt fire.
2796 * We need to try and force an autonegotiation
2797 * session, then bring up link.
2798 */
2799 hw->mac.ops.setup_sfp(hw);
2800 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2801 schedule_work(&adapter->multispeed_fiber_task);
2802 } else {
2803 /*
2804 * Direct Attach Cu and non-multispeed fiber modules
2805 * still need to be configured properly prior to
2806 * attempting link.
2807 */
2808 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2809 schedule_work(&adapter->sfp_config_module_task);
2810 }
2811}
2812
2813/**
2814 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2815 * @hw: pointer to private hardware struct
2816 *
2817 * Returns 0 on success, negative on failure
2818 **/
e8e26350 2819static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2820{
2821 u32 autoneg;
8620a103 2822 bool negotiation, link_up = false;
0ecc061d
PWJ		 2823 u32 ret = IXGBE_ERR_LINK_SETUP;
2824
2825 if (hw->mac.ops.check_link)
2826 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2827
2828 if (ret)
2829 goto link_cfg_out;
2830
2831 if (hw->mac.ops.get_link_capabilities)
8620a103 2832 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2833 if (ret)
2834 goto link_cfg_out;
2835
8620a103
MC		 2836 if (hw->mac.ops.setup_link)
2837 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2838link_cfg_out:
2839 return ret;
2840}
2841
e8e26350
PW		 2842#define IXGBE_MAX_RX_DESC_POLL 10
2843static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2844 int rxr)
2845{
4a0b9ca0 2846 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2847 int k;
2848
2849 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2850 if (IXGBE_READ_REG(&adapter->hw,
2851 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2852 break;
2853 else
2854 msleep(1);
2855 }
2856 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2857 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2858 "not set within the polling period\n", rxr);
2859 }
4a0b9ca0
PW		 2860 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2861 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2862}
2863
9a799d71
AK		 2864static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2865{
2866 struct net_device *netdev = adapter->netdev;
9a799d71 2867 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2868 int i, j = 0;
e8e26350 2869 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2870 int err;
9a799d71 2871 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2872 u32 txdctl, rxdctl, mhadd;
e8e26350 2873 u32 dmatxctl;
021230d4 2874 u32 gpie;
c9205697 2875 u32 ctrl_ext;
9a799d71 2876
5eba3699
AV		 2877 ixgbe_get_hw_control(adapter);
2878
021230d4
AV		 2879 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2880 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2881 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2882 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2883 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2884 } else {
2885 /* MSI only */
021230d4 2886 gpie = 0;
9a799d71 2887 }
1cdd1ec8
GR		 2888 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2889 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2890 gpie |= IXGBE_GPIE_VTMODE_64;
2891 }
021230d4
AV		 2892 /* XXX: to interrupt immediately for EICS writes, enable this */
2893 /* gpie |= IXGBE_GPIE_EIMEN; */
2894 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2895 }
2896
9b471446
JB		 2897 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2898 /*
2899 * use EIAM to auto-mask when MSI-X interrupt is asserted
2900 * this saves a register write for every interrupt
2901 */
2902 switch (hw->mac.type) {
2903 case ixgbe_mac_82598EB:
2904 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2905 break;
2906 default:
2907 case ixgbe_mac_82599EB:
2908 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2909 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2910 break;
2911 }
2912 } else {
021230d4
AV		 2913 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2914 * specifically only auto mask tx and rx interrupts */
2915 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2916 }
9a799d71 2917
0befdb3e
JB		 2918 /* Enable fan failure interrupt if media type is copper */
2919 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2920 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2921 gpie |= IXGBE_SDP1_GPIEN;
2922 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2923 }
2924
e8e26350
PW		 2925 if (hw->mac.type == ixgbe_mac_82599EB) {
2926 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2927 gpie |= IXGBE_SDP1_GPIEN;
2928 gpie |= IXGBE_SDP2_GPIEN;
2929 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2930 }
2931
63f39bd1
YZ		 2932#ifdef IXGBE_FCOE
2933 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2934 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2935 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2936 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2937
2938#endif /* IXGBE_FCOE */
021230d4 2939 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2940 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2941 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2942 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2943
2944 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2945 }
2946
2947 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2948 j = adapter->tx_ring[i]->reg_idx;
021230d4 2949 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 2950 if (adapter->rx_itr_setting == 0) {
2951 /* cannot set wthresh when itr==0 */
2952 txdctl &= ~0x007F0000;
2953 } else {
2954 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2955 txdctl |= (8 << 16);
2956 }
e8e26350
PW		 2957 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2958 }
2959
2960 if (hw->mac.type == ixgbe_mac_82599EB) {
2961 /* DMATXCTL.EN must be set after all Tx queue config is done */
2962 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2963 dmatxctl |= IXGBE_DMATXCTL_TE;
2964 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2965 }
2966 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2967 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2968 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2969 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2970 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2971 if (hw->mac.type == ixgbe_mac_82599EB) {
2972 int wait_loop = 10;
2973 /* poll for Tx Enable ready */
2974 do {
2975 msleep(1);
2976 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2977 } while (--wait_loop &&
2978 !(txdctl & IXGBE_TXDCTL_ENABLE));
2979 if (!wait_loop)
2980 DPRINTK(DRV, ERR, "Could not enable "
2981 "Tx Queue %d\n", j);
2982 }
9a799d71
AK		 2983 }
2984
e8e26350 2985 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2986 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2987 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2988 /* enable PTHRESH=32 descriptors (half the internal cache)
2989 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2990 * this also removes a pesky rx_no_buffer_count increment */
2991 rxdctl |= 0x0020;
9a799d71 2992 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2993 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2994 if (hw->mac.type == ixgbe_mac_82599EB)
2995 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2996 }
2997 /* enable all receives */
2998 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2999 if (hw->mac.type == ixgbe_mac_82598EB)
3000 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3001 else
3002 rxdctl |= IXGBE_RXCTRL_RXEN;
3003 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3004
3005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3006 ixgbe_configure_msix(adapter);
3007 else
3008 ixgbe_configure_msi_and_legacy(adapter);
3009
61fac744
PW		 3010 /* enable the optics */
3011 if (hw->phy.multispeed_fiber)
3012 hw->mac.ops.enable_tx_laser(hw);
3013
9a799d71 3014 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3015 ixgbe_napi_enable_all(adapter);
3016
3017 /* clear any pending interrupts, may auto mask */
3018 IXGBE_READ_REG(hw, IXGBE_EICR);
3019
9a799d71
AK		 3020 ixgbe_irq_enable(adapter);
3021
bf069c97
DS		 3022 /*
3023 * If this adapter has a fan, check to see if we had a failure
3024 * before we enabled the interrupt.
3025 */
3026 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3027 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3028 if (esdp & IXGBE_ESDP_SDP1)
3029 DPRINTK(DRV, CRIT,
3030 "Fan has stopped, replace the adapter\n");
3031 }
3032
e8e26350
PW		 3033 /*
3034 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3035 * arrived before interrupts were enabled but after probe. Such
3036 * devices wouldn't have their type identified yet. We need to
3037 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3038 * If we're not hot-pluggable SFP+, we just need to configure link
3039 * and bring it up.
3040 */
19343de2
DS		 3041 if (hw->phy.type == ixgbe_phy_unknown) {
3042 err = hw->phy.ops.identify(hw);
3043 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3044 /*
3045 * Take the device down and schedule the sfp tasklet
3046 * which will unregister_netdev and log it.
3047 */
19343de2 3048 ixgbe_down(adapter);
5da43c1a 3049 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3050 return err;
3051 }
e8e26350
PW		 3052 }
3053
3054 if (ixgbe_is_sfp(hw)) {
3055 ixgbe_sfp_link_config(adapter);
3056 } else {
3057 err = ixgbe_non_sfp_link_config(hw);
3058 if (err)
3059 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3060 }
0ecc061d 3061
c4cf55e5
PWJ		 3062 for (i = 0; i < adapter->num_tx_queues; i++)
3063 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3064 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3065
1da100bb
PWJ		 3066 /* enable transmits */
3067 netif_tx_start_all_queues(netdev);
3068
9a799d71
AK		 3069 /* bring the link up in the watchdog, this could race with our first
3070 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3071 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3072 adapter->link_check_timeout = jiffies;
9a799d71 3073 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3074
3075 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3076 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3077 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3078 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3079
9a799d71
AK		 3080 return 0;
3081}
3082
d4f80882
AV		 3083void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3084{
3085 WARN_ON(in_interrupt());
3086 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3087 msleep(1);
3088 ixgbe_down(adapter);
5809a1ae
GR		 3089 /*
3090 * If SR-IOV enabled then wait a bit before bringing the adapter
3091 * back up to give the VFs time to respond to the reset. The
3092 * two second wait is based upon the watchdog timer cycle in
3093 * the VF driver.
3094 */
3095 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3096 msleep(2000);
d4f80882
AV		 3097 ixgbe_up(adapter);
3098 clear_bit(__IXGBE_RESETTING, &adapter->state);
3099}
3100
9a799d71
AK		 3101int ixgbe_up(struct ixgbe_adapter *adapter)
3102{
3103 /* hardware has been reset, we need to reload some things */
3104 ixgbe_configure(adapter);
3105
3106 return ixgbe_up_complete(adapter);
3107}
3108
3109void ixgbe_reset(struct ixgbe_adapter *adapter)
3110{
c44ade9e 3111 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3112 int err;
3113
3114 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3115 switch (err) {
3116 case 0:
3117 case IXGBE_ERR_SFP_NOT_PRESENT:
3118 break;
3119 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3120 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3121 break;
794caeb2
PWJ		 3122 case IXGBE_ERR_EEPROM_VERSION:
3123 /* We are running on a pre-production device, log a warning */
3124 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3125 "adapter/LOM. Please be aware there may be issues "
3126 "associated with your hardware. If you are "
3127 "experiencing problems please contact your Intel or "
3128 "hardware representative who provided you with this "
3129 "hardware.\n");
3130 break;
da4dd0f7
PWJ		 3131 default:
3132 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3133 }
9a799d71
AK		 3134
3135 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3136 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3137 IXGBE_RAH_AV);
9a799d71
AK		 3138}
3139
9a799d71
AK		 3140/**
3141 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3142 * @adapter: board private structure
3143 * @rx_ring: ring to free buffers from
3144 **/
3145static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3146 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3147{
3148 struct pci_dev *pdev = adapter->pdev;
3149 unsigned long size;
3150 unsigned int i;
3151
3152 /* Free all the Rx ring sk_buffs */
3153
3154 for (i = 0; i < rx_ring->count; i++) {
3155 struct ixgbe_rx_buffer *rx_buffer_info;
3156
3157 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3158 if (rx_buffer_info->dma) {
1b507730 3159 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3160 rx_ring->rx_buf_len,
1b507730 3161 DMA_FROM_DEVICE);
9a799d71
AK		 3162 rx_buffer_info->dma = 0;
3163 }
3164 if (rx_buffer_info->skb) {
f8212f97 3165 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3166 rx_buffer_info->skb = NULL;
f8212f97
AD		 3167 do {
3168 struct sk_buff *this = skb;
fd3686a8 3169 if (IXGBE_RSC_CB(this)->dma) {
1b507730
NN		 3170 dma_unmap_single(&pdev->dev,
3171 IXGBE_RSC_CB(this)->dma,
43634e82 3172 rx_ring->rx_buf_len,
1b507730 3173 DMA_FROM_DEVICE);
fd3686a8
MC		 3174 IXGBE_RSC_CB(this)->dma = 0;
3175 }
f8212f97
AD		 3176 skb = skb->prev;
3177 dev_kfree_skb(this);
3178 } while (skb);
9a799d71
AK		 3179 }
3180 if (!rx_buffer_info->page)
3181 continue;
4f57ca6e 3182 if (rx_buffer_info->page_dma) {
1b507730
NN		 3183 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3184 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3185 rx_buffer_info->page_dma = 0;
3186 }
9a799d71
AK		 3187 put_page(rx_buffer_info->page);
3188 rx_buffer_info->page = NULL;
762f4c57 3189 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3190 }
3191
3192 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3193 memset(rx_ring->rx_buffer_info, 0, size);
3194
3195 /* Zero out the descriptor ring */
3196 memset(rx_ring->desc, 0, rx_ring->size);
3197
3198 rx_ring->next_to_clean = 0;
3199 rx_ring->next_to_use = 0;
3200
9891ca7c
JB		 3201 if (rx_ring->head)
3202 writel(0, adapter->hw.hw_addr + rx_ring->head);
3203 if (rx_ring->tail)
3204 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3205}
3206
3207/**
3208 * ixgbe_clean_tx_ring - Free Tx Buffers
3209 * @adapter: board private structure
3210 * @tx_ring: ring to be cleaned
3211 **/
3212static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3213 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3214{
3215 struct ixgbe_tx_buffer *tx_buffer_info;
3216 unsigned long size;
3217 unsigned int i;
3218
3219 /* Free all the Tx ring sk_buffs */
3220
3221 for (i = 0; i < tx_ring->count; i++) {
3222 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3223 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3224 }
3225
3226 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3227 memset(tx_ring->tx_buffer_info, 0, size);
3228
3229 /* Zero out the descriptor ring */
3230 memset(tx_ring->desc, 0, tx_ring->size);
3231
3232 tx_ring->next_to_use = 0;
3233 tx_ring->next_to_clean = 0;
3234
9891ca7c
JB		 3235 if (tx_ring->head)
3236 writel(0, adapter->hw.hw_addr + tx_ring->head);
3237 if (tx_ring->tail)
3238 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3239}
3240
3241/**
021230d4 3242 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3243 * @adapter: board private structure
3244 **/
021230d4 3245static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3246{
3247 int i;
3248
021230d4 3249 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3250 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3251}
3252
3253/**
021230d4 3254 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3255 * @adapter: board private structure
3256 **/
021230d4 3257static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3258{
3259 int i;
3260
021230d4 3261 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3262 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3263}
3264
3265void ixgbe_down(struct ixgbe_adapter *adapter)
3266{
3267 struct net_device *netdev = adapter->netdev;
7f821875 3268 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3269 u32 rxctrl;
7f821875
JB		 3270 u32 txdctl;
3271 int i, j;
9a799d71
AK		 3272
3273 /* signal that we are down to the interrupt handler */
3274 set_bit(__IXGBE_DOWN, &adapter->state);
3275
61fac744
PW		 3276 /* power down the optics */
3277 if (hw->phy.multispeed_fiber)
3278 hw->mac.ops.disable_tx_laser(hw);
3279
767081ad
GR		 3280 /* disable receive for all VFs and wait one second */
3281 if (adapter->num_vfs) {
767081ad
GR		 3282 /* ping all the active vfs to let them know we are going down */
3283 ixgbe_ping_all_vfs(adapter);
581d1aa7 3284
767081ad
GR		 3285 /* Disable all VFTE/VFRE TX/RX */
3286 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3287
3288 /* Mark all the VFs as inactive */
3289 for (i = 0 ; i < adapter->num_vfs; i++)
3290 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3291 }
3292
9a799d71 3293 /* disable receives */
7f821875
JB		 3294 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3295 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3296
7f821875 3297 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3298 msleep(10);
3299
7f821875
JB		 3300 netif_tx_stop_all_queues(netdev);
3301
0a1f87cb
DS		 3302 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3303 del_timer_sync(&adapter->sfp_timer);
9a799d71 3304 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3305 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3306
c0dfb90e
JF		 3307 netif_carrier_off(netdev);
3308 netif_tx_disable(netdev);
3309
3310 ixgbe_irq_disable(adapter);
3311
3312 ixgbe_napi_disable_all(adapter);
3313
c4cf55e5
PWJ		 3314 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3315 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3316 cancel_work_sync(&adapter->fdir_reinit_task);
3317
7f821875
JB		 3318 /* disable transmits in the hardware now that interrupts are off */
3319 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3320 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3321 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3322 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3323 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3324 }
88512539
PW		 3325 /* Disable the Tx DMA engine on 82599 */
3326 if (hw->mac.type == ixgbe_mac_82599EB)
3327 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3328 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3329 ~IXGBE_DMATXCTL_TE));
7f821875 3330
9a713e7c
PW		 3331 /* clear n-tuple filters that are cached */
3332 ethtool_ntuple_flush(netdev);
3333
6f4a0e45
PL		 3334 if (!pci_channel_offline(adapter->pdev))
3335 ixgbe_reset(adapter);
9a799d71
AK		 3336 ixgbe_clean_all_tx_rings(adapter);
3337 ixgbe_clean_all_rx_rings(adapter);
3338
5dd2d332 3339#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3340 /* since we reset the hardware DCA settings were cleared */
e35ec126 3341 ixgbe_setup_dca(adapter);
96b0e0f6 3342#endif
9a799d71
AK		 3343}
3344
9a799d71 3345/**
021230d4
AV		 3346 * ixgbe_poll - NAPI Rx polling callback
3347 * @napi: structure for representing this polling device
3348 * @budget: how many packets driver is allowed to clean
3349 *
3350 * This function is used for legacy and MSI, NAPI mode
9a799d71 3351 **/
021230d4 3352static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3353{
9a1a69ad
JB		 3354 struct ixgbe_q_vector *q_vector =
3355 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3356 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3357 int tx_clean_complete, work_done = 0;
9a799d71 3358
5dd2d332 3359#ifdef CONFIG_IXGBE_DCA
bd0362dd 3360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3361 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3362 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3363 }
3364#endif
3365
4a0b9ca0
PW		 3366 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3367 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3368
9a1a69ad 3369 if (!tx_clean_complete)
d2c7ddd6
DM		 3370 work_done = budget;
3371
53e52c72
DM		 3372 /* If budget not fully consumed, exit the polling mode */
3373 if (work_done < budget) {
288379f0 3374 napi_complete(napi);
f7554a2b 3375 if (adapter->rx_itr_setting & 1)
f494e8fa 3376 ixgbe_set_itr(adapter);
d4f80882 3377 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3378 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3379 }
9a799d71
AK		 3380 return work_done;
3381}
3382
3383/**
3384 * ixgbe_tx_timeout - Respond to a Tx Hang
3385 * @netdev: network interface device structure
3386 **/
3387static void ixgbe_tx_timeout(struct net_device *netdev)
3388{
3389 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3390
3391 /* Do the reset outside of interrupt context */
3392 schedule_work(&adapter->reset_task);
3393}
3394
3395static void ixgbe_reset_task(struct work_struct *work)
3396{
3397 struct ixgbe_adapter *adapter;
3398 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3399
2f90b865
AD		 3400 /* If we're already down or resetting, just bail */
3401 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3402 test_bit(__IXGBE_RESETTING, &adapter->state))
3403 return;
3404
9a799d71
AK		 3405 adapter->tx_timeout_count++;
3406
d4f80882 3407 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3408}
3409
bc97114d
PWJ		 3410#ifdef CONFIG_IXGBE_DCB
3411static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3412{
bc97114d 3413 bool ret = false;
0cefafad 3414 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3415
0cefafad
JB		 3416 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3417 return ret;
3418
3419 f->mask = 0x7 << 3;
3420 adapter->num_rx_queues = f->indices;
3421 adapter->num_tx_queues = f->indices;
3422 ret = true;
2f90b865 3423
bc97114d
PWJ		 3424 return ret;
3425}
3426#endif
3427
4df10466
JB		 3428/**
3429 * ixgbe_set_rss_queues: Allocate queues for RSS
3430 * @adapter: board private structure to initialize
3431 *
3432 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3433 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3434 *
3435 **/
bc97114d
PWJ		 3436static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3437{
3438 bool ret = false;
0cefafad 3439 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3440
3441 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3442 f->mask = 0xF;
3443 adapter->num_rx_queues = f->indices;
3444 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3445 ret = true;
3446 } else {
bc97114d 3447 ret = false;
b9804972
JB		 3448 }
3449
bc97114d
PWJ		 3450 return ret;
3451}
3452
c4cf55e5
PWJ		 3453/**
3454 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3455 * @adapter: board private structure to initialize
3456 *
3457 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3458 * to the original CPU that initiated the Tx session. This runs in addition
3459 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3460 * Rx load across CPUs using RSS.
3461 *
3462 **/
3463static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3464{
3465 bool ret = false;
3466 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3467
3468 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3469 f_fdir->mask = 0;
3470
3471 /* Flow Director must have RSS enabled */
3472 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3473 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3474 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3475 adapter->num_tx_queues = f_fdir->indices;
3476 adapter->num_rx_queues = f_fdir->indices;
3477 ret = true;
3478 } else {
3479 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3480 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3481 }
3482 return ret;
3483}
3484
0331a832
YZ		 3485#ifdef IXGBE_FCOE
3486/**
3487 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3488 * @adapter: board private structure to initialize
3489 *
3490 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3491 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3492 * rx queues out of the max number of rx queues, instead, it is used as the
3493 * index of the first rx queue used by FCoE.
3494 *
3495 **/
3496static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3497{
3498 bool ret = false;
3499 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3500
3501 f->indices = min((int)num_online_cpus(), f->indices);
3502 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3503 adapter->num_rx_queues = 1;
3504 adapter->num_tx_queues = 1;
0331a832
YZ		 3505#ifdef CONFIG_IXGBE_DCB
3506 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
d6dbee86 3507 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
0331a832
YZ		 3508 ixgbe_set_dcb_queues(adapter);
3509 }
3510#endif
3511 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
d6dbee86 3512 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3513 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3514 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3515 ixgbe_set_fdir_queues(adapter);
3516 else
3517 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3518 }
3519 /* adding FCoE rx rings to the end */
3520 f->mask = adapter->num_rx_queues;
3521 adapter->num_rx_queues += f->indices;
8de8b2e6 3522 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3523
3524 ret = true;
3525 }
3526
3527 return ret;
3528}
3529
3530#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3531/**
3532 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3533 * @adapter: board private structure to initialize
3534 *
3535 * IOV doesn't actually use anything, so just NAK the
3536 * request for now and let the other queue routines
3537 * figure out what to do.
3538 */
3539static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3540{
3541 return false;
3542}
3543
4df10466
JB		 3544/*
3545 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3546 * @adapter: board private structure to initialize
3547 *
3548 * This is the top level queue allocation routine. The order here is very
3549 * important, starting with the "most" number of features turned on at once,
3550 * and ending with the smallest set of features. This way large combinations
3551 * can be allocated if they're turned on, and smaller combinations are the
3552 * fallthrough conditions.
3553 *
3554 **/
bc97114d
PWJ		 3555static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3556{
1cdd1ec8
GR		 3557 /* Start with base case */
3558 adapter->num_rx_queues = 1;
3559 adapter->num_tx_queues = 1;
3560 adapter->num_rx_pools = adapter->num_rx_queues;
3561 adapter->num_rx_queues_per_pool = 1;
3562
3563 if (ixgbe_set_sriov_queues(adapter))
3564 return;
3565
0331a832
YZ		 3566#ifdef IXGBE_FCOE
3567 if (ixgbe_set_fcoe_queues(adapter))
3568 goto done;
3569
3570#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3571#ifdef CONFIG_IXGBE_DCB
3572 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3573 goto done;
bc97114d
PWJ		 3574
3575#endif
c4cf55e5
PWJ		 3576 if (ixgbe_set_fdir_queues(adapter))
3577 goto done;
3578
bc97114d 3579 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3580 goto done;
3581
3582 /* fallback to base case */
3583 adapter->num_rx_queues = 1;
3584 adapter->num_tx_queues = 1;
3585
3586done:
3587 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3588 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3589}
3590
021230d4 3591static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3592 int vectors)
021230d4
AV		 3593{
3594 int err, vector_threshold;
3595
3596 /* We'll want at least 3 (vector_threshold):
3597 * 1) TxQ[0] Cleanup
3598 * 2) RxQ[0] Cleanup
3599 * 3) Other (Link Status Change, etc.)
3600 * 4) TCP Timer (optional)
3601 */
3602 vector_threshold = MIN_MSIX_COUNT;
3603
3604 /* The more we get, the more we will assign to Tx/Rx Cleanup
3605 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3606 * Right now, we simply care about how many we'll get; we'll
3607 * set them up later while requesting irq's.
3608 */
3609 while (vectors >= vector_threshold) {
3610 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3611 vectors);
021230d4
AV		 3612 if (!err) /* Success in acquiring all requested vectors. */
3613 break;
3614 else if (err < 0)
3615 vectors = 0; /* Nasty failure, quit now */
3616 else /* err == number of vectors we should try again with */
3617 vectors = err;
3618 }
3619
3620 if (vectors < vector_threshold) {
3621 /* Can't allocate enough MSI-X interrupts? Oh well.
3622 * This just means we'll go with either a single MSI
3623 * vector or fall back to legacy interrupts.
3624 */
3625 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3626 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3627 kfree(adapter->msix_entries);
3628 adapter->msix_entries = NULL;
021230d4
AV		 3629 } else {
3630 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3631 /*
3632 * Adjust for only the vectors we'll use, which is minimum
3633 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3634 * vectors we were allocated.
3635 */
3636 adapter->num_msix_vectors = min(vectors,
3637 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3638 }
3639}
3640
021230d4 3641/**
bc97114d 3642 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3643 * @adapter: board private structure to initialize
3644 *
bc97114d
PWJ		 3645 * Cache the descriptor ring offsets for RSS to the assigned rings.
3646 *
021230d4 3647 **/
bc97114d 3648static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3649{
bc97114d
PWJ		 3650 int i;
3651 bool ret = false;
3652
3653 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3654 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3655 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3656 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3657 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3658 ret = true;
3659 } else {
3660 ret = false;
3661 }
3662
3663 return ret;
3664}
3665
3666#ifdef CONFIG_IXGBE_DCB
3667/**
3668 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3669 * @adapter: board private structure to initialize
3670 *
3671 * Cache the descriptor ring offsets for DCB to the assigned rings.
3672 *
3673 **/
3674static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3675{
3676 int i;
3677 bool ret = false;
3678 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3679
3680 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3681 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3682 /* the number of queues is assumed to be symmetric */
3683 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3684 adapter->rx_ring[i]->reg_idx = i << 3;
3685 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3686 }
bc97114d 3687 ret = true;
e8e26350 3688 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3689 if (dcb_i == 8) {
3690 /*
3691 * Tx TC0 starts at: descriptor queue 0
3692 * Tx TC1 starts at: descriptor queue 32
3693 * Tx TC2 starts at: descriptor queue 64
3694 * Tx TC3 starts at: descriptor queue 80
3695 * Tx TC4 starts at: descriptor queue 96
3696 * Tx TC5 starts at: descriptor queue 104
3697 * Tx TC6 starts at: descriptor queue 112
3698 * Tx TC7 starts at: descriptor queue 120
3699 *
3700 * Rx TC0-TC7 are offset by 16 queues each
3701 */
3702 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3703 adapter->tx_ring[i]->reg_idx = i << 5;
3704 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3705 }
3706 for ( ; i < 5; i++) {
4a0b9ca0 3707 adapter->tx_ring[i]->reg_idx =
f92ef202 3708 ((i + 2) << 4);
4a0b9ca0 3709 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3710 }
3711 for ( ; i < dcb_i; i++) {
4a0b9ca0 3712 adapter->tx_ring[i]->reg_idx =
f92ef202 3713 ((i + 8) << 3);
4a0b9ca0 3714 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3715 }
3716
3717 ret = true;
3718 } else if (dcb_i == 4) {
3719 /*
3720 * Tx TC0 starts at: descriptor queue 0
3721 * Tx TC1 starts at: descriptor queue 64
3722 * Tx TC2 starts at: descriptor queue 96
3723 * Tx TC3 starts at: descriptor queue 112
3724 *
3725 * Rx TC0-TC3 are offset by 32 queues each
3726 */
4a0b9ca0
PW		 3727 adapter->tx_ring[0]->reg_idx = 0;
3728 adapter->tx_ring[1]->reg_idx = 64;
3729 adapter->tx_ring[2]->reg_idx = 96;
3730 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3731 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3732 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3733
3734 ret = true;
3735 } else {
3736 ret = false;
e8e26350 3737 }
bc97114d
PWJ		 3738 } else {
3739 ret = false;
021230d4 3740 }
bc97114d
PWJ		 3741 } else {
3742 ret = false;
021230d4 3743 }
bc97114d
PWJ		 3744
3745 return ret;
3746}
3747#endif
3748
c4cf55e5
PWJ		 3749/**
3750 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3751 * @adapter: board private structure to initialize
3752 *
3753 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3754 *
3755 **/
3756static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3757{
3758 int i;
3759 bool ret = false;
3760
3761 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3762 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3763 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3764 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3765 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3766 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3767 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3768 ret = true;
3769 }
3770
3771 return ret;
3772}
3773
0331a832
YZ		 3774#ifdef IXGBE_FCOE
3775/**
3776 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3777 * @adapter: board private structure to initialize
3778 *
3779 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3780 *
3781 */
3782static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3783{
8de8b2e6 3784 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3785 bool ret = false;
3786 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3787
3788 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3789#ifdef CONFIG_IXGBE_DCB
3790 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3791 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3792
0331a832 3793 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3794 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3795 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3796 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3797 /*
3798 * In 82599, the number of Tx queues for each traffic
3799 * class for both 8-TC and 4-TC modes are:
3800 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3801 * 8 TCs: 32 32 16 16 8 8 8 8
3802 * 4 TCs: 64 64 32 32
3803 * We have max 8 queues for FCoE, where 8 the is
3804 * FCoE redirection table size. If TC for FCoE is
3805 * less than or equal to TC3, we have enough queues
3806 * to add max of 8 queues for FCoE, so we start FCoE
3807 * tx descriptor from the next one, i.e., reg_idx + 1.
3808 * If TC for FCoE is above TC3, implying 8 TC mode,
3809 * and we need 8 for FCoE, we have to take all queues
3810 * in that traffic class for FCoE.
3811 */
3812 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3813 fcoe_tx_i--;
0331a832
YZ		 3814 }
3815#endif /* CONFIG_IXGBE_DCB */
3816 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3817 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3818 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3819 ixgbe_cache_ring_fdir(adapter);
3820 else
3821 ixgbe_cache_ring_rss(adapter);
3822
8de8b2e6
YZ		 3823 fcoe_rx_i = f->mask;
3824 fcoe_tx_i = f->mask;
3825 }
3826 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3827 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3828 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3829 }
0331a832
YZ		 3830 ret = true;
3831 }
3832 return ret;
3833}
3834
3835#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3836/**
3837 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3838 * @adapter: board private structure to initialize
3839 *
3840 * SR-IOV doesn't use any descriptor rings but changes the default if
3841 * no other mapping is used.
3842 *
3843 */
3844static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3845{
4a0b9ca0
PW		 3846 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3847 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3848 if (adapter->num_vfs)
3849 return true;
3850 else
3851 return false;
3852}
3853
bc97114d
PWJ		 3854/**
3855 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3856 * @adapter: board private structure to initialize
3857 *
3858 * Once we know the feature-set enabled for the device, we'll cache
3859 * the register offset the descriptor ring is assigned to.
3860 *
3861 * Note, the order the various feature calls is important. It must start with
3862 * the "most" features enabled at the same time, then trickle down to the
3863 * least amount of features turned on at once.
3864 **/
3865static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3866{
3867 /* start with default case */
4a0b9ca0
PW		 3868 adapter->rx_ring[0]->reg_idx = 0;
3869 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3870
1cdd1ec8
GR		 3871 if (ixgbe_cache_ring_sriov(adapter))
3872 return;
3873
0331a832
YZ		 3874#ifdef IXGBE_FCOE
3875 if (ixgbe_cache_ring_fcoe(adapter))
3876 return;
3877
3878#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3879#ifdef CONFIG_IXGBE_DCB
3880 if (ixgbe_cache_ring_dcb(adapter))
3881 return;
3882
3883#endif
c4cf55e5
PWJ		 3884 if (ixgbe_cache_ring_fdir(adapter))
3885 return;
3886
bc97114d
PWJ		 3887 if (ixgbe_cache_ring_rss(adapter))
3888 return;
021230d4
AV		 3889}
3890
9a799d71
AK		 3891/**
3892 * ixgbe_alloc_queues - Allocate memory for all rings
3893 * @adapter: board private structure to initialize
3894 *
3895 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3896 * number of queues at compile-time. The polling_netdev array is
3897 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3898 **/
2f90b865 3899static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3900{
3901 int i;
4a0b9ca0 3902 int orig_node = adapter->node;
9a799d71 3903
021230d4 3904 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3905 struct ixgbe_ring *ring = adapter->tx_ring[i];
3906 if (orig_node == -1) {
3907 int cur_node = next_online_node(adapter->node);
3908 if (cur_node == MAX_NUMNODES)
3909 cur_node = first_online_node;
3910 adapter->node = cur_node;
3911 }
3912 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3913 adapter->node);
3914 if (!ring)
3915 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3916 if (!ring)
3917 goto err_tx_ring_allocation;
3918 ring->count = adapter->tx_ring_count;
3919 ring->queue_index = i;
3920 ring->numa_node = adapter->node;
3921
3922 adapter->tx_ring[i] = ring;
021230d4 3923 }
b9804972 3924
4a0b9ca0
PW		 3925 /* Restore the adapter's original node */
3926 adapter->node = orig_node;
3927
9a799d71 3928 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3929 struct ixgbe_ring *ring = adapter->rx_ring[i];
3930 if (orig_node == -1) {
3931 int cur_node = next_online_node(adapter->node);
3932 if (cur_node == MAX_NUMNODES)
3933 cur_node = first_online_node;
3934 adapter->node = cur_node;
3935 }
3936 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3937 adapter->node);
3938 if (!ring)
3939 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3940 if (!ring)
3941 goto err_rx_ring_allocation;
3942 ring->count = adapter->rx_ring_count;
3943 ring->queue_index = i;
3944 ring->numa_node = adapter->node;
3945
3946 adapter->rx_ring[i] = ring;
021230d4
AV		 3947 }
3948
4a0b9ca0
PW		 3949 /* Restore the adapter's original node */
3950 adapter->node = orig_node;
3951
021230d4
AV		 3952 ixgbe_cache_ring_register(adapter);
3953
3954 return 0;
3955
3956err_rx_ring_allocation:
4a0b9ca0
PW		 3957 for (i = 0; i < adapter->num_tx_queues; i++)
3958 kfree(adapter->tx_ring[i]);
021230d4
AV		 3959err_tx_ring_allocation:
3960 return -ENOMEM;
3961}
3962
3963/**
3964 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3965 * @adapter: board private structure to initialize
3966 *
3967 * Attempt to configure the interrupts using the best available
3968 * capabilities of the hardware and the kernel.
3969 **/
feea6a57 3970static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3971{
8be0e467 3972 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3973 int err = 0;
3974 int vector, v_budget;
3975
3976 /*
3977 * It's easy to be greedy for MSI-X vectors, but it really
3978 * doesn't do us much good if we have a lot more vectors
3979 * than CPU's. So let's be conservative and only ask for
342bde1b 3980 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3981 */
3982 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3983 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3984
3985 /*
3986 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3987 * hw.mac->max_msix_vectors vectors. With features
3988 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3989 * descriptor queues supported by our device. Thus, we cap it off in
3990 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3991 */
8be0e467 3992 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3993
3994 /* A failure in MSI-X entry allocation isn't fatal, but it does
3995 * mean we disable MSI-X capabilities of the adapter. */
3996 adapter->msix_entries = kcalloc(v_budget,
b4617240 3997 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3998 if (adapter->msix_entries) {
3999 for (vector = 0; vector < v_budget; vector++)
4000 adapter->msix_entries[vector].entry = vector;
021230d4 4001
7a921c93 4002 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4003
7a921c93
AD		 4004 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4005 goto out;
4006 }
021230d4 4007
7a921c93
AD		 4008 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4009 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4010 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4011 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4012 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4013 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4014 ixgbe_disable_sriov(adapter);
4015
7a921c93 4016 ixgbe_set_num_queues(adapter);
021230d4 4017
021230d4
AV		 4018 err = pci_enable_msi(adapter->pdev);
4019 if (!err) {
4020 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4021 } else {
4022 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 4023 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4024 /* reset err */
4025 err = 0;
4026 }
4027
4028out:
021230d4
AV		 4029 return err;
4030}
4031
7a921c93
AD		 4032/**
4033 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4034 * @adapter: board private structure to initialize
4035 *
4036 * We allocate one q_vector per queue interrupt. If allocation fails we
4037 * return -ENOMEM.
4038 **/
4039static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4040{
4041 int q_idx, num_q_vectors;
4042 struct ixgbe_q_vector *q_vector;
4043 int napi_vectors;
4044 int (*poll)(struct napi_struct *, int);
4045
4046 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4047 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4048 napi_vectors = adapter->num_rx_queues;
91281fd3 4049 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4050 } else {
4051 num_q_vectors = 1;
4052 napi_vectors = 1;
4053 poll = &ixgbe_poll;
4054 }
4055
4056 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4057 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4058 GFP_KERNEL, adapter->node);
4059 if (!q_vector)
4060 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4061 GFP_KERNEL);
7a921c93
AD		 4062 if (!q_vector)
4063 goto err_out;
4064 q_vector->adapter = adapter;
f7554a2b
NS		 4065 if (q_vector->txr_count && !q_vector->rxr_count)
4066 q_vector->eitr = adapter->tx_eitr_param;
4067 else
4068 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4069 q_vector->v_idx = q_idx;
91281fd3 4070 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4071 adapter->q_vector[q_idx] = q_vector;
4072 }
4073
4074 return 0;
4075
4076err_out:
4077 while (q_idx) {
4078 q_idx--;
4079 q_vector = adapter->q_vector[q_idx];
4080 netif_napi_del(&q_vector->napi);
4081 kfree(q_vector);
4082 adapter->q_vector[q_idx] = NULL;
4083 }
4084 return -ENOMEM;
4085}
4086
4087/**
4088 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4089 * @adapter: board private structure to initialize
4090 *
4091 * This function frees the memory allocated to the q_vectors. In addition if
4092 * NAPI is enabled it will delete any references to the NAPI struct prior
4093 * to freeing the q_vector.
4094 **/
4095static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4096{
4097 int q_idx, num_q_vectors;
7a921c93 4098
91281fd3 4099 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4100 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4101 else
7a921c93 4102 num_q_vectors = 1;
7a921c93
AD		 4103
4104 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4105 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4106 adapter->q_vector[q_idx] = NULL;
91281fd3 4107 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4108 kfree(q_vector);
4109 }
4110}
4111
7b25cdba 4112static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4113{
4114 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4115 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4116 pci_disable_msix(adapter->pdev);
4117 kfree(adapter->msix_entries);
4118 adapter->msix_entries = NULL;
4119 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4120 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4121 pci_disable_msi(adapter->pdev);
4122 }
4123 return;
4124}
4125
4126/**
4127 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4128 * @adapter: board private structure to initialize
4129 *
4130 * We determine which interrupt scheme to use based on...
4131 * - Kernel support (MSI, MSI-X)
4132 * - which can be user-defined (via MODULE_PARAM)
4133 * - Hardware queue count (num_*_queues)
4134 * - defined by miscellaneous hardware support/features (RSS, etc.)
4135 **/
2f90b865 4136int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4137{
4138 int err;
4139
4140 /* Number of supported queues */
4141 ixgbe_set_num_queues(adapter);
4142
021230d4
AV		 4143 err = ixgbe_set_interrupt_capability(adapter);
4144 if (err) {
4145 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4146 goto err_set_interrupt;
9a799d71
AK		 4147 }
4148
7a921c93
AD		 4149 err = ixgbe_alloc_q_vectors(adapter);
4150 if (err) {
4151 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4152 "vectors\n");
4153 goto err_alloc_q_vectors;
4154 }
4155
4156 err = ixgbe_alloc_queues(adapter);
4157 if (err) {
4158 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4159 goto err_alloc_queues;
4160 }
4161
021230d4 4162 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4163 "Tx Queue count = %u\n",
4164 (adapter->num_rx_queues > 1) ? "Enabled" :
4165 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4166
4167 set_bit(__IXGBE_DOWN, &adapter->state);
4168
9a799d71 4169 return 0;
021230d4 4170
7a921c93
AD		 4171err_alloc_queues:
4172 ixgbe_free_q_vectors(adapter);
4173err_alloc_q_vectors:
4174 ixgbe_reset_interrupt_capability(adapter);
021230d4 4175err_set_interrupt:
7a921c93
AD		 4176 return err;
4177}
4178
4179/**
4180 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4181 * @adapter: board private structure to clear interrupt scheme on
4182 *
4183 * We go through and clear interrupt specific resources and reset the structure
4184 * to pre-load conditions
4185 **/
4186void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4187{
4a0b9ca0
PW		 4188 int i;
4189
4190 for (i = 0; i < adapter->num_tx_queues; i++) {
4191 kfree(adapter->tx_ring[i]);
4192 adapter->tx_ring[i] = NULL;
4193 }
4194 for (i = 0; i < adapter->num_rx_queues; i++) {
4195 kfree(adapter->rx_ring[i]);
4196 adapter->rx_ring[i] = NULL;
4197 }
7a921c93
AD		 4198
4199 ixgbe_free_q_vectors(adapter);
4200 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4201}
4202
c4900be0
DS		 4203/**
4204 * ixgbe_sfp_timer - worker thread to find a missing module
4205 * @data: pointer to our adapter struct
4206 **/
4207static void ixgbe_sfp_timer(unsigned long data)
4208{
4209 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4210
4df10466
JB		 4211 /*
4212 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4213 * delays that sfp+ detection requires
4214 */
4215 schedule_work(&adapter->sfp_task);
4216}
4217
4218/**
4219 * ixgbe_sfp_task - worker thread to find a missing module
4220 * @work: pointer to work_struct containing our data
4221 **/
4222static void ixgbe_sfp_task(struct work_struct *work)
4223{
4224 struct ixgbe_adapter *adapter = container_of(work,
4225 struct ixgbe_adapter,
4226 sfp_task);
4227 struct ixgbe_hw *hw = &adapter->hw;
4228
4229 if ((hw->phy.type == ixgbe_phy_nl) &&
4230 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4231 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4232 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4233 goto reschedule;
4234 ret = hw->phy.ops.reset(hw);
4235 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4236 dev_err(&adapter->pdev->dev, "failed to initialize "
4237 "because an unsupported SFP+ module type "
4238 "was detected.\n"
4239 "Reload the driver after installing a "
4240 "supported module.\n");
c4900be0
DS		 4241 unregister_netdev(adapter->netdev);
4242 } else {
4243 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4244 hw->phy.sfp_type);
4245 }
4246 /* don't need this routine any more */
4247 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4248 }
4249 return;
4250reschedule:
4251 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4252 mod_timer(&adapter->sfp_timer,
4253 round_jiffies(jiffies + (2 * HZ)));
4254}
4255
9a799d71
AK		 4256/**
4257 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4258 * @adapter: board private structure to initialize
4259 *
4260 * ixgbe_sw_init initializes the Adapter private data structure.
4261 * Fields are initialized based on PCI device information and
4262 * OS network device settings (MTU size).
4263 **/
4264static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4265{
4266 struct ixgbe_hw *hw = &adapter->hw;
4267 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4268 struct net_device *dev = adapter->netdev;
021230d4 4269 unsigned int rss;
7a6b6f51 4270#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4271 int j;
4272 struct tc_configuration *tc;
4273#endif
021230d4 4274
c44ade9e
JB		 4275 /* PCI config space info */
4276
4277 hw->vendor_id = pdev->vendor;
4278 hw->device_id = pdev->device;
4279 hw->revision_id = pdev->revision;
4280 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4281 hw->subsystem_device_id = pdev->subsystem_device;
4282
021230d4
AV		 4283 /* Set capability flags */
4284 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4285 adapter->ring_feature[RING_F_RSS].indices = rss;
4286 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4287 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4288 if (hw->mac.type == ixgbe_mac_82598EB) {
4289 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4290 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4291 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4292 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4293 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4294 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4295 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4296 if (dev->features & NETIF_F_NTUPLE) {
4297 /* Flow Director perfect filter enabled */
4298 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4299 adapter->atr_sample_rate = 0;
4300 spin_lock_init(&adapter->fdir_perfect_lock);
4301 } else {
4302 /* Flow Director hash filters enabled */
4303 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4304 adapter->atr_sample_rate = 20;
4305 }
c4cf55e5
PWJ		 4306 adapter->ring_feature[RING_F_FDIR].indices =
4307 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4308 adapter->fdir_pballoc = 0;
eacd73f7 4309#ifdef IXGBE_FCOE
0d551589
YZ		 4310 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4311 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4312 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4313#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4314 /* Default traffic class to use for FCoE */
4315 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4316#endif
eacd73f7 4317#endif /* IXGBE_FCOE */
f8212f97 4318 }
2f90b865 4319
7a6b6f51 4320#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4321 /* Configure DCB traffic classes */
4322 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4323 tc = &adapter->dcb_cfg.tc_config[j];
4324 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4325 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4326 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4327 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4328 tc->dcb_pfc = pfc_disabled;
4329 }
4330 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4331 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4332 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4333 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4334 adapter->dcb_cfg.round_robin_enable = false;
4335 adapter->dcb_set_bitmap = 0x00;
4336 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4337 adapter->ring_feature[RING_F_DCB].indices);
4338
4339#endif
9a799d71
AK		 4340
4341 /* default flow control settings */
cd7664f6 4342 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4343 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4344#ifdef CONFIG_DCB
4345 adapter->last_lfc_mode = hw->fc.current_mode;
4346#endif
2b9ade93
JB		 4347 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4348 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4349 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4350 hw->fc.send_xon = true;
71fd570b 4351 hw->fc.disable_fc_autoneg = false;
9a799d71 4352
30efa5a3 4353 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4354 adapter->rx_itr_setting = 1;
4355 adapter->rx_eitr_param = 20000;
4356 adapter->tx_itr_setting = 1;
4357 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4358
4359 /* set defaults for eitr in MegaBytes */
4360 adapter->eitr_low = 10;
4361 adapter->eitr_high = 20;
4362
4363 /* set default ring sizes */
4364 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4365 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4366
9a799d71 4367 /* initialize eeprom parameters */
c44ade9e 4368 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4369 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4370 return -EIO;
4371 }
4372
021230d4 4373 /* enable rx csum by default */
9a799d71
AK		 4374 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4375
1a6c14a2
JB		 4376 /* get assigned NUMA node */
4377 adapter->node = dev_to_node(&pdev->dev);
4378
9a799d71
AK		 4379 set_bit(__IXGBE_DOWN, &adapter->state);
4380
4381 return 0;
4382}
4383
4384/**
4385 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4386 * @adapter: board private structure
3a581073 4387 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4388 *
4389 * Return 0 on success, negative on failure
4390 **/
4391int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4392 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4393{
4394 struct pci_dev *pdev = adapter->pdev;
4395 int size;
4396
3a581073 4397 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4398 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4399 if (!tx_ring->tx_buffer_info)
4400 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4401 if (!tx_ring->tx_buffer_info)
4402 goto err;
3a581073 4403 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4404
4405 /* round up to nearest 4K */
12207e49 4406 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4407 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4408
1b507730
NN		 4409 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4410 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4411 if (!tx_ring->desc)
4412 goto err;
9a799d71 4413
3a581073
JB		 4414 tx_ring->next_to_use = 0;
4415 tx_ring->next_to_clean = 0;
4416 tx_ring->work_limit = tx_ring->count;
9a799d71 4417 return 0;
e01c31a5
JB		 4418
4419err:
4420 vfree(tx_ring->tx_buffer_info);
4421 tx_ring->tx_buffer_info = NULL;
4422 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4423 "descriptor ring\n");
4424 return -ENOMEM;
9a799d71
AK		 4425}
4426
69888674
AD		 4427/**
4428 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4429 * @adapter: board private structure
4430 *
4431 * If this function returns with an error, then it's possible one or
4432 * more of the rings is populated (while the rest are not). It is the
4433 * callers duty to clean those orphaned rings.
4434 *
4435 * Return 0 on success, negative on failure
4436 **/
4437static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4438{
4439 int i, err = 0;
4440
4441 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4442 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4443 if (!err)
4444 continue;
4445 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4446 break;
4447 }
4448
4449 return err;
4450}
4451
9a799d71
AK		 4452/**
4453 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4454 * @adapter: board private structure
3a581073 4455 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4456 *
4457 * Returns 0 on success, negative on failure
4458 **/
4459int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4460 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4461{
4462 struct pci_dev *pdev = adapter->pdev;
021230d4 4463 int size;
9a799d71 4464
3a581073 4465 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4466 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4467 if (!rx_ring->rx_buffer_info)
4468 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4469 if (!rx_ring->rx_buffer_info) {
9a799d71 4470 DPRINTK(PROBE, ERR,
b4617240 4471 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4472 goto alloc_failed;
9a799d71 4473 }
3a581073 4474 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4475
9a799d71 4476 /* Round up to nearest 4K */
3a581073
JB		 4477 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4478 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4479
1b507730
NN		 4480 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4481 &rx_ring->dma, GFP_KERNEL);
9a799d71 4482
3a581073 4483 if (!rx_ring->desc) {
9a799d71 4484 DPRINTK(PROBE, ERR,
b4617240 4485 "Memory allocation failed for the rx desc ring\n");
3a581073 4486 vfree(rx_ring->rx_buffer_info);
177db6ff 4487 goto alloc_failed;
9a799d71
AK		 4488 }
4489
3a581073
JB		 4490 rx_ring->next_to_clean = 0;
4491 rx_ring->next_to_use = 0;
9a799d71
AK		 4492
4493 return 0;
177db6ff
MC		 4494
4495alloc_failed:
177db6ff 4496 return -ENOMEM;
9a799d71
AK		 4497}
4498
69888674
AD		 4499/**
4500 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4501 * @adapter: board private structure
4502 *
4503 * If this function returns with an error, then it's possible one or
4504 * more of the rings is populated (while the rest are not). It is the
4505 * callers duty to clean those orphaned rings.
4506 *
4507 * Return 0 on success, negative on failure
4508 **/
4509
4510static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4511{
4512 int i, err = 0;
4513
4514 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4515 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4516 if (!err)
4517 continue;
4518 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4519 break;
4520 }
4521
4522 return err;
4523}
4524
9a799d71
AK		 4525/**
4526 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4527 * @adapter: board private structure
4528 * @tx_ring: Tx descriptor ring for a specific queue
4529 *
4530 * Free all transmit software resources
4531 **/
c431f97e
JB		 4532void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4533 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4534{
4535 struct pci_dev *pdev = adapter->pdev;
4536
4537 ixgbe_clean_tx_ring(adapter, tx_ring);
4538
4539 vfree(tx_ring->tx_buffer_info);
4540 tx_ring->tx_buffer_info = NULL;
4541
1b507730
NN		 4542 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4543 tx_ring->dma);
9a799d71
AK		 4544
4545 tx_ring->desc = NULL;
4546}
4547
4548/**
4549 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4550 * @adapter: board private structure
4551 *
4552 * Free all transmit software resources
4553 **/
4554static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4555{
4556 int i;
4557
4558 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4559 if (adapter->tx_ring[i]->desc)
4560 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4561}
4562
4563/**
b4617240 4564 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4565 * @adapter: board private structure
4566 * @rx_ring: ring to clean the resources from
4567 *
4568 * Free all receive software resources
4569 **/
c431f97e
JB		 4570void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4571 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4572{
4573 struct pci_dev *pdev = adapter->pdev;
4574
4575 ixgbe_clean_rx_ring(adapter, rx_ring);
4576
4577 vfree(rx_ring->rx_buffer_info);
4578 rx_ring->rx_buffer_info = NULL;
4579
1b507730
NN		 4580 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4581 rx_ring->dma);
9a799d71
AK		 4582
4583 rx_ring->desc = NULL;
4584}
4585
4586/**
4587 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4588 * @adapter: board private structure
4589 *
4590 * Free all receive software resources
4591 **/
4592static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4593{
4594 int i;
4595
4596 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4597 if (adapter->rx_ring[i]->desc)
4598 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4599}
4600
9a799d71
AK		 4601/**
4602 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4603 * @netdev: network interface device structure
4604 * @new_mtu: new value for maximum frame size
4605 *
4606 * Returns 0 on success, negative on failure
4607 **/
4608static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4609{
4610 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4611 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4612
42c783c5
JB		 4613 /* MTU < 68 is an error and causes problems on some kernels */
4614 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4615 return -EINVAL;
4616
021230d4 4617 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4618 netdev->mtu, new_mtu);
021230d4 4619 /* must set new MTU before calling down or up */
9a799d71
AK		 4620 netdev->mtu = new_mtu;
4621
d4f80882
AV		 4622 if (netif_running(netdev))
4623 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4624
4625 return 0;
4626}
4627
4628/**
4629 * ixgbe_open - Called when a network interface is made active
4630 * @netdev: network interface device structure
4631 *
4632 * Returns 0 on success, negative value on failure
4633 *
4634 * The open entry point is called when a network interface is made
4635 * active by the system (IFF_UP). At this point all resources needed
4636 * for transmit and receive operations are allocated, the interrupt
4637 * handler is registered with the OS, the watchdog timer is started,
4638 * and the stack is notified that the interface is ready.
4639 **/
4640static int ixgbe_open(struct net_device *netdev)
4641{
4642 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4643 int err;
4bebfaa5
AK		 4644
4645 /* disallow open during test */
4646 if (test_bit(__IXGBE_TESTING, &adapter->state))
4647 return -EBUSY;
9a799d71 4648
54386467
JB		 4649 netif_carrier_off(netdev);
4650
9a799d71
AK		 4651 /* allocate transmit descriptors */
4652 err = ixgbe_setup_all_tx_resources(adapter);
4653 if (err)
4654 goto err_setup_tx;
4655
9a799d71
AK		 4656 /* allocate receive descriptors */
4657 err = ixgbe_setup_all_rx_resources(adapter);
4658 if (err)
4659 goto err_setup_rx;
4660
4661 ixgbe_configure(adapter);
4662
021230d4 4663 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4664 if (err)
4665 goto err_req_irq;
4666
9a799d71
AK		 4667 err = ixgbe_up_complete(adapter);
4668 if (err)
4669 goto err_up;
4670
d55b53ff
JK		 4671 netif_tx_start_all_queues(netdev);
4672
9a799d71
AK		 4673 return 0;
4674
4675err_up:
5eba3699 4676 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4677 ixgbe_free_irq(adapter);
4678err_req_irq:
9a799d71 4679err_setup_rx:
a20a1199 4680 ixgbe_free_all_rx_resources(adapter);
9a799d71 4681err_setup_tx:
a20a1199 4682 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4683 ixgbe_reset(adapter);
4684
4685 return err;
4686}
4687
4688/**
4689 * ixgbe_close - Disables a network interface
4690 * @netdev: network interface device structure
4691 *
4692 * Returns 0, this is not allowed to fail
4693 *
4694 * The close entry point is called when an interface is de-activated
4695 * by the OS. The hardware is still under the drivers control, but
4696 * needs to be disabled. A global MAC reset is issued to stop the
4697 * hardware, and all transmit and receive resources are freed.
4698 **/
4699static int ixgbe_close(struct net_device *netdev)
4700{
4701 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4702
4703 ixgbe_down(adapter);
4704 ixgbe_free_irq(adapter);
4705
4706 ixgbe_free_all_tx_resources(adapter);
4707 ixgbe_free_all_rx_resources(adapter);
4708
5eba3699 4709 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4710
4711 return 0;
4712}
4713
b3c8b4ba
AD		 4714#ifdef CONFIG_PM
4715static int ixgbe_resume(struct pci_dev *pdev)
4716{
4717 struct net_device *netdev = pci_get_drvdata(pdev);
4718 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4719 u32 err;
4720
4721 pci_set_power_state(pdev, PCI_D0);
4722 pci_restore_state(pdev);
656ab817
DS		 4723 /*
4724 * pci_restore_state clears dev->state_saved so call
4725 * pci_save_state to restore it.
4726 */
4727 pci_save_state(pdev);
9ce77666 4728
4729 err = pci_enable_device_mem(pdev);
b3c8b4ba 4730 if (err) {
69888674 4731 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4732 "suspend\n");
4733 return err;
4734 }
4735 pci_set_master(pdev);
4736
dd4d8ca6 4737 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4738
4739 err = ixgbe_init_interrupt_scheme(adapter);
4740 if (err) {
4741 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4742 "device\n");
4743 return err;
4744 }
4745
b3c8b4ba
AD		 4746 ixgbe_reset(adapter);
4747
495dce12
WJP		 4748 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4749
b3c8b4ba
AD		 4750 if (netif_running(netdev)) {
4751 err = ixgbe_open(adapter->netdev);
4752 if (err)
4753 return err;
4754 }
4755
4756 netif_device_attach(netdev);
4757
4758 return 0;
4759}
b3c8b4ba 4760#endif /* CONFIG_PM */
9d8d05ae
RW		 4761
4762static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4763{
4764 struct net_device *netdev = pci_get_drvdata(pdev);
4765 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4766 struct ixgbe_hw *hw = &adapter->hw;
4767 u32 ctrl, fctrl;
4768 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4769#ifdef CONFIG_PM
4770 int retval = 0;
4771#endif
4772
4773 netif_device_detach(netdev);
4774
4775 if (netif_running(netdev)) {
4776 ixgbe_down(adapter);
4777 ixgbe_free_irq(adapter);
4778 ixgbe_free_all_tx_resources(adapter);
4779 ixgbe_free_all_rx_resources(adapter);
4780 }
7a921c93 4781 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4782
4783#ifdef CONFIG_PM
4784 retval = pci_save_state(pdev);
4785 if (retval)
4786 return retval;
4df10466 4787
b3c8b4ba 4788#endif
e8e26350
PW		 4789 if (wufc) {
4790 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4791
e8e26350
PW		 4792 /* turn on all-multi mode if wake on multicast is enabled */
4793 if (wufc & IXGBE_WUFC_MC) {
4794 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4795 fctrl |= IXGBE_FCTRL_MPE;
4796 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4797 }
4798
4799 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4800 ctrl |= IXGBE_CTRL_GIO_DIS;
4801 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4802
4803 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4804 } else {
4805 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4806 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4807 }
4808
dd4d8ca6
DS		 4809 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4810 pci_wake_from_d3(pdev, true);
4811 else
4812 pci_wake_from_d3(pdev, false);
b3c8b4ba 4813
9d8d05ae
RW		 4814 *enable_wake = !!wufc;
4815
b3c8b4ba
AD		 4816 ixgbe_release_hw_control(adapter);
4817
4818 pci_disable_device(pdev);
4819
9d8d05ae
RW		 4820 return 0;
4821}
4822
4823#ifdef CONFIG_PM
4824static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4825{
4826 int retval;
4827 bool wake;
4828
4829 retval = __ixgbe_shutdown(pdev, &wake);
4830 if (retval)
4831 return retval;
4832
4833 if (wake) {
4834 pci_prepare_to_sleep(pdev);
4835 } else {
4836 pci_wake_from_d3(pdev, false);
4837 pci_set_power_state(pdev, PCI_D3hot);
4838 }
b3c8b4ba
AD		 4839
4840 return 0;
4841}
9d8d05ae 4842#endif /* CONFIG_PM */
b3c8b4ba
AD		 4843
4844static void ixgbe_shutdown(struct pci_dev *pdev)
4845{
9d8d05ae
RW		 4846 bool wake;
4847
4848 __ixgbe_shutdown(pdev, &wake);
4849
4850 if (system_state == SYSTEM_POWER_OFF) {
4851 pci_wake_from_d3(pdev, wake);
4852 pci_set_power_state(pdev, PCI_D3hot);
4853 }
b3c8b4ba
AD		 4854}
4855
9a799d71
AK		 4856/**
4857 * ixgbe_update_stats - Update the board statistics counters.
4858 * @adapter: board private structure
4859 **/
4860void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4861{
2d86f139 4862 struct net_device *netdev = adapter->netdev;
9a799d71 4863 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4864 u64 total_mpc = 0;
4865 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4866 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4867
94b982b2 4868 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4869 u64 rsc_count = 0;
94b982b2 4870 u64 rsc_flush = 0;
d51019a4
PW		 4871 for (i = 0; i < 16; i++)
4872 adapter->hw_rx_no_dma_resources +=
4873 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4874 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4875 rsc_count += adapter->rx_ring[i]->rsc_count;
4876 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4877 }
4878 adapter->rsc_total_count = rsc_count;
4879 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4880 }
4881
7ca3bc58
JB		 4882 /* gather some stats to the adapter struct that are per queue */
4883 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4884 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4885 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4886
4887 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4888 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4889 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4890
9a799d71 4891 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4892 for (i = 0; i < 8; i++) {
4893 /* for packet buffers not used, the register should read 0 */
4894 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4895 missed_rx += mpc;
4896 adapter->stats.mpc[i] += mpc;
4897 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4898 if (hw->mac.type == ixgbe_mac_82598EB)
4899 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4900 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4901 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4902 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4903 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4904 if (hw->mac.type == ixgbe_mac_82599EB) {
4905 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4906 IXGBE_PXONRXCNT(i));
4907 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4908 IXGBE_PXOFFRXCNT(i));
4909 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4910 } else {
4911 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4912 IXGBE_PXONRXC(i));
4913 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4914 IXGBE_PXOFFRXC(i));
4915 }
2f90b865
AD		 4916 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4917 IXGBE_PXONTXC(i));
2f90b865 4918 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4919 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4920 }
4921 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4922 /* work around hardware counting issue */
4923 adapter->stats.gprc -= missed_rx;
4924
4925 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4926 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4927 u64 tmp;
e8e26350 4928 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4929 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4930 adapter->stats.gorc += (tmp << 32);
e8e26350 4931 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4932 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4933 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4934 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4935 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4936 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4937 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4938 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4939 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4940#ifdef IXGBE_FCOE
4941 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4942 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4943 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4944 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4945 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4946 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4947#endif /* IXGBE_FCOE */
e8e26350
PW		 4948 } else {
4949 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4950 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4951 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4952 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4953 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4954 }
9a799d71
AK		 4955 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4956 adapter->stats.bprc += bprc;
4957 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4958 if (hw->mac.type == ixgbe_mac_82598EB)
4959 adapter->stats.mprc -= bprc;
9a799d71
AK		 4960 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4961 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4962 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4963 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4964 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4965 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4966 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4967 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4968 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4969 adapter->stats.lxontxc += lxon;
4970 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4971 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4972 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4973 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4974 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4975 /*
4976 * 82598 errata - tx of flow control packets is included in tx counters
4977 */
4978 xon_off_tot = lxon + lxoff;
4979 adapter->stats.gptc -= xon_off_tot;
4980 adapter->stats.mptc -= xon_off_tot;
4981 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4982 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4983 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4984 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4985 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4986 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4987 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4988 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4989 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4990 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4991 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4992 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4993 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4994
4995 /* Fill out the OS statistics structure */
2d86f139 4996 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4997
4998 /* Rx Errors */
2d86f139 4999 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5000 adapter->stats.rlec;
2d86f139
AK		 5001 netdev->stats.rx_dropped = 0;
5002 netdev->stats.rx_length_errors = adapter->stats.rlec;
5003 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5004 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5005}
5006
5007/**
5008 * ixgbe_watchdog - Timer Call-back
5009 * @data: pointer to adapter cast into an unsigned long
5010 **/
5011static void ixgbe_watchdog(unsigned long data)
5012{
5013 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5014 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5015 u64 eics = 0;
5016 int i;
cf8280ee 5017
fe49f04a
AD		 5018 /*
5019 * Do the watchdog outside of interrupt context due to the lovely
5020 * delays that some of the newer hardware requires
5021 */
22d5a71b 5022
fe49f04a
AD		 5023 if (test_bit(__IXGBE_DOWN, &adapter->state))
5024 goto watchdog_short_circuit;
22d5a71b 5025
fe49f04a
AD		 5026 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5027 /*
5028 * for legacy and MSI interrupts don't set any bits
5029 * that are enabled for EIAM, because this operation
5030 * would set *both* EIMS and EICS for any bit in EIAM
5031 */
5032 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5033 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5034 goto watchdog_reschedule;
5035 }
5036
5037 /* get one bit for every active tx/rx interrupt vector */
5038 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5039 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5040 if (qv->rxr_count || qv->txr_count)
5041 eics |= ((u64)1 << i);
cf8280ee 5042 }
9a799d71 5043
fe49f04a
AD		 5044 /* Cause software interrupt to ensure rx rings are cleaned */
5045 ixgbe_irq_rearm_queues(adapter, eics);
5046
5047watchdog_reschedule:
5048 /* Reset the timer */
5049 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5050
5051watchdog_short_circuit:
cf8280ee
JB		 5052 schedule_work(&adapter->watchdog_task);
5053}
5054
e8e26350
PW		 5055/**
5056 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5057 * @work: pointer to work_struct containing our data
5058 **/
5059static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5060{
5061 struct ixgbe_adapter *adapter = container_of(work,
5062 struct ixgbe_adapter,
5063 multispeed_fiber_task);
5064 struct ixgbe_hw *hw = &adapter->hw;
5065 u32 autoneg;
8620a103 5066 bool negotiation;
e8e26350
PW		 5067
5068 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5069 autoneg = hw->phy.autoneg_advertised;
5070 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5071 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5072 hw->mac.autotry_restart = false;
8620a103
MC		 5073 if (hw->mac.ops.setup_link)
5074 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5075 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5076 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5077}
5078
5079/**
5080 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5081 * @work: pointer to work_struct containing our data
5082 **/
5083static void ixgbe_sfp_config_module_task(struct work_struct *work)
5084{
5085 struct ixgbe_adapter *adapter = container_of(work,
5086 struct ixgbe_adapter,
5087 sfp_config_module_task);
5088 struct ixgbe_hw *hw = &adapter->hw;
5089 u32 err;
5090
5091 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5092
5093 /* Time for electrical oscillations to settle down */
5094 msleep(100);
e8e26350 5095 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5096
e8e26350 5097 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5098 dev_err(&adapter->pdev->dev, "failed to initialize because "
5099 "an unsupported SFP+ module type was detected.\n"
5100 "Reload the driver after installing a supported "
5101 "module.\n");
63d6e1d8 5102 unregister_netdev(adapter->netdev);
e8e26350
PW		 5103 return;
5104 }
5105 hw->mac.ops.setup_sfp(hw);
5106
8d1c3c07 5107 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5108 /* This will also work for DA Twinax connections */
5109 schedule_work(&adapter->multispeed_fiber_task);
5110 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5111}
5112
c4cf55e5
PWJ		 5113/**
5114 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5115 * @work: pointer to work_struct containing our data
5116 **/
5117static void ixgbe_fdir_reinit_task(struct work_struct *work)
5118{
5119 struct ixgbe_adapter *adapter = container_of(work,
5120 struct ixgbe_adapter,
5121 fdir_reinit_task);
5122 struct ixgbe_hw *hw = &adapter->hw;
5123 int i;
5124
5125 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5126 for (i = 0; i < adapter->num_tx_queues; i++)
5127 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5128 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5129 } else {
5130 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
d6dbee86 5131 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5132 }
5133 /* Done FDIR Re-initialization, enable transmits */
5134 netif_tx_start_all_queues(adapter->netdev);
5135}
5136
10eec955
JF		 5137static DEFINE_MUTEX(ixgbe_watchdog_lock);
5138
cf8280ee 5139/**
69888674
AD		 5140 * ixgbe_watchdog_task - worker thread to bring link up
5141 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5142 **/
5143static void ixgbe_watchdog_task(struct work_struct *work)
5144{
5145 struct ixgbe_adapter *adapter = container_of(work,
5146 struct ixgbe_adapter,
5147 watchdog_task);
5148 struct net_device *netdev = adapter->netdev;
5149 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5150 u32 link_speed;
5151 bool link_up;
bc59fcda
NS		 5152 int i;
5153 struct ixgbe_ring *tx_ring;
5154 int some_tx_pending = 0;
cf8280ee 5155
10eec955
JF		 5156 mutex_lock(&ixgbe_watchdog_lock);
5157
5158 link_up = adapter->link_up;
5159 link_speed = adapter->link_speed;
cf8280ee
JB		 5160
5161 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5162 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5163 if (link_up) {
5164#ifdef CONFIG_DCB
5165 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5166 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5167 hw->mac.ops.fc_enable(hw, i);
264857b8 5168 } else {
620fa036 5169 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5170 }
5171#else
620fa036 5172 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5173#endif
5174 }
5175
cf8280ee
JB		 5176 if (link_up ||
5177 time_after(jiffies, (adapter->link_check_timeout +
5178 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5179 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5180 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5181 }
5182 adapter->link_up = link_up;
5183 adapter->link_speed = link_speed;
5184 }
9a799d71
AK		 5185
5186 if (link_up) {
5187 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5188 bool flow_rx, flow_tx;
5189
5190 if (hw->mac.type == ixgbe_mac_82599EB) {
5191 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5192 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5193 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5194 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5195 } else {
5196 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5197 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5198 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5199 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5200 }
5201
a46e534b
JK		 5202 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5203 "Flow Control: %s\n",
5204 netdev->name,
5205 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5206 "10 Gbps" :
5207 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5208 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5209 ((flow_rx && flow_tx) ? "RX/TX" :
5210 (flow_rx ? "RX" :
5211 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5212
5213 netif_carrier_on(netdev);
9a799d71
AK		 5214 } else {
5215 /* Force detection of hung controller */
5216 adapter->detect_tx_hung = true;
5217 }
5218 } else {
cf8280ee
JB		 5219 adapter->link_up = false;
5220 adapter->link_speed = 0;
9a799d71 5221 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5222 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5223 netdev->name);
9a799d71 5224 netif_carrier_off(netdev);
9a799d71
AK		 5225 }
5226 }
5227
bc59fcda
NS		 5228 if (!netif_carrier_ok(netdev)) {
5229 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5230 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5231 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5232 some_tx_pending = 1;
5233 break;
5234 }
5235 }
5236
5237 if (some_tx_pending) {
5238 /* We've lost link, so the controller stops DMA,
5239 * but we've got queued Tx work that's never going
5240 * to get done, so reset controller to flush Tx.
5241 * (Do the reset outside of interrupt context).
5242 */
5243 schedule_work(&adapter->reset_task);
5244 }
5245 }
5246
9a799d71 5247 ixgbe_update_stats(adapter);
10eec955 5248 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5249}
5250
9a799d71 5251static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5252 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5253 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5254{
5255 struct ixgbe_adv_tx_context_desc *context_desc;
5256 unsigned int i;
5257 int err;
5258 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5259 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5260 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5261
5262 if (skb_is_gso(skb)) {
5263 if (skb_header_cloned(skb)) {
5264 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5265 if (err)
5266 return err;
5267 }
5268 l4len = tcp_hdrlen(skb);
5269 *hdr_len += l4len;
5270
8327d000 5271 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5272 struct iphdr *iph = ip_hdr(skb);
5273 iph->tot_len = 0;
5274 iph->check = 0;
5275 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5276 iph->daddr, 0,
5277 IPPROTO_TCP,
5278 0);
8e1e8a47 5279 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5280 ipv6_hdr(skb)->payload_len = 0;
5281 tcp_hdr(skb)->check =
5282 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5283 &ipv6_hdr(skb)->daddr,
5284 0, IPPROTO_TCP, 0);
9a799d71
AK		 5285 }
5286
5287 i = tx_ring->next_to_use;
5288
5289 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5290 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5291
5292 /* VLAN MACLEN IPLEN */
5293 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5294 vlan_macip_lens |=
5295 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5296 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5297 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5298 *hdr_len += skb_network_offset(skb);
5299 vlan_macip_lens |=
5300 (skb_transport_header(skb) - skb_network_header(skb));
5301 *hdr_len +=
5302 (skb_transport_header(skb) - skb_network_header(skb));
5303 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5304 context_desc->seqnum_seed = 0;
5305
5306 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5307 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5308 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5309
8327d000 5310 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5311 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5312 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5313 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5314
5315 /* MSS L4LEN IDX */
9f8cdf4f 5316 mss_l4len_idx =
9a799d71
AK		 5317 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5318 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5319 /* use index 1 for TSO */
5320 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5321 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5322
5323 tx_buffer_info->time_stamp = jiffies;
5324 tx_buffer_info->next_to_watch = i;
5325
5326 i++;
5327 if (i == tx_ring->count)
5328 i = 0;
5329 tx_ring->next_to_use = i;
5330
5331 return true;
5332 }
5333 return false;
5334}
5335
5336static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5337 struct ixgbe_ring *tx_ring,
5338 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5339{
5340 struct ixgbe_adv_tx_context_desc *context_desc;
5341 unsigned int i;
5342 struct ixgbe_tx_buffer *tx_buffer_info;
5343 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5344
5345 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5346 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5347 i = tx_ring->next_to_use;
5348 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5349 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5350
5351 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5352 vlan_macip_lens |=
5353 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5354 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5355 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5356 if (skb->ip_summed == CHECKSUM_PARTIAL)
5357 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5358 skb_network_header(skb));
9a799d71
AK		 5359
5360 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5361 context_desc->seqnum_seed = 0;
5362
5363 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5364 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5365
5366 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5367 __be16 protocol;
5368
5369 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5370 const struct vlan_ethhdr *vhdr =
5371 (const struct vlan_ethhdr *)skb->data;
5372
5373 protocol = vhdr->h_vlan_encapsulated_proto;
5374 } else {
5375 protocol = skb->protocol;
5376 }
5377
5378 switch (protocol) {
09640e63 5379 case cpu_to_be16(ETH_P_IP):
9a799d71 5380 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5381 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5382 type_tucmd_mlhl |=
b4617240 5383 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5384 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5385 type_tucmd_mlhl |=
5386 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5387 break;
09640e63 5388 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5389 /* XXX what about other V6 headers?? */
5390 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5391 type_tucmd_mlhl |=
b4617240 5392 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5393 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5394 type_tucmd_mlhl |=
5395 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5396 break;
41825d71
AK		 5397 default:
5398 if (unlikely(net_ratelimit())) {
5399 DPRINTK(PROBE, WARNING,
5400 "partial checksum but proto=%x!\n",
5401 skb->protocol);
5402 }
5403 break;
5404 }
9a799d71
AK		 5405 }
5406
5407 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5408 /* use index zero for tx checksum offload */
9a799d71
AK		 5409 context_desc->mss_l4len_idx = 0;
5410
5411 tx_buffer_info->time_stamp = jiffies;
5412 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5413
9a799d71
AK		 5414 i++;
5415 if (i == tx_ring->count)
5416 i = 0;
5417 tx_ring->next_to_use = i;
5418
5419 return true;
5420 }
9f8cdf4f 5421
9a799d71
AK		 5422 return false;
5423}
5424
5425static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5426 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5427 struct sk_buff *skb, u32 tx_flags,
5428 unsigned int first)
9a799d71 5429{
e5a43549 5430 struct pci_dev *pdev = adapter->pdev;
9a799d71 5431 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5432 unsigned int len;
5433 unsigned int total = skb->len;
9a799d71
AK		 5434 unsigned int offset = 0, size, count = 0, i;
5435 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5436 unsigned int f;
9a799d71
AK		 5437
5438 i = tx_ring->next_to_use;
5439
eacd73f7
YZ		 5440 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5441 /* excluding fcoe_crc_eof for FCoE */
5442 total -= sizeof(struct fcoe_crc_eof);
5443
5444 len = min(skb_headlen(skb), total);
9a799d71
AK		 5445 while (len) {
5446 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5447 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5448
5449 tx_buffer_info->length = size;
e5a43549 5450 tx_buffer_info->mapped_as_page = false;
1b507730 5451 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5452 skb->data + offset,
1b507730
NN		 5453 size, DMA_TO_DEVICE);
5454 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5455 goto dma_error;
9a799d71
AK		 5456 tx_buffer_info->time_stamp = jiffies;
5457 tx_buffer_info->next_to_watch = i;
5458
5459 len -= size;
eacd73f7 5460 total -= size;
9a799d71
AK		 5461 offset += size;
5462 count++;
44df32c5
AD		 5463
5464 if (len) {
5465 i++;
5466 if (i == tx_ring->count)
5467 i = 0;
5468 }
9a799d71
AK		 5469 }
5470
5471 for (f = 0; f < nr_frags; f++) {
5472 struct skb_frag_struct *frag;
5473
5474 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5475 len = min((unsigned int)frag->size, total);
e5a43549 5476 offset = frag->page_offset;
9a799d71
AK		 5477
5478 while (len) {
44df32c5
AD		 5479 i++;
5480 if (i == tx_ring->count)
5481 i = 0;
5482
9a799d71
AK		 5483 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5484 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5485
5486 tx_buffer_info->length = size;
1b507730 5487 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5488 frag->page,
5489 offset, size,
1b507730 5490 DMA_TO_DEVICE);
e5a43549 5491 tx_buffer_info->mapped_as_page = true;
1b507730 5492 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5493 goto dma_error;
9a799d71
AK		 5494 tx_buffer_info->time_stamp = jiffies;
5495 tx_buffer_info->next_to_watch = i;
5496
5497 len -= size;
eacd73f7 5498 total -= size;
9a799d71
AK		 5499 offset += size;
5500 count++;
9a799d71 5501 }
eacd73f7
YZ		 5502 if (total == 0)
5503 break;
9a799d71 5504 }
44df32c5 5505
9a799d71
AK		 5506 tx_ring->tx_buffer_info[i].skb = skb;
5507 tx_ring->tx_buffer_info[first].next_to_watch = i;
5508
e5a43549
AD		 5509 return count;
5510
5511dma_error:
5512 dev_err(&pdev->dev, "TX DMA map failed\n");
5513
5514 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5515 tx_buffer_info->dma = 0;
5516 tx_buffer_info->time_stamp = 0;
5517 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5518 if (count)
5519 count--;
e5a43549
AD		 5520
5521 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5522 while (count--) {
5523 if (i==0)
e5a43549 5524 i += tx_ring->count;
c1fa347f 5525 i--;
e5a43549
AD		 5526 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5527 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5528 }
5529
e44d38e1 5530 return 0;
9a799d71
AK		 5531}
5532
5533static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5534 struct ixgbe_ring *tx_ring,
5535 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5536{
5537 union ixgbe_adv_tx_desc *tx_desc = NULL;
5538 struct ixgbe_tx_buffer *tx_buffer_info;
5539 u32 olinfo_status = 0, cmd_type_len = 0;
5540 unsigned int i;
5541 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5542
5543 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5544
5545 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5546
5547 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5548 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5549
5550 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5551 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5552
5553 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5554 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5555
4eeae6fd
PW		 5556 /* use index 1 context for tso */
5557 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5558 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5559 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5560 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5561
5562 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5563 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5564 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5565
eacd73f7
YZ		 5566 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5567 olinfo_status |= IXGBE_ADVTXD_CC;
5568 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5569 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5570 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5571 }
5572
9a799d71
AK		 5573 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5574
5575 i = tx_ring->next_to_use;
5576 while (count--) {
5577 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5578 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5579 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5580 tx_desc->read.cmd_type_len =
b4617240 5581 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5582 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5583 i++;
5584 if (i == tx_ring->count)
5585 i = 0;
5586 }
5587
5588 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5589
5590 /*
5591 * Force memory writes to complete before letting h/w
5592 * know there are new descriptors to fetch. (Only
5593 * applicable for weak-ordered memory model archs,
5594 * such as IA-64).
5595 */
5596 wmb();
5597
5598 tx_ring->next_to_use = i;
5599 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5600}
5601
c4cf55e5
PWJ		 5602static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5603 int queue, u32 tx_flags)
5604{
5605 /* Right now, we support IPv4 only */
5606 struct ixgbe_atr_input atr_input;
5607 struct tcphdr *th;
c4cf55e5
PWJ		 5608 struct iphdr *iph = ip_hdr(skb);
5609 struct ethhdr *eth = (struct ethhdr *)skb->data;
5610 u16 vlan_id, src_port, dst_port, flex_bytes;
5611 u32 src_ipv4_addr, dst_ipv4_addr;
5612 u8 l4type = 0;
5613
5614 /* check if we're UDP or TCP */
5615 if (iph->protocol == IPPROTO_TCP) {
5616 th = tcp_hdr(skb);
5617 src_port = th->source;
5618 dst_port = th->dest;
5619 l4type |= IXGBE_ATR_L4TYPE_TCP;
5620 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5621 } else {
5622 /* Unsupported L4 header, just bail here */
5623 return;
5624 }
5625
5626 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5627
5628 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5629 IXGBE_TX_FLAGS_VLAN_SHIFT;
5630 src_ipv4_addr = iph->saddr;
5631 dst_ipv4_addr = iph->daddr;
5632 flex_bytes = eth->h_proto;
5633
5634 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5635 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5636 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5637 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5638 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5639 /* src and dst are inverted, think how the receiver sees them */
5640 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5641 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5642
5643 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5644 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5645}
5646
e092be60 5647static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5648 struct ixgbe_ring *tx_ring, int size)
e092be60 5649{
30eba97a 5650 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5651 /* Herbert's original patch had:
5652 * smp_mb__after_netif_stop_queue();
5653 * but since that doesn't exist yet, just open code it. */
5654 smp_mb();
5655
5656 /* We need to check again in a case another CPU has just
5657 * made room available. */
5658 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5659 return -EBUSY;
5660
5661 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5662 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5663 ++tx_ring->restart_queue;
e092be60
AV		 5664 return 0;
5665}
5666
5667static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5668 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5669{
5670 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5671 return 0;
5672 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5673}
5674
09a3b1f8
SH		 5675static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5676{
5677 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5678 int txq = smp_processor_id();
09a3b1f8 5679
fdd3d631
KK		 5680 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5681 while (unlikely(txq >= dev->real_num_tx_queues))
5682 txq -= dev->real_num_tx_queues;
5f715823 5683 return txq;
fdd3d631 5684 }
c4cf55e5 5685
5f715823
YZ		 5686#ifdef IXGBE_FCOE
5687 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
ca77cd59
RL		 5688 ((skb->protocol == htons(ETH_P_FCOE)) ||
5689 (skb->protocol == htons(ETH_P_FIP)))) {
5f715823
YZ		 5690 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5691 txq += adapter->ring_feature[RING_F_FCOE].mask;
5692 return txq;
5693 }
5694#endif
2ea186ae
JF		 5695 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5696 if (skb->priority == TC_PRIO_CONTROL)
5697 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5698 else
5699 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5700 >> 13;
5701 return txq;
5702 }
09a3b1f8
SH		 5703
5704 return skb_tx_hash(dev, skb);
5705}
5706
3b29a56d
SH		 5707static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5708 struct net_device *netdev)
9a799d71
AK		 5709{
5710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5711 struct ixgbe_ring *tx_ring;
60d51134 5712 struct netdev_queue *txq;
9a799d71
AK		 5713 unsigned int first;
5714 unsigned int tx_flags = 0;
30eba97a 5715 u8 hdr_len = 0;
5f715823 5716 int tso;
9a799d71
AK		 5717 int count = 0;
5718 unsigned int f;
9f8cdf4f 5719
9f8cdf4f
JB		 5720 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5721 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5722 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5723 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5724 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5725 }
5726 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5727 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5728 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2ea186ae
JF		 5729 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5730 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5731 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 5732 }
eacd73f7 5733
4a0b9ca0 5734 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5735
09ad1cc0 5736#ifdef IXGBE_FCOE
ca77cd59 5737 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
61a0f421 5738#ifdef CONFIG_IXGBE_DCB
ca77cd59
RL		 5739 /* for FCoE with DCB, we force the priority to what
5740 * was specified by the switch */
5741 if ((skb->protocol == htons(ETH_P_FCOE)) ||
5742 (skb->protocol == htons(ETH_P_FIP))) {
5743 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5744 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5745 tx_flags |= ((adapter->fcoe.up << 13)
5746 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5747 }
09ad1cc0 5748#endif
ca77cd59
RL		 5749 /* flag for FCoE offloads */
5750 if (skb->protocol == htons(ETH_P_FCOE))
5751 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5752 }
ca77cd59
RL		 5753#endif
5754
eacd73f7 5755 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5756 if (skb_is_gso(skb) ||
5757 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5758 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5759 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5760 count++;
5761
9f8cdf4f
JB		 5762 count += TXD_USE_COUNT(skb_headlen(skb));
5763 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5764 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5765
e092be60 5766 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5767 adapter->tx_busy++;
9a799d71
AK		 5768 return NETDEV_TX_BUSY;
5769 }
9a799d71 5770
9a799d71 5771 first = tx_ring->next_to_use;
eacd73f7
YZ		 5772 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5773#ifdef IXGBE_FCOE
5774 /* setup tx offload for FCoE */
5775 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5776 if (tso < 0) {
5777 dev_kfree_skb_any(skb);
5778 return NETDEV_TX_OK;
5779 }
5780 if (tso)
5781 tx_flags |= IXGBE_TX_FLAGS_FSO;
5782#endif /* IXGBE_FCOE */
5783 } else {
5784 if (skb->protocol == htons(ETH_P_IP))
5785 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5786 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5787 if (tso < 0) {
5788 dev_kfree_skb_any(skb);
5789 return NETDEV_TX_OK;
5790 }
9a799d71 5791
eacd73f7
YZ		 5792 if (tso)
5793 tx_flags |= IXGBE_TX_FLAGS_TSO;
5794 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5795 (skb->ip_summed == CHECKSUM_PARTIAL))
5796 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5797 }
9a799d71 5798
eacd73f7 5799 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5800 if (count) {
c4cf55e5
PWJ		 5801 /* add the ATR filter if ATR is on */
5802 if (tx_ring->atr_sample_rate) {
5803 ++tx_ring->atr_count;
5804 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5805 test_bit(__IXGBE_FDIR_INIT_DONE,
5806 &tx_ring->reinit_state)) {
5807 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5808 tx_flags);
5809 tx_ring->atr_count = 0;
5810 }
5811 }
60d51134
ED		 5812 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5813 txq->tx_bytes += skb->len;
5814 txq->tx_packets++;
44df32c5
AD		 5815 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5816 hdr_len);
44df32c5 5817 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5818
44df32c5
AD		 5819 } else {
5820 dev_kfree_skb_any(skb);
5821 tx_ring->tx_buffer_info[first].time_stamp = 0;
5822 tx_ring->next_to_use = first;
5823 }
9a799d71
AK		 5824
5825 return NETDEV_TX_OK;
5826}
5827
9a799d71
AK		 5828/**
5829 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5830 * @netdev: network interface device structure
5831 * @p: pointer to an address structure
5832 *
5833 * Returns 0 on success, negative on failure
5834 **/
5835static int ixgbe_set_mac(struct net_device *netdev, void *p)
5836{
5837 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5838 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5839 struct sockaddr *addr = p;
5840
5841 if (!is_valid_ether_addr(addr->sa_data))
5842 return -EADDRNOTAVAIL;
5843
5844 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5845 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5846
1cdd1ec8
GR		 5847 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5848 IXGBE_RAH_AV);
9a799d71
AK		 5849
5850 return 0;
5851}
5852
6b73e10d
BH		 5853static int
5854ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5855{
5856 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5857 struct ixgbe_hw *hw = &adapter->hw;
5858 u16 value;
5859 int rc;
5860
5861 if (prtad != hw->phy.mdio.prtad)
5862 return -EINVAL;
5863 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5864 if (!rc)
5865 rc = value;
5866 return rc;
5867}
5868
5869static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5870 u16 addr, u16 value)
5871{
5872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5873 struct ixgbe_hw *hw = &adapter->hw;
5874
5875 if (prtad != hw->phy.mdio.prtad)
5876 return -EINVAL;
5877 return hw->phy.ops.write_reg(hw, addr, devad, value);
5878}
5879
5880static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5881{
5882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5883
5884 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5885}
5886
0365e6e4
PW		 5887/**
5888 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5889 * netdev->dev_addrs
0365e6e4
PW		 5890 * @netdev: network interface device structure
5891 *
5892 * Returns non-zero on failure
5893 **/
5894static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5895{
5896 int err = 0;
5897 struct ixgbe_adapter *adapter = netdev_priv(dev);
5898 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5899
5900 if (is_valid_ether_addr(mac->san_addr)) {
5901 rtnl_lock();
5902 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5903 rtnl_unlock();
5904 }
5905 return err;
5906}
5907
5908/**
5909 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5910 * netdev->dev_addrs
0365e6e4
PW		 5911 * @netdev: network interface device structure
5912 *
5913 * Returns non-zero on failure
5914 **/
5915static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5916{
5917 int err = 0;
5918 struct ixgbe_adapter *adapter = netdev_priv(dev);
5919 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5920
5921 if (is_valid_ether_addr(mac->san_addr)) {
5922 rtnl_lock();
5923 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5924 rtnl_unlock();
5925 }
5926 return err;
5927}
5928
9a799d71
AK		 5929#ifdef CONFIG_NET_POLL_CONTROLLER
5930/*
5931 * Polling 'interrupt' - used by things like netconsole to send skbs
5932 * without having to re-enable interrupts. It's not called while
5933 * the interrupt routine is executing.
5934 */
5935static void ixgbe_netpoll(struct net_device *netdev)
5936{
5937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5938 int i;
9a799d71 5939
1a647bd2
AD		 5940 /* if interface is down do nothing */
5941 if (test_bit(__IXGBE_DOWN, &adapter->state))
5942 return;
5943
9a799d71 5944 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5945 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5946 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5947 for (i = 0; i < num_q_vectors; i++) {
5948 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5949 ixgbe_msix_clean_many(0, q_vector);
5950 }
5951 } else {
5952 ixgbe_intr(adapter->pdev->irq, netdev);
5953 }
9a799d71 5954 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5955}
5956#endif
5957
0edc3527
SH		 5958static const struct net_device_ops ixgbe_netdev_ops = {
5959 .ndo_open = ixgbe_open,
5960 .ndo_stop = ixgbe_close,
00829823 5961 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5962 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5963 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5964 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5965 .ndo_validate_addr = eth_validate_addr,
5966 .ndo_set_mac_address = ixgbe_set_mac,
5967 .ndo_change_mtu = ixgbe_change_mtu,
5968 .ndo_tx_timeout = ixgbe_tx_timeout,
5969 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5970 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5971 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5972 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5973#ifdef CONFIG_NET_POLL_CONTROLLER
5974 .ndo_poll_controller = ixgbe_netpoll,
5975#endif
332d4a7d
YZ		 5976#ifdef IXGBE_FCOE
5977 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5978 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5979 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5980 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5981 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5982#endif /* IXGBE_FCOE */
0edc3527
SH		 5983};
5984
1cdd1ec8
GR		 5985static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5986 const struct ixgbe_info *ii)
5987{
5988#ifdef CONFIG_PCI_IOV
5989 struct ixgbe_hw *hw = &adapter->hw;
5990 int err;
5991
5992 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5993 return;
5994
5995 /* The 82599 supports up to 64 VFs per physical function
5996 * but this implementation limits allocation to 63 so that
5997 * basic networking resources are still available to the
5998 * physical function
5999 */
6000 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6001 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6002 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6003 if (err) {
6004 DPRINTK(PROBE, ERR,
6005 "Failed to enable PCI sriov: %d\n", err);
6006 goto err_novfs;
6007 }
6008 /* If call to enable VFs succeeded then allocate memory
6009 * for per VF control structures.
6010 */
6011 adapter->vfinfo =
6012 kcalloc(adapter->num_vfs,
6013 sizeof(struct vf_data_storage), GFP_KERNEL);
6014 if (adapter->vfinfo) {
6015 /* Now that we're sure SR-IOV is enabled
6016 * and memory allocated set up the mailbox parameters
6017 */
6018 ixgbe_init_mbx_params_pf(hw);
6019 memcpy(&hw->mbx.ops, ii->mbx_ops,
6020 sizeof(hw->mbx.ops));
6021
6022 /* Disable RSC when in SR-IOV mode */
6023 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6024 IXGBE_FLAG2_RSC_ENABLED);
6025 return;
6026 }
6027
6028 /* Oh oh */
6029 DPRINTK(PROBE, ERR,
6030 "Unable to allocate memory for VF "
6031 "Data Storage - SRIOV disabled\n");
6032 pci_disable_sriov(adapter->pdev);
6033
6034err_novfs:
6035 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6036 adapter->num_vfs = 0;
6037#endif /* CONFIG_PCI_IOV */
6038}
6039
9a799d71
AK		 6040/**
6041 * ixgbe_probe - Device Initialization Routine
6042 * @pdev: PCI device information struct
6043 * @ent: entry in ixgbe_pci_tbl
6044 *
6045 * Returns 0 on success, negative on failure
6046 *
6047 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6048 * The OS initialization, configuring of the adapter private structure,
6049 * and a hardware reset occur.
6050 **/
6051static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6052 const struct pci_device_id *ent)
9a799d71
AK		 6053{
6054 struct net_device *netdev;
6055 struct ixgbe_adapter *adapter = NULL;
6056 struct ixgbe_hw *hw;
6057 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6058 static int cards_found;
6059 int i, err, pci_using_dac;
c85a2618 6060 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6061#ifdef IXGBE_FCOE
6062 u16 device_caps;
6063#endif
c44ade9e 6064 u32 part_num, eec;
9a799d71 6065
9ce77666 6066 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6067 if (err)
6068 return err;
6069
1b507730
NN		 6070 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6071 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6072 pci_using_dac = 1;
6073 } else {
1b507730 6074 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6075 if (err) {
1b507730
NN		 6076 err = dma_set_coherent_mask(&pdev->dev,
6077 DMA_BIT_MASK(32));
9a799d71 6078 if (err) {
b4617240
PW		 6079 dev_err(&pdev->dev, "No usable DMA "
6080 "configuration, aborting\n");
9a799d71
AK		 6081 goto err_dma;
6082 }
6083 }
6084 pci_using_dac = 0;
6085 }
6086
9ce77666 6087 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6088 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6089 if (err) {
9ce77666 6090 dev_err(&pdev->dev,
6091 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6092 goto err_pci_reg;
6093 }
6094
19d5afd4 6095 pci_enable_pcie_error_reporting(pdev);
6fabd715 6096
9a799d71 6097 pci_set_master(pdev);
fb3b27bc 6098 pci_save_state(pdev);
9a799d71 6099
c85a2618
JF		 6100 if (ii->mac == ixgbe_mac_82598EB)
6101 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6102 else
6103 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6104
6105 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6106#ifdef IXGBE_FCOE
6107 indices += min_t(unsigned int, num_possible_cpus(),
6108 IXGBE_MAX_FCOE_INDICES);
6109#endif
c85a2618 6110 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6111 if (!netdev) {
6112 err = -ENOMEM;
6113 goto err_alloc_etherdev;
6114 }
6115
9a799d71
AK		 6116 SET_NETDEV_DEV(netdev, &pdev->dev);
6117
6118 pci_set_drvdata(pdev, netdev);
6119 adapter = netdev_priv(netdev);
6120
6121 adapter->netdev = netdev;
6122 adapter->pdev = pdev;
6123 hw = &adapter->hw;
6124 hw->back = adapter;
6125 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6126
05857980
JK		 6127 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6128 pci_resource_len(pdev, 0));
9a799d71
AK		 6129 if (!hw->hw_addr) {
6130 err = -EIO;
6131 goto err_ioremap;
6132 }
6133
6134 for (i = 1; i <= 5; i++) {
6135 if (pci_resource_len(pdev, i) == 0)
6136 continue;
6137 }
6138
0edc3527 6139 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6140 ixgbe_set_ethtool_ops(netdev);
9a799d71 6141 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6142 strcpy(netdev->name, pci_name(pdev));
6143
9a799d71
AK		 6144 adapter->bd_number = cards_found;
6145
9a799d71
AK		 6146 /* Setup hw api */
6147 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6148 hw->mac.type = ii->mac;
9a799d71 6149
c44ade9e
JB		 6150 /* EEPROM */
6151 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6152 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6153 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6154 if (!(eec & (1 << 8)))
6155 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6156
6157 /* PHY */
6158 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6159 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6160 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6161 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6162 hw->phy.mdio.mmds = 0;
6163 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6164 hw->phy.mdio.dev = netdev;
6165 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6166 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6167
6168 /* set up this timer and work struct before calling get_invariants
6169 * which might start the timer
6170 */
6171 init_timer(&adapter->sfp_timer);
6172 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6173 adapter->sfp_timer.data = (unsigned long) adapter;
6174
6175 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6176
e8e26350
PW		 6177 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6178 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6179
6180 /* a new SFP+ module arrival, called from GPI SDP2 context */
6181 INIT_WORK(&adapter->sfp_config_module_task,
6182 ixgbe_sfp_config_module_task);
6183
8ca783ab 6184 ii->get_invariants(hw);
9a799d71
AK		 6185
6186 /* setup the private structure */
6187 err = ixgbe_sw_init(adapter);
6188 if (err)
6189 goto err_sw_init;
6190
e86bff0e
DS		 6191 /* Make it possible the adapter to be woken up via WOL */
6192 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6194
bf069c97
DS		 6195 /*
6196 * If there is a fan on this device and it has failed log the
6197 * failure.
6198 */
6199 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6200 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6201 if (esdp & IXGBE_ESDP_SDP1)
6202 DPRINTK(PROBE, CRIT,
6203 "Fan has stopped, replace the adapter\n");
6204 }
6205
c44ade9e
JB		 6206 /* reset_hw fills in the perm_addr as well */
6207 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6208 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6209 hw->mac.type == ixgbe_mac_82598EB) {
6210 /*
6211 * Start a kernel thread to watch for a module to arrive.
6212 * Only do this for 82598, since 82599 will generate
6213 * interrupts on module arrival.
6214 */
6215 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6216 mod_timer(&adapter->sfp_timer,
6217 round_jiffies(jiffies + (2 * HZ)));
6218 err = 0;
6219 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6220 dev_err(&adapter->pdev->dev, "failed to initialize because "
6221 "an unsupported SFP+ module type was detected.\n"
6222 "Reload the driver after installing a supported "
6223 "module.\n");
04f165ef
PW		 6224 goto err_sw_init;
6225 } else if (err) {
c44ade9e
JB		 6226 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6227 goto err_sw_init;
6228 }
6229
1cdd1ec8
GR		 6230 ixgbe_probe_vf(adapter, ii);
6231
9a799d71 6232 netdev->features = NETIF_F_SG |
b4617240
PW		 6233 NETIF_F_IP_CSUM |
6234 NETIF_F_HW_VLAN_TX |
6235 NETIF_F_HW_VLAN_RX |
6236 NETIF_F_HW_VLAN_FILTER;
9a799d71 6237
e9990a9c 6238 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6239 netdev->features |= NETIF_F_TSO;
9a799d71 6240 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6241 netdev->features |= NETIF_F_GRO;
ad31c402 6242
45a5ead0
JB		 6243 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6244 netdev->features |= NETIF_F_SCTP_CSUM;
6245
ad31c402
JK		 6246 netdev->vlan_features |= NETIF_F_TSO;
6247 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6248 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6249 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6250 netdev->vlan_features |= NETIF_F_SG;
6251
1cdd1ec8
GR		 6252 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6253 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6254 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6255 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6256 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6257
7a6b6f51 6258#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6259 netdev->dcbnl_ops = &dcbnl_ops;
6260#endif
6261
eacd73f7 6262#ifdef IXGBE_FCOE
0d551589 6263 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6264 if (hw->mac.ops.get_device_caps) {
6265 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6266 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6267 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6268 }
6269 }
6270#endif /* IXGBE_FCOE */
9a799d71
AK		 6271 if (pci_using_dac)
6272 netdev->features |= NETIF_F_HIGHDMA;
6273
0c19d6af 6274 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6275 netdev->features |= NETIF_F_LRO;
6276
9a799d71 6277 /* make sure the EEPROM is good */
c44ade9e 6278 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6279 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6280 err = -EIO;
6281 goto err_eeprom;
6282 }
6283
6284 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6285 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6286
c44ade9e
JB		 6287 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6288 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6289 err = -EIO;
6290 goto err_eeprom;
6291 }
6292
61fac744
PW		 6293 /* power down the optics */
6294 if (hw->phy.multispeed_fiber)
6295 hw->mac.ops.disable_tx_laser(hw);
6296
9a799d71
AK		 6297 init_timer(&adapter->watchdog_timer);
6298 adapter->watchdog_timer.function = &ixgbe_watchdog;
6299 adapter->watchdog_timer.data = (unsigned long)adapter;
6300
6301 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6302 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6303
021230d4
AV		 6304 err = ixgbe_init_interrupt_scheme(adapter);
6305 if (err)
6306 goto err_sw_init;
9a799d71 6307
e8e26350
PW		 6308 switch (pdev->device) {
6309 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6310 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6311 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6312 break;
6313 default:
6314 adapter->wol = 0;
6315 break;
6316 }
e8e26350
PW		 6317 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6318
04f165ef
PW		 6319 /* pick up the PCI bus settings for reporting later */
6320 hw->mac.ops.get_bus_info(hw);
6321
9a799d71 6322 /* print bus type/speed/width info */
7c510e4b 6323 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6324 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6325 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6326 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6327 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6328 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6329 "Unknown"),
7c510e4b 6330 netdev->dev_addr);
c44ade9e 6331 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6332 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6333 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6334 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6335 (part_num >> 8), (part_num & 0xff));
6336 else
6337 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6338 hw->mac.type, hw->phy.type,
6339 (part_num >> 8), (part_num & 0xff));
9a799d71 6340
e8e26350 6341 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6342 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6343 "this card is not sufficient for optimal "
6344 "performance.\n");
0c254d86 6345 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6346 "PCI-Express slot is required.\n");
0c254d86
AK		 6347 }
6348
34b0368c
PWJ		 6349 /* save off EEPROM version number */
6350 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6351
9a799d71 6352 /* reset the hardware with the new settings */
794caeb2 6353 err = hw->mac.ops.start_hw(hw);
c44ade9e 6354
794caeb2
PWJ		 6355 if (err == IXGBE_ERR_EEPROM_VERSION) {
6356 /* We are running on a pre-production device, log a warning */
6357 dev_warn(&pdev->dev, "This device is a pre-production "
6358 "adapter/LOM. Please be aware there may be issues "
6359 "associated with your hardware. If you are "
6360 "experiencing problems please contact your Intel or "
6361 "hardware representative who provided you with this "
6362 "hardware.\n");
6363 }
9a799d71
AK		 6364 strcpy(netdev->name, "eth%d");
6365 err = register_netdev(netdev);
6366 if (err)
6367 goto err_register;
6368
54386467
JB		 6369 /* carrier off reporting is important to ethtool even BEFORE open */
6370 netif_carrier_off(netdev);
6371
c4cf55e5
PWJ		 6372 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6373 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6374 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6375
5dd2d332 6376#ifdef CONFIG_IXGBE_DCA
652f093f 6377 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6378 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6379 ixgbe_setup_dca(adapter);
6380 }
6381#endif
1cdd1ec8
GR		 6382 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6383 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6384 adapter->num_vfs);
6385 for (i = 0; i < adapter->num_vfs; i++)
6386 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6387 }
6388
0365e6e4
PW		 6389 /* add san mac addr to netdev */
6390 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6391
6392 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6393 cards_found++;
6394 return 0;
6395
6396err_register:
5eba3699 6397 ixgbe_release_hw_control(adapter);
7a921c93 6398 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6399err_sw_init:
6400err_eeprom:
1cdd1ec8
GR		 6401 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6402 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6403 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6404 del_timer_sync(&adapter->sfp_timer);
6405 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6406 cancel_work_sync(&adapter->multispeed_fiber_task);
6407 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6408 iounmap(hw->hw_addr);
6409err_ioremap:
6410 free_netdev(netdev);
6411err_alloc_etherdev:
9ce77666 6412 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6413 IORESOURCE_MEM));
9a799d71
AK		 6414err_pci_reg:
6415err_dma:
6416 pci_disable_device(pdev);
6417 return err;
6418}
6419
6420/**
6421 * ixgbe_remove - Device Removal Routine
6422 * @pdev: PCI device information struct
6423 *
6424 * ixgbe_remove is called by the PCI subsystem to alert the driver
6425 * that it should release a PCI device. The could be caused by a
6426 * Hot-Plug event, or because the driver is going to be removed from
6427 * memory.
6428 **/
6429static void __devexit ixgbe_remove(struct pci_dev *pdev)
6430{
6431 struct net_device *netdev = pci_get_drvdata(pdev);
6432 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6433
6434 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6435 /* clear the module not found bit to make sure the worker won't
6436 * reschedule
6437 */
6438 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6439 del_timer_sync(&adapter->watchdog_timer);
6440
c4900be0
DS		 6441 del_timer_sync(&adapter->sfp_timer);
6442 cancel_work_sync(&adapter->watchdog_task);
6443 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6444 cancel_work_sync(&adapter->multispeed_fiber_task);
6445 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6446 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6447 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6448 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6449 flush_scheduled_work();
6450
5dd2d332 6451#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6452 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6453 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6454 dca_remove_requester(&pdev->dev);
6455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6456 }
6457
6458#endif
332d4a7d
YZ		 6459#ifdef IXGBE_FCOE
6460 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6461 ixgbe_cleanup_fcoe(adapter);
6462
6463#endif /* IXGBE_FCOE */
0365e6e4
PW		 6464
6465 /* remove the added san mac */
6466 ixgbe_del_sanmac_netdev(netdev);
6467
c4900be0
DS		 6468 if (netdev->reg_state == NETREG_REGISTERED)
6469 unregister_netdev(netdev);
9a799d71 6470
1cdd1ec8
GR		 6471 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6472 ixgbe_disable_sriov(adapter);
6473
7a921c93 6474 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6475
021230d4 6476 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6477
6478 iounmap(adapter->hw.hw_addr);
9ce77666 6479 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6480 IORESOURCE_MEM));
9a799d71 6481
021230d4 6482 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6483
9a799d71
AK		 6484 free_netdev(netdev);
6485
19d5afd4 6486 pci_disable_pcie_error_reporting(pdev);
6fabd715 6487
9a799d71
AK		 6488 pci_disable_device(pdev);
6489}
6490
6491/**
6492 * ixgbe_io_error_detected - called when PCI error is detected
6493 * @pdev: Pointer to PCI device
6494 * @state: The current pci connection state
6495 *
6496 * This function is called after a PCI bus error affecting
6497 * this device has been detected.
6498 */
6499static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6500 pci_channel_state_t state)
9a799d71
AK		 6501{
6502 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6503 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6504
6505 netif_device_detach(netdev);
6506
3044b8d1
BL		 6507 if (state == pci_channel_io_perm_failure)
6508 return PCI_ERS_RESULT_DISCONNECT;
6509
9a799d71
AK		 6510 if (netif_running(netdev))
6511 ixgbe_down(adapter);
6512 pci_disable_device(pdev);
6513
b4617240 6514 /* Request a slot reset. */
9a799d71
AK		 6515 return PCI_ERS_RESULT_NEED_RESET;
6516}
6517
6518/**
6519 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6520 * @pdev: Pointer to PCI device
6521 *
6522 * Restart the card from scratch, as if from a cold-boot.
6523 */
6524static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6525{
6526 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6528 pci_ers_result_t result;
6529 int err;
9a799d71 6530
9ce77666 6531 if (pci_enable_device_mem(pdev)) {
9a799d71 6532 DPRINTK(PROBE, ERR,
b4617240 6533 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6534 result = PCI_ERS_RESULT_DISCONNECT;
6535 } else {
6536 pci_set_master(pdev);
6537 pci_restore_state(pdev);
c0e1f68b 6538 pci_save_state(pdev);
9a799d71 6539
dd4d8ca6 6540 pci_wake_from_d3(pdev, false);
9a799d71 6541
6fabd715 6542 ixgbe_reset(adapter);
88512539 6543 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6544 result = PCI_ERS_RESULT_RECOVERED;
6545 }
6546
6547 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6548 if (err) {
6549 dev_err(&pdev->dev,
6550 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6551 /* non-fatal, continue */
6552 }
9a799d71 6553
6fabd715 6554 return result;
9a799d71
AK		 6555}
6556
6557/**
6558 * ixgbe_io_resume - called when traffic can start flowing again.
6559 * @pdev: Pointer to PCI device
6560 *
6561 * This callback is called when the error recovery driver tells us that
6562 * its OK to resume normal operation.
6563 */
6564static void ixgbe_io_resume(struct pci_dev *pdev)
6565{
6566 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6567 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6568
6569 if (netif_running(netdev)) {
6570 if (ixgbe_up(adapter)) {
6571 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6572 return;
6573 }
6574 }
6575
6576 netif_device_attach(netdev);
9a799d71
AK		 6577}
6578
6579static struct pci_error_handlers ixgbe_err_handler = {
6580 .error_detected = ixgbe_io_error_detected,
6581 .slot_reset = ixgbe_io_slot_reset,
6582 .resume = ixgbe_io_resume,
6583};
6584
6585static struct pci_driver ixgbe_driver = {
6586 .name = ixgbe_driver_name,
6587 .id_table = ixgbe_pci_tbl,
6588 .probe = ixgbe_probe,
6589 .remove = __devexit_p(ixgbe_remove),
6590#ifdef CONFIG_PM
6591 .suspend = ixgbe_suspend,
6592 .resume = ixgbe_resume,
6593#endif
6594 .shutdown = ixgbe_shutdown,
6595 .err_handler = &ixgbe_err_handler
6596};
6597
6598/**
6599 * ixgbe_init_module - Driver Registration Routine
6600 *
6601 * ixgbe_init_module is the first routine called when the driver is
6602 * loaded. All it does is register with the PCI subsystem.
6603 **/
6604static int __init ixgbe_init_module(void)
6605{
6606 int ret;
6607 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6608 ixgbe_driver_string, ixgbe_driver_version);
6609
6610 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6611
5dd2d332 6612#ifdef CONFIG_IXGBE_DCA
bd0362dd 6613 dca_register_notify(&dca_notifier);
bd0362dd 6614#endif
5dd2d332 6615
9a799d71
AK		 6616 ret = pci_register_driver(&ixgbe_driver);
6617 return ret;
6618}
b4617240 6619
9a799d71
AK		 6620module_init(ixgbe_init_module);
6621
6622/**
6623 * ixgbe_exit_module - Driver Exit Cleanup Routine
6624 *
6625 * ixgbe_exit_module is called just before the driver is removed
6626 * from memory.
6627 **/
6628static void __exit ixgbe_exit_module(void)
6629{
5dd2d332 6630#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6631 dca_unregister_notify(&dca_notifier);
6632#endif
9a799d71
AK		 6633 pci_unregister_driver(&ixgbe_driver);
6634}
bd0362dd 6635
5dd2d332 6636#ifdef CONFIG_IXGBE_DCA
bd0362dd 6637static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6638 void *p)
bd0362dd
JC		 6639{
6640 int ret_val;
6641
6642 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6643 __ixgbe_notify_dca);
bd0362dd
JC		 6644
6645 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6646}
b453368d 6647
5dd2d332 6648#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6649#ifdef DEBUG
6650/**
6651 * ixgbe_get_hw_dev_name - return device name string
6652 * used by hardware layer to print debugging information
6653 **/
6654char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6655{
6656 struct ixgbe_adapter *adapter = hw->back;
6657 return adapter->netdev->name;
6658}
bd0362dd 6659
b453368d 6660#endif
9a799d71
AK		 6661module_exit(ixgbe_exit_module);
6662
6663/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree