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ixgbe: enable HW RSC for 82599
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
04193058 50#define DRV_VERSION "2.0.16-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71 189{
44df32c5 190 tx_buffer_info->dma = 0;
9a799d71 191 if (tx_buffer_info->skb) {
44df32c5
AD		 192 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193 DMA_TO_DEVICE);
9a799d71
AK		 194 dev_kfree_skb_any(tx_buffer_info->skb);
195 tx_buffer_info->skb = NULL;
196 }
44df32c5 197 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 198 /* tx_buffer_info must be completely set up in the transmit path */
199}
200
201static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 202 struct ixgbe_ring *tx_ring,
203 unsigned int eop)
9a799d71 204{
e01c31a5 205 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 206
9a799d71 207 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 208 * check with the clearing of time_stamp and movement of eop */
9a799d71 209 adapter->detect_tx_hung = false;
44df32c5 210 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 211 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213 /* detected Tx unit hang */
e01c31a5
JB		 214 union ixgbe_adv_tx_desc *tx_desc;
215 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 216 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 217 " Tx Queue <%d>\n"
218 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 219 " next_to_use <%x>\n"
220 " next_to_clean <%x>\n"
221 "tx_buffer_info[next_to_clean]\n"
222 " time_stamp <%lx>\n"
e01c31a5
JB		 223 " jiffies <%lx>\n",
224 tx_ring->queue_index,
44df32c5
AD		 225 IXGBE_READ_REG(hw, tx_ring->head),
226 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 227 tx_ring->next_to_use, eop,
228 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 229 return true;
230 }
231
232 return false;
233}
234
b4617240
PW		 235#define IXGBE_MAX_TXD_PWR 14
236#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 237
238/* Tx Descriptors needed, worst case */
239#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 242 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 243
e01c31a5
JB		 244static void ixgbe_tx_timeout(struct net_device *netdev);
245
9a799d71
AK		 246/**
247 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248 * @adapter: board private structure
e01c31a5 249 * @tx_ring: tx ring to clean
9a1a69ad
JB		 250 *
251 * returns true if transmit work is done
9a799d71
AK		 252 **/
253static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 254 struct ixgbe_ring *tx_ring)
9a799d71 255{
e01c31a5 256 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 257 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 unsigned int i, eop, count = 0;
e01c31a5 260 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 261
262 i = tx_ring->next_to_clean;
12207e49
PWJ		 263 eop = tx_ring->tx_buffer_info[i].next_to_watch;
264 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 267 (count < tx_ring->work_limit)) {
12207e49
PWJ		 268 bool cleaned = false;
269 for ( ; !cleaned; count++) {
270 struct sk_buff *skb;
9a799d71
AK		 271 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 273 cleaned = (i == eop);
e01c31a5 274 skb = tx_buffer_info->skb;
9a799d71 275
12207e49 276 if (cleaned && skb) {
e092be60 277 unsigned int segs, bytecount;
e01c31a5
JB		 278
279 /* gso_segs is currently only valid for tcp */
e092be60
AV		 280 segs = skb_shinfo(skb)->gso_segs ?: 1;
281 /* multiply data chunks by size of headers */
282 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 283 skb->len;
284 total_packets += segs;
285 total_bytes += bytecount;
e092be60 286 }
e01c31a5 287
9a799d71 288 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 289 tx_buffer_info);
9a799d71 290
12207e49
PWJ		 291 tx_desc->wb.status = 0;
292
9a799d71
AK		 293 i++;
294 if (i == tx_ring->count)
295 i = 0;
e01c31a5 296 }
12207e49
PWJ		 297
298 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300 }
301
9a799d71
AK		 302 tx_ring->next_to_clean = i;
303
e092be60 304#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 305 if (unlikely(count && netif_carrier_ok(netdev) &&
306 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 307 /* Make sure that anybody stopping the queue after this
308 * sees the new next_to_clean.
309 */
310 smp_mb();
30eba97a
AV		 311 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312 !test_bit(__IXGBE_DOWN, &adapter->state)) {
313 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 314 ++adapter->restart_queue;
30eba97a 315 }
e092be60 316 }
9a799d71 317
e01c31a5
JB		 318 if (adapter->detect_tx_hung) {
319 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320 /* schedule immediate reset if we believe we hung */
321 DPRINTK(PROBE, INFO,
322 "tx hang %d detected, resetting adapter\n",
323 adapter->tx_timeout_count + 1);
324 ixgbe_tx_timeout(adapter->netdev);
325 }
326 }
9a799d71 327
e01c31a5 328 /* re-arm the interrupt */
9a1a69ad 329 if (count >= tx_ring->work_limit)
e01c31a5 330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 331
e01c31a5
JB		 332 tx_ring->total_bytes += total_bytes;
333 tx_ring->total_packets += total_packets;
e01c31a5 334 tx_ring->stats.packets += total_packets;
12207e49 335 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 336 adapter->net_stats.tx_bytes += total_bytes;
337 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 338 return (count < tx_ring->work_limit);
9a799d71
AK		 339}
340
5dd2d332 341#ifdef CONFIG_IXGBE_DCA
bd0362dd 342static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 343 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 344{
345 u32 rxctrl;
346 int cpu = get_cpu();
3a581073 347 int q = rx_ring - adapter->rx_ring;
bd0362dd 348
3a581073 349 if (rx_ring->cpu != cpu) {
bd0362dd 350 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 351 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
352 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
353 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
354 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
355 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
356 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
357 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
358 }
bd0362dd
JC		 359 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
360 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 361 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
362 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 363 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 365 rx_ring->cpu = cpu;
bd0362dd
JC		 366 }
367 put_cpu();
368}
369
370static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 371 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 372{
373 u32 txctrl;
374 int cpu = get_cpu();
3a581073 375 int q = tx_ring - adapter->tx_ring;
bd0362dd 376
3a581073 377 if (tx_ring->cpu != cpu) {
bd0362dd 378 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 379 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
380 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
381 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
382 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
383 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
384 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
385 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
386 }
bd0362dd
JC		 387 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 389 tx_ring->cpu = cpu;
bd0362dd
JC		 390 }
391 put_cpu();
392}
393
394static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
395{
396 int i;
397
398 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
399 return;
400
401 for (i = 0; i < adapter->num_tx_queues; i++) {
402 adapter->tx_ring[i].cpu = -1;
403 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
404 }
405 for (i = 0; i < adapter->num_rx_queues; i++) {
406 adapter->rx_ring[i].cpu = -1;
407 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
408 }
409}
410
411static int __ixgbe_notify_dca(struct device *dev, void *data)
412{
413 struct net_device *netdev = dev_get_drvdata(dev);
414 struct ixgbe_adapter *adapter = netdev_priv(netdev);
415 unsigned long event = *(unsigned long *)data;
416
417 switch (event) {
418 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 419 /* if we're already enabled, don't do it again */
420 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
421 break;
bd0362dd
JC		 422 /* Always use CB2 mode, difference is masked
423 * in the CB driver. */
424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 425 if (dca_add_requester(dev) == 0) {
96b0e0f6 426 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 427 ixgbe_setup_dca(adapter);
428 break;
429 }
430 /* Fall Through since DCA is disabled. */
431 case DCA_PROVIDER_REMOVE:
432 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
433 dca_remove_requester(dev);
434 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
436 }
437 break;
438 }
439
652f093f 440 return 0;
bd0362dd
JC		 441}
442
5dd2d332 443#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 444/**
445 * ixgbe_receive_skb - Send a completed packet up the stack
446 * @adapter: board private structure
447 * @skb: packet to send up
177db6ff
MC		 448 * @status: hardware indication of status of receive
449 * @rx_ring: rx descriptor ring (for a specific queue) to setup
450 * @rx_desc: rx descriptor
9a799d71 451 **/
78b6f4ce 452static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 453 struct sk_buff *skb, u8 status,
177db6ff 454 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 455{
78b6f4ce
HX		 456 struct ixgbe_adapter *adapter = q_vector->adapter;
457 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 458 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
459 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 460
0c8dfc83 461 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
182ff8df 462 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 463 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 464 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 465 else
78b6f4ce 466 napi_gro_receive(napi, skb);
177db6ff 467 } else {
182ff8df
AD		 468 if (adapter->vlgrp && is_vlan && (tag != 0))
469 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
470 else
471 netif_rx(skb);
9a799d71
AK		 472 }
473}
474
e59bd25d
AV		 475/**
476 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
477 * @adapter: address of board private structure
478 * @status_err: hardware indication of status of receive
479 * @skb: skb currently being received and modified
480 **/
9a799d71 481static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 482 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 483{
484 skb->ip_summed = CHECKSUM_NONE;
485
712744be
JB		 486 /* Rx csum disabled */
487 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 488 return;
e59bd25d
AV		 489
490 /* if IP and error */
491 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
492 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 493 adapter->hw_csum_rx_error++;
494 return;
495 }
e59bd25d
AV		 496
497 if (!(status_err & IXGBE_RXD_STAT_L4CS))
498 return;
499
500 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
501 adapter->hw_csum_rx_error++;
502 return;
503 }
504
9a799d71 505 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 506 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 507 adapter->hw_csum_rx_good++;
508}
509
e8e26350
PW		 510static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
511 struct ixgbe_ring *rx_ring, u32 val)
512{
513 /*
514 * Force memory writes to complete before letting h/w
515 * know there are new descriptors to fetch. (Only
516 * applicable for weak-ordered memory model archs,
517 * such as IA-64).
518 */
519 wmb();
520 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
521}
522
9a799d71
AK		 523/**
524 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
525 * @adapter: address of board private structure
526 **/
527static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 528 struct ixgbe_ring *rx_ring,
529 int cleaned_count)
9a799d71 530{
9a799d71
AK		 531 struct pci_dev *pdev = adapter->pdev;
532 union ixgbe_adv_rx_desc *rx_desc;
3a581073 533 struct ixgbe_rx_buffer *bi;
9a799d71 534 unsigned int i;
e8e26350 535 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 536
537 i = rx_ring->next_to_use;
3a581073 538 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 539
540 while (cleaned_count--) {
541 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
542
762f4c57 543 if (!bi->page_dma &&
3a581073 544 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 545 if (!bi->page) {
762f4c57
JB		 546 bi->page = alloc_page(GFP_ATOMIC);
547 if (!bi->page) {
548 adapter->alloc_rx_page_failed++;
549 goto no_buffers;
550 }
551 bi->page_offset = 0;
552 } else {
553 /* use a half page if we're re-using */
554 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 555 }
762f4c57
JB		 556
557 bi->page_dma = pci_map_page(pdev, bi->page,
558 bi->page_offset,
559 (PAGE_SIZE / 2),
560 PCI_DMA_FROMDEVICE);
9a799d71
AK		 561 }
562
3a581073 563 if (!bi->skb) {
5ecc3614 564 struct sk_buff *skb;
e8e26350 565 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 566
567 if (!skb) {
568 adapter->alloc_rx_buff_failed++;
569 goto no_buffers;
570 }
571
572 /*
573 * Make buffer alignment 2 beyond a 16 byte boundary
574 * this will result in a 16 byte aligned IP header after
575 * the 14 byte MAC header is removed
576 */
577 skb_reserve(skb, NET_IP_ALIGN);
578
3a581073 579 bi->skb = skb;
e8e26350 580 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 581 PCI_DMA_FROMDEVICE);
9a799d71
AK		 582 }
583 /* Refresh the desc even if buffer_addrs didn't change because
584 * each write-back erases this info. */
585 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 586 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
587 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 588 } else {
3a581073 589 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 590 }
591
592 i++;
593 if (i == rx_ring->count)
594 i = 0;
3a581073 595 bi = &rx_ring->rx_buffer_info[i];
9a799d71 596 }
7c6e0a43 597
9a799d71
AK		 598no_buffers:
599 if (rx_ring->next_to_use != i) {
600 rx_ring->next_to_use = i;
601 if (i-- == 0)
602 i = (rx_ring->count - 1);
603
e8e26350 604 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 605 }
606}
607
7c6e0a43
JB		 608static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
609{
610 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
611}
612
613static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
614{
615 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
616}
617
f8212f97
AD		 618static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
619{
620 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
621 IXGBE_RXDADV_RSCCNT_MASK) >>
622 IXGBE_RXDADV_RSCCNT_SHIFT;
623}
624
625/**
626 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
627 * @skb: pointer to the last skb in the rsc queue
628 *
629 * This function changes a queue full of hw rsc buffers into a completed
630 * packet. It uses the ->prev pointers to find the first packet and then
631 * turns it into the frag list owner.
632 **/
633static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
634{
635 unsigned int frag_list_size = 0;
636
637 while (skb->prev) {
638 struct sk_buff *prev = skb->prev;
639 frag_list_size += skb->len;
640 skb->prev = NULL;
641 skb = prev;
642 }
643
644 skb_shinfo(skb)->frag_list = skb->next;
645 skb->next = NULL;
646 skb->len += frag_list_size;
647 skb->data_len += frag_list_size;
648 skb->truesize += frag_list_size;
649 return skb;
650}
651
78b6f4ce 652static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 653 struct ixgbe_ring *rx_ring,
654 int *work_done, int work_to_do)
9a799d71 655{
78b6f4ce 656 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 657 struct pci_dev *pdev = adapter->pdev;
658 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
659 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
660 struct sk_buff *skb;
f8212f97 661 unsigned int i, rsc_count = 0;
7c6e0a43 662 u32 len, staterr;
177db6ff
MC		 663 u16 hdr_info;
664 bool cleaned = false;
9a799d71 665 int cleaned_count = 0;
d2f4fbe2 666 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 667
668 i = rx_ring->next_to_clean;
9a799d71
AK		 669 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
670 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
671 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 672
673 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 674 u32 upper_len = 0;
9a799d71
AK		 675 if (*work_done >= work_to_do)
676 break;
677 (*work_done)++;
678
679 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 680 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
681 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 682 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 683 if (hdr_info & IXGBE_RXDADV_SPH)
684 adapter->rx_hdr_split++;
685 if (len > IXGBE_RX_HDR_SIZE)
686 len = IXGBE_RX_HDR_SIZE;
687 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 688 } else {
9a799d71 689 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 690 }
9a799d71
AK		 691
692 cleaned = true;
693 skb = rx_buffer_info->skb;
694 prefetch(skb->data - NET_IP_ALIGN);
695 rx_buffer_info->skb = NULL;
696
697 if (len && !skb_shinfo(skb)->nr_frags) {
698 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 699 rx_ring->rx_buf_len,
b4617240 700 PCI_DMA_FROMDEVICE);
9a799d71
AK		 701 skb_put(skb, len);
702 }
703
704 if (upper_len) {
705 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 706 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 707 rx_buffer_info->page_dma = 0;
708 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 709 rx_buffer_info->page,
710 rx_buffer_info->page_offset,
711 upper_len);
712
713 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
714 (page_count(rx_buffer_info->page) != 1))
715 rx_buffer_info->page = NULL;
716 else
717 get_page(rx_buffer_info->page);
9a799d71
AK		 718
719 skb->len += upper_len;
720 skb->data_len += upper_len;
721 skb->truesize += upper_len;
722 }
723
724 i++;
725 if (i == rx_ring->count)
726 i = 0;
9a799d71
AK		 727
728 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
729 prefetch(next_rxd);
9a799d71 730 cleaned_count++;
f8212f97
AD		 731
732 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
733 rsc_count = ixgbe_get_rsc_count(rx_desc);
734
735 if (rsc_count) {
736 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
737 IXGBE_RXDADV_NEXTP_SHIFT;
738 next_buffer = &rx_ring->rx_buffer_info[nextp];
739 rx_ring->rsc_count += (rsc_count - 1);
740 } else {
741 next_buffer = &rx_ring->rx_buffer_info[i];
742 }
743
9a799d71 744 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 745 if (skb->prev)
746 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 747 rx_ring->stats.packets++;
748 rx_ring->stats.bytes += skb->len;
749 } else {
f8212f97
AD		 750 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
751 rx_buffer_info->skb = next_buffer->skb;
752 rx_buffer_info->dma = next_buffer->dma;
753 next_buffer->skb = skb;
754 next_buffer->dma = 0;
755 } else {
756 skb->next = next_buffer->skb;
757 skb->next->prev = skb;
758 }
9a799d71
AK		 759 adapter->non_eop_descs++;
760 goto next_desc;
761 }
762
763 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
764 dev_kfree_skb_irq(skb);
765 goto next_desc;
766 }
767
768 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 769
770 /* probably a little skewed due to removing CRC */
771 total_rx_bytes += skb->len;
772 total_rx_packets++;
773
74ce8dd2 774 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 775 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 776
777next_desc:
778 rx_desc->wb.upper.status_error = 0;
779
780 /* return some buffers to hardware, one at a time is too slow */
781 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
782 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
783 cleaned_count = 0;
784 }
785
786 /* use prefetched values */
787 rx_desc = next_rxd;
f8212f97 788 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 789
790 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 791 }
792
9a799d71
AK		 793 rx_ring->next_to_clean = i;
794 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
795
796 if (cleaned_count)
797 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
798
f494e8fa
AV		 799 rx_ring->total_packets += total_rx_packets;
800 rx_ring->total_bytes += total_rx_bytes;
801 adapter->net_stats.rx_bytes += total_rx_bytes;
802 adapter->net_stats.rx_packets += total_rx_packets;
803
9a799d71
AK		 804 return cleaned;
805}
806
021230d4 807static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 808/**
809 * ixgbe_configure_msix - Configure MSI-X hardware
810 * @adapter: board private structure
811 *
812 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
813 * interrupts.
814 **/
815static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
816{
021230d4
AV		 817 struct ixgbe_q_vector *q_vector;
818 int i, j, q_vectors, v_idx, r_idx;
819 u32 mask;
9a799d71 820
021230d4 821 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 822
4df10466
JB		 823 /*
824 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 825 * corresponding register.
826 */
827 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
828 q_vector = &adapter->q_vector[v_idx];
829 /* XXX for_each_bit(...) */
830 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 831 adapter->num_rx_queues);
021230d4
AV		 832
833 for (i = 0; i < q_vector->rxr_count; i++) {
834 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 835 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 836 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 837 adapter->num_rx_queues,
838 r_idx + 1);
021230d4
AV		 839 }
840 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 841 adapter->num_tx_queues);
021230d4
AV		 842
843 for (i = 0; i < q_vector->txr_count; i++) {
844 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 845 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 846 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 847 adapter->num_tx_queues,
848 r_idx + 1);
021230d4
AV		 849 }
850
30efa5a3 851 /* if this is a tx only vector halve the interrupt rate */
021230d4 852 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 853 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 854 else if (q_vector->rxr_count)
30efa5a3
JB		 855 /* rx only */
856 q_vector->eitr = adapter->eitr_param;
021230d4 857
509ee935 858 /*
4df10466 859 * since this is initial set up don't need to call
509ee935
JB		 860 * ixgbe_write_eitr helper
861 */
021230d4 862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 863 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 864 }
865
e8e26350
PW		 866 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
867 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
868 v_idx);
869 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
870 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 871 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
872
41fb9248 873 /* set up to autoclear timer, and the vectors */
021230d4 874 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 875 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 877}
878
f494e8fa
AV		 879enum latency_range {
880 lowest_latency = 0,
881 low_latency = 1,
882 bulk_latency = 2,
883 latency_invalid = 255
884};
885
886/**
887 * ixgbe_update_itr - update the dynamic ITR value based on statistics
888 * @adapter: pointer to adapter
889 * @eitr: eitr setting (ints per sec) to give last timeslice
890 * @itr_setting: current throttle rate in ints/second
891 * @packets: the number of packets during this measurement interval
892 * @bytes: the number of bytes during this measurement interval
893 *
894 * Stores a new ITR value based on packets and byte
895 * counts during the last interrupt. The advantage of per interrupt
896 * computation is faster updates and more accurate ITR for the current
897 * traffic pattern. Constants in this function were computed
898 * based on theoretical maximum wire speed and thresholds were set based
899 * on testing data as well as attempting to minimize response time
900 * while increasing bulk throughput.
901 * this functionality is controlled by the InterruptThrottleRate module
902 * parameter (see ixgbe_param.c)
903 **/
904static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 905 u32 eitr, u8 itr_setting,
906 int packets, int bytes)
f494e8fa
AV		 907{
908 unsigned int retval = itr_setting;
909 u32 timepassed_us;
910 u64 bytes_perint;
911
912 if (packets == 0)
913 goto update_itr_done;
914
915
916 /* simple throttlerate management
917 * 0-20MB/s lowest (100000 ints/s)
918 * 20-100MB/s low (20000 ints/s)
919 * 100-1249MB/s bulk (8000 ints/s)
920 */
921 /* what was last interrupt timeslice? */
922 timepassed_us = 1000000/eitr;
923 bytes_perint = bytes / timepassed_us; /* bytes/usec */
924
925 switch (itr_setting) {
926 case lowest_latency:
927 if (bytes_perint > adapter->eitr_low)
928 retval = low_latency;
929 break;
930 case low_latency:
931 if (bytes_perint > adapter->eitr_high)
932 retval = bulk_latency;
933 else if (bytes_perint <= adapter->eitr_low)
934 retval = lowest_latency;
935 break;
936 case bulk_latency:
937 if (bytes_perint <= adapter->eitr_high)
938 retval = low_latency;
939 break;
940 }
941
942update_itr_done:
943 return retval;
944}
945
509ee935
JB		 946/**
947 * ixgbe_write_eitr - write EITR register in hardware specific way
948 * @adapter: pointer to adapter struct
949 * @v_idx: vector index into q_vector array
950 * @itr_reg: new value to be written in *register* format, not ints/s
951 *
952 * This function is made to be called by ethtool and by the driver
953 * when it needs to update EITR registers at runtime. Hardware
954 * specific quirks/differences are taken care of here.
955 */
956void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
957{
958 struct ixgbe_hw *hw = &adapter->hw;
959 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
960 /* must write high and low 16 bits to reset counter */
961 itr_reg |= (itr_reg << 16);
962 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
963 /*
964 * set the WDIS bit to not clear the timer bits and cause an
965 * immediate assertion of the interrupt
966 */
967 itr_reg |= IXGBE_EITR_CNT_WDIS;
968 }
969 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
970}
971
f494e8fa
AV		 972static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
973{
974 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 975 u32 new_itr;
976 u8 current_itr, ret_itr;
977 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 978 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 979 struct ixgbe_ring *rx_ring, *tx_ring;
980
981 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
982 for (i = 0; i < q_vector->txr_count; i++) {
983 tx_ring = &(adapter->tx_ring[r_idx]);
984 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 985 q_vector->tx_itr,
986 tx_ring->total_packets,
987 tx_ring->total_bytes);
f494e8fa
AV		 988 /* if the result for this queue would decrease interrupt
989 * rate for this vector then use that result */
30efa5a3 990 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 991 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 992 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 993 r_idx + 1);
f494e8fa
AV		 994 }
995
996 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
997 for (i = 0; i < q_vector->rxr_count; i++) {
998 rx_ring = &(adapter->rx_ring[r_idx]);
999 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1000 q_vector->rx_itr,
1001 rx_ring->total_packets,
1002 rx_ring->total_bytes);
f494e8fa
AV		 1003 /* if the result for this queue would decrease interrupt
1004 * rate for this vector then use that result */
30efa5a3 1005 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1006 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1007 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1008 r_idx + 1);
f494e8fa
AV		 1009 }
1010
30efa5a3 1011 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1012
1013 switch (current_itr) {
1014 /* counts and packets in update_itr are dependent on these numbers */
1015 case lowest_latency:
1016 new_itr = 100000;
1017 break;
1018 case low_latency:
1019 new_itr = 20000; /* aka hwitr = ~200 */
1020 break;
1021 case bulk_latency:
1022 default:
1023 new_itr = 8000;
1024 break;
1025 }
1026
1027 if (new_itr != q_vector->eitr) {
1028 u32 itr_reg;
509ee935
JB		 1029
1030 /* save the algorithm value here, not the smoothed one */
1031 q_vector->eitr = new_itr;
f494e8fa
AV		 1032 /* do an exponential smoothing */
1033 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1034 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1035 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1036 }
1037
1038 return;
1039}
1040
0befdb3e
JB		 1041static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1042{
1043 struct ixgbe_hw *hw = &adapter->hw;
1044
1045 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1046 (eicr & IXGBE_EICR_GPI_SDP1)) {
1047 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1048 /* write to clear the interrupt */
1049 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1050 }
1051}
cf8280ee 1052
e8e26350
PW		 1053static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1054{
1055 struct ixgbe_hw *hw = &adapter->hw;
1056
1057 if (eicr & IXGBE_EICR_GPI_SDP1) {
1058 /* Clear the interrupt */
1059 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1060 schedule_work(&adapter->multispeed_fiber_task);
1061 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1062 /* Clear the interrupt */
1063 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1064 schedule_work(&adapter->sfp_config_module_task);
1065 } else {
1066 /* Interrupt isn't for us... */
1067 return;
1068 }
1069}
1070
cf8280ee
JB		 1071static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1072{
1073 struct ixgbe_hw *hw = &adapter->hw;
1074
1075 adapter->lsc_int++;
1076 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1077 adapter->link_check_timeout = jiffies;
1078 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1079 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1080 schedule_work(&adapter->watchdog_task);
1081 }
1082}
1083
9a799d71
AK		 1084static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1085{
1086 struct net_device *netdev = data;
1087 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1088 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1089 u32 eicr;
1090
1091 /*
1092 * Workaround for Silicon errata. Use clear-by-write instead
1093 * of clear-by-read. Reading with EICS will return the
1094 * interrupt causes without clearing, which later be done
1095 * with the write to EICR.
1096 */
1097 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1098 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1099
cf8280ee
JB		 1100 if (eicr & IXGBE_EICR_LSC)
1101 ixgbe_check_lsc(adapter);
d4f80882 1102
e8e26350
PW		 1103 if (hw->mac.type == ixgbe_mac_82598EB)
1104 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1105
e8e26350
PW		 1106 if (hw->mac.type == ixgbe_mac_82599EB)
1107 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1108 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1109 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1110
1111 return IRQ_HANDLED;
1112}
1113
1114static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1115{
021230d4
AV		 1116 struct ixgbe_q_vector *q_vector = data;
1117 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1118 struct ixgbe_ring *tx_ring;
021230d4
AV		 1119 int i, r_idx;
1120
1121 if (!q_vector->txr_count)
1122 return IRQ_HANDLED;
1123
1124 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1125 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1126 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1127#ifdef CONFIG_IXGBE_DCA
bd0362dd 1128 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1129 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1130#endif
3a581073
JB		 1131 tx_ring->total_bytes = 0;
1132 tx_ring->total_packets = 0;
1133 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1134 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1135 r_idx + 1);
021230d4 1136 }
9a799d71 1137
9a799d71
AK		 1138 return IRQ_HANDLED;
1139}
1140
021230d4
AV		 1141/**
1142 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1143 * @irq: unused
1144 * @data: pointer to our q_vector struct for this interrupt vector
1145 **/
9a799d71
AK		 1146static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1147{
021230d4
AV		 1148 struct ixgbe_q_vector *q_vector = data;
1149 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1150 struct ixgbe_ring *rx_ring;
021230d4 1151 int r_idx;
30efa5a3 1152 int i;
021230d4
AV		 1153
1154 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1155 for (i = 0; i < q_vector->rxr_count; i++) {
1156 rx_ring = &(adapter->rx_ring[r_idx]);
1157 rx_ring->total_bytes = 0;
1158 rx_ring->total_packets = 0;
1159 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1160 r_idx + 1);
1161 }
1162
021230d4
AV		 1163 if (!q_vector->rxr_count)
1164 return IRQ_HANDLED;
1165
30efa5a3 1166 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1167 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1168 /* disable interrupts on this vector only */
3a581073 1169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1170 napi_schedule(&q_vector->napi);
021230d4
AV		 1171
1172 return IRQ_HANDLED;
1173}
1174
1175static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1176{
1177 ixgbe_msix_clean_rx(irq, data);
1178 ixgbe_msix_clean_tx(irq, data);
9a799d71 1179
9a799d71
AK		 1180 return IRQ_HANDLED;
1181}
1182
021230d4
AV		 1183/**
1184 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1185 * @napi: napi struct with our devices info in it
1186 * @budget: amount of work driver is allowed to do this pass, in packets
1187 *
f0848276
JB		 1188 * This function is optimized for cleaning one queue only on a single
1189 * q_vector!!!
021230d4 1190 **/
9a799d71
AK		 1191static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1192{
021230d4 1193 struct ixgbe_q_vector *q_vector =
b4617240 1194 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1195 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1196 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1197 int work_done = 0;
021230d4 1198 long r_idx;
9a799d71 1199
021230d4 1200 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1201 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1202#ifdef CONFIG_IXGBE_DCA
bd0362dd 1203 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1204 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1205#endif
9a799d71 1206
78b6f4ce 1207 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1208
021230d4
AV		 1209 /* If all Rx work done, exit the polling mode */
1210 if (work_done < budget) {
288379f0 1211 napi_complete(napi);
509ee935 1212 if (adapter->itr_setting & 1)
f494e8fa 1213 ixgbe_set_itr_msix(q_vector);
9a799d71 1214 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1216 }
1217
1218 return work_done;
1219}
1220
f0848276
JB		 1221/**
1222 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1223 * @napi: napi struct with our devices info in it
1224 * @budget: amount of work driver is allowed to do this pass, in packets
1225 *
1226 * This function will clean more than one rx queue associated with a
1227 * q_vector.
1228 **/
1229static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1230{
1231 struct ixgbe_q_vector *q_vector =
1232 container_of(napi, struct ixgbe_q_vector, napi);
1233 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1234 struct ixgbe_ring *rx_ring = NULL;
1235 int work_done = 0, i;
1236 long r_idx;
1237 u16 enable_mask = 0;
1238
1239 /* attempt to distribute budget to each queue fairly, but don't allow
1240 * the budget to go below 1 because we'll exit polling */
1241 budget /= (q_vector->rxr_count ?: 1);
1242 budget = max(budget, 1);
1243 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1244 for (i = 0; i < q_vector->rxr_count; i++) {
1245 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1246#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1247 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1248 ixgbe_update_rx_dca(adapter, rx_ring);
1249#endif
78b6f4ce 1250 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1251 enable_mask |= rx_ring->v_idx;
1252 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1253 r_idx + 1);
1254 }
1255
1256 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1257 rx_ring = &(adapter->rx_ring[r_idx]);
1258 /* If all Rx work done, exit the polling mode */
7f821875 1259 if (work_done < budget) {
288379f0 1260 napi_complete(napi);
509ee935 1261 if (adapter->itr_setting & 1)
f0848276
JB		 1262 ixgbe_set_itr_msix(q_vector);
1263 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1264 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1265 return 0;
1266 }
1267
1268 return work_done;
1269}
021230d4 1270static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1271 int r_idx)
021230d4
AV		 1272{
1273 a->q_vector[v_idx].adapter = a;
1274 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1275 a->q_vector[v_idx].rxr_count++;
1276 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1277}
1278
1279static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1280 int r_idx)
021230d4
AV		 1281{
1282 a->q_vector[v_idx].adapter = a;
1283 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1284 a->q_vector[v_idx].txr_count++;
1285 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1286}
1287
9a799d71 1288/**
021230d4
AV		 1289 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1290 * @adapter: board private structure to initialize
1291 * @vectors: allotted vector count for descriptor rings
9a799d71 1292 *
021230d4
AV		 1293 * This function maps descriptor rings to the queue-specific vectors
1294 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1295 * one vector per ring/queue, but on a constrained vector budget, we
1296 * group the rings as "efficiently" as possible. You would add new
1297 * mapping configurations in here.
9a799d71 1298 **/
021230d4 1299static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1300 int vectors)
021230d4
AV		 1301{
1302 int v_start = 0;
1303 int rxr_idx = 0, txr_idx = 0;
1304 int rxr_remaining = adapter->num_rx_queues;
1305 int txr_remaining = adapter->num_tx_queues;
1306 int i, j;
1307 int rqpv, tqpv;
1308 int err = 0;
1309
1310 /* No mapping required if MSI-X is disabled. */
1311 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1312 goto out;
9a799d71 1313
021230d4
AV		 1314 /*
1315 * The ideal configuration...
1316 * We have enough vectors to map one per queue.
1317 */
1318 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1319 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1320 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1321
021230d4
AV		 1322 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1323 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1324
9a799d71 1325 goto out;
021230d4 1326 }
9a799d71 1327
021230d4
AV		 1328 /*
1329 * If we don't have enough vectors for a 1-to-1
1330 * mapping, we'll have to group them so there are
1331 * multiple queues per vector.
1332 */
1333 /* Re-adjusting *qpv takes care of the remainder. */
1334 for (i = v_start; i < vectors; i++) {
1335 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1336 for (j = 0; j < rqpv; j++) {
1337 map_vector_to_rxq(adapter, i, rxr_idx);
1338 rxr_idx++;
1339 rxr_remaining--;
1340 }
1341 }
1342 for (i = v_start; i < vectors; i++) {
1343 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1344 for (j = 0; j < tqpv; j++) {
1345 map_vector_to_txq(adapter, i, txr_idx);
1346 txr_idx++;
1347 txr_remaining--;
9a799d71 1348 }
9a799d71
AK		 1349 }
1350
021230d4
AV		 1351out:
1352 return err;
1353}
1354
1355/**
1356 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1357 * @adapter: board private structure
1358 *
1359 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1360 * interrupts from the kernel.
1361 **/
1362static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1363{
1364 struct net_device *netdev = adapter->netdev;
1365 irqreturn_t (*handler)(int, void *);
1366 int i, vector, q_vectors, err;
cb13fc20 1367 int ri=0, ti=0;
021230d4
AV		 1368
1369 /* Decrement for Other and TCP Timer vectors */
1370 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1371
1372 /* Map the Tx/Rx rings to the vectors we were allotted. */
1373 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1374 if (err)
1375 goto out;
1376
1377#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1378 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1379 &ixgbe_msix_clean_many)
021230d4
AV		 1380 for (vector = 0; vector < q_vectors; vector++) {
1381 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1382
1383 if(handler == &ixgbe_msix_clean_rx) {
1384 sprintf(adapter->name[vector], "%s-%s-%d",
1385 netdev->name, "rx", ri++);
1386 }
1387 else if(handler == &ixgbe_msix_clean_tx) {
1388 sprintf(adapter->name[vector], "%s-%s-%d",
1389 netdev->name, "tx", ti++);
1390 }
1391 else
1392 sprintf(adapter->name[vector], "%s-%s-%d",
1393 netdev->name, "TxRx", vector);
1394
021230d4 1395 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1396 handler, 0, adapter->name[vector],
1397 &(adapter->q_vector[vector]));
9a799d71
AK		 1398 if (err) {
1399 DPRINTK(PROBE, ERR,
b4617240
PW		 1400 "request_irq failed for MSIX interrupt "
1401 "Error: %d\n", err);
021230d4 1402 goto free_queue_irqs;
9a799d71 1403 }
9a799d71
AK		 1404 }
1405
021230d4
AV		 1406 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1407 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1408 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1409 if (err) {
1410 DPRINTK(PROBE, ERR,
1411 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1412 goto free_queue_irqs;
9a799d71
AK		 1413 }
1414
9a799d71
AK		 1415 return 0;
1416
021230d4
AV		 1417free_queue_irqs:
1418 for (i = vector - 1; i >= 0; i--)
1419 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1420 &(adapter->q_vector[i]));
021230d4
AV		 1421 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1422 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1423 kfree(adapter->msix_entries);
1424 adapter->msix_entries = NULL;
021230d4 1425out:
9a799d71
AK		 1426 return err;
1427}
1428
f494e8fa
AV		 1429static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1430{
f494e8fa
AV		 1431 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1432 u8 current_itr;
1433 u32 new_itr = q_vector->eitr;
1434 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1435 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1436
30efa5a3 1437 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1438 q_vector->tx_itr,
1439 tx_ring->total_packets,
1440 tx_ring->total_bytes);
30efa5a3 1441 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1442 q_vector->rx_itr,
1443 rx_ring->total_packets,
1444 rx_ring->total_bytes);
f494e8fa 1445
30efa5a3 1446 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1447
1448 switch (current_itr) {
1449 /* counts and packets in update_itr are dependent on these numbers */
1450 case lowest_latency:
1451 new_itr = 100000;
1452 break;
1453 case low_latency:
1454 new_itr = 20000; /* aka hwitr = ~200 */
1455 break;
1456 case bulk_latency:
1457 new_itr = 8000;
1458 break;
1459 default:
1460 break;
1461 }
1462
1463 if (new_itr != q_vector->eitr) {
1464 u32 itr_reg;
509ee935
JB		 1465
1466 /* save the algorithm value here, not the smoothed one */
1467 q_vector->eitr = new_itr;
f494e8fa
AV		 1468 /* do an exponential smoothing */
1469 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1470 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1471 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1472 }
1473
1474 return;
1475}
1476
79aefa45
AD		 1477/**
1478 * ixgbe_irq_enable - Enable default interrupt generation settings
1479 * @adapter: board private structure
1480 **/
1481static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1482{
1483 u32 mask;
1484 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1485 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1486 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1487 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1488 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1489 mask |= IXGBE_EIMS_GPI_SDP1;
1490 mask |= IXGBE_EIMS_GPI_SDP2;
1491 }
1492
79aefa45 1493 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
e8e26350
PW		 1494 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1495 /* enable the rest of the queue vectors */
1496 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1497 (IXGBE_EIMS_RTX_QUEUE << 16));
1498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1499 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1500 IXGBE_EIMS_RTX_QUEUE));
1501 }
79aefa45
AD		 1502 IXGBE_WRITE_FLUSH(&adapter->hw);
1503}
021230d4 1504
9a799d71 1505/**
021230d4 1506 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1507 * @irq: interrupt number
1508 * @data: pointer to a network interface device structure
9a799d71
AK		 1509 **/
1510static irqreturn_t ixgbe_intr(int irq, void *data)
1511{
1512 struct net_device *netdev = data;
1513 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1514 struct ixgbe_hw *hw = &adapter->hw;
1515 u32 eicr;
1516
54037505
DS		 1517 /*
1518 * Workaround for silicon errata. Mask the interrupts
1519 * before the read of EICR.
1520 */
1521 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1522
021230d4
AV		 1523 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1524 * therefore no explict interrupt disable is necessary */
1525 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1526 if (!eicr) {
1527 /* shared interrupt alert!
1528 * make sure interrupts are enabled because the read will
1529 * have disabled interrupts due to EIAM */
1530 ixgbe_irq_enable(adapter);
9a799d71 1531 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1532 }
9a799d71 1533
cf8280ee
JB		 1534 if (eicr & IXGBE_EICR_LSC)
1535 ixgbe_check_lsc(adapter);
021230d4 1536
e8e26350
PW		 1537 if (hw->mac.type == ixgbe_mac_82599EB)
1538 ixgbe_check_sfp_event(adapter, eicr);
1539
0befdb3e
JB		 1540 ixgbe_check_fan_failure(adapter, eicr);
1541
288379f0 1542 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1543 adapter->tx_ring[0].total_packets = 0;
1544 adapter->tx_ring[0].total_bytes = 0;
1545 adapter->rx_ring[0].total_packets = 0;
1546 adapter->rx_ring[0].total_bytes = 0;
021230d4 1547 /* would disable interrupts here but EIAM disabled it */
288379f0 1548 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1549 }
1550
1551 return IRQ_HANDLED;
1552}
1553
021230d4
AV		 1554static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1555{
1556 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1557
1558 for (i = 0; i < q_vectors; i++) {
1559 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1560 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1561 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1562 q_vector->rxr_count = 0;
1563 q_vector->txr_count = 0;
1564 }
1565}
1566
9a799d71
AK		 1567/**
1568 * ixgbe_request_irq - initialize interrupts
1569 * @adapter: board private structure
1570 *
1571 * Attempts to configure interrupts using the best available
1572 * capabilities of the hardware and kernel.
1573 **/
021230d4 1574static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1575{
1576 struct net_device *netdev = adapter->netdev;
021230d4 1577 int err;
9a799d71 1578
021230d4
AV		 1579 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1580 err = ixgbe_request_msix_irqs(adapter);
1581 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1582 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1583 netdev->name, netdev);
021230d4
AV		 1584 } else {
1585 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1586 netdev->name, netdev);
9a799d71
AK		 1587 }
1588
9a799d71
AK		 1589 if (err)
1590 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1591
9a799d71
AK		 1592 return err;
1593}
1594
1595static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1596{
1597 struct net_device *netdev = adapter->netdev;
1598
1599 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1600 int i, q_vectors;
9a799d71 1601
021230d4
AV		 1602 q_vectors = adapter->num_msix_vectors;
1603
1604 i = q_vectors - 1;
9a799d71 1605 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1606
021230d4
AV		 1607 i--;
1608 for (; i >= 0; i--) {
1609 free_irq(adapter->msix_entries[i].vector,
b4617240 1610 &(adapter->q_vector[i]));
021230d4
AV		 1611 }
1612
1613 ixgbe_reset_q_vectors(adapter);
1614 } else {
1615 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1616 }
1617}
1618
22d5a71b
JB		 1619/**
1620 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1621 * @adapter: board private structure
1622 **/
1623static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1624{
1625 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1626 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1629 }
1630 IXGBE_WRITE_FLUSH(&adapter->hw);
1631 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1632 int i;
1633 for (i = 0; i < adapter->num_msix_vectors; i++)
1634 synchronize_irq(adapter->msix_entries[i].vector);
1635 } else {
1636 synchronize_irq(adapter->pdev->irq);
1637 }
1638}
1639
1640static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter)
1641{
1642 u32 mask = IXGBE_EIMS_RTX_QUEUE;
1643 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1644 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1645 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask << 16);
1646 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1647 (mask << 16 | mask));
1648 }
1649 /* skip the flush */
1650}
1651
9a799d71
AK		 1652/**
1653 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1654 *
1655 **/
1656static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1657{
9a799d71
AK		 1658 struct ixgbe_hw *hw = &adapter->hw;
1659
021230d4 1660 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1661 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1662
e8e26350
PW		 1663 ixgbe_set_ivar(adapter, 0, 0, 0);
1664 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1665
1666 map_vector_to_rxq(adapter, 0, 0);
1667 map_vector_to_txq(adapter, 0, 0);
1668
1669 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1670}
1671
1672/**
3a581073 1673 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1674 * @adapter: board private structure
1675 *
1676 * Configure the Tx unit of the MAC after a reset.
1677 **/
1678static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1679{
12207e49 1680 u64 tdba;
9a799d71 1681 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1682 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1683
1684 /* Setup the HW Tx Head and Tail descriptor pointers */
1685 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1686 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1687 j = ring->reg_idx;
1688 tdba = ring->dma;
1689 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1690 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1691 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1692 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1693 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1694 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1695 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1696 adapter->tx_ring[i].head = IXGBE_TDH(j);
1697 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1698 /* Disable Tx Head Writeback RO bit, since this hoses
1699 * bookkeeping if things aren't delivered in order.
1700 */
e01c31a5 1701 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1702 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1703 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1704 }
e8e26350
PW		 1705 if (hw->mac.type == ixgbe_mac_82599EB) {
1706 /* We enable 8 traffic classes, DCB only */
1707 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1708 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1709 IXGBE_MTQC_8TC_8TQ));
1710 }
9a799d71
AK		 1711}
1712
e8e26350 1713#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1714
1715static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1716{
1717 struct ixgbe_ring *rx_ring;
1718 u32 srrctl;
e8e26350 1719 int queue0 = 0;
3be1adfb
AD		 1720 unsigned long mask;
1721
e8e26350
PW		 1722 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1723 queue0 = index;
cc41ac7c 1724 } else {
3be1adfb
AD		 1725 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1726 queue0 = index & mask;
1727 index = index & mask;
cc41ac7c 1728 }
3be1adfb 1729
cc41ac7c
JB		 1730 rx_ring = &adapter->rx_ring[queue0];
1731
1732 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1733
1734 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1735 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1736
1737 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1738 u16 bufsz = IXGBE_RXBUFFER_2048;
1739 /* grow the amount we can receive on large page machines */
1740 if (bufsz < (PAGE_SIZE / 2))
1741 bufsz = (PAGE_SIZE / 2);
1742 /* cap the bufsz at our largest descriptor size */
1743 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1744
1745 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1746 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1747 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1748 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1749 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1750 } else {
1751 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1752
1753 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1754 srrctl |= IXGBE_RXBUFFER_2048 >>
1755 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1756 else
1757 srrctl |= rx_ring->rx_buf_len >>
1758 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1759 }
e8e26350 1760
cc41ac7c
JB		 1761 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1762}
9a799d71 1763
9a799d71 1764/**
3a581073 1765 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1766 * @adapter: board private structure
1767 *
1768 * Configure the Rx unit of the MAC after a reset.
1769 **/
1770static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1771{
1772 u64 rdba;
1773 struct ixgbe_hw *hw = &adapter->hw;
1774 struct net_device *netdev = adapter->netdev;
1775 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1776 int i, j;
9a799d71 1777 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1778 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1779 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1780 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1781 u32 fctrl, hlreg0;
509ee935 1782 u32 reta = 0, mrqc = 0;
cc41ac7c 1783 u32 rdrxctl;
f8212f97 1784 u32 rscctrl;
7c6e0a43 1785 int rx_buf_len;
9a799d71
AK		 1786
1787 /* Decide whether to use packet split mode or not */
762f4c57 1788 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1789
1790 /* Set the RX buffer length according to the mode */
1791 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1792 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1793 if (hw->mac.type == ixgbe_mac_82599EB) {
1794 /* PSRTYPE must be initialized in 82599 */
1795 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1796 IXGBE_PSRTYPE_UDPHDR |
1797 IXGBE_PSRTYPE_IPV4HDR |
1798 IXGBE_PSRTYPE_IPV6HDR;
1799 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1800 }
9a799d71 1801 } else {
f8212f97
AD		 1802 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1803 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1804 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1805 else
7c6e0a43 1806 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1807 }
1808
1809 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1810 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1811 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1812 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1813 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1814
1815 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1816 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1817 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1818 else
1819 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1820 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1821
9a799d71
AK		 1822 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1823 /* disable receives while setting up the descriptors */
1824 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1825 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1826
1827 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1828 * the Base and Length of the Rx Descriptor Ring */
1829 for (i = 0; i < adapter->num_rx_queues; i++) {
1830 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1831 j = adapter->rx_ring[i].reg_idx;
284901a9 1832 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1833 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1834 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1835 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1836 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1837 adapter->rx_ring[i].head = IXGBE_RDH(j);
1838 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1839 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1840
1841 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1842 }
1843
e8e26350
PW		 1844 if (hw->mac.type == ixgbe_mac_82598EB) {
1845 /*
1846 * For VMDq support of different descriptor types or
1847 * buffer sizes through the use of multiple SRRCTL
1848 * registers, RDRXCTL.MVMEN must be set to 1
1849 *
1850 * also, the manual doesn't mention it clearly but DCA hints
1851 * will only use queue 0's tags unless this bit is set. Side
1852 * effects of setting this bit are only that SRRCTL must be
1853 * fully programmed [0..15]
1854 */
2a41ff81
JB		 1855 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1856 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1857 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1858 }
177db6ff 1859
e8e26350
PW		 1860 /* Program MRQC for the distribution of queues */
1861 if (hw->mac.type == ixgbe_mac_82599EB) {
1862 int mask = adapter->flags & (
1863 IXGBE_FLAG_RSS_ENABLED
1864 | IXGBE_FLAG_DCB_ENABLED
1865 );
1866
1867 switch (mask) {
1868 case (IXGBE_FLAG_RSS_ENABLED):
1869 mrqc = IXGBE_MRQC_RSSEN;
1870 break;
1871 case (IXGBE_FLAG_DCB_ENABLED):
1872 mrqc = IXGBE_MRQC_RT8TCEN;
1873 break;
1874 default:
1875 break;
1876 }
1877 }
021230d4 1878 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1879 /* Fill out redirection table */
021230d4
AV		 1880 for (i = 0, j = 0; i < 128; i++, j++) {
1881 if (j == adapter->ring_feature[RING_F_RSS].indices)
1882 j = 0;
1883 /* reta = 4-byte sliding window of
1884 * 0x00..(indices-1)(indices-1)00..etc. */
1885 reta = (reta << 8) | (j * 0x11);
1886 if ((i & 3) == 3)
1887 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1888 }
1889
1890 /* Fill out hash function seeds */
1891 for (i = 0; i < 10; i++)
7c6e0a43 1892 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1893
2a41ff81
JB		 1894 if (hw->mac.type == ixgbe_mac_82598EB)
1895 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1896 /* Perform hash on these packet types */
2a41ff81
JB		 1897 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1898 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1899 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1900 | IXGBE_MRQC_RSS_FIELD_IPV6
1901 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1902 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1903 }
2a41ff81 1904 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1905
021230d4
AV		 1906 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1907
1908 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1909 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1910 /* Disable indicating checksum in descriptor, enables
1911 * RSS hash */
9a799d71 1912 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1913 }
021230d4
AV		 1914 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1915 /* Enable IPv4 payload checksum for UDP fragments
1916 * if PCSD is not set */
1917 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1918 }
1919
1920 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1921
1922 if (hw->mac.type == ixgbe_mac_82599EB) {
1923 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1924 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 1925 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 1926 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1927 }
f8212f97
AD		 1928
1929 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1930 /* Enable 82599 HW-RSC */
1931 for (i = 0; i < adapter->num_rx_queues; i++) {
1932 j = adapter->rx_ring[i].reg_idx;
1933 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1934 rscctrl |= IXGBE_RSCCTL_RSCEN;
1935 /*
1936 * if packet split is enabled we can only support up
1937 * to max frags + 1 descriptors.
1938 */
1939 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1940#if (MAX_SKB_FRAGS < 3)
1941 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1942#elif (MAX_SKB_FRAGS < 7)
1943 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1944#elif (MAX_SKB_FRAGS < 15)
1945 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1946#else
1947 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1948#endif
1949 else
1950 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1951 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1952 }
1953 /* Disable RSC for ACK packets */
1954 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1955 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1956 }
9a799d71
AK		 1957}
1958
068c89b0
DS		 1959static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1960{
1961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1962 struct ixgbe_hw *hw = &adapter->hw;
1963
1964 /* add VID to filter table */
1965 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1966}
1967
1968static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1969{
1970 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1971 struct ixgbe_hw *hw = &adapter->hw;
1972
1973 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1974 ixgbe_irq_disable(adapter);
1975
1976 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1977
1978 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1979 ixgbe_irq_enable(adapter);
1980
1981 /* remove VID from filter table */
1982 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1983}
1984
9a799d71 1985static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1986 struct vlan_group *grp)
9a799d71
AK		 1987{
1988 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1989 u32 ctrl;
e8e26350 1990 int i, j;
9a799d71 1991
d4f80882
AV		 1992 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1993 ixgbe_irq_disable(adapter);
9a799d71
AK		 1994 adapter->vlgrp = grp;
1995
2f90b865
AD		 1996 /*
1997 * For a DCB driver, always enable VLAN tag stripping so we can
1998 * still receive traffic from a DCB-enabled host even if we're
1999 * not in DCB mode.
2000 */
2001 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2002 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2003 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2004 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2006 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2007 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2008 /* enable VLAN tag insert/strip */
2009 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2010 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2011 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2012 for (i = 0; i < adapter->num_rx_queues; i++) {
2013 j = adapter->rx_ring[i].reg_idx;
2014 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2015 ctrl |= IXGBE_RXDCTL_VME;
2016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2017 }
9a799d71 2018 }
e8e26350 2019 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2020
d4f80882
AV		 2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable(adapter);
9a799d71
AK		 2023}
2024
9a799d71
AK		 2025static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2026{
2027 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2028
2029 if (adapter->vlgrp) {
2030 u16 vid;
2031 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2032 if (!vlan_group_get_device(adapter->vlgrp, vid))
2033 continue;
2034 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2035 }
2036 }
2037}
2038
2c5645cf
CL		 2039static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2040{
2041 struct dev_mc_list *mc_ptr;
2042 u8 *addr = *mc_addr_ptr;
2043 *vmdq = 0;
2044
2045 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2046 if (mc_ptr->next)
2047 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2048 else
2049 *mc_addr_ptr = NULL;
2050
2051 return addr;
2052}
2053
9a799d71 2054/**
2c5645cf 2055 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2056 * @netdev: network interface device structure
2057 *
2c5645cf
CL		 2058 * The set_rx_method entry point is called whenever the unicast/multicast
2059 * address list or the network interface flags are updated. This routine is
2060 * responsible for configuring the hardware for proper unicast, multicast and
2061 * promiscuous mode.
9a799d71 2062 **/
2c5645cf 2063static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2064{
2065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2066 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2067 u32 fctrl, vlnctrl;
2c5645cf
CL		 2068 u8 *addr_list = NULL;
2069 int addr_count = 0;
9a799d71
AK		 2070
2071 /* Check for Promiscuous and All Multicast modes */
2072
2073 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2074 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2075
2076 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2077 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2078 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2079 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2080 } else {
746b9f02
PM		 2081 if (netdev->flags & IFF_ALLMULTI) {
2082 fctrl |= IXGBE_FCTRL_MPE;
2083 fctrl &= ~IXGBE_FCTRL_UPE;
2084 } else {
2085 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2086 }
3d01625a 2087 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2088 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2089 }
2090
2091 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2092 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2093
2c5645cf
CL		 2094 /* reprogram secondary unicast list */
2095 addr_count = netdev->uc_count;
2096 if (addr_count)
2097 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2098 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2099 ixgbe_addr_list_itr);
9a799d71 2100
2c5645cf
CL		 2101 /* reprogram multicast list */
2102 addr_count = netdev->mc_count;
2103 if (addr_count)
2104 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2105 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2106 ixgbe_addr_list_itr);
9a799d71
AK		 2107}
2108
021230d4
AV		 2109static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2110{
2111 int q_idx;
2112 struct ixgbe_q_vector *q_vector;
2113 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2114
2115 /* legacy and MSI only use one vector */
2116 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2117 q_vectors = 1;
2118
2119 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2120 struct napi_struct *napi;
021230d4
AV		 2121 q_vector = &adapter->q_vector[q_idx];
2122 if (!q_vector->rxr_count)
2123 continue;
f0848276
JB		 2124 napi = &q_vector->napi;
2125 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2126 (q_vector->rxr_count > 1))
2127 napi->poll = &ixgbe_clean_rxonly_many;
2128
2129 napi_enable(napi);
021230d4
AV		 2130 }
2131}
2132
2133static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2134{
2135 int q_idx;
2136 struct ixgbe_q_vector *q_vector;
2137 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2138
2139 /* legacy and MSI only use one vector */
2140 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2141 q_vectors = 1;
2142
2143 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2144 q_vector = &adapter->q_vector[q_idx];
2145 if (!q_vector->rxr_count)
2146 continue;
2147 napi_disable(&q_vector->napi);
2148 }
2149}
2150
7a6b6f51 2151#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2152/*
2153 * ixgbe_configure_dcb - Configure DCB hardware
2154 * @adapter: ixgbe adapter struct
2155 *
2156 * This is called by the driver on open to configure the DCB hardware.
2157 * This is also called by the gennetlink interface when reconfiguring
2158 * the DCB state.
2159 */
2160static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2161{
2162 struct ixgbe_hw *hw = &adapter->hw;
2163 u32 txdctl, vlnctrl;
2164 int i, j;
2165
2166 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2167 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2168 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2169
2170 /* reconfigure the hardware */
2171 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2172
2173 for (i = 0; i < adapter->num_tx_queues; i++) {
2174 j = adapter->tx_ring[i].reg_idx;
2175 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2176 /* PThresh workaround for Tx hang with DFP enabled. */
2177 txdctl |= 32;
2178 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2179 }
2180 /* Enable VLAN tag insert/strip */
2181 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2182 if (hw->mac.type == ixgbe_mac_82598EB) {
2183 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2184 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2185 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2186 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2187 vlnctrl |= IXGBE_VLNCTRL_VFE;
2188 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2189 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2190 for (i = 0; i < adapter->num_rx_queues; i++) {
2191 j = adapter->rx_ring[i].reg_idx;
2192 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2193 vlnctrl |= IXGBE_RXDCTL_VME;
2194 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2195 }
2196 }
2f90b865
AD		 2197 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2198}
2199
2200#endif
9a799d71
AK		 2201static void ixgbe_configure(struct ixgbe_adapter *adapter)
2202{
2203 struct net_device *netdev = adapter->netdev;
2204 int i;
2205
2c5645cf 2206 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2207
2208 ixgbe_restore_vlan(adapter);
7a6b6f51 2209#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2210 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2211 netif_set_gso_max_size(netdev, 32768);
2212 ixgbe_configure_dcb(adapter);
2213 } else {
2214 netif_set_gso_max_size(netdev, 65536);
2215 }
2216#else
2217 netif_set_gso_max_size(netdev, 65536);
2218#endif
9a799d71
AK		 2219
2220 ixgbe_configure_tx(adapter);
2221 ixgbe_configure_rx(adapter);
2222 for (i = 0; i < adapter->num_rx_queues; i++)
2223 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2224 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2225}
2226
e8e26350
PW		 2227static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2228{
2229 switch (hw->phy.type) {
2230 case ixgbe_phy_sfp_avago:
2231 case ixgbe_phy_sfp_ftl:
2232 case ixgbe_phy_sfp_intel:
2233 case ixgbe_phy_sfp_unknown:
2234 case ixgbe_phy_tw_tyco:
2235 case ixgbe_phy_tw_unknown:
2236 return true;
2237 default:
2238 return false;
2239 }
2240}
2241
0ecc061d 2242/**
e8e26350
PW		 2243 * ixgbe_sfp_link_config - set up SFP+ link
2244 * @adapter: pointer to private adapter struct
2245 **/
2246static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2247{
2248 struct ixgbe_hw *hw = &adapter->hw;
2249
2250 if (hw->phy.multispeed_fiber) {
2251 /*
2252 * In multispeed fiber setups, the device may not have
2253 * had a physical connection when the driver loaded.
2254 * If that's the case, the initial link configuration
2255 * couldn't get the MAC into 10G or 1G mode, so we'll
2256 * never have a link status change interrupt fire.
2257 * We need to try and force an autonegotiation
2258 * session, then bring up link.
2259 */
2260 hw->mac.ops.setup_sfp(hw);
2261 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2262 schedule_work(&adapter->multispeed_fiber_task);
2263 } else {
2264 /*
2265 * Direct Attach Cu and non-multispeed fiber modules
2266 * still need to be configured properly prior to
2267 * attempting link.
2268 */
2269 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2270 schedule_work(&adapter->sfp_config_module_task);
2271 }
2272}
2273
2274/**
2275 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2276 * @hw: pointer to private hardware struct
2277 *
2278 * Returns 0 on success, negative on failure
2279 **/
e8e26350 2280static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2281{
2282 u32 autoneg;
2283 bool link_up = false;
2284 u32 ret = IXGBE_ERR_LINK_SETUP;
2285
2286 if (hw->mac.ops.check_link)
2287 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2288
2289 if (ret)
2290 goto link_cfg_out;
2291
2292 if (hw->mac.ops.get_link_capabilities)
2293 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2294 &hw->mac.autoneg);
2295 if (ret)
2296 goto link_cfg_out;
2297
2298 if (hw->mac.ops.setup_link_speed)
2299 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2300link_cfg_out:
2301 return ret;
2302}
2303
e8e26350
PW		 2304#define IXGBE_MAX_RX_DESC_POLL 10
2305static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2306 int rxr)
2307{
2308 int j = adapter->rx_ring[rxr].reg_idx;
2309 int k;
2310
2311 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2312 if (IXGBE_READ_REG(&adapter->hw,
2313 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2314 break;
2315 else
2316 msleep(1);
2317 }
2318 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2319 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2320 "not set within the polling period\n", rxr);
2321 }
2322 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2323 (adapter->rx_ring[rxr].count - 1));
2324}
2325
9a799d71
AK		 2326static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2327{
2328 struct net_device *netdev = adapter->netdev;
9a799d71 2329 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2330 int i, j = 0;
e8e26350 2331 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2332 int err;
9a799d71 2333 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2334 u32 txdctl, rxdctl, mhadd;
e8e26350 2335 u32 dmatxctl;
021230d4 2336 u32 gpie;
9a799d71 2337
5eba3699
AV		 2338 ixgbe_get_hw_control(adapter);
2339
021230d4
AV		 2340 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2341 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2344 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2345 } else {
2346 /* MSI only */
021230d4 2347 gpie = 0;
9a799d71 2348 }
021230d4
AV		 2349 /* XXX: to interrupt immediately for EICS writes, enable this */
2350 /* gpie |= IXGBE_GPIE_EIMEN; */
2351 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2352 }
2353
021230d4
AV		 2354 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2355 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2356 * specifically only auto mask tx and rx interrupts */
2357 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2358 }
9a799d71 2359
0befdb3e
JB		 2360 /* Enable fan failure interrupt if media type is copper */
2361 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2362 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2363 gpie |= IXGBE_SDP1_GPIEN;
2364 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2365 }
2366
e8e26350
PW		 2367 if (hw->mac.type == ixgbe_mac_82599EB) {
2368 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2369 gpie |= IXGBE_SDP1_GPIEN;
2370 gpie |= IXGBE_SDP2_GPIEN;
2371 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2372 }
2373
021230d4 2374 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2375 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2376 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2377 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2378
2379 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2380 }
2381
2382 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2383 j = adapter->tx_ring[i].reg_idx;
2384 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2385 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2386 txdctl |= (8 << 16);
e8e26350
PW		 2387 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2388 }
2389
2390 if (hw->mac.type == ixgbe_mac_82599EB) {
2391 /* DMATXCTL.EN must be set after all Tx queue config is done */
2392 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2393 dmatxctl |= IXGBE_DMATXCTL_TE;
2394 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2395 }
2396 for (i = 0; i < adapter->num_tx_queues; i++) {
2397 j = adapter->tx_ring[i].reg_idx;
2398 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2399 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2400 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2401 }
2402
e8e26350 2403 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2404 j = adapter->rx_ring[i].reg_idx;
2405 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2406 /* enable PTHRESH=32 descriptors (half the internal cache)
2407 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2408 * this also removes a pesky rx_no_buffer_count increment */
2409 rxdctl |= 0x0020;
9a799d71 2410 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2411 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2412 if (hw->mac.type == ixgbe_mac_82599EB)
2413 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2414 }
2415 /* enable all receives */
2416 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2417 if (hw->mac.type == ixgbe_mac_82598EB)
2418 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2419 else
2420 rxdctl |= IXGBE_RXCTRL_RXEN;
2421 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2422
2423 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2424 ixgbe_configure_msix(adapter);
2425 else
2426 ixgbe_configure_msi_and_legacy(adapter);
2427
2428 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2429 ixgbe_napi_enable_all(adapter);
2430
2431 /* clear any pending interrupts, may auto mask */
2432 IXGBE_READ_REG(hw, IXGBE_EICR);
2433
9a799d71
AK		 2434 ixgbe_irq_enable(adapter);
2435
e8e26350
PW		 2436 /*
2437 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2438 * arrived before interrupts were enabled. We need to kick off
2439 * the SFP+ module setup first, then try to bring up link.
2440 * If we're not hot-pluggable SFP+, we just need to configure link
2441 * and bring it up.
2442 */
2443 err = hw->phy.ops.identify(hw);
2444 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2445 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2446 ixgbe_down(adapter);
2447 return err;
2448 }
2449
2450 if (ixgbe_is_sfp(hw)) {
2451 ixgbe_sfp_link_config(adapter);
2452 } else {
2453 err = ixgbe_non_sfp_link_config(hw);
2454 if (err)
2455 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2456 }
0ecc061d 2457
1da100bb
PWJ		 2458 /* enable transmits */
2459 netif_tx_start_all_queues(netdev);
2460
9a799d71
AK		 2461 /* bring the link up in the watchdog, this could race with our first
2462 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2463 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2464 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2465 mod_timer(&adapter->watchdog_timer, jiffies);
2466 return 0;
2467}
2468
d4f80882
AV		 2469void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2470{
2471 WARN_ON(in_interrupt());
2472 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2473 msleep(1);
2474 ixgbe_down(adapter);
2475 ixgbe_up(adapter);
2476 clear_bit(__IXGBE_RESETTING, &adapter->state);
2477}
2478
9a799d71
AK		 2479int ixgbe_up(struct ixgbe_adapter *adapter)
2480{
2481 /* hardware has been reset, we need to reload some things */
2482 ixgbe_configure(adapter);
2483
4dd64df8
JB		 2484 ixgbe_napi_add_all(adapter);
2485
9a799d71
AK		 2486 return ixgbe_up_complete(adapter);
2487}
2488
2489void ixgbe_reset(struct ixgbe_adapter *adapter)
2490{
c44ade9e
JB		 2491 struct ixgbe_hw *hw = &adapter->hw;
2492 if (hw->mac.ops.init_hw(hw))
2493 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2494
2495 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2496 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2497
2498}
2499
9a799d71
AK		 2500/**
2501 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2502 * @adapter: board private structure
2503 * @rx_ring: ring to free buffers from
2504 **/
2505static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2506 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2507{
2508 struct pci_dev *pdev = adapter->pdev;
2509 unsigned long size;
2510 unsigned int i;
2511
2512 /* Free all the Rx ring sk_buffs */
2513
2514 for (i = 0; i < rx_ring->count; i++) {
2515 struct ixgbe_rx_buffer *rx_buffer_info;
2516
2517 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2518 if (rx_buffer_info->dma) {
2519 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2520 rx_ring->rx_buf_len,
2521 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2522 rx_buffer_info->dma = 0;
2523 }
2524 if (rx_buffer_info->skb) {
f8212f97 2525 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2526 rx_buffer_info->skb = NULL;
f8212f97
AD		 2527 do {
2528 struct sk_buff *this = skb;
2529 skb = skb->prev;
2530 dev_kfree_skb(this);
2531 } while (skb);
9a799d71
AK		 2532 }
2533 if (!rx_buffer_info->page)
2534 continue;
762f4c57
JB		 2535 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2536 PCI_DMA_FROMDEVICE);
9a799d71 2537 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2538 put_page(rx_buffer_info->page);
2539 rx_buffer_info->page = NULL;
762f4c57 2540 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2541 }
2542
2543 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2544 memset(rx_ring->rx_buffer_info, 0, size);
2545
2546 /* Zero out the descriptor ring */
2547 memset(rx_ring->desc, 0, rx_ring->size);
2548
2549 rx_ring->next_to_clean = 0;
2550 rx_ring->next_to_use = 0;
2551
9891ca7c
JB		 2552 if (rx_ring->head)
2553 writel(0, adapter->hw.hw_addr + rx_ring->head);
2554 if (rx_ring->tail)
2555 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2556}
2557
2558/**
2559 * ixgbe_clean_tx_ring - Free Tx Buffers
2560 * @adapter: board private structure
2561 * @tx_ring: ring to be cleaned
2562 **/
2563static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2564 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2565{
2566 struct ixgbe_tx_buffer *tx_buffer_info;
2567 unsigned long size;
2568 unsigned int i;
2569
2570 /* Free all the Tx ring sk_buffs */
2571
2572 for (i = 0; i < tx_ring->count; i++) {
2573 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2574 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2575 }
2576
2577 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2578 memset(tx_ring->tx_buffer_info, 0, size);
2579
2580 /* Zero out the descriptor ring */
2581 memset(tx_ring->desc, 0, tx_ring->size);
2582
2583 tx_ring->next_to_use = 0;
2584 tx_ring->next_to_clean = 0;
2585
9891ca7c
JB		 2586 if (tx_ring->head)
2587 writel(0, adapter->hw.hw_addr + tx_ring->head);
2588 if (tx_ring->tail)
2589 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2590}
2591
2592/**
021230d4 2593 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2594 * @adapter: board private structure
2595 **/
021230d4 2596static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2597{
2598 int i;
2599
021230d4
AV		 2600 for (i = 0; i < adapter->num_rx_queues; i++)
2601 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2602}
2603
2604/**
021230d4 2605 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2606 * @adapter: board private structure
2607 **/
021230d4 2608static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2609{
2610 int i;
2611
021230d4
AV		 2612 for (i = 0; i < adapter->num_tx_queues; i++)
2613 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2614}
2615
2616void ixgbe_down(struct ixgbe_adapter *adapter)
2617{
2618 struct net_device *netdev = adapter->netdev;
7f821875 2619 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2620 u32 rxctrl;
7f821875
JB		 2621 u32 txdctl;
2622 int i, j;
9a799d71
AK		 2623
2624 /* signal that we are down to the interrupt handler */
2625 set_bit(__IXGBE_DOWN, &adapter->state);
2626
2627 /* disable receives */
7f821875
JB		 2628 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2629 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2630
2631 netif_tx_disable(netdev);
2632
7f821875 2633 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2634 msleep(10);
2635
7f821875
JB		 2636 netif_tx_stop_all_queues(netdev);
2637
9a799d71
AK		 2638 ixgbe_irq_disable(adapter);
2639
021230d4 2640 ixgbe_napi_disable_all(adapter);
7f821875 2641
9a799d71 2642 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2643 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2644
7f821875
JB		 2645 /* disable transmits in the hardware now that interrupts are off */
2646 for (i = 0; i < adapter->num_tx_queues; i++) {
2647 j = adapter->tx_ring[i].reg_idx;
2648 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2649 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2650 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2651 }
88512539
PW		 2652 /* Disable the Tx DMA engine on 82599 */
2653 if (hw->mac.type == ixgbe_mac_82599EB)
2654 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2655 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2656 ~IXGBE_DMATXCTL_TE));
7f821875 2657
9a799d71 2658 netif_carrier_off(netdev);
9a799d71 2659
5dd2d332 2660#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2661 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2662 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2663 dca_remove_requester(&adapter->pdev->dev);
2664 }
2665
2666#endif
6f4a0e45
PL		 2667 if (!pci_channel_offline(adapter->pdev))
2668 ixgbe_reset(adapter);
9a799d71
AK		 2669 ixgbe_clean_all_tx_rings(adapter);
2670 ixgbe_clean_all_rx_rings(adapter);
2671
5dd2d332 2672#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2673 /* since we reset the hardware DCA settings were cleared */
2674 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2675 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2676 /* always use CB2 mode, difference is masked
2677 * in the CB driver */
b4617240 2678 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2679 ixgbe_setup_dca(adapter);
2680 }
2681#endif
9a799d71
AK		 2682}
2683
9a799d71 2684/**
021230d4
AV		 2685 * ixgbe_poll - NAPI Rx polling callback
2686 * @napi: structure for representing this polling device
2687 * @budget: how many packets driver is allowed to clean
2688 *
2689 * This function is used for legacy and MSI, NAPI mode
9a799d71 2690 **/
021230d4 2691static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2692{
9a1a69ad
JB		 2693 struct ixgbe_q_vector *q_vector =
2694 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2695 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2696 int tx_clean_complete, work_done = 0;
9a799d71 2697
5dd2d332 2698#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2699 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2700 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2701 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2702 }
2703#endif
2704
9a1a69ad 2705 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2706 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2707
9a1a69ad 2708 if (!tx_clean_complete)
d2c7ddd6
DM		 2709 work_done = budget;
2710
53e52c72
DM		 2711 /* If budget not fully consumed, exit the polling mode */
2712 if (work_done < budget) {
288379f0 2713 napi_complete(napi);
509ee935 2714 if (adapter->itr_setting & 1)
f494e8fa 2715 ixgbe_set_itr(adapter);
d4f80882 2716 if (!test_bit(__IXGBE_DOWN, &adapter->state))
22d5a71b 2717 ixgbe_irq_enable_queues(adapter);
9a799d71 2718 }
9a799d71
AK		 2719 return work_done;
2720}
2721
2722/**
2723 * ixgbe_tx_timeout - Respond to a Tx Hang
2724 * @netdev: network interface device structure
2725 **/
2726static void ixgbe_tx_timeout(struct net_device *netdev)
2727{
2728 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2729
2730 /* Do the reset outside of interrupt context */
2731 schedule_work(&adapter->reset_task);
2732}
2733
2734static void ixgbe_reset_task(struct work_struct *work)
2735{
2736 struct ixgbe_adapter *adapter;
2737 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2738
2f90b865
AD		 2739 /* If we're already down or resetting, just bail */
2740 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2741 test_bit(__IXGBE_RESETTING, &adapter->state))
2742 return;
2743
9a799d71
AK		 2744 adapter->tx_timeout_count++;
2745
d4f80882 2746 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2747}
2748
bc97114d
PWJ		 2749#ifdef CONFIG_IXGBE_DCB
2750static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2751{
bc97114d 2752 bool ret = false;
b9804972 2753
bc97114d
PWJ		 2754 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2755 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2756 adapter->num_rx_queues =
2757 adapter->ring_feature[RING_F_DCB].indices;
2758 adapter->num_tx_queues =
2759 adapter->ring_feature[RING_F_DCB].indices;
2760 ret = true;
2761 } else {
bc97114d
PWJ		 2762 ret = false;
2763 }
2f90b865 2764
bc97114d
PWJ		 2765 return ret;
2766}
2767#endif
2768
4df10466
JB		 2769/**
2770 * ixgbe_set_rss_queues: Allocate queues for RSS
2771 * @adapter: board private structure to initialize
2772 *
2773 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2774 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2775 *
2776 **/
bc97114d
PWJ		 2777static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2778{
2779 bool ret = false;
2780
2781 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2782 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2783 adapter->num_rx_queues =
2784 adapter->ring_feature[RING_F_RSS].indices;
2785 adapter->num_tx_queues =
2786 adapter->ring_feature[RING_F_RSS].indices;
2787 ret = true;
2788 } else {
bc97114d 2789 ret = false;
b9804972
JB		 2790 }
2791
bc97114d
PWJ		 2792 return ret;
2793}
2794
4df10466
JB		 2795/*
2796 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2797 * @adapter: board private structure to initialize
2798 *
2799 * This is the top level queue allocation routine. The order here is very
2800 * important, starting with the "most" number of features turned on at once,
2801 * and ending with the smallest set of features. This way large combinations
2802 * can be allocated if they're turned on, and smaller combinations are the
2803 * fallthrough conditions.
2804 *
2805 **/
bc97114d
PWJ		 2806static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2807{
bc97114d
PWJ		 2808#ifdef CONFIG_IXGBE_DCB
2809 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2810 goto done;
bc97114d
PWJ		 2811
2812#endif
2813 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2814 goto done;
2815
2816 /* fallback to base case */
2817 adapter->num_rx_queues = 1;
2818 adapter->num_tx_queues = 1;
2819
2820done:
2821 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2822 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2823}
2824
021230d4 2825static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2826 int vectors)
021230d4
AV		 2827{
2828 int err, vector_threshold;
2829
2830 /* We'll want at least 3 (vector_threshold):
2831 * 1) TxQ[0] Cleanup
2832 * 2) RxQ[0] Cleanup
2833 * 3) Other (Link Status Change, etc.)
2834 * 4) TCP Timer (optional)
2835 */
2836 vector_threshold = MIN_MSIX_COUNT;
2837
2838 /* The more we get, the more we will assign to Tx/Rx Cleanup
2839 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2840 * Right now, we simply care about how many we'll get; we'll
2841 * set them up later while requesting irq's.
2842 */
2843 while (vectors >= vector_threshold) {
2844 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2845 vectors);
021230d4
AV		 2846 if (!err) /* Success in acquiring all requested vectors. */
2847 break;
2848 else if (err < 0)
2849 vectors = 0; /* Nasty failure, quit now */
2850 else /* err == number of vectors we should try again with */
2851 vectors = err;
2852 }
2853
2854 if (vectors < vector_threshold) {
2855 /* Can't allocate enough MSI-X interrupts? Oh well.
2856 * This just means we'll go with either a single MSI
2857 * vector or fall back to legacy interrupts.
2858 */
2859 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2860 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2861 kfree(adapter->msix_entries);
2862 adapter->msix_entries = NULL;
2f90b865 2863 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2864 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2865 ixgbe_set_num_queues(adapter);
021230d4
AV		 2866 } else {
2867 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2868 /*
2869 * Adjust for only the vectors we'll use, which is minimum
2870 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2871 * vectors we were allocated.
2872 */
2873 adapter->num_msix_vectors = min(vectors,
2874 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2875 }
2876}
2877
021230d4 2878/**
bc97114d 2879 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2880 * @adapter: board private structure to initialize
2881 *
bc97114d
PWJ		 2882 * Cache the descriptor ring offsets for RSS to the assigned rings.
2883 *
021230d4 2884 **/
bc97114d 2885static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2886{
bc97114d
PWJ		 2887 int i;
2888 bool ret = false;
2889
2890 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2891 for (i = 0; i < adapter->num_rx_queues; i++)
2892 adapter->rx_ring[i].reg_idx = i;
2893 for (i = 0; i < adapter->num_tx_queues; i++)
2894 adapter->tx_ring[i].reg_idx = i;
2895 ret = true;
2896 } else {
2897 ret = false;
2898 }
2899
2900 return ret;
2901}
2902
2903#ifdef CONFIG_IXGBE_DCB
2904/**
2905 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2906 * @adapter: board private structure to initialize
2907 *
2908 * Cache the descriptor ring offsets for DCB to the assigned rings.
2909 *
2910 **/
2911static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2912{
2913 int i;
2914 bool ret = false;
2915 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2916
2917 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2918 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2919 /* the number of queues is assumed to be symmetric */
2920 for (i = 0; i < dcb_i; i++) {
2921 adapter->rx_ring[i].reg_idx = i << 3;
2922 adapter->tx_ring[i].reg_idx = i << 2;
2923 }
bc97114d 2924 ret = true;
e8e26350 2925 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 2926 if (dcb_i == 8) {
2927 /*
2928 * Tx TC0 starts at: descriptor queue 0
2929 * Tx TC1 starts at: descriptor queue 32
2930 * Tx TC2 starts at: descriptor queue 64
2931 * Tx TC3 starts at: descriptor queue 80
2932 * Tx TC4 starts at: descriptor queue 96
2933 * Tx TC5 starts at: descriptor queue 104
2934 * Tx TC6 starts at: descriptor queue 112
2935 * Tx TC7 starts at: descriptor queue 120
2936 *
2937 * Rx TC0-TC7 are offset by 16 queues each
2938 */
2939 for (i = 0; i < 3; i++) {
2940 adapter->tx_ring[i].reg_idx = i << 5;
2941 adapter->rx_ring[i].reg_idx = i << 4;
2942 }
2943 for ( ; i < 5; i++) {
2944 adapter->tx_ring[i].reg_idx =
2945 ((i + 2) << 4);
2946 adapter->rx_ring[i].reg_idx = i << 4;
2947 }
2948 for ( ; i < dcb_i; i++) {
2949 adapter->tx_ring[i].reg_idx =
2950 ((i + 8) << 3);
2951 adapter->rx_ring[i].reg_idx = i << 4;
2952 }
2953
2954 ret = true;
2955 } else if (dcb_i == 4) {
2956 /*
2957 * Tx TC0 starts at: descriptor queue 0
2958 * Tx TC1 starts at: descriptor queue 64
2959 * Tx TC2 starts at: descriptor queue 96
2960 * Tx TC3 starts at: descriptor queue 112
2961 *
2962 * Rx TC0-TC3 are offset by 32 queues each
2963 */
2964 adapter->tx_ring[0].reg_idx = 0;
2965 adapter->tx_ring[1].reg_idx = 64;
2966 adapter->tx_ring[2].reg_idx = 96;
2967 adapter->tx_ring[3].reg_idx = 112;
2968 for (i = 0 ; i < dcb_i; i++)
2969 adapter->rx_ring[i].reg_idx = i << 5;
2970
2971 ret = true;
2972 } else {
2973 ret = false;
e8e26350 2974 }
bc97114d
PWJ		 2975 } else {
2976 ret = false;
021230d4 2977 }
bc97114d
PWJ		 2978 } else {
2979 ret = false;
021230d4 2980 }
bc97114d
PWJ		 2981
2982 return ret;
2983}
2984#endif
2985
2986/**
2987 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2988 * @adapter: board private structure to initialize
2989 *
2990 * Once we know the feature-set enabled for the device, we'll cache
2991 * the register offset the descriptor ring is assigned to.
2992 *
2993 * Note, the order the various feature calls is important. It must start with
2994 * the "most" features enabled at the same time, then trickle down to the
2995 * least amount of features turned on at once.
2996 **/
2997static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2998{
2999 /* start with default case */
3000 adapter->rx_ring[0].reg_idx = 0;
3001 adapter->tx_ring[0].reg_idx = 0;
3002
3003#ifdef CONFIG_IXGBE_DCB
3004 if (ixgbe_cache_ring_dcb(adapter))
3005 return;
3006
3007#endif
3008 if (ixgbe_cache_ring_rss(adapter))
3009 return;
021230d4
AV		 3010}
3011
9a799d71
AK		 3012/**
3013 * ixgbe_alloc_queues - Allocate memory for all rings
3014 * @adapter: board private structure to initialize
3015 *
3016 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3017 * number of queues at compile-time. The polling_netdev array is
3018 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3019 **/
2f90b865 3020static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3021{
3022 int i;
3023
3024 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3025 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3026 if (!adapter->tx_ring)
021230d4 3027 goto err_tx_ring_allocation;
9a799d71
AK		 3028
3029 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3030 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3031 if (!adapter->rx_ring)
3032 goto err_rx_ring_allocation;
9a799d71 3033
021230d4 3034 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3035 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3036 adapter->tx_ring[i].queue_index = i;
3037 }
b9804972 3038
9a799d71 3039 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3040 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3041 adapter->rx_ring[i].queue_index = i;
3042 }
3043
3044 ixgbe_cache_ring_register(adapter);
3045
3046 return 0;
3047
3048err_rx_ring_allocation:
3049 kfree(adapter->tx_ring);
3050err_tx_ring_allocation:
3051 return -ENOMEM;
3052}
3053
3054/**
3055 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3056 * @adapter: board private structure to initialize
3057 *
3058 * Attempt to configure the interrupts using the best available
3059 * capabilities of the hardware and the kernel.
3060 **/
feea6a57 3061static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3062{
8be0e467 3063 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3064 int err = 0;
3065 int vector, v_budget;
3066
3067 /*
3068 * It's easy to be greedy for MSI-X vectors, but it really
3069 * doesn't do us much good if we have a lot more vectors
3070 * than CPU's. So let's be conservative and only ask for
3071 * (roughly) twice the number of vectors as there are CPU's.
3072 */
3073 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3074 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3075
3076 /*
3077 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3078 * hw.mac->max_msix_vectors vectors. With features
3079 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3080 * descriptor queues supported by our device. Thus, we cap it off in
3081 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3082 */
8be0e467 3083 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3084
3085 /* A failure in MSI-X entry allocation isn't fatal, but it does
3086 * mean we disable MSI-X capabilities of the adapter. */
3087 adapter->msix_entries = kcalloc(v_budget,
b4617240 3088 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 3089 if (!adapter->msix_entries) {
2f90b865 3090 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 3091 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3092 ixgbe_set_num_queues(adapter);
3093 kfree(adapter->tx_ring);
3094 kfree(adapter->rx_ring);
3095 err = ixgbe_alloc_queues(adapter);
3096 if (err) {
3097 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 3098 "for queues\n");
021230d4
AV		 3099 goto out;
3100 }
3101
3102 goto try_msi;
3103 }
3104
3105 for (vector = 0; vector < v_budget; vector++)
3106 adapter->msix_entries[vector].entry = vector;
3107
3108 ixgbe_acquire_msix_vectors(adapter, v_budget);
3109
3110 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3111 goto out;
3112
3113try_msi:
3114 err = pci_enable_msi(adapter->pdev);
3115 if (!err) {
3116 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3117 } else {
3118 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3119 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3120 /* reset err */
3121 err = 0;
3122 }
3123
3124out:
021230d4
AV		 3125 return err;
3126}
3127
2f90b865 3128void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3129{
3130 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3131 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3132 pci_disable_msix(adapter->pdev);
3133 kfree(adapter->msix_entries);
3134 adapter->msix_entries = NULL;
3135 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3136 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3137 pci_disable_msi(adapter->pdev);
3138 }
3139 return;
3140}
3141
3142/**
3143 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3144 * @adapter: board private structure to initialize
3145 *
3146 * We determine which interrupt scheme to use based on...
3147 * - Kernel support (MSI, MSI-X)
3148 * - which can be user-defined (via MODULE_PARAM)
3149 * - Hardware queue count (num_*_queues)
3150 * - defined by miscellaneous hardware support/features (RSS, etc.)
3151 **/
2f90b865 3152int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3153{
3154 int err;
3155
3156 /* Number of supported queues */
3157 ixgbe_set_num_queues(adapter);
3158
3159 err = ixgbe_alloc_queues(adapter);
3160 if (err) {
3161 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3162 goto err_alloc_queues;
3163 }
3164
3165 err = ixgbe_set_interrupt_capability(adapter);
3166 if (err) {
3167 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3168 goto err_set_interrupt;
9a799d71
AK		 3169 }
3170
021230d4 3171 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3172 "Tx Queue count = %u\n",
3173 (adapter->num_rx_queues > 1) ? "Enabled" :
3174 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3175
3176 set_bit(__IXGBE_DOWN, &adapter->state);
3177
9a799d71 3178 return 0;
021230d4
AV		 3179
3180err_set_interrupt:
3181 kfree(adapter->tx_ring);
3182 kfree(adapter->rx_ring);
3183err_alloc_queues:
3184 return err;
9a799d71
AK		 3185}
3186
c4900be0
DS		 3187/**
3188 * ixgbe_sfp_timer - worker thread to find a missing module
3189 * @data: pointer to our adapter struct
3190 **/
3191static void ixgbe_sfp_timer(unsigned long data)
3192{
3193 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3194
4df10466
JB		 3195 /*
3196 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3197 * delays that sfp+ detection requires
3198 */
3199 schedule_work(&adapter->sfp_task);
3200}
3201
3202/**
3203 * ixgbe_sfp_task - worker thread to find a missing module
3204 * @work: pointer to work_struct containing our data
3205 **/
3206static void ixgbe_sfp_task(struct work_struct *work)
3207{
3208 struct ixgbe_adapter *adapter = container_of(work,
3209 struct ixgbe_adapter,
3210 sfp_task);
3211 struct ixgbe_hw *hw = &adapter->hw;
3212
3213 if ((hw->phy.type == ixgbe_phy_nl) &&
3214 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3215 s32 ret = hw->phy.ops.identify_sfp(hw);
3216 if (ret)
3217 goto reschedule;
3218 ret = hw->phy.ops.reset(hw);
3219 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3220 DPRINTK(PROBE, ERR, "failed to initialize because an "
3221 "unsupported SFP+ module type was detected.\n"
3222 "Reload the driver after installing a "
3223 "supported module.\n");
3224 unregister_netdev(adapter->netdev);
3225 } else {
3226 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3227 hw->phy.sfp_type);
3228 }
3229 /* don't need this routine any more */
3230 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3231 }
3232 return;
3233reschedule:
3234 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3235 mod_timer(&adapter->sfp_timer,
3236 round_jiffies(jiffies + (2 * HZ)));
3237}
3238
9a799d71
AK		 3239/**
3240 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3241 * @adapter: board private structure to initialize
3242 *
3243 * ixgbe_sw_init initializes the Adapter private data structure.
3244 * Fields are initialized based on PCI device information and
3245 * OS network device settings (MTU size).
3246 **/
3247static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3248{
3249 struct ixgbe_hw *hw = &adapter->hw;
3250 struct pci_dev *pdev = adapter->pdev;
021230d4 3251 unsigned int rss;
7a6b6f51 3252#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3253 int j;
3254 struct tc_configuration *tc;
3255#endif
021230d4 3256
c44ade9e
JB		 3257 /* PCI config space info */
3258
3259 hw->vendor_id = pdev->vendor;
3260 hw->device_id = pdev->device;
3261 hw->revision_id = pdev->revision;
3262 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3263 hw->subsystem_device_id = pdev->subsystem_device;
3264
021230d4
AV		 3265 /* Set capability flags */
3266 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3267 adapter->ring_feature[RING_F_RSS].indices = rss;
3268 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3269 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3270 if (hw->mac.type == ixgbe_mac_82598EB)
3271 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
f8212f97 3272 else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3273 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3274 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3275 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3276 }
2f90b865 3277
7a6b6f51 3278#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3279 /* Configure DCB traffic classes */
3280 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3281 tc = &adapter->dcb_cfg.tc_config[j];
3282 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3283 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3284 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3285 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3286 tc->dcb_pfc = pfc_disabled;
3287 }
3288 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3289 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3290 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3291 adapter->dcb_cfg.round_robin_enable = false;
3292 adapter->dcb_set_bitmap = 0x00;
3293 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3294 adapter->ring_feature[RING_F_DCB].indices);
3295
3296#endif
9a799d71
AK		 3297
3298 /* default flow control settings */
cd7664f6 3299 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3300 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
2b9ade93
JB		 3301 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3302 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3303 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3304 hw->fc.send_xon = true;
71fd570b 3305 hw->fc.disable_fc_autoneg = false;
9a799d71 3306
30efa5a3
JB		 3307 /* enable itr by default in dynamic mode */
3308 adapter->itr_setting = 1;
3309 adapter->eitr_param = 20000;
3310
3311 /* set defaults for eitr in MegaBytes */
3312 adapter->eitr_low = 10;
3313 adapter->eitr_high = 20;
3314
3315 /* set default ring sizes */
3316 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3317 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3318
9a799d71 3319 /* initialize eeprom parameters */
c44ade9e 3320 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3321 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3322 return -EIO;
3323 }
3324
021230d4 3325 /* enable rx csum by default */
9a799d71
AK		 3326 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3327
9a799d71
AK		 3328 set_bit(__IXGBE_DOWN, &adapter->state);
3329
3330 return 0;
3331}
3332
3333/**
3334 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3335 * @adapter: board private structure
3a581073 3336 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3337 *
3338 * Return 0 on success, negative on failure
3339 **/
3340int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3341 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3342{
3343 struct pci_dev *pdev = adapter->pdev;
3344 int size;
3345
3a581073
JB		 3346 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3347 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3348 if (!tx_ring->tx_buffer_info)
3349 goto err;
3a581073 3350 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3351
3352 /* round up to nearest 4K */
12207e49 3353 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3354 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3355
3a581073
JB		 3356 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3357 &tx_ring->dma);
e01c31a5
JB		 3358 if (!tx_ring->desc)
3359 goto err;
9a799d71 3360
3a581073
JB		 3361 tx_ring->next_to_use = 0;
3362 tx_ring->next_to_clean = 0;
3363 tx_ring->work_limit = tx_ring->count;
9a799d71 3364 return 0;
e01c31a5
JB		 3365
3366err:
3367 vfree(tx_ring->tx_buffer_info);
3368 tx_ring->tx_buffer_info = NULL;
3369 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3370 "descriptor ring\n");
3371 return -ENOMEM;
9a799d71
AK		 3372}
3373
69888674
AD		 3374/**
3375 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3376 * @adapter: board private structure
3377 *
3378 * If this function returns with an error, then it's possible one or
3379 * more of the rings is populated (while the rest are not). It is the
3380 * callers duty to clean those orphaned rings.
3381 *
3382 * Return 0 on success, negative on failure
3383 **/
3384static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3385{
3386 int i, err = 0;
3387
3388 for (i = 0; i < adapter->num_tx_queues; i++) {
3389 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3390 if (!err)
3391 continue;
3392 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3393 break;
3394 }
3395
3396 return err;
3397}
3398
9a799d71
AK		 3399/**
3400 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3401 * @adapter: board private structure
3a581073 3402 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3403 *
3404 * Returns 0 on success, negative on failure
3405 **/
3406int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3407 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3408{
3409 struct pci_dev *pdev = adapter->pdev;
021230d4 3410 int size;
9a799d71 3411
3a581073
JB		 3412 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3413 rx_ring->rx_buffer_info = vmalloc(size);
3414 if (!rx_ring->rx_buffer_info) {
9a799d71 3415 DPRINTK(PROBE, ERR,
b4617240 3416 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3417 goto alloc_failed;
9a799d71 3418 }
3a581073 3419 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3420
9a799d71 3421 /* Round up to nearest 4K */
3a581073
JB		 3422 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3423 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3424
3a581073 3425 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3426
3a581073 3427 if (!rx_ring->desc) {
9a799d71 3428 DPRINTK(PROBE, ERR,
b4617240 3429 "Memory allocation failed for the rx desc ring\n");
3a581073 3430 vfree(rx_ring->rx_buffer_info);
177db6ff 3431 goto alloc_failed;
9a799d71
AK		 3432 }
3433
3a581073
JB		 3434 rx_ring->next_to_clean = 0;
3435 rx_ring->next_to_use = 0;
9a799d71
AK		 3436
3437 return 0;
177db6ff
MC		 3438
3439alloc_failed:
177db6ff 3440 return -ENOMEM;
9a799d71
AK		 3441}
3442
69888674
AD		 3443/**
3444 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3445 * @adapter: board private structure
3446 *
3447 * If this function returns with an error, then it's possible one or
3448 * more of the rings is populated (while the rest are not). It is the
3449 * callers duty to clean those orphaned rings.
3450 *
3451 * Return 0 on success, negative on failure
3452 **/
3453
3454static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3455{
3456 int i, err = 0;
3457
3458 for (i = 0; i < adapter->num_rx_queues; i++) {
3459 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3460 if (!err)
3461 continue;
3462 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3463 break;
3464 }
3465
3466 return err;
3467}
3468
9a799d71
AK		 3469/**
3470 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3471 * @adapter: board private structure
3472 * @tx_ring: Tx descriptor ring for a specific queue
3473 *
3474 * Free all transmit software resources
3475 **/
c431f97e
JB		 3476void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3477 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3478{
3479 struct pci_dev *pdev = adapter->pdev;
3480
3481 ixgbe_clean_tx_ring(adapter, tx_ring);
3482
3483 vfree(tx_ring->tx_buffer_info);
3484 tx_ring->tx_buffer_info = NULL;
3485
3486 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3487
3488 tx_ring->desc = NULL;
3489}
3490
3491/**
3492 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3493 * @adapter: board private structure
3494 *
3495 * Free all transmit software resources
3496 **/
3497static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3498{
3499 int i;
3500
3501 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3502 if (adapter->tx_ring[i].desc)
3503 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3504}
3505
3506/**
b4617240 3507 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3508 * @adapter: board private structure
3509 * @rx_ring: ring to clean the resources from
3510 *
3511 * Free all receive software resources
3512 **/
c431f97e
JB		 3513void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3514 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3515{
3516 struct pci_dev *pdev = adapter->pdev;
3517
3518 ixgbe_clean_rx_ring(adapter, rx_ring);
3519
3520 vfree(rx_ring->rx_buffer_info);
3521 rx_ring->rx_buffer_info = NULL;
3522
3523 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3524
3525 rx_ring->desc = NULL;
3526}
3527
3528/**
3529 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3530 * @adapter: board private structure
3531 *
3532 * Free all receive software resources
3533 **/
3534static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3535{
3536 int i;
3537
3538 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3539 if (adapter->rx_ring[i].desc)
3540 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3541}
3542
9a799d71
AK		 3543/**
3544 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3545 * @netdev: network interface device structure
3546 * @new_mtu: new value for maximum frame size
3547 *
3548 * Returns 0 on success, negative on failure
3549 **/
3550static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3551{
3552 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3553 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3554
42c783c5
JB		 3555 /* MTU < 68 is an error and causes problems on some kernels */
3556 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3557 return -EINVAL;
3558
021230d4 3559 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3560 netdev->mtu, new_mtu);
021230d4 3561 /* must set new MTU before calling down or up */
9a799d71
AK		 3562 netdev->mtu = new_mtu;
3563
d4f80882
AV		 3564 if (netif_running(netdev))
3565 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3566
3567 return 0;
3568}
3569
3570/**
3571 * ixgbe_open - Called when a network interface is made active
3572 * @netdev: network interface device structure
3573 *
3574 * Returns 0 on success, negative value on failure
3575 *
3576 * The open entry point is called when a network interface is made
3577 * active by the system (IFF_UP). At this point all resources needed
3578 * for transmit and receive operations are allocated, the interrupt
3579 * handler is registered with the OS, the watchdog timer is started,
3580 * and the stack is notified that the interface is ready.
3581 **/
3582static int ixgbe_open(struct net_device *netdev)
3583{
3584 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3585 int err;
4bebfaa5
AK		 3586
3587 /* disallow open during test */
3588 if (test_bit(__IXGBE_TESTING, &adapter->state))
3589 return -EBUSY;
9a799d71 3590
54386467
JB		 3591 netif_carrier_off(netdev);
3592
9a799d71
AK		 3593 /* allocate transmit descriptors */
3594 err = ixgbe_setup_all_tx_resources(adapter);
3595 if (err)
3596 goto err_setup_tx;
3597
9a799d71
AK		 3598 /* allocate receive descriptors */
3599 err = ixgbe_setup_all_rx_resources(adapter);
3600 if (err)
3601 goto err_setup_rx;
3602
3603 ixgbe_configure(adapter);
3604
4dd64df8
JB		 3605 ixgbe_napi_add_all(adapter);
3606
021230d4 3607 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3608 if (err)
3609 goto err_req_irq;
3610
9a799d71
AK		 3611 err = ixgbe_up_complete(adapter);
3612 if (err)
3613 goto err_up;
3614
d55b53ff
JK		 3615 netif_tx_start_all_queues(netdev);
3616
9a799d71
AK		 3617 return 0;
3618
3619err_up:
5eba3699 3620 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3621 ixgbe_free_irq(adapter);
3622err_req_irq:
9a799d71 3623err_setup_rx:
a20a1199 3624 ixgbe_free_all_rx_resources(adapter);
9a799d71 3625err_setup_tx:
a20a1199 3626 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3627 ixgbe_reset(adapter);
3628
3629 return err;
3630}
3631
3632/**
3633 * ixgbe_close - Disables a network interface
3634 * @netdev: network interface device structure
3635 *
3636 * Returns 0, this is not allowed to fail
3637 *
3638 * The close entry point is called when an interface is de-activated
3639 * by the OS. The hardware is still under the drivers control, but
3640 * needs to be disabled. A global MAC reset is issued to stop the
3641 * hardware, and all transmit and receive resources are freed.
3642 **/
3643static int ixgbe_close(struct net_device *netdev)
3644{
3645 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3646
3647 ixgbe_down(adapter);
3648 ixgbe_free_irq(adapter);
3649
3650 ixgbe_free_all_tx_resources(adapter);
3651 ixgbe_free_all_rx_resources(adapter);
3652
5eba3699 3653 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3654
3655 return 0;
3656}
3657
b3c8b4ba
AD		 3658/**
3659 * ixgbe_napi_add_all - prep napi structs for use
3660 * @adapter: private struct
4dd64df8 3661 *
b3c8b4ba
AD		 3662 * helper function to napi_add each possible q_vector->napi
3663 */
2f90b865 3664void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3665{
3666 int q_idx, q_vectors;
7adf1525 3667 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3668 int (*poll)(struct napi_struct *, int);
3669
7adf1525
PWJ		 3670 /* check if we already have our netdev->napi_list populated */
3671 if (&netdev->napi_list != netdev->napi_list.next)
3672 return;
3673
b3c8b4ba
AD		 3674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3675 poll = &ixgbe_clean_rxonly;
3676 /* Only enable as many vectors as we have rx queues. */
3677 q_vectors = adapter->num_rx_queues;
3678 } else {
3679 poll = &ixgbe_poll;
3680 /* only one q_vector for legacy modes */
3681 q_vectors = 1;
3682 }
3683
3684 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3685 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3686 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3687 }
3688}
3689
2f90b865 3690void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3691{
3692 int q_idx;
3693 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3694
3695 /* legacy and MSI only use one vector */
3696 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3697 q_vectors = 1;
3698
3699 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3700 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3701 if (!q_vector->rxr_count)
3702 continue;
3703 netif_napi_del(&q_vector->napi);
3704 }
3705}
3706
3707#ifdef CONFIG_PM
3708static int ixgbe_resume(struct pci_dev *pdev)
3709{
3710 struct net_device *netdev = pci_get_drvdata(pdev);
3711 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3712 u32 err;
3713
3714 pci_set_power_state(pdev, PCI_D0);
3715 pci_restore_state(pdev);
3716 err = pci_enable_device(pdev);
3717 if (err) {
69888674 3718 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3719 "suspend\n");
3720 return err;
3721 }
3722 pci_set_master(pdev);
3723
3724 pci_enable_wake(pdev, PCI_D3hot, 0);
3725 pci_enable_wake(pdev, PCI_D3cold, 0);
3726
3727 err = ixgbe_init_interrupt_scheme(adapter);
3728 if (err) {
3729 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3730 "device\n");
3731 return err;
3732 }
3733
b3c8b4ba
AD		 3734 ixgbe_reset(adapter);
3735
3736 if (netif_running(netdev)) {
3737 err = ixgbe_open(adapter->netdev);
3738 if (err)
3739 return err;
3740 }
3741
3742 netif_device_attach(netdev);
3743
3744 return 0;
3745}
b3c8b4ba 3746#endif /* CONFIG_PM */
9d8d05ae
RW		 3747
3748static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3749{
3750 struct net_device *netdev = pci_get_drvdata(pdev);
3751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3752 struct ixgbe_hw *hw = &adapter->hw;
3753 u32 ctrl, fctrl;
3754 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3755#ifdef CONFIG_PM
3756 int retval = 0;
3757#endif
3758
3759 netif_device_detach(netdev);
3760
3761 if (netif_running(netdev)) {
3762 ixgbe_down(adapter);
3763 ixgbe_free_irq(adapter);
3764 ixgbe_free_all_tx_resources(adapter);
3765 ixgbe_free_all_rx_resources(adapter);
3766 }
3767 ixgbe_reset_interrupt_capability(adapter);
3768 ixgbe_napi_del_all(adapter);
7adf1525 3769 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3770 kfree(adapter->tx_ring);
3771 kfree(adapter->rx_ring);
3772
3773#ifdef CONFIG_PM
3774 retval = pci_save_state(pdev);
3775 if (retval)
3776 return retval;
4df10466 3777
b3c8b4ba 3778#endif
e8e26350
PW		 3779 if (wufc) {
3780 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3781
e8e26350
PW		 3782 /* turn on all-multi mode if wake on multicast is enabled */
3783 if (wufc & IXGBE_WUFC_MC) {
3784 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3785 fctrl |= IXGBE_FCTRL_MPE;
3786 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3787 }
3788
3789 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3790 ctrl |= IXGBE_CTRL_GIO_DIS;
3791 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3792
3793 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3794 } else {
3795 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3796 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3797 }
3798
3799 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3800 pci_enable_wake(pdev, PCI_D3hot, 1);
3801 pci_enable_wake(pdev, PCI_D3cold, 1);
3802 } else {
3803 pci_enable_wake(pdev, PCI_D3hot, 0);
3804 pci_enable_wake(pdev, PCI_D3cold, 0);
3805 }
b3c8b4ba 3806
9d8d05ae
RW		 3807 *enable_wake = !!wufc;
3808
b3c8b4ba
AD		 3809 ixgbe_release_hw_control(adapter);
3810
3811 pci_disable_device(pdev);
3812
9d8d05ae
RW		 3813 return 0;
3814}
3815
3816#ifdef CONFIG_PM
3817static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3818{
3819 int retval;
3820 bool wake;
3821
3822 retval = __ixgbe_shutdown(pdev, &wake);
3823 if (retval)
3824 return retval;
3825
3826 if (wake) {
3827 pci_prepare_to_sleep(pdev);
3828 } else {
3829 pci_wake_from_d3(pdev, false);
3830 pci_set_power_state(pdev, PCI_D3hot);
3831 }
b3c8b4ba
AD		 3832
3833 return 0;
3834}
9d8d05ae 3835#endif /* CONFIG_PM */
b3c8b4ba
AD		 3836
3837static void ixgbe_shutdown(struct pci_dev *pdev)
3838{
9d8d05ae
RW		 3839 bool wake;
3840
3841 __ixgbe_shutdown(pdev, &wake);
3842
3843 if (system_state == SYSTEM_POWER_OFF) {
3844 pci_wake_from_d3(pdev, wake);
3845 pci_set_power_state(pdev, PCI_D3hot);
3846 }
b3c8b4ba
AD		 3847}
3848
9a799d71
AK		 3849/**
3850 * ixgbe_update_stats - Update the board statistics counters.
3851 * @adapter: board private structure
3852 **/
3853void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3854{
3855 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3856 u64 total_mpc = 0;
3857 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3858
d51019a4 3859 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 3860 u64 rsc_count = 0;
d51019a4
PW		 3861 for (i = 0; i < 16; i++)
3862 adapter->hw_rx_no_dma_resources +=
3863 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 3864 for (i = 0; i < adapter->num_rx_queues; i++)
3865 rsc_count += adapter->rx_ring[i].rsc_count;
3866 adapter->rsc_count = rsc_count;
d51019a4
PW		 3867 }
3868
9a799d71 3869 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3870 for (i = 0; i < 8; i++) {
3871 /* for packet buffers not used, the register should read 0 */
3872 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3873 missed_rx += mpc;
3874 adapter->stats.mpc[i] += mpc;
3875 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3876 if (hw->mac.type == ixgbe_mac_82598EB)
3877 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3878 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3879 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3880 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3881 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3882 if (hw->mac.type == ixgbe_mac_82599EB) {
3883 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3884 IXGBE_PXONRXCNT(i));
3885 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3886 IXGBE_PXOFFRXCNT(i));
3887 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3888 } else {
3889 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3890 IXGBE_PXONRXC(i));
3891 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3892 IXGBE_PXOFFRXC(i));
3893 }
2f90b865
AD		 3894 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3895 IXGBE_PXONTXC(i));
2f90b865 3896 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3897 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3898 }
3899 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3900 /* work around hardware counting issue */
3901 adapter->stats.gprc -= missed_rx;
3902
3903 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3904 if (hw->mac.type == ixgbe_mac_82599EB) {
3905 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3906 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3907 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3908 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3909 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3910 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3911 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3912 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3913 } else {
3914 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3915 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3916 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3917 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3918 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3919 }
9a799d71
AK		 3920 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3921 adapter->stats.bprc += bprc;
3922 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3923 if (hw->mac.type == ixgbe_mac_82598EB)
3924 adapter->stats.mprc -= bprc;
9a799d71
AK		 3925 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3926 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3927 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3928 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3929 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3930 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3931 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3932 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3933 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3934 adapter->stats.lxontxc += lxon;
3935 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3936 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3937 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3938 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3939 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3940 /*
3941 * 82598 errata - tx of flow control packets is included in tx counters
3942 */
3943 xon_off_tot = lxon + lxoff;
3944 adapter->stats.gptc -= xon_off_tot;
3945 adapter->stats.mptc -= xon_off_tot;
3946 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3947 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3948 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3949 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3950 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3951 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3952 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3953 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3954 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3955 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3956 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3957 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3958 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3959
3960 /* Fill out the OS statistics structure */
9a799d71
AK		 3961 adapter->net_stats.multicast = adapter->stats.mprc;
3962
3963 /* Rx Errors */
3964 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3965 adapter->stats.rlec;
9a799d71
AK		 3966 adapter->net_stats.rx_dropped = 0;
3967 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3968 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3969 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3970}
3971
3972/**
3973 * ixgbe_watchdog - Timer Call-back
3974 * @data: pointer to adapter cast into an unsigned long
3975 **/
3976static void ixgbe_watchdog(unsigned long data)
3977{
3978 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3979 struct ixgbe_hw *hw = &adapter->hw;
3980
3981 /* Do the watchdog outside of interrupt context due to the lovely
3982 * delays that some of the newer hardware requires */
3983 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 3984 u64 eics = 0;
3985 int i;
3986
3987 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
3988 eics |= (1 << i);
3989
cf8280ee 3990 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 3991 switch (hw->mac.type) {
3992 case ixgbe_mac_82598EB:
3993 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3994 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
3995 } else {
3996 /*
3997 * for legacy and MSI interrupts don't set any
3998 * bits that are enabled for EIAM, because this
3999 * operation would set *both* EIMS and EICS for
4000 * any bit in EIAM
4001 */
4002 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4003 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4004 }
4005 break;
4006 case ixgbe_mac_82599EB:
4007 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4008 /*
4009 * EICS(0..15) first 0-15 q vectors
4010 * EICS[1] (16..31) q vectors 16-31
4011 * EICS[2] (0..31) q vectors 32-63
4012 */
4013 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4014 (u32)(eics & 0xFFFF));
4015 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4016 (u32)(eics & 0xFFFF0000));
4017 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(2),
4018 (u32)(eics >> 32));
4019 } else {
4020 /*
4021 * for legacy and MSI interrupts don't set any
4022 * bits that are enabled for EIAM, because this
4023 * operation would set *both* EIMS and EICS for
4024 * any bit in EIAM
4025 */
4026 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4027 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4028 }
4029 break;
4030 default:
4031 break;
cf8280ee
JB		 4032 }
4033 /* Reset the timer */
4034 mod_timer(&adapter->watchdog_timer,
4035 round_jiffies(jiffies + 2 * HZ));
4036 }
9a799d71 4037
cf8280ee
JB		 4038 schedule_work(&adapter->watchdog_task);
4039}
4040
e8e26350
PW		 4041/**
4042 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4043 * @work: pointer to work_struct containing our data
4044 **/
4045static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4046{
4047 struct ixgbe_adapter *adapter = container_of(work,
4048 struct ixgbe_adapter,
4049 multispeed_fiber_task);
4050 struct ixgbe_hw *hw = &adapter->hw;
4051 u32 autoneg;
4052
4053 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4054 if (hw->mac.ops.get_link_capabilities)
4055 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4056 &hw->mac.autoneg);
4057 if (hw->mac.ops.setup_link_speed)
4058 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4059 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4060 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4061}
4062
4063/**
4064 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4065 * @work: pointer to work_struct containing our data
4066 **/
4067static void ixgbe_sfp_config_module_task(struct work_struct *work)
4068{
4069 struct ixgbe_adapter *adapter = container_of(work,
4070 struct ixgbe_adapter,
4071 sfp_config_module_task);
4072 struct ixgbe_hw *hw = &adapter->hw;
4073 u32 err;
4074
4075 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4076 err = hw->phy.ops.identify_sfp(hw);
4077 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4078 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4079 ixgbe_down(adapter);
4080 return;
4081 }
4082 hw->mac.ops.setup_sfp(hw);
4083
8d1c3c07 4084 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4085 /* This will also work for DA Twinax connections */
4086 schedule_work(&adapter->multispeed_fiber_task);
4087 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4088}
4089
cf8280ee 4090/**
69888674
AD		 4091 * ixgbe_watchdog_task - worker thread to bring link up
4092 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4093 **/
4094static void ixgbe_watchdog_task(struct work_struct *work)
4095{
4096 struct ixgbe_adapter *adapter = container_of(work,
4097 struct ixgbe_adapter,
4098 watchdog_task);
4099 struct net_device *netdev = adapter->netdev;
4100 struct ixgbe_hw *hw = &adapter->hw;
4101 u32 link_speed = adapter->link_speed;
4102 bool link_up = adapter->link_up;
4103
4104 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4105
4106 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4107 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4108 if (link_up ||
4109 time_after(jiffies, (adapter->link_check_timeout +
4110 IXGBE_TRY_LINK_TIMEOUT))) {
4111 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4112 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4113 }
4114 adapter->link_up = link_up;
4115 adapter->link_speed = link_speed;
4116 }
9a799d71
AK		 4117
4118 if (link_up) {
4119 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4120 bool flow_rx, flow_tx;
4121
4122 if (hw->mac.type == ixgbe_mac_82599EB) {
4123 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4124 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4125 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4126 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4127 } else {
4128 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4129 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4130 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4131 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4132 }
4133
a46e534b
JK		 4134 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4135 "Flow Control: %s\n",
4136 netdev->name,
4137 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4138 "10 Gbps" :
4139 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4140 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4141 ((flow_rx && flow_tx) ? "RX/TX" :
4142 (flow_rx ? "RX" :
4143 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4144
4145 netif_carrier_on(netdev);
9a799d71
AK		 4146 } else {
4147 /* Force detection of hung controller */
4148 adapter->detect_tx_hung = true;
4149 }
4150 } else {
cf8280ee
JB		 4151 adapter->link_up = false;
4152 adapter->link_speed = 0;
9a799d71 4153 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4154 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4155 netdev->name);
9a799d71 4156 netif_carrier_off(netdev);
9a799d71
AK		 4157 }
4158 }
4159
4160 ixgbe_update_stats(adapter);
cf8280ee 4161 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4162}
4163
9a799d71 4164static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4165 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4166 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4167{
4168 struct ixgbe_adv_tx_context_desc *context_desc;
4169 unsigned int i;
4170 int err;
4171 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4172 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4173 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4174
4175 if (skb_is_gso(skb)) {
4176 if (skb_header_cloned(skb)) {
4177 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4178 if (err)
4179 return err;
4180 }
4181 l4len = tcp_hdrlen(skb);
4182 *hdr_len += l4len;
4183
8327d000 4184 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4185 struct iphdr *iph = ip_hdr(skb);
4186 iph->tot_len = 0;
4187 iph->check = 0;
4188 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4189 iph->daddr, 0,
4190 IPPROTO_TCP,
4191 0);
9a799d71
AK		 4192 adapter->hw_tso_ctxt++;
4193 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4194 ipv6_hdr(skb)->payload_len = 0;
4195 tcp_hdr(skb)->check =
4196 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4197 &ipv6_hdr(skb)->daddr,
4198 0, IPPROTO_TCP, 0);
9a799d71
AK		 4199 adapter->hw_tso6_ctxt++;
4200 }
4201
4202 i = tx_ring->next_to_use;
4203
4204 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4205 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4206
4207 /* VLAN MACLEN IPLEN */
4208 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4209 vlan_macip_lens |=
4210 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4211 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4212 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4213 *hdr_len += skb_network_offset(skb);
4214 vlan_macip_lens |=
4215 (skb_transport_header(skb) - skb_network_header(skb));
4216 *hdr_len +=
4217 (skb_transport_header(skb) - skb_network_header(skb));
4218 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4219 context_desc->seqnum_seed = 0;
4220
4221 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4222 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4223 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4224
8327d000 4225 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4226 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4227 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4228 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4229
4230 /* MSS L4LEN IDX */
9f8cdf4f 4231 mss_l4len_idx =
9a799d71
AK		 4232 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4233 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4234 /* use index 1 for TSO */
4235 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4236 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4237
4238 tx_buffer_info->time_stamp = jiffies;
4239 tx_buffer_info->next_to_watch = i;
4240
4241 i++;
4242 if (i == tx_ring->count)
4243 i = 0;
4244 tx_ring->next_to_use = i;
4245
4246 return true;
4247 }
4248 return false;
4249}
4250
4251static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4252 struct ixgbe_ring *tx_ring,
4253 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4254{
4255 struct ixgbe_adv_tx_context_desc *context_desc;
4256 unsigned int i;
4257 struct ixgbe_tx_buffer *tx_buffer_info;
4258 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4259
4260 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4261 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4262 i = tx_ring->next_to_use;
4263 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4264 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4265
4266 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4267 vlan_macip_lens |=
4268 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4269 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4270 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4271 if (skb->ip_summed == CHECKSUM_PARTIAL)
4272 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4273 skb_network_header(skb));
9a799d71
AK		 4274
4275 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4276 context_desc->seqnum_seed = 0;
4277
4278 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4279 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4280
4281 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4282 switch (skb->protocol) {
09640e63 4283 case cpu_to_be16(ETH_P_IP):
9a799d71 4284 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4285 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4286 type_tucmd_mlhl |=
b4617240 4287 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4288 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4289 type_tucmd_mlhl |=
4290 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4291 break;
09640e63 4292 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4293 /* XXX what about other V6 headers?? */
4294 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4295 type_tucmd_mlhl |=
b4617240 4296 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4297 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4298 type_tucmd_mlhl |=
4299 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4300 break;
41825d71
AK		 4301 default:
4302 if (unlikely(net_ratelimit())) {
4303 DPRINTK(PROBE, WARNING,
4304 "partial checksum but proto=%x!\n",
4305 skb->protocol);
4306 }
4307 break;
4308 }
9a799d71
AK		 4309 }
4310
4311 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4312 /* use index zero for tx checksum offload */
9a799d71
AK		 4313 context_desc->mss_l4len_idx = 0;
4314
4315 tx_buffer_info->time_stamp = jiffies;
4316 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4317
9a799d71
AK		 4318 adapter->hw_csum_tx_good++;
4319 i++;
4320 if (i == tx_ring->count)
4321 i = 0;
4322 tx_ring->next_to_use = i;
4323
4324 return true;
4325 }
9f8cdf4f 4326
9a799d71
AK		 4327 return false;
4328}
4329
4330static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4331 struct ixgbe_ring *tx_ring,
4332 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4333{
4334 struct ixgbe_tx_buffer *tx_buffer_info;
44df32c5 4335 unsigned int len = skb_headlen(skb);
9a799d71
AK		 4336 unsigned int offset = 0, size, count = 0, i;
4337 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4338 unsigned int f;
44df32c5 4339 dma_addr_t *map;
9a799d71
AK		 4340
4341 i = tx_ring->next_to_use;
4342
44df32c5
AD		 4343 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4344 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4345 return 0;
4346 }
4347
4348 map = skb_shinfo(skb)->dma_maps;
4349
9a799d71
AK		 4350 while (len) {
4351 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4352 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4353
4354 tx_buffer_info->length = size;
44df32c5 4355 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4356 tx_buffer_info->time_stamp = jiffies;
4357 tx_buffer_info->next_to_watch = i;
4358
4359 len -= size;
4360 offset += size;
4361 count++;
44df32c5
AD		 4362
4363 if (len) {
4364 i++;
4365 if (i == tx_ring->count)
4366 i = 0;
4367 }
9a799d71
AK		 4368 }
4369
4370 for (f = 0; f < nr_frags; f++) {
4371 struct skb_frag_struct *frag;
4372
4373 frag = &skb_shinfo(skb)->frags[f];
4374 len = frag->size;
44df32c5 4375 offset = 0;
9a799d71
AK		 4376
4377 while (len) {
44df32c5
AD		 4378 i++;
4379 if (i == tx_ring->count)
4380 i = 0;
4381
9a799d71
AK		 4382 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4383 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4384
4385 tx_buffer_info->length = size;
44df32c5 4386 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4387 tx_buffer_info->time_stamp = jiffies;
4388 tx_buffer_info->next_to_watch = i;
4389
4390 len -= size;
4391 offset += size;
4392 count++;
9a799d71
AK		 4393 }
4394 }
44df32c5 4395
9a799d71
AK		 4396 tx_ring->tx_buffer_info[i].skb = skb;
4397 tx_ring->tx_buffer_info[first].next_to_watch = i;
4398
4399 return count;
4400}
4401
4402static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4403 struct ixgbe_ring *tx_ring,
4404 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4405{
4406 union ixgbe_adv_tx_desc *tx_desc = NULL;
4407 struct ixgbe_tx_buffer *tx_buffer_info;
4408 u32 olinfo_status = 0, cmd_type_len = 0;
4409 unsigned int i;
4410 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4411
4412 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4413
4414 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4415
4416 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4417 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4418
4419 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4420 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4421
4422 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4423 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4424
4eeae6fd
PW		 4425 /* use index 1 context for tso */
4426 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4427 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4428 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4429 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4430
4431 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4432 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4433 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4434
4435 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4436
4437 i = tx_ring->next_to_use;
4438 while (count--) {
4439 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4440 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4441 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4442 tx_desc->read.cmd_type_len =
b4617240 4443 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4444 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4445 i++;
4446 if (i == tx_ring->count)
4447 i = 0;
4448 }
4449
4450 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4451
4452 /*
4453 * Force memory writes to complete before letting h/w
4454 * know there are new descriptors to fetch. (Only
4455 * applicable for weak-ordered memory model archs,
4456 * such as IA-64).
4457 */
4458 wmb();
4459
4460 tx_ring->next_to_use = i;
4461 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4462}
4463
e092be60 4464static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4465 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4466{
4467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4468
30eba97a 4469 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4470 /* Herbert's original patch had:
4471 * smp_mb__after_netif_stop_queue();
4472 * but since that doesn't exist yet, just open code it. */
4473 smp_mb();
4474
4475 /* We need to check again in a case another CPU has just
4476 * made room available. */
4477 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4478 return -EBUSY;
4479
4480 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4481 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4482 ++adapter->restart_queue;
4483 return 0;
4484}
4485
4486static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4487 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4488{
4489 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4490 return 0;
4491 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4492}
4493
09a3b1f8
SH		 4494static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4495{
4496 struct ixgbe_adapter *adapter = netdev_priv(dev);
4497
4498 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4499 return 0; /* All traffic should default to class 0 */
4500
4501 return skb_tx_hash(dev, skb);
4502}
4503
9a799d71
AK		 4504static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4505{
4506 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4507 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4508 unsigned int first;
4509 unsigned int tx_flags = 0;
30eba97a
AV		 4510 u8 hdr_len = 0;
4511 int r_idx = 0, tso;
9a799d71
AK		 4512 int count = 0;
4513 unsigned int f;
9f8cdf4f 4514
95615d90 4515 r_idx = skb->queue_mapping;
30eba97a 4516 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4517
9f8cdf4f
JB		 4518 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4519 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4520 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4521 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4522 tx_flags |= (skb->queue_mapping << 13);
4523 }
4524 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4525 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4526 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4527 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4528 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4529 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4530 }
9f8cdf4f
JB		 4531 /* three things can cause us to need a context descriptor */
4532 if (skb_is_gso(skb) ||
4533 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4534 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4535 count++;
4536
9f8cdf4f
JB		 4537 count += TXD_USE_COUNT(skb_headlen(skb));
4538 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4539 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4540
e092be60 4541 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4542 adapter->tx_busy++;
9a799d71
AK		 4543 return NETDEV_TX_BUSY;
4544 }
9a799d71 4545
8327d000 4546 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4547 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4548 first = tx_ring->next_to_use;
4549 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4550 if (tso < 0) {
4551 dev_kfree_skb_any(skb);
4552 return NETDEV_TX_OK;
4553 }
4554
4555 if (tso)
4556 tx_flags |= IXGBE_TX_FLAGS_TSO;
4557 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4558 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4559 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4560
44df32c5 4561 count = ixgbe_tx_map(adapter, tx_ring, skb, first);
9a799d71 4562
44df32c5
AD		 4563 if (count) {
4564 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4565 hdr_len);
4566 netdev->trans_start = jiffies;
4567 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4568
44df32c5
AD		 4569 } else {
4570 dev_kfree_skb_any(skb);
4571 tx_ring->tx_buffer_info[first].time_stamp = 0;
4572 tx_ring->next_to_use = first;
4573 }
9a799d71
AK		 4574
4575 return NETDEV_TX_OK;
4576}
4577
4578/**
4579 * ixgbe_get_stats - Get System Network Statistics
4580 * @netdev: network interface device structure
4581 *
4582 * Returns the address of the device statistics structure.
4583 * The statistics are actually updated from the timer callback.
4584 **/
4585static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4586{
4587 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4588
4589 /* only return the current stats */
4590 return &adapter->net_stats;
4591}
4592
4593/**
4594 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4595 * @netdev: network interface device structure
4596 * @p: pointer to an address structure
4597 *
4598 * Returns 0 on success, negative on failure
4599 **/
4600static int ixgbe_set_mac(struct net_device *netdev, void *p)
4601{
4602 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4603 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4604 struct sockaddr *addr = p;
4605
4606 if (!is_valid_ether_addr(addr->sa_data))
4607 return -EADDRNOTAVAIL;
4608
4609 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4610 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4611
b4617240 4612 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4613
4614 return 0;
4615}
4616
4617#ifdef CONFIG_NET_POLL_CONTROLLER
4618/*
4619 * Polling 'interrupt' - used by things like netconsole to send skbs
4620 * without having to re-enable interrupts. It's not called while
4621 * the interrupt routine is executing.
4622 */
4623static void ixgbe_netpoll(struct net_device *netdev)
4624{
4625 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4626
4627 disable_irq(adapter->pdev->irq);
4628 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4629 ixgbe_intr(adapter->pdev->irq, netdev);
4630 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4631 enable_irq(adapter->pdev->irq);
4632}
4633#endif
4634
0edc3527
SH		 4635static const struct net_device_ops ixgbe_netdev_ops = {
4636 .ndo_open = ixgbe_open,
4637 .ndo_stop = ixgbe_close,
00829823 4638 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 4639 .ndo_select_queue = ixgbe_select_queue,
0edc3527 4640 .ndo_get_stats = ixgbe_get_stats,
e90d400c 4641 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 4642 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4643 .ndo_validate_addr = eth_validate_addr,
4644 .ndo_set_mac_address = ixgbe_set_mac,
4645 .ndo_change_mtu = ixgbe_change_mtu,
4646 .ndo_tx_timeout = ixgbe_tx_timeout,
4647 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4648 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4649 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4650#ifdef CONFIG_NET_POLL_CONTROLLER
4651 .ndo_poll_controller = ixgbe_netpoll,
4652#endif
4653};
4654
9a799d71
AK		 4655/**
4656 * ixgbe_probe - Device Initialization Routine
4657 * @pdev: PCI device information struct
4658 * @ent: entry in ixgbe_pci_tbl
4659 *
4660 * Returns 0 on success, negative on failure
4661 *
4662 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4663 * The OS initialization, configuring of the adapter private structure,
4664 * and a hardware reset occur.
4665 **/
4666static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4667 const struct pci_device_id *ent)
9a799d71
AK		 4668{
4669 struct net_device *netdev;
4670 struct ixgbe_adapter *adapter = NULL;
4671 struct ixgbe_hw *hw;
4672 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4673 static int cards_found;
4674 int i, err, pci_using_dac;
e8e26350 4675 u16 pm_value = 0;
c44ade9e 4676 u32 part_num, eec;
9a799d71
AK		 4677
4678 err = pci_enable_device(pdev);
4679 if (err)
4680 return err;
4681
6a35528a
YH		 4682 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4683 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 4684 pci_using_dac = 1;
4685 } else {
284901a9 4686 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4687 if (err) {
284901a9 4688 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4689 if (err) {
b4617240
PW		 4690 dev_err(&pdev->dev, "No usable DMA "
4691 "configuration, aborting\n");
9a799d71
AK		 4692 goto err_dma;
4693 }
4694 }
4695 pci_using_dac = 0;
4696 }
4697
4698 err = pci_request_regions(pdev, ixgbe_driver_name);
4699 if (err) {
4700 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4701 goto err_pci_reg;
4702 }
4703
6fabd715
PWJ		 4704 err = pci_enable_pcie_error_reporting(pdev);
4705 if (err) {
4706 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4707 "0x%x\n", err);
4708 /* non-fatal, continue */
4709 }
4710
9a799d71 4711 pci_set_master(pdev);
fb3b27bc 4712 pci_save_state(pdev);
9a799d71 4713
30eba97a 4714 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4715 if (!netdev) {
4716 err = -ENOMEM;
4717 goto err_alloc_etherdev;
4718 }
4719
9a799d71
AK		 4720 SET_NETDEV_DEV(netdev, &pdev->dev);
4721
4722 pci_set_drvdata(pdev, netdev);
4723 adapter = netdev_priv(netdev);
4724
4725 adapter->netdev = netdev;
4726 adapter->pdev = pdev;
4727 hw = &adapter->hw;
4728 hw->back = adapter;
4729 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4730
05857980
JK		 4731 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4732 pci_resource_len(pdev, 0));
9a799d71
AK		 4733 if (!hw->hw_addr) {
4734 err = -EIO;
4735 goto err_ioremap;
4736 }
4737
4738 for (i = 1; i <= 5; i++) {
4739 if (pci_resource_len(pdev, i) == 0)
4740 continue;
4741 }
4742
0edc3527 4743 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4744 ixgbe_set_ethtool_ops(netdev);
9a799d71 4745 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4746 strcpy(netdev->name, pci_name(pdev));
4747
9a799d71
AK		 4748 adapter->bd_number = cards_found;
4749
9a799d71
AK		 4750 /* Setup hw api */
4751 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4752 hw->mac.type = ii->mac;
9a799d71 4753
c44ade9e
JB		 4754 /* EEPROM */
4755 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4756 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4757 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4758 if (!(eec & (1 << 8)))
4759 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4760
4761 /* PHY */
4762 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4763 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4764
4765 /* set up this timer and work struct before calling get_invariants
4766 * which might start the timer
4767 */
4768 init_timer(&adapter->sfp_timer);
4769 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4770 adapter->sfp_timer.data = (unsigned long) adapter;
4771
4772 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4773
e8e26350
PW		 4774 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4775 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4776
4777 /* a new SFP+ module arrival, called from GPI SDP2 context */
4778 INIT_WORK(&adapter->sfp_config_module_task,
4779 ixgbe_sfp_config_module_task);
4780
9a799d71 4781 err = ii->get_invariants(hw);
c4900be0
DS		 4782 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4783 /* start a kernel thread to watch for a module to arrive */
4784 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4785 mod_timer(&adapter->sfp_timer,
4786 round_jiffies(jiffies + (2 * HZ)));
4787 err = 0;
4788 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4789 DPRINTK(PROBE, ERR, "failed to load because an "
4790 "unsupported SFP+ module type was detected.\n");
9a799d71 4791 goto err_hw_init;
c4900be0
DS		 4792 } else if (err) {
4793 goto err_hw_init;
4794 }
9a799d71
AK		 4795
4796 /* setup the private structure */
4797 err = ixgbe_sw_init(adapter);
4798 if (err)
4799 goto err_sw_init;
4800
c44ade9e
JB		 4801 /* reset_hw fills in the perm_addr as well */
4802 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 4803 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4804 dev_err(&adapter->pdev->dev, "failed to load because an "
4805 "unsupported SFP+ module type was detected.\n");
4806 goto err_sw_init;
4807 } else if (err) {
c44ade9e
JB		 4808 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4809 goto err_sw_init;
4810 }
4811
9a799d71 4812 netdev->features = NETIF_F_SG |
b4617240
PW		 4813 NETIF_F_IP_CSUM |
4814 NETIF_F_HW_VLAN_TX |
4815 NETIF_F_HW_VLAN_RX |
4816 NETIF_F_HW_VLAN_FILTER;
9a799d71 4817
e9990a9c 4818 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4819 netdev->features |= NETIF_F_TSO;
9a799d71 4820 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4821 netdev->features |= NETIF_F_GRO;
ad31c402 4822
45a5ead0
JB		 4823 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4824 netdev->features |= NETIF_F_SCTP_CSUM;
4825
ad31c402
JK		 4826 netdev->vlan_features |= NETIF_F_TSO;
4827 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4828 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4829 netdev->vlan_features |= NETIF_F_SG;
4830
2f90b865
AD		 4831 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4832 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4833
7a6b6f51 4834#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4835 netdev->dcbnl_ops = &dcbnl_ops;
4836#endif
4837
9a799d71
AK		 4838 if (pci_using_dac)
4839 netdev->features |= NETIF_F_HIGHDMA;
4840
f8212f97
AD		 4841 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
4842 netdev->features |= NETIF_F_LRO;
4843
9a799d71 4844 /* make sure the EEPROM is good */
c44ade9e 4845 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4846 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4847 err = -EIO;
4848 goto err_eeprom;
4849 }
4850
4851 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4852 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4853
c44ade9e
JB		 4854 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4855 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4856 err = -EIO;
4857 goto err_eeprom;
4858 }
4859
4860 init_timer(&adapter->watchdog_timer);
4861 adapter->watchdog_timer.function = &ixgbe_watchdog;
4862 adapter->watchdog_timer.data = (unsigned long)adapter;
4863
4864 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4865 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4866
021230d4
AV		 4867 err = ixgbe_init_interrupt_scheme(adapter);
4868 if (err)
4869 goto err_sw_init;
9a799d71 4870
e8e26350
PW		 4871 switch (pdev->device) {
4872 case IXGBE_DEV_ID_82599_KX4:
4873#define IXGBE_PCIE_PMCSR 0x44
4874 adapter->wol = IXGBE_WUFC_MAG;
4875 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4876 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4877 (pm_value | (1 << 8)));
4878 break;
4879 default:
4880 adapter->wol = 0;
4881 break;
4882 }
4883 device_init_wakeup(&adapter->pdev->dev, true);
4884 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4885
04f165ef
PW		 4886 /* pick up the PCI bus settings for reporting later */
4887 hw->mac.ops.get_bus_info(hw);
4888
9a799d71 4889 /* print bus type/speed/width info */
7c510e4b 4890 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 4891 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4892 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4893 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4894 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4895 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 4896 "Unknown"),
7c510e4b 4897 netdev->dev_addr);
c44ade9e 4898 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 4899 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4900 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4901 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4902 (part_num >> 8), (part_num & 0xff));
4903 else
4904 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4905 hw->mac.type, hw->phy.type,
4906 (part_num >> 8), (part_num & 0xff));
9a799d71 4907
e8e26350 4908 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 4909 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4910 "this card is not sufficient for optimal "
4911 "performance.\n");
0c254d86 4912 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4913 "PCI-Express slot is required.\n");
0c254d86
AK		 4914 }
4915
34b0368c
PWJ		 4916 /* save off EEPROM version number */
4917 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4918
9a799d71 4919 /* reset the hardware with the new settings */
c44ade9e
JB		 4920 hw->mac.ops.start_hw(hw);
4921
9a799d71
AK		 4922 strcpy(netdev->name, "eth%d");
4923 err = register_netdev(netdev);
4924 if (err)
4925 goto err_register;
4926
54386467
JB		 4927 /* carrier off reporting is important to ethtool even BEFORE open */
4928 netif_carrier_off(netdev);
4929
5dd2d332 4930#ifdef CONFIG_IXGBE_DCA
652f093f 4931 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4932 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4933 /* always use CB2 mode, difference is masked
4934 * in the CB driver */
4935 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4936 ixgbe_setup_dca(adapter);
4937 }
4938#endif
9a799d71
AK		 4939
4940 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4941 cards_found++;
4942 return 0;
4943
4944err_register:
5eba3699 4945 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4946err_hw_init:
4947err_sw_init:
021230d4 4948 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4949err_eeprom:
c4900be0
DS		 4950 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4951 del_timer_sync(&adapter->sfp_timer);
4952 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4953 cancel_work_sync(&adapter->multispeed_fiber_task);
4954 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4955 iounmap(hw->hw_addr);
4956err_ioremap:
4957 free_netdev(netdev);
4958err_alloc_etherdev:
4959 pci_release_regions(pdev);
4960err_pci_reg:
4961err_dma:
4962 pci_disable_device(pdev);
4963 return err;
4964}
4965
4966/**
4967 * ixgbe_remove - Device Removal Routine
4968 * @pdev: PCI device information struct
4969 *
4970 * ixgbe_remove is called by the PCI subsystem to alert the driver
4971 * that it should release a PCI device. The could be caused by a
4972 * Hot-Plug event, or because the driver is going to be removed from
4973 * memory.
4974 **/
4975static void __devexit ixgbe_remove(struct pci_dev *pdev)
4976{
4977 struct net_device *netdev = pci_get_drvdata(pdev);
4978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4979 int err;
9a799d71
AK		 4980
4981 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4982 /* clear the module not found bit to make sure the worker won't
4983 * reschedule
4984 */
4985 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4986 del_timer_sync(&adapter->watchdog_timer);
4987
c4900be0
DS		 4988 del_timer_sync(&adapter->sfp_timer);
4989 cancel_work_sync(&adapter->watchdog_task);
4990 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4991 cancel_work_sync(&adapter->multispeed_fiber_task);
4992 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4993 flush_scheduled_work();
4994
5dd2d332 4995#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4996 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4997 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4998 dca_remove_requester(&pdev->dev);
4999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5000 }
5001
5002#endif
c4900be0
DS		 5003 if (netdev->reg_state == NETREG_REGISTERED)
5004 unregister_netdev(netdev);
9a799d71 5005
021230d4 5006 ixgbe_reset_interrupt_capability(adapter);
5eba3699 5007
021230d4 5008 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5009
5010 iounmap(adapter->hw.hw_addr);
5011 pci_release_regions(pdev);
5012
021230d4
AV		 5013 DPRINTK(PROBE, INFO, "complete\n");
5014 kfree(adapter->tx_ring);
5015 kfree(adapter->rx_ring);
5016
9a799d71
AK		 5017 free_netdev(netdev);
5018
6fabd715
PWJ		 5019 err = pci_disable_pcie_error_reporting(pdev);
5020 if (err)
5021 dev_err(&pdev->dev,
5022 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5023
9a799d71
AK		 5024 pci_disable_device(pdev);
5025}
5026
5027/**
5028 * ixgbe_io_error_detected - called when PCI error is detected
5029 * @pdev: Pointer to PCI device
5030 * @state: The current pci connection state
5031 *
5032 * This function is called after a PCI bus error affecting
5033 * this device has been detected.
5034 */
5035static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5036 pci_channel_state_t state)
9a799d71
AK		 5037{
5038 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5039 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5040
5041 netif_device_detach(netdev);
5042
5043 if (netif_running(netdev))
5044 ixgbe_down(adapter);
5045 pci_disable_device(pdev);
5046
b4617240 5047 /* Request a slot reset. */
9a799d71
AK		 5048 return PCI_ERS_RESULT_NEED_RESET;
5049}
5050
5051/**
5052 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5053 * @pdev: Pointer to PCI device
5054 *
5055 * Restart the card from scratch, as if from a cold-boot.
5056 */
5057static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5058{
5059 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5061 pci_ers_result_t result;
5062 int err;
9a799d71
AK		 5063
5064 if (pci_enable_device(pdev)) {
5065 DPRINTK(PROBE, ERR,
b4617240 5066 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5067 result = PCI_ERS_RESULT_DISCONNECT;
5068 } else {
5069 pci_set_master(pdev);
5070 pci_restore_state(pdev);
9a799d71 5071
6fabd715
PWJ		 5072 pci_enable_wake(pdev, PCI_D3hot, 0);
5073 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 5074
6fabd715 5075 ixgbe_reset(adapter);
88512539 5076 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5077 result = PCI_ERS_RESULT_RECOVERED;
5078 }
5079
5080 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5081 if (err) {
5082 dev_err(&pdev->dev,
5083 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5084 /* non-fatal, continue */
5085 }
9a799d71 5086
6fabd715 5087 return result;
9a799d71
AK		 5088}
5089
5090/**
5091 * ixgbe_io_resume - called when traffic can start flowing again.
5092 * @pdev: Pointer to PCI device
5093 *
5094 * This callback is called when the error recovery driver tells us that
5095 * its OK to resume normal operation.
5096 */
5097static void ixgbe_io_resume(struct pci_dev *pdev)
5098{
5099 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5100 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5101
5102 if (netif_running(netdev)) {
5103 if (ixgbe_up(adapter)) {
5104 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5105 return;
5106 }
5107 }
5108
5109 netif_device_attach(netdev);
9a799d71
AK		 5110}
5111
5112static struct pci_error_handlers ixgbe_err_handler = {
5113 .error_detected = ixgbe_io_error_detected,
5114 .slot_reset = ixgbe_io_slot_reset,
5115 .resume = ixgbe_io_resume,
5116};
5117
5118static struct pci_driver ixgbe_driver = {
5119 .name = ixgbe_driver_name,
5120 .id_table = ixgbe_pci_tbl,
5121 .probe = ixgbe_probe,
5122 .remove = __devexit_p(ixgbe_remove),
5123#ifdef CONFIG_PM
5124 .suspend = ixgbe_suspend,
5125 .resume = ixgbe_resume,
5126#endif
5127 .shutdown = ixgbe_shutdown,
5128 .err_handler = &ixgbe_err_handler
5129};
5130
5131/**
5132 * ixgbe_init_module - Driver Registration Routine
5133 *
5134 * ixgbe_init_module is the first routine called when the driver is
5135 * loaded. All it does is register with the PCI subsystem.
5136 **/
5137static int __init ixgbe_init_module(void)
5138{
5139 int ret;
5140 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5141 ixgbe_driver_string, ixgbe_driver_version);
5142
5143 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5144
5dd2d332 5145#ifdef CONFIG_IXGBE_DCA
bd0362dd 5146 dca_register_notify(&dca_notifier);
bd0362dd 5147#endif
5dd2d332 5148
9a799d71
AK		 5149 ret = pci_register_driver(&ixgbe_driver);
5150 return ret;
5151}
b4617240 5152
9a799d71
AK		 5153module_init(ixgbe_init_module);
5154
5155/**
5156 * ixgbe_exit_module - Driver Exit Cleanup Routine
5157 *
5158 * ixgbe_exit_module is called just before the driver is removed
5159 * from memory.
5160 **/
5161static void __exit ixgbe_exit_module(void)
5162{
5dd2d332 5163#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5164 dca_unregister_notify(&dca_notifier);
5165#endif
9a799d71
AK		 5166 pci_unregister_driver(&ixgbe_driver);
5167}
bd0362dd 5168
5dd2d332 5169#ifdef CONFIG_IXGBE_DCA
bd0362dd 5170static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5171 void *p)
bd0362dd
JC		 5172{
5173 int ret_val;
5174
5175 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5176 __ixgbe_notify_dca);
bd0362dd
JC		 5177
5178 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5179}
b453368d 5180
5dd2d332 5181#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5182#ifdef DEBUG
5183/**
5184 * ixgbe_get_hw_dev_name - return device name string
5185 * used by hardware layer to print debugging information
5186 **/
5187char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5188{
5189 struct ixgbe_adapter *adapter = hw->back;
5190 return adapter->netdev->name;
5191}
bd0362dd 5192
b453368d 5193#endif
9a799d71
AK		 5194module_exit(ixgbe_exit_module);
5195
5196/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree