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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
8d792cd9 51#define DRV_VERSION "1.3.18-k4"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
b95f5fcb
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
78 board_82598 },
9a799d71
AK		 79
80 /* required last entry */
81 {0, }
82};
83MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
84
a1f96ee7 85#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 86static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
87 void *p);
88static struct notifier_block dca_notifier = {
89 .notifier_call = ixgbe_notify_dca,
90 .next = NULL,
91 .priority = 0
92};
93#endif
94
9a799d71
AK		 95MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
96MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100#define DEFAULT_DEBUG_LEVEL_SHIFT 3
101
5eba3699
AV		 102static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
103{
104 u32 ctrl_ext;
105
106 /* Let firmware take over control of h/w */
107 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
109 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
110}
111
112static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
113{
114 u32 ctrl_ext;
115
116 /* Let firmware know the driver has taken over */
117 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
119 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
120}
9a799d71
AK		 121
122#ifdef DEBUG
123/**
124 * ixgbe_get_hw_dev_name - return device name string
125 * used by hardware layer to print debugging information
126 **/
127char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
128{
129 struct ixgbe_adapter *adapter = hw->back;
130 struct net_device *netdev = adapter->netdev;
131 return netdev->name;
132}
133#endif
134
135static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
136 u8 msix_vector)
137{
138 u32 ivar, index;
139
140 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
141 index = (int_alloc_entry >> 2) & 0x1F;
142 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
143 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
144 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
145 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
146}
147
148static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
149 struct ixgbe_tx_buffer
150 *tx_buffer_info)
151{
152 if (tx_buffer_info->dma) {
e01c31a5 153 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
9a799d71
AK		 154 tx_buffer_info->length, PCI_DMA_TODEVICE);
155 tx_buffer_info->dma = 0;
156 }
157 if (tx_buffer_info->skb) {
158 dev_kfree_skb_any(tx_buffer_info->skb);
159 tx_buffer_info->skb = NULL;
160 }
161 /* tx_buffer_info must be completely set up in the transmit path */
162}
163
164static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
165 struct ixgbe_ring *tx_ring,
e01c31a5 166 unsigned int eop)
9a799d71 167{
e01c31a5
JB		 168 struct ixgbe_hw *hw = &adapter->hw;
169 u32 head, tail;
170
9a799d71 171 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 172 * check with the clearing of time_stamp and movement of eop */
173 head = IXGBE_READ_REG(hw, tx_ring->head);
174 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 175 adapter->detect_tx_hung = false;
e01c31a5
JB		 176 if ((head != tail) &&
177 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 178 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
179 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
180 /* detected Tx unit hang */
e01c31a5
JB		 181 union ixgbe_adv_tx_desc *tx_desc;
182 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 183 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 184 " Tx Queue <%d>\n"
185 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 186 " next_to_use <%x>\n"
187 " next_to_clean <%x>\n"
188 "tx_buffer_info[next_to_clean]\n"
189 " time_stamp <%lx>\n"
e01c31a5
JB		 190 " jiffies <%lx>\n",
191 tx_ring->queue_index,
192 head, tail,
193 tx_ring->next_to_use, eop,
194 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 195 return true;
196 }
197
198 return false;
199}
200
e092be60
AV		 201#define IXGBE_MAX_TXD_PWR 14
202#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
203
204/* Tx Descriptors needed, worst case */
205#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
206 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
207#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
208 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
209
e01c31a5
JB		 210#define GET_TX_HEAD_FROM_RING(ring) (\
211 *(volatile u32 *) \
212 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
213static void ixgbe_tx_timeout(struct net_device *netdev);
214
9a799d71
AK		 215/**
216 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
217 * @adapter: board private structure
e01c31a5 218 * @tx_ring: tx ring to clean
9a799d71
AK		 219 **/
220static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 221 struct ixgbe_ring *tx_ring)
9a799d71 222{
e01c31a5 223 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 224 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 225 struct net_device *netdev = adapter->netdev;
226 struct sk_buff *skb;
227 unsigned int i;
228 u32 head, oldhead;
229 unsigned int count = 0;
230 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 231
e01c31a5
JB		 232 rmb();
233 head = GET_TX_HEAD_FROM_RING(tx_ring);
234 head = le32_to_cpu(head);
9a799d71 235 i = tx_ring->next_to_clean;
e01c31a5
JB		 236 while (1) {
237 while (i != head) {
9a799d71
AK		 238 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
239 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 240 skb = tx_buffer_info->skb;
9a799d71 241
e01c31a5 242 if (skb) {
e092be60 243 unsigned int segs, bytecount;
e01c31a5
JB		 244
245 /* gso_segs is currently only valid for tcp */
e092be60
AV		 246 segs = skb_shinfo(skb)->gso_segs ?: 1;
247 /* multiply data chunks by size of headers */
248 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 249 skb->len;
250 total_packets += segs;
251 total_bytes += bytecount;
e092be60 252 }
e01c31a5 253
9a799d71 254 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 255 tx_buffer_info);
9a799d71
AK		 256
257 i++;
258 if (i == tx_ring->count)
259 i = 0;
9a799d71 260
e01c31a5
JB		 261 count++;
262 if (count == tx_ring->count)
263 goto done_cleaning;
264 }
265 oldhead = head;
266 rmb();
267 head = GET_TX_HEAD_FROM_RING(tx_ring);
268 head = le32_to_cpu(head);
269 if (head == oldhead)
270 goto done_cleaning;
271 } /* while (1) */
272
273done_cleaning:
9a799d71
AK		 274 tx_ring->next_to_clean = i;
275
e092be60 276#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 277 if (unlikely(count && netif_carrier_ok(netdev) &&
278 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 279 /* Make sure that anybody stopping the queue after this
280 * sees the new next_to_clean.
281 */
282 smp_mb();
30eba97a
AV		 283 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
284 !test_bit(__IXGBE_DOWN, &adapter->state)) {
285 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 286 ++adapter->restart_queue;
30eba97a 287 }
e092be60 288 }
9a799d71 289
e01c31a5
JB		 290 if (adapter->detect_tx_hung) {
291 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
292 /* schedule immediate reset if we believe we hung */
293 DPRINTK(PROBE, INFO,
294 "tx hang %d detected, resetting adapter\n",
295 adapter->tx_timeout_count + 1);
296 ixgbe_tx_timeout(adapter->netdev);
297 }
298 }
9a799d71 299
e01c31a5
JB		 300 /* re-arm the interrupt */
301 if ((total_packets >= tx_ring->work_limit) ||
302 (count == tx_ring->count))
303 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 304
e01c31a5
JB		 305 tx_ring->total_bytes += total_bytes;
306 tx_ring->total_packets += total_packets;
307 tx_ring->stats.bytes += total_bytes;
308 tx_ring->stats.packets += total_packets;
309 adapter->net_stats.tx_bytes += total_bytes;
310 adapter->net_stats.tx_packets += total_packets;
311 return (total_packets ? true : false);
9a799d71
AK		 312}
313
a1f96ee7 314#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 315static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
3a581073 316 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 317{
318 u32 rxctrl;
319 int cpu = get_cpu();
3a581073 320 int q = rx_ring - adapter->rx_ring;
bd0362dd 321
3a581073 322 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 323 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
324 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 325 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 326 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
327 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
328 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 329 rx_ring->cpu = cpu;
bd0362dd
JC		 330 }
331 put_cpu();
332}
333
334static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
3a581073 335 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 336{
337 u32 txctrl;
338 int cpu = get_cpu();
3a581073 339 int q = tx_ring - adapter->tx_ring;
bd0362dd 340
3a581073 341 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 342 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
343 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 344 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 345 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
346 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 347 tx_ring->cpu = cpu;
bd0362dd
JC		 348 }
349 put_cpu();
350}
351
352static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
353{
354 int i;
355
356 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
357 return;
358
359 for (i = 0; i < adapter->num_tx_queues; i++) {
360 adapter->tx_ring[i].cpu = -1;
361 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
362 }
363 for (i = 0; i < adapter->num_rx_queues; i++) {
364 adapter->rx_ring[i].cpu = -1;
365 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
366 }
367}
368
369static int __ixgbe_notify_dca(struct device *dev, void *data)
370{
371 struct net_device *netdev = dev_get_drvdata(dev);
372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
373 unsigned long event = *(unsigned long *)data;
374
375 switch (event) {
376 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 377 /* if we're already enabled, don't do it again */
378 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
379 break;
bd0362dd
JC		 380 /* Always use CB2 mode, difference is masked
381 * in the CB driver. */
382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 383 if (dca_add_requester(dev) == 0) {
96b0e0f6 384 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 385 ixgbe_setup_dca(adapter);
386 break;
387 }
388 /* Fall Through since DCA is disabled. */
389 case DCA_PROVIDER_REMOVE:
390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
391 dca_remove_requester(dev);
392 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
394 }
395 break;
396 }
397
652f093f 398 return 0;
bd0362dd
JC		 399}
400
96b0e0f6 401#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
9a799d71
AK		 402/**
403 * ixgbe_receive_skb - Send a completed packet up the stack
404 * @adapter: board private structure
405 * @skb: packet to send up
177db6ff
MC		 406 * @status: hardware indication of status of receive
407 * @rx_ring: rx descriptor ring (for a specific queue) to setup
408 * @rx_desc: rx descriptor
9a799d71
AK		 409 **/
410static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
177db6ff
MC		 411 struct sk_buff *skb, u8 status,
412 struct ixgbe_ring *ring,
413 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 414{
177db6ff
MC		 415 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
416 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 417
177db6ff
MC		 418 if (adapter->netdev->features & NETIF_F_LRO &&
419 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 420 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 421 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
422 adapter->vlgrp, tag,
423 rx_desc);
9a799d71 424 else
177db6ff
MC		 425 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
426 ring->lro_used = true;
427 } else {
428 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
429 if (adapter->vlgrp && is_vlan)
430 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
431 else
432 netif_receive_skb(skb);
433 } else {
434 if (adapter->vlgrp && is_vlan)
435 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
436 else
437 netif_rx(skb);
438 }
9a799d71
AK		 439 }
440}
441
e59bd25d
AV		 442/**
443 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
444 * @adapter: address of board private structure
445 * @status_err: hardware indication of status of receive
446 * @skb: skb currently being received and modified
447 **/
9a799d71 448static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 449 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 450{
451 skb->ip_summed = CHECKSUM_NONE;
452
712744be
JB		 453 /* Rx csum disabled */
454 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 455 return;
e59bd25d
AV		 456
457 /* if IP and error */
458 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
459 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 460 adapter->hw_csum_rx_error++;
461 return;
462 }
e59bd25d
AV		 463
464 if (!(status_err & IXGBE_RXD_STAT_L4CS))
465 return;
466
467 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
468 adapter->hw_csum_rx_error++;
469 return;
470 }
471
9a799d71 472 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 473 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 474 adapter->hw_csum_rx_good++;
475}
476
477/**
478 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
479 * @adapter: address of board private structure
480 **/
481static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 482 struct ixgbe_ring *rx_ring,
483 int cleaned_count)
9a799d71
AK		 484{
485 struct net_device *netdev = adapter->netdev;
486 struct pci_dev *pdev = adapter->pdev;
487 union ixgbe_adv_rx_desc *rx_desc;
3a581073 488 struct ixgbe_rx_buffer *bi;
9a799d71 489 unsigned int i;
7c6e0a43 490 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 491
492 i = rx_ring->next_to_use;
3a581073 493 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 494
495 while (cleaned_count--) {
496 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
497
762f4c57 498 if (!bi->page_dma &&
3a581073 499 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 500 if (!bi->page) {
762f4c57
JB		 501 bi->page = alloc_page(GFP_ATOMIC);
502 if (!bi->page) {
503 adapter->alloc_rx_page_failed++;
504 goto no_buffers;
505 }
506 bi->page_offset = 0;
507 } else {
508 /* use a half page if we're re-using */
509 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 510 }
762f4c57
JB		 511
512 bi->page_dma = pci_map_page(pdev, bi->page,
513 bi->page_offset,
514 (PAGE_SIZE / 2),
515 PCI_DMA_FROMDEVICE);
9a799d71
AK		 516 }
517
3a581073
JB		 518 if (!bi->skb) {
519 struct sk_buff *skb = netdev_alloc_skb(netdev, bufsz);
9a799d71
AK		 520
521 if (!skb) {
522 adapter->alloc_rx_buff_failed++;
523 goto no_buffers;
524 }
525
526 /*
527 * Make buffer alignment 2 beyond a 16 byte boundary
528 * this will result in a 16 byte aligned IP header after
529 * the 14 byte MAC header is removed
530 */
531 skb_reserve(skb, NET_IP_ALIGN);
532
3a581073
JB		 533 bi->skb = skb;
534 bi->dma = pci_map_single(pdev, skb->data, bufsz,
535 PCI_DMA_FROMDEVICE);
9a799d71
AK		 536 }
537 /* Refresh the desc even if buffer_addrs didn't change because
538 * each write-back erases this info. */
539 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 540 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
541 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 542 } else {
3a581073 543 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 544 }
545
546 i++;
547 if (i == rx_ring->count)
548 i = 0;
3a581073 549 bi = &rx_ring->rx_buffer_info[i];
9a799d71 550 }
7c6e0a43 551
9a799d71
AK		 552no_buffers:
553 if (rx_ring->next_to_use != i) {
554 rx_ring->next_to_use = i;
555 if (i-- == 0)
556 i = (rx_ring->count - 1);
557
558 /*
559 * Force memory writes to complete before letting h/w
560 * know there are new descriptors to fetch. (Only
561 * applicable for weak-ordered memory model archs,
562 * such as IA-64).
563 */
564 wmb();
565 writel(i, adapter->hw.hw_addr + rx_ring->tail);
566 }
567}
568
7c6e0a43
JB		 569static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
570{
571 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
572}
573
574static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
575{
576 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
577}
578
9a799d71 579static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 580 struct ixgbe_ring *rx_ring,
581 int *work_done, int work_to_do)
9a799d71
AK		 582{
583 struct net_device *netdev = adapter->netdev;
584 struct pci_dev *pdev = adapter->pdev;
585 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
586 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
587 struct sk_buff *skb;
588 unsigned int i;
7c6e0a43 589 u32 len, staterr;
177db6ff
MC		 590 u16 hdr_info;
591 bool cleaned = false;
9a799d71 592 int cleaned_count = 0;
d2f4fbe2 593 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 594
595 i = rx_ring->next_to_clean;
9a799d71
AK		 596 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
597 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
598 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 599
600 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 601 u32 upper_len = 0;
9a799d71
AK		 602 if (*work_done >= work_to_do)
603 break;
604 (*work_done)++;
605
606 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 607 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
608 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 609 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 610 if (hdr_info & IXGBE_RXDADV_SPH)
611 adapter->rx_hdr_split++;
612 if (len > IXGBE_RX_HDR_SIZE)
613 len = IXGBE_RX_HDR_SIZE;
614 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 615 } else {
9a799d71 616 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 617 }
9a799d71
AK		 618
619 cleaned = true;
620 skb = rx_buffer_info->skb;
621 prefetch(skb->data - NET_IP_ALIGN);
622 rx_buffer_info->skb = NULL;
623
624 if (len && !skb_shinfo(skb)->nr_frags) {
625 pci_unmap_single(pdev, rx_buffer_info->dma,
7c6e0a43
JB		 626 rx_ring->rx_buf_len + NET_IP_ALIGN,
627 PCI_DMA_FROMDEVICE);
9a799d71
AK		 628 skb_put(skb, len);
629 }
630
631 if (upper_len) {
632 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 633 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 634 rx_buffer_info->page_dma = 0;
635 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 636 rx_buffer_info->page,
637 rx_buffer_info->page_offset,
638 upper_len);
639
640 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
641 (page_count(rx_buffer_info->page) != 1))
642 rx_buffer_info->page = NULL;
643 else
644 get_page(rx_buffer_info->page);
9a799d71
AK		 645
646 skb->len += upper_len;
647 skb->data_len += upper_len;
648 skb->truesize += upper_len;
649 }
650
651 i++;
652 if (i == rx_ring->count)
653 i = 0;
654 next_buffer = &rx_ring->rx_buffer_info[i];
655
656 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
657 prefetch(next_rxd);
658
659 cleaned_count++;
660 if (staterr & IXGBE_RXD_STAT_EOP) {
661 rx_ring->stats.packets++;
662 rx_ring->stats.bytes += skb->len;
663 } else {
664 rx_buffer_info->skb = next_buffer->skb;
665 rx_buffer_info->dma = next_buffer->dma;
666 next_buffer->skb = skb;
762f4c57 667 next_buffer->dma = 0;
9a799d71
AK		 668 adapter->non_eop_descs++;
669 goto next_desc;
670 }
671
672 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
673 dev_kfree_skb_irq(skb);
674 goto next_desc;
675 }
676
677 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 678
679 /* probably a little skewed due to removing CRC */
680 total_rx_bytes += skb->len;
681 total_rx_packets++;
682
9a799d71 683 skb->protocol = eth_type_trans(skb, netdev);
177db6ff 684 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 685 netdev->last_rx = jiffies;
686
687next_desc:
688 rx_desc->wb.upper.status_error = 0;
689
690 /* return some buffers to hardware, one at a time is too slow */
691 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
692 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
693 cleaned_count = 0;
694 }
695
696 /* use prefetched values */
697 rx_desc = next_rxd;
698 rx_buffer_info = next_buffer;
699
700 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 701 }
702
703 if (rx_ring->lro_used) {
704 lro_flush_all(&rx_ring->lro_mgr);
705 rx_ring->lro_used = false;
9a799d71
AK		 706 }
707
708 rx_ring->next_to_clean = i;
709 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
710
711 if (cleaned_count)
712 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
713
f494e8fa
AV		 714 rx_ring->total_packets += total_rx_packets;
715 rx_ring->total_bytes += total_rx_bytes;
716 adapter->net_stats.rx_bytes += total_rx_bytes;
717 adapter->net_stats.rx_packets += total_rx_packets;
718
9a799d71
AK		 719 return cleaned;
720}
721
021230d4 722static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 723/**
724 * ixgbe_configure_msix - Configure MSI-X hardware
725 * @adapter: board private structure
726 *
727 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
728 * interrupts.
729 **/
730static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
731{
021230d4
AV		 732 struct ixgbe_q_vector *q_vector;
733 int i, j, q_vectors, v_idx, r_idx;
734 u32 mask;
9a799d71 735
021230d4 736 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 737
021230d4
AV		 738 /* Populate the IVAR table and set the ITR values to the
739 * corresponding register.
740 */
741 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
742 q_vector = &adapter->q_vector[v_idx];
743 /* XXX for_each_bit(...) */
744 r_idx = find_first_bit(q_vector->rxr_idx,
745 adapter->num_rx_queues);
746
747 for (i = 0; i < q_vector->rxr_count; i++) {
748 j = adapter->rx_ring[r_idx].reg_idx;
749 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
750 r_idx = find_next_bit(q_vector->rxr_idx,
751 adapter->num_rx_queues,
752 r_idx + 1);
753 }
754 r_idx = find_first_bit(q_vector->txr_idx,
755 adapter->num_tx_queues);
756
757 for (i = 0; i < q_vector->txr_count; i++) {
758 j = adapter->tx_ring[r_idx].reg_idx;
759 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
760 r_idx = find_next_bit(q_vector->txr_idx,
761 adapter->num_tx_queues,
762 r_idx + 1);
763 }
764
30efa5a3 765 /* if this is a tx only vector halve the interrupt rate */
021230d4 766 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 767 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 768 else
30efa5a3
JB		 769 /* rx only */
770 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 771
772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
773 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 774 }
775
021230d4
AV		 776 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
778
41fb9248 779 /* set up to autoclear timer, and the vectors */
021230d4 780 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 781 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 782 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 783}
784
f494e8fa
AV		 785enum latency_range {
786 lowest_latency = 0,
787 low_latency = 1,
788 bulk_latency = 2,
789 latency_invalid = 255
790};
791
792/**
793 * ixgbe_update_itr - update the dynamic ITR value based on statistics
794 * @adapter: pointer to adapter
795 * @eitr: eitr setting (ints per sec) to give last timeslice
796 * @itr_setting: current throttle rate in ints/second
797 * @packets: the number of packets during this measurement interval
798 * @bytes: the number of bytes during this measurement interval
799 *
800 * Stores a new ITR value based on packets and byte
801 * counts during the last interrupt. The advantage of per interrupt
802 * computation is faster updates and more accurate ITR for the current
803 * traffic pattern. Constants in this function were computed
804 * based on theoretical maximum wire speed and thresholds were set based
805 * on testing data as well as attempting to minimize response time
806 * while increasing bulk throughput.
807 * this functionality is controlled by the InterruptThrottleRate module
808 * parameter (see ixgbe_param.c)
809 **/
810static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
811 u32 eitr, u8 itr_setting,
812 int packets, int bytes)
813{
814 unsigned int retval = itr_setting;
815 u32 timepassed_us;
816 u64 bytes_perint;
817
818 if (packets == 0)
819 goto update_itr_done;
820
821
822 /* simple throttlerate management
823 * 0-20MB/s lowest (100000 ints/s)
824 * 20-100MB/s low (20000 ints/s)
825 * 100-1249MB/s bulk (8000 ints/s)
826 */
827 /* what was last interrupt timeslice? */
828 timepassed_us = 1000000/eitr;
829 bytes_perint = bytes / timepassed_us; /* bytes/usec */
830
831 switch (itr_setting) {
832 case lowest_latency:
833 if (bytes_perint > adapter->eitr_low)
834 retval = low_latency;
835 break;
836 case low_latency:
837 if (bytes_perint > adapter->eitr_high)
838 retval = bulk_latency;
839 else if (bytes_perint <= adapter->eitr_low)
840 retval = lowest_latency;
841 break;
842 case bulk_latency:
843 if (bytes_perint <= adapter->eitr_high)
844 retval = low_latency;
845 break;
846 }
847
848update_itr_done:
849 return retval;
850}
851
852static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
853{
854 struct ixgbe_adapter *adapter = q_vector->adapter;
855 struct ixgbe_hw *hw = &adapter->hw;
856 u32 new_itr;
857 u8 current_itr, ret_itr;
858 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
859 sizeof(struct ixgbe_q_vector);
860 struct ixgbe_ring *rx_ring, *tx_ring;
861
862 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
863 for (i = 0; i < q_vector->txr_count; i++) {
864 tx_ring = &(adapter->tx_ring[r_idx]);
865 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
30efa5a3 866 q_vector->tx_itr,
f494e8fa
AV		 867 tx_ring->total_packets,
868 tx_ring->total_bytes);
869 /* if the result for this queue would decrease interrupt
870 * rate for this vector then use that result */
30efa5a3
JB		 871 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
872 q_vector->tx_itr - 1 : ret_itr);
f494e8fa
AV		 873 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
874 r_idx + 1);
875 }
876
877 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
878 for (i = 0; i < q_vector->rxr_count; i++) {
879 rx_ring = &(adapter->rx_ring[r_idx]);
880 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
30efa5a3 881 q_vector->rx_itr,
f494e8fa
AV		 882 rx_ring->total_packets,
883 rx_ring->total_bytes);
884 /* if the result for this queue would decrease interrupt
885 * rate for this vector then use that result */
30efa5a3
JB		 886 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
887 q_vector->rx_itr - 1 : ret_itr);
f494e8fa
AV		 888 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
889 r_idx + 1);
890 }
891
30efa5a3 892 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 893
894 switch (current_itr) {
895 /* counts and packets in update_itr are dependent on these numbers */
896 case lowest_latency:
897 new_itr = 100000;
898 break;
899 case low_latency:
900 new_itr = 20000; /* aka hwitr = ~200 */
901 break;
902 case bulk_latency:
903 default:
904 new_itr = 8000;
905 break;
906 }
907
908 if (new_itr != q_vector->eitr) {
909 u32 itr_reg;
910 /* do an exponential smoothing */
911 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
912 q_vector->eitr = new_itr;
913 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
914 /* must write high and low 16 bits to reset counter */
915 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
916 itr_reg);
917 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
918 }
919
920 return;
921}
922
cf8280ee
JB		 923
924static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
925{
926 struct ixgbe_hw *hw = &adapter->hw;
927
928 adapter->lsc_int++;
929 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
930 adapter->link_check_timeout = jiffies;
931 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
932 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
933 schedule_work(&adapter->watchdog_task);
934 }
935}
936
9a799d71
AK		 937static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
938{
939 struct net_device *netdev = data;
940 struct ixgbe_adapter *adapter = netdev_priv(netdev);
941 struct ixgbe_hw *hw = &adapter->hw;
942 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
943
cf8280ee
JB		 944 if (eicr & IXGBE_EICR_LSC)
945 ixgbe_check_lsc(adapter);
d4f80882
AV		 946
947 if (!test_bit(__IXGBE_DOWN, &adapter->state))
948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 949
950 return IRQ_HANDLED;
951}
952
953static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
954{
021230d4
AV		 955 struct ixgbe_q_vector *q_vector = data;
956 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 957 struct ixgbe_ring *tx_ring;
021230d4
AV		 958 int i, r_idx;
959
960 if (!q_vector->txr_count)
961 return IRQ_HANDLED;
962
963 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
964 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 965 tx_ring = &(adapter->tx_ring[r_idx]);
a1f96ee7 966#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 967 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 968 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 969#endif
3a581073
JB		 970 tx_ring->total_bytes = 0;
971 tx_ring->total_packets = 0;
972 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4
AV		 973 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
974 r_idx + 1);
975 }
9a799d71 976
9a799d71
AK		 977 return IRQ_HANDLED;
978}
979
021230d4
AV		 980/**
981 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
982 * @irq: unused
983 * @data: pointer to our q_vector struct for this interrupt vector
984 **/
9a799d71
AK		 985static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
986{
021230d4
AV		 987 struct ixgbe_q_vector *q_vector = data;
988 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 989 struct ixgbe_ring *rx_ring;
021230d4 990 int r_idx;
30efa5a3 991 int i;
021230d4
AV		 992
993 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 994 for (i = 0; i < q_vector->rxr_count; i++) {
995 rx_ring = &(adapter->rx_ring[r_idx]);
996 rx_ring->total_bytes = 0;
997 rx_ring->total_packets = 0;
998 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
999 r_idx + 1);
1000 }
1001
021230d4
AV		 1002 if (!q_vector->rxr_count)
1003 return IRQ_HANDLED;
1004
30efa5a3 1005 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1006 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1007 /* disable interrupts on this vector only */
3a581073 1008 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
021230d4
AV		 1009 netif_rx_schedule(adapter->netdev, &q_vector->napi);
1010
1011 return IRQ_HANDLED;
1012}
1013
1014static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1015{
1016 ixgbe_msix_clean_rx(irq, data);
1017 ixgbe_msix_clean_tx(irq, data);
9a799d71 1018
9a799d71
AK		 1019 return IRQ_HANDLED;
1020}
1021
021230d4
AV		 1022/**
1023 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1024 * @napi: napi struct with our devices info in it
1025 * @budget: amount of work driver is allowed to do this pass, in packets
1026 *
1027 **/
9a799d71
AK		 1028static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1029{
021230d4
AV		 1030 struct ixgbe_q_vector *q_vector =
1031 container_of(napi, struct ixgbe_q_vector, napi);
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1033 struct ixgbe_ring *rx_ring;
9a799d71 1034 int work_done = 0;
021230d4 1035 long r_idx;
9a799d71 1036
021230d4 1037 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1038 rx_ring = &(adapter->rx_ring[r_idx]);
a1f96ee7 1039#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 1040 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1041 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1042#endif
9a799d71 1043
3a581073 1044 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1045
021230d4
AV		 1046 /* If all Rx work done, exit the polling mode */
1047 if (work_done < budget) {
1048 netif_rx_complete(adapter->netdev, napi);
30efa5a3 1049 if (adapter->itr_setting & 3)
f494e8fa 1050 ixgbe_set_itr_msix(q_vector);
9a799d71 1051 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1053 }
1054
1055 return work_done;
1056}
1057
021230d4
AV		 1058static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1059 int r_idx)
1060{
1061 a->q_vector[v_idx].adapter = a;
1062 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1063 a->q_vector[v_idx].rxr_count++;
1064 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1065}
1066
1067static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1068 int r_idx)
1069{
1070 a->q_vector[v_idx].adapter = a;
1071 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1072 a->q_vector[v_idx].txr_count++;
1073 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1074}
1075
9a799d71 1076/**
021230d4
AV		 1077 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1078 * @adapter: board private structure to initialize
1079 * @vectors: allotted vector count for descriptor rings
9a799d71 1080 *
021230d4
AV		 1081 * This function maps descriptor rings to the queue-specific vectors
1082 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1083 * one vector per ring/queue, but on a constrained vector budget, we
1084 * group the rings as "efficiently" as possible. You would add new
1085 * mapping configurations in here.
9a799d71 1086 **/
021230d4
AV		 1087static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1088 int vectors)
1089{
1090 int v_start = 0;
1091 int rxr_idx = 0, txr_idx = 0;
1092 int rxr_remaining = adapter->num_rx_queues;
1093 int txr_remaining = adapter->num_tx_queues;
1094 int i, j;
1095 int rqpv, tqpv;
1096 int err = 0;
1097
1098 /* No mapping required if MSI-X is disabled. */
1099 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1100 goto out;
9a799d71 1101
021230d4
AV		 1102 /*
1103 * The ideal configuration...
1104 * We have enough vectors to map one per queue.
1105 */
1106 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1107 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1108 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1109
021230d4
AV		 1110 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1111 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1112
9a799d71 1113 goto out;
021230d4 1114 }
9a799d71 1115
021230d4
AV		 1116 /*
1117 * If we don't have enough vectors for a 1-to-1
1118 * mapping, we'll have to group them so there are
1119 * multiple queues per vector.
1120 */
1121 /* Re-adjusting *qpv takes care of the remainder. */
1122 for (i = v_start; i < vectors; i++) {
1123 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1124 for (j = 0; j < rqpv; j++) {
1125 map_vector_to_rxq(adapter, i, rxr_idx);
1126 rxr_idx++;
1127 rxr_remaining--;
1128 }
1129 }
1130 for (i = v_start; i < vectors; i++) {
1131 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1132 for (j = 0; j < tqpv; j++) {
1133 map_vector_to_txq(adapter, i, txr_idx);
1134 txr_idx++;
1135 txr_remaining--;
9a799d71 1136 }
9a799d71
AK		 1137 }
1138
021230d4
AV		 1139out:
1140 return err;
1141}
1142
1143/**
1144 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1145 * @adapter: board private structure
1146 *
1147 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1148 * interrupts from the kernel.
1149 **/
1150static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1151{
1152 struct net_device *netdev = adapter->netdev;
1153 irqreturn_t (*handler)(int, void *);
1154 int i, vector, q_vectors, err;
1155
1156 /* Decrement for Other and TCP Timer vectors */
1157 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1158
1159 /* Map the Tx/Rx rings to the vectors we were allotted. */
1160 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1161 if (err)
1162 goto out;
1163
1164#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1165 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1166 &ixgbe_msix_clean_many)
1167 for (vector = 0; vector < q_vectors; vector++) {
1168 handler = SET_HANDLER(&adapter->q_vector[vector]);
1169 sprintf(adapter->name[vector], "%s:v%d-%s",
1170 netdev->name, vector,
1171 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1172 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1173 err = request_irq(adapter->msix_entries[vector].vector,
1174 handler, 0, adapter->name[vector],
1175 &(adapter->q_vector[vector]));
9a799d71
AK		 1176 if (err) {
1177 DPRINTK(PROBE, ERR,
1178 "request_irq failed for MSIX interrupt "
1179 "Error: %d\n", err);
021230d4 1180 goto free_queue_irqs;
9a799d71 1181 }
9a799d71
AK		 1182 }
1183
021230d4
AV		 1184 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1185 err = request_irq(adapter->msix_entries[vector].vector,
1186 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1187 if (err) {
1188 DPRINTK(PROBE, ERR,
1189 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1190 goto free_queue_irqs;
9a799d71
AK		 1191 }
1192
9a799d71
AK		 1193 return 0;
1194
021230d4
AV		 1195free_queue_irqs:
1196 for (i = vector - 1; i >= 0; i--)
1197 free_irq(adapter->msix_entries[--vector].vector,
1198 &(adapter->q_vector[i]));
1199 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1200 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1201 kfree(adapter->msix_entries);
1202 adapter->msix_entries = NULL;
021230d4 1203out:
9a799d71
AK		 1204 return err;
1205}
1206
f494e8fa
AV		 1207static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1208{
1209 struct ixgbe_hw *hw = &adapter->hw;
1210 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1211 u8 current_itr;
1212 u32 new_itr = q_vector->eitr;
1213 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1214 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1215
30efa5a3
JB		 1216 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1217 q_vector->tx_itr,
1218 tx_ring->total_packets,
1219 tx_ring->total_bytes);
1220 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1221 q_vector->rx_itr,
1222 rx_ring->total_packets,
1223 rx_ring->total_bytes);
f494e8fa 1224
30efa5a3 1225 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1226
1227 switch (current_itr) {
1228 /* counts and packets in update_itr are dependent on these numbers */
1229 case lowest_latency:
1230 new_itr = 100000;
1231 break;
1232 case low_latency:
1233 new_itr = 20000; /* aka hwitr = ~200 */
1234 break;
1235 case bulk_latency:
1236 new_itr = 8000;
1237 break;
1238 default:
1239 break;
1240 }
1241
1242 if (new_itr != q_vector->eitr) {
1243 u32 itr_reg;
1244 /* do an exponential smoothing */
1245 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1246 q_vector->eitr = new_itr;
1247 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1248 /* must write high and low 16 bits to reset counter */
1249 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1250 }
1251
1252 return;
1253}
1254
021230d4
AV		 1255static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1256
9a799d71 1257/**
021230d4 1258 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1259 * @irq: interrupt number
1260 * @data: pointer to a network interface device structure
1261 * @pt_regs: CPU registers structure
1262 **/
1263static irqreturn_t ixgbe_intr(int irq, void *data)
1264{
1265 struct net_device *netdev = data;
1266 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1267 struct ixgbe_hw *hw = &adapter->hw;
1268 u32 eicr;
1269
9a799d71 1270
021230d4
AV		 1271 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1272 * therefore no explict interrupt disable is necessary */
1273 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1274 if (!eicr) {
1275 /* shared interrupt alert!
1276 * make sure interrupts are enabled because the read will
1277 * have disabled interrupts due to EIAM */
1278 ixgbe_irq_enable(adapter);
9a799d71 1279 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1280 }
9a799d71 1281
cf8280ee
JB		 1282 if (eicr & IXGBE_EICR_LSC)
1283 ixgbe_check_lsc(adapter);
021230d4
AV		 1284
1285 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1286 adapter->tx_ring[0].total_packets = 0;
1287 adapter->tx_ring[0].total_bytes = 0;
1288 adapter->rx_ring[0].total_packets = 0;
1289 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1290 /* would disable interrupts here but EIAM disabled it */
1291 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1292 }
1293
1294 return IRQ_HANDLED;
1295}
1296
021230d4
AV		 1297static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1298{
1299 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1300
1301 for (i = 0; i < q_vectors; i++) {
1302 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1303 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1304 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1305 q_vector->rxr_count = 0;
1306 q_vector->txr_count = 0;
1307 }
1308}
1309
9a799d71
AK		 1310/**
1311 * ixgbe_request_irq - initialize interrupts
1312 * @adapter: board private structure
1313 *
1314 * Attempts to configure interrupts using the best available
1315 * capabilities of the hardware and kernel.
1316 **/
021230d4 1317static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1318{
1319 struct net_device *netdev = adapter->netdev;
021230d4 1320 int err;
9a799d71 1321
021230d4
AV		 1322 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1323 err = ixgbe_request_msix_irqs(adapter);
1324 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1325 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1326 netdev->name, netdev);
1327 } else {
1328 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1329 netdev->name, netdev);
9a799d71
AK		 1330 }
1331
9a799d71
AK		 1332 if (err)
1333 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1334
9a799d71
AK		 1335 return err;
1336}
1337
1338static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1339{
1340 struct net_device *netdev = adapter->netdev;
1341
1342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1343 int i, q_vectors;
9a799d71 1344
021230d4
AV		 1345 q_vectors = adapter->num_msix_vectors;
1346
1347 i = q_vectors - 1;
9a799d71 1348 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1349
021230d4
AV		 1350 i--;
1351 for (; i >= 0; i--) {
1352 free_irq(adapter->msix_entries[i].vector,
1353 &(adapter->q_vector[i]));
1354 }
1355
1356 ixgbe_reset_q_vectors(adapter);
1357 } else {
1358 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1359 }
1360}
1361
1362/**
1363 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1364 * @adapter: board private structure
1365 **/
1366static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1367{
9a799d71
AK		 1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1369 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1370 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1371 int i;
1372 for (i = 0; i < adapter->num_msix_vectors; i++)
1373 synchronize_irq(adapter->msix_entries[i].vector);
1374 } else {
1375 synchronize_irq(adapter->pdev->irq);
1376 }
9a799d71
AK		 1377}
1378
1379/**
1380 * ixgbe_irq_enable - Enable default interrupt generation settings
1381 * @adapter: board private structure
1382 **/
1383static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1384{
021230d4
AV		 1385 u32 mask;
1386 mask = IXGBE_EIMS_ENABLE_MASK;
1387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1388 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1389}
1390
1391/**
1392 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1393 *
1394 **/
1395static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1396{
9a799d71
AK		 1397 struct ixgbe_hw *hw = &adapter->hw;
1398
021230d4 1399 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1400 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1401
1402 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1403 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1404
1405 map_vector_to_rxq(adapter, 0, 0);
1406 map_vector_to_txq(adapter, 0, 0);
1407
1408 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1409}
1410
1411/**
3a581073 1412 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1413 * @adapter: board private structure
1414 *
1415 * Configure the Tx unit of the MAC after a reset.
1416 **/
1417static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1418{
e01c31a5 1419 u64 tdba, tdwba;
9a799d71 1420 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1421 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1422
1423 /* Setup the HW Tx Head and Tail descriptor pointers */
1424 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1425 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1426 j = ring->reg_idx;
1427 tdba = ring->dma;
1428 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1429 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1430 (tdba & DMA_32BIT_MASK));
021230d4 1431 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1432 tdwba = ring->dma +
1433 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1434 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1435 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1436 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1437 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1438 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1439 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1440 adapter->tx_ring[i].head = IXGBE_TDH(j);
1441 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1442 /* Disable Tx Head Writeback RO bit, since this hoses
1443 * bookkeeping if things aren't delivered in order.
1444 */
e01c31a5 1445 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1446 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1447 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1448 }
9a799d71
AK		 1449}
1450
cc41ac7c
JB		 1451#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1452
1453static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1454{
1455 struct ixgbe_ring *rx_ring;
1456 u32 srrctl;
1457 int queue0;
3be1adfb
AD		 1458 unsigned long mask;
1459
1460 /* program one srrctl register per VMDq index */
1461 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1462 long shift, len;
1463 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1464 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1465 shift = find_first_bit(&mask, len);
1466 queue0 = index & mask;
1467 index = (index & mask) >> shift;
1468 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1469 } else {
3be1adfb
AD		 1470 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1471 queue0 = index & mask;
1472 index = index & mask;
cc41ac7c 1473 }
3be1adfb 1474
cc41ac7c
JB		 1475 rx_ring = &adapter->rx_ring[queue0];
1476
1477 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1478
1479 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1480 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1481
1482 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1483 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1484 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1485 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1486 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1487 IXGBE_SRRCTL_BSIZEHDR_MASK);
1488 } else {
1489 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1490
1491 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1492 srrctl |= IXGBE_RXBUFFER_2048 >>
1493 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1494 else
1495 srrctl |= rx_ring->rx_buf_len >>
1496 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1497 }
1498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1499}
9a799d71 1500
177db6ff
MC		 1501/**
1502 * ixgbe_get_skb_hdr - helper function for LRO header processing
1503 * @skb: pointer to sk_buff to be added to LRO packet
1504 * @iphdr: pointer to tcp header structure
1505 * @tcph: pointer to tcp header structure
1506 * @hdr_flags: pointer to header flags
1507 * @priv: private data
1508 **/
1509static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1510 u64 *hdr_flags, void *priv)
1511{
1512 union ixgbe_adv_rx_desc *rx_desc = priv;
1513
1514 /* Verify that this is a valid IPv4 TCP packet */
e9990a9c
JB		 1515 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1516 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
177db6ff
MC		 1517 return -1;
1518
1519 /* Set network headers */
1520 skb_reset_network_header(skb);
1521 skb_set_transport_header(skb, ip_hdrlen(skb));
1522 *iphdr = ip_hdr(skb);
1523 *tcph = tcp_hdr(skb);
1524 *hdr_flags = LRO_IPV4 | LRO_TCP;
1525 return 0;
1526}
1527
cc41ac7c
JB		 1528#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1529 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1530
9a799d71 1531/**
3a581073 1532 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1533 * @adapter: board private structure
1534 *
1535 * Configure the Rx unit of the MAC after a reset.
1536 **/
1537static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1538{
1539 u64 rdba;
1540 struct ixgbe_hw *hw = &adapter->hw;
1541 struct net_device *netdev = adapter->netdev;
1542 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1543 int i, j;
9a799d71 1544 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1545 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1546 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1547 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1548 u32 fctrl, hlreg0;
9a799d71 1549 u32 pages;
cc41ac7c
JB		 1550 u32 reta = 0, mrqc;
1551 u32 rdrxctl;
7c6e0a43 1552 int rx_buf_len;
9a799d71
AK		 1553
1554 /* Decide whether to use packet split mode or not */
762f4c57 1555 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1556
1557 /* Set the RX buffer length according to the mode */
1558 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1559 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1560 } else {
1561 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1562 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1563 else
7c6e0a43 1564 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1565 }
1566
1567 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1568 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1569 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1571
1572 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1573 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1574 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1575 else
1576 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1577 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1578
1579 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1580
9a799d71
AK		 1581 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1582 /* disable receives while setting up the descriptors */
1583 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1584 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1585
1586 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1587 * the Base and Length of the Rx Descriptor Ring */
1588 for (i = 0; i < adapter->num_rx_queues; i++) {
1589 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1590 j = adapter->rx_ring[i].reg_idx;
1591 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1592 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1593 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1594 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1595 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1596 adapter->rx_ring[i].head = IXGBE_RDH(j);
1597 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1598 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
e9990a9c
JB		 1599 /* Intitial LRO Settings */
1600 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1601 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1602 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1603 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1604 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1605 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1606 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1607 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1608 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
cc41ac7c
JB		 1609
1610 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1611 }
1612
cc41ac7c
JB		 1613 /*
1614 * For VMDq support of different descriptor types or
1615 * buffer sizes through the use of multiple SRRCTL
1616 * registers, RDRXCTL.MVMEN must be set to 1
1617 *
1618 * also, the manual doesn't mention it clearly but DCA hints
1619 * will only use queue 0's tags unless this bit is set. Side
1620 * effects of setting this bit are only that SRRCTL must be
1621 * fully programmed [0..15]
1622 */
1623 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1624 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1625 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1626
177db6ff 1627
021230d4 1628 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1629 /* Fill out redirection table */
021230d4
AV		 1630 for (i = 0, j = 0; i < 128; i++, j++) {
1631 if (j == adapter->ring_feature[RING_F_RSS].indices)
1632 j = 0;
1633 /* reta = 4-byte sliding window of
1634 * 0x00..(indices-1)(indices-1)00..etc. */
1635 reta = (reta << 8) | (j * 0x11);
1636 if ((i & 3) == 3)
1637 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1638 }
1639
1640 /* Fill out hash function seeds */
1641 for (i = 0; i < 10; i++)
7c6e0a43 1642 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1643
1644 mrqc = IXGBE_MRQC_RSSEN
1645 /* Perform hash on these packet types */
7c6e0a43
JB		 1646 | IXGBE_MRQC_RSS_FIELD_IPV4
1647 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1648 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1649 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1650 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1651 | IXGBE_MRQC_RSS_FIELD_IPV6
1652 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1653 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1654 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1655 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1656 }
9a799d71 1657
021230d4
AV		 1658 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1659
1660 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1661 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1662 /* Disable indicating checksum in descriptor, enables
1663 * RSS hash */
9a799d71 1664 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1665 }
021230d4
AV		 1666 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1667 /* Enable IPv4 payload checksum for UDP fragments
1668 * if PCSD is not set */
1669 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1670 }
1671
1672 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1673}
1674
1675static void ixgbe_vlan_rx_register(struct net_device *netdev,
1676 struct vlan_group *grp)
1677{
1678 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1679 u32 ctrl;
1680
d4f80882
AV		 1681 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1682 ixgbe_irq_disable(adapter);
9a799d71
AK		 1683 adapter->vlgrp = grp;
1684
1685 if (grp) {
1686 /* enable VLAN tag insert/strip */
1687 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1688 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1689 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1691 }
1692
d4f80882
AV		 1693 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1694 ixgbe_irq_enable(adapter);
9a799d71
AK		 1695}
1696
1697static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1698{
1699 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1700
1701 /* add VID to filter table */
1702 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1703}
1704
1705static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1706{
1707 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1708
d4f80882
AV		 1709 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1710 ixgbe_irq_disable(adapter);
1711
9a799d71 1712 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1713
1714 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1715 ixgbe_irq_enable(adapter);
9a799d71
AK		 1716
1717 /* remove VID from filter table */
1718 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1719}
1720
1721static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1722{
1723 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1724
1725 if (adapter->vlgrp) {
1726 u16 vid;
1727 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1728 if (!vlan_group_get_device(adapter->vlgrp, vid))
1729 continue;
1730 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1731 }
1732 }
1733}
1734
2c5645cf
CL		 1735static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1736{
1737 struct dev_mc_list *mc_ptr;
1738 u8 *addr = *mc_addr_ptr;
1739 *vmdq = 0;
1740
1741 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1742 if (mc_ptr->next)
1743 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1744 else
1745 *mc_addr_ptr = NULL;
1746
1747 return addr;
1748}
1749
9a799d71 1750/**
2c5645cf 1751 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1752 * @netdev: network interface device structure
1753 *
2c5645cf
CL		 1754 * The set_rx_method entry point is called whenever the unicast/multicast
1755 * address list or the network interface flags are updated. This routine is
1756 * responsible for configuring the hardware for proper unicast, multicast and
1757 * promiscuous mode.
9a799d71 1758 **/
2c5645cf 1759static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1760{
1761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1762 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1763 u32 fctrl, vlnctrl;
2c5645cf
CL		 1764 u8 *addr_list = NULL;
1765 int addr_count = 0;
9a799d71
AK		 1766
1767 /* Check for Promiscuous and All Multicast modes */
1768
1769 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1770 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1771
1772 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1773 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1774 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1775 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1776 } else {
746b9f02
PM		 1777 if (netdev->flags & IFF_ALLMULTI) {
1778 fctrl |= IXGBE_FCTRL_MPE;
1779 fctrl &= ~IXGBE_FCTRL_UPE;
1780 } else {
1781 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1782 }
3d01625a 1783 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1784 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1785 }
1786
1787 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1788 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1789
2c5645cf
CL		 1790 /* reprogram secondary unicast list */
1791 addr_count = netdev->uc_count;
1792 if (addr_count)
1793 addr_list = netdev->uc_list->dmi_addr;
1794 ixgbe_update_uc_addr_list(hw, addr_list, addr_count,
1795 ixgbe_addr_list_itr);
9a799d71 1796
2c5645cf
CL		 1797 /* reprogram multicast list */
1798 addr_count = netdev->mc_count;
1799 if (addr_count)
1800 addr_list = netdev->mc_list->dmi_addr;
1801 ixgbe_update_mc_addr_list(hw, addr_list, addr_count,
1802 ixgbe_addr_list_itr);
9a799d71
AK		 1803}
1804
021230d4
AV		 1805static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1806{
1807 int q_idx;
1808 struct ixgbe_q_vector *q_vector;
1809 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1810
1811 /* legacy and MSI only use one vector */
1812 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1813 q_vectors = 1;
1814
1815 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1816 q_vector = &adapter->q_vector[q_idx];
1817 if (!q_vector->rxr_count)
1818 continue;
1819 napi_enable(&q_vector->napi);
1820 }
1821}
1822
1823static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1824{
1825 int q_idx;
1826 struct ixgbe_q_vector *q_vector;
1827 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1828
1829 /* legacy and MSI only use one vector */
1830 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1831 q_vectors = 1;
1832
1833 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1834 q_vector = &adapter->q_vector[q_idx];
1835 if (!q_vector->rxr_count)
1836 continue;
1837 napi_disable(&q_vector->napi);
1838 }
1839}
1840
9a799d71
AK		 1841static void ixgbe_configure(struct ixgbe_adapter *adapter)
1842{
1843 struct net_device *netdev = adapter->netdev;
1844 int i;
1845
2c5645cf 1846 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1847
1848 ixgbe_restore_vlan(adapter);
1849
1850 ixgbe_configure_tx(adapter);
1851 ixgbe_configure_rx(adapter);
1852 for (i = 0; i < adapter->num_rx_queues; i++)
1853 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1854 (adapter->rx_ring[i].count - 1));
1855}
1856
1857static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1858{
1859 struct net_device *netdev = adapter->netdev;
9a799d71 1860 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1861 int i, j = 0;
9a799d71 1862 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1863 u32 txdctl, rxdctl, mhadd;
1864 u32 gpie;
9a799d71 1865
5eba3699
AV		 1866 ixgbe_get_hw_control(adapter);
1867
021230d4
AV		 1868 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1869 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1870 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1871 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1872 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1873 } else {
1874 /* MSI only */
021230d4 1875 gpie = 0;
9a799d71 1876 }
021230d4
AV		 1877 /* XXX: to interrupt immediately for EICS writes, enable this */
1878 /* gpie |= IXGBE_GPIE_EIMEN; */
1879 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1880 }
1881
021230d4
AV		 1882 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1883 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1884 * specifically only auto mask tx and rx interrupts */
1885 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1886 }
9a799d71 1887
021230d4 1888 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1889 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1890 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1891 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1892
1893 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1894 }
1895
1896 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1897 j = adapter->tx_ring[i].reg_idx;
1898 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 1899 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1900 txdctl |= (8 << 16);
9a799d71 1901 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1902 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1903 }
1904
1905 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1906 j = adapter->rx_ring[i].reg_idx;
1907 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1908 /* enable PTHRESH=32 descriptors (half the internal cache)
1909 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1910 * this also removes a pesky rx_no_buffer_count increment */
1911 rxdctl |= 0x0020;
9a799d71 1912 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1913 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1914 }
1915 /* enable all receives */
1916 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1917 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1918 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1919
1920 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1921 ixgbe_configure_msix(adapter);
1922 else
1923 ixgbe_configure_msi_and_legacy(adapter);
1924
1925 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1926 ixgbe_napi_enable_all(adapter);
1927
1928 /* clear any pending interrupts, may auto mask */
1929 IXGBE_READ_REG(hw, IXGBE_EICR);
1930
9a799d71
AK		 1931 ixgbe_irq_enable(adapter);
1932
1933 /* bring the link up in the watchdog, this could race with our first
1934 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 1935 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1936 adapter->link_check_timeout = jiffies;
9a799d71
AK		 1937 mod_timer(&adapter->watchdog_timer, jiffies);
1938 return 0;
1939}
1940
d4f80882
AV		 1941void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1942{
1943 WARN_ON(in_interrupt());
1944 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1945 msleep(1);
1946 ixgbe_down(adapter);
1947 ixgbe_up(adapter);
1948 clear_bit(__IXGBE_RESETTING, &adapter->state);
1949}
1950
9a799d71
AK		 1951int ixgbe_up(struct ixgbe_adapter *adapter)
1952{
1953 /* hardware has been reset, we need to reload some things */
1954 ixgbe_configure(adapter);
1955
1956 return ixgbe_up_complete(adapter);
1957}
1958
1959void ixgbe_reset(struct ixgbe_adapter *adapter)
1960{
1961 if (ixgbe_init_hw(&adapter->hw))
1962 DPRINTK(PROBE, ERR, "Hardware Error\n");
1963
1964 /* reprogram the RAR[0] in case user changed it. */
1965 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1966
1967}
1968
1969#ifdef CONFIG_PM
1970static int ixgbe_resume(struct pci_dev *pdev)
1971{
1972 struct net_device *netdev = pci_get_drvdata(pdev);
1973 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1974 u32 err;
9a799d71
AK		 1975
1976 pci_set_power_state(pdev, PCI_D0);
1977 pci_restore_state(pdev);
1978 err = pci_enable_device(pdev);
1979 if (err) {
1980 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1981 "suspend\n");
1982 return err;
1983 }
1984 pci_set_master(pdev);
1985
1986 pci_enable_wake(pdev, PCI_D3hot, 0);
1987 pci_enable_wake(pdev, PCI_D3cold, 0);
1988
1989 if (netif_running(netdev)) {
021230d4 1990 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1991 if (err)
1992 return err;
1993 }
1994
1995 ixgbe_reset(adapter);
1996
1997 if (netif_running(netdev))
1998 ixgbe_up(adapter);
1999
2000 netif_device_attach(netdev);
2001
2002 return 0;
2003}
2004#endif
2005
2006/**
2007 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2008 * @adapter: board private structure
2009 * @rx_ring: ring to free buffers from
2010 **/
2011static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2012 struct ixgbe_ring *rx_ring)
2013{
2014 struct pci_dev *pdev = adapter->pdev;
2015 unsigned long size;
2016 unsigned int i;
2017
2018 /* Free all the Rx ring sk_buffs */
2019
2020 for (i = 0; i < rx_ring->count; i++) {
2021 struct ixgbe_rx_buffer *rx_buffer_info;
2022
2023 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2024 if (rx_buffer_info->dma) {
2025 pci_unmap_single(pdev, rx_buffer_info->dma,
7c6e0a43 2026 rx_ring->rx_buf_len,
9a799d71
AK		 2027 PCI_DMA_FROMDEVICE);
2028 rx_buffer_info->dma = 0;
2029 }
2030 if (rx_buffer_info->skb) {
2031 dev_kfree_skb(rx_buffer_info->skb);
2032 rx_buffer_info->skb = NULL;
2033 }
2034 if (!rx_buffer_info->page)
2035 continue;
762f4c57
JB		 2036 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2037 PCI_DMA_FROMDEVICE);
9a799d71 2038 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2039 put_page(rx_buffer_info->page);
2040 rx_buffer_info->page = NULL;
762f4c57 2041 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2042 }
2043
2044 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2045 memset(rx_ring->rx_buffer_info, 0, size);
2046
2047 /* Zero out the descriptor ring */
2048 memset(rx_ring->desc, 0, rx_ring->size);
2049
2050 rx_ring->next_to_clean = 0;
2051 rx_ring->next_to_use = 0;
2052
2053 writel(0, adapter->hw.hw_addr + rx_ring->head);
2054 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2055}
2056
2057/**
2058 * ixgbe_clean_tx_ring - Free Tx Buffers
2059 * @adapter: board private structure
2060 * @tx_ring: ring to be cleaned
2061 **/
2062static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2063 struct ixgbe_ring *tx_ring)
2064{
2065 struct ixgbe_tx_buffer *tx_buffer_info;
2066 unsigned long size;
2067 unsigned int i;
2068
2069 /* Free all the Tx ring sk_buffs */
2070
2071 for (i = 0; i < tx_ring->count; i++) {
2072 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2073 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2074 }
2075
2076 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2077 memset(tx_ring->tx_buffer_info, 0, size);
2078
2079 /* Zero out the descriptor ring */
2080 memset(tx_ring->desc, 0, tx_ring->size);
2081
2082 tx_ring->next_to_use = 0;
2083 tx_ring->next_to_clean = 0;
2084
2085 writel(0, adapter->hw.hw_addr + tx_ring->head);
2086 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2087}
2088
2089/**
021230d4 2090 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2091 * @adapter: board private structure
2092 **/
021230d4 2093static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2094{
2095 int i;
2096
021230d4
AV		 2097 for (i = 0; i < adapter->num_rx_queues; i++)
2098 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2099}
2100
2101/**
021230d4 2102 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2103 * @adapter: board private structure
2104 **/
021230d4 2105static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2106{
2107 int i;
2108
021230d4
AV		 2109 for (i = 0; i < adapter->num_tx_queues; i++)
2110 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2111}
2112
2113void ixgbe_down(struct ixgbe_adapter *adapter)
2114{
2115 struct net_device *netdev = adapter->netdev;
2116 u32 rxctrl;
2117
2118 /* signal that we are down to the interrupt handler */
2119 set_bit(__IXGBE_DOWN, &adapter->state);
2120
2121 /* disable receives */
2122 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
2123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
2124 rxctrl & ~IXGBE_RXCTRL_RXEN);
2125
2126 netif_tx_disable(netdev);
2127
2128 /* disable transmits in the hardware */
2129
2130 /* flush both disables */
2131 IXGBE_WRITE_FLUSH(&adapter->hw);
2132 msleep(10);
2133
2134 ixgbe_irq_disable(adapter);
2135
021230d4 2136 ixgbe_napi_disable_all(adapter);
9a799d71 2137 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2138 cancel_work_sync(&adapter->watchdog_task);
9a799d71
AK		 2139
2140 netif_carrier_off(netdev);
fd2ea0a7 2141 netif_tx_stop_all_queues(netdev);
9a799d71 2142
a1f96ee7 2143#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
96b0e0f6
JB		 2144 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2145 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2146 dca_remove_requester(&adapter->pdev->dev);
2147 }
2148
2149#endif
6f4a0e45
PL		 2150 if (!pci_channel_offline(adapter->pdev))
2151 ixgbe_reset(adapter);
9a799d71
AK		 2152 ixgbe_clean_all_tx_rings(adapter);
2153 ixgbe_clean_all_rx_rings(adapter);
2154
a1f96ee7 2155#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
96b0e0f6
JB		 2156 /* since we reset the hardware DCA settings were cleared */
2157 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2158 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2159 /* always use CB2 mode, difference is masked
2160 * in the CB driver */
2161 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
2162 ixgbe_setup_dca(adapter);
2163 }
2164#endif
9a799d71
AK		 2165}
2166
2167static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2168{
2169 struct net_device *netdev = pci_get_drvdata(pdev);
2170 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2171#ifdef CONFIG_PM
2172 int retval = 0;
2173#endif
2174
2175 netif_device_detach(netdev);
2176
2177 if (netif_running(netdev)) {
2178 ixgbe_down(adapter);
2179 ixgbe_free_irq(adapter);
2180 }
2181
2182#ifdef CONFIG_PM
2183 retval = pci_save_state(pdev);
2184 if (retval)
2185 return retval;
2186#endif
2187
2188 pci_enable_wake(pdev, PCI_D3hot, 0);
2189 pci_enable_wake(pdev, PCI_D3cold, 0);
2190
5eba3699
AV		 2191 ixgbe_release_hw_control(adapter);
2192
9a799d71
AK		 2193 pci_disable_device(pdev);
2194
2195 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2196
2197 return 0;
2198}
2199
2200static void ixgbe_shutdown(struct pci_dev *pdev)
2201{
2202 ixgbe_suspend(pdev, PMSG_SUSPEND);
2203}
2204
2205/**
021230d4
AV		 2206 * ixgbe_poll - NAPI Rx polling callback
2207 * @napi: structure for representing this polling device
2208 * @budget: how many packets driver is allowed to clean
2209 *
2210 * This function is used for legacy and MSI, NAPI mode
9a799d71 2211 **/
021230d4 2212static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2213{
021230d4
AV		 2214 struct ixgbe_q_vector *q_vector = container_of(napi,
2215 struct ixgbe_q_vector, napi);
2216 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 2217 int tx_cleaned = 0, work_done = 0;
9a799d71 2218
a1f96ee7 2219#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 2220 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2221 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2222 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2223 }
2224#endif
2225
d2c7ddd6 2226 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2227 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2228
d2c7ddd6
DM		 2229 if (tx_cleaned)
2230 work_done = budget;
2231
53e52c72
DM		 2232 /* If budget not fully consumed, exit the polling mode */
2233 if (work_done < budget) {
021230d4 2234 netif_rx_complete(adapter->netdev, napi);
30efa5a3 2235 if (adapter->itr_setting & 3)
f494e8fa 2236 ixgbe_set_itr(adapter);
d4f80882
AV		 2237 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2238 ixgbe_irq_enable(adapter);
9a799d71
AK		 2239 }
2240
2241 return work_done;
2242}
2243
2244/**
2245 * ixgbe_tx_timeout - Respond to a Tx Hang
2246 * @netdev: network interface device structure
2247 **/
2248static void ixgbe_tx_timeout(struct net_device *netdev)
2249{
2250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2251
2252 /* Do the reset outside of interrupt context */
2253 schedule_work(&adapter->reset_task);
2254}
2255
2256static void ixgbe_reset_task(struct work_struct *work)
2257{
2258 struct ixgbe_adapter *adapter;
2259 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2260
2261 adapter->tx_timeout_count++;
2262
d4f80882 2263 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2264}
2265
021230d4
AV		 2266static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2267 int vectors)
2268{
2269 int err, vector_threshold;
2270
2271 /* We'll want at least 3 (vector_threshold):
2272 * 1) TxQ[0] Cleanup
2273 * 2) RxQ[0] Cleanup
2274 * 3) Other (Link Status Change, etc.)
2275 * 4) TCP Timer (optional)
2276 */
2277 vector_threshold = MIN_MSIX_COUNT;
2278
2279 /* The more we get, the more we will assign to Tx/Rx Cleanup
2280 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2281 * Right now, we simply care about how many we'll get; we'll
2282 * set them up later while requesting irq's.
2283 */
2284 while (vectors >= vector_threshold) {
2285 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2286 vectors);
2287 if (!err) /* Success in acquiring all requested vectors. */
2288 break;
2289 else if (err < 0)
2290 vectors = 0; /* Nasty failure, quit now */
2291 else /* err == number of vectors we should try again with */
2292 vectors = err;
2293 }
2294
2295 if (vectors < vector_threshold) {
2296 /* Can't allocate enough MSI-X interrupts? Oh well.
2297 * This just means we'll go with either a single MSI
2298 * vector or fall back to legacy interrupts.
2299 */
2300 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2301 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2302 kfree(adapter->msix_entries);
2303 adapter->msix_entries = NULL;
2304 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2305 adapter->num_tx_queues = 1;
2306 adapter->num_rx_queues = 1;
2307 } else {
2308 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2309 adapter->num_msix_vectors = vectors;
2310 }
2311}
2312
2313static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2314{
2315 int nrq, ntq;
2316 int feature_mask = 0, rss_i, rss_m;
2317
2318 /* Number of supported queues */
2319 switch (adapter->hw.mac.type) {
2320 case ixgbe_mac_82598EB:
2321 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2322 rss_m = 0;
2323 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2324
2325 switch (adapter->flags & feature_mask) {
2326 case (IXGBE_FLAG_RSS_ENABLED):
2327 rss_m = 0xF;
2328 nrq = rss_i;
30eba97a 2329 ntq = rss_i;
021230d4
AV		 2330 break;
2331 case 0:
2332 default:
2333 rss_i = 0;
2334 rss_m = 0;
2335 nrq = 1;
2336 ntq = 1;
2337 break;
2338 }
2339
2340 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2341 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2342 break;
2343 default:
2344 nrq = 1;
2345 ntq = 1;
2346 break;
2347 }
2348
2349 adapter->num_rx_queues = nrq;
2350 adapter->num_tx_queues = ntq;
2351}
2352
2353/**
2354 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2355 * @adapter: board private structure to initialize
2356 *
2357 * Once we know the feature-set enabled for the device, we'll cache
2358 * the register offset the descriptor ring is assigned to.
2359 **/
2360static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2361{
2362 /* TODO: Remove all uses of the indices in the cases where multiple
2363 * features are OR'd together, if the feature set makes sense.
2364 */
2365 int feature_mask = 0, rss_i;
2366 int i, txr_idx, rxr_idx;
2367
2368 /* Number of supported queues */
2369 switch (adapter->hw.mac.type) {
2370 case ixgbe_mac_82598EB:
2371 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2372 txr_idx = 0;
2373 rxr_idx = 0;
2374 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2375 switch (adapter->flags & feature_mask) {
2376 case (IXGBE_FLAG_RSS_ENABLED):
2377 for (i = 0; i < adapter->num_rx_queues; i++)
2378 adapter->rx_ring[i].reg_idx = i;
2379 for (i = 0; i < adapter->num_tx_queues; i++)
2380 adapter->tx_ring[i].reg_idx = i;
2381 break;
2382 case 0:
2383 default:
2384 break;
2385 }
2386 break;
2387 default:
2388 break;
2389 }
2390}
2391
9a799d71
AK		 2392/**
2393 * ixgbe_alloc_queues - Allocate memory for all rings
2394 * @adapter: board private structure to initialize
2395 *
2396 * We allocate one ring per queue at run-time since we don't know the
2397 * number of queues at compile-time. The polling_netdev array is
2398 * intended for Multiqueue, but should work fine with a single queue.
2399 **/
2400static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2401{
2402 int i;
2403
2404 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2405 sizeof(struct ixgbe_ring), GFP_KERNEL);
2406 if (!adapter->tx_ring)
021230d4 2407 goto err_tx_ring_allocation;
9a799d71
AK		 2408
2409 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2410 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2411 if (!adapter->rx_ring)
2412 goto err_rx_ring_allocation;
9a799d71 2413
021230d4
AV		 2414 for (i = 0; i < adapter->num_tx_queues; i++) {
2415 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2416 adapter->tx_ring[i].queue_index = i;
2417 }
9a799d71 2418 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 2419 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 2420 adapter->rx_ring[i].queue_index = i;
2421 }
2422
2423 ixgbe_cache_ring_register(adapter);
2424
2425 return 0;
2426
2427err_rx_ring_allocation:
2428 kfree(adapter->tx_ring);
2429err_tx_ring_allocation:
2430 return -ENOMEM;
2431}
2432
2433/**
2434 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2435 * @adapter: board private structure to initialize
2436 *
2437 * Attempt to configure the interrupts using the best available
2438 * capabilities of the hardware and the kernel.
2439 **/
2440static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2441 *adapter)
2442{
2443 int err = 0;
2444 int vector, v_budget;
2445
2446 /*
2447 * It's easy to be greedy for MSI-X vectors, but it really
2448 * doesn't do us much good if we have a lot more vectors
2449 * than CPU's. So let's be conservative and only ask for
2450 * (roughly) twice the number of vectors as there are CPU's.
2451 */
2452 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2453 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2454
2455 /*
2456 * At the same time, hardware can only support a maximum of
2457 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2458 * we can easily reach upwards of 64 Rx descriptor queues and
2459 * 32 Tx queues. Thus, we cap it off in those rare cases where
2460 * the cpu count also exceeds our vector limit.
2461 */
2462 v_budget = min(v_budget, MAX_MSIX_COUNT);
2463
2464 /* A failure in MSI-X entry allocation isn't fatal, but it does
2465 * mean we disable MSI-X capabilities of the adapter. */
2466 adapter->msix_entries = kcalloc(v_budget,
2467 sizeof(struct msix_entry), GFP_KERNEL);
2468 if (!adapter->msix_entries) {
2469 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2470 ixgbe_set_num_queues(adapter);
2471 kfree(adapter->tx_ring);
2472 kfree(adapter->rx_ring);
2473 err = ixgbe_alloc_queues(adapter);
2474 if (err) {
2475 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2476 "for queues\n");
2477 goto out;
2478 }
2479
2480 goto try_msi;
2481 }
2482
2483 for (vector = 0; vector < v_budget; vector++)
2484 adapter->msix_entries[vector].entry = vector;
2485
2486 ixgbe_acquire_msix_vectors(adapter, v_budget);
2487
2488 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2489 goto out;
2490
2491try_msi:
2492 err = pci_enable_msi(adapter->pdev);
2493 if (!err) {
2494 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2495 } else {
2496 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2497 "falling back to legacy. Error: %d\n", err);
2498 /* reset err */
2499 err = 0;
2500 }
2501
2502out:
30eba97a 2503 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2504 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2505
2506 return err;
2507}
2508
2509static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2510{
2511 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2512 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2513 pci_disable_msix(adapter->pdev);
2514 kfree(adapter->msix_entries);
2515 adapter->msix_entries = NULL;
2516 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2517 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2518 pci_disable_msi(adapter->pdev);
2519 }
2520 return;
2521}
2522
2523/**
2524 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2525 * @adapter: board private structure to initialize
2526 *
2527 * We determine which interrupt scheme to use based on...
2528 * - Kernel support (MSI, MSI-X)
2529 * - which can be user-defined (via MODULE_PARAM)
2530 * - Hardware queue count (num_*_queues)
2531 * - defined by miscellaneous hardware support/features (RSS, etc.)
2532 **/
2533static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2534{
2535 int err;
2536
2537 /* Number of supported queues */
2538 ixgbe_set_num_queues(adapter);
2539
2540 err = ixgbe_alloc_queues(adapter);
2541 if (err) {
2542 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2543 goto err_alloc_queues;
2544 }
2545
2546 err = ixgbe_set_interrupt_capability(adapter);
2547 if (err) {
2548 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2549 goto err_set_interrupt;
9a799d71
AK		 2550 }
2551
021230d4
AV		 2552 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2553 "Tx Queue count = %u\n",
2554 (adapter->num_rx_queues > 1) ? "Enabled" :
2555 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2556
2557 set_bit(__IXGBE_DOWN, &adapter->state);
2558
9a799d71 2559 return 0;
021230d4
AV		 2560
2561err_set_interrupt:
2562 kfree(adapter->tx_ring);
2563 kfree(adapter->rx_ring);
2564err_alloc_queues:
2565 return err;
9a799d71
AK		 2566}
2567
2568/**
2569 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2570 * @adapter: board private structure to initialize
2571 *
2572 * ixgbe_sw_init initializes the Adapter private data structure.
2573 * Fields are initialized based on PCI device information and
2574 * OS network device settings (MTU size).
2575 **/
2576static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2577{
2578 struct ixgbe_hw *hw = &adapter->hw;
2579 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2580 unsigned int rss;
2581
2582 /* Set capability flags */
2583 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2584 adapter->ring_feature[RING_F_RSS].indices = rss;
2585 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71
AK		 2586
2587 /* default flow control settings */
2b9ade93
JB		 2588 hw->fc.original_type = ixgbe_fc_none;
2589 hw->fc.type = ixgbe_fc_none;
2590 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2591 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2592 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2593 hw->fc.send_xon = true;
9a799d71 2594
021230d4 2595 /* select 10G link by default */
9a799d71
AK		 2596 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2597 if (hw->mac.ops.reset(hw)) {
2598 dev_err(&pdev->dev, "HW Init failed\n");
2599 return -EIO;
2600 }
3957d63d
AK		 2601 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2602 false)) {
9a799d71
AK		 2603 dev_err(&pdev->dev, "Link Speed setup failed\n");
2604 return -EIO;
2605 }
2606
30efa5a3
JB		 2607 /* enable itr by default in dynamic mode */
2608 adapter->itr_setting = 1;
2609 adapter->eitr_param = 20000;
2610
2611 /* set defaults for eitr in MegaBytes */
2612 adapter->eitr_low = 10;
2613 adapter->eitr_high = 20;
2614
2615 /* set default ring sizes */
2616 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2617 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2618
9a799d71
AK		 2619 /* initialize eeprom parameters */
2620 if (ixgbe_init_eeprom(hw)) {
2621 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2622 return -EIO;
2623 }
2624
021230d4 2625 /* enable rx csum by default */
9a799d71
AK		 2626 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2627
9a799d71
AK		 2628 set_bit(__IXGBE_DOWN, &adapter->state);
2629
2630 return 0;
2631}
2632
2633/**
2634 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2635 * @adapter: board private structure
3a581073 2636 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2637 *
2638 * Return 0 on success, negative on failure
2639 **/
2640int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2641 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2642{
2643 struct pci_dev *pdev = adapter->pdev;
2644 int size;
2645
3a581073
JB		 2646 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2647 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2648 if (!tx_ring->tx_buffer_info)
2649 goto err;
3a581073 2650 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2651
2652 /* round up to nearest 4K */
e01c31a5
JB		 2653 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2654 sizeof(u32);
3a581073 2655 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2656
3a581073
JB		 2657 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2658 &tx_ring->dma);
e01c31a5
JB		 2659 if (!tx_ring->desc)
2660 goto err;
9a799d71 2661
3a581073
JB		 2662 tx_ring->next_to_use = 0;
2663 tx_ring->next_to_clean = 0;
2664 tx_ring->work_limit = tx_ring->count;
9a799d71 2665 return 0;
e01c31a5
JB		 2666
2667err:
2668 vfree(tx_ring->tx_buffer_info);
2669 tx_ring->tx_buffer_info = NULL;
2670 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2671 "descriptor ring\n");
2672 return -ENOMEM;
9a799d71
AK		 2673}
2674
2675/**
2676 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2677 * @adapter: board private structure
3a581073 2678 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2679 *
2680 * Returns 0 on success, negative on failure
2681 **/
2682int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3a581073 2683 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2684{
2685 struct pci_dev *pdev = adapter->pdev;
021230d4 2686 int size;
9a799d71 2687
177db6ff 2688 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2689 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2690 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2691 return -ENOMEM;
3a581073 2692 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2693
3a581073
JB		 2694 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2695 rx_ring->rx_buffer_info = vmalloc(size);
2696 if (!rx_ring->rx_buffer_info) {
9a799d71
AK		 2697 DPRINTK(PROBE, ERR,
2698 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2699 goto alloc_failed;
9a799d71 2700 }
3a581073 2701 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2702
9a799d71 2703 /* Round up to nearest 4K */
3a581073
JB		 2704 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2705 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2706
3a581073 2707 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2708
3a581073 2709 if (!rx_ring->desc) {
9a799d71
AK		 2710 DPRINTK(PROBE, ERR,
2711 "Memory allocation failed for the rx desc ring\n");
3a581073 2712 vfree(rx_ring->rx_buffer_info);
177db6ff 2713 goto alloc_failed;
9a799d71
AK		 2714 }
2715
3a581073
JB		 2716 rx_ring->next_to_clean = 0;
2717 rx_ring->next_to_use = 0;
9a799d71
AK		 2718
2719 return 0;
177db6ff
MC		 2720
2721alloc_failed:
3a581073
JB		 2722 vfree(rx_ring->lro_mgr.lro_arr);
2723 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2724 return -ENOMEM;
9a799d71
AK		 2725}
2726
2727/**
2728 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2729 * @adapter: board private structure
2730 * @tx_ring: Tx descriptor ring for a specific queue
2731 *
2732 * Free all transmit software resources
2733 **/
c431f97e
JB		 2734void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2735 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2736{
2737 struct pci_dev *pdev = adapter->pdev;
2738
2739 ixgbe_clean_tx_ring(adapter, tx_ring);
2740
2741 vfree(tx_ring->tx_buffer_info);
2742 tx_ring->tx_buffer_info = NULL;
2743
2744 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2745
2746 tx_ring->desc = NULL;
2747}
2748
2749/**
2750 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2751 * @adapter: board private structure
2752 *
2753 * Free all transmit software resources
2754 **/
2755static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2756{
2757 int i;
2758
2759 for (i = 0; i < adapter->num_tx_queues; i++)
2760 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2761}
2762
2763/**
c431f97e 2764 * ixgbe_ree_rx_resources - Free Rx Resources
9a799d71
AK		 2765 * @adapter: board private structure
2766 * @rx_ring: ring to clean the resources from
2767 *
2768 * Free all receive software resources
2769 **/
c431f97e
JB		 2770void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2771 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2772{
2773 struct pci_dev *pdev = adapter->pdev;
2774
177db6ff
MC		 2775 vfree(rx_ring->lro_mgr.lro_arr);
2776 rx_ring->lro_mgr.lro_arr = NULL;
2777
9a799d71
AK		 2778 ixgbe_clean_rx_ring(adapter, rx_ring);
2779
2780 vfree(rx_ring->rx_buffer_info);
2781 rx_ring->rx_buffer_info = NULL;
2782
2783 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2784
2785 rx_ring->desc = NULL;
2786}
2787
2788/**
2789 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2790 * @adapter: board private structure
2791 *
2792 * Free all receive software resources
2793 **/
2794static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2795{
2796 int i;
2797
2798 for (i = 0; i < adapter->num_rx_queues; i++)
2799 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2800}
2801
2802/**
021230d4 2803 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2804 * @adapter: board private structure
2805 *
2806 * If this function returns with an error, then it's possible one or
2807 * more of the rings is populated (while the rest are not). It is the
2808 * callers duty to clean those orphaned rings.
2809 *
2810 * Return 0 on success, negative on failure
2811 **/
2812static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2813{
2814 int i, err = 0;
2815
2816 for (i = 0; i < adapter->num_tx_queues; i++) {
2817 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2818 if (err) {
2819 DPRINTK(PROBE, ERR,
2820 "Allocation for Tx Queue %u failed\n", i);
2821 break;
2822 }
2823 }
2824
2825 return err;
2826}
2827
2828/**
021230d4 2829 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2830 * @adapter: board private structure
2831 *
2832 * If this function returns with an error, then it's possible one or
2833 * more of the rings is populated (while the rest are not). It is the
2834 * callers duty to clean those orphaned rings.
2835 *
2836 * Return 0 on success, negative on failure
2837 **/
2838
2839static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2840{
2841 int i, err = 0;
2842
2843 for (i = 0; i < adapter->num_rx_queues; i++) {
2844 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2845 if (err) {
2846 DPRINTK(PROBE, ERR,
2847 "Allocation for Rx Queue %u failed\n", i);
2848 break;
2849 }
2850 }
2851
2852 return err;
2853}
2854
2855/**
2856 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2857 * @netdev: network interface device structure
2858 * @new_mtu: new value for maximum frame size
2859 *
2860 * Returns 0 on success, negative on failure
2861 **/
2862static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2863{
2864 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2865 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2866
42c783c5
JB		 2867 /* MTU < 68 is an error and causes problems on some kernels */
2868 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 2869 return -EINVAL;
2870
021230d4
AV		 2871 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2872 netdev->mtu, new_mtu);
2873 /* must set new MTU before calling down or up */
9a799d71
AK		 2874 netdev->mtu = new_mtu;
2875
d4f80882
AV		 2876 if (netif_running(netdev))
2877 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2878
2879 return 0;
2880}
2881
2882/**
2883 * ixgbe_open - Called when a network interface is made active
2884 * @netdev: network interface device structure
2885 *
2886 * Returns 0 on success, negative value on failure
2887 *
2888 * The open entry point is called when a network interface is made
2889 * active by the system (IFF_UP). At this point all resources needed
2890 * for transmit and receive operations are allocated, the interrupt
2891 * handler is registered with the OS, the watchdog timer is started,
2892 * and the stack is notified that the interface is ready.
2893 **/
2894static int ixgbe_open(struct net_device *netdev)
2895{
2896 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2897 int err;
4bebfaa5
AK		 2898
2899 /* disallow open during test */
2900 if (test_bit(__IXGBE_TESTING, &adapter->state))
2901 return -EBUSY;
9a799d71 2902
9a799d71
AK		 2903 /* allocate transmit descriptors */
2904 err = ixgbe_setup_all_tx_resources(adapter);
2905 if (err)
2906 goto err_setup_tx;
2907
9a799d71
AK		 2908 /* allocate receive descriptors */
2909 err = ixgbe_setup_all_rx_resources(adapter);
2910 if (err)
2911 goto err_setup_rx;
2912
2913 ixgbe_configure(adapter);
2914
021230d4 2915 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2916 if (err)
2917 goto err_req_irq;
2918
9a799d71
AK		 2919 err = ixgbe_up_complete(adapter);
2920 if (err)
2921 goto err_up;
2922
d55b53ff
JK		 2923 netif_tx_start_all_queues(netdev);
2924
9a799d71
AK		 2925 return 0;
2926
2927err_up:
5eba3699 2928 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2929 ixgbe_free_irq(adapter);
2930err_req_irq:
2931 ixgbe_free_all_rx_resources(adapter);
2932err_setup_rx:
2933 ixgbe_free_all_tx_resources(adapter);
2934err_setup_tx:
2935 ixgbe_reset(adapter);
2936
2937 return err;
2938}
2939
2940/**
2941 * ixgbe_close - Disables a network interface
2942 * @netdev: network interface device structure
2943 *
2944 * Returns 0, this is not allowed to fail
2945 *
2946 * The close entry point is called when an interface is de-activated
2947 * by the OS. The hardware is still under the drivers control, but
2948 * needs to be disabled. A global MAC reset is issued to stop the
2949 * hardware, and all transmit and receive resources are freed.
2950 **/
2951static int ixgbe_close(struct net_device *netdev)
2952{
2953 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2954
2955 ixgbe_down(adapter);
2956 ixgbe_free_irq(adapter);
2957
2958 ixgbe_free_all_tx_resources(adapter);
2959 ixgbe_free_all_rx_resources(adapter);
2960
5eba3699 2961 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2962
2963 return 0;
2964}
2965
2966/**
2967 * ixgbe_update_stats - Update the board statistics counters.
2968 * @adapter: board private structure
2969 **/
2970void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2971{
2972 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2973 u64 total_mpc = 0;
2974 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2975
2976 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2977 for (i = 0; i < 8; i++) {
2978 /* for packet buffers not used, the register should read 0 */
2979 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2980 missed_rx += mpc;
2981 adapter->stats.mpc[i] += mpc;
2982 total_mpc += adapter->stats.mpc[i];
2983 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2984 }
2985 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2986 /* work around hardware counting issue */
2987 adapter->stats.gprc -= missed_rx;
2988
2989 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2990 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2991 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2992 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2993 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2994 adapter->stats.bprc += bprc;
2995 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2996 adapter->stats.mprc -= bprc;
2997 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2998 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2999 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3000 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3001 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3002 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3003 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3004 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3005 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3006 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3007 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3008 adapter->stats.lxontxc += lxon;
3009 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3010 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3011 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3012 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3013 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3014 /*
3015 * 82598 errata - tx of flow control packets is included in tx counters
3016 */
3017 xon_off_tot = lxon + lxoff;
3018 adapter->stats.gptc -= xon_off_tot;
3019 adapter->stats.mptc -= xon_off_tot;
3020 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3021 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3022 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3023 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3024 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3025 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3026 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3027 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3028 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3029 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3030 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3031 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3032 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3033
3034 /* Fill out the OS statistics structure */
9a799d71
AK		 3035 adapter->net_stats.multicast = adapter->stats.mprc;
3036
3037 /* Rx Errors */
3038 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3039 adapter->stats.rlec;
3040 adapter->net_stats.rx_dropped = 0;
3041 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3042 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3043 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3044}
3045
3046/**
3047 * ixgbe_watchdog - Timer Call-back
3048 * @data: pointer to adapter cast into an unsigned long
3049 **/
3050static void ixgbe_watchdog(unsigned long data)
3051{
3052 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3053 struct ixgbe_hw *hw = &adapter->hw;
3054
3055 /* Do the watchdog outside of interrupt context due to the lovely
3056 * delays that some of the newer hardware requires */
3057 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3058 /* Cause software interrupt to ensure rx rings are cleaned */
3059 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3060 u32 eics =
3061 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3062 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3063 } else {
3064 /* For legacy and MSI interrupts don't set any bits that
3065 * are enabled for EIAM, because this operation would
3066 * set *both* EIMS and EICS for any bit in EIAM */
3067 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3068 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3069 }
3070 /* Reset the timer */
3071 mod_timer(&adapter->watchdog_timer,
3072 round_jiffies(jiffies + 2 * HZ));
3073 }
9a799d71 3074
cf8280ee
JB		 3075 schedule_work(&adapter->watchdog_task);
3076}
3077
3078/**
3079 * ixgbe_watchdog_task - worker thread to bring link up
3080 * @work: pointer to work_struct containing our data
3081 **/
3082static void ixgbe_watchdog_task(struct work_struct *work)
3083{
3084 struct ixgbe_adapter *adapter = container_of(work,
3085 struct ixgbe_adapter,
3086 watchdog_task);
3087 struct net_device *netdev = adapter->netdev;
3088 struct ixgbe_hw *hw = &adapter->hw;
3089 u32 link_speed = adapter->link_speed;
3090 bool link_up = adapter->link_up;
3091
3092 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3093
3094 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3095 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3096 if (link_up ||
3097 time_after(jiffies, (adapter->link_check_timeout +
3098 IXGBE_TRY_LINK_TIMEOUT))) {
3099 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3100 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3101 }
3102 adapter->link_up = link_up;
3103 adapter->link_speed = link_speed;
3104 }
9a799d71
AK		 3105
3106 if (link_up) {
3107 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3108 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3109 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3110#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3111#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3112 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
cf8280ee
JB		 3113 "Flow Control: %s\n",
3114 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3115 "10 Gbps" :
3116 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3117 "1 Gbps" : "unknown speed")),
3118 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3119 (FLOW_RX ? "RX" :
3120 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3121
3122 netif_carrier_on(netdev);
fd2ea0a7 3123 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 3124 } else {
3125 /* Force detection of hung controller */
3126 adapter->detect_tx_hung = true;
3127 }
3128 } else {
cf8280ee
JB		 3129 adapter->link_up = false;
3130 adapter->link_speed = 0;
9a799d71
AK		 3131 if (netif_carrier_ok(netdev)) {
3132 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3133 netif_carrier_off(netdev);
fd2ea0a7 3134 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 3135 }
3136 }
3137
3138 ixgbe_update_stats(adapter);
cf8280ee 3139 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3140}
3141
9a799d71
AK		 3142static int ixgbe_tso(struct ixgbe_adapter *adapter,
3143 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3144 u32 tx_flags, u8 *hdr_len)
3145{
3146 struct ixgbe_adv_tx_context_desc *context_desc;
3147 unsigned int i;
3148 int err;
3149 struct ixgbe_tx_buffer *tx_buffer_info;
3150 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3151 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 3152
3153 if (skb_is_gso(skb)) {
3154 if (skb_header_cloned(skb)) {
3155 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3156 if (err)
3157 return err;
3158 }
3159 l4len = tcp_hdrlen(skb);
3160 *hdr_len += l4len;
3161
8327d000 3162 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3163 struct iphdr *iph = ip_hdr(skb);
3164 iph->tot_len = 0;
3165 iph->check = 0;
3166 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3167 iph->daddr, 0,
3168 IPPROTO_TCP,
3169 0);
3170 adapter->hw_tso_ctxt++;
3171 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3172 ipv6_hdr(skb)->payload_len = 0;
3173 tcp_hdr(skb)->check =
3174 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3175 &ipv6_hdr(skb)->daddr,
3176 0, IPPROTO_TCP, 0);
3177 adapter->hw_tso6_ctxt++;
3178 }
3179
3180 i = tx_ring->next_to_use;
3181
3182 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3183 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3184
3185 /* VLAN MACLEN IPLEN */
3186 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3187 vlan_macip_lens |=
3188 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3189 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3190 IXGBE_ADVTXD_MACLEN_SHIFT);
3191 *hdr_len += skb_network_offset(skb);
3192 vlan_macip_lens |=
3193 (skb_transport_header(skb) - skb_network_header(skb));
3194 *hdr_len +=
3195 (skb_transport_header(skb) - skb_network_header(skb));
3196 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3197 context_desc->seqnum_seed = 0;
3198
3199 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3200 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3201 IXGBE_ADVTXD_DTYP_CTXT);
3202
8327d000 3203 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3204 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3205 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3206 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3207
3208 /* MSS L4LEN IDX */
3209 mss_l4len_idx |=
3210 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3211 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3212 /* use index 1 for TSO */
3213 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3214 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3215
3216 tx_buffer_info->time_stamp = jiffies;
3217 tx_buffer_info->next_to_watch = i;
3218
3219 i++;
3220 if (i == tx_ring->count)
3221 i = 0;
3222 tx_ring->next_to_use = i;
3223
3224 return true;
3225 }
3226 return false;
3227}
3228
3229static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3230 struct ixgbe_ring *tx_ring,
3231 struct sk_buff *skb, u32 tx_flags)
3232{
3233 struct ixgbe_adv_tx_context_desc *context_desc;
3234 unsigned int i;
3235 struct ixgbe_tx_buffer *tx_buffer_info;
3236 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3237
3238 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3239 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3240 i = tx_ring->next_to_use;
3241 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3242 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3243
3244 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3245 vlan_macip_lens |=
3246 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3247 vlan_macip_lens |= (skb_network_offset(skb) <<
3248 IXGBE_ADVTXD_MACLEN_SHIFT);
3249 if (skb->ip_summed == CHECKSUM_PARTIAL)
3250 vlan_macip_lens |= (skb_transport_header(skb) -
3251 skb_network_header(skb));
3252
3253 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3254 context_desc->seqnum_seed = 0;
3255
3256 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3257 IXGBE_ADVTXD_DTYP_CTXT);
3258
3259 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3260 switch (skb->protocol) {
3261 case __constant_htons(ETH_P_IP):
9a799d71 3262 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3263 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3264 type_tucmd_mlhl |=
3265 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3266 break;
3267
3268 case __constant_htons(ETH_P_IPV6):
3269 /* XXX what about other V6 headers?? */
3270 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3271 type_tucmd_mlhl |=
3272 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3273 break;
9a799d71 3274
41825d71
AK		 3275 default:
3276 if (unlikely(net_ratelimit())) {
3277 DPRINTK(PROBE, WARNING,
3278 "partial checksum but proto=%x!\n",
3279 skb->protocol);
3280 }
3281 break;
3282 }
9a799d71
AK		 3283 }
3284
3285 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3286 /* use index zero for tx checksum offload */
9a799d71
AK		 3287 context_desc->mss_l4len_idx = 0;
3288
3289 tx_buffer_info->time_stamp = jiffies;
3290 tx_buffer_info->next_to_watch = i;
3291 adapter->hw_csum_tx_good++;
3292 i++;
3293 if (i == tx_ring->count)
3294 i = 0;
3295 tx_ring->next_to_use = i;
3296
3297 return true;
3298 }
3299 return false;
3300}
3301
3302static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3303 struct ixgbe_ring *tx_ring,
3304 struct sk_buff *skb, unsigned int first)
3305{
3306 struct ixgbe_tx_buffer *tx_buffer_info;
3307 unsigned int len = skb->len;
3308 unsigned int offset = 0, size, count = 0, i;
3309 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3310 unsigned int f;
3311
3312 len -= skb->data_len;
3313
3314 i = tx_ring->next_to_use;
3315
3316 while (len) {
3317 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3318 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3319
3320 tx_buffer_info->length = size;
3321 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3322 skb->data + offset,
3323 size, PCI_DMA_TODEVICE);
3324 tx_buffer_info->time_stamp = jiffies;
3325 tx_buffer_info->next_to_watch = i;
3326
3327 len -= size;
3328 offset += size;
3329 count++;
3330 i++;
3331 if (i == tx_ring->count)
3332 i = 0;
3333 }
3334
3335 for (f = 0; f < nr_frags; f++) {
3336 struct skb_frag_struct *frag;
3337
3338 frag = &skb_shinfo(skb)->frags[f];
3339 len = frag->size;
3340 offset = frag->page_offset;
3341
3342 while (len) {
3343 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3344 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3345
3346 tx_buffer_info->length = size;
3347 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3348 frag->page,
3349 offset,
3350 size, PCI_DMA_TODEVICE);
3351 tx_buffer_info->time_stamp = jiffies;
3352 tx_buffer_info->next_to_watch = i;
3353
3354 len -= size;
3355 offset += size;
3356 count++;
3357 i++;
3358 if (i == tx_ring->count)
3359 i = 0;
3360 }
3361 }
3362 if (i == 0)
3363 i = tx_ring->count - 1;
3364 else
3365 i = i - 1;
3366 tx_ring->tx_buffer_info[i].skb = skb;
3367 tx_ring->tx_buffer_info[first].next_to_watch = i;
3368
3369 return count;
3370}
3371
3372static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3373 struct ixgbe_ring *tx_ring,
3374 int tx_flags, int count, u32 paylen, u8 hdr_len)
3375{
3376 union ixgbe_adv_tx_desc *tx_desc = NULL;
3377 struct ixgbe_tx_buffer *tx_buffer_info;
3378 u32 olinfo_status = 0, cmd_type_len = 0;
3379 unsigned int i;
3380 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3381
3382 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3383
3384 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3385
3386 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3387 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3388
3389 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3390 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3391
3392 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3393 IXGBE_ADVTXD_POPTS_SHIFT;
3394
4eeae6fd
PW		 3395 /* use index 1 context for tso */
3396 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3397 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3398 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3399 IXGBE_ADVTXD_POPTS_SHIFT;
3400
3401 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3402 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3403 IXGBE_ADVTXD_POPTS_SHIFT;
3404
3405 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3406
3407 i = tx_ring->next_to_use;
3408 while (count--) {
3409 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3410 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3411 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3412 tx_desc->read.cmd_type_len =
3413 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3414 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3415
3416 i++;
3417 if (i == tx_ring->count)
3418 i = 0;
3419 }
3420
3421 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3422
3423 /*
3424 * Force memory writes to complete before letting h/w
3425 * know there are new descriptors to fetch. (Only
3426 * applicable for weak-ordered memory model archs,
3427 * such as IA-64).
3428 */
3429 wmb();
3430
3431 tx_ring->next_to_use = i;
3432 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3433}
3434
e092be60
AV		 3435static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3436 struct ixgbe_ring *tx_ring, int size)
3437{
3438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3439
30eba97a 3440 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3441 /* Herbert's original patch had:
3442 * smp_mb__after_netif_stop_queue();
3443 * but since that doesn't exist yet, just open code it. */
3444 smp_mb();
3445
3446 /* We need to check again in a case another CPU has just
3447 * made room available. */
3448 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3449 return -EBUSY;
3450
3451 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3452 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3453 ++adapter->restart_queue;
3454 return 0;
3455}
3456
3457static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3458 struct ixgbe_ring *tx_ring, int size)
3459{
3460 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3461 return 0;
3462 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3463}
3464
3465
9a799d71
AK		 3466static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3467{
3468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3469 struct ixgbe_ring *tx_ring;
3470 unsigned int len = skb->len;
3471 unsigned int first;
3472 unsigned int tx_flags = 0;
30eba97a
AV		 3473 u8 hdr_len = 0;
3474 int r_idx = 0, tso;
9a799d71
AK		 3475 unsigned int mss = 0;
3476 int count = 0;
3477 unsigned int f;
3478 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3479 len -= skb->data_len;
30eba97a 3480 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3481 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3482
9a799d71
AK		 3483
3484 if (skb->len <= 0) {
3485 dev_kfree_skb(skb);
3486 return NETDEV_TX_OK;
3487 }
3488 mss = skb_shinfo(skb)->gso_size;
3489
3490 if (mss)
3491 count++;
3492 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3493 count++;
3494
3495 count += TXD_USE_COUNT(len);
3496 for (f = 0; f < nr_frags; f++)
3497 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3498
e092be60 3499 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3500 adapter->tx_busy++;
9a799d71
AK		 3501 return NETDEV_TX_BUSY;
3502 }
9a799d71
AK		 3503 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3504 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3505 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3506 }
3507
8327d000 3508 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3509 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3510 first = tx_ring->next_to_use;
3511 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3512 if (tso < 0) {
3513 dev_kfree_skb_any(skb);
3514 return NETDEV_TX_OK;
3515 }
3516
3517 if (tso)
3518 tx_flags |= IXGBE_TX_FLAGS_TSO;
3519 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3520 (skb->ip_summed == CHECKSUM_PARTIAL))
3521 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3522
3523 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3524 ixgbe_tx_map(adapter, tx_ring, skb, first),
3525 skb->len, hdr_len);
3526
3527 netdev->trans_start = jiffies;
3528
e092be60 3529 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3530
3531 return NETDEV_TX_OK;
3532}
3533
3534/**
3535 * ixgbe_get_stats - Get System Network Statistics
3536 * @netdev: network interface device structure
3537 *
3538 * Returns the address of the device statistics structure.
3539 * The statistics are actually updated from the timer callback.
3540 **/
3541static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3542{
3543 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3544
3545 /* only return the current stats */
3546 return &adapter->net_stats;
3547}
3548
3549/**
3550 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3551 * @netdev: network interface device structure
3552 * @p: pointer to an address structure
3553 *
3554 * Returns 0 on success, negative on failure
3555 **/
3556static int ixgbe_set_mac(struct net_device *netdev, void *p)
3557{
3558 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3559 struct sockaddr *addr = p;
3560
3561 if (!is_valid_ether_addr(addr->sa_data))
3562 return -EADDRNOTAVAIL;
3563
3564 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3565 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3566
3567 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3568
3569 return 0;
3570}
3571
3572#ifdef CONFIG_NET_POLL_CONTROLLER
3573/*
3574 * Polling 'interrupt' - used by things like netconsole to send skbs
3575 * without having to re-enable interrupts. It's not called while
3576 * the interrupt routine is executing.
3577 */
3578static void ixgbe_netpoll(struct net_device *netdev)
3579{
3580 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3581
3582 disable_irq(adapter->pdev->irq);
3583 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3584 ixgbe_intr(adapter->pdev->irq, netdev);
3585 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3586 enable_irq(adapter->pdev->irq);
3587}
3588#endif
3589
021230d4
AV		 3590/**
3591 * ixgbe_napi_add_all - prep napi structs for use
3592 * @adapter: private struct
3593 * helper function to napi_add each possible q_vector->napi
3594 */
3595static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3596{
3597 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3598 int (*poll)(struct napi_struct *, int);
3599
3600 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3601 poll = &ixgbe_clean_rxonly;
3602 } else {
3603 poll = &ixgbe_poll;
3604 /* only one q_vector for legacy modes */
3605 q_vectors = 1;
3606 }
3607
3608 for (i = 0; i < q_vectors; i++) {
3609 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3610 netif_napi_add(adapter->netdev, &q_vector->napi,
3611 (*poll), 64);
3612 }
3613}
3614
9a799d71
AK		 3615/**
3616 * ixgbe_probe - Device Initialization Routine
3617 * @pdev: PCI device information struct
3618 * @ent: entry in ixgbe_pci_tbl
3619 *
3620 * Returns 0 on success, negative on failure
3621 *
3622 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3623 * The OS initialization, configuring of the adapter private structure,
3624 * and a hardware reset occur.
3625 **/
3626static int __devinit ixgbe_probe(struct pci_dev *pdev,
3627 const struct pci_device_id *ent)
3628{
3629 struct net_device *netdev;
3630 struct ixgbe_adapter *adapter = NULL;
3631 struct ixgbe_hw *hw;
3632 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3633 static int cards_found;
3634 int i, err, pci_using_dac;
3635 u16 link_status, link_speed, link_width;
3636 u32 part_num;
3637
3638 err = pci_enable_device(pdev);
3639 if (err)
3640 return err;
3641
3642 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3643 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3644 pci_using_dac = 1;
3645 } else {
3646 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3647 if (err) {
3648 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3649 if (err) {
3650 dev_err(&pdev->dev, "No usable DMA "
3651 "configuration, aborting\n");
3652 goto err_dma;
3653 }
3654 }
3655 pci_using_dac = 0;
3656 }
3657
3658 err = pci_request_regions(pdev, ixgbe_driver_name);
3659 if (err) {
3660 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3661 goto err_pci_reg;
3662 }
3663
3664 pci_set_master(pdev);
fb3b27bc 3665 pci_save_state(pdev);
9a799d71 3666
30eba97a 3667 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3668 if (!netdev) {
3669 err = -ENOMEM;
3670 goto err_alloc_etherdev;
3671 }
3672
9a799d71
AK		 3673 SET_NETDEV_DEV(netdev, &pdev->dev);
3674
3675 pci_set_drvdata(pdev, netdev);
3676 adapter = netdev_priv(netdev);
3677
3678 adapter->netdev = netdev;
3679 adapter->pdev = pdev;
3680 hw = &adapter->hw;
3681 hw->back = adapter;
3682 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3683
05857980
JK		 3684 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3685 pci_resource_len(pdev, 0));
9a799d71
AK		 3686 if (!hw->hw_addr) {
3687 err = -EIO;
3688 goto err_ioremap;
3689 }
3690
3691 for (i = 1; i <= 5; i++) {
3692 if (pci_resource_len(pdev, i) == 0)
3693 continue;
3694 }
3695
3696 netdev->open = &ixgbe_open;
3697 netdev->stop = &ixgbe_close;
3698 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3699 netdev->get_stats = &ixgbe_get_stats;
2c5645cf
CL		 3700 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3701 netdev->set_multicast_list = &ixgbe_set_rx_mode;
9a799d71
AK		 3702 netdev->set_mac_address = &ixgbe_set_mac;
3703 netdev->change_mtu = &ixgbe_change_mtu;
3704 ixgbe_set_ethtool_ops(netdev);
3705 netdev->tx_timeout = &ixgbe_tx_timeout;
3706 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3707 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3708 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3709 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3710#ifdef CONFIG_NET_POLL_CONTROLLER
3711 netdev->poll_controller = ixgbe_netpoll;
3712#endif
3713 strcpy(netdev->name, pci_name(pdev));
3714
9a799d71
AK		 3715 adapter->bd_number = cards_found;
3716
3717 /* PCI config space info */
3718 hw->vendor_id = pdev->vendor;
3719 hw->device_id = pdev->device;
3720 hw->revision_id = pdev->revision;
3721 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3722 hw->subsystem_device_id = pdev->subsystem_device;
3723
3724 /* Setup hw api */
3725 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3726 hw->mac.type = ii->mac;
9a799d71
AK		 3727
3728 err = ii->get_invariants(hw);
3729 if (err)
3730 goto err_hw_init;
3731
3732 /* setup the private structure */
3733 err = ixgbe_sw_init(adapter);
3734 if (err)
3735 goto err_sw_init;
3736
3737 netdev->features = NETIF_F_SG |
22f32b7a 3738 NETIF_F_IP_CSUM |
9a799d71
AK		 3739 NETIF_F_HW_VLAN_TX |
3740 NETIF_F_HW_VLAN_RX |
3741 NETIF_F_HW_VLAN_FILTER;
3742
e9990a9c 3743 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 3744 netdev->features |= NETIF_F_TSO;
9a799d71 3745 netdev->features |= NETIF_F_TSO6;
e9990a9c 3746 netdev->features |= NETIF_F_LRO;
ad31c402
JK		 3747
3748 netdev->vlan_features |= NETIF_F_TSO;
3749 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 3750 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 3751 netdev->vlan_features |= NETIF_F_SG;
3752
9a799d71
AK		 3753 if (pci_using_dac)
3754 netdev->features |= NETIF_F_HIGHDMA;
3755
9a799d71
AK		 3756 /* make sure the EEPROM is good */
3757 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3758 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3759 err = -EIO;
3760 goto err_eeprom;
3761 }
3762
3763 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3764 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3765
3766 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3767 err = -EIO;
3768 goto err_eeprom;
3769 }
3770
3771 init_timer(&adapter->watchdog_timer);
3772 adapter->watchdog_timer.function = &ixgbe_watchdog;
3773 adapter->watchdog_timer.data = (unsigned long)adapter;
3774
3775 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 3776 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 3777
021230d4
AV		 3778 err = ixgbe_init_interrupt_scheme(adapter);
3779 if (err)
3780 goto err_sw_init;
9a799d71
AK		 3781
3782 /* print bus type/speed/width info */
3783 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3784 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3785 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3786 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3787 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3788 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3789 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3790 "Unknown"),
3791 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3792 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3793 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3794 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3795 "Unknown"),
3796 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3797 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3798 ixgbe_read_part_num(hw, &part_num);
3799 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3800 hw->mac.type, hw->phy.type,
3801 (part_num >> 8), (part_num & 0xff));
3802
0c254d86
AK		 3803 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3804 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3805 "this card is not sufficient for optimal "
3806 "performance.\n");
3807 dev_warn(&pdev->dev, "For optimal performance a x8 "
3808 "PCI-Express slot is required.\n");
3809 }
3810
9a799d71
AK		 3811 /* reset the hardware with the new settings */
3812 ixgbe_start_hw(hw);
3813
3814 netif_carrier_off(netdev);
fd2ea0a7 3815 netif_tx_stop_all_queues(netdev);
9a799d71 3816
021230d4
AV		 3817 ixgbe_napi_add_all(adapter);
3818
9a799d71
AK		 3819 strcpy(netdev->name, "eth%d");
3820 err = register_netdev(netdev);
3821 if (err)
3822 goto err_register;
3823
a1f96ee7 3824#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
652f093f 3825 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3826 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3827 /* always use CB2 mode, difference is masked
3828 * in the CB driver */
3829 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3830 ixgbe_setup_dca(adapter);
3831 }
3832#endif
9a799d71
AK		 3833
3834 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3835 cards_found++;
3836 return 0;
3837
3838err_register:
5eba3699 3839 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3840err_hw_init:
3841err_sw_init:
021230d4 3842 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3843err_eeprom:
3844 iounmap(hw->hw_addr);
3845err_ioremap:
3846 free_netdev(netdev);
3847err_alloc_etherdev:
3848 pci_release_regions(pdev);
3849err_pci_reg:
3850err_dma:
3851 pci_disable_device(pdev);
3852 return err;
3853}
3854
3855/**
3856 * ixgbe_remove - Device Removal Routine
3857 * @pdev: PCI device information struct
3858 *
3859 * ixgbe_remove is called by the PCI subsystem to alert the driver
3860 * that it should release a PCI device. The could be caused by a
3861 * Hot-Plug event, or because the driver is going to be removed from
3862 * memory.
3863 **/
3864static void __devexit ixgbe_remove(struct pci_dev *pdev)
3865{
3866 struct net_device *netdev = pci_get_drvdata(pdev);
3867 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3868
3869 set_bit(__IXGBE_DOWN, &adapter->state);
3870 del_timer_sync(&adapter->watchdog_timer);
3871
3872 flush_scheduled_work();
3873
a1f96ee7 3874#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 3875 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3876 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3877 dca_remove_requester(&pdev->dev);
3878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3879 }
3880
3881#endif
9a799d71
AK		 3882 unregister_netdev(netdev);
3883
021230d4 3884 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3885
021230d4 3886 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3887
3888 iounmap(adapter->hw.hw_addr);
3889 pci_release_regions(pdev);
3890
021230d4
AV		 3891 DPRINTK(PROBE, INFO, "complete\n");
3892 kfree(adapter->tx_ring);
3893 kfree(adapter->rx_ring);
3894
9a799d71
AK		 3895 free_netdev(netdev);
3896
3897 pci_disable_device(pdev);
3898}
3899
3900/**
3901 * ixgbe_io_error_detected - called when PCI error is detected
3902 * @pdev: Pointer to PCI device
3903 * @state: The current pci connection state
3904 *
3905 * This function is called after a PCI bus error affecting
3906 * this device has been detected.
3907 */
3908static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3909 pci_channel_state_t state)
3910{
3911 struct net_device *netdev = pci_get_drvdata(pdev);
3912 struct ixgbe_adapter *adapter = netdev->priv;
3913
3914 netif_device_detach(netdev);
3915
3916 if (netif_running(netdev))
3917 ixgbe_down(adapter);
3918 pci_disable_device(pdev);
3919
3920 /* Request a slot slot reset. */
3921 return PCI_ERS_RESULT_NEED_RESET;
3922}
3923
3924/**
3925 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3926 * @pdev: Pointer to PCI device
3927 *
3928 * Restart the card from scratch, as if from a cold-boot.
3929 */
3930static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3931{
3932 struct net_device *netdev = pci_get_drvdata(pdev);
3933 struct ixgbe_adapter *adapter = netdev->priv;
3934
3935 if (pci_enable_device(pdev)) {
3936 DPRINTK(PROBE, ERR,
3937 "Cannot re-enable PCI device after reset.\n");
3938 return PCI_ERS_RESULT_DISCONNECT;
3939 }
3940 pci_set_master(pdev);
fb3b27bc 3941 pci_restore_state(pdev);
9a799d71
AK		 3942
3943 pci_enable_wake(pdev, PCI_D3hot, 0);
3944 pci_enable_wake(pdev, PCI_D3cold, 0);
3945
3946 ixgbe_reset(adapter);
3947
3948 return PCI_ERS_RESULT_RECOVERED;
3949}
3950
3951/**
3952 * ixgbe_io_resume - called when traffic can start flowing again.
3953 * @pdev: Pointer to PCI device
3954 *
3955 * This callback is called when the error recovery driver tells us that
3956 * its OK to resume normal operation.
3957 */
3958static void ixgbe_io_resume(struct pci_dev *pdev)
3959{
3960 struct net_device *netdev = pci_get_drvdata(pdev);
3961 struct ixgbe_adapter *adapter = netdev->priv;
3962
3963 if (netif_running(netdev)) {
3964 if (ixgbe_up(adapter)) {
3965 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3966 return;
3967 }
3968 }
3969
3970 netif_device_attach(netdev);
3971
3972}
3973
3974static struct pci_error_handlers ixgbe_err_handler = {
3975 .error_detected = ixgbe_io_error_detected,
3976 .slot_reset = ixgbe_io_slot_reset,
3977 .resume = ixgbe_io_resume,
3978};
3979
3980static struct pci_driver ixgbe_driver = {
3981 .name = ixgbe_driver_name,
3982 .id_table = ixgbe_pci_tbl,
3983 .probe = ixgbe_probe,
3984 .remove = __devexit_p(ixgbe_remove),
3985#ifdef CONFIG_PM
3986 .suspend = ixgbe_suspend,
3987 .resume = ixgbe_resume,
3988#endif
3989 .shutdown = ixgbe_shutdown,
3990 .err_handler = &ixgbe_err_handler
3991};
3992
3993/**
3994 * ixgbe_init_module - Driver Registration Routine
3995 *
3996 * ixgbe_init_module is the first routine called when the driver is
3997 * loaded. All it does is register with the PCI subsystem.
3998 **/
3999static int __init ixgbe_init_module(void)
4000{
4001 int ret;
4002 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4003 ixgbe_driver_string, ixgbe_driver_version);
4004
4005 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4006
a1f96ee7 4007#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4008 dca_register_notify(&dca_notifier);
4009
4010#endif
9a799d71
AK		 4011 ret = pci_register_driver(&ixgbe_driver);
4012 return ret;
4013}
4014module_init(ixgbe_init_module);
4015
4016/**
4017 * ixgbe_exit_module - Driver Exit Cleanup Routine
4018 *
4019 * ixgbe_exit_module is called just before the driver is removed
4020 * from memory.
4021 **/
4022static void __exit ixgbe_exit_module(void)
4023{
a1f96ee7 4024#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4025 dca_unregister_notify(&dca_notifier);
4026#endif
9a799d71
AK		 4027 pci_unregister_driver(&ixgbe_driver);
4028}
bd0362dd 4029
a1f96ee7 4030#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4031static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4032 void *p)
4033{
4034 int ret_val;
4035
4036 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4037 __ixgbe_notify_dca);
4038
4039 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4040}
96b0e0f6 4041#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
bd0362dd 4042
9a799d71
AK		 4043module_exit(ixgbe_exit_module);
4044
4045/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree