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ixgbe: feature - driver to default with FC on.
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
e8e26350 50#define DRV_VERSION "2.0.8-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71
AK		 189{
190 if (tx_buffer_info->dma) {
e01c31a5 191 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 192 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 193 tx_buffer_info->dma = 0;
194 }
195 if (tx_buffer_info->skb) {
196 dev_kfree_skb_any(tx_buffer_info->skb);
197 tx_buffer_info->skb = NULL;
198 }
199 /* tx_buffer_info must be completely set up in the transmit path */
200}
201
202static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 203 struct ixgbe_ring *tx_ring,
204 unsigned int eop)
9a799d71 205{
e01c31a5
JB		 206 struct ixgbe_hw *hw = &adapter->hw;
207 u32 head, tail;
208
9a799d71 209 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 210 * check with the clearing of time_stamp and movement of eop */
211 head = IXGBE_READ_REG(hw, tx_ring->head);
212 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 213 adapter->detect_tx_hung = false;
e01c31a5
JB		 214 if ((head != tail) &&
215 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 216 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
217 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
218 /* detected Tx unit hang */
e01c31a5
JB		 219 union ixgbe_adv_tx_desc *tx_desc;
220 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 221 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 222 " Tx Queue <%d>\n"
223 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 224 " next_to_use <%x>\n"
225 " next_to_clean <%x>\n"
226 "tx_buffer_info[next_to_clean]\n"
227 " time_stamp <%lx>\n"
e01c31a5
JB		 228 " jiffies <%lx>\n",
229 tx_ring->queue_index,
230 head, tail,
231 tx_ring->next_to_use, eop,
232 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 233 return true;
234 }
235
236 return false;
237}
238
b4617240
PW		 239#define IXGBE_MAX_TXD_PWR 14
240#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 241
242/* Tx Descriptors needed, worst case */
243#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
244 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
245#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 246 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 247
e01c31a5
JB		 248static void ixgbe_tx_timeout(struct net_device *netdev);
249
9a799d71
AK		 250/**
251 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
252 * @adapter: board private structure
e01c31a5 253 * @tx_ring: tx ring to clean
9a1a69ad
JB		 254 *
255 * returns true if transmit work is done
9a799d71
AK		 256 **/
257static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 258 struct ixgbe_ring *tx_ring)
9a799d71 259{
e01c31a5 260 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 261 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
262 struct ixgbe_tx_buffer *tx_buffer_info;
263 unsigned int i, eop, count = 0;
e01c31a5 264 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 265
266 i = tx_ring->next_to_clean;
12207e49
PWJ		 267 eop = tx_ring->tx_buffer_info[i].next_to_watch;
268 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
269
270 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 271 (count < tx_ring->work_limit)) {
12207e49
PWJ		 272 bool cleaned = false;
273 for ( ; !cleaned; count++) {
274 struct sk_buff *skb;
9a799d71
AK		 275 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
276 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 277 cleaned = (i == eop);
e01c31a5 278 skb = tx_buffer_info->skb;
9a799d71 279
12207e49 280 if (cleaned && skb) {
e092be60 281 unsigned int segs, bytecount;
e01c31a5
JB		 282
283 /* gso_segs is currently only valid for tcp */
e092be60
AV		 284 segs = skb_shinfo(skb)->gso_segs ?: 1;
285 /* multiply data chunks by size of headers */
286 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 287 skb->len;
288 total_packets += segs;
289 total_bytes += bytecount;
e092be60 290 }
e01c31a5 291
9a799d71 292 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 293 tx_buffer_info);
9a799d71 294
12207e49
PWJ		 295 tx_desc->wb.status = 0;
296
9a799d71
AK		 297 i++;
298 if (i == tx_ring->count)
299 i = 0;
e01c31a5 300 }
12207e49
PWJ		 301
302 eop = tx_ring->tx_buffer_info[i].next_to_watch;
303 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
304 }
305
9a799d71
AK		 306 tx_ring->next_to_clean = i;
307
e092be60 308#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 309 if (unlikely(count && netif_carrier_ok(netdev) &&
310 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 311 /* Make sure that anybody stopping the queue after this
312 * sees the new next_to_clean.
313 */
314 smp_mb();
30eba97a
AV		 315 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
316 !test_bit(__IXGBE_DOWN, &adapter->state)) {
317 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 318 ++adapter->restart_queue;
30eba97a 319 }
e092be60 320 }
9a799d71 321
e01c31a5
JB		 322 if (adapter->detect_tx_hung) {
323 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
324 /* schedule immediate reset if we believe we hung */
325 DPRINTK(PROBE, INFO,
326 "tx hang %d detected, resetting adapter\n",
327 adapter->tx_timeout_count + 1);
328 ixgbe_tx_timeout(adapter->netdev);
329 }
330 }
9a799d71 331
e01c31a5 332 /* re-arm the interrupt */
9a1a69ad 333 if (count >= tx_ring->work_limit)
e01c31a5 334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 335
e01c31a5
JB		 336 tx_ring->total_bytes += total_bytes;
337 tx_ring->total_packets += total_packets;
e01c31a5 338 tx_ring->stats.packets += total_packets;
12207e49 339 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 340 adapter->net_stats.tx_bytes += total_bytes;
341 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 342 return (count < tx_ring->work_limit);
9a799d71
AK		 343}
344
5dd2d332 345#ifdef CONFIG_IXGBE_DCA
bd0362dd 346static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 347 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 348{
349 u32 rxctrl;
350 int cpu = get_cpu();
3a581073 351 int q = rx_ring - adapter->rx_ring;
bd0362dd 352
3a581073 353 if (rx_ring->cpu != cpu) {
bd0362dd 354 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 355 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
356 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
357 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
358 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
359 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
360 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
361 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
362 }
bd0362dd
JC		 363 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
364 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 365 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
366 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 367 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 369 rx_ring->cpu = cpu;
bd0362dd
JC		 370 }
371 put_cpu();
372}
373
374static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 375 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 376{
377 u32 txctrl;
378 int cpu = get_cpu();
3a581073 379 int q = tx_ring - adapter->tx_ring;
bd0362dd 380
3a581073 381 if (tx_ring->cpu != cpu) {
bd0362dd 382 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 383 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
384 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
385 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
386 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
387 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
388 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
389 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
390 }
bd0362dd
JC		 391 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 393 tx_ring->cpu = cpu;
bd0362dd
JC		 394 }
395 put_cpu();
396}
397
398static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
399{
400 int i;
401
402 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
403 return;
404
405 for (i = 0; i < adapter->num_tx_queues; i++) {
406 adapter->tx_ring[i].cpu = -1;
407 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
408 }
409 for (i = 0; i < adapter->num_rx_queues; i++) {
410 adapter->rx_ring[i].cpu = -1;
411 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
412 }
413}
414
415static int __ixgbe_notify_dca(struct device *dev, void *data)
416{
417 struct net_device *netdev = dev_get_drvdata(dev);
418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
419 unsigned long event = *(unsigned long *)data;
420
421 switch (event) {
422 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 423 /* if we're already enabled, don't do it again */
424 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
425 break;
bd0362dd
JC		 426 /* Always use CB2 mode, difference is masked
427 * in the CB driver. */
428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 429 if (dca_add_requester(dev) == 0) {
96b0e0f6 430 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 431 ixgbe_setup_dca(adapter);
432 break;
433 }
434 /* Fall Through since DCA is disabled. */
435 case DCA_PROVIDER_REMOVE:
436 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
437 dca_remove_requester(dev);
438 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
440 }
441 break;
442 }
443
652f093f 444 return 0;
bd0362dd
JC		 445}
446
5dd2d332 447#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 448/**
449 * ixgbe_receive_skb - Send a completed packet up the stack
450 * @adapter: board private structure
451 * @skb: packet to send up
177db6ff
MC		 452 * @status: hardware indication of status of receive
453 * @rx_ring: rx descriptor ring (for a specific queue) to setup
454 * @rx_desc: rx descriptor
9a799d71 455 **/
78b6f4ce 456static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 457 struct sk_buff *skb, u8 status,
177db6ff 458 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 459{
78b6f4ce
HX		 460 struct ixgbe_adapter *adapter = q_vector->adapter;
461 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 462 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
463 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 464
0c8dfc83 465 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
78b6f4ce 466 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 467 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 468 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 469 else
78b6f4ce 470 napi_gro_receive(napi, skb);
177db6ff
MC		 471 } else {
472 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 473 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 474 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
475 else
476 netif_receive_skb(skb);
477 } else {
2f90b865 478 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 479 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
480 else
481 netif_rx(skb);
482 }
9a799d71
AK		 483 }
484}
485
e59bd25d
AV		 486/**
487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
488 * @adapter: address of board private structure
489 * @status_err: hardware indication of status of receive
490 * @skb: skb currently being received and modified
491 **/
9a799d71 492static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 493 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 494{
495 skb->ip_summed = CHECKSUM_NONE;
496
712744be
JB		 497 /* Rx csum disabled */
498 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 499 return;
e59bd25d
AV		 500
501 /* if IP and error */
502 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
503 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 504 adapter->hw_csum_rx_error++;
505 return;
506 }
e59bd25d
AV		 507
508 if (!(status_err & IXGBE_RXD_STAT_L4CS))
509 return;
510
511 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
512 adapter->hw_csum_rx_error++;
513 return;
514 }
515
9a799d71 516 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 517 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 518 adapter->hw_csum_rx_good++;
519}
520
e8e26350
PW		 521static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
522 struct ixgbe_ring *rx_ring, u32 val)
523{
524 /*
525 * Force memory writes to complete before letting h/w
526 * know there are new descriptors to fetch. (Only
527 * applicable for weak-ordered memory model archs,
528 * such as IA-64).
529 */
530 wmb();
531 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
532}
533
9a799d71
AK		 534/**
535 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
536 * @adapter: address of board private structure
537 **/
538static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 539 struct ixgbe_ring *rx_ring,
540 int cleaned_count)
9a799d71 541{
9a799d71
AK		 542 struct pci_dev *pdev = adapter->pdev;
543 union ixgbe_adv_rx_desc *rx_desc;
3a581073 544 struct ixgbe_rx_buffer *bi;
9a799d71 545 unsigned int i;
e8e26350 546 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 547
548 i = rx_ring->next_to_use;
3a581073 549 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 550
551 while (cleaned_count--) {
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553
762f4c57 554 if (!bi->page_dma &&
3a581073 555 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 556 if (!bi->page) {
762f4c57
JB		 557 bi->page = alloc_page(GFP_ATOMIC);
558 if (!bi->page) {
559 adapter->alloc_rx_page_failed++;
560 goto no_buffers;
561 }
562 bi->page_offset = 0;
563 } else {
564 /* use a half page if we're re-using */
565 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 566 }
762f4c57
JB		 567
568 bi->page_dma = pci_map_page(pdev, bi->page,
569 bi->page_offset,
570 (PAGE_SIZE / 2),
571 PCI_DMA_FROMDEVICE);
9a799d71
AK		 572 }
573
3a581073 574 if (!bi->skb) {
5ecc3614 575 struct sk_buff *skb;
e8e26350 576 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 577
578 if (!skb) {
579 adapter->alloc_rx_buff_failed++;
580 goto no_buffers;
581 }
582
583 /*
584 * Make buffer alignment 2 beyond a 16 byte boundary
585 * this will result in a 16 byte aligned IP header after
586 * the 14 byte MAC header is removed
587 */
588 skb_reserve(skb, NET_IP_ALIGN);
589
3a581073 590 bi->skb = skb;
e8e26350 591 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 592 PCI_DMA_FROMDEVICE);
9a799d71
AK		 593 }
594 /* Refresh the desc even if buffer_addrs didn't change because
595 * each write-back erases this info. */
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 597 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
598 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 599 } else {
3a581073 600 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 601 }
602
603 i++;
604 if (i == rx_ring->count)
605 i = 0;
3a581073 606 bi = &rx_ring->rx_buffer_info[i];
9a799d71 607 }
7c6e0a43 608
9a799d71
AK		 609no_buffers:
610 if (rx_ring->next_to_use != i) {
611 rx_ring->next_to_use = i;
612 if (i-- == 0)
613 i = (rx_ring->count - 1);
614
e8e26350 615 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 616 }
617}
618
7c6e0a43
JB		 619static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
620{
621 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
622}
623
624static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
625{
626 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
627}
628
78b6f4ce 629static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 630 struct ixgbe_ring *rx_ring,
631 int *work_done, int work_to_do)
9a799d71 632{
78b6f4ce 633 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 634 struct pci_dev *pdev = adapter->pdev;
635 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
636 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
637 struct sk_buff *skb;
638 unsigned int i;
7c6e0a43 639 u32 len, staterr;
177db6ff
MC		 640 u16 hdr_info;
641 bool cleaned = false;
9a799d71 642 int cleaned_count = 0;
d2f4fbe2 643 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 644
645 i = rx_ring->next_to_clean;
9a799d71
AK		 646 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
647 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
648 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 649
650 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 651 u32 upper_len = 0;
9a799d71
AK		 652 if (*work_done >= work_to_do)
653 break;
654 (*work_done)++;
655
656 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 657 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
658 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 659 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 660 if (hdr_info & IXGBE_RXDADV_SPH)
661 adapter->rx_hdr_split++;
662 if (len > IXGBE_RX_HDR_SIZE)
663 len = IXGBE_RX_HDR_SIZE;
664 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 665 } else {
9a799d71 666 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 667 }
9a799d71
AK		 668
669 cleaned = true;
670 skb = rx_buffer_info->skb;
671 prefetch(skb->data - NET_IP_ALIGN);
672 rx_buffer_info->skb = NULL;
673
674 if (len && !skb_shinfo(skb)->nr_frags) {
675 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 676 rx_ring->rx_buf_len,
b4617240 677 PCI_DMA_FROMDEVICE);
9a799d71
AK		 678 skb_put(skb, len);
679 }
680
681 if (upper_len) {
682 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 683 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 684 rx_buffer_info->page_dma = 0;
685 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 686 rx_buffer_info->page,
687 rx_buffer_info->page_offset,
688 upper_len);
689
690 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
691 (page_count(rx_buffer_info->page) != 1))
692 rx_buffer_info->page = NULL;
693 else
694 get_page(rx_buffer_info->page);
9a799d71
AK		 695
696 skb->len += upper_len;
697 skb->data_len += upper_len;
698 skb->truesize += upper_len;
699 }
700
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 next_buffer = &rx_ring->rx_buffer_info[i];
705
706 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
707 prefetch(next_rxd);
708
709 cleaned_count++;
710 if (staterr & IXGBE_RXD_STAT_EOP) {
711 rx_ring->stats.packets++;
712 rx_ring->stats.bytes += skb->len;
713 } else {
714 rx_buffer_info->skb = next_buffer->skb;
715 rx_buffer_info->dma = next_buffer->dma;
716 next_buffer->skb = skb;
762f4c57 717 next_buffer->dma = 0;
9a799d71
AK		 718 adapter->non_eop_descs++;
719 goto next_desc;
720 }
721
722 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
723 dev_kfree_skb_irq(skb);
724 goto next_desc;
725 }
726
727 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 728
729 /* probably a little skewed due to removing CRC */
730 total_rx_bytes += skb->len;
731 total_rx_packets++;
732
74ce8dd2 733 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 734 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 735
736next_desc:
737 rx_desc->wb.upper.status_error = 0;
738
739 /* return some buffers to hardware, one at a time is too slow */
740 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
741 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
742 cleaned_count = 0;
743 }
744
745 /* use prefetched values */
746 rx_desc = next_rxd;
747 rx_buffer_info = next_buffer;
748
749 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 750 }
751
9a799d71
AK		 752 rx_ring->next_to_clean = i;
753 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
754
755 if (cleaned_count)
756 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
757
f494e8fa
AV		 758 rx_ring->total_packets += total_rx_packets;
759 rx_ring->total_bytes += total_rx_bytes;
760 adapter->net_stats.rx_bytes += total_rx_bytes;
761 adapter->net_stats.rx_packets += total_rx_packets;
762
9a799d71
AK		 763 return cleaned;
764}
765
021230d4 766static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 767/**
768 * ixgbe_configure_msix - Configure MSI-X hardware
769 * @adapter: board private structure
770 *
771 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
772 * interrupts.
773 **/
774static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
775{
021230d4
AV		 776 struct ixgbe_q_vector *q_vector;
777 int i, j, q_vectors, v_idx, r_idx;
778 u32 mask;
9a799d71 779
021230d4 780 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 781
4df10466
JB		 782 /*
783 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 784 * corresponding register.
785 */
786 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
787 q_vector = &adapter->q_vector[v_idx];
788 /* XXX for_each_bit(...) */
789 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 790 adapter->num_rx_queues);
021230d4
AV		 791
792 for (i = 0; i < q_vector->rxr_count; i++) {
793 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 794 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 795 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 796 adapter->num_rx_queues,
797 r_idx + 1);
021230d4
AV		 798 }
799 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 800 adapter->num_tx_queues);
021230d4
AV		 801
802 for (i = 0; i < q_vector->txr_count; i++) {
803 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 804 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 805 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 806 adapter->num_tx_queues,
807 r_idx + 1);
021230d4
AV		 808 }
809
30efa5a3 810 /* if this is a tx only vector halve the interrupt rate */
021230d4 811 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 812 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 813 else if (q_vector->rxr_count)
30efa5a3
JB		 814 /* rx only */
815 q_vector->eitr = adapter->eitr_param;
021230d4 816
509ee935 817 /*
4df10466 818 * since this is initial set up don't need to call
509ee935
JB		 819 * ixgbe_write_eitr helper
820 */
021230d4 821 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 822 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 823 }
824
e8e26350
PW		 825 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
826 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
827 v_idx);
828 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
829 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
831
41fb9248 832 /* set up to autoclear timer, and the vectors */
021230d4 833 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 834 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 836}
837
f494e8fa
AV		 838enum latency_range {
839 lowest_latency = 0,
840 low_latency = 1,
841 bulk_latency = 2,
842 latency_invalid = 255
843};
844
845/**
846 * ixgbe_update_itr - update the dynamic ITR value based on statistics
847 * @adapter: pointer to adapter
848 * @eitr: eitr setting (ints per sec) to give last timeslice
849 * @itr_setting: current throttle rate in ints/second
850 * @packets: the number of packets during this measurement interval
851 * @bytes: the number of bytes during this measurement interval
852 *
853 * Stores a new ITR value based on packets and byte
854 * counts during the last interrupt. The advantage of per interrupt
855 * computation is faster updates and more accurate ITR for the current
856 * traffic pattern. Constants in this function were computed
857 * based on theoretical maximum wire speed and thresholds were set based
858 * on testing data as well as attempting to minimize response time
859 * while increasing bulk throughput.
860 * this functionality is controlled by the InterruptThrottleRate module
861 * parameter (see ixgbe_param.c)
862 **/
863static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 864 u32 eitr, u8 itr_setting,
865 int packets, int bytes)
f494e8fa
AV		 866{
867 unsigned int retval = itr_setting;
868 u32 timepassed_us;
869 u64 bytes_perint;
870
871 if (packets == 0)
872 goto update_itr_done;
873
874
875 /* simple throttlerate management
876 * 0-20MB/s lowest (100000 ints/s)
877 * 20-100MB/s low (20000 ints/s)
878 * 100-1249MB/s bulk (8000 ints/s)
879 */
880 /* what was last interrupt timeslice? */
881 timepassed_us = 1000000/eitr;
882 bytes_perint = bytes / timepassed_us; /* bytes/usec */
883
884 switch (itr_setting) {
885 case lowest_latency:
886 if (bytes_perint > adapter->eitr_low)
887 retval = low_latency;
888 break;
889 case low_latency:
890 if (bytes_perint > adapter->eitr_high)
891 retval = bulk_latency;
892 else if (bytes_perint <= adapter->eitr_low)
893 retval = lowest_latency;
894 break;
895 case bulk_latency:
896 if (bytes_perint <= adapter->eitr_high)
897 retval = low_latency;
898 break;
899 }
900
901update_itr_done:
902 return retval;
903}
904
509ee935
JB		 905/**
906 * ixgbe_write_eitr - write EITR register in hardware specific way
907 * @adapter: pointer to adapter struct
908 * @v_idx: vector index into q_vector array
909 * @itr_reg: new value to be written in *register* format, not ints/s
910 *
911 * This function is made to be called by ethtool and by the driver
912 * when it needs to update EITR registers at runtime. Hardware
913 * specific quirks/differences are taken care of here.
914 */
915void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
916{
917 struct ixgbe_hw *hw = &adapter->hw;
918 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
919 /* must write high and low 16 bits to reset counter */
920 itr_reg |= (itr_reg << 16);
921 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
922 /*
923 * set the WDIS bit to not clear the timer bits and cause an
924 * immediate assertion of the interrupt
925 */
926 itr_reg |= IXGBE_EITR_CNT_WDIS;
927 }
928 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
929}
930
f494e8fa
AV		 931static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
932{
933 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 934 u32 new_itr;
935 u8 current_itr, ret_itr;
936 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 937 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 938 struct ixgbe_ring *rx_ring, *tx_ring;
939
940 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
941 for (i = 0; i < q_vector->txr_count; i++) {
942 tx_ring = &(adapter->tx_ring[r_idx]);
943 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 944 q_vector->tx_itr,
945 tx_ring->total_packets,
946 tx_ring->total_bytes);
f494e8fa
AV		 947 /* if the result for this queue would decrease interrupt
948 * rate for this vector then use that result */
30efa5a3 949 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 950 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 951 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 952 r_idx + 1);
f494e8fa
AV		 953 }
954
955 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
956 for (i = 0; i < q_vector->rxr_count; i++) {
957 rx_ring = &(adapter->rx_ring[r_idx]);
958 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 959 q_vector->rx_itr,
960 rx_ring->total_packets,
961 rx_ring->total_bytes);
f494e8fa
AV		 962 /* if the result for this queue would decrease interrupt
963 * rate for this vector then use that result */
30efa5a3 964 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 965 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 966 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 967 r_idx + 1);
f494e8fa
AV		 968 }
969
30efa5a3 970 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 971
972 switch (current_itr) {
973 /* counts and packets in update_itr are dependent on these numbers */
974 case lowest_latency:
975 new_itr = 100000;
976 break;
977 case low_latency:
978 new_itr = 20000; /* aka hwitr = ~200 */
979 break;
980 case bulk_latency:
981 default:
982 new_itr = 8000;
983 break;
984 }
985
986 if (new_itr != q_vector->eitr) {
987 u32 itr_reg;
509ee935
JB		 988
989 /* save the algorithm value here, not the smoothed one */
990 q_vector->eitr = new_itr;
f494e8fa
AV		 991 /* do an exponential smoothing */
992 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 993 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 994 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 995 }
996
997 return;
998}
999
0befdb3e
JB		 1000static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1001{
1002 struct ixgbe_hw *hw = &adapter->hw;
1003
1004 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1005 (eicr & IXGBE_EICR_GPI_SDP1)) {
1006 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1007 /* write to clear the interrupt */
1008 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1009 }
1010}
cf8280ee 1011
e8e26350
PW		 1012static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1013{
1014 struct ixgbe_hw *hw = &adapter->hw;
1015
1016 if (eicr & IXGBE_EICR_GPI_SDP1) {
1017 /* Clear the interrupt */
1018 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1019 schedule_work(&adapter->multispeed_fiber_task);
1020 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1021 /* Clear the interrupt */
1022 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1023 schedule_work(&adapter->sfp_config_module_task);
1024 } else {
1025 /* Interrupt isn't for us... */
1026 return;
1027 }
1028}
1029
cf8280ee
JB		 1030static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1031{
1032 struct ixgbe_hw *hw = &adapter->hw;
1033
1034 adapter->lsc_int++;
1035 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1036 adapter->link_check_timeout = jiffies;
1037 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1038 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1039 schedule_work(&adapter->watchdog_task);
1040 }
1041}
1042
9a799d71
AK		 1043static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1044{
1045 struct net_device *netdev = data;
1046 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1047 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1048 u32 eicr;
1049
1050 /*
1051 * Workaround for Silicon errata. Use clear-by-write instead
1052 * of clear-by-read. Reading with EICS will return the
1053 * interrupt causes without clearing, which later be done
1054 * with the write to EICR.
1055 */
1056 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1057 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1058
cf8280ee
JB		 1059 if (eicr & IXGBE_EICR_LSC)
1060 ixgbe_check_lsc(adapter);
d4f80882 1061
e8e26350
PW		 1062 if (hw->mac.type == ixgbe_mac_82598EB)
1063 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1064
e8e26350
PW		 1065 if (hw->mac.type == ixgbe_mac_82599EB)
1066 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1067 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1068 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1069
1070 return IRQ_HANDLED;
1071}
1072
1073static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1074{
021230d4
AV		 1075 struct ixgbe_q_vector *q_vector = data;
1076 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1077 struct ixgbe_ring *tx_ring;
021230d4
AV		 1078 int i, r_idx;
1079
1080 if (!q_vector->txr_count)
1081 return IRQ_HANDLED;
1082
1083 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1084 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1085 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1086#ifdef CONFIG_IXGBE_DCA
bd0362dd 1087 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1088 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1089#endif
3a581073
JB		 1090 tx_ring->total_bytes = 0;
1091 tx_ring->total_packets = 0;
1092 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1093 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1094 r_idx + 1);
021230d4 1095 }
9a799d71 1096
9a799d71
AK		 1097 return IRQ_HANDLED;
1098}
1099
021230d4
AV		 1100/**
1101 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1102 * @irq: unused
1103 * @data: pointer to our q_vector struct for this interrupt vector
1104 **/
9a799d71
AK		 1105static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1106{
021230d4
AV		 1107 struct ixgbe_q_vector *q_vector = data;
1108 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1109 struct ixgbe_ring *rx_ring;
021230d4 1110 int r_idx;
30efa5a3 1111 int i;
021230d4
AV		 1112
1113 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1114 for (i = 0; i < q_vector->rxr_count; i++) {
1115 rx_ring = &(adapter->rx_ring[r_idx]);
1116 rx_ring->total_bytes = 0;
1117 rx_ring->total_packets = 0;
1118 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1119 r_idx + 1);
1120 }
1121
021230d4
AV		 1122 if (!q_vector->rxr_count)
1123 return IRQ_HANDLED;
1124
30efa5a3 1125 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1126 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1127 /* disable interrupts on this vector only */
3a581073 1128 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1129 napi_schedule(&q_vector->napi);
021230d4
AV		 1130
1131 return IRQ_HANDLED;
1132}
1133
1134static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1135{
1136 ixgbe_msix_clean_rx(irq, data);
1137 ixgbe_msix_clean_tx(irq, data);
9a799d71 1138
9a799d71
AK		 1139 return IRQ_HANDLED;
1140}
1141
021230d4
AV		 1142/**
1143 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1144 * @napi: napi struct with our devices info in it
1145 * @budget: amount of work driver is allowed to do this pass, in packets
1146 *
f0848276
JB		 1147 * This function is optimized for cleaning one queue only on a single
1148 * q_vector!!!
021230d4 1149 **/
9a799d71
AK		 1150static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1151{
021230d4 1152 struct ixgbe_q_vector *q_vector =
b4617240 1153 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1154 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1155 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1156 int work_done = 0;
021230d4 1157 long r_idx;
9a799d71 1158
021230d4 1159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1160 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1161#ifdef CONFIG_IXGBE_DCA
bd0362dd 1162 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1163 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1164#endif
9a799d71 1165
78b6f4ce 1166 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1167
021230d4
AV		 1168 /* If all Rx work done, exit the polling mode */
1169 if (work_done < budget) {
288379f0 1170 napi_complete(napi);
509ee935 1171 if (adapter->itr_setting & 1)
f494e8fa 1172 ixgbe_set_itr_msix(q_vector);
9a799d71 1173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1174 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1175 }
1176
1177 return work_done;
1178}
1179
f0848276
JB		 1180/**
1181 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1182 * @napi: napi struct with our devices info in it
1183 * @budget: amount of work driver is allowed to do this pass, in packets
1184 *
1185 * This function will clean more than one rx queue associated with a
1186 * q_vector.
1187 **/
1188static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1189{
1190 struct ixgbe_q_vector *q_vector =
1191 container_of(napi, struct ixgbe_q_vector, napi);
1192 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1193 struct ixgbe_ring *rx_ring = NULL;
1194 int work_done = 0, i;
1195 long r_idx;
1196 u16 enable_mask = 0;
1197
1198 /* attempt to distribute budget to each queue fairly, but don't allow
1199 * the budget to go below 1 because we'll exit polling */
1200 budget /= (q_vector->rxr_count ?: 1);
1201 budget = max(budget, 1);
1202 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1203 for (i = 0; i < q_vector->rxr_count; i++) {
1204 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1205#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1206 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1207 ixgbe_update_rx_dca(adapter, rx_ring);
1208#endif
78b6f4ce 1209 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1210 enable_mask |= rx_ring->v_idx;
1211 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1212 r_idx + 1);
1213 }
1214
1215 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1216 rx_ring = &(adapter->rx_ring[r_idx]);
1217 /* If all Rx work done, exit the polling mode */
7f821875 1218 if (work_done < budget) {
288379f0 1219 napi_complete(napi);
509ee935 1220 if (adapter->itr_setting & 1)
f0848276
JB		 1221 ixgbe_set_itr_msix(q_vector);
1222 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1223 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1224 return 0;
1225 }
1226
1227 return work_done;
1228}
021230d4 1229static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1230 int r_idx)
021230d4
AV		 1231{
1232 a->q_vector[v_idx].adapter = a;
1233 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1234 a->q_vector[v_idx].rxr_count++;
1235 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1236}
1237
1238static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1239 int r_idx)
021230d4
AV		 1240{
1241 a->q_vector[v_idx].adapter = a;
1242 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1243 a->q_vector[v_idx].txr_count++;
1244 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1245}
1246
9a799d71 1247/**
021230d4
AV		 1248 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1249 * @adapter: board private structure to initialize
1250 * @vectors: allotted vector count for descriptor rings
9a799d71 1251 *
021230d4
AV		 1252 * This function maps descriptor rings to the queue-specific vectors
1253 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1254 * one vector per ring/queue, but on a constrained vector budget, we
1255 * group the rings as "efficiently" as possible. You would add new
1256 * mapping configurations in here.
9a799d71 1257 **/
021230d4 1258static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1259 int vectors)
021230d4
AV		 1260{
1261 int v_start = 0;
1262 int rxr_idx = 0, txr_idx = 0;
1263 int rxr_remaining = adapter->num_rx_queues;
1264 int txr_remaining = adapter->num_tx_queues;
1265 int i, j;
1266 int rqpv, tqpv;
1267 int err = 0;
1268
1269 /* No mapping required if MSI-X is disabled. */
1270 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1271 goto out;
9a799d71 1272
021230d4
AV		 1273 /*
1274 * The ideal configuration...
1275 * We have enough vectors to map one per queue.
1276 */
1277 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1279 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1280
021230d4
AV		 1281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1282 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1283
9a799d71 1284 goto out;
021230d4 1285 }
9a799d71 1286
021230d4
AV		 1287 /*
1288 * If we don't have enough vectors for a 1-to-1
1289 * mapping, we'll have to group them so there are
1290 * multiple queues per vector.
1291 */
1292 /* Re-adjusting *qpv takes care of the remainder. */
1293 for (i = v_start; i < vectors; i++) {
1294 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1295 for (j = 0; j < rqpv; j++) {
1296 map_vector_to_rxq(adapter, i, rxr_idx);
1297 rxr_idx++;
1298 rxr_remaining--;
1299 }
1300 }
1301 for (i = v_start; i < vectors; i++) {
1302 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1303 for (j = 0; j < tqpv; j++) {
1304 map_vector_to_txq(adapter, i, txr_idx);
1305 txr_idx++;
1306 txr_remaining--;
9a799d71 1307 }
9a799d71
AK		 1308 }
1309
021230d4
AV		 1310out:
1311 return err;
1312}
1313
1314/**
1315 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1316 * @adapter: board private structure
1317 *
1318 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1319 * interrupts from the kernel.
1320 **/
1321static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1322{
1323 struct net_device *netdev = adapter->netdev;
1324 irqreturn_t (*handler)(int, void *);
1325 int i, vector, q_vectors, err;
cb13fc20 1326 int ri=0, ti=0;
021230d4
AV		 1327
1328 /* Decrement for Other and TCP Timer vectors */
1329 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1330
1331 /* Map the Tx/Rx rings to the vectors we were allotted. */
1332 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1333 if (err)
1334 goto out;
1335
1336#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1337 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1338 &ixgbe_msix_clean_many)
021230d4
AV		 1339 for (vector = 0; vector < q_vectors; vector++) {
1340 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1341
1342 if(handler == &ixgbe_msix_clean_rx) {
1343 sprintf(adapter->name[vector], "%s-%s-%d",
1344 netdev->name, "rx", ri++);
1345 }
1346 else if(handler == &ixgbe_msix_clean_tx) {
1347 sprintf(adapter->name[vector], "%s-%s-%d",
1348 netdev->name, "tx", ti++);
1349 }
1350 else
1351 sprintf(adapter->name[vector], "%s-%s-%d",
1352 netdev->name, "TxRx", vector);
1353
021230d4 1354 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1355 handler, 0, adapter->name[vector],
1356 &(adapter->q_vector[vector]));
9a799d71
AK		 1357 if (err) {
1358 DPRINTK(PROBE, ERR,
b4617240
PW		 1359 "request_irq failed for MSIX interrupt "
1360 "Error: %d\n", err);
021230d4 1361 goto free_queue_irqs;
9a799d71 1362 }
9a799d71
AK		 1363 }
1364
021230d4
AV		 1365 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1366 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1367 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1368 if (err) {
1369 DPRINTK(PROBE, ERR,
1370 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1371 goto free_queue_irqs;
9a799d71
AK		 1372 }
1373
9a799d71
AK		 1374 return 0;
1375
021230d4
AV		 1376free_queue_irqs:
1377 for (i = vector - 1; i >= 0; i--)
1378 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1379 &(adapter->q_vector[i]));
021230d4
AV		 1380 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1381 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1382 kfree(adapter->msix_entries);
1383 adapter->msix_entries = NULL;
021230d4 1384out:
9a799d71
AK		 1385 return err;
1386}
1387
f494e8fa
AV		 1388static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1389{
f494e8fa
AV		 1390 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1391 u8 current_itr;
1392 u32 new_itr = q_vector->eitr;
1393 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1394 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1395
30efa5a3 1396 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1397 q_vector->tx_itr,
1398 tx_ring->total_packets,
1399 tx_ring->total_bytes);
30efa5a3 1400 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1401 q_vector->rx_itr,
1402 rx_ring->total_packets,
1403 rx_ring->total_bytes);
f494e8fa 1404
30efa5a3 1405 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1406
1407 switch (current_itr) {
1408 /* counts and packets in update_itr are dependent on these numbers */
1409 case lowest_latency:
1410 new_itr = 100000;
1411 break;
1412 case low_latency:
1413 new_itr = 20000; /* aka hwitr = ~200 */
1414 break;
1415 case bulk_latency:
1416 new_itr = 8000;
1417 break;
1418 default:
1419 break;
1420 }
1421
1422 if (new_itr != q_vector->eitr) {
1423 u32 itr_reg;
509ee935
JB		 1424
1425 /* save the algorithm value here, not the smoothed one */
1426 q_vector->eitr = new_itr;
f494e8fa
AV		 1427 /* do an exponential smoothing */
1428 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1429 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1430 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1431 }
1432
1433 return;
1434}
1435
79aefa45
AD		 1436/**
1437 * ixgbe_irq_enable - Enable default interrupt generation settings
1438 * @adapter: board private structure
1439 **/
1440static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1441{
1442 u32 mask;
1443 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1444 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1445 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1446 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1447 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1448 mask |= IXGBE_EIMS_GPI_SDP1;
1449 mask |= IXGBE_EIMS_GPI_SDP2;
1450 }
1451
79aefa45 1452 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
e8e26350
PW		 1453 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1454 /* enable the rest of the queue vectors */
1455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1456 (IXGBE_EIMS_RTX_QUEUE << 16));
1457 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1458 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1459 IXGBE_EIMS_RTX_QUEUE));
1460 }
79aefa45
AD		 1461 IXGBE_WRITE_FLUSH(&adapter->hw);
1462}
021230d4 1463
9a799d71 1464/**
021230d4 1465 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1466 * @irq: interrupt number
1467 * @data: pointer to a network interface device structure
9a799d71
AK		 1468 **/
1469static irqreturn_t ixgbe_intr(int irq, void *data)
1470{
1471 struct net_device *netdev = data;
1472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1473 struct ixgbe_hw *hw = &adapter->hw;
1474 u32 eicr;
1475
54037505
DS		 1476 /*
1477 * Workaround for silicon errata. Mask the interrupts
1478 * before the read of EICR.
1479 */
1480 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1481
021230d4
AV		 1482 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1483 * therefore no explict interrupt disable is necessary */
1484 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1485 if (!eicr) {
1486 /* shared interrupt alert!
1487 * make sure interrupts are enabled because the read will
1488 * have disabled interrupts due to EIAM */
1489 ixgbe_irq_enable(adapter);
9a799d71 1490 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1491 }
9a799d71 1492
cf8280ee
JB		 1493 if (eicr & IXGBE_EICR_LSC)
1494 ixgbe_check_lsc(adapter);
021230d4 1495
e8e26350
PW		 1496 if (hw->mac.type == ixgbe_mac_82599EB)
1497 ixgbe_check_sfp_event(adapter, eicr);
1498
0befdb3e
JB		 1499 ixgbe_check_fan_failure(adapter, eicr);
1500
288379f0 1501 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1502 adapter->tx_ring[0].total_packets = 0;
1503 adapter->tx_ring[0].total_bytes = 0;
1504 adapter->rx_ring[0].total_packets = 0;
1505 adapter->rx_ring[0].total_bytes = 0;
021230d4 1506 /* would disable interrupts here but EIAM disabled it */
288379f0 1507 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1508 }
1509
1510 return IRQ_HANDLED;
1511}
1512
021230d4
AV		 1513static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1514{
1515 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1516
1517 for (i = 0; i < q_vectors; i++) {
1518 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1519 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1520 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1521 q_vector->rxr_count = 0;
1522 q_vector->txr_count = 0;
1523 }
1524}
1525
9a799d71
AK		 1526/**
1527 * ixgbe_request_irq - initialize interrupts
1528 * @adapter: board private structure
1529 *
1530 * Attempts to configure interrupts using the best available
1531 * capabilities of the hardware and kernel.
1532 **/
021230d4 1533static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1534{
1535 struct net_device *netdev = adapter->netdev;
021230d4 1536 int err;
9a799d71 1537
021230d4
AV		 1538 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1539 err = ixgbe_request_msix_irqs(adapter);
1540 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1541 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1542 netdev->name, netdev);
021230d4
AV		 1543 } else {
1544 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1545 netdev->name, netdev);
9a799d71
AK		 1546 }
1547
9a799d71
AK		 1548 if (err)
1549 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1550
9a799d71
AK		 1551 return err;
1552}
1553
1554static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1555{
1556 struct net_device *netdev = adapter->netdev;
1557
1558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1559 int i, q_vectors;
9a799d71 1560
021230d4
AV		 1561 q_vectors = adapter->num_msix_vectors;
1562
1563 i = q_vectors - 1;
9a799d71 1564 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1565
021230d4
AV		 1566 i--;
1567 for (; i >= 0; i--) {
1568 free_irq(adapter->msix_entries[i].vector,
b4617240 1569 &(adapter->q_vector[i]));
021230d4
AV		 1570 }
1571
1572 ixgbe_reset_q_vectors(adapter);
1573 } else {
1574 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1575 }
1576}
1577
22d5a71b
JB		 1578/**
1579 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1580 * @adapter: board private structure
1581 **/
1582static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1583{
1584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1585 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1588 }
1589 IXGBE_WRITE_FLUSH(&adapter->hw);
1590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1591 int i;
1592 for (i = 0; i < adapter->num_msix_vectors; i++)
1593 synchronize_irq(adapter->msix_entries[i].vector);
1594 } else {
1595 synchronize_irq(adapter->pdev->irq);
1596 }
1597}
1598
1599static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter)
1600{
1601 u32 mask = IXGBE_EIMS_RTX_QUEUE;
1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1603 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask << 16);
1605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1606 (mask << 16 | mask));
1607 }
1608 /* skip the flush */
1609}
1610
9a799d71
AK		 1611/**
1612 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1613 *
1614 **/
1615static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1616{
9a799d71
AK		 1617 struct ixgbe_hw *hw = &adapter->hw;
1618
021230d4 1619 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1620 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1621
e8e26350
PW		 1622 ixgbe_set_ivar(adapter, 0, 0, 0);
1623 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1624
1625 map_vector_to_rxq(adapter, 0, 0);
1626 map_vector_to_txq(adapter, 0, 0);
1627
1628 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1629}
1630
1631/**
3a581073 1632 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1633 * @adapter: board private structure
1634 *
1635 * Configure the Tx unit of the MAC after a reset.
1636 **/
1637static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1638{
12207e49 1639 u64 tdba;
9a799d71 1640 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1641 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1642
1643 /* Setup the HW Tx Head and Tail descriptor pointers */
1644 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1645 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1646 j = ring->reg_idx;
1647 tdba = ring->dma;
1648 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1649 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1650 (tdba & DMA_32BIT_MASK));
021230d4
AV		 1651 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1652 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1653 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1654 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1655 adapter->tx_ring[i].head = IXGBE_TDH(j);
1656 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1657 /* Disable Tx Head Writeback RO bit, since this hoses
1658 * bookkeeping if things aren't delivered in order.
1659 */
e01c31a5 1660 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1661 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1662 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1663 }
e8e26350
PW		 1664 if (hw->mac.type == ixgbe_mac_82599EB) {
1665 /* We enable 8 traffic classes, DCB only */
1666 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1667 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1668 IXGBE_MTQC_8TC_8TQ));
1669 }
9a799d71
AK		 1670}
1671
e8e26350 1672#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1673
1674static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1675{
1676 struct ixgbe_ring *rx_ring;
1677 u32 srrctl;
e8e26350 1678 int queue0 = 0;
3be1adfb
AD		 1679 unsigned long mask;
1680
e8e26350
PW		 1681 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1682 queue0 = index;
cc41ac7c 1683 } else {
3be1adfb
AD		 1684 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1685 queue0 = index & mask;
1686 index = index & mask;
cc41ac7c 1687 }
3be1adfb 1688
cc41ac7c
JB		 1689 rx_ring = &adapter->rx_ring[queue0];
1690
1691 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1692
1693 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1694 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1695
1696 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1697 u16 bufsz = IXGBE_RXBUFFER_2048;
1698 /* grow the amount we can receive on large page machines */
1699 if (bufsz < (PAGE_SIZE / 2))
1700 bufsz = (PAGE_SIZE / 2);
1701 /* cap the bufsz at our largest descriptor size */
1702 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1703
1704 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1705 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1706 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1707 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1708 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1709 } else {
1710 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1711
1712 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1713 srrctl |= IXGBE_RXBUFFER_2048 >>
1714 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1715 else
1716 srrctl |= rx_ring->rx_buf_len >>
1717 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1718 }
e8e26350 1719
cc41ac7c
JB		 1720 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1721}
9a799d71 1722
9a799d71 1723/**
3a581073 1724 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1725 * @adapter: board private structure
1726 *
1727 * Configure the Rx unit of the MAC after a reset.
1728 **/
1729static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1730{
1731 u64 rdba;
1732 struct ixgbe_hw *hw = &adapter->hw;
1733 struct net_device *netdev = adapter->netdev;
1734 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1735 int i, j;
9a799d71 1736 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1737 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1738 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1739 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1740 u32 fctrl, hlreg0;
509ee935 1741 u32 reta = 0, mrqc = 0;
cc41ac7c 1742 u32 rdrxctl;
7c6e0a43 1743 int rx_buf_len;
9a799d71
AK		 1744
1745 /* Decide whether to use packet split mode or not */
762f4c57 1746 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1747
1748 /* Set the RX buffer length according to the mode */
1749 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1750 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1751 if (hw->mac.type == ixgbe_mac_82599EB) {
1752 /* PSRTYPE must be initialized in 82599 */
1753 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1754 IXGBE_PSRTYPE_UDPHDR |
1755 IXGBE_PSRTYPE_IPV4HDR |
1756 IXGBE_PSRTYPE_IPV6HDR;
1757 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1758 }
9a799d71
AK		 1759 } else {
1760 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1761 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1762 else
7c6e0a43 1763 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1764 }
1765
1766 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1767 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1768 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1769 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1770 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1771
1772 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1773 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1774 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1775 else
1776 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1777 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1778
9a799d71
AK		 1779 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1780 /* disable receives while setting up the descriptors */
1781 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1782 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1783
1784 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1785 * the Base and Length of the Rx Descriptor Ring */
1786 for (i = 0; i < adapter->num_rx_queues; i++) {
1787 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1788 j = adapter->rx_ring[i].reg_idx;
1789 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1790 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1791 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1792 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1793 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1794 adapter->rx_ring[i].head = IXGBE_RDH(j);
1795 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1796 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1797
1798 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1799 }
1800
e8e26350
PW		 1801 if (hw->mac.type == ixgbe_mac_82598EB) {
1802 /*
1803 * For VMDq support of different descriptor types or
1804 * buffer sizes through the use of multiple SRRCTL
1805 * registers, RDRXCTL.MVMEN must be set to 1
1806 *
1807 * also, the manual doesn't mention it clearly but DCA hints
1808 * will only use queue 0's tags unless this bit is set. Side
1809 * effects of setting this bit are only that SRRCTL must be
1810 * fully programmed [0..15]
1811 */
2a41ff81
JB		 1812 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1813 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1814 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1815 }
177db6ff 1816
e8e26350
PW		 1817 /* Program MRQC for the distribution of queues */
1818 if (hw->mac.type == ixgbe_mac_82599EB) {
1819 int mask = adapter->flags & (
1820 IXGBE_FLAG_RSS_ENABLED
1821 | IXGBE_FLAG_DCB_ENABLED
1822 );
1823
1824 switch (mask) {
1825 case (IXGBE_FLAG_RSS_ENABLED):
1826 mrqc = IXGBE_MRQC_RSSEN;
1827 break;
1828 case (IXGBE_FLAG_DCB_ENABLED):
1829 mrqc = IXGBE_MRQC_RT8TCEN;
1830 break;
1831 default:
1832 break;
1833 }
1834 }
021230d4 1835 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1836 /* Fill out redirection table */
021230d4
AV		 1837 for (i = 0, j = 0; i < 128; i++, j++) {
1838 if (j == adapter->ring_feature[RING_F_RSS].indices)
1839 j = 0;
1840 /* reta = 4-byte sliding window of
1841 * 0x00..(indices-1)(indices-1)00..etc. */
1842 reta = (reta << 8) | (j * 0x11);
1843 if ((i & 3) == 3)
1844 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1845 }
1846
1847 /* Fill out hash function seeds */
1848 for (i = 0; i < 10; i++)
7c6e0a43 1849 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1850
2a41ff81
JB		 1851 if (hw->mac.type == ixgbe_mac_82598EB)
1852 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1853 /* Perform hash on these packet types */
2a41ff81
JB		 1854 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1855 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1856 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1857 | IXGBE_MRQC_RSS_FIELD_IPV6
1858 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1859 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1860 }
2a41ff81 1861 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1862
021230d4
AV		 1863 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1864
1865 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1866 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1867 /* Disable indicating checksum in descriptor, enables
1868 * RSS hash */
9a799d71 1869 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1870 }
021230d4
AV		 1871 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1872 /* Enable IPv4 payload checksum for UDP fragments
1873 * if PCSD is not set */
1874 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1875 }
1876
1877 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1878
1879 if (hw->mac.type == ixgbe_mac_82599EB) {
1880 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1881 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1882 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1883 }
9a799d71
AK		 1884}
1885
068c89b0
DS		 1886static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1887{
1888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1889 struct ixgbe_hw *hw = &adapter->hw;
1890
1891 /* add VID to filter table */
1892 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1893}
1894
1895static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1896{
1897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1898 struct ixgbe_hw *hw = &adapter->hw;
1899
1900 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1901 ixgbe_irq_disable(adapter);
1902
1903 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1904
1905 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1906 ixgbe_irq_enable(adapter);
1907
1908 /* remove VID from filter table */
1909 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1910}
1911
9a799d71 1912static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1913 struct vlan_group *grp)
9a799d71
AK		 1914{
1915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1916 u32 ctrl;
e8e26350 1917 int i, j;
9a799d71 1918
d4f80882
AV		 1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920 ixgbe_irq_disable(adapter);
9a799d71
AK		 1921 adapter->vlgrp = grp;
1922
2f90b865
AD		 1923 /*
1924 * For a DCB driver, always enable VLAN tag stripping so we can
1925 * still receive traffic from a DCB-enabled host even if we're
1926 * not in DCB mode.
1927 */
1928 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 1929 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1930 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1931 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1933 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1934 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 1935 /* enable VLAN tag insert/strip */
1936 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 1937 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1938 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 1939 for (i = 0; i < adapter->num_rx_queues; i++) {
1940 j = adapter->rx_ring[i].reg_idx;
1941 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1942 ctrl |= IXGBE_RXDCTL_VME;
1943 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1944 }
9a799d71 1945 }
e8e26350 1946 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 1947
d4f80882
AV		 1948 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1949 ixgbe_irq_enable(adapter);
9a799d71
AK		 1950}
1951
9a799d71
AK		 1952static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1953{
1954 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1955
1956 if (adapter->vlgrp) {
1957 u16 vid;
1958 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1959 if (!vlan_group_get_device(adapter->vlgrp, vid))
1960 continue;
1961 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1962 }
1963 }
1964}
1965
2c5645cf
CL		 1966static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1967{
1968 struct dev_mc_list *mc_ptr;
1969 u8 *addr = *mc_addr_ptr;
1970 *vmdq = 0;
1971
1972 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1973 if (mc_ptr->next)
1974 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1975 else
1976 *mc_addr_ptr = NULL;
1977
1978 return addr;
1979}
1980
9a799d71 1981/**
2c5645cf 1982 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1983 * @netdev: network interface device structure
1984 *
2c5645cf
CL		 1985 * The set_rx_method entry point is called whenever the unicast/multicast
1986 * address list or the network interface flags are updated. This routine is
1987 * responsible for configuring the hardware for proper unicast, multicast and
1988 * promiscuous mode.
9a799d71 1989 **/
2c5645cf 1990static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1991{
1992 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1993 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1994 u32 fctrl, vlnctrl;
2c5645cf
CL		 1995 u8 *addr_list = NULL;
1996 int addr_count = 0;
9a799d71
AK		 1997
1998 /* Check for Promiscuous and All Multicast modes */
1999
2000 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2001 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2002
2003 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2004 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2005 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2006 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2007 } else {
746b9f02
PM		 2008 if (netdev->flags & IFF_ALLMULTI) {
2009 fctrl |= IXGBE_FCTRL_MPE;
2010 fctrl &= ~IXGBE_FCTRL_UPE;
2011 } else {
2012 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2013 }
3d01625a 2014 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2015 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2016 }
2017
2018 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2019 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2020
2c5645cf
CL		 2021 /* reprogram secondary unicast list */
2022 addr_count = netdev->uc_count;
2023 if (addr_count)
2024 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2025 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2026 ixgbe_addr_list_itr);
9a799d71 2027
2c5645cf
CL		 2028 /* reprogram multicast list */
2029 addr_count = netdev->mc_count;
2030 if (addr_count)
2031 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2032 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2033 ixgbe_addr_list_itr);
9a799d71
AK		 2034}
2035
021230d4
AV		 2036static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2037{
2038 int q_idx;
2039 struct ixgbe_q_vector *q_vector;
2040 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2041
2042 /* legacy and MSI only use one vector */
2043 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2044 q_vectors = 1;
2045
2046 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2047 struct napi_struct *napi;
021230d4
AV		 2048 q_vector = &adapter->q_vector[q_idx];
2049 if (!q_vector->rxr_count)
2050 continue;
f0848276
JB		 2051 napi = &q_vector->napi;
2052 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2053 (q_vector->rxr_count > 1))
2054 napi->poll = &ixgbe_clean_rxonly_many;
2055
2056 napi_enable(napi);
021230d4
AV		 2057 }
2058}
2059
2060static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2061{
2062 int q_idx;
2063 struct ixgbe_q_vector *q_vector;
2064 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2065
2066 /* legacy and MSI only use one vector */
2067 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2068 q_vectors = 1;
2069
2070 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2071 q_vector = &adapter->q_vector[q_idx];
2072 if (!q_vector->rxr_count)
2073 continue;
2074 napi_disable(&q_vector->napi);
2075 }
2076}
2077
7a6b6f51 2078#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2079/*
2080 * ixgbe_configure_dcb - Configure DCB hardware
2081 * @adapter: ixgbe adapter struct
2082 *
2083 * This is called by the driver on open to configure the DCB hardware.
2084 * This is also called by the gennetlink interface when reconfiguring
2085 * the DCB state.
2086 */
2087static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2088{
2089 struct ixgbe_hw *hw = &adapter->hw;
2090 u32 txdctl, vlnctrl;
2091 int i, j;
2092
2093 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2094 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2095 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2096
2097 /* reconfigure the hardware */
2098 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2099
2100 for (i = 0; i < adapter->num_tx_queues; i++) {
2101 j = adapter->tx_ring[i].reg_idx;
2102 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2103 /* PThresh workaround for Tx hang with DFP enabled. */
2104 txdctl |= 32;
2105 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2106 }
2107 /* Enable VLAN tag insert/strip */
2108 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2109 if (hw->mac.type == ixgbe_mac_82598EB) {
2110 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2111 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2112 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2113 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2114 vlnctrl |= IXGBE_VLNCTRL_VFE;
2115 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2117 for (i = 0; i < adapter->num_rx_queues; i++) {
2118 j = adapter->rx_ring[i].reg_idx;
2119 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2120 vlnctrl |= IXGBE_RXDCTL_VME;
2121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2122 }
2123 }
2f90b865
AD		 2124 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2125}
2126
2127#endif
9a799d71
AK		 2128static void ixgbe_configure(struct ixgbe_adapter *adapter)
2129{
2130 struct net_device *netdev = adapter->netdev;
2131 int i;
2132
2c5645cf 2133 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2134
2135 ixgbe_restore_vlan(adapter);
7a6b6f51 2136#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2137 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2138 netif_set_gso_max_size(netdev, 32768);
2139 ixgbe_configure_dcb(adapter);
2140 } else {
2141 netif_set_gso_max_size(netdev, 65536);
2142 }
2143#else
2144 netif_set_gso_max_size(netdev, 65536);
2145#endif
9a799d71
AK		 2146
2147 ixgbe_configure_tx(adapter);
2148 ixgbe_configure_rx(adapter);
2149 for (i = 0; i < adapter->num_rx_queues; i++)
2150 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2151 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2152}
2153
e8e26350
PW		 2154static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2155{
2156 switch (hw->phy.type) {
2157 case ixgbe_phy_sfp_avago:
2158 case ixgbe_phy_sfp_ftl:
2159 case ixgbe_phy_sfp_intel:
2160 case ixgbe_phy_sfp_unknown:
2161 case ixgbe_phy_tw_tyco:
2162 case ixgbe_phy_tw_unknown:
2163 return true;
2164 default:
2165 return false;
2166 }
2167}
2168
0ecc061d 2169/**
e8e26350
PW		 2170 * ixgbe_sfp_link_config - set up SFP+ link
2171 * @adapter: pointer to private adapter struct
2172 **/
2173static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2174{
2175 struct ixgbe_hw *hw = &adapter->hw;
2176
2177 if (hw->phy.multispeed_fiber) {
2178 /*
2179 * In multispeed fiber setups, the device may not have
2180 * had a physical connection when the driver loaded.
2181 * If that's the case, the initial link configuration
2182 * couldn't get the MAC into 10G or 1G mode, so we'll
2183 * never have a link status change interrupt fire.
2184 * We need to try and force an autonegotiation
2185 * session, then bring up link.
2186 */
2187 hw->mac.ops.setup_sfp(hw);
2188 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2189 schedule_work(&adapter->multispeed_fiber_task);
2190 } else {
2191 /*
2192 * Direct Attach Cu and non-multispeed fiber modules
2193 * still need to be configured properly prior to
2194 * attempting link.
2195 */
2196 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2197 schedule_work(&adapter->sfp_config_module_task);
2198 }
2199}
2200
2201/**
2202 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2203 * @hw: pointer to private hardware struct
2204 *
2205 * Returns 0 on success, negative on failure
2206 **/
e8e26350 2207static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2208{
2209 u32 autoneg;
2210 bool link_up = false;
2211 u32 ret = IXGBE_ERR_LINK_SETUP;
2212
2213 if (hw->mac.ops.check_link)
2214 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2215
2216 if (ret)
2217 goto link_cfg_out;
2218
2219 if (hw->mac.ops.get_link_capabilities)
2220 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2221 &hw->mac.autoneg);
2222 if (ret)
2223 goto link_cfg_out;
2224
2225 if (hw->mac.ops.setup_link_speed)
2226 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2227link_cfg_out:
2228 return ret;
2229}
2230
e8e26350
PW		 2231#define IXGBE_MAX_RX_DESC_POLL 10
2232static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2233 int rxr)
2234{
2235 int j = adapter->rx_ring[rxr].reg_idx;
2236 int k;
2237
2238 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2239 if (IXGBE_READ_REG(&adapter->hw,
2240 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2241 break;
2242 else
2243 msleep(1);
2244 }
2245 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2246 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2247 "not set within the polling period\n", rxr);
2248 }
2249 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2250 (adapter->rx_ring[rxr].count - 1));
2251}
2252
9a799d71
AK		 2253static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2254{
2255 struct net_device *netdev = adapter->netdev;
9a799d71 2256 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2257 int i, j = 0;
e8e26350 2258 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2259 int err;
9a799d71 2260 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2261 u32 txdctl, rxdctl, mhadd;
e8e26350 2262 u32 dmatxctl;
021230d4 2263 u32 gpie;
9a799d71 2264
5eba3699
AV		 2265 ixgbe_get_hw_control(adapter);
2266
021230d4
AV		 2267 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2268 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2269 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2270 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2271 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2272 } else {
2273 /* MSI only */
021230d4 2274 gpie = 0;
9a799d71 2275 }
021230d4
AV		 2276 /* XXX: to interrupt immediately for EICS writes, enable this */
2277 /* gpie |= IXGBE_GPIE_EIMEN; */
2278 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2279 }
2280
021230d4
AV		 2281 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2282 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2283 * specifically only auto mask tx and rx interrupts */
2284 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2285 }
9a799d71 2286
0befdb3e
JB		 2287 /* Enable fan failure interrupt if media type is copper */
2288 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2289 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2290 gpie |= IXGBE_SDP1_GPIEN;
2291 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2292 }
2293
e8e26350
PW		 2294 if (hw->mac.type == ixgbe_mac_82599EB) {
2295 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2296 gpie |= IXGBE_SDP1_GPIEN;
2297 gpie |= IXGBE_SDP2_GPIEN;
2298 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2299 }
2300
021230d4 2301 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2302 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2303 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2304 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2305
2306 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2307 }
2308
2309 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2310 j = adapter->tx_ring[i].reg_idx;
2311 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2312 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2313 txdctl |= (8 << 16);
e8e26350
PW		 2314 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2315 }
2316
2317 if (hw->mac.type == ixgbe_mac_82599EB) {
2318 /* DMATXCTL.EN must be set after all Tx queue config is done */
2319 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2320 dmatxctl |= IXGBE_DMATXCTL_TE;
2321 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2322 }
2323 for (i = 0; i < adapter->num_tx_queues; i++) {
2324 j = adapter->tx_ring[i].reg_idx;
2325 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2326 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2327 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2328 }
2329
e8e26350 2330 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2331 j = adapter->rx_ring[i].reg_idx;
2332 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2333 /* enable PTHRESH=32 descriptors (half the internal cache)
2334 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2335 * this also removes a pesky rx_no_buffer_count increment */
2336 rxdctl |= 0x0020;
9a799d71 2337 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2338 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2339 if (hw->mac.type == ixgbe_mac_82599EB)
2340 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2341 }
2342 /* enable all receives */
2343 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2344 if (hw->mac.type == ixgbe_mac_82598EB)
2345 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2346 else
2347 rxdctl |= IXGBE_RXCTRL_RXEN;
2348 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2349
2350 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2351 ixgbe_configure_msix(adapter);
2352 else
2353 ixgbe_configure_msi_and_legacy(adapter);
2354
2355 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2356 ixgbe_napi_enable_all(adapter);
2357
2358 /* clear any pending interrupts, may auto mask */
2359 IXGBE_READ_REG(hw, IXGBE_EICR);
2360
9a799d71
AK		 2361 ixgbe_irq_enable(adapter);
2362
e8e26350
PW		 2363 /*
2364 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2365 * arrived before interrupts were enabled. We need to kick off
2366 * the SFP+ module setup first, then try to bring up link.
2367 * If we're not hot-pluggable SFP+, we just need to configure link
2368 * and bring it up.
2369 */
2370 err = hw->phy.ops.identify(hw);
2371 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2372 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2373 ixgbe_down(adapter);
2374 return err;
2375 }
2376
2377 if (ixgbe_is_sfp(hw)) {
2378 ixgbe_sfp_link_config(adapter);
2379 } else {
2380 err = ixgbe_non_sfp_link_config(hw);
2381 if (err)
2382 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2383 }
0ecc061d 2384
1da100bb
PWJ		 2385 /* enable transmits */
2386 netif_tx_start_all_queues(netdev);
2387
9a799d71
AK		 2388 /* bring the link up in the watchdog, this could race with our first
2389 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2390 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2391 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2392 mod_timer(&adapter->watchdog_timer, jiffies);
2393 return 0;
2394}
2395
d4f80882
AV		 2396void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2397{
2398 WARN_ON(in_interrupt());
2399 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2400 msleep(1);
2401 ixgbe_down(adapter);
2402 ixgbe_up(adapter);
2403 clear_bit(__IXGBE_RESETTING, &adapter->state);
2404}
2405
9a799d71
AK		 2406int ixgbe_up(struct ixgbe_adapter *adapter)
2407{
2408 /* hardware has been reset, we need to reload some things */
2409 ixgbe_configure(adapter);
2410
4dd64df8
JB		 2411 ixgbe_napi_add_all(adapter);
2412
9a799d71
AK		 2413 return ixgbe_up_complete(adapter);
2414}
2415
2416void ixgbe_reset(struct ixgbe_adapter *adapter)
2417{
c44ade9e
JB		 2418 struct ixgbe_hw *hw = &adapter->hw;
2419 if (hw->mac.ops.init_hw(hw))
2420 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2421
2422 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2423 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2424
2425}
2426
9a799d71
AK		 2427/**
2428 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2429 * @adapter: board private structure
2430 * @rx_ring: ring to free buffers from
2431 **/
2432static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2433 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2434{
2435 struct pci_dev *pdev = adapter->pdev;
2436 unsigned long size;
2437 unsigned int i;
2438
2439 /* Free all the Rx ring sk_buffs */
2440
2441 for (i = 0; i < rx_ring->count; i++) {
2442 struct ixgbe_rx_buffer *rx_buffer_info;
2443
2444 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2445 if (rx_buffer_info->dma) {
2446 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2447 rx_ring->rx_buf_len,
2448 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2449 rx_buffer_info->dma = 0;
2450 }
2451 if (rx_buffer_info->skb) {
2452 dev_kfree_skb(rx_buffer_info->skb);
2453 rx_buffer_info->skb = NULL;
2454 }
2455 if (!rx_buffer_info->page)
2456 continue;
762f4c57
JB		 2457 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2458 PCI_DMA_FROMDEVICE);
9a799d71 2459 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2460 put_page(rx_buffer_info->page);
2461 rx_buffer_info->page = NULL;
762f4c57 2462 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2463 }
2464
2465 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2466 memset(rx_ring->rx_buffer_info, 0, size);
2467
2468 /* Zero out the descriptor ring */
2469 memset(rx_ring->desc, 0, rx_ring->size);
2470
2471 rx_ring->next_to_clean = 0;
2472 rx_ring->next_to_use = 0;
2473
9891ca7c
JB		 2474 if (rx_ring->head)
2475 writel(0, adapter->hw.hw_addr + rx_ring->head);
2476 if (rx_ring->tail)
2477 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2478}
2479
2480/**
2481 * ixgbe_clean_tx_ring - Free Tx Buffers
2482 * @adapter: board private structure
2483 * @tx_ring: ring to be cleaned
2484 **/
2485static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2486 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2487{
2488 struct ixgbe_tx_buffer *tx_buffer_info;
2489 unsigned long size;
2490 unsigned int i;
2491
2492 /* Free all the Tx ring sk_buffs */
2493
2494 for (i = 0; i < tx_ring->count; i++) {
2495 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2496 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2497 }
2498
2499 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2500 memset(tx_ring->tx_buffer_info, 0, size);
2501
2502 /* Zero out the descriptor ring */
2503 memset(tx_ring->desc, 0, tx_ring->size);
2504
2505 tx_ring->next_to_use = 0;
2506 tx_ring->next_to_clean = 0;
2507
9891ca7c
JB		 2508 if (tx_ring->head)
2509 writel(0, adapter->hw.hw_addr + tx_ring->head);
2510 if (tx_ring->tail)
2511 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2512}
2513
2514/**
021230d4 2515 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2516 * @adapter: board private structure
2517 **/
021230d4 2518static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2519{
2520 int i;
2521
021230d4
AV		 2522 for (i = 0; i < adapter->num_rx_queues; i++)
2523 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2524}
2525
2526/**
021230d4 2527 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2528 * @adapter: board private structure
2529 **/
021230d4 2530static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2531{
2532 int i;
2533
021230d4
AV		 2534 for (i = 0; i < adapter->num_tx_queues; i++)
2535 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2536}
2537
2538void ixgbe_down(struct ixgbe_adapter *adapter)
2539{
2540 struct net_device *netdev = adapter->netdev;
7f821875 2541 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2542 u32 rxctrl;
7f821875
JB		 2543 u32 txdctl;
2544 int i, j;
9a799d71
AK		 2545
2546 /* signal that we are down to the interrupt handler */
2547 set_bit(__IXGBE_DOWN, &adapter->state);
2548
2549 /* disable receives */
7f821875
JB		 2550 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2551 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2552
2553 netif_tx_disable(netdev);
2554
7f821875 2555 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2556 msleep(10);
2557
7f821875
JB		 2558 netif_tx_stop_all_queues(netdev);
2559
9a799d71
AK		 2560 ixgbe_irq_disable(adapter);
2561
021230d4 2562 ixgbe_napi_disable_all(adapter);
7f821875 2563
9a799d71 2564 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2565 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2566
7f821875
JB		 2567 /* disable transmits in the hardware now that interrupts are off */
2568 for (i = 0; i < adapter->num_tx_queues; i++) {
2569 j = adapter->tx_ring[i].reg_idx;
2570 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2571 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2572 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2573 }
88512539
PW		 2574 /* Disable the Tx DMA engine on 82599 */
2575 if (hw->mac.type == ixgbe_mac_82599EB)
2576 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2577 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2578 ~IXGBE_DMATXCTL_TE));
7f821875 2579
9a799d71 2580 netif_carrier_off(netdev);
9a799d71 2581
5dd2d332 2582#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2583 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2584 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2585 dca_remove_requester(&adapter->pdev->dev);
2586 }
2587
2588#endif
6f4a0e45
PL		 2589 if (!pci_channel_offline(adapter->pdev))
2590 ixgbe_reset(adapter);
9a799d71
AK		 2591 ixgbe_clean_all_tx_rings(adapter);
2592 ixgbe_clean_all_rx_rings(adapter);
2593
5dd2d332 2594#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2595 /* since we reset the hardware DCA settings were cleared */
2596 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2597 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2598 /* always use CB2 mode, difference is masked
2599 * in the CB driver */
b4617240 2600 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2601 ixgbe_setup_dca(adapter);
2602 }
2603#endif
9a799d71
AK		 2604}
2605
9a799d71 2606/**
021230d4
AV		 2607 * ixgbe_poll - NAPI Rx polling callback
2608 * @napi: structure for representing this polling device
2609 * @budget: how many packets driver is allowed to clean
2610 *
2611 * This function is used for legacy and MSI, NAPI mode
9a799d71 2612 **/
021230d4 2613static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2614{
9a1a69ad
JB		 2615 struct ixgbe_q_vector *q_vector =
2616 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2617 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2618 int tx_clean_complete, work_done = 0;
9a799d71 2619
5dd2d332 2620#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2621 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2622 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2623 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2624 }
2625#endif
2626
9a1a69ad 2627 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2628 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2629
9a1a69ad 2630 if (!tx_clean_complete)
d2c7ddd6
DM		 2631 work_done = budget;
2632
53e52c72
DM		 2633 /* If budget not fully consumed, exit the polling mode */
2634 if (work_done < budget) {
288379f0 2635 napi_complete(napi);
509ee935 2636 if (adapter->itr_setting & 1)
f494e8fa 2637 ixgbe_set_itr(adapter);
d4f80882 2638 if (!test_bit(__IXGBE_DOWN, &adapter->state))
22d5a71b 2639 ixgbe_irq_enable_queues(adapter);
9a799d71 2640 }
9a799d71
AK		 2641 return work_done;
2642}
2643
2644/**
2645 * ixgbe_tx_timeout - Respond to a Tx Hang
2646 * @netdev: network interface device structure
2647 **/
2648static void ixgbe_tx_timeout(struct net_device *netdev)
2649{
2650 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2651
2652 /* Do the reset outside of interrupt context */
2653 schedule_work(&adapter->reset_task);
2654}
2655
2656static void ixgbe_reset_task(struct work_struct *work)
2657{
2658 struct ixgbe_adapter *adapter;
2659 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2660
2f90b865
AD		 2661 /* If we're already down or resetting, just bail */
2662 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2663 test_bit(__IXGBE_RESETTING, &adapter->state))
2664 return;
2665
9a799d71
AK		 2666 adapter->tx_timeout_count++;
2667
d4f80882 2668 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2669}
2670
bc97114d
PWJ		 2671#ifdef CONFIG_IXGBE_DCB
2672static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2673{
bc97114d 2674 bool ret = false;
b9804972 2675
bc97114d
PWJ		 2676 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2677 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2678 adapter->num_rx_queues =
2679 adapter->ring_feature[RING_F_DCB].indices;
2680 adapter->num_tx_queues =
2681 adapter->ring_feature[RING_F_DCB].indices;
2682 ret = true;
2683 } else {
bc97114d
PWJ		 2684 ret = false;
2685 }
2f90b865 2686
bc97114d
PWJ		 2687 return ret;
2688}
2689#endif
2690
4df10466
JB		 2691/**
2692 * ixgbe_set_rss_queues: Allocate queues for RSS
2693 * @adapter: board private structure to initialize
2694 *
2695 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2696 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2697 *
2698 **/
bc97114d
PWJ		 2699static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2700{
2701 bool ret = false;
2702
2703 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2704 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2705 adapter->num_rx_queues =
2706 adapter->ring_feature[RING_F_RSS].indices;
2707 adapter->num_tx_queues =
2708 adapter->ring_feature[RING_F_RSS].indices;
2709 ret = true;
2710 } else {
bc97114d 2711 ret = false;
b9804972
JB		 2712 }
2713
bc97114d
PWJ		 2714 return ret;
2715}
2716
4df10466
JB		 2717/*
2718 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2719 * @adapter: board private structure to initialize
2720 *
2721 * This is the top level queue allocation routine. The order here is very
2722 * important, starting with the "most" number of features turned on at once,
2723 * and ending with the smallest set of features. This way large combinations
2724 * can be allocated if they're turned on, and smaller combinations are the
2725 * fallthrough conditions.
2726 *
2727 **/
bc97114d
PWJ		 2728static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2729{
2730 /* Start with base case */
2731 adapter->num_rx_queues = 1;
2732 adapter->num_tx_queues = 1;
2733
2734#ifdef CONFIG_IXGBE_DCB
2735 if (ixgbe_set_dcb_queues(adapter))
2736 return;
2737
2738#endif
2739 if (ixgbe_set_rss_queues(adapter))
2740 return;
b9804972
JB		 2741}
2742
021230d4 2743static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2744 int vectors)
021230d4
AV		 2745{
2746 int err, vector_threshold;
2747
2748 /* We'll want at least 3 (vector_threshold):
2749 * 1) TxQ[0] Cleanup
2750 * 2) RxQ[0] Cleanup
2751 * 3) Other (Link Status Change, etc.)
2752 * 4) TCP Timer (optional)
2753 */
2754 vector_threshold = MIN_MSIX_COUNT;
2755
2756 /* The more we get, the more we will assign to Tx/Rx Cleanup
2757 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2758 * Right now, we simply care about how many we'll get; we'll
2759 * set them up later while requesting irq's.
2760 */
2761 while (vectors >= vector_threshold) {
2762 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2763 vectors);
021230d4
AV		 2764 if (!err) /* Success in acquiring all requested vectors. */
2765 break;
2766 else if (err < 0)
2767 vectors = 0; /* Nasty failure, quit now */
2768 else /* err == number of vectors we should try again with */
2769 vectors = err;
2770 }
2771
2772 if (vectors < vector_threshold) {
2773 /* Can't allocate enough MSI-X interrupts? Oh well.
2774 * This just means we'll go with either a single MSI
2775 * vector or fall back to legacy interrupts.
2776 */
2777 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2778 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2779 kfree(adapter->msix_entries);
2780 adapter->msix_entries = NULL;
2f90b865 2781 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2782 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2783 ixgbe_set_num_queues(adapter);
021230d4
AV		 2784 } else {
2785 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2786 /*
2787 * Adjust for only the vectors we'll use, which is minimum
2788 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2789 * vectors we were allocated.
2790 */
2791 adapter->num_msix_vectors = min(vectors,
2792 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2793 }
2794}
2795
021230d4 2796/**
bc97114d 2797 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2798 * @adapter: board private structure to initialize
2799 *
bc97114d
PWJ		 2800 * Cache the descriptor ring offsets for RSS to the assigned rings.
2801 *
021230d4 2802 **/
bc97114d 2803static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2804{
bc97114d
PWJ		 2805 int i;
2806 bool ret = false;
2807
2808 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2809 for (i = 0; i < adapter->num_rx_queues; i++)
2810 adapter->rx_ring[i].reg_idx = i;
2811 for (i = 0; i < adapter->num_tx_queues; i++)
2812 adapter->tx_ring[i].reg_idx = i;
2813 ret = true;
2814 } else {
2815 ret = false;
2816 }
2817
2818 return ret;
2819}
2820
2821#ifdef CONFIG_IXGBE_DCB
2822/**
2823 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2824 * @adapter: board private structure to initialize
2825 *
2826 * Cache the descriptor ring offsets for DCB to the assigned rings.
2827 *
2828 **/
2829static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2830{
2831 int i;
2832 bool ret = false;
2833 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2834
2835 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2836 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2837 /* the number of queues is assumed to be symmetric */
2838 for (i = 0; i < dcb_i; i++) {
2839 adapter->rx_ring[i].reg_idx = i << 3;
2840 adapter->tx_ring[i].reg_idx = i << 2;
2841 }
bc97114d 2842 ret = true;
e8e26350
PW		 2843 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2844 for (i = 0; i < dcb_i; i++) {
2845 adapter->rx_ring[i].reg_idx = i << 4;
2846 adapter->tx_ring[i].reg_idx = i << 4;
2847 }
2848 ret = true;
bc97114d
PWJ		 2849 } else {
2850 ret = false;
021230d4 2851 }
bc97114d
PWJ		 2852 } else {
2853 ret = false;
021230d4 2854 }
bc97114d
PWJ		 2855
2856 return ret;
2857}
2858#endif
2859
2860/**
2861 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2862 * @adapter: board private structure to initialize
2863 *
2864 * Once we know the feature-set enabled for the device, we'll cache
2865 * the register offset the descriptor ring is assigned to.
2866 *
2867 * Note, the order the various feature calls is important. It must start with
2868 * the "most" features enabled at the same time, then trickle down to the
2869 * least amount of features turned on at once.
2870 **/
2871static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2872{
2873 /* start with default case */
2874 adapter->rx_ring[0].reg_idx = 0;
2875 adapter->tx_ring[0].reg_idx = 0;
2876
2877#ifdef CONFIG_IXGBE_DCB
2878 if (ixgbe_cache_ring_dcb(adapter))
2879 return;
2880
2881#endif
2882 if (ixgbe_cache_ring_rss(adapter))
2883 return;
021230d4
AV		 2884}
2885
9a799d71
AK		 2886/**
2887 * ixgbe_alloc_queues - Allocate memory for all rings
2888 * @adapter: board private structure to initialize
2889 *
2890 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 2891 * number of queues at compile-time. The polling_netdev array is
2892 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 2893 **/
2f90b865 2894static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2895{
2896 int i;
2897
2898 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2899 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2900 if (!adapter->tx_ring)
021230d4 2901 goto err_tx_ring_allocation;
9a799d71
AK		 2902
2903 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2904 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2905 if (!adapter->rx_ring)
2906 goto err_rx_ring_allocation;
9a799d71 2907
021230d4 2908 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2909 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2910 adapter->tx_ring[i].queue_index = i;
2911 }
b9804972 2912
9a799d71 2913 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2914 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2915 adapter->rx_ring[i].queue_index = i;
2916 }
2917
2918 ixgbe_cache_ring_register(adapter);
2919
2920 return 0;
2921
2922err_rx_ring_allocation:
2923 kfree(adapter->tx_ring);
2924err_tx_ring_allocation:
2925 return -ENOMEM;
2926}
2927
2928/**
2929 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2930 * @adapter: board private structure to initialize
2931 *
2932 * Attempt to configure the interrupts using the best available
2933 * capabilities of the hardware and the kernel.
2934 **/
feea6a57 2935static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2936{
2937 int err = 0;
2938 int vector, v_budget;
2939
2940 /*
2941 * It's easy to be greedy for MSI-X vectors, but it really
2942 * doesn't do us much good if we have a lot more vectors
2943 * than CPU's. So let's be conservative and only ask for
2944 * (roughly) twice the number of vectors as there are CPU's.
2945 */
2946 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2947 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2948
2949 /*
2950 * At the same time, hardware can only support a maximum of
2951 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2952 * we can easily reach upwards of 64 Rx descriptor queues and
2953 * 32 Tx queues. Thus, we cap it off in those rare cases where
2954 * the cpu count also exceeds our vector limit.
2955 */
2956 v_budget = min(v_budget, MAX_MSIX_COUNT);
2957
2958 /* A failure in MSI-X entry allocation isn't fatal, but it does
2959 * mean we disable MSI-X capabilities of the adapter. */
2960 adapter->msix_entries = kcalloc(v_budget,
b4617240 2961 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 2962 if (!adapter->msix_entries) {
2f90b865 2963 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2964 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2965 ixgbe_set_num_queues(adapter);
2966 kfree(adapter->tx_ring);
2967 kfree(adapter->rx_ring);
2968 err = ixgbe_alloc_queues(adapter);
2969 if (err) {
2970 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2971 "for queues\n");
021230d4
AV		 2972 goto out;
2973 }
2974
2975 goto try_msi;
2976 }
2977
2978 for (vector = 0; vector < v_budget; vector++)
2979 adapter->msix_entries[vector].entry = vector;
2980
2981 ixgbe_acquire_msix_vectors(adapter, v_budget);
2982
2983 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2984 goto out;
2985
2986try_msi:
2987 err = pci_enable_msi(adapter->pdev);
2988 if (!err) {
2989 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2990 } else {
2991 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2992 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2993 /* reset err */
2994 err = 0;
2995 }
2996
2997out:
30eba97a 2998 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2999 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 3000
3001 return err;
3002}
3003
2f90b865 3004void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3005{
3006 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3007 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3008 pci_disable_msix(adapter->pdev);
3009 kfree(adapter->msix_entries);
3010 adapter->msix_entries = NULL;
3011 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3012 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3013 pci_disable_msi(adapter->pdev);
3014 }
3015 return;
3016}
3017
3018/**
3019 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3020 * @adapter: board private structure to initialize
3021 *
3022 * We determine which interrupt scheme to use based on...
3023 * - Kernel support (MSI, MSI-X)
3024 * - which can be user-defined (via MODULE_PARAM)
3025 * - Hardware queue count (num_*_queues)
3026 * - defined by miscellaneous hardware support/features (RSS, etc.)
3027 **/
2f90b865 3028int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3029{
3030 int err;
3031
3032 /* Number of supported queues */
3033 ixgbe_set_num_queues(adapter);
3034
3035 err = ixgbe_alloc_queues(adapter);
3036 if (err) {
3037 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3038 goto err_alloc_queues;
3039 }
3040
3041 err = ixgbe_set_interrupt_capability(adapter);
3042 if (err) {
3043 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3044 goto err_set_interrupt;
9a799d71
AK		 3045 }
3046
021230d4 3047 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3048 "Tx Queue count = %u\n",
3049 (adapter->num_rx_queues > 1) ? "Enabled" :
3050 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3051
3052 set_bit(__IXGBE_DOWN, &adapter->state);
3053
9a799d71 3054 return 0;
021230d4
AV		 3055
3056err_set_interrupt:
3057 kfree(adapter->tx_ring);
3058 kfree(adapter->rx_ring);
3059err_alloc_queues:
3060 return err;
9a799d71
AK		 3061}
3062
c4900be0
DS		 3063/**
3064 * ixgbe_sfp_timer - worker thread to find a missing module
3065 * @data: pointer to our adapter struct
3066 **/
3067static void ixgbe_sfp_timer(unsigned long data)
3068{
3069 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3070
4df10466
JB		 3071 /*
3072 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3073 * delays that sfp+ detection requires
3074 */
3075 schedule_work(&adapter->sfp_task);
3076}
3077
3078/**
3079 * ixgbe_sfp_task - worker thread to find a missing module
3080 * @work: pointer to work_struct containing our data
3081 **/
3082static void ixgbe_sfp_task(struct work_struct *work)
3083{
3084 struct ixgbe_adapter *adapter = container_of(work,
3085 struct ixgbe_adapter,
3086 sfp_task);
3087 struct ixgbe_hw *hw = &adapter->hw;
3088
3089 if ((hw->phy.type == ixgbe_phy_nl) &&
3090 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3091 s32 ret = hw->phy.ops.identify_sfp(hw);
3092 if (ret)
3093 goto reschedule;
3094 ret = hw->phy.ops.reset(hw);
3095 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3096 DPRINTK(PROBE, ERR, "failed to initialize because an "
3097 "unsupported SFP+ module type was detected.\n"
3098 "Reload the driver after installing a "
3099 "supported module.\n");
3100 unregister_netdev(adapter->netdev);
3101 } else {
3102 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3103 hw->phy.sfp_type);
3104 }
3105 /* don't need this routine any more */
3106 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3107 }
3108 return;
3109reschedule:
3110 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3111 mod_timer(&adapter->sfp_timer,
3112 round_jiffies(jiffies + (2 * HZ)));
3113}
3114
9a799d71
AK		 3115/**
3116 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3117 * @adapter: board private structure to initialize
3118 *
3119 * ixgbe_sw_init initializes the Adapter private data structure.
3120 * Fields are initialized based on PCI device information and
3121 * OS network device settings (MTU size).
3122 **/
3123static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3124{
3125 struct ixgbe_hw *hw = &adapter->hw;
3126 struct pci_dev *pdev = adapter->pdev;
021230d4 3127 unsigned int rss;
7a6b6f51 3128#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3129 int j;
3130 struct tc_configuration *tc;
3131#endif
021230d4 3132
c44ade9e
JB		 3133 /* PCI config space info */
3134
3135 hw->vendor_id = pdev->vendor;
3136 hw->device_id = pdev->device;
3137 hw->revision_id = pdev->revision;
3138 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3139 hw->subsystem_device_id = pdev->subsystem_device;
3140
021230d4
AV		 3141 /* Set capability flags */
3142 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3143 adapter->ring_feature[RING_F_RSS].indices = rss;
3144 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3145 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3146 if (hw->mac.type == ixgbe_mac_82598EB)
3147 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3148 else if (hw->mac.type == ixgbe_mac_82599EB)
3149 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
2f90b865 3150
7a6b6f51 3151#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3152 /* Configure DCB traffic classes */
3153 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3154 tc = &adapter->dcb_cfg.tc_config[j];
3155 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3156 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3157 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3158 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3159 tc->dcb_pfc = pfc_disabled;
3160 }
3161 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3162 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3163 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3164 adapter->dcb_cfg.round_robin_enable = false;
3165 adapter->dcb_set_bitmap = 0x00;
3166 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3167 adapter->ring_feature[RING_F_DCB].indices);
3168
3169#endif
9a799d71
AK		 3170
3171 /* default flow control settings */
cd7664f6 3172 hw->fc.requested_mode = ixgbe_fc_full;
2b9ade93
JB		 3173 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3174 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3175 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3176 hw->fc.send_xon = true;
9a799d71 3177
30efa5a3
JB		 3178 /* enable itr by default in dynamic mode */
3179 adapter->itr_setting = 1;
3180 adapter->eitr_param = 20000;
3181
3182 /* set defaults for eitr in MegaBytes */
3183 adapter->eitr_low = 10;
3184 adapter->eitr_high = 20;
3185
3186 /* set default ring sizes */
3187 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3188 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3189
9a799d71 3190 /* initialize eeprom parameters */
c44ade9e 3191 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3192 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3193 return -EIO;
3194 }
3195
021230d4 3196 /* enable rx csum by default */
9a799d71
AK		 3197 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3198
9a799d71
AK		 3199 set_bit(__IXGBE_DOWN, &adapter->state);
3200
3201 return 0;
3202}
3203
3204/**
3205 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3206 * @adapter: board private structure
3a581073 3207 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3208 *
3209 * Return 0 on success, negative on failure
3210 **/
3211int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3212 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3213{
3214 struct pci_dev *pdev = adapter->pdev;
3215 int size;
3216
3a581073
JB		 3217 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3218 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3219 if (!tx_ring->tx_buffer_info)
3220 goto err;
3a581073 3221 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3222
3223 /* round up to nearest 4K */
12207e49 3224 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3225 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3226
3a581073
JB		 3227 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3228 &tx_ring->dma);
e01c31a5
JB		 3229 if (!tx_ring->desc)
3230 goto err;
9a799d71 3231
3a581073
JB		 3232 tx_ring->next_to_use = 0;
3233 tx_ring->next_to_clean = 0;
3234 tx_ring->work_limit = tx_ring->count;
9a799d71 3235 return 0;
e01c31a5
JB		 3236
3237err:
3238 vfree(tx_ring->tx_buffer_info);
3239 tx_ring->tx_buffer_info = NULL;
3240 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3241 "descriptor ring\n");
3242 return -ENOMEM;
9a799d71
AK		 3243}
3244
69888674
AD		 3245/**
3246 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3247 * @adapter: board private structure
3248 *
3249 * If this function returns with an error, then it's possible one or
3250 * more of the rings is populated (while the rest are not). It is the
3251 * callers duty to clean those orphaned rings.
3252 *
3253 * Return 0 on success, negative on failure
3254 **/
3255static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3256{
3257 int i, err = 0;
3258
3259 for (i = 0; i < adapter->num_tx_queues; i++) {
3260 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3261 if (!err)
3262 continue;
3263 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3264 break;
3265 }
3266
3267 return err;
3268}
3269
9a799d71
AK		 3270/**
3271 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3272 * @adapter: board private structure
3a581073 3273 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3274 *
3275 * Returns 0 on success, negative on failure
3276 **/
3277int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3278 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3279{
3280 struct pci_dev *pdev = adapter->pdev;
021230d4 3281 int size;
9a799d71 3282
3a581073
JB		 3283 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3284 rx_ring->rx_buffer_info = vmalloc(size);
3285 if (!rx_ring->rx_buffer_info) {
9a799d71 3286 DPRINTK(PROBE, ERR,
b4617240 3287 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3288 goto alloc_failed;
9a799d71 3289 }
3a581073 3290 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3291
9a799d71 3292 /* Round up to nearest 4K */
3a581073
JB		 3293 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3294 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3295
3a581073 3296 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3297
3a581073 3298 if (!rx_ring->desc) {
9a799d71 3299 DPRINTK(PROBE, ERR,
b4617240 3300 "Memory allocation failed for the rx desc ring\n");
3a581073 3301 vfree(rx_ring->rx_buffer_info);
177db6ff 3302 goto alloc_failed;
9a799d71
AK		 3303 }
3304
3a581073
JB		 3305 rx_ring->next_to_clean = 0;
3306 rx_ring->next_to_use = 0;
9a799d71
AK		 3307
3308 return 0;
177db6ff
MC		 3309
3310alloc_failed:
177db6ff 3311 return -ENOMEM;
9a799d71
AK		 3312}
3313
69888674
AD		 3314/**
3315 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3316 * @adapter: board private structure
3317 *
3318 * If this function returns with an error, then it's possible one or
3319 * more of the rings is populated (while the rest are not). It is the
3320 * callers duty to clean those orphaned rings.
3321 *
3322 * Return 0 on success, negative on failure
3323 **/
3324
3325static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3326{
3327 int i, err = 0;
3328
3329 for (i = 0; i < adapter->num_rx_queues; i++) {
3330 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3331 if (!err)
3332 continue;
3333 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3334 break;
3335 }
3336
3337 return err;
3338}
3339
9a799d71
AK		 3340/**
3341 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3342 * @adapter: board private structure
3343 * @tx_ring: Tx descriptor ring for a specific queue
3344 *
3345 * Free all transmit software resources
3346 **/
c431f97e
JB		 3347void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3348 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3349{
3350 struct pci_dev *pdev = adapter->pdev;
3351
3352 ixgbe_clean_tx_ring(adapter, tx_ring);
3353
3354 vfree(tx_ring->tx_buffer_info);
3355 tx_ring->tx_buffer_info = NULL;
3356
3357 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3358
3359 tx_ring->desc = NULL;
3360}
3361
3362/**
3363 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3364 * @adapter: board private structure
3365 *
3366 * Free all transmit software resources
3367 **/
3368static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3369{
3370 int i;
3371
3372 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3373 if (adapter->tx_ring[i].desc)
3374 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3375}
3376
3377/**
b4617240 3378 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3379 * @adapter: board private structure
3380 * @rx_ring: ring to clean the resources from
3381 *
3382 * Free all receive software resources
3383 **/
c431f97e
JB		 3384void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3385 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3386{
3387 struct pci_dev *pdev = adapter->pdev;
3388
3389 ixgbe_clean_rx_ring(adapter, rx_ring);
3390
3391 vfree(rx_ring->rx_buffer_info);
3392 rx_ring->rx_buffer_info = NULL;
3393
3394 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3395
3396 rx_ring->desc = NULL;
3397}
3398
3399/**
3400 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3401 * @adapter: board private structure
3402 *
3403 * Free all receive software resources
3404 **/
3405static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3406{
3407 int i;
3408
3409 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3410 if (adapter->rx_ring[i].desc)
3411 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3412}
3413
9a799d71
AK		 3414/**
3415 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3416 * @netdev: network interface device structure
3417 * @new_mtu: new value for maximum frame size
3418 *
3419 * Returns 0 on success, negative on failure
3420 **/
3421static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3422{
3423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3424 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3425
42c783c5
JB		 3426 /* MTU < 68 is an error and causes problems on some kernels */
3427 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3428 return -EINVAL;
3429
021230d4 3430 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3431 netdev->mtu, new_mtu);
021230d4 3432 /* must set new MTU before calling down or up */
9a799d71
AK		 3433 netdev->mtu = new_mtu;
3434
d4f80882
AV		 3435 if (netif_running(netdev))
3436 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3437
3438 return 0;
3439}
3440
3441/**
3442 * ixgbe_open - Called when a network interface is made active
3443 * @netdev: network interface device structure
3444 *
3445 * Returns 0 on success, negative value on failure
3446 *
3447 * The open entry point is called when a network interface is made
3448 * active by the system (IFF_UP). At this point all resources needed
3449 * for transmit and receive operations are allocated, the interrupt
3450 * handler is registered with the OS, the watchdog timer is started,
3451 * and the stack is notified that the interface is ready.
3452 **/
3453static int ixgbe_open(struct net_device *netdev)
3454{
3455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3456 int err;
4bebfaa5
AK		 3457
3458 /* disallow open during test */
3459 if (test_bit(__IXGBE_TESTING, &adapter->state))
3460 return -EBUSY;
9a799d71 3461
9a799d71
AK		 3462 /* allocate transmit descriptors */
3463 err = ixgbe_setup_all_tx_resources(adapter);
3464 if (err)
3465 goto err_setup_tx;
3466
9a799d71
AK		 3467 /* allocate receive descriptors */
3468 err = ixgbe_setup_all_rx_resources(adapter);
3469 if (err)
3470 goto err_setup_rx;
3471
3472 ixgbe_configure(adapter);
3473
4dd64df8
JB		 3474 ixgbe_napi_add_all(adapter);
3475
021230d4 3476 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3477 if (err)
3478 goto err_req_irq;
3479
9a799d71
AK		 3480 err = ixgbe_up_complete(adapter);
3481 if (err)
3482 goto err_up;
3483
d55b53ff
JK		 3484 netif_tx_start_all_queues(netdev);
3485
9a799d71
AK		 3486 return 0;
3487
3488err_up:
5eba3699 3489 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3490 ixgbe_free_irq(adapter);
3491err_req_irq:
3492 ixgbe_free_all_rx_resources(adapter);
3493err_setup_rx:
3494 ixgbe_free_all_tx_resources(adapter);
3495err_setup_tx:
3496 ixgbe_reset(adapter);
3497
3498 return err;
3499}
3500
3501/**
3502 * ixgbe_close - Disables a network interface
3503 * @netdev: network interface device structure
3504 *
3505 * Returns 0, this is not allowed to fail
3506 *
3507 * The close entry point is called when an interface is de-activated
3508 * by the OS. The hardware is still under the drivers control, but
3509 * needs to be disabled. A global MAC reset is issued to stop the
3510 * hardware, and all transmit and receive resources are freed.
3511 **/
3512static int ixgbe_close(struct net_device *netdev)
3513{
3514 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3515
3516 ixgbe_down(adapter);
3517 ixgbe_free_irq(adapter);
3518
3519 ixgbe_free_all_tx_resources(adapter);
3520 ixgbe_free_all_rx_resources(adapter);
3521
5eba3699 3522 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3523
3524 return 0;
3525}
3526
b3c8b4ba
AD		 3527/**
3528 * ixgbe_napi_add_all - prep napi structs for use
3529 * @adapter: private struct
4dd64df8 3530 *
b3c8b4ba
AD		 3531 * helper function to napi_add each possible q_vector->napi
3532 */
2f90b865 3533void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3534{
3535 int q_idx, q_vectors;
7adf1525 3536 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3537 int (*poll)(struct napi_struct *, int);
3538
7adf1525
PWJ		 3539 /* check if we already have our netdev->napi_list populated */
3540 if (&netdev->napi_list != netdev->napi_list.next)
3541 return;
3542
b3c8b4ba
AD		 3543 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3544 poll = &ixgbe_clean_rxonly;
3545 /* Only enable as many vectors as we have rx queues. */
3546 q_vectors = adapter->num_rx_queues;
3547 } else {
3548 poll = &ixgbe_poll;
3549 /* only one q_vector for legacy modes */
3550 q_vectors = 1;
3551 }
3552
3553 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3554 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3555 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3556 }
3557}
3558
2f90b865 3559void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3560{
3561 int q_idx;
3562 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3563
3564 /* legacy and MSI only use one vector */
3565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3566 q_vectors = 1;
3567
3568 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3569 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3570 if (!q_vector->rxr_count)
3571 continue;
3572 netif_napi_del(&q_vector->napi);
3573 }
3574}
3575
3576#ifdef CONFIG_PM
3577static int ixgbe_resume(struct pci_dev *pdev)
3578{
3579 struct net_device *netdev = pci_get_drvdata(pdev);
3580 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3581 u32 err;
3582
3583 pci_set_power_state(pdev, PCI_D0);
3584 pci_restore_state(pdev);
3585 err = pci_enable_device(pdev);
3586 if (err) {
69888674 3587 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3588 "suspend\n");
3589 return err;
3590 }
3591 pci_set_master(pdev);
3592
3593 pci_enable_wake(pdev, PCI_D3hot, 0);
3594 pci_enable_wake(pdev, PCI_D3cold, 0);
3595
3596 err = ixgbe_init_interrupt_scheme(adapter);
3597 if (err) {
3598 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3599 "device\n");
3600 return err;
3601 }
3602
b3c8b4ba
AD		 3603 ixgbe_reset(adapter);
3604
3605 if (netif_running(netdev)) {
3606 err = ixgbe_open(adapter->netdev);
3607 if (err)
3608 return err;
3609 }
3610
3611 netif_device_attach(netdev);
3612
3613 return 0;
3614}
3615
3616#endif /* CONFIG_PM */
3617static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3618{
3619 struct net_device *netdev = pci_get_drvdata(pdev);
3620 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3621 struct ixgbe_hw *hw = &adapter->hw;
3622 u32 ctrl, fctrl;
3623 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3624#ifdef CONFIG_PM
3625 int retval = 0;
3626#endif
3627
3628 netif_device_detach(netdev);
3629
3630 if (netif_running(netdev)) {
3631 ixgbe_down(adapter);
3632 ixgbe_free_irq(adapter);
3633 ixgbe_free_all_tx_resources(adapter);
3634 ixgbe_free_all_rx_resources(adapter);
3635 }
3636 ixgbe_reset_interrupt_capability(adapter);
3637 ixgbe_napi_del_all(adapter);
7adf1525 3638 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3639 kfree(adapter->tx_ring);
3640 kfree(adapter->rx_ring);
3641
3642#ifdef CONFIG_PM
3643 retval = pci_save_state(pdev);
3644 if (retval)
3645 return retval;
4df10466 3646
b3c8b4ba 3647#endif
e8e26350
PW		 3648 if (wufc) {
3649 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3650
e8e26350
PW		 3651 /* turn on all-multi mode if wake on multicast is enabled */
3652 if (wufc & IXGBE_WUFC_MC) {
3653 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3654 fctrl |= IXGBE_FCTRL_MPE;
3655 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3656 }
3657
3658 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3659 ctrl |= IXGBE_CTRL_GIO_DIS;
3660 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3661
3662 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3663 } else {
3664 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3665 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3666 }
3667
3668 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3669 pci_enable_wake(pdev, PCI_D3hot, 1);
3670 pci_enable_wake(pdev, PCI_D3cold, 1);
3671 } else {
3672 pci_enable_wake(pdev, PCI_D3hot, 0);
3673 pci_enable_wake(pdev, PCI_D3cold, 0);
3674 }
b3c8b4ba
AD		 3675
3676 ixgbe_release_hw_control(adapter);
3677
3678 pci_disable_device(pdev);
3679
3680 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3681
3682 return 0;
3683}
3684
3685static void ixgbe_shutdown(struct pci_dev *pdev)
3686{
3687 ixgbe_suspend(pdev, PMSG_SUSPEND);
3688}
3689
9a799d71
AK		 3690/**
3691 * ixgbe_update_stats - Update the board statistics counters.
3692 * @adapter: board private structure
3693 **/
3694void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3695{
3696 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3697 u64 total_mpc = 0;
3698 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3699
d51019a4
PW		 3700 if (hw->mac.type == ixgbe_mac_82599EB) {
3701 for (i = 0; i < 16; i++)
3702 adapter->hw_rx_no_dma_resources +=
3703 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3704 }
3705
9a799d71 3706 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3707 for (i = 0; i < 8; i++) {
3708 /* for packet buffers not used, the register should read 0 */
3709 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3710 missed_rx += mpc;
3711 adapter->stats.mpc[i] += mpc;
3712 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3713 if (hw->mac.type == ixgbe_mac_82598EB)
3714 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3715 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3716 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3717 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3718 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3719 if (hw->mac.type == ixgbe_mac_82599EB) {
3720 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3721 IXGBE_PXONRXCNT(i));
3722 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3723 IXGBE_PXOFFRXCNT(i));
3724 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3725 } else {
3726 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3727 IXGBE_PXONRXC(i));
3728 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3729 IXGBE_PXOFFRXC(i));
3730 }
2f90b865
AD		 3731 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3732 IXGBE_PXONTXC(i));
2f90b865 3733 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3734 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3735 }
3736 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3737 /* work around hardware counting issue */
3738 adapter->stats.gprc -= missed_rx;
3739
3740 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3741 if (hw->mac.type == ixgbe_mac_82599EB) {
3742 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3743 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3744 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3745 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3746 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3747 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3748 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3749 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3750 } else {
3751 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3752 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3753 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3754 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3755 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3756 }
9a799d71
AK		 3757 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3758 adapter->stats.bprc += bprc;
3759 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3760 if (hw->mac.type == ixgbe_mac_82598EB)
3761 adapter->stats.mprc -= bprc;
9a799d71
AK		 3762 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3763 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3764 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3765 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3766 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3767 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3768 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3769 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3770 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3771 adapter->stats.lxontxc += lxon;
3772 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3773 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3774 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3775 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3776 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3777 /*
3778 * 82598 errata - tx of flow control packets is included in tx counters
3779 */
3780 xon_off_tot = lxon + lxoff;
3781 adapter->stats.gptc -= xon_off_tot;
3782 adapter->stats.mptc -= xon_off_tot;
3783 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3784 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3785 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3786 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3787 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3788 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3789 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3790 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3791 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3792 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3793 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3794 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3795 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3796
3797 /* Fill out the OS statistics structure */
9a799d71
AK		 3798 adapter->net_stats.multicast = adapter->stats.mprc;
3799
3800 /* Rx Errors */
3801 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3802 adapter->stats.rlec;
9a799d71
AK		 3803 adapter->net_stats.rx_dropped = 0;
3804 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3805 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3806 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3807}
3808
3809/**
3810 * ixgbe_watchdog - Timer Call-back
3811 * @data: pointer to adapter cast into an unsigned long
3812 **/
3813static void ixgbe_watchdog(unsigned long data)
3814{
3815 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3816 struct ixgbe_hw *hw = &adapter->hw;
3817
3818 /* Do the watchdog outside of interrupt context due to the lovely
3819 * delays that some of the newer hardware requires */
3820 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 3821 u64 eics = 0;
3822 int i;
3823
3824 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
3825 eics |= (1 << i);
3826
cf8280ee 3827 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 3828 switch (hw->mac.type) {
3829 case ixgbe_mac_82598EB:
3830 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3831 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
3832 } else {
3833 /*
3834 * for legacy and MSI interrupts don't set any
3835 * bits that are enabled for EIAM, because this
3836 * operation would set *both* EIMS and EICS for
3837 * any bit in EIAM
3838 */
3839 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3840 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3841 }
3842 break;
3843 case ixgbe_mac_82599EB:
3844 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3845 /*
3846 * EICS(0..15) first 0-15 q vectors
3847 * EICS[1] (16..31) q vectors 16-31
3848 * EICS[2] (0..31) q vectors 32-63
3849 */
3850 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3851 (u32)(eics & 0xFFFF));
3852 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
3853 (u32)(eics & 0xFFFF0000));
3854 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(2),
3855 (u32)(eics >> 32));
3856 } else {
3857 /*
3858 * for legacy and MSI interrupts don't set any
3859 * bits that are enabled for EIAM, because this
3860 * operation would set *both* EIMS and EICS for
3861 * any bit in EIAM
3862 */
3863 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3864 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3865 }
3866 break;
3867 default:
3868 break;
cf8280ee
JB		 3869 }
3870 /* Reset the timer */
3871 mod_timer(&adapter->watchdog_timer,
3872 round_jiffies(jiffies + 2 * HZ));
3873 }
9a799d71 3874
cf8280ee
JB		 3875 schedule_work(&adapter->watchdog_task);
3876}
3877
e8e26350
PW		 3878/**
3879 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3880 * @work: pointer to work_struct containing our data
3881 **/
3882static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3883{
3884 struct ixgbe_adapter *adapter = container_of(work,
3885 struct ixgbe_adapter,
3886 multispeed_fiber_task);
3887 struct ixgbe_hw *hw = &adapter->hw;
3888 u32 autoneg;
3889
3890 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3891 if (hw->mac.ops.get_link_capabilities)
3892 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3893 &hw->mac.autoneg);
3894 if (hw->mac.ops.setup_link_speed)
3895 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3896 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3897 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3898}
3899
3900/**
3901 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3902 * @work: pointer to work_struct containing our data
3903 **/
3904static void ixgbe_sfp_config_module_task(struct work_struct *work)
3905{
3906 struct ixgbe_adapter *adapter = container_of(work,
3907 struct ixgbe_adapter,
3908 sfp_config_module_task);
3909 struct ixgbe_hw *hw = &adapter->hw;
3910 u32 err;
3911
3912 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3913 err = hw->phy.ops.identify_sfp(hw);
3914 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3915 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3916 ixgbe_down(adapter);
3917 return;
3918 }
3919 hw->mac.ops.setup_sfp(hw);
3920
3921 if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)
3922 /* This will also work for DA Twinax connections */
3923 schedule_work(&adapter->multispeed_fiber_task);
3924 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3925}
3926
cf8280ee 3927/**
69888674
AD		 3928 * ixgbe_watchdog_task - worker thread to bring link up
3929 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3930 **/
3931static void ixgbe_watchdog_task(struct work_struct *work)
3932{
3933 struct ixgbe_adapter *adapter = container_of(work,
3934 struct ixgbe_adapter,
3935 watchdog_task);
3936 struct net_device *netdev = adapter->netdev;
3937 struct ixgbe_hw *hw = &adapter->hw;
3938 u32 link_speed = adapter->link_speed;
3939 bool link_up = adapter->link_up;
3940
3941 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3942
3943 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3944 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3945 if (link_up ||
3946 time_after(jiffies, (adapter->link_check_timeout +
3947 IXGBE_TRY_LINK_TIMEOUT))) {
3948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3949 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3950 }
3951 adapter->link_up = link_up;
3952 adapter->link_speed = link_speed;
3953 }
9a799d71
AK		 3954
3955 if (link_up) {
3956 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 3957 bool flow_rx, flow_tx;
3958
3959 if (hw->mac.type == ixgbe_mac_82599EB) {
3960 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3961 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3962 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
3963 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
3964 } else {
3965 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3966 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3967 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
3968 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
3969 }
3970
a46e534b
JK		 3971 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3972 "Flow Control: %s\n",
3973 netdev->name,
3974 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3975 "10 Gbps" :
3976 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3977 "1 Gbps" : "unknown speed")),
e8e26350
PW		 3978 ((flow_rx && flow_tx) ? "RX/TX" :
3979 (flow_rx ? "RX" :
3980 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 3981
3982 netif_carrier_on(netdev);
9a799d71
AK		 3983 } else {
3984 /* Force detection of hung controller */
3985 adapter->detect_tx_hung = true;
3986 }
3987 } else {
cf8280ee
JB		 3988 adapter->link_up = false;
3989 adapter->link_speed = 0;
9a799d71 3990 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 3991 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3992 netdev->name);
9a799d71 3993 netif_carrier_off(netdev);
9a799d71
AK		 3994 }
3995 }
3996
3997 ixgbe_update_stats(adapter);
cf8280ee 3998 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3999}
4000
9a799d71 4001static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4002 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4003 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4004{
4005 struct ixgbe_adv_tx_context_desc *context_desc;
4006 unsigned int i;
4007 int err;
4008 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4009 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4010 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4011
4012 if (skb_is_gso(skb)) {
4013 if (skb_header_cloned(skb)) {
4014 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4015 if (err)
4016 return err;
4017 }
4018 l4len = tcp_hdrlen(skb);
4019 *hdr_len += l4len;
4020
8327d000 4021 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4022 struct iphdr *iph = ip_hdr(skb);
4023 iph->tot_len = 0;
4024 iph->check = 0;
4025 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4026 iph->daddr, 0,
4027 IPPROTO_TCP,
4028 0);
9a799d71
AK		 4029 adapter->hw_tso_ctxt++;
4030 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4031 ipv6_hdr(skb)->payload_len = 0;
4032 tcp_hdr(skb)->check =
4033 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4034 &ipv6_hdr(skb)->daddr,
4035 0, IPPROTO_TCP, 0);
9a799d71
AK		 4036 adapter->hw_tso6_ctxt++;
4037 }
4038
4039 i = tx_ring->next_to_use;
4040
4041 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4042 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4043
4044 /* VLAN MACLEN IPLEN */
4045 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4046 vlan_macip_lens |=
4047 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4048 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4049 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4050 *hdr_len += skb_network_offset(skb);
4051 vlan_macip_lens |=
4052 (skb_transport_header(skb) - skb_network_header(skb));
4053 *hdr_len +=
4054 (skb_transport_header(skb) - skb_network_header(skb));
4055 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4056 context_desc->seqnum_seed = 0;
4057
4058 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4059 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4060 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4061
8327d000 4062 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4063 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4064 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4065 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4066
4067 /* MSS L4LEN IDX */
9f8cdf4f 4068 mss_l4len_idx =
9a799d71
AK		 4069 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4070 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4071 /* use index 1 for TSO */
4072 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4073 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4074
4075 tx_buffer_info->time_stamp = jiffies;
4076 tx_buffer_info->next_to_watch = i;
4077
4078 i++;
4079 if (i == tx_ring->count)
4080 i = 0;
4081 tx_ring->next_to_use = i;
4082
4083 return true;
4084 }
4085 return false;
4086}
4087
4088static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4089 struct ixgbe_ring *tx_ring,
4090 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4091{
4092 struct ixgbe_adv_tx_context_desc *context_desc;
4093 unsigned int i;
4094 struct ixgbe_tx_buffer *tx_buffer_info;
4095 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4096
4097 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4098 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4099 i = tx_ring->next_to_use;
4100 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4101 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4102
4103 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4104 vlan_macip_lens |=
4105 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4106 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4107 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4108 if (skb->ip_summed == CHECKSUM_PARTIAL)
4109 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4110 skb_network_header(skb));
9a799d71
AK		 4111
4112 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4113 context_desc->seqnum_seed = 0;
4114
4115 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4116 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4117
4118 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4119 switch (skb->protocol) {
09640e63 4120 case cpu_to_be16(ETH_P_IP):
9a799d71 4121 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4122 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4123 type_tucmd_mlhl |=
b4617240 4124 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4125 break;
09640e63 4126 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4127 /* XXX what about other V6 headers?? */
4128 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4129 type_tucmd_mlhl |=
b4617240 4130 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4131 break;
41825d71
AK		 4132 default:
4133 if (unlikely(net_ratelimit())) {
4134 DPRINTK(PROBE, WARNING,
4135 "partial checksum but proto=%x!\n",
4136 skb->protocol);
4137 }
4138 break;
4139 }
9a799d71
AK		 4140 }
4141
4142 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4143 /* use index zero for tx checksum offload */
9a799d71
AK		 4144 context_desc->mss_l4len_idx = 0;
4145
4146 tx_buffer_info->time_stamp = jiffies;
4147 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4148
9a799d71
AK		 4149 adapter->hw_csum_tx_good++;
4150 i++;
4151 if (i == tx_ring->count)
4152 i = 0;
4153 tx_ring->next_to_use = i;
4154
4155 return true;
4156 }
9f8cdf4f 4157
9a799d71
AK		 4158 return false;
4159}
4160
4161static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4162 struct ixgbe_ring *tx_ring,
4163 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4164{
4165 struct ixgbe_tx_buffer *tx_buffer_info;
4166 unsigned int len = skb->len;
4167 unsigned int offset = 0, size, count = 0, i;
4168 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4169 unsigned int f;
4170
4171 len -= skb->data_len;
4172
4173 i = tx_ring->next_to_use;
4174
4175 while (len) {
4176 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4177 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4178
4179 tx_buffer_info->length = size;
4180 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 4181 skb->data + offset,
4182 size, PCI_DMA_TODEVICE);
9a799d71
AK		 4183 tx_buffer_info->time_stamp = jiffies;
4184 tx_buffer_info->next_to_watch = i;
4185
4186 len -= size;
4187 offset += size;
4188 count++;
4189 i++;
4190 if (i == tx_ring->count)
4191 i = 0;
4192 }
4193
4194 for (f = 0; f < nr_frags; f++) {
4195 struct skb_frag_struct *frag;
4196
4197 frag = &skb_shinfo(skb)->frags[f];
4198 len = frag->size;
4199 offset = frag->page_offset;
4200
4201 while (len) {
4202 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4203 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4204
4205 tx_buffer_info->length = size;
4206 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 4207 frag->page,
4208 offset,
4209 size,
4210 PCI_DMA_TODEVICE);
9a799d71
AK		 4211 tx_buffer_info->time_stamp = jiffies;
4212 tx_buffer_info->next_to_watch = i;
4213
4214 len -= size;
4215 offset += size;
4216 count++;
4217 i++;
4218 if (i == tx_ring->count)
4219 i = 0;
4220 }
4221 }
4222 if (i == 0)
4223 i = tx_ring->count - 1;
4224 else
4225 i = i - 1;
4226 tx_ring->tx_buffer_info[i].skb = skb;
4227 tx_ring->tx_buffer_info[first].next_to_watch = i;
4228
4229 return count;
4230}
4231
4232static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4233 struct ixgbe_ring *tx_ring,
4234 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4235{
4236 union ixgbe_adv_tx_desc *tx_desc = NULL;
4237 struct ixgbe_tx_buffer *tx_buffer_info;
4238 u32 olinfo_status = 0, cmd_type_len = 0;
4239 unsigned int i;
4240 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4241
4242 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4243
4244 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4245
4246 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4247 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4248
4249 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4250 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4251
4252 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4253 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4254
4eeae6fd
PW		 4255 /* use index 1 context for tso */
4256 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4257 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4258 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4259 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4260
4261 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4262 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4263 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4264
4265 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4266
4267 i = tx_ring->next_to_use;
4268 while (count--) {
4269 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4270 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4271 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4272 tx_desc->read.cmd_type_len =
b4617240 4273 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4274 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4275 i++;
4276 if (i == tx_ring->count)
4277 i = 0;
4278 }
4279
4280 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4281
4282 /*
4283 * Force memory writes to complete before letting h/w
4284 * know there are new descriptors to fetch. (Only
4285 * applicable for weak-ordered memory model archs,
4286 * such as IA-64).
4287 */
4288 wmb();
4289
4290 tx_ring->next_to_use = i;
4291 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4292}
4293
e092be60 4294static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4295 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4296{
4297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4298
30eba97a 4299 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4300 /* Herbert's original patch had:
4301 * smp_mb__after_netif_stop_queue();
4302 * but since that doesn't exist yet, just open code it. */
4303 smp_mb();
4304
4305 /* We need to check again in a case another CPU has just
4306 * made room available. */
4307 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4308 return -EBUSY;
4309
4310 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4311 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4312 ++adapter->restart_queue;
4313 return 0;
4314}
4315
4316static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4317 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4318{
4319 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4320 return 0;
4321 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4322}
4323
09a3b1f8
SH		 4324static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4325{
4326 struct ixgbe_adapter *adapter = netdev_priv(dev);
4327
4328 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4329 return 0; /* All traffic should default to class 0 */
4330
4331 return skb_tx_hash(dev, skb);
4332}
4333
9a799d71
AK		 4334static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4335{
4336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4337 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4338 unsigned int first;
4339 unsigned int tx_flags = 0;
30eba97a
AV		 4340 u8 hdr_len = 0;
4341 int r_idx = 0, tso;
9a799d71
AK		 4342 int count = 0;
4343 unsigned int f;
9f8cdf4f 4344
30eba97a 4345 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 4346 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4347
9f8cdf4f
JB		 4348 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4349 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4350 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4351 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4352 tx_flags |= (skb->queue_mapping << 13);
4353 }
4354 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4355 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4356 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4357 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4358 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4359 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4360 }
9f8cdf4f
JB		 4361 /* three things can cause us to need a context descriptor */
4362 if (skb_is_gso(skb) ||
4363 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4364 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4365 count++;
4366
9f8cdf4f
JB		 4367 count += TXD_USE_COUNT(skb_headlen(skb));
4368 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4369 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4370
e092be60 4371 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4372 adapter->tx_busy++;
9a799d71
AK		 4373 return NETDEV_TX_BUSY;
4374 }
9a799d71 4375
8327d000 4376 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4377 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4378 first = tx_ring->next_to_use;
4379 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4380 if (tso < 0) {
4381 dev_kfree_skb_any(skb);
4382 return NETDEV_TX_OK;
4383 }
4384
4385 if (tso)
4386 tx_flags |= IXGBE_TX_FLAGS_TSO;
4387 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4388 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4389 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4390
4391 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 4392 ixgbe_tx_map(adapter, tx_ring, skb, first),
4393 skb->len, hdr_len);
9a799d71
AK		 4394
4395 netdev->trans_start = jiffies;
4396
e092be60 4397 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 4398
4399 return NETDEV_TX_OK;
4400}
4401
4402/**
4403 * ixgbe_get_stats - Get System Network Statistics
4404 * @netdev: network interface device structure
4405 *
4406 * Returns the address of the device statistics structure.
4407 * The statistics are actually updated from the timer callback.
4408 **/
4409static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4410{
4411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4412
4413 /* only return the current stats */
4414 return &adapter->net_stats;
4415}
4416
4417/**
4418 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4419 * @netdev: network interface device structure
4420 * @p: pointer to an address structure
4421 *
4422 * Returns 0 on success, negative on failure
4423 **/
4424static int ixgbe_set_mac(struct net_device *netdev, void *p)
4425{
4426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4427 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4428 struct sockaddr *addr = p;
4429
4430 if (!is_valid_ether_addr(addr->sa_data))
4431 return -EADDRNOTAVAIL;
4432
4433 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4434 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4435
b4617240 4436 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4437
4438 return 0;
4439}
4440
4441#ifdef CONFIG_NET_POLL_CONTROLLER
4442/*
4443 * Polling 'interrupt' - used by things like netconsole to send skbs
4444 * without having to re-enable interrupts. It's not called while
4445 * the interrupt routine is executing.
4446 */
4447static void ixgbe_netpoll(struct net_device *netdev)
4448{
4449 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4450
4451 disable_irq(adapter->pdev->irq);
4452 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4453 ixgbe_intr(adapter->pdev->irq, netdev);
4454 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4455 enable_irq(adapter->pdev->irq);
4456}
4457#endif
4458
0edc3527
SH		 4459static const struct net_device_ops ixgbe_netdev_ops = {
4460 .ndo_open = ixgbe_open,
4461 .ndo_stop = ixgbe_close,
00829823 4462 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 4463 .ndo_select_queue = ixgbe_select_queue,
0edc3527 4464 .ndo_get_stats = ixgbe_get_stats,
e90d400c 4465 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 4466 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4467 .ndo_validate_addr = eth_validate_addr,
4468 .ndo_set_mac_address = ixgbe_set_mac,
4469 .ndo_change_mtu = ixgbe_change_mtu,
4470 .ndo_tx_timeout = ixgbe_tx_timeout,
4471 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4472 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4473 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4474#ifdef CONFIG_NET_POLL_CONTROLLER
4475 .ndo_poll_controller = ixgbe_netpoll,
4476#endif
4477};
4478
9a799d71
AK		 4479/**
4480 * ixgbe_probe - Device Initialization Routine
4481 * @pdev: PCI device information struct
4482 * @ent: entry in ixgbe_pci_tbl
4483 *
4484 * Returns 0 on success, negative on failure
4485 *
4486 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4487 * The OS initialization, configuring of the adapter private structure,
4488 * and a hardware reset occur.
4489 **/
4490static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4491 const struct pci_device_id *ent)
9a799d71
AK		 4492{
4493 struct net_device *netdev;
4494 struct ixgbe_adapter *adapter = NULL;
4495 struct ixgbe_hw *hw;
4496 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4497 static int cards_found;
4498 int i, err, pci_using_dac;
e8e26350 4499 u16 pm_value = 0;
c44ade9e 4500 u32 part_num, eec;
9a799d71
AK		 4501
4502 err = pci_enable_device(pdev);
4503 if (err)
4504 return err;
4505
4506 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
4507 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4508 pci_using_dac = 1;
4509 } else {
4510 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4511 if (err) {
4512 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4513 if (err) {
b4617240
PW		 4514 dev_err(&pdev->dev, "No usable DMA "
4515 "configuration, aborting\n");
9a799d71
AK		 4516 goto err_dma;
4517 }
4518 }
4519 pci_using_dac = 0;
4520 }
4521
4522 err = pci_request_regions(pdev, ixgbe_driver_name);
4523 if (err) {
4524 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4525 goto err_pci_reg;
4526 }
4527
6fabd715
PWJ		 4528 err = pci_enable_pcie_error_reporting(pdev);
4529 if (err) {
4530 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4531 "0x%x\n", err);
4532 /* non-fatal, continue */
4533 }
4534
9a799d71 4535 pci_set_master(pdev);
fb3b27bc 4536 pci_save_state(pdev);
9a799d71 4537
30eba97a 4538 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4539 if (!netdev) {
4540 err = -ENOMEM;
4541 goto err_alloc_etherdev;
4542 }
4543
9a799d71
AK		 4544 SET_NETDEV_DEV(netdev, &pdev->dev);
4545
4546 pci_set_drvdata(pdev, netdev);
4547 adapter = netdev_priv(netdev);
4548
4549 adapter->netdev = netdev;
4550 adapter->pdev = pdev;
4551 hw = &adapter->hw;
4552 hw->back = adapter;
4553 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4554
05857980
JK		 4555 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4556 pci_resource_len(pdev, 0));
9a799d71
AK		 4557 if (!hw->hw_addr) {
4558 err = -EIO;
4559 goto err_ioremap;
4560 }
4561
4562 for (i = 1; i <= 5; i++) {
4563 if (pci_resource_len(pdev, i) == 0)
4564 continue;
4565 }
4566
0edc3527 4567 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4568 ixgbe_set_ethtool_ops(netdev);
9a799d71 4569 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4570 strcpy(netdev->name, pci_name(pdev));
4571
9a799d71
AK		 4572 adapter->bd_number = cards_found;
4573
9a799d71
AK		 4574 /* Setup hw api */
4575 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4576 hw->mac.type = ii->mac;
9a799d71 4577
c44ade9e
JB		 4578 /* EEPROM */
4579 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4580 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4581 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4582 if (!(eec & (1 << 8)))
4583 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4584
4585 /* PHY */
4586 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4587 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4588
4589 /* set up this timer and work struct before calling get_invariants
4590 * which might start the timer
4591 */
4592 init_timer(&adapter->sfp_timer);
4593 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4594 adapter->sfp_timer.data = (unsigned long) adapter;
4595
4596 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4597
e8e26350
PW		 4598 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4599 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4600
4601 /* a new SFP+ module arrival, called from GPI SDP2 context */
4602 INIT_WORK(&adapter->sfp_config_module_task,
4603 ixgbe_sfp_config_module_task);
4604
9a799d71 4605 err = ii->get_invariants(hw);
c4900be0
DS		 4606 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4607 /* start a kernel thread to watch for a module to arrive */
4608 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4609 mod_timer(&adapter->sfp_timer,
4610 round_jiffies(jiffies + (2 * HZ)));
4611 err = 0;
4612 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4613 DPRINTK(PROBE, ERR, "failed to load because an "
4614 "unsupported SFP+ module type was detected.\n");
9a799d71 4615 goto err_hw_init;
c4900be0
DS		 4616 } else if (err) {
4617 goto err_hw_init;
4618 }
9a799d71
AK		 4619
4620 /* setup the private structure */
4621 err = ixgbe_sw_init(adapter);
4622 if (err)
4623 goto err_sw_init;
4624
c44ade9e
JB		 4625 /* reset_hw fills in the perm_addr as well */
4626 err = hw->mac.ops.reset_hw(hw);
4627 if (err) {
4628 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4629 goto err_sw_init;
4630 }
4631
9a799d71 4632 netdev->features = NETIF_F_SG |
b4617240
PW		 4633 NETIF_F_IP_CSUM |
4634 NETIF_F_HW_VLAN_TX |
4635 NETIF_F_HW_VLAN_RX |
4636 NETIF_F_HW_VLAN_FILTER;
9a799d71 4637
e9990a9c 4638 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4639 netdev->features |= NETIF_F_TSO;
9a799d71 4640 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4641 netdev->features |= NETIF_F_GRO;
ad31c402
JK		 4642
4643 netdev->vlan_features |= NETIF_F_TSO;
4644 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4645 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4646 netdev->vlan_features |= NETIF_F_SG;
4647
2f90b865
AD		 4648 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4649 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4650
7a6b6f51 4651#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4652 netdev->dcbnl_ops = &dcbnl_ops;
4653#endif
4654
9a799d71
AK		 4655 if (pci_using_dac)
4656 netdev->features |= NETIF_F_HIGHDMA;
4657
9a799d71 4658 /* make sure the EEPROM is good */
c44ade9e 4659 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4660 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4661 err = -EIO;
4662 goto err_eeprom;
4663 }
4664
4665 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4666 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4667
c44ade9e
JB		 4668 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4669 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4670 err = -EIO;
4671 goto err_eeprom;
4672 }
4673
4674 init_timer(&adapter->watchdog_timer);
4675 adapter->watchdog_timer.function = &ixgbe_watchdog;
4676 adapter->watchdog_timer.data = (unsigned long)adapter;
4677
4678 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4679 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4680
021230d4
AV		 4681 err = ixgbe_init_interrupt_scheme(adapter);
4682 if (err)
4683 goto err_sw_init;
9a799d71 4684
e8e26350
PW		 4685 switch (pdev->device) {
4686 case IXGBE_DEV_ID_82599_KX4:
4687#define IXGBE_PCIE_PMCSR 0x44
4688 adapter->wol = IXGBE_WUFC_MAG;
4689 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4690 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4691 (pm_value | (1 << 8)));
4692 break;
4693 default:
4694 adapter->wol = 0;
4695 break;
4696 }
4697 device_init_wakeup(&adapter->pdev->dev, true);
4698 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4699
9a799d71 4700 /* print bus type/speed/width info */
7c510e4b 4701 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 4702 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4703 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4704 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4705 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4706 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 4707 "Unknown"),
7c510e4b 4708 netdev->dev_addr);
c44ade9e 4709 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 4710 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4711 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4712 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4713 (part_num >> 8), (part_num & 0xff));
4714 else
4715 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4716 hw->mac.type, hw->phy.type,
4717 (part_num >> 8), (part_num & 0xff));
9a799d71 4718
e8e26350 4719 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 4720 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4721 "this card is not sufficient for optimal "
4722 "performance.\n");
0c254d86 4723 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4724 "PCI-Express slot is required.\n");
0c254d86
AK		 4725 }
4726
34b0368c
PWJ		 4727 /* save off EEPROM version number */
4728 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4729
9a799d71 4730 /* reset the hardware with the new settings */
c44ade9e
JB		 4731 hw->mac.ops.start_hw(hw);
4732
9a799d71 4733 netif_carrier_off(netdev);
9a799d71
AK		 4734
4735 strcpy(netdev->name, "eth%d");
4736 err = register_netdev(netdev);
4737 if (err)
4738 goto err_register;
4739
5dd2d332 4740#ifdef CONFIG_IXGBE_DCA
652f093f 4741 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4742 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4743 /* always use CB2 mode, difference is masked
4744 * in the CB driver */
4745 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4746 ixgbe_setup_dca(adapter);
4747 }
4748#endif
9a799d71
AK		 4749
4750 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4751 cards_found++;
4752 return 0;
4753
4754err_register:
5eba3699 4755 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4756err_hw_init:
4757err_sw_init:
021230d4 4758 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4759err_eeprom:
c4900be0
DS		 4760 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4761 del_timer_sync(&adapter->sfp_timer);
4762 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4763 cancel_work_sync(&adapter->multispeed_fiber_task);
4764 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4765 iounmap(hw->hw_addr);
4766err_ioremap:
4767 free_netdev(netdev);
4768err_alloc_etherdev:
4769 pci_release_regions(pdev);
4770err_pci_reg:
4771err_dma:
4772 pci_disable_device(pdev);
4773 return err;
4774}
4775
4776/**
4777 * ixgbe_remove - Device Removal Routine
4778 * @pdev: PCI device information struct
4779 *
4780 * ixgbe_remove is called by the PCI subsystem to alert the driver
4781 * that it should release a PCI device. The could be caused by a
4782 * Hot-Plug event, or because the driver is going to be removed from
4783 * memory.
4784 **/
4785static void __devexit ixgbe_remove(struct pci_dev *pdev)
4786{
4787 struct net_device *netdev = pci_get_drvdata(pdev);
4788 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4789 int err;
9a799d71
AK		 4790
4791 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4792 /* clear the module not found bit to make sure the worker won't
4793 * reschedule
4794 */
4795 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4796 del_timer_sync(&adapter->watchdog_timer);
4797
c4900be0
DS		 4798 del_timer_sync(&adapter->sfp_timer);
4799 cancel_work_sync(&adapter->watchdog_task);
4800 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4801 cancel_work_sync(&adapter->multispeed_fiber_task);
4802 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4803 flush_scheduled_work();
4804
5dd2d332 4805#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4806 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4807 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4808 dca_remove_requester(&pdev->dev);
4809 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4810 }
4811
4812#endif
c4900be0
DS		 4813 if (netdev->reg_state == NETREG_REGISTERED)
4814 unregister_netdev(netdev);
9a799d71 4815
021230d4 4816 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4817
021230d4 4818 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4819
4820 iounmap(adapter->hw.hw_addr);
4821 pci_release_regions(pdev);
4822
021230d4
AV		 4823 DPRINTK(PROBE, INFO, "complete\n");
4824 kfree(adapter->tx_ring);
4825 kfree(adapter->rx_ring);
4826
9a799d71
AK		 4827 free_netdev(netdev);
4828
6fabd715
PWJ		 4829 err = pci_disable_pcie_error_reporting(pdev);
4830 if (err)
4831 dev_err(&pdev->dev,
4832 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4833
9a799d71
AK		 4834 pci_disable_device(pdev);
4835}
4836
4837/**
4838 * ixgbe_io_error_detected - called when PCI error is detected
4839 * @pdev: Pointer to PCI device
4840 * @state: The current pci connection state
4841 *
4842 * This function is called after a PCI bus error affecting
4843 * this device has been detected.
4844 */
4845static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4846 pci_channel_state_t state)
9a799d71
AK		 4847{
4848 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4850
4851 netif_device_detach(netdev);
4852
4853 if (netif_running(netdev))
4854 ixgbe_down(adapter);
4855 pci_disable_device(pdev);
4856
b4617240 4857 /* Request a slot reset. */
9a799d71
AK		 4858 return PCI_ERS_RESULT_NEED_RESET;
4859}
4860
4861/**
4862 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4863 * @pdev: Pointer to PCI device
4864 *
4865 * Restart the card from scratch, as if from a cold-boot.
4866 */
4867static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4868{
4869 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4870 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 4871 pci_ers_result_t result;
4872 int err;
9a799d71
AK		 4873
4874 if (pci_enable_device(pdev)) {
4875 DPRINTK(PROBE, ERR,
b4617240 4876 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 4877 result = PCI_ERS_RESULT_DISCONNECT;
4878 } else {
4879 pci_set_master(pdev);
4880 pci_restore_state(pdev);
9a799d71 4881
6fabd715
PWJ		 4882 pci_enable_wake(pdev, PCI_D3hot, 0);
4883 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 4884
6fabd715 4885 ixgbe_reset(adapter);
88512539 4886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 4887 result = PCI_ERS_RESULT_RECOVERED;
4888 }
4889
4890 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4891 if (err) {
4892 dev_err(&pdev->dev,
4893 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4894 /* non-fatal, continue */
4895 }
9a799d71 4896
6fabd715 4897 return result;
9a799d71
AK		 4898}
4899
4900/**
4901 * ixgbe_io_resume - called when traffic can start flowing again.
4902 * @pdev: Pointer to PCI device
4903 *
4904 * This callback is called when the error recovery driver tells us that
4905 * its OK to resume normal operation.
4906 */
4907static void ixgbe_io_resume(struct pci_dev *pdev)
4908{
4909 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4910 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4911
4912 if (netif_running(netdev)) {
4913 if (ixgbe_up(adapter)) {
4914 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4915 return;
4916 }
4917 }
4918
4919 netif_device_attach(netdev);
9a799d71
AK		 4920}
4921
4922static struct pci_error_handlers ixgbe_err_handler = {
4923 .error_detected = ixgbe_io_error_detected,
4924 .slot_reset = ixgbe_io_slot_reset,
4925 .resume = ixgbe_io_resume,
4926};
4927
4928static struct pci_driver ixgbe_driver = {
4929 .name = ixgbe_driver_name,
4930 .id_table = ixgbe_pci_tbl,
4931 .probe = ixgbe_probe,
4932 .remove = __devexit_p(ixgbe_remove),
4933#ifdef CONFIG_PM
4934 .suspend = ixgbe_suspend,
4935 .resume = ixgbe_resume,
4936#endif
4937 .shutdown = ixgbe_shutdown,
4938 .err_handler = &ixgbe_err_handler
4939};
4940
4941/**
4942 * ixgbe_init_module - Driver Registration Routine
4943 *
4944 * ixgbe_init_module is the first routine called when the driver is
4945 * loaded. All it does is register with the PCI subsystem.
4946 **/
4947static int __init ixgbe_init_module(void)
4948{
4949 int ret;
4950 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4951 ixgbe_driver_string, ixgbe_driver_version);
4952
4953 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4954
5dd2d332 4955#ifdef CONFIG_IXGBE_DCA
bd0362dd 4956 dca_register_notify(&dca_notifier);
bd0362dd 4957#endif
5dd2d332 4958
9a799d71
AK		 4959 ret = pci_register_driver(&ixgbe_driver);
4960 return ret;
4961}
b4617240 4962
9a799d71
AK		 4963module_init(ixgbe_init_module);
4964
4965/**
4966 * ixgbe_exit_module - Driver Exit Cleanup Routine
4967 *
4968 * ixgbe_exit_module is called just before the driver is removed
4969 * from memory.
4970 **/
4971static void __exit ixgbe_exit_module(void)
4972{
5dd2d332 4973#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4974 dca_unregister_notify(&dca_notifier);
4975#endif
9a799d71
AK		 4976 pci_unregister_driver(&ixgbe_driver);
4977}
bd0362dd 4978
5dd2d332 4979#ifdef CONFIG_IXGBE_DCA
bd0362dd 4980static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4981 void *p)
bd0362dd
JC		 4982{
4983 int ret_val;
4984
4985 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4986 __ixgbe_notify_dca);
bd0362dd
JC		 4987
4988 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4989}
b453368d 4990
5dd2d332 4991#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 4992#ifdef DEBUG
4993/**
4994 * ixgbe_get_hw_dev_name - return device name string
4995 * used by hardware layer to print debugging information
4996 **/
4997char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
4998{
4999 struct ixgbe_adapter *adapter = hw->back;
5000 return adapter->netdev->name;
5001}
bd0362dd 5002
b453368d 5003#endif
9a799d71
AK		 5004module_exit(ixgbe_exit_module);
5005
5006/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree