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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
9a799d71
AK		 48
49char ixgbe_driver_name[] = "ixgbe";
9c8eb720 50static const char ixgbe_driver_string[] =
b4617240 51 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 52
e0f4daff 53#define DRV_VERSION "2.0.44-k2"
9c8eb720 54const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 55static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 56
57static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 58 [board_82598] = &ixgbe_82598_info,
e8e26350 59 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 60};
61
62/* ixgbe_pci_tbl - PCI Device ID Table
63 *
64 * Wildcard entries (PCI_ANY_ID) should come last
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
70static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 76 board_82598 },
0befdb3e
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
78 board_82598 },
3845bec0
PWJ		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
80 board_82598 },
9a799d71 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 82 board_82598 },
8d792cd9
JB		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
84 board_82598 },
c4900be0
DS		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
88 board_82598 },
b95f5fcb
JB		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
90 board_82598 },
c4900be0
DS		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
92 board_82598 },
2f21bdd3
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
94 board_82598 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
96 board_82599 },
1fcf03e6
PWJ		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
98 board_82599 },
74757d49
DS		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
100 board_82599 },
e8e26350
PW		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
102 board_82599 },
38ad1c8e
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
104 board_82599 },
dbfec662
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
106 board_82599 },
8911184f
PWJ		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
108 board_82599 },
312eb931
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
110 board_82599 },
9a799d71
AK		 111
112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
9a799d71
AK		 127MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
128MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
129MODULE_LICENSE("GPL");
130MODULE_VERSION(DRV_VERSION);
131
132#define DEFAULT_DEBUG_LEVEL_SHIFT 3
133
5eba3699
AV		 134static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
135{
136 u32 ctrl_ext;
137
138 /* Let firmware take over control of h/w */
139 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
140 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 141 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 142}
143
144static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
145{
146 u32 ctrl_ext;
147
148 /* Let firmware know the driver has taken over */
149 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
150 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 151 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 152}
9a799d71 153
e8e26350
PW		 154/*
155 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
156 * @adapter: pointer to adapter struct
157 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
158 * @queue: queue to map the corresponding interrupt to
159 * @msix_vector: the vector to map to the corresponding queue
160 *
161 */
162static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
163 u8 queue, u8 msix_vector)
9a799d71
AK		 164{
165 u32 ivar, index;
e8e26350
PW		 166 struct ixgbe_hw *hw = &adapter->hw;
167 switch (hw->mac.type) {
168 case ixgbe_mac_82598EB:
169 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
170 if (direction == -1)
171 direction = 0;
172 index = (((direction * 64) + queue) >> 2) & 0x1F;
173 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
174 ivar &= ~(0xFF << (8 * (queue & 0x3)));
175 ivar |= (msix_vector << (8 * (queue & 0x3)));
176 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
177 break;
178 case ixgbe_mac_82599EB:
179 if (direction == -1) {
180 /* other causes */
181 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
182 index = ((queue & 1) * 8);
183 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
184 ivar &= ~(0xFF << index);
185 ivar |= (msix_vector << index);
186 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
187 break;
188 } else {
189 /* tx or rx causes */
190 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
191 index = ((16 * (queue & 1)) + (8 * direction));
192 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
193 ivar &= ~(0xFF << index);
194 ivar |= (msix_vector << index);
195 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
196 break;
197 }
198 default:
199 break;
200 }
9a799d71
AK		 201}
202
fe49f04a
AD		 203static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
204 u64 qmask)
205{
206 u32 mask;
207
208 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
209 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
211 } else {
212 mask = (qmask & 0xFFFFFFFF);
213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
214 mask = (qmask >> 32);
215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
216 }
217}
218
9a799d71 219static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 220 struct ixgbe_tx_buffer
221 *tx_buffer_info)
9a799d71 222{
e5a43549
AD		 223 if (tx_buffer_info->dma) {
224 if (tx_buffer_info->mapped_as_page)
225 pci_unmap_page(adapter->pdev,
226 tx_buffer_info->dma,
227 tx_buffer_info->length,
228 PCI_DMA_TODEVICE);
229 else
230 pci_unmap_single(adapter->pdev,
231 tx_buffer_info->dma,
232 tx_buffer_info->length,
233 PCI_DMA_TODEVICE);
234 tx_buffer_info->dma = 0;
235 }
9a799d71
AK		 236 if (tx_buffer_info->skb) {
237 dev_kfree_skb_any(tx_buffer_info->skb);
238 tx_buffer_info->skb = NULL;
239 }
44df32c5 240 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 241 /* tx_buffer_info must be completely set up in the transmit path */
242}
243
26f23d82
YZ		 244/**
245 * ixgbe_tx_is_paused - check if the tx ring is paused
246 * @adapter: the ixgbe adapter
247 * @tx_ring: the corresponding tx_ring
248 *
249 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
250 * corresponding TC of this tx_ring when checking TFCS.
251 *
252 * Returns : true if paused
253 */
254static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
255 struct ixgbe_ring *tx_ring)
256{
26f23d82
YZ		 257 u32 txoff = IXGBE_TFCS_TXOFF;
258
259#ifdef CONFIG_IXGBE_DCB
260 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 261 int tc;
26f23d82
YZ		 262 int reg_idx = tx_ring->reg_idx;
263 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
264
265 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
266 tc = reg_idx >> 2;
267 txoff = IXGBE_TFCS_TXOFF0;
268 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
269 tc = 0;
270 txoff = IXGBE_TFCS_TXOFF;
271 if (dcb_i == 8) {
272 /* TC0, TC1 */
273 tc = reg_idx >> 5;
274 if (tc == 2) /* TC2, TC3 */
275 tc += (reg_idx - 64) >> 4;
276 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
277 tc += 1 + ((reg_idx - 96) >> 3);
278 } else if (dcb_i == 4) {
279 /* TC0, TC1 */
280 tc = reg_idx >> 6;
281 if (tc == 1) {
282 tc += (reg_idx - 64) >> 5;
283 if (tc == 2) /* TC2, TC3 */
284 tc += (reg_idx - 96) >> 4;
285 }
286 }
287 }
288 txoff <<= tc;
289 }
290#endif
291 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
292}
293
9a799d71 294static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 295 struct ixgbe_ring *tx_ring,
296 unsigned int eop)
9a799d71 297{
e01c31a5 298 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 299
9a799d71 300 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 301 * check with the clearing of time_stamp and movement of eop */
9a799d71 302 adapter->detect_tx_hung = false;
44df32c5 303 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 304 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 305 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 306 /* detected Tx unit hang */
e01c31a5
JB		 307 union ixgbe_adv_tx_desc *tx_desc;
308 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 309 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 310 " Tx Queue <%d>\n"
311 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 312 " next_to_use <%x>\n"
313 " next_to_clean <%x>\n"
314 "tx_buffer_info[next_to_clean]\n"
315 " time_stamp <%lx>\n"
e01c31a5
JB		 316 " jiffies <%lx>\n",
317 tx_ring->queue_index,
44df32c5
AD		 318 IXGBE_READ_REG(hw, tx_ring->head),
319 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 320 tx_ring->next_to_use, eop,
321 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 322 return true;
323 }
324
325 return false;
326}
327
b4617240
PW		 328#define IXGBE_MAX_TXD_PWR 14
329#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 330
331/* Tx Descriptors needed, worst case */
332#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
333 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
334#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 335 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 336
e01c31a5
JB		 337static void ixgbe_tx_timeout(struct net_device *netdev);
338
9a799d71
AK		 339/**
340 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 341 * @q_vector: structure containing interrupt and ring information
e01c31a5 342 * @tx_ring: tx ring to clean
9a799d71 343 **/
fe49f04a 344static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 345 struct ixgbe_ring *tx_ring)
9a799d71 346{
fe49f04a 347 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 348 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 349 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
350 struct ixgbe_tx_buffer *tx_buffer_info;
351 unsigned int i, eop, count = 0;
e01c31a5 352 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 353
354 i = tx_ring->next_to_clean;
12207e49
PWJ		 355 eop = tx_ring->tx_buffer_info[i].next_to_watch;
356 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
357
358 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 359 (count < tx_ring->work_limit)) {
12207e49
PWJ		 360 bool cleaned = false;
361 for ( ; !cleaned; count++) {
362 struct sk_buff *skb;
9a799d71
AK		 363 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
364 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 365 cleaned = (i == eop);
e01c31a5 366 skb = tx_buffer_info->skb;
9a799d71 367
12207e49 368 if (cleaned && skb) {
e092be60 369 unsigned int segs, bytecount;
3d8fd385 370 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 371
372 /* gso_segs is currently only valid for tcp */
e092be60 373 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 374#ifdef IXGBE_FCOE
375 /* adjust for FCoE Sequence Offload */
376 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
377 && (skb->protocol == htons(ETH_P_FCOE)) &&
378 skb_is_gso(skb)) {
379 hlen = skb_transport_offset(skb) +
380 sizeof(struct fc_frame_header) +
381 sizeof(struct fcoe_crc_eof);
382 segs = DIV_ROUND_UP(skb->len - hlen,
383 skb_shinfo(skb)->gso_size);
384 }
385#endif /* IXGBE_FCOE */
e092be60 386 /* multiply data chunks by size of headers */
3d8fd385 387 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 388 total_packets += segs;
389 total_bytes += bytecount;
e092be60 390 }
e01c31a5 391
9a799d71 392 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 393 tx_buffer_info);
9a799d71 394
12207e49
PWJ		 395 tx_desc->wb.status = 0;
396
9a799d71
AK		 397 i++;
398 if (i == tx_ring->count)
399 i = 0;
e01c31a5 400 }
12207e49
PWJ		 401
402 eop = tx_ring->tx_buffer_info[i].next_to_watch;
403 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
404 }
405
9a799d71
AK		 406 tx_ring->next_to_clean = i;
407
e092be60 408#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 409 if (unlikely(count && netif_carrier_ok(netdev) &&
410 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 411 /* Make sure that anybody stopping the queue after this
412 * sees the new next_to_clean.
413 */
414 smp_mb();
30eba97a
AV		 415 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
416 !test_bit(__IXGBE_DOWN, &adapter->state)) {
417 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 418 ++tx_ring->restart_queue;
30eba97a 419 }
e092be60 420 }
9a799d71 421
e01c31a5
JB		 422 if (adapter->detect_tx_hung) {
423 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
424 /* schedule immediate reset if we believe we hung */
425 DPRINTK(PROBE, INFO,
426 "tx hang %d detected, resetting adapter\n",
427 adapter->tx_timeout_count + 1);
428 ixgbe_tx_timeout(adapter->netdev);
429 }
430 }
9a799d71 431
e01c31a5 432 /* re-arm the interrupt */
fe49f04a
AD		 433 if (count >= tx_ring->work_limit)
434 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 435
e01c31a5
JB		 436 tx_ring->total_bytes += total_bytes;
437 tx_ring->total_packets += total_packets;
e01c31a5 438 tx_ring->stats.packets += total_packets;
12207e49 439 tx_ring->stats.bytes += total_bytes;
9a1a69ad 440 return (count < tx_ring->work_limit);
9a799d71
AK		 441}
442
5dd2d332 443#ifdef CONFIG_IXGBE_DCA
bd0362dd 444static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 445 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 446{
447 u32 rxctrl;
448 int cpu = get_cpu();
3a581073 449 int q = rx_ring - adapter->rx_ring;
bd0362dd 450
3a581073 451 if (rx_ring->cpu != cpu) {
bd0362dd 452 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 453 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
454 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
455 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
456 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
457 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
458 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
459 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
460 }
bd0362dd
JC		 461 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
462 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 463 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
464 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 465 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 467 rx_ring->cpu = cpu;
bd0362dd
JC		 468 }
469 put_cpu();
470}
471
472static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 473 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 474{
475 u32 txctrl;
476 int cpu = get_cpu();
3a581073 477 int q = tx_ring - adapter->tx_ring;
ee5f784a 478 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 479
3a581073 480 if (tx_ring->cpu != cpu) {
e8e26350 481 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 482 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 483 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
484 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 485 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
486 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 487 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 488 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 489 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
490 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 491 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
492 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
493 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 494 }
3a581073 495 tx_ring->cpu = cpu;
bd0362dd
JC		 496 }
497 put_cpu();
498}
499
500static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
501{
502 int i;
503
504 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
505 return;
506
e35ec126
AD		 507 /* always use CB2 mode, difference is masked in the CB driver */
508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
509
bd0362dd
JC		 510 for (i = 0; i < adapter->num_tx_queues; i++) {
511 adapter->tx_ring[i].cpu = -1;
512 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
513 }
514 for (i = 0; i < adapter->num_rx_queues; i++) {
515 adapter->rx_ring[i].cpu = -1;
516 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
517 }
518}
519
520static int __ixgbe_notify_dca(struct device *dev, void *data)
521{
522 struct net_device *netdev = dev_get_drvdata(dev);
523 struct ixgbe_adapter *adapter = netdev_priv(netdev);
524 unsigned long event = *(unsigned long *)data;
525
526 switch (event) {
527 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 528 /* if we're already enabled, don't do it again */
529 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
530 break;
652f093f 531 if (dca_add_requester(dev) == 0) {
96b0e0f6 532 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 533 ixgbe_setup_dca(adapter);
534 break;
535 }
536 /* Fall Through since DCA is disabled. */
537 case DCA_PROVIDER_REMOVE:
538 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
539 dca_remove_requester(dev);
540 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
542 }
543 break;
544 }
545
652f093f 546 return 0;
bd0362dd
JC		 547}
548
5dd2d332 549#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 550/**
551 * ixgbe_receive_skb - Send a completed packet up the stack
552 * @adapter: board private structure
553 * @skb: packet to send up
177db6ff
MC		 554 * @status: hardware indication of status of receive
555 * @rx_ring: rx descriptor ring (for a specific queue) to setup
556 * @rx_desc: rx descriptor
9a799d71 557 **/
78b6f4ce 558static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 559 struct sk_buff *skb, u8 status,
fdaff1ce 560 struct ixgbe_ring *ring,
177db6ff 561 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 562{
78b6f4ce
HX		 563 struct ixgbe_adapter *adapter = q_vector->adapter;
564 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 565 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
566 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 567
fdaff1ce 568 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 569 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 570 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 571 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 572 else
78b6f4ce 573 napi_gro_receive(napi, skb);
177db6ff 574 } else {
8a62babf 575 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 576 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
577 else
578 netif_rx(skb);
9a799d71
AK		 579 }
580}
581
e59bd25d
AV		 582/**
583 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
584 * @adapter: address of board private structure
585 * @status_err: hardware indication of status of receive
586 * @skb: skb currently being received and modified
587 **/
9a799d71 588static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 589 union ixgbe_adv_rx_desc *rx_desc,
590 struct sk_buff *skb)
9a799d71 591{
8bae1b2b
DS		 592 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
593
9a799d71
AK		 594 skb->ip_summed = CHECKSUM_NONE;
595
712744be
JB		 596 /* Rx csum disabled */
597 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 598 return;
e59bd25d
AV		 599
600 /* if IP and error */
601 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
602 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 603 adapter->hw_csum_rx_error++;
604 return;
605 }
e59bd25d
AV		 606
607 if (!(status_err & IXGBE_RXD_STAT_L4CS))
608 return;
609
610 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 611 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
612
613 /*
614 * 82599 errata, UDP frames with a 0 checksum can be marked as
615 * checksum errors.
616 */
617 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
618 (adapter->hw.mac.type == ixgbe_mac_82599EB))
619 return;
620
e59bd25d
AV		 621 adapter->hw_csum_rx_error++;
622 return;
623 }
624
9a799d71 625 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 626 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 627}
628
e8e26350
PW		 629static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
630 struct ixgbe_ring *rx_ring, u32 val)
631{
632 /*
633 * Force memory writes to complete before letting h/w
634 * know there are new descriptors to fetch. (Only
635 * applicable for weak-ordered memory model archs,
636 * such as IA-64).
637 */
638 wmb();
639 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
640}
641
9a799d71
AK		 642/**
643 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
644 * @adapter: address of board private structure
645 **/
646static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 647 struct ixgbe_ring *rx_ring,
648 int cleaned_count)
9a799d71 649{
9a799d71
AK		 650 struct pci_dev *pdev = adapter->pdev;
651 union ixgbe_adv_rx_desc *rx_desc;
3a581073 652 struct ixgbe_rx_buffer *bi;
9a799d71 653 unsigned int i;
9a799d71
AK		 654
655 i = rx_ring->next_to_use;
3a581073 656 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 657
658 while (cleaned_count--) {
659 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
660
762f4c57 661 if (!bi->page_dma &&
6e455b89 662 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 663 if (!bi->page) {
762f4c57
JB		 664 bi->page = alloc_page(GFP_ATOMIC);
665 if (!bi->page) {
666 adapter->alloc_rx_page_failed++;
667 goto no_buffers;
668 }
669 bi->page_offset = 0;
670 } else {
671 /* use a half page if we're re-using */
672 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 673 }
762f4c57
JB		 674
675 bi->page_dma = pci_map_page(pdev, bi->page,
676 bi->page_offset,
677 (PAGE_SIZE / 2),
678 PCI_DMA_FROMDEVICE);
9a799d71
AK		 679 }
680
3a581073 681 if (!bi->skb) {
5ecc3614 682 struct sk_buff *skb;
7ca3bc58
JB		 683 /* netdev_alloc_skb reserves 32 bytes up front!! */
684 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
685 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 686
687 if (!skb) {
688 adapter->alloc_rx_buff_failed++;
689 goto no_buffers;
690 }
691
7ca3bc58
JB		 692 /* advance the data pointer to the next cache line */
693 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
694 - skb->data));
695
3a581073 696 bi->skb = skb;
4f57ca6e
JB		 697 bi->dma = pci_map_single(pdev, skb->data,
698 rx_ring->rx_buf_len,
3a581073 699 PCI_DMA_FROMDEVICE);
9a799d71
AK		 700 }
701 /* Refresh the desc even if buffer_addrs didn't change because
702 * each write-back erases this info. */
6e455b89 703 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 704 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
705 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 706 } else {
3a581073 707 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 708 }
709
710 i++;
711 if (i == rx_ring->count)
712 i = 0;
3a581073 713 bi = &rx_ring->rx_buffer_info[i];
9a799d71 714 }
7c6e0a43 715
9a799d71
AK		 716no_buffers:
717 if (rx_ring->next_to_use != i) {
718 rx_ring->next_to_use = i;
719 if (i-- == 0)
720 i = (rx_ring->count - 1);
721
e8e26350 722 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 723 }
724}
725
7c6e0a43
JB		 726static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
727{
728 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
729}
730
731static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
732{
733 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
734}
735
f8212f97
AD		 736static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
737{
738 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
739 IXGBE_RXDADV_RSCCNT_MASK) >>
740 IXGBE_RXDADV_RSCCNT_SHIFT;
741}
742
743/**
744 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
745 * @skb: pointer to the last skb in the rsc queue
94b982b2 746 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 747 *
748 * This function changes a queue full of hw rsc buffers into a completed
749 * packet. It uses the ->prev pointers to find the first packet and then
750 * turns it into the frag list owner.
751 **/
94b982b2
MC		 752static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
753 u64 *count)
f8212f97
AD		 754{
755 unsigned int frag_list_size = 0;
756
757 while (skb->prev) {
758 struct sk_buff *prev = skb->prev;
759 frag_list_size += skb->len;
760 skb->prev = NULL;
761 skb = prev;
94b982b2 762 *count += 1;
f8212f97
AD		 763 }
764
765 skb_shinfo(skb)->frag_list = skb->next;
766 skb->next = NULL;
767 skb->len += frag_list_size;
768 skb->data_len += frag_list_size;
769 skb->truesize += frag_list_size;
770 return skb;
771}
772
78b6f4ce 773static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 774 struct ixgbe_ring *rx_ring,
775 int *work_done, int work_to_do)
9a799d71 776{
78b6f4ce 777 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 778 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 779 struct pci_dev *pdev = adapter->pdev;
780 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
781 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
782 struct sk_buff *skb;
f8212f97 783 unsigned int i, rsc_count = 0;
7c6e0a43 784 u32 len, staterr;
177db6ff
MC		 785 u16 hdr_info;
786 bool cleaned = false;
9a799d71 787 int cleaned_count = 0;
d2f4fbe2 788 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 789#ifdef IXGBE_FCOE
790 int ddp_bytes = 0;
791#endif /* IXGBE_FCOE */
9a799d71
AK		 792
793 i = rx_ring->next_to_clean;
9a799d71
AK		 794 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
795 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
796 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 797
798 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 799 u32 upper_len = 0;
9a799d71
AK		 800 if (*work_done >= work_to_do)
801 break;
802 (*work_done)++;
803
6e455b89 804 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 805 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
806 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 807 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 808 if (len > IXGBE_RX_HDR_SIZE)
809 len = IXGBE_RX_HDR_SIZE;
810 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 811 } else {
9a799d71 812 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 813 }
9a799d71
AK		 814
815 cleaned = true;
816 skb = rx_buffer_info->skb;
7ca3bc58 817 prefetch(skb->data);
9a799d71
AK		 818 rx_buffer_info->skb = NULL;
819
21fa4e66 820 if (rx_buffer_info->dma) {
9a799d71 821 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 822 rx_ring->rx_buf_len,
b4617240 823 PCI_DMA_FROMDEVICE);
4f57ca6e 824 rx_buffer_info->dma = 0;
9a799d71
AK		 825 skb_put(skb, len);
826 }
827
828 if (upper_len) {
829 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 830 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 831 rx_buffer_info->page_dma = 0;
832 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 833 rx_buffer_info->page,
834 rx_buffer_info->page_offset,
835 upper_len);
836
837 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
838 (page_count(rx_buffer_info->page) != 1))
839 rx_buffer_info->page = NULL;
840 else
841 get_page(rx_buffer_info->page);
9a799d71
AK		 842
843 skb->len += upper_len;
844 skb->data_len += upper_len;
845 skb->truesize += upper_len;
846 }
847
848 i++;
849 if (i == rx_ring->count)
850 i = 0;
9a799d71
AK		 851
852 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
853 prefetch(next_rxd);
9a799d71 854 cleaned_count++;
f8212f97 855
0c19d6af 856 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 857 rsc_count = ixgbe_get_rsc_count(rx_desc);
858
859 if (rsc_count) {
860 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
861 IXGBE_RXDADV_NEXTP_SHIFT;
862 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 863 } else {
864 next_buffer = &rx_ring->rx_buffer_info[i];
865 }
866
9a799d71 867 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 868 if (skb->prev)
94b982b2
MC		 869 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
870 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
871 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
872 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
873 else
874 rx_ring->rsc_count++;
875 rx_ring->rsc_flush++;
876 }
9a799d71
AK		 877 rx_ring->stats.packets++;
878 rx_ring->stats.bytes += skb->len;
879 } else {
6e455b89 880 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 881 rx_buffer_info->skb = next_buffer->skb;
882 rx_buffer_info->dma = next_buffer->dma;
883 next_buffer->skb = skb;
884 next_buffer->dma = 0;
885 } else {
886 skb->next = next_buffer->skb;
887 skb->next->prev = skb;
888 }
7ca3bc58 889 rx_ring->non_eop_descs++;
9a799d71
AK		 890 goto next_desc;
891 }
892
893 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
894 dev_kfree_skb_irq(skb);
895 goto next_desc;
896 }
897
8bae1b2b 898 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 899
900 /* probably a little skewed due to removing CRC */
901 total_rx_bytes += skb->len;
902 total_rx_packets++;
903
74ce8dd2 904 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 905#ifdef IXGBE_FCOE
906 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 907 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
908 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
909 if (!ddp_bytes)
332d4a7d 910 goto next_desc;
3d8fd385 911 }
332d4a7d 912#endif /* IXGBE_FCOE */
fdaff1ce 913 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 914
915next_desc:
916 rx_desc->wb.upper.status_error = 0;
917
918 /* return some buffers to hardware, one at a time is too slow */
919 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
920 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
921 cleaned_count = 0;
922 }
923
924 /* use prefetched values */
925 rx_desc = next_rxd;
f8212f97 926 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 927
928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 929 }
930
9a799d71
AK		 931 rx_ring->next_to_clean = i;
932 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
933
934 if (cleaned_count)
935 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
936
3d8fd385
YZ		 937#ifdef IXGBE_FCOE
938 /* include DDPed FCoE data */
939 if (ddp_bytes > 0) {
940 unsigned int mss;
941
942 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
943 sizeof(struct fc_frame_header) -
944 sizeof(struct fcoe_crc_eof);
945 if (mss > 512)
946 mss &= ~511;
947 total_rx_bytes += ddp_bytes;
948 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
949 }
950#endif /* IXGBE_FCOE */
951
f494e8fa
AV		 952 rx_ring->total_packets += total_rx_packets;
953 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 954 netdev->stats.rx_bytes += total_rx_bytes;
955 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 956
9a799d71
AK		 957 return cleaned;
958}
959
021230d4 960static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 961/**
962 * ixgbe_configure_msix - Configure MSI-X hardware
963 * @adapter: board private structure
964 *
965 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
966 * interrupts.
967 **/
968static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
969{
021230d4
AV		 970 struct ixgbe_q_vector *q_vector;
971 int i, j, q_vectors, v_idx, r_idx;
972 u32 mask;
9a799d71 973
021230d4 974 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 975
4df10466
JB		 976 /*
977 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 978 * corresponding register.
979 */
980 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 981 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 982 /* XXX for_each_bit(...) */
983 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 984 adapter->num_rx_queues);
021230d4
AV		 985
986 for (i = 0; i < q_vector->rxr_count; i++) {
987 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 988 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 989 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 990 adapter->num_rx_queues,
991 r_idx + 1);
021230d4
AV		 992 }
993 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 994 adapter->num_tx_queues);
021230d4
AV		 995
996 for (i = 0; i < q_vector->txr_count; i++) {
997 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 998 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 999 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1000 adapter->num_tx_queues,
1001 r_idx + 1);
021230d4
AV		 1002 }
1003
021230d4 1004 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1005 /* tx only */
1006 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1007 else if (q_vector->rxr_count)
f7554a2b
NS		 1008 /* rx or mixed */
1009 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1010
fe49f04a 1011 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1012 }
1013
e8e26350
PW		 1014 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1015 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1016 v_idx);
1017 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1018 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1020
41fb9248 1021 /* set up to autoclear timer, and the vectors */
021230d4 1022 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 1023 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1024 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1025}
1026
f494e8fa
AV		 1027enum latency_range {
1028 lowest_latency = 0,
1029 low_latency = 1,
1030 bulk_latency = 2,
1031 latency_invalid = 255
1032};
1033
1034/**
1035 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1036 * @adapter: pointer to adapter
1037 * @eitr: eitr setting (ints per sec) to give last timeslice
1038 * @itr_setting: current throttle rate in ints/second
1039 * @packets: the number of packets during this measurement interval
1040 * @bytes: the number of bytes during this measurement interval
1041 *
1042 * Stores a new ITR value based on packets and byte
1043 * counts during the last interrupt. The advantage of per interrupt
1044 * computation is faster updates and more accurate ITR for the current
1045 * traffic pattern. Constants in this function were computed
1046 * based on theoretical maximum wire speed and thresholds were set based
1047 * on testing data as well as attempting to minimize response time
1048 * while increasing bulk throughput.
1049 * this functionality is controlled by the InterruptThrottleRate module
1050 * parameter (see ixgbe_param.c)
1051 **/
1052static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1053 u32 eitr, u8 itr_setting,
1054 int packets, int bytes)
f494e8fa
AV		 1055{
1056 unsigned int retval = itr_setting;
1057 u32 timepassed_us;
1058 u64 bytes_perint;
1059
1060 if (packets == 0)
1061 goto update_itr_done;
1062
1063
1064 /* simple throttlerate management
1065 * 0-20MB/s lowest (100000 ints/s)
1066 * 20-100MB/s low (20000 ints/s)
1067 * 100-1249MB/s bulk (8000 ints/s)
1068 */
1069 /* what was last interrupt timeslice? */
1070 timepassed_us = 1000000/eitr;
1071 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1072
1073 switch (itr_setting) {
1074 case lowest_latency:
1075 if (bytes_perint > adapter->eitr_low)
1076 retval = low_latency;
1077 break;
1078 case low_latency:
1079 if (bytes_perint > adapter->eitr_high)
1080 retval = bulk_latency;
1081 else if (bytes_perint <= adapter->eitr_low)
1082 retval = lowest_latency;
1083 break;
1084 case bulk_latency:
1085 if (bytes_perint <= adapter->eitr_high)
1086 retval = low_latency;
1087 break;
1088 }
1089
1090update_itr_done:
1091 return retval;
1092}
1093
509ee935
JB		 1094/**
1095 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1096 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1097 *
1098 * This function is made to be called by ethtool and by the driver
1099 * when it needs to update EITR registers at runtime. Hardware
1100 * specific quirks/differences are taken care of here.
1101 */
fe49f04a 1102void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1103{
fe49f04a 1104 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1105 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1106 int v_idx = q_vector->v_idx;
1107 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1108
509ee935
JB		 1109 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1110 /* must write high and low 16 bits to reset counter */
1111 itr_reg |= (itr_reg << 16);
1112 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1113 /*
1114 * set the WDIS bit to not clear the timer bits and cause an
1115 * immediate assertion of the interrupt
1116 */
1117 itr_reg |= IXGBE_EITR_CNT_WDIS;
1118 }
1119 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1120}
1121
f494e8fa
AV		 1122static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1123{
1124 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1125 u32 new_itr;
1126 u8 current_itr, ret_itr;
fe49f04a 1127 int i, r_idx;
f494e8fa
AV		 1128 struct ixgbe_ring *rx_ring, *tx_ring;
1129
1130 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1131 for (i = 0; i < q_vector->txr_count; i++) {
1132 tx_ring = &(adapter->tx_ring[r_idx]);
1133 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1134 q_vector->tx_itr,
1135 tx_ring->total_packets,
1136 tx_ring->total_bytes);
f494e8fa
AV		 1137 /* if the result for this queue would decrease interrupt
1138 * rate for this vector then use that result */
30efa5a3 1139 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1140 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1141 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1142 r_idx + 1);
f494e8fa
AV		 1143 }
1144
1145 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1146 for (i = 0; i < q_vector->rxr_count; i++) {
1147 rx_ring = &(adapter->rx_ring[r_idx]);
1148 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1149 q_vector->rx_itr,
1150 rx_ring->total_packets,
1151 rx_ring->total_bytes);
f494e8fa
AV		 1152 /* if the result for this queue would decrease interrupt
1153 * rate for this vector then use that result */
30efa5a3 1154 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1155 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1156 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1157 r_idx + 1);
f494e8fa
AV		 1158 }
1159
30efa5a3 1160 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1161
1162 switch (current_itr) {
1163 /* counts and packets in update_itr are dependent on these numbers */
1164 case lowest_latency:
1165 new_itr = 100000;
1166 break;
1167 case low_latency:
1168 new_itr = 20000; /* aka hwitr = ~200 */
1169 break;
1170 case bulk_latency:
1171 default:
1172 new_itr = 8000;
1173 break;
1174 }
1175
1176 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1177 /* do an exponential smoothing */
1178 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1179
1180 /* save the algorithm value here, not the smoothed one */
1181 q_vector->eitr = new_itr;
fe49f04a
AD		 1182
1183 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1184 }
1185
1186 return;
1187}
1188
0befdb3e
JB		 1189static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1190{
1191 struct ixgbe_hw *hw = &adapter->hw;
1192
1193 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1194 (eicr & IXGBE_EICR_GPI_SDP1)) {
1195 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1196 /* write to clear the interrupt */
1197 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1198 }
1199}
cf8280ee 1200
e8e26350
PW		 1201static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1202{
1203 struct ixgbe_hw *hw = &adapter->hw;
1204
1205 if (eicr & IXGBE_EICR_GPI_SDP1) {
1206 /* Clear the interrupt */
1207 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1208 schedule_work(&adapter->multispeed_fiber_task);
1209 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1210 /* Clear the interrupt */
1211 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1212 schedule_work(&adapter->sfp_config_module_task);
1213 } else {
1214 /* Interrupt isn't for us... */
1215 return;
1216 }
1217}
1218
cf8280ee
JB		 1219static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1220{
1221 struct ixgbe_hw *hw = &adapter->hw;
1222
1223 adapter->lsc_int++;
1224 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1225 adapter->link_check_timeout = jiffies;
1226 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1227 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1228 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1229 schedule_work(&adapter->watchdog_task);
1230 }
1231}
1232
9a799d71
AK		 1233static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1234{
1235 struct net_device *netdev = data;
1236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1237 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1238 u32 eicr;
1239
1240 /*
1241 * Workaround for Silicon errata. Use clear-by-write instead
1242 * of clear-by-read. Reading with EICS will return the
1243 * interrupt causes without clearing, which later be done
1244 * with the write to EICR.
1245 */
1246 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1247 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1248
cf8280ee
JB		 1249 if (eicr & IXGBE_EICR_LSC)
1250 ixgbe_check_lsc(adapter);
d4f80882 1251
e8e26350
PW		 1252 if (hw->mac.type == ixgbe_mac_82598EB)
1253 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1254
c4cf55e5 1255 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1256 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1257
1258 /* Handle Flow Director Full threshold interrupt */
1259 if (eicr & IXGBE_EICR_FLOW_DIR) {
1260 int i;
1261 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1262 /* Disable transmits before FDIR Re-initialization */
1263 netif_tx_stop_all_queues(netdev);
1264 for (i = 0; i < adapter->num_tx_queues; i++) {
1265 struct ixgbe_ring *tx_ring =
1266 &adapter->tx_ring[i];
1267 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1268 &tx_ring->reinit_state))
1269 schedule_work(&adapter->fdir_reinit_task);
1270 }
1271 }
1272 }
d4f80882
AV		 1273 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1274 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1275
1276 return IRQ_HANDLED;
1277}
1278
fe49f04a
AD		 1279static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1280 u64 qmask)
1281{
1282 u32 mask;
1283
1284 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1285 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1286 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1287 } else {
1288 mask = (qmask & 0xFFFFFFFF);
1289 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1290 mask = (qmask >> 32);
1291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1292 }
1293 /* skip the flush */
1294}
1295
1296static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1297 u64 qmask)
1298{
1299 u32 mask;
1300
1301 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1302 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1303 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1304 } else {
1305 mask = (qmask & 0xFFFFFFFF);
1306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1307 mask = (qmask >> 32);
1308 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1309 }
1310 /* skip the flush */
1311}
1312
9a799d71
AK		 1313static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1314{
021230d4
AV		 1315 struct ixgbe_q_vector *q_vector = data;
1316 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1317 struct ixgbe_ring *tx_ring;
021230d4
AV		 1318 int i, r_idx;
1319
1320 if (!q_vector->txr_count)
1321 return IRQ_HANDLED;
1322
1323 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1324 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1325 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1326 tx_ring->total_bytes = 0;
1327 tx_ring->total_packets = 0;
021230d4 1328 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1329 r_idx + 1);
021230d4 1330 }
9a799d71 1331
9b471446 1332 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1333 napi_schedule(&q_vector->napi);
1334
9a799d71
AK		 1335 return IRQ_HANDLED;
1336}
1337
021230d4
AV		 1338/**
1339 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1340 * @irq: unused
1341 * @data: pointer to our q_vector struct for this interrupt vector
1342 **/
9a799d71
AK		 1343static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1344{
021230d4
AV		 1345 struct ixgbe_q_vector *q_vector = data;
1346 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1347 struct ixgbe_ring *rx_ring;
021230d4 1348 int r_idx;
30efa5a3 1349 int i;
021230d4
AV		 1350
1351 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1352 for (i = 0; i < q_vector->rxr_count; i++) {
1353 rx_ring = &(adapter->rx_ring[r_idx]);
1354 rx_ring->total_bytes = 0;
1355 rx_ring->total_packets = 0;
1356 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1357 r_idx + 1);
1358 }
1359
021230d4
AV		 1360 if (!q_vector->rxr_count)
1361 return IRQ_HANDLED;
1362
021230d4 1363 /* disable interrupts on this vector only */
9b471446 1364 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1365 napi_schedule(&q_vector->napi);
021230d4
AV		 1366
1367 return IRQ_HANDLED;
1368}
1369
1370static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1371{
91281fd3
AD		 1372 struct ixgbe_q_vector *q_vector = data;
1373 struct ixgbe_adapter *adapter = q_vector->adapter;
1374 struct ixgbe_ring *ring;
1375 int r_idx;
1376 int i;
1377
1378 if (!q_vector->txr_count && !q_vector->rxr_count)
1379 return IRQ_HANDLED;
1380
1381 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1382 for (i = 0; i < q_vector->txr_count; i++) {
1383 ring = &(adapter->tx_ring[r_idx]);
1384 ring->total_bytes = 0;
1385 ring->total_packets = 0;
1386 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1387 r_idx + 1);
1388 }
1389
1390 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1391 for (i = 0; i < q_vector->rxr_count; i++) {
1392 ring = &(adapter->rx_ring[r_idx]);
1393 ring->total_bytes = 0;
1394 ring->total_packets = 0;
1395 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1396 r_idx + 1);
1397 }
1398
9b471446 1399 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1400 napi_schedule(&q_vector->napi);
9a799d71 1401
9a799d71
AK		 1402 return IRQ_HANDLED;
1403}
1404
021230d4
AV		 1405/**
1406 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1407 * @napi: napi struct with our devices info in it
1408 * @budget: amount of work driver is allowed to do this pass, in packets
1409 *
f0848276
JB		 1410 * This function is optimized for cleaning one queue only on a single
1411 * q_vector!!!
021230d4 1412 **/
9a799d71
AK		 1413static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1414{
021230d4 1415 struct ixgbe_q_vector *q_vector =
b4617240 1416 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1417 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1418 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1419 int work_done = 0;
021230d4 1420 long r_idx;
9a799d71 1421
021230d4 1422 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1423 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1424#ifdef CONFIG_IXGBE_DCA
bd0362dd 1425 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1426 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1427#endif
9a799d71 1428
78b6f4ce 1429 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1430
021230d4
AV		 1431 /* If all Rx work done, exit the polling mode */
1432 if (work_done < budget) {
288379f0 1433 napi_complete(napi);
f7554a2b 1434 if (adapter->rx_itr_setting & 1)
f494e8fa 1435 ixgbe_set_itr_msix(q_vector);
9a799d71 1436 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1437 ixgbe_irq_enable_queues(adapter,
1438 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1439 }
1440
1441 return work_done;
1442}
1443
f0848276 1444/**
91281fd3 1445 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1446 * @napi: napi struct with our devices info in it
1447 * @budget: amount of work driver is allowed to do this pass, in packets
1448 *
1449 * This function will clean more than one rx queue associated with a
1450 * q_vector.
1451 **/
91281fd3 1452static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1453{
1454 struct ixgbe_q_vector *q_vector =
1455 container_of(napi, struct ixgbe_q_vector, napi);
1456 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1457 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1458 int work_done = 0, i;
1459 long r_idx;
91281fd3
AD		 1460 bool tx_clean_complete = true;
1461
1462 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1463 for (i = 0; i < q_vector->txr_count; i++) {
1464 ring = &(adapter->tx_ring[r_idx]);
1465#ifdef CONFIG_IXGBE_DCA
1466 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1467 ixgbe_update_tx_dca(adapter, ring);
1468#endif
1469 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1470 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1471 r_idx + 1);
1472 }
f0848276
JB		 1473
1474 /* attempt to distribute budget to each queue fairly, but don't allow
1475 * the budget to go below 1 because we'll exit polling */
1476 budget /= (q_vector->rxr_count ?: 1);
1477 budget = max(budget, 1);
1478 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1479 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1480 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1481#ifdef CONFIG_IXGBE_DCA
f0848276 1482 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1483 ixgbe_update_rx_dca(adapter, ring);
f0848276 1484#endif
91281fd3 1485 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1486 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1487 r_idx + 1);
1488 }
1489
1490 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1491 ring = &(adapter->rx_ring[r_idx]);
f0848276 1492 /* If all Rx work done, exit the polling mode */
7f821875 1493 if (work_done < budget) {
288379f0 1494 napi_complete(napi);
f7554a2b 1495 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1496 ixgbe_set_itr_msix(q_vector);
1497 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1498 ixgbe_irq_enable_queues(adapter,
1499 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1500 return 0;
1501 }
1502
1503 return work_done;
1504}
91281fd3
AD		 1505
1506/**
1507 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1508 * @napi: napi struct with our devices info in it
1509 * @budget: amount of work driver is allowed to do this pass, in packets
1510 *
1511 * This function is optimized for cleaning one queue only on a single
1512 * q_vector!!!
1513 **/
1514static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1515{
1516 struct ixgbe_q_vector *q_vector =
1517 container_of(napi, struct ixgbe_q_vector, napi);
1518 struct ixgbe_adapter *adapter = q_vector->adapter;
1519 struct ixgbe_ring *tx_ring = NULL;
1520 int work_done = 0;
1521 long r_idx;
1522
1523 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1524 tx_ring = &(adapter->tx_ring[r_idx]);
1525#ifdef CONFIG_IXGBE_DCA
1526 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1527 ixgbe_update_tx_dca(adapter, tx_ring);
1528#endif
1529
1530 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1531 work_done = budget;
1532
f7554a2b 1533 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1534 if (work_done < budget) {
1535 napi_complete(napi);
f7554a2b 1536 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1537 ixgbe_set_itr_msix(q_vector);
1538 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1539 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1540 }
1541
1542 return work_done;
1543}
1544
021230d4 1545static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1546 int r_idx)
021230d4 1547{
7a921c93
AD		 1548 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1549
1550 set_bit(r_idx, q_vector->rxr_idx);
1551 q_vector->rxr_count++;
021230d4
AV		 1552}
1553
1554static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1555 int t_idx)
021230d4 1556{
7a921c93
AD		 1557 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1558
1559 set_bit(t_idx, q_vector->txr_idx);
1560 q_vector->txr_count++;
021230d4
AV		 1561}
1562
9a799d71 1563/**
021230d4
AV		 1564 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1565 * @adapter: board private structure to initialize
1566 * @vectors: allotted vector count for descriptor rings
9a799d71 1567 *
021230d4
AV		 1568 * This function maps descriptor rings to the queue-specific vectors
1569 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1570 * one vector per ring/queue, but on a constrained vector budget, we
1571 * group the rings as "efficiently" as possible. You would add new
1572 * mapping configurations in here.
9a799d71 1573 **/
021230d4 1574static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1575 int vectors)
021230d4
AV		 1576{
1577 int v_start = 0;
1578 int rxr_idx = 0, txr_idx = 0;
1579 int rxr_remaining = adapter->num_rx_queues;
1580 int txr_remaining = adapter->num_tx_queues;
1581 int i, j;
1582 int rqpv, tqpv;
1583 int err = 0;
1584
1585 /* No mapping required if MSI-X is disabled. */
1586 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1587 goto out;
9a799d71 1588
021230d4
AV		 1589 /*
1590 * The ideal configuration...
1591 * We have enough vectors to map one per queue.
1592 */
1593 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1594 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1595 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1596
021230d4
AV		 1597 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1598 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1599
9a799d71 1600 goto out;
021230d4 1601 }
9a799d71 1602
021230d4
AV		 1603 /*
1604 * If we don't have enough vectors for a 1-to-1
1605 * mapping, we'll have to group them so there are
1606 * multiple queues per vector.
1607 */
1608 /* Re-adjusting *qpv takes care of the remainder. */
1609 for (i = v_start; i < vectors; i++) {
1610 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1611 for (j = 0; j < rqpv; j++) {
1612 map_vector_to_rxq(adapter, i, rxr_idx);
1613 rxr_idx++;
1614 rxr_remaining--;
1615 }
1616 }
1617 for (i = v_start; i < vectors; i++) {
1618 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1619 for (j = 0; j < tqpv; j++) {
1620 map_vector_to_txq(adapter, i, txr_idx);
1621 txr_idx++;
1622 txr_remaining--;
9a799d71 1623 }
9a799d71
AK		 1624 }
1625
021230d4
AV		 1626out:
1627 return err;
1628}
1629
1630/**
1631 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1632 * @adapter: board private structure
1633 *
1634 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1635 * interrupts from the kernel.
1636 **/
1637static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1638{
1639 struct net_device *netdev = adapter->netdev;
1640 irqreturn_t (*handler)(int, void *);
1641 int i, vector, q_vectors, err;
cb13fc20 1642 int ri=0, ti=0;
021230d4
AV		 1643
1644 /* Decrement for Other and TCP Timer vectors */
1645 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1646
1647 /* Map the Tx/Rx rings to the vectors we were allotted. */
1648 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1649 if (err)
1650 goto out;
1651
1652#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1653 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1654 &ixgbe_msix_clean_many)
021230d4 1655 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1656 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1657
1658 if(handler == &ixgbe_msix_clean_rx) {
1659 sprintf(adapter->name[vector], "%s-%s-%d",
1660 netdev->name, "rx", ri++);
1661 }
1662 else if(handler == &ixgbe_msix_clean_tx) {
1663 sprintf(adapter->name[vector], "%s-%s-%d",
1664 netdev->name, "tx", ti++);
1665 }
1666 else
1667 sprintf(adapter->name[vector], "%s-%s-%d",
1668 netdev->name, "TxRx", vector);
1669
021230d4 1670 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1671 handler, 0, adapter->name[vector],
7a921c93 1672 adapter->q_vector[vector]);
9a799d71
AK		 1673 if (err) {
1674 DPRINTK(PROBE, ERR,
b4617240
PW		 1675 "request_irq failed for MSIX interrupt "
1676 "Error: %d\n", err);
021230d4 1677 goto free_queue_irqs;
9a799d71 1678 }
9a799d71
AK		 1679 }
1680
021230d4
AV		 1681 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1682 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1683 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1684 if (err) {
1685 DPRINTK(PROBE, ERR,
1686 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1687 goto free_queue_irqs;
9a799d71
AK		 1688 }
1689
9a799d71
AK		 1690 return 0;
1691
021230d4
AV		 1692free_queue_irqs:
1693 for (i = vector - 1; i >= 0; i--)
1694 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1695 adapter->q_vector[i]);
021230d4
AV		 1696 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1697 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1698 kfree(adapter->msix_entries);
1699 adapter->msix_entries = NULL;
021230d4 1700out:
9a799d71
AK		 1701 return err;
1702}
1703
f494e8fa
AV		 1704static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1705{
7a921c93 1706 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1707 u8 current_itr;
1708 u32 new_itr = q_vector->eitr;
1709 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1710 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1711
30efa5a3 1712 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1713 q_vector->tx_itr,
1714 tx_ring->total_packets,
1715 tx_ring->total_bytes);
30efa5a3 1716 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1717 q_vector->rx_itr,
1718 rx_ring->total_packets,
1719 rx_ring->total_bytes);
f494e8fa 1720
30efa5a3 1721 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1722
1723 switch (current_itr) {
1724 /* counts and packets in update_itr are dependent on these numbers */
1725 case lowest_latency:
1726 new_itr = 100000;
1727 break;
1728 case low_latency:
1729 new_itr = 20000; /* aka hwitr = ~200 */
1730 break;
1731 case bulk_latency:
1732 new_itr = 8000;
1733 break;
1734 default:
1735 break;
1736 }
1737
1738 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1739 /* do an exponential smoothing */
1740 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1741
1742 /* save the algorithm value here, not the smoothed one */
1743 q_vector->eitr = new_itr;
fe49f04a
AD		 1744
1745 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1746 }
1747
1748 return;
1749}
1750
79aefa45
AD		 1751/**
1752 * ixgbe_irq_enable - Enable default interrupt generation settings
1753 * @adapter: board private structure
1754 **/
1755static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1756{
1757 u32 mask;
835462fc
NS		 1758
1759 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1760 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1761 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1762 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1763 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1764 mask |= IXGBE_EIMS_GPI_SDP1;
1765 mask |= IXGBE_EIMS_GPI_SDP2;
1766 }
c4cf55e5
PWJ		 1767 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1768 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1769 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1770
79aefa45 1771 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1772 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1773 IXGBE_WRITE_FLUSH(&adapter->hw);
1774}
021230d4 1775
9a799d71 1776/**
021230d4 1777 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1778 * @irq: interrupt number
1779 * @data: pointer to a network interface device structure
9a799d71
AK		 1780 **/
1781static irqreturn_t ixgbe_intr(int irq, void *data)
1782{
1783 struct net_device *netdev = data;
1784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1785 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1786 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1787 u32 eicr;
1788
54037505
DS		 1789 /*
1790 * Workaround for silicon errata. Mask the interrupts
1791 * before the read of EICR.
1792 */
1793 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1794
021230d4
AV		 1795 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1796 * therefore no explict interrupt disable is necessary */
1797 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1798 if (!eicr) {
1799 /* shared interrupt alert!
1800 * make sure interrupts are enabled because the read will
1801 * have disabled interrupts due to EIAM */
1802 ixgbe_irq_enable(adapter);
9a799d71 1803 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1804 }
9a799d71 1805
cf8280ee
JB		 1806 if (eicr & IXGBE_EICR_LSC)
1807 ixgbe_check_lsc(adapter);
021230d4 1808
e8e26350
PW		 1809 if (hw->mac.type == ixgbe_mac_82599EB)
1810 ixgbe_check_sfp_event(adapter, eicr);
1811
0befdb3e
JB		 1812 ixgbe_check_fan_failure(adapter, eicr);
1813
7a921c93 1814 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1815 adapter->tx_ring[0].total_packets = 0;
1816 adapter->tx_ring[0].total_bytes = 0;
1817 adapter->rx_ring[0].total_packets = 0;
1818 adapter->rx_ring[0].total_bytes = 0;
021230d4 1819 /* would disable interrupts here but EIAM disabled it */
7a921c93 1820 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1821 }
1822
1823 return IRQ_HANDLED;
1824}
1825
021230d4
AV		 1826static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1827{
1828 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1829
1830 for (i = 0; i < q_vectors; i++) {
7a921c93 1831 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1832 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1833 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1834 q_vector->rxr_count = 0;
1835 q_vector->txr_count = 0;
1836 }
1837}
1838
9a799d71
AK		 1839/**
1840 * ixgbe_request_irq - initialize interrupts
1841 * @adapter: board private structure
1842 *
1843 * Attempts to configure interrupts using the best available
1844 * capabilities of the hardware and kernel.
1845 **/
021230d4 1846static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1847{
1848 struct net_device *netdev = adapter->netdev;
021230d4 1849 int err;
9a799d71 1850
021230d4
AV		 1851 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1852 err = ixgbe_request_msix_irqs(adapter);
1853 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1854 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1855 netdev->name, netdev);
021230d4 1856 } else {
a0607fd3 1857 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1858 netdev->name, netdev);
9a799d71
AK		 1859 }
1860
9a799d71
AK		 1861 if (err)
1862 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1863
9a799d71
AK		 1864 return err;
1865}
1866
1867static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1868{
1869 struct net_device *netdev = adapter->netdev;
1870
1871 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1872 int i, q_vectors;
9a799d71 1873
021230d4
AV		 1874 q_vectors = adapter->num_msix_vectors;
1875
1876 i = q_vectors - 1;
9a799d71 1877 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1878
021230d4
AV		 1879 i--;
1880 for (; i >= 0; i--) {
1881 free_irq(adapter->msix_entries[i].vector,
7a921c93 1882 adapter->q_vector[i]);
021230d4
AV		 1883 }
1884
1885 ixgbe_reset_q_vectors(adapter);
1886 } else {
1887 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1888 }
1889}
1890
22d5a71b
JB		 1891/**
1892 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1893 * @adapter: board private structure
1894 **/
1895static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1896{
835462fc
NS		 1897 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1899 } else {
1900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1903 }
1904 IXGBE_WRITE_FLUSH(&adapter->hw);
1905 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1906 int i;
1907 for (i = 0; i < adapter->num_msix_vectors; i++)
1908 synchronize_irq(adapter->msix_entries[i].vector);
1909 } else {
1910 synchronize_irq(adapter->pdev->irq);
1911 }
1912}
1913
9a799d71
AK		 1914/**
1915 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1916 *
1917 **/
1918static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1919{
9a799d71
AK		 1920 struct ixgbe_hw *hw = &adapter->hw;
1921
021230d4 1922 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1923 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1924
e8e26350
PW		 1925 ixgbe_set_ivar(adapter, 0, 0, 0);
1926 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1927
1928 map_vector_to_rxq(adapter, 0, 0);
1929 map_vector_to_txq(adapter, 0, 0);
1930
1931 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1932}
1933
1934/**
3a581073 1935 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1936 * @adapter: board private structure
1937 *
1938 * Configure the Tx unit of the MAC after a reset.
1939 **/
1940static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1941{
12207e49 1942 u64 tdba;
9a799d71 1943 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1944 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1945
1946 /* Setup the HW Tx Head and Tail descriptor pointers */
1947 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1948 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1949 j = ring->reg_idx;
1950 tdba = ring->dma;
1951 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1952 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1953 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1954 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1955 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1956 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1957 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1958 adapter->tx_ring[i].head = IXGBE_TDH(j);
1959 adapter->tx_ring[i].tail = IXGBE_TDT(j);
84f62d4b
PWJ		 1960 /*
1961 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 1962 * bookkeeping if things aren't delivered in order.
1963 */
84f62d4b
PWJ		 1964 switch (hw->mac.type) {
1965 case ixgbe_mac_82598EB:
1966 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1967 break;
1968 case ixgbe_mac_82599EB:
1969 default:
1970 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1971 break;
1972 }
021230d4 1973 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 1974 switch (hw->mac.type) {
1975 case ixgbe_mac_82598EB:
1976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1977 break;
1978 case ixgbe_mac_82599EB:
1979 default:
1980 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1981 break;
1982 }
9a799d71 1983 }
ee5f784a 1984
e8e26350 1985 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a
DS		 1986 u32 rttdcs;
1987
1988 /* disable the arbiter while setting MTQC */
1989 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1990 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1991 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1992
e8e26350
PW		 1993 /* We enable 8 traffic classes, DCB only */
1994 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1995 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1996 IXGBE_MTQC_8TC_8TQ));
ee5f784a
DS		 1997 else
1998 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1999
2000 /* re-eable the arbiter */
2001 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2002 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2003 }
9a799d71
AK		 2004}
2005
e8e26350 2006#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2007
a6616b42
YZ		 2008static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2009 struct ixgbe_ring *rx_ring)
cc41ac7c 2010{
cc41ac7c 2011 u32 srrctl;
a6616b42 2012 int index;
0cefafad 2013 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2014
a6616b42
YZ		 2015 index = rx_ring->reg_idx;
2016 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2017 unsigned long mask;
0cefafad 2018 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2019 index = index & mask;
cc41ac7c 2020 }
cc41ac7c
JB		 2021 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2022
2023 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2024 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2025
afafd5b0
AD		 2026 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2027 IXGBE_SRRCTL_BSIZEHDR_MASK;
2028
6e455b89 2029 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2030#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2031 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2032#else
2033 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2034#endif
cc41ac7c 2035 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2036 } else {
afafd5b0
AD		 2037 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2038 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2039 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2040 }
e8e26350 2041
cc41ac7c
JB		 2042 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2043}
9a799d71 2044
0cefafad
JB		 2045static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2046{
2047 u32 mrqc = 0;
2048 int mask;
2049
2050 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2051 return mrqc;
2052
2053 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2054#ifdef CONFIG_IXGBE_DCB
2055 | IXGBE_FLAG_DCB_ENABLED
2056#endif
2057 );
2058
2059 switch (mask) {
2060 case (IXGBE_FLAG_RSS_ENABLED):
2061 mrqc = IXGBE_MRQC_RSSEN;
2062 break;
2063#ifdef CONFIG_IXGBE_DCB
2064 case (IXGBE_FLAG_DCB_ENABLED):
2065 mrqc = IXGBE_MRQC_RT8TCEN;
2066 break;
2067#endif /* CONFIG_IXGBE_DCB */
2068 default:
2069 break;
2070 }
2071
2072 return mrqc;
2073}
2074
bb5a9ad2
NS		 2075/**
2076 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2077 * @adapter: address of board private structure
2078 * @index: index of ring to set
bb5a9ad2 2079 **/
edd2ea55 2080static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2081{
2082 struct ixgbe_ring *rx_ring;
2083 struct ixgbe_hw *hw = &adapter->hw;
2084 int j;
2085 u32 rscctrl;
edd2ea55 2086 int rx_buf_len;
bb5a9ad2
NS		 2087
2088 rx_ring = &adapter->rx_ring[index];
2089 j = rx_ring->reg_idx;
edd2ea55 2090 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2091 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2092 rscctrl |= IXGBE_RSCCTL_RSCEN;
2093 /*
2094 * we must limit the number of descriptors so that the
2095 * total size of max desc * buf_len is not greater
2096 * than 65535
2097 */
2098 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2099#if (MAX_SKB_FRAGS > 16)
2100 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2101#elif (MAX_SKB_FRAGS > 8)
2102 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2103#elif (MAX_SKB_FRAGS > 4)
2104 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2105#else
2106 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2107#endif
2108 } else {
2109 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2110 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2111 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2112 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2113 else
2114 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2115 }
2116 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2117}
2118
9a799d71 2119/**
3a581073 2120 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2121 * @adapter: board private structure
2122 *
2123 * Configure the Rx unit of the MAC after a reset.
2124 **/
2125static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2126{
2127 u64 rdba;
2128 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2129 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2130 struct net_device *netdev = adapter->netdev;
2131 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2132 int i, j;
9a799d71 2133 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2134 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2135 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2136 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2137 u32 fctrl, hlreg0;
509ee935 2138 u32 reta = 0, mrqc = 0;
cc41ac7c 2139 u32 rdrxctl;
7c6e0a43 2140 int rx_buf_len;
9a799d71
AK		 2141
2142 /* Decide whether to use packet split mode or not */
762f4c57 2143 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2144
2145 /* Set the RX buffer length according to the mode */
2146 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2147 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2148 if (hw->mac.type == ixgbe_mac_82599EB) {
2149 /* PSRTYPE must be initialized in 82599 */
2150 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2151 IXGBE_PSRTYPE_UDPHDR |
2152 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2153 IXGBE_PSRTYPE_IPV6HDR |
2154 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2155 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2156 }
9a799d71 2157 } else {
0c19d6af 2158 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2159 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2160 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2161 else
7c6e0a43 2162 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2163 }
2164
2165 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2166 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2167 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2168 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2170
2171 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2172 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2173 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2174 else
2175 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2176#ifdef IXGBE_FCOE
f34c5c82 2177 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2178 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2179#endif
9a799d71
AK		 2180 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2181
9a799d71
AK		 2182 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2183 /* disable receives while setting up the descriptors */
2184 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2185 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2186
0cefafad
JB		 2187 /*
2188 * Setup the HW Rx Head and Tail Descriptor Pointers and
2189 * the Base and Length of the Rx Descriptor Ring
2190 */
9a799d71 2191 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2192 rx_ring = &adapter->rx_ring[i];
2193 rdba = rx_ring->dma;
2194 j = rx_ring->reg_idx;
284901a9 2195 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2196 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2197 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2198 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2199 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2200 rx_ring->head = IXGBE_RDH(j);
2201 rx_ring->tail = IXGBE_RDT(j);
2202 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2203
6e455b89
YZ		 2204 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2205 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2206 else
2207 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2208
63f39bd1 2209#ifdef IXGBE_FCOE
f34c5c82 2210 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2211 struct ixgbe_ring_feature *f;
2212 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2213 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2214 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2215 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2216 rx_ring->rx_buf_len =
2217 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2218 }
63f39bd1
YZ		 2219 }
2220
2221#endif /* IXGBE_FCOE */
a6616b42 2222 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2223 }
2224
e8e26350
PW		 2225 if (hw->mac.type == ixgbe_mac_82598EB) {
2226 /*
2227 * For VMDq support of different descriptor types or
2228 * buffer sizes through the use of multiple SRRCTL
2229 * registers, RDRXCTL.MVMEN must be set to 1
2230 *
2231 * also, the manual doesn't mention it clearly but DCA hints
2232 * will only use queue 0's tags unless this bit is set. Side
2233 * effects of setting this bit are only that SRRCTL must be
2234 * fully programmed [0..15]
2235 */
2a41ff81
JB		 2236 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2237 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2238 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2239 }
177db6ff 2240
e8e26350 2241 /* Program MRQC for the distribution of queues */
0cefafad 2242 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2243
021230d4 2244 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2245 /* Fill out redirection table */
021230d4
AV		 2246 for (i = 0, j = 0; i < 128; i++, j++) {
2247 if (j == adapter->ring_feature[RING_F_RSS].indices)
2248 j = 0;
2249 /* reta = 4-byte sliding window of
2250 * 0x00..(indices-1)(indices-1)00..etc. */
2251 reta = (reta << 8) | (j * 0x11);
2252 if ((i & 3) == 3)
2253 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2254 }
2255
2256 /* Fill out hash function seeds */
2257 for (i = 0; i < 10; i++)
7c6e0a43 2258 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2259
2a41ff81
JB		 2260 if (hw->mac.type == ixgbe_mac_82598EB)
2261 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2262 /* Perform hash on these packet types */
2a41ff81
JB		 2263 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2264 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2265 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2266 | IXGBE_MRQC_RSS_FIELD_IPV6
2267 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2268 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2269 }
2a41ff81 2270 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2271
021230d4
AV		 2272 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2273
2274 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2275 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2276 /* Disable indicating checksum in descriptor, enables
2277 * RSS hash */
9a799d71 2278 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2279 }
021230d4
AV		 2280 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2281 /* Enable IPv4 payload checksum for UDP fragments
2282 * if PCSD is not set */
2283 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2284 }
2285
2286 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2287
2288 if (hw->mac.type == ixgbe_mac_82599EB) {
2289 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2290 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2291 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2292 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2293 }
f8212f97 2294
0c19d6af 2295 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2296 /* Enable 82599 HW-RSC */
bb5a9ad2 2297 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2298 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2299
f8212f97
AD		 2300 /* Disable RSC for ACK packets */
2301 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2302 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2303 }
9a799d71
AK		 2304}
2305
068c89b0
DS		 2306static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2307{
2308 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2309 struct ixgbe_hw *hw = &adapter->hw;
2310
2311 /* add VID to filter table */
2312 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2313}
2314
2315static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2316{
2317 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2318 struct ixgbe_hw *hw = &adapter->hw;
2319
2320 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2321 ixgbe_irq_disable(adapter);
2322
2323 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2324
2325 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2326 ixgbe_irq_enable(adapter);
2327
2328 /* remove VID from filter table */
2329 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2330}
2331
9a799d71 2332static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2333 struct vlan_group *grp)
9a799d71
AK		 2334{
2335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2336 u32 ctrl;
e8e26350 2337 int i, j;
9a799d71 2338
d4f80882
AV		 2339 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2340 ixgbe_irq_disable(adapter);
9a799d71
AK		 2341 adapter->vlgrp = grp;
2342
2f90b865
AD		 2343 /*
2344 * For a DCB driver, always enable VLAN tag stripping so we can
2345 * still receive traffic from a DCB-enabled host even if we're
2346 * not in DCB mode.
2347 */
2348 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
dc63d377
AD		 2349
2350 /* Disable CFI check */
2351 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2352
2353 /* enable VLAN tag stripping */
e8e26350 2354 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
dc63d377 2355 ctrl |= IXGBE_VLNCTRL_VME;
e8e26350 2356 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
e8e26350 2357 for (i = 0; i < adapter->num_rx_queues; i++) {
dc63d377 2358 u32 ctrl;
e8e26350
PW		 2359 j = adapter->rx_ring[i].reg_idx;
2360 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2361 ctrl |= IXGBE_RXDCTL_VME;
2362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2363 }
9a799d71 2364 }
dc63d377
AD		 2365
2366 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2367
e8e26350 2368 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2369
d4f80882
AV		 2370 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2371 ixgbe_irq_enable(adapter);
9a799d71
AK		 2372}
2373
9a799d71
AK		 2374static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2375{
2376 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2377
2378 if (adapter->vlgrp) {
2379 u16 vid;
2380 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2381 if (!vlan_group_get_device(adapter->vlgrp, vid))
2382 continue;
2383 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2384 }
2385 }
2386}
2387
2c5645cf
CL		 2388static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2389{
2390 struct dev_mc_list *mc_ptr;
2391 u8 *addr = *mc_addr_ptr;
2392 *vmdq = 0;
2393
2394 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2395 if (mc_ptr->next)
2396 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2397 else
2398 *mc_addr_ptr = NULL;
2399
2400 return addr;
2401}
2402
9a799d71 2403/**
2c5645cf 2404 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2405 * @netdev: network interface device structure
2406 *
2c5645cf
CL		 2407 * The set_rx_method entry point is called whenever the unicast/multicast
2408 * address list or the network interface flags are updated. This routine is
2409 * responsible for configuring the hardware for proper unicast, multicast and
2410 * promiscuous mode.
9a799d71 2411 **/
2c5645cf 2412static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2413{
2414 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2415 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2416 u32 fctrl, vlnctrl;
2c5645cf
CL		 2417 u8 *addr_list = NULL;
2418 int addr_count = 0;
9a799d71
AK		 2419
2420 /* Check for Promiscuous and All Multicast modes */
2421
2422 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2423 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2424
2425 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2426 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2427 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2428 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2429 } else {
746b9f02
PM		 2430 if (netdev->flags & IFF_ALLMULTI) {
2431 fctrl |= IXGBE_FCTRL_MPE;
2432 fctrl &= ~IXGBE_FCTRL_UPE;
2433 } else {
2434 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2435 }
3d01625a 2436 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2437 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2438 }
2439
2440 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2441 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2442
2c5645cf 2443 /* reprogram secondary unicast list */
31278e71 2444 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2445
2c5645cf
CL		 2446 /* reprogram multicast list */
2447 addr_count = netdev->mc_count;
2448 if (addr_count)
2449 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2450 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2451 ixgbe_addr_list_itr);
9a799d71
AK		 2452}
2453
021230d4
AV		 2454static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2455{
2456 int q_idx;
2457 struct ixgbe_q_vector *q_vector;
2458 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2459
2460 /* legacy and MSI only use one vector */
2461 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2462 q_vectors = 1;
2463
2464 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2465 struct napi_struct *napi;
7a921c93 2466 q_vector = adapter->q_vector[q_idx];
f0848276 2467 napi = &q_vector->napi;
91281fd3
AD		 2468 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2469 if (!q_vector->rxr_count || !q_vector->txr_count) {
2470 if (q_vector->txr_count == 1)
2471 napi->poll = &ixgbe_clean_txonly;
2472 else if (q_vector->rxr_count == 1)
2473 napi->poll = &ixgbe_clean_rxonly;
2474 }
2475 }
f0848276
JB		 2476
2477 napi_enable(napi);
021230d4
AV		 2478 }
2479}
2480
2481static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2482{
2483 int q_idx;
2484 struct ixgbe_q_vector *q_vector;
2485 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2486
2487 /* legacy and MSI only use one vector */
2488 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2489 q_vectors = 1;
2490
2491 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2492 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2493 napi_disable(&q_vector->napi);
2494 }
2495}
2496
7a6b6f51 2497#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2498/*
2499 * ixgbe_configure_dcb - Configure DCB hardware
2500 * @adapter: ixgbe adapter struct
2501 *
2502 * This is called by the driver on open to configure the DCB hardware.
2503 * This is also called by the gennetlink interface when reconfiguring
2504 * the DCB state.
2505 */
2506static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2507{
2508 struct ixgbe_hw *hw = &adapter->hw;
2509 u32 txdctl, vlnctrl;
2510 int i, j;
2511
2512 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2513 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2514 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2515
2516 /* reconfigure the hardware */
2517 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2518
2519 for (i = 0; i < adapter->num_tx_queues; i++) {
2520 j = adapter->tx_ring[i].reg_idx;
2521 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2522 /* PThresh workaround for Tx hang with DFP enabled. */
2523 txdctl |= 32;
2524 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2525 }
2526 /* Enable VLAN tag insert/strip */
2527 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2528 if (hw->mac.type == ixgbe_mac_82598EB) {
2529 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2530 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2531 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2532 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2533 vlnctrl |= IXGBE_VLNCTRL_VFE;
2534 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2535 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2536 for (i = 0; i < adapter->num_rx_queues; i++) {
2537 j = adapter->rx_ring[i].reg_idx;
2538 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2539 vlnctrl |= IXGBE_RXDCTL_VME;
2540 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2541 }
2542 }
2f90b865
AD		 2543 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2544}
2545
2546#endif
9a799d71
AK		 2547static void ixgbe_configure(struct ixgbe_adapter *adapter)
2548{
2549 struct net_device *netdev = adapter->netdev;
c4cf55e5 2550 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2551 int i;
2552
2c5645cf 2553 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2554
2555 ixgbe_restore_vlan(adapter);
7a6b6f51 2556#ifdef CONFIG_IXGBE_DCB
2f90b865 2557 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2558 if (hw->mac.type == ixgbe_mac_82598EB)
2559 netif_set_gso_max_size(netdev, 32768);
2560 else
2561 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2562 ixgbe_configure_dcb(adapter);
2563 } else {
2564 netif_set_gso_max_size(netdev, 65536);
2565 }
2566#else
2567 netif_set_gso_max_size(netdev, 65536);
2568#endif
9a799d71 2569
eacd73f7
YZ		 2570#ifdef IXGBE_FCOE
2571 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2572 ixgbe_configure_fcoe(adapter);
2573
2574#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2575 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2576 for (i = 0; i < adapter->num_tx_queues; i++)
2577 adapter->tx_ring[i].atr_sample_rate =
2578 adapter->atr_sample_rate;
2579 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2580 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2581 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2582 }
2583
9a799d71
AK		 2584 ixgbe_configure_tx(adapter);
2585 ixgbe_configure_rx(adapter);
2586 for (i = 0; i < adapter->num_rx_queues; i++)
2587 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2588 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2589}
2590
e8e26350
PW		 2591static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2592{
2593 switch (hw->phy.type) {
2594 case ixgbe_phy_sfp_avago:
2595 case ixgbe_phy_sfp_ftl:
2596 case ixgbe_phy_sfp_intel:
2597 case ixgbe_phy_sfp_unknown:
2598 case ixgbe_phy_tw_tyco:
2599 case ixgbe_phy_tw_unknown:
2600 return true;
2601 default:
2602 return false;
2603 }
2604}
2605
0ecc061d 2606/**
e8e26350
PW		 2607 * ixgbe_sfp_link_config - set up SFP+ link
2608 * @adapter: pointer to private adapter struct
2609 **/
2610static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2611{
2612 struct ixgbe_hw *hw = &adapter->hw;
2613
2614 if (hw->phy.multispeed_fiber) {
2615 /*
2616 * In multispeed fiber setups, the device may not have
2617 * had a physical connection when the driver loaded.
2618 * If that's the case, the initial link configuration
2619 * couldn't get the MAC into 10G or 1G mode, so we'll
2620 * never have a link status change interrupt fire.
2621 * We need to try and force an autonegotiation
2622 * session, then bring up link.
2623 */
2624 hw->mac.ops.setup_sfp(hw);
2625 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2626 schedule_work(&adapter->multispeed_fiber_task);
2627 } else {
2628 /*
2629 * Direct Attach Cu and non-multispeed fiber modules
2630 * still need to be configured properly prior to
2631 * attempting link.
2632 */
2633 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2634 schedule_work(&adapter->sfp_config_module_task);
2635 }
2636}
2637
2638/**
2639 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2640 * @hw: pointer to private hardware struct
2641 *
2642 * Returns 0 on success, negative on failure
2643 **/
e8e26350 2644static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2645{
2646 u32 autoneg;
8620a103 2647 bool negotiation, link_up = false;
0ecc061d
PWJ		 2648 u32 ret = IXGBE_ERR_LINK_SETUP;
2649
2650 if (hw->mac.ops.check_link)
2651 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2652
2653 if (ret)
2654 goto link_cfg_out;
2655
2656 if (hw->mac.ops.get_link_capabilities)
8620a103 2657 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2658 if (ret)
2659 goto link_cfg_out;
2660
8620a103
MC		 2661 if (hw->mac.ops.setup_link)
2662 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2663link_cfg_out:
2664 return ret;
2665}
2666
e8e26350
PW		 2667#define IXGBE_MAX_RX_DESC_POLL 10
2668static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2669 int rxr)
2670{
2671 int j = adapter->rx_ring[rxr].reg_idx;
2672 int k;
2673
2674 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2675 if (IXGBE_READ_REG(&adapter->hw,
2676 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2677 break;
2678 else
2679 msleep(1);
2680 }
2681 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2682 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2683 "not set within the polling period\n", rxr);
2684 }
2685 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2686 (adapter->rx_ring[rxr].count - 1));
2687}
2688
9a799d71
AK		 2689static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2690{
2691 struct net_device *netdev = adapter->netdev;
9a799d71 2692 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2693 int i, j = 0;
e8e26350 2694 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2695 int err;
9a799d71 2696 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2697 u32 txdctl, rxdctl, mhadd;
e8e26350 2698 u32 dmatxctl;
021230d4 2699 u32 gpie;
9a799d71 2700
5eba3699
AV		 2701 ixgbe_get_hw_control(adapter);
2702
021230d4
AV		 2703 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2704 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2705 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2706 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2707 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2708 } else {
2709 /* MSI only */
021230d4 2710 gpie = 0;
9a799d71 2711 }
021230d4
AV		 2712 /* XXX: to interrupt immediately for EICS writes, enable this */
2713 /* gpie |= IXGBE_GPIE_EIMEN; */
2714 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2715 }
2716
9b471446
JB		 2717 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2718 /*
2719 * use EIAM to auto-mask when MSI-X interrupt is asserted
2720 * this saves a register write for every interrupt
2721 */
2722 switch (hw->mac.type) {
2723 case ixgbe_mac_82598EB:
2724 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2725 break;
2726 default:
2727 case ixgbe_mac_82599EB:
2728 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2729 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2730 break;
2731 }
2732 } else {
021230d4
AV		 2733 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2734 * specifically only auto mask tx and rx interrupts */
2735 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2736 }
9a799d71 2737
0befdb3e
JB		 2738 /* Enable fan failure interrupt if media type is copper */
2739 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2740 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2741 gpie |= IXGBE_SDP1_GPIEN;
2742 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2743 }
2744
e8e26350
PW		 2745 if (hw->mac.type == ixgbe_mac_82599EB) {
2746 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2747 gpie |= IXGBE_SDP1_GPIEN;
2748 gpie |= IXGBE_SDP2_GPIEN;
2749 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2750 }
2751
63f39bd1
YZ		 2752#ifdef IXGBE_FCOE
2753 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2754 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2755 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2756 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2757
2758#endif /* IXGBE_FCOE */
021230d4 2759 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2760 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2761 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2762 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2763
2764 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2765 }
2766
2767 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2768 j = adapter->tx_ring[i].reg_idx;
2769 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2770 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2771 txdctl |= (8 << 16);
e8e26350
PW		 2772 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2773 }
2774
2775 if (hw->mac.type == ixgbe_mac_82599EB) {
2776 /* DMATXCTL.EN must be set after all Tx queue config is done */
2777 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2778 dmatxctl |= IXGBE_DMATXCTL_TE;
2779 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2780 }
2781 for (i = 0; i < adapter->num_tx_queues; i++) {
2782 j = adapter->tx_ring[i].reg_idx;
2783 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2784 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2785 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2786 }
2787
e8e26350 2788 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2789 j = adapter->rx_ring[i].reg_idx;
2790 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2791 /* enable PTHRESH=32 descriptors (half the internal cache)
2792 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2793 * this also removes a pesky rx_no_buffer_count increment */
2794 rxdctl |= 0x0020;
9a799d71 2795 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2796 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2797 if (hw->mac.type == ixgbe_mac_82599EB)
2798 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2799 }
2800 /* enable all receives */
2801 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2802 if (hw->mac.type == ixgbe_mac_82598EB)
2803 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2804 else
2805 rxdctl |= IXGBE_RXCTRL_RXEN;
2806 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2807
2808 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2809 ixgbe_configure_msix(adapter);
2810 else
2811 ixgbe_configure_msi_and_legacy(adapter);
2812
2813 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2814 ixgbe_napi_enable_all(adapter);
2815
2816 /* clear any pending interrupts, may auto mask */
2817 IXGBE_READ_REG(hw, IXGBE_EICR);
2818
9a799d71
AK		 2819 ixgbe_irq_enable(adapter);
2820
bf069c97
DS		 2821 /*
2822 * If this adapter has a fan, check to see if we had a failure
2823 * before we enabled the interrupt.
2824 */
2825 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2826 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2827 if (esdp & IXGBE_ESDP_SDP1)
2828 DPRINTK(DRV, CRIT,
2829 "Fan has stopped, replace the adapter\n");
2830 }
2831
e8e26350
PW		 2832 /*
2833 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2834 * arrived before interrupts were enabled but after probe. Such
2835 * devices wouldn't have their type identified yet. We need to
2836 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2837 * If we're not hot-pluggable SFP+, we just need to configure link
2838 * and bring it up.
2839 */
19343de2
DS		 2840 if (hw->phy.type == ixgbe_phy_unknown) {
2841 err = hw->phy.ops.identify(hw);
2842 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2843 /*
2844 * Take the device down and schedule the sfp tasklet
2845 * which will unregister_netdev and log it.
2846 */
19343de2 2847 ixgbe_down(adapter);
5da43c1a 2848 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2849 return err;
2850 }
e8e26350
PW		 2851 }
2852
2853 if (ixgbe_is_sfp(hw)) {
2854 ixgbe_sfp_link_config(adapter);
2855 } else {
2856 err = ixgbe_non_sfp_link_config(hw);
2857 if (err)
2858 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2859 }
0ecc061d 2860
c4cf55e5
PWJ		 2861 for (i = 0; i < adapter->num_tx_queues; i++)
2862 set_bit(__IXGBE_FDIR_INIT_DONE,
2863 &(adapter->tx_ring[i].reinit_state));
2864
1da100bb
PWJ		 2865 /* enable transmits */
2866 netif_tx_start_all_queues(netdev);
2867
9a799d71
AK		 2868 /* bring the link up in the watchdog, this could race with our first
2869 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2870 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2871 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2872 mod_timer(&adapter->watchdog_timer, jiffies);
2873 return 0;
2874}
2875
d4f80882
AV		 2876void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2877{
2878 WARN_ON(in_interrupt());
2879 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2880 msleep(1);
2881 ixgbe_down(adapter);
2882 ixgbe_up(adapter);
2883 clear_bit(__IXGBE_RESETTING, &adapter->state);
2884}
2885
9a799d71
AK		 2886int ixgbe_up(struct ixgbe_adapter *adapter)
2887{
2888 /* hardware has been reset, we need to reload some things */
2889 ixgbe_configure(adapter);
2890
2891 return ixgbe_up_complete(adapter);
2892}
2893
2894void ixgbe_reset(struct ixgbe_adapter *adapter)
2895{
c44ade9e 2896 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2897 int err;
2898
2899 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2900 switch (err) {
2901 case 0:
2902 case IXGBE_ERR_SFP_NOT_PRESENT:
2903 break;
2904 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2905 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2906 break;
794caeb2
PWJ		 2907 case IXGBE_ERR_EEPROM_VERSION:
2908 /* We are running on a pre-production device, log a warning */
2909 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2910 "adapter/LOM. Please be aware there may be issues "
2911 "associated with your hardware. If you are "
2912 "experiencing problems please contact your Intel or "
2913 "hardware representative who provided you with this "
2914 "hardware.\n");
2915 break;
da4dd0f7
PWJ		 2916 default:
2917 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2918 }
9a799d71
AK		 2919
2920 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2921 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2922}
2923
9a799d71
AK		 2924/**
2925 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2926 * @adapter: board private structure
2927 * @rx_ring: ring to free buffers from
2928 **/
2929static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2930 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2931{
2932 struct pci_dev *pdev = adapter->pdev;
2933 unsigned long size;
2934 unsigned int i;
2935
2936 /* Free all the Rx ring sk_buffs */
2937
2938 for (i = 0; i < rx_ring->count; i++) {
2939 struct ixgbe_rx_buffer *rx_buffer_info;
2940
2941 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2942 if (rx_buffer_info->dma) {
2943 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2944 rx_ring->rx_buf_len,
2945 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2946 rx_buffer_info->dma = 0;
2947 }
2948 if (rx_buffer_info->skb) {
f8212f97 2949 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2950 rx_buffer_info->skb = NULL;
f8212f97
AD		 2951 do {
2952 struct sk_buff *this = skb;
2953 skb = skb->prev;
2954 dev_kfree_skb(this);
2955 } while (skb);
9a799d71
AK		 2956 }
2957 if (!rx_buffer_info->page)
2958 continue;
4f57ca6e
JB		 2959 if (rx_buffer_info->page_dma) {
2960 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2961 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2962 rx_buffer_info->page_dma = 0;
2963 }
9a799d71
AK		 2964 put_page(rx_buffer_info->page);
2965 rx_buffer_info->page = NULL;
762f4c57 2966 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2967 }
2968
2969 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2970 memset(rx_ring->rx_buffer_info, 0, size);
2971
2972 /* Zero out the descriptor ring */
2973 memset(rx_ring->desc, 0, rx_ring->size);
2974
2975 rx_ring->next_to_clean = 0;
2976 rx_ring->next_to_use = 0;
2977
9891ca7c
JB		 2978 if (rx_ring->head)
2979 writel(0, adapter->hw.hw_addr + rx_ring->head);
2980 if (rx_ring->tail)
2981 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2982}
2983
2984/**
2985 * ixgbe_clean_tx_ring - Free Tx Buffers
2986 * @adapter: board private structure
2987 * @tx_ring: ring to be cleaned
2988 **/
2989static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2990 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2991{
2992 struct ixgbe_tx_buffer *tx_buffer_info;
2993 unsigned long size;
2994 unsigned int i;
2995
2996 /* Free all the Tx ring sk_buffs */
2997
2998 for (i = 0; i < tx_ring->count; i++) {
2999 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3000 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3001 }
3002
3003 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3004 memset(tx_ring->tx_buffer_info, 0, size);
3005
3006 /* Zero out the descriptor ring */
3007 memset(tx_ring->desc, 0, tx_ring->size);
3008
3009 tx_ring->next_to_use = 0;
3010 tx_ring->next_to_clean = 0;
3011
9891ca7c
JB		 3012 if (tx_ring->head)
3013 writel(0, adapter->hw.hw_addr + tx_ring->head);
3014 if (tx_ring->tail)
3015 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3016}
3017
3018/**
021230d4 3019 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3020 * @adapter: board private structure
3021 **/
021230d4 3022static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3023{
3024 int i;
3025
021230d4
AV		 3026 for (i = 0; i < adapter->num_rx_queues; i++)
3027 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3028}
3029
3030/**
021230d4 3031 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3032 * @adapter: board private structure
3033 **/
021230d4 3034static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3035{
3036 int i;
3037
021230d4
AV		 3038 for (i = 0; i < adapter->num_tx_queues; i++)
3039 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3040}
3041
3042void ixgbe_down(struct ixgbe_adapter *adapter)
3043{
3044 struct net_device *netdev = adapter->netdev;
7f821875 3045 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3046 u32 rxctrl;
7f821875
JB		 3047 u32 txdctl;
3048 int i, j;
9a799d71
AK		 3049
3050 /* signal that we are down to the interrupt handler */
3051 set_bit(__IXGBE_DOWN, &adapter->state);
3052
3053 /* disable receives */
7f821875
JB		 3054 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3055 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3056
3057 netif_tx_disable(netdev);
3058
7f821875 3059 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3060 msleep(10);
3061
7f821875
JB		 3062 netif_tx_stop_all_queues(netdev);
3063
9a799d71
AK		 3064 ixgbe_irq_disable(adapter);
3065
021230d4 3066 ixgbe_napi_disable_all(adapter);
7f821875 3067
0a1f87cb
DS		 3068 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3069 del_timer_sync(&adapter->sfp_timer);
9a799d71 3070 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3071 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3072
c4cf55e5
PWJ		 3073 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3074 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3075 cancel_work_sync(&adapter->fdir_reinit_task);
3076
7f821875
JB		 3077 /* disable transmits in the hardware now that interrupts are off */
3078 for (i = 0; i < adapter->num_tx_queues; i++) {
3079 j = adapter->tx_ring[i].reg_idx;
3080 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3081 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3082 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3083 }
88512539
PW		 3084 /* Disable the Tx DMA engine on 82599 */
3085 if (hw->mac.type == ixgbe_mac_82599EB)
3086 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3087 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3088 ~IXGBE_DMATXCTL_TE));
7f821875 3089
9a799d71 3090 netif_carrier_off(netdev);
9a799d71 3091
6f4a0e45
PL		 3092 if (!pci_channel_offline(adapter->pdev))
3093 ixgbe_reset(adapter);
9a799d71
AK		 3094 ixgbe_clean_all_tx_rings(adapter);
3095 ixgbe_clean_all_rx_rings(adapter);
3096
5dd2d332 3097#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3098 /* since we reset the hardware DCA settings were cleared */
e35ec126 3099 ixgbe_setup_dca(adapter);
96b0e0f6 3100#endif
9a799d71
AK		 3101}
3102
9a799d71 3103/**
021230d4
AV		 3104 * ixgbe_poll - NAPI Rx polling callback
3105 * @napi: structure for representing this polling device
3106 * @budget: how many packets driver is allowed to clean
3107 *
3108 * This function is used for legacy and MSI, NAPI mode
9a799d71 3109 **/
021230d4 3110static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3111{
9a1a69ad
JB		 3112 struct ixgbe_q_vector *q_vector =
3113 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3114 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3115 int tx_clean_complete, work_done = 0;
9a799d71 3116
5dd2d332 3117#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 3118 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3119 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3120 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3121 }
3122#endif
3123
fe49f04a 3124 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 3125 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 3126
9a1a69ad 3127 if (!tx_clean_complete)
d2c7ddd6
DM		 3128 work_done = budget;
3129
53e52c72
DM		 3130 /* If budget not fully consumed, exit the polling mode */
3131 if (work_done < budget) {
288379f0 3132 napi_complete(napi);
f7554a2b 3133 if (adapter->rx_itr_setting & 1)
f494e8fa 3134 ixgbe_set_itr(adapter);
d4f80882 3135 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3136 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3137 }
9a799d71
AK		 3138 return work_done;
3139}
3140
3141/**
3142 * ixgbe_tx_timeout - Respond to a Tx Hang
3143 * @netdev: network interface device structure
3144 **/
3145static void ixgbe_tx_timeout(struct net_device *netdev)
3146{
3147 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3148
3149 /* Do the reset outside of interrupt context */
3150 schedule_work(&adapter->reset_task);
3151}
3152
3153static void ixgbe_reset_task(struct work_struct *work)
3154{
3155 struct ixgbe_adapter *adapter;
3156 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3157
2f90b865
AD		 3158 /* If we're already down or resetting, just bail */
3159 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3160 test_bit(__IXGBE_RESETTING, &adapter->state))
3161 return;
3162
9a799d71
AK		 3163 adapter->tx_timeout_count++;
3164
d4f80882 3165 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3166}
3167
bc97114d
PWJ		 3168#ifdef CONFIG_IXGBE_DCB
3169static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3170{
bc97114d 3171 bool ret = false;
0cefafad 3172 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3173
0cefafad
JB		 3174 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3175 return ret;
3176
3177 f->mask = 0x7 << 3;
3178 adapter->num_rx_queues = f->indices;
3179 adapter->num_tx_queues = f->indices;
3180 ret = true;
2f90b865 3181
bc97114d
PWJ		 3182 return ret;
3183}
3184#endif
3185
4df10466
JB		 3186/**
3187 * ixgbe_set_rss_queues: Allocate queues for RSS
3188 * @adapter: board private structure to initialize
3189 *
3190 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3191 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3192 *
3193 **/
bc97114d
PWJ		 3194static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3195{
3196 bool ret = false;
0cefafad 3197 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3198
3199 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3200 f->mask = 0xF;
3201 adapter->num_rx_queues = f->indices;
3202 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3203 ret = true;
3204 } else {
bc97114d 3205 ret = false;
b9804972
JB		 3206 }
3207
bc97114d
PWJ		 3208 return ret;
3209}
3210
c4cf55e5
PWJ		 3211/**
3212 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3213 * @adapter: board private structure to initialize
3214 *
3215 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3216 * to the original CPU that initiated the Tx session. This runs in addition
3217 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3218 * Rx load across CPUs using RSS.
3219 *
3220 **/
3221static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3222{
3223 bool ret = false;
3224 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3225
3226 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3227 f_fdir->mask = 0;
3228
3229 /* Flow Director must have RSS enabled */
3230 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3231 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3232 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3233 adapter->num_tx_queues = f_fdir->indices;
3234 adapter->num_rx_queues = f_fdir->indices;
3235 ret = true;
3236 } else {
3237 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3238 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3239 }
3240 return ret;
3241}
3242
0331a832
YZ		 3243#ifdef IXGBE_FCOE
3244/**
3245 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3246 * @adapter: board private structure to initialize
3247 *
3248 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3249 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3250 * rx queues out of the max number of rx queues, instead, it is used as the
3251 * index of the first rx queue used by FCoE.
3252 *
3253 **/
3254static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3255{
3256 bool ret = false;
3257 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3258
3259 f->indices = min((int)num_online_cpus(), f->indices);
3260 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3261 adapter->num_rx_queues = 1;
3262 adapter->num_tx_queues = 1;
0331a832
YZ		 3263#ifdef CONFIG_IXGBE_DCB
3264 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3265 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3266 ixgbe_set_dcb_queues(adapter);
3267 }
3268#endif
3269 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3270 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3271 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3272 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3273 ixgbe_set_fdir_queues(adapter);
3274 else
3275 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3276 }
3277 /* adding FCoE rx rings to the end */
3278 f->mask = adapter->num_rx_queues;
3279 adapter->num_rx_queues += f->indices;
8de8b2e6 3280 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3281
3282 ret = true;
3283 }
3284
3285 return ret;
3286}
3287
3288#endif /* IXGBE_FCOE */
4df10466
JB		 3289/*
3290 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3291 * @adapter: board private structure to initialize
3292 *
3293 * This is the top level queue allocation routine. The order here is very
3294 * important, starting with the "most" number of features turned on at once,
3295 * and ending with the smallest set of features. This way large combinations
3296 * can be allocated if they're turned on, and smaller combinations are the
3297 * fallthrough conditions.
3298 *
3299 **/
bc97114d
PWJ		 3300static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3301{
0331a832
YZ		 3302#ifdef IXGBE_FCOE
3303 if (ixgbe_set_fcoe_queues(adapter))
3304 goto done;
3305
3306#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3307#ifdef CONFIG_IXGBE_DCB
3308 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3309 goto done;
bc97114d
PWJ		 3310
3311#endif
c4cf55e5
PWJ		 3312 if (ixgbe_set_fdir_queues(adapter))
3313 goto done;
3314
bc97114d 3315 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3316 goto done;
3317
3318 /* fallback to base case */
3319 adapter->num_rx_queues = 1;
3320 adapter->num_tx_queues = 1;
3321
3322done:
3323 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3324 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3325}
3326
021230d4 3327static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3328 int vectors)
021230d4
AV		 3329{
3330 int err, vector_threshold;
3331
3332 /* We'll want at least 3 (vector_threshold):
3333 * 1) TxQ[0] Cleanup
3334 * 2) RxQ[0] Cleanup
3335 * 3) Other (Link Status Change, etc.)
3336 * 4) TCP Timer (optional)
3337 */
3338 vector_threshold = MIN_MSIX_COUNT;
3339
3340 /* The more we get, the more we will assign to Tx/Rx Cleanup
3341 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3342 * Right now, we simply care about how many we'll get; we'll
3343 * set them up later while requesting irq's.
3344 */
3345 while (vectors >= vector_threshold) {
3346 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3347 vectors);
021230d4
AV		 3348 if (!err) /* Success in acquiring all requested vectors. */
3349 break;
3350 else if (err < 0)
3351 vectors = 0; /* Nasty failure, quit now */
3352 else /* err == number of vectors we should try again with */
3353 vectors = err;
3354 }
3355
3356 if (vectors < vector_threshold) {
3357 /* Can't allocate enough MSI-X interrupts? Oh well.
3358 * This just means we'll go with either a single MSI
3359 * vector or fall back to legacy interrupts.
3360 */
3361 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3362 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3363 kfree(adapter->msix_entries);
3364 adapter->msix_entries = NULL;
021230d4
AV		 3365 } else {
3366 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3367 /*
3368 * Adjust for only the vectors we'll use, which is minimum
3369 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3370 * vectors we were allocated.
3371 */
3372 adapter->num_msix_vectors = min(vectors,
3373 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3374 }
3375}
3376
021230d4 3377/**
bc97114d 3378 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3379 * @adapter: board private structure to initialize
3380 *
bc97114d
PWJ		 3381 * Cache the descriptor ring offsets for RSS to the assigned rings.
3382 *
021230d4 3383 **/
bc97114d 3384static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3385{
bc97114d
PWJ		 3386 int i;
3387 bool ret = false;
3388
3389 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3390 for (i = 0; i < adapter->num_rx_queues; i++)
3391 adapter->rx_ring[i].reg_idx = i;
3392 for (i = 0; i < adapter->num_tx_queues; i++)
3393 adapter->tx_ring[i].reg_idx = i;
3394 ret = true;
3395 } else {
3396 ret = false;
3397 }
3398
3399 return ret;
3400}
3401
3402#ifdef CONFIG_IXGBE_DCB
3403/**
3404 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3405 * @adapter: board private structure to initialize
3406 *
3407 * Cache the descriptor ring offsets for DCB to the assigned rings.
3408 *
3409 **/
3410static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3411{
3412 int i;
3413 bool ret = false;
3414 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3415
3416 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3417 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3418 /* the number of queues is assumed to be symmetric */
3419 for (i = 0; i < dcb_i; i++) {
3420 adapter->rx_ring[i].reg_idx = i << 3;
3421 adapter->tx_ring[i].reg_idx = i << 2;
3422 }
bc97114d 3423 ret = true;
e8e26350 3424 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3425 if (dcb_i == 8) {
3426 /*
3427 * Tx TC0 starts at: descriptor queue 0
3428 * Tx TC1 starts at: descriptor queue 32
3429 * Tx TC2 starts at: descriptor queue 64
3430 * Tx TC3 starts at: descriptor queue 80
3431 * Tx TC4 starts at: descriptor queue 96
3432 * Tx TC5 starts at: descriptor queue 104
3433 * Tx TC6 starts at: descriptor queue 112
3434 * Tx TC7 starts at: descriptor queue 120
3435 *
3436 * Rx TC0-TC7 are offset by 16 queues each
3437 */
3438 for (i = 0; i < 3; i++) {
3439 adapter->tx_ring[i].reg_idx = i << 5;
3440 adapter->rx_ring[i].reg_idx = i << 4;
3441 }
3442 for ( ; i < 5; i++) {
3443 adapter->tx_ring[i].reg_idx =
3444 ((i + 2) << 4);
3445 adapter->rx_ring[i].reg_idx = i << 4;
3446 }
3447 for ( ; i < dcb_i; i++) {
3448 adapter->tx_ring[i].reg_idx =
3449 ((i + 8) << 3);
3450 adapter->rx_ring[i].reg_idx = i << 4;
3451 }
3452
3453 ret = true;
3454 } else if (dcb_i == 4) {
3455 /*
3456 * Tx TC0 starts at: descriptor queue 0
3457 * Tx TC1 starts at: descriptor queue 64
3458 * Tx TC2 starts at: descriptor queue 96
3459 * Tx TC3 starts at: descriptor queue 112
3460 *
3461 * Rx TC0-TC3 are offset by 32 queues each
3462 */
3463 adapter->tx_ring[0].reg_idx = 0;
3464 adapter->tx_ring[1].reg_idx = 64;
3465 adapter->tx_ring[2].reg_idx = 96;
3466 adapter->tx_ring[3].reg_idx = 112;
3467 for (i = 0 ; i < dcb_i; i++)
3468 adapter->rx_ring[i].reg_idx = i << 5;
3469
3470 ret = true;
3471 } else {
3472 ret = false;
e8e26350 3473 }
bc97114d
PWJ		 3474 } else {
3475 ret = false;
021230d4 3476 }
bc97114d
PWJ		 3477 } else {
3478 ret = false;
021230d4 3479 }
bc97114d
PWJ		 3480
3481 return ret;
3482}
3483#endif
3484
c4cf55e5
PWJ		 3485/**
3486 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3487 * @adapter: board private structure to initialize
3488 *
3489 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3490 *
3491 **/
3492static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3493{
3494 int i;
3495 bool ret = false;
3496
3497 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3498 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3499 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3500 for (i = 0; i < adapter->num_rx_queues; i++)
3501 adapter->rx_ring[i].reg_idx = i;
3502 for (i = 0; i < adapter->num_tx_queues; i++)
3503 adapter->tx_ring[i].reg_idx = i;
3504 ret = true;
3505 }
3506
3507 return ret;
3508}
3509
0331a832
YZ		 3510#ifdef IXGBE_FCOE
3511/**
3512 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3513 * @adapter: board private structure to initialize
3514 *
3515 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3516 *
3517 */
3518static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3519{
8de8b2e6 3520 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3521 bool ret = false;
3522 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3523
3524 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3525#ifdef CONFIG_IXGBE_DCB
3526 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3527 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3528
0331a832 3529 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3530 /* find out queues in TC for FCoE */
3531 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3532 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3533 /*
3534 * In 82599, the number of Tx queues for each traffic
3535 * class for both 8-TC and 4-TC modes are:
3536 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3537 * 8 TCs: 32 32 16 16 8 8 8 8
3538 * 4 TCs: 64 64 32 32
3539 * We have max 8 queues for FCoE, where 8 the is
3540 * FCoE redirection table size. If TC for FCoE is
3541 * less than or equal to TC3, we have enough queues
3542 * to add max of 8 queues for FCoE, so we start FCoE
3543 * tx descriptor from the next one, i.e., reg_idx + 1.
3544 * If TC for FCoE is above TC3, implying 8 TC mode,
3545 * and we need 8 for FCoE, we have to take all queues
3546 * in that traffic class for FCoE.
3547 */
3548 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3549 fcoe_tx_i--;
0331a832
YZ		 3550 }
3551#endif /* CONFIG_IXGBE_DCB */
3552 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3553 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3554 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3555 ixgbe_cache_ring_fdir(adapter);
3556 else
3557 ixgbe_cache_ring_rss(adapter);
3558
8de8b2e6
YZ		 3559 fcoe_rx_i = f->mask;
3560 fcoe_tx_i = f->mask;
3561 }
3562 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3563 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3564 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3565 }
0331a832
YZ		 3566 ret = true;
3567 }
3568 return ret;
3569}
3570
3571#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3572/**
3573 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3574 * @adapter: board private structure to initialize
3575 *
3576 * Once we know the feature-set enabled for the device, we'll cache
3577 * the register offset the descriptor ring is assigned to.
3578 *
3579 * Note, the order the various feature calls is important. It must start with
3580 * the "most" features enabled at the same time, then trickle down to the
3581 * least amount of features turned on at once.
3582 **/
3583static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3584{
3585 /* start with default case */
3586 adapter->rx_ring[0].reg_idx = 0;
3587 adapter->tx_ring[0].reg_idx = 0;
3588
0331a832
YZ		 3589#ifdef IXGBE_FCOE
3590 if (ixgbe_cache_ring_fcoe(adapter))
3591 return;
3592
3593#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3594#ifdef CONFIG_IXGBE_DCB
3595 if (ixgbe_cache_ring_dcb(adapter))
3596 return;
3597
3598#endif
c4cf55e5
PWJ		 3599 if (ixgbe_cache_ring_fdir(adapter))
3600 return;
3601
bc97114d
PWJ		 3602 if (ixgbe_cache_ring_rss(adapter))
3603 return;
021230d4
AV		 3604}
3605
9a799d71
AK		 3606/**
3607 * ixgbe_alloc_queues - Allocate memory for all rings
3608 * @adapter: board private structure to initialize
3609 *
3610 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3611 * number of queues at compile-time. The polling_netdev array is
3612 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3613 **/
2f90b865 3614static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3615{
3616 int i;
3617
3618 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3619 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3620 if (!adapter->tx_ring)
021230d4 3621 goto err_tx_ring_allocation;
9a799d71
AK		 3622
3623 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3624 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3625 if (!adapter->rx_ring)
3626 goto err_rx_ring_allocation;
9a799d71 3627
021230d4 3628 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3629 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3630 adapter->tx_ring[i].queue_index = i;
3631 }
b9804972 3632
9a799d71 3633 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3634 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3635 adapter->rx_ring[i].queue_index = i;
3636 }
3637
3638 ixgbe_cache_ring_register(adapter);
3639
3640 return 0;
3641
3642err_rx_ring_allocation:
3643 kfree(adapter->tx_ring);
3644err_tx_ring_allocation:
3645 return -ENOMEM;
3646}
3647
3648/**
3649 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3650 * @adapter: board private structure to initialize
3651 *
3652 * Attempt to configure the interrupts using the best available
3653 * capabilities of the hardware and the kernel.
3654 **/
feea6a57 3655static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3656{
8be0e467 3657 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3658 int err = 0;
3659 int vector, v_budget;
3660
3661 /*
3662 * It's easy to be greedy for MSI-X vectors, but it really
3663 * doesn't do us much good if we have a lot more vectors
3664 * than CPU's. So let's be conservative and only ask for
342bde1b 3665 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3666 */
3667 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3668 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3669
3670 /*
3671 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3672 * hw.mac->max_msix_vectors vectors. With features
3673 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3674 * descriptor queues supported by our device. Thus, we cap it off in
3675 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3676 */
8be0e467 3677 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3678
3679 /* A failure in MSI-X entry allocation isn't fatal, but it does
3680 * mean we disable MSI-X capabilities of the adapter. */
3681 adapter->msix_entries = kcalloc(v_budget,
b4617240 3682 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3683 if (adapter->msix_entries) {
3684 for (vector = 0; vector < v_budget; vector++)
3685 adapter->msix_entries[vector].entry = vector;
021230d4 3686
7a921c93 3687 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3688
7a921c93
AD		 3689 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3690 goto out;
3691 }
021230d4 3692
7a921c93
AD		 3693 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3694 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3695 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3696 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3697 adapter->atr_sample_rate = 0;
7a921c93 3698 ixgbe_set_num_queues(adapter);
021230d4 3699
021230d4
AV		 3700 err = pci_enable_msi(adapter->pdev);
3701 if (!err) {
3702 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3703 } else {
3704 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3705 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3706 /* reset err */
3707 err = 0;
3708 }
3709
3710out:
021230d4
AV		 3711 return err;
3712}
3713
7a921c93
AD		 3714/**
3715 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3716 * @adapter: board private structure to initialize
3717 *
3718 * We allocate one q_vector per queue interrupt. If allocation fails we
3719 * return -ENOMEM.
3720 **/
3721static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3722{
3723 int q_idx, num_q_vectors;
3724 struct ixgbe_q_vector *q_vector;
3725 int napi_vectors;
3726 int (*poll)(struct napi_struct *, int);
3727
3728 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3729 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3730 napi_vectors = adapter->num_rx_queues;
91281fd3 3731 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3732 } else {
3733 num_q_vectors = 1;
3734 napi_vectors = 1;
3735 poll = &ixgbe_poll;
3736 }
3737
3738 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3739 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3740 if (!q_vector)
3741 goto err_out;
3742 q_vector->adapter = adapter;
f7554a2b
NS		 3743 if (q_vector->txr_count && !q_vector->rxr_count)
3744 q_vector->eitr = adapter->tx_eitr_param;
3745 else
3746 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3747 q_vector->v_idx = q_idx;
91281fd3 3748 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3749 adapter->q_vector[q_idx] = q_vector;
3750 }
3751
3752 return 0;
3753
3754err_out:
3755 while (q_idx) {
3756 q_idx--;
3757 q_vector = adapter->q_vector[q_idx];
3758 netif_napi_del(&q_vector->napi);
3759 kfree(q_vector);
3760 adapter->q_vector[q_idx] = NULL;
3761 }
3762 return -ENOMEM;
3763}
3764
3765/**
3766 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3767 * @adapter: board private structure to initialize
3768 *
3769 * This function frees the memory allocated to the q_vectors. In addition if
3770 * NAPI is enabled it will delete any references to the NAPI struct prior
3771 * to freeing the q_vector.
3772 **/
3773static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3774{
3775 int q_idx, num_q_vectors;
7a921c93 3776
91281fd3 3777 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3778 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3779 else
7a921c93 3780 num_q_vectors = 1;
7a921c93
AD		 3781
3782 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3783 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3784 adapter->q_vector[q_idx] = NULL;
91281fd3 3785 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3786 kfree(q_vector);
3787 }
3788}
3789
7b25cdba 3790static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3791{
3792 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3793 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3794 pci_disable_msix(adapter->pdev);
3795 kfree(adapter->msix_entries);
3796 adapter->msix_entries = NULL;
3797 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3798 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3799 pci_disable_msi(adapter->pdev);
3800 }
3801 return;
3802}
3803
3804/**
3805 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3806 * @adapter: board private structure to initialize
3807 *
3808 * We determine which interrupt scheme to use based on...
3809 * - Kernel support (MSI, MSI-X)
3810 * - which can be user-defined (via MODULE_PARAM)
3811 * - Hardware queue count (num_*_queues)
3812 * - defined by miscellaneous hardware support/features (RSS, etc.)
3813 **/
2f90b865 3814int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3815{
3816 int err;
3817
3818 /* Number of supported queues */
3819 ixgbe_set_num_queues(adapter);
3820
021230d4
AV		 3821 err = ixgbe_set_interrupt_capability(adapter);
3822 if (err) {
3823 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3824 goto err_set_interrupt;
9a799d71
AK		 3825 }
3826
7a921c93
AD		 3827 err = ixgbe_alloc_q_vectors(adapter);
3828 if (err) {
3829 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3830 "vectors\n");
3831 goto err_alloc_q_vectors;
3832 }
3833
3834 err = ixgbe_alloc_queues(adapter);
3835 if (err) {
3836 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3837 goto err_alloc_queues;
3838 }
3839
021230d4 3840 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3841 "Tx Queue count = %u\n",
3842 (adapter->num_rx_queues > 1) ? "Enabled" :
3843 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3844
3845 set_bit(__IXGBE_DOWN, &adapter->state);
3846
9a799d71 3847 return 0;
021230d4 3848
7a921c93
AD		 3849err_alloc_queues:
3850 ixgbe_free_q_vectors(adapter);
3851err_alloc_q_vectors:
3852 ixgbe_reset_interrupt_capability(adapter);
021230d4 3853err_set_interrupt:
7a921c93
AD		 3854 return err;
3855}
3856
3857/**
3858 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3859 * @adapter: board private structure to clear interrupt scheme on
3860 *
3861 * We go through and clear interrupt specific resources and reset the structure
3862 * to pre-load conditions
3863 **/
3864void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3865{
021230d4
AV		 3866 kfree(adapter->tx_ring);
3867 kfree(adapter->rx_ring);
7a921c93
AD		 3868 adapter->tx_ring = NULL;
3869 adapter->rx_ring = NULL;
3870
3871 ixgbe_free_q_vectors(adapter);
3872 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3873}
3874
c4900be0
DS		 3875/**
3876 * ixgbe_sfp_timer - worker thread to find a missing module
3877 * @data: pointer to our adapter struct
3878 **/
3879static void ixgbe_sfp_timer(unsigned long data)
3880{
3881 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3882
4df10466
JB		 3883 /*
3884 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3885 * delays that sfp+ detection requires
3886 */
3887 schedule_work(&adapter->sfp_task);
3888}
3889
3890/**
3891 * ixgbe_sfp_task - worker thread to find a missing module
3892 * @work: pointer to work_struct containing our data
3893 **/
3894static void ixgbe_sfp_task(struct work_struct *work)
3895{
3896 struct ixgbe_adapter *adapter = container_of(work,
3897 struct ixgbe_adapter,
3898 sfp_task);
3899 struct ixgbe_hw *hw = &adapter->hw;
3900
3901 if ((hw->phy.type == ixgbe_phy_nl) &&
3902 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3903 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3904 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3905 goto reschedule;
3906 ret = hw->phy.ops.reset(hw);
3907 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3908 dev_err(&adapter->pdev->dev, "failed to initialize "
3909 "because an unsupported SFP+ module type "
3910 "was detected.\n"
3911 "Reload the driver after installing a "
3912 "supported module.\n");
c4900be0
DS		 3913 unregister_netdev(adapter->netdev);
3914 } else {
3915 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3916 hw->phy.sfp_type);
3917 }
3918 /* don't need this routine any more */
3919 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3920 }
3921 return;
3922reschedule:
3923 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3924 mod_timer(&adapter->sfp_timer,
3925 round_jiffies(jiffies + (2 * HZ)));
3926}
3927
9a799d71
AK		 3928/**
3929 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3930 * @adapter: board private structure to initialize
3931 *
3932 * ixgbe_sw_init initializes the Adapter private data structure.
3933 * Fields are initialized based on PCI device information and
3934 * OS network device settings (MTU size).
3935 **/
3936static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3937{
3938 struct ixgbe_hw *hw = &adapter->hw;
3939 struct pci_dev *pdev = adapter->pdev;
021230d4 3940 unsigned int rss;
7a6b6f51 3941#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3942 int j;
3943 struct tc_configuration *tc;
3944#endif
021230d4 3945
c44ade9e
JB		 3946 /* PCI config space info */
3947
3948 hw->vendor_id = pdev->vendor;
3949 hw->device_id = pdev->device;
3950 hw->revision_id = pdev->revision;
3951 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3952 hw->subsystem_device_id = pdev->subsystem_device;
3953
021230d4
AV		 3954 /* Set capability flags */
3955 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3956 adapter->ring_feature[RING_F_RSS].indices = rss;
3957 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3958 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3959 if (hw->mac.type == ixgbe_mac_82598EB) {
3960 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3961 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3962 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3963 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3964 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3965 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3966 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3967 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3968 adapter->ring_feature[RING_F_FDIR].indices =
3969 IXGBE_MAX_FDIR_INDICES;
3970 adapter->atr_sample_rate = 20;
3971 adapter->fdir_pballoc = 0;
eacd73f7 3972#ifdef IXGBE_FCOE
0d551589
YZ		 3973 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3974 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3975 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 3976#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 3977 /* Default traffic class to use for FCoE */
3978 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 3979#endif
eacd73f7 3980#endif /* IXGBE_FCOE */
f8212f97 3981 }
2f90b865 3982
7a6b6f51 3983#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3984 /* Configure DCB traffic classes */
3985 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3986 tc = &adapter->dcb_cfg.tc_config[j];
3987 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3988 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3989 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3990 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3991 tc->dcb_pfc = pfc_disabled;
3992 }
3993 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3994 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3995 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3996 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3997 adapter->dcb_cfg.round_robin_enable = false;
3998 adapter->dcb_set_bitmap = 0x00;
3999 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4000 adapter->ring_feature[RING_F_DCB].indices);
4001
4002#endif
9a799d71
AK		 4003
4004 /* default flow control settings */
cd7664f6 4005 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4006 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4007#ifdef CONFIG_DCB
4008 adapter->last_lfc_mode = hw->fc.current_mode;
4009#endif
2b9ade93
JB		 4010 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4011 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4012 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4013 hw->fc.send_xon = true;
71fd570b 4014 hw->fc.disable_fc_autoneg = false;
9a799d71 4015
30efa5a3 4016 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4017 adapter->rx_itr_setting = 1;
4018 adapter->rx_eitr_param = 20000;
4019 adapter->tx_itr_setting = 1;
4020 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4021
4022 /* set defaults for eitr in MegaBytes */
4023 adapter->eitr_low = 10;
4024 adapter->eitr_high = 20;
4025
4026 /* set default ring sizes */
4027 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4028 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4029
9a799d71 4030 /* initialize eeprom parameters */
c44ade9e 4031 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4032 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4033 return -EIO;
4034 }
4035
021230d4 4036 /* enable rx csum by default */
9a799d71
AK		 4037 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4038
9a799d71
AK		 4039 set_bit(__IXGBE_DOWN, &adapter->state);
4040
4041 return 0;
4042}
4043
4044/**
4045 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4046 * @adapter: board private structure
3a581073 4047 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4048 *
4049 * Return 0 on success, negative on failure
4050 **/
4051int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4052 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4053{
4054 struct pci_dev *pdev = adapter->pdev;
4055 int size;
4056
3a581073
JB		 4057 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4058 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4059 if (!tx_ring->tx_buffer_info)
4060 goto err;
3a581073 4061 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4062
4063 /* round up to nearest 4K */
12207e49 4064 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4065 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4066
3a581073
JB		 4067 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4068 &tx_ring->dma);
e01c31a5
JB		 4069 if (!tx_ring->desc)
4070 goto err;
9a799d71 4071
3a581073
JB		 4072 tx_ring->next_to_use = 0;
4073 tx_ring->next_to_clean = 0;
4074 tx_ring->work_limit = tx_ring->count;
9a799d71 4075 return 0;
e01c31a5
JB		 4076
4077err:
4078 vfree(tx_ring->tx_buffer_info);
4079 tx_ring->tx_buffer_info = NULL;
4080 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4081 "descriptor ring\n");
4082 return -ENOMEM;
9a799d71
AK		 4083}
4084
69888674
AD		 4085/**
4086 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4087 * @adapter: board private structure
4088 *
4089 * If this function returns with an error, then it's possible one or
4090 * more of the rings is populated (while the rest are not). It is the
4091 * callers duty to clean those orphaned rings.
4092 *
4093 * Return 0 on success, negative on failure
4094 **/
4095static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4096{
4097 int i, err = 0;
4098
4099 for (i = 0; i < adapter->num_tx_queues; i++) {
4100 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4101 if (!err)
4102 continue;
4103 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4104 break;
4105 }
4106
4107 return err;
4108}
4109
9a799d71
AK		 4110/**
4111 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4112 * @adapter: board private structure
3a581073 4113 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4114 *
4115 * Returns 0 on success, negative on failure
4116 **/
4117int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4118 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4119{
4120 struct pci_dev *pdev = adapter->pdev;
021230d4 4121 int size;
9a799d71 4122
3a581073
JB		 4123 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4124 rx_ring->rx_buffer_info = vmalloc(size);
4125 if (!rx_ring->rx_buffer_info) {
9a799d71 4126 DPRINTK(PROBE, ERR,
b4617240 4127 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4128 goto alloc_failed;
9a799d71 4129 }
3a581073 4130 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4131
9a799d71 4132 /* Round up to nearest 4K */
3a581073
JB		 4133 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4134 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4135
3a581073 4136 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4137
3a581073 4138 if (!rx_ring->desc) {
9a799d71 4139 DPRINTK(PROBE, ERR,
b4617240 4140 "Memory allocation failed for the rx desc ring\n");
3a581073 4141 vfree(rx_ring->rx_buffer_info);
177db6ff 4142 goto alloc_failed;
9a799d71
AK		 4143 }
4144
3a581073
JB		 4145 rx_ring->next_to_clean = 0;
4146 rx_ring->next_to_use = 0;
9a799d71
AK		 4147
4148 return 0;
177db6ff
MC		 4149
4150alloc_failed:
177db6ff 4151 return -ENOMEM;
9a799d71
AK		 4152}
4153
69888674
AD		 4154/**
4155 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4156 * @adapter: board private structure
4157 *
4158 * If this function returns with an error, then it's possible one or
4159 * more of the rings is populated (while the rest are not). It is the
4160 * callers duty to clean those orphaned rings.
4161 *
4162 * Return 0 on success, negative on failure
4163 **/
4164
4165static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4166{
4167 int i, err = 0;
4168
4169 for (i = 0; i < adapter->num_rx_queues; i++) {
4170 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4171 if (!err)
4172 continue;
4173 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4174 break;
4175 }
4176
4177 return err;
4178}
4179
9a799d71
AK		 4180/**
4181 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4182 * @adapter: board private structure
4183 * @tx_ring: Tx descriptor ring for a specific queue
4184 *
4185 * Free all transmit software resources
4186 **/
c431f97e
JB		 4187void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4188 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4189{
4190 struct pci_dev *pdev = adapter->pdev;
4191
4192 ixgbe_clean_tx_ring(adapter, tx_ring);
4193
4194 vfree(tx_ring->tx_buffer_info);
4195 tx_ring->tx_buffer_info = NULL;
4196
4197 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4198
4199 tx_ring->desc = NULL;
4200}
4201
4202/**
4203 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4204 * @adapter: board private structure
4205 *
4206 * Free all transmit software resources
4207 **/
4208static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4209{
4210 int i;
4211
4212 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4213 if (adapter->tx_ring[i].desc)
4214 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4215}
4216
4217/**
b4617240 4218 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4219 * @adapter: board private structure
4220 * @rx_ring: ring to clean the resources from
4221 *
4222 * Free all receive software resources
4223 **/
c431f97e
JB		 4224void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4225 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4226{
4227 struct pci_dev *pdev = adapter->pdev;
4228
4229 ixgbe_clean_rx_ring(adapter, rx_ring);
4230
4231 vfree(rx_ring->rx_buffer_info);
4232 rx_ring->rx_buffer_info = NULL;
4233
4234 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4235
4236 rx_ring->desc = NULL;
4237}
4238
4239/**
4240 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4241 * @adapter: board private structure
4242 *
4243 * Free all receive software resources
4244 **/
4245static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4246{
4247 int i;
4248
4249 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4250 if (adapter->rx_ring[i].desc)
4251 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4252}
4253
9a799d71
AK		 4254/**
4255 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4256 * @netdev: network interface device structure
4257 * @new_mtu: new value for maximum frame size
4258 *
4259 * Returns 0 on success, negative on failure
4260 **/
4261static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4262{
4263 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4264 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4265
42c783c5
JB		 4266 /* MTU < 68 is an error and causes problems on some kernels */
4267 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4268 return -EINVAL;
4269
021230d4 4270 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4271 netdev->mtu, new_mtu);
021230d4 4272 /* must set new MTU before calling down or up */
9a799d71
AK		 4273 netdev->mtu = new_mtu;
4274
d4f80882
AV		 4275 if (netif_running(netdev))
4276 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4277
4278 return 0;
4279}
4280
4281/**
4282 * ixgbe_open - Called when a network interface is made active
4283 * @netdev: network interface device structure
4284 *
4285 * Returns 0 on success, negative value on failure
4286 *
4287 * The open entry point is called when a network interface is made
4288 * active by the system (IFF_UP). At this point all resources needed
4289 * for transmit and receive operations are allocated, the interrupt
4290 * handler is registered with the OS, the watchdog timer is started,
4291 * and the stack is notified that the interface is ready.
4292 **/
4293static int ixgbe_open(struct net_device *netdev)
4294{
4295 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4296 int err;
4bebfaa5
AK		 4297
4298 /* disallow open during test */
4299 if (test_bit(__IXGBE_TESTING, &adapter->state))
4300 return -EBUSY;
9a799d71 4301
54386467
JB		 4302 netif_carrier_off(netdev);
4303
9a799d71
AK		 4304 /* allocate transmit descriptors */
4305 err = ixgbe_setup_all_tx_resources(adapter);
4306 if (err)
4307 goto err_setup_tx;
4308
9a799d71
AK		 4309 /* allocate receive descriptors */
4310 err = ixgbe_setup_all_rx_resources(adapter);
4311 if (err)
4312 goto err_setup_rx;
4313
4314 ixgbe_configure(adapter);
4315
021230d4 4316 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4317 if (err)
4318 goto err_req_irq;
4319
9a799d71
AK		 4320 err = ixgbe_up_complete(adapter);
4321 if (err)
4322 goto err_up;
4323
d55b53ff
JK		 4324 netif_tx_start_all_queues(netdev);
4325
9a799d71
AK		 4326 return 0;
4327
4328err_up:
5eba3699 4329 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4330 ixgbe_free_irq(adapter);
4331err_req_irq:
9a799d71 4332err_setup_rx:
a20a1199 4333 ixgbe_free_all_rx_resources(adapter);
9a799d71 4334err_setup_tx:
a20a1199 4335 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4336 ixgbe_reset(adapter);
4337
4338 return err;
4339}
4340
4341/**
4342 * ixgbe_close - Disables a network interface
4343 * @netdev: network interface device structure
4344 *
4345 * Returns 0, this is not allowed to fail
4346 *
4347 * The close entry point is called when an interface is de-activated
4348 * by the OS. The hardware is still under the drivers control, but
4349 * needs to be disabled. A global MAC reset is issued to stop the
4350 * hardware, and all transmit and receive resources are freed.
4351 **/
4352static int ixgbe_close(struct net_device *netdev)
4353{
4354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4355
4356 ixgbe_down(adapter);
4357 ixgbe_free_irq(adapter);
4358
4359 ixgbe_free_all_tx_resources(adapter);
4360 ixgbe_free_all_rx_resources(adapter);
4361
5eba3699 4362 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4363
4364 return 0;
4365}
4366
b3c8b4ba
AD		 4367#ifdef CONFIG_PM
4368static int ixgbe_resume(struct pci_dev *pdev)
4369{
4370 struct net_device *netdev = pci_get_drvdata(pdev);
4371 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4372 u32 err;
4373
4374 pci_set_power_state(pdev, PCI_D0);
4375 pci_restore_state(pdev);
9ce77666 4376
4377 err = pci_enable_device_mem(pdev);
b3c8b4ba 4378 if (err) {
69888674 4379 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4380 "suspend\n");
4381 return err;
4382 }
4383 pci_set_master(pdev);
4384
dd4d8ca6 4385 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4386
4387 err = ixgbe_init_interrupt_scheme(adapter);
4388 if (err) {
4389 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4390 "device\n");
4391 return err;
4392 }
4393
b3c8b4ba
AD		 4394 ixgbe_reset(adapter);
4395
495dce12
WJP		 4396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4397
b3c8b4ba
AD		 4398 if (netif_running(netdev)) {
4399 err = ixgbe_open(adapter->netdev);
4400 if (err)
4401 return err;
4402 }
4403
4404 netif_device_attach(netdev);
4405
4406 return 0;
4407}
b3c8b4ba 4408#endif /* CONFIG_PM */
9d8d05ae
RW		 4409
4410static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4411{
4412 struct net_device *netdev = pci_get_drvdata(pdev);
4413 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4414 struct ixgbe_hw *hw = &adapter->hw;
4415 u32 ctrl, fctrl;
4416 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4417#ifdef CONFIG_PM
4418 int retval = 0;
4419#endif
4420
4421 netif_device_detach(netdev);
4422
4423 if (netif_running(netdev)) {
4424 ixgbe_down(adapter);
4425 ixgbe_free_irq(adapter);
4426 ixgbe_free_all_tx_resources(adapter);
4427 ixgbe_free_all_rx_resources(adapter);
4428 }
7a921c93 4429 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4430
4431#ifdef CONFIG_PM
4432 retval = pci_save_state(pdev);
4433 if (retval)
4434 return retval;
4df10466 4435
b3c8b4ba 4436#endif
e8e26350
PW		 4437 if (wufc) {
4438 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4439
e8e26350
PW		 4440 /* turn on all-multi mode if wake on multicast is enabled */
4441 if (wufc & IXGBE_WUFC_MC) {
4442 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4443 fctrl |= IXGBE_FCTRL_MPE;
4444 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4445 }
4446
4447 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4448 ctrl |= IXGBE_CTRL_GIO_DIS;
4449 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4450
4451 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4452 } else {
4453 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4454 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4455 }
4456
dd4d8ca6
DS		 4457 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4458 pci_wake_from_d3(pdev, true);
4459 else
4460 pci_wake_from_d3(pdev, false);
b3c8b4ba 4461
9d8d05ae
RW		 4462 *enable_wake = !!wufc;
4463
b3c8b4ba
AD		 4464 ixgbe_release_hw_control(adapter);
4465
4466 pci_disable_device(pdev);
4467
9d8d05ae
RW		 4468 return 0;
4469}
4470
4471#ifdef CONFIG_PM
4472static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4473{
4474 int retval;
4475 bool wake;
4476
4477 retval = __ixgbe_shutdown(pdev, &wake);
4478 if (retval)
4479 return retval;
4480
4481 if (wake) {
4482 pci_prepare_to_sleep(pdev);
4483 } else {
4484 pci_wake_from_d3(pdev, false);
4485 pci_set_power_state(pdev, PCI_D3hot);
4486 }
b3c8b4ba
AD		 4487
4488 return 0;
4489}
9d8d05ae 4490#endif /* CONFIG_PM */
b3c8b4ba
AD		 4491
4492static void ixgbe_shutdown(struct pci_dev *pdev)
4493{
9d8d05ae
RW		 4494 bool wake;
4495
4496 __ixgbe_shutdown(pdev, &wake);
4497
4498 if (system_state == SYSTEM_POWER_OFF) {
4499 pci_wake_from_d3(pdev, wake);
4500 pci_set_power_state(pdev, PCI_D3hot);
4501 }
b3c8b4ba
AD		 4502}
4503
9a799d71
AK		 4504/**
4505 * ixgbe_update_stats - Update the board statistics counters.
4506 * @adapter: board private structure
4507 **/
4508void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4509{
2d86f139 4510 struct net_device *netdev = adapter->netdev;
9a799d71 4511 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4512 u64 total_mpc = 0;
4513 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4514 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4515
94b982b2 4516 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4517 u64 rsc_count = 0;
94b982b2 4518 u64 rsc_flush = 0;
d51019a4
PW		 4519 for (i = 0; i < 16; i++)
4520 adapter->hw_rx_no_dma_resources +=
4521 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4522 for (i = 0; i < adapter->num_rx_queues; i++) {
f8212f97 4523 rsc_count += adapter->rx_ring[i].rsc_count;
94b982b2
MC		 4524 rsc_flush += adapter->rx_ring[i].rsc_flush;
4525 }
4526 adapter->rsc_total_count = rsc_count;
4527 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4528 }
4529
7ca3bc58
JB		 4530 /* gather some stats to the adapter struct that are per queue */
4531 for (i = 0; i < adapter->num_tx_queues; i++)
eb985f09
MC		 4532 restart_queue += adapter->tx_ring[i].restart_queue;
4533 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4534
4535 for (i = 0; i < adapter->num_rx_queues; i++)
eb985f09
MC		 4536 non_eop_descs += adapter->rx_ring[i].non_eop_descs;
4537 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4538
9a799d71 4539 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4540 for (i = 0; i < 8; i++) {
4541 /* for packet buffers not used, the register should read 0 */
4542 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4543 missed_rx += mpc;
4544 adapter->stats.mpc[i] += mpc;
4545 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4546 if (hw->mac.type == ixgbe_mac_82598EB)
4547 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4548 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4549 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4550 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4551 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4552 if (hw->mac.type == ixgbe_mac_82599EB) {
4553 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4554 IXGBE_PXONRXCNT(i));
4555 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4556 IXGBE_PXOFFRXCNT(i));
4557 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4558 } else {
4559 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4560 IXGBE_PXONRXC(i));
4561 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4562 IXGBE_PXOFFRXC(i));
4563 }
2f90b865
AD		 4564 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4565 IXGBE_PXONTXC(i));
2f90b865 4566 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4567 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4568 }
4569 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4570 /* work around hardware counting issue */
4571 adapter->stats.gprc -= missed_rx;
4572
4573 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4574 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4575 u64 tmp;
e8e26350 4576 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4577 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4578 adapter->stats.gorc += (tmp << 32);
e8e26350 4579 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4580 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4581 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4582 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4583 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4584 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4585 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4586 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4587 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4588#ifdef IXGBE_FCOE
4589 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4590 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4591 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4592 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4593 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4594 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4595#endif /* IXGBE_FCOE */
e8e26350
PW		 4596 } else {
4597 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4598 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4599 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4600 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4601 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4602 }
9a799d71
AK		 4603 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4604 adapter->stats.bprc += bprc;
4605 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4606 if (hw->mac.type == ixgbe_mac_82598EB)
4607 adapter->stats.mprc -= bprc;
9a799d71
AK		 4608 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4609 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4610 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4611 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4612 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4613 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4614 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4615 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4616 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4617 adapter->stats.lxontxc += lxon;
4618 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4619 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4620 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4621 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4622 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4623 /*
4624 * 82598 errata - tx of flow control packets is included in tx counters
4625 */
4626 xon_off_tot = lxon + lxoff;
4627 adapter->stats.gptc -= xon_off_tot;
4628 adapter->stats.mptc -= xon_off_tot;
4629 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4630 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4631 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4632 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4633 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4634 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4635 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4636 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4637 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4638 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4639 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4640 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4641 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4642
4643 /* Fill out the OS statistics structure */
2d86f139 4644 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4645
4646 /* Rx Errors */
2d86f139 4647 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4648 adapter->stats.rlec;
2d86f139
AK		 4649 netdev->stats.rx_dropped = 0;
4650 netdev->stats.rx_length_errors = adapter->stats.rlec;
4651 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4652 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4653}
4654
4655/**
4656 * ixgbe_watchdog - Timer Call-back
4657 * @data: pointer to adapter cast into an unsigned long
4658 **/
4659static void ixgbe_watchdog(unsigned long data)
4660{
4661 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4662 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4663 u64 eics = 0;
4664 int i;
cf8280ee 4665
fe49f04a
AD		 4666 /*
4667 * Do the watchdog outside of interrupt context due to the lovely
4668 * delays that some of the newer hardware requires
4669 */
22d5a71b 4670
fe49f04a
AD		 4671 if (test_bit(__IXGBE_DOWN, &adapter->state))
4672 goto watchdog_short_circuit;
22d5a71b 4673
fe49f04a
AD		 4674 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4675 /*
4676 * for legacy and MSI interrupts don't set any bits
4677 * that are enabled for EIAM, because this operation
4678 * would set *both* EIMS and EICS for any bit in EIAM
4679 */
4680 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4681 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4682 goto watchdog_reschedule;
4683 }
4684
4685 /* get one bit for every active tx/rx interrupt vector */
4686 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4687 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4688 if (qv->rxr_count || qv->txr_count)
4689 eics |= ((u64)1 << i);
cf8280ee 4690 }
9a799d71 4691
fe49f04a
AD		 4692 /* Cause software interrupt to ensure rx rings are cleaned */
4693 ixgbe_irq_rearm_queues(adapter, eics);
4694
4695watchdog_reschedule:
4696 /* Reset the timer */
4697 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4698
4699watchdog_short_circuit:
cf8280ee
JB		 4700 schedule_work(&adapter->watchdog_task);
4701}
4702
e8e26350
PW		 4703/**
4704 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4705 * @work: pointer to work_struct containing our data
4706 **/
4707static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4708{
4709 struct ixgbe_adapter *adapter = container_of(work,
4710 struct ixgbe_adapter,
4711 multispeed_fiber_task);
4712 struct ixgbe_hw *hw = &adapter->hw;
4713 u32 autoneg;
8620a103 4714 bool negotiation;
e8e26350
PW		 4715
4716 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4717 autoneg = hw->phy.autoneg_advertised;
4718 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4719 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4720 if (hw->mac.ops.setup_link)
4721 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4722 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4723 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4724}
4725
4726/**
4727 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4728 * @work: pointer to work_struct containing our data
4729 **/
4730static void ixgbe_sfp_config_module_task(struct work_struct *work)
4731{
4732 struct ixgbe_adapter *adapter = container_of(work,
4733 struct ixgbe_adapter,
4734 sfp_config_module_task);
4735 struct ixgbe_hw *hw = &adapter->hw;
4736 u32 err;
4737
4738 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4739
4740 /* Time for electrical oscillations to settle down */
4741 msleep(100);
e8e26350 4742 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4743
e8e26350 4744 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4745 dev_err(&adapter->pdev->dev, "failed to initialize because "
4746 "an unsupported SFP+ module type was detected.\n"
4747 "Reload the driver after installing a supported "
4748 "module.\n");
63d6e1d8 4749 unregister_netdev(adapter->netdev);
e8e26350
PW		 4750 return;
4751 }
4752 hw->mac.ops.setup_sfp(hw);
4753
8d1c3c07 4754 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4755 /* This will also work for DA Twinax connections */
4756 schedule_work(&adapter->multispeed_fiber_task);
4757 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4758}
4759
c4cf55e5
PWJ		 4760/**
4761 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4762 * @work: pointer to work_struct containing our data
4763 **/
4764static void ixgbe_fdir_reinit_task(struct work_struct *work)
4765{
4766 struct ixgbe_adapter *adapter = container_of(work,
4767 struct ixgbe_adapter,
4768 fdir_reinit_task);
4769 struct ixgbe_hw *hw = &adapter->hw;
4770 int i;
4771
4772 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4773 for (i = 0; i < adapter->num_tx_queues; i++)
4774 set_bit(__IXGBE_FDIR_INIT_DONE,
4775 &(adapter->tx_ring[i].reinit_state));
4776 } else {
4777 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4778 "ignored adding FDIR ATR filters \n");
4779 }
4780 /* Done FDIR Re-initialization, enable transmits */
4781 netif_tx_start_all_queues(adapter->netdev);
4782}
4783
cf8280ee 4784/**
69888674
AD		 4785 * ixgbe_watchdog_task - worker thread to bring link up
4786 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4787 **/
4788static void ixgbe_watchdog_task(struct work_struct *work)
4789{
4790 struct ixgbe_adapter *adapter = container_of(work,
4791 struct ixgbe_adapter,
4792 watchdog_task);
4793 struct net_device *netdev = adapter->netdev;
4794 struct ixgbe_hw *hw = &adapter->hw;
4795 u32 link_speed = adapter->link_speed;
4796 bool link_up = adapter->link_up;
bc59fcda
NS		 4797 int i;
4798 struct ixgbe_ring *tx_ring;
4799 int some_tx_pending = 0;
cf8280ee
JB		 4800
4801 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4802
4803 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4804 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4805 if (link_up) {
4806#ifdef CONFIG_DCB
4807 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4808 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4809 hw->mac.ops.fc_enable(hw, i);
264857b8 4810 } else {
620fa036 4811 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4812 }
4813#else
620fa036 4814 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4815#endif
4816 }
4817
cf8280ee
JB		 4818 if (link_up ||
4819 time_after(jiffies, (adapter->link_check_timeout +
4820 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4821 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4822 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4823 }
4824 adapter->link_up = link_up;
4825 adapter->link_speed = link_speed;
4826 }
9a799d71
AK		 4827
4828 if (link_up) {
4829 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4830 bool flow_rx, flow_tx;
4831
4832 if (hw->mac.type == ixgbe_mac_82599EB) {
4833 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4834 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4835 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4836 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4837 } else {
4838 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4839 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4840 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4841 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4842 }
4843
a46e534b
JK		 4844 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4845 "Flow Control: %s\n",
4846 netdev->name,
4847 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4848 "10 Gbps" :
4849 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4850 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4851 ((flow_rx && flow_tx) ? "RX/TX" :
4852 (flow_rx ? "RX" :
4853 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4854
4855 netif_carrier_on(netdev);
9a799d71
AK		 4856 } else {
4857 /* Force detection of hung controller */
4858 adapter->detect_tx_hung = true;
4859 }
4860 } else {
cf8280ee
JB		 4861 adapter->link_up = false;
4862 adapter->link_speed = 0;
9a799d71 4863 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4864 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4865 netdev->name);
9a799d71 4866 netif_carrier_off(netdev);
9a799d71
AK		 4867 }
4868 }
4869
bc59fcda
NS		 4870 if (!netif_carrier_ok(netdev)) {
4871 for (i = 0; i < adapter->num_tx_queues; i++) {
4872 tx_ring = &adapter->tx_ring[i];
4873 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4874 some_tx_pending = 1;
4875 break;
4876 }
4877 }
4878
4879 if (some_tx_pending) {
4880 /* We've lost link, so the controller stops DMA,
4881 * but we've got queued Tx work that's never going
4882 * to get done, so reset controller to flush Tx.
4883 * (Do the reset outside of interrupt context).
4884 */
4885 schedule_work(&adapter->reset_task);
4886 }
4887 }
4888
9a799d71 4889 ixgbe_update_stats(adapter);
cf8280ee 4890 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4891}
4892
9a799d71 4893static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4894 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4895 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4896{
4897 struct ixgbe_adv_tx_context_desc *context_desc;
4898 unsigned int i;
4899 int err;
4900 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4901 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4902 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4903
4904 if (skb_is_gso(skb)) {
4905 if (skb_header_cloned(skb)) {
4906 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4907 if (err)
4908 return err;
4909 }
4910 l4len = tcp_hdrlen(skb);
4911 *hdr_len += l4len;
4912
8327d000 4913 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4914 struct iphdr *iph = ip_hdr(skb);
4915 iph->tot_len = 0;
4916 iph->check = 0;
4917 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4918 iph->daddr, 0,
4919 IPPROTO_TCP,
4920 0);
9a799d71
AK		 4921 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4922 ipv6_hdr(skb)->payload_len = 0;
4923 tcp_hdr(skb)->check =
4924 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4925 &ipv6_hdr(skb)->daddr,
4926 0, IPPROTO_TCP, 0);
9a799d71
AK		 4927 }
4928
4929 i = tx_ring->next_to_use;
4930
4931 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4932 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4933
4934 /* VLAN MACLEN IPLEN */
4935 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4936 vlan_macip_lens |=
4937 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4938 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4939 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4940 *hdr_len += skb_network_offset(skb);
4941 vlan_macip_lens |=
4942 (skb_transport_header(skb) - skb_network_header(skb));
4943 *hdr_len +=
4944 (skb_transport_header(skb) - skb_network_header(skb));
4945 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4946 context_desc->seqnum_seed = 0;
4947
4948 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4949 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4950 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4951
8327d000 4952 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4953 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4954 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4955 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4956
4957 /* MSS L4LEN IDX */
9f8cdf4f 4958 mss_l4len_idx =
9a799d71
AK		 4959 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4960 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4961 /* use index 1 for TSO */
4962 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4963 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4964
4965 tx_buffer_info->time_stamp = jiffies;
4966 tx_buffer_info->next_to_watch = i;
4967
4968 i++;
4969 if (i == tx_ring->count)
4970 i = 0;
4971 tx_ring->next_to_use = i;
4972
4973 return true;
4974 }
4975 return false;
4976}
4977
4978static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4979 struct ixgbe_ring *tx_ring,
4980 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4981{
4982 struct ixgbe_adv_tx_context_desc *context_desc;
4983 unsigned int i;
4984 struct ixgbe_tx_buffer *tx_buffer_info;
4985 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4986
4987 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4988 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4989 i = tx_ring->next_to_use;
4990 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4991 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4992
4993 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4994 vlan_macip_lens |=
4995 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4996 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4997 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4998 if (skb->ip_summed == CHECKSUM_PARTIAL)
4999 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5000 skb_network_header(skb));
9a799d71
AK		 5001
5002 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5003 context_desc->seqnum_seed = 0;
5004
5005 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5006 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5007
5008 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5009 __be16 protocol;
5010
5011 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5012 const struct vlan_ethhdr *vhdr =
5013 (const struct vlan_ethhdr *)skb->data;
5014
5015 protocol = vhdr->h_vlan_encapsulated_proto;
5016 } else {
5017 protocol = skb->protocol;
5018 }
5019
5020 switch (protocol) {
09640e63 5021 case cpu_to_be16(ETH_P_IP):
9a799d71 5022 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5023 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5024 type_tucmd_mlhl |=
b4617240 5025 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5026 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5027 type_tucmd_mlhl |=
5028 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5029 break;
09640e63 5030 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5031 /* XXX what about other V6 headers?? */
5032 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5033 type_tucmd_mlhl |=
b4617240 5034 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5035 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5036 type_tucmd_mlhl |=
5037 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5038 break;
41825d71
AK		 5039 default:
5040 if (unlikely(net_ratelimit())) {
5041 DPRINTK(PROBE, WARNING,
5042 "partial checksum but proto=%x!\n",
5043 skb->protocol);
5044 }
5045 break;
5046 }
9a799d71
AK		 5047 }
5048
5049 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5050 /* use index zero for tx checksum offload */
9a799d71
AK		 5051 context_desc->mss_l4len_idx = 0;
5052
5053 tx_buffer_info->time_stamp = jiffies;
5054 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5055
9a799d71
AK		 5056 i++;
5057 if (i == tx_ring->count)
5058 i = 0;
5059 tx_ring->next_to_use = i;
5060
5061 return true;
5062 }
9f8cdf4f 5063
9a799d71
AK		 5064 return false;
5065}
5066
5067static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5068 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5069 struct sk_buff *skb, u32 tx_flags,
5070 unsigned int first)
9a799d71 5071{
e5a43549 5072 struct pci_dev *pdev = adapter->pdev;
9a799d71 5073 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5074 unsigned int len;
5075 unsigned int total = skb->len;
9a799d71
AK		 5076 unsigned int offset = 0, size, count = 0, i;
5077 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5078 unsigned int f;
9a799d71
AK		 5079
5080 i = tx_ring->next_to_use;
5081
eacd73f7
YZ		 5082 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5083 /* excluding fcoe_crc_eof for FCoE */
5084 total -= sizeof(struct fcoe_crc_eof);
5085
5086 len = min(skb_headlen(skb), total);
9a799d71
AK		 5087 while (len) {
5088 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5089 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5090
5091 tx_buffer_info->length = size;
e5a43549
AD		 5092 tx_buffer_info->mapped_as_page = false;
5093 tx_buffer_info->dma = pci_map_single(pdev,
5094 skb->data + offset,
5095 size, PCI_DMA_TODEVICE);
5096 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5097 goto dma_error;
9a799d71
AK		 5098 tx_buffer_info->time_stamp = jiffies;
5099 tx_buffer_info->next_to_watch = i;
5100
5101 len -= size;
eacd73f7 5102 total -= size;
9a799d71
AK		 5103 offset += size;
5104 count++;
44df32c5
AD		 5105
5106 if (len) {
5107 i++;
5108 if (i == tx_ring->count)
5109 i = 0;
5110 }
9a799d71
AK		 5111 }
5112
5113 for (f = 0; f < nr_frags; f++) {
5114 struct skb_frag_struct *frag;
5115
5116 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5117 len = min((unsigned int)frag->size, total);
e5a43549 5118 offset = frag->page_offset;
9a799d71
AK		 5119
5120 while (len) {
44df32c5
AD		 5121 i++;
5122 if (i == tx_ring->count)
5123 i = 0;
5124
9a799d71
AK		 5125 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5126 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5127
5128 tx_buffer_info->length = size;
e5a43549
AD		 5129 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5130 frag->page,
5131 offset, size,
5132 PCI_DMA_TODEVICE);
5133 tx_buffer_info->mapped_as_page = true;
5134 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5135 goto dma_error;
9a799d71
AK		 5136 tx_buffer_info->time_stamp = jiffies;
5137 tx_buffer_info->next_to_watch = i;
5138
5139 len -= size;
eacd73f7 5140 total -= size;
9a799d71
AK		 5141 offset += size;
5142 count++;
9a799d71 5143 }
eacd73f7
YZ		 5144 if (total == 0)
5145 break;
9a799d71 5146 }
44df32c5 5147
9a799d71
AK		 5148 tx_ring->tx_buffer_info[i].skb = skb;
5149 tx_ring->tx_buffer_info[first].next_to_watch = i;
5150
e5a43549
AD		 5151 return count;
5152
5153dma_error:
5154 dev_err(&pdev->dev, "TX DMA map failed\n");
5155
5156 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5157 tx_buffer_info->dma = 0;
5158 tx_buffer_info->time_stamp = 0;
5159 tx_buffer_info->next_to_watch = 0;
5160 count--;
5161
5162 /* clear timestamp and dma mappings for remaining portion of packet */
5163 while (count >= 0) {
5164 count--;
5165 i--;
5166 if (i < 0)
5167 i += tx_ring->count;
5168 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5169 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5170 }
5171
9a799d71
AK		 5172 return count;
5173}
5174
5175static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5176 struct ixgbe_ring *tx_ring,
5177 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5178{
5179 union ixgbe_adv_tx_desc *tx_desc = NULL;
5180 struct ixgbe_tx_buffer *tx_buffer_info;
5181 u32 olinfo_status = 0, cmd_type_len = 0;
5182 unsigned int i;
5183 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5184
5185 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5186
5187 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5188
5189 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5190 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5191
5192 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5193 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5194
5195 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5196 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5197
4eeae6fd
PW		 5198 /* use index 1 context for tso */
5199 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5200 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5201 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5202 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5203
5204 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5205 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5206 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5207
eacd73f7
YZ		 5208 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5209 olinfo_status |= IXGBE_ADVTXD_CC;
5210 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5211 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5212 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5213 }
5214
9a799d71
AK		 5215 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5216
5217 i = tx_ring->next_to_use;
5218 while (count--) {
5219 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5220 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5221 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5222 tx_desc->read.cmd_type_len =
b4617240 5223 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5224 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5225 i++;
5226 if (i == tx_ring->count)
5227 i = 0;
5228 }
5229
5230 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5231
5232 /*
5233 * Force memory writes to complete before letting h/w
5234 * know there are new descriptors to fetch. (Only
5235 * applicable for weak-ordered memory model archs,
5236 * such as IA-64).
5237 */
5238 wmb();
5239
5240 tx_ring->next_to_use = i;
5241 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5242}
5243
c4cf55e5
PWJ		 5244static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5245 int queue, u32 tx_flags)
5246{
5247 /* Right now, we support IPv4 only */
5248 struct ixgbe_atr_input atr_input;
5249 struct tcphdr *th;
c4cf55e5
PWJ		 5250 struct iphdr *iph = ip_hdr(skb);
5251 struct ethhdr *eth = (struct ethhdr *)skb->data;
5252 u16 vlan_id, src_port, dst_port, flex_bytes;
5253 u32 src_ipv4_addr, dst_ipv4_addr;
5254 u8 l4type = 0;
5255
5256 /* check if we're UDP or TCP */
5257 if (iph->protocol == IPPROTO_TCP) {
5258 th = tcp_hdr(skb);
5259 src_port = th->source;
5260 dst_port = th->dest;
5261 l4type |= IXGBE_ATR_L4TYPE_TCP;
5262 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5263 } else {
5264 /* Unsupported L4 header, just bail here */
5265 return;
5266 }
5267
5268 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5269
5270 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5271 IXGBE_TX_FLAGS_VLAN_SHIFT;
5272 src_ipv4_addr = iph->saddr;
5273 dst_ipv4_addr = iph->daddr;
5274 flex_bytes = eth->h_proto;
5275
5276 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5277 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5278 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5279 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5280 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5281 /* src and dst are inverted, think how the receiver sees them */
5282 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5283 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5284
5285 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5286 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5287}
5288
e092be60 5289static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5290 struct ixgbe_ring *tx_ring, int size)
e092be60 5291{
30eba97a 5292 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5293 /* Herbert's original patch had:
5294 * smp_mb__after_netif_stop_queue();
5295 * but since that doesn't exist yet, just open code it. */
5296 smp_mb();
5297
5298 /* We need to check again in a case another CPU has just
5299 * made room available. */
5300 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5301 return -EBUSY;
5302
5303 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5304 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5305 ++tx_ring->restart_queue;
e092be60
AV		 5306 return 0;
5307}
5308
5309static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5310 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5311{
5312 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5313 return 0;
5314 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5315}
5316
09a3b1f8
SH		 5317static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5318{
5319 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5320 int txq = smp_processor_id();
09a3b1f8 5321
c4cf55e5 5322 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5f715823 5323 return txq;
c4cf55e5 5324
5f715823
YZ		 5325#ifdef IXGBE_FCOE
5326 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5327 (skb->protocol == htons(ETH_P_FCOE))) {
5328 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5329 txq += adapter->ring_feature[RING_F_FCOE].mask;
5330 return txq;
5331 }
5332#endif
09a3b1f8 5333 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5334 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5335
5336 return skb_tx_hash(dev, skb);
5337}
5338
3b29a56d
SH		 5339static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5340 struct net_device *netdev)
9a799d71
AK		 5341{
5342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5343 struct ixgbe_ring *tx_ring;
60d51134 5344 struct netdev_queue *txq;
9a799d71
AK		 5345 unsigned int first;
5346 unsigned int tx_flags = 0;
30eba97a 5347 u8 hdr_len = 0;
5f715823 5348 int tso;
9a799d71
AK		 5349 int count = 0;
5350 unsigned int f;
9f8cdf4f 5351
9f8cdf4f
JB		 5352 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5353 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5354 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5355 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5356 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5357 }
5358 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5359 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5360 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865 5361 if (skb->priority != TC_PRIO_CONTROL) {
5f715823 5362 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
60127865
LL		 5363 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5364 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5365 } else {
5366 skb->queue_mapping =
5367 adapter->ring_feature[RING_F_DCB].indices-1;
5368 }
9a799d71 5369 }
eacd73f7 5370
5f715823 5371 tx_ring = &adapter->tx_ring[skb->queue_mapping];
60127865 5372
eacd73f7 5373 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5374 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5375 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5376#ifdef IXGBE_FCOE
61a0f421
YZ		 5377#ifdef CONFIG_IXGBE_DCB
5378 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5379 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5380 tx_flags |= ((adapter->fcoe.up << 13)
5381 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5382#endif
09ad1cc0
YZ		 5383#endif
5384 }
eacd73f7 5385 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5386 if (skb_is_gso(skb) ||
5387 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5388 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5389 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5390 count++;
5391
9f8cdf4f
JB		 5392 count += TXD_USE_COUNT(skb_headlen(skb));
5393 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5394 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5395
e092be60 5396 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5397 adapter->tx_busy++;
9a799d71
AK		 5398 return NETDEV_TX_BUSY;
5399 }
9a799d71 5400
9a799d71 5401 first = tx_ring->next_to_use;
eacd73f7
YZ		 5402 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5403#ifdef IXGBE_FCOE
5404 /* setup tx offload for FCoE */
5405 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5406 if (tso < 0) {
5407 dev_kfree_skb_any(skb);
5408 return NETDEV_TX_OK;
5409 }
5410 if (tso)
5411 tx_flags |= IXGBE_TX_FLAGS_FSO;
5412#endif /* IXGBE_FCOE */
5413 } else {
5414 if (skb->protocol == htons(ETH_P_IP))
5415 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5416 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5417 if (tso < 0) {
5418 dev_kfree_skb_any(skb);
5419 return NETDEV_TX_OK;
5420 }
9a799d71 5421
eacd73f7
YZ		 5422 if (tso)
5423 tx_flags |= IXGBE_TX_FLAGS_TSO;
5424 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5425 (skb->ip_summed == CHECKSUM_PARTIAL))
5426 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5427 }
9a799d71 5428
eacd73f7 5429 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5430 if (count) {
c4cf55e5
PWJ		 5431 /* add the ATR filter if ATR is on */
5432 if (tx_ring->atr_sample_rate) {
5433 ++tx_ring->atr_count;
5434 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5435 test_bit(__IXGBE_FDIR_INIT_DONE,
5436 &tx_ring->reinit_state)) {
5437 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5438 tx_flags);
5439 tx_ring->atr_count = 0;
5440 }
5441 }
60d51134
ED		 5442 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5443 txq->tx_bytes += skb->len;
5444 txq->tx_packets++;
44df32c5
AD		 5445 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5446 hdr_len);
44df32c5 5447 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5448
44df32c5
AD		 5449 } else {
5450 dev_kfree_skb_any(skb);
5451 tx_ring->tx_buffer_info[first].time_stamp = 0;
5452 tx_ring->next_to_use = first;
5453 }
9a799d71
AK		 5454
5455 return NETDEV_TX_OK;
5456}
5457
9a799d71
AK		 5458/**
5459 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5460 * @netdev: network interface device structure
5461 * @p: pointer to an address structure
5462 *
5463 * Returns 0 on success, negative on failure
5464 **/
5465static int ixgbe_set_mac(struct net_device *netdev, void *p)
5466{
5467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5468 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5469 struct sockaddr *addr = p;
5470
5471 if (!is_valid_ether_addr(addr->sa_data))
5472 return -EADDRNOTAVAIL;
5473
5474 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5475 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5476
b4617240 5477 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5478
5479 return 0;
5480}
5481
6b73e10d
BH		 5482static int
5483ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5484{
5485 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5486 struct ixgbe_hw *hw = &adapter->hw;
5487 u16 value;
5488 int rc;
5489
5490 if (prtad != hw->phy.mdio.prtad)
5491 return -EINVAL;
5492 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5493 if (!rc)
5494 rc = value;
5495 return rc;
5496}
5497
5498static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5499 u16 addr, u16 value)
5500{
5501 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5502 struct ixgbe_hw *hw = &adapter->hw;
5503
5504 if (prtad != hw->phy.mdio.prtad)
5505 return -EINVAL;
5506 return hw->phy.ops.write_reg(hw, addr, devad, value);
5507}
5508
5509static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5510{
5511 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5512
5513 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5514}
5515
0365e6e4
PW		 5516/**
5517 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5518 * netdev->dev_addrs
0365e6e4
PW		 5519 * @netdev: network interface device structure
5520 *
5521 * Returns non-zero on failure
5522 **/
5523static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5524{
5525 int err = 0;
5526 struct ixgbe_adapter *adapter = netdev_priv(dev);
5527 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5528
5529 if (is_valid_ether_addr(mac->san_addr)) {
5530 rtnl_lock();
5531 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5532 rtnl_unlock();
5533 }
5534 return err;
5535}
5536
5537/**
5538 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5539 * netdev->dev_addrs
0365e6e4
PW		 5540 * @netdev: network interface device structure
5541 *
5542 * Returns non-zero on failure
5543 **/
5544static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5545{
5546 int err = 0;
5547 struct ixgbe_adapter *adapter = netdev_priv(dev);
5548 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5549
5550 if (is_valid_ether_addr(mac->san_addr)) {
5551 rtnl_lock();
5552 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5553 rtnl_unlock();
5554 }
5555 return err;
5556}
5557
9a799d71
AK		 5558#ifdef CONFIG_NET_POLL_CONTROLLER
5559/*
5560 * Polling 'interrupt' - used by things like netconsole to send skbs
5561 * without having to re-enable interrupts. It's not called while
5562 * the interrupt routine is executing.
5563 */
5564static void ixgbe_netpoll(struct net_device *netdev)
5565{
5566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5567 int i;
9a799d71 5568
9a799d71 5569 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5570 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5571 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5572 for (i = 0; i < num_q_vectors; i++) {
5573 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5574 ixgbe_msix_clean_many(0, q_vector);
5575 }
5576 } else {
5577 ixgbe_intr(adapter->pdev->irq, netdev);
5578 }
9a799d71 5579 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5580}
5581#endif
5582
0edc3527
SH		 5583static const struct net_device_ops ixgbe_netdev_ops = {
5584 .ndo_open = ixgbe_open,
5585 .ndo_stop = ixgbe_close,
00829823 5586 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5587 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5588 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5589 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5590 .ndo_validate_addr = eth_validate_addr,
5591 .ndo_set_mac_address = ixgbe_set_mac,
5592 .ndo_change_mtu = ixgbe_change_mtu,
5593 .ndo_tx_timeout = ixgbe_tx_timeout,
5594 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5595 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5596 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5597 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5598#ifdef CONFIG_NET_POLL_CONTROLLER
5599 .ndo_poll_controller = ixgbe_netpoll,
5600#endif
332d4a7d
YZ		 5601#ifdef IXGBE_FCOE
5602 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5603 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5604 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5605 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5606 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5607#endif /* IXGBE_FCOE */
0edc3527
SH		 5608};
5609
9a799d71
AK		 5610/**
5611 * ixgbe_probe - Device Initialization Routine
5612 * @pdev: PCI device information struct
5613 * @ent: entry in ixgbe_pci_tbl
5614 *
5615 * Returns 0 on success, negative on failure
5616 *
5617 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5618 * The OS initialization, configuring of the adapter private structure,
5619 * and a hardware reset occur.
5620 **/
5621static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5622 const struct pci_device_id *ent)
9a799d71
AK		 5623{
5624 struct net_device *netdev;
5625 struct ixgbe_adapter *adapter = NULL;
5626 struct ixgbe_hw *hw;
5627 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5628 static int cards_found;
5629 int i, err, pci_using_dac;
eacd73f7
YZ		 5630#ifdef IXGBE_FCOE
5631 u16 device_caps;
5632#endif
c44ade9e 5633 u32 part_num, eec;
9a799d71 5634
9ce77666 5635 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5636 if (err)
5637 return err;
5638
6a35528a
YH		 5639 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5640 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5641 pci_using_dac = 1;
5642 } else {
284901a9 5643 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5644 if (err) {
284901a9 5645 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5646 if (err) {
b4617240
PW		 5647 dev_err(&pdev->dev, "No usable DMA "
5648 "configuration, aborting\n");
9a799d71
AK		 5649 goto err_dma;
5650 }
5651 }
5652 pci_using_dac = 0;
5653 }
5654
9ce77666 5655 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5656 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5657 if (err) {
9ce77666 5658 dev_err(&pdev->dev,
5659 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5660 goto err_pci_reg;
5661 }
5662
19d5afd4 5663 pci_enable_pcie_error_reporting(pdev);
6fabd715 5664
9a799d71 5665 pci_set_master(pdev);
fb3b27bc 5666 pci_save_state(pdev);
9a799d71 5667
30eba97a 5668 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5669 if (!netdev) {
5670 err = -ENOMEM;
5671 goto err_alloc_etherdev;
5672 }
5673
9a799d71
AK		 5674 SET_NETDEV_DEV(netdev, &pdev->dev);
5675
5676 pci_set_drvdata(pdev, netdev);
5677 adapter = netdev_priv(netdev);
5678
5679 adapter->netdev = netdev;
5680 adapter->pdev = pdev;
5681 hw = &adapter->hw;
5682 hw->back = adapter;
5683 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5684
05857980
JK		 5685 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5686 pci_resource_len(pdev, 0));
9a799d71
AK		 5687 if (!hw->hw_addr) {
5688 err = -EIO;
5689 goto err_ioremap;
5690 }
5691
5692 for (i = 1; i <= 5; i++) {
5693 if (pci_resource_len(pdev, i) == 0)
5694 continue;
5695 }
5696
0edc3527 5697 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5698 ixgbe_set_ethtool_ops(netdev);
9a799d71 5699 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5700 strcpy(netdev->name, pci_name(pdev));
5701
9a799d71
AK		 5702 adapter->bd_number = cards_found;
5703
9a799d71
AK		 5704 /* Setup hw api */
5705 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5706 hw->mac.type = ii->mac;
9a799d71 5707
c44ade9e
JB		 5708 /* EEPROM */
5709 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5710 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5711 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5712 if (!(eec & (1 << 8)))
5713 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5714
5715 /* PHY */
5716 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5717 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5718 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5719 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5720 hw->phy.mdio.mmds = 0;
5721 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5722 hw->phy.mdio.dev = netdev;
5723 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5724 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5725
5726 /* set up this timer and work struct before calling get_invariants
5727 * which might start the timer
5728 */
5729 init_timer(&adapter->sfp_timer);
5730 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5731 adapter->sfp_timer.data = (unsigned long) adapter;
5732
5733 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5734
e8e26350
PW		 5735 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5736 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5737
5738 /* a new SFP+ module arrival, called from GPI SDP2 context */
5739 INIT_WORK(&adapter->sfp_config_module_task,
5740 ixgbe_sfp_config_module_task);
5741
8ca783ab 5742 ii->get_invariants(hw);
9a799d71
AK		 5743
5744 /* setup the private structure */
5745 err = ixgbe_sw_init(adapter);
5746 if (err)
5747 goto err_sw_init;
5748
bf069c97
DS		 5749 /*
5750 * If there is a fan on this device and it has failed log the
5751 * failure.
5752 */
5753 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5754 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5755 if (esdp & IXGBE_ESDP_SDP1)
5756 DPRINTK(PROBE, CRIT,
5757 "Fan has stopped, replace the adapter\n");
5758 }
5759
c44ade9e
JB		 5760 /* reset_hw fills in the perm_addr as well */
5761 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5762 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5763 hw->mac.type == ixgbe_mac_82598EB) {
5764 /*
5765 * Start a kernel thread to watch for a module to arrive.
5766 * Only do this for 82598, since 82599 will generate
5767 * interrupts on module arrival.
5768 */
5769 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5770 mod_timer(&adapter->sfp_timer,
5771 round_jiffies(jiffies + (2 * HZ)));
5772 err = 0;
5773 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5774 dev_err(&adapter->pdev->dev, "failed to initialize because "
5775 "an unsupported SFP+ module type was detected.\n"
5776 "Reload the driver after installing a supported "
5777 "module.\n");
04f165ef
PW		 5778 goto err_sw_init;
5779 } else if (err) {
c44ade9e
JB		 5780 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5781 goto err_sw_init;
5782 }
5783
9a799d71 5784 netdev->features = NETIF_F_SG |
b4617240
PW		 5785 NETIF_F_IP_CSUM |
5786 NETIF_F_HW_VLAN_TX |
5787 NETIF_F_HW_VLAN_RX |
5788 NETIF_F_HW_VLAN_FILTER;
9a799d71 5789
e9990a9c 5790 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5791 netdev->features |= NETIF_F_TSO;
9a799d71 5792 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5793 netdev->features |= NETIF_F_GRO;
ad31c402 5794
45a5ead0
JB		 5795 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5796 netdev->features |= NETIF_F_SCTP_CSUM;
5797
ad31c402
JK		 5798 netdev->vlan_features |= NETIF_F_TSO;
5799 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5800 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5801 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5802 netdev->vlan_features |= NETIF_F_SG;
5803
2f90b865
AD		 5804 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5805 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5806
7a6b6f51 5807#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5808 netdev->dcbnl_ops = &dcbnl_ops;
5809#endif
5810
eacd73f7 5811#ifdef IXGBE_FCOE
0d551589 5812 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5813 if (hw->mac.ops.get_device_caps) {
5814 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5815 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5816 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5817 }
5818 }
5819#endif /* IXGBE_FCOE */
9a799d71
AK		 5820 if (pci_using_dac)
5821 netdev->features |= NETIF_F_HIGHDMA;
5822
0c19d6af 5823 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5824 netdev->features |= NETIF_F_LRO;
5825
9a799d71 5826 /* make sure the EEPROM is good */
c44ade9e 5827 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5828 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5829 err = -EIO;
5830 goto err_eeprom;
5831 }
5832
5833 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5834 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5835
c44ade9e
JB		 5836 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5837 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5838 err = -EIO;
5839 goto err_eeprom;
5840 }
5841
5842 init_timer(&adapter->watchdog_timer);
5843 adapter->watchdog_timer.function = &ixgbe_watchdog;
5844 adapter->watchdog_timer.data = (unsigned long)adapter;
5845
5846 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5847 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5848
021230d4
AV		 5849 err = ixgbe_init_interrupt_scheme(adapter);
5850 if (err)
5851 goto err_sw_init;
9a799d71 5852
e8e26350
PW		 5853 switch (pdev->device) {
5854 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5855 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5856 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5857 /* Enable ACPI wakeup in GRC */
5858 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5859 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5860 break;
5861 default:
5862 adapter->wol = 0;
5863 break;
5864 }
e8e26350
PW		 5865 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5866
04f165ef
PW		 5867 /* pick up the PCI bus settings for reporting later */
5868 hw->mac.ops.get_bus_info(hw);
5869
9a799d71 5870 /* print bus type/speed/width info */
7c510e4b 5871 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5872 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5873 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5874 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5875 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5876 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5877 "Unknown"),
7c510e4b 5878 netdev->dev_addr);
c44ade9e 5879 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5880 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5881 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5882 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5883 (part_num >> 8), (part_num & 0xff));
5884 else
5885 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5886 hw->mac.type, hw->phy.type,
5887 (part_num >> 8), (part_num & 0xff));
9a799d71 5888
e8e26350 5889 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5890 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5891 "this card is not sufficient for optimal "
5892 "performance.\n");
0c254d86 5893 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5894 "PCI-Express slot is required.\n");
0c254d86
AK		 5895 }
5896
34b0368c
PWJ		 5897 /* save off EEPROM version number */
5898 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5899
9a799d71 5900 /* reset the hardware with the new settings */
794caeb2 5901 err = hw->mac.ops.start_hw(hw);
c44ade9e 5902
794caeb2
PWJ		 5903 if (err == IXGBE_ERR_EEPROM_VERSION) {
5904 /* We are running on a pre-production device, log a warning */
5905 dev_warn(&pdev->dev, "This device is a pre-production "
5906 "adapter/LOM. Please be aware there may be issues "
5907 "associated with your hardware. If you are "
5908 "experiencing problems please contact your Intel or "
5909 "hardware representative who provided you with this "
5910 "hardware.\n");
5911 }
9a799d71
AK		 5912 strcpy(netdev->name, "eth%d");
5913 err = register_netdev(netdev);
5914 if (err)
5915 goto err_register;
5916
54386467
JB		 5917 /* carrier off reporting is important to ethtool even BEFORE open */
5918 netif_carrier_off(netdev);
5919
c4cf55e5
PWJ		 5920 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5921 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5922 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5923
5dd2d332 5924#ifdef CONFIG_IXGBE_DCA
652f093f 5925 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5926 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5927 ixgbe_setup_dca(adapter);
5928 }
5929#endif
0365e6e4
PW		 5930 /* add san mac addr to netdev */
5931 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5932
5933 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5934 cards_found++;
5935 return 0;
5936
5937err_register:
5eba3699 5938 ixgbe_release_hw_control(adapter);
7a921c93 5939 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5940err_sw_init:
5941err_eeprom:
c4900be0
DS		 5942 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5943 del_timer_sync(&adapter->sfp_timer);
5944 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5945 cancel_work_sync(&adapter->multispeed_fiber_task);
5946 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5947 iounmap(hw->hw_addr);
5948err_ioremap:
5949 free_netdev(netdev);
5950err_alloc_etherdev:
9ce77666 5951 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5952 IORESOURCE_MEM));
9a799d71
AK		 5953err_pci_reg:
5954err_dma:
5955 pci_disable_device(pdev);
5956 return err;
5957}
5958
5959/**
5960 * ixgbe_remove - Device Removal Routine
5961 * @pdev: PCI device information struct
5962 *
5963 * ixgbe_remove is called by the PCI subsystem to alert the driver
5964 * that it should release a PCI device. The could be caused by a
5965 * Hot-Plug event, or because the driver is going to be removed from
5966 * memory.
5967 **/
5968static void __devexit ixgbe_remove(struct pci_dev *pdev)
5969{
5970 struct net_device *netdev = pci_get_drvdata(pdev);
5971 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5972
5973 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5974 /* clear the module not found bit to make sure the worker won't
5975 * reschedule
5976 */
5977 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5978 del_timer_sync(&adapter->watchdog_timer);
5979
c4900be0
DS		 5980 del_timer_sync(&adapter->sfp_timer);
5981 cancel_work_sync(&adapter->watchdog_task);
5982 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5983 cancel_work_sync(&adapter->multispeed_fiber_task);
5984 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5985 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5986 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5987 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5988 flush_scheduled_work();
5989
5dd2d332 5990#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5991 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5992 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5993 dca_remove_requester(&pdev->dev);
5994 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5995 }
5996
5997#endif
332d4a7d
YZ		 5998#ifdef IXGBE_FCOE
5999 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6000 ixgbe_cleanup_fcoe(adapter);
6001
6002#endif /* IXGBE_FCOE */
0365e6e4
PW		 6003
6004 /* remove the added san mac */
6005 ixgbe_del_sanmac_netdev(netdev);
6006
c4900be0
DS		 6007 if (netdev->reg_state == NETREG_REGISTERED)
6008 unregister_netdev(netdev);
9a799d71 6009
7a921c93 6010 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6011
021230d4 6012 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6013
6014 iounmap(adapter->hw.hw_addr);
9ce77666 6015 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6016 IORESOURCE_MEM));
9a799d71 6017
021230d4 6018 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6019
9a799d71
AK		 6020 free_netdev(netdev);
6021
19d5afd4 6022 pci_disable_pcie_error_reporting(pdev);
6fabd715 6023
9a799d71
AK		 6024 pci_disable_device(pdev);
6025}
6026
6027/**
6028 * ixgbe_io_error_detected - called when PCI error is detected
6029 * @pdev: Pointer to PCI device
6030 * @state: The current pci connection state
6031 *
6032 * This function is called after a PCI bus error affecting
6033 * this device has been detected.
6034 */
6035static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6036 pci_channel_state_t state)
9a799d71
AK		 6037{
6038 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6039 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6040
6041 netif_device_detach(netdev);
6042
3044b8d1
BL		 6043 if (state == pci_channel_io_perm_failure)
6044 return PCI_ERS_RESULT_DISCONNECT;
6045
9a799d71
AK		 6046 if (netif_running(netdev))
6047 ixgbe_down(adapter);
6048 pci_disable_device(pdev);
6049
b4617240 6050 /* Request a slot reset. */
9a799d71
AK		 6051 return PCI_ERS_RESULT_NEED_RESET;
6052}
6053
6054/**
6055 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6056 * @pdev: Pointer to PCI device
6057 *
6058 * Restart the card from scratch, as if from a cold-boot.
6059 */
6060static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6061{
6062 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6063 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6064 pci_ers_result_t result;
6065 int err;
9a799d71 6066
9ce77666 6067 if (pci_enable_device_mem(pdev)) {
9a799d71 6068 DPRINTK(PROBE, ERR,
b4617240 6069 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6070 result = PCI_ERS_RESULT_DISCONNECT;
6071 } else {
6072 pci_set_master(pdev);
6073 pci_restore_state(pdev);
c0e1f68b 6074 pci_save_state(pdev);
9a799d71 6075
dd4d8ca6 6076 pci_wake_from_d3(pdev, false);
9a799d71 6077
6fabd715 6078 ixgbe_reset(adapter);
88512539 6079 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6080 result = PCI_ERS_RESULT_RECOVERED;
6081 }
6082
6083 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6084 if (err) {
6085 dev_err(&pdev->dev,
6086 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6087 /* non-fatal, continue */
6088 }
9a799d71 6089
6fabd715 6090 return result;
9a799d71
AK		 6091}
6092
6093/**
6094 * ixgbe_io_resume - called when traffic can start flowing again.
6095 * @pdev: Pointer to PCI device
6096 *
6097 * This callback is called when the error recovery driver tells us that
6098 * its OK to resume normal operation.
6099 */
6100static void ixgbe_io_resume(struct pci_dev *pdev)
6101{
6102 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6103 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6104
6105 if (netif_running(netdev)) {
6106 if (ixgbe_up(adapter)) {
6107 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6108 return;
6109 }
6110 }
6111
6112 netif_device_attach(netdev);
9a799d71
AK		 6113}
6114
6115static struct pci_error_handlers ixgbe_err_handler = {
6116 .error_detected = ixgbe_io_error_detected,
6117 .slot_reset = ixgbe_io_slot_reset,
6118 .resume = ixgbe_io_resume,
6119};
6120
6121static struct pci_driver ixgbe_driver = {
6122 .name = ixgbe_driver_name,
6123 .id_table = ixgbe_pci_tbl,
6124 .probe = ixgbe_probe,
6125 .remove = __devexit_p(ixgbe_remove),
6126#ifdef CONFIG_PM
6127 .suspend = ixgbe_suspend,
6128 .resume = ixgbe_resume,
6129#endif
6130 .shutdown = ixgbe_shutdown,
6131 .err_handler = &ixgbe_err_handler
6132};
6133
6134/**
6135 * ixgbe_init_module - Driver Registration Routine
6136 *
6137 * ixgbe_init_module is the first routine called when the driver is
6138 * loaded. All it does is register with the PCI subsystem.
6139 **/
6140static int __init ixgbe_init_module(void)
6141{
6142 int ret;
6143 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6144 ixgbe_driver_string, ixgbe_driver_version);
6145
6146 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6147
5dd2d332 6148#ifdef CONFIG_IXGBE_DCA
bd0362dd 6149 dca_register_notify(&dca_notifier);
bd0362dd 6150#endif
5dd2d332 6151
9a799d71
AK		 6152 ret = pci_register_driver(&ixgbe_driver);
6153 return ret;
6154}
b4617240 6155
9a799d71
AK		 6156module_init(ixgbe_init_module);
6157
6158/**
6159 * ixgbe_exit_module - Driver Exit Cleanup Routine
6160 *
6161 * ixgbe_exit_module is called just before the driver is removed
6162 * from memory.
6163 **/
6164static void __exit ixgbe_exit_module(void)
6165{
5dd2d332 6166#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6167 dca_unregister_notify(&dca_notifier);
6168#endif
9a799d71
AK		 6169 pci_unregister_driver(&ixgbe_driver);
6170}
bd0362dd 6171
5dd2d332 6172#ifdef CONFIG_IXGBE_DCA
bd0362dd 6173static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6174 void *p)
bd0362dd
JC		 6175{
6176 int ret_val;
6177
6178 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6179 __ixgbe_notify_dca);
bd0362dd
JC		 6180
6181 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6182}
b453368d 6183
5dd2d332 6184#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6185#ifdef DEBUG
6186/**
6187 * ixgbe_get_hw_dev_name - return device name string
6188 * used by hardware layer to print debugging information
6189 **/
6190char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6191{
6192 struct ixgbe_adapter *adapter = hw->back;
6193 return adapter->netdev->name;
6194}
bd0362dd 6195
b453368d 6196#endif
9a799d71
AK		 6197module_exit(ixgbe_exit_module);
6198
6199/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree