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ixgbe: move GSO segments and byte count processing into ixgbe_tx_map
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601}
602
84418e3b 603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
e8e9f696
JP		 604 struct ixgbe_tx_buffer
605 *tx_buffer_info)
9a799d71 606{
e5a43549
AD		 607 if (tx_buffer_info->dma) {
608 if (tx_buffer_info->mapped_as_page)
1b507730 609 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 610 tx_buffer_info->dma,
611 tx_buffer_info->length,
1b507730 612 DMA_TO_DEVICE);
e5a43549 613 else
1b507730 614 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 615 tx_buffer_info->dma,
616 tx_buffer_info->length,
1b507730 617 DMA_TO_DEVICE);
e5a43549
AD		 618 tx_buffer_info->dma = 0;
619 }
9a799d71
AK		 620 if (tx_buffer_info->skb) {
621 dev_kfree_skb_any(tx_buffer_info->skb);
622 tx_buffer_info->skb = NULL;
623 }
44df32c5 624 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 625 /* tx_buffer_info must be completely set up in the transmit path */
626}
627
26f23d82 628/**
7483d9dd 629 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 630 * @adapter: the ixgbe adapter
631 * @tx_ring: the corresponding tx_ring
632 *
633 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
634 * corresponding TC of this tx_ring when checking TFCS.
635 *
7483d9dd 636 * Returns : true if in xon state (currently not paused)
26f23d82 637 */
7483d9dd 638static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 639 struct ixgbe_ring *tx_ring)
26f23d82 640{
26f23d82
YZ		 641 u32 txoff = IXGBE_TFCS_TXOFF;
642
643#ifdef CONFIG_IXGBE_DCB
ca739481 644 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 645 int tc;
26f23d82
YZ		 646 int reg_idx = tx_ring->reg_idx;
647 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
648
6837e895
PW		 649 switch (adapter->hw.mac.type) {
650 case ixgbe_mac_82598EB:
26f23d82
YZ		 651 tc = reg_idx >> 2;
652 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 653 break;
654 case ixgbe_mac_82599EB:
26f23d82
YZ		 655 tc = 0;
656 txoff = IXGBE_TFCS_TXOFF;
657 if (dcb_i == 8) {
658 /* TC0, TC1 */
659 tc = reg_idx >> 5;
660 if (tc == 2) /* TC2, TC3 */
661 tc += (reg_idx - 64) >> 4;
662 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
663 tc += 1 + ((reg_idx - 96) >> 3);
664 } else if (dcb_i == 4) {
665 /* TC0, TC1 */
666 tc = reg_idx >> 6;
667 if (tc == 1) {
668 tc += (reg_idx - 64) >> 5;
669 if (tc == 2) /* TC2, TC3 */
670 tc += (reg_idx - 96) >> 4;
671 }
672 }
6837e895
PW		 673 break;
674 default:
675 tc = 0;
26f23d82
YZ		 676 }
677 txoff <<= tc;
678 }
679#endif
680 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
681}
682
9a799d71 683static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 684 struct ixgbe_ring *tx_ring,
685 unsigned int eop)
9a799d71 686{
e01c31a5 687 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 688
9a799d71 689 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 690 * check with the clearing of time_stamp and movement of eop */
9a799d71 691 adapter->detect_tx_hung = false;
44df32c5 692 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 693 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 694 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 695 /* detected Tx unit hang */
e01c31a5 696 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 697 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 698 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 699 " Tx Queue <%d>\n"
700 " TDH, TDT <%x>, <%x>\n"
701 " next_to_use <%x>\n"
702 " next_to_clean <%x>\n"
703 "tx_buffer_info[next_to_clean]\n"
704 " time_stamp <%lx>\n"
705 " jiffies <%lx>\n",
706 tx_ring->queue_index,
707 IXGBE_READ_REG(hw, tx_ring->head),
708 IXGBE_READ_REG(hw, tx_ring->tail),
709 tx_ring->next_to_use, eop,
710 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 711 return true;
712 }
713
714 return false;
715}
716
b4617240
PW		 717#define IXGBE_MAX_TXD_PWR 14
718#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 719
720/* Tx Descriptors needed, worst case */
721#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
722 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
723#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 724 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 725
e01c31a5
JB		 726static void ixgbe_tx_timeout(struct net_device *netdev);
727
9a799d71
AK		 728/**
729 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 730 * @q_vector: structure containing interrupt and ring information
e01c31a5 731 * @tx_ring: tx ring to clean
9a799d71 732 **/
fe49f04a 733static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 734 struct ixgbe_ring *tx_ring)
9a799d71 735{
fe49f04a 736 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 737 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 738 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
739 struct ixgbe_tx_buffer *tx_buffer_info;
740 unsigned int i, eop, count = 0;
e01c31a5 741 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 742
743 i = tx_ring->next_to_clean;
12207e49 744 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 745 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 746
747 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 748 (count < tx_ring->work_limit)) {
12207e49 749 bool cleaned = false;
2d0bb1c1 750 rmb(); /* read buffer_info after eop_desc */
12207e49 751 for ( ; !cleaned; count++) {
31f05a2d 752 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 753 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 754
755 tx_desc->wb.status = 0;
12207e49 756 cleaned = (i == eop);
9a799d71 757
8ad494b0
AD		 758 i++;
759 if (i == tx_ring->count)
760 i = 0;
e01c31a5 761
8ad494b0
AD		 762 if (cleaned && tx_buffer_info->skb) {
763 total_bytes += tx_buffer_info->bytecount;
764 total_packets += tx_buffer_info->gso_segs;
e092be60 765 }
e01c31a5 766
9a799d71 767 ixgbe_unmap_and_free_tx_resource(adapter,
e8e9f696 768 tx_buffer_info);
e01c31a5 769 }
12207e49
PWJ		 770
771 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 772 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 773 }
774
9a799d71
AK		 775 tx_ring->next_to_clean = i;
776
e092be60 777#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5 778 if (unlikely(count && netif_carrier_ok(netdev) &&
e8e9f696 779 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 780 /* Make sure that anybody stopping the queue after this
781 * sees the new next_to_clean.
782 */
783 smp_mb();
30eba97a
AV		 784 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
785 !test_bit(__IXGBE_DOWN, &adapter->state)) {
786 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 787 ++tx_ring->restart_queue;
30eba97a 788 }
e092be60 789 }
9a799d71 790
e01c31a5
JB		 791 if (adapter->detect_tx_hung) {
792 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
793 /* schedule immediate reset if we believe we hung */
396e799c
ET		 794 e_info(probe, "tx hang %d detected, resetting "
795 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 796 ixgbe_tx_timeout(adapter->netdev);
797 }
798 }
9a799d71 799
e01c31a5 800 /* re-arm the interrupt */
fe49f04a
AD		 801 if (count >= tx_ring->work_limit)
802 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 803
e01c31a5
JB		 804 tx_ring->total_bytes += total_bytes;
805 tx_ring->total_packets += total_packets;
de1036b1 806 u64_stats_update_begin(&tx_ring->syncp);
e01c31a5 807 tx_ring->stats.packets += total_packets;
12207e49 808 tx_ring->stats.bytes += total_bytes;
de1036b1 809 u64_stats_update_end(&tx_ring->syncp);
807540ba 810 return count < tx_ring->work_limit;
9a799d71
AK		 811}
812
5dd2d332 813#ifdef CONFIG_IXGBE_DCA
bd0362dd 814static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
e8e9f696 815 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 816{
817 u32 rxctrl;
818 int cpu = get_cpu();
4a0b9ca0 819 int q = rx_ring->reg_idx;
bd0362dd 820
3a581073 821 if (rx_ring->cpu != cpu) {
bd0362dd 822 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
824 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
825 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
826 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
827 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
828 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 829 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
e8e26350 830 }
bd0362dd
JC		 831 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
832 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 833 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
834 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e9f696 835 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 837 rx_ring->cpu = cpu;
bd0362dd
JC		 838 }
839 put_cpu();
840}
841
842static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
e8e9f696 843 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 844{
845 u32 txctrl;
846 int cpu = get_cpu();
4a0b9ca0 847 int q = tx_ring->reg_idx;
ee5f784a 848 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 849
3a581073 850 if (tx_ring->cpu != cpu) {
e8e26350 851 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 852 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 853 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
854 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 855 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
856 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 857 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 858 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 859 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
860 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 861 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
ee5f784a
DS		 862 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
863 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 864 }
3a581073 865 tx_ring->cpu = cpu;
bd0362dd
JC		 866 }
867 put_cpu();
868}
869
870static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
871{
872 int i;
873
874 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
875 return;
876
e35ec126
AD		 877 /* always use CB2 mode, difference is masked in the CB driver */
878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
879
bd0362dd 880 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 881 adapter->tx_ring[i]->cpu = -1;
882 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 883 }
884 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 885 adapter->rx_ring[i]->cpu = -1;
886 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 887 }
888}
889
890static int __ixgbe_notify_dca(struct device *dev, void *data)
891{
892 struct net_device *netdev = dev_get_drvdata(dev);
893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
894 unsigned long event = *(unsigned long *)data;
895
896 switch (event) {
897 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 898 /* if we're already enabled, don't do it again */
899 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
900 break;
652f093f 901 if (dca_add_requester(dev) == 0) {
96b0e0f6 902 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 903 ixgbe_setup_dca(adapter);
904 break;
905 }
906 /* Fall Through since DCA is disabled. */
907 case DCA_PROVIDER_REMOVE:
908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
909 dca_remove_requester(dev);
910 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
912 }
913 break;
914 }
915
652f093f 916 return 0;
bd0362dd
JC		 917}
918
5dd2d332 919#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 920/**
921 * ixgbe_receive_skb - Send a completed packet up the stack
922 * @adapter: board private structure
923 * @skb: packet to send up
177db6ff
MC		 924 * @status: hardware indication of status of receive
925 * @rx_ring: rx descriptor ring (for a specific queue) to setup
926 * @rx_desc: rx descriptor
9a799d71 927 **/
78b6f4ce 928static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 929 struct sk_buff *skb, u8 status,
930 struct ixgbe_ring *ring,
931 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 932{
78b6f4ce
HX		 933 struct ixgbe_adapter *adapter = q_vector->adapter;
934 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 935 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
936 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 937
f62bbb5e
JG		 938 if (is_vlan && (tag & VLAN_VID_MASK))
939 __vlan_hwaccel_put_tag(skb, tag);
940
941 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
942 napi_gro_receive(napi, skb);
943 else
944 netif_rx(skb);
9a799d71
AK		 945}
946
e59bd25d
AV		 947/**
948 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
949 * @adapter: address of board private structure
950 * @status_err: hardware indication of status of receive
951 * @skb: skb currently being received and modified
952 **/
9a799d71 953static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 954 union ixgbe_adv_rx_desc *rx_desc,
955 struct sk_buff *skb)
9a799d71 956{
8bae1b2b
DS		 957 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
958
bc8acf2c 959 skb_checksum_none_assert(skb);
9a799d71 960
712744be
JB		 961 /* Rx csum disabled */
962 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 963 return;
e59bd25d
AV		 964
965 /* if IP and error */
966 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
967 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 968 adapter->hw_csum_rx_error++;
969 return;
970 }
e59bd25d
AV		 971
972 if (!(status_err & IXGBE_RXD_STAT_L4CS))
973 return;
974
975 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 976 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
977
978 /*
979 * 82599 errata, UDP frames with a 0 checksum can be marked as
980 * checksum errors.
981 */
982 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
983 (adapter->hw.mac.type == ixgbe_mac_82599EB))
984 return;
985
e59bd25d
AV		 986 adapter->hw_csum_rx_error++;
987 return;
988 }
989
9a799d71 990 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 991 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 992}
993
e8e26350 994static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
e8e9f696 995 struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 996{
997 /*
998 * Force memory writes to complete before letting h/w
999 * know there are new descriptors to fetch. (Only
1000 * applicable for weak-ordered memory model archs,
1001 * such as IA-64).
1002 */
1003 wmb();
1004 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1005}
1006
9a799d71
AK		 1007/**
1008 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1009 * @adapter: address of board private structure
1010 **/
84418e3b 1011void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1012 struct ixgbe_ring *rx_ring,
1013 int cleaned_count)
9a799d71 1014{
d716a7d8 1015 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1016 struct pci_dev *pdev = adapter->pdev;
1017 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1018 struct ixgbe_rx_buffer *bi;
9a799d71 1019 unsigned int i;
d716a7d8 1020 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1021
1022 i = rx_ring->next_to_use;
3a581073 1023 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1024
1025 while (cleaned_count--) {
31f05a2d 1026 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1027
762f4c57 1028 if (!bi->page_dma &&
6e455b89 1029 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1030 if (!bi->page) {
d716a7d8 1031 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1032 if (!bi->page) {
1033 adapter->alloc_rx_page_failed++;
1034 goto no_buffers;
1035 }
1036 bi->page_offset = 0;
1037 } else {
1038 /* use a half page if we're re-using */
1039 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1040 }
762f4c57 1041
1b507730 1042 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
e8e9f696
JP		 1043 bi->page_offset,
1044 (PAGE_SIZE / 2),
1b507730 1045 DMA_FROM_DEVICE);
9a799d71
AK		 1046 }
1047
3a581073 1048 if (!bi->skb) {
d716a7d8
AD		 1049 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1050 bufsz);
1051 bi->skb = skb;
9a799d71
AK		 1052
1053 if (!skb) {
1054 adapter->alloc_rx_buff_failed++;
1055 goto no_buffers;
1056 }
d716a7d8
AD		 1057 /* initialize queue mapping */
1058 skb_record_rx_queue(skb, rx_ring->queue_index);
1059 }
9a799d71 1060
d716a7d8
AD		 1061 if (!bi->dma) {
1062 bi->dma = dma_map_single(&pdev->dev,
1063 bi->skb->data,
e8e9f696 1064 rx_ring->rx_buf_len,
1b507730 1065 DMA_FROM_DEVICE);
9a799d71
AK		 1066 }
1067 /* Refresh the desc even if buffer_addrs didn't change because
1068 * each write-back erases this info. */
6e455b89 1069 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1070 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1071 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1072 } else {
3a581073 1073 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1074 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1075 }
1076
1077 i++;
1078 if (i == rx_ring->count)
1079 i = 0;
3a581073 1080 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1081 }
7c6e0a43 1082
9a799d71
AK		 1083no_buffers:
1084 if (rx_ring->next_to_use != i) {
1085 rx_ring->next_to_use = i;
1086 if (i-- == 0)
1087 i = (rx_ring->count - 1);
1088
e8e26350 1089 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1090 }
1091}
1092
7c6e0a43
JB		 1093static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1094{
1095 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1096}
1097
1098static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1099{
1100 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1101}
1102
f8212f97
AD		 1103static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1104{
1105 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1106 IXGBE_RXDADV_RSCCNT_MASK) >>
1107 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1108}
1109
1110/**
1111 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1112 * @skb: pointer to the last skb in the rsc queue
94b982b2 1113 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1114 *
1115 * This function changes a queue full of hw rsc buffers into a completed
1116 * packet. It uses the ->prev pointers to find the first packet and then
1117 * turns it into the frag list owner.
1118 **/
94b982b2 1119static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1120 u64 *count)
f8212f97
AD		 1121{
1122 unsigned int frag_list_size = 0;
1123
1124 while (skb->prev) {
1125 struct sk_buff *prev = skb->prev;
1126 frag_list_size += skb->len;
1127 skb->prev = NULL;
1128 skb = prev;
94b982b2 1129 *count += 1;
f8212f97
AD		 1130 }
1131
1132 skb_shinfo(skb)->frag_list = skb->next;
1133 skb->next = NULL;
1134 skb->len += frag_list_size;
1135 skb->data_len += frag_list_size;
1136 skb->truesize += frag_list_size;
1137 return skb;
1138}
1139
43634e82
MC		 1140struct ixgbe_rsc_cb {
1141 dma_addr_t dma;
e8171aaa 1142 bool delay_unmap;
43634e82
MC		 1143};
1144
1145#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1146
78b6f4ce 1147static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1148 struct ixgbe_ring *rx_ring,
1149 int *work_done, int work_to_do)
9a799d71 1150{
78b6f4ce 1151 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1152 struct pci_dev *pdev = adapter->pdev;
1153 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1154 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1155 struct sk_buff *skb;
f8212f97 1156 unsigned int i, rsc_count = 0;
7c6e0a43 1157 u32 len, staterr;
177db6ff
MC		 1158 u16 hdr_info;
1159 bool cleaned = false;
9a799d71 1160 int cleaned_count = 0;
d2f4fbe2 1161 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1162#ifdef IXGBE_FCOE
1163 int ddp_bytes = 0;
1164#endif /* IXGBE_FCOE */
9a799d71
AK		 1165
1166 i = rx_ring->next_to_clean;
31f05a2d 1167 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1168 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1169 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1170
1171 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1172 u32 upper_len = 0;
9a799d71
AK		 1173 if (*work_done >= work_to_do)
1174 break;
1175 (*work_done)++;
1176
3c945e5b 1177 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1178 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1179 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1180 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1181 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1182 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1183 if ((len > IXGBE_RX_HDR_SIZE) ||
1184 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1185 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1186 } else {
9a799d71 1187 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1188 }
9a799d71
AK		 1189
1190 cleaned = true;
1191 skb = rx_buffer_info->skb;
7ca3bc58 1192 prefetch(skb->data);
9a799d71
AK		 1193 rx_buffer_info->skb = NULL;
1194
21fa4e66 1195 if (rx_buffer_info->dma) {
43634e82
MC		 1196 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1197 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1198 (!(skb->prev))) {
43634e82
MC		 1199 /*
1200 * When HWRSC is enabled, delay unmapping
1201 * of the first packet. It carries the
1202 * header information, HW may still
1203 * access the header after the writeback.
1204 * Only unmap it when EOP is reached
1205 */
e8171aaa 1206 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1207 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1208 } else {
1b507730 1209 dma_unmap_single(&pdev->dev,
e8e9f696
JP		 1210 rx_buffer_info->dma,
1211 rx_ring->rx_buf_len,
1212 DMA_FROM_DEVICE);
e8171aaa 1213 }
4f57ca6e 1214 rx_buffer_info->dma = 0;
9a799d71
AK		 1215 skb_put(skb, len);
1216 }
1217
1218 if (upper_len) {
1b507730
NN		 1219 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1220 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1221 rx_buffer_info->page_dma = 0;
1222 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1223 rx_buffer_info->page,
1224 rx_buffer_info->page_offset,
1225 upper_len);
762f4c57
JB		 1226
1227 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1228 (page_count(rx_buffer_info->page) != 1))
1229 rx_buffer_info->page = NULL;
1230 else
1231 get_page(rx_buffer_info->page);
9a799d71
AK		 1232
1233 skb->len += upper_len;
1234 skb->data_len += upper_len;
1235 skb->truesize += upper_len;
1236 }
1237
1238 i++;
1239 if (i == rx_ring->count)
1240 i = 0;
9a799d71 1241
31f05a2d 1242 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1243 prefetch(next_rxd);
9a799d71 1244 cleaned_count++;
f8212f97 1245
0c19d6af 1246 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1247 rsc_count = ixgbe_get_rsc_count(rx_desc);
1248
1249 if (rsc_count) {
1250 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1251 IXGBE_RXDADV_NEXTP_SHIFT;
1252 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1253 } else {
1254 next_buffer = &rx_ring->rx_buffer_info[i];
1255 }
1256
9a799d71 1257 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1258 if (skb->prev)
e8e9f696
JP		 1259 skb = ixgbe_transform_rsc_queue(skb,
1260 &(rx_ring->rsc_count));
94b982b2 1261 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1262 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1263 dma_unmap_single(&pdev->dev,
1264 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1265 rx_ring->rx_buf_len,
1b507730 1266 DMA_FROM_DEVICE);
fd3686a8 1267 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1268 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1269 }
94b982b2 1270 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
e8e9f696
JP		 1271 rx_ring->rsc_count +=
1272 skb_shinfo(skb)->nr_frags;
94b982b2
MC		 1273 else
1274 rx_ring->rsc_count++;
1275 rx_ring->rsc_flush++;
1276 }
de1036b1 1277 u64_stats_update_begin(&rx_ring->syncp);
9a799d71
AK		 1278 rx_ring->stats.packets++;
1279 rx_ring->stats.bytes += skb->len;
de1036b1 1280 u64_stats_update_end(&rx_ring->syncp);
9a799d71 1281 } else {
6e455b89 1282 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1283 rx_buffer_info->skb = next_buffer->skb;
1284 rx_buffer_info->dma = next_buffer->dma;
1285 next_buffer->skb = skb;
1286 next_buffer->dma = 0;
1287 } else {
1288 skb->next = next_buffer->skb;
1289 skb->next->prev = skb;
1290 }
7ca3bc58 1291 rx_ring->non_eop_descs++;
9a799d71
AK		 1292 goto next_desc;
1293 }
1294
1295 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1296 dev_kfree_skb_irq(skb);
1297 goto next_desc;
1298 }
1299
8bae1b2b 1300 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1301
1302 /* probably a little skewed due to removing CRC */
1303 total_rx_bytes += skb->len;
1304 total_rx_packets++;
1305
74ce8dd2 1306 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1307#ifdef IXGBE_FCOE
1308 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1309 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1310 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1311 if (!ddp_bytes)
332d4a7d 1312 goto next_desc;
3d8fd385 1313 }
332d4a7d 1314#endif /* IXGBE_FCOE */
fdaff1ce 1315 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1316
1317next_desc:
1318 rx_desc->wb.upper.status_error = 0;
1319
1320 /* return some buffers to hardware, one at a time is too slow */
1321 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1322 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1323 cleaned_count = 0;
1324 }
1325
1326 /* use prefetched values */
1327 rx_desc = next_rxd;
f8212f97 1328 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1329
1330 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1331 }
1332
9a799d71
AK		 1333 rx_ring->next_to_clean = i;
1334 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1335
1336 if (cleaned_count)
1337 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1338
3d8fd385
YZ		 1339#ifdef IXGBE_FCOE
1340 /* include DDPed FCoE data */
1341 if (ddp_bytes > 0) {
1342 unsigned int mss;
1343
1344 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1345 sizeof(struct fc_frame_header) -
1346 sizeof(struct fcoe_crc_eof);
1347 if (mss > 512)
1348 mss &= ~511;
1349 total_rx_bytes += ddp_bytes;
1350 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1351 }
1352#endif /* IXGBE_FCOE */
1353
f494e8fa
AV		 1354 rx_ring->total_packets += total_rx_packets;
1355 rx_ring->total_bytes += total_rx_bytes;
f494e8fa 1356
9a799d71
AK		 1357 return cleaned;
1358}
1359
021230d4 1360static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1361/**
1362 * ixgbe_configure_msix - Configure MSI-X hardware
1363 * @adapter: board private structure
1364 *
1365 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1366 * interrupts.
1367 **/
1368static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1369{
021230d4
AV		 1370 struct ixgbe_q_vector *q_vector;
1371 int i, j, q_vectors, v_idx, r_idx;
1372 u32 mask;
9a799d71 1373
021230d4 1374 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1375
4df10466
JB		 1376 /*
1377 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1378 * corresponding register.
1379 */
1380 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1381 q_vector = adapter->q_vector[v_idx];
984b3f57 1382 /* XXX for_each_set_bit(...) */
021230d4 1383 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1384 adapter->num_rx_queues);
021230d4
AV		 1385
1386 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1387 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1388 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1389 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1390 adapter->num_rx_queues,
1391 r_idx + 1);
021230d4
AV		 1392 }
1393 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1394 adapter->num_tx_queues);
021230d4
AV		 1395
1396 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1397 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1398 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1399 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1400 adapter->num_tx_queues,
1401 r_idx + 1);
021230d4
AV		 1402 }
1403
021230d4 1404 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1405 /* tx only */
1406 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1407 else if (q_vector->rxr_count)
f7554a2b
NS		 1408 /* rx or mixed */
1409 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1410
fe49f04a 1411 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1412 /* If Flow Director is enabled, set interrupt affinity */
1413 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1414 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1415 /*
1416 * Allocate the affinity_hint cpumask, assign the mask
1417 * for this vector, and set our affinity_hint for
1418 * this irq.
1419 */
1420 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1421 GFP_KERNEL))
1422 return;
1423 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1424 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1425 q_vector->affinity_mask);
1426 }
9a799d71
AK		 1427 }
1428
e8e26350
PW		 1429 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1430 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1431 v_idx);
e8e26350
PW		 1432 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1433 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1435
41fb9248 1436 /* set up to autoclear timer, and the vectors */
021230d4 1437 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1438 if (adapter->num_vfs)
1439 mask &= ~(IXGBE_EIMS_OTHER |
1440 IXGBE_EIMS_MAILBOX |
1441 IXGBE_EIMS_LSC);
1442 else
1443 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1445}
1446
f494e8fa
AV		 1447enum latency_range {
1448 lowest_latency = 0,
1449 low_latency = 1,
1450 bulk_latency = 2,
1451 latency_invalid = 255
1452};
1453
1454/**
1455 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1456 * @adapter: pointer to adapter
1457 * @eitr: eitr setting (ints per sec) to give last timeslice
1458 * @itr_setting: current throttle rate in ints/second
1459 * @packets: the number of packets during this measurement interval
1460 * @bytes: the number of bytes during this measurement interval
1461 *
1462 * Stores a new ITR value based on packets and byte
1463 * counts during the last interrupt. The advantage of per interrupt
1464 * computation is faster updates and more accurate ITR for the current
1465 * traffic pattern. Constants in this function were computed
1466 * based on theoretical maximum wire speed and thresholds were set based
1467 * on testing data as well as attempting to minimize response time
1468 * while increasing bulk throughput.
1469 * this functionality is controlled by the InterruptThrottleRate module
1470 * parameter (see ixgbe_param.c)
1471 **/
1472static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1473 u32 eitr, u8 itr_setting,
1474 int packets, int bytes)
f494e8fa
AV		 1475{
1476 unsigned int retval = itr_setting;
1477 u32 timepassed_us;
1478 u64 bytes_perint;
1479
1480 if (packets == 0)
1481 goto update_itr_done;
1482
1483
1484 /* simple throttlerate management
1485 * 0-20MB/s lowest (100000 ints/s)
1486 * 20-100MB/s low (20000 ints/s)
1487 * 100-1249MB/s bulk (8000 ints/s)
1488 */
1489 /* what was last interrupt timeslice? */
1490 timepassed_us = 1000000/eitr;
1491 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1492
1493 switch (itr_setting) {
1494 case lowest_latency:
1495 if (bytes_perint > adapter->eitr_low)
1496 retval = low_latency;
1497 break;
1498 case low_latency:
1499 if (bytes_perint > adapter->eitr_high)
1500 retval = bulk_latency;
1501 else if (bytes_perint <= adapter->eitr_low)
1502 retval = lowest_latency;
1503 break;
1504 case bulk_latency:
1505 if (bytes_perint <= adapter->eitr_high)
1506 retval = low_latency;
1507 break;
1508 }
1509
1510update_itr_done:
1511 return retval;
1512}
1513
509ee935
JB		 1514/**
1515 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1516 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1517 *
1518 * This function is made to be called by ethtool and by the driver
1519 * when it needs to update EITR registers at runtime. Hardware
1520 * specific quirks/differences are taken care of here.
1521 */
fe49f04a 1522void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1523{
fe49f04a 1524 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1525 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1526 int v_idx = q_vector->v_idx;
1527 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1528
509ee935
JB		 1529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1530 /* must write high and low 16 bits to reset counter */
1531 itr_reg |= (itr_reg << 16);
1532 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1533 /*
1534 * 82599 can support a value of zero, so allow it for
1535 * max interrupt rate, but there is an errata where it can
1536 * not be zero with RSC
1537 */
1538 if (itr_reg == 8 &&
1539 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1540 itr_reg = 0;
1541
509ee935
JB		 1542 /*
1543 * set the WDIS bit to not clear the timer bits and cause an
1544 * immediate assertion of the interrupt
1545 */
1546 itr_reg |= IXGBE_EITR_CNT_WDIS;
1547 }
1548 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1549}
1550
f494e8fa
AV		 1551static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1552{
1553 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1554 u32 new_itr;
1555 u8 current_itr, ret_itr;
fe49f04a 1556 int i, r_idx;
f494e8fa
AV		 1557 struct ixgbe_ring *rx_ring, *tx_ring;
1558
1559 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1560 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1561 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1562 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1563 q_vector->tx_itr,
1564 tx_ring->total_packets,
1565 tx_ring->total_bytes);
f494e8fa
AV		 1566 /* if the result for this queue would decrease interrupt
1567 * rate for this vector then use that result */
30efa5a3 1568 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1569 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1570 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1571 r_idx + 1);
f494e8fa
AV		 1572 }
1573
1574 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1575 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1576 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1577 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1578 q_vector->rx_itr,
1579 rx_ring->total_packets,
1580 rx_ring->total_bytes);
f494e8fa
AV		 1581 /* if the result for this queue would decrease interrupt
1582 * rate for this vector then use that result */
30efa5a3 1583 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1584 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1585 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1586 r_idx + 1);
f494e8fa
AV		 1587 }
1588
30efa5a3 1589 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1590
1591 switch (current_itr) {
1592 /* counts and packets in update_itr are dependent on these numbers */
1593 case lowest_latency:
1594 new_itr = 100000;
1595 break;
1596 case low_latency:
1597 new_itr = 20000; /* aka hwitr = ~200 */
1598 break;
1599 case bulk_latency:
1600 default:
1601 new_itr = 8000;
1602 break;
1603 }
1604
1605 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1606 /* do an exponential smoothing */
1607 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1608
1609 /* save the algorithm value here, not the smoothed one */
1610 q_vector->eitr = new_itr;
fe49f04a
AD		 1611
1612 ixgbe_write_eitr(q_vector);
f494e8fa 1613 }
f494e8fa
AV		 1614}
1615
119fc60a
MC		 1616/**
1617 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1618 * @work: pointer to work_struct containing our data
1619 **/
1620static void ixgbe_check_overtemp_task(struct work_struct *work)
1621{
1622 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1623 struct ixgbe_adapter,
1624 check_overtemp_task);
119fc60a
MC		 1625 struct ixgbe_hw *hw = &adapter->hw;
1626 u32 eicr = adapter->interrupt_event;
1627
7ca647bd
JP		 1628 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1629 return;
1630
1631 switch (hw->device_id) {
1632 case IXGBE_DEV_ID_82599_T3_LOM: {
1633 u32 autoneg;
1634 bool link_up = false;
1635
1636 if (hw->mac.ops.check_link)
1637 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1638
1639 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1640 (eicr & IXGBE_EICR_LSC))
1641 /* Check if this is due to overtemp */
1642 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1643 break;
1644 return;
1645 }
1646 default:
1647 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1648 return;
7ca647bd 1649 break;
119fc60a 1650 }
7ca647bd
JP		 1651 e_crit(drv,
1652 "Network adapter has been stopped because it has over heated. "
1653 "Restart the computer. If the problem persists, "
1654 "power off the system and replace the adapter\n");
1655 /* write to clear the interrupt */
1656 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1657}
1658
0befdb3e
JB		 1659static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1660{
1661 struct ixgbe_hw *hw = &adapter->hw;
1662
1663 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1664 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1665 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1666 /* write to clear the interrupt */
1667 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1668 }
1669}
cf8280ee 1670
e8e26350
PW		 1671static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1672{
1673 struct ixgbe_hw *hw = &adapter->hw;
1674
1675 if (eicr & IXGBE_EICR_GPI_SDP1) {
1676 /* Clear the interrupt */
1677 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1678 schedule_work(&adapter->multispeed_fiber_task);
1679 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1680 /* Clear the interrupt */
1681 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1682 schedule_work(&adapter->sfp_config_module_task);
1683 } else {
1684 /* Interrupt isn't for us... */
1685 return;
1686 }
1687}
1688
cf8280ee
JB		 1689static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1690{
1691 struct ixgbe_hw *hw = &adapter->hw;
1692
1693 adapter->lsc_int++;
1694 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1695 adapter->link_check_timeout = jiffies;
1696 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1697 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1698 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1699 schedule_work(&adapter->watchdog_task);
1700 }
1701}
1702
9a799d71
AK		 1703static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1704{
1705 struct net_device *netdev = data;
1706 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1707 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1708 u32 eicr;
1709
1710 /*
1711 * Workaround for Silicon errata. Use clear-by-write instead
1712 * of clear-by-read. Reading with EICS will return the
1713 * interrupt causes without clearing, which later be done
1714 * with the write to EICR.
1715 */
1716 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1717 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1718
cf8280ee
JB		 1719 if (eicr & IXGBE_EICR_LSC)
1720 ixgbe_check_lsc(adapter);
d4f80882 1721
1cdd1ec8
GR		 1722 if (eicr & IXGBE_EICR_MAILBOX)
1723 ixgbe_msg_task(adapter);
1724
e8e26350
PW		 1725 if (hw->mac.type == ixgbe_mac_82598EB)
1726 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1727
c4cf55e5 1728 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1729 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1730 adapter->interrupt_event = eicr;
1731 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1732 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1733 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1734
1735 /* Handle Flow Director Full threshold interrupt */
1736 if (eicr & IXGBE_EICR_FLOW_DIR) {
1737 int i;
1738 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1739 /* Disable transmits before FDIR Re-initialization */
1740 netif_tx_stop_all_queues(netdev);
1741 for (i = 0; i < adapter->num_tx_queues; i++) {
1742 struct ixgbe_ring *tx_ring =
e8e9f696 1743 adapter->tx_ring[i];
c4cf55e5 1744 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 1745 &tx_ring->reinit_state))
c4cf55e5
PWJ		 1746 schedule_work(&adapter->fdir_reinit_task);
1747 }
1748 }
1749 }
d4f80882
AV		 1750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1751 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1752
1753 return IRQ_HANDLED;
1754}
1755
fe49f04a
AD		 1756static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1757 u64 qmask)
1758{
1759 u32 mask;
1760
1761 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1762 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1764 } else {
1765 mask = (qmask & 0xFFFFFFFF);
1766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1767 mask = (qmask >> 32);
1768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1769 }
1770 /* skip the flush */
1771}
1772
1773static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1774 u64 qmask)
fe49f04a
AD		 1775{
1776 u32 mask;
1777
1778 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1779 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1780 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1781 } else {
1782 mask = (qmask & 0xFFFFFFFF);
1783 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1784 mask = (qmask >> 32);
1785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1786 }
1787 /* skip the flush */
1788}
1789
9a799d71
AK		 1790static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1791{
021230d4
AV		 1792 struct ixgbe_q_vector *q_vector = data;
1793 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1794 struct ixgbe_ring *tx_ring;
021230d4
AV		 1795 int i, r_idx;
1796
1797 if (!q_vector->txr_count)
1798 return IRQ_HANDLED;
1799
1800 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1801 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1802 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1803 tx_ring->total_bytes = 0;
1804 tx_ring->total_packets = 0;
021230d4 1805 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1806 r_idx + 1);
021230d4 1807 }
9a799d71 1808
9b471446 1809 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1810 napi_schedule(&q_vector->napi);
1811
9a799d71
AK		 1812 return IRQ_HANDLED;
1813}
1814
021230d4
AV		 1815/**
1816 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1817 * @irq: unused
1818 * @data: pointer to our q_vector struct for this interrupt vector
1819 **/
9a799d71
AK		 1820static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1821{
021230d4
AV		 1822 struct ixgbe_q_vector *q_vector = data;
1823 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1824 struct ixgbe_ring *rx_ring;
021230d4 1825 int r_idx;
30efa5a3 1826 int i;
021230d4
AV		 1827
1828 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1829 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1830 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1831 rx_ring->total_bytes = 0;
1832 rx_ring->total_packets = 0;
1833 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1834 r_idx + 1);
30efa5a3
JB		 1835 }
1836
021230d4
AV		 1837 if (!q_vector->rxr_count)
1838 return IRQ_HANDLED;
1839
021230d4 1840 /* disable interrupts on this vector only */
9b471446 1841 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1842 napi_schedule(&q_vector->napi);
021230d4
AV		 1843
1844 return IRQ_HANDLED;
1845}
1846
1847static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1848{
91281fd3
AD		 1849 struct ixgbe_q_vector *q_vector = data;
1850 struct ixgbe_adapter *adapter = q_vector->adapter;
1851 struct ixgbe_ring *ring;
1852 int r_idx;
1853 int i;
1854
1855 if (!q_vector->txr_count && !q_vector->rxr_count)
1856 return IRQ_HANDLED;
1857
1858 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1859 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1860 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1861 ring->total_bytes = 0;
1862 ring->total_packets = 0;
1863 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1864 r_idx + 1);
91281fd3
AD		 1865 }
1866
1867 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1868 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1869 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1870 ring->total_bytes = 0;
1871 ring->total_packets = 0;
1872 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1873 r_idx + 1);
91281fd3
AD		 1874 }
1875
9b471446 1876 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1877 napi_schedule(&q_vector->napi);
9a799d71 1878
9a799d71
AK		 1879 return IRQ_HANDLED;
1880}
1881
021230d4
AV		 1882/**
1883 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1884 * @napi: napi struct with our devices info in it
1885 * @budget: amount of work driver is allowed to do this pass, in packets
1886 *
f0848276
JB		 1887 * This function is optimized for cleaning one queue only on a single
1888 * q_vector!!!
021230d4 1889 **/
9a799d71
AK		 1890static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1891{
021230d4 1892 struct ixgbe_q_vector *q_vector =
e8e9f696 1893 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1894 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1895 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1896 int work_done = 0;
021230d4 1897 long r_idx;
9a799d71 1898
021230d4 1899 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1900 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1901#ifdef CONFIG_IXGBE_DCA
bd0362dd 1902 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1903 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1904#endif
9a799d71 1905
78b6f4ce 1906 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1907
021230d4
AV		 1908 /* If all Rx work done, exit the polling mode */
1909 if (work_done < budget) {
288379f0 1910 napi_complete(napi);
f7554a2b 1911 if (adapter->rx_itr_setting & 1)
f494e8fa 1912 ixgbe_set_itr_msix(q_vector);
9a799d71 1913 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1914 ixgbe_irq_enable_queues(adapter,
e8e9f696 1915 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1916 }
1917
1918 return work_done;
1919}
1920
f0848276 1921/**
91281fd3 1922 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1923 * @napi: napi struct with our devices info in it
1924 * @budget: amount of work driver is allowed to do this pass, in packets
1925 *
1926 * This function will clean more than one rx queue associated with a
1927 * q_vector.
1928 **/
91281fd3 1929static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1930{
1931 struct ixgbe_q_vector *q_vector =
e8e9f696 1932 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1933 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1934 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1935 int work_done = 0, i;
1936 long r_idx;
91281fd3
AD		 1937 bool tx_clean_complete = true;
1938
1939 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1940 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1941 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1942#ifdef CONFIG_IXGBE_DCA
1943 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1944 ixgbe_update_tx_dca(adapter, ring);
1945#endif
1946 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1947 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1948 r_idx + 1);
91281fd3 1949 }
f0848276
JB		 1950
1951 /* attempt to distribute budget to each queue fairly, but don't allow
1952 * the budget to go below 1 because we'll exit polling */
1953 budget /= (q_vector->rxr_count ?: 1);
1954 budget = max(budget, 1);
1955 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1956 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1957 ring = adapter->rx_ring[r_idx];
5dd2d332 1958#ifdef CONFIG_IXGBE_DCA
f0848276 1959 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1960 ixgbe_update_rx_dca(adapter, ring);
f0848276 1961#endif
91281fd3 1962 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 1963 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1964 r_idx + 1);
f0848276
JB		 1965 }
1966
1967 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1968 ring = adapter->rx_ring[r_idx];
f0848276 1969 /* If all Rx work done, exit the polling mode */
7f821875 1970 if (work_done < budget) {
288379f0 1971 napi_complete(napi);
f7554a2b 1972 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1973 ixgbe_set_itr_msix(q_vector);
1974 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1975 ixgbe_irq_enable_queues(adapter,
e8e9f696 1976 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1977 return 0;
1978 }
1979
1980 return work_done;
1981}
91281fd3
AD		 1982
1983/**
1984 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1985 * @napi: napi struct with our devices info in it
1986 * @budget: amount of work driver is allowed to do this pass, in packets
1987 *
1988 * This function is optimized for cleaning one queue only on a single
1989 * q_vector!!!
1990 **/
1991static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1992{
1993 struct ixgbe_q_vector *q_vector =
e8e9f696 1994 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 1995 struct ixgbe_adapter *adapter = q_vector->adapter;
1996 struct ixgbe_ring *tx_ring = NULL;
1997 int work_done = 0;
1998 long r_idx;
1999
2000 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2001 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2002#ifdef CONFIG_IXGBE_DCA
2003 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2004 ixgbe_update_tx_dca(adapter, tx_ring);
2005#endif
2006
2007 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2008 work_done = budget;
2009
f7554a2b 2010 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2011 if (work_done < budget) {
2012 napi_complete(napi);
f7554a2b 2013 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2014 ixgbe_set_itr_msix(q_vector);
2015 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2016 ixgbe_irq_enable_queues(adapter,
2017 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2018 }
2019
2020 return work_done;
2021}
2022
021230d4 2023static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2024 int r_idx)
021230d4 2025{
7a921c93
AD		 2026 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2027
2028 set_bit(r_idx, q_vector->rxr_idx);
2029 q_vector->rxr_count++;
021230d4
AV		 2030}
2031
2032static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2033 int t_idx)
021230d4 2034{
7a921c93
AD		 2035 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2036
2037 set_bit(t_idx, q_vector->txr_idx);
2038 q_vector->txr_count++;
021230d4
AV		 2039}
2040
9a799d71 2041/**
021230d4
AV		 2042 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2043 * @adapter: board private structure to initialize
2044 * @vectors: allotted vector count for descriptor rings
9a799d71 2045 *
021230d4
AV		 2046 * This function maps descriptor rings to the queue-specific vectors
2047 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2048 * one vector per ring/queue, but on a constrained vector budget, we
2049 * group the rings as "efficiently" as possible. You would add new
2050 * mapping configurations in here.
9a799d71 2051 **/
021230d4 2052static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2053 int vectors)
021230d4
AV		 2054{
2055 int v_start = 0;
2056 int rxr_idx = 0, txr_idx = 0;
2057 int rxr_remaining = adapter->num_rx_queues;
2058 int txr_remaining = adapter->num_tx_queues;
2059 int i, j;
2060 int rqpv, tqpv;
2061 int err = 0;
2062
2063 /* No mapping required if MSI-X is disabled. */
2064 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2065 goto out;
9a799d71 2066
021230d4
AV		 2067 /*
2068 * The ideal configuration...
2069 * We have enough vectors to map one per queue.
2070 */
2071 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2072 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2073 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2074
021230d4
AV		 2075 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2076 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2077
9a799d71 2078 goto out;
021230d4 2079 }
9a799d71 2080
021230d4
AV		 2081 /*
2082 * If we don't have enough vectors for a 1-to-1
2083 * mapping, we'll have to group them so there are
2084 * multiple queues per vector.
2085 */
2086 /* Re-adjusting *qpv takes care of the remainder. */
2087 for (i = v_start; i < vectors; i++) {
2088 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2089 for (j = 0; j < rqpv; j++) {
2090 map_vector_to_rxq(adapter, i, rxr_idx);
2091 rxr_idx++;
2092 rxr_remaining--;
2093 }
2094 }
2095 for (i = v_start; i < vectors; i++) {
2096 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2097 for (j = 0; j < tqpv; j++) {
2098 map_vector_to_txq(adapter, i, txr_idx);
2099 txr_idx++;
2100 txr_remaining--;
9a799d71 2101 }
9a799d71
AK		 2102 }
2103
021230d4
AV		 2104out:
2105 return err;
2106}
2107
2108/**
2109 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2110 * @adapter: board private structure
2111 *
2112 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2113 * interrupts from the kernel.
2114 **/
2115static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2116{
2117 struct net_device *netdev = adapter->netdev;
2118 irqreturn_t (*handler)(int, void *);
2119 int i, vector, q_vectors, err;
e8e9f696 2120 int ri = 0, ti = 0;
021230d4
AV		 2121
2122 /* Decrement for Other and TCP Timer vectors */
2123 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2124
2125 /* Map the Tx/Rx rings to the vectors we were allotted. */
2126 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2127 if (err)
2128 goto out;
2129
2130#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2131 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2132 &ixgbe_msix_clean_many)
021230d4 2133 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2134 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2135
e8e9f696 2136 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2137 sprintf(adapter->name[vector], "%s-%s-%d",
2138 netdev->name, "rx", ri++);
e8e9f696 2139 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2140 sprintf(adapter->name[vector], "%s-%s-%d",
2141 netdev->name, "tx", ti++);
e8e9f696 2142 } else
cb13fc20
RO		 2143 sprintf(adapter->name[vector], "%s-%s-%d",
2144 netdev->name, "TxRx", vector);
2145
021230d4 2146 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2147 handler, 0, adapter->name[vector],
2148 adapter->q_vector[vector]);
9a799d71 2149 if (err) {
396e799c 2150 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2151 "Error: %d\n", err);
021230d4 2152 goto free_queue_irqs;
9a799d71 2153 }
9a799d71
AK		 2154 }
2155
021230d4
AV		 2156 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2157 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2158 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2159 if (err) {
396e799c 2160 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2161 goto free_queue_irqs;
9a799d71
AK		 2162 }
2163
9a799d71
AK		 2164 return 0;
2165
021230d4
AV		 2166free_queue_irqs:
2167 for (i = vector - 1; i >= 0; i--)
2168 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2169 adapter->q_vector[i]);
021230d4
AV		 2170 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2171 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2172 kfree(adapter->msix_entries);
2173 adapter->msix_entries = NULL;
021230d4 2174out:
9a799d71
AK		 2175 return err;
2176}
2177
f494e8fa
AV		 2178static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2179{
7a921c93 2180 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2181 u8 current_itr;
2182 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2183 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2184 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2185
30efa5a3 2186 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2187 q_vector->tx_itr,
2188 tx_ring->total_packets,
2189 tx_ring->total_bytes);
30efa5a3 2190 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2191 q_vector->rx_itr,
2192 rx_ring->total_packets,
2193 rx_ring->total_bytes);
f494e8fa 2194
30efa5a3 2195 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2196
2197 switch (current_itr) {
2198 /* counts and packets in update_itr are dependent on these numbers */
2199 case lowest_latency:
2200 new_itr = 100000;
2201 break;
2202 case low_latency:
2203 new_itr = 20000; /* aka hwitr = ~200 */
2204 break;
2205 case bulk_latency:
2206 new_itr = 8000;
2207 break;
2208 default:
2209 break;
2210 }
2211
2212 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2213 /* do an exponential smoothing */
2214 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2215
2216 /* save the algorithm value here, not the smoothed one */
2217 q_vector->eitr = new_itr;
fe49f04a
AD		 2218
2219 ixgbe_write_eitr(q_vector);
f494e8fa 2220 }
f494e8fa
AV		 2221}
2222
79aefa45
AD		 2223/**
2224 * ixgbe_irq_enable - Enable default interrupt generation settings
2225 * @adapter: board private structure
2226 **/
6af3b9eb
ET		 2227static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2228 bool flush)
79aefa45
AD		 2229{
2230 u32 mask;
835462fc
NS		 2231
2232 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2233 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2234 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2235 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2236 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2237 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2238 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2239 mask |= IXGBE_EIMS_GPI_SDP1;
2240 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2241 if (adapter->num_vfs)
2242 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2243 }
c4cf55e5
PWJ		 2244 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2245 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2246 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2247
79aefa45 2248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2249 if (queues)
2250 ixgbe_irq_enable_queues(adapter, ~0);
2251 if (flush)
2252 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2253
2254 if (adapter->num_vfs > 32) {
2255 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2257 }
79aefa45 2258}
021230d4 2259
9a799d71 2260/**
021230d4 2261 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2262 * @irq: interrupt number
2263 * @data: pointer to a network interface device structure
9a799d71
AK		 2264 **/
2265static irqreturn_t ixgbe_intr(int irq, void *data)
2266{
2267 struct net_device *netdev = data;
2268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2269 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2270 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2271 u32 eicr;
2272
54037505 2273 /*
6af3b9eb 2274 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2275 * before the read of EICR.
2276 */
2277 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2278
021230d4
AV		 2279 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2280 * therefore no explict interrupt disable is necessary */
2281 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2282 if (!eicr) {
6af3b9eb
ET		 2283 /*
2284 * shared interrupt alert!
f47cf66e 2285 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2286 * have disabled interrupts due to EIAM
2287 * finish the workaround of silicon errata on 82598. Unmask
2288 * the interrupt that we masked before the EICR read.
2289 */
2290 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2291 ixgbe_irq_enable(adapter, true, true);
9a799d71 2292 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2293 }
9a799d71 2294
cf8280ee
JB		 2295 if (eicr & IXGBE_EICR_LSC)
2296 ixgbe_check_lsc(adapter);
021230d4 2297
e8e26350
PW		 2298 if (hw->mac.type == ixgbe_mac_82599EB)
2299 ixgbe_check_sfp_event(adapter, eicr);
2300
0befdb3e 2301 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2302 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2303 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2304 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2305
7a921c93 2306 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2307 adapter->tx_ring[0]->total_packets = 0;
2308 adapter->tx_ring[0]->total_bytes = 0;
2309 adapter->rx_ring[0]->total_packets = 0;
2310 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2311 /* would disable interrupts here but EIAM disabled it */
7a921c93 2312 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2313 }
2314
6af3b9eb
ET		 2315 /*
2316 * re-enable link(maybe) and non-queue interrupts, no flush.
2317 * ixgbe_poll will re-enable the queue interrupts
2318 */
2319
2320 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2321 ixgbe_irq_enable(adapter, false, false);
2322
9a799d71
AK		 2323 return IRQ_HANDLED;
2324}
2325
021230d4
AV		 2326static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2327{
2328 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2329
2330 for (i = 0; i < q_vectors; i++) {
7a921c93 2331 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2332 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2333 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2334 q_vector->rxr_count = 0;
2335 q_vector->txr_count = 0;
2336 }
2337}
2338
9a799d71
AK		 2339/**
2340 * ixgbe_request_irq - initialize interrupts
2341 * @adapter: board private structure
2342 *
2343 * Attempts to configure interrupts using the best available
2344 * capabilities of the hardware and kernel.
2345 **/
021230d4 2346static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2347{
2348 struct net_device *netdev = adapter->netdev;
021230d4 2349 int err;
9a799d71 2350
021230d4
AV		 2351 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2352 err = ixgbe_request_msix_irqs(adapter);
2353 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2354 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2355 netdev->name, netdev);
021230d4 2356 } else {
a0607fd3 2357 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2358 netdev->name, netdev);
9a799d71
AK		 2359 }
2360
9a799d71 2361 if (err)
396e799c 2362 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2363
9a799d71
AK		 2364 return err;
2365}
2366
2367static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2368{
2369 struct net_device *netdev = adapter->netdev;
2370
2371 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2372 int i, q_vectors;
9a799d71 2373
021230d4
AV		 2374 q_vectors = adapter->num_msix_vectors;
2375
2376 i = q_vectors - 1;
9a799d71 2377 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2378
021230d4
AV		 2379 i--;
2380 for (; i >= 0; i--) {
2381 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2382 adapter->q_vector[i]);
021230d4
AV		 2383 }
2384
2385 ixgbe_reset_q_vectors(adapter);
2386 } else {
2387 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2388 }
2389}
2390
22d5a71b
JB		 2391/**
2392 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2393 * @adapter: board private structure
2394 **/
2395static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2396{
835462fc
NS		 2397 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2399 } else {
2400 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2403 if (adapter->num_vfs > 32)
2404 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2405 }
2406 IXGBE_WRITE_FLUSH(&adapter->hw);
2407 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2408 int i;
2409 for (i = 0; i < adapter->num_msix_vectors; i++)
2410 synchronize_irq(adapter->msix_entries[i].vector);
2411 } else {
2412 synchronize_irq(adapter->pdev->irq);
2413 }
2414}
2415
9a799d71
AK		 2416/**
2417 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2418 *
2419 **/
2420static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2421{
9a799d71
AK		 2422 struct ixgbe_hw *hw = &adapter->hw;
2423
021230d4 2424 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2425 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2426
e8e26350
PW		 2427 ixgbe_set_ivar(adapter, 0, 0, 0);
2428 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2429
2430 map_vector_to_rxq(adapter, 0, 0);
2431 map_vector_to_txq(adapter, 0, 0);
2432
396e799c 2433 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2434}
2435
43e69bf0
AD		 2436/**
2437 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2438 * @adapter: board private structure
2439 * @ring: structure containing ring specific data
2440 *
2441 * Configure the Tx descriptor ring after a reset.
2442 **/
84418e3b
AD		 2443void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2444 struct ixgbe_ring *ring)
43e69bf0
AD		 2445{
2446 struct ixgbe_hw *hw = &adapter->hw;
2447 u64 tdba = ring->dma;
2f1860b8
AD		 2448 int wait_loop = 10;
2449 u32 txdctl;
43e69bf0
AD		 2450 u16 reg_idx = ring->reg_idx;
2451
2f1860b8
AD		 2452 /* disable queue to avoid issues while updating state */
2453 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2454 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2455 txdctl & ~IXGBE_TXDCTL_ENABLE);
2456 IXGBE_WRITE_FLUSH(hw);
2457
43e69bf0 2458 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2459 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2460 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2461 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2462 ring->count * sizeof(union ixgbe_adv_tx_desc));
2463 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2464 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2465 ring->head = IXGBE_TDH(reg_idx);
2466 ring->tail = IXGBE_TDT(reg_idx);
2467
2f1860b8
AD		 2468 /* configure fetching thresholds */
2469 if (adapter->rx_itr_setting == 0) {
2470 /* cannot set wthresh when itr==0 */
2471 txdctl &= ~0x007F0000;
2472 } else {
2473 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2474 txdctl |= (8 << 16);
2475 }
2476 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2477 /* PThresh workaround for Tx hang with DFP enabled. */
2478 txdctl |= 32;
2479 }
2480
2481 /* reinitialize flowdirector state */
2482 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2483
2484 /* enable queue */
2485 txdctl |= IXGBE_TXDCTL_ENABLE;
2486 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2487
2488 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2489 if (hw->mac.type == ixgbe_mac_82598EB &&
2490 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2491 return;
2492
2493 /* poll to verify queue is enabled */
2494 do {
2495 msleep(1);
2496 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2497 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2498 if (!wait_loop)
2499 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2500}
2501
120ff942
AD		 2502static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2503{
2504 struct ixgbe_hw *hw = &adapter->hw;
2505 u32 rttdcs;
2506 u32 mask;
2507
2508 if (hw->mac.type == ixgbe_mac_82598EB)
2509 return;
2510
2511 /* disable the arbiter while setting MTQC */
2512 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2513 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2514 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2515
2516 /* set transmit pool layout */
2517 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2518 switch (adapter->flags & mask) {
2519
2520 case (IXGBE_FLAG_SRIOV_ENABLED):
2521 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2522 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2523 break;
2524
2525 case (IXGBE_FLAG_DCB_ENABLED):
2526 /* We enable 8 traffic classes, DCB only */
2527 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2528 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2529 break;
2530
2531 default:
2532 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2533 break;
2534 }
2535
2536 /* re-enable the arbiter */
2537 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2538 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2539}
2540
9a799d71 2541/**
3a581073 2542 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2543 * @adapter: board private structure
2544 *
2545 * Configure the Tx unit of the MAC after a reset.
2546 **/
2547static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2548{
2f1860b8
AD		 2549 struct ixgbe_hw *hw = &adapter->hw;
2550 u32 dmatxctl;
43e69bf0 2551 u32 i;
9a799d71 2552
2f1860b8
AD		 2553 ixgbe_setup_mtqc(adapter);
2554
2555 if (hw->mac.type != ixgbe_mac_82598EB) {
2556 /* DMATXCTL.EN must be before Tx queues are enabled */
2557 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2558 dmatxctl |= IXGBE_DMATXCTL_TE;
2559 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2560 }
2561
9a799d71 2562 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2563 for (i = 0; i < adapter->num_tx_queues; i++)
2564 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2565}
2566
e8e26350 2567#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2568
a6616b42 2569static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2570 struct ixgbe_ring *rx_ring)
cc41ac7c 2571{
cc41ac7c 2572 u32 srrctl;
a6616b42 2573 int index;
0cefafad 2574 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2575
a6616b42
YZ		 2576 index = rx_ring->reg_idx;
2577 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2578 unsigned long mask;
0cefafad 2579 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2580 index = index & mask;
cc41ac7c 2581 }
cc41ac7c
JB		 2582 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2583
2584 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2585 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2586 if (adapter->num_vfs)
2587 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2588
afafd5b0
AD		 2589 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2590 IXGBE_SRRCTL_BSIZEHDR_MASK;
2591
6e455b89 2592 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2593#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2594 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2595#else
2596 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2597#endif
cc41ac7c 2598 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2599 } else {
afafd5b0
AD		 2600 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2601 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2602 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2603 }
e8e26350 2604
cc41ac7c
JB		 2605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2606}
9a799d71 2607
05abb126 2608static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2609{
05abb126
AD		 2610 struct ixgbe_hw *hw = &adapter->hw;
2611 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2612 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2613 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2614 u32 mrqc = 0, reta = 0;
2615 u32 rxcsum;
2616 int i, j;
0cefafad
JB		 2617 int mask;
2618
05abb126
AD		 2619 /* Fill out hash function seeds */
2620 for (i = 0; i < 10; i++)
2621 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2622
2623 /* Fill out redirection table */
2624 for (i = 0, j = 0; i < 128; i++, j++) {
2625 if (j == adapter->ring_feature[RING_F_RSS].indices)
2626 j = 0;
2627 /* reta = 4-byte sliding window of
2628 * 0x00..(indices-1)(indices-1)00..etc. */
2629 reta = (reta << 8) | (j * 0x11);
2630 if ((i & 3) == 3)
2631 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2632 }
0cefafad 2633
05abb126
AD		 2634 /* Disable indicating checksum in descriptor, enables RSS hash */
2635 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2636 rxcsum |= IXGBE_RXCSUM_PCSD;
2637 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2638
2639 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2640 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2641 else
2642 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2643#ifdef CONFIG_IXGBE_DCB
05abb126 2644 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2645#endif
05abb126
AD		 2646 | IXGBE_FLAG_SRIOV_ENABLED
2647 );
0cefafad
JB		 2648
2649 switch (mask) {
2650 case (IXGBE_FLAG_RSS_ENABLED):
2651 mrqc = IXGBE_MRQC_RSSEN;
2652 break;
1cdd1ec8
GR		 2653 case (IXGBE_FLAG_SRIOV_ENABLED):
2654 mrqc = IXGBE_MRQC_VMDQEN;
2655 break;
0cefafad
JB		 2656#ifdef CONFIG_IXGBE_DCB
2657 case (IXGBE_FLAG_DCB_ENABLED):
2658 mrqc = IXGBE_MRQC_RT8TCEN;
2659 break;
2660#endif /* CONFIG_IXGBE_DCB */
2661 default:
2662 break;
2663 }
2664
05abb126
AD		 2665 /* Perform hash on these packet types */
2666 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2667 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2668 | IXGBE_MRQC_RSS_FIELD_IPV6
2669 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2670
2671 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2672}
2673
bb5a9ad2
NS		 2674/**
2675 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2676 * @adapter: address of board private structure
2677 * @index: index of ring to set
bb5a9ad2 2678 **/
7367096a
AD		 2679static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2680 struct ixgbe_ring *ring)
bb5a9ad2 2681{
bb5a9ad2 2682 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2683 u32 rscctrl;
edd2ea55 2684 int rx_buf_len;
7367096a
AD		 2685 u16 reg_idx = ring->reg_idx;
2686
2687 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2688 return;
bb5a9ad2 2689
7367096a
AD		 2690 rx_buf_len = ring->rx_buf_len;
2691 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2692 rscctrl |= IXGBE_RSCCTL_RSCEN;
2693 /*
2694 * we must limit the number of descriptors so that the
2695 * total size of max desc * buf_len is not greater
2696 * than 65535
2697 */
7367096a 2698 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2699#if (MAX_SKB_FRAGS > 16)
2700 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2701#elif (MAX_SKB_FRAGS > 8)
2702 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2703#elif (MAX_SKB_FRAGS > 4)
2704 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2705#else
2706 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2707#endif
2708 } else {
2709 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2710 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2711 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2712 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2713 else
2714 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2715 }
7367096a 2716 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2717}
2718
9e10e045
AD		 2719/**
2720 * ixgbe_set_uta - Set unicast filter table address
2721 * @adapter: board private structure
2722 *
2723 * The unicast table address is a register array of 32-bit registers.
2724 * The table is meant to be used in a way similar to how the MTA is used
2725 * however due to certain limitations in the hardware it is necessary to
2726 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2727 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2728 **/
2729static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2730{
2731 struct ixgbe_hw *hw = &adapter->hw;
2732 int i;
2733
2734 /* The UTA table only exists on 82599 hardware and newer */
2735 if (hw->mac.type < ixgbe_mac_82599EB)
2736 return;
2737
2738 /* we only need to do this if VMDq is enabled */
2739 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2740 return;
2741
2742 for (i = 0; i < 128; i++)
2743 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2744}
2745
2746#define IXGBE_MAX_RX_DESC_POLL 10
2747static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2748 struct ixgbe_ring *ring)
2749{
2750 struct ixgbe_hw *hw = &adapter->hw;
2751 int reg_idx = ring->reg_idx;
2752 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2753 u32 rxdctl;
2754
2755 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2756 if (hw->mac.type == ixgbe_mac_82598EB &&
2757 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2758 return;
2759
2760 do {
2761 msleep(1);
2762 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2763 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2764
2765 if (!wait_loop) {
2766 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2767 "the polling period\n", reg_idx);
2768 }
2769}
2770
84418e3b
AD		 2771void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2772 struct ixgbe_ring *ring)
acd37177
AD		 2773{
2774 struct ixgbe_hw *hw = &adapter->hw;
2775 u64 rdba = ring->dma;
9e10e045 2776 u32 rxdctl;
acd37177
AD		 2777 u16 reg_idx = ring->reg_idx;
2778
9e10e045
AD		 2779 /* disable queue to avoid issues while updating state */
2780 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2781 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2782 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2783 IXGBE_WRITE_FLUSH(hw);
2784
acd37177
AD		 2785 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2786 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2787 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2788 ring->count * sizeof(union ixgbe_adv_rx_desc));
2789 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2790 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2791 ring->head = IXGBE_RDH(reg_idx);
2792 ring->tail = IXGBE_RDT(reg_idx);
9e10e045
AD		 2793
2794 ixgbe_configure_srrctl(adapter, ring);
2795 ixgbe_configure_rscctl(adapter, ring);
2796
2797 if (hw->mac.type == ixgbe_mac_82598EB) {
2798 /*
2799 * enable cache line friendly hardware writes:
2800 * PTHRESH=32 descriptors (half the internal cache),
2801 * this also removes ugly rx_no_buffer_count increment
2802 * HTHRESH=4 descriptors (to minimize latency on fetch)
2803 * WTHRESH=8 burst writeback up to two cache lines
2804 */
2805 rxdctl &= ~0x3FFFFF;
2806 rxdctl |= 0x080420;
2807 }
2808
2809 /* enable receive descriptor ring */
2810 rxdctl |= IXGBE_RXDCTL_ENABLE;
2811 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2812
2813 ixgbe_rx_desc_queue_enable(adapter, ring);
2814 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2815}
2816
48654521
AD		 2817static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2818{
2819 struct ixgbe_hw *hw = &adapter->hw;
2820 int p;
2821
2822 /* PSRTYPE must be initialized in non 82598 adapters */
2823 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2824 IXGBE_PSRTYPE_UDPHDR |
2825 IXGBE_PSRTYPE_IPV4HDR |
48654521 2826 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2827 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2828
2829 if (hw->mac.type == ixgbe_mac_82598EB)
2830 return;
2831
2832 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2833 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2834
2835 for (p = 0; p < adapter->num_rx_pools; p++)
2836 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2837 psrtype);
2838}
2839
f5b4a52e
AD		 2840static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2841{
2842 struct ixgbe_hw *hw = &adapter->hw;
2843 u32 gcr_ext;
2844 u32 vt_reg_bits;
2845 u32 reg_offset, vf_shift;
2846 u32 vmdctl;
2847
2848 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2849 return;
2850
2851 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2852 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2853 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2854 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2855
2856 vf_shift = adapter->num_vfs % 32;
2857 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2858
2859 /* Enable only the PF's pool for Tx/Rx */
2860 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2861 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2862 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2863 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2864 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2865
2866 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2867 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2868
2869 /*
2870 * Set up VF register offsets for selected VT Mode,
2871 * i.e. 32 or 64 VFs for SR-IOV
2872 */
2873 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2874 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2875 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2876 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2877
2878 /* enable Tx loopback for VF/PF communication */
2879 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2880}
2881
477de6ed 2882static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2883{
9a799d71
AK		 2884 struct ixgbe_hw *hw = &adapter->hw;
2885 struct net_device *netdev = adapter->netdev;
2886 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2887 int rx_buf_len;
477de6ed
AD		 2888 struct ixgbe_ring *rx_ring;
2889 int i;
2890 u32 mhadd, hlreg0;
48654521 2891
9a799d71 2892 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2893 /* Do not use packet split if we're in SR-IOV Mode */
2894 if (!adapter->num_vfs)
2895 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2896
2897 /* Set the RX buffer length according to the mode */
2898 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2899 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2900 } else {
0c19d6af 2901 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2902 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2903 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2904 else
477de6ed 2905 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2906 }
2907
63f39bd1 2908#ifdef IXGBE_FCOE
477de6ed
AD		 2909 /* adjust max frame to be able to do baby jumbo for FCoE */
2910 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2911 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2912 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2913
477de6ed
AD		 2914#endif /* IXGBE_FCOE */
2915 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2916 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2917 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2918 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2919
2920 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2921 }
2922
2923 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2924 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2925 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2926 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2927
0cefafad
JB		 2928 /*
2929 * Setup the HW Rx Head and Tail Descriptor Pointers and
2930 * the Base and Length of the Rx Descriptor Ring
2931 */
9a799d71 2932 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2933 rx_ring = adapter->rx_ring[i];
a6616b42 2934 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2935
6e455b89
YZ		 2936 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2937 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2938 else
2939 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2940
63f39bd1 2941#ifdef IXGBE_FCOE
e8e9f696 2942 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2943 struct ixgbe_ring_feature *f;
2944 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2945 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2946 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2947 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2948 rx_ring->rx_buf_len =
e8e9f696 2949 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2950 }
63f39bd1 2951 }
63f39bd1 2952#endif /* IXGBE_FCOE */
477de6ed
AD		 2953 }
2954
2955}
2956
7367096a
AD		 2957static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2958{
2959 struct ixgbe_hw *hw = &adapter->hw;
2960 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2961
2962 switch (hw->mac.type) {
2963 case ixgbe_mac_82598EB:
2964 /*
2965 * For VMDq support of different descriptor types or
2966 * buffer sizes through the use of multiple SRRCTL
2967 * registers, RDRXCTL.MVMEN must be set to 1
2968 *
2969 * also, the manual doesn't mention it clearly but DCA hints
2970 * will only use queue 0's tags unless this bit is set. Side
2971 * effects of setting this bit are only that SRRCTL must be
2972 * fully programmed [0..15]
2973 */
2974 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2975 break;
2976 case ixgbe_mac_82599EB:
2977 /* Disable RSC for ACK packets */
2978 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2979 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2980 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2981 /* hardware requires some bits to be set by default */
2982 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2983 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2984 break;
2985 default:
2986 /* We should do nothing since we don't know this hardware */
2987 return;
2988 }
2989
2990 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2991}
2992
477de6ed
AD		 2993/**
2994 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2995 * @adapter: board private structure
2996 *
2997 * Configure the Rx unit of the MAC after a reset.
2998 **/
2999static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3000{
3001 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3002 int i;
3003 u32 rxctrl;
477de6ed
AD		 3004
3005 /* disable receives while setting up the descriptors */
3006 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3007 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3008
3009 ixgbe_setup_psrtype(adapter);
7367096a 3010 ixgbe_setup_rdrxctl(adapter);
477de6ed 3011
9e10e045 3012 /* Program registers for the distribution of queues */
f5b4a52e 3013 ixgbe_setup_mrqc(adapter);
f5b4a52e 3014
9e10e045
AD		 3015 ixgbe_set_uta(adapter);
3016
477de6ed
AD		 3017 /* set_rx_buffer_len must be called before ring initialization */
3018 ixgbe_set_rx_buffer_len(adapter);
3019
3020 /*
3021 * Setup the HW Rx Head and Tail Descriptor Pointers and
3022 * the Base and Length of the Rx Descriptor Ring
3023 */
9e10e045
AD		 3024 for (i = 0; i < adapter->num_rx_queues; i++)
3025 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3026
9e10e045
AD		 3027 /* disable drop enable for 82598 parts */
3028 if (hw->mac.type == ixgbe_mac_82598EB)
3029 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3030
3031 /* enable all receives */
3032 rxctrl |= IXGBE_RXCTRL_RXEN;
3033 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3034}
3035
068c89b0
DS		 3036static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3037{
3038 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3039 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3040 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3041
3042 /* add VID to filter table */
1ada1b1b 3043 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3044 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3045}
3046
3047static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3048{
3049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3050 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3051 int pool_ndx = adapter->num_vfs;
068c89b0 3052
068c89b0 3053 /* remove VID from filter table */
1ada1b1b 3054 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3055 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3056}
3057
5f6c0181
JB		 3058/**
3059 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3060 * @adapter: driver data
3061 */
3062static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3063{
3064 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3065 u32 vlnctrl;
3066
3067 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3068 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3069 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3070}
3071
3072/**
3073 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3074 * @adapter: driver data
3075 */
3076static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3077{
3078 struct ixgbe_hw *hw = &adapter->hw;
3079 u32 vlnctrl;
3080
3081 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3082 vlnctrl |= IXGBE_VLNCTRL_VFE;
3083 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3084 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3085}
3086
3087/**
3088 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3089 * @adapter: driver data
3090 */
3091static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3092{
3093 struct ixgbe_hw *hw = &adapter->hw;
3094 u32 vlnctrl;
5f6c0181
JB		 3095 int i, j;
3096
3097 switch (hw->mac.type) {
3098 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3099 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3100 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3101 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3102 break;
3103 case ixgbe_mac_82599EB:
5f6c0181
JB		 3104 for (i = 0; i < adapter->num_rx_queues; i++) {
3105 j = adapter->rx_ring[i]->reg_idx;
3106 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3107 vlnctrl &= ~IXGBE_RXDCTL_VME;
3108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3109 }
3110 break;
3111 default:
3112 break;
3113 }
3114}
3115
3116/**
f62bbb5e 3117 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3118 * @adapter: driver data
3119 */
f62bbb5e 3120static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3121{
3122 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3123 u32 vlnctrl;
5f6c0181
JB		 3124 int i, j;
3125
3126 switch (hw->mac.type) {
3127 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3128 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3129 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3130 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3131 break;
3132 case ixgbe_mac_82599EB:
5f6c0181
JB		 3133 for (i = 0; i < adapter->num_rx_queues; i++) {
3134 j = adapter->rx_ring[i]->reg_idx;
3135 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3136 vlnctrl |= IXGBE_RXDCTL_VME;
3137 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3138 }
3139 break;
3140 default:
3141 break;
3142 }
3143}
3144
9a799d71
AK		 3145static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3146{
f62bbb5e 3147 u16 vid;
9a799d71 3148
f62bbb5e
JG		 3149 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3150
3151 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3152 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3153}
3154
2850062a
AD		 3155/**
3156 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3157 * @netdev: network interface device structure
3158 *
3159 * Writes unicast address list to the RAR table.
3160 * Returns: -ENOMEM on failure/insufficient address space
3161 * 0 on no addresses written
3162 * X on writing X addresses to the RAR table
3163 **/
3164static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3165{
3166 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3167 struct ixgbe_hw *hw = &adapter->hw;
3168 unsigned int vfn = adapter->num_vfs;
3169 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3170 int count = 0;
3171
3172 /* return ENOMEM indicating insufficient memory for addresses */
3173 if (netdev_uc_count(netdev) > rar_entries)
3174 return -ENOMEM;
3175
3176 if (!netdev_uc_empty(netdev) && rar_entries) {
3177 struct netdev_hw_addr *ha;
3178 /* return error if we do not support writing to RAR table */
3179 if (!hw->mac.ops.set_rar)
3180 return -ENOMEM;
3181
3182 netdev_for_each_uc_addr(ha, netdev) {
3183 if (!rar_entries)
3184 break;
3185 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3186 vfn, IXGBE_RAH_AV);
3187 count++;
3188 }
3189 }
3190 /* write the addresses in reverse order to avoid write combining */
3191 for (; rar_entries > 0 ; rar_entries--)
3192 hw->mac.ops.clear_rar(hw, rar_entries);
3193
3194 return count;
3195}
3196
9a799d71 3197/**
2c5645cf 3198 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3199 * @netdev: network interface device structure
3200 *
2c5645cf
CL		 3201 * The set_rx_method entry point is called whenever the unicast/multicast
3202 * address list or the network interface flags are updated. This routine is
3203 * responsible for configuring the hardware for proper unicast, multicast and
3204 * promiscuous mode.
9a799d71 3205 **/
7f870475 3206void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3207{
3208 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3209 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3210 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3211 int count;
9a799d71
AK		 3212
3213 /* Check for Promiscuous and All Multicast modes */
3214
3215 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3216
f5dc442b
AD		 3217 /* set all bits that we expect to always be set */
3218 fctrl |= IXGBE_FCTRL_BAM;
3219 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3220 fctrl |= IXGBE_FCTRL_PMCF;
3221
2850062a
AD		 3222 /* clear the bits we are changing the status of */
3223 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3224
9a799d71 3225 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3226 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3227 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3228 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3229 /* don't hardware filter vlans in promisc mode */
3230 ixgbe_vlan_filter_disable(adapter);
9a799d71 3231 } else {
746b9f02
PM		 3232 if (netdev->flags & IFF_ALLMULTI) {
3233 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3234 vmolr |= IXGBE_VMOLR_MPE;
3235 } else {
3236 /*
3237 * Write addresses to the MTA, if the attempt fails
3238 * then we should just turn on promiscous mode so
3239 * that we can at least receive multicast traffic
3240 */
3241 hw->mac.ops.update_mc_addr_list(hw, netdev);
3242 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3243 }
5f6c0181 3244 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3245 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3246 /*
3247 * Write addresses to available RAR registers, if there is not
3248 * sufficient space to store all the addresses then enable
3249 * unicast promiscous mode
3250 */
3251 count = ixgbe_write_uc_addr_list(netdev);
3252 if (count < 0) {
3253 fctrl |= IXGBE_FCTRL_UPE;
3254 vmolr |= IXGBE_VMOLR_ROPE;
3255 }
9a799d71
AK		 3256 }
3257
2850062a 3258 if (adapter->num_vfs) {
1cdd1ec8 3259 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3260 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3261 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3262 IXGBE_VMOLR_ROPE);
3263 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3264 }
3265
3266 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3267
3268 if (netdev->features & NETIF_F_HW_VLAN_RX)
3269 ixgbe_vlan_strip_enable(adapter);
3270 else
3271 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3272}
3273
021230d4
AV		 3274static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3275{
3276 int q_idx;
3277 struct ixgbe_q_vector *q_vector;
3278 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3279
3280 /* legacy and MSI only use one vector */
3281 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3282 q_vectors = 1;
3283
3284 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3285 struct napi_struct *napi;
7a921c93 3286 q_vector = adapter->q_vector[q_idx];
f0848276 3287 napi = &q_vector->napi;
91281fd3
AD		 3288 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3289 if (!q_vector->rxr_count || !q_vector->txr_count) {
3290 if (q_vector->txr_count == 1)
3291 napi->poll = &ixgbe_clean_txonly;
3292 else if (q_vector->rxr_count == 1)
3293 napi->poll = &ixgbe_clean_rxonly;
3294 }
3295 }
f0848276
JB		 3296
3297 napi_enable(napi);
021230d4
AV		 3298 }
3299}
3300
3301static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3302{
3303 int q_idx;
3304 struct ixgbe_q_vector *q_vector;
3305 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3306
3307 /* legacy and MSI only use one vector */
3308 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3309 q_vectors = 1;
3310
3311 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3312 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3313 napi_disable(&q_vector->napi);
3314 }
3315}
3316
7a6b6f51 3317#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3318/*
3319 * ixgbe_configure_dcb - Configure DCB hardware
3320 * @adapter: ixgbe adapter struct
3321 *
3322 * This is called by the driver on open to configure the DCB hardware.
3323 * This is also called by the gennetlink interface when reconfiguring
3324 * the DCB state.
3325 */
3326static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3327{
3328 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3329 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5f6c0181 3330 u32 txdctl;
2f90b865
AD		 3331 int i, j;
3332
67ebd791
AD		 3333 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3334 if (hw->mac.type == ixgbe_mac_82598EB)
3335 netif_set_gso_max_size(adapter->netdev, 65536);
3336 return;
3337 }
3338
3339 if (hw->mac.type == ixgbe_mac_82598EB)
3340 netif_set_gso_max_size(adapter->netdev, 32768);
3341
9806307a
JF		 3342#ifdef CONFIG_FCOE
3343 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3344 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3345#endif
3346
80ab193d 3347 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3348 DCB_TX_CONFIG);
80ab193d 3349 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3350 DCB_RX_CONFIG);
2f90b865
AD		 3351
3352 /* reconfigure the hardware */
3353 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3354
3355 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3356 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3357 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3358 /* PThresh workaround for Tx hang with DFP enabled. */
3359 txdctl |= 32;
3360 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3361 }
3362 /* Enable VLAN tag insert/strip */
f62bbb5e 3363 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3364
2f90b865
AD		 3365 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3366}
3367
3368#endif
9a799d71
AK		 3369static void ixgbe_configure(struct ixgbe_adapter *adapter)
3370{
3371 struct net_device *netdev = adapter->netdev;
c4cf55e5 3372 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3373 int i;
3374
7a6b6f51 3375#ifdef CONFIG_IXGBE_DCB
67ebd791 3376 ixgbe_configure_dcb(adapter);
2f90b865 3377#endif
9a799d71 3378
f62bbb5e
JG		 3379 ixgbe_set_rx_mode(netdev);
3380 ixgbe_restore_vlan(adapter);
3381
eacd73f7
YZ		 3382#ifdef IXGBE_FCOE
3383 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3384 ixgbe_configure_fcoe(adapter);
3385
3386#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3387 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3388 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3389 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3390 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3391 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3392 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3393 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3394 }
933d41f1 3395 ixgbe_configure_virtualization(adapter);
c4cf55e5 3396
9a799d71
AK		 3397 ixgbe_configure_tx(adapter);
3398 ixgbe_configure_rx(adapter);
9a799d71
AK		 3399}
3400
e8e26350
PW		 3401static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3402{
3403 switch (hw->phy.type) {
3404 case ixgbe_phy_sfp_avago:
3405 case ixgbe_phy_sfp_ftl:
3406 case ixgbe_phy_sfp_intel:
3407 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3408 case ixgbe_phy_sfp_passive_tyco:
3409 case ixgbe_phy_sfp_passive_unknown:
3410 case ixgbe_phy_sfp_active_unknown:
3411 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3412 return true;
3413 default:
3414 return false;
3415 }
3416}
3417
0ecc061d 3418/**
e8e26350
PW		 3419 * ixgbe_sfp_link_config - set up SFP+ link
3420 * @adapter: pointer to private adapter struct
3421 **/
3422static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3423{
3424 struct ixgbe_hw *hw = &adapter->hw;
3425
3426 if (hw->phy.multispeed_fiber) {
3427 /*
3428 * In multispeed fiber setups, the device may not have
3429 * had a physical connection when the driver loaded.
3430 * If that's the case, the initial link configuration
3431 * couldn't get the MAC into 10G or 1G mode, so we'll
3432 * never have a link status change interrupt fire.
3433 * We need to try and force an autonegotiation
3434 * session, then bring up link.
3435 */
3436 hw->mac.ops.setup_sfp(hw);
3437 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3438 schedule_work(&adapter->multispeed_fiber_task);
3439 } else {
3440 /*
3441 * Direct Attach Cu and non-multispeed fiber modules
3442 * still need to be configured properly prior to
3443 * attempting link.
3444 */
3445 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3446 schedule_work(&adapter->sfp_config_module_task);
3447 }
3448}
3449
3450/**
3451 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3452 * @hw: pointer to private hardware struct
3453 *
3454 * Returns 0 on success, negative on failure
3455 **/
e8e26350 3456static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3457{
3458 u32 autoneg;
8620a103 3459 bool negotiation, link_up = false;
0ecc061d
PWJ		 3460 u32 ret = IXGBE_ERR_LINK_SETUP;
3461
3462 if (hw->mac.ops.check_link)
3463 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3464
3465 if (ret)
3466 goto link_cfg_out;
3467
3468 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3469 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3470 &negotiation);
0ecc061d
PWJ		 3471 if (ret)
3472 goto link_cfg_out;
3473
8620a103
MC		 3474 if (hw->mac.ops.setup_link)
3475 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3476link_cfg_out:
3477 return ret;
3478}
3479
a34bcfff 3480static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3481{
9a799d71 3482 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3483 u32 gpie = 0;
9a799d71 3484
9b471446 3485 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3486 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3487 IXGBE_GPIE_OCD;
3488 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3489 /*
3490 * use EIAM to auto-mask when MSI-X interrupt is asserted
3491 * this saves a register write for every interrupt
3492 */
3493 switch (hw->mac.type) {
3494 case ixgbe_mac_82598EB:
3495 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3496 break;
3497 default:
3498 case ixgbe_mac_82599EB:
3499 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3500 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3501 break;
3502 }
3503 } else {
021230d4
AV		 3504 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3505 * specifically only auto mask tx and rx interrupts */
3506 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3507 }
9a799d71 3508
a34bcfff
AD		 3509 /* XXX: to interrupt immediately for EICS writes, enable this */
3510 /* gpie |= IXGBE_GPIE_EIMEN; */
3511
3512 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3513 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3514 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3515 }
3516
a34bcfff
AD		 3517 /* Enable fan failure interrupt */
3518 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3519 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3520
a34bcfff 3521 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3522 gpie |= IXGBE_SDP1_GPIEN;
3523 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3524
3525 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3526}
3527
3528static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3529{
3530 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3531 int err;
a34bcfff
AD		 3532 u32 ctrl_ext;
3533
3534 ixgbe_get_hw_control(adapter);
3535 ixgbe_setup_gpie(adapter);
e8e26350 3536
9a799d71
AK		 3537 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3538 ixgbe_configure_msix(adapter);
3539 else
3540 ixgbe_configure_msi_and_legacy(adapter);
3541
61fac744
PW		 3542 /* enable the optics */
3543 if (hw->phy.multispeed_fiber)
3544 hw->mac.ops.enable_tx_laser(hw);
3545
9a799d71 3546 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3547 ixgbe_napi_enable_all(adapter);
3548
3549 /* clear any pending interrupts, may auto mask */
3550 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3551 ixgbe_irq_enable(adapter, true, true);
9a799d71 3552
bf069c97
DS		 3553 /*
3554 * If this adapter has a fan, check to see if we had a failure
3555 * before we enabled the interrupt.
3556 */
3557 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3558 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3559 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3560 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3561 }
3562
e8e26350
PW		 3563 /*
3564 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3565 * arrived before interrupts were enabled but after probe. Such
3566 * devices wouldn't have their type identified yet. We need to
3567 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3568 * If we're not hot-pluggable SFP+, we just need to configure link
3569 * and bring it up.
3570 */
19343de2
DS		 3571 if (hw->phy.type == ixgbe_phy_unknown) {
3572 err = hw->phy.ops.identify(hw);
3573 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3574 /*
3575 * Take the device down and schedule the sfp tasklet
3576 * which will unregister_netdev and log it.
3577 */
19343de2 3578 ixgbe_down(adapter);
5da43c1a 3579 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3580 return err;
3581 }
e8e26350
PW		 3582 }
3583
3584 if (ixgbe_is_sfp(hw)) {
3585 ixgbe_sfp_link_config(adapter);
3586 } else {
3587 err = ixgbe_non_sfp_link_config(hw);
3588 if (err)
396e799c 3589 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3590 }
0ecc061d 3591
1da100bb 3592 /* enable transmits */
477de6ed 3593 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3594
9a799d71
AK		 3595 /* bring the link up in the watchdog, this could race with our first
3596 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3597 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3598 adapter->link_check_timeout = jiffies;
9a799d71 3599 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3600
3601 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3602 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3603 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3604 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3605
9a799d71
AK		 3606 return 0;
3607}
3608
d4f80882
AV		 3609void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3610{
3611 WARN_ON(in_interrupt());
3612 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3613 msleep(1);
3614 ixgbe_down(adapter);
5809a1ae
GR		 3615 /*
3616 * If SR-IOV enabled then wait a bit before bringing the adapter
3617 * back up to give the VFs time to respond to the reset. The
3618 * two second wait is based upon the watchdog timer cycle in
3619 * the VF driver.
3620 */
3621 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3622 msleep(2000);
d4f80882
AV		 3623 ixgbe_up(adapter);
3624 clear_bit(__IXGBE_RESETTING, &adapter->state);
3625}
3626
9a799d71
AK		 3627int ixgbe_up(struct ixgbe_adapter *adapter)
3628{
3629 /* hardware has been reset, we need to reload some things */
3630 ixgbe_configure(adapter);
3631
3632 return ixgbe_up_complete(adapter);
3633}
3634
3635void ixgbe_reset(struct ixgbe_adapter *adapter)
3636{
c44ade9e 3637 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3638 int err;
3639
3640 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3641 switch (err) {
3642 case 0:
3643 case IXGBE_ERR_SFP_NOT_PRESENT:
3644 break;
3645 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3646 e_dev_err("master disable timed out\n");
da4dd0f7 3647 break;
794caeb2
PWJ		 3648 case IXGBE_ERR_EEPROM_VERSION:
3649 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3650 e_dev_warn("This device is a pre-production adapter/LOM. "
3651 "Please be aware there may be issuesassociated with "
3652 "your hardware. If you are experiencing problems "
3653 "please contact your Intel or hardware "
3654 "representative who provided you with this "
3655 "hardware.\n");
794caeb2 3656 break;
da4dd0f7 3657 default:
849c4542 3658 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3659 }
9a799d71
AK		 3660
3661 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3662 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3663 IXGBE_RAH_AV);
9a799d71
AK		 3664}
3665
9a799d71
AK		 3666/**
3667 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3668 * @adapter: board private structure
3669 * @rx_ring: ring to free buffers from
3670 **/
3671static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3672 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3673{
3674 struct pci_dev *pdev = adapter->pdev;
3675 unsigned long size;
3676 unsigned int i;
3677
84418e3b
AD		 3678 /* ring already cleared, nothing to do */
3679 if (!rx_ring->rx_buffer_info)
3680 return;
9a799d71 3681
84418e3b 3682 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3683 for (i = 0; i < rx_ring->count; i++) {
3684 struct ixgbe_rx_buffer *rx_buffer_info;
3685
3686 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3687 if (rx_buffer_info->dma) {
1b507730 3688 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
e8e9f696 3689 rx_ring->rx_buf_len,
1b507730 3690 DMA_FROM_DEVICE);
9a799d71
AK		 3691 rx_buffer_info->dma = 0;
3692 }
3693 if (rx_buffer_info->skb) {
f8212f97 3694 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3695 rx_buffer_info->skb = NULL;
f8212f97
AD		 3696 do {
3697 struct sk_buff *this = skb;
e8171aaa 3698 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3699 dma_unmap_single(&pdev->dev,
3700 IXGBE_RSC_CB(this)->dma,
e8e9f696 3701 rx_ring->rx_buf_len,
1b507730 3702 DMA_FROM_DEVICE);
fd3686a8 3703 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3704 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3705 }
f8212f97
AD		 3706 skb = skb->prev;
3707 dev_kfree_skb(this);
3708 } while (skb);
9a799d71
AK		 3709 }
3710 if (!rx_buffer_info->page)
3711 continue;
4f57ca6e 3712 if (rx_buffer_info->page_dma) {
1b507730
NN		 3713 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3714 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3715 rx_buffer_info->page_dma = 0;
3716 }
9a799d71
AK		 3717 put_page(rx_buffer_info->page);
3718 rx_buffer_info->page = NULL;
762f4c57 3719 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3720 }
3721
3722 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3723 memset(rx_ring->rx_buffer_info, 0, size);
3724
3725 /* Zero out the descriptor ring */
3726 memset(rx_ring->desc, 0, rx_ring->size);
3727
3728 rx_ring->next_to_clean = 0;
3729 rx_ring->next_to_use = 0;
3730
9891ca7c
JB		 3731 if (rx_ring->head)
3732 writel(0, adapter->hw.hw_addr + rx_ring->head);
3733 if (rx_ring->tail)
3734 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3735}
3736
3737/**
3738 * ixgbe_clean_tx_ring - Free Tx Buffers
3739 * @adapter: board private structure
3740 * @tx_ring: ring to be cleaned
3741 **/
3742static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3743 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3744{
3745 struct ixgbe_tx_buffer *tx_buffer_info;
3746 unsigned long size;
3747 unsigned int i;
3748
84418e3b
AD		 3749 /* ring already cleared, nothing to do */
3750 if (!tx_ring->tx_buffer_info)
3751 return;
9a799d71 3752
84418e3b 3753 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3754 for (i = 0; i < tx_ring->count; i++) {
3755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3756 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3757 }
3758
3759 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3760 memset(tx_ring->tx_buffer_info, 0, size);
3761
3762 /* Zero out the descriptor ring */
3763 memset(tx_ring->desc, 0, tx_ring->size);
3764
3765 tx_ring->next_to_use = 0;
3766 tx_ring->next_to_clean = 0;
3767
9891ca7c
JB		 3768 if (tx_ring->head)
3769 writel(0, adapter->hw.hw_addr + tx_ring->head);
3770 if (tx_ring->tail)
3771 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3772}
3773
3774/**
021230d4 3775 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3776 * @adapter: board private structure
3777 **/
021230d4 3778static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3779{
3780 int i;
3781
021230d4 3782 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3783 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3784}
3785
3786/**
021230d4 3787 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3788 * @adapter: board private structure
3789 **/
021230d4 3790static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3791{
3792 int i;
3793
021230d4 3794 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3795 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3796}
3797
3798void ixgbe_down(struct ixgbe_adapter *adapter)
3799{
3800 struct net_device *netdev = adapter->netdev;
7f821875 3801 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3802 u32 rxctrl;
7f821875
JB		 3803 u32 txdctl;
3804 int i, j;
b25ebfd2 3805 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3806
3807 /* signal that we are down to the interrupt handler */
3808 set_bit(__IXGBE_DOWN, &adapter->state);
3809
767081ad
GR		 3810 /* disable receive for all VFs and wait one second */
3811 if (adapter->num_vfs) {
767081ad
GR		 3812 /* ping all the active vfs to let them know we are going down */
3813 ixgbe_ping_all_vfs(adapter);
581d1aa7 3814
767081ad
GR		 3815 /* Disable all VFTE/VFRE TX/RX */
3816 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3817
3818 /* Mark all the VFs as inactive */
3819 for (i = 0 ; i < adapter->num_vfs; i++)
3820 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3821 }
3822
9a799d71 3823 /* disable receives */
7f821875
JB		 3824 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3825 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3826
7f821875 3827 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3828 msleep(10);
3829
7f821875
JB		 3830 netif_tx_stop_all_queues(netdev);
3831
0a1f87cb
DS		 3832 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3833 del_timer_sync(&adapter->sfp_timer);
9a799d71 3834 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3835 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3836
c0dfb90e
JF		 3837 netif_carrier_off(netdev);
3838 netif_tx_disable(netdev);
3839
3840 ixgbe_irq_disable(adapter);
3841
3842 ixgbe_napi_disable_all(adapter);
3843
b25ebfd2
PW		 3844 /* Cleanup the affinity_hint CPU mask memory and callback */
3845 for (i = 0; i < num_q_vectors; i++) {
3846 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3847 /* clear the affinity_mask in the IRQ descriptor */
3848 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3849 /* release the CPU mask memory */
3850 free_cpumask_var(q_vector->affinity_mask);
3851 }
3852
c4cf55e5
PWJ		 3853 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3854 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3855 cancel_work_sync(&adapter->fdir_reinit_task);
3856
119fc60a
MC		 3857 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3858 cancel_work_sync(&adapter->check_overtemp_task);
3859
7f821875
JB		 3860 /* disable transmits in the hardware now that interrupts are off */
3861 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3862 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3863 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3864 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3865 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3866 }
88512539
PW		 3867 /* Disable the Tx DMA engine on 82599 */
3868 if (hw->mac.type == ixgbe_mac_82599EB)
3869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3870 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3871 ~IXGBE_DMATXCTL_TE));
7f821875 3872
9f756f01
JF		 3873 /* power down the optics */
3874 if (hw->phy.multispeed_fiber)
3875 hw->mac.ops.disable_tx_laser(hw);
3876
9a713e7c
PW		 3877 /* clear n-tuple filters that are cached */
3878 ethtool_ntuple_flush(netdev);
3879
6f4a0e45
PL		 3880 if (!pci_channel_offline(adapter->pdev))
3881 ixgbe_reset(adapter);
9a799d71
AK		 3882 ixgbe_clean_all_tx_rings(adapter);
3883 ixgbe_clean_all_rx_rings(adapter);
3884
5dd2d332 3885#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3886 /* since we reset the hardware DCA settings were cleared */
e35ec126 3887 ixgbe_setup_dca(adapter);
96b0e0f6 3888#endif
9a799d71
AK		 3889}
3890
9a799d71 3891/**
021230d4
AV		 3892 * ixgbe_poll - NAPI Rx polling callback
3893 * @napi: structure for representing this polling device
3894 * @budget: how many packets driver is allowed to clean
3895 *
3896 * This function is used for legacy and MSI, NAPI mode
9a799d71 3897 **/
021230d4 3898static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3899{
9a1a69ad 3900 struct ixgbe_q_vector *q_vector =
e8e9f696 3901 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3902 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3903 int tx_clean_complete, work_done = 0;
9a799d71 3904
5dd2d332 3905#ifdef CONFIG_IXGBE_DCA
bd0362dd 3906 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3907 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3908 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3909 }
3910#endif
3911
4a0b9ca0
PW		 3912 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3913 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3914
9a1a69ad 3915 if (!tx_clean_complete)
d2c7ddd6
DM		 3916 work_done = budget;
3917
53e52c72
DM		 3918 /* If budget not fully consumed, exit the polling mode */
3919 if (work_done < budget) {
288379f0 3920 napi_complete(napi);
f7554a2b 3921 if (adapter->rx_itr_setting & 1)
f494e8fa 3922 ixgbe_set_itr(adapter);
d4f80882 3923 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3924 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3925 }
9a799d71
AK		 3926 return work_done;
3927}
3928
3929/**
3930 * ixgbe_tx_timeout - Respond to a Tx Hang
3931 * @netdev: network interface device structure
3932 **/
3933static void ixgbe_tx_timeout(struct net_device *netdev)
3934{
3935 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3936
3937 /* Do the reset outside of interrupt context */
3938 schedule_work(&adapter->reset_task);
3939}
3940
3941static void ixgbe_reset_task(struct work_struct *work)
3942{
3943 struct ixgbe_adapter *adapter;
3944 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3945
2f90b865
AD		 3946 /* If we're already down or resetting, just bail */
3947 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3948 test_bit(__IXGBE_RESETTING, &adapter->state))
3949 return;
3950
9a799d71
AK		 3951 adapter->tx_timeout_count++;
3952
dcd79aeb
TI		 3953 ixgbe_dump(adapter);
3954 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3955 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3956}
3957
bc97114d
PWJ		 3958#ifdef CONFIG_IXGBE_DCB
3959static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3960{
bc97114d 3961 bool ret = false;
0cefafad 3962 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3963
0cefafad
JB		 3964 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3965 return ret;
3966
3967 f->mask = 0x7 << 3;
3968 adapter->num_rx_queues = f->indices;
3969 adapter->num_tx_queues = f->indices;
3970 ret = true;
2f90b865 3971
bc97114d
PWJ		 3972 return ret;
3973}
3974#endif
3975
4df10466
JB		 3976/**
3977 * ixgbe_set_rss_queues: Allocate queues for RSS
3978 * @adapter: board private structure to initialize
3979 *
3980 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3981 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3982 *
3983 **/
bc97114d
PWJ		 3984static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3985{
3986 bool ret = false;
0cefafad 3987 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3988
3989 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3990 f->mask = 0xF;
3991 adapter->num_rx_queues = f->indices;
3992 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3993 ret = true;
3994 } else {
bc97114d 3995 ret = false;
b9804972
JB		 3996 }
3997
bc97114d
PWJ		 3998 return ret;
3999}
4000
c4cf55e5
PWJ		 4001/**
4002 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4003 * @adapter: board private structure to initialize
4004 *
4005 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4006 * to the original CPU that initiated the Tx session. This runs in addition
4007 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4008 * Rx load across CPUs using RSS.
4009 *
4010 **/
e8e9f696 4011static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4012{
4013 bool ret = false;
4014 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4015
4016 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4017 f_fdir->mask = 0;
4018
4019 /* Flow Director must have RSS enabled */
4020 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4021 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4022 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4023 adapter->num_tx_queues = f_fdir->indices;
4024 adapter->num_rx_queues = f_fdir->indices;
4025 ret = true;
4026 } else {
4027 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4028 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4029 }
4030 return ret;
4031}
4032
0331a832
YZ		 4033#ifdef IXGBE_FCOE
4034/**
4035 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4036 * @adapter: board private structure to initialize
4037 *
4038 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4039 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4040 * rx queues out of the max number of rx queues, instead, it is used as the
4041 * index of the first rx queue used by FCoE.
4042 *
4043 **/
4044static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4045{
4046 bool ret = false;
4047 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4048
4049 f->indices = min((int)num_online_cpus(), f->indices);
4050 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4051 adapter->num_rx_queues = 1;
4052 adapter->num_tx_queues = 1;
0331a832
YZ		 4053#ifdef CONFIG_IXGBE_DCB
4054 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4055 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4056 ixgbe_set_dcb_queues(adapter);
4057 }
4058#endif
4059 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4060 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4061 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4062 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4063 ixgbe_set_fdir_queues(adapter);
4064 else
4065 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4066 }
4067 /* adding FCoE rx rings to the end */
4068 f->mask = adapter->num_rx_queues;
4069 adapter->num_rx_queues += f->indices;
8de8b2e6 4070 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4071
4072 ret = true;
4073 }
4074
4075 return ret;
4076}
4077
4078#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4079/**
4080 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4081 * @adapter: board private structure to initialize
4082 *
4083 * IOV doesn't actually use anything, so just NAK the
4084 * request for now and let the other queue routines
4085 * figure out what to do.
4086 */
4087static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4088{
4089 return false;
4090}
4091
4df10466
JB		 4092/*
4093 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4094 * @adapter: board private structure to initialize
4095 *
4096 * This is the top level queue allocation routine. The order here is very
4097 * important, starting with the "most" number of features turned on at once,
4098 * and ending with the smallest set of features. This way large combinations
4099 * can be allocated if they're turned on, and smaller combinations are the
4100 * fallthrough conditions.
4101 *
4102 **/
847f53ff 4103static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4104{
1cdd1ec8
GR		 4105 /* Start with base case */
4106 adapter->num_rx_queues = 1;
4107 adapter->num_tx_queues = 1;
4108 adapter->num_rx_pools = adapter->num_rx_queues;
4109 adapter->num_rx_queues_per_pool = 1;
4110
4111 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4112 goto done;
1cdd1ec8 4113
0331a832
YZ		 4114#ifdef IXGBE_FCOE
4115 if (ixgbe_set_fcoe_queues(adapter))
4116 goto done;
4117
4118#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4119#ifdef CONFIG_IXGBE_DCB
4120 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4121 goto done;
bc97114d
PWJ		 4122
4123#endif
c4cf55e5
PWJ		 4124 if (ixgbe_set_fdir_queues(adapter))
4125 goto done;
4126
bc97114d 4127 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4128 goto done;
4129
4130 /* fallback to base case */
4131 adapter->num_rx_queues = 1;
4132 adapter->num_tx_queues = 1;
4133
4134done:
847f53ff 4135 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4136 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4137 return netif_set_real_num_rx_queues(adapter->netdev,
4138 adapter->num_rx_queues);
b9804972
JB		 4139}
4140
021230d4 4141static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4142 int vectors)
021230d4
AV		 4143{
4144 int err, vector_threshold;
4145
4146 /* We'll want at least 3 (vector_threshold):
4147 * 1) TxQ[0] Cleanup
4148 * 2) RxQ[0] Cleanup
4149 * 3) Other (Link Status Change, etc.)
4150 * 4) TCP Timer (optional)
4151 */
4152 vector_threshold = MIN_MSIX_COUNT;
4153
4154 /* The more we get, the more we will assign to Tx/Rx Cleanup
4155 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4156 * Right now, we simply care about how many we'll get; we'll
4157 * set them up later while requesting irq's.
4158 */
4159 while (vectors >= vector_threshold) {
4160 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4161 vectors);
021230d4
AV		 4162 if (!err) /* Success in acquiring all requested vectors. */
4163 break;
4164 else if (err < 0)
4165 vectors = 0; /* Nasty failure, quit now */
4166 else /* err == number of vectors we should try again with */
4167 vectors = err;
4168 }
4169
4170 if (vectors < vector_threshold) {
4171 /* Can't allocate enough MSI-X interrupts? Oh well.
4172 * This just means we'll go with either a single MSI
4173 * vector or fall back to legacy interrupts.
4174 */
849c4542
ET		 4175 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4176 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4178 kfree(adapter->msix_entries);
4179 adapter->msix_entries = NULL;
021230d4
AV		 4180 } else {
4181 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4182 /*
4183 * Adjust for only the vectors we'll use, which is minimum
4184 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4185 * vectors we were allocated.
4186 */
4187 adapter->num_msix_vectors = min(vectors,
e8e9f696 4188 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4189 }
4190}
4191
021230d4 4192/**
bc97114d 4193 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4194 * @adapter: board private structure to initialize
4195 *
bc97114d
PWJ		 4196 * Cache the descriptor ring offsets for RSS to the assigned rings.
4197 *
021230d4 4198 **/
bc97114d 4199static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4200{
bc97114d
PWJ		 4201 int i;
4202 bool ret = false;
4203
4204 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4205 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4206 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4207 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4208 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4209 ret = true;
4210 } else {
4211 ret = false;
4212 }
4213
4214 return ret;
4215}
4216
4217#ifdef CONFIG_IXGBE_DCB
4218/**
4219 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4220 * @adapter: board private structure to initialize
4221 *
4222 * Cache the descriptor ring offsets for DCB to the assigned rings.
4223 *
4224 **/
4225static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4226{
4227 int i;
4228 bool ret = false;
4229 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4230
4231 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4232 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4233 /* the number of queues is assumed to be symmetric */
4234 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4235 adapter->rx_ring[i]->reg_idx = i << 3;
4236 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4237 }
bc97114d 4238 ret = true;
e8e26350 4239 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4240 if (dcb_i == 8) {
4241 /*
4242 * Tx TC0 starts at: descriptor queue 0
4243 * Tx TC1 starts at: descriptor queue 32
4244 * Tx TC2 starts at: descriptor queue 64
4245 * Tx TC3 starts at: descriptor queue 80
4246 * Tx TC4 starts at: descriptor queue 96
4247 * Tx TC5 starts at: descriptor queue 104
4248 * Tx TC6 starts at: descriptor queue 112
4249 * Tx TC7 starts at: descriptor queue 120
4250 *
4251 * Rx TC0-TC7 are offset by 16 queues each
4252 */
4253 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4254 adapter->tx_ring[i]->reg_idx = i << 5;
4255 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4256 }
4257 for ( ; i < 5; i++) {
4a0b9ca0 4258 adapter->tx_ring[i]->reg_idx =
e8e9f696 4259 ((i + 2) << 4);
4a0b9ca0 4260 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4261 }
4262 for ( ; i < dcb_i; i++) {
4a0b9ca0 4263 adapter->tx_ring[i]->reg_idx =
e8e9f696 4264 ((i + 8) << 3);
4a0b9ca0 4265 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4266 }
4267
4268 ret = true;
4269 } else if (dcb_i == 4) {
4270 /*
4271 * Tx TC0 starts at: descriptor queue 0
4272 * Tx TC1 starts at: descriptor queue 64
4273 * Tx TC2 starts at: descriptor queue 96
4274 * Tx TC3 starts at: descriptor queue 112
4275 *
4276 * Rx TC0-TC3 are offset by 32 queues each
4277 */
4a0b9ca0
PW		 4278 adapter->tx_ring[0]->reg_idx = 0;
4279 adapter->tx_ring[1]->reg_idx = 64;
4280 adapter->tx_ring[2]->reg_idx = 96;
4281 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4282 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4283 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4284
4285 ret = true;
4286 } else {
4287 ret = false;
e8e26350 4288 }
bc97114d
PWJ		 4289 } else {
4290 ret = false;
021230d4 4291 }
bc97114d
PWJ		 4292 } else {
4293 ret = false;
021230d4 4294 }
bc97114d
PWJ		 4295
4296 return ret;
4297}
4298#endif
4299
c4cf55e5
PWJ		 4300/**
4301 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4302 * @adapter: board private structure to initialize
4303 *
4304 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4305 *
4306 **/
e8e9f696 4307static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4308{
4309 int i;
4310 bool ret = false;
4311
4312 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4313 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4314 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4315 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4316 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4317 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4318 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4319 ret = true;
4320 }
4321
4322 return ret;
4323}
4324
0331a832
YZ		 4325#ifdef IXGBE_FCOE
4326/**
4327 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4328 * @adapter: board private structure to initialize
4329 *
4330 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4331 *
4332 */
4333static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4334{
8de8b2e6 4335 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4336 bool ret = false;
4337 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4338
4339 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4340#ifdef CONFIG_IXGBE_DCB
4341 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4342 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4343
0331a832 4344 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4345 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4346 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4347 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4348 /*
4349 * In 82599, the number of Tx queues for each traffic
4350 * class for both 8-TC and 4-TC modes are:
4351 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4352 * 8 TCs: 32 32 16 16 8 8 8 8
4353 * 4 TCs: 64 64 32 32
4354 * We have max 8 queues for FCoE, where 8 the is
4355 * FCoE redirection table size. If TC for FCoE is
4356 * less than or equal to TC3, we have enough queues
4357 * to add max of 8 queues for FCoE, so we start FCoE
4358 * tx descriptor from the next one, i.e., reg_idx + 1.
4359 * If TC for FCoE is above TC3, implying 8 TC mode,
4360 * and we need 8 for FCoE, we have to take all queues
4361 * in that traffic class for FCoE.
4362 */
4363 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4364 fcoe_tx_i--;
0331a832
YZ		 4365 }
4366#endif /* CONFIG_IXGBE_DCB */
4367 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4368 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4369 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4370 ixgbe_cache_ring_fdir(adapter);
4371 else
4372 ixgbe_cache_ring_rss(adapter);
4373
8de8b2e6
YZ		 4374 fcoe_rx_i = f->mask;
4375 fcoe_tx_i = f->mask;
4376 }
4377 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4378 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4379 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4380 }
0331a832
YZ		 4381 ret = true;
4382 }
4383 return ret;
4384}
4385
4386#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4387/**
4388 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4389 * @adapter: board private structure to initialize
4390 *
4391 * SR-IOV doesn't use any descriptor rings but changes the default if
4392 * no other mapping is used.
4393 *
4394 */
4395static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4396{
4a0b9ca0
PW		 4397 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4398 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4399 if (adapter->num_vfs)
4400 return true;
4401 else
4402 return false;
4403}
4404
bc97114d
PWJ		 4405/**
4406 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4407 * @adapter: board private structure to initialize
4408 *
4409 * Once we know the feature-set enabled for the device, we'll cache
4410 * the register offset the descriptor ring is assigned to.
4411 *
4412 * Note, the order the various feature calls is important. It must start with
4413 * the "most" features enabled at the same time, then trickle down to the
4414 * least amount of features turned on at once.
4415 **/
4416static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4417{
4418 /* start with default case */
4a0b9ca0
PW		 4419 adapter->rx_ring[0]->reg_idx = 0;
4420 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4421
1cdd1ec8
GR		 4422 if (ixgbe_cache_ring_sriov(adapter))
4423 return;
4424
0331a832
YZ		 4425#ifdef IXGBE_FCOE
4426 if (ixgbe_cache_ring_fcoe(adapter))
4427 return;
4428
4429#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4430#ifdef CONFIG_IXGBE_DCB
4431 if (ixgbe_cache_ring_dcb(adapter))
4432 return;
4433
4434#endif
c4cf55e5
PWJ		 4435 if (ixgbe_cache_ring_fdir(adapter))
4436 return;
4437
bc97114d
PWJ		 4438 if (ixgbe_cache_ring_rss(adapter))
4439 return;
021230d4
AV		 4440}
4441
9a799d71
AK		 4442/**
4443 * ixgbe_alloc_queues - Allocate memory for all rings
4444 * @adapter: board private structure to initialize
4445 *
4446 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4447 * number of queues at compile-time. The polling_netdev array is
4448 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4449 **/
2f90b865 4450static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4451{
4452 int i;
4a0b9ca0 4453 int orig_node = adapter->node;
9a799d71 4454
021230d4 4455 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4456 struct ixgbe_ring *ring = adapter->tx_ring[i];
4457 if (orig_node == -1) {
4458 int cur_node = next_online_node(adapter->node);
4459 if (cur_node == MAX_NUMNODES)
4460 cur_node = first_online_node;
4461 adapter->node = cur_node;
4462 }
4463 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4464 adapter->node);
4a0b9ca0
PW		 4465 if (!ring)
4466 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4467 if (!ring)
4468 goto err_tx_ring_allocation;
4469 ring->count = adapter->tx_ring_count;
4470 ring->queue_index = i;
4471 ring->numa_node = adapter->node;
4472
4473 adapter->tx_ring[i] = ring;
021230d4 4474 }
b9804972 4475
4a0b9ca0
PW		 4476 /* Restore the adapter's original node */
4477 adapter->node = orig_node;
4478
9a799d71 4479 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4480 struct ixgbe_ring *ring = adapter->rx_ring[i];
4481 if (orig_node == -1) {
4482 int cur_node = next_online_node(adapter->node);
4483 if (cur_node == MAX_NUMNODES)
4484 cur_node = first_online_node;
4485 adapter->node = cur_node;
4486 }
4487 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4488 adapter->node);
4a0b9ca0
PW		 4489 if (!ring)
4490 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4491 if (!ring)
4492 goto err_rx_ring_allocation;
4493 ring->count = adapter->rx_ring_count;
4494 ring->queue_index = i;
4495 ring->numa_node = adapter->node;
4496
4497 adapter->rx_ring[i] = ring;
021230d4
AV		 4498 }
4499
4a0b9ca0
PW		 4500 /* Restore the adapter's original node */
4501 adapter->node = orig_node;
4502
021230d4
AV		 4503 ixgbe_cache_ring_register(adapter);
4504
4505 return 0;
4506
4507err_rx_ring_allocation:
4a0b9ca0
PW		 4508 for (i = 0; i < adapter->num_tx_queues; i++)
4509 kfree(adapter->tx_ring[i]);
021230d4
AV		 4510err_tx_ring_allocation:
4511 return -ENOMEM;
4512}
4513
4514/**
4515 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4516 * @adapter: board private structure to initialize
4517 *
4518 * Attempt to configure the interrupts using the best available
4519 * capabilities of the hardware and the kernel.
4520 **/
feea6a57 4521static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4522{
8be0e467 4523 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4524 int err = 0;
4525 int vector, v_budget;
4526
4527 /*
4528 * It's easy to be greedy for MSI-X vectors, but it really
4529 * doesn't do us much good if we have a lot more vectors
4530 * than CPU's. So let's be conservative and only ask for
342bde1b 4531 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4532 */
4533 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4534 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4535
4536 /*
4537 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4538 * hw.mac->max_msix_vectors vectors. With features
4539 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4540 * descriptor queues supported by our device. Thus, we cap it off in
4541 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4542 */
8be0e467 4543 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4544
4545 /* A failure in MSI-X entry allocation isn't fatal, but it does
4546 * mean we disable MSI-X capabilities of the adapter. */
4547 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4548 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4549 if (adapter->msix_entries) {
4550 for (vector = 0; vector < v_budget; vector++)
4551 adapter->msix_entries[vector].entry = vector;
021230d4 4552
7a921c93 4553 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4554
7a921c93
AD		 4555 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4556 goto out;
4557 }
26d27844 4558
7a921c93
AD		 4559 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4560 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4561 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4562 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4563 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4564 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4565 ixgbe_disable_sriov(adapter);
4566
847f53ff
BH		 4567 err = ixgbe_set_num_queues(adapter);
4568 if (err)
4569 return err;
021230d4 4570
021230d4
AV		 4571 err = pci_enable_msi(adapter->pdev);
4572 if (!err) {
4573 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4574 } else {
849c4542
ET		 4575 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4576 "Unable to allocate MSI interrupt, "
4577 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4578 /* reset err */
4579 err = 0;
4580 }
4581
4582out:
021230d4
AV		 4583 return err;
4584}
4585
7a921c93
AD		 4586/**
4587 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4588 * @adapter: board private structure to initialize
4589 *
4590 * We allocate one q_vector per queue interrupt. If allocation fails we
4591 * return -ENOMEM.
4592 **/
4593static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4594{
4595 int q_idx, num_q_vectors;
4596 struct ixgbe_q_vector *q_vector;
4597 int napi_vectors;
4598 int (*poll)(struct napi_struct *, int);
4599
4600 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4601 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4602 napi_vectors = adapter->num_rx_queues;
91281fd3 4603 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4604 } else {
4605 num_q_vectors = 1;
4606 napi_vectors = 1;
4607 poll = &ixgbe_poll;
4608 }
4609
4610 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4611 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4612 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4613 if (!q_vector)
4614 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4615 GFP_KERNEL);
7a921c93
AD		 4616 if (!q_vector)
4617 goto err_out;
4618 q_vector->adapter = adapter;
f7554a2b
NS		 4619 if (q_vector->txr_count && !q_vector->rxr_count)
4620 q_vector->eitr = adapter->tx_eitr_param;
4621 else
4622 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4623 q_vector->v_idx = q_idx;
91281fd3 4624 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4625 adapter->q_vector[q_idx] = q_vector;
4626 }
4627
4628 return 0;
4629
4630err_out:
4631 while (q_idx) {
4632 q_idx--;
4633 q_vector = adapter->q_vector[q_idx];
4634 netif_napi_del(&q_vector->napi);
4635 kfree(q_vector);
4636 adapter->q_vector[q_idx] = NULL;
4637 }
4638 return -ENOMEM;
4639}
4640
4641/**
4642 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4643 * @adapter: board private structure to initialize
4644 *
4645 * This function frees the memory allocated to the q_vectors. In addition if
4646 * NAPI is enabled it will delete any references to the NAPI struct prior
4647 * to freeing the q_vector.
4648 **/
4649static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4650{
4651 int q_idx, num_q_vectors;
7a921c93 4652
91281fd3 4653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4654 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4655 else
7a921c93 4656 num_q_vectors = 1;
7a921c93
AD		 4657
4658 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4659 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4660 adapter->q_vector[q_idx] = NULL;
91281fd3 4661 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4662 kfree(q_vector);
4663 }
4664}
4665
7b25cdba 4666static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4667{
4668 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4669 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4670 pci_disable_msix(adapter->pdev);
4671 kfree(adapter->msix_entries);
4672 adapter->msix_entries = NULL;
4673 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4674 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4675 pci_disable_msi(adapter->pdev);
4676 }
021230d4
AV		 4677}
4678
4679/**
4680 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4681 * @adapter: board private structure to initialize
4682 *
4683 * We determine which interrupt scheme to use based on...
4684 * - Kernel support (MSI, MSI-X)
4685 * - which can be user-defined (via MODULE_PARAM)
4686 * - Hardware queue count (num_*_queues)
4687 * - defined by miscellaneous hardware support/features (RSS, etc.)
4688 **/
2f90b865 4689int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4690{
4691 int err;
4692
4693 /* Number of supported queues */
847f53ff
BH		 4694 err = ixgbe_set_num_queues(adapter);
4695 if (err)
4696 return err;
021230d4 4697
021230d4
AV		 4698 err = ixgbe_set_interrupt_capability(adapter);
4699 if (err) {
849c4542 4700 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4701 goto err_set_interrupt;
9a799d71
AK		 4702 }
4703
7a921c93
AD		 4704 err = ixgbe_alloc_q_vectors(adapter);
4705 if (err) {
849c4542 4706 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4707 goto err_alloc_q_vectors;
4708 }
4709
4710 err = ixgbe_alloc_queues(adapter);
4711 if (err) {
849c4542 4712 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4713 goto err_alloc_queues;
4714 }
4715
849c4542 4716 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4717 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4718 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4719
4720 set_bit(__IXGBE_DOWN, &adapter->state);
4721
9a799d71 4722 return 0;
021230d4 4723
7a921c93
AD		 4724err_alloc_queues:
4725 ixgbe_free_q_vectors(adapter);
4726err_alloc_q_vectors:
4727 ixgbe_reset_interrupt_capability(adapter);
021230d4 4728err_set_interrupt:
7a921c93
AD		 4729 return err;
4730}
4731
1a51502b
ED		 4732static void ring_free_rcu(struct rcu_head *head)
4733{
4734 kfree(container_of(head, struct ixgbe_ring, rcu));
4735}
4736
7a921c93
AD		 4737/**
4738 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4739 * @adapter: board private structure to clear interrupt scheme on
4740 *
4741 * We go through and clear interrupt specific resources and reset the structure
4742 * to pre-load conditions
4743 **/
4744void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4745{
4a0b9ca0
PW		 4746 int i;
4747
4748 for (i = 0; i < adapter->num_tx_queues; i++) {
4749 kfree(adapter->tx_ring[i]);
4750 adapter->tx_ring[i] = NULL;
4751 }
4752 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4753 struct ixgbe_ring *ring = adapter->rx_ring[i];
4754
4755 /* ixgbe_get_stats64() might access this ring, we must wait
4756 * a grace period before freeing it.
4757 */
4758 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 4759 adapter->rx_ring[i] = NULL;
4760 }
7a921c93
AD		 4761
4762 ixgbe_free_q_vectors(adapter);
4763 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4764}
4765
c4900be0
DS		 4766/**
4767 * ixgbe_sfp_timer - worker thread to find a missing module
4768 * @data: pointer to our adapter struct
4769 **/
4770static void ixgbe_sfp_timer(unsigned long data)
4771{
4772 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4773
4df10466
JB		 4774 /*
4775 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4776 * delays that sfp+ detection requires
4777 */
4778 schedule_work(&adapter->sfp_task);
4779}
4780
4781/**
4782 * ixgbe_sfp_task - worker thread to find a missing module
4783 * @work: pointer to work_struct containing our data
4784 **/
4785static void ixgbe_sfp_task(struct work_struct *work)
4786{
4787 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4788 struct ixgbe_adapter,
4789 sfp_task);
c4900be0
DS		 4790 struct ixgbe_hw *hw = &adapter->hw;
4791
4792 if ((hw->phy.type == ixgbe_phy_nl) &&
4793 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4794 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4795 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4796 goto reschedule;
4797 ret = hw->phy.ops.reset(hw);
4798 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4799 e_dev_err("failed to initialize because an unsupported "
4800 "SFP+ module type was detected.\n");
4801 e_dev_err("Reload the driver after installing a "
4802 "supported module.\n");
c4900be0
DS		 4803 unregister_netdev(adapter->netdev);
4804 } else {
396e799c 4805 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4806 }
4807 /* don't need this routine any more */
4808 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4809 }
4810 return;
4811reschedule:
4812 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4813 mod_timer(&adapter->sfp_timer,
e8e9f696 4814 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4815}
4816
9a799d71
AK		 4817/**
4818 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4819 * @adapter: board private structure to initialize
4820 *
4821 * ixgbe_sw_init initializes the Adapter private data structure.
4822 * Fields are initialized based on PCI device information and
4823 * OS network device settings (MTU size).
4824 **/
4825static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4826{
4827 struct ixgbe_hw *hw = &adapter->hw;
4828 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4829 struct net_device *dev = adapter->netdev;
021230d4 4830 unsigned int rss;
7a6b6f51 4831#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4832 int j;
4833 struct tc_configuration *tc;
4834#endif
16b61beb 4835 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4836
c44ade9e
JB		 4837 /* PCI config space info */
4838
4839 hw->vendor_id = pdev->vendor;
4840 hw->device_id = pdev->device;
4841 hw->revision_id = pdev->revision;
4842 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4843 hw->subsystem_device_id = pdev->subsystem_device;
4844
021230d4
AV		 4845 /* Set capability flags */
4846 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4847 adapter->ring_feature[RING_F_RSS].indices = rss;
4848 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4849 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4850 if (hw->mac.type == ixgbe_mac_82598EB) {
4851 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4852 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4853 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4854 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4855 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4856 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4857 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4858 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4859 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4860 if (dev->features & NETIF_F_NTUPLE) {
4861 /* Flow Director perfect filter enabled */
4862 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4863 adapter->atr_sample_rate = 0;
4864 spin_lock_init(&adapter->fdir_perfect_lock);
4865 } else {
4866 /* Flow Director hash filters enabled */
4867 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4868 adapter->atr_sample_rate = 20;
4869 }
c4cf55e5 4870 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4871 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4872 adapter->fdir_pballoc = 0;
eacd73f7 4873#ifdef IXGBE_FCOE
0d551589
YZ		 4874 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4875 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4876 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4877#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4878 /* Default traffic class to use for FCoE */
4879 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4880 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4881#endif
eacd73f7 4882#endif /* IXGBE_FCOE */
f8212f97 4883 }
2f90b865 4884
7a6b6f51 4885#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4886 /* Configure DCB traffic classes */
4887 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4888 tc = &adapter->dcb_cfg.tc_config[j];
4889 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4890 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4891 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4892 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4893 tc->dcb_pfc = pfc_disabled;
4894 }
4895 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4896 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4897 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4898 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4899 adapter->dcb_cfg.round_robin_enable = false;
4900 adapter->dcb_set_bitmap = 0x00;
4901 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4902 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4903
4904#endif
9a799d71
AK		 4905
4906 /* default flow control settings */
cd7664f6 4907 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4908 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4909#ifdef CONFIG_DCB
4910 adapter->last_lfc_mode = hw->fc.current_mode;
4911#endif
16b61beb
JF		 4912 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4913 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 4914 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4915 hw->fc.send_xon = true;
71fd570b 4916 hw->fc.disable_fc_autoneg = false;
9a799d71 4917
30efa5a3 4918 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4919 adapter->rx_itr_setting = 1;
4920 adapter->rx_eitr_param = 20000;
4921 adapter->tx_itr_setting = 1;
4922 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4923
4924 /* set defaults for eitr in MegaBytes */
4925 adapter->eitr_low = 10;
4926 adapter->eitr_high = 20;
4927
4928 /* set default ring sizes */
4929 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4930 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4931
9a799d71 4932 /* initialize eeprom parameters */
c44ade9e 4933 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4934 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4935 return -EIO;
4936 }
4937
021230d4 4938 /* enable rx csum by default */
9a799d71
AK		 4939 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4940
1a6c14a2
JB		 4941 /* get assigned NUMA node */
4942 adapter->node = dev_to_node(&pdev->dev);
4943
9a799d71
AK		 4944 set_bit(__IXGBE_DOWN, &adapter->state);
4945
4946 return 0;
4947}
4948
4949/**
4950 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4951 * @adapter: board private structure
3a581073 4952 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4953 *
4954 * Return 0 on success, negative on failure
4955 **/
4956int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 4957 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4958{
4959 struct pci_dev *pdev = adapter->pdev;
4960 int size;
4961
3a581073 4962 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4963 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4964 if (!tx_ring->tx_buffer_info)
4965 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4966 if (!tx_ring->tx_buffer_info)
4967 goto err;
3a581073 4968 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4969
4970 /* round up to nearest 4K */
12207e49 4971 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4972 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4973
1b507730
NN		 4974 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4975 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4976 if (!tx_ring->desc)
4977 goto err;
9a799d71 4978
3a581073
JB		 4979 tx_ring->next_to_use = 0;
4980 tx_ring->next_to_clean = 0;
4981 tx_ring->work_limit = tx_ring->count;
9a799d71 4982 return 0;
e01c31a5
JB		 4983
4984err:
4985 vfree(tx_ring->tx_buffer_info);
4986 tx_ring->tx_buffer_info = NULL;
396e799c 4987 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4988 return -ENOMEM;
9a799d71
AK		 4989}
4990
69888674
AD		 4991/**
4992 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4993 * @adapter: board private structure
4994 *
4995 * If this function returns with an error, then it's possible one or
4996 * more of the rings is populated (while the rest are not). It is the
4997 * callers duty to clean those orphaned rings.
4998 *
4999 * Return 0 on success, negative on failure
5000 **/
5001static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5002{
5003 int i, err = 0;
5004
5005 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5006 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 5007 if (!err)
5008 continue;
396e799c 5009 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5010 break;
5011 }
5012
5013 return err;
5014}
5015
9a799d71
AK		 5016/**
5017 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5018 * @adapter: board private structure
3a581073 5019 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5020 *
5021 * Returns 0 on success, negative on failure
5022 **/
5023int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5024 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5025{
5026 struct pci_dev *pdev = adapter->pdev;
021230d4 5027 int size;
9a799d71 5028
3a581073 5029 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 5030 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5031 if (!rx_ring->rx_buffer_info)
5032 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 5033 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 5034 e_err(probe, "vmalloc allocation failed for the Rx "
5035 "descriptor ring\n");
177db6ff 5036 goto alloc_failed;
9a799d71 5037 }
3a581073 5038 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5039
9a799d71 5040 /* Round up to nearest 4K */
3a581073
JB		 5041 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5042 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5043
1b507730
NN		 5044 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5045 &rx_ring->dma, GFP_KERNEL);
9a799d71 5046
3a581073 5047 if (!rx_ring->desc) {
396e799c
ET		 5048 e_err(probe, "Memory allocation failed for the Rx "
5049 "descriptor ring\n");
3a581073 5050 vfree(rx_ring->rx_buffer_info);
177db6ff 5051 goto alloc_failed;
9a799d71
AK		 5052 }
5053
3a581073
JB		 5054 rx_ring->next_to_clean = 0;
5055 rx_ring->next_to_use = 0;
9a799d71
AK		 5056
5057 return 0;
177db6ff
MC		 5058
5059alloc_failed:
177db6ff 5060 return -ENOMEM;
9a799d71
AK		 5061}
5062
69888674
AD		 5063/**
5064 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5065 * @adapter: board private structure
5066 *
5067 * If this function returns with an error, then it's possible one or
5068 * more of the rings is populated (while the rest are not). It is the
5069 * callers duty to clean those orphaned rings.
5070 *
5071 * Return 0 on success, negative on failure
5072 **/
5073
5074static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5075{
5076 int i, err = 0;
5077
5078 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 5079 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 5080 if (!err)
5081 continue;
396e799c 5082 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5083 break;
5084 }
5085
5086 return err;
5087}
5088
9a799d71
AK		 5089/**
5090 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5091 * @adapter: board private structure
5092 * @tx_ring: Tx descriptor ring for a specific queue
5093 *
5094 * Free all transmit software resources
5095 **/
c431f97e 5096void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5097 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5098{
5099 struct pci_dev *pdev = adapter->pdev;
5100
5101 ixgbe_clean_tx_ring(adapter, tx_ring);
5102
5103 vfree(tx_ring->tx_buffer_info);
5104 tx_ring->tx_buffer_info = NULL;
5105
1b507730
NN		 5106 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5107 tx_ring->dma);
9a799d71
AK		 5108
5109 tx_ring->desc = NULL;
5110}
5111
5112/**
5113 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5114 * @adapter: board private structure
5115 *
5116 * Free all transmit software resources
5117 **/
5118static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5119{
5120 int i;
5121
5122 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5123 if (adapter->tx_ring[i]->desc)
5124 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5125}
5126
5127/**
b4617240 5128 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5129 * @adapter: board private structure
5130 * @rx_ring: ring to clean the resources from
5131 *
5132 * Free all receive software resources
5133 **/
c431f97e 5134void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5135 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5136{
5137 struct pci_dev *pdev = adapter->pdev;
5138
5139 ixgbe_clean_rx_ring(adapter, rx_ring);
5140
5141 vfree(rx_ring->rx_buffer_info);
5142 rx_ring->rx_buffer_info = NULL;
5143
1b507730
NN		 5144 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5145 rx_ring->dma);
9a799d71
AK		 5146
5147 rx_ring->desc = NULL;
5148}
5149
5150/**
5151 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5152 * @adapter: board private structure
5153 *
5154 * Free all receive software resources
5155 **/
5156static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5157{
5158 int i;
5159
5160 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5161 if (adapter->rx_ring[i]->desc)
5162 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5163}
5164
9a799d71
AK		 5165/**
5166 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5167 * @netdev: network interface device structure
5168 * @new_mtu: new value for maximum frame size
5169 *
5170 * Returns 0 on success, negative on failure
5171 **/
5172static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5173{
5174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5175 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5176 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5177
42c783c5
JB		 5178 /* MTU < 68 is an error and causes problems on some kernels */
5179 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5180 return -EINVAL;
5181
396e799c 5182 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5183 /* must set new MTU before calling down or up */
9a799d71
AK		 5184 netdev->mtu = new_mtu;
5185
16b61beb
JF		 5186 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5187 hw->fc.low_water = FC_LOW_WATER(max_frame);
5188
d4f80882
AV		 5189 if (netif_running(netdev))
5190 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5191
5192 return 0;
5193}
5194
5195/**
5196 * ixgbe_open - Called when a network interface is made active
5197 * @netdev: network interface device structure
5198 *
5199 * Returns 0 on success, negative value on failure
5200 *
5201 * The open entry point is called when a network interface is made
5202 * active by the system (IFF_UP). At this point all resources needed
5203 * for transmit and receive operations are allocated, the interrupt
5204 * handler is registered with the OS, the watchdog timer is started,
5205 * and the stack is notified that the interface is ready.
5206 **/
5207static int ixgbe_open(struct net_device *netdev)
5208{
5209 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5210 int err;
4bebfaa5
AK		 5211
5212 /* disallow open during test */
5213 if (test_bit(__IXGBE_TESTING, &adapter->state))
5214 return -EBUSY;
9a799d71 5215
54386467
JB		 5216 netif_carrier_off(netdev);
5217
9a799d71
AK		 5218 /* allocate transmit descriptors */
5219 err = ixgbe_setup_all_tx_resources(adapter);
5220 if (err)
5221 goto err_setup_tx;
5222
9a799d71
AK		 5223 /* allocate receive descriptors */
5224 err = ixgbe_setup_all_rx_resources(adapter);
5225 if (err)
5226 goto err_setup_rx;
5227
5228 ixgbe_configure(adapter);
5229
021230d4 5230 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5231 if (err)
5232 goto err_req_irq;
5233
9a799d71
AK		 5234 err = ixgbe_up_complete(adapter);
5235 if (err)
5236 goto err_up;
5237
d55b53ff
JK		 5238 netif_tx_start_all_queues(netdev);
5239
9a799d71
AK		 5240 return 0;
5241
5242err_up:
5eba3699 5243 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5244 ixgbe_free_irq(adapter);
5245err_req_irq:
9a799d71 5246err_setup_rx:
a20a1199 5247 ixgbe_free_all_rx_resources(adapter);
9a799d71 5248err_setup_tx:
a20a1199 5249 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5250 ixgbe_reset(adapter);
5251
5252 return err;
5253}
5254
5255/**
5256 * ixgbe_close - Disables a network interface
5257 * @netdev: network interface device structure
5258 *
5259 * Returns 0, this is not allowed to fail
5260 *
5261 * The close entry point is called when an interface is de-activated
5262 * by the OS. The hardware is still under the drivers control, but
5263 * needs to be disabled. A global MAC reset is issued to stop the
5264 * hardware, and all transmit and receive resources are freed.
5265 **/
5266static int ixgbe_close(struct net_device *netdev)
5267{
5268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5269
5270 ixgbe_down(adapter);
5271 ixgbe_free_irq(adapter);
5272
5273 ixgbe_free_all_tx_resources(adapter);
5274 ixgbe_free_all_rx_resources(adapter);
5275
5eba3699 5276 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5277
5278 return 0;
5279}
5280
b3c8b4ba
AD		 5281#ifdef CONFIG_PM
5282static int ixgbe_resume(struct pci_dev *pdev)
5283{
5284 struct net_device *netdev = pci_get_drvdata(pdev);
5285 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5286 u32 err;
5287
5288 pci_set_power_state(pdev, PCI_D0);
5289 pci_restore_state(pdev);
656ab817
DS		 5290 /*
5291 * pci_restore_state clears dev->state_saved so call
5292 * pci_save_state to restore it.
5293 */
5294 pci_save_state(pdev);
9ce77666 5295
5296 err = pci_enable_device_mem(pdev);
b3c8b4ba 5297 if (err) {
849c4542 5298 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5299 return err;
5300 }
5301 pci_set_master(pdev);
5302
dd4d8ca6 5303 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5304
5305 err = ixgbe_init_interrupt_scheme(adapter);
5306 if (err) {
849c4542 5307 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5308 return err;
5309 }
5310
b3c8b4ba
AD		 5311 ixgbe_reset(adapter);
5312
495dce12
WJP		 5313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5314
b3c8b4ba
AD		 5315 if (netif_running(netdev)) {
5316 err = ixgbe_open(adapter->netdev);
5317 if (err)
5318 return err;
5319 }
5320
5321 netif_device_attach(netdev);
5322
5323 return 0;
5324}
b3c8b4ba 5325#endif /* CONFIG_PM */
9d8d05ae
RW		 5326
5327static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5328{
5329 struct net_device *netdev = pci_get_drvdata(pdev);
5330 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5331 struct ixgbe_hw *hw = &adapter->hw;
5332 u32 ctrl, fctrl;
5333 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5334#ifdef CONFIG_PM
5335 int retval = 0;
5336#endif
5337
5338 netif_device_detach(netdev);
5339
5340 if (netif_running(netdev)) {
5341 ixgbe_down(adapter);
5342 ixgbe_free_irq(adapter);
5343 ixgbe_free_all_tx_resources(adapter);
5344 ixgbe_free_all_rx_resources(adapter);
5345 }
b3c8b4ba
AD		 5346
5347#ifdef CONFIG_PM
5348 retval = pci_save_state(pdev);
5349 if (retval)
5350 return retval;
4df10466 5351
b3c8b4ba 5352#endif
e8e26350
PW		 5353 if (wufc) {
5354 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5355
e8e26350
PW		 5356 /* turn on all-multi mode if wake on multicast is enabled */
5357 if (wufc & IXGBE_WUFC_MC) {
5358 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5359 fctrl |= IXGBE_FCTRL_MPE;
5360 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5361 }
5362
5363 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5364 ctrl |= IXGBE_CTRL_GIO_DIS;
5365 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5366
5367 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5368 } else {
5369 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5370 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5371 }
5372
dd4d8ca6
DS		 5373 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5374 pci_wake_from_d3(pdev, true);
5375 else
5376 pci_wake_from_d3(pdev, false);
b3c8b4ba 5377
9d8d05ae
RW		 5378 *enable_wake = !!wufc;
5379
fa378134
AG		 5380 ixgbe_clear_interrupt_scheme(adapter);
5381
b3c8b4ba
AD		 5382 ixgbe_release_hw_control(adapter);
5383
5384 pci_disable_device(pdev);
5385
9d8d05ae
RW		 5386 return 0;
5387}
5388
5389#ifdef CONFIG_PM
5390static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5391{
5392 int retval;
5393 bool wake;
5394
5395 retval = __ixgbe_shutdown(pdev, &wake);
5396 if (retval)
5397 return retval;
5398
5399 if (wake) {
5400 pci_prepare_to_sleep(pdev);
5401 } else {
5402 pci_wake_from_d3(pdev, false);
5403 pci_set_power_state(pdev, PCI_D3hot);
5404 }
b3c8b4ba
AD		 5405
5406 return 0;
5407}
9d8d05ae 5408#endif /* CONFIG_PM */
b3c8b4ba
AD		 5409
5410static void ixgbe_shutdown(struct pci_dev *pdev)
5411{
9d8d05ae
RW		 5412 bool wake;
5413
5414 __ixgbe_shutdown(pdev, &wake);
5415
5416 if (system_state == SYSTEM_POWER_OFF) {
5417 pci_wake_from_d3(pdev, wake);
5418 pci_set_power_state(pdev, PCI_D3hot);
5419 }
b3c8b4ba
AD		 5420}
5421
9a799d71
AK		 5422/**
5423 * ixgbe_update_stats - Update the board statistics counters.
5424 * @adapter: board private structure
5425 **/
5426void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5427{
2d86f139 5428 struct net_device *netdev = adapter->netdev;
9a799d71 5429 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5430 u64 total_mpc = 0;
5431 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5432 u64 non_eop_descs = 0, restart_queue = 0;
7ca647bd 5433 struct ixgbe_hw_stats *hwstats = &adapter->stats;
9a799d71 5434
d08935c2
DS		 5435 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5436 test_bit(__IXGBE_RESETTING, &adapter->state))
5437 return;
5438
94b982b2 5439 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5440 u64 rsc_count = 0;
94b982b2 5441 u64 rsc_flush = 0;
d51019a4
PW		 5442 for (i = 0; i < 16; i++)
5443 adapter->hw_rx_no_dma_resources +=
7ca647bd 5444 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5445 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5446 rsc_count += adapter->rx_ring[i]->rsc_count;
5447 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5448 }
5449 adapter->rsc_total_count = rsc_count;
5450 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5451 }
5452
7ca3bc58
JB		 5453 /* gather some stats to the adapter struct that are per queue */
5454 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5455 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5456 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5457
5458 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5459 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5460 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5461
7ca647bd 5462 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5463 for (i = 0; i < 8; i++) {
5464 /* for packet buffers not used, the register should read 0 */
5465 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5466 missed_rx += mpc;
7ca647bd
JP		 5467 hwstats->mpc[i] += mpc;
5468 total_mpc += hwstats->mpc[i];
e8e26350 5469 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5470 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5471 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5472 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5473 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5474 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350 5475 if (hw->mac.type == ixgbe_mac_82599EB) {
7ca647bd
JP		 5476 hwstats->pxonrxc[i] +=
5477 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5478 hwstats->pxoffrxc[i] +=
5479 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5480 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350 5481 } else {
7ca647bd
JP		 5482 hwstats->pxonrxc[i] +=
5483 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5484 hwstats->pxoffrxc[i] +=
5485 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
e8e26350 5486 }
7ca647bd
JP		 5487 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5488 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5489 }
7ca647bd 5490 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5491 /* work around hardware counting issue */
7ca647bd 5492 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5493
5494 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5495 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5496 u64 tmp;
7ca647bd 5497 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5498 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5499 /* 4 high bits of GORC */
7ca647bd
JP		 5500 hwstats->gorc += (tmp << 32);
5501 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5502 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5503 /* 4 high bits of GOTC */
7ca647bd
JP		 5504 hwstats->gotc += (tmp << 32);
5505 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5506 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5507 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5508 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5509 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5510 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5511#ifdef IXGBE_FCOE
7ca647bd
JP		 5512 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5513 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5514 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5515 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5516 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5517 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5518#endif /* IXGBE_FCOE */
e8e26350 5519 } else {
7ca647bd
JP		 5520 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5521 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5522 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5523 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5524 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
e8e26350 5525 }
9a799d71 5526 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5527 hwstats->bprc += bprc;
5528 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5529 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5530 hwstats->mprc -= bprc;
5531 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5532 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5533 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5534 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5535 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5536 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5537 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5538 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5539 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5540 hwstats->lxontxc += lxon;
6f11eef7 5541 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5542 hwstats->lxofftxc += lxoff;
5543 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5544 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5545 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5546 /*
5547 * 82598 errata - tx of flow control packets is included in tx counters
5548 */
5549 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5550 hwstats->gptc -= xon_off_tot;
5551 hwstats->mptc -= xon_off_tot;
5552 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5553 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5554 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5555 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5556 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5557 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5558 hwstats->ptc64 -= xon_off_tot;
5559 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5560 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5561 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5562 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5563 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5564 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5565
5566 /* Fill out the OS statistics structure */
7ca647bd 5567 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5568
5569 /* Rx Errors */
7ca647bd 5570 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5571 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5572 netdev->stats.rx_length_errors = hwstats->rlec;
5573 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5574 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5575}
5576
5577/**
5578 * ixgbe_watchdog - Timer Call-back
5579 * @data: pointer to adapter cast into an unsigned long
5580 **/
5581static void ixgbe_watchdog(unsigned long data)
5582{
5583 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5584 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5585 u64 eics = 0;
5586 int i;
cf8280ee 5587
fe49f04a
AD		 5588 /*
5589 * Do the watchdog outside of interrupt context due to the lovely
5590 * delays that some of the newer hardware requires
5591 */
22d5a71b 5592
fe49f04a
AD		 5593 if (test_bit(__IXGBE_DOWN, &adapter->state))
5594 goto watchdog_short_circuit;
22d5a71b 5595
fe49f04a
AD		 5596 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5597 /*
5598 * for legacy and MSI interrupts don't set any bits
5599 * that are enabled for EIAM, because this operation
5600 * would set *both* EIMS and EICS for any bit in EIAM
5601 */
5602 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5603 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5604 goto watchdog_reschedule;
5605 }
5606
5607 /* get one bit for every active tx/rx interrupt vector */
5608 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5609 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5610 if (qv->rxr_count || qv->txr_count)
5611 eics |= ((u64)1 << i);
cf8280ee 5612 }
9a799d71 5613
fe49f04a
AD		 5614 /* Cause software interrupt to ensure rx rings are cleaned */
5615 ixgbe_irq_rearm_queues(adapter, eics);
5616
5617watchdog_reschedule:
5618 /* Reset the timer */
5619 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5620
5621watchdog_short_circuit:
cf8280ee
JB		 5622 schedule_work(&adapter->watchdog_task);
5623}
5624
e8e26350
PW		 5625/**
5626 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5627 * @work: pointer to work_struct containing our data
5628 **/
5629static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5630{
5631 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5632 struct ixgbe_adapter,
5633 multispeed_fiber_task);
e8e26350
PW		 5634 struct ixgbe_hw *hw = &adapter->hw;
5635 u32 autoneg;
8620a103 5636 bool negotiation;
e8e26350
PW		 5637
5638 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5639 autoneg = hw->phy.autoneg_advertised;
5640 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5641 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5642 hw->mac.autotry_restart = false;
8620a103
MC		 5643 if (hw->mac.ops.setup_link)
5644 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5645 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5646 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5647}
5648
5649/**
5650 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5651 * @work: pointer to work_struct containing our data
5652 **/
5653static void ixgbe_sfp_config_module_task(struct work_struct *work)
5654{
5655 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5656 struct ixgbe_adapter,
5657 sfp_config_module_task);
e8e26350
PW		 5658 struct ixgbe_hw *hw = &adapter->hw;
5659 u32 err;
5660
5661 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5662
5663 /* Time for electrical oscillations to settle down */
5664 msleep(100);
e8e26350 5665 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5666
e8e26350 5667 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5668 e_dev_err("failed to initialize because an unsupported SFP+ "
5669 "module type was detected.\n");
5670 e_dev_err("Reload the driver after installing a supported "
5671 "module.\n");
63d6e1d8 5672 unregister_netdev(adapter->netdev);
e8e26350
PW		 5673 return;
5674 }
5675 hw->mac.ops.setup_sfp(hw);
5676
8d1c3c07 5677 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5678 /* This will also work for DA Twinax connections */
5679 schedule_work(&adapter->multispeed_fiber_task);
5680 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5681}
5682
c4cf55e5
PWJ		 5683/**
5684 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5685 * @work: pointer to work_struct containing our data
5686 **/
5687static void ixgbe_fdir_reinit_task(struct work_struct *work)
5688{
5689 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5690 struct ixgbe_adapter,
5691 fdir_reinit_task);
c4cf55e5
PWJ		 5692 struct ixgbe_hw *hw = &adapter->hw;
5693 int i;
5694
5695 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5696 for (i = 0; i < adapter->num_tx_queues; i++)
5697 set_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 5698 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5699 } else {
396e799c 5700 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5701 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5702 }
5703 /* Done FDIR Re-initialization, enable transmits */
5704 netif_tx_start_all_queues(adapter->netdev);
5705}
5706
10eec955
JF		 5707static DEFINE_MUTEX(ixgbe_watchdog_lock);
5708
cf8280ee 5709/**
69888674
AD		 5710 * ixgbe_watchdog_task - worker thread to bring link up
5711 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5712 **/
5713static void ixgbe_watchdog_task(struct work_struct *work)
5714{
5715 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5716 struct ixgbe_adapter,
5717 watchdog_task);
cf8280ee
JB		 5718 struct net_device *netdev = adapter->netdev;
5719 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5720 u32 link_speed;
5721 bool link_up;
bc59fcda
NS		 5722 int i;
5723 struct ixgbe_ring *tx_ring;
5724 int some_tx_pending = 0;
cf8280ee 5725
10eec955
JF		 5726 mutex_lock(&ixgbe_watchdog_lock);
5727
5728 link_up = adapter->link_up;
5729 link_speed = adapter->link_speed;
cf8280ee
JB		 5730
5731 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5732 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5733 if (link_up) {
5734#ifdef CONFIG_DCB
5735 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5736 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5737 hw->mac.ops.fc_enable(hw, i);
264857b8 5738 } else {
620fa036 5739 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5740 }
5741#else
620fa036 5742 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5743#endif
5744 }
5745
cf8280ee
JB		 5746 if (link_up ||
5747 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5748 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5749 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5750 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5751 }
5752 adapter->link_up = link_up;
5753 adapter->link_speed = link_speed;
5754 }
9a799d71
AK		 5755
5756 if (link_up) {
5757 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5758 bool flow_rx, flow_tx;
5759
5760 if (hw->mac.type == ixgbe_mac_82599EB) {
5761 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5762 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5763 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5764 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5765 } else {
5766 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5767 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5768 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5769 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5770 }
5771
396e799c 5772 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5773 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5774 "10 Gbps" :
5775 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5776 "1 Gbps" : "unknown speed")),
e8e26350 5777 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5778 (flow_rx ? "RX" :
5779 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5780
5781 netif_carrier_on(netdev);
9a799d71
AK		 5782 } else {
5783 /* Force detection of hung controller */
5784 adapter->detect_tx_hung = true;
5785 }
5786 } else {
cf8280ee
JB		 5787 adapter->link_up = false;
5788 adapter->link_speed = 0;
9a799d71 5789 if (netif_carrier_ok(netdev)) {
396e799c 5790 e_info(drv, "NIC Link is Down\n");
9a799d71 5791 netif_carrier_off(netdev);
9a799d71
AK		 5792 }
5793 }
5794
bc59fcda
NS		 5795 if (!netif_carrier_ok(netdev)) {
5796 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5797 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5798 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5799 some_tx_pending = 1;
5800 break;
5801 }
5802 }
5803
5804 if (some_tx_pending) {
5805 /* We've lost link, so the controller stops DMA,
5806 * but we've got queued Tx work that's never going
5807 * to get done, so reset controller to flush Tx.
5808 * (Do the reset outside of interrupt context).
5809 */
5810 schedule_work(&adapter->reset_task);
5811 }
5812 }
5813
9a799d71 5814 ixgbe_update_stats(adapter);
10eec955 5815 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5816}
5817
9a799d71 5818static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 5819 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 5820 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 5821{
5822 struct ixgbe_adv_tx_context_desc *context_desc;
5823 unsigned int i;
5824 int err;
5825 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5826 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5827 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5828
5829 if (skb_is_gso(skb)) {
5830 if (skb_header_cloned(skb)) {
5831 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5832 if (err)
5833 return err;
5834 }
5835 l4len = tcp_hdrlen(skb);
5836 *hdr_len += l4len;
5837
5e09a105 5838 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5839 struct iphdr *iph = ip_hdr(skb);
5840 iph->tot_len = 0;
5841 iph->check = 0;
5842 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5843 iph->daddr, 0,
5844 IPPROTO_TCP,
5845 0);
8e1e8a47 5846 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5847 ipv6_hdr(skb)->payload_len = 0;
5848 tcp_hdr(skb)->check =
5849 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5850 &ipv6_hdr(skb)->daddr,
5851 0, IPPROTO_TCP, 0);
9a799d71
AK		 5852 }
5853
5854 i = tx_ring->next_to_use;
5855
5856 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5857 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5858
5859 /* VLAN MACLEN IPLEN */
5860 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5861 vlan_macip_lens |=
5862 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5863 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5864 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5865 *hdr_len += skb_network_offset(skb);
5866 vlan_macip_lens |=
5867 (skb_transport_header(skb) - skb_network_header(skb));
5868 *hdr_len +=
5869 (skb_transport_header(skb) - skb_network_header(skb));
5870 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5871 context_desc->seqnum_seed = 0;
5872
5873 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5874 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5875 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5876
5e09a105 5877 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 5878 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5879 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5880 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5881
5882 /* MSS L4LEN IDX */
9f8cdf4f 5883 mss_l4len_idx =
9a799d71
AK		 5884 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5885 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5886 /* use index 1 for TSO */
5887 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5888 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5889
5890 tx_buffer_info->time_stamp = jiffies;
5891 tx_buffer_info->next_to_watch = i;
5892
5893 i++;
5894 if (i == tx_ring->count)
5895 i = 0;
5896 tx_ring->next_to_use = i;
5897
5898 return true;
5899 }
5900 return false;
5901}
5902
5e09a105
HZ		 5903static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5904 __be16 protocol)
7ca647bd
JP		 5905{
5906 u32 rtn = 0;
7ca647bd
JP		 5907
5908 switch (protocol) {
5909 case cpu_to_be16(ETH_P_IP):
5910 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5911 switch (ip_hdr(skb)->protocol) {
5912 case IPPROTO_TCP:
5913 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5914 break;
5915 case IPPROTO_SCTP:
5916 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5917 break;
5918 }
5919 break;
5920 case cpu_to_be16(ETH_P_IPV6):
5921 /* XXX what about other V6 headers?? */
5922 switch (ipv6_hdr(skb)->nexthdr) {
5923 case IPPROTO_TCP:
5924 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5925 break;
5926 case IPPROTO_SCTP:
5927 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5928 break;
5929 }
5930 break;
5931 default:
5932 if (unlikely(net_ratelimit()))
5933 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 5934 protocol);
7ca647bd
JP		 5935 break;
5936 }
5937
5938 return rtn;
5939}
5940
9a799d71 5941static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 5942 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 5943 struct sk_buff *skb, u32 tx_flags,
5944 __be16 protocol)
9a799d71
AK		 5945{
5946 struct ixgbe_adv_tx_context_desc *context_desc;
5947 unsigned int i;
5948 struct ixgbe_tx_buffer *tx_buffer_info;
5949 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5950
5951 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5952 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5953 i = tx_ring->next_to_use;
5954 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5955 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5956
5957 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5958 vlan_macip_lens |=
5959 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5960 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 5961 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5962 if (skb->ip_summed == CHECKSUM_PARTIAL)
5963 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 5964 skb_network_header(skb));
9a799d71
AK		 5965
5966 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5967 context_desc->seqnum_seed = 0;
5968
5969 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 5970 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5971
7ca647bd 5972 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 5973 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 5974
5975 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5976 /* use index zero for tx checksum offload */
9a799d71
AK		 5977 context_desc->mss_l4len_idx = 0;
5978
5979 tx_buffer_info->time_stamp = jiffies;
5980 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5981
9a799d71
AK		 5982 i++;
5983 if (i == tx_ring->count)
5984 i = 0;
5985 tx_ring->next_to_use = i;
5986
5987 return true;
5988 }
9f8cdf4f 5989
9a799d71
AK		 5990 return false;
5991}
5992
5993static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5994 struct ixgbe_ring *tx_ring,
5995 struct sk_buff *skb, u32 tx_flags,
8ad494b0 5996 unsigned int first, const u8 hdr_len)
9a799d71 5997{
e5a43549 5998 struct pci_dev *pdev = adapter->pdev;
9a799d71 5999 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6000 unsigned int len;
6001 unsigned int total = skb->len;
9a799d71
AK		 6002 unsigned int offset = 0, size, count = 0, i;
6003 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6004 unsigned int f;
8ad494b0
AD		 6005 unsigned int bytecount = skb->len;
6006 u16 gso_segs = 1;
9a799d71
AK		 6007
6008 i = tx_ring->next_to_use;
6009
eacd73f7
YZ		 6010 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6011 /* excluding fcoe_crc_eof for FCoE */
6012 total -= sizeof(struct fcoe_crc_eof);
6013
6014 len = min(skb_headlen(skb), total);
9a799d71
AK		 6015 while (len) {
6016 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6017 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6018
6019 tx_buffer_info->length = size;
e5a43549 6020 tx_buffer_info->mapped_as_page = false;
1b507730 6021 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 6022 skb->data + offset,
1b507730
NN		 6023 size, DMA_TO_DEVICE);
6024 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6025 goto dma_error;
9a799d71
AK		 6026 tx_buffer_info->time_stamp = jiffies;
6027 tx_buffer_info->next_to_watch = i;
6028
6029 len -= size;
eacd73f7 6030 total -= size;
9a799d71
AK		 6031 offset += size;
6032 count++;
44df32c5
AD		 6033
6034 if (len) {
6035 i++;
6036 if (i == tx_ring->count)
6037 i = 0;
6038 }
9a799d71
AK		 6039 }
6040
6041 for (f = 0; f < nr_frags; f++) {
6042 struct skb_frag_struct *frag;
6043
6044 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6045 len = min((unsigned int)frag->size, total);
e5a43549 6046 offset = frag->page_offset;
9a799d71
AK		 6047
6048 while (len) {
44df32c5
AD		 6049 i++;
6050 if (i == tx_ring->count)
6051 i = 0;
6052
9a799d71
AK		 6053 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6054 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6055
6056 tx_buffer_info->length = size;
1b507730 6057 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 6058 frag->page,
6059 offset, size,
1b507730 6060 DMA_TO_DEVICE);
e5a43549 6061 tx_buffer_info->mapped_as_page = true;
1b507730 6062 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6063 goto dma_error;
9a799d71
AK		 6064 tx_buffer_info->time_stamp = jiffies;
6065 tx_buffer_info->next_to_watch = i;
6066
6067 len -= size;
eacd73f7 6068 total -= size;
9a799d71
AK		 6069 offset += size;
6070 count++;
9a799d71 6071 }
eacd73f7
YZ		 6072 if (total == 0)
6073 break;
9a799d71 6074 }
44df32c5 6075
8ad494b0
AD		 6076 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6077 gso_segs = skb_shinfo(skb)->gso_segs;
6078#ifdef IXGBE_FCOE
6079 /* adjust for FCoE Sequence Offload */
6080 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6081 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6082 skb_shinfo(skb)->gso_size);
6083#endif /* IXGBE_FCOE */
6084 bytecount += (gso_segs - 1) * hdr_len;
6085
6086 /* multiply data chunks by size of headers */
6087 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6088 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6089 tx_ring->tx_buffer_info[i].skb = skb;
6090 tx_ring->tx_buffer_info[first].next_to_watch = i;
6091
e5a43549
AD		 6092 return count;
6093
6094dma_error:
849c4542 6095 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6096
6097 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6098 tx_buffer_info->dma = 0;
6099 tx_buffer_info->time_stamp = 0;
6100 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6101 if (count)
6102 count--;
e5a43549
AD		 6103
6104 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6105 while (count--) {
e8e9f696 6106 if (i == 0)
e5a43549 6107 i += tx_ring->count;
c1fa347f 6108 i--;
e5a43549
AD		 6109 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6110 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6111 }
6112
e44d38e1 6113 return 0;
9a799d71
AK		 6114}
6115
6116static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6117 struct ixgbe_ring *tx_ring,
6118 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6119{
6120 union ixgbe_adv_tx_desc *tx_desc = NULL;
6121 struct ixgbe_tx_buffer *tx_buffer_info;
6122 u32 olinfo_status = 0, cmd_type_len = 0;
6123 unsigned int i;
6124 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6125
6126 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6127
6128 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6129
6130 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6131 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6132
6133 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6134 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6135
6136 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6137 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6138
4eeae6fd
PW		 6139 /* use index 1 context for tso */
6140 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6141 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6142 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6143 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6144
6145 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6146 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6147 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6148
eacd73f7
YZ		 6149 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6150 olinfo_status |= IXGBE_ADVTXD_CC;
6151 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6152 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6153 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6154 }
6155
9a799d71
AK		 6156 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6157
6158 i = tx_ring->next_to_use;
6159 while (count--) {
6160 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6161 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6162 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6163 tx_desc->read.cmd_type_len =
e8e9f696 6164 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6165 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6166 i++;
6167 if (i == tx_ring->count)
6168 i = 0;
6169 }
6170
6171 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6172
6173 /*
6174 * Force memory writes to complete before letting h/w
6175 * know there are new descriptors to fetch. (Only
6176 * applicable for weak-ordered memory model archs,
6177 * such as IA-64).
6178 */
6179 wmb();
6180
6181 tx_ring->next_to_use = i;
6182 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6183}
6184
c4cf55e5 6185static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5e09a105 6186 int queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6187{
c4cf55e5
PWJ		 6188 struct ixgbe_atr_input atr_input;
6189 struct tcphdr *th;
c4cf55e5
PWJ		 6190 struct iphdr *iph = ip_hdr(skb);
6191 struct ethhdr *eth = (struct ethhdr *)skb->data;
6192 u16 vlan_id, src_port, dst_port, flex_bytes;
6193 u32 src_ipv4_addr, dst_ipv4_addr;
6194 u8 l4type = 0;
6195
d3ead241 6196 /* Right now, we support IPv4 only */
5e09a105 6197 if (protocol != htons(ETH_P_IP))
d3ead241 6198 return;
c4cf55e5
PWJ		 6199 /* check if we're UDP or TCP */
6200 if (iph->protocol == IPPROTO_TCP) {
6201 th = tcp_hdr(skb);
6202 src_port = th->source;
6203 dst_port = th->dest;
6204 l4type |= IXGBE_ATR_L4TYPE_TCP;
6205 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6206 } else {
6207 /* Unsupported L4 header, just bail here */
6208 return;
6209 }
6210
6211 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6212
6213 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6214 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6215 src_ipv4_addr = iph->saddr;
6216 dst_ipv4_addr = iph->daddr;
6217 flex_bytes = eth->h_proto;
6218
6219 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6220 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6221 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6222 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6223 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6224 /* src and dst are inverted, think how the receiver sees them */
6225 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6226 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6227
6228 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6229 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6230}
6231
e092be60 6232static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6233 struct ixgbe_ring *tx_ring, int size)
e092be60 6234{
30eba97a 6235 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6236 /* Herbert's original patch had:
6237 * smp_mb__after_netif_stop_queue();
6238 * but since that doesn't exist yet, just open code it. */
6239 smp_mb();
6240
6241 /* We need to check again in a case another CPU has just
6242 * made room available. */
6243 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6244 return -EBUSY;
6245
6246 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6247 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6248 ++tx_ring->restart_queue;
e092be60
AV		 6249 return 0;
6250}
6251
6252static int ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6253 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6254{
6255 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6256 return 0;
6257 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6258}
6259
09a3b1f8
SH		 6260static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6261{
6262 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6263 int txq = smp_processor_id();
56075a98 6264#ifdef IXGBE_FCOE
5e09a105
HZ		 6265 __be16 protocol;
6266
6267 protocol = vlan_get_protocol(skb);
6268
6269 if ((protocol == htons(ETH_P_FCOE)) ||
6270 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6271 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6272 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6273 txq += adapter->ring_feature[RING_F_FCOE].mask;
6274 return txq;
4bc091d8 6275#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6276 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6277 txq = adapter->fcoe.up;
6278 return txq;
4bc091d8 6279#endif
56075a98
JF		 6280 }
6281 }
6282#endif
6283
fdd3d631
KK		 6284 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6285 while (unlikely(txq >= dev->real_num_tx_queues))
6286 txq -= dev->real_num_tx_queues;
5f715823 6287 return txq;
fdd3d631 6288 }
c4cf55e5 6289
2ea186ae
JF		 6290 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6291 if (skb->priority == TC_PRIO_CONTROL)
6292 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6293 else
6294 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6295 >> 13;
6296 return txq;
6297 }
09a3b1f8
SH		 6298
6299 return skb_tx_hash(dev, skb);
6300}
6301
84418e3b
AD		 6302netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6303 struct ixgbe_adapter *adapter,
6304 struct ixgbe_ring *tx_ring)
9a799d71 6305{
60d51134 6306 struct netdev_queue *txq;
9a799d71
AK		 6307 unsigned int first;
6308 unsigned int tx_flags = 0;
30eba97a 6309 u8 hdr_len = 0;
5f715823 6310 int tso;
9a799d71
AK		 6311 int count = 0;
6312 unsigned int f;
5e09a105
HZ		 6313 __be16 protocol;
6314
6315 protocol = vlan_get_protocol(skb);
9f8cdf4f 6316
eab6d18d 6317 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6318 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6319 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6320 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6321 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6322 }
6323 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6324 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6325 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6326 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6327 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6328 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6329 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6330 }
eacd73f7 6331
09ad1cc0 6332#ifdef IXGBE_FCOE
56075a98
JF		 6333 /* for FCoE with DCB, we force the priority to what
6334 * was specified by the switch */
6335 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6336 (protocol == htons(ETH_P_FCOE) ||
6337 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6338#ifdef CONFIG_IXGBE_DCB
6339 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6340 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6341 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6342 tx_flags |= ((adapter->fcoe.up << 13)
6343 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6344 }
6345#endif
ca77cd59 6346 /* flag for FCoE offloads */
5e09a105 6347 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6348 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6349 }
ca77cd59
RL		 6350#endif
6351
eacd73f7 6352 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6353 if (skb_is_gso(skb) ||
6354 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6355 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6356 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6357 count++;
6358
9f8cdf4f
JB		 6359 count += TXD_USE_COUNT(skb_headlen(skb));
6360 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6361 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6362
e092be60 6363 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6364 adapter->tx_busy++;
9a799d71
AK		 6365 return NETDEV_TX_BUSY;
6366 }
9a799d71 6367
9a799d71 6368 first = tx_ring->next_to_use;
eacd73f7
YZ		 6369 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6370#ifdef IXGBE_FCOE
6371 /* setup tx offload for FCoE */
6372 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6373 if (tso < 0) {
6374 dev_kfree_skb_any(skb);
6375 return NETDEV_TX_OK;
6376 }
6377 if (tso)
6378 tx_flags |= IXGBE_TX_FLAGS_FSO;
6379#endif /* IXGBE_FCOE */
6380 } else {
5e09a105 6381 if (protocol == htons(ETH_P_IP))
eacd73f7 6382 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6383 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6384 protocol);
eacd73f7
YZ		 6385 if (tso < 0) {
6386 dev_kfree_skb_any(skb);
6387 return NETDEV_TX_OK;
6388 }
9a799d71 6389
eacd73f7
YZ		 6390 if (tso)
6391 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6392 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6393 protocol) &&
eacd73f7
YZ		 6394 (skb->ip_summed == CHECKSUM_PARTIAL))
6395 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6396 }
9a799d71 6397
8ad494b0 6398 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6399 if (count) {
c4cf55e5
PWJ		 6400 /* add the ATR filter if ATR is on */
6401 if (tx_ring->atr_sample_rate) {
6402 ++tx_ring->atr_count;
6403 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
e8e9f696
JP		 6404 test_bit(__IXGBE_FDIR_INIT_DONE,
6405 &tx_ring->reinit_state)) {
c4cf55e5 6406 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6407 tx_flags, protocol);
c4cf55e5
PWJ		 6408 tx_ring->atr_count = 0;
6409 }
6410 }
60d51134
ED		 6411 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6412 txq->tx_bytes += skb->len;
6413 txq->tx_packets++;
44df32c5 6414 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
e8e9f696 6415 hdr_len);
44df32c5 6416 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6417
44df32c5
AD		 6418 } else {
6419 dev_kfree_skb_any(skb);
6420 tx_ring->tx_buffer_info[first].time_stamp = 0;
6421 tx_ring->next_to_use = first;
6422 }
9a799d71
AK		 6423
6424 return NETDEV_TX_OK;
6425}
6426
84418e3b
AD		 6427static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6428{
6429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6430 struct ixgbe_ring *tx_ring;
6431
6432 tx_ring = adapter->tx_ring[skb->queue_mapping];
6433 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6434}
6435
9a799d71
AK		 6436/**
6437 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6438 * @netdev: network interface device structure
6439 * @p: pointer to an address structure
6440 *
6441 * Returns 0 on success, negative on failure
6442 **/
6443static int ixgbe_set_mac(struct net_device *netdev, void *p)
6444{
6445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6446 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6447 struct sockaddr *addr = p;
6448
6449 if (!is_valid_ether_addr(addr->sa_data))
6450 return -EADDRNOTAVAIL;
6451
6452 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6453 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6454
1cdd1ec8
GR		 6455 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6456 IXGBE_RAH_AV);
9a799d71
AK		 6457
6458 return 0;
6459}
6460
6b73e10d
BH		 6461static int
6462ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6463{
6464 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6465 struct ixgbe_hw *hw = &adapter->hw;
6466 u16 value;
6467 int rc;
6468
6469 if (prtad != hw->phy.mdio.prtad)
6470 return -EINVAL;
6471 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6472 if (!rc)
6473 rc = value;
6474 return rc;
6475}
6476
6477static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6478 u16 addr, u16 value)
6479{
6480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6481 struct ixgbe_hw *hw = &adapter->hw;
6482
6483 if (prtad != hw->phy.mdio.prtad)
6484 return -EINVAL;
6485 return hw->phy.ops.write_reg(hw, addr, devad, value);
6486}
6487
6488static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6489{
6490 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6491
6492 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6493}
6494
0365e6e4
PW		 6495/**
6496 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6497 * netdev->dev_addrs
0365e6e4
PW		 6498 * @netdev: network interface device structure
6499 *
6500 * Returns non-zero on failure
6501 **/
6502static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6503{
6504 int err = 0;
6505 struct ixgbe_adapter *adapter = netdev_priv(dev);
6506 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6507
6508 if (is_valid_ether_addr(mac->san_addr)) {
6509 rtnl_lock();
6510 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6511 rtnl_unlock();
6512 }
6513 return err;
6514}
6515
6516/**
6517 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6518 * netdev->dev_addrs
0365e6e4
PW		 6519 * @netdev: network interface device structure
6520 *
6521 * Returns non-zero on failure
6522 **/
6523static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6524{
6525 int err = 0;
6526 struct ixgbe_adapter *adapter = netdev_priv(dev);
6527 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6528
6529 if (is_valid_ether_addr(mac->san_addr)) {
6530 rtnl_lock();
6531 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6532 rtnl_unlock();
6533 }
6534 return err;
6535}
6536
9a799d71
AK		 6537#ifdef CONFIG_NET_POLL_CONTROLLER
6538/*
6539 * Polling 'interrupt' - used by things like netconsole to send skbs
6540 * without having to re-enable interrupts. It's not called while
6541 * the interrupt routine is executing.
6542 */
6543static void ixgbe_netpoll(struct net_device *netdev)
6544{
6545 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6546 int i;
9a799d71 6547
1a647bd2
AD		 6548 /* if interface is down do nothing */
6549 if (test_bit(__IXGBE_DOWN, &adapter->state))
6550 return;
6551
9a799d71 6552 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6553 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6554 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6555 for (i = 0; i < num_q_vectors; i++) {
6556 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6557 ixgbe_msix_clean_many(0, q_vector);
6558 }
6559 } else {
6560 ixgbe_intr(adapter->pdev->irq, netdev);
6561 }
9a799d71 6562 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6563}
6564#endif
6565
de1036b1
ED		 6566static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6567 struct rtnl_link_stats64 *stats)
6568{
6569 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6570 int i;
6571
6572 /* accurate rx/tx bytes/packets stats */
6573 dev_txq_stats_fold(netdev, stats);
1a51502b 6574 rcu_read_lock();
de1036b1 6575 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6576 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6577 u64 bytes, packets;
6578 unsigned int start;
6579
1a51502b
ED		 6580 if (ring) {
6581 do {
6582 start = u64_stats_fetch_begin_bh(&ring->syncp);
6583 packets = ring->stats.packets;
6584 bytes = ring->stats.bytes;
6585 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6586 stats->rx_packets += packets;
6587 stats->rx_bytes += bytes;
6588 }
de1036b1 6589 }
1a51502b 6590 rcu_read_unlock();
de1036b1
ED		 6591 /* following stats updated by ixgbe_watchdog_task() */
6592 stats->multicast = netdev->stats.multicast;
6593 stats->rx_errors = netdev->stats.rx_errors;
6594 stats->rx_length_errors = netdev->stats.rx_length_errors;
6595 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6596 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6597 return stats;
6598}
6599
6600
0edc3527 6601static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6602 .ndo_open = ixgbe_open,
0edc3527 6603 .ndo_stop = ixgbe_close,
00829823 6604 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6605 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6606 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6607 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6608 .ndo_validate_addr = eth_validate_addr,
6609 .ndo_set_mac_address = ixgbe_set_mac,
6610 .ndo_change_mtu = ixgbe_change_mtu,
6611 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6612 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6613 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6614 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6615 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6616 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6617 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6618 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6619 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6620#ifdef CONFIG_NET_POLL_CONTROLLER
6621 .ndo_poll_controller = ixgbe_netpoll,
6622#endif
332d4a7d
YZ		 6623#ifdef IXGBE_FCOE
6624 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6625 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6626 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6627 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6628 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6629#endif /* IXGBE_FCOE */
0edc3527
SH		 6630};
6631
1cdd1ec8
GR		 6632static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6633 const struct ixgbe_info *ii)
6634{
6635#ifdef CONFIG_PCI_IOV
6636 struct ixgbe_hw *hw = &adapter->hw;
6637 int err;
6638
6639 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6640 return;
6641
6642 /* The 82599 supports up to 64 VFs per physical function
6643 * but this implementation limits allocation to 63 so that
6644 * basic networking resources are still available to the
6645 * physical function
6646 */
6647 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6648 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6649 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6650 if (err) {
396e799c 6651 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6652 goto err_novfs;
6653 }
6654 /* If call to enable VFs succeeded then allocate memory
6655 * for per VF control structures.
6656 */
6657 adapter->vfinfo =
6658 kcalloc(adapter->num_vfs,
6659 sizeof(struct vf_data_storage), GFP_KERNEL);
6660 if (adapter->vfinfo) {
6661 /* Now that we're sure SR-IOV is enabled
6662 * and memory allocated set up the mailbox parameters
6663 */
6664 ixgbe_init_mbx_params_pf(hw);
6665 memcpy(&hw->mbx.ops, ii->mbx_ops,
6666 sizeof(hw->mbx.ops));
6667
6668 /* Disable RSC when in SR-IOV mode */
6669 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6670 IXGBE_FLAG2_RSC_ENABLED);
6671 return;
6672 }
6673
6674 /* Oh oh */
396e799c
ET		 6675 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6676 "SRIOV disabled\n");
1cdd1ec8
GR		 6677 pci_disable_sriov(adapter->pdev);
6678
6679err_novfs:
6680 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6681 adapter->num_vfs = 0;
6682#endif /* CONFIG_PCI_IOV */
6683}
6684
9a799d71
AK		 6685/**
6686 * ixgbe_probe - Device Initialization Routine
6687 * @pdev: PCI device information struct
6688 * @ent: entry in ixgbe_pci_tbl
6689 *
6690 * Returns 0 on success, negative on failure
6691 *
6692 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6693 * The OS initialization, configuring of the adapter private structure,
6694 * and a hardware reset occur.
6695 **/
6696static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6697 const struct pci_device_id *ent)
9a799d71
AK		 6698{
6699 struct net_device *netdev;
6700 struct ixgbe_adapter *adapter = NULL;
6701 struct ixgbe_hw *hw;
6702 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6703 static int cards_found;
6704 int i, err, pci_using_dac;
c85a2618 6705 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6706#ifdef IXGBE_FCOE
6707 u16 device_caps;
6708#endif
c44ade9e 6709 u32 part_num, eec;
9a799d71 6710
bded64a7
AG		 6711 /* Catch broken hardware that put the wrong VF device ID in
6712 * the PCIe SR-IOV capability.
6713 */
6714 if (pdev->is_virtfn) {
6715 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6716 pci_name(pdev), pdev->vendor, pdev->device);
6717 return -EINVAL;
6718 }
6719
9ce77666 6720 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6721 if (err)
6722 return err;
6723
1b507730
NN		 6724 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6725 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6726 pci_using_dac = 1;
6727 } else {
1b507730 6728 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6729 if (err) {
1b507730
NN		 6730 err = dma_set_coherent_mask(&pdev->dev,
6731 DMA_BIT_MASK(32));
9a799d71 6732 if (err) {
b8bc0421
DC		 6733 dev_err(&pdev->dev,
6734 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6735 goto err_dma;
6736 }
6737 }
6738 pci_using_dac = 0;
6739 }
6740
9ce77666 6741 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6742 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6743 if (err) {
b8bc0421
DC		 6744 dev_err(&pdev->dev,
6745 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6746 goto err_pci_reg;
6747 }
6748
19d5afd4 6749 pci_enable_pcie_error_reporting(pdev);
6fabd715 6750
9a799d71 6751 pci_set_master(pdev);
fb3b27bc 6752 pci_save_state(pdev);
9a799d71 6753
c85a2618
JF		 6754 if (ii->mac == ixgbe_mac_82598EB)
6755 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6756 else
6757 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6758
6759 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6760#ifdef IXGBE_FCOE
6761 indices += min_t(unsigned int, num_possible_cpus(),
6762 IXGBE_MAX_FCOE_INDICES);
6763#endif
c85a2618 6764 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6765 if (!netdev) {
6766 err = -ENOMEM;
6767 goto err_alloc_etherdev;
6768 }
6769
9a799d71
AK		 6770 SET_NETDEV_DEV(netdev, &pdev->dev);
6771
6772 pci_set_drvdata(pdev, netdev);
6773 adapter = netdev_priv(netdev);
6774
6775 adapter->netdev = netdev;
6776 adapter->pdev = pdev;
6777 hw = &adapter->hw;
6778 hw->back = adapter;
6779 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6780
05857980 6781 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6782 pci_resource_len(pdev, 0));
9a799d71
AK		 6783 if (!hw->hw_addr) {
6784 err = -EIO;
6785 goto err_ioremap;
6786 }
6787
6788 for (i = 1; i <= 5; i++) {
6789 if (pci_resource_len(pdev, i) == 0)
6790 continue;
6791 }
6792
0edc3527 6793 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6794 ixgbe_set_ethtool_ops(netdev);
9a799d71 6795 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6796 strcpy(netdev->name, pci_name(pdev));
6797
9a799d71
AK		 6798 adapter->bd_number = cards_found;
6799
9a799d71
AK		 6800 /* Setup hw api */
6801 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6802 hw->mac.type = ii->mac;
9a799d71 6803
c44ade9e
JB		 6804 /* EEPROM */
6805 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6806 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6807 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6808 if (!(eec & (1 << 8)))
6809 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6810
6811 /* PHY */
6812 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6813 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6814 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6815 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6816 hw->phy.mdio.mmds = 0;
6817 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6818 hw->phy.mdio.dev = netdev;
6819 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6820 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6821
6822 /* set up this timer and work struct before calling get_invariants
6823 * which might start the timer
6824 */
6825 init_timer(&adapter->sfp_timer);
c061b18d 6826 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6827 adapter->sfp_timer.data = (unsigned long) adapter;
6828
6829 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6830
e8e26350
PW		 6831 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6832 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6833
6834 /* a new SFP+ module arrival, called from GPI SDP2 context */
6835 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6836 ixgbe_sfp_config_module_task);
e8e26350 6837
8ca783ab 6838 ii->get_invariants(hw);
9a799d71
AK		 6839
6840 /* setup the private structure */
6841 err = ixgbe_sw_init(adapter);
6842 if (err)
6843 goto err_sw_init;
6844
e86bff0e
DS		 6845 /* Make it possible the adapter to be woken up via WOL */
6846 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6848
bf069c97
DS		 6849 /*
6850 * If there is a fan on this device and it has failed log the
6851 * failure.
6852 */
6853 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6854 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6855 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6856 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6857 }
6858
c44ade9e 6859 /* reset_hw fills in the perm_addr as well */
119fc60a 6860 hw->phy.reset_if_overtemp = true;
c44ade9e 6861 err = hw->mac.ops.reset_hw(hw);
119fc60a 6862 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6863 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6864 hw->mac.type == ixgbe_mac_82598EB) {
6865 /*
6866 * Start a kernel thread to watch for a module to arrive.
6867 * Only do this for 82598, since 82599 will generate
6868 * interrupts on module arrival.
6869 */
6870 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6871 mod_timer(&adapter->sfp_timer,
6872 round_jiffies(jiffies + (2 * HZ)));
6873 err = 0;
6874 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6875 e_dev_err("failed to initialize because an unsupported SFP+ "
6876 "module type was detected.\n");
6877 e_dev_err("Reload the driver after installing a supported "
6878 "module.\n");
04f165ef
PW		 6879 goto err_sw_init;
6880 } else if (err) {
849c4542 6881 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6882 goto err_sw_init;
6883 }
6884
1cdd1ec8
GR		 6885 ixgbe_probe_vf(adapter, ii);
6886
396e799c 6887 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6888 NETIF_F_IP_CSUM |
6889 NETIF_F_HW_VLAN_TX |
6890 NETIF_F_HW_VLAN_RX |
6891 NETIF_F_HW_VLAN_FILTER;
9a799d71 6892
e9990a9c 6893 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6894 netdev->features |= NETIF_F_TSO;
9a799d71 6895 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6896 netdev->features |= NETIF_F_GRO;
ad31c402 6897
45a5ead0
JB		 6898 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6899 netdev->features |= NETIF_F_SCTP_CSUM;
6900
ad31c402
JK		 6901 netdev->vlan_features |= NETIF_F_TSO;
6902 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6903 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6904 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6905 netdev->vlan_features |= NETIF_F_SG;
6906
1cdd1ec8
GR		 6907 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6908 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6909 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6910 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6911 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6912
7a6b6f51 6913#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6914 netdev->dcbnl_ops = &dcbnl_ops;
6915#endif
6916
eacd73f7 6917#ifdef IXGBE_FCOE
0d551589 6918 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6919 if (hw->mac.ops.get_device_caps) {
6920 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6921 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6922 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6923 }
6924 }
5e09d7f6
YZ		 6925 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6926 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6927 netdev->vlan_features |= NETIF_F_FSO;
6928 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6929 }
eacd73f7 6930#endif /* IXGBE_FCOE */
7b872a55 6931 if (pci_using_dac) {
9a799d71 6932 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6933 netdev->vlan_features |= NETIF_F_HIGHDMA;
6934 }
9a799d71 6935
0c19d6af 6936 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6937 netdev->features |= NETIF_F_LRO;
6938
9a799d71 6939 /* make sure the EEPROM is good */
c44ade9e 6940 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6941 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6942 err = -EIO;
6943 goto err_eeprom;
6944 }
6945
6946 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6947 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6948
c44ade9e 6949 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6950 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6951 err = -EIO;
6952 goto err_eeprom;
6953 }
6954
61fac744
PW		 6955 /* power down the optics */
6956 if (hw->phy.multispeed_fiber)
6957 hw->mac.ops.disable_tx_laser(hw);
6958
9a799d71 6959 init_timer(&adapter->watchdog_timer);
c061b18d 6960 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 6961 adapter->watchdog_timer.data = (unsigned long)adapter;
6962
6963 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6964 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6965
021230d4
AV		 6966 err = ixgbe_init_interrupt_scheme(adapter);
6967 if (err)
6968 goto err_sw_init;
9a799d71 6969
e8e26350
PW		 6970 switch (pdev->device) {
6971 case IXGBE_DEV_ID_82599_KX4:
495dce12 6972 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 6973 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6974 break;
6975 default:
6976 adapter->wol = 0;
6977 break;
6978 }
e8e26350
PW		 6979 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6980
04f165ef
PW		 6981 /* pick up the PCI bus settings for reporting later */
6982 hw->mac.ops.get_bus_info(hw);
6983
9a799d71 6984 /* print bus type/speed/width info */
849c4542 6985 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 6986 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6987 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6988 "Unknown"),
6989 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6990 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6991 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6992 "Unknown"),
6993 netdev->dev_addr);
c44ade9e 6994 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6995 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6996 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6997 "PBA No: %06x-%03x\n",
6998 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6999 (part_num >> 8), (part_num & 0xff));
e8e26350 7000 else
849c4542
ET		 7001 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7002 hw->mac.type, hw->phy.type,
7003 (part_num >> 8), (part_num & 0xff));
9a799d71 7004
e8e26350 7005 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7006 e_dev_warn("PCI-Express bandwidth available for this card is "
7007 "not sufficient for optimal performance.\n");
7008 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7009 "is required.\n");
0c254d86
AK		 7010 }
7011
34b0368c
PWJ		 7012 /* save off EEPROM version number */
7013 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7014
9a799d71 7015 /* reset the hardware with the new settings */
794caeb2 7016 err = hw->mac.ops.start_hw(hw);
c44ade9e 7017
794caeb2
PWJ		 7018 if (err == IXGBE_ERR_EEPROM_VERSION) {
7019 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7020 e_dev_warn("This device is a pre-production adapter/LOM. "
7021 "Please be aware there may be issues associated "
7022 "with your hardware. If you are experiencing "
7023 "problems please contact your Intel or hardware "
7024 "representative who provided you with this "
7025 "hardware.\n");
794caeb2 7026 }
9a799d71
AK		 7027 strcpy(netdev->name, "eth%d");
7028 err = register_netdev(netdev);
7029 if (err)
7030 goto err_register;
7031
54386467
JB		 7032 /* carrier off reporting is important to ethtool even BEFORE open */
7033 netif_carrier_off(netdev);
7034
c4cf55e5
PWJ		 7035 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7036 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7037 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7038
119fc60a 7039 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7040 INIT_WORK(&adapter->check_overtemp_task,
7041 ixgbe_check_overtemp_task);
5dd2d332 7042#ifdef CONFIG_IXGBE_DCA
652f093f 7043 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7044 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7045 ixgbe_setup_dca(adapter);
7046 }
7047#endif
1cdd1ec8 7048 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7049 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7050 for (i = 0; i < adapter->num_vfs; i++)
7051 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7052 }
7053
0365e6e4
PW		 7054 /* add san mac addr to netdev */
7055 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7056
849c4542 7057 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7058 cards_found++;
7059 return 0;
7060
7061err_register:
5eba3699 7062 ixgbe_release_hw_control(adapter);
7a921c93 7063 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7064err_sw_init:
7065err_eeprom:
1cdd1ec8
GR		 7066 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7067 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7068 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7069 del_timer_sync(&adapter->sfp_timer);
7070 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7071 cancel_work_sync(&adapter->multispeed_fiber_task);
7072 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7073 iounmap(hw->hw_addr);
7074err_ioremap:
7075 free_netdev(netdev);
7076err_alloc_etherdev:
e8e9f696
JP		 7077 pci_release_selected_regions(pdev,
7078 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7079err_pci_reg:
7080err_dma:
7081 pci_disable_device(pdev);
7082 return err;
7083}
7084
7085/**
7086 * ixgbe_remove - Device Removal Routine
7087 * @pdev: PCI device information struct
7088 *
7089 * ixgbe_remove is called by the PCI subsystem to alert the driver
7090 * that it should release a PCI device. The could be caused by a
7091 * Hot-Plug event, or because the driver is going to be removed from
7092 * memory.
7093 **/
7094static void __devexit ixgbe_remove(struct pci_dev *pdev)
7095{
7096 struct net_device *netdev = pci_get_drvdata(pdev);
7097 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7098
7099 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7100 /* clear the module not found bit to make sure the worker won't
7101 * reschedule
7102 */
7103 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7104 del_timer_sync(&adapter->watchdog_timer);
7105
c4900be0
DS		 7106 del_timer_sync(&adapter->sfp_timer);
7107 cancel_work_sync(&adapter->watchdog_task);
7108 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7109 cancel_work_sync(&adapter->multispeed_fiber_task);
7110 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7111 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7112 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7113 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7114 flush_scheduled_work();
7115
5dd2d332 7116#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7117 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7118 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7119 dca_remove_requester(&pdev->dev);
7120 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7121 }
7122
7123#endif
332d4a7d
YZ		 7124#ifdef IXGBE_FCOE
7125 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7126 ixgbe_cleanup_fcoe(adapter);
7127
7128#endif /* IXGBE_FCOE */
0365e6e4
PW		 7129
7130 /* remove the added san mac */
7131 ixgbe_del_sanmac_netdev(netdev);
7132
c4900be0
DS		 7133 if (netdev->reg_state == NETREG_REGISTERED)
7134 unregister_netdev(netdev);
9a799d71 7135
1cdd1ec8
GR		 7136 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7137 ixgbe_disable_sriov(adapter);
7138
7a921c93 7139 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7140
021230d4 7141 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7142
7143 iounmap(adapter->hw.hw_addr);
9ce77666 7144 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7145 IORESOURCE_MEM));
9a799d71 7146
849c4542 7147 e_dev_info("complete\n");
021230d4 7148
9a799d71
AK		 7149 free_netdev(netdev);
7150
19d5afd4 7151 pci_disable_pcie_error_reporting(pdev);
6fabd715 7152
9a799d71
AK		 7153 pci_disable_device(pdev);
7154}
7155
7156/**
7157 * ixgbe_io_error_detected - called when PCI error is detected
7158 * @pdev: Pointer to PCI device
7159 * @state: The current pci connection state
7160 *
7161 * This function is called after a PCI bus error affecting
7162 * this device has been detected.
7163 */
7164static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7165 pci_channel_state_t state)
9a799d71
AK		 7166{
7167 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7168 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7169
7170 netif_device_detach(netdev);
7171
3044b8d1
BL		 7172 if (state == pci_channel_io_perm_failure)
7173 return PCI_ERS_RESULT_DISCONNECT;
7174
9a799d71
AK		 7175 if (netif_running(netdev))
7176 ixgbe_down(adapter);
7177 pci_disable_device(pdev);
7178
b4617240 7179 /* Request a slot reset. */
9a799d71
AK		 7180 return PCI_ERS_RESULT_NEED_RESET;
7181}
7182
7183/**
7184 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7185 * @pdev: Pointer to PCI device
7186 *
7187 * Restart the card from scratch, as if from a cold-boot.
7188 */
7189static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7190{
7191 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7192 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7193 pci_ers_result_t result;
7194 int err;
9a799d71 7195
9ce77666 7196 if (pci_enable_device_mem(pdev)) {
396e799c 7197 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7198 result = PCI_ERS_RESULT_DISCONNECT;
7199 } else {
7200 pci_set_master(pdev);
7201 pci_restore_state(pdev);
c0e1f68b 7202 pci_save_state(pdev);
9a799d71 7203
dd4d8ca6 7204 pci_wake_from_d3(pdev, false);
9a799d71 7205
6fabd715 7206 ixgbe_reset(adapter);
88512539 7207 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7208 result = PCI_ERS_RESULT_RECOVERED;
7209 }
7210
7211 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7212 if (err) {
849c4542
ET		 7213 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7214 "failed 0x%0x\n", err);
6fabd715
PWJ		 7215 /* non-fatal, continue */
7216 }
9a799d71 7217
6fabd715 7218 return result;
9a799d71
AK		 7219}
7220
7221/**
7222 * ixgbe_io_resume - called when traffic can start flowing again.
7223 * @pdev: Pointer to PCI device
7224 *
7225 * This callback is called when the error recovery driver tells us that
7226 * its OK to resume normal operation.
7227 */
7228static void ixgbe_io_resume(struct pci_dev *pdev)
7229{
7230 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7231 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7232
7233 if (netif_running(netdev)) {
7234 if (ixgbe_up(adapter)) {
396e799c 7235 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7236 return;
7237 }
7238 }
7239
7240 netif_device_attach(netdev);
9a799d71
AK		 7241}
7242
7243static struct pci_error_handlers ixgbe_err_handler = {
7244 .error_detected = ixgbe_io_error_detected,
7245 .slot_reset = ixgbe_io_slot_reset,
7246 .resume = ixgbe_io_resume,
7247};
7248
7249static struct pci_driver ixgbe_driver = {
7250 .name = ixgbe_driver_name,
7251 .id_table = ixgbe_pci_tbl,
7252 .probe = ixgbe_probe,
7253 .remove = __devexit_p(ixgbe_remove),
7254#ifdef CONFIG_PM
7255 .suspend = ixgbe_suspend,
7256 .resume = ixgbe_resume,
7257#endif
7258 .shutdown = ixgbe_shutdown,
7259 .err_handler = &ixgbe_err_handler
7260};
7261
7262/**
7263 * ixgbe_init_module - Driver Registration Routine
7264 *
7265 * ixgbe_init_module is the first routine called when the driver is
7266 * loaded. All it does is register with the PCI subsystem.
7267 **/
7268static int __init ixgbe_init_module(void)
7269{
7270 int ret;
c7689578 7271 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7272 pr_info("%s\n", ixgbe_copyright);
9a799d71 7273
5dd2d332 7274#ifdef CONFIG_IXGBE_DCA
bd0362dd 7275 dca_register_notify(&dca_notifier);
bd0362dd 7276#endif
5dd2d332 7277
9a799d71
AK		 7278 ret = pci_register_driver(&ixgbe_driver);
7279 return ret;
7280}
b4617240 7281
9a799d71
AK		 7282module_init(ixgbe_init_module);
7283
7284/**
7285 * ixgbe_exit_module - Driver Exit Cleanup Routine
7286 *
7287 * ixgbe_exit_module is called just before the driver is removed
7288 * from memory.
7289 **/
7290static void __exit ixgbe_exit_module(void)
7291{
5dd2d332 7292#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7293 dca_unregister_notify(&dca_notifier);
7294#endif
9a799d71 7295 pci_unregister_driver(&ixgbe_driver);
1a51502b 7296 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7297}
bd0362dd 7298
5dd2d332 7299#ifdef CONFIG_IXGBE_DCA
bd0362dd 7300static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7301 void *p)
bd0362dd
JC		 7302{
7303 int ret_val;
7304
7305 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7306 __ixgbe_notify_dca);
bd0362dd
JC		 7307
7308 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7309}
b453368d 7310
5dd2d332 7311#endif /* CONFIG_IXGBE_DCA */
849c4542 7312
b453368d 7313/**
849c4542 7314 * ixgbe_get_hw_dev return device
b453368d
AD		 7315 * used by hardware layer to print debugging information
7316 **/
849c4542 7317struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7318{
7319 struct ixgbe_adapter *adapter = hw->back;
849c4542 7320 return adapter->netdev;
b453368d 7321}
bd0362dd 7322
9a799d71
AK		 7323module_exit(ixgbe_exit_module);
7324
7325/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree