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ixgbe: add a state flags to ring
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601}
602
b6ec895e
AD		 603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
604 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 605{
e5a43549
AD		 606 if (tx_buffer_info->dma) {
607 if (tx_buffer_info->mapped_as_page)
b6ec895e 608 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 609 tx_buffer_info->dma,
610 tx_buffer_info->length,
1b507730 611 DMA_TO_DEVICE);
e5a43549 612 else
b6ec895e 613 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 614 tx_buffer_info->dma,
615 tx_buffer_info->length,
1b507730 616 DMA_TO_DEVICE);
e5a43549
AD		 617 tx_buffer_info->dma = 0;
618 }
9a799d71
AK		 619 if (tx_buffer_info->skb) {
620 dev_kfree_skb_any(tx_buffer_info->skb);
621 tx_buffer_info->skb = NULL;
622 }
44df32c5 623 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 624 /* tx_buffer_info must be completely set up in the transmit path */
625}
626
26f23d82 627/**
7483d9dd 628 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 629 * @adapter: the ixgbe adapter
630 * @tx_ring: the corresponding tx_ring
631 *
632 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
633 * corresponding TC of this tx_ring when checking TFCS.
634 *
7483d9dd 635 * Returns : true if in xon state (currently not paused)
26f23d82 636 */
7483d9dd 637static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 638 struct ixgbe_ring *tx_ring)
26f23d82 639{
26f23d82
YZ		 640 u32 txoff = IXGBE_TFCS_TXOFF;
641
642#ifdef CONFIG_IXGBE_DCB
ca739481 643 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 644 int tc;
26f23d82
YZ		 645 int reg_idx = tx_ring->reg_idx;
646 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
647
6837e895
PW		 648 switch (adapter->hw.mac.type) {
649 case ixgbe_mac_82598EB:
26f23d82
YZ		 650 tc = reg_idx >> 2;
651 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 652 break;
653 case ixgbe_mac_82599EB:
26f23d82
YZ		 654 tc = 0;
655 txoff = IXGBE_TFCS_TXOFF;
656 if (dcb_i == 8) {
657 /* TC0, TC1 */
658 tc = reg_idx >> 5;
659 if (tc == 2) /* TC2, TC3 */
660 tc += (reg_idx - 64) >> 4;
661 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
662 tc += 1 + ((reg_idx - 96) >> 3);
663 } else if (dcb_i == 4) {
664 /* TC0, TC1 */
665 tc = reg_idx >> 6;
666 if (tc == 1) {
667 tc += (reg_idx - 64) >> 5;
668 if (tc == 2) /* TC2, TC3 */
669 tc += (reg_idx - 96) >> 4;
670 }
671 }
6837e895
PW		 672 break;
673 default:
674 tc = 0;
26f23d82
YZ		 675 }
676 txoff <<= tc;
677 }
678#endif
679 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
680}
681
9a799d71 682static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 683 struct ixgbe_ring *tx_ring,
684 unsigned int eop)
9a799d71 685{
e01c31a5 686 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 687
9a799d71 688 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 689 * check with the clearing of time_stamp and movement of eop */
7d637bcc 690 clear_check_for_tx_hang(tx_ring);
44df32c5 691 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 692 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 693 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 694 /* detected Tx unit hang */
e01c31a5 695 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 696 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 697 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 698 " Tx Queue <%d>\n"
699 " TDH, TDT <%x>, <%x>\n"
700 " next_to_use <%x>\n"
701 " next_to_clean <%x>\n"
702 "tx_buffer_info[next_to_clean]\n"
703 " time_stamp <%lx>\n"
704 " jiffies <%lx>\n",
705 tx_ring->queue_index,
84ea2591
AD		 706 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
707 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
849c4542
ET		 708 tx_ring->next_to_use, eop,
709 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 710 return true;
711 }
712
713 return false;
714}
715
b4617240
PW		 716#define IXGBE_MAX_TXD_PWR 14
717#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 718
719/* Tx Descriptors needed, worst case */
720#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
721 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
722#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 723 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 724
e01c31a5
JB		 725static void ixgbe_tx_timeout(struct net_device *netdev);
726
9a799d71
AK		 727/**
728 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 729 * @q_vector: structure containing interrupt and ring information
e01c31a5 730 * @tx_ring: tx ring to clean
9a799d71 731 **/
fe49f04a 732static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 733 struct ixgbe_ring *tx_ring)
9a799d71 734{
fe49f04a 735 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 736 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
737 struct ixgbe_tx_buffer *tx_buffer_info;
738 unsigned int i, eop, count = 0;
e01c31a5 739 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 740
741 i = tx_ring->next_to_clean;
12207e49 742 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 743 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 744
745 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 746 (count < tx_ring->work_limit)) {
12207e49 747 bool cleaned = false;
2d0bb1c1 748 rmb(); /* read buffer_info after eop_desc */
12207e49 749 for ( ; !cleaned; count++) {
31f05a2d 750 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 751 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 752
753 tx_desc->wb.status = 0;
12207e49 754 cleaned = (i == eop);
9a799d71 755
8ad494b0
AD		 756 i++;
757 if (i == tx_ring->count)
758 i = 0;
e01c31a5 759
8ad494b0
AD		 760 if (cleaned && tx_buffer_info->skb) {
761 total_bytes += tx_buffer_info->bytecount;
762 total_packets += tx_buffer_info->gso_segs;
e092be60 763 }
e01c31a5 764
b6ec895e 765 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 766 tx_buffer_info);
e01c31a5 767 }
12207e49
PWJ		 768
769 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 770 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 771 }
772
9a799d71
AK		 773 tx_ring->next_to_clean = i;
774
e092be60 775#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 776 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 777 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 778 /* Make sure that anybody stopping the queue after this
779 * sees the new next_to_clean.
780 */
781 smp_mb();
fc77dc3c 782 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 783 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 784 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 785 ++tx_ring->tx_stats.restart_queue;
30eba97a 786 }
e092be60 787 }
9a799d71 788
7d637bcc
AD		 789 if (check_for_tx_hang(tx_ring) &&
790 ixgbe_check_tx_hang(adapter, tx_ring, i)) {
791 /* schedule immediate reset if we believe we hung */
792 e_info(probe, "tx hang %d detected, resetting "
793 "adapter\n", adapter->tx_timeout_count + 1);
794 ixgbe_tx_timeout(adapter->netdev);
e01c31a5 795 }
9a799d71 796
e01c31a5 797 /* re-arm the interrupt */
fe49f04a
AD		 798 if (count >= tx_ring->work_limit)
799 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 800
e01c31a5
JB		 801 tx_ring->total_bytes += total_bytes;
802 tx_ring->total_packets += total_packets;
de1036b1 803 u64_stats_update_begin(&tx_ring->syncp);
e01c31a5 804 tx_ring->stats.packets += total_packets;
12207e49 805 tx_ring->stats.bytes += total_bytes;
de1036b1 806 u64_stats_update_end(&tx_ring->syncp);
807540ba 807 return count < tx_ring->work_limit;
9a799d71
AK		 808}
809
5dd2d332 810#ifdef CONFIG_IXGBE_DCA
bd0362dd 811static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 812 struct ixgbe_ring *rx_ring,
813 int cpu)
bd0362dd 814{
33cf09c9 815 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 816 u32 rxctrl;
33cf09c9
AD		 817 u8 reg_idx = rx_ring->reg_idx;
818
819 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
820 switch (hw->mac.type) {
821 case ixgbe_mac_82598EB:
822 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
823 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
824 break;
825 case ixgbe_mac_82599EB:
826 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
827 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
828 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
829 break;
830 default:
831 break;
bd0362dd 832 }
33cf09c9
AD		 833 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
834 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
835 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
836 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
837 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
838 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 839}
840
841static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 842 struct ixgbe_ring *tx_ring,
843 int cpu)
bd0362dd 844{
33cf09c9 845 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 846 u32 txctrl;
33cf09c9
AD		 847 u8 reg_idx = tx_ring->reg_idx;
848
849 switch (hw->mac.type) {
850 case ixgbe_mac_82598EB:
851 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
852 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
853 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
854 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
855 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
856 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
857 break;
858 case ixgbe_mac_82599EB:
859 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
860 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
861 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
862 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
863 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
864 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
865 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
866 break;
867 default:
868 break;
869 }
870}
871
872static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
873{
874 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 875 int cpu = get_cpu();
33cf09c9
AD		 876 long r_idx;
877 int i;
bd0362dd 878
33cf09c9
AD		 879 if (q_vector->cpu == cpu)
880 goto out_no_update;
881
882 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
883 for (i = 0; i < q_vector->txr_count; i++) {
884 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
885 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
886 r_idx + 1);
bd0362dd 887 }
33cf09c9
AD		 888
889 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
890 for (i = 0; i < q_vector->rxr_count; i++) {
891 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
892 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
893 r_idx + 1);
894 }
895
896 q_vector->cpu = cpu;
897out_no_update:
bd0362dd
JC		 898 put_cpu();
899}
900
901static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
902{
33cf09c9 903 int num_q_vectors;
bd0362dd
JC		 904 int i;
905
906 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
907 return;
908
e35ec126
AD		 909 /* always use CB2 mode, difference is masked in the CB driver */
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
911
33cf09c9
AD		 912 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
913 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
914 else
915 num_q_vectors = 1;
916
917 for (i = 0; i < num_q_vectors; i++) {
918 adapter->q_vector[i]->cpu = -1;
919 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 920 }
921}
922
923static int __ixgbe_notify_dca(struct device *dev, void *data)
924{
c60fbb00 925 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 926 unsigned long event = *(unsigned long *)data;
927
33cf09c9
AD		 928 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
929 return 0;
930
bd0362dd
JC		 931 switch (event) {
932 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 933 /* if we're already enabled, don't do it again */
934 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
935 break;
652f093f 936 if (dca_add_requester(dev) == 0) {
96b0e0f6 937 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 938 ixgbe_setup_dca(adapter);
939 break;
940 }
941 /* Fall Through since DCA is disabled. */
942 case DCA_PROVIDER_REMOVE:
943 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
944 dca_remove_requester(dev);
945 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
947 }
948 break;
949 }
950
652f093f 951 return 0;
bd0362dd
JC		 952}
953
5dd2d332 954#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 955/**
956 * ixgbe_receive_skb - Send a completed packet up the stack
957 * @adapter: board private structure
958 * @skb: packet to send up
177db6ff
MC		 959 * @status: hardware indication of status of receive
960 * @rx_ring: rx descriptor ring (for a specific queue) to setup
961 * @rx_desc: rx descriptor
9a799d71 962 **/
78b6f4ce 963static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 964 struct sk_buff *skb, u8 status,
965 struct ixgbe_ring *ring,
966 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 967{
78b6f4ce
HX		 968 struct ixgbe_adapter *adapter = q_vector->adapter;
969 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 970 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
971 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 972
f62bbb5e
JG		 973 if (is_vlan && (tag & VLAN_VID_MASK))
974 __vlan_hwaccel_put_tag(skb, tag);
975
976 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
977 napi_gro_receive(napi, skb);
978 else
979 netif_rx(skb);
9a799d71
AK		 980}
981
e59bd25d
AV		 982/**
983 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
984 * @adapter: address of board private structure
985 * @status_err: hardware indication of status of receive
986 * @skb: skb currently being received and modified
987 **/
9a799d71 988static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 989 union ixgbe_adv_rx_desc *rx_desc,
990 struct sk_buff *skb)
9a799d71 991{
8bae1b2b
DS		 992 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
993
bc8acf2c 994 skb_checksum_none_assert(skb);
9a799d71 995
712744be
JB		 996 /* Rx csum disabled */
997 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 998 return;
e59bd25d
AV		 999
1000 /* if IP and error */
1001 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1002 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1003 adapter->hw_csum_rx_error++;
1004 return;
1005 }
e59bd25d
AV		 1006
1007 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1008 return;
1009
1010 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1011 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1012
1013 /*
1014 * 82599 errata, UDP frames with a 0 checksum can be marked as
1015 * checksum errors.
1016 */
1017 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1018 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1019 return;
1020
e59bd25d
AV		 1021 adapter->hw_csum_rx_error++;
1022 return;
1023 }
1024
9a799d71 1025 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1026 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1027}
1028
84ea2591 1029static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1030{
1031 /*
1032 * Force memory writes to complete before letting h/w
1033 * know there are new descriptors to fetch. (Only
1034 * applicable for weak-ordered memory model archs,
1035 * such as IA-64).
1036 */
1037 wmb();
84ea2591 1038 writel(val, rx_ring->tail);
e8e26350
PW		 1039}
1040
9a799d71
AK		 1041/**
1042 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1043 * @rx_ring: ring to place buffers on
1044 * @cleaned_count: number of buffers to replace
9a799d71 1045 **/
fc77dc3c 1046void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1047{
9a799d71 1048 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1049 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1050 struct sk_buff *skb;
1051 u16 i = rx_ring->next_to_use;
9a799d71 1052
fc77dc3c
AD		 1053 /* do nothing if no valid netdev defined */
1054 if (!rx_ring->netdev)
1055 return;
1056
9a799d71 1057 while (cleaned_count--) {
31f05a2d 1058 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1059 bi = &rx_ring->rx_buffer_info[i];
1060 skb = bi->skb;
9a799d71 1061
d5f398ed 1062 if (!skb) {
fc77dc3c 1063 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1064 rx_ring->rx_buf_len);
9a799d71 1065 if (!skb) {
5b7da515 1066 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1067 goto no_buffers;
1068 }
d716a7d8
AD		 1069 /* initialize queue mapping */
1070 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1071 bi->skb = skb;
d716a7d8 1072 }
9a799d71 1073
d716a7d8 1074 if (!bi->dma) {
b6ec895e 1075 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1076 skb->data,
e8e9f696 1077 rx_ring->rx_buf_len,
1b507730 1078 DMA_FROM_DEVICE);
b6ec895e 1079 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1080 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1081 bi->dma = 0;
1082 goto no_buffers;
1083 }
9a799d71 1084 }
d5f398ed 1085
7d637bcc 1086 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1087 if (!bi->page) {
fc77dc3c 1088 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1089 if (!bi->page) {
5b7da515 1090 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1091 goto no_buffers;
1092 }
1093 }
1094
1095 if (!bi->page_dma) {
1096 /* use a half page if we're re-using */
1097 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1098 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1099 bi->page,
1100 bi->page_offset,
1101 PAGE_SIZE / 2,
1102 DMA_FROM_DEVICE);
b6ec895e 1103 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1104 bi->page_dma)) {
5b7da515 1105 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1106 bi->page_dma = 0;
1107 goto no_buffers;
1108 }
1109 }
1110
1111 /* Refresh the desc even if buffer_addrs didn't change
1112 * because each write-back erases this info. */
3a581073
JB		 1113 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1114 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1115 } else {
3a581073 1116 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1117 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1118 }
1119
1120 i++;
1121 if (i == rx_ring->count)
1122 i = 0;
9a799d71 1123 }
7c6e0a43 1124
9a799d71
AK		 1125no_buffers:
1126 if (rx_ring->next_to_use != i) {
1127 rx_ring->next_to_use = i;
84ea2591 1128 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1129 }
1130}
1131
7c6e0a43
JB		 1132static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1133{
1134 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1135}
1136
1137static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1138{
1139 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1140}
1141
f8212f97
AD		 1142static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1143{
1144 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1145 IXGBE_RXDADV_RSCCNT_MASK) >>
1146 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1147}
1148
1149/**
1150 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1151 * @skb: pointer to the last skb in the rsc queue
94b982b2 1152 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1153 *
1154 * This function changes a queue full of hw rsc buffers into a completed
1155 * packet. It uses the ->prev pointers to find the first packet and then
1156 * turns it into the frag list owner.
1157 **/
94b982b2 1158static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1159 u64 *count)
f8212f97
AD		 1160{
1161 unsigned int frag_list_size = 0;
1162
1163 while (skb->prev) {
1164 struct sk_buff *prev = skb->prev;
1165 frag_list_size += skb->len;
1166 skb->prev = NULL;
1167 skb = prev;
94b982b2 1168 *count += 1;
f8212f97
AD		 1169 }
1170
1171 skb_shinfo(skb)->frag_list = skb->next;
1172 skb->next = NULL;
1173 skb->len += frag_list_size;
1174 skb->data_len += frag_list_size;
1175 skb->truesize += frag_list_size;
1176 return skb;
1177}
1178
43634e82
MC		 1179struct ixgbe_rsc_cb {
1180 dma_addr_t dma;
e8171aaa 1181 bool delay_unmap;
43634e82
MC		 1182};
1183
1184#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1185
78b6f4ce 1186static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1187 struct ixgbe_ring *rx_ring,
1188 int *work_done, int work_to_do)
9a799d71 1189{
78b6f4ce 1190 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1191 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1192 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1193 struct sk_buff *skb;
f8212f97 1194 unsigned int i, rsc_count = 0;
7c6e0a43 1195 u32 len, staterr;
177db6ff
MC		 1196 u16 hdr_info;
1197 bool cleaned = false;
9a799d71 1198 int cleaned_count = 0;
d2f4fbe2 1199 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1200#ifdef IXGBE_FCOE
1201 int ddp_bytes = 0;
1202#endif /* IXGBE_FCOE */
9a799d71
AK		 1203
1204 i = rx_ring->next_to_clean;
31f05a2d 1205 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1206 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1207 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1208
1209 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1210 u32 upper_len = 0;
9a799d71
AK		 1211 if (*work_done >= work_to_do)
1212 break;
1213 (*work_done)++;
1214
3c945e5b 1215 rmb(); /* read descriptor and rx_buffer_info after status DD */
7d637bcc 1216 if (ring_is_ps_enabled(rx_ring)) {
7c6e0a43
JB		 1217 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1218 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1219 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1220 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1221 if ((len > IXGBE_RX_HDR_SIZE) ||
1222 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1223 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1224 } else {
9a799d71 1225 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1226 }
9a799d71
AK		 1227
1228 cleaned = true;
1229 skb = rx_buffer_info->skb;
7ca3bc58 1230 prefetch(skb->data);
9a799d71
AK		 1231 rx_buffer_info->skb = NULL;
1232
21fa4e66 1233 if (rx_buffer_info->dma) {
43634e82
MC		 1234 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1235 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1236 (!(skb->prev))) {
43634e82
MC		 1237 /*
1238 * When HWRSC is enabled, delay unmapping
1239 * of the first packet. It carries the
1240 * header information, HW may still
1241 * access the header after the writeback.
1242 * Only unmap it when EOP is reached
1243 */
e8171aaa 1244 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1245 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1246 } else {
b6ec895e 1247 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1248 rx_buffer_info->dma,
1249 rx_ring->rx_buf_len,
1250 DMA_FROM_DEVICE);
e8171aaa 1251 }
4f57ca6e 1252 rx_buffer_info->dma = 0;
9a799d71
AK		 1253 skb_put(skb, len);
1254 }
1255
1256 if (upper_len) {
b6ec895e
AD		 1257 dma_unmap_page(rx_ring->dev,
1258 rx_buffer_info->page_dma,
1259 PAGE_SIZE / 2,
1260 DMA_FROM_DEVICE);
9a799d71
AK		 1261 rx_buffer_info->page_dma = 0;
1262 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1263 rx_buffer_info->page,
1264 rx_buffer_info->page_offset,
1265 upper_len);
762f4c57
JB		 1266
1267 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1268 (page_count(rx_buffer_info->page) != 1))
1269 rx_buffer_info->page = NULL;
1270 else
1271 get_page(rx_buffer_info->page);
9a799d71
AK		 1272
1273 skb->len += upper_len;
1274 skb->data_len += upper_len;
1275 skb->truesize += upper_len;
1276 }
1277
1278 i++;
1279 if (i == rx_ring->count)
1280 i = 0;
9a799d71 1281
31f05a2d 1282 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1283 prefetch(next_rxd);
9a799d71 1284 cleaned_count++;
f8212f97 1285
7d637bcc 1286 if (ring_is_rsc_enabled(rx_ring))
f8212f97
AD		 1287 rsc_count = ixgbe_get_rsc_count(rx_desc);
1288
1289 if (rsc_count) {
1290 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1291 IXGBE_RXDADV_NEXTP_SHIFT;
1292 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1293 } else {
1294 next_buffer = &rx_ring->rx_buffer_info[i];
1295 }
1296
9a799d71 1297 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1298 if (skb->prev)
e8e9f696 1299 skb = ixgbe_transform_rsc_queue(skb,
5b7da515 1300 &(rx_ring->rx_stats.rsc_count));
7d637bcc 1301 if (ring_is_rsc_enabled(rx_ring)) {
e8171aaa 1302 if (IXGBE_RSC_CB(skb)->delay_unmap) {
b6ec895e 1303 dma_unmap_single(rx_ring->dev,
1b507730 1304 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1305 rx_ring->rx_buf_len,
1b507730 1306 DMA_FROM_DEVICE);
fd3686a8 1307 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1308 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1309 }
7d637bcc 1310 if (ring_is_ps_enabled(rx_ring))
5b7da515
AD		 1311 rx_ring->rx_stats.rsc_count +=
1312 skb_shinfo(skb)->nr_frags;
94b982b2 1313 else
5b7da515
AD		 1314 rx_ring->rx_stats.rsc_count++;
1315 rx_ring->rx_stats.rsc_flush++;
94b982b2 1316 }
de1036b1 1317 u64_stats_update_begin(&rx_ring->syncp);
9a799d71
AK		 1318 rx_ring->stats.packets++;
1319 rx_ring->stats.bytes += skb->len;
de1036b1 1320 u64_stats_update_end(&rx_ring->syncp);
9a799d71 1321 } else {
7d637bcc 1322 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1323 rx_buffer_info->skb = next_buffer->skb;
1324 rx_buffer_info->dma = next_buffer->dma;
1325 next_buffer->skb = skb;
1326 next_buffer->dma = 0;
1327 } else {
1328 skb->next = next_buffer->skb;
1329 skb->next->prev = skb;
1330 }
5b7da515 1331 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1332 goto next_desc;
1333 }
1334
1335 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1336 dev_kfree_skb_irq(skb);
1337 goto next_desc;
1338 }
1339
8bae1b2b 1340 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1341
1342 /* probably a little skewed due to removing CRC */
1343 total_rx_bytes += skb->len;
1344 total_rx_packets++;
1345
fc77dc3c 1346 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1347#ifdef IXGBE_FCOE
1348 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1349 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1350 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1351 if (!ddp_bytes)
332d4a7d 1352 goto next_desc;
3d8fd385 1353 }
332d4a7d 1354#endif /* IXGBE_FCOE */
fdaff1ce 1355 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1356
1357next_desc:
1358 rx_desc->wb.upper.status_error = 0;
1359
1360 /* return some buffers to hardware, one at a time is too slow */
1361 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1362 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1363 cleaned_count = 0;
1364 }
1365
1366 /* use prefetched values */
1367 rx_desc = next_rxd;
f8212f97 1368 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1369
1370 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1371 }
1372
9a799d71
AK		 1373 rx_ring->next_to_clean = i;
1374 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1375
1376 if (cleaned_count)
fc77dc3c 1377 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1378
3d8fd385
YZ		 1379#ifdef IXGBE_FCOE
1380 /* include DDPed FCoE data */
1381 if (ddp_bytes > 0) {
1382 unsigned int mss;
1383
fc77dc3c 1384 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1385 sizeof(struct fc_frame_header) -
1386 sizeof(struct fcoe_crc_eof);
1387 if (mss > 512)
1388 mss &= ~511;
1389 total_rx_bytes += ddp_bytes;
1390 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1391 }
1392#endif /* IXGBE_FCOE */
1393
f494e8fa
AV		 1394 rx_ring->total_packets += total_rx_packets;
1395 rx_ring->total_bytes += total_rx_bytes;
f494e8fa 1396
9a799d71
AK		 1397 return cleaned;
1398}
1399
021230d4 1400static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1401/**
1402 * ixgbe_configure_msix - Configure MSI-X hardware
1403 * @adapter: board private structure
1404 *
1405 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1406 * interrupts.
1407 **/
1408static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1409{
021230d4
AV		 1410 struct ixgbe_q_vector *q_vector;
1411 int i, j, q_vectors, v_idx, r_idx;
1412 u32 mask;
9a799d71 1413
021230d4 1414 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1415
4df10466
JB		 1416 /*
1417 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1418 * corresponding register.
1419 */
1420 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1421 q_vector = adapter->q_vector[v_idx];
984b3f57 1422 /* XXX for_each_set_bit(...) */
021230d4 1423 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1424 adapter->num_rx_queues);
021230d4
AV		 1425
1426 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1427 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1428 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1429 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1430 adapter->num_rx_queues,
1431 r_idx + 1);
021230d4
AV		 1432 }
1433 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1434 adapter->num_tx_queues);
021230d4
AV		 1435
1436 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1437 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1438 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1439 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1440 adapter->num_tx_queues,
1441 r_idx + 1);
021230d4
AV		 1442 }
1443
021230d4 1444 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1445 /* tx only */
1446 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1447 else if (q_vector->rxr_count)
f7554a2b
NS		 1448 /* rx or mixed */
1449 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1450
fe49f04a 1451 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1452 /* If Flow Director is enabled, set interrupt affinity */
1453 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1454 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1455 /*
1456 * Allocate the affinity_hint cpumask, assign the mask
1457 * for this vector, and set our affinity_hint for
1458 * this irq.
1459 */
1460 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1461 GFP_KERNEL))
1462 return;
1463 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1464 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1465 q_vector->affinity_mask);
1466 }
9a799d71
AK		 1467 }
1468
e8e26350
PW		 1469 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1470 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1471 v_idx);
e8e26350
PW		 1472 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1473 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1475
41fb9248 1476 /* set up to autoclear timer, and the vectors */
021230d4 1477 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1478 if (adapter->num_vfs)
1479 mask &= ~(IXGBE_EIMS_OTHER |
1480 IXGBE_EIMS_MAILBOX |
1481 IXGBE_EIMS_LSC);
1482 else
1483 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1484 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1485}
1486
f494e8fa
AV		 1487enum latency_range {
1488 lowest_latency = 0,
1489 low_latency = 1,
1490 bulk_latency = 2,
1491 latency_invalid = 255
1492};
1493
1494/**
1495 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1496 * @adapter: pointer to adapter
1497 * @eitr: eitr setting (ints per sec) to give last timeslice
1498 * @itr_setting: current throttle rate in ints/second
1499 * @packets: the number of packets during this measurement interval
1500 * @bytes: the number of bytes during this measurement interval
1501 *
1502 * Stores a new ITR value based on packets and byte
1503 * counts during the last interrupt. The advantage of per interrupt
1504 * computation is faster updates and more accurate ITR for the current
1505 * traffic pattern. Constants in this function were computed
1506 * based on theoretical maximum wire speed and thresholds were set based
1507 * on testing data as well as attempting to minimize response time
1508 * while increasing bulk throughput.
1509 * this functionality is controlled by the InterruptThrottleRate module
1510 * parameter (see ixgbe_param.c)
1511 **/
1512static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1513 u32 eitr, u8 itr_setting,
1514 int packets, int bytes)
f494e8fa
AV		 1515{
1516 unsigned int retval = itr_setting;
1517 u32 timepassed_us;
1518 u64 bytes_perint;
1519
1520 if (packets == 0)
1521 goto update_itr_done;
1522
1523
1524 /* simple throttlerate management
1525 * 0-20MB/s lowest (100000 ints/s)
1526 * 20-100MB/s low (20000 ints/s)
1527 * 100-1249MB/s bulk (8000 ints/s)
1528 */
1529 /* what was last interrupt timeslice? */
1530 timepassed_us = 1000000/eitr;
1531 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1532
1533 switch (itr_setting) {
1534 case lowest_latency:
1535 if (bytes_perint > adapter->eitr_low)
1536 retval = low_latency;
1537 break;
1538 case low_latency:
1539 if (bytes_perint > adapter->eitr_high)
1540 retval = bulk_latency;
1541 else if (bytes_perint <= adapter->eitr_low)
1542 retval = lowest_latency;
1543 break;
1544 case bulk_latency:
1545 if (bytes_perint <= adapter->eitr_high)
1546 retval = low_latency;
1547 break;
1548 }
1549
1550update_itr_done:
1551 return retval;
1552}
1553
509ee935
JB		 1554/**
1555 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1556 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1557 *
1558 * This function is made to be called by ethtool and by the driver
1559 * when it needs to update EITR registers at runtime. Hardware
1560 * specific quirks/differences are taken care of here.
1561 */
fe49f04a 1562void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1563{
fe49f04a 1564 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1565 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1566 int v_idx = q_vector->v_idx;
1567 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1568
509ee935
JB		 1569 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1570 /* must write high and low 16 bits to reset counter */
1571 itr_reg |= (itr_reg << 16);
1572 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1573 /*
1574 * 82599 can support a value of zero, so allow it for
1575 * max interrupt rate, but there is an errata where it can
1576 * not be zero with RSC
1577 */
1578 if (itr_reg == 8 &&
1579 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1580 itr_reg = 0;
1581
509ee935
JB		 1582 /*
1583 * set the WDIS bit to not clear the timer bits and cause an
1584 * immediate assertion of the interrupt
1585 */
1586 itr_reg |= IXGBE_EITR_CNT_WDIS;
1587 }
1588 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1589}
1590
f494e8fa
AV		 1591static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1592{
1593 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1594 u32 new_itr;
1595 u8 current_itr, ret_itr;
fe49f04a 1596 int i, r_idx;
f494e8fa
AV		 1597 struct ixgbe_ring *rx_ring, *tx_ring;
1598
1599 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1600 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1601 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1602 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1603 q_vector->tx_itr,
1604 tx_ring->total_packets,
1605 tx_ring->total_bytes);
f494e8fa
AV		 1606 /* if the result for this queue would decrease interrupt
1607 * rate for this vector then use that result */
30efa5a3 1608 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1609 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1610 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1611 r_idx + 1);
f494e8fa
AV		 1612 }
1613
1614 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1615 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1616 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1617 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1618 q_vector->rx_itr,
1619 rx_ring->total_packets,
1620 rx_ring->total_bytes);
f494e8fa
AV		 1621 /* if the result for this queue would decrease interrupt
1622 * rate for this vector then use that result */
30efa5a3 1623 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1624 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1625 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1626 r_idx + 1);
f494e8fa
AV		 1627 }
1628
30efa5a3 1629 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1630
1631 switch (current_itr) {
1632 /* counts and packets in update_itr are dependent on these numbers */
1633 case lowest_latency:
1634 new_itr = 100000;
1635 break;
1636 case low_latency:
1637 new_itr = 20000; /* aka hwitr = ~200 */
1638 break;
1639 case bulk_latency:
1640 default:
1641 new_itr = 8000;
1642 break;
1643 }
1644
1645 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1646 /* do an exponential smoothing */
1647 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1648
1649 /* save the algorithm value here, not the smoothed one */
1650 q_vector->eitr = new_itr;
fe49f04a
AD		 1651
1652 ixgbe_write_eitr(q_vector);
f494e8fa 1653 }
f494e8fa
AV		 1654}
1655
119fc60a
MC		 1656/**
1657 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1658 * @work: pointer to work_struct containing our data
1659 **/
1660static void ixgbe_check_overtemp_task(struct work_struct *work)
1661{
1662 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1663 struct ixgbe_adapter,
1664 check_overtemp_task);
119fc60a
MC		 1665 struct ixgbe_hw *hw = &adapter->hw;
1666 u32 eicr = adapter->interrupt_event;
1667
7ca647bd
JP		 1668 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1669 return;
1670
1671 switch (hw->device_id) {
1672 case IXGBE_DEV_ID_82599_T3_LOM: {
1673 u32 autoneg;
1674 bool link_up = false;
1675
1676 if (hw->mac.ops.check_link)
1677 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1678
1679 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1680 (eicr & IXGBE_EICR_LSC))
1681 /* Check if this is due to overtemp */
1682 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1683 break;
1684 return;
1685 }
1686 default:
1687 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1688 return;
7ca647bd 1689 break;
119fc60a 1690 }
7ca647bd
JP		 1691 e_crit(drv,
1692 "Network adapter has been stopped because it has over heated. "
1693 "Restart the computer. If the problem persists, "
1694 "power off the system and replace the adapter\n");
1695 /* write to clear the interrupt */
1696 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1697}
1698
0befdb3e
JB		 1699static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1700{
1701 struct ixgbe_hw *hw = &adapter->hw;
1702
1703 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1704 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1705 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1706 /* write to clear the interrupt */
1707 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1708 }
1709}
cf8280ee 1710
e8e26350
PW		 1711static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1712{
1713 struct ixgbe_hw *hw = &adapter->hw;
1714
1715 if (eicr & IXGBE_EICR_GPI_SDP1) {
1716 /* Clear the interrupt */
1717 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1718 schedule_work(&adapter->multispeed_fiber_task);
1719 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1720 /* Clear the interrupt */
1721 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1722 schedule_work(&adapter->sfp_config_module_task);
1723 } else {
1724 /* Interrupt isn't for us... */
1725 return;
1726 }
1727}
1728
cf8280ee
JB		 1729static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1730{
1731 struct ixgbe_hw *hw = &adapter->hw;
1732
1733 adapter->lsc_int++;
1734 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1735 adapter->link_check_timeout = jiffies;
1736 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1737 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1738 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1739 schedule_work(&adapter->watchdog_task);
1740 }
1741}
1742
9a799d71
AK		 1743static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1744{
1745 struct net_device *netdev = data;
1746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1747 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1748 u32 eicr;
1749
1750 /*
1751 * Workaround for Silicon errata. Use clear-by-write instead
1752 * of clear-by-read. Reading with EICS will return the
1753 * interrupt causes without clearing, which later be done
1754 * with the write to EICR.
1755 */
1756 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1757 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1758
cf8280ee
JB		 1759 if (eicr & IXGBE_EICR_LSC)
1760 ixgbe_check_lsc(adapter);
d4f80882 1761
1cdd1ec8
GR		 1762 if (eicr & IXGBE_EICR_MAILBOX)
1763 ixgbe_msg_task(adapter);
1764
e8e26350
PW		 1765 if (hw->mac.type == ixgbe_mac_82598EB)
1766 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1767
c4cf55e5 1768 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1769 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1770 adapter->interrupt_event = eicr;
1771 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1772 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1773 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1774
1775 /* Handle Flow Director Full threshold interrupt */
1776 if (eicr & IXGBE_EICR_FLOW_DIR) {
1777 int i;
1778 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1779 /* Disable transmits before FDIR Re-initialization */
1780 netif_tx_stop_all_queues(netdev);
1781 for (i = 0; i < adapter->num_tx_queues; i++) {
1782 struct ixgbe_ring *tx_ring =
e8e9f696 1783 adapter->tx_ring[i];
7d637bcc
AD		 1784 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1785 &tx_ring->state))
c4cf55e5
PWJ		 1786 schedule_work(&adapter->fdir_reinit_task);
1787 }
1788 }
1789 }
d4f80882
AV		 1790 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1791 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1792
1793 return IRQ_HANDLED;
1794}
1795
fe49f04a
AD		 1796static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1797 u64 qmask)
1798{
1799 u32 mask;
1800
1801 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1802 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1803 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1804 } else {
1805 mask = (qmask & 0xFFFFFFFF);
1806 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1807 mask = (qmask >> 32);
1808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1809 }
1810 /* skip the flush */
1811}
1812
1813static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1814 u64 qmask)
fe49f04a
AD		 1815{
1816 u32 mask;
1817
1818 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1819 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1820 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1821 } else {
1822 mask = (qmask & 0xFFFFFFFF);
1823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1824 mask = (qmask >> 32);
1825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1826 }
1827 /* skip the flush */
1828}
1829
9a799d71
AK		 1830static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1831{
021230d4
AV		 1832 struct ixgbe_q_vector *q_vector = data;
1833 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1834 struct ixgbe_ring *tx_ring;
021230d4
AV		 1835 int i, r_idx;
1836
1837 if (!q_vector->txr_count)
1838 return IRQ_HANDLED;
1839
1840 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1841 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1842 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1843 tx_ring->total_bytes = 0;
1844 tx_ring->total_packets = 0;
021230d4 1845 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1846 r_idx + 1);
021230d4 1847 }
9a799d71 1848
9b471446 1849 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1850 napi_schedule(&q_vector->napi);
1851
9a799d71
AK		 1852 return IRQ_HANDLED;
1853}
1854
021230d4
AV		 1855/**
1856 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1857 * @irq: unused
1858 * @data: pointer to our q_vector struct for this interrupt vector
1859 **/
9a799d71
AK		 1860static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1861{
021230d4
AV		 1862 struct ixgbe_q_vector *q_vector = data;
1863 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1864 struct ixgbe_ring *rx_ring;
021230d4 1865 int r_idx;
30efa5a3 1866 int i;
021230d4 1867
33cf09c9
AD		 1868#ifdef CONFIG_IXGBE_DCA
1869 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1870 ixgbe_update_dca(q_vector);
1871#endif
1872
021230d4 1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 1874 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1875 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1876 rx_ring->total_bytes = 0;
1877 rx_ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1879 r_idx + 1);
30efa5a3
JB		 1880 }
1881
021230d4
AV		 1882 if (!q_vector->rxr_count)
1883 return IRQ_HANDLED;
1884
9b471446 1885 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1886 napi_schedule(&q_vector->napi);
021230d4
AV		 1887
1888 return IRQ_HANDLED;
1889}
1890
1891static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1892{
91281fd3
AD		 1893 struct ixgbe_q_vector *q_vector = data;
1894 struct ixgbe_adapter *adapter = q_vector->adapter;
1895 struct ixgbe_ring *ring;
1896 int r_idx;
1897 int i;
1898
1899 if (!q_vector->txr_count && !q_vector->rxr_count)
1900 return IRQ_HANDLED;
1901
1902 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1903 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1904 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1905 ring->total_bytes = 0;
1906 ring->total_packets = 0;
1907 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1908 r_idx + 1);
91281fd3
AD		 1909 }
1910
1911 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1912 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1913 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1914 ring->total_bytes = 0;
1915 ring->total_packets = 0;
1916 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1917 r_idx + 1);
91281fd3
AD		 1918 }
1919
9b471446 1920 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1921 napi_schedule(&q_vector->napi);
9a799d71 1922
9a799d71
AK		 1923 return IRQ_HANDLED;
1924}
1925
021230d4
AV		 1926/**
1927 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1928 * @napi: napi struct with our devices info in it
1929 * @budget: amount of work driver is allowed to do this pass, in packets
1930 *
f0848276
JB		 1931 * This function is optimized for cleaning one queue only on a single
1932 * q_vector!!!
021230d4 1933 **/
9a799d71
AK		 1934static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1935{
021230d4 1936 struct ixgbe_q_vector *q_vector =
e8e9f696 1937 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1938 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1939 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1940 int work_done = 0;
021230d4 1941 long r_idx;
9a799d71 1942
5dd2d332 1943#ifdef CONFIG_IXGBE_DCA
bd0362dd 1944 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 1945 ixgbe_update_dca(q_vector);
bd0362dd 1946#endif
9a799d71 1947
33cf09c9
AD		 1948 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1949 rx_ring = adapter->rx_ring[r_idx];
1950
78b6f4ce 1951 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1952
021230d4
AV		 1953 /* If all Rx work done, exit the polling mode */
1954 if (work_done < budget) {
288379f0 1955 napi_complete(napi);
f7554a2b 1956 if (adapter->rx_itr_setting & 1)
f494e8fa 1957 ixgbe_set_itr_msix(q_vector);
9a799d71 1958 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1959 ixgbe_irq_enable_queues(adapter,
e8e9f696 1960 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1961 }
1962
1963 return work_done;
1964}
1965
f0848276 1966/**
91281fd3 1967 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1968 * @napi: napi struct with our devices info in it
1969 * @budget: amount of work driver is allowed to do this pass, in packets
1970 *
1971 * This function will clean more than one rx queue associated with a
1972 * q_vector.
1973 **/
91281fd3 1974static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1975{
1976 struct ixgbe_q_vector *q_vector =
e8e9f696 1977 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1978 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1979 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1980 int work_done = 0, i;
1981 long r_idx;
91281fd3
AD		 1982 bool tx_clean_complete = true;
1983
33cf09c9
AD		 1984#ifdef CONFIG_IXGBE_DCA
1985 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1986 ixgbe_update_dca(q_vector);
1987#endif
1988
91281fd3
AD		 1989 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1990 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1991 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1992 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1993 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1994 r_idx + 1);
91281fd3 1995 }
f0848276
JB		 1996
1997 /* attempt to distribute budget to each queue fairly, but don't allow
1998 * the budget to go below 1 because we'll exit polling */
1999 budget /= (q_vector->rxr_count ?: 1);
2000 budget = max(budget, 1);
2001 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2002 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2003 ring = adapter->rx_ring[r_idx];
91281fd3 2004 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2005 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2006 r_idx + 1);
f0848276
JB		 2007 }
2008
2009 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2010 ring = adapter->rx_ring[r_idx];
f0848276 2011 /* If all Rx work done, exit the polling mode */
7f821875 2012 if (work_done < budget) {
288379f0 2013 napi_complete(napi);
f7554a2b 2014 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2015 ixgbe_set_itr_msix(q_vector);
2016 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2017 ixgbe_irq_enable_queues(adapter,
e8e9f696 2018 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2019 return 0;
2020 }
2021
2022 return work_done;
2023}
91281fd3
AD		 2024
2025/**
2026 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2027 * @napi: napi struct with our devices info in it
2028 * @budget: amount of work driver is allowed to do this pass, in packets
2029 *
2030 * This function is optimized for cleaning one queue only on a single
2031 * q_vector!!!
2032 **/
2033static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2034{
2035 struct ixgbe_q_vector *q_vector =
e8e9f696 2036 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2037 struct ixgbe_adapter *adapter = q_vector->adapter;
2038 struct ixgbe_ring *tx_ring = NULL;
2039 int work_done = 0;
2040 long r_idx;
2041
91281fd3
AD		 2042#ifdef CONFIG_IXGBE_DCA
2043 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2044 ixgbe_update_dca(q_vector);
91281fd3
AD		 2045#endif
2046
33cf09c9
AD		 2047 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2048 tx_ring = adapter->tx_ring[r_idx];
2049
91281fd3
AD		 2050 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2051 work_done = budget;
2052
f7554a2b 2053 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2054 if (work_done < budget) {
2055 napi_complete(napi);
f7554a2b 2056 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2057 ixgbe_set_itr_msix(q_vector);
2058 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2059 ixgbe_irq_enable_queues(adapter,
2060 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2061 }
2062
2063 return work_done;
2064}
2065
021230d4 2066static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2067 int r_idx)
021230d4 2068{
7a921c93
AD		 2069 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2070
2071 set_bit(r_idx, q_vector->rxr_idx);
2072 q_vector->rxr_count++;
021230d4
AV		 2073}
2074
2075static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2076 int t_idx)
021230d4 2077{
7a921c93
AD		 2078 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2079
2080 set_bit(t_idx, q_vector->txr_idx);
2081 q_vector->txr_count++;
021230d4
AV		 2082}
2083
9a799d71 2084/**
021230d4
AV		 2085 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2086 * @adapter: board private structure to initialize
2087 * @vectors: allotted vector count for descriptor rings
9a799d71 2088 *
021230d4
AV		 2089 * This function maps descriptor rings to the queue-specific vectors
2090 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2091 * one vector per ring/queue, but on a constrained vector budget, we
2092 * group the rings as "efficiently" as possible. You would add new
2093 * mapping configurations in here.
9a799d71 2094 **/
021230d4 2095static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2096 int vectors)
021230d4
AV		 2097{
2098 int v_start = 0;
2099 int rxr_idx = 0, txr_idx = 0;
2100 int rxr_remaining = adapter->num_rx_queues;
2101 int txr_remaining = adapter->num_tx_queues;
2102 int i, j;
2103 int rqpv, tqpv;
2104 int err = 0;
2105
2106 /* No mapping required if MSI-X is disabled. */
2107 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2108 goto out;
9a799d71 2109
021230d4
AV		 2110 /*
2111 * The ideal configuration...
2112 * We have enough vectors to map one per queue.
2113 */
2114 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2115 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2116 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2117
021230d4
AV		 2118 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2119 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2120
9a799d71 2121 goto out;
021230d4 2122 }
9a799d71 2123
021230d4
AV		 2124 /*
2125 * If we don't have enough vectors for a 1-to-1
2126 * mapping, we'll have to group them so there are
2127 * multiple queues per vector.
2128 */
2129 /* Re-adjusting *qpv takes care of the remainder. */
2130 for (i = v_start; i < vectors; i++) {
2131 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2132 for (j = 0; j < rqpv; j++) {
2133 map_vector_to_rxq(adapter, i, rxr_idx);
2134 rxr_idx++;
2135 rxr_remaining--;
2136 }
2137 }
2138 for (i = v_start; i < vectors; i++) {
2139 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2140 for (j = 0; j < tqpv; j++) {
2141 map_vector_to_txq(adapter, i, txr_idx);
2142 txr_idx++;
2143 txr_remaining--;
9a799d71 2144 }
9a799d71
AK		 2145 }
2146
021230d4
AV		 2147out:
2148 return err;
2149}
2150
2151/**
2152 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2153 * @adapter: board private structure
2154 *
2155 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2156 * interrupts from the kernel.
2157 **/
2158static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2159{
2160 struct net_device *netdev = adapter->netdev;
2161 irqreturn_t (*handler)(int, void *);
2162 int i, vector, q_vectors, err;
e8e9f696 2163 int ri = 0, ti = 0;
021230d4
AV		 2164
2165 /* Decrement for Other and TCP Timer vectors */
2166 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2167
2168 /* Map the Tx/Rx rings to the vectors we were allotted. */
2169 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2170 if (err)
2171 goto out;
2172
2173#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2174 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2175 &ixgbe_msix_clean_many)
021230d4 2176 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2177 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2178
e8e9f696 2179 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2180 sprintf(adapter->name[vector], "%s-%s-%d",
2181 netdev->name, "rx", ri++);
e8e9f696 2182 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2183 sprintf(adapter->name[vector], "%s-%s-%d",
2184 netdev->name, "tx", ti++);
e8e9f696 2185 } else
cb13fc20
RO		 2186 sprintf(adapter->name[vector], "%s-%s-%d",
2187 netdev->name, "TxRx", vector);
2188
021230d4 2189 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2190 handler, 0, adapter->name[vector],
2191 adapter->q_vector[vector]);
9a799d71 2192 if (err) {
396e799c 2193 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2194 "Error: %d\n", err);
021230d4 2195 goto free_queue_irqs;
9a799d71 2196 }
9a799d71
AK		 2197 }
2198
021230d4
AV		 2199 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2200 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2201 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2202 if (err) {
396e799c 2203 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2204 goto free_queue_irqs;
9a799d71
AK		 2205 }
2206
9a799d71
AK		 2207 return 0;
2208
021230d4
AV		 2209free_queue_irqs:
2210 for (i = vector - 1; i >= 0; i--)
2211 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2212 adapter->q_vector[i]);
021230d4
AV		 2213 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2214 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2215 kfree(adapter->msix_entries);
2216 adapter->msix_entries = NULL;
021230d4 2217out:
9a799d71
AK		 2218 return err;
2219}
2220
f494e8fa
AV		 2221static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2222{
7a921c93 2223 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2224 u8 current_itr;
2225 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2226 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2227 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2228
30efa5a3 2229 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2230 q_vector->tx_itr,
2231 tx_ring->total_packets,
2232 tx_ring->total_bytes);
30efa5a3 2233 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2234 q_vector->rx_itr,
2235 rx_ring->total_packets,
2236 rx_ring->total_bytes);
f494e8fa 2237
30efa5a3 2238 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2239
2240 switch (current_itr) {
2241 /* counts and packets in update_itr are dependent on these numbers */
2242 case lowest_latency:
2243 new_itr = 100000;
2244 break;
2245 case low_latency:
2246 new_itr = 20000; /* aka hwitr = ~200 */
2247 break;
2248 case bulk_latency:
2249 new_itr = 8000;
2250 break;
2251 default:
2252 break;
2253 }
2254
2255 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2256 /* do an exponential smoothing */
2257 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2258
2259 /* save the algorithm value here, not the smoothed one */
2260 q_vector->eitr = new_itr;
fe49f04a
AD		 2261
2262 ixgbe_write_eitr(q_vector);
f494e8fa 2263 }
f494e8fa
AV		 2264}
2265
79aefa45
AD		 2266/**
2267 * ixgbe_irq_enable - Enable default interrupt generation settings
2268 * @adapter: board private structure
2269 **/
6af3b9eb
ET		 2270static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2271 bool flush)
79aefa45
AD		 2272{
2273 u32 mask;
835462fc
NS		 2274
2275 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2276 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2277 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2278 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2279 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2280 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2281 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2282 mask |= IXGBE_EIMS_GPI_SDP1;
2283 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2284 if (adapter->num_vfs)
2285 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2286 }
c4cf55e5
PWJ		 2287 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2288 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2289 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2290
79aefa45 2291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2292 if (queues)
2293 ixgbe_irq_enable_queues(adapter, ~0);
2294 if (flush)
2295 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2296
2297 if (adapter->num_vfs > 32) {
2298 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2299 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2300 }
79aefa45 2301}
021230d4 2302
9a799d71 2303/**
021230d4 2304 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2305 * @irq: interrupt number
2306 * @data: pointer to a network interface device structure
9a799d71
AK		 2307 **/
2308static irqreturn_t ixgbe_intr(int irq, void *data)
2309{
2310 struct net_device *netdev = data;
2311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2312 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2313 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2314 u32 eicr;
2315
54037505 2316 /*
6af3b9eb 2317 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2318 * before the read of EICR.
2319 */
2320 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2321
021230d4
AV		 2322 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2323 * therefore no explict interrupt disable is necessary */
2324 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2325 if (!eicr) {
6af3b9eb
ET		 2326 /*
2327 * shared interrupt alert!
f47cf66e 2328 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2329 * have disabled interrupts due to EIAM
2330 * finish the workaround of silicon errata on 82598. Unmask
2331 * the interrupt that we masked before the EICR read.
2332 */
2333 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2334 ixgbe_irq_enable(adapter, true, true);
9a799d71 2335 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2336 }
9a799d71 2337
cf8280ee
JB		 2338 if (eicr & IXGBE_EICR_LSC)
2339 ixgbe_check_lsc(adapter);
021230d4 2340
e8e26350
PW		 2341 if (hw->mac.type == ixgbe_mac_82599EB)
2342 ixgbe_check_sfp_event(adapter, eicr);
2343
0befdb3e 2344 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2345 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2346 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2347 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2348
7a921c93 2349 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2350 adapter->tx_ring[0]->total_packets = 0;
2351 adapter->tx_ring[0]->total_bytes = 0;
2352 adapter->rx_ring[0]->total_packets = 0;
2353 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2354 /* would disable interrupts here but EIAM disabled it */
7a921c93 2355 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2356 }
2357
6af3b9eb
ET		 2358 /*
2359 * re-enable link(maybe) and non-queue interrupts, no flush.
2360 * ixgbe_poll will re-enable the queue interrupts
2361 */
2362
2363 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2364 ixgbe_irq_enable(adapter, false, false);
2365
9a799d71
AK		 2366 return IRQ_HANDLED;
2367}
2368
021230d4
AV		 2369static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2370{
2371 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2372
2373 for (i = 0; i < q_vectors; i++) {
7a921c93 2374 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2375 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2376 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2377 q_vector->rxr_count = 0;
2378 q_vector->txr_count = 0;
2379 }
2380}
2381
9a799d71
AK		 2382/**
2383 * ixgbe_request_irq - initialize interrupts
2384 * @adapter: board private structure
2385 *
2386 * Attempts to configure interrupts using the best available
2387 * capabilities of the hardware and kernel.
2388 **/
021230d4 2389static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2390{
2391 struct net_device *netdev = adapter->netdev;
021230d4 2392 int err;
9a799d71 2393
021230d4
AV		 2394 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2395 err = ixgbe_request_msix_irqs(adapter);
2396 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2397 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2398 netdev->name, netdev);
021230d4 2399 } else {
a0607fd3 2400 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2401 netdev->name, netdev);
9a799d71
AK		 2402 }
2403
9a799d71 2404 if (err)
396e799c 2405 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2406
9a799d71
AK		 2407 return err;
2408}
2409
2410static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2411{
2412 struct net_device *netdev = adapter->netdev;
2413
2414 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2415 int i, q_vectors;
9a799d71 2416
021230d4
AV		 2417 q_vectors = adapter->num_msix_vectors;
2418
2419 i = q_vectors - 1;
9a799d71 2420 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2421
021230d4
AV		 2422 i--;
2423 for (; i >= 0; i--) {
2424 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2425 adapter->q_vector[i]);
021230d4
AV		 2426 }
2427
2428 ixgbe_reset_q_vectors(adapter);
2429 } else {
2430 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2431 }
2432}
2433
22d5a71b
JB		 2434/**
2435 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2436 * @adapter: board private structure
2437 **/
2438static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2439{
835462fc
NS		 2440 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2442 } else {
2443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2446 if (adapter->num_vfs > 32)
2447 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2448 }
2449 IXGBE_WRITE_FLUSH(&adapter->hw);
2450 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2451 int i;
2452 for (i = 0; i < adapter->num_msix_vectors; i++)
2453 synchronize_irq(adapter->msix_entries[i].vector);
2454 } else {
2455 synchronize_irq(adapter->pdev->irq);
2456 }
2457}
2458
9a799d71
AK		 2459/**
2460 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2461 *
2462 **/
2463static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2464{
9a799d71
AK		 2465 struct ixgbe_hw *hw = &adapter->hw;
2466
021230d4 2467 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2468 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2469
e8e26350
PW		 2470 ixgbe_set_ivar(adapter, 0, 0, 0);
2471 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2472
2473 map_vector_to_rxq(adapter, 0, 0);
2474 map_vector_to_txq(adapter, 0, 0);
2475
396e799c 2476 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2477}
2478
43e69bf0
AD		 2479/**
2480 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2481 * @adapter: board private structure
2482 * @ring: structure containing ring specific data
2483 *
2484 * Configure the Tx descriptor ring after a reset.
2485 **/
84418e3b
AD		 2486void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2487 struct ixgbe_ring *ring)
43e69bf0
AD		 2488{
2489 struct ixgbe_hw *hw = &adapter->hw;
2490 u64 tdba = ring->dma;
2f1860b8
AD		 2491 int wait_loop = 10;
2492 u32 txdctl;
43e69bf0
AD		 2493 u16 reg_idx = ring->reg_idx;
2494
2f1860b8
AD		 2495 /* disable queue to avoid issues while updating state */
2496 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2497 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2498 txdctl & ~IXGBE_TXDCTL_ENABLE);
2499 IXGBE_WRITE_FLUSH(hw);
2500
43e69bf0 2501 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2502 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2503 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2504 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2505 ring->count * sizeof(union ixgbe_adv_tx_desc));
2506 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2507 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2508 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2509
2f1860b8
AD		 2510 /* configure fetching thresholds */
2511 if (adapter->rx_itr_setting == 0) {
2512 /* cannot set wthresh when itr==0 */
2513 txdctl &= ~0x007F0000;
2514 } else {
2515 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2516 txdctl |= (8 << 16);
2517 }
2518 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2519 /* PThresh workaround for Tx hang with DFP enabled. */
2520 txdctl |= 32;
2521 }
2522
2523 /* reinitialize flowdirector state */
7d637bcc 2524 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2f1860b8
AD		 2525
2526 /* enable queue */
2527 txdctl |= IXGBE_TXDCTL_ENABLE;
2528 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2529
2530 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2531 if (hw->mac.type == ixgbe_mac_82598EB &&
2532 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2533 return;
2534
2535 /* poll to verify queue is enabled */
2536 do {
2537 msleep(1);
2538 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2539 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2540 if (!wait_loop)
2541 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2542}
2543
120ff942
AD		 2544static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2545{
2546 struct ixgbe_hw *hw = &adapter->hw;
2547 u32 rttdcs;
2548 u32 mask;
2549
2550 if (hw->mac.type == ixgbe_mac_82598EB)
2551 return;
2552
2553 /* disable the arbiter while setting MTQC */
2554 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2555 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2556 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2557
2558 /* set transmit pool layout */
2559 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2560 switch (adapter->flags & mask) {
2561
2562 case (IXGBE_FLAG_SRIOV_ENABLED):
2563 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2564 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2565 break;
2566
2567 case (IXGBE_FLAG_DCB_ENABLED):
2568 /* We enable 8 traffic classes, DCB only */
2569 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2570 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2571 break;
2572
2573 default:
2574 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2575 break;
2576 }
2577
2578 /* re-enable the arbiter */
2579 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2580 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2581}
2582
9a799d71 2583/**
3a581073 2584 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2585 * @adapter: board private structure
2586 *
2587 * Configure the Tx unit of the MAC after a reset.
2588 **/
2589static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2590{
2f1860b8
AD		 2591 struct ixgbe_hw *hw = &adapter->hw;
2592 u32 dmatxctl;
43e69bf0 2593 u32 i;
9a799d71 2594
2f1860b8
AD		 2595 ixgbe_setup_mtqc(adapter);
2596
2597 if (hw->mac.type != ixgbe_mac_82598EB) {
2598 /* DMATXCTL.EN must be before Tx queues are enabled */
2599 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2600 dmatxctl |= IXGBE_DMATXCTL_TE;
2601 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2602 }
2603
9a799d71 2604 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2605 for (i = 0; i < adapter->num_tx_queues; i++)
2606 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2607}
2608
e8e26350 2609#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2610
a6616b42 2611static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2612 struct ixgbe_ring *rx_ring)
cc41ac7c 2613{
cc41ac7c 2614 u32 srrctl;
a6616b42 2615 int index;
0cefafad 2616 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2617
a6616b42
YZ		 2618 index = rx_ring->reg_idx;
2619 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2620 unsigned long mask;
0cefafad 2621 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2622 index = index & mask;
cc41ac7c 2623 }
cc41ac7c
JB		 2624 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2625
2626 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2627 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2628 if (adapter->num_vfs)
2629 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2630
afafd5b0
AD		 2631 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2632 IXGBE_SRRCTL_BSIZEHDR_MASK;
2633
7d637bcc 2634 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2635#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2636 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2637#else
2638 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2639#endif
cc41ac7c 2640 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2641 } else {
afafd5b0
AD		 2642 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2643 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2644 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2645 }
e8e26350 2646
cc41ac7c
JB		 2647 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2648}
9a799d71 2649
05abb126 2650static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2651{
05abb126
AD		 2652 struct ixgbe_hw *hw = &adapter->hw;
2653 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2654 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2655 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2656 u32 mrqc = 0, reta = 0;
2657 u32 rxcsum;
2658 int i, j;
0cefafad
JB		 2659 int mask;
2660
05abb126
AD		 2661 /* Fill out hash function seeds */
2662 for (i = 0; i < 10; i++)
2663 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2664
2665 /* Fill out redirection table */
2666 for (i = 0, j = 0; i < 128; i++, j++) {
2667 if (j == adapter->ring_feature[RING_F_RSS].indices)
2668 j = 0;
2669 /* reta = 4-byte sliding window of
2670 * 0x00..(indices-1)(indices-1)00..etc. */
2671 reta = (reta << 8) | (j * 0x11);
2672 if ((i & 3) == 3)
2673 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2674 }
0cefafad 2675
05abb126
AD		 2676 /* Disable indicating checksum in descriptor, enables RSS hash */
2677 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2678 rxcsum |= IXGBE_RXCSUM_PCSD;
2679 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2680
2681 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2682 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2683 else
2684 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2685#ifdef CONFIG_IXGBE_DCB
05abb126 2686 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2687#endif
05abb126
AD		 2688 | IXGBE_FLAG_SRIOV_ENABLED
2689 );
0cefafad
JB		 2690
2691 switch (mask) {
2692 case (IXGBE_FLAG_RSS_ENABLED):
2693 mrqc = IXGBE_MRQC_RSSEN;
2694 break;
1cdd1ec8
GR		 2695 case (IXGBE_FLAG_SRIOV_ENABLED):
2696 mrqc = IXGBE_MRQC_VMDQEN;
2697 break;
0cefafad
JB		 2698#ifdef CONFIG_IXGBE_DCB
2699 case (IXGBE_FLAG_DCB_ENABLED):
2700 mrqc = IXGBE_MRQC_RT8TCEN;
2701 break;
2702#endif /* CONFIG_IXGBE_DCB */
2703 default:
2704 break;
2705 }
2706
05abb126
AD		 2707 /* Perform hash on these packet types */
2708 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2709 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2710 | IXGBE_MRQC_RSS_FIELD_IPV6
2711 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2712
2713 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2714}
2715
bb5a9ad2
NS		 2716/**
2717 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2718 * @adapter: address of board private structure
2719 * @index: index of ring to set
bb5a9ad2 2720 **/
7367096a
AD		 2721static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2722 struct ixgbe_ring *ring)
bb5a9ad2 2723{
bb5a9ad2 2724 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2725 u32 rscctrl;
edd2ea55 2726 int rx_buf_len;
7367096a
AD		 2727 u16 reg_idx = ring->reg_idx;
2728
7d637bcc 2729 if (!ring_is_rsc_enabled(ring))
7367096a 2730 return;
bb5a9ad2 2731
7367096a
AD		 2732 rx_buf_len = ring->rx_buf_len;
2733 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2734 rscctrl |= IXGBE_RSCCTL_RSCEN;
2735 /*
2736 * we must limit the number of descriptors so that the
2737 * total size of max desc * buf_len is not greater
2738 * than 65535
2739 */
7d637bcc 2740 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2741#if (MAX_SKB_FRAGS > 16)
2742 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2743#elif (MAX_SKB_FRAGS > 8)
2744 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2745#elif (MAX_SKB_FRAGS > 4)
2746 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2747#else
2748 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2749#endif
2750 } else {
2751 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2752 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2753 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2754 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2755 else
2756 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2757 }
7367096a 2758 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2759}
2760
9e10e045
AD		 2761/**
2762 * ixgbe_set_uta - Set unicast filter table address
2763 * @adapter: board private structure
2764 *
2765 * The unicast table address is a register array of 32-bit registers.
2766 * The table is meant to be used in a way similar to how the MTA is used
2767 * however due to certain limitations in the hardware it is necessary to
2768 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2769 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2770 **/
2771static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2772{
2773 struct ixgbe_hw *hw = &adapter->hw;
2774 int i;
2775
2776 /* The UTA table only exists on 82599 hardware and newer */
2777 if (hw->mac.type < ixgbe_mac_82599EB)
2778 return;
2779
2780 /* we only need to do this if VMDq is enabled */
2781 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2782 return;
2783
2784 for (i = 0; i < 128; i++)
2785 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2786}
2787
2788#define IXGBE_MAX_RX_DESC_POLL 10
2789static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2790 struct ixgbe_ring *ring)
2791{
2792 struct ixgbe_hw *hw = &adapter->hw;
2793 int reg_idx = ring->reg_idx;
2794 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2795 u32 rxdctl;
2796
2797 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2798 if (hw->mac.type == ixgbe_mac_82598EB &&
2799 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2800 return;
2801
2802 do {
2803 msleep(1);
2804 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2805 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2806
2807 if (!wait_loop) {
2808 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2809 "the polling period\n", reg_idx);
2810 }
2811}
2812
84418e3b
AD		 2813void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2814 struct ixgbe_ring *ring)
acd37177
AD		 2815{
2816 struct ixgbe_hw *hw = &adapter->hw;
2817 u64 rdba = ring->dma;
9e10e045 2818 u32 rxdctl;
acd37177
AD		 2819 u16 reg_idx = ring->reg_idx;
2820
9e10e045
AD		 2821 /* disable queue to avoid issues while updating state */
2822 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2823 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2824 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2825 IXGBE_WRITE_FLUSH(hw);
2826
acd37177
AD		 2827 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2828 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2829 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2830 ring->count * sizeof(union ixgbe_adv_rx_desc));
2831 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2832 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2833 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2834
2835 ixgbe_configure_srrctl(adapter, ring);
2836 ixgbe_configure_rscctl(adapter, ring);
2837
2838 if (hw->mac.type == ixgbe_mac_82598EB) {
2839 /*
2840 * enable cache line friendly hardware writes:
2841 * PTHRESH=32 descriptors (half the internal cache),
2842 * this also removes ugly rx_no_buffer_count increment
2843 * HTHRESH=4 descriptors (to minimize latency on fetch)
2844 * WTHRESH=8 burst writeback up to two cache lines
2845 */
2846 rxdctl &= ~0x3FFFFF;
2847 rxdctl |= 0x080420;
2848 }
2849
2850 /* enable receive descriptor ring */
2851 rxdctl |= IXGBE_RXDCTL_ENABLE;
2852 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2853
2854 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 2855 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2856}
2857
48654521
AD		 2858static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2859{
2860 struct ixgbe_hw *hw = &adapter->hw;
2861 int p;
2862
2863 /* PSRTYPE must be initialized in non 82598 adapters */
2864 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2865 IXGBE_PSRTYPE_UDPHDR |
2866 IXGBE_PSRTYPE_IPV4HDR |
48654521 2867 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2868 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2869
2870 if (hw->mac.type == ixgbe_mac_82598EB)
2871 return;
2872
2873 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2874 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2875
2876 for (p = 0; p < adapter->num_rx_pools; p++)
2877 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2878 psrtype);
2879}
2880
f5b4a52e
AD		 2881static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2882{
2883 struct ixgbe_hw *hw = &adapter->hw;
2884 u32 gcr_ext;
2885 u32 vt_reg_bits;
2886 u32 reg_offset, vf_shift;
2887 u32 vmdctl;
2888
2889 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2890 return;
2891
2892 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2893 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2894 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2895 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2896
2897 vf_shift = adapter->num_vfs % 32;
2898 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2899
2900 /* Enable only the PF's pool for Tx/Rx */
2901 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2902 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2903 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2904 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2905 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2906
2907 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2908 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2909
2910 /*
2911 * Set up VF register offsets for selected VT Mode,
2912 * i.e. 32 or 64 VFs for SR-IOV
2913 */
2914 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2915 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2916 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2917 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2918
2919 /* enable Tx loopback for VF/PF communication */
2920 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2921}
2922
477de6ed 2923static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2924{
9a799d71
AK		 2925 struct ixgbe_hw *hw = &adapter->hw;
2926 struct net_device *netdev = adapter->netdev;
2927 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2928 int rx_buf_len;
477de6ed
AD		 2929 struct ixgbe_ring *rx_ring;
2930 int i;
2931 u32 mhadd, hlreg0;
48654521 2932
9a799d71 2933 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2934 /* Do not use packet split if we're in SR-IOV Mode */
2935 if (!adapter->num_vfs)
2936 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2937
2938 /* Set the RX buffer length according to the mode */
2939 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2940 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2941 } else {
0c19d6af 2942 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2943 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2944 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2945 else
477de6ed 2946 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2947 }
2948
63f39bd1 2949#ifdef IXGBE_FCOE
477de6ed
AD		 2950 /* adjust max frame to be able to do baby jumbo for FCoE */
2951 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2952 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2953 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2954
477de6ed
AD		 2955#endif /* IXGBE_FCOE */
2956 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2957 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2958 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2959 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2960
2961 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2962 }
2963
2964 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2965 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2966 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2967 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2968
0cefafad
JB		 2969 /*
2970 * Setup the HW Rx Head and Tail Descriptor Pointers and
2971 * the Base and Length of the Rx Descriptor Ring
2972 */
9a799d71 2973 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2974 rx_ring = adapter->rx_ring[i];
a6616b42 2975 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2976
6e455b89 2977 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2978 set_ring_ps_enabled(rx_ring);
2979 else
2980 clear_ring_ps_enabled(rx_ring);
2981
2982 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2983 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2984 else
7d637bcc 2985 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2986
63f39bd1 2987#ifdef IXGBE_FCOE
e8e9f696 2988 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2989 struct ixgbe_ring_feature *f;
2990 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2991 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2992 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2993 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2994 rx_ring->rx_buf_len =
e8e9f696 2995 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2996 } else if (!ring_is_rsc_enabled(rx_ring) &&
2997 !ring_is_ps_enabled(rx_ring)) {
2998 rx_ring->rx_buf_len =
2999 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3000 }
63f39bd1 3001 }
63f39bd1 3002#endif /* IXGBE_FCOE */
477de6ed
AD		 3003 }
3004
3005}
3006
7367096a
AD		 3007static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3008{
3009 struct ixgbe_hw *hw = &adapter->hw;
3010 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3011
3012 switch (hw->mac.type) {
3013 case ixgbe_mac_82598EB:
3014 /*
3015 * For VMDq support of different descriptor types or
3016 * buffer sizes through the use of multiple SRRCTL
3017 * registers, RDRXCTL.MVMEN must be set to 1
3018 *
3019 * also, the manual doesn't mention it clearly but DCA hints
3020 * will only use queue 0's tags unless this bit is set. Side
3021 * effects of setting this bit are only that SRRCTL must be
3022 * fully programmed [0..15]
3023 */
3024 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3025 break;
3026 case ixgbe_mac_82599EB:
3027 /* Disable RSC for ACK packets */
3028 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3029 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3030 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3031 /* hardware requires some bits to be set by default */
3032 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3033 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3034 break;
3035 default:
3036 /* We should do nothing since we don't know this hardware */
3037 return;
3038 }
3039
3040 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3041}
3042
477de6ed
AD		 3043/**
3044 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3045 * @adapter: board private structure
3046 *
3047 * Configure the Rx unit of the MAC after a reset.
3048 **/
3049static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3052 int i;
3053 u32 rxctrl;
477de6ed
AD		 3054
3055 /* disable receives while setting up the descriptors */
3056 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3057 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3058
3059 ixgbe_setup_psrtype(adapter);
7367096a 3060 ixgbe_setup_rdrxctl(adapter);
477de6ed 3061
9e10e045 3062 /* Program registers for the distribution of queues */
f5b4a52e 3063 ixgbe_setup_mrqc(adapter);
f5b4a52e 3064
9e10e045
AD		 3065 ixgbe_set_uta(adapter);
3066
477de6ed
AD		 3067 /* set_rx_buffer_len must be called before ring initialization */
3068 ixgbe_set_rx_buffer_len(adapter);
3069
3070 /*
3071 * Setup the HW Rx Head and Tail Descriptor Pointers and
3072 * the Base and Length of the Rx Descriptor Ring
3073 */
9e10e045
AD		 3074 for (i = 0; i < adapter->num_rx_queues; i++)
3075 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3076
9e10e045
AD		 3077 /* disable drop enable for 82598 parts */
3078 if (hw->mac.type == ixgbe_mac_82598EB)
3079 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3080
3081 /* enable all receives */
3082 rxctrl |= IXGBE_RXCTRL_RXEN;
3083 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3084}
3085
068c89b0
DS		 3086static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3087{
3088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3089 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3090 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3091
3092 /* add VID to filter table */
1ada1b1b 3093 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3094 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3095}
3096
3097static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3098{
3099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3100 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3101 int pool_ndx = adapter->num_vfs;
068c89b0 3102
068c89b0 3103 /* remove VID from filter table */
1ada1b1b 3104 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3105 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3106}
3107
5f6c0181
JB		 3108/**
3109 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3110 * @adapter: driver data
3111 */
3112static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3113{
3114 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3115 u32 vlnctrl;
3116
3117 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3118 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3119 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3120}
3121
3122/**
3123 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3124 * @adapter: driver data
3125 */
3126static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3127{
3128 struct ixgbe_hw *hw = &adapter->hw;
3129 u32 vlnctrl;
3130
3131 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3132 vlnctrl |= IXGBE_VLNCTRL_VFE;
3133 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3135}
3136
3137/**
3138 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3139 * @adapter: driver data
3140 */
3141static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3142{
3143 struct ixgbe_hw *hw = &adapter->hw;
3144 u32 vlnctrl;
5f6c0181
JB		 3145 int i, j;
3146
3147 switch (hw->mac.type) {
3148 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3149 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3150 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3151 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3152 break;
3153 case ixgbe_mac_82599EB:
5f6c0181
JB		 3154 for (i = 0; i < adapter->num_rx_queues; i++) {
3155 j = adapter->rx_ring[i]->reg_idx;
3156 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3157 vlnctrl &= ~IXGBE_RXDCTL_VME;
3158 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3159 }
3160 break;
3161 default:
3162 break;
3163 }
3164}
3165
3166/**
f62bbb5e 3167 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3168 * @adapter: driver data
3169 */
f62bbb5e 3170static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3171{
3172 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3173 u32 vlnctrl;
5f6c0181
JB		 3174 int i, j;
3175
3176 switch (hw->mac.type) {
3177 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3178 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3179 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3180 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3181 break;
3182 case ixgbe_mac_82599EB:
5f6c0181
JB		 3183 for (i = 0; i < adapter->num_rx_queues; i++) {
3184 j = adapter->rx_ring[i]->reg_idx;
3185 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3186 vlnctrl |= IXGBE_RXDCTL_VME;
3187 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3188 }
3189 break;
3190 default:
3191 break;
3192 }
3193}
3194
9a799d71
AK		 3195static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3196{
f62bbb5e 3197 u16 vid;
9a799d71 3198
f62bbb5e
JG		 3199 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3200
3201 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3202 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3203}
3204
2850062a
AD		 3205/**
3206 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3207 * @netdev: network interface device structure
3208 *
3209 * Writes unicast address list to the RAR table.
3210 * Returns: -ENOMEM on failure/insufficient address space
3211 * 0 on no addresses written
3212 * X on writing X addresses to the RAR table
3213 **/
3214static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3215{
3216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3217 struct ixgbe_hw *hw = &adapter->hw;
3218 unsigned int vfn = adapter->num_vfs;
3219 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3220 int count = 0;
3221
3222 /* return ENOMEM indicating insufficient memory for addresses */
3223 if (netdev_uc_count(netdev) > rar_entries)
3224 return -ENOMEM;
3225
3226 if (!netdev_uc_empty(netdev) && rar_entries) {
3227 struct netdev_hw_addr *ha;
3228 /* return error if we do not support writing to RAR table */
3229 if (!hw->mac.ops.set_rar)
3230 return -ENOMEM;
3231
3232 netdev_for_each_uc_addr(ha, netdev) {
3233 if (!rar_entries)
3234 break;
3235 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3236 vfn, IXGBE_RAH_AV);
3237 count++;
3238 }
3239 }
3240 /* write the addresses in reverse order to avoid write combining */
3241 for (; rar_entries > 0 ; rar_entries--)
3242 hw->mac.ops.clear_rar(hw, rar_entries);
3243
3244 return count;
3245}
3246
9a799d71 3247/**
2c5645cf 3248 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3249 * @netdev: network interface device structure
3250 *
2c5645cf
CL		 3251 * The set_rx_method entry point is called whenever the unicast/multicast
3252 * address list or the network interface flags are updated. This routine is
3253 * responsible for configuring the hardware for proper unicast, multicast and
3254 * promiscuous mode.
9a799d71 3255 **/
7f870475 3256void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3257{
3258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3259 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3260 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3261 int count;
9a799d71
AK		 3262
3263 /* Check for Promiscuous and All Multicast modes */
3264
3265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3266
f5dc442b
AD		 3267 /* set all bits that we expect to always be set */
3268 fctrl |= IXGBE_FCTRL_BAM;
3269 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3270 fctrl |= IXGBE_FCTRL_PMCF;
3271
2850062a
AD		 3272 /* clear the bits we are changing the status of */
3273 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3274
9a799d71 3275 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3276 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3277 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3278 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3279 /* don't hardware filter vlans in promisc mode */
3280 ixgbe_vlan_filter_disable(adapter);
9a799d71 3281 } else {
746b9f02
PM		 3282 if (netdev->flags & IFF_ALLMULTI) {
3283 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3284 vmolr |= IXGBE_VMOLR_MPE;
3285 } else {
3286 /*
3287 * Write addresses to the MTA, if the attempt fails
3288 * then we should just turn on promiscous mode so
3289 * that we can at least receive multicast traffic
3290 */
3291 hw->mac.ops.update_mc_addr_list(hw, netdev);
3292 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3293 }
5f6c0181 3294 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3295 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3296 /*
3297 * Write addresses to available RAR registers, if there is not
3298 * sufficient space to store all the addresses then enable
3299 * unicast promiscous mode
3300 */
3301 count = ixgbe_write_uc_addr_list(netdev);
3302 if (count < 0) {
3303 fctrl |= IXGBE_FCTRL_UPE;
3304 vmolr |= IXGBE_VMOLR_ROPE;
3305 }
9a799d71
AK		 3306 }
3307
2850062a 3308 if (adapter->num_vfs) {
1cdd1ec8 3309 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3310 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3311 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3312 IXGBE_VMOLR_ROPE);
3313 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3314 }
3315
3316 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3317
3318 if (netdev->features & NETIF_F_HW_VLAN_RX)
3319 ixgbe_vlan_strip_enable(adapter);
3320 else
3321 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3322}
3323
021230d4
AV		 3324static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3325{
3326 int q_idx;
3327 struct ixgbe_q_vector *q_vector;
3328 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3329
3330 /* legacy and MSI only use one vector */
3331 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3332 q_vectors = 1;
3333
3334 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3335 struct napi_struct *napi;
7a921c93 3336 q_vector = adapter->q_vector[q_idx];
f0848276 3337 napi = &q_vector->napi;
91281fd3
AD		 3338 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3339 if (!q_vector->rxr_count || !q_vector->txr_count) {
3340 if (q_vector->txr_count == 1)
3341 napi->poll = &ixgbe_clean_txonly;
3342 else if (q_vector->rxr_count == 1)
3343 napi->poll = &ixgbe_clean_rxonly;
3344 }
3345 }
f0848276
JB		 3346
3347 napi_enable(napi);
021230d4
AV		 3348 }
3349}
3350
3351static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3352{
3353 int q_idx;
3354 struct ixgbe_q_vector *q_vector;
3355 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3356
3357 /* legacy and MSI only use one vector */
3358 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3359 q_vectors = 1;
3360
3361 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3362 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3363 napi_disable(&q_vector->napi);
3364 }
3365}
3366
7a6b6f51 3367#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3368/*
3369 * ixgbe_configure_dcb - Configure DCB hardware
3370 * @adapter: ixgbe adapter struct
3371 *
3372 * This is called by the driver on open to configure the DCB hardware.
3373 * This is also called by the gennetlink interface when reconfiguring
3374 * the DCB state.
3375 */
3376static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3377{
3378 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3379 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3380
67ebd791
AD		 3381 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3382 if (hw->mac.type == ixgbe_mac_82598EB)
3383 netif_set_gso_max_size(adapter->netdev, 65536);
3384 return;
3385 }
3386
3387 if (hw->mac.type == ixgbe_mac_82598EB)
3388 netif_set_gso_max_size(adapter->netdev, 32768);
3389
9806307a
JF		 3390#ifdef CONFIG_FCOE
3391 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3392 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3393#endif
3394
80ab193d 3395 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3396 DCB_TX_CONFIG);
80ab193d 3397 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3398 DCB_RX_CONFIG);
2f90b865 3399
2f90b865 3400 /* Enable VLAN tag insert/strip */
f62bbb5e 3401 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3402
2f90b865 3403 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3404
3405 /* reconfigure the hardware */
3406 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
2f90b865
AD		 3407}
3408
3409#endif
9a799d71
AK		 3410static void ixgbe_configure(struct ixgbe_adapter *adapter)
3411{
3412 struct net_device *netdev = adapter->netdev;
c4cf55e5 3413 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3414 int i;
3415
7a6b6f51 3416#ifdef CONFIG_IXGBE_DCB
67ebd791 3417 ixgbe_configure_dcb(adapter);
2f90b865 3418#endif
9a799d71 3419
f62bbb5e
JG		 3420 ixgbe_set_rx_mode(netdev);
3421 ixgbe_restore_vlan(adapter);
3422
eacd73f7
YZ		 3423#ifdef IXGBE_FCOE
3424 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3425 ixgbe_configure_fcoe(adapter);
3426
3427#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3428 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3429 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3430 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3431 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3432 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3433 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3434 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3435 }
933d41f1 3436 ixgbe_configure_virtualization(adapter);
c4cf55e5 3437
9a799d71
AK		 3438 ixgbe_configure_tx(adapter);
3439 ixgbe_configure_rx(adapter);
9a799d71
AK		 3440}
3441
e8e26350
PW		 3442static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3443{
3444 switch (hw->phy.type) {
3445 case ixgbe_phy_sfp_avago:
3446 case ixgbe_phy_sfp_ftl:
3447 case ixgbe_phy_sfp_intel:
3448 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3449 case ixgbe_phy_sfp_passive_tyco:
3450 case ixgbe_phy_sfp_passive_unknown:
3451 case ixgbe_phy_sfp_active_unknown:
3452 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3453 return true;
3454 default:
3455 return false;
3456 }
3457}
3458
0ecc061d 3459/**
e8e26350
PW		 3460 * ixgbe_sfp_link_config - set up SFP+ link
3461 * @adapter: pointer to private adapter struct
3462 **/
3463static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3464{
3465 struct ixgbe_hw *hw = &adapter->hw;
3466
3467 if (hw->phy.multispeed_fiber) {
3468 /*
3469 * In multispeed fiber setups, the device may not have
3470 * had a physical connection when the driver loaded.
3471 * If that's the case, the initial link configuration
3472 * couldn't get the MAC into 10G or 1G mode, so we'll
3473 * never have a link status change interrupt fire.
3474 * We need to try and force an autonegotiation
3475 * session, then bring up link.
3476 */
3477 hw->mac.ops.setup_sfp(hw);
3478 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3479 schedule_work(&adapter->multispeed_fiber_task);
3480 } else {
3481 /*
3482 * Direct Attach Cu and non-multispeed fiber modules
3483 * still need to be configured properly prior to
3484 * attempting link.
3485 */
3486 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3487 schedule_work(&adapter->sfp_config_module_task);
3488 }
3489}
3490
3491/**
3492 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3493 * @hw: pointer to private hardware struct
3494 *
3495 * Returns 0 on success, negative on failure
3496 **/
e8e26350 3497static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3498{
3499 u32 autoneg;
8620a103 3500 bool negotiation, link_up = false;
0ecc061d
PWJ		 3501 u32 ret = IXGBE_ERR_LINK_SETUP;
3502
3503 if (hw->mac.ops.check_link)
3504 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3505
3506 if (ret)
3507 goto link_cfg_out;
3508
3509 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3510 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3511 &negotiation);
0ecc061d
PWJ		 3512 if (ret)
3513 goto link_cfg_out;
3514
8620a103
MC		 3515 if (hw->mac.ops.setup_link)
3516 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3517link_cfg_out:
3518 return ret;
3519}
3520
a34bcfff 3521static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3522{
9a799d71 3523 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3524 u32 gpie = 0;
9a799d71 3525
9b471446 3526 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3527 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3528 IXGBE_GPIE_OCD;
3529 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3530 /*
3531 * use EIAM to auto-mask when MSI-X interrupt is asserted
3532 * this saves a register write for every interrupt
3533 */
3534 switch (hw->mac.type) {
3535 case ixgbe_mac_82598EB:
3536 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3537 break;
3538 default:
3539 case ixgbe_mac_82599EB:
3540 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3541 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3542 break;
3543 }
3544 } else {
021230d4
AV		 3545 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3546 * specifically only auto mask tx and rx interrupts */
3547 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3548 }
9a799d71 3549
a34bcfff
AD		 3550 /* XXX: to interrupt immediately for EICS writes, enable this */
3551 /* gpie |= IXGBE_GPIE_EIMEN; */
3552
3553 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3554 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3555 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3556 }
3557
a34bcfff
AD		 3558 /* Enable fan failure interrupt */
3559 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3560 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3561
a34bcfff 3562 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3563 gpie |= IXGBE_SDP1_GPIEN;
3564 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3565
3566 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3567}
3568
3569static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3570{
3571 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3572 int err;
a34bcfff
AD		 3573 u32 ctrl_ext;
3574
3575 ixgbe_get_hw_control(adapter);
3576 ixgbe_setup_gpie(adapter);
e8e26350 3577
9a799d71
AK		 3578 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3579 ixgbe_configure_msix(adapter);
3580 else
3581 ixgbe_configure_msi_and_legacy(adapter);
3582
61fac744
PW		 3583 /* enable the optics */
3584 if (hw->phy.multispeed_fiber)
3585 hw->mac.ops.enable_tx_laser(hw);
3586
9a799d71 3587 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3588 ixgbe_napi_enable_all(adapter);
3589
3590 /* clear any pending interrupts, may auto mask */
3591 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3592 ixgbe_irq_enable(adapter, true, true);
9a799d71 3593
bf069c97
DS		 3594 /*
3595 * If this adapter has a fan, check to see if we had a failure
3596 * before we enabled the interrupt.
3597 */
3598 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3599 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3600 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3601 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3602 }
3603
e8e26350
PW		 3604 /*
3605 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3606 * arrived before interrupts were enabled but after probe. Such
3607 * devices wouldn't have their type identified yet. We need to
3608 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3609 * If we're not hot-pluggable SFP+, we just need to configure link
3610 * and bring it up.
3611 */
19343de2
DS		 3612 if (hw->phy.type == ixgbe_phy_unknown) {
3613 err = hw->phy.ops.identify(hw);
3614 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3615 /*
3616 * Take the device down and schedule the sfp tasklet
3617 * which will unregister_netdev and log it.
3618 */
19343de2 3619 ixgbe_down(adapter);
5da43c1a 3620 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3621 return err;
3622 }
e8e26350
PW		 3623 }
3624
3625 if (ixgbe_is_sfp(hw)) {
3626 ixgbe_sfp_link_config(adapter);
3627 } else {
3628 err = ixgbe_non_sfp_link_config(hw);
3629 if (err)
396e799c 3630 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3631 }
0ecc061d 3632
1da100bb 3633 /* enable transmits */
477de6ed 3634 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3635
9a799d71
AK		 3636 /* bring the link up in the watchdog, this could race with our first
3637 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3638 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3639 adapter->link_check_timeout = jiffies;
9a799d71 3640 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3641
3642 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3643 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3644 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3645 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3646
9a799d71
AK		 3647 return 0;
3648}
3649
d4f80882
AV		 3650void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3651{
3652 WARN_ON(in_interrupt());
3653 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3654 msleep(1);
3655 ixgbe_down(adapter);
5809a1ae
GR		 3656 /*
3657 * If SR-IOV enabled then wait a bit before bringing the adapter
3658 * back up to give the VFs time to respond to the reset. The
3659 * two second wait is based upon the watchdog timer cycle in
3660 * the VF driver.
3661 */
3662 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3663 msleep(2000);
d4f80882
AV		 3664 ixgbe_up(adapter);
3665 clear_bit(__IXGBE_RESETTING, &adapter->state);
3666}
3667
9a799d71
AK		 3668int ixgbe_up(struct ixgbe_adapter *adapter)
3669{
3670 /* hardware has been reset, we need to reload some things */
3671 ixgbe_configure(adapter);
3672
3673 return ixgbe_up_complete(adapter);
3674}
3675
3676void ixgbe_reset(struct ixgbe_adapter *adapter)
3677{
c44ade9e 3678 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3679 int err;
3680
3681 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3682 switch (err) {
3683 case 0:
3684 case IXGBE_ERR_SFP_NOT_PRESENT:
3685 break;
3686 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3687 e_dev_err("master disable timed out\n");
da4dd0f7 3688 break;
794caeb2
PWJ		 3689 case IXGBE_ERR_EEPROM_VERSION:
3690 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3691 e_dev_warn("This device is a pre-production adapter/LOM. "
3692 "Please be aware there may be issuesassociated with "
3693 "your hardware. If you are experiencing problems "
3694 "please contact your Intel or hardware "
3695 "representative who provided you with this "
3696 "hardware.\n");
794caeb2 3697 break;
da4dd0f7 3698 default:
849c4542 3699 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3700 }
9a799d71
AK		 3701
3702 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3703 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3704 IXGBE_RAH_AV);
9a799d71
AK		 3705}
3706
9a799d71
AK		 3707/**
3708 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3709 * @rx_ring: ring to free buffers from
3710 **/
b6ec895e 3711static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3712{
b6ec895e 3713 struct device *dev = rx_ring->dev;
9a799d71 3714 unsigned long size;
b6ec895e 3715 u16 i;
9a799d71 3716
84418e3b
AD		 3717 /* ring already cleared, nothing to do */
3718 if (!rx_ring->rx_buffer_info)
3719 return;
9a799d71 3720
84418e3b 3721 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3722 for (i = 0; i < rx_ring->count; i++) {
3723 struct ixgbe_rx_buffer *rx_buffer_info;
3724
3725 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3726 if (rx_buffer_info->dma) {
b6ec895e 3727 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3728 rx_ring->rx_buf_len,
1b507730 3729 DMA_FROM_DEVICE);
9a799d71
AK		 3730 rx_buffer_info->dma = 0;
3731 }
3732 if (rx_buffer_info->skb) {
f8212f97 3733 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3734 rx_buffer_info->skb = NULL;
f8212f97
AD		 3735 do {
3736 struct sk_buff *this = skb;
e8171aaa 3737 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3738 dma_unmap_single(dev,
1b507730 3739 IXGBE_RSC_CB(this)->dma,
e8e9f696 3740 rx_ring->rx_buf_len,
1b507730 3741 DMA_FROM_DEVICE);
fd3686a8 3742 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3743 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3744 }
f8212f97
AD		 3745 skb = skb->prev;
3746 dev_kfree_skb(this);
3747 } while (skb);
9a799d71
AK		 3748 }
3749 if (!rx_buffer_info->page)
3750 continue;
4f57ca6e 3751 if (rx_buffer_info->page_dma) {
b6ec895e 3752 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3753 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3754 rx_buffer_info->page_dma = 0;
3755 }
9a799d71
AK		 3756 put_page(rx_buffer_info->page);
3757 rx_buffer_info->page = NULL;
762f4c57 3758 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3759 }
3760
3761 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3762 memset(rx_ring->rx_buffer_info, 0, size);
3763
3764 /* Zero out the descriptor ring */
3765 memset(rx_ring->desc, 0, rx_ring->size);
3766
3767 rx_ring->next_to_clean = 0;
3768 rx_ring->next_to_use = 0;
9a799d71
AK		 3769}
3770
3771/**
3772 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3773 * @tx_ring: ring to be cleaned
3774 **/
b6ec895e 3775static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3776{
3777 struct ixgbe_tx_buffer *tx_buffer_info;
3778 unsigned long size;
b6ec895e 3779 u16 i;
9a799d71 3780
84418e3b
AD		 3781 /* ring already cleared, nothing to do */
3782 if (!tx_ring->tx_buffer_info)
3783 return;
9a799d71 3784
84418e3b 3785 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3786 for (i = 0; i < tx_ring->count; i++) {
3787 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3788 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3789 }
3790
3791 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3792 memset(tx_ring->tx_buffer_info, 0, size);
3793
3794 /* Zero out the descriptor ring */
3795 memset(tx_ring->desc, 0, tx_ring->size);
3796
3797 tx_ring->next_to_use = 0;
3798 tx_ring->next_to_clean = 0;
9a799d71
AK		 3799}
3800
3801/**
021230d4 3802 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3803 * @adapter: board private structure
3804 **/
021230d4 3805static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3806{
3807 int i;
3808
021230d4 3809 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3810 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3811}
3812
3813/**
021230d4 3814 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3815 * @adapter: board private structure
3816 **/
021230d4 3817static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3818{
3819 int i;
3820
021230d4 3821 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3822 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3823}
3824
3825void ixgbe_down(struct ixgbe_adapter *adapter)
3826{
3827 struct net_device *netdev = adapter->netdev;
7f821875 3828 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3829 u32 rxctrl;
7f821875
JB		 3830 u32 txdctl;
3831 int i, j;
b25ebfd2 3832 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3833
3834 /* signal that we are down to the interrupt handler */
3835 set_bit(__IXGBE_DOWN, &adapter->state);
3836
767081ad
GR		 3837 /* disable receive for all VFs and wait one second */
3838 if (adapter->num_vfs) {
767081ad
GR		 3839 /* ping all the active vfs to let them know we are going down */
3840 ixgbe_ping_all_vfs(adapter);
581d1aa7 3841
767081ad
GR		 3842 /* Disable all VFTE/VFRE TX/RX */
3843 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3844
3845 /* Mark all the VFs as inactive */
3846 for (i = 0 ; i < adapter->num_vfs; i++)
3847 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3848 }
3849
9a799d71 3850 /* disable receives */
7f821875
JB		 3851 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3852 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3853
7f821875 3854 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3855 msleep(10);
3856
7f821875
JB		 3857 netif_tx_stop_all_queues(netdev);
3858
0a1f87cb
DS		 3859 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3860 del_timer_sync(&adapter->sfp_timer);
9a799d71 3861 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3862 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3863
c0dfb90e
JF		 3864 netif_carrier_off(netdev);
3865 netif_tx_disable(netdev);
3866
3867 ixgbe_irq_disable(adapter);
3868
3869 ixgbe_napi_disable_all(adapter);
3870
b25ebfd2
PW		 3871 /* Cleanup the affinity_hint CPU mask memory and callback */
3872 for (i = 0; i < num_q_vectors; i++) {
3873 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3874 /* clear the affinity_mask in the IRQ descriptor */
3875 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3876 /* release the CPU mask memory */
3877 free_cpumask_var(q_vector->affinity_mask);
3878 }
3879
c4cf55e5
PWJ		 3880 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3881 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3882 cancel_work_sync(&adapter->fdir_reinit_task);
3883
119fc60a
MC		 3884 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3885 cancel_work_sync(&adapter->check_overtemp_task);
3886
7f821875
JB		 3887 /* disable transmits in the hardware now that interrupts are off */
3888 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3889 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3890 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3891 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3892 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3893 }
88512539
PW		 3894 /* Disable the Tx DMA engine on 82599 */
3895 if (hw->mac.type == ixgbe_mac_82599EB)
3896 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3897 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3898 ~IXGBE_DMATXCTL_TE));
7f821875 3899
9f756f01
JF		 3900 /* power down the optics */
3901 if (hw->phy.multispeed_fiber)
3902 hw->mac.ops.disable_tx_laser(hw);
3903
9a713e7c
PW		 3904 /* clear n-tuple filters that are cached */
3905 ethtool_ntuple_flush(netdev);
3906
6f4a0e45
PL		 3907 if (!pci_channel_offline(adapter->pdev))
3908 ixgbe_reset(adapter);
9a799d71
AK		 3909 ixgbe_clean_all_tx_rings(adapter);
3910 ixgbe_clean_all_rx_rings(adapter);
3911
5dd2d332 3912#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3913 /* since we reset the hardware DCA settings were cleared */
e35ec126 3914 ixgbe_setup_dca(adapter);
96b0e0f6 3915#endif
9a799d71
AK		 3916}
3917
9a799d71 3918/**
021230d4
AV		 3919 * ixgbe_poll - NAPI Rx polling callback
3920 * @napi: structure for representing this polling device
3921 * @budget: how many packets driver is allowed to clean
3922 *
3923 * This function is used for legacy and MSI, NAPI mode
9a799d71 3924 **/
021230d4 3925static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3926{
9a1a69ad 3927 struct ixgbe_q_vector *q_vector =
e8e9f696 3928 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3929 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3930 int tx_clean_complete, work_done = 0;
9a799d71 3931
5dd2d332 3932#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 3933 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3934 ixgbe_update_dca(q_vector);
bd0362dd
JC		 3935#endif
3936
4a0b9ca0
PW		 3937 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3938 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3939
9a1a69ad 3940 if (!tx_clean_complete)
d2c7ddd6
DM		 3941 work_done = budget;
3942
53e52c72
DM		 3943 /* If budget not fully consumed, exit the polling mode */
3944 if (work_done < budget) {
288379f0 3945 napi_complete(napi);
f7554a2b 3946 if (adapter->rx_itr_setting & 1)
f494e8fa 3947 ixgbe_set_itr(adapter);
d4f80882 3948 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3949 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3950 }
9a799d71
AK		 3951 return work_done;
3952}
3953
3954/**
3955 * ixgbe_tx_timeout - Respond to a Tx Hang
3956 * @netdev: network interface device structure
3957 **/
3958static void ixgbe_tx_timeout(struct net_device *netdev)
3959{
3960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3961
3962 /* Do the reset outside of interrupt context */
3963 schedule_work(&adapter->reset_task);
3964}
3965
3966static void ixgbe_reset_task(struct work_struct *work)
3967{
3968 struct ixgbe_adapter *adapter;
3969 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3970
2f90b865
AD		 3971 /* If we're already down or resetting, just bail */
3972 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3973 test_bit(__IXGBE_RESETTING, &adapter->state))
3974 return;
3975
9a799d71
AK		 3976 adapter->tx_timeout_count++;
3977
dcd79aeb
TI		 3978 ixgbe_dump(adapter);
3979 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3980 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3981}
3982
bc97114d
PWJ		 3983#ifdef CONFIG_IXGBE_DCB
3984static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3985{
bc97114d 3986 bool ret = false;
0cefafad 3987 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3988
0cefafad
JB		 3989 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3990 return ret;
3991
3992 f->mask = 0x7 << 3;
3993 adapter->num_rx_queues = f->indices;
3994 adapter->num_tx_queues = f->indices;
3995 ret = true;
2f90b865 3996
bc97114d
PWJ		 3997 return ret;
3998}
3999#endif
4000
4df10466
JB		 4001/**
4002 * ixgbe_set_rss_queues: Allocate queues for RSS
4003 * @adapter: board private structure to initialize
4004 *
4005 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4006 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4007 *
4008 **/
bc97114d
PWJ		 4009static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4010{
4011 bool ret = false;
0cefafad 4012 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4013
4014 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4015 f->mask = 0xF;
4016 adapter->num_rx_queues = f->indices;
4017 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4018 ret = true;
4019 } else {
bc97114d 4020 ret = false;
b9804972
JB		 4021 }
4022
bc97114d
PWJ		 4023 return ret;
4024}
4025
c4cf55e5
PWJ		 4026/**
4027 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4028 * @adapter: board private structure to initialize
4029 *
4030 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4031 * to the original CPU that initiated the Tx session. This runs in addition
4032 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4033 * Rx load across CPUs using RSS.
4034 *
4035 **/
e8e9f696 4036static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4037{
4038 bool ret = false;
4039 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4040
4041 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4042 f_fdir->mask = 0;
4043
4044 /* Flow Director must have RSS enabled */
4045 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4046 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4047 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4048 adapter->num_tx_queues = f_fdir->indices;
4049 adapter->num_rx_queues = f_fdir->indices;
4050 ret = true;
4051 } else {
4052 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4053 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4054 }
4055 return ret;
4056}
4057
0331a832
YZ		 4058#ifdef IXGBE_FCOE
4059/**
4060 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4061 * @adapter: board private structure to initialize
4062 *
4063 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4064 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4065 * rx queues out of the max number of rx queues, instead, it is used as the
4066 * index of the first rx queue used by FCoE.
4067 *
4068 **/
4069static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4070{
4071 bool ret = false;
4072 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4073
4074 f->indices = min((int)num_online_cpus(), f->indices);
4075 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4076 adapter->num_rx_queues = 1;
4077 adapter->num_tx_queues = 1;
0331a832
YZ		 4078#ifdef CONFIG_IXGBE_DCB
4079 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4080 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4081 ixgbe_set_dcb_queues(adapter);
4082 }
4083#endif
4084 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4085 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4086 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4087 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4088 ixgbe_set_fdir_queues(adapter);
4089 else
4090 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4091 }
4092 /* adding FCoE rx rings to the end */
4093 f->mask = adapter->num_rx_queues;
4094 adapter->num_rx_queues += f->indices;
8de8b2e6 4095 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4096
4097 ret = true;
4098 }
4099
4100 return ret;
4101}
4102
4103#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4104/**
4105 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4106 * @adapter: board private structure to initialize
4107 *
4108 * IOV doesn't actually use anything, so just NAK the
4109 * request for now and let the other queue routines
4110 * figure out what to do.
4111 */
4112static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4113{
4114 return false;
4115}
4116
4df10466
JB		 4117/*
4118 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4119 * @adapter: board private structure to initialize
4120 *
4121 * This is the top level queue allocation routine. The order here is very
4122 * important, starting with the "most" number of features turned on at once,
4123 * and ending with the smallest set of features. This way large combinations
4124 * can be allocated if they're turned on, and smaller combinations are the
4125 * fallthrough conditions.
4126 *
4127 **/
847f53ff 4128static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4129{
1cdd1ec8
GR		 4130 /* Start with base case */
4131 adapter->num_rx_queues = 1;
4132 adapter->num_tx_queues = 1;
4133 adapter->num_rx_pools = adapter->num_rx_queues;
4134 adapter->num_rx_queues_per_pool = 1;
4135
4136 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4137 goto done;
1cdd1ec8 4138
0331a832
YZ		 4139#ifdef IXGBE_FCOE
4140 if (ixgbe_set_fcoe_queues(adapter))
4141 goto done;
4142
4143#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4144#ifdef CONFIG_IXGBE_DCB
4145 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4146 goto done;
bc97114d
PWJ		 4147
4148#endif
c4cf55e5
PWJ		 4149 if (ixgbe_set_fdir_queues(adapter))
4150 goto done;
4151
bc97114d 4152 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4153 goto done;
4154
4155 /* fallback to base case */
4156 adapter->num_rx_queues = 1;
4157 adapter->num_tx_queues = 1;
4158
4159done:
847f53ff 4160 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4161 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4162 return netif_set_real_num_rx_queues(adapter->netdev,
4163 adapter->num_rx_queues);
b9804972
JB		 4164}
4165
021230d4 4166static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4167 int vectors)
021230d4
AV		 4168{
4169 int err, vector_threshold;
4170
4171 /* We'll want at least 3 (vector_threshold):
4172 * 1) TxQ[0] Cleanup
4173 * 2) RxQ[0] Cleanup
4174 * 3) Other (Link Status Change, etc.)
4175 * 4) TCP Timer (optional)
4176 */
4177 vector_threshold = MIN_MSIX_COUNT;
4178
4179 /* The more we get, the more we will assign to Tx/Rx Cleanup
4180 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4181 * Right now, we simply care about how many we'll get; we'll
4182 * set them up later while requesting irq's.
4183 */
4184 while (vectors >= vector_threshold) {
4185 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4186 vectors);
021230d4
AV		 4187 if (!err) /* Success in acquiring all requested vectors. */
4188 break;
4189 else if (err < 0)
4190 vectors = 0; /* Nasty failure, quit now */
4191 else /* err == number of vectors we should try again with */
4192 vectors = err;
4193 }
4194
4195 if (vectors < vector_threshold) {
4196 /* Can't allocate enough MSI-X interrupts? Oh well.
4197 * This just means we'll go with either a single MSI
4198 * vector or fall back to legacy interrupts.
4199 */
849c4542
ET		 4200 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4201 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4202 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4203 kfree(adapter->msix_entries);
4204 adapter->msix_entries = NULL;
021230d4
AV		 4205 } else {
4206 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4207 /*
4208 * Adjust for only the vectors we'll use, which is minimum
4209 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4210 * vectors we were allocated.
4211 */
4212 adapter->num_msix_vectors = min(vectors,
e8e9f696 4213 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4214 }
4215}
4216
021230d4 4217/**
bc97114d 4218 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4219 * @adapter: board private structure to initialize
4220 *
bc97114d
PWJ		 4221 * Cache the descriptor ring offsets for RSS to the assigned rings.
4222 *
021230d4 4223 **/
bc97114d 4224static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4225{
bc97114d
PWJ		 4226 int i;
4227 bool ret = false;
4228
4229 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4230 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4231 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4232 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4233 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4234 ret = true;
4235 } else {
4236 ret = false;
4237 }
4238
4239 return ret;
4240}
4241
4242#ifdef CONFIG_IXGBE_DCB
4243/**
4244 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4245 * @adapter: board private structure to initialize
4246 *
4247 * Cache the descriptor ring offsets for DCB to the assigned rings.
4248 *
4249 **/
4250static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4251{
4252 int i;
4253 bool ret = false;
4254 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4255
4256 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4257 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4258 /* the number of queues is assumed to be symmetric */
4259 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4260 adapter->rx_ring[i]->reg_idx = i << 3;
4261 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4262 }
bc97114d 4263 ret = true;
e8e26350 4264 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4265 if (dcb_i == 8) {
4266 /*
4267 * Tx TC0 starts at: descriptor queue 0
4268 * Tx TC1 starts at: descriptor queue 32
4269 * Tx TC2 starts at: descriptor queue 64
4270 * Tx TC3 starts at: descriptor queue 80
4271 * Tx TC4 starts at: descriptor queue 96
4272 * Tx TC5 starts at: descriptor queue 104
4273 * Tx TC6 starts at: descriptor queue 112
4274 * Tx TC7 starts at: descriptor queue 120
4275 *
4276 * Rx TC0-TC7 are offset by 16 queues each
4277 */
4278 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4279 adapter->tx_ring[i]->reg_idx = i << 5;
4280 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4281 }
4282 for ( ; i < 5; i++) {
4a0b9ca0 4283 adapter->tx_ring[i]->reg_idx =
e8e9f696 4284 ((i + 2) << 4);
4a0b9ca0 4285 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4286 }
4287 for ( ; i < dcb_i; i++) {
4a0b9ca0 4288 adapter->tx_ring[i]->reg_idx =
e8e9f696 4289 ((i + 8) << 3);
4a0b9ca0 4290 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4291 }
4292
4293 ret = true;
4294 } else if (dcb_i == 4) {
4295 /*
4296 * Tx TC0 starts at: descriptor queue 0
4297 * Tx TC1 starts at: descriptor queue 64
4298 * Tx TC2 starts at: descriptor queue 96
4299 * Tx TC3 starts at: descriptor queue 112
4300 *
4301 * Rx TC0-TC3 are offset by 32 queues each
4302 */
4a0b9ca0
PW		 4303 adapter->tx_ring[0]->reg_idx = 0;
4304 adapter->tx_ring[1]->reg_idx = 64;
4305 adapter->tx_ring[2]->reg_idx = 96;
4306 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4307 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4308 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4309
4310 ret = true;
4311 } else {
4312 ret = false;
e8e26350 4313 }
bc97114d
PWJ		 4314 } else {
4315 ret = false;
021230d4 4316 }
bc97114d
PWJ		 4317 } else {
4318 ret = false;
021230d4 4319 }
bc97114d
PWJ		 4320
4321 return ret;
4322}
4323#endif
4324
c4cf55e5
PWJ		 4325/**
4326 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4327 * @adapter: board private structure to initialize
4328 *
4329 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4330 *
4331 **/
e8e9f696 4332static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4333{
4334 int i;
4335 bool ret = false;
4336
4337 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4338 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4339 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4340 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4341 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4342 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4343 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4344 ret = true;
4345 }
4346
4347 return ret;
4348}
4349
0331a832
YZ		 4350#ifdef IXGBE_FCOE
4351/**
4352 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4353 * @adapter: board private structure to initialize
4354 *
4355 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4356 *
4357 */
4358static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4359{
8de8b2e6 4360 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4361 bool ret = false;
4362 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4363
4364 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4365#ifdef CONFIG_IXGBE_DCB
4366 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4367 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4368
0331a832 4369 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4370 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4371 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4372 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4373 /*
4374 * In 82599, the number of Tx queues for each traffic
4375 * class for both 8-TC and 4-TC modes are:
4376 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4377 * 8 TCs: 32 32 16 16 8 8 8 8
4378 * 4 TCs: 64 64 32 32
4379 * We have max 8 queues for FCoE, where 8 the is
4380 * FCoE redirection table size. If TC for FCoE is
4381 * less than or equal to TC3, we have enough queues
4382 * to add max of 8 queues for FCoE, so we start FCoE
4383 * tx descriptor from the next one, i.e., reg_idx + 1.
4384 * If TC for FCoE is above TC3, implying 8 TC mode,
4385 * and we need 8 for FCoE, we have to take all queues
4386 * in that traffic class for FCoE.
4387 */
4388 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4389 fcoe_tx_i--;
0331a832
YZ		 4390 }
4391#endif /* CONFIG_IXGBE_DCB */
4392 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4393 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4394 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4395 ixgbe_cache_ring_fdir(adapter);
4396 else
4397 ixgbe_cache_ring_rss(adapter);
4398
8de8b2e6
YZ		 4399 fcoe_rx_i = f->mask;
4400 fcoe_tx_i = f->mask;
4401 }
4402 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4403 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4404 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4405 }
0331a832
YZ		 4406 ret = true;
4407 }
4408 return ret;
4409}
4410
4411#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4412/**
4413 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4414 * @adapter: board private structure to initialize
4415 *
4416 * SR-IOV doesn't use any descriptor rings but changes the default if
4417 * no other mapping is used.
4418 *
4419 */
4420static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4421{
4a0b9ca0
PW		 4422 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4423 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4424 if (adapter->num_vfs)
4425 return true;
4426 else
4427 return false;
4428}
4429
bc97114d
PWJ		 4430/**
4431 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4432 * @adapter: board private structure to initialize
4433 *
4434 * Once we know the feature-set enabled for the device, we'll cache
4435 * the register offset the descriptor ring is assigned to.
4436 *
4437 * Note, the order the various feature calls is important. It must start with
4438 * the "most" features enabled at the same time, then trickle down to the
4439 * least amount of features turned on at once.
4440 **/
4441static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4442{
4443 /* start with default case */
4a0b9ca0
PW		 4444 adapter->rx_ring[0]->reg_idx = 0;
4445 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4446
1cdd1ec8
GR		 4447 if (ixgbe_cache_ring_sriov(adapter))
4448 return;
4449
0331a832
YZ		 4450#ifdef IXGBE_FCOE
4451 if (ixgbe_cache_ring_fcoe(adapter))
4452 return;
4453
4454#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4455#ifdef CONFIG_IXGBE_DCB
4456 if (ixgbe_cache_ring_dcb(adapter))
4457 return;
4458
4459#endif
c4cf55e5
PWJ		 4460 if (ixgbe_cache_ring_fdir(adapter))
4461 return;
4462
bc97114d
PWJ		 4463 if (ixgbe_cache_ring_rss(adapter))
4464 return;
021230d4
AV		 4465}
4466
9a799d71
AK		 4467/**
4468 * ixgbe_alloc_queues - Allocate memory for all rings
4469 * @adapter: board private structure to initialize
4470 *
4471 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4472 * number of queues at compile-time. The polling_netdev array is
4473 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4474 **/
2f90b865 4475static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4476{
4477 int i;
b6ec895e 4478 int rx_count;
4a0b9ca0 4479 int orig_node = adapter->node;
9a799d71 4480
021230d4 4481 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4482 struct ixgbe_ring *ring = adapter->tx_ring[i];
4483 if (orig_node == -1) {
4484 int cur_node = next_online_node(adapter->node);
4485 if (cur_node == MAX_NUMNODES)
4486 cur_node = first_online_node;
4487 adapter->node = cur_node;
4488 }
4489 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4490 adapter->node);
4a0b9ca0
PW		 4491 if (!ring)
4492 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4493 if (!ring)
4494 goto err_tx_ring_allocation;
4495 ring->count = adapter->tx_ring_count;
4496 ring->queue_index = i;
b6ec895e 4497 ring->dev = &adapter->pdev->dev;
fc77dc3c 4498 ring->netdev = adapter->netdev;
4a0b9ca0
PW		 4499 ring->numa_node = adapter->node;
4500
4501 adapter->tx_ring[i] = ring;
021230d4 4502 }
b9804972 4503
4a0b9ca0
PW		 4504 /* Restore the adapter's original node */
4505 adapter->node = orig_node;
4506
b6ec895e 4507 rx_count = adapter->rx_ring_count;
9a799d71 4508 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4509 struct ixgbe_ring *ring = adapter->rx_ring[i];
4510 if (orig_node == -1) {
4511 int cur_node = next_online_node(adapter->node);
4512 if (cur_node == MAX_NUMNODES)
4513 cur_node = first_online_node;
4514 adapter->node = cur_node;
4515 }
4516 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4517 adapter->node);
4a0b9ca0
PW		 4518 if (!ring)
4519 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4520 if (!ring)
4521 goto err_rx_ring_allocation;
b6ec895e 4522 ring->count = rx_count;
4a0b9ca0 4523 ring->queue_index = i;
b6ec895e 4524 ring->dev = &adapter->pdev->dev;
fc77dc3c 4525 ring->netdev = adapter->netdev;
4a0b9ca0
PW		 4526 ring->numa_node = adapter->node;
4527
4528 adapter->rx_ring[i] = ring;
021230d4
AV		 4529 }
4530
4a0b9ca0
PW		 4531 /* Restore the adapter's original node */
4532 adapter->node = orig_node;
4533
021230d4
AV		 4534 ixgbe_cache_ring_register(adapter);
4535
4536 return 0;
4537
4538err_rx_ring_allocation:
4a0b9ca0
PW		 4539 for (i = 0; i < adapter->num_tx_queues; i++)
4540 kfree(adapter->tx_ring[i]);
021230d4
AV		 4541err_tx_ring_allocation:
4542 return -ENOMEM;
4543}
4544
4545/**
4546 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4547 * @adapter: board private structure to initialize
4548 *
4549 * Attempt to configure the interrupts using the best available
4550 * capabilities of the hardware and the kernel.
4551 **/
feea6a57 4552static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4553{
8be0e467 4554 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4555 int err = 0;
4556 int vector, v_budget;
4557
4558 /*
4559 * It's easy to be greedy for MSI-X vectors, but it really
4560 * doesn't do us much good if we have a lot more vectors
4561 * than CPU's. So let's be conservative and only ask for
342bde1b 4562 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4563 */
4564 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4565 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4566
4567 /*
4568 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4569 * hw.mac->max_msix_vectors vectors. With features
4570 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4571 * descriptor queues supported by our device. Thus, we cap it off in
4572 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4573 */
8be0e467 4574 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4575
4576 /* A failure in MSI-X entry allocation isn't fatal, but it does
4577 * mean we disable MSI-X capabilities of the adapter. */
4578 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4579 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4580 if (adapter->msix_entries) {
4581 for (vector = 0; vector < v_budget; vector++)
4582 adapter->msix_entries[vector].entry = vector;
021230d4 4583
7a921c93 4584 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4585
7a921c93
AD		 4586 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4587 goto out;
4588 }
26d27844 4589
7a921c93
AD		 4590 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4591 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4592 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4593 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4594 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4595 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4596 ixgbe_disable_sriov(adapter);
4597
847f53ff
BH		 4598 err = ixgbe_set_num_queues(adapter);
4599 if (err)
4600 return err;
021230d4 4601
021230d4
AV		 4602 err = pci_enable_msi(adapter->pdev);
4603 if (!err) {
4604 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4605 } else {
849c4542
ET		 4606 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4607 "Unable to allocate MSI interrupt, "
4608 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4609 /* reset err */
4610 err = 0;
4611 }
4612
4613out:
021230d4
AV		 4614 return err;
4615}
4616
7a921c93
AD		 4617/**
4618 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4619 * @adapter: board private structure to initialize
4620 *
4621 * We allocate one q_vector per queue interrupt. If allocation fails we
4622 * return -ENOMEM.
4623 **/
4624static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4625{
4626 int q_idx, num_q_vectors;
4627 struct ixgbe_q_vector *q_vector;
4628 int napi_vectors;
4629 int (*poll)(struct napi_struct *, int);
4630
4631 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4632 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4633 napi_vectors = adapter->num_rx_queues;
91281fd3 4634 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4635 } else {
4636 num_q_vectors = 1;
4637 napi_vectors = 1;
4638 poll = &ixgbe_poll;
4639 }
4640
4641 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4642 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4643 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4644 if (!q_vector)
4645 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4646 GFP_KERNEL);
7a921c93
AD		 4647 if (!q_vector)
4648 goto err_out;
4649 q_vector->adapter = adapter;
f7554a2b
NS		 4650 if (q_vector->txr_count && !q_vector->rxr_count)
4651 q_vector->eitr = adapter->tx_eitr_param;
4652 else
4653 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4654 q_vector->v_idx = q_idx;
91281fd3 4655 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4656 adapter->q_vector[q_idx] = q_vector;
4657 }
4658
4659 return 0;
4660
4661err_out:
4662 while (q_idx) {
4663 q_idx--;
4664 q_vector = adapter->q_vector[q_idx];
4665 netif_napi_del(&q_vector->napi);
4666 kfree(q_vector);
4667 adapter->q_vector[q_idx] = NULL;
4668 }
4669 return -ENOMEM;
4670}
4671
4672/**
4673 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4674 * @adapter: board private structure to initialize
4675 *
4676 * This function frees the memory allocated to the q_vectors. In addition if
4677 * NAPI is enabled it will delete any references to the NAPI struct prior
4678 * to freeing the q_vector.
4679 **/
4680static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4681{
4682 int q_idx, num_q_vectors;
7a921c93 4683
91281fd3 4684 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4685 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4686 else
7a921c93 4687 num_q_vectors = 1;
7a921c93
AD		 4688
4689 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4690 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4691 adapter->q_vector[q_idx] = NULL;
91281fd3 4692 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4693 kfree(q_vector);
4694 }
4695}
4696
7b25cdba 4697static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4698{
4699 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4700 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4701 pci_disable_msix(adapter->pdev);
4702 kfree(adapter->msix_entries);
4703 adapter->msix_entries = NULL;
4704 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4705 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4706 pci_disable_msi(adapter->pdev);
4707 }
021230d4
AV		 4708}
4709
4710/**
4711 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4712 * @adapter: board private structure to initialize
4713 *
4714 * We determine which interrupt scheme to use based on...
4715 * - Kernel support (MSI, MSI-X)
4716 * - which can be user-defined (via MODULE_PARAM)
4717 * - Hardware queue count (num_*_queues)
4718 * - defined by miscellaneous hardware support/features (RSS, etc.)
4719 **/
2f90b865 4720int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4721{
4722 int err;
4723
4724 /* Number of supported queues */
847f53ff
BH		 4725 err = ixgbe_set_num_queues(adapter);
4726 if (err)
4727 return err;
021230d4 4728
021230d4
AV		 4729 err = ixgbe_set_interrupt_capability(adapter);
4730 if (err) {
849c4542 4731 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4732 goto err_set_interrupt;
9a799d71
AK		 4733 }
4734
7a921c93
AD		 4735 err = ixgbe_alloc_q_vectors(adapter);
4736 if (err) {
849c4542 4737 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4738 goto err_alloc_q_vectors;
4739 }
4740
4741 err = ixgbe_alloc_queues(adapter);
4742 if (err) {
849c4542 4743 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4744 goto err_alloc_queues;
4745 }
4746
849c4542 4747 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4748 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4749 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4750
4751 set_bit(__IXGBE_DOWN, &adapter->state);
4752
9a799d71 4753 return 0;
021230d4 4754
7a921c93
AD		 4755err_alloc_queues:
4756 ixgbe_free_q_vectors(adapter);
4757err_alloc_q_vectors:
4758 ixgbe_reset_interrupt_capability(adapter);
021230d4 4759err_set_interrupt:
7a921c93
AD		 4760 return err;
4761}
4762
1a51502b
ED		 4763static void ring_free_rcu(struct rcu_head *head)
4764{
4765 kfree(container_of(head, struct ixgbe_ring, rcu));
4766}
4767
7a921c93
AD		 4768/**
4769 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4770 * @adapter: board private structure to clear interrupt scheme on
4771 *
4772 * We go through and clear interrupt specific resources and reset the structure
4773 * to pre-load conditions
4774 **/
4775void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4776{
4a0b9ca0
PW		 4777 int i;
4778
4779 for (i = 0; i < adapter->num_tx_queues; i++) {
4780 kfree(adapter->tx_ring[i]);
4781 adapter->tx_ring[i] = NULL;
4782 }
4783 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4784 struct ixgbe_ring *ring = adapter->rx_ring[i];
4785
4786 /* ixgbe_get_stats64() might access this ring, we must wait
4787 * a grace period before freeing it.
4788 */
4789 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 4790 adapter->rx_ring[i] = NULL;
4791 }
7a921c93
AD		 4792
4793 ixgbe_free_q_vectors(adapter);
4794 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4795}
4796
c4900be0
DS		 4797/**
4798 * ixgbe_sfp_timer - worker thread to find a missing module
4799 * @data: pointer to our adapter struct
4800 **/
4801static void ixgbe_sfp_timer(unsigned long data)
4802{
4803 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4804
4df10466
JB		 4805 /*
4806 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4807 * delays that sfp+ detection requires
4808 */
4809 schedule_work(&adapter->sfp_task);
4810}
4811
4812/**
4813 * ixgbe_sfp_task - worker thread to find a missing module
4814 * @work: pointer to work_struct containing our data
4815 **/
4816static void ixgbe_sfp_task(struct work_struct *work)
4817{
4818 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4819 struct ixgbe_adapter,
4820 sfp_task);
c4900be0
DS		 4821 struct ixgbe_hw *hw = &adapter->hw;
4822
4823 if ((hw->phy.type == ixgbe_phy_nl) &&
4824 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4825 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4826 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4827 goto reschedule;
4828 ret = hw->phy.ops.reset(hw);
4829 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4830 e_dev_err("failed to initialize because an unsupported "
4831 "SFP+ module type was detected.\n");
4832 e_dev_err("Reload the driver after installing a "
4833 "supported module.\n");
c4900be0
DS		 4834 unregister_netdev(adapter->netdev);
4835 } else {
396e799c 4836 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4837 }
4838 /* don't need this routine any more */
4839 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4840 }
4841 return;
4842reschedule:
4843 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4844 mod_timer(&adapter->sfp_timer,
e8e9f696 4845 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4846}
4847
9a799d71
AK		 4848/**
4849 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4850 * @adapter: board private structure to initialize
4851 *
4852 * ixgbe_sw_init initializes the Adapter private data structure.
4853 * Fields are initialized based on PCI device information and
4854 * OS network device settings (MTU size).
4855 **/
4856static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4857{
4858 struct ixgbe_hw *hw = &adapter->hw;
4859 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4860 struct net_device *dev = adapter->netdev;
021230d4 4861 unsigned int rss;
7a6b6f51 4862#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4863 int j;
4864 struct tc_configuration *tc;
4865#endif
16b61beb 4866 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4867
c44ade9e
JB		 4868 /* PCI config space info */
4869
4870 hw->vendor_id = pdev->vendor;
4871 hw->device_id = pdev->device;
4872 hw->revision_id = pdev->revision;
4873 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4874 hw->subsystem_device_id = pdev->subsystem_device;
4875
021230d4
AV		 4876 /* Set capability flags */
4877 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4878 adapter->ring_feature[RING_F_RSS].indices = rss;
4879 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4880 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4881 if (hw->mac.type == ixgbe_mac_82598EB) {
4882 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4883 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4884 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4885 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4886 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4887 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4888 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4889 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4890 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4891 if (dev->features & NETIF_F_NTUPLE) {
4892 /* Flow Director perfect filter enabled */
4893 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4894 adapter->atr_sample_rate = 0;
4895 spin_lock_init(&adapter->fdir_perfect_lock);
4896 } else {
4897 /* Flow Director hash filters enabled */
4898 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4899 adapter->atr_sample_rate = 20;
4900 }
c4cf55e5 4901 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4902 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4903 adapter->fdir_pballoc = 0;
eacd73f7 4904#ifdef IXGBE_FCOE
0d551589
YZ		 4905 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4906 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4907 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4908#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4909 /* Default traffic class to use for FCoE */
4910 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4911 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4912#endif
eacd73f7 4913#endif /* IXGBE_FCOE */
f8212f97 4914 }
2f90b865 4915
7a6b6f51 4916#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4917 /* Configure DCB traffic classes */
4918 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4919 tc = &adapter->dcb_cfg.tc_config[j];
4920 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4921 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4922 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4923 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4924 tc->dcb_pfc = pfc_disabled;
4925 }
4926 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4927 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4928 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4929 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4930 adapter->dcb_cfg.round_robin_enable = false;
4931 adapter->dcb_set_bitmap = 0x00;
4932 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4933 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4934
4935#endif
9a799d71
AK		 4936
4937 /* default flow control settings */
cd7664f6 4938 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4939 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4940#ifdef CONFIG_DCB
4941 adapter->last_lfc_mode = hw->fc.current_mode;
4942#endif
16b61beb
JF		 4943 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4944 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 4945 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4946 hw->fc.send_xon = true;
71fd570b 4947 hw->fc.disable_fc_autoneg = false;
9a799d71 4948
30efa5a3 4949 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4950 adapter->rx_itr_setting = 1;
4951 adapter->rx_eitr_param = 20000;
4952 adapter->tx_itr_setting = 1;
4953 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4954
4955 /* set defaults for eitr in MegaBytes */
4956 adapter->eitr_low = 10;
4957 adapter->eitr_high = 20;
4958
4959 /* set default ring sizes */
4960 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4961 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4962
9a799d71 4963 /* initialize eeprom parameters */
c44ade9e 4964 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4965 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4966 return -EIO;
4967 }
4968
021230d4 4969 /* enable rx csum by default */
9a799d71
AK		 4970 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4971
1a6c14a2
JB		 4972 /* get assigned NUMA node */
4973 adapter->node = dev_to_node(&pdev->dev);
4974
9a799d71
AK		 4975 set_bit(__IXGBE_DOWN, &adapter->state);
4976
4977 return 0;
4978}
4979
4980/**
4981 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4982 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4983 *
4984 * Return 0 on success, negative on failure
4985 **/
b6ec895e 4986int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4987{
b6ec895e 4988 struct device *dev = tx_ring->dev;
9a799d71
AK		 4989 int size;
4990
3a581073 4991 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4992 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4993 if (!tx_ring->tx_buffer_info)
4994 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4995 if (!tx_ring->tx_buffer_info)
4996 goto err;
3a581073 4997 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4998
4999 /* round up to nearest 4K */
12207e49 5000 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5001 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5002
b6ec895e 5003 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5004 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5005 if (!tx_ring->desc)
5006 goto err;
9a799d71 5007
3a581073
JB		 5008 tx_ring->next_to_use = 0;
5009 tx_ring->next_to_clean = 0;
5010 tx_ring->work_limit = tx_ring->count;
9a799d71 5011 return 0;
e01c31a5
JB		 5012
5013err:
5014 vfree(tx_ring->tx_buffer_info);
5015 tx_ring->tx_buffer_info = NULL;
b6ec895e 5016 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5017 return -ENOMEM;
9a799d71
AK		 5018}
5019
69888674
AD		 5020/**
5021 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5022 * @adapter: board private structure
5023 *
5024 * If this function returns with an error, then it's possible one or
5025 * more of the rings is populated (while the rest are not). It is the
5026 * callers duty to clean those orphaned rings.
5027 *
5028 * Return 0 on success, negative on failure
5029 **/
5030static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5031{
5032 int i, err = 0;
5033
5034 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5035 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5036 if (!err)
5037 continue;
396e799c 5038 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5039 break;
5040 }
5041
5042 return err;
5043}
5044
9a799d71
AK		 5045/**
5046 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5047 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5048 *
5049 * Returns 0 on success, negative on failure
5050 **/
b6ec895e 5051int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5052{
b6ec895e 5053 struct device *dev = rx_ring->dev;
021230d4 5054 int size;
9a799d71 5055
3a581073 5056 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
b6ec895e 5057 rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
1a6c14a2
JB		 5058 if (!rx_ring->rx_buffer_info)
5059 rx_ring->rx_buffer_info = vmalloc(size);
b6ec895e
AD		 5060 if (!rx_ring->rx_buffer_info)
5061 goto err;
3a581073 5062 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5063
9a799d71 5064 /* Round up to nearest 4K */
3a581073
JB		 5065 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5066 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5067
b6ec895e 5068 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5069 &rx_ring->dma, GFP_KERNEL);
9a799d71 5070
b6ec895e
AD		 5071 if (!rx_ring->desc)
5072 goto err;
9a799d71 5073
3a581073
JB		 5074 rx_ring->next_to_clean = 0;
5075 rx_ring->next_to_use = 0;
9a799d71
AK		 5076
5077 return 0;
b6ec895e
AD		 5078err:
5079 vfree(rx_ring->rx_buffer_info);
5080 rx_ring->rx_buffer_info = NULL;
5081 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5082 return -ENOMEM;
9a799d71
AK		 5083}
5084
69888674
AD		 5085/**
5086 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5087 * @adapter: board private structure
5088 *
5089 * If this function returns with an error, then it's possible one or
5090 * more of the rings is populated (while the rest are not). It is the
5091 * callers duty to clean those orphaned rings.
5092 *
5093 * Return 0 on success, negative on failure
5094 **/
69888674
AD		 5095static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5096{
5097 int i, err = 0;
5098
5099 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5100 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5101 if (!err)
5102 continue;
396e799c 5103 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5104 break;
5105 }
5106
5107 return err;
5108}
5109
9a799d71
AK		 5110/**
5111 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5112 * @tx_ring: Tx descriptor ring for a specific queue
5113 *
5114 * Free all transmit software resources
5115 **/
b6ec895e 5116void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5117{
b6ec895e 5118 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5119
5120 vfree(tx_ring->tx_buffer_info);
5121 tx_ring->tx_buffer_info = NULL;
5122
b6ec895e
AD		 5123 /* if not set, then don't free */
5124 if (!tx_ring->desc)
5125 return;
5126
5127 dma_free_coherent(tx_ring->dev, tx_ring->size,
5128 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5129
5130 tx_ring->desc = NULL;
5131}
5132
5133/**
5134 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5135 * @adapter: board private structure
5136 *
5137 * Free all transmit software resources
5138 **/
5139static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5140{
5141 int i;
5142
5143 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5144 if (adapter->tx_ring[i]->desc)
b6ec895e 5145 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5146}
5147
5148/**
b4617240 5149 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5150 * @rx_ring: ring to clean the resources from
5151 *
5152 * Free all receive software resources
5153 **/
b6ec895e 5154void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5155{
b6ec895e 5156 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5157
5158 vfree(rx_ring->rx_buffer_info);
5159 rx_ring->rx_buffer_info = NULL;
5160
b6ec895e
AD		 5161 /* if not set, then don't free */
5162 if (!rx_ring->desc)
5163 return;
5164
5165 dma_free_coherent(rx_ring->dev, rx_ring->size,
5166 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5167
5168 rx_ring->desc = NULL;
5169}
5170
5171/**
5172 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5173 * @adapter: board private structure
5174 *
5175 * Free all receive software resources
5176 **/
5177static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5178{
5179 int i;
5180
5181 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5182 if (adapter->rx_ring[i]->desc)
b6ec895e 5183 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5184}
5185
9a799d71
AK		 5186/**
5187 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5188 * @netdev: network interface device structure
5189 * @new_mtu: new value for maximum frame size
5190 *
5191 * Returns 0 on success, negative on failure
5192 **/
5193static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5194{
5195 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5196 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5197 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5198
42c783c5
JB		 5199 /* MTU < 68 is an error and causes problems on some kernels */
5200 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5201 return -EINVAL;
5202
396e799c 5203 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5204 /* must set new MTU before calling down or up */
9a799d71
AK		 5205 netdev->mtu = new_mtu;
5206
16b61beb
JF		 5207 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5208 hw->fc.low_water = FC_LOW_WATER(max_frame);
5209
d4f80882
AV		 5210 if (netif_running(netdev))
5211 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5212
5213 return 0;
5214}
5215
5216/**
5217 * ixgbe_open - Called when a network interface is made active
5218 * @netdev: network interface device structure
5219 *
5220 * Returns 0 on success, negative value on failure
5221 *
5222 * The open entry point is called when a network interface is made
5223 * active by the system (IFF_UP). At this point all resources needed
5224 * for transmit and receive operations are allocated, the interrupt
5225 * handler is registered with the OS, the watchdog timer is started,
5226 * and the stack is notified that the interface is ready.
5227 **/
5228static int ixgbe_open(struct net_device *netdev)
5229{
5230 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5231 int err;
4bebfaa5
AK		 5232
5233 /* disallow open during test */
5234 if (test_bit(__IXGBE_TESTING, &adapter->state))
5235 return -EBUSY;
9a799d71 5236
54386467
JB		 5237 netif_carrier_off(netdev);
5238
9a799d71
AK		 5239 /* allocate transmit descriptors */
5240 err = ixgbe_setup_all_tx_resources(adapter);
5241 if (err)
5242 goto err_setup_tx;
5243
9a799d71
AK		 5244 /* allocate receive descriptors */
5245 err = ixgbe_setup_all_rx_resources(adapter);
5246 if (err)
5247 goto err_setup_rx;
5248
5249 ixgbe_configure(adapter);
5250
021230d4 5251 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5252 if (err)
5253 goto err_req_irq;
5254
9a799d71
AK		 5255 err = ixgbe_up_complete(adapter);
5256 if (err)
5257 goto err_up;
5258
d55b53ff
JK		 5259 netif_tx_start_all_queues(netdev);
5260
9a799d71
AK		 5261 return 0;
5262
5263err_up:
5eba3699 5264 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5265 ixgbe_free_irq(adapter);
5266err_req_irq:
9a799d71 5267err_setup_rx:
a20a1199 5268 ixgbe_free_all_rx_resources(adapter);
9a799d71 5269err_setup_tx:
a20a1199 5270 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5271 ixgbe_reset(adapter);
5272
5273 return err;
5274}
5275
5276/**
5277 * ixgbe_close - Disables a network interface
5278 * @netdev: network interface device structure
5279 *
5280 * Returns 0, this is not allowed to fail
5281 *
5282 * The close entry point is called when an interface is de-activated
5283 * by the OS. The hardware is still under the drivers control, but
5284 * needs to be disabled. A global MAC reset is issued to stop the
5285 * hardware, and all transmit and receive resources are freed.
5286 **/
5287static int ixgbe_close(struct net_device *netdev)
5288{
5289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5290
5291 ixgbe_down(adapter);
5292 ixgbe_free_irq(adapter);
5293
5294 ixgbe_free_all_tx_resources(adapter);
5295 ixgbe_free_all_rx_resources(adapter);
5296
5eba3699 5297 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5298
5299 return 0;
5300}
5301
b3c8b4ba
AD		 5302#ifdef CONFIG_PM
5303static int ixgbe_resume(struct pci_dev *pdev)
5304{
c60fbb00
AD		 5305 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5306 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5307 u32 err;
5308
5309 pci_set_power_state(pdev, PCI_D0);
5310 pci_restore_state(pdev);
656ab817
DS		 5311 /*
5312 * pci_restore_state clears dev->state_saved so call
5313 * pci_save_state to restore it.
5314 */
5315 pci_save_state(pdev);
9ce77666 5316
5317 err = pci_enable_device_mem(pdev);
b3c8b4ba 5318 if (err) {
849c4542 5319 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5320 return err;
5321 }
5322 pci_set_master(pdev);
5323
dd4d8ca6 5324 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5325
5326 err = ixgbe_init_interrupt_scheme(adapter);
5327 if (err) {
849c4542 5328 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5329 return err;
5330 }
5331
b3c8b4ba
AD		 5332 ixgbe_reset(adapter);
5333
495dce12
WJP		 5334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5335
b3c8b4ba 5336 if (netif_running(netdev)) {
c60fbb00 5337 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5338 if (err)
5339 return err;
5340 }
5341
5342 netif_device_attach(netdev);
5343
5344 return 0;
5345}
b3c8b4ba 5346#endif /* CONFIG_PM */
9d8d05ae
RW		 5347
5348static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5349{
c60fbb00
AD		 5350 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5351 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5352 struct ixgbe_hw *hw = &adapter->hw;
5353 u32 ctrl, fctrl;
5354 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5355#ifdef CONFIG_PM
5356 int retval = 0;
5357#endif
5358
5359 netif_device_detach(netdev);
5360
5361 if (netif_running(netdev)) {
5362 ixgbe_down(adapter);
5363 ixgbe_free_irq(adapter);
5364 ixgbe_free_all_tx_resources(adapter);
5365 ixgbe_free_all_rx_resources(adapter);
5366 }
b3c8b4ba 5367
5f5ae6fc
AD		 5368 ixgbe_clear_interrupt_scheme(adapter);
5369
b3c8b4ba
AD		 5370#ifdef CONFIG_PM
5371 retval = pci_save_state(pdev);
5372 if (retval)
5373 return retval;
4df10466 5374
b3c8b4ba 5375#endif
e8e26350
PW		 5376 if (wufc) {
5377 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5378
e8e26350
PW		 5379 /* turn on all-multi mode if wake on multicast is enabled */
5380 if (wufc & IXGBE_WUFC_MC) {
5381 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5382 fctrl |= IXGBE_FCTRL_MPE;
5383 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5384 }
5385
5386 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5387 ctrl |= IXGBE_CTRL_GIO_DIS;
5388 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5389
5390 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5391 } else {
5392 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5393 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5394 }
5395
dd4d8ca6
DS		 5396 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5397 pci_wake_from_d3(pdev, true);
5398 else
5399 pci_wake_from_d3(pdev, false);
b3c8b4ba 5400
9d8d05ae
RW		 5401 *enable_wake = !!wufc;
5402
b3c8b4ba
AD		 5403 ixgbe_release_hw_control(adapter);
5404
5405 pci_disable_device(pdev);
5406
9d8d05ae
RW		 5407 return 0;
5408}
5409
5410#ifdef CONFIG_PM
5411static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5412{
5413 int retval;
5414 bool wake;
5415
5416 retval = __ixgbe_shutdown(pdev, &wake);
5417 if (retval)
5418 return retval;
5419
5420 if (wake) {
5421 pci_prepare_to_sleep(pdev);
5422 } else {
5423 pci_wake_from_d3(pdev, false);
5424 pci_set_power_state(pdev, PCI_D3hot);
5425 }
b3c8b4ba
AD		 5426
5427 return 0;
5428}
9d8d05ae 5429#endif /* CONFIG_PM */
b3c8b4ba
AD		 5430
5431static void ixgbe_shutdown(struct pci_dev *pdev)
5432{
9d8d05ae
RW		 5433 bool wake;
5434
5435 __ixgbe_shutdown(pdev, &wake);
5436
5437 if (system_state == SYSTEM_POWER_OFF) {
5438 pci_wake_from_d3(pdev, wake);
5439 pci_set_power_state(pdev, PCI_D3hot);
5440 }
b3c8b4ba
AD		 5441}
5442
9a799d71
AK		 5443/**
5444 * ixgbe_update_stats - Update the board statistics counters.
5445 * @adapter: board private structure
5446 **/
5447void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5448{
2d86f139 5449 struct net_device *netdev = adapter->netdev;
9a799d71 5450 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5451 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5452 u64 total_mpc = 0;
5453 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5454 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5455 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5456 u64 bytes = 0, packets = 0;
9a799d71 5457
d08935c2
DS		 5458 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5459 test_bit(__IXGBE_RESETTING, &adapter->state))
5460 return;
5461
94b982b2 5462 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5463 u64 rsc_count = 0;
94b982b2 5464 u64 rsc_flush = 0;
d51019a4
PW		 5465 for (i = 0; i < 16; i++)
5466 adapter->hw_rx_no_dma_resources +=
7ca647bd 5467 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5468 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5469 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5470 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5471 }
5472 adapter->rsc_total_count = rsc_count;
5473 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5474 }
5475
5b7da515
AD		 5476 for (i = 0; i < adapter->num_rx_queues; i++) {
5477 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5478 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5479 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5480 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5481 bytes += rx_ring->stats.bytes;
5482 packets += rx_ring->stats.packets;
5483 }
5484 adapter->non_eop_descs = non_eop_descs;
5485 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5486 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5487 netdev->stats.rx_bytes = bytes;
5488 netdev->stats.rx_packets = packets;
5489
5490 bytes = 0;
5491 packets = 0;
7ca3bc58 5492 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5493 for (i = 0; i < adapter->num_tx_queues; i++) {
5494 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5495 restart_queue += tx_ring->tx_stats.restart_queue;
5496 tx_busy += tx_ring->tx_stats.tx_busy;
5497 bytes += tx_ring->stats.bytes;
5498 packets += tx_ring->stats.packets;
5499 }
eb985f09 5500 adapter->restart_queue = restart_queue;
5b7da515
AD		 5501 adapter->tx_busy = tx_busy;
5502 netdev->stats.tx_bytes = bytes;
5503 netdev->stats.tx_packets = packets;
7ca3bc58 5504
7ca647bd 5505 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5506 for (i = 0; i < 8; i++) {
5507 /* for packet buffers not used, the register should read 0 */
5508 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5509 missed_rx += mpc;
7ca647bd
JP		 5510 hwstats->mpc[i] += mpc;
5511 total_mpc += hwstats->mpc[i];
e8e26350 5512 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5513 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5514 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5515 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5516 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5517 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350 5518 if (hw->mac.type == ixgbe_mac_82599EB) {
7ca647bd
JP		 5519 hwstats->pxonrxc[i] +=
5520 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5521 hwstats->pxoffrxc[i] +=
5522 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5523 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350 5524 } else {
7ca647bd
JP		 5525 hwstats->pxonrxc[i] +=
5526 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5527 hwstats->pxoffrxc[i] +=
5528 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
e8e26350 5529 }
7ca647bd
JP		 5530 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5531 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5532 }
7ca647bd 5533 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5534 /* work around hardware counting issue */
7ca647bd 5535 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5536
5537 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5538 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5539 u64 tmp;
7ca647bd 5540 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5541 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5542 /* 4 high bits of GORC */
7ca647bd
JP		 5543 hwstats->gorc += (tmp << 32);
5544 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5545 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5546 /* 4 high bits of GOTC */
7ca647bd
JP		 5547 hwstats->gotc += (tmp << 32);
5548 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5549 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5550 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5551 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5552 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5553 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5554#ifdef IXGBE_FCOE
7ca647bd
JP		 5555 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5556 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5557 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5558 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5559 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5560 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5561#endif /* IXGBE_FCOE */
e8e26350 5562 } else {
7ca647bd
JP		 5563 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5564 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5565 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5566 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5567 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
e8e26350 5568 }
9a799d71 5569 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5570 hwstats->bprc += bprc;
5571 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5572 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5573 hwstats->mprc -= bprc;
5574 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5575 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5576 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5577 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5578 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5579 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5580 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5581 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5582 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5583 hwstats->lxontxc += lxon;
6f11eef7 5584 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5585 hwstats->lxofftxc += lxoff;
5586 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5587 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5588 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5589 /*
5590 * 82598 errata - tx of flow control packets is included in tx counters
5591 */
5592 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5593 hwstats->gptc -= xon_off_tot;
5594 hwstats->mptc -= xon_off_tot;
5595 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5596 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5597 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5598 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5599 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5600 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5601 hwstats->ptc64 -= xon_off_tot;
5602 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5603 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5604 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5605 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5606 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5607 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5608
5609 /* Fill out the OS statistics structure */
7ca647bd 5610 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5611
5612 /* Rx Errors */
7ca647bd 5613 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5614 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5615 netdev->stats.rx_length_errors = hwstats->rlec;
5616 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5617 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5618}
5619
5620/**
5621 * ixgbe_watchdog - Timer Call-back
5622 * @data: pointer to adapter cast into an unsigned long
5623 **/
5624static void ixgbe_watchdog(unsigned long data)
5625{
5626 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5627 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5628 u64 eics = 0;
5629 int i;
cf8280ee 5630
fe49f04a
AD		 5631 /*
5632 * Do the watchdog outside of interrupt context due to the lovely
5633 * delays that some of the newer hardware requires
5634 */
22d5a71b 5635
fe49f04a
AD		 5636 if (test_bit(__IXGBE_DOWN, &adapter->state))
5637 goto watchdog_short_circuit;
22d5a71b 5638
fe49f04a
AD		 5639 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5640 /*
5641 * for legacy and MSI interrupts don't set any bits
5642 * that are enabled for EIAM, because this operation
5643 * would set *both* EIMS and EICS for any bit in EIAM
5644 */
5645 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5646 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5647 goto watchdog_reschedule;
5648 }
5649
5650 /* get one bit for every active tx/rx interrupt vector */
5651 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5652 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5653 if (qv->rxr_count || qv->txr_count)
5654 eics |= ((u64)1 << i);
cf8280ee 5655 }
9a799d71 5656
fe49f04a
AD		 5657 /* Cause software interrupt to ensure rx rings are cleaned */
5658 ixgbe_irq_rearm_queues(adapter, eics);
5659
5660watchdog_reschedule:
5661 /* Reset the timer */
5662 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5663
5664watchdog_short_circuit:
cf8280ee
JB		 5665 schedule_work(&adapter->watchdog_task);
5666}
5667
e8e26350
PW		 5668/**
5669 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5670 * @work: pointer to work_struct containing our data
5671 **/
5672static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5673{
5674 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5675 struct ixgbe_adapter,
5676 multispeed_fiber_task);
e8e26350
PW		 5677 struct ixgbe_hw *hw = &adapter->hw;
5678 u32 autoneg;
8620a103 5679 bool negotiation;
e8e26350
PW		 5680
5681 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5682 autoneg = hw->phy.autoneg_advertised;
5683 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5684 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5685 hw->mac.autotry_restart = false;
8620a103
MC		 5686 if (hw->mac.ops.setup_link)
5687 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5688 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5689 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5690}
5691
5692/**
5693 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5694 * @work: pointer to work_struct containing our data
5695 **/
5696static void ixgbe_sfp_config_module_task(struct work_struct *work)
5697{
5698 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5699 struct ixgbe_adapter,
5700 sfp_config_module_task);
e8e26350
PW		 5701 struct ixgbe_hw *hw = &adapter->hw;
5702 u32 err;
5703
5704 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5705
5706 /* Time for electrical oscillations to settle down */
5707 msleep(100);
e8e26350 5708 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5709
e8e26350 5710 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5711 e_dev_err("failed to initialize because an unsupported SFP+ "
5712 "module type was detected.\n");
5713 e_dev_err("Reload the driver after installing a supported "
5714 "module.\n");
63d6e1d8 5715 unregister_netdev(adapter->netdev);
e8e26350
PW		 5716 return;
5717 }
5718 hw->mac.ops.setup_sfp(hw);
5719
8d1c3c07 5720 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5721 /* This will also work for DA Twinax connections */
5722 schedule_work(&adapter->multispeed_fiber_task);
5723 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5724}
5725
c4cf55e5
PWJ		 5726/**
5727 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5728 * @work: pointer to work_struct containing our data
5729 **/
5730static void ixgbe_fdir_reinit_task(struct work_struct *work)
5731{
5732 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5733 struct ixgbe_adapter,
5734 fdir_reinit_task);
c4cf55e5
PWJ		 5735 struct ixgbe_hw *hw = &adapter->hw;
5736 int i;
5737
5738 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5739 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 5740 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5741 &(adapter->tx_ring[i]->state));
c4cf55e5 5742 } else {
396e799c 5743 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5744 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5745 }
5746 /* Done FDIR Re-initialization, enable transmits */
5747 netif_tx_start_all_queues(adapter->netdev);
5748}
5749
10eec955
JF		 5750static DEFINE_MUTEX(ixgbe_watchdog_lock);
5751
cf8280ee 5752/**
69888674
AD		 5753 * ixgbe_watchdog_task - worker thread to bring link up
5754 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5755 **/
5756static void ixgbe_watchdog_task(struct work_struct *work)
5757{
5758 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5759 struct ixgbe_adapter,
5760 watchdog_task);
cf8280ee
JB		 5761 struct net_device *netdev = adapter->netdev;
5762 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5763 u32 link_speed;
5764 bool link_up;
bc59fcda
NS		 5765 int i;
5766 struct ixgbe_ring *tx_ring;
5767 int some_tx_pending = 0;
cf8280ee 5768
10eec955
JF		 5769 mutex_lock(&ixgbe_watchdog_lock);
5770
5771 link_up = adapter->link_up;
5772 link_speed = adapter->link_speed;
cf8280ee
JB		 5773
5774 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5775 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5776 if (link_up) {
5777#ifdef CONFIG_DCB
5778 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5779 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5780 hw->mac.ops.fc_enable(hw, i);
264857b8 5781 } else {
620fa036 5782 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5783 }
5784#else
620fa036 5785 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5786#endif
5787 }
5788
cf8280ee
JB		 5789 if (link_up ||
5790 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5791 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5792 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5793 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5794 }
5795 adapter->link_up = link_up;
5796 adapter->link_speed = link_speed;
5797 }
9a799d71
AK		 5798
5799 if (link_up) {
5800 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5801 bool flow_rx, flow_tx;
5802
5803 if (hw->mac.type == ixgbe_mac_82599EB) {
5804 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5805 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5806 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5807 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5808 } else {
5809 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5810 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5811 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5812 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5813 }
5814
396e799c 5815 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5816 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5817 "10 Gbps" :
5818 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5819 "1 Gbps" : "unknown speed")),
e8e26350 5820 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5821 (flow_rx ? "RX" :
5822 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5823
5824 netif_carrier_on(netdev);
9a799d71
AK		 5825 } else {
5826 /* Force detection of hung controller */
7d637bcc
AD		 5827 for (i = 0; i < adapter->num_tx_queues; i++) {
5828 tx_ring = adapter->tx_ring[i];
5829 set_check_for_tx_hang(tx_ring);
5830 }
9a799d71
AK		 5831 }
5832 } else {
cf8280ee
JB		 5833 adapter->link_up = false;
5834 adapter->link_speed = 0;
9a799d71 5835 if (netif_carrier_ok(netdev)) {
396e799c 5836 e_info(drv, "NIC Link is Down\n");
9a799d71 5837 netif_carrier_off(netdev);
9a799d71
AK		 5838 }
5839 }
5840
bc59fcda
NS		 5841 if (!netif_carrier_ok(netdev)) {
5842 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5843 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5844 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5845 some_tx_pending = 1;
5846 break;
5847 }
5848 }
5849
5850 if (some_tx_pending) {
5851 /* We've lost link, so the controller stops DMA,
5852 * but we've got queued Tx work that's never going
5853 * to get done, so reset controller to flush Tx.
5854 * (Do the reset outside of interrupt context).
5855 */
5856 schedule_work(&adapter->reset_task);
5857 }
5858 }
5859
9a799d71 5860 ixgbe_update_stats(adapter);
10eec955 5861 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5862}
5863
9a799d71 5864static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 5865 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 5866 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 5867{
5868 struct ixgbe_adv_tx_context_desc *context_desc;
5869 unsigned int i;
5870 int err;
5871 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5872 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5873 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5874
5875 if (skb_is_gso(skb)) {
5876 if (skb_header_cloned(skb)) {
5877 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5878 if (err)
5879 return err;
5880 }
5881 l4len = tcp_hdrlen(skb);
5882 *hdr_len += l4len;
5883
5e09a105 5884 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5885 struct iphdr *iph = ip_hdr(skb);
5886 iph->tot_len = 0;
5887 iph->check = 0;
5888 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5889 iph->daddr, 0,
5890 IPPROTO_TCP,
5891 0);
8e1e8a47 5892 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5893 ipv6_hdr(skb)->payload_len = 0;
5894 tcp_hdr(skb)->check =
5895 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5896 &ipv6_hdr(skb)->daddr,
5897 0, IPPROTO_TCP, 0);
9a799d71
AK		 5898 }
5899
5900 i = tx_ring->next_to_use;
5901
5902 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5903 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5904
5905 /* VLAN MACLEN IPLEN */
5906 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5907 vlan_macip_lens |=
5908 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5909 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5910 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5911 *hdr_len += skb_network_offset(skb);
5912 vlan_macip_lens |=
5913 (skb_transport_header(skb) - skb_network_header(skb));
5914 *hdr_len +=
5915 (skb_transport_header(skb) - skb_network_header(skb));
5916 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5917 context_desc->seqnum_seed = 0;
5918
5919 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5920 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5921 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5922
5e09a105 5923 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 5924 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5925 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5926 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5927
5928 /* MSS L4LEN IDX */
9f8cdf4f 5929 mss_l4len_idx =
9a799d71
AK		 5930 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5931 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5932 /* use index 1 for TSO */
5933 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5934 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5935
5936 tx_buffer_info->time_stamp = jiffies;
5937 tx_buffer_info->next_to_watch = i;
5938
5939 i++;
5940 if (i == tx_ring->count)
5941 i = 0;
5942 tx_ring->next_to_use = i;
5943
5944 return true;
5945 }
5946 return false;
5947}
5948
5e09a105
HZ		 5949static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5950 __be16 protocol)
7ca647bd
JP		 5951{
5952 u32 rtn = 0;
7ca647bd
JP		 5953
5954 switch (protocol) {
5955 case cpu_to_be16(ETH_P_IP):
5956 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5957 switch (ip_hdr(skb)->protocol) {
5958 case IPPROTO_TCP:
5959 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5960 break;
5961 case IPPROTO_SCTP:
5962 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5963 break;
5964 }
5965 break;
5966 case cpu_to_be16(ETH_P_IPV6):
5967 /* XXX what about other V6 headers?? */
5968 switch (ipv6_hdr(skb)->nexthdr) {
5969 case IPPROTO_TCP:
5970 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5971 break;
5972 case IPPROTO_SCTP:
5973 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5974 break;
5975 }
5976 break;
5977 default:
5978 if (unlikely(net_ratelimit()))
5979 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 5980 protocol);
7ca647bd
JP		 5981 break;
5982 }
5983
5984 return rtn;
5985}
5986
9a799d71 5987static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 5988 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 5989 struct sk_buff *skb, u32 tx_flags,
5990 __be16 protocol)
9a799d71
AK		 5991{
5992 struct ixgbe_adv_tx_context_desc *context_desc;
5993 unsigned int i;
5994 struct ixgbe_tx_buffer *tx_buffer_info;
5995 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5996
5997 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5998 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5999 i = tx_ring->next_to_use;
6000 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6001 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6002
6003 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6004 vlan_macip_lens |=
6005 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6006 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6007 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6008 if (skb->ip_summed == CHECKSUM_PARTIAL)
6009 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6010 skb_network_header(skb));
9a799d71
AK		 6011
6012 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6013 context_desc->seqnum_seed = 0;
6014
6015 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6016 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6017
7ca647bd 6018 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6019 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6020
6021 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6022 /* use index zero for tx checksum offload */
9a799d71
AK		 6023 context_desc->mss_l4len_idx = 0;
6024
6025 tx_buffer_info->time_stamp = jiffies;
6026 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6027
9a799d71
AK		 6028 i++;
6029 if (i == tx_ring->count)
6030 i = 0;
6031 tx_ring->next_to_use = i;
6032
6033 return true;
6034 }
9f8cdf4f 6035
9a799d71
AK		 6036 return false;
6037}
6038
6039static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6040 struct ixgbe_ring *tx_ring,
6041 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6042 unsigned int first, const u8 hdr_len)
9a799d71 6043{
b6ec895e 6044 struct device *dev = tx_ring->dev;
9a799d71 6045 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6046 unsigned int len;
6047 unsigned int total = skb->len;
9a799d71
AK		 6048 unsigned int offset = 0, size, count = 0, i;
6049 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6050 unsigned int f;
8ad494b0
AD		 6051 unsigned int bytecount = skb->len;
6052 u16 gso_segs = 1;
9a799d71
AK		 6053
6054 i = tx_ring->next_to_use;
6055
eacd73f7
YZ		 6056 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6057 /* excluding fcoe_crc_eof for FCoE */
6058 total -= sizeof(struct fcoe_crc_eof);
6059
6060 len = min(skb_headlen(skb), total);
9a799d71
AK		 6061 while (len) {
6062 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6063 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6064
6065 tx_buffer_info->length = size;
e5a43549 6066 tx_buffer_info->mapped_as_page = false;
b6ec895e 6067 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6068 skb->data + offset,
1b507730 6069 size, DMA_TO_DEVICE);
b6ec895e 6070 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6071 goto dma_error;
9a799d71
AK		 6072 tx_buffer_info->time_stamp = jiffies;
6073 tx_buffer_info->next_to_watch = i;
6074
6075 len -= size;
eacd73f7 6076 total -= size;
9a799d71
AK		 6077 offset += size;
6078 count++;
44df32c5
AD		 6079
6080 if (len) {
6081 i++;
6082 if (i == tx_ring->count)
6083 i = 0;
6084 }
9a799d71
AK		 6085 }
6086
6087 for (f = 0; f < nr_frags; f++) {
6088 struct skb_frag_struct *frag;
6089
6090 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6091 len = min((unsigned int)frag->size, total);
e5a43549 6092 offset = frag->page_offset;
9a799d71
AK		 6093
6094 while (len) {
44df32c5
AD		 6095 i++;
6096 if (i == tx_ring->count)
6097 i = 0;
6098
9a799d71
AK		 6099 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6100 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6101
6102 tx_buffer_info->length = size;
b6ec895e 6103 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6104 frag->page,
6105 offset, size,
1b507730 6106 DMA_TO_DEVICE);
e5a43549 6107 tx_buffer_info->mapped_as_page = true;
b6ec895e 6108 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6109 goto dma_error;
9a799d71
AK		 6110 tx_buffer_info->time_stamp = jiffies;
6111 tx_buffer_info->next_to_watch = i;
6112
6113 len -= size;
eacd73f7 6114 total -= size;
9a799d71
AK		 6115 offset += size;
6116 count++;
9a799d71 6117 }
eacd73f7
YZ		 6118 if (total == 0)
6119 break;
9a799d71 6120 }
44df32c5 6121
8ad494b0
AD		 6122 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6123 gso_segs = skb_shinfo(skb)->gso_segs;
6124#ifdef IXGBE_FCOE
6125 /* adjust for FCoE Sequence Offload */
6126 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6127 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6128 skb_shinfo(skb)->gso_size);
6129#endif /* IXGBE_FCOE */
6130 bytecount += (gso_segs - 1) * hdr_len;
6131
6132 /* multiply data chunks by size of headers */
6133 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6134 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6135 tx_ring->tx_buffer_info[i].skb = skb;
6136 tx_ring->tx_buffer_info[first].next_to_watch = i;
6137
e5a43549
AD		 6138 return count;
6139
6140dma_error:
849c4542 6141 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6142
6143 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6144 tx_buffer_info->dma = 0;
6145 tx_buffer_info->time_stamp = 0;
6146 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6147 if (count)
6148 count--;
e5a43549
AD		 6149
6150 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6151 while (count--) {
e8e9f696 6152 if (i == 0)
e5a43549 6153 i += tx_ring->count;
c1fa347f 6154 i--;
e5a43549 6155 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6156 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6157 }
6158
e44d38e1 6159 return 0;
9a799d71
AK		 6160}
6161
84ea2591 6162static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6163 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6164{
6165 union ixgbe_adv_tx_desc *tx_desc = NULL;
6166 struct ixgbe_tx_buffer *tx_buffer_info;
6167 u32 olinfo_status = 0, cmd_type_len = 0;
6168 unsigned int i;
6169 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6170
6171 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6172
6173 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6174
6175 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6176 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6177
6178 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6179 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6180
6181 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6182 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6183
4eeae6fd
PW		 6184 /* use index 1 context for tso */
6185 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6186 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6187 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6188 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6189
6190 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6191 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6192 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6193
eacd73f7
YZ		 6194 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6195 olinfo_status |= IXGBE_ADVTXD_CC;
6196 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6197 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6198 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6199 }
6200
9a799d71
AK		 6201 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6202
6203 i = tx_ring->next_to_use;
6204 while (count--) {
6205 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6206 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6207 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6208 tx_desc->read.cmd_type_len =
e8e9f696 6209 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6210 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6211 i++;
6212 if (i == tx_ring->count)
6213 i = 0;
6214 }
6215
6216 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6217
6218 /*
6219 * Force memory writes to complete before letting h/w
6220 * know there are new descriptors to fetch. (Only
6221 * applicable for weak-ordered memory model archs,
6222 * such as IA-64).
6223 */
6224 wmb();
6225
6226 tx_ring->next_to_use = i;
84ea2591 6227 writel(i, tx_ring->tail);
9a799d71
AK		 6228}
6229
c4cf55e5 6230static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5e09a105 6231 int queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6232{
c4cf55e5
PWJ		 6233 struct ixgbe_atr_input atr_input;
6234 struct tcphdr *th;
c4cf55e5
PWJ		 6235 struct iphdr *iph = ip_hdr(skb);
6236 struct ethhdr *eth = (struct ethhdr *)skb->data;
6237 u16 vlan_id, src_port, dst_port, flex_bytes;
6238 u32 src_ipv4_addr, dst_ipv4_addr;
6239 u8 l4type = 0;
6240
d3ead241 6241 /* Right now, we support IPv4 only */
5e09a105 6242 if (protocol != htons(ETH_P_IP))
d3ead241 6243 return;
c4cf55e5
PWJ		 6244 /* check if we're UDP or TCP */
6245 if (iph->protocol == IPPROTO_TCP) {
6246 th = tcp_hdr(skb);
6247 src_port = th->source;
6248 dst_port = th->dest;
6249 l4type |= IXGBE_ATR_L4TYPE_TCP;
6250 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6251 } else {
6252 /* Unsupported L4 header, just bail here */
6253 return;
6254 }
6255
6256 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6257
6258 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6259 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6260 src_ipv4_addr = iph->saddr;
6261 dst_ipv4_addr = iph->daddr;
6262 flex_bytes = eth->h_proto;
6263
6264 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6265 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6266 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6267 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6268 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6269 /* src and dst are inverted, think how the receiver sees them */
6270 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6271 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6272
6273 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6274 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6275}
6276
fc77dc3c 6277static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6278{
fc77dc3c 6279 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6280 /* Herbert's original patch had:
6281 * smp_mb__after_netif_stop_queue();
6282 * but since that doesn't exist yet, just open code it. */
6283 smp_mb();
6284
6285 /* We need to check again in a case another CPU has just
6286 * made room available. */
6287 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6288 return -EBUSY;
6289
6290 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6291 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6292 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6293 return 0;
6294}
6295
fc77dc3c 6296static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6297{
6298 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6299 return 0;
fc77dc3c 6300 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6301}
6302
09a3b1f8
SH		 6303static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6304{
6305 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6306 int txq = smp_processor_id();
56075a98 6307#ifdef IXGBE_FCOE
5e09a105
HZ		 6308 __be16 protocol;
6309
6310 protocol = vlan_get_protocol(skb);
6311
6312 if ((protocol == htons(ETH_P_FCOE)) ||
6313 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6314 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6315 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6316 txq += adapter->ring_feature[RING_F_FCOE].mask;
6317 return txq;
4bc091d8 6318#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6319 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6320 txq = adapter->fcoe.up;
6321 return txq;
4bc091d8 6322#endif
56075a98
JF		 6323 }
6324 }
6325#endif
6326
fdd3d631
KK		 6327 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6328 while (unlikely(txq >= dev->real_num_tx_queues))
6329 txq -= dev->real_num_tx_queues;
5f715823 6330 return txq;
fdd3d631 6331 }
c4cf55e5 6332
2ea186ae
JF		 6333 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6334 if (skb->priority == TC_PRIO_CONTROL)
6335 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6336 else
6337 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6338 >> 13;
6339 return txq;
6340 }
09a3b1f8
SH		 6341
6342 return skb_tx_hash(dev, skb);
6343}
6344
fc77dc3c 6345netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6346 struct ixgbe_adapter *adapter,
6347 struct ixgbe_ring *tx_ring)
9a799d71 6348{
fc77dc3c 6349 struct net_device *netdev = tx_ring->netdev;
60d51134 6350 struct netdev_queue *txq;
9a799d71
AK		 6351 unsigned int first;
6352 unsigned int tx_flags = 0;
30eba97a 6353 u8 hdr_len = 0;
5f715823 6354 int tso;
9a799d71
AK		 6355 int count = 0;
6356 unsigned int f;
5e09a105
HZ		 6357 __be16 protocol;
6358
6359 protocol = vlan_get_protocol(skb);
9f8cdf4f 6360
eab6d18d 6361 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6362 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6363 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6364 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6365 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6366 }
6367 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6368 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6369 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6370 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6371 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6372 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6373 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6374 }
eacd73f7 6375
09ad1cc0 6376#ifdef IXGBE_FCOE
56075a98
JF		 6377 /* for FCoE with DCB, we force the priority to what
6378 * was specified by the switch */
6379 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6380 (protocol == htons(ETH_P_FCOE) ||
6381 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6382#ifdef CONFIG_IXGBE_DCB
6383 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6384 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6385 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6386 tx_flags |= ((adapter->fcoe.up << 13)
6387 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6388 }
6389#endif
ca77cd59 6390 /* flag for FCoE offloads */
5e09a105 6391 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6392 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6393 }
ca77cd59
RL		 6394#endif
6395
eacd73f7 6396 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6397 if (skb_is_gso(skb) ||
6398 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6399 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6400 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6401 count++;
6402
9f8cdf4f
JB		 6403 count += TXD_USE_COUNT(skb_headlen(skb));
6404 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6405 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6406
fc77dc3c 6407 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6408 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6409 return NETDEV_TX_BUSY;
6410 }
9a799d71 6411
9a799d71 6412 first = tx_ring->next_to_use;
eacd73f7
YZ		 6413 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6414#ifdef IXGBE_FCOE
6415 /* setup tx offload for FCoE */
6416 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6417 if (tso < 0) {
6418 dev_kfree_skb_any(skb);
6419 return NETDEV_TX_OK;
6420 }
6421 if (tso)
6422 tx_flags |= IXGBE_TX_FLAGS_FSO;
6423#endif /* IXGBE_FCOE */
6424 } else {
5e09a105 6425 if (protocol == htons(ETH_P_IP))
eacd73f7 6426 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6427 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6428 protocol);
eacd73f7
YZ		 6429 if (tso < 0) {
6430 dev_kfree_skb_any(skb);
6431 return NETDEV_TX_OK;
6432 }
9a799d71 6433
eacd73f7
YZ		 6434 if (tso)
6435 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6436 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6437 protocol) &&
eacd73f7
YZ		 6438 (skb->ip_summed == CHECKSUM_PARTIAL))
6439 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6440 }
9a799d71 6441
8ad494b0 6442 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6443 if (count) {
c4cf55e5
PWJ		 6444 /* add the ATR filter if ATR is on */
6445 if (tx_ring->atr_sample_rate) {
6446 ++tx_ring->atr_count;
6447 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
7d637bcc
AD		 6448 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6449 &tx_ring->state)) {
c4cf55e5 6450 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6451 tx_flags, protocol);
c4cf55e5
PWJ		 6452 tx_ring->atr_count = 0;
6453 }
6454 }
60d51134
ED		 6455 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6456 txq->tx_bytes += skb->len;
6457 txq->tx_packets++;
84ea2591 6458 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6459 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6460
44df32c5
AD		 6461 } else {
6462 dev_kfree_skb_any(skb);
6463 tx_ring->tx_buffer_info[first].time_stamp = 0;
6464 tx_ring->next_to_use = first;
6465 }
9a799d71
AK		 6466
6467 return NETDEV_TX_OK;
6468}
6469
84418e3b
AD		 6470static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6471{
6472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6473 struct ixgbe_ring *tx_ring;
6474
6475 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6476 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6477}
6478
9a799d71
AK		 6479/**
6480 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6481 * @netdev: network interface device structure
6482 * @p: pointer to an address structure
6483 *
6484 * Returns 0 on success, negative on failure
6485 **/
6486static int ixgbe_set_mac(struct net_device *netdev, void *p)
6487{
6488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6489 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6490 struct sockaddr *addr = p;
6491
6492 if (!is_valid_ether_addr(addr->sa_data))
6493 return -EADDRNOTAVAIL;
6494
6495 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6496 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6497
1cdd1ec8
GR		 6498 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6499 IXGBE_RAH_AV);
9a799d71
AK		 6500
6501 return 0;
6502}
6503
6b73e10d
BH		 6504static int
6505ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6506{
6507 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6508 struct ixgbe_hw *hw = &adapter->hw;
6509 u16 value;
6510 int rc;
6511
6512 if (prtad != hw->phy.mdio.prtad)
6513 return -EINVAL;
6514 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6515 if (!rc)
6516 rc = value;
6517 return rc;
6518}
6519
6520static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6521 u16 addr, u16 value)
6522{
6523 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6524 struct ixgbe_hw *hw = &adapter->hw;
6525
6526 if (prtad != hw->phy.mdio.prtad)
6527 return -EINVAL;
6528 return hw->phy.ops.write_reg(hw, addr, devad, value);
6529}
6530
6531static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6532{
6533 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6534
6535 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6536}
6537
0365e6e4
PW		 6538/**
6539 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6540 * netdev->dev_addrs
0365e6e4
PW		 6541 * @netdev: network interface device structure
6542 *
6543 * Returns non-zero on failure
6544 **/
6545static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6546{
6547 int err = 0;
6548 struct ixgbe_adapter *adapter = netdev_priv(dev);
6549 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6550
6551 if (is_valid_ether_addr(mac->san_addr)) {
6552 rtnl_lock();
6553 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6554 rtnl_unlock();
6555 }
6556 return err;
6557}
6558
6559/**
6560 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6561 * netdev->dev_addrs
0365e6e4
PW		 6562 * @netdev: network interface device structure
6563 *
6564 * Returns non-zero on failure
6565 **/
6566static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6567{
6568 int err = 0;
6569 struct ixgbe_adapter *adapter = netdev_priv(dev);
6570 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6571
6572 if (is_valid_ether_addr(mac->san_addr)) {
6573 rtnl_lock();
6574 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6575 rtnl_unlock();
6576 }
6577 return err;
6578}
6579
9a799d71
AK		 6580#ifdef CONFIG_NET_POLL_CONTROLLER
6581/*
6582 * Polling 'interrupt' - used by things like netconsole to send skbs
6583 * without having to re-enable interrupts. It's not called while
6584 * the interrupt routine is executing.
6585 */
6586static void ixgbe_netpoll(struct net_device *netdev)
6587{
6588 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6589 int i;
9a799d71 6590
1a647bd2
AD		 6591 /* if interface is down do nothing */
6592 if (test_bit(__IXGBE_DOWN, &adapter->state))
6593 return;
6594
9a799d71 6595 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6596 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6597 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6598 for (i = 0; i < num_q_vectors; i++) {
6599 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6600 ixgbe_msix_clean_many(0, q_vector);
6601 }
6602 } else {
6603 ixgbe_intr(adapter->pdev->irq, netdev);
6604 }
9a799d71 6605 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6606}
6607#endif
6608
de1036b1
ED		 6609static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6610 struct rtnl_link_stats64 *stats)
6611{
6612 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6613 int i;
6614
6615 /* accurate rx/tx bytes/packets stats */
6616 dev_txq_stats_fold(netdev, stats);
1a51502b 6617 rcu_read_lock();
de1036b1 6618 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6619 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6620 u64 bytes, packets;
6621 unsigned int start;
6622
1a51502b
ED		 6623 if (ring) {
6624 do {
6625 start = u64_stats_fetch_begin_bh(&ring->syncp);
6626 packets = ring->stats.packets;
6627 bytes = ring->stats.bytes;
6628 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6629 stats->rx_packets += packets;
6630 stats->rx_bytes += bytes;
6631 }
de1036b1 6632 }
1a51502b 6633 rcu_read_unlock();
de1036b1
ED		 6634 /* following stats updated by ixgbe_watchdog_task() */
6635 stats->multicast = netdev->stats.multicast;
6636 stats->rx_errors = netdev->stats.rx_errors;
6637 stats->rx_length_errors = netdev->stats.rx_length_errors;
6638 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6639 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6640 return stats;
6641}
6642
6643
0edc3527 6644static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6645 .ndo_open = ixgbe_open,
0edc3527 6646 .ndo_stop = ixgbe_close,
00829823 6647 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6648 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6649 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6650 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6651 .ndo_validate_addr = eth_validate_addr,
6652 .ndo_set_mac_address = ixgbe_set_mac,
6653 .ndo_change_mtu = ixgbe_change_mtu,
6654 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6655 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6656 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6657 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6658 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6659 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6660 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6661 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6662 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6663#ifdef CONFIG_NET_POLL_CONTROLLER
6664 .ndo_poll_controller = ixgbe_netpoll,
6665#endif
332d4a7d
YZ		 6666#ifdef IXGBE_FCOE
6667 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6668 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6669 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6670 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6671 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6672#endif /* IXGBE_FCOE */
0edc3527
SH		 6673};
6674
1cdd1ec8
GR		 6675static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6676 const struct ixgbe_info *ii)
6677{
6678#ifdef CONFIG_PCI_IOV
6679 struct ixgbe_hw *hw = &adapter->hw;
6680 int err;
6681
6682 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6683 return;
6684
6685 /* The 82599 supports up to 64 VFs per physical function
6686 * but this implementation limits allocation to 63 so that
6687 * basic networking resources are still available to the
6688 * physical function
6689 */
6690 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6691 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6692 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6693 if (err) {
396e799c 6694 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6695 goto err_novfs;
6696 }
6697 /* If call to enable VFs succeeded then allocate memory
6698 * for per VF control structures.
6699 */
6700 adapter->vfinfo =
6701 kcalloc(adapter->num_vfs,
6702 sizeof(struct vf_data_storage), GFP_KERNEL);
6703 if (adapter->vfinfo) {
6704 /* Now that we're sure SR-IOV is enabled
6705 * and memory allocated set up the mailbox parameters
6706 */
6707 ixgbe_init_mbx_params_pf(hw);
6708 memcpy(&hw->mbx.ops, ii->mbx_ops,
6709 sizeof(hw->mbx.ops));
6710
6711 /* Disable RSC when in SR-IOV mode */
6712 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6713 IXGBE_FLAG2_RSC_ENABLED);
6714 return;
6715 }
6716
6717 /* Oh oh */
396e799c
ET		 6718 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6719 "SRIOV disabled\n");
1cdd1ec8
GR		 6720 pci_disable_sriov(adapter->pdev);
6721
6722err_novfs:
6723 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6724 adapter->num_vfs = 0;
6725#endif /* CONFIG_PCI_IOV */
6726}
6727
9a799d71
AK		 6728/**
6729 * ixgbe_probe - Device Initialization Routine
6730 * @pdev: PCI device information struct
6731 * @ent: entry in ixgbe_pci_tbl
6732 *
6733 * Returns 0 on success, negative on failure
6734 *
6735 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6736 * The OS initialization, configuring of the adapter private structure,
6737 * and a hardware reset occur.
6738 **/
6739static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6740 const struct pci_device_id *ent)
9a799d71
AK		 6741{
6742 struct net_device *netdev;
6743 struct ixgbe_adapter *adapter = NULL;
6744 struct ixgbe_hw *hw;
6745 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6746 static int cards_found;
6747 int i, err, pci_using_dac;
c85a2618 6748 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6749#ifdef IXGBE_FCOE
6750 u16 device_caps;
6751#endif
c44ade9e 6752 u32 part_num, eec;
9a799d71 6753
bded64a7
AG		 6754 /* Catch broken hardware that put the wrong VF device ID in
6755 * the PCIe SR-IOV capability.
6756 */
6757 if (pdev->is_virtfn) {
6758 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6759 pci_name(pdev), pdev->vendor, pdev->device);
6760 return -EINVAL;
6761 }
6762
9ce77666 6763 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6764 if (err)
6765 return err;
6766
1b507730
NN		 6767 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6768 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6769 pci_using_dac = 1;
6770 } else {
1b507730 6771 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6772 if (err) {
1b507730
NN		 6773 err = dma_set_coherent_mask(&pdev->dev,
6774 DMA_BIT_MASK(32));
9a799d71 6775 if (err) {
b8bc0421
DC		 6776 dev_err(&pdev->dev,
6777 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6778 goto err_dma;
6779 }
6780 }
6781 pci_using_dac = 0;
6782 }
6783
9ce77666 6784 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6785 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6786 if (err) {
b8bc0421
DC		 6787 dev_err(&pdev->dev,
6788 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6789 goto err_pci_reg;
6790 }
6791
19d5afd4 6792 pci_enable_pcie_error_reporting(pdev);
6fabd715 6793
9a799d71 6794 pci_set_master(pdev);
fb3b27bc 6795 pci_save_state(pdev);
9a799d71 6796
c85a2618
JF		 6797 if (ii->mac == ixgbe_mac_82598EB)
6798 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6799 else
6800 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6801
6802 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6803#ifdef IXGBE_FCOE
6804 indices += min_t(unsigned int, num_possible_cpus(),
6805 IXGBE_MAX_FCOE_INDICES);
6806#endif
c85a2618 6807 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6808 if (!netdev) {
6809 err = -ENOMEM;
6810 goto err_alloc_etherdev;
6811 }
6812
9a799d71
AK		 6813 SET_NETDEV_DEV(netdev, &pdev->dev);
6814
9a799d71 6815 adapter = netdev_priv(netdev);
c60fbb00 6816 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 6817
6818 adapter->netdev = netdev;
6819 adapter->pdev = pdev;
6820 hw = &adapter->hw;
6821 hw->back = adapter;
6822 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6823
05857980 6824 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6825 pci_resource_len(pdev, 0));
9a799d71
AK		 6826 if (!hw->hw_addr) {
6827 err = -EIO;
6828 goto err_ioremap;
6829 }
6830
6831 for (i = 1; i <= 5; i++) {
6832 if (pci_resource_len(pdev, i) == 0)
6833 continue;
6834 }
6835
0edc3527 6836 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6837 ixgbe_set_ethtool_ops(netdev);
9a799d71 6838 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6839 strcpy(netdev->name, pci_name(pdev));
6840
9a799d71
AK		 6841 adapter->bd_number = cards_found;
6842
9a799d71
AK		 6843 /* Setup hw api */
6844 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6845 hw->mac.type = ii->mac;
9a799d71 6846
c44ade9e
JB		 6847 /* EEPROM */
6848 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6849 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6850 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6851 if (!(eec & (1 << 8)))
6852 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6853
6854 /* PHY */
6855 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6856 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6857 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6858 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6859 hw->phy.mdio.mmds = 0;
6860 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6861 hw->phy.mdio.dev = netdev;
6862 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6863 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6864
6865 /* set up this timer and work struct before calling get_invariants
6866 * which might start the timer
6867 */
6868 init_timer(&adapter->sfp_timer);
c061b18d 6869 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6870 adapter->sfp_timer.data = (unsigned long) adapter;
6871
6872 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6873
e8e26350
PW		 6874 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6875 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6876
6877 /* a new SFP+ module arrival, called from GPI SDP2 context */
6878 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6879 ixgbe_sfp_config_module_task);
e8e26350 6880
8ca783ab 6881 ii->get_invariants(hw);
9a799d71
AK		 6882
6883 /* setup the private structure */
6884 err = ixgbe_sw_init(adapter);
6885 if (err)
6886 goto err_sw_init;
6887
e86bff0e
DS		 6888 /* Make it possible the adapter to be woken up via WOL */
6889 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6890 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6891
bf069c97
DS		 6892 /*
6893 * If there is a fan on this device and it has failed log the
6894 * failure.
6895 */
6896 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6897 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6898 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6899 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6900 }
6901
c44ade9e 6902 /* reset_hw fills in the perm_addr as well */
119fc60a 6903 hw->phy.reset_if_overtemp = true;
c44ade9e 6904 err = hw->mac.ops.reset_hw(hw);
119fc60a 6905 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6906 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6907 hw->mac.type == ixgbe_mac_82598EB) {
6908 /*
6909 * Start a kernel thread to watch for a module to arrive.
6910 * Only do this for 82598, since 82599 will generate
6911 * interrupts on module arrival.
6912 */
6913 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6914 mod_timer(&adapter->sfp_timer,
6915 round_jiffies(jiffies + (2 * HZ)));
6916 err = 0;
6917 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6918 e_dev_err("failed to initialize because an unsupported SFP+ "
6919 "module type was detected.\n");
6920 e_dev_err("Reload the driver after installing a supported "
6921 "module.\n");
04f165ef
PW		 6922 goto err_sw_init;
6923 } else if (err) {
849c4542 6924 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6925 goto err_sw_init;
6926 }
6927
1cdd1ec8
GR		 6928 ixgbe_probe_vf(adapter, ii);
6929
396e799c 6930 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6931 NETIF_F_IP_CSUM |
6932 NETIF_F_HW_VLAN_TX |
6933 NETIF_F_HW_VLAN_RX |
6934 NETIF_F_HW_VLAN_FILTER;
9a799d71 6935
e9990a9c 6936 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6937 netdev->features |= NETIF_F_TSO;
9a799d71 6938 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6939 netdev->features |= NETIF_F_GRO;
ad31c402 6940
45a5ead0
JB		 6941 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6942 netdev->features |= NETIF_F_SCTP_CSUM;
6943
ad31c402
JK		 6944 netdev->vlan_features |= NETIF_F_TSO;
6945 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6946 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6947 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6948 netdev->vlan_features |= NETIF_F_SG;
6949
1cdd1ec8
GR		 6950 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6951 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6952 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6953 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6954 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6955
7a6b6f51 6956#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6957 netdev->dcbnl_ops = &dcbnl_ops;
6958#endif
6959
eacd73f7 6960#ifdef IXGBE_FCOE
0d551589 6961 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6962 if (hw->mac.ops.get_device_caps) {
6963 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6964 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6965 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6966 }
6967 }
5e09d7f6
YZ		 6968 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6969 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6970 netdev->vlan_features |= NETIF_F_FSO;
6971 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6972 }
eacd73f7 6973#endif /* IXGBE_FCOE */
7b872a55 6974 if (pci_using_dac) {
9a799d71 6975 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6976 netdev->vlan_features |= NETIF_F_HIGHDMA;
6977 }
9a799d71 6978
0c19d6af 6979 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6980 netdev->features |= NETIF_F_LRO;
6981
9a799d71 6982 /* make sure the EEPROM is good */
c44ade9e 6983 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6984 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6985 err = -EIO;
6986 goto err_eeprom;
6987 }
6988
6989 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6990 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6991
c44ade9e 6992 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6993 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6994 err = -EIO;
6995 goto err_eeprom;
6996 }
6997
61fac744
PW		 6998 /* power down the optics */
6999 if (hw->phy.multispeed_fiber)
7000 hw->mac.ops.disable_tx_laser(hw);
7001
9a799d71 7002 init_timer(&adapter->watchdog_timer);
c061b18d 7003 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7004 adapter->watchdog_timer.data = (unsigned long)adapter;
7005
7006 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7007 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7008
021230d4
AV		 7009 err = ixgbe_init_interrupt_scheme(adapter);
7010 if (err)
7011 goto err_sw_init;
9a799d71 7012
e8e26350
PW		 7013 switch (pdev->device) {
7014 case IXGBE_DEV_ID_82599_KX4:
495dce12 7015 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7016 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7017 break;
7018 default:
7019 adapter->wol = 0;
7020 break;
7021 }
e8e26350
PW		 7022 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7023
04f165ef
PW		 7024 /* pick up the PCI bus settings for reporting later */
7025 hw->mac.ops.get_bus_info(hw);
7026
9a799d71 7027 /* print bus type/speed/width info */
849c4542 7028 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 7029 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7030 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7031 "Unknown"),
7032 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7033 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7034 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7035 "Unknown"),
7036 netdev->dev_addr);
c44ade9e 7037 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 7038 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 7039 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7040 "PBA No: %06x-%03x\n",
7041 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7042 (part_num >> 8), (part_num & 0xff));
e8e26350 7043 else
849c4542
ET		 7044 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7045 hw->mac.type, hw->phy.type,
7046 (part_num >> 8), (part_num & 0xff));
9a799d71 7047
e8e26350 7048 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7049 e_dev_warn("PCI-Express bandwidth available for this card is "
7050 "not sufficient for optimal performance.\n");
7051 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7052 "is required.\n");
0c254d86
AK		 7053 }
7054
34b0368c
PWJ		 7055 /* save off EEPROM version number */
7056 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7057
9a799d71 7058 /* reset the hardware with the new settings */
794caeb2 7059 err = hw->mac.ops.start_hw(hw);
c44ade9e 7060
794caeb2
PWJ		 7061 if (err == IXGBE_ERR_EEPROM_VERSION) {
7062 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7063 e_dev_warn("This device is a pre-production adapter/LOM. "
7064 "Please be aware there may be issues associated "
7065 "with your hardware. If you are experiencing "
7066 "problems please contact your Intel or hardware "
7067 "representative who provided you with this "
7068 "hardware.\n");
794caeb2 7069 }
9a799d71
AK		 7070 strcpy(netdev->name, "eth%d");
7071 err = register_netdev(netdev);
7072 if (err)
7073 goto err_register;
7074
54386467
JB		 7075 /* carrier off reporting is important to ethtool even BEFORE open */
7076 netif_carrier_off(netdev);
7077
c4cf55e5
PWJ		 7078 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7079 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7080 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7081
119fc60a 7082 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7083 INIT_WORK(&adapter->check_overtemp_task,
7084 ixgbe_check_overtemp_task);
5dd2d332 7085#ifdef CONFIG_IXGBE_DCA
652f093f 7086 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7087 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7088 ixgbe_setup_dca(adapter);
7089 }
7090#endif
1cdd1ec8 7091 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7092 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7093 for (i = 0; i < adapter->num_vfs; i++)
7094 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7095 }
7096
0365e6e4
PW		 7097 /* add san mac addr to netdev */
7098 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7099
849c4542 7100 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7101 cards_found++;
7102 return 0;
7103
7104err_register:
5eba3699 7105 ixgbe_release_hw_control(adapter);
7a921c93 7106 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7107err_sw_init:
7108err_eeprom:
1cdd1ec8
GR		 7109 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7110 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7111 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7112 del_timer_sync(&adapter->sfp_timer);
7113 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7114 cancel_work_sync(&adapter->multispeed_fiber_task);
7115 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7116 iounmap(hw->hw_addr);
7117err_ioremap:
7118 free_netdev(netdev);
7119err_alloc_etherdev:
e8e9f696
JP		 7120 pci_release_selected_regions(pdev,
7121 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7122err_pci_reg:
7123err_dma:
7124 pci_disable_device(pdev);
7125 return err;
7126}
7127
7128/**
7129 * ixgbe_remove - Device Removal Routine
7130 * @pdev: PCI device information struct
7131 *
7132 * ixgbe_remove is called by the PCI subsystem to alert the driver
7133 * that it should release a PCI device. The could be caused by a
7134 * Hot-Plug event, or because the driver is going to be removed from
7135 * memory.
7136 **/
7137static void __devexit ixgbe_remove(struct pci_dev *pdev)
7138{
c60fbb00
AD		 7139 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7140 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7141
7142 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7143 /* clear the module not found bit to make sure the worker won't
7144 * reschedule
7145 */
7146 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7147 del_timer_sync(&adapter->watchdog_timer);
7148
c4900be0
DS		 7149 del_timer_sync(&adapter->sfp_timer);
7150 cancel_work_sync(&adapter->watchdog_task);
7151 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7152 cancel_work_sync(&adapter->multispeed_fiber_task);
7153 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7154 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7155 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7156 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7157 flush_scheduled_work();
7158
5dd2d332 7159#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7160 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7161 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7162 dca_remove_requester(&pdev->dev);
7163 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7164 }
7165
7166#endif
332d4a7d
YZ		 7167#ifdef IXGBE_FCOE
7168 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7169 ixgbe_cleanup_fcoe(adapter);
7170
7171#endif /* IXGBE_FCOE */
0365e6e4
PW		 7172
7173 /* remove the added san mac */
7174 ixgbe_del_sanmac_netdev(netdev);
7175
c4900be0
DS		 7176 if (netdev->reg_state == NETREG_REGISTERED)
7177 unregister_netdev(netdev);
9a799d71 7178
1cdd1ec8
GR		 7179 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7180 ixgbe_disable_sriov(adapter);
7181
7a921c93 7182 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7183
021230d4 7184 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7185
7186 iounmap(adapter->hw.hw_addr);
9ce77666 7187 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7188 IORESOURCE_MEM));
9a799d71 7189
849c4542 7190 e_dev_info("complete\n");
021230d4 7191
9a799d71
AK		 7192 free_netdev(netdev);
7193
19d5afd4 7194 pci_disable_pcie_error_reporting(pdev);
6fabd715 7195
9a799d71
AK		 7196 pci_disable_device(pdev);
7197}
7198
7199/**
7200 * ixgbe_io_error_detected - called when PCI error is detected
7201 * @pdev: Pointer to PCI device
7202 * @state: The current pci connection state
7203 *
7204 * This function is called after a PCI bus error affecting
7205 * this device has been detected.
7206 */
7207static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7208 pci_channel_state_t state)
9a799d71 7209{
c60fbb00
AD		 7210 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7211 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7212
7213 netif_device_detach(netdev);
7214
3044b8d1
BL		 7215 if (state == pci_channel_io_perm_failure)
7216 return PCI_ERS_RESULT_DISCONNECT;
7217
9a799d71
AK		 7218 if (netif_running(netdev))
7219 ixgbe_down(adapter);
7220 pci_disable_device(pdev);
7221
b4617240 7222 /* Request a slot reset. */
9a799d71
AK		 7223 return PCI_ERS_RESULT_NEED_RESET;
7224}
7225
7226/**
7227 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7228 * @pdev: Pointer to PCI device
7229 *
7230 * Restart the card from scratch, as if from a cold-boot.
7231 */
7232static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7233{
c60fbb00 7234 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7235 pci_ers_result_t result;
7236 int err;
9a799d71 7237
9ce77666 7238 if (pci_enable_device_mem(pdev)) {
396e799c 7239 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7240 result = PCI_ERS_RESULT_DISCONNECT;
7241 } else {
7242 pci_set_master(pdev);
7243 pci_restore_state(pdev);
c0e1f68b 7244 pci_save_state(pdev);
9a799d71 7245
dd4d8ca6 7246 pci_wake_from_d3(pdev, false);
9a799d71 7247
6fabd715 7248 ixgbe_reset(adapter);
88512539 7249 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7250 result = PCI_ERS_RESULT_RECOVERED;
7251 }
7252
7253 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7254 if (err) {
849c4542
ET		 7255 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7256 "failed 0x%0x\n", err);
6fabd715
PWJ		 7257 /* non-fatal, continue */
7258 }
9a799d71 7259
6fabd715 7260 return result;
9a799d71
AK		 7261}
7262
7263/**
7264 * ixgbe_io_resume - called when traffic can start flowing again.
7265 * @pdev: Pointer to PCI device
7266 *
7267 * This callback is called when the error recovery driver tells us that
7268 * its OK to resume normal operation.
7269 */
7270static void ixgbe_io_resume(struct pci_dev *pdev)
7271{
c60fbb00
AD		 7272 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7273 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7274
7275 if (netif_running(netdev)) {
7276 if (ixgbe_up(adapter)) {
396e799c 7277 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7278 return;
7279 }
7280 }
7281
7282 netif_device_attach(netdev);
9a799d71
AK		 7283}
7284
7285static struct pci_error_handlers ixgbe_err_handler = {
7286 .error_detected = ixgbe_io_error_detected,
7287 .slot_reset = ixgbe_io_slot_reset,
7288 .resume = ixgbe_io_resume,
7289};
7290
7291static struct pci_driver ixgbe_driver = {
7292 .name = ixgbe_driver_name,
7293 .id_table = ixgbe_pci_tbl,
7294 .probe = ixgbe_probe,
7295 .remove = __devexit_p(ixgbe_remove),
7296#ifdef CONFIG_PM
7297 .suspend = ixgbe_suspend,
7298 .resume = ixgbe_resume,
7299#endif
7300 .shutdown = ixgbe_shutdown,
7301 .err_handler = &ixgbe_err_handler
7302};
7303
7304/**
7305 * ixgbe_init_module - Driver Registration Routine
7306 *
7307 * ixgbe_init_module is the first routine called when the driver is
7308 * loaded. All it does is register with the PCI subsystem.
7309 **/
7310static int __init ixgbe_init_module(void)
7311{
7312 int ret;
c7689578 7313 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7314 pr_info("%s\n", ixgbe_copyright);
9a799d71 7315
5dd2d332 7316#ifdef CONFIG_IXGBE_DCA
bd0362dd 7317 dca_register_notify(&dca_notifier);
bd0362dd 7318#endif
5dd2d332 7319
9a799d71
AK		 7320 ret = pci_register_driver(&ixgbe_driver);
7321 return ret;
7322}
b4617240 7323
9a799d71
AK		 7324module_init(ixgbe_init_module);
7325
7326/**
7327 * ixgbe_exit_module - Driver Exit Cleanup Routine
7328 *
7329 * ixgbe_exit_module is called just before the driver is removed
7330 * from memory.
7331 **/
7332static void __exit ixgbe_exit_module(void)
7333{
5dd2d332 7334#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7335 dca_unregister_notify(&dca_notifier);
7336#endif
9a799d71 7337 pci_unregister_driver(&ixgbe_driver);
1a51502b 7338 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7339}
bd0362dd 7340
5dd2d332 7341#ifdef CONFIG_IXGBE_DCA
bd0362dd 7342static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7343 void *p)
bd0362dd
JC		 7344{
7345 int ret_val;
7346
7347 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7348 __ixgbe_notify_dca);
bd0362dd
JC		 7349
7350 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7351}
b453368d 7352
5dd2d332 7353#endif /* CONFIG_IXGBE_DCA */
849c4542 7354
b453368d 7355/**
849c4542 7356 * ixgbe_get_hw_dev return device
b453368d
AD		 7357 * used by hardware layer to print debugging information
7358 **/
849c4542 7359struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7360{
7361 struct ixgbe_adapter *adapter = hw->back;
849c4542 7362 return adapter->netdev;
b453368d 7363}
bd0362dd 7364
9a799d71
AK		 7365module_exit(ixgbe_exit_module);
7366
7367/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree