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ixgbe: combine some stats into a union to allow for Tx/Rx stats overlap
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601}
602
b6ec895e
AD		 603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
604 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 605{
e5a43549
AD		 606 if (tx_buffer_info->dma) {
607 if (tx_buffer_info->mapped_as_page)
b6ec895e 608 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 609 tx_buffer_info->dma,
610 tx_buffer_info->length,
1b507730 611 DMA_TO_DEVICE);
e5a43549 612 else
b6ec895e 613 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 614 tx_buffer_info->dma,
615 tx_buffer_info->length,
1b507730 616 DMA_TO_DEVICE);
e5a43549
AD		 617 tx_buffer_info->dma = 0;
618 }
9a799d71
AK		 619 if (tx_buffer_info->skb) {
620 dev_kfree_skb_any(tx_buffer_info->skb);
621 tx_buffer_info->skb = NULL;
622 }
44df32c5 623 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 624 /* tx_buffer_info must be completely set up in the transmit path */
625}
626
26f23d82 627/**
7483d9dd 628 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 629 * @adapter: the ixgbe adapter
630 * @tx_ring: the corresponding tx_ring
631 *
632 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
633 * corresponding TC of this tx_ring when checking TFCS.
634 *
7483d9dd 635 * Returns : true if in xon state (currently not paused)
26f23d82 636 */
7483d9dd 637static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 638 struct ixgbe_ring *tx_ring)
26f23d82 639{
26f23d82
YZ		 640 u32 txoff = IXGBE_TFCS_TXOFF;
641
642#ifdef CONFIG_IXGBE_DCB
ca739481 643 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 644 int tc;
26f23d82
YZ		 645 int reg_idx = tx_ring->reg_idx;
646 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
647
6837e895
PW		 648 switch (adapter->hw.mac.type) {
649 case ixgbe_mac_82598EB:
26f23d82
YZ		 650 tc = reg_idx >> 2;
651 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 652 break;
653 case ixgbe_mac_82599EB:
26f23d82
YZ		 654 tc = 0;
655 txoff = IXGBE_TFCS_TXOFF;
656 if (dcb_i == 8) {
657 /* TC0, TC1 */
658 tc = reg_idx >> 5;
659 if (tc == 2) /* TC2, TC3 */
660 tc += (reg_idx - 64) >> 4;
661 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
662 tc += 1 + ((reg_idx - 96) >> 3);
663 } else if (dcb_i == 4) {
664 /* TC0, TC1 */
665 tc = reg_idx >> 6;
666 if (tc == 1) {
667 tc += (reg_idx - 64) >> 5;
668 if (tc == 2) /* TC2, TC3 */
669 tc += (reg_idx - 96) >> 4;
670 }
671 }
6837e895
PW		 672 break;
673 default:
674 tc = 0;
26f23d82
YZ		 675 }
676 txoff <<= tc;
677 }
678#endif
679 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
680}
681
9a799d71 682static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 683 struct ixgbe_ring *tx_ring,
684 unsigned int eop)
9a799d71 685{
e01c31a5 686 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 687
9a799d71 688 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 689 * check with the clearing of time_stamp and movement of eop */
9a799d71 690 adapter->detect_tx_hung = false;
44df32c5 691 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 692 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 693 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 694 /* detected Tx unit hang */
e01c31a5 695 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 696 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 697 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 698 " Tx Queue <%d>\n"
699 " TDH, TDT <%x>, <%x>\n"
700 " next_to_use <%x>\n"
701 " next_to_clean <%x>\n"
702 "tx_buffer_info[next_to_clean]\n"
703 " time_stamp <%lx>\n"
704 " jiffies <%lx>\n",
705 tx_ring->queue_index,
84ea2591
AD		 706 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
707 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
849c4542
ET		 708 tx_ring->next_to_use, eop,
709 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 710 return true;
711 }
712
713 return false;
714}
715
b4617240
PW		 716#define IXGBE_MAX_TXD_PWR 14
717#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 718
719/* Tx Descriptors needed, worst case */
720#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
721 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
722#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 723 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 724
e01c31a5
JB		 725static void ixgbe_tx_timeout(struct net_device *netdev);
726
9a799d71
AK		 727/**
728 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 729 * @q_vector: structure containing interrupt and ring information
e01c31a5 730 * @tx_ring: tx ring to clean
9a799d71 731 **/
fe49f04a 732static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 733 struct ixgbe_ring *tx_ring)
9a799d71 734{
fe49f04a 735 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 736 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 737 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
738 struct ixgbe_tx_buffer *tx_buffer_info;
739 unsigned int i, eop, count = 0;
e01c31a5 740 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 741
742 i = tx_ring->next_to_clean;
12207e49 743 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 744 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 745
746 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 747 (count < tx_ring->work_limit)) {
12207e49 748 bool cleaned = false;
2d0bb1c1 749 rmb(); /* read buffer_info after eop_desc */
12207e49 750 for ( ; !cleaned; count++) {
31f05a2d 751 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 752 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 753
754 tx_desc->wb.status = 0;
12207e49 755 cleaned = (i == eop);
9a799d71 756
8ad494b0
AD		 757 i++;
758 if (i == tx_ring->count)
759 i = 0;
e01c31a5 760
8ad494b0
AD		 761 if (cleaned && tx_buffer_info->skb) {
762 total_bytes += tx_buffer_info->bytecount;
763 total_packets += tx_buffer_info->gso_segs;
e092be60 764 }
e01c31a5 765
b6ec895e 766 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 767 tx_buffer_info);
e01c31a5 768 }
12207e49
PWJ		 769
770 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 771 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 772 }
773
9a799d71
AK		 774 tx_ring->next_to_clean = i;
775
e092be60 776#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5 777 if (unlikely(count && netif_carrier_ok(netdev) &&
e8e9f696 778 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 779 /* Make sure that anybody stopping the queue after this
780 * sees the new next_to_clean.
781 */
782 smp_mb();
30eba97a
AV		 783 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
784 !test_bit(__IXGBE_DOWN, &adapter->state)) {
785 netif_wake_subqueue(netdev, tx_ring->queue_index);
5b7da515 786 ++tx_ring->tx_stats.restart_queue;
30eba97a 787 }
e092be60 788 }
9a799d71 789
e01c31a5
JB		 790 if (adapter->detect_tx_hung) {
791 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
792 /* schedule immediate reset if we believe we hung */
396e799c
ET		 793 e_info(probe, "tx hang %d detected, resetting "
794 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 795 ixgbe_tx_timeout(adapter->netdev);
796 }
797 }
9a799d71 798
e01c31a5 799 /* re-arm the interrupt */
fe49f04a
AD		 800 if (count >= tx_ring->work_limit)
801 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 802
e01c31a5
JB		 803 tx_ring->total_bytes += total_bytes;
804 tx_ring->total_packets += total_packets;
de1036b1 805 u64_stats_update_begin(&tx_ring->syncp);
e01c31a5 806 tx_ring->stats.packets += total_packets;
12207e49 807 tx_ring->stats.bytes += total_bytes;
de1036b1 808 u64_stats_update_end(&tx_ring->syncp);
807540ba 809 return count < tx_ring->work_limit;
9a799d71
AK		 810}
811
5dd2d332 812#ifdef CONFIG_IXGBE_DCA
bd0362dd 813static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
e8e9f696 814 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 815{
816 u32 rxctrl;
817 int cpu = get_cpu();
4a0b9ca0 818 int q = rx_ring->reg_idx;
bd0362dd 819
3a581073 820 if (rx_ring->cpu != cpu) {
bd0362dd 821 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 822 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
823 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
824 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
825 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
826 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
827 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 828 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
e8e26350 829 }
bd0362dd
JC		 830 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
831 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 832 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
833 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e9f696 834 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 836 rx_ring->cpu = cpu;
bd0362dd
JC		 837 }
838 put_cpu();
839}
840
841static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
e8e9f696 842 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 843{
844 u32 txctrl;
845 int cpu = get_cpu();
4a0b9ca0 846 int q = tx_ring->reg_idx;
ee5f784a 847 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 848
3a581073 849 if (tx_ring->cpu != cpu) {
e8e26350 850 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 851 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 852 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
853 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 854 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
855 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 856 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 857 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 858 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
859 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 860 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
ee5f784a
DS		 861 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
862 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 863 }
3a581073 864 tx_ring->cpu = cpu;
bd0362dd
JC		 865 }
866 put_cpu();
867}
868
869static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
870{
871 int i;
872
873 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
874 return;
875
e35ec126
AD		 876 /* always use CB2 mode, difference is masked in the CB driver */
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
878
bd0362dd 879 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 880 adapter->tx_ring[i]->cpu = -1;
881 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 882 }
883 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 884 adapter->rx_ring[i]->cpu = -1;
885 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 886 }
887}
888
889static int __ixgbe_notify_dca(struct device *dev, void *data)
890{
891 struct net_device *netdev = dev_get_drvdata(dev);
892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
893 unsigned long event = *(unsigned long *)data;
894
895 switch (event) {
896 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 897 /* if we're already enabled, don't do it again */
898 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
899 break;
652f093f 900 if (dca_add_requester(dev) == 0) {
96b0e0f6 901 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 902 ixgbe_setup_dca(adapter);
903 break;
904 }
905 /* Fall Through since DCA is disabled. */
906 case DCA_PROVIDER_REMOVE:
907 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
908 dca_remove_requester(dev);
909 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
911 }
912 break;
913 }
914
652f093f 915 return 0;
bd0362dd
JC		 916}
917
5dd2d332 918#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 919/**
920 * ixgbe_receive_skb - Send a completed packet up the stack
921 * @adapter: board private structure
922 * @skb: packet to send up
177db6ff
MC		 923 * @status: hardware indication of status of receive
924 * @rx_ring: rx descriptor ring (for a specific queue) to setup
925 * @rx_desc: rx descriptor
9a799d71 926 **/
78b6f4ce 927static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 928 struct sk_buff *skb, u8 status,
929 struct ixgbe_ring *ring,
930 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 931{
78b6f4ce
HX		 932 struct ixgbe_adapter *adapter = q_vector->adapter;
933 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 934 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
935 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 936
f62bbb5e
JG		 937 if (is_vlan && (tag & VLAN_VID_MASK))
938 __vlan_hwaccel_put_tag(skb, tag);
939
940 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
941 napi_gro_receive(napi, skb);
942 else
943 netif_rx(skb);
9a799d71
AK		 944}
945
e59bd25d
AV		 946/**
947 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
948 * @adapter: address of board private structure
949 * @status_err: hardware indication of status of receive
950 * @skb: skb currently being received and modified
951 **/
9a799d71 952static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 953 union ixgbe_adv_rx_desc *rx_desc,
954 struct sk_buff *skb)
9a799d71 955{
8bae1b2b
DS		 956 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
957
bc8acf2c 958 skb_checksum_none_assert(skb);
9a799d71 959
712744be
JB		 960 /* Rx csum disabled */
961 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 962 return;
e59bd25d
AV		 963
964 /* if IP and error */
965 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
966 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 967 adapter->hw_csum_rx_error++;
968 return;
969 }
e59bd25d
AV		 970
971 if (!(status_err & IXGBE_RXD_STAT_L4CS))
972 return;
973
974 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 975 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
976
977 /*
978 * 82599 errata, UDP frames with a 0 checksum can be marked as
979 * checksum errors.
980 */
981 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
982 (adapter->hw.mac.type == ixgbe_mac_82599EB))
983 return;
984
e59bd25d
AV		 985 adapter->hw_csum_rx_error++;
986 return;
987 }
988
9a799d71 989 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 990 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 991}
992
84ea2591 993static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 994{
995 /*
996 * Force memory writes to complete before letting h/w
997 * know there are new descriptors to fetch. (Only
998 * applicable for weak-ordered memory model archs,
999 * such as IA-64).
1000 */
1001 wmb();
84ea2591 1002 writel(val, rx_ring->tail);
e8e26350
PW		 1003}
1004
9a799d71
AK		 1005/**
1006 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1007 * @adapter: address of board private structure
1008 **/
84418e3b 1009void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
e8e9f696 1010 struct ixgbe_ring *rx_ring,
d5f398ed 1011 u16 cleaned_count)
9a799d71 1012{
9a799d71 1013 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1014 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1015 struct sk_buff *skb;
1016 u16 i = rx_ring->next_to_use;
9a799d71
AK		 1017
1018 while (cleaned_count--) {
31f05a2d 1019 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1020 bi = &rx_ring->rx_buffer_info[i];
1021 skb = bi->skb;
9a799d71 1022
d5f398ed
AD		 1023 if (!skb) {
1024 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1025 rx_ring->rx_buf_len);
9a799d71 1026 if (!skb) {
5b7da515 1027 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1028 goto no_buffers;
1029 }
d716a7d8
AD		 1030 /* initialize queue mapping */
1031 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1032 bi->skb = skb;
d716a7d8 1033 }
9a799d71 1034
d716a7d8 1035 if (!bi->dma) {
b6ec895e 1036 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1037 skb->data,
e8e9f696 1038 rx_ring->rx_buf_len,
1b507730 1039 DMA_FROM_DEVICE);
b6ec895e 1040 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1041 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1042 bi->dma = 0;
1043 goto no_buffers;
1044 }
9a799d71 1045 }
d5f398ed 1046
6e455b89 1047 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
d5f398ed
AD		 1048 if (!bi->page) {
1049 bi->page = netdev_alloc_page(adapter->netdev);
1050 if (!bi->page) {
5b7da515 1051 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1052 goto no_buffers;
1053 }
1054 }
1055
1056 if (!bi->page_dma) {
1057 /* use a half page if we're re-using */
1058 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1059 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1060 bi->page,
1061 bi->page_offset,
1062 PAGE_SIZE / 2,
1063 DMA_FROM_DEVICE);
b6ec895e 1064 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1065 bi->page_dma)) {
5b7da515 1066 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1067 bi->page_dma = 0;
1068 goto no_buffers;
1069 }
1070 }
1071
1072 /* Refresh the desc even if buffer_addrs didn't change
1073 * because each write-back erases this info. */
3a581073
JB		 1074 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1075 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1076 } else {
3a581073 1077 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1078 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1079 }
1080
1081 i++;
1082 if (i == rx_ring->count)
1083 i = 0;
9a799d71 1084 }
7c6e0a43 1085
9a799d71
AK		 1086no_buffers:
1087 if (rx_ring->next_to_use != i) {
1088 rx_ring->next_to_use = i;
84ea2591 1089 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1090 }
1091}
1092
7c6e0a43
JB		 1093static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1094{
1095 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1096}
1097
1098static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1099{
1100 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1101}
1102
f8212f97
AD		 1103static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1104{
1105 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1106 IXGBE_RXDADV_RSCCNT_MASK) >>
1107 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1108}
1109
1110/**
1111 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1112 * @skb: pointer to the last skb in the rsc queue
94b982b2 1113 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1114 *
1115 * This function changes a queue full of hw rsc buffers into a completed
1116 * packet. It uses the ->prev pointers to find the first packet and then
1117 * turns it into the frag list owner.
1118 **/
94b982b2 1119static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1120 u64 *count)
f8212f97
AD		 1121{
1122 unsigned int frag_list_size = 0;
1123
1124 while (skb->prev) {
1125 struct sk_buff *prev = skb->prev;
1126 frag_list_size += skb->len;
1127 skb->prev = NULL;
1128 skb = prev;
94b982b2 1129 *count += 1;
f8212f97
AD		 1130 }
1131
1132 skb_shinfo(skb)->frag_list = skb->next;
1133 skb->next = NULL;
1134 skb->len += frag_list_size;
1135 skb->data_len += frag_list_size;
1136 skb->truesize += frag_list_size;
1137 return skb;
1138}
1139
43634e82
MC		 1140struct ixgbe_rsc_cb {
1141 dma_addr_t dma;
e8171aaa 1142 bool delay_unmap;
43634e82
MC		 1143};
1144
1145#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1146
78b6f4ce 1147static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1148 struct ixgbe_ring *rx_ring,
1149 int *work_done, int work_to_do)
9a799d71 1150{
78b6f4ce 1151 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1152 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1153 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1154 struct sk_buff *skb;
f8212f97 1155 unsigned int i, rsc_count = 0;
7c6e0a43 1156 u32 len, staterr;
177db6ff
MC		 1157 u16 hdr_info;
1158 bool cleaned = false;
9a799d71 1159 int cleaned_count = 0;
d2f4fbe2 1160 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1161#ifdef IXGBE_FCOE
1162 int ddp_bytes = 0;
1163#endif /* IXGBE_FCOE */
9a799d71
AK		 1164
1165 i = rx_ring->next_to_clean;
31f05a2d 1166 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1167 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1168 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1169
1170 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1171 u32 upper_len = 0;
9a799d71
AK		 1172 if (*work_done >= work_to_do)
1173 break;
1174 (*work_done)++;
1175
3c945e5b 1176 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1177 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1178 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1179 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1180 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1181 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1182 if ((len > IXGBE_RX_HDR_SIZE) ||
1183 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1184 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1185 } else {
9a799d71 1186 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1187 }
9a799d71
AK		 1188
1189 cleaned = true;
1190 skb = rx_buffer_info->skb;
7ca3bc58 1191 prefetch(skb->data);
9a799d71
AK		 1192 rx_buffer_info->skb = NULL;
1193
21fa4e66 1194 if (rx_buffer_info->dma) {
43634e82
MC		 1195 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1196 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1197 (!(skb->prev))) {
43634e82
MC		 1198 /*
1199 * When HWRSC is enabled, delay unmapping
1200 * of the first packet. It carries the
1201 * header information, HW may still
1202 * access the header after the writeback.
1203 * Only unmap it when EOP is reached
1204 */
e8171aaa 1205 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1206 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1207 } else {
b6ec895e 1208 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1209 rx_buffer_info->dma,
1210 rx_ring->rx_buf_len,
1211 DMA_FROM_DEVICE);
e8171aaa 1212 }
4f57ca6e 1213 rx_buffer_info->dma = 0;
9a799d71
AK		 1214 skb_put(skb, len);
1215 }
1216
1217 if (upper_len) {
b6ec895e
AD		 1218 dma_unmap_page(rx_ring->dev,
1219 rx_buffer_info->page_dma,
1220 PAGE_SIZE / 2,
1221 DMA_FROM_DEVICE);
9a799d71
AK		 1222 rx_buffer_info->page_dma = 0;
1223 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1224 rx_buffer_info->page,
1225 rx_buffer_info->page_offset,
1226 upper_len);
762f4c57
JB		 1227
1228 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1229 (page_count(rx_buffer_info->page) != 1))
1230 rx_buffer_info->page = NULL;
1231 else
1232 get_page(rx_buffer_info->page);
9a799d71
AK		 1233
1234 skb->len += upper_len;
1235 skb->data_len += upper_len;
1236 skb->truesize += upper_len;
1237 }
1238
1239 i++;
1240 if (i == rx_ring->count)
1241 i = 0;
9a799d71 1242
31f05a2d 1243 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1244 prefetch(next_rxd);
9a799d71 1245 cleaned_count++;
f8212f97 1246
0c19d6af 1247 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1248 rsc_count = ixgbe_get_rsc_count(rx_desc);
1249
1250 if (rsc_count) {
1251 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1252 IXGBE_RXDADV_NEXTP_SHIFT;
1253 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1254 } else {
1255 next_buffer = &rx_ring->rx_buffer_info[i];
1256 }
1257
9a799d71 1258 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1259 if (skb->prev)
e8e9f696 1260 skb = ixgbe_transform_rsc_queue(skb,
5b7da515 1261 &(rx_ring->rx_stats.rsc_count));
94b982b2 1262 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1263 if (IXGBE_RSC_CB(skb)->delay_unmap) {
b6ec895e 1264 dma_unmap_single(rx_ring->dev,
1b507730 1265 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1266 rx_ring->rx_buf_len,
1b507730 1267 DMA_FROM_DEVICE);
fd3686a8 1268 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1269 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1270 }
94b982b2 1271 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
5b7da515
AD		 1272 rx_ring->rx_stats.rsc_count +=
1273 skb_shinfo(skb)->nr_frags;
94b982b2 1274 else
5b7da515
AD		 1275 rx_ring->rx_stats.rsc_count++;
1276 rx_ring->rx_stats.rsc_flush++;
94b982b2 1277 }
de1036b1 1278 u64_stats_update_begin(&rx_ring->syncp);
9a799d71
AK		 1279 rx_ring->stats.packets++;
1280 rx_ring->stats.bytes += skb->len;
de1036b1 1281 u64_stats_update_end(&rx_ring->syncp);
9a799d71 1282 } else {
6e455b89 1283 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1284 rx_buffer_info->skb = next_buffer->skb;
1285 rx_buffer_info->dma = next_buffer->dma;
1286 next_buffer->skb = skb;
1287 next_buffer->dma = 0;
1288 } else {
1289 skb->next = next_buffer->skb;
1290 skb->next->prev = skb;
1291 }
5b7da515 1292 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1293 goto next_desc;
1294 }
1295
1296 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1297 dev_kfree_skb_irq(skb);
1298 goto next_desc;
1299 }
1300
8bae1b2b 1301 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1302
1303 /* probably a little skewed due to removing CRC */
1304 total_rx_bytes += skb->len;
1305 total_rx_packets++;
1306
74ce8dd2 1307 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1308#ifdef IXGBE_FCOE
1309 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1310 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1311 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1312 if (!ddp_bytes)
332d4a7d 1313 goto next_desc;
3d8fd385 1314 }
332d4a7d 1315#endif /* IXGBE_FCOE */
fdaff1ce 1316 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1317
1318next_desc:
1319 rx_desc->wb.upper.status_error = 0;
1320
1321 /* return some buffers to hardware, one at a time is too slow */
1322 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1323 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1324 cleaned_count = 0;
1325 }
1326
1327 /* use prefetched values */
1328 rx_desc = next_rxd;
f8212f97 1329 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1330
1331 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1332 }
1333
9a799d71
AK		 1334 rx_ring->next_to_clean = i;
1335 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1336
1337 if (cleaned_count)
1338 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1339
3d8fd385
YZ		 1340#ifdef IXGBE_FCOE
1341 /* include DDPed FCoE data */
1342 if (ddp_bytes > 0) {
1343 unsigned int mss;
1344
1345 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1346 sizeof(struct fc_frame_header) -
1347 sizeof(struct fcoe_crc_eof);
1348 if (mss > 512)
1349 mss &= ~511;
1350 total_rx_bytes += ddp_bytes;
1351 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1352 }
1353#endif /* IXGBE_FCOE */
1354
f494e8fa
AV		 1355 rx_ring->total_packets += total_rx_packets;
1356 rx_ring->total_bytes += total_rx_bytes;
f494e8fa 1357
9a799d71
AK		 1358 return cleaned;
1359}
1360
021230d4 1361static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1362/**
1363 * ixgbe_configure_msix - Configure MSI-X hardware
1364 * @adapter: board private structure
1365 *
1366 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1367 * interrupts.
1368 **/
1369static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1370{
021230d4
AV		 1371 struct ixgbe_q_vector *q_vector;
1372 int i, j, q_vectors, v_idx, r_idx;
1373 u32 mask;
9a799d71 1374
021230d4 1375 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1376
4df10466
JB		 1377 /*
1378 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1379 * corresponding register.
1380 */
1381 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1382 q_vector = adapter->q_vector[v_idx];
984b3f57 1383 /* XXX for_each_set_bit(...) */
021230d4 1384 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1385 adapter->num_rx_queues);
021230d4
AV		 1386
1387 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1388 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1389 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1390 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1391 adapter->num_rx_queues,
1392 r_idx + 1);
021230d4
AV		 1393 }
1394 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1395 adapter->num_tx_queues);
021230d4
AV		 1396
1397 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1398 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1399 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1400 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1401 adapter->num_tx_queues,
1402 r_idx + 1);
021230d4
AV		 1403 }
1404
021230d4 1405 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1406 /* tx only */
1407 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1408 else if (q_vector->rxr_count)
f7554a2b
NS		 1409 /* rx or mixed */
1410 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1411
fe49f04a 1412 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1413 /* If Flow Director is enabled, set interrupt affinity */
1414 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1415 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1416 /*
1417 * Allocate the affinity_hint cpumask, assign the mask
1418 * for this vector, and set our affinity_hint for
1419 * this irq.
1420 */
1421 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1422 GFP_KERNEL))
1423 return;
1424 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1425 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1426 q_vector->affinity_mask);
1427 }
9a799d71
AK		 1428 }
1429
e8e26350
PW		 1430 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1431 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1432 v_idx);
e8e26350
PW		 1433 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1434 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1436
41fb9248 1437 /* set up to autoclear timer, and the vectors */
021230d4 1438 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1439 if (adapter->num_vfs)
1440 mask &= ~(IXGBE_EIMS_OTHER |
1441 IXGBE_EIMS_MAILBOX |
1442 IXGBE_EIMS_LSC);
1443 else
1444 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1446}
1447
f494e8fa
AV		 1448enum latency_range {
1449 lowest_latency = 0,
1450 low_latency = 1,
1451 bulk_latency = 2,
1452 latency_invalid = 255
1453};
1454
1455/**
1456 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1457 * @adapter: pointer to adapter
1458 * @eitr: eitr setting (ints per sec) to give last timeslice
1459 * @itr_setting: current throttle rate in ints/second
1460 * @packets: the number of packets during this measurement interval
1461 * @bytes: the number of bytes during this measurement interval
1462 *
1463 * Stores a new ITR value based on packets and byte
1464 * counts during the last interrupt. The advantage of per interrupt
1465 * computation is faster updates and more accurate ITR for the current
1466 * traffic pattern. Constants in this function were computed
1467 * based on theoretical maximum wire speed and thresholds were set based
1468 * on testing data as well as attempting to minimize response time
1469 * while increasing bulk throughput.
1470 * this functionality is controlled by the InterruptThrottleRate module
1471 * parameter (see ixgbe_param.c)
1472 **/
1473static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1474 u32 eitr, u8 itr_setting,
1475 int packets, int bytes)
f494e8fa
AV		 1476{
1477 unsigned int retval = itr_setting;
1478 u32 timepassed_us;
1479 u64 bytes_perint;
1480
1481 if (packets == 0)
1482 goto update_itr_done;
1483
1484
1485 /* simple throttlerate management
1486 * 0-20MB/s lowest (100000 ints/s)
1487 * 20-100MB/s low (20000 ints/s)
1488 * 100-1249MB/s bulk (8000 ints/s)
1489 */
1490 /* what was last interrupt timeslice? */
1491 timepassed_us = 1000000/eitr;
1492 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1493
1494 switch (itr_setting) {
1495 case lowest_latency:
1496 if (bytes_perint > adapter->eitr_low)
1497 retval = low_latency;
1498 break;
1499 case low_latency:
1500 if (bytes_perint > adapter->eitr_high)
1501 retval = bulk_latency;
1502 else if (bytes_perint <= adapter->eitr_low)
1503 retval = lowest_latency;
1504 break;
1505 case bulk_latency:
1506 if (bytes_perint <= adapter->eitr_high)
1507 retval = low_latency;
1508 break;
1509 }
1510
1511update_itr_done:
1512 return retval;
1513}
1514
509ee935
JB		 1515/**
1516 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1517 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1518 *
1519 * This function is made to be called by ethtool and by the driver
1520 * when it needs to update EITR registers at runtime. Hardware
1521 * specific quirks/differences are taken care of here.
1522 */
fe49f04a 1523void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1524{
fe49f04a 1525 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1526 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1527 int v_idx = q_vector->v_idx;
1528 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1529
509ee935
JB		 1530 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1531 /* must write high and low 16 bits to reset counter */
1532 itr_reg |= (itr_reg << 16);
1533 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1534 /*
1535 * 82599 can support a value of zero, so allow it for
1536 * max interrupt rate, but there is an errata where it can
1537 * not be zero with RSC
1538 */
1539 if (itr_reg == 8 &&
1540 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1541 itr_reg = 0;
1542
509ee935
JB		 1543 /*
1544 * set the WDIS bit to not clear the timer bits and cause an
1545 * immediate assertion of the interrupt
1546 */
1547 itr_reg |= IXGBE_EITR_CNT_WDIS;
1548 }
1549 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1550}
1551
f494e8fa
AV		 1552static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1553{
1554 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1555 u32 new_itr;
1556 u8 current_itr, ret_itr;
fe49f04a 1557 int i, r_idx;
f494e8fa
AV		 1558 struct ixgbe_ring *rx_ring, *tx_ring;
1559
1560 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1561 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1562 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1563 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1564 q_vector->tx_itr,
1565 tx_ring->total_packets,
1566 tx_ring->total_bytes);
f494e8fa
AV		 1567 /* if the result for this queue would decrease interrupt
1568 * rate for this vector then use that result */
30efa5a3 1569 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1570 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1571 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1572 r_idx + 1);
f494e8fa
AV		 1573 }
1574
1575 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1576 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1577 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1578 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1579 q_vector->rx_itr,
1580 rx_ring->total_packets,
1581 rx_ring->total_bytes);
f494e8fa
AV		 1582 /* if the result for this queue would decrease interrupt
1583 * rate for this vector then use that result */
30efa5a3 1584 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1585 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1586 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1587 r_idx + 1);
f494e8fa
AV		 1588 }
1589
30efa5a3 1590 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1591
1592 switch (current_itr) {
1593 /* counts and packets in update_itr are dependent on these numbers */
1594 case lowest_latency:
1595 new_itr = 100000;
1596 break;
1597 case low_latency:
1598 new_itr = 20000; /* aka hwitr = ~200 */
1599 break;
1600 case bulk_latency:
1601 default:
1602 new_itr = 8000;
1603 break;
1604 }
1605
1606 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1607 /* do an exponential smoothing */
1608 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1609
1610 /* save the algorithm value here, not the smoothed one */
1611 q_vector->eitr = new_itr;
fe49f04a
AD		 1612
1613 ixgbe_write_eitr(q_vector);
f494e8fa 1614 }
f494e8fa
AV		 1615}
1616
119fc60a
MC		 1617/**
1618 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1619 * @work: pointer to work_struct containing our data
1620 **/
1621static void ixgbe_check_overtemp_task(struct work_struct *work)
1622{
1623 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1624 struct ixgbe_adapter,
1625 check_overtemp_task);
119fc60a
MC		 1626 struct ixgbe_hw *hw = &adapter->hw;
1627 u32 eicr = adapter->interrupt_event;
1628
7ca647bd
JP		 1629 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1630 return;
1631
1632 switch (hw->device_id) {
1633 case IXGBE_DEV_ID_82599_T3_LOM: {
1634 u32 autoneg;
1635 bool link_up = false;
1636
1637 if (hw->mac.ops.check_link)
1638 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1639
1640 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1641 (eicr & IXGBE_EICR_LSC))
1642 /* Check if this is due to overtemp */
1643 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1644 break;
1645 return;
1646 }
1647 default:
1648 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1649 return;
7ca647bd 1650 break;
119fc60a 1651 }
7ca647bd
JP		 1652 e_crit(drv,
1653 "Network adapter has been stopped because it has over heated. "
1654 "Restart the computer. If the problem persists, "
1655 "power off the system and replace the adapter\n");
1656 /* write to clear the interrupt */
1657 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1658}
1659
0befdb3e
JB		 1660static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1661{
1662 struct ixgbe_hw *hw = &adapter->hw;
1663
1664 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1665 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1666 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1667 /* write to clear the interrupt */
1668 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1669 }
1670}
cf8280ee 1671
e8e26350
PW		 1672static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1673{
1674 struct ixgbe_hw *hw = &adapter->hw;
1675
1676 if (eicr & IXGBE_EICR_GPI_SDP1) {
1677 /* Clear the interrupt */
1678 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1679 schedule_work(&adapter->multispeed_fiber_task);
1680 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1681 /* Clear the interrupt */
1682 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1683 schedule_work(&adapter->sfp_config_module_task);
1684 } else {
1685 /* Interrupt isn't for us... */
1686 return;
1687 }
1688}
1689
cf8280ee
JB		 1690static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1691{
1692 struct ixgbe_hw *hw = &adapter->hw;
1693
1694 adapter->lsc_int++;
1695 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1696 adapter->link_check_timeout = jiffies;
1697 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1698 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1699 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1700 schedule_work(&adapter->watchdog_task);
1701 }
1702}
1703
9a799d71
AK		 1704static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1705{
1706 struct net_device *netdev = data;
1707 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1708 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1709 u32 eicr;
1710
1711 /*
1712 * Workaround for Silicon errata. Use clear-by-write instead
1713 * of clear-by-read. Reading with EICS will return the
1714 * interrupt causes without clearing, which later be done
1715 * with the write to EICR.
1716 */
1717 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1718 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1719
cf8280ee
JB		 1720 if (eicr & IXGBE_EICR_LSC)
1721 ixgbe_check_lsc(adapter);
d4f80882 1722
1cdd1ec8
GR		 1723 if (eicr & IXGBE_EICR_MAILBOX)
1724 ixgbe_msg_task(adapter);
1725
e8e26350
PW		 1726 if (hw->mac.type == ixgbe_mac_82598EB)
1727 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1728
c4cf55e5 1729 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1730 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1731 adapter->interrupt_event = eicr;
1732 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1733 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1734 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1735
1736 /* Handle Flow Director Full threshold interrupt */
1737 if (eicr & IXGBE_EICR_FLOW_DIR) {
1738 int i;
1739 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1740 /* Disable transmits before FDIR Re-initialization */
1741 netif_tx_stop_all_queues(netdev);
1742 for (i = 0; i < adapter->num_tx_queues; i++) {
1743 struct ixgbe_ring *tx_ring =
e8e9f696 1744 adapter->tx_ring[i];
c4cf55e5 1745 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 1746 &tx_ring->reinit_state))
c4cf55e5
PWJ		 1747 schedule_work(&adapter->fdir_reinit_task);
1748 }
1749 }
1750 }
d4f80882
AV		 1751 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1752 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1753
1754 return IRQ_HANDLED;
1755}
1756
fe49f04a
AD		 1757static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1758 u64 qmask)
1759{
1760 u32 mask;
1761
1762 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1763 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1765 } else {
1766 mask = (qmask & 0xFFFFFFFF);
1767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1768 mask = (qmask >> 32);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1770 }
1771 /* skip the flush */
1772}
1773
1774static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1775 u64 qmask)
fe49f04a
AD		 1776{
1777 u32 mask;
1778
1779 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1780 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1782 } else {
1783 mask = (qmask & 0xFFFFFFFF);
1784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1785 mask = (qmask >> 32);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1787 }
1788 /* skip the flush */
1789}
1790
9a799d71
AK		 1791static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1792{
021230d4
AV		 1793 struct ixgbe_q_vector *q_vector = data;
1794 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1795 struct ixgbe_ring *tx_ring;
021230d4
AV		 1796 int i, r_idx;
1797
1798 if (!q_vector->txr_count)
1799 return IRQ_HANDLED;
1800
1801 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1802 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1803 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1804 tx_ring->total_bytes = 0;
1805 tx_ring->total_packets = 0;
021230d4 1806 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1807 r_idx + 1);
021230d4 1808 }
9a799d71 1809
9b471446 1810 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1811 napi_schedule(&q_vector->napi);
1812
9a799d71
AK		 1813 return IRQ_HANDLED;
1814}
1815
021230d4
AV		 1816/**
1817 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1818 * @irq: unused
1819 * @data: pointer to our q_vector struct for this interrupt vector
1820 **/
9a799d71
AK		 1821static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1822{
021230d4
AV		 1823 struct ixgbe_q_vector *q_vector = data;
1824 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1825 struct ixgbe_ring *rx_ring;
021230d4 1826 int r_idx;
30efa5a3 1827 int i;
021230d4
AV		 1828
1829 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1830 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1831 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1832 rx_ring->total_bytes = 0;
1833 rx_ring->total_packets = 0;
1834 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1835 r_idx + 1);
30efa5a3
JB		 1836 }
1837
021230d4
AV		 1838 if (!q_vector->rxr_count)
1839 return IRQ_HANDLED;
1840
021230d4 1841 /* disable interrupts on this vector only */
9b471446 1842 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1843 napi_schedule(&q_vector->napi);
021230d4
AV		 1844
1845 return IRQ_HANDLED;
1846}
1847
1848static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1849{
91281fd3
AD		 1850 struct ixgbe_q_vector *q_vector = data;
1851 struct ixgbe_adapter *adapter = q_vector->adapter;
1852 struct ixgbe_ring *ring;
1853 int r_idx;
1854 int i;
1855
1856 if (!q_vector->txr_count && !q_vector->rxr_count)
1857 return IRQ_HANDLED;
1858
1859 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1860 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1861 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1862 ring->total_bytes = 0;
1863 ring->total_packets = 0;
1864 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1865 r_idx + 1);
91281fd3
AD		 1866 }
1867
1868 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1869 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1870 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1871 ring->total_bytes = 0;
1872 ring->total_packets = 0;
1873 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1874 r_idx + 1);
91281fd3
AD		 1875 }
1876
9b471446 1877 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1878 napi_schedule(&q_vector->napi);
9a799d71 1879
9a799d71
AK		 1880 return IRQ_HANDLED;
1881}
1882
021230d4
AV		 1883/**
1884 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1885 * @napi: napi struct with our devices info in it
1886 * @budget: amount of work driver is allowed to do this pass, in packets
1887 *
f0848276
JB		 1888 * This function is optimized for cleaning one queue only on a single
1889 * q_vector!!!
021230d4 1890 **/
9a799d71
AK		 1891static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1892{
021230d4 1893 struct ixgbe_q_vector *q_vector =
e8e9f696 1894 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1895 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1896 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1897 int work_done = 0;
021230d4 1898 long r_idx;
9a799d71 1899
021230d4 1900 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1901 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1902#ifdef CONFIG_IXGBE_DCA
bd0362dd 1903 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1904 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1905#endif
9a799d71 1906
78b6f4ce 1907 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1908
021230d4
AV		 1909 /* If all Rx work done, exit the polling mode */
1910 if (work_done < budget) {
288379f0 1911 napi_complete(napi);
f7554a2b 1912 if (adapter->rx_itr_setting & 1)
f494e8fa 1913 ixgbe_set_itr_msix(q_vector);
9a799d71 1914 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1915 ixgbe_irq_enable_queues(adapter,
e8e9f696 1916 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1917 }
1918
1919 return work_done;
1920}
1921
f0848276 1922/**
91281fd3 1923 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1924 * @napi: napi struct with our devices info in it
1925 * @budget: amount of work driver is allowed to do this pass, in packets
1926 *
1927 * This function will clean more than one rx queue associated with a
1928 * q_vector.
1929 **/
91281fd3 1930static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1931{
1932 struct ixgbe_q_vector *q_vector =
e8e9f696 1933 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1934 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1935 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1936 int work_done = 0, i;
1937 long r_idx;
91281fd3
AD		 1938 bool tx_clean_complete = true;
1939
1940 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1941 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1942 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1943#ifdef CONFIG_IXGBE_DCA
1944 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1945 ixgbe_update_tx_dca(adapter, ring);
1946#endif
1947 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1948 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1949 r_idx + 1);
91281fd3 1950 }
f0848276
JB		 1951
1952 /* attempt to distribute budget to each queue fairly, but don't allow
1953 * the budget to go below 1 because we'll exit polling */
1954 budget /= (q_vector->rxr_count ?: 1);
1955 budget = max(budget, 1);
1956 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1957 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1958 ring = adapter->rx_ring[r_idx];
5dd2d332 1959#ifdef CONFIG_IXGBE_DCA
f0848276 1960 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1961 ixgbe_update_rx_dca(adapter, ring);
f0848276 1962#endif
91281fd3 1963 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 1964 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1965 r_idx + 1);
f0848276
JB		 1966 }
1967
1968 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1969 ring = adapter->rx_ring[r_idx];
f0848276 1970 /* If all Rx work done, exit the polling mode */
7f821875 1971 if (work_done < budget) {
288379f0 1972 napi_complete(napi);
f7554a2b 1973 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1974 ixgbe_set_itr_msix(q_vector);
1975 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1976 ixgbe_irq_enable_queues(adapter,
e8e9f696 1977 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1978 return 0;
1979 }
1980
1981 return work_done;
1982}
91281fd3
AD		 1983
1984/**
1985 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1986 * @napi: napi struct with our devices info in it
1987 * @budget: amount of work driver is allowed to do this pass, in packets
1988 *
1989 * This function is optimized for cleaning one queue only on a single
1990 * q_vector!!!
1991 **/
1992static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1993{
1994 struct ixgbe_q_vector *q_vector =
e8e9f696 1995 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 1996 struct ixgbe_adapter *adapter = q_vector->adapter;
1997 struct ixgbe_ring *tx_ring = NULL;
1998 int work_done = 0;
1999 long r_idx;
2000
2001 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2002 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2003#ifdef CONFIG_IXGBE_DCA
2004 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2005 ixgbe_update_tx_dca(adapter, tx_ring);
2006#endif
2007
2008 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2009 work_done = budget;
2010
f7554a2b 2011 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2012 if (work_done < budget) {
2013 napi_complete(napi);
f7554a2b 2014 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2015 ixgbe_set_itr_msix(q_vector);
2016 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2017 ixgbe_irq_enable_queues(adapter,
2018 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2019 }
2020
2021 return work_done;
2022}
2023
021230d4 2024static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2025 int r_idx)
021230d4 2026{
7a921c93
AD		 2027 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2028
2029 set_bit(r_idx, q_vector->rxr_idx);
2030 q_vector->rxr_count++;
021230d4
AV		 2031}
2032
2033static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2034 int t_idx)
021230d4 2035{
7a921c93
AD		 2036 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2037
2038 set_bit(t_idx, q_vector->txr_idx);
2039 q_vector->txr_count++;
021230d4
AV		 2040}
2041
9a799d71 2042/**
021230d4
AV		 2043 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2044 * @adapter: board private structure to initialize
2045 * @vectors: allotted vector count for descriptor rings
9a799d71 2046 *
021230d4
AV		 2047 * This function maps descriptor rings to the queue-specific vectors
2048 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2049 * one vector per ring/queue, but on a constrained vector budget, we
2050 * group the rings as "efficiently" as possible. You would add new
2051 * mapping configurations in here.
9a799d71 2052 **/
021230d4 2053static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2054 int vectors)
021230d4
AV		 2055{
2056 int v_start = 0;
2057 int rxr_idx = 0, txr_idx = 0;
2058 int rxr_remaining = adapter->num_rx_queues;
2059 int txr_remaining = adapter->num_tx_queues;
2060 int i, j;
2061 int rqpv, tqpv;
2062 int err = 0;
2063
2064 /* No mapping required if MSI-X is disabled. */
2065 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2066 goto out;
9a799d71 2067
021230d4
AV		 2068 /*
2069 * The ideal configuration...
2070 * We have enough vectors to map one per queue.
2071 */
2072 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2073 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2074 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2075
021230d4
AV		 2076 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2077 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2078
9a799d71 2079 goto out;
021230d4 2080 }
9a799d71 2081
021230d4
AV		 2082 /*
2083 * If we don't have enough vectors for a 1-to-1
2084 * mapping, we'll have to group them so there are
2085 * multiple queues per vector.
2086 */
2087 /* Re-adjusting *qpv takes care of the remainder. */
2088 for (i = v_start; i < vectors; i++) {
2089 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2090 for (j = 0; j < rqpv; j++) {
2091 map_vector_to_rxq(adapter, i, rxr_idx);
2092 rxr_idx++;
2093 rxr_remaining--;
2094 }
2095 }
2096 for (i = v_start; i < vectors; i++) {
2097 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2098 for (j = 0; j < tqpv; j++) {
2099 map_vector_to_txq(adapter, i, txr_idx);
2100 txr_idx++;
2101 txr_remaining--;
9a799d71 2102 }
9a799d71
AK		 2103 }
2104
021230d4
AV		 2105out:
2106 return err;
2107}
2108
2109/**
2110 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2111 * @adapter: board private structure
2112 *
2113 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2114 * interrupts from the kernel.
2115 **/
2116static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2117{
2118 struct net_device *netdev = adapter->netdev;
2119 irqreturn_t (*handler)(int, void *);
2120 int i, vector, q_vectors, err;
e8e9f696 2121 int ri = 0, ti = 0;
021230d4
AV		 2122
2123 /* Decrement for Other and TCP Timer vectors */
2124 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2125
2126 /* Map the Tx/Rx rings to the vectors we were allotted. */
2127 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2128 if (err)
2129 goto out;
2130
2131#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2132 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2133 &ixgbe_msix_clean_many)
021230d4 2134 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2135 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2136
e8e9f696 2137 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2138 sprintf(adapter->name[vector], "%s-%s-%d",
2139 netdev->name, "rx", ri++);
e8e9f696 2140 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2141 sprintf(adapter->name[vector], "%s-%s-%d",
2142 netdev->name, "tx", ti++);
e8e9f696 2143 } else
cb13fc20
RO		 2144 sprintf(adapter->name[vector], "%s-%s-%d",
2145 netdev->name, "TxRx", vector);
2146
021230d4 2147 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2148 handler, 0, adapter->name[vector],
2149 adapter->q_vector[vector]);
9a799d71 2150 if (err) {
396e799c 2151 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2152 "Error: %d\n", err);
021230d4 2153 goto free_queue_irqs;
9a799d71 2154 }
9a799d71
AK		 2155 }
2156
021230d4
AV		 2157 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2158 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2159 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2160 if (err) {
396e799c 2161 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2162 goto free_queue_irqs;
9a799d71
AK		 2163 }
2164
9a799d71
AK		 2165 return 0;
2166
021230d4
AV		 2167free_queue_irqs:
2168 for (i = vector - 1; i >= 0; i--)
2169 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2170 adapter->q_vector[i]);
021230d4
AV		 2171 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2172 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2173 kfree(adapter->msix_entries);
2174 adapter->msix_entries = NULL;
021230d4 2175out:
9a799d71
AK		 2176 return err;
2177}
2178
f494e8fa
AV		 2179static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2180{
7a921c93 2181 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2182 u8 current_itr;
2183 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2184 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2185 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2186
30efa5a3 2187 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2188 q_vector->tx_itr,
2189 tx_ring->total_packets,
2190 tx_ring->total_bytes);
30efa5a3 2191 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2192 q_vector->rx_itr,
2193 rx_ring->total_packets,
2194 rx_ring->total_bytes);
f494e8fa 2195
30efa5a3 2196 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2197
2198 switch (current_itr) {
2199 /* counts and packets in update_itr are dependent on these numbers */
2200 case lowest_latency:
2201 new_itr = 100000;
2202 break;
2203 case low_latency:
2204 new_itr = 20000; /* aka hwitr = ~200 */
2205 break;
2206 case bulk_latency:
2207 new_itr = 8000;
2208 break;
2209 default:
2210 break;
2211 }
2212
2213 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2214 /* do an exponential smoothing */
2215 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2216
2217 /* save the algorithm value here, not the smoothed one */
2218 q_vector->eitr = new_itr;
fe49f04a
AD		 2219
2220 ixgbe_write_eitr(q_vector);
f494e8fa 2221 }
f494e8fa
AV		 2222}
2223
79aefa45
AD		 2224/**
2225 * ixgbe_irq_enable - Enable default interrupt generation settings
2226 * @adapter: board private structure
2227 **/
6af3b9eb
ET		 2228static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2229 bool flush)
79aefa45
AD		 2230{
2231 u32 mask;
835462fc
NS		 2232
2233 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2234 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2235 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2236 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2237 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2238 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2239 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2240 mask |= IXGBE_EIMS_GPI_SDP1;
2241 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2242 if (adapter->num_vfs)
2243 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2244 }
c4cf55e5
PWJ		 2245 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2246 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2247 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2248
79aefa45 2249 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2250 if (queues)
2251 ixgbe_irq_enable_queues(adapter, ~0);
2252 if (flush)
2253 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2254
2255 if (adapter->num_vfs > 32) {
2256 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2258 }
79aefa45 2259}
021230d4 2260
9a799d71 2261/**
021230d4 2262 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2263 * @irq: interrupt number
2264 * @data: pointer to a network interface device structure
9a799d71
AK		 2265 **/
2266static irqreturn_t ixgbe_intr(int irq, void *data)
2267{
2268 struct net_device *netdev = data;
2269 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2270 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2271 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2272 u32 eicr;
2273
54037505 2274 /*
6af3b9eb 2275 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2276 * before the read of EICR.
2277 */
2278 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2279
021230d4
AV		 2280 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2281 * therefore no explict interrupt disable is necessary */
2282 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2283 if (!eicr) {
6af3b9eb
ET		 2284 /*
2285 * shared interrupt alert!
f47cf66e 2286 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2287 * have disabled interrupts due to EIAM
2288 * finish the workaround of silicon errata on 82598. Unmask
2289 * the interrupt that we masked before the EICR read.
2290 */
2291 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2292 ixgbe_irq_enable(adapter, true, true);
9a799d71 2293 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2294 }
9a799d71 2295
cf8280ee
JB		 2296 if (eicr & IXGBE_EICR_LSC)
2297 ixgbe_check_lsc(adapter);
021230d4 2298
e8e26350
PW		 2299 if (hw->mac.type == ixgbe_mac_82599EB)
2300 ixgbe_check_sfp_event(adapter, eicr);
2301
0befdb3e 2302 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2303 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2304 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2305 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2306
7a921c93 2307 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2308 adapter->tx_ring[0]->total_packets = 0;
2309 adapter->tx_ring[0]->total_bytes = 0;
2310 adapter->rx_ring[0]->total_packets = 0;
2311 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2312 /* would disable interrupts here but EIAM disabled it */
7a921c93 2313 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2314 }
2315
6af3b9eb
ET		 2316 /*
2317 * re-enable link(maybe) and non-queue interrupts, no flush.
2318 * ixgbe_poll will re-enable the queue interrupts
2319 */
2320
2321 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2322 ixgbe_irq_enable(adapter, false, false);
2323
9a799d71
AK		 2324 return IRQ_HANDLED;
2325}
2326
021230d4
AV		 2327static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2328{
2329 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2330
2331 for (i = 0; i < q_vectors; i++) {
7a921c93 2332 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2333 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2334 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2335 q_vector->rxr_count = 0;
2336 q_vector->txr_count = 0;
2337 }
2338}
2339
9a799d71
AK		 2340/**
2341 * ixgbe_request_irq - initialize interrupts
2342 * @adapter: board private structure
2343 *
2344 * Attempts to configure interrupts using the best available
2345 * capabilities of the hardware and kernel.
2346 **/
021230d4 2347static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2348{
2349 struct net_device *netdev = adapter->netdev;
021230d4 2350 int err;
9a799d71 2351
021230d4
AV		 2352 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2353 err = ixgbe_request_msix_irqs(adapter);
2354 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2355 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2356 netdev->name, netdev);
021230d4 2357 } else {
a0607fd3 2358 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2359 netdev->name, netdev);
9a799d71
AK		 2360 }
2361
9a799d71 2362 if (err)
396e799c 2363 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2364
9a799d71
AK		 2365 return err;
2366}
2367
2368static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2369{
2370 struct net_device *netdev = adapter->netdev;
2371
2372 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2373 int i, q_vectors;
9a799d71 2374
021230d4
AV		 2375 q_vectors = adapter->num_msix_vectors;
2376
2377 i = q_vectors - 1;
9a799d71 2378 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2379
021230d4
AV		 2380 i--;
2381 for (; i >= 0; i--) {
2382 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2383 adapter->q_vector[i]);
021230d4
AV		 2384 }
2385
2386 ixgbe_reset_q_vectors(adapter);
2387 } else {
2388 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2389 }
2390}
2391
22d5a71b
JB		 2392/**
2393 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2394 * @adapter: board private structure
2395 **/
2396static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2397{
835462fc
NS		 2398 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2400 } else {
2401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2404 if (adapter->num_vfs > 32)
2405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2406 }
2407 IXGBE_WRITE_FLUSH(&adapter->hw);
2408 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2409 int i;
2410 for (i = 0; i < adapter->num_msix_vectors; i++)
2411 synchronize_irq(adapter->msix_entries[i].vector);
2412 } else {
2413 synchronize_irq(adapter->pdev->irq);
2414 }
2415}
2416
9a799d71
AK		 2417/**
2418 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2419 *
2420 **/
2421static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2422{
9a799d71
AK		 2423 struct ixgbe_hw *hw = &adapter->hw;
2424
021230d4 2425 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2426 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2427
e8e26350
PW		 2428 ixgbe_set_ivar(adapter, 0, 0, 0);
2429 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2430
2431 map_vector_to_rxq(adapter, 0, 0);
2432 map_vector_to_txq(adapter, 0, 0);
2433
396e799c 2434 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2435}
2436
43e69bf0
AD		 2437/**
2438 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2439 * @adapter: board private structure
2440 * @ring: structure containing ring specific data
2441 *
2442 * Configure the Tx descriptor ring after a reset.
2443 **/
84418e3b
AD		 2444void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2445 struct ixgbe_ring *ring)
43e69bf0
AD		 2446{
2447 struct ixgbe_hw *hw = &adapter->hw;
2448 u64 tdba = ring->dma;
2f1860b8
AD		 2449 int wait_loop = 10;
2450 u32 txdctl;
43e69bf0
AD		 2451 u16 reg_idx = ring->reg_idx;
2452
2f1860b8
AD		 2453 /* disable queue to avoid issues while updating state */
2454 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2455 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2456 txdctl & ~IXGBE_TXDCTL_ENABLE);
2457 IXGBE_WRITE_FLUSH(hw);
2458
43e69bf0 2459 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2460 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2461 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2462 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2463 ring->count * sizeof(union ixgbe_adv_tx_desc));
2464 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2465 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2466 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2467
2f1860b8
AD		 2468 /* configure fetching thresholds */
2469 if (adapter->rx_itr_setting == 0) {
2470 /* cannot set wthresh when itr==0 */
2471 txdctl &= ~0x007F0000;
2472 } else {
2473 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2474 txdctl |= (8 << 16);
2475 }
2476 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2477 /* PThresh workaround for Tx hang with DFP enabled. */
2478 txdctl |= 32;
2479 }
2480
2481 /* reinitialize flowdirector state */
2482 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2483
2484 /* enable queue */
2485 txdctl |= IXGBE_TXDCTL_ENABLE;
2486 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2487
2488 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2489 if (hw->mac.type == ixgbe_mac_82598EB &&
2490 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2491 return;
2492
2493 /* poll to verify queue is enabled */
2494 do {
2495 msleep(1);
2496 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2497 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2498 if (!wait_loop)
2499 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2500}
2501
120ff942
AD		 2502static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2503{
2504 struct ixgbe_hw *hw = &adapter->hw;
2505 u32 rttdcs;
2506 u32 mask;
2507
2508 if (hw->mac.type == ixgbe_mac_82598EB)
2509 return;
2510
2511 /* disable the arbiter while setting MTQC */
2512 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2513 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2514 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2515
2516 /* set transmit pool layout */
2517 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2518 switch (adapter->flags & mask) {
2519
2520 case (IXGBE_FLAG_SRIOV_ENABLED):
2521 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2522 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2523 break;
2524
2525 case (IXGBE_FLAG_DCB_ENABLED):
2526 /* We enable 8 traffic classes, DCB only */
2527 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2528 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2529 break;
2530
2531 default:
2532 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2533 break;
2534 }
2535
2536 /* re-enable the arbiter */
2537 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2538 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2539}
2540
9a799d71 2541/**
3a581073 2542 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2543 * @adapter: board private structure
2544 *
2545 * Configure the Tx unit of the MAC after a reset.
2546 **/
2547static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2548{
2f1860b8
AD		 2549 struct ixgbe_hw *hw = &adapter->hw;
2550 u32 dmatxctl;
43e69bf0 2551 u32 i;
9a799d71 2552
2f1860b8
AD		 2553 ixgbe_setup_mtqc(adapter);
2554
2555 if (hw->mac.type != ixgbe_mac_82598EB) {
2556 /* DMATXCTL.EN must be before Tx queues are enabled */
2557 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2558 dmatxctl |= IXGBE_DMATXCTL_TE;
2559 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2560 }
2561
9a799d71 2562 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2563 for (i = 0; i < adapter->num_tx_queues; i++)
2564 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2565}
2566
e8e26350 2567#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2568
a6616b42 2569static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2570 struct ixgbe_ring *rx_ring)
cc41ac7c 2571{
cc41ac7c 2572 u32 srrctl;
a6616b42 2573 int index;
0cefafad 2574 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2575
a6616b42
YZ		 2576 index = rx_ring->reg_idx;
2577 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2578 unsigned long mask;
0cefafad 2579 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2580 index = index & mask;
cc41ac7c 2581 }
cc41ac7c
JB		 2582 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2583
2584 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2585 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2586 if (adapter->num_vfs)
2587 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2588
afafd5b0
AD		 2589 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2590 IXGBE_SRRCTL_BSIZEHDR_MASK;
2591
6e455b89 2592 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2593#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2594 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2595#else
2596 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2597#endif
cc41ac7c 2598 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2599 } else {
afafd5b0
AD		 2600 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2601 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2602 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2603 }
e8e26350 2604
cc41ac7c
JB		 2605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2606}
9a799d71 2607
05abb126 2608static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2609{
05abb126
AD		 2610 struct ixgbe_hw *hw = &adapter->hw;
2611 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2612 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2613 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2614 u32 mrqc = 0, reta = 0;
2615 u32 rxcsum;
2616 int i, j;
0cefafad
JB		 2617 int mask;
2618
05abb126
AD		 2619 /* Fill out hash function seeds */
2620 for (i = 0; i < 10; i++)
2621 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2622
2623 /* Fill out redirection table */
2624 for (i = 0, j = 0; i < 128; i++, j++) {
2625 if (j == adapter->ring_feature[RING_F_RSS].indices)
2626 j = 0;
2627 /* reta = 4-byte sliding window of
2628 * 0x00..(indices-1)(indices-1)00..etc. */
2629 reta = (reta << 8) | (j * 0x11);
2630 if ((i & 3) == 3)
2631 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2632 }
0cefafad 2633
05abb126
AD		 2634 /* Disable indicating checksum in descriptor, enables RSS hash */
2635 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2636 rxcsum |= IXGBE_RXCSUM_PCSD;
2637 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2638
2639 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2640 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2641 else
2642 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2643#ifdef CONFIG_IXGBE_DCB
05abb126 2644 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2645#endif
05abb126
AD		 2646 | IXGBE_FLAG_SRIOV_ENABLED
2647 );
0cefafad
JB		 2648
2649 switch (mask) {
2650 case (IXGBE_FLAG_RSS_ENABLED):
2651 mrqc = IXGBE_MRQC_RSSEN;
2652 break;
1cdd1ec8
GR		 2653 case (IXGBE_FLAG_SRIOV_ENABLED):
2654 mrqc = IXGBE_MRQC_VMDQEN;
2655 break;
0cefafad
JB		 2656#ifdef CONFIG_IXGBE_DCB
2657 case (IXGBE_FLAG_DCB_ENABLED):
2658 mrqc = IXGBE_MRQC_RT8TCEN;
2659 break;
2660#endif /* CONFIG_IXGBE_DCB */
2661 default:
2662 break;
2663 }
2664
05abb126
AD		 2665 /* Perform hash on these packet types */
2666 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2667 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2668 | IXGBE_MRQC_RSS_FIELD_IPV6
2669 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2670
2671 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2672}
2673
bb5a9ad2
NS		 2674/**
2675 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2676 * @adapter: address of board private structure
2677 * @index: index of ring to set
bb5a9ad2 2678 **/
7367096a
AD		 2679static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2680 struct ixgbe_ring *ring)
bb5a9ad2 2681{
bb5a9ad2 2682 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2683 u32 rscctrl;
edd2ea55 2684 int rx_buf_len;
7367096a
AD		 2685 u16 reg_idx = ring->reg_idx;
2686
2687 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2688 return;
bb5a9ad2 2689
7367096a
AD		 2690 rx_buf_len = ring->rx_buf_len;
2691 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2692 rscctrl |= IXGBE_RSCCTL_RSCEN;
2693 /*
2694 * we must limit the number of descriptors so that the
2695 * total size of max desc * buf_len is not greater
2696 * than 65535
2697 */
7367096a 2698 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2699#if (MAX_SKB_FRAGS > 16)
2700 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2701#elif (MAX_SKB_FRAGS > 8)
2702 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2703#elif (MAX_SKB_FRAGS > 4)
2704 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2705#else
2706 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2707#endif
2708 } else {
2709 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2710 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2711 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2712 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2713 else
2714 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2715 }
7367096a 2716 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2717}
2718
9e10e045
AD		 2719/**
2720 * ixgbe_set_uta - Set unicast filter table address
2721 * @adapter: board private structure
2722 *
2723 * The unicast table address is a register array of 32-bit registers.
2724 * The table is meant to be used in a way similar to how the MTA is used
2725 * however due to certain limitations in the hardware it is necessary to
2726 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2727 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2728 **/
2729static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2730{
2731 struct ixgbe_hw *hw = &adapter->hw;
2732 int i;
2733
2734 /* The UTA table only exists on 82599 hardware and newer */
2735 if (hw->mac.type < ixgbe_mac_82599EB)
2736 return;
2737
2738 /* we only need to do this if VMDq is enabled */
2739 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2740 return;
2741
2742 for (i = 0; i < 128; i++)
2743 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2744}
2745
2746#define IXGBE_MAX_RX_DESC_POLL 10
2747static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2748 struct ixgbe_ring *ring)
2749{
2750 struct ixgbe_hw *hw = &adapter->hw;
2751 int reg_idx = ring->reg_idx;
2752 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2753 u32 rxdctl;
2754
2755 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2756 if (hw->mac.type == ixgbe_mac_82598EB &&
2757 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2758 return;
2759
2760 do {
2761 msleep(1);
2762 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2763 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2764
2765 if (!wait_loop) {
2766 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2767 "the polling period\n", reg_idx);
2768 }
2769}
2770
84418e3b
AD		 2771void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2772 struct ixgbe_ring *ring)
acd37177
AD		 2773{
2774 struct ixgbe_hw *hw = &adapter->hw;
2775 u64 rdba = ring->dma;
9e10e045 2776 u32 rxdctl;
acd37177
AD		 2777 u16 reg_idx = ring->reg_idx;
2778
9e10e045
AD		 2779 /* disable queue to avoid issues while updating state */
2780 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2781 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2782 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2783 IXGBE_WRITE_FLUSH(hw);
2784
acd37177
AD		 2785 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2786 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2787 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2788 ring->count * sizeof(union ixgbe_adv_rx_desc));
2789 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2790 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2791 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2792
2793 ixgbe_configure_srrctl(adapter, ring);
2794 ixgbe_configure_rscctl(adapter, ring);
2795
2796 if (hw->mac.type == ixgbe_mac_82598EB) {
2797 /*
2798 * enable cache line friendly hardware writes:
2799 * PTHRESH=32 descriptors (half the internal cache),
2800 * this also removes ugly rx_no_buffer_count increment
2801 * HTHRESH=4 descriptors (to minimize latency on fetch)
2802 * WTHRESH=8 burst writeback up to two cache lines
2803 */
2804 rxdctl &= ~0x3FFFFF;
2805 rxdctl |= 0x080420;
2806 }
2807
2808 /* enable receive descriptor ring */
2809 rxdctl |= IXGBE_RXDCTL_ENABLE;
2810 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2811
2812 ixgbe_rx_desc_queue_enable(adapter, ring);
2813 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2814}
2815
48654521
AD		 2816static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2817{
2818 struct ixgbe_hw *hw = &adapter->hw;
2819 int p;
2820
2821 /* PSRTYPE must be initialized in non 82598 adapters */
2822 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2823 IXGBE_PSRTYPE_UDPHDR |
2824 IXGBE_PSRTYPE_IPV4HDR |
48654521 2825 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2826 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2827
2828 if (hw->mac.type == ixgbe_mac_82598EB)
2829 return;
2830
2831 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2832 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2833
2834 for (p = 0; p < adapter->num_rx_pools; p++)
2835 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2836 psrtype);
2837}
2838
f5b4a52e
AD		 2839static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2840{
2841 struct ixgbe_hw *hw = &adapter->hw;
2842 u32 gcr_ext;
2843 u32 vt_reg_bits;
2844 u32 reg_offset, vf_shift;
2845 u32 vmdctl;
2846
2847 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2848 return;
2849
2850 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2851 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2852 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2853 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2854
2855 vf_shift = adapter->num_vfs % 32;
2856 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2857
2858 /* Enable only the PF's pool for Tx/Rx */
2859 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2860 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2861 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2862 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2863 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2864
2865 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2866 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2867
2868 /*
2869 * Set up VF register offsets for selected VT Mode,
2870 * i.e. 32 or 64 VFs for SR-IOV
2871 */
2872 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2873 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2874 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2875 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2876
2877 /* enable Tx loopback for VF/PF communication */
2878 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2879}
2880
477de6ed 2881static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2882{
9a799d71
AK		 2883 struct ixgbe_hw *hw = &adapter->hw;
2884 struct net_device *netdev = adapter->netdev;
2885 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2886 int rx_buf_len;
477de6ed
AD		 2887 struct ixgbe_ring *rx_ring;
2888 int i;
2889 u32 mhadd, hlreg0;
48654521 2890
9a799d71 2891 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2892 /* Do not use packet split if we're in SR-IOV Mode */
2893 if (!adapter->num_vfs)
2894 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2895
2896 /* Set the RX buffer length according to the mode */
2897 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2898 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2899 } else {
0c19d6af 2900 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2901 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2902 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2903 else
477de6ed 2904 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2905 }
2906
63f39bd1 2907#ifdef IXGBE_FCOE
477de6ed
AD		 2908 /* adjust max frame to be able to do baby jumbo for FCoE */
2909 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2910 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2911 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2912
477de6ed
AD		 2913#endif /* IXGBE_FCOE */
2914 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2915 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2916 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2917 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2918
2919 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2920 }
2921
2922 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2923 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2924 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2925 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2926
0cefafad
JB		 2927 /*
2928 * Setup the HW Rx Head and Tail Descriptor Pointers and
2929 * the Base and Length of the Rx Descriptor Ring
2930 */
9a799d71 2931 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2932 rx_ring = adapter->rx_ring[i];
a6616b42 2933 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2934
6e455b89
YZ		 2935 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2936 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2937 else
2938 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2939
63f39bd1 2940#ifdef IXGBE_FCOE
e8e9f696 2941 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2942 struct ixgbe_ring_feature *f;
2943 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2944 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2945 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2946 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2947 rx_ring->rx_buf_len =
e8e9f696 2948 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2949 }
63f39bd1 2950 }
63f39bd1 2951#endif /* IXGBE_FCOE */
477de6ed
AD		 2952 }
2953
2954}
2955
7367096a
AD		 2956static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2957{
2958 struct ixgbe_hw *hw = &adapter->hw;
2959 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2960
2961 switch (hw->mac.type) {
2962 case ixgbe_mac_82598EB:
2963 /*
2964 * For VMDq support of different descriptor types or
2965 * buffer sizes through the use of multiple SRRCTL
2966 * registers, RDRXCTL.MVMEN must be set to 1
2967 *
2968 * also, the manual doesn't mention it clearly but DCA hints
2969 * will only use queue 0's tags unless this bit is set. Side
2970 * effects of setting this bit are only that SRRCTL must be
2971 * fully programmed [0..15]
2972 */
2973 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2974 break;
2975 case ixgbe_mac_82599EB:
2976 /* Disable RSC for ACK packets */
2977 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2978 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2979 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2980 /* hardware requires some bits to be set by default */
2981 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2982 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2983 break;
2984 default:
2985 /* We should do nothing since we don't know this hardware */
2986 return;
2987 }
2988
2989 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2990}
2991
477de6ed
AD		 2992/**
2993 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2994 * @adapter: board private structure
2995 *
2996 * Configure the Rx unit of the MAC after a reset.
2997 **/
2998static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2999{
3000 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3001 int i;
3002 u32 rxctrl;
477de6ed
AD		 3003
3004 /* disable receives while setting up the descriptors */
3005 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3006 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3007
3008 ixgbe_setup_psrtype(adapter);
7367096a 3009 ixgbe_setup_rdrxctl(adapter);
477de6ed 3010
9e10e045 3011 /* Program registers for the distribution of queues */
f5b4a52e 3012 ixgbe_setup_mrqc(adapter);
f5b4a52e 3013
9e10e045
AD		 3014 ixgbe_set_uta(adapter);
3015
477de6ed
AD		 3016 /* set_rx_buffer_len must be called before ring initialization */
3017 ixgbe_set_rx_buffer_len(adapter);
3018
3019 /*
3020 * Setup the HW Rx Head and Tail Descriptor Pointers and
3021 * the Base and Length of the Rx Descriptor Ring
3022 */
9e10e045
AD		 3023 for (i = 0; i < adapter->num_rx_queues; i++)
3024 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3025
9e10e045
AD		 3026 /* disable drop enable for 82598 parts */
3027 if (hw->mac.type == ixgbe_mac_82598EB)
3028 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3029
3030 /* enable all receives */
3031 rxctrl |= IXGBE_RXCTRL_RXEN;
3032 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3033}
3034
068c89b0
DS		 3035static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3036{
3037 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3038 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3039 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3040
3041 /* add VID to filter table */
1ada1b1b 3042 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3043 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3044}
3045
3046static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3047{
3048 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3049 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3050 int pool_ndx = adapter->num_vfs;
068c89b0 3051
068c89b0 3052 /* remove VID from filter table */
1ada1b1b 3053 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3054 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3055}
3056
5f6c0181
JB		 3057/**
3058 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3059 * @adapter: driver data
3060 */
3061static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3062{
3063 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3064 u32 vlnctrl;
3065
3066 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3067 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3068 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3069}
3070
3071/**
3072 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3073 * @adapter: driver data
3074 */
3075static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3076{
3077 struct ixgbe_hw *hw = &adapter->hw;
3078 u32 vlnctrl;
3079
3080 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3081 vlnctrl |= IXGBE_VLNCTRL_VFE;
3082 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3083 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3084}
3085
3086/**
3087 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3088 * @adapter: driver data
3089 */
3090static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3091{
3092 struct ixgbe_hw *hw = &adapter->hw;
3093 u32 vlnctrl;
5f6c0181
JB		 3094 int i, j;
3095
3096 switch (hw->mac.type) {
3097 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3098 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3099 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3100 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3101 break;
3102 case ixgbe_mac_82599EB:
5f6c0181
JB		 3103 for (i = 0; i < adapter->num_rx_queues; i++) {
3104 j = adapter->rx_ring[i]->reg_idx;
3105 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3106 vlnctrl &= ~IXGBE_RXDCTL_VME;
3107 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3108 }
3109 break;
3110 default:
3111 break;
3112 }
3113}
3114
3115/**
f62bbb5e 3116 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3117 * @adapter: driver data
3118 */
f62bbb5e 3119static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3120{
3121 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3122 u32 vlnctrl;
5f6c0181
JB		 3123 int i, j;
3124
3125 switch (hw->mac.type) {
3126 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3127 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3128 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3129 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3130 break;
3131 case ixgbe_mac_82599EB:
5f6c0181
JB		 3132 for (i = 0; i < adapter->num_rx_queues; i++) {
3133 j = adapter->rx_ring[i]->reg_idx;
3134 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3135 vlnctrl |= IXGBE_RXDCTL_VME;
3136 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3137 }
3138 break;
3139 default:
3140 break;
3141 }
3142}
3143
9a799d71
AK		 3144static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3145{
f62bbb5e 3146 u16 vid;
9a799d71 3147
f62bbb5e
JG		 3148 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3149
3150 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3151 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3152}
3153
2850062a
AD		 3154/**
3155 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3156 * @netdev: network interface device structure
3157 *
3158 * Writes unicast address list to the RAR table.
3159 * Returns: -ENOMEM on failure/insufficient address space
3160 * 0 on no addresses written
3161 * X on writing X addresses to the RAR table
3162 **/
3163static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3164{
3165 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3166 struct ixgbe_hw *hw = &adapter->hw;
3167 unsigned int vfn = adapter->num_vfs;
3168 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3169 int count = 0;
3170
3171 /* return ENOMEM indicating insufficient memory for addresses */
3172 if (netdev_uc_count(netdev) > rar_entries)
3173 return -ENOMEM;
3174
3175 if (!netdev_uc_empty(netdev) && rar_entries) {
3176 struct netdev_hw_addr *ha;
3177 /* return error if we do not support writing to RAR table */
3178 if (!hw->mac.ops.set_rar)
3179 return -ENOMEM;
3180
3181 netdev_for_each_uc_addr(ha, netdev) {
3182 if (!rar_entries)
3183 break;
3184 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3185 vfn, IXGBE_RAH_AV);
3186 count++;
3187 }
3188 }
3189 /* write the addresses in reverse order to avoid write combining */
3190 for (; rar_entries > 0 ; rar_entries--)
3191 hw->mac.ops.clear_rar(hw, rar_entries);
3192
3193 return count;
3194}
3195
9a799d71 3196/**
2c5645cf 3197 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3198 * @netdev: network interface device structure
3199 *
2c5645cf
CL		 3200 * The set_rx_method entry point is called whenever the unicast/multicast
3201 * address list or the network interface flags are updated. This routine is
3202 * responsible for configuring the hardware for proper unicast, multicast and
3203 * promiscuous mode.
9a799d71 3204 **/
7f870475 3205void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3206{
3207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3208 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3209 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3210 int count;
9a799d71
AK		 3211
3212 /* Check for Promiscuous and All Multicast modes */
3213
3214 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3215
f5dc442b
AD		 3216 /* set all bits that we expect to always be set */
3217 fctrl |= IXGBE_FCTRL_BAM;
3218 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3219 fctrl |= IXGBE_FCTRL_PMCF;
3220
2850062a
AD		 3221 /* clear the bits we are changing the status of */
3222 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3223
9a799d71 3224 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3225 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3226 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3227 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3228 /* don't hardware filter vlans in promisc mode */
3229 ixgbe_vlan_filter_disable(adapter);
9a799d71 3230 } else {
746b9f02
PM		 3231 if (netdev->flags & IFF_ALLMULTI) {
3232 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3233 vmolr |= IXGBE_VMOLR_MPE;
3234 } else {
3235 /*
3236 * Write addresses to the MTA, if the attempt fails
3237 * then we should just turn on promiscous mode so
3238 * that we can at least receive multicast traffic
3239 */
3240 hw->mac.ops.update_mc_addr_list(hw, netdev);
3241 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3242 }
5f6c0181 3243 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3244 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3245 /*
3246 * Write addresses to available RAR registers, if there is not
3247 * sufficient space to store all the addresses then enable
3248 * unicast promiscous mode
3249 */
3250 count = ixgbe_write_uc_addr_list(netdev);
3251 if (count < 0) {
3252 fctrl |= IXGBE_FCTRL_UPE;
3253 vmolr |= IXGBE_VMOLR_ROPE;
3254 }
9a799d71
AK		 3255 }
3256
2850062a 3257 if (adapter->num_vfs) {
1cdd1ec8 3258 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3259 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3260 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3261 IXGBE_VMOLR_ROPE);
3262 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3263 }
3264
3265 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3266
3267 if (netdev->features & NETIF_F_HW_VLAN_RX)
3268 ixgbe_vlan_strip_enable(adapter);
3269 else
3270 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3271}
3272
021230d4
AV		 3273static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3274{
3275 int q_idx;
3276 struct ixgbe_q_vector *q_vector;
3277 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3278
3279 /* legacy and MSI only use one vector */
3280 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3281 q_vectors = 1;
3282
3283 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3284 struct napi_struct *napi;
7a921c93 3285 q_vector = adapter->q_vector[q_idx];
f0848276 3286 napi = &q_vector->napi;
91281fd3
AD		 3287 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3288 if (!q_vector->rxr_count || !q_vector->txr_count) {
3289 if (q_vector->txr_count == 1)
3290 napi->poll = &ixgbe_clean_txonly;
3291 else if (q_vector->rxr_count == 1)
3292 napi->poll = &ixgbe_clean_rxonly;
3293 }
3294 }
f0848276
JB		 3295
3296 napi_enable(napi);
021230d4
AV		 3297 }
3298}
3299
3300static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3301{
3302 int q_idx;
3303 struct ixgbe_q_vector *q_vector;
3304 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3305
3306 /* legacy and MSI only use one vector */
3307 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3308 q_vectors = 1;
3309
3310 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3311 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3312 napi_disable(&q_vector->napi);
3313 }
3314}
3315
7a6b6f51 3316#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3317/*
3318 * ixgbe_configure_dcb - Configure DCB hardware
3319 * @adapter: ixgbe adapter struct
3320 *
3321 * This is called by the driver on open to configure the DCB hardware.
3322 * This is also called by the gennetlink interface when reconfiguring
3323 * the DCB state.
3324 */
3325static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3326{
3327 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3328 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5f6c0181 3329 u32 txdctl;
2f90b865
AD		 3330 int i, j;
3331
67ebd791
AD		 3332 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3333 if (hw->mac.type == ixgbe_mac_82598EB)
3334 netif_set_gso_max_size(adapter->netdev, 65536);
3335 return;
3336 }
3337
3338 if (hw->mac.type == ixgbe_mac_82598EB)
3339 netif_set_gso_max_size(adapter->netdev, 32768);
3340
9806307a
JF		 3341#ifdef CONFIG_FCOE
3342 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3343 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3344#endif
3345
80ab193d 3346 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3347 DCB_TX_CONFIG);
80ab193d 3348 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3349 DCB_RX_CONFIG);
2f90b865
AD		 3350
3351 /* reconfigure the hardware */
3352 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3353
3354 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3355 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3356 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3357 /* PThresh workaround for Tx hang with DFP enabled. */
3358 txdctl |= 32;
3359 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3360 }
3361 /* Enable VLAN tag insert/strip */
f62bbb5e 3362 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3363
2f90b865
AD		 3364 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3365}
3366
3367#endif
9a799d71
AK		 3368static void ixgbe_configure(struct ixgbe_adapter *adapter)
3369{
3370 struct net_device *netdev = adapter->netdev;
c4cf55e5 3371 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3372 int i;
3373
7a6b6f51 3374#ifdef CONFIG_IXGBE_DCB
67ebd791 3375 ixgbe_configure_dcb(adapter);
2f90b865 3376#endif
9a799d71 3377
f62bbb5e
JG		 3378 ixgbe_set_rx_mode(netdev);
3379 ixgbe_restore_vlan(adapter);
3380
eacd73f7
YZ		 3381#ifdef IXGBE_FCOE
3382 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3383 ixgbe_configure_fcoe(adapter);
3384
3385#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3386 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3387 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3388 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3389 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3390 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3391 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3392 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3393 }
933d41f1 3394 ixgbe_configure_virtualization(adapter);
c4cf55e5 3395
9a799d71
AK		 3396 ixgbe_configure_tx(adapter);
3397 ixgbe_configure_rx(adapter);
9a799d71
AK		 3398}
3399
e8e26350
PW		 3400static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3401{
3402 switch (hw->phy.type) {
3403 case ixgbe_phy_sfp_avago:
3404 case ixgbe_phy_sfp_ftl:
3405 case ixgbe_phy_sfp_intel:
3406 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3407 case ixgbe_phy_sfp_passive_tyco:
3408 case ixgbe_phy_sfp_passive_unknown:
3409 case ixgbe_phy_sfp_active_unknown:
3410 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3411 return true;
3412 default:
3413 return false;
3414 }
3415}
3416
0ecc061d 3417/**
e8e26350
PW		 3418 * ixgbe_sfp_link_config - set up SFP+ link
3419 * @adapter: pointer to private adapter struct
3420 **/
3421static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3422{
3423 struct ixgbe_hw *hw = &adapter->hw;
3424
3425 if (hw->phy.multispeed_fiber) {
3426 /*
3427 * In multispeed fiber setups, the device may not have
3428 * had a physical connection when the driver loaded.
3429 * If that's the case, the initial link configuration
3430 * couldn't get the MAC into 10G or 1G mode, so we'll
3431 * never have a link status change interrupt fire.
3432 * We need to try and force an autonegotiation
3433 * session, then bring up link.
3434 */
3435 hw->mac.ops.setup_sfp(hw);
3436 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3437 schedule_work(&adapter->multispeed_fiber_task);
3438 } else {
3439 /*
3440 * Direct Attach Cu and non-multispeed fiber modules
3441 * still need to be configured properly prior to
3442 * attempting link.
3443 */
3444 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3445 schedule_work(&adapter->sfp_config_module_task);
3446 }
3447}
3448
3449/**
3450 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3451 * @hw: pointer to private hardware struct
3452 *
3453 * Returns 0 on success, negative on failure
3454 **/
e8e26350 3455static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3456{
3457 u32 autoneg;
8620a103 3458 bool negotiation, link_up = false;
0ecc061d
PWJ		 3459 u32 ret = IXGBE_ERR_LINK_SETUP;
3460
3461 if (hw->mac.ops.check_link)
3462 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3463
3464 if (ret)
3465 goto link_cfg_out;
3466
3467 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3468 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3469 &negotiation);
0ecc061d
PWJ		 3470 if (ret)
3471 goto link_cfg_out;
3472
8620a103
MC		 3473 if (hw->mac.ops.setup_link)
3474 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3475link_cfg_out:
3476 return ret;
3477}
3478
a34bcfff 3479static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3480{
9a799d71 3481 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3482 u32 gpie = 0;
9a799d71 3483
9b471446 3484 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3485 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3486 IXGBE_GPIE_OCD;
3487 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3488 /*
3489 * use EIAM to auto-mask when MSI-X interrupt is asserted
3490 * this saves a register write for every interrupt
3491 */
3492 switch (hw->mac.type) {
3493 case ixgbe_mac_82598EB:
3494 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3495 break;
3496 default:
3497 case ixgbe_mac_82599EB:
3498 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3499 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3500 break;
3501 }
3502 } else {
021230d4
AV		 3503 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3504 * specifically only auto mask tx and rx interrupts */
3505 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3506 }
9a799d71 3507
a34bcfff
AD		 3508 /* XXX: to interrupt immediately for EICS writes, enable this */
3509 /* gpie |= IXGBE_GPIE_EIMEN; */
3510
3511 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3512 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3513 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3514 }
3515
a34bcfff
AD		 3516 /* Enable fan failure interrupt */
3517 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3518 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3519
a34bcfff 3520 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3521 gpie |= IXGBE_SDP1_GPIEN;
3522 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3523
3524 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3525}
3526
3527static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3528{
3529 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3530 int err;
a34bcfff
AD		 3531 u32 ctrl_ext;
3532
3533 ixgbe_get_hw_control(adapter);
3534 ixgbe_setup_gpie(adapter);
e8e26350 3535
9a799d71
AK		 3536 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3537 ixgbe_configure_msix(adapter);
3538 else
3539 ixgbe_configure_msi_and_legacy(adapter);
3540
61fac744
PW		 3541 /* enable the optics */
3542 if (hw->phy.multispeed_fiber)
3543 hw->mac.ops.enable_tx_laser(hw);
3544
9a799d71 3545 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3546 ixgbe_napi_enable_all(adapter);
3547
3548 /* clear any pending interrupts, may auto mask */
3549 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3550 ixgbe_irq_enable(adapter, true, true);
9a799d71 3551
bf069c97
DS		 3552 /*
3553 * If this adapter has a fan, check to see if we had a failure
3554 * before we enabled the interrupt.
3555 */
3556 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3557 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3558 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3559 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3560 }
3561
e8e26350
PW		 3562 /*
3563 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3564 * arrived before interrupts were enabled but after probe. Such
3565 * devices wouldn't have their type identified yet. We need to
3566 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3567 * If we're not hot-pluggable SFP+, we just need to configure link
3568 * and bring it up.
3569 */
19343de2
DS		 3570 if (hw->phy.type == ixgbe_phy_unknown) {
3571 err = hw->phy.ops.identify(hw);
3572 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3573 /*
3574 * Take the device down and schedule the sfp tasklet
3575 * which will unregister_netdev and log it.
3576 */
19343de2 3577 ixgbe_down(adapter);
5da43c1a 3578 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3579 return err;
3580 }
e8e26350
PW		 3581 }
3582
3583 if (ixgbe_is_sfp(hw)) {
3584 ixgbe_sfp_link_config(adapter);
3585 } else {
3586 err = ixgbe_non_sfp_link_config(hw);
3587 if (err)
396e799c 3588 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3589 }
0ecc061d 3590
1da100bb 3591 /* enable transmits */
477de6ed 3592 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3593
9a799d71
AK		 3594 /* bring the link up in the watchdog, this could race with our first
3595 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3596 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3597 adapter->link_check_timeout = jiffies;
9a799d71 3598 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3599
3600 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3601 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3602 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3603 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3604
9a799d71
AK		 3605 return 0;
3606}
3607
d4f80882
AV		 3608void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3609{
3610 WARN_ON(in_interrupt());
3611 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3612 msleep(1);
3613 ixgbe_down(adapter);
5809a1ae
GR		 3614 /*
3615 * If SR-IOV enabled then wait a bit before bringing the adapter
3616 * back up to give the VFs time to respond to the reset. The
3617 * two second wait is based upon the watchdog timer cycle in
3618 * the VF driver.
3619 */
3620 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3621 msleep(2000);
d4f80882
AV		 3622 ixgbe_up(adapter);
3623 clear_bit(__IXGBE_RESETTING, &adapter->state);
3624}
3625
9a799d71
AK		 3626int ixgbe_up(struct ixgbe_adapter *adapter)
3627{
3628 /* hardware has been reset, we need to reload some things */
3629 ixgbe_configure(adapter);
3630
3631 return ixgbe_up_complete(adapter);
3632}
3633
3634void ixgbe_reset(struct ixgbe_adapter *adapter)
3635{
c44ade9e 3636 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3637 int err;
3638
3639 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3640 switch (err) {
3641 case 0:
3642 case IXGBE_ERR_SFP_NOT_PRESENT:
3643 break;
3644 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3645 e_dev_err("master disable timed out\n");
da4dd0f7 3646 break;
794caeb2
PWJ		 3647 case IXGBE_ERR_EEPROM_VERSION:
3648 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3649 e_dev_warn("This device is a pre-production adapter/LOM. "
3650 "Please be aware there may be issuesassociated with "
3651 "your hardware. If you are experiencing problems "
3652 "please contact your Intel or hardware "
3653 "representative who provided you with this "
3654 "hardware.\n");
794caeb2 3655 break;
da4dd0f7 3656 default:
849c4542 3657 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3658 }
9a799d71
AK		 3659
3660 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3661 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3662 IXGBE_RAH_AV);
9a799d71
AK		 3663}
3664
9a799d71
AK		 3665/**
3666 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3667 * @rx_ring: ring to free buffers from
3668 **/
b6ec895e 3669static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3670{
b6ec895e 3671 struct device *dev = rx_ring->dev;
9a799d71 3672 unsigned long size;
b6ec895e 3673 u16 i;
9a799d71 3674
84418e3b
AD		 3675 /* ring already cleared, nothing to do */
3676 if (!rx_ring->rx_buffer_info)
3677 return;
9a799d71 3678
84418e3b 3679 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3680 for (i = 0; i < rx_ring->count; i++) {
3681 struct ixgbe_rx_buffer *rx_buffer_info;
3682
3683 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3684 if (rx_buffer_info->dma) {
b6ec895e 3685 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3686 rx_ring->rx_buf_len,
1b507730 3687 DMA_FROM_DEVICE);
9a799d71
AK		 3688 rx_buffer_info->dma = 0;
3689 }
3690 if (rx_buffer_info->skb) {
f8212f97 3691 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3692 rx_buffer_info->skb = NULL;
f8212f97
AD		 3693 do {
3694 struct sk_buff *this = skb;
e8171aaa 3695 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3696 dma_unmap_single(dev,
1b507730 3697 IXGBE_RSC_CB(this)->dma,
e8e9f696 3698 rx_ring->rx_buf_len,
1b507730 3699 DMA_FROM_DEVICE);
fd3686a8 3700 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3701 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3702 }
f8212f97
AD		 3703 skb = skb->prev;
3704 dev_kfree_skb(this);
3705 } while (skb);
9a799d71
AK		 3706 }
3707 if (!rx_buffer_info->page)
3708 continue;
4f57ca6e 3709 if (rx_buffer_info->page_dma) {
b6ec895e 3710 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3711 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3712 rx_buffer_info->page_dma = 0;
3713 }
9a799d71
AK		 3714 put_page(rx_buffer_info->page);
3715 rx_buffer_info->page = NULL;
762f4c57 3716 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3717 }
3718
3719 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3720 memset(rx_ring->rx_buffer_info, 0, size);
3721
3722 /* Zero out the descriptor ring */
3723 memset(rx_ring->desc, 0, rx_ring->size);
3724
3725 rx_ring->next_to_clean = 0;
3726 rx_ring->next_to_use = 0;
9a799d71
AK		 3727}
3728
3729/**
3730 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3731 * @tx_ring: ring to be cleaned
3732 **/
b6ec895e 3733static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3734{
3735 struct ixgbe_tx_buffer *tx_buffer_info;
3736 unsigned long size;
b6ec895e 3737 u16 i;
9a799d71 3738
84418e3b
AD		 3739 /* ring already cleared, nothing to do */
3740 if (!tx_ring->tx_buffer_info)
3741 return;
9a799d71 3742
84418e3b 3743 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3744 for (i = 0; i < tx_ring->count; i++) {
3745 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3746 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3747 }
3748
3749 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3750 memset(tx_ring->tx_buffer_info, 0, size);
3751
3752 /* Zero out the descriptor ring */
3753 memset(tx_ring->desc, 0, tx_ring->size);
3754
3755 tx_ring->next_to_use = 0;
3756 tx_ring->next_to_clean = 0;
9a799d71
AK		 3757}
3758
3759/**
021230d4 3760 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3761 * @adapter: board private structure
3762 **/
021230d4 3763static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3764{
3765 int i;
3766
021230d4 3767 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3768 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3769}
3770
3771/**
021230d4 3772 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3773 * @adapter: board private structure
3774 **/
021230d4 3775static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3776{
3777 int i;
3778
021230d4 3779 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3780 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3781}
3782
3783void ixgbe_down(struct ixgbe_adapter *adapter)
3784{
3785 struct net_device *netdev = adapter->netdev;
7f821875 3786 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3787 u32 rxctrl;
7f821875
JB		 3788 u32 txdctl;
3789 int i, j;
b25ebfd2 3790 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3791
3792 /* signal that we are down to the interrupt handler */
3793 set_bit(__IXGBE_DOWN, &adapter->state);
3794
767081ad
GR		 3795 /* disable receive for all VFs and wait one second */
3796 if (adapter->num_vfs) {
767081ad
GR		 3797 /* ping all the active vfs to let them know we are going down */
3798 ixgbe_ping_all_vfs(adapter);
581d1aa7 3799
767081ad
GR		 3800 /* Disable all VFTE/VFRE TX/RX */
3801 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3802
3803 /* Mark all the VFs as inactive */
3804 for (i = 0 ; i < adapter->num_vfs; i++)
3805 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3806 }
3807
9a799d71 3808 /* disable receives */
7f821875
JB		 3809 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3810 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3811
7f821875 3812 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3813 msleep(10);
3814
7f821875
JB		 3815 netif_tx_stop_all_queues(netdev);
3816
0a1f87cb
DS		 3817 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3818 del_timer_sync(&adapter->sfp_timer);
9a799d71 3819 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3820 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3821
c0dfb90e
JF		 3822 netif_carrier_off(netdev);
3823 netif_tx_disable(netdev);
3824
3825 ixgbe_irq_disable(adapter);
3826
3827 ixgbe_napi_disable_all(adapter);
3828
b25ebfd2
PW		 3829 /* Cleanup the affinity_hint CPU mask memory and callback */
3830 for (i = 0; i < num_q_vectors; i++) {
3831 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3832 /* clear the affinity_mask in the IRQ descriptor */
3833 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3834 /* release the CPU mask memory */
3835 free_cpumask_var(q_vector->affinity_mask);
3836 }
3837
c4cf55e5
PWJ		 3838 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3839 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3840 cancel_work_sync(&adapter->fdir_reinit_task);
3841
119fc60a
MC		 3842 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3843 cancel_work_sync(&adapter->check_overtemp_task);
3844
7f821875
JB		 3845 /* disable transmits in the hardware now that interrupts are off */
3846 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3847 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3848 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3849 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3850 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3851 }
88512539
PW		 3852 /* Disable the Tx DMA engine on 82599 */
3853 if (hw->mac.type == ixgbe_mac_82599EB)
3854 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3855 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3856 ~IXGBE_DMATXCTL_TE));
7f821875 3857
9f756f01
JF		 3858 /* power down the optics */
3859 if (hw->phy.multispeed_fiber)
3860 hw->mac.ops.disable_tx_laser(hw);
3861
9a713e7c
PW		 3862 /* clear n-tuple filters that are cached */
3863 ethtool_ntuple_flush(netdev);
3864
6f4a0e45
PL		 3865 if (!pci_channel_offline(adapter->pdev))
3866 ixgbe_reset(adapter);
9a799d71
AK		 3867 ixgbe_clean_all_tx_rings(adapter);
3868 ixgbe_clean_all_rx_rings(adapter);
3869
5dd2d332 3870#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3871 /* since we reset the hardware DCA settings were cleared */
e35ec126 3872 ixgbe_setup_dca(adapter);
96b0e0f6 3873#endif
9a799d71
AK		 3874}
3875
9a799d71 3876/**
021230d4
AV		 3877 * ixgbe_poll - NAPI Rx polling callback
3878 * @napi: structure for representing this polling device
3879 * @budget: how many packets driver is allowed to clean
3880 *
3881 * This function is used for legacy and MSI, NAPI mode
9a799d71 3882 **/
021230d4 3883static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3884{
9a1a69ad 3885 struct ixgbe_q_vector *q_vector =
e8e9f696 3886 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3887 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3888 int tx_clean_complete, work_done = 0;
9a799d71 3889
5dd2d332 3890#ifdef CONFIG_IXGBE_DCA
bd0362dd 3891 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3892 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3893 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3894 }
3895#endif
3896
4a0b9ca0
PW		 3897 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3898 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3899
9a1a69ad 3900 if (!tx_clean_complete)
d2c7ddd6
DM		 3901 work_done = budget;
3902
53e52c72
DM		 3903 /* If budget not fully consumed, exit the polling mode */
3904 if (work_done < budget) {
288379f0 3905 napi_complete(napi);
f7554a2b 3906 if (adapter->rx_itr_setting & 1)
f494e8fa 3907 ixgbe_set_itr(adapter);
d4f80882 3908 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3909 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3910 }
9a799d71
AK		 3911 return work_done;
3912}
3913
3914/**
3915 * ixgbe_tx_timeout - Respond to a Tx Hang
3916 * @netdev: network interface device structure
3917 **/
3918static void ixgbe_tx_timeout(struct net_device *netdev)
3919{
3920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3921
3922 /* Do the reset outside of interrupt context */
3923 schedule_work(&adapter->reset_task);
3924}
3925
3926static void ixgbe_reset_task(struct work_struct *work)
3927{
3928 struct ixgbe_adapter *adapter;
3929 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3930
2f90b865
AD		 3931 /* If we're already down or resetting, just bail */
3932 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3933 test_bit(__IXGBE_RESETTING, &adapter->state))
3934 return;
3935
9a799d71
AK		 3936 adapter->tx_timeout_count++;
3937
dcd79aeb
TI		 3938 ixgbe_dump(adapter);
3939 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3940 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3941}
3942
bc97114d
PWJ		 3943#ifdef CONFIG_IXGBE_DCB
3944static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3945{
bc97114d 3946 bool ret = false;
0cefafad 3947 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3948
0cefafad
JB		 3949 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3950 return ret;
3951
3952 f->mask = 0x7 << 3;
3953 adapter->num_rx_queues = f->indices;
3954 adapter->num_tx_queues = f->indices;
3955 ret = true;
2f90b865 3956
bc97114d
PWJ		 3957 return ret;
3958}
3959#endif
3960
4df10466
JB		 3961/**
3962 * ixgbe_set_rss_queues: Allocate queues for RSS
3963 * @adapter: board private structure to initialize
3964 *
3965 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3966 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3967 *
3968 **/
bc97114d
PWJ		 3969static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3970{
3971 bool ret = false;
0cefafad 3972 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3973
3974 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3975 f->mask = 0xF;
3976 adapter->num_rx_queues = f->indices;
3977 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3978 ret = true;
3979 } else {
bc97114d 3980 ret = false;
b9804972
JB		 3981 }
3982
bc97114d
PWJ		 3983 return ret;
3984}
3985
c4cf55e5
PWJ		 3986/**
3987 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3988 * @adapter: board private structure to initialize
3989 *
3990 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3991 * to the original CPU that initiated the Tx session. This runs in addition
3992 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3993 * Rx load across CPUs using RSS.
3994 *
3995 **/
e8e9f696 3996static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 3997{
3998 bool ret = false;
3999 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4000
4001 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4002 f_fdir->mask = 0;
4003
4004 /* Flow Director must have RSS enabled */
4005 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4006 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4007 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4008 adapter->num_tx_queues = f_fdir->indices;
4009 adapter->num_rx_queues = f_fdir->indices;
4010 ret = true;
4011 } else {
4012 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4013 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4014 }
4015 return ret;
4016}
4017
0331a832
YZ		 4018#ifdef IXGBE_FCOE
4019/**
4020 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4021 * @adapter: board private structure to initialize
4022 *
4023 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4024 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4025 * rx queues out of the max number of rx queues, instead, it is used as the
4026 * index of the first rx queue used by FCoE.
4027 *
4028 **/
4029static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4030{
4031 bool ret = false;
4032 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4033
4034 f->indices = min((int)num_online_cpus(), f->indices);
4035 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4036 adapter->num_rx_queues = 1;
4037 adapter->num_tx_queues = 1;
0331a832
YZ		 4038#ifdef CONFIG_IXGBE_DCB
4039 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4040 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4041 ixgbe_set_dcb_queues(adapter);
4042 }
4043#endif
4044 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4045 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4046 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4047 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4048 ixgbe_set_fdir_queues(adapter);
4049 else
4050 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4051 }
4052 /* adding FCoE rx rings to the end */
4053 f->mask = adapter->num_rx_queues;
4054 adapter->num_rx_queues += f->indices;
8de8b2e6 4055 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4056
4057 ret = true;
4058 }
4059
4060 return ret;
4061}
4062
4063#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4064/**
4065 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4066 * @adapter: board private structure to initialize
4067 *
4068 * IOV doesn't actually use anything, so just NAK the
4069 * request for now and let the other queue routines
4070 * figure out what to do.
4071 */
4072static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4073{
4074 return false;
4075}
4076
4df10466
JB		 4077/*
4078 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4079 * @adapter: board private structure to initialize
4080 *
4081 * This is the top level queue allocation routine. The order here is very
4082 * important, starting with the "most" number of features turned on at once,
4083 * and ending with the smallest set of features. This way large combinations
4084 * can be allocated if they're turned on, and smaller combinations are the
4085 * fallthrough conditions.
4086 *
4087 **/
847f53ff 4088static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4089{
1cdd1ec8
GR		 4090 /* Start with base case */
4091 adapter->num_rx_queues = 1;
4092 adapter->num_tx_queues = 1;
4093 adapter->num_rx_pools = adapter->num_rx_queues;
4094 adapter->num_rx_queues_per_pool = 1;
4095
4096 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4097 goto done;
1cdd1ec8 4098
0331a832
YZ		 4099#ifdef IXGBE_FCOE
4100 if (ixgbe_set_fcoe_queues(adapter))
4101 goto done;
4102
4103#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4104#ifdef CONFIG_IXGBE_DCB
4105 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4106 goto done;
bc97114d
PWJ		 4107
4108#endif
c4cf55e5
PWJ		 4109 if (ixgbe_set_fdir_queues(adapter))
4110 goto done;
4111
bc97114d 4112 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4113 goto done;
4114
4115 /* fallback to base case */
4116 adapter->num_rx_queues = 1;
4117 adapter->num_tx_queues = 1;
4118
4119done:
847f53ff 4120 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4121 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4122 return netif_set_real_num_rx_queues(adapter->netdev,
4123 adapter->num_rx_queues);
b9804972
JB		 4124}
4125
021230d4 4126static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4127 int vectors)
021230d4
AV		 4128{
4129 int err, vector_threshold;
4130
4131 /* We'll want at least 3 (vector_threshold):
4132 * 1) TxQ[0] Cleanup
4133 * 2) RxQ[0] Cleanup
4134 * 3) Other (Link Status Change, etc.)
4135 * 4) TCP Timer (optional)
4136 */
4137 vector_threshold = MIN_MSIX_COUNT;
4138
4139 /* The more we get, the more we will assign to Tx/Rx Cleanup
4140 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4141 * Right now, we simply care about how many we'll get; we'll
4142 * set them up later while requesting irq's.
4143 */
4144 while (vectors >= vector_threshold) {
4145 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4146 vectors);
021230d4
AV		 4147 if (!err) /* Success in acquiring all requested vectors. */
4148 break;
4149 else if (err < 0)
4150 vectors = 0; /* Nasty failure, quit now */
4151 else /* err == number of vectors we should try again with */
4152 vectors = err;
4153 }
4154
4155 if (vectors < vector_threshold) {
4156 /* Can't allocate enough MSI-X interrupts? Oh well.
4157 * This just means we'll go with either a single MSI
4158 * vector or fall back to legacy interrupts.
4159 */
849c4542
ET		 4160 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4161 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4162 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4163 kfree(adapter->msix_entries);
4164 adapter->msix_entries = NULL;
021230d4
AV		 4165 } else {
4166 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4167 /*
4168 * Adjust for only the vectors we'll use, which is minimum
4169 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4170 * vectors we were allocated.
4171 */
4172 adapter->num_msix_vectors = min(vectors,
e8e9f696 4173 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4174 }
4175}
4176
021230d4 4177/**
bc97114d 4178 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4179 * @adapter: board private structure to initialize
4180 *
bc97114d
PWJ		 4181 * Cache the descriptor ring offsets for RSS to the assigned rings.
4182 *
021230d4 4183 **/
bc97114d 4184static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4185{
bc97114d
PWJ		 4186 int i;
4187 bool ret = false;
4188
4189 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4190 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4191 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4192 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4193 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4194 ret = true;
4195 } else {
4196 ret = false;
4197 }
4198
4199 return ret;
4200}
4201
4202#ifdef CONFIG_IXGBE_DCB
4203/**
4204 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4205 * @adapter: board private structure to initialize
4206 *
4207 * Cache the descriptor ring offsets for DCB to the assigned rings.
4208 *
4209 **/
4210static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4211{
4212 int i;
4213 bool ret = false;
4214 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4215
4216 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4217 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4218 /* the number of queues is assumed to be symmetric */
4219 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4220 adapter->rx_ring[i]->reg_idx = i << 3;
4221 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4222 }
bc97114d 4223 ret = true;
e8e26350 4224 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4225 if (dcb_i == 8) {
4226 /*
4227 * Tx TC0 starts at: descriptor queue 0
4228 * Tx TC1 starts at: descriptor queue 32
4229 * Tx TC2 starts at: descriptor queue 64
4230 * Tx TC3 starts at: descriptor queue 80
4231 * Tx TC4 starts at: descriptor queue 96
4232 * Tx TC5 starts at: descriptor queue 104
4233 * Tx TC6 starts at: descriptor queue 112
4234 * Tx TC7 starts at: descriptor queue 120
4235 *
4236 * Rx TC0-TC7 are offset by 16 queues each
4237 */
4238 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4239 adapter->tx_ring[i]->reg_idx = i << 5;
4240 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4241 }
4242 for ( ; i < 5; i++) {
4a0b9ca0 4243 adapter->tx_ring[i]->reg_idx =
e8e9f696 4244 ((i + 2) << 4);
4a0b9ca0 4245 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4246 }
4247 for ( ; i < dcb_i; i++) {
4a0b9ca0 4248 adapter->tx_ring[i]->reg_idx =
e8e9f696 4249 ((i + 8) << 3);
4a0b9ca0 4250 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4251 }
4252
4253 ret = true;
4254 } else if (dcb_i == 4) {
4255 /*
4256 * Tx TC0 starts at: descriptor queue 0
4257 * Tx TC1 starts at: descriptor queue 64
4258 * Tx TC2 starts at: descriptor queue 96
4259 * Tx TC3 starts at: descriptor queue 112
4260 *
4261 * Rx TC0-TC3 are offset by 32 queues each
4262 */
4a0b9ca0
PW		 4263 adapter->tx_ring[0]->reg_idx = 0;
4264 adapter->tx_ring[1]->reg_idx = 64;
4265 adapter->tx_ring[2]->reg_idx = 96;
4266 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4267 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4268 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4269
4270 ret = true;
4271 } else {
4272 ret = false;
e8e26350 4273 }
bc97114d
PWJ		 4274 } else {
4275 ret = false;
021230d4 4276 }
bc97114d
PWJ		 4277 } else {
4278 ret = false;
021230d4 4279 }
bc97114d
PWJ		 4280
4281 return ret;
4282}
4283#endif
4284
c4cf55e5
PWJ		 4285/**
4286 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4287 * @adapter: board private structure to initialize
4288 *
4289 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4290 *
4291 **/
e8e9f696 4292static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4293{
4294 int i;
4295 bool ret = false;
4296
4297 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4298 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4299 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4300 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4301 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4302 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4303 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4304 ret = true;
4305 }
4306
4307 return ret;
4308}
4309
0331a832
YZ		 4310#ifdef IXGBE_FCOE
4311/**
4312 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4313 * @adapter: board private structure to initialize
4314 *
4315 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4316 *
4317 */
4318static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4319{
8de8b2e6 4320 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4321 bool ret = false;
4322 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4323
4324 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4325#ifdef CONFIG_IXGBE_DCB
4326 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4327 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4328
0331a832 4329 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4330 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4331 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4332 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4333 /*
4334 * In 82599, the number of Tx queues for each traffic
4335 * class for both 8-TC and 4-TC modes are:
4336 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4337 * 8 TCs: 32 32 16 16 8 8 8 8
4338 * 4 TCs: 64 64 32 32
4339 * We have max 8 queues for FCoE, where 8 the is
4340 * FCoE redirection table size. If TC for FCoE is
4341 * less than or equal to TC3, we have enough queues
4342 * to add max of 8 queues for FCoE, so we start FCoE
4343 * tx descriptor from the next one, i.e., reg_idx + 1.
4344 * If TC for FCoE is above TC3, implying 8 TC mode,
4345 * and we need 8 for FCoE, we have to take all queues
4346 * in that traffic class for FCoE.
4347 */
4348 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4349 fcoe_tx_i--;
0331a832
YZ		 4350 }
4351#endif /* CONFIG_IXGBE_DCB */
4352 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4353 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4354 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4355 ixgbe_cache_ring_fdir(adapter);
4356 else
4357 ixgbe_cache_ring_rss(adapter);
4358
8de8b2e6
YZ		 4359 fcoe_rx_i = f->mask;
4360 fcoe_tx_i = f->mask;
4361 }
4362 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4363 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4364 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4365 }
0331a832
YZ		 4366 ret = true;
4367 }
4368 return ret;
4369}
4370
4371#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4372/**
4373 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4374 * @adapter: board private structure to initialize
4375 *
4376 * SR-IOV doesn't use any descriptor rings but changes the default if
4377 * no other mapping is used.
4378 *
4379 */
4380static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4381{
4a0b9ca0
PW		 4382 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4383 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4384 if (adapter->num_vfs)
4385 return true;
4386 else
4387 return false;
4388}
4389
bc97114d
PWJ		 4390/**
4391 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4392 * @adapter: board private structure to initialize
4393 *
4394 * Once we know the feature-set enabled for the device, we'll cache
4395 * the register offset the descriptor ring is assigned to.
4396 *
4397 * Note, the order the various feature calls is important. It must start with
4398 * the "most" features enabled at the same time, then trickle down to the
4399 * least amount of features turned on at once.
4400 **/
4401static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4402{
4403 /* start with default case */
4a0b9ca0
PW		 4404 adapter->rx_ring[0]->reg_idx = 0;
4405 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4406
1cdd1ec8
GR		 4407 if (ixgbe_cache_ring_sriov(adapter))
4408 return;
4409
0331a832
YZ		 4410#ifdef IXGBE_FCOE
4411 if (ixgbe_cache_ring_fcoe(adapter))
4412 return;
4413
4414#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4415#ifdef CONFIG_IXGBE_DCB
4416 if (ixgbe_cache_ring_dcb(adapter))
4417 return;
4418
4419#endif
c4cf55e5
PWJ		 4420 if (ixgbe_cache_ring_fdir(adapter))
4421 return;
4422
bc97114d
PWJ		 4423 if (ixgbe_cache_ring_rss(adapter))
4424 return;
021230d4
AV		 4425}
4426
9a799d71
AK		 4427/**
4428 * ixgbe_alloc_queues - Allocate memory for all rings
4429 * @adapter: board private structure to initialize
4430 *
4431 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4432 * number of queues at compile-time. The polling_netdev array is
4433 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4434 **/
2f90b865 4435static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4436{
4437 int i;
b6ec895e 4438 int rx_count;
4a0b9ca0 4439 int orig_node = adapter->node;
9a799d71 4440
021230d4 4441 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4442 struct ixgbe_ring *ring = adapter->tx_ring[i];
4443 if (orig_node == -1) {
4444 int cur_node = next_online_node(adapter->node);
4445 if (cur_node == MAX_NUMNODES)
4446 cur_node = first_online_node;
4447 adapter->node = cur_node;
4448 }
4449 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4450 adapter->node);
4a0b9ca0
PW		 4451 if (!ring)
4452 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4453 if (!ring)
4454 goto err_tx_ring_allocation;
4455 ring->count = adapter->tx_ring_count;
4456 ring->queue_index = i;
b6ec895e 4457 ring->dev = &adapter->pdev->dev;
4a0b9ca0
PW		 4458 ring->numa_node = adapter->node;
4459
4460 adapter->tx_ring[i] = ring;
021230d4 4461 }
b9804972 4462
4a0b9ca0
PW		 4463 /* Restore the adapter's original node */
4464 adapter->node = orig_node;
4465
b6ec895e 4466 rx_count = adapter->rx_ring_count;
9a799d71 4467 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4468 struct ixgbe_ring *ring = adapter->rx_ring[i];
4469 if (orig_node == -1) {
4470 int cur_node = next_online_node(adapter->node);
4471 if (cur_node == MAX_NUMNODES)
4472 cur_node = first_online_node;
4473 adapter->node = cur_node;
4474 }
4475 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4476 adapter->node);
4a0b9ca0
PW		 4477 if (!ring)
4478 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4479 if (!ring)
4480 goto err_rx_ring_allocation;
b6ec895e 4481 ring->count = rx_count;
4a0b9ca0 4482 ring->queue_index = i;
b6ec895e 4483 ring->dev = &adapter->pdev->dev;
4a0b9ca0
PW		 4484 ring->numa_node = adapter->node;
4485
4486 adapter->rx_ring[i] = ring;
021230d4
AV		 4487 }
4488
4a0b9ca0
PW		 4489 /* Restore the adapter's original node */
4490 adapter->node = orig_node;
4491
021230d4
AV		 4492 ixgbe_cache_ring_register(adapter);
4493
4494 return 0;
4495
4496err_rx_ring_allocation:
4a0b9ca0
PW		 4497 for (i = 0; i < adapter->num_tx_queues; i++)
4498 kfree(adapter->tx_ring[i]);
021230d4
AV		 4499err_tx_ring_allocation:
4500 return -ENOMEM;
4501}
4502
4503/**
4504 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4505 * @adapter: board private structure to initialize
4506 *
4507 * Attempt to configure the interrupts using the best available
4508 * capabilities of the hardware and the kernel.
4509 **/
feea6a57 4510static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4511{
8be0e467 4512 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4513 int err = 0;
4514 int vector, v_budget;
4515
4516 /*
4517 * It's easy to be greedy for MSI-X vectors, but it really
4518 * doesn't do us much good if we have a lot more vectors
4519 * than CPU's. So let's be conservative and only ask for
342bde1b 4520 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4521 */
4522 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4523 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4524
4525 /*
4526 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4527 * hw.mac->max_msix_vectors vectors. With features
4528 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4529 * descriptor queues supported by our device. Thus, we cap it off in
4530 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4531 */
8be0e467 4532 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4533
4534 /* A failure in MSI-X entry allocation isn't fatal, but it does
4535 * mean we disable MSI-X capabilities of the adapter. */
4536 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4537 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4538 if (adapter->msix_entries) {
4539 for (vector = 0; vector < v_budget; vector++)
4540 adapter->msix_entries[vector].entry = vector;
021230d4 4541
7a921c93 4542 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4543
7a921c93
AD		 4544 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4545 goto out;
4546 }
26d27844 4547
7a921c93
AD		 4548 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4549 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4550 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4551 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4552 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4553 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4554 ixgbe_disable_sriov(adapter);
4555
847f53ff
BH		 4556 err = ixgbe_set_num_queues(adapter);
4557 if (err)
4558 return err;
021230d4 4559
021230d4
AV		 4560 err = pci_enable_msi(adapter->pdev);
4561 if (!err) {
4562 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4563 } else {
849c4542
ET		 4564 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4565 "Unable to allocate MSI interrupt, "
4566 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4567 /* reset err */
4568 err = 0;
4569 }
4570
4571out:
021230d4
AV		 4572 return err;
4573}
4574
7a921c93
AD		 4575/**
4576 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4577 * @adapter: board private structure to initialize
4578 *
4579 * We allocate one q_vector per queue interrupt. If allocation fails we
4580 * return -ENOMEM.
4581 **/
4582static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4583{
4584 int q_idx, num_q_vectors;
4585 struct ixgbe_q_vector *q_vector;
4586 int napi_vectors;
4587 int (*poll)(struct napi_struct *, int);
4588
4589 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4590 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4591 napi_vectors = adapter->num_rx_queues;
91281fd3 4592 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4593 } else {
4594 num_q_vectors = 1;
4595 napi_vectors = 1;
4596 poll = &ixgbe_poll;
4597 }
4598
4599 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4600 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4601 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4602 if (!q_vector)
4603 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4604 GFP_KERNEL);
7a921c93
AD		 4605 if (!q_vector)
4606 goto err_out;
4607 q_vector->adapter = adapter;
f7554a2b
NS		 4608 if (q_vector->txr_count && !q_vector->rxr_count)
4609 q_vector->eitr = adapter->tx_eitr_param;
4610 else
4611 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4612 q_vector->v_idx = q_idx;
91281fd3 4613 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4614 adapter->q_vector[q_idx] = q_vector;
4615 }
4616
4617 return 0;
4618
4619err_out:
4620 while (q_idx) {
4621 q_idx--;
4622 q_vector = adapter->q_vector[q_idx];
4623 netif_napi_del(&q_vector->napi);
4624 kfree(q_vector);
4625 adapter->q_vector[q_idx] = NULL;
4626 }
4627 return -ENOMEM;
4628}
4629
4630/**
4631 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4632 * @adapter: board private structure to initialize
4633 *
4634 * This function frees the memory allocated to the q_vectors. In addition if
4635 * NAPI is enabled it will delete any references to the NAPI struct prior
4636 * to freeing the q_vector.
4637 **/
4638static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4639{
4640 int q_idx, num_q_vectors;
7a921c93 4641
91281fd3 4642 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4643 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4644 else
7a921c93 4645 num_q_vectors = 1;
7a921c93
AD		 4646
4647 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4648 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4649 adapter->q_vector[q_idx] = NULL;
91281fd3 4650 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4651 kfree(q_vector);
4652 }
4653}
4654
7b25cdba 4655static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4656{
4657 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4658 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4659 pci_disable_msix(adapter->pdev);
4660 kfree(adapter->msix_entries);
4661 adapter->msix_entries = NULL;
4662 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4663 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4664 pci_disable_msi(adapter->pdev);
4665 }
021230d4
AV		 4666}
4667
4668/**
4669 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4670 * @adapter: board private structure to initialize
4671 *
4672 * We determine which interrupt scheme to use based on...
4673 * - Kernel support (MSI, MSI-X)
4674 * - which can be user-defined (via MODULE_PARAM)
4675 * - Hardware queue count (num_*_queues)
4676 * - defined by miscellaneous hardware support/features (RSS, etc.)
4677 **/
2f90b865 4678int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4679{
4680 int err;
4681
4682 /* Number of supported queues */
847f53ff
BH		 4683 err = ixgbe_set_num_queues(adapter);
4684 if (err)
4685 return err;
021230d4 4686
021230d4
AV		 4687 err = ixgbe_set_interrupt_capability(adapter);
4688 if (err) {
849c4542 4689 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4690 goto err_set_interrupt;
9a799d71
AK		 4691 }
4692
7a921c93
AD		 4693 err = ixgbe_alloc_q_vectors(adapter);
4694 if (err) {
849c4542 4695 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4696 goto err_alloc_q_vectors;
4697 }
4698
4699 err = ixgbe_alloc_queues(adapter);
4700 if (err) {
849c4542 4701 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4702 goto err_alloc_queues;
4703 }
4704
849c4542 4705 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4706 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4707 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4708
4709 set_bit(__IXGBE_DOWN, &adapter->state);
4710
9a799d71 4711 return 0;
021230d4 4712
7a921c93
AD		 4713err_alloc_queues:
4714 ixgbe_free_q_vectors(adapter);
4715err_alloc_q_vectors:
4716 ixgbe_reset_interrupt_capability(adapter);
021230d4 4717err_set_interrupt:
7a921c93
AD		 4718 return err;
4719}
4720
1a51502b
ED		 4721static void ring_free_rcu(struct rcu_head *head)
4722{
4723 kfree(container_of(head, struct ixgbe_ring, rcu));
4724}
4725
7a921c93
AD		 4726/**
4727 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4728 * @adapter: board private structure to clear interrupt scheme on
4729 *
4730 * We go through and clear interrupt specific resources and reset the structure
4731 * to pre-load conditions
4732 **/
4733void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4734{
4a0b9ca0
PW		 4735 int i;
4736
4737 for (i = 0; i < adapter->num_tx_queues; i++) {
4738 kfree(adapter->tx_ring[i]);
4739 adapter->tx_ring[i] = NULL;
4740 }
4741 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4742 struct ixgbe_ring *ring = adapter->rx_ring[i];
4743
4744 /* ixgbe_get_stats64() might access this ring, we must wait
4745 * a grace period before freeing it.
4746 */
4747 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 4748 adapter->rx_ring[i] = NULL;
4749 }
7a921c93
AD		 4750
4751 ixgbe_free_q_vectors(adapter);
4752 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4753}
4754
c4900be0
DS		 4755/**
4756 * ixgbe_sfp_timer - worker thread to find a missing module
4757 * @data: pointer to our adapter struct
4758 **/
4759static void ixgbe_sfp_timer(unsigned long data)
4760{
4761 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4762
4df10466
JB		 4763 /*
4764 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4765 * delays that sfp+ detection requires
4766 */
4767 schedule_work(&adapter->sfp_task);
4768}
4769
4770/**
4771 * ixgbe_sfp_task - worker thread to find a missing module
4772 * @work: pointer to work_struct containing our data
4773 **/
4774static void ixgbe_sfp_task(struct work_struct *work)
4775{
4776 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4777 struct ixgbe_adapter,
4778 sfp_task);
c4900be0
DS		 4779 struct ixgbe_hw *hw = &adapter->hw;
4780
4781 if ((hw->phy.type == ixgbe_phy_nl) &&
4782 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4783 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4784 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4785 goto reschedule;
4786 ret = hw->phy.ops.reset(hw);
4787 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4788 e_dev_err("failed to initialize because an unsupported "
4789 "SFP+ module type was detected.\n");
4790 e_dev_err("Reload the driver after installing a "
4791 "supported module.\n");
c4900be0
DS		 4792 unregister_netdev(adapter->netdev);
4793 } else {
396e799c 4794 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4795 }
4796 /* don't need this routine any more */
4797 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4798 }
4799 return;
4800reschedule:
4801 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4802 mod_timer(&adapter->sfp_timer,
e8e9f696 4803 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4804}
4805
9a799d71
AK		 4806/**
4807 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4808 * @adapter: board private structure to initialize
4809 *
4810 * ixgbe_sw_init initializes the Adapter private data structure.
4811 * Fields are initialized based on PCI device information and
4812 * OS network device settings (MTU size).
4813 **/
4814static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4815{
4816 struct ixgbe_hw *hw = &adapter->hw;
4817 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4818 struct net_device *dev = adapter->netdev;
021230d4 4819 unsigned int rss;
7a6b6f51 4820#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4821 int j;
4822 struct tc_configuration *tc;
4823#endif
16b61beb 4824 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4825
c44ade9e
JB		 4826 /* PCI config space info */
4827
4828 hw->vendor_id = pdev->vendor;
4829 hw->device_id = pdev->device;
4830 hw->revision_id = pdev->revision;
4831 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4832 hw->subsystem_device_id = pdev->subsystem_device;
4833
021230d4
AV		 4834 /* Set capability flags */
4835 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4836 adapter->ring_feature[RING_F_RSS].indices = rss;
4837 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4838 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4839 if (hw->mac.type == ixgbe_mac_82598EB) {
4840 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4841 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4842 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4843 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4844 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4845 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4846 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4847 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4848 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4849 if (dev->features & NETIF_F_NTUPLE) {
4850 /* Flow Director perfect filter enabled */
4851 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4852 adapter->atr_sample_rate = 0;
4853 spin_lock_init(&adapter->fdir_perfect_lock);
4854 } else {
4855 /* Flow Director hash filters enabled */
4856 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4857 adapter->atr_sample_rate = 20;
4858 }
c4cf55e5 4859 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4860 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4861 adapter->fdir_pballoc = 0;
eacd73f7 4862#ifdef IXGBE_FCOE
0d551589
YZ		 4863 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4864 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4865 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4866#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4867 /* Default traffic class to use for FCoE */
4868 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4869 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4870#endif
eacd73f7 4871#endif /* IXGBE_FCOE */
f8212f97 4872 }
2f90b865 4873
7a6b6f51 4874#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4875 /* Configure DCB traffic classes */
4876 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4877 tc = &adapter->dcb_cfg.tc_config[j];
4878 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4879 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4880 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4881 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4882 tc->dcb_pfc = pfc_disabled;
4883 }
4884 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4885 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4886 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4887 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4888 adapter->dcb_cfg.round_robin_enable = false;
4889 adapter->dcb_set_bitmap = 0x00;
4890 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4891 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4892
4893#endif
9a799d71
AK		 4894
4895 /* default flow control settings */
cd7664f6 4896 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4897 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4898#ifdef CONFIG_DCB
4899 adapter->last_lfc_mode = hw->fc.current_mode;
4900#endif
16b61beb
JF		 4901 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4902 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 4903 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4904 hw->fc.send_xon = true;
71fd570b 4905 hw->fc.disable_fc_autoneg = false;
9a799d71 4906
30efa5a3 4907 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4908 adapter->rx_itr_setting = 1;
4909 adapter->rx_eitr_param = 20000;
4910 adapter->tx_itr_setting = 1;
4911 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4912
4913 /* set defaults for eitr in MegaBytes */
4914 adapter->eitr_low = 10;
4915 adapter->eitr_high = 20;
4916
4917 /* set default ring sizes */
4918 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4919 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4920
9a799d71 4921 /* initialize eeprom parameters */
c44ade9e 4922 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4923 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4924 return -EIO;
4925 }
4926
021230d4 4927 /* enable rx csum by default */
9a799d71
AK		 4928 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4929
1a6c14a2
JB		 4930 /* get assigned NUMA node */
4931 adapter->node = dev_to_node(&pdev->dev);
4932
9a799d71
AK		 4933 set_bit(__IXGBE_DOWN, &adapter->state);
4934
4935 return 0;
4936}
4937
4938/**
4939 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4940 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4941 *
4942 * Return 0 on success, negative on failure
4943 **/
b6ec895e 4944int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4945{
b6ec895e 4946 struct device *dev = tx_ring->dev;
9a799d71
AK		 4947 int size;
4948
3a581073 4949 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4950 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4951 if (!tx_ring->tx_buffer_info)
4952 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4953 if (!tx_ring->tx_buffer_info)
4954 goto err;
3a581073 4955 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4956
4957 /* round up to nearest 4K */
12207e49 4958 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4959 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4960
b6ec895e 4961 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 4962 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4963 if (!tx_ring->desc)
4964 goto err;
9a799d71 4965
3a581073
JB		 4966 tx_ring->next_to_use = 0;
4967 tx_ring->next_to_clean = 0;
4968 tx_ring->work_limit = tx_ring->count;
9a799d71 4969 return 0;
e01c31a5
JB		 4970
4971err:
4972 vfree(tx_ring->tx_buffer_info);
4973 tx_ring->tx_buffer_info = NULL;
b6ec895e 4974 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4975 return -ENOMEM;
9a799d71
AK		 4976}
4977
69888674
AD		 4978/**
4979 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4980 * @adapter: board private structure
4981 *
4982 * If this function returns with an error, then it's possible one or
4983 * more of the rings is populated (while the rest are not). It is the
4984 * callers duty to clean those orphaned rings.
4985 *
4986 * Return 0 on success, negative on failure
4987 **/
4988static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4989{
4990 int i, err = 0;
4991
4992 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4993 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4994 if (!err)
4995 continue;
396e799c 4996 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4997 break;
4998 }
4999
5000 return err;
5001}
5002
9a799d71
AK		 5003/**
5004 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5005 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5006 *
5007 * Returns 0 on success, negative on failure
5008 **/
b6ec895e 5009int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5010{
b6ec895e 5011 struct device *dev = rx_ring->dev;
021230d4 5012 int size;
9a799d71 5013
3a581073 5014 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
b6ec895e 5015 rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
1a6c14a2
JB		 5016 if (!rx_ring->rx_buffer_info)
5017 rx_ring->rx_buffer_info = vmalloc(size);
b6ec895e
AD		 5018 if (!rx_ring->rx_buffer_info)
5019 goto err;
3a581073 5020 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5021
9a799d71 5022 /* Round up to nearest 4K */
3a581073
JB		 5023 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5024 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5025
b6ec895e 5026 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5027 &rx_ring->dma, GFP_KERNEL);
9a799d71 5028
b6ec895e
AD		 5029 if (!rx_ring->desc)
5030 goto err;
9a799d71 5031
3a581073
JB		 5032 rx_ring->next_to_clean = 0;
5033 rx_ring->next_to_use = 0;
9a799d71
AK		 5034
5035 return 0;
b6ec895e
AD		 5036err:
5037 vfree(rx_ring->rx_buffer_info);
5038 rx_ring->rx_buffer_info = NULL;
5039 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5040 return -ENOMEM;
9a799d71
AK		 5041}
5042
69888674
AD		 5043/**
5044 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5045 * @adapter: board private structure
5046 *
5047 * If this function returns with an error, then it's possible one or
5048 * more of the rings is populated (while the rest are not). It is the
5049 * callers duty to clean those orphaned rings.
5050 *
5051 * Return 0 on success, negative on failure
5052 **/
69888674
AD		 5053static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5054{
5055 int i, err = 0;
5056
5057 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5058 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5059 if (!err)
5060 continue;
396e799c 5061 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5062 break;
5063 }
5064
5065 return err;
5066}
5067
9a799d71
AK		 5068/**
5069 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5070 * @tx_ring: Tx descriptor ring for a specific queue
5071 *
5072 * Free all transmit software resources
5073 **/
b6ec895e 5074void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5075{
b6ec895e 5076 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5077
5078 vfree(tx_ring->tx_buffer_info);
5079 tx_ring->tx_buffer_info = NULL;
5080
b6ec895e
AD		 5081 /* if not set, then don't free */
5082 if (!tx_ring->desc)
5083 return;
5084
5085 dma_free_coherent(tx_ring->dev, tx_ring->size,
5086 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5087
5088 tx_ring->desc = NULL;
5089}
5090
5091/**
5092 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5093 * @adapter: board private structure
5094 *
5095 * Free all transmit software resources
5096 **/
5097static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5098{
5099 int i;
5100
5101 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5102 if (adapter->tx_ring[i]->desc)
b6ec895e 5103 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5104}
5105
5106/**
b4617240 5107 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5108 * @rx_ring: ring to clean the resources from
5109 *
5110 * Free all receive software resources
5111 **/
b6ec895e 5112void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5113{
b6ec895e 5114 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5115
5116 vfree(rx_ring->rx_buffer_info);
5117 rx_ring->rx_buffer_info = NULL;
5118
b6ec895e
AD		 5119 /* if not set, then don't free */
5120 if (!rx_ring->desc)
5121 return;
5122
5123 dma_free_coherent(rx_ring->dev, rx_ring->size,
5124 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5125
5126 rx_ring->desc = NULL;
5127}
5128
5129/**
5130 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5131 * @adapter: board private structure
5132 *
5133 * Free all receive software resources
5134 **/
5135static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5136{
5137 int i;
5138
5139 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5140 if (adapter->rx_ring[i]->desc)
b6ec895e 5141 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5142}
5143
9a799d71
AK		 5144/**
5145 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5146 * @netdev: network interface device structure
5147 * @new_mtu: new value for maximum frame size
5148 *
5149 * Returns 0 on success, negative on failure
5150 **/
5151static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5152{
5153 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5154 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5155 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5156
42c783c5
JB		 5157 /* MTU < 68 is an error and causes problems on some kernels */
5158 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5159 return -EINVAL;
5160
396e799c 5161 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5162 /* must set new MTU before calling down or up */
9a799d71
AK		 5163 netdev->mtu = new_mtu;
5164
16b61beb
JF		 5165 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5166 hw->fc.low_water = FC_LOW_WATER(max_frame);
5167
d4f80882
AV		 5168 if (netif_running(netdev))
5169 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5170
5171 return 0;
5172}
5173
5174/**
5175 * ixgbe_open - Called when a network interface is made active
5176 * @netdev: network interface device structure
5177 *
5178 * Returns 0 on success, negative value on failure
5179 *
5180 * The open entry point is called when a network interface is made
5181 * active by the system (IFF_UP). At this point all resources needed
5182 * for transmit and receive operations are allocated, the interrupt
5183 * handler is registered with the OS, the watchdog timer is started,
5184 * and the stack is notified that the interface is ready.
5185 **/
5186static int ixgbe_open(struct net_device *netdev)
5187{
5188 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5189 int err;
4bebfaa5
AK		 5190
5191 /* disallow open during test */
5192 if (test_bit(__IXGBE_TESTING, &adapter->state))
5193 return -EBUSY;
9a799d71 5194
54386467
JB		 5195 netif_carrier_off(netdev);
5196
9a799d71
AK		 5197 /* allocate transmit descriptors */
5198 err = ixgbe_setup_all_tx_resources(adapter);
5199 if (err)
5200 goto err_setup_tx;
5201
9a799d71
AK		 5202 /* allocate receive descriptors */
5203 err = ixgbe_setup_all_rx_resources(adapter);
5204 if (err)
5205 goto err_setup_rx;
5206
5207 ixgbe_configure(adapter);
5208
021230d4 5209 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5210 if (err)
5211 goto err_req_irq;
5212
9a799d71
AK		 5213 err = ixgbe_up_complete(adapter);
5214 if (err)
5215 goto err_up;
5216
d55b53ff
JK		 5217 netif_tx_start_all_queues(netdev);
5218
9a799d71
AK		 5219 return 0;
5220
5221err_up:
5eba3699 5222 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5223 ixgbe_free_irq(adapter);
5224err_req_irq:
9a799d71 5225err_setup_rx:
a20a1199 5226 ixgbe_free_all_rx_resources(adapter);
9a799d71 5227err_setup_tx:
a20a1199 5228 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5229 ixgbe_reset(adapter);
5230
5231 return err;
5232}
5233
5234/**
5235 * ixgbe_close - Disables a network interface
5236 * @netdev: network interface device structure
5237 *
5238 * Returns 0, this is not allowed to fail
5239 *
5240 * The close entry point is called when an interface is de-activated
5241 * by the OS. The hardware is still under the drivers control, but
5242 * needs to be disabled. A global MAC reset is issued to stop the
5243 * hardware, and all transmit and receive resources are freed.
5244 **/
5245static int ixgbe_close(struct net_device *netdev)
5246{
5247 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5248
5249 ixgbe_down(adapter);
5250 ixgbe_free_irq(adapter);
5251
5252 ixgbe_free_all_tx_resources(adapter);
5253 ixgbe_free_all_rx_resources(adapter);
5254
5eba3699 5255 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5256
5257 return 0;
5258}
5259
b3c8b4ba
AD		 5260#ifdef CONFIG_PM
5261static int ixgbe_resume(struct pci_dev *pdev)
5262{
5263 struct net_device *netdev = pci_get_drvdata(pdev);
5264 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5265 u32 err;
5266
5267 pci_set_power_state(pdev, PCI_D0);
5268 pci_restore_state(pdev);
656ab817
DS		 5269 /*
5270 * pci_restore_state clears dev->state_saved so call
5271 * pci_save_state to restore it.
5272 */
5273 pci_save_state(pdev);
9ce77666 5274
5275 err = pci_enable_device_mem(pdev);
b3c8b4ba 5276 if (err) {
849c4542 5277 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5278 return err;
5279 }
5280 pci_set_master(pdev);
5281
dd4d8ca6 5282 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5283
5284 err = ixgbe_init_interrupt_scheme(adapter);
5285 if (err) {
849c4542 5286 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5287 return err;
5288 }
5289
b3c8b4ba
AD		 5290 ixgbe_reset(adapter);
5291
495dce12
WJP		 5292 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5293
b3c8b4ba
AD		 5294 if (netif_running(netdev)) {
5295 err = ixgbe_open(adapter->netdev);
5296 if (err)
5297 return err;
5298 }
5299
5300 netif_device_attach(netdev);
5301
5302 return 0;
5303}
b3c8b4ba 5304#endif /* CONFIG_PM */
9d8d05ae
RW		 5305
5306static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5307{
5308 struct net_device *netdev = pci_get_drvdata(pdev);
5309 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5310 struct ixgbe_hw *hw = &adapter->hw;
5311 u32 ctrl, fctrl;
5312 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5313#ifdef CONFIG_PM
5314 int retval = 0;
5315#endif
5316
5317 netif_device_detach(netdev);
5318
5319 if (netif_running(netdev)) {
5320 ixgbe_down(adapter);
5321 ixgbe_free_irq(adapter);
5322 ixgbe_free_all_tx_resources(adapter);
5323 ixgbe_free_all_rx_resources(adapter);
5324 }
b3c8b4ba
AD		 5325
5326#ifdef CONFIG_PM
5327 retval = pci_save_state(pdev);
5328 if (retval)
5329 return retval;
4df10466 5330
b3c8b4ba 5331#endif
e8e26350
PW		 5332 if (wufc) {
5333 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5334
e8e26350
PW		 5335 /* turn on all-multi mode if wake on multicast is enabled */
5336 if (wufc & IXGBE_WUFC_MC) {
5337 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5338 fctrl |= IXGBE_FCTRL_MPE;
5339 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5340 }
5341
5342 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5343 ctrl |= IXGBE_CTRL_GIO_DIS;
5344 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5345
5346 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5347 } else {
5348 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5349 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5350 }
5351
dd4d8ca6
DS		 5352 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5353 pci_wake_from_d3(pdev, true);
5354 else
5355 pci_wake_from_d3(pdev, false);
b3c8b4ba 5356
9d8d05ae
RW		 5357 *enable_wake = !!wufc;
5358
fa378134
AG		 5359 ixgbe_clear_interrupt_scheme(adapter);
5360
b3c8b4ba
AD		 5361 ixgbe_release_hw_control(adapter);
5362
5363 pci_disable_device(pdev);
5364
9d8d05ae
RW		 5365 return 0;
5366}
5367
5368#ifdef CONFIG_PM
5369static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5370{
5371 int retval;
5372 bool wake;
5373
5374 retval = __ixgbe_shutdown(pdev, &wake);
5375 if (retval)
5376 return retval;
5377
5378 if (wake) {
5379 pci_prepare_to_sleep(pdev);
5380 } else {
5381 pci_wake_from_d3(pdev, false);
5382 pci_set_power_state(pdev, PCI_D3hot);
5383 }
b3c8b4ba
AD		 5384
5385 return 0;
5386}
9d8d05ae 5387#endif /* CONFIG_PM */
b3c8b4ba
AD		 5388
5389static void ixgbe_shutdown(struct pci_dev *pdev)
5390{
9d8d05ae
RW		 5391 bool wake;
5392
5393 __ixgbe_shutdown(pdev, &wake);
5394
5395 if (system_state == SYSTEM_POWER_OFF) {
5396 pci_wake_from_d3(pdev, wake);
5397 pci_set_power_state(pdev, PCI_D3hot);
5398 }
b3c8b4ba
AD		 5399}
5400
9a799d71
AK		 5401/**
5402 * ixgbe_update_stats - Update the board statistics counters.
5403 * @adapter: board private structure
5404 **/
5405void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5406{
2d86f139 5407 struct net_device *netdev = adapter->netdev;
9a799d71 5408 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5409 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5410 u64 total_mpc = 0;
5411 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5412 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5413 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5414 u64 bytes = 0, packets = 0;
9a799d71 5415
d08935c2
DS		 5416 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5417 test_bit(__IXGBE_RESETTING, &adapter->state))
5418 return;
5419
94b982b2 5420 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5421 u64 rsc_count = 0;
94b982b2 5422 u64 rsc_flush = 0;
d51019a4
PW		 5423 for (i = 0; i < 16; i++)
5424 adapter->hw_rx_no_dma_resources +=
7ca647bd 5425 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5426 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5427 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5428 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5429 }
5430 adapter->rsc_total_count = rsc_count;
5431 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5432 }
5433
5b7da515
AD		 5434 for (i = 0; i < adapter->num_rx_queues; i++) {
5435 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5436 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5437 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5438 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5439 bytes += rx_ring->stats.bytes;
5440 packets += rx_ring->stats.packets;
5441 }
5442 adapter->non_eop_descs = non_eop_descs;
5443 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5444 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5445 netdev->stats.rx_bytes = bytes;
5446 netdev->stats.rx_packets = packets;
5447
5448 bytes = 0;
5449 packets = 0;
7ca3bc58 5450 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5451 for (i = 0; i < adapter->num_tx_queues; i++) {
5452 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5453 restart_queue += tx_ring->tx_stats.restart_queue;
5454 tx_busy += tx_ring->tx_stats.tx_busy;
5455 bytes += tx_ring->stats.bytes;
5456 packets += tx_ring->stats.packets;
5457 }
eb985f09 5458 adapter->restart_queue = restart_queue;
5b7da515
AD		 5459 adapter->tx_busy = tx_busy;
5460 netdev->stats.tx_bytes = bytes;
5461 netdev->stats.tx_packets = packets;
7ca3bc58 5462
7ca647bd 5463 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5464 for (i = 0; i < 8; i++) {
5465 /* for packet buffers not used, the register should read 0 */
5466 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5467 missed_rx += mpc;
7ca647bd
JP		 5468 hwstats->mpc[i] += mpc;
5469 total_mpc += hwstats->mpc[i];
e8e26350 5470 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5471 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5472 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5473 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5474 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5475 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350 5476 if (hw->mac.type == ixgbe_mac_82599EB) {
7ca647bd
JP		 5477 hwstats->pxonrxc[i] +=
5478 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5479 hwstats->pxoffrxc[i] +=
5480 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5481 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350 5482 } else {
7ca647bd
JP		 5483 hwstats->pxonrxc[i] +=
5484 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5485 hwstats->pxoffrxc[i] +=
5486 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
e8e26350 5487 }
7ca647bd
JP		 5488 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5489 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5490 }
7ca647bd 5491 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5492 /* work around hardware counting issue */
7ca647bd 5493 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5494
5495 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5496 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5497 u64 tmp;
7ca647bd 5498 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5499 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5500 /* 4 high bits of GORC */
7ca647bd
JP		 5501 hwstats->gorc += (tmp << 32);
5502 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5503 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5504 /* 4 high bits of GOTC */
7ca647bd
JP		 5505 hwstats->gotc += (tmp << 32);
5506 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5507 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5508 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5509 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5510 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5511 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5512#ifdef IXGBE_FCOE
7ca647bd
JP		 5513 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5514 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5515 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5516 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5517 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5518 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5519#endif /* IXGBE_FCOE */
e8e26350 5520 } else {
7ca647bd
JP		 5521 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5522 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5523 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5524 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5525 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
e8e26350 5526 }
9a799d71 5527 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5528 hwstats->bprc += bprc;
5529 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5530 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5531 hwstats->mprc -= bprc;
5532 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5533 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5534 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5535 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5536 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5537 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5538 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5539 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5540 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5541 hwstats->lxontxc += lxon;
6f11eef7 5542 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5543 hwstats->lxofftxc += lxoff;
5544 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5545 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5546 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5547 /*
5548 * 82598 errata - tx of flow control packets is included in tx counters
5549 */
5550 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5551 hwstats->gptc -= xon_off_tot;
5552 hwstats->mptc -= xon_off_tot;
5553 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5554 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5555 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5556 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5557 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5558 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5559 hwstats->ptc64 -= xon_off_tot;
5560 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5561 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5562 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5563 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5564 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5565 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5566
5567 /* Fill out the OS statistics structure */
7ca647bd 5568 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5569
5570 /* Rx Errors */
7ca647bd 5571 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5572 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5573 netdev->stats.rx_length_errors = hwstats->rlec;
5574 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5575 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5576}
5577
5578/**
5579 * ixgbe_watchdog - Timer Call-back
5580 * @data: pointer to adapter cast into an unsigned long
5581 **/
5582static void ixgbe_watchdog(unsigned long data)
5583{
5584 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5585 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5586 u64 eics = 0;
5587 int i;
cf8280ee 5588
fe49f04a
AD		 5589 /*
5590 * Do the watchdog outside of interrupt context due to the lovely
5591 * delays that some of the newer hardware requires
5592 */
22d5a71b 5593
fe49f04a
AD		 5594 if (test_bit(__IXGBE_DOWN, &adapter->state))
5595 goto watchdog_short_circuit;
22d5a71b 5596
fe49f04a
AD		 5597 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5598 /*
5599 * for legacy and MSI interrupts don't set any bits
5600 * that are enabled for EIAM, because this operation
5601 * would set *both* EIMS and EICS for any bit in EIAM
5602 */
5603 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5604 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5605 goto watchdog_reschedule;
5606 }
5607
5608 /* get one bit for every active tx/rx interrupt vector */
5609 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5610 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5611 if (qv->rxr_count || qv->txr_count)
5612 eics |= ((u64)1 << i);
cf8280ee 5613 }
9a799d71 5614
fe49f04a
AD		 5615 /* Cause software interrupt to ensure rx rings are cleaned */
5616 ixgbe_irq_rearm_queues(adapter, eics);
5617
5618watchdog_reschedule:
5619 /* Reset the timer */
5620 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5621
5622watchdog_short_circuit:
cf8280ee
JB		 5623 schedule_work(&adapter->watchdog_task);
5624}
5625
e8e26350
PW		 5626/**
5627 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5628 * @work: pointer to work_struct containing our data
5629 **/
5630static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5631{
5632 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5633 struct ixgbe_adapter,
5634 multispeed_fiber_task);
e8e26350
PW		 5635 struct ixgbe_hw *hw = &adapter->hw;
5636 u32 autoneg;
8620a103 5637 bool negotiation;
e8e26350
PW		 5638
5639 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5640 autoneg = hw->phy.autoneg_advertised;
5641 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5642 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5643 hw->mac.autotry_restart = false;
8620a103
MC		 5644 if (hw->mac.ops.setup_link)
5645 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5646 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5647 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5648}
5649
5650/**
5651 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5652 * @work: pointer to work_struct containing our data
5653 **/
5654static void ixgbe_sfp_config_module_task(struct work_struct *work)
5655{
5656 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5657 struct ixgbe_adapter,
5658 sfp_config_module_task);
e8e26350
PW		 5659 struct ixgbe_hw *hw = &adapter->hw;
5660 u32 err;
5661
5662 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5663
5664 /* Time for electrical oscillations to settle down */
5665 msleep(100);
e8e26350 5666 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5667
e8e26350 5668 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5669 e_dev_err("failed to initialize because an unsupported SFP+ "
5670 "module type was detected.\n");
5671 e_dev_err("Reload the driver after installing a supported "
5672 "module.\n");
63d6e1d8 5673 unregister_netdev(adapter->netdev);
e8e26350
PW		 5674 return;
5675 }
5676 hw->mac.ops.setup_sfp(hw);
5677
8d1c3c07 5678 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5679 /* This will also work for DA Twinax connections */
5680 schedule_work(&adapter->multispeed_fiber_task);
5681 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5682}
5683
c4cf55e5
PWJ		 5684/**
5685 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5686 * @work: pointer to work_struct containing our data
5687 **/
5688static void ixgbe_fdir_reinit_task(struct work_struct *work)
5689{
5690 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5691 struct ixgbe_adapter,
5692 fdir_reinit_task);
c4cf55e5
PWJ		 5693 struct ixgbe_hw *hw = &adapter->hw;
5694 int i;
5695
5696 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5697 for (i = 0; i < adapter->num_tx_queues; i++)
5698 set_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 5699 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5700 } else {
396e799c 5701 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5702 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5703 }
5704 /* Done FDIR Re-initialization, enable transmits */
5705 netif_tx_start_all_queues(adapter->netdev);
5706}
5707
10eec955
JF		 5708static DEFINE_MUTEX(ixgbe_watchdog_lock);
5709
cf8280ee 5710/**
69888674
AD		 5711 * ixgbe_watchdog_task - worker thread to bring link up
5712 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5713 **/
5714static void ixgbe_watchdog_task(struct work_struct *work)
5715{
5716 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5717 struct ixgbe_adapter,
5718 watchdog_task);
cf8280ee
JB		 5719 struct net_device *netdev = adapter->netdev;
5720 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5721 u32 link_speed;
5722 bool link_up;
bc59fcda
NS		 5723 int i;
5724 struct ixgbe_ring *tx_ring;
5725 int some_tx_pending = 0;
cf8280ee 5726
10eec955
JF		 5727 mutex_lock(&ixgbe_watchdog_lock);
5728
5729 link_up = adapter->link_up;
5730 link_speed = adapter->link_speed;
cf8280ee
JB		 5731
5732 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5733 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5734 if (link_up) {
5735#ifdef CONFIG_DCB
5736 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5737 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5738 hw->mac.ops.fc_enable(hw, i);
264857b8 5739 } else {
620fa036 5740 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5741 }
5742#else
620fa036 5743 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5744#endif
5745 }
5746
cf8280ee
JB		 5747 if (link_up ||
5748 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5749 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5750 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5751 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5752 }
5753 adapter->link_up = link_up;
5754 adapter->link_speed = link_speed;
5755 }
9a799d71
AK		 5756
5757 if (link_up) {
5758 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5759 bool flow_rx, flow_tx;
5760
5761 if (hw->mac.type == ixgbe_mac_82599EB) {
5762 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5763 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5764 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5765 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5766 } else {
5767 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5768 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5769 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5770 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5771 }
5772
396e799c 5773 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5774 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5775 "10 Gbps" :
5776 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5777 "1 Gbps" : "unknown speed")),
e8e26350 5778 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5779 (flow_rx ? "RX" :
5780 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5781
5782 netif_carrier_on(netdev);
9a799d71
AK		 5783 } else {
5784 /* Force detection of hung controller */
5785 adapter->detect_tx_hung = true;
5786 }
5787 } else {
cf8280ee
JB		 5788 adapter->link_up = false;
5789 adapter->link_speed = 0;
9a799d71 5790 if (netif_carrier_ok(netdev)) {
396e799c 5791 e_info(drv, "NIC Link is Down\n");
9a799d71 5792 netif_carrier_off(netdev);
9a799d71
AK		 5793 }
5794 }
5795
bc59fcda
NS		 5796 if (!netif_carrier_ok(netdev)) {
5797 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5798 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5799 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5800 some_tx_pending = 1;
5801 break;
5802 }
5803 }
5804
5805 if (some_tx_pending) {
5806 /* We've lost link, so the controller stops DMA,
5807 * but we've got queued Tx work that's never going
5808 * to get done, so reset controller to flush Tx.
5809 * (Do the reset outside of interrupt context).
5810 */
5811 schedule_work(&adapter->reset_task);
5812 }
5813 }
5814
9a799d71 5815 ixgbe_update_stats(adapter);
10eec955 5816 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5817}
5818
9a799d71 5819static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 5820 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 5821 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 5822{
5823 struct ixgbe_adv_tx_context_desc *context_desc;
5824 unsigned int i;
5825 int err;
5826 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5827 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5828 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5829
5830 if (skb_is_gso(skb)) {
5831 if (skb_header_cloned(skb)) {
5832 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5833 if (err)
5834 return err;
5835 }
5836 l4len = tcp_hdrlen(skb);
5837 *hdr_len += l4len;
5838
5e09a105 5839 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5840 struct iphdr *iph = ip_hdr(skb);
5841 iph->tot_len = 0;
5842 iph->check = 0;
5843 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5844 iph->daddr, 0,
5845 IPPROTO_TCP,
5846 0);
8e1e8a47 5847 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5848 ipv6_hdr(skb)->payload_len = 0;
5849 tcp_hdr(skb)->check =
5850 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5851 &ipv6_hdr(skb)->daddr,
5852 0, IPPROTO_TCP, 0);
9a799d71
AK		 5853 }
5854
5855 i = tx_ring->next_to_use;
5856
5857 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5858 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5859
5860 /* VLAN MACLEN IPLEN */
5861 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5862 vlan_macip_lens |=
5863 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5864 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5865 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5866 *hdr_len += skb_network_offset(skb);
5867 vlan_macip_lens |=
5868 (skb_transport_header(skb) - skb_network_header(skb));
5869 *hdr_len +=
5870 (skb_transport_header(skb) - skb_network_header(skb));
5871 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5872 context_desc->seqnum_seed = 0;
5873
5874 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5875 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5876 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5877
5e09a105 5878 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 5879 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5880 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5881 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5882
5883 /* MSS L4LEN IDX */
9f8cdf4f 5884 mss_l4len_idx =
9a799d71
AK		 5885 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5886 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5887 /* use index 1 for TSO */
5888 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5889 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5890
5891 tx_buffer_info->time_stamp = jiffies;
5892 tx_buffer_info->next_to_watch = i;
5893
5894 i++;
5895 if (i == tx_ring->count)
5896 i = 0;
5897 tx_ring->next_to_use = i;
5898
5899 return true;
5900 }
5901 return false;
5902}
5903
5e09a105
HZ		 5904static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5905 __be16 protocol)
7ca647bd
JP		 5906{
5907 u32 rtn = 0;
7ca647bd
JP		 5908
5909 switch (protocol) {
5910 case cpu_to_be16(ETH_P_IP):
5911 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5912 switch (ip_hdr(skb)->protocol) {
5913 case IPPROTO_TCP:
5914 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5915 break;
5916 case IPPROTO_SCTP:
5917 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5918 break;
5919 }
5920 break;
5921 case cpu_to_be16(ETH_P_IPV6):
5922 /* XXX what about other V6 headers?? */
5923 switch (ipv6_hdr(skb)->nexthdr) {
5924 case IPPROTO_TCP:
5925 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5926 break;
5927 case IPPROTO_SCTP:
5928 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5929 break;
5930 }
5931 break;
5932 default:
5933 if (unlikely(net_ratelimit()))
5934 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 5935 protocol);
7ca647bd
JP		 5936 break;
5937 }
5938
5939 return rtn;
5940}
5941
9a799d71 5942static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 5943 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 5944 struct sk_buff *skb, u32 tx_flags,
5945 __be16 protocol)
9a799d71
AK		 5946{
5947 struct ixgbe_adv_tx_context_desc *context_desc;
5948 unsigned int i;
5949 struct ixgbe_tx_buffer *tx_buffer_info;
5950 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5951
5952 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5953 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5954 i = tx_ring->next_to_use;
5955 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5956 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5957
5958 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5959 vlan_macip_lens |=
5960 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5961 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 5962 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5963 if (skb->ip_summed == CHECKSUM_PARTIAL)
5964 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 5965 skb_network_header(skb));
9a799d71
AK		 5966
5967 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5968 context_desc->seqnum_seed = 0;
5969
5970 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 5971 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5972
7ca647bd 5973 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 5974 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 5975
5976 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5977 /* use index zero for tx checksum offload */
9a799d71
AK		 5978 context_desc->mss_l4len_idx = 0;
5979
5980 tx_buffer_info->time_stamp = jiffies;
5981 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5982
9a799d71
AK		 5983 i++;
5984 if (i == tx_ring->count)
5985 i = 0;
5986 tx_ring->next_to_use = i;
5987
5988 return true;
5989 }
9f8cdf4f 5990
9a799d71
AK		 5991 return false;
5992}
5993
5994static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5995 struct ixgbe_ring *tx_ring,
5996 struct sk_buff *skb, u32 tx_flags,
8ad494b0 5997 unsigned int first, const u8 hdr_len)
9a799d71 5998{
b6ec895e 5999 struct device *dev = tx_ring->dev;
9a799d71 6000 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6001 unsigned int len;
6002 unsigned int total = skb->len;
9a799d71
AK		 6003 unsigned int offset = 0, size, count = 0, i;
6004 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6005 unsigned int f;
8ad494b0
AD		 6006 unsigned int bytecount = skb->len;
6007 u16 gso_segs = 1;
9a799d71
AK		 6008
6009 i = tx_ring->next_to_use;
6010
eacd73f7
YZ		 6011 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6012 /* excluding fcoe_crc_eof for FCoE */
6013 total -= sizeof(struct fcoe_crc_eof);
6014
6015 len = min(skb_headlen(skb), total);
9a799d71
AK		 6016 while (len) {
6017 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6018 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6019
6020 tx_buffer_info->length = size;
e5a43549 6021 tx_buffer_info->mapped_as_page = false;
b6ec895e 6022 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6023 skb->data + offset,
1b507730 6024 size, DMA_TO_DEVICE);
b6ec895e 6025 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6026 goto dma_error;
9a799d71
AK		 6027 tx_buffer_info->time_stamp = jiffies;
6028 tx_buffer_info->next_to_watch = i;
6029
6030 len -= size;
eacd73f7 6031 total -= size;
9a799d71
AK		 6032 offset += size;
6033 count++;
44df32c5
AD		 6034
6035 if (len) {
6036 i++;
6037 if (i == tx_ring->count)
6038 i = 0;
6039 }
9a799d71
AK		 6040 }
6041
6042 for (f = 0; f < nr_frags; f++) {
6043 struct skb_frag_struct *frag;
6044
6045 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6046 len = min((unsigned int)frag->size, total);
e5a43549 6047 offset = frag->page_offset;
9a799d71
AK		 6048
6049 while (len) {
44df32c5
AD		 6050 i++;
6051 if (i == tx_ring->count)
6052 i = 0;
6053
9a799d71
AK		 6054 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6055 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6056
6057 tx_buffer_info->length = size;
b6ec895e 6058 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6059 frag->page,
6060 offset, size,
1b507730 6061 DMA_TO_DEVICE);
e5a43549 6062 tx_buffer_info->mapped_as_page = true;
b6ec895e 6063 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6064 goto dma_error;
9a799d71
AK		 6065 tx_buffer_info->time_stamp = jiffies;
6066 tx_buffer_info->next_to_watch = i;
6067
6068 len -= size;
eacd73f7 6069 total -= size;
9a799d71
AK		 6070 offset += size;
6071 count++;
9a799d71 6072 }
eacd73f7
YZ		 6073 if (total == 0)
6074 break;
9a799d71 6075 }
44df32c5 6076
8ad494b0
AD		 6077 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6078 gso_segs = skb_shinfo(skb)->gso_segs;
6079#ifdef IXGBE_FCOE
6080 /* adjust for FCoE Sequence Offload */
6081 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6082 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6083 skb_shinfo(skb)->gso_size);
6084#endif /* IXGBE_FCOE */
6085 bytecount += (gso_segs - 1) * hdr_len;
6086
6087 /* multiply data chunks by size of headers */
6088 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6089 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6090 tx_ring->tx_buffer_info[i].skb = skb;
6091 tx_ring->tx_buffer_info[first].next_to_watch = i;
6092
e5a43549
AD		 6093 return count;
6094
6095dma_error:
849c4542 6096 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6097
6098 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6099 tx_buffer_info->dma = 0;
6100 tx_buffer_info->time_stamp = 0;
6101 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6102 if (count)
6103 count--;
e5a43549
AD		 6104
6105 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6106 while (count--) {
e8e9f696 6107 if (i == 0)
e5a43549 6108 i += tx_ring->count;
c1fa347f 6109 i--;
e5a43549 6110 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6111 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6112 }
6113
e44d38e1 6114 return 0;
9a799d71
AK		 6115}
6116
84ea2591 6117static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6118 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6119{
6120 union ixgbe_adv_tx_desc *tx_desc = NULL;
6121 struct ixgbe_tx_buffer *tx_buffer_info;
6122 u32 olinfo_status = 0, cmd_type_len = 0;
6123 unsigned int i;
6124 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6125
6126 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6127
6128 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6129
6130 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6131 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6132
6133 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6134 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6135
6136 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6137 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6138
4eeae6fd
PW		 6139 /* use index 1 context for tso */
6140 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6141 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6142 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6143 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6144
6145 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6146 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6147 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6148
eacd73f7
YZ		 6149 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6150 olinfo_status |= IXGBE_ADVTXD_CC;
6151 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6152 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6153 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6154 }
6155
9a799d71
AK		 6156 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6157
6158 i = tx_ring->next_to_use;
6159 while (count--) {
6160 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6161 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6162 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6163 tx_desc->read.cmd_type_len =
e8e9f696 6164 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6165 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6166 i++;
6167 if (i == tx_ring->count)
6168 i = 0;
6169 }
6170
6171 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6172
6173 /*
6174 * Force memory writes to complete before letting h/w
6175 * know there are new descriptors to fetch. (Only
6176 * applicable for weak-ordered memory model archs,
6177 * such as IA-64).
6178 */
6179 wmb();
6180
6181 tx_ring->next_to_use = i;
84ea2591 6182 writel(i, tx_ring->tail);
9a799d71
AK		 6183}
6184
c4cf55e5 6185static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5e09a105 6186 int queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6187{
c4cf55e5
PWJ		 6188 struct ixgbe_atr_input atr_input;
6189 struct tcphdr *th;
c4cf55e5
PWJ		 6190 struct iphdr *iph = ip_hdr(skb);
6191 struct ethhdr *eth = (struct ethhdr *)skb->data;
6192 u16 vlan_id, src_port, dst_port, flex_bytes;
6193 u32 src_ipv4_addr, dst_ipv4_addr;
6194 u8 l4type = 0;
6195
d3ead241 6196 /* Right now, we support IPv4 only */
5e09a105 6197 if (protocol != htons(ETH_P_IP))
d3ead241 6198 return;
c4cf55e5
PWJ		 6199 /* check if we're UDP or TCP */
6200 if (iph->protocol == IPPROTO_TCP) {
6201 th = tcp_hdr(skb);
6202 src_port = th->source;
6203 dst_port = th->dest;
6204 l4type |= IXGBE_ATR_L4TYPE_TCP;
6205 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6206 } else {
6207 /* Unsupported L4 header, just bail here */
6208 return;
6209 }
6210
6211 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6212
6213 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6214 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6215 src_ipv4_addr = iph->saddr;
6216 dst_ipv4_addr = iph->daddr;
6217 flex_bytes = eth->h_proto;
6218
6219 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6220 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6221 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6222 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6223 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6224 /* src and dst are inverted, think how the receiver sees them */
6225 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6226 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6227
6228 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6229 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6230}
6231
e092be60 6232static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6233 struct ixgbe_ring *tx_ring, int size)
e092be60 6234{
30eba97a 6235 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6236 /* Herbert's original patch had:
6237 * smp_mb__after_netif_stop_queue();
6238 * but since that doesn't exist yet, just open code it. */
6239 smp_mb();
6240
6241 /* We need to check again in a case another CPU has just
6242 * made room available. */
6243 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6244 return -EBUSY;
6245
6246 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6247 netif_start_subqueue(netdev, tx_ring->queue_index);
5b7da515 6248 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6249 return 0;
6250}
6251
6252static int ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6253 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6254{
6255 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6256 return 0;
6257 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6258}
6259
09a3b1f8
SH		 6260static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6261{
6262 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6263 int txq = smp_processor_id();
56075a98 6264#ifdef IXGBE_FCOE
5e09a105
HZ		 6265 __be16 protocol;
6266
6267 protocol = vlan_get_protocol(skb);
6268
6269 if ((protocol == htons(ETH_P_FCOE)) ||
6270 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6271 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6272 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6273 txq += adapter->ring_feature[RING_F_FCOE].mask;
6274 return txq;
4bc091d8 6275#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6276 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6277 txq = adapter->fcoe.up;
6278 return txq;
4bc091d8 6279#endif
56075a98
JF		 6280 }
6281 }
6282#endif
6283
fdd3d631
KK		 6284 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6285 while (unlikely(txq >= dev->real_num_tx_queues))
6286 txq -= dev->real_num_tx_queues;
5f715823 6287 return txq;
fdd3d631 6288 }
c4cf55e5 6289
2ea186ae
JF		 6290 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6291 if (skb->priority == TC_PRIO_CONTROL)
6292 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6293 else
6294 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6295 >> 13;
6296 return txq;
6297 }
09a3b1f8
SH		 6298
6299 return skb_tx_hash(dev, skb);
6300}
6301
84418e3b
AD		 6302netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6303 struct ixgbe_adapter *adapter,
6304 struct ixgbe_ring *tx_ring)
9a799d71 6305{
60d51134 6306 struct netdev_queue *txq;
9a799d71
AK		 6307 unsigned int first;
6308 unsigned int tx_flags = 0;
30eba97a 6309 u8 hdr_len = 0;
5f715823 6310 int tso;
9a799d71
AK		 6311 int count = 0;
6312 unsigned int f;
5e09a105
HZ		 6313 __be16 protocol;
6314
6315 protocol = vlan_get_protocol(skb);
9f8cdf4f 6316
eab6d18d 6317 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6318 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6319 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6320 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6321 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6322 }
6323 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6324 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6325 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6326 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6327 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6328 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6329 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6330 }
eacd73f7 6331
09ad1cc0 6332#ifdef IXGBE_FCOE
56075a98
JF		 6333 /* for FCoE with DCB, we force the priority to what
6334 * was specified by the switch */
6335 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6336 (protocol == htons(ETH_P_FCOE) ||
6337 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6338#ifdef CONFIG_IXGBE_DCB
6339 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6340 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6341 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6342 tx_flags |= ((adapter->fcoe.up << 13)
6343 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6344 }
6345#endif
ca77cd59 6346 /* flag for FCoE offloads */
5e09a105 6347 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6348 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6349 }
ca77cd59
RL		 6350#endif
6351
eacd73f7 6352 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6353 if (skb_is_gso(skb) ||
6354 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6355 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6356 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6357 count++;
6358
9f8cdf4f
JB		 6359 count += TXD_USE_COUNT(skb_headlen(skb));
6360 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6361 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6362
e092be60 6363 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5b7da515 6364 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6365 return NETDEV_TX_BUSY;
6366 }
9a799d71 6367
9a799d71 6368 first = tx_ring->next_to_use;
eacd73f7
YZ		 6369 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6370#ifdef IXGBE_FCOE
6371 /* setup tx offload for FCoE */
6372 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6373 if (tso < 0) {
6374 dev_kfree_skb_any(skb);
6375 return NETDEV_TX_OK;
6376 }
6377 if (tso)
6378 tx_flags |= IXGBE_TX_FLAGS_FSO;
6379#endif /* IXGBE_FCOE */
6380 } else {
5e09a105 6381 if (protocol == htons(ETH_P_IP))
eacd73f7 6382 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6383 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6384 protocol);
eacd73f7
YZ		 6385 if (tso < 0) {
6386 dev_kfree_skb_any(skb);
6387 return NETDEV_TX_OK;
6388 }
9a799d71 6389
eacd73f7
YZ		 6390 if (tso)
6391 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6392 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6393 protocol) &&
eacd73f7
YZ		 6394 (skb->ip_summed == CHECKSUM_PARTIAL))
6395 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6396 }
9a799d71 6397
8ad494b0 6398 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6399 if (count) {
c4cf55e5
PWJ		 6400 /* add the ATR filter if ATR is on */
6401 if (tx_ring->atr_sample_rate) {
6402 ++tx_ring->atr_count;
6403 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
e8e9f696
JP		 6404 test_bit(__IXGBE_FDIR_INIT_DONE,
6405 &tx_ring->reinit_state)) {
c4cf55e5 6406 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6407 tx_flags, protocol);
c4cf55e5
PWJ		 6408 tx_ring->atr_count = 0;
6409 }
6410 }
60d51134
ED		 6411 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6412 txq->tx_bytes += skb->len;
6413 txq->tx_packets++;
84ea2591 6414 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
44df32c5 6415 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6416
44df32c5
AD		 6417 } else {
6418 dev_kfree_skb_any(skb);
6419 tx_ring->tx_buffer_info[first].time_stamp = 0;
6420 tx_ring->next_to_use = first;
6421 }
9a799d71
AK		 6422
6423 return NETDEV_TX_OK;
6424}
6425
84418e3b
AD		 6426static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6427{
6428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6429 struct ixgbe_ring *tx_ring;
6430
6431 tx_ring = adapter->tx_ring[skb->queue_mapping];
6432 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6433}
6434
9a799d71
AK		 6435/**
6436 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6437 * @netdev: network interface device structure
6438 * @p: pointer to an address structure
6439 *
6440 * Returns 0 on success, negative on failure
6441 **/
6442static int ixgbe_set_mac(struct net_device *netdev, void *p)
6443{
6444 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6445 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6446 struct sockaddr *addr = p;
6447
6448 if (!is_valid_ether_addr(addr->sa_data))
6449 return -EADDRNOTAVAIL;
6450
6451 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6452 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6453
1cdd1ec8
GR		 6454 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6455 IXGBE_RAH_AV);
9a799d71
AK		 6456
6457 return 0;
6458}
6459
6b73e10d
BH		 6460static int
6461ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6462{
6463 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6464 struct ixgbe_hw *hw = &adapter->hw;
6465 u16 value;
6466 int rc;
6467
6468 if (prtad != hw->phy.mdio.prtad)
6469 return -EINVAL;
6470 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6471 if (!rc)
6472 rc = value;
6473 return rc;
6474}
6475
6476static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6477 u16 addr, u16 value)
6478{
6479 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6480 struct ixgbe_hw *hw = &adapter->hw;
6481
6482 if (prtad != hw->phy.mdio.prtad)
6483 return -EINVAL;
6484 return hw->phy.ops.write_reg(hw, addr, devad, value);
6485}
6486
6487static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6488{
6489 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6490
6491 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6492}
6493
0365e6e4
PW		 6494/**
6495 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6496 * netdev->dev_addrs
0365e6e4
PW		 6497 * @netdev: network interface device structure
6498 *
6499 * Returns non-zero on failure
6500 **/
6501static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6502{
6503 int err = 0;
6504 struct ixgbe_adapter *adapter = netdev_priv(dev);
6505 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6506
6507 if (is_valid_ether_addr(mac->san_addr)) {
6508 rtnl_lock();
6509 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6510 rtnl_unlock();
6511 }
6512 return err;
6513}
6514
6515/**
6516 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6517 * netdev->dev_addrs
0365e6e4
PW		 6518 * @netdev: network interface device structure
6519 *
6520 * Returns non-zero on failure
6521 **/
6522static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6523{
6524 int err = 0;
6525 struct ixgbe_adapter *adapter = netdev_priv(dev);
6526 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6527
6528 if (is_valid_ether_addr(mac->san_addr)) {
6529 rtnl_lock();
6530 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6531 rtnl_unlock();
6532 }
6533 return err;
6534}
6535
9a799d71
AK		 6536#ifdef CONFIG_NET_POLL_CONTROLLER
6537/*
6538 * Polling 'interrupt' - used by things like netconsole to send skbs
6539 * without having to re-enable interrupts. It's not called while
6540 * the interrupt routine is executing.
6541 */
6542static void ixgbe_netpoll(struct net_device *netdev)
6543{
6544 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6545 int i;
9a799d71 6546
1a647bd2
AD		 6547 /* if interface is down do nothing */
6548 if (test_bit(__IXGBE_DOWN, &adapter->state))
6549 return;
6550
9a799d71 6551 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6552 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6553 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6554 for (i = 0; i < num_q_vectors; i++) {
6555 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6556 ixgbe_msix_clean_many(0, q_vector);
6557 }
6558 } else {
6559 ixgbe_intr(adapter->pdev->irq, netdev);
6560 }
9a799d71 6561 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6562}
6563#endif
6564
de1036b1
ED		 6565static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6566 struct rtnl_link_stats64 *stats)
6567{
6568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6569 int i;
6570
6571 /* accurate rx/tx bytes/packets stats */
6572 dev_txq_stats_fold(netdev, stats);
1a51502b 6573 rcu_read_lock();
de1036b1 6574 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6575 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6576 u64 bytes, packets;
6577 unsigned int start;
6578
1a51502b
ED		 6579 if (ring) {
6580 do {
6581 start = u64_stats_fetch_begin_bh(&ring->syncp);
6582 packets = ring->stats.packets;
6583 bytes = ring->stats.bytes;
6584 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6585 stats->rx_packets += packets;
6586 stats->rx_bytes += bytes;
6587 }
de1036b1 6588 }
1a51502b 6589 rcu_read_unlock();
de1036b1
ED		 6590 /* following stats updated by ixgbe_watchdog_task() */
6591 stats->multicast = netdev->stats.multicast;
6592 stats->rx_errors = netdev->stats.rx_errors;
6593 stats->rx_length_errors = netdev->stats.rx_length_errors;
6594 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6595 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6596 return stats;
6597}
6598
6599
0edc3527 6600static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6601 .ndo_open = ixgbe_open,
0edc3527 6602 .ndo_stop = ixgbe_close,
00829823 6603 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6604 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6605 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6606 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6607 .ndo_validate_addr = eth_validate_addr,
6608 .ndo_set_mac_address = ixgbe_set_mac,
6609 .ndo_change_mtu = ixgbe_change_mtu,
6610 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6611 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6612 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6613 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6614 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6615 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6616 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6617 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6618 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6619#ifdef CONFIG_NET_POLL_CONTROLLER
6620 .ndo_poll_controller = ixgbe_netpoll,
6621#endif
332d4a7d
YZ		 6622#ifdef IXGBE_FCOE
6623 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6624 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6625 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6626 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6627 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6628#endif /* IXGBE_FCOE */
0edc3527
SH		 6629};
6630
1cdd1ec8
GR		 6631static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6632 const struct ixgbe_info *ii)
6633{
6634#ifdef CONFIG_PCI_IOV
6635 struct ixgbe_hw *hw = &adapter->hw;
6636 int err;
6637
6638 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6639 return;
6640
6641 /* The 82599 supports up to 64 VFs per physical function
6642 * but this implementation limits allocation to 63 so that
6643 * basic networking resources are still available to the
6644 * physical function
6645 */
6646 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6647 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6648 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6649 if (err) {
396e799c 6650 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6651 goto err_novfs;
6652 }
6653 /* If call to enable VFs succeeded then allocate memory
6654 * for per VF control structures.
6655 */
6656 adapter->vfinfo =
6657 kcalloc(adapter->num_vfs,
6658 sizeof(struct vf_data_storage), GFP_KERNEL);
6659 if (adapter->vfinfo) {
6660 /* Now that we're sure SR-IOV is enabled
6661 * and memory allocated set up the mailbox parameters
6662 */
6663 ixgbe_init_mbx_params_pf(hw);
6664 memcpy(&hw->mbx.ops, ii->mbx_ops,
6665 sizeof(hw->mbx.ops));
6666
6667 /* Disable RSC when in SR-IOV mode */
6668 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6669 IXGBE_FLAG2_RSC_ENABLED);
6670 return;
6671 }
6672
6673 /* Oh oh */
396e799c
ET		 6674 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6675 "SRIOV disabled\n");
1cdd1ec8
GR		 6676 pci_disable_sriov(adapter->pdev);
6677
6678err_novfs:
6679 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6680 adapter->num_vfs = 0;
6681#endif /* CONFIG_PCI_IOV */
6682}
6683
9a799d71
AK		 6684/**
6685 * ixgbe_probe - Device Initialization Routine
6686 * @pdev: PCI device information struct
6687 * @ent: entry in ixgbe_pci_tbl
6688 *
6689 * Returns 0 on success, negative on failure
6690 *
6691 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6692 * The OS initialization, configuring of the adapter private structure,
6693 * and a hardware reset occur.
6694 **/
6695static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6696 const struct pci_device_id *ent)
9a799d71
AK		 6697{
6698 struct net_device *netdev;
6699 struct ixgbe_adapter *adapter = NULL;
6700 struct ixgbe_hw *hw;
6701 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6702 static int cards_found;
6703 int i, err, pci_using_dac;
c85a2618 6704 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6705#ifdef IXGBE_FCOE
6706 u16 device_caps;
6707#endif
c44ade9e 6708 u32 part_num, eec;
9a799d71 6709
bded64a7
AG		 6710 /* Catch broken hardware that put the wrong VF device ID in
6711 * the PCIe SR-IOV capability.
6712 */
6713 if (pdev->is_virtfn) {
6714 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6715 pci_name(pdev), pdev->vendor, pdev->device);
6716 return -EINVAL;
6717 }
6718
9ce77666 6719 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6720 if (err)
6721 return err;
6722
1b507730
NN		 6723 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6724 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6725 pci_using_dac = 1;
6726 } else {
1b507730 6727 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6728 if (err) {
1b507730
NN		 6729 err = dma_set_coherent_mask(&pdev->dev,
6730 DMA_BIT_MASK(32));
9a799d71 6731 if (err) {
b8bc0421
DC		 6732 dev_err(&pdev->dev,
6733 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6734 goto err_dma;
6735 }
6736 }
6737 pci_using_dac = 0;
6738 }
6739
9ce77666 6740 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6741 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6742 if (err) {
b8bc0421
DC		 6743 dev_err(&pdev->dev,
6744 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6745 goto err_pci_reg;
6746 }
6747
19d5afd4 6748 pci_enable_pcie_error_reporting(pdev);
6fabd715 6749
9a799d71 6750 pci_set_master(pdev);
fb3b27bc 6751 pci_save_state(pdev);
9a799d71 6752
c85a2618
JF		 6753 if (ii->mac == ixgbe_mac_82598EB)
6754 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6755 else
6756 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6757
6758 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6759#ifdef IXGBE_FCOE
6760 indices += min_t(unsigned int, num_possible_cpus(),
6761 IXGBE_MAX_FCOE_INDICES);
6762#endif
c85a2618 6763 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6764 if (!netdev) {
6765 err = -ENOMEM;
6766 goto err_alloc_etherdev;
6767 }
6768
9a799d71
AK		 6769 SET_NETDEV_DEV(netdev, &pdev->dev);
6770
6771 pci_set_drvdata(pdev, netdev);
6772 adapter = netdev_priv(netdev);
6773
6774 adapter->netdev = netdev;
6775 adapter->pdev = pdev;
6776 hw = &adapter->hw;
6777 hw->back = adapter;
6778 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6779
05857980 6780 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6781 pci_resource_len(pdev, 0));
9a799d71
AK		 6782 if (!hw->hw_addr) {
6783 err = -EIO;
6784 goto err_ioremap;
6785 }
6786
6787 for (i = 1; i <= 5; i++) {
6788 if (pci_resource_len(pdev, i) == 0)
6789 continue;
6790 }
6791
0edc3527 6792 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6793 ixgbe_set_ethtool_ops(netdev);
9a799d71 6794 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6795 strcpy(netdev->name, pci_name(pdev));
6796
9a799d71
AK		 6797 adapter->bd_number = cards_found;
6798
9a799d71
AK		 6799 /* Setup hw api */
6800 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6801 hw->mac.type = ii->mac;
9a799d71 6802
c44ade9e
JB		 6803 /* EEPROM */
6804 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6805 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6806 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6807 if (!(eec & (1 << 8)))
6808 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6809
6810 /* PHY */
6811 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6812 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6813 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6814 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6815 hw->phy.mdio.mmds = 0;
6816 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6817 hw->phy.mdio.dev = netdev;
6818 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6819 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6820
6821 /* set up this timer and work struct before calling get_invariants
6822 * which might start the timer
6823 */
6824 init_timer(&adapter->sfp_timer);
c061b18d 6825 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6826 adapter->sfp_timer.data = (unsigned long) adapter;
6827
6828 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6829
e8e26350
PW		 6830 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6831 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6832
6833 /* a new SFP+ module arrival, called from GPI SDP2 context */
6834 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6835 ixgbe_sfp_config_module_task);
e8e26350 6836
8ca783ab 6837 ii->get_invariants(hw);
9a799d71
AK		 6838
6839 /* setup the private structure */
6840 err = ixgbe_sw_init(adapter);
6841 if (err)
6842 goto err_sw_init;
6843
e86bff0e
DS		 6844 /* Make it possible the adapter to be woken up via WOL */
6845 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6846 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6847
bf069c97
DS		 6848 /*
6849 * If there is a fan on this device and it has failed log the
6850 * failure.
6851 */
6852 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6853 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6854 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6855 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6856 }
6857
c44ade9e 6858 /* reset_hw fills in the perm_addr as well */
119fc60a 6859 hw->phy.reset_if_overtemp = true;
c44ade9e 6860 err = hw->mac.ops.reset_hw(hw);
119fc60a 6861 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6862 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6863 hw->mac.type == ixgbe_mac_82598EB) {
6864 /*
6865 * Start a kernel thread to watch for a module to arrive.
6866 * Only do this for 82598, since 82599 will generate
6867 * interrupts on module arrival.
6868 */
6869 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6870 mod_timer(&adapter->sfp_timer,
6871 round_jiffies(jiffies + (2 * HZ)));
6872 err = 0;
6873 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6874 e_dev_err("failed to initialize because an unsupported SFP+ "
6875 "module type was detected.\n");
6876 e_dev_err("Reload the driver after installing a supported "
6877 "module.\n");
04f165ef
PW		 6878 goto err_sw_init;
6879 } else if (err) {
849c4542 6880 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6881 goto err_sw_init;
6882 }
6883
1cdd1ec8
GR		 6884 ixgbe_probe_vf(adapter, ii);
6885
396e799c 6886 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6887 NETIF_F_IP_CSUM |
6888 NETIF_F_HW_VLAN_TX |
6889 NETIF_F_HW_VLAN_RX |
6890 NETIF_F_HW_VLAN_FILTER;
9a799d71 6891
e9990a9c 6892 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6893 netdev->features |= NETIF_F_TSO;
9a799d71 6894 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6895 netdev->features |= NETIF_F_GRO;
ad31c402 6896
45a5ead0
JB		 6897 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6898 netdev->features |= NETIF_F_SCTP_CSUM;
6899
ad31c402
JK		 6900 netdev->vlan_features |= NETIF_F_TSO;
6901 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6902 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6903 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6904 netdev->vlan_features |= NETIF_F_SG;
6905
1cdd1ec8
GR		 6906 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6907 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6908 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6909 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6910 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6911
7a6b6f51 6912#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6913 netdev->dcbnl_ops = &dcbnl_ops;
6914#endif
6915
eacd73f7 6916#ifdef IXGBE_FCOE
0d551589 6917 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6918 if (hw->mac.ops.get_device_caps) {
6919 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6920 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6921 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6922 }
6923 }
5e09d7f6
YZ		 6924 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6925 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6926 netdev->vlan_features |= NETIF_F_FSO;
6927 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6928 }
eacd73f7 6929#endif /* IXGBE_FCOE */
7b872a55 6930 if (pci_using_dac) {
9a799d71 6931 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6932 netdev->vlan_features |= NETIF_F_HIGHDMA;
6933 }
9a799d71 6934
0c19d6af 6935 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6936 netdev->features |= NETIF_F_LRO;
6937
9a799d71 6938 /* make sure the EEPROM is good */
c44ade9e 6939 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6940 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6941 err = -EIO;
6942 goto err_eeprom;
6943 }
6944
6945 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6946 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6947
c44ade9e 6948 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6949 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6950 err = -EIO;
6951 goto err_eeprom;
6952 }
6953
61fac744
PW		 6954 /* power down the optics */
6955 if (hw->phy.multispeed_fiber)
6956 hw->mac.ops.disable_tx_laser(hw);
6957
9a799d71 6958 init_timer(&adapter->watchdog_timer);
c061b18d 6959 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 6960 adapter->watchdog_timer.data = (unsigned long)adapter;
6961
6962 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6963 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6964
021230d4
AV		 6965 err = ixgbe_init_interrupt_scheme(adapter);
6966 if (err)
6967 goto err_sw_init;
9a799d71 6968
e8e26350
PW		 6969 switch (pdev->device) {
6970 case IXGBE_DEV_ID_82599_KX4:
495dce12 6971 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 6972 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6973 break;
6974 default:
6975 adapter->wol = 0;
6976 break;
6977 }
e8e26350
PW		 6978 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6979
04f165ef
PW		 6980 /* pick up the PCI bus settings for reporting later */
6981 hw->mac.ops.get_bus_info(hw);
6982
9a799d71 6983 /* print bus type/speed/width info */
849c4542 6984 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 6985 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6986 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6987 "Unknown"),
6988 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6989 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6990 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6991 "Unknown"),
6992 netdev->dev_addr);
c44ade9e 6993 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6994 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6995 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6996 "PBA No: %06x-%03x\n",
6997 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6998 (part_num >> 8), (part_num & 0xff));
e8e26350 6999 else
849c4542
ET		 7000 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7001 hw->mac.type, hw->phy.type,
7002 (part_num >> 8), (part_num & 0xff));
9a799d71 7003
e8e26350 7004 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7005 e_dev_warn("PCI-Express bandwidth available for this card is "
7006 "not sufficient for optimal performance.\n");
7007 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7008 "is required.\n");
0c254d86
AK		 7009 }
7010
34b0368c
PWJ		 7011 /* save off EEPROM version number */
7012 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7013
9a799d71 7014 /* reset the hardware with the new settings */
794caeb2 7015 err = hw->mac.ops.start_hw(hw);
c44ade9e 7016
794caeb2
PWJ		 7017 if (err == IXGBE_ERR_EEPROM_VERSION) {
7018 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7019 e_dev_warn("This device is a pre-production adapter/LOM. "
7020 "Please be aware there may be issues associated "
7021 "with your hardware. If you are experiencing "
7022 "problems please contact your Intel or hardware "
7023 "representative who provided you with this "
7024 "hardware.\n");
794caeb2 7025 }
9a799d71
AK		 7026 strcpy(netdev->name, "eth%d");
7027 err = register_netdev(netdev);
7028 if (err)
7029 goto err_register;
7030
54386467
JB		 7031 /* carrier off reporting is important to ethtool even BEFORE open */
7032 netif_carrier_off(netdev);
7033
c4cf55e5
PWJ		 7034 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7035 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7036 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7037
119fc60a 7038 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7039 INIT_WORK(&adapter->check_overtemp_task,
7040 ixgbe_check_overtemp_task);
5dd2d332 7041#ifdef CONFIG_IXGBE_DCA
652f093f 7042 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7043 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7044 ixgbe_setup_dca(adapter);
7045 }
7046#endif
1cdd1ec8 7047 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7048 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7049 for (i = 0; i < adapter->num_vfs; i++)
7050 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7051 }
7052
0365e6e4
PW		 7053 /* add san mac addr to netdev */
7054 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7055
849c4542 7056 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7057 cards_found++;
7058 return 0;
7059
7060err_register:
5eba3699 7061 ixgbe_release_hw_control(adapter);
7a921c93 7062 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7063err_sw_init:
7064err_eeprom:
1cdd1ec8
GR		 7065 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7066 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7067 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7068 del_timer_sync(&adapter->sfp_timer);
7069 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7070 cancel_work_sync(&adapter->multispeed_fiber_task);
7071 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7072 iounmap(hw->hw_addr);
7073err_ioremap:
7074 free_netdev(netdev);
7075err_alloc_etherdev:
e8e9f696
JP		 7076 pci_release_selected_regions(pdev,
7077 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7078err_pci_reg:
7079err_dma:
7080 pci_disable_device(pdev);
7081 return err;
7082}
7083
7084/**
7085 * ixgbe_remove - Device Removal Routine
7086 * @pdev: PCI device information struct
7087 *
7088 * ixgbe_remove is called by the PCI subsystem to alert the driver
7089 * that it should release a PCI device. The could be caused by a
7090 * Hot-Plug event, or because the driver is going to be removed from
7091 * memory.
7092 **/
7093static void __devexit ixgbe_remove(struct pci_dev *pdev)
7094{
7095 struct net_device *netdev = pci_get_drvdata(pdev);
7096 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7097
7098 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7099 /* clear the module not found bit to make sure the worker won't
7100 * reschedule
7101 */
7102 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7103 del_timer_sync(&adapter->watchdog_timer);
7104
c4900be0
DS		 7105 del_timer_sync(&adapter->sfp_timer);
7106 cancel_work_sync(&adapter->watchdog_task);
7107 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7108 cancel_work_sync(&adapter->multispeed_fiber_task);
7109 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7110 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7111 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7112 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7113 flush_scheduled_work();
7114
5dd2d332 7115#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7116 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7117 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7118 dca_remove_requester(&pdev->dev);
7119 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7120 }
7121
7122#endif
332d4a7d
YZ		 7123#ifdef IXGBE_FCOE
7124 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7125 ixgbe_cleanup_fcoe(adapter);
7126
7127#endif /* IXGBE_FCOE */
0365e6e4
PW		 7128
7129 /* remove the added san mac */
7130 ixgbe_del_sanmac_netdev(netdev);
7131
c4900be0
DS		 7132 if (netdev->reg_state == NETREG_REGISTERED)
7133 unregister_netdev(netdev);
9a799d71 7134
1cdd1ec8
GR		 7135 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7136 ixgbe_disable_sriov(adapter);
7137
7a921c93 7138 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7139
021230d4 7140 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7141
7142 iounmap(adapter->hw.hw_addr);
9ce77666 7143 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7144 IORESOURCE_MEM));
9a799d71 7145
849c4542 7146 e_dev_info("complete\n");
021230d4 7147
9a799d71
AK		 7148 free_netdev(netdev);
7149
19d5afd4 7150 pci_disable_pcie_error_reporting(pdev);
6fabd715 7151
9a799d71
AK		 7152 pci_disable_device(pdev);
7153}
7154
7155/**
7156 * ixgbe_io_error_detected - called when PCI error is detected
7157 * @pdev: Pointer to PCI device
7158 * @state: The current pci connection state
7159 *
7160 * This function is called after a PCI bus error affecting
7161 * this device has been detected.
7162 */
7163static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7164 pci_channel_state_t state)
9a799d71
AK		 7165{
7166 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7167 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7168
7169 netif_device_detach(netdev);
7170
3044b8d1
BL		 7171 if (state == pci_channel_io_perm_failure)
7172 return PCI_ERS_RESULT_DISCONNECT;
7173
9a799d71
AK		 7174 if (netif_running(netdev))
7175 ixgbe_down(adapter);
7176 pci_disable_device(pdev);
7177
b4617240 7178 /* Request a slot reset. */
9a799d71
AK		 7179 return PCI_ERS_RESULT_NEED_RESET;
7180}
7181
7182/**
7183 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7184 * @pdev: Pointer to PCI device
7185 *
7186 * Restart the card from scratch, as if from a cold-boot.
7187 */
7188static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7189{
7190 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7191 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7192 pci_ers_result_t result;
7193 int err;
9a799d71 7194
9ce77666 7195 if (pci_enable_device_mem(pdev)) {
396e799c 7196 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7197 result = PCI_ERS_RESULT_DISCONNECT;
7198 } else {
7199 pci_set_master(pdev);
7200 pci_restore_state(pdev);
c0e1f68b 7201 pci_save_state(pdev);
9a799d71 7202
dd4d8ca6 7203 pci_wake_from_d3(pdev, false);
9a799d71 7204
6fabd715 7205 ixgbe_reset(adapter);
88512539 7206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7207 result = PCI_ERS_RESULT_RECOVERED;
7208 }
7209
7210 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7211 if (err) {
849c4542
ET		 7212 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7213 "failed 0x%0x\n", err);
6fabd715
PWJ		 7214 /* non-fatal, continue */
7215 }
9a799d71 7216
6fabd715 7217 return result;
9a799d71
AK		 7218}
7219
7220/**
7221 * ixgbe_io_resume - called when traffic can start flowing again.
7222 * @pdev: Pointer to PCI device
7223 *
7224 * This callback is called when the error recovery driver tells us that
7225 * its OK to resume normal operation.
7226 */
7227static void ixgbe_io_resume(struct pci_dev *pdev)
7228{
7229 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7230 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7231
7232 if (netif_running(netdev)) {
7233 if (ixgbe_up(adapter)) {
396e799c 7234 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7235 return;
7236 }
7237 }
7238
7239 netif_device_attach(netdev);
9a799d71
AK		 7240}
7241
7242static struct pci_error_handlers ixgbe_err_handler = {
7243 .error_detected = ixgbe_io_error_detected,
7244 .slot_reset = ixgbe_io_slot_reset,
7245 .resume = ixgbe_io_resume,
7246};
7247
7248static struct pci_driver ixgbe_driver = {
7249 .name = ixgbe_driver_name,
7250 .id_table = ixgbe_pci_tbl,
7251 .probe = ixgbe_probe,
7252 .remove = __devexit_p(ixgbe_remove),
7253#ifdef CONFIG_PM
7254 .suspend = ixgbe_suspend,
7255 .resume = ixgbe_resume,
7256#endif
7257 .shutdown = ixgbe_shutdown,
7258 .err_handler = &ixgbe_err_handler
7259};
7260
7261/**
7262 * ixgbe_init_module - Driver Registration Routine
7263 *
7264 * ixgbe_init_module is the first routine called when the driver is
7265 * loaded. All it does is register with the PCI subsystem.
7266 **/
7267static int __init ixgbe_init_module(void)
7268{
7269 int ret;
c7689578 7270 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7271 pr_info("%s\n", ixgbe_copyright);
9a799d71 7272
5dd2d332 7273#ifdef CONFIG_IXGBE_DCA
bd0362dd 7274 dca_register_notify(&dca_notifier);
bd0362dd 7275#endif
5dd2d332 7276
9a799d71
AK		 7277 ret = pci_register_driver(&ixgbe_driver);
7278 return ret;
7279}
b4617240 7280
9a799d71
AK		 7281module_init(ixgbe_init_module);
7282
7283/**
7284 * ixgbe_exit_module - Driver Exit Cleanup Routine
7285 *
7286 * ixgbe_exit_module is called just before the driver is removed
7287 * from memory.
7288 **/
7289static void __exit ixgbe_exit_module(void)
7290{
5dd2d332 7291#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7292 dca_unregister_notify(&dca_notifier);
7293#endif
9a799d71 7294 pci_unregister_driver(&ixgbe_driver);
1a51502b 7295 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7296}
bd0362dd 7297
5dd2d332 7298#ifdef CONFIG_IXGBE_DCA
bd0362dd 7299static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7300 void *p)
bd0362dd
JC		 7301{
7302 int ret_val;
7303
7304 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7305 __ixgbe_notify_dca);
bd0362dd
JC		 7306
7307 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7308}
b453368d 7309
5dd2d332 7310#endif /* CONFIG_IXGBE_DCA */
849c4542 7311
b453368d 7312/**
849c4542 7313 * ixgbe_get_hw_dev return device
b453368d
AD		 7314 * used by hardware layer to print debugging information
7315 **/
849c4542 7316struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7317{
7318 struct ixgbe_adapter *adapter = hw->back;
849c4542 7319 return adapter->netdev;
b453368d 7320}
bd0362dd 7321
9a799d71
AK		 7322module_exit(ixgbe_exit_module);
7323
7324/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree