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ixgbe: Resolve null function pointer accesses on 82598 w/ multi-speed fiber
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
bd508178
AD		 592 switch (adapter->hw.mac.type) {
593 case ixgbe_mac_82598EB:
fe49f04a
AD		 594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 596 break;
597 case ixgbe_mac_82599EB:
fe49f04a
AD		 598 mask = (qmask & 0xFFFFFFFF);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
600 mask = (qmask >> 32);
601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 602 break;
603 default:
604 break;
fe49f04a
AD		 605 }
606}
607
b6ec895e
AD		 608void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
609 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 610{
e5a43549
AD		 611 if (tx_buffer_info->dma) {
612 if (tx_buffer_info->mapped_as_page)
b6ec895e 613 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 614 tx_buffer_info->dma,
615 tx_buffer_info->length,
1b507730 616 DMA_TO_DEVICE);
e5a43549 617 else
b6ec895e 618 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 619 tx_buffer_info->dma,
620 tx_buffer_info->length,
1b507730 621 DMA_TO_DEVICE);
e5a43549
AD		 622 tx_buffer_info->dma = 0;
623 }
9a799d71
AK		 624 if (tx_buffer_info->skb) {
625 dev_kfree_skb_any(tx_buffer_info->skb);
626 tx_buffer_info->skb = NULL;
627 }
44df32c5 628 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 629 /* tx_buffer_info must be completely set up in the transmit path */
630}
631
26f23d82 632/**
7483d9dd 633 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 634 * @adapter: the ixgbe adapter
635 * @tx_ring: the corresponding tx_ring
636 *
637 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
638 * corresponding TC of this tx_ring when checking TFCS.
639 *
7483d9dd 640 * Returns : true if in xon state (currently not paused)
26f23d82 641 */
7483d9dd 642static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 643 struct ixgbe_ring *tx_ring)
26f23d82 644{
26f23d82
YZ		 645 u32 txoff = IXGBE_TFCS_TXOFF;
646
647#ifdef CONFIG_IXGBE_DCB
ca739481 648 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 649 int tc;
26f23d82 650 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
bf29ee6c 651 u8 reg_idx = tx_ring->reg_idx;
26f23d82 652
6837e895
PW		 653 switch (adapter->hw.mac.type) {
654 case ixgbe_mac_82598EB:
26f23d82
YZ		 655 tc = reg_idx >> 2;
656 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 657 break;
658 case ixgbe_mac_82599EB:
26f23d82
YZ		 659 tc = 0;
660 txoff = IXGBE_TFCS_TXOFF;
661 if (dcb_i == 8) {
662 /* TC0, TC1 */
663 tc = reg_idx >> 5;
664 if (tc == 2) /* TC2, TC3 */
665 tc += (reg_idx - 64) >> 4;
666 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
667 tc += 1 + ((reg_idx - 96) >> 3);
668 } else if (dcb_i == 4) {
669 /* TC0, TC1 */
670 tc = reg_idx >> 6;
671 if (tc == 1) {
672 tc += (reg_idx - 64) >> 5;
673 if (tc == 2) /* TC2, TC3 */
674 tc += (reg_idx - 96) >> 4;
675 }
676 }
6837e895
PW		 677 break;
678 default:
679 tc = 0;
bd508178 680 break;
26f23d82
YZ		 681 }
682 txoff <<= tc;
683 }
684#endif
685 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
686}
687
9a799d71 688static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 689 struct ixgbe_ring *tx_ring,
690 unsigned int eop)
9a799d71 691{
e01c31a5 692 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 693
9a799d71 694 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 695 * check with the clearing of time_stamp and movement of eop */
7d637bcc 696 clear_check_for_tx_hang(tx_ring);
44df32c5 697 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 698 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 699 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 700 /* detected Tx unit hang */
e01c31a5 701 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 702 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 703 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 704 " Tx Queue <%d>\n"
705 " TDH, TDT <%x>, <%x>\n"
706 " next_to_use <%x>\n"
707 " next_to_clean <%x>\n"
708 "tx_buffer_info[next_to_clean]\n"
709 " time_stamp <%lx>\n"
710 " jiffies <%lx>\n",
711 tx_ring->queue_index,
84ea2591
AD		 712 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
713 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
849c4542
ET		 714 tx_ring->next_to_use, eop,
715 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 716 return true;
717 }
718
719 return false;
720}
721
b4617240
PW		 722#define IXGBE_MAX_TXD_PWR 14
723#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 724
725/* Tx Descriptors needed, worst case */
726#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
727 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
728#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 729 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 730
e01c31a5
JB		 731static void ixgbe_tx_timeout(struct net_device *netdev);
732
9a799d71
AK		 733/**
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 735 * @q_vector: structure containing interrupt and ring information
e01c31a5 736 * @tx_ring: tx ring to clean
9a799d71 737 **/
fe49f04a 738static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 739 struct ixgbe_ring *tx_ring)
9a799d71 740{
fe49f04a 741 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 742 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
743 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 744 unsigned int total_bytes = 0, total_packets = 0;
b953799e 745 u16 i, eop, count = 0;
9a799d71
AK		 746
747 i = tx_ring->next_to_clean;
12207e49 748 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 749 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 750
751 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 752 (count < tx_ring->work_limit)) {
12207e49 753 bool cleaned = false;
2d0bb1c1 754 rmb(); /* read buffer_info after eop_desc */
12207e49 755 for ( ; !cleaned; count++) {
31f05a2d 756 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 757 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 758
759 tx_desc->wb.status = 0;
12207e49 760 cleaned = (i == eop);
9a799d71 761
8ad494b0
AD		 762 i++;
763 if (i == tx_ring->count)
764 i = 0;
e01c31a5 765
8ad494b0
AD		 766 if (cleaned && tx_buffer_info->skb) {
767 total_bytes += tx_buffer_info->bytecount;
768 total_packets += tx_buffer_info->gso_segs;
e092be60 769 }
e01c31a5 770
b6ec895e 771 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 772 tx_buffer_info);
e01c31a5 773 }
12207e49
PWJ		 774
775 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 776 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 777 }
778
9a799d71 779 tx_ring->next_to_clean = i;
b953799e
AD		 780 tx_ring->total_bytes += total_bytes;
781 tx_ring->total_packets += total_packets;
782 u64_stats_update_begin(&tx_ring->syncp);
783 tx_ring->stats.packets += total_packets;
784 tx_ring->stats.bytes += total_bytes;
785 u64_stats_update_end(&tx_ring->syncp);
786
787 if (check_for_tx_hang(tx_ring) &&
788 ixgbe_check_tx_hang(adapter, tx_ring, i)) {
789 /* schedule immediate reset if we believe we hung */
790 e_info(probe, "tx hang %d detected, resetting "
791 "adapter\n", adapter->tx_timeout_count + 1);
792 ixgbe_tx_timeout(adapter->netdev);
793
794 /* the adapter is about to reset, no point in enabling stuff */
795 return true;
796 }
9a799d71 797
e092be60 798#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 799 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 800 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
803 */
804 smp_mb();
fc77dc3c 805 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 806 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 807 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 808 ++tx_ring->tx_stats.restart_queue;
30eba97a 809 }
e092be60 810 }
9a799d71 811
807540ba 812 return count < tx_ring->work_limit;
9a799d71
AK		 813}
814
5dd2d332 815#ifdef CONFIG_IXGBE_DCA
bd0362dd 816static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 817 struct ixgbe_ring *rx_ring,
818 int cpu)
bd0362dd 819{
33cf09c9 820 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 821 u32 rxctrl;
33cf09c9
AD		 822 u8 reg_idx = rx_ring->reg_idx;
823
824 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
828 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
829 break;
830 case ixgbe_mac_82599EB:
831 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
832 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
833 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
834 break;
835 default:
836 break;
bd0362dd 837 }
33cf09c9
AD		 838 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
839 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
840 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
841 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
842 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
843 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 844}
845
846static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 847 struct ixgbe_ring *tx_ring,
848 int cpu)
bd0362dd 849{
33cf09c9 850 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 851 u32 txctrl;
33cf09c9
AD		 852 u8 reg_idx = tx_ring->reg_idx;
853
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
857 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
858 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
859 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
860 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
861 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
862 break;
863 case ixgbe_mac_82599EB:
864 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
865 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
866 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
867 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
868 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
869 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
870 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
871 break;
872 default:
873 break;
874 }
875}
876
877static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
878{
879 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 880 int cpu = get_cpu();
33cf09c9
AD		 881 long r_idx;
882 int i;
bd0362dd 883
33cf09c9
AD		 884 if (q_vector->cpu == cpu)
885 goto out_no_update;
886
887 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
888 for (i = 0; i < q_vector->txr_count; i++) {
889 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
890 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
891 r_idx + 1);
bd0362dd 892 }
33cf09c9
AD		 893
894 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
895 for (i = 0; i < q_vector->rxr_count; i++) {
896 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
897 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
898 r_idx + 1);
899 }
900
901 q_vector->cpu = cpu;
902out_no_update:
bd0362dd
JC		 903 put_cpu();
904}
905
906static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
907{
33cf09c9 908 int num_q_vectors;
bd0362dd
JC		 909 int i;
910
911 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
912 return;
913
e35ec126
AD		 914 /* always use CB2 mode, difference is masked in the CB driver */
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
916
33cf09c9
AD		 917 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
918 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
919 else
920 num_q_vectors = 1;
921
922 for (i = 0; i < num_q_vectors; i++) {
923 adapter->q_vector[i]->cpu = -1;
924 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 925 }
926}
927
928static int __ixgbe_notify_dca(struct device *dev, void *data)
929{
c60fbb00 930 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 931 unsigned long event = *(unsigned long *)data;
932
33cf09c9
AD		 933 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
934 return 0;
935
bd0362dd
JC		 936 switch (event) {
937 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 938 /* if we're already enabled, don't do it again */
939 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
940 break;
652f093f 941 if (dca_add_requester(dev) == 0) {
96b0e0f6 942 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 943 ixgbe_setup_dca(adapter);
944 break;
945 }
946 /* Fall Through since DCA is disabled. */
947 case DCA_PROVIDER_REMOVE:
948 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
949 dca_remove_requester(dev);
950 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
952 }
953 break;
954 }
955
652f093f 956 return 0;
bd0362dd
JC		 957}
958
5dd2d332 959#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 960/**
961 * ixgbe_receive_skb - Send a completed packet up the stack
962 * @adapter: board private structure
963 * @skb: packet to send up
177db6ff
MC		 964 * @status: hardware indication of status of receive
965 * @rx_ring: rx descriptor ring (for a specific queue) to setup
966 * @rx_desc: rx descriptor
9a799d71 967 **/
78b6f4ce 968static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 969 struct sk_buff *skb, u8 status,
970 struct ixgbe_ring *ring,
971 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 972{
78b6f4ce
HX		 973 struct ixgbe_adapter *adapter = q_vector->adapter;
974 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 975 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
976 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 977
f62bbb5e
JG		 978 if (is_vlan && (tag & VLAN_VID_MASK))
979 __vlan_hwaccel_put_tag(skb, tag);
980
981 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
982 napi_gro_receive(napi, skb);
983 else
984 netif_rx(skb);
9a799d71
AK		 985}
986
e59bd25d
AV		 987/**
988 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
989 * @adapter: address of board private structure
990 * @status_err: hardware indication of status of receive
991 * @skb: skb currently being received and modified
992 **/
9a799d71 993static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 994 union ixgbe_adv_rx_desc *rx_desc,
995 struct sk_buff *skb)
9a799d71 996{
8bae1b2b
DS		 997 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
998
bc8acf2c 999 skb_checksum_none_assert(skb);
9a799d71 1000
712744be
JB		 1001 /* Rx csum disabled */
1002 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1003 return;
e59bd25d
AV		 1004
1005 /* if IP and error */
1006 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1007 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1008 adapter->hw_csum_rx_error++;
1009 return;
1010 }
e59bd25d
AV		 1011
1012 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1013 return;
1014
1015 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1016 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1017
1018 /*
1019 * 82599 errata, UDP frames with a 0 checksum can be marked as
1020 * checksum errors.
1021 */
1022 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1023 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1024 return;
1025
e59bd25d
AV		 1026 adapter->hw_csum_rx_error++;
1027 return;
1028 }
1029
9a799d71 1030 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1031 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1032}
1033
84ea2591 1034static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1035{
1036 /*
1037 * Force memory writes to complete before letting h/w
1038 * know there are new descriptors to fetch. (Only
1039 * applicable for weak-ordered memory model archs,
1040 * such as IA-64).
1041 */
1042 wmb();
84ea2591 1043 writel(val, rx_ring->tail);
e8e26350
PW		 1044}
1045
9a799d71
AK		 1046/**
1047 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1048 * @rx_ring: ring to place buffers on
1049 * @cleaned_count: number of buffers to replace
9a799d71 1050 **/
fc77dc3c 1051void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1052{
9a799d71 1053 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1054 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1055 struct sk_buff *skb;
1056 u16 i = rx_ring->next_to_use;
9a799d71 1057
fc77dc3c
AD		 1058 /* do nothing if no valid netdev defined */
1059 if (!rx_ring->netdev)
1060 return;
1061
9a799d71 1062 while (cleaned_count--) {
31f05a2d 1063 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1064 bi = &rx_ring->rx_buffer_info[i];
1065 skb = bi->skb;
9a799d71 1066
d5f398ed 1067 if (!skb) {
fc77dc3c 1068 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1069 rx_ring->rx_buf_len);
9a799d71 1070 if (!skb) {
5b7da515 1071 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1072 goto no_buffers;
1073 }
d716a7d8
AD		 1074 /* initialize queue mapping */
1075 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1076 bi->skb = skb;
d716a7d8 1077 }
9a799d71 1078
d716a7d8 1079 if (!bi->dma) {
b6ec895e 1080 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1081 skb->data,
e8e9f696 1082 rx_ring->rx_buf_len,
1b507730 1083 DMA_FROM_DEVICE);
b6ec895e 1084 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1085 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1086 bi->dma = 0;
1087 goto no_buffers;
1088 }
9a799d71 1089 }
d5f398ed 1090
7d637bcc 1091 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1092 if (!bi->page) {
fc77dc3c 1093 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1094 if (!bi->page) {
5b7da515 1095 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1096 goto no_buffers;
1097 }
1098 }
1099
1100 if (!bi->page_dma) {
1101 /* use a half page if we're re-using */
1102 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1103 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1104 bi->page,
1105 bi->page_offset,
1106 PAGE_SIZE / 2,
1107 DMA_FROM_DEVICE);
b6ec895e 1108 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1109 bi->page_dma)) {
5b7da515 1110 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1111 bi->page_dma = 0;
1112 goto no_buffers;
1113 }
1114 }
1115
1116 /* Refresh the desc even if buffer_addrs didn't change
1117 * because each write-back erases this info. */
3a581073
JB		 1118 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1119 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1120 } else {
3a581073 1121 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1122 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1123 }
1124
1125 i++;
1126 if (i == rx_ring->count)
1127 i = 0;
9a799d71 1128 }
7c6e0a43 1129
9a799d71
AK		 1130no_buffers:
1131 if (rx_ring->next_to_use != i) {
1132 rx_ring->next_to_use = i;
84ea2591 1133 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1134 }
1135}
1136
c267fc16 1137static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1138{
c267fc16
AD		 1139 /* HW will not DMA in data larger than the given buffer, even if it
1140 * parses the (NFS, of course) header to be larger. In that case, it
1141 * fills the header buffer and spills the rest into the page.
1142 */
1143 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1144 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1145 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1146 if (hlen > IXGBE_RX_HDR_SIZE)
1147 hlen = IXGBE_RX_HDR_SIZE;
1148 return hlen;
7c6e0a43
JB		 1149}
1150
f8212f97
AD		 1151/**
1152 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1153 * @skb: pointer to the last skb in the rsc queue
1154 *
1155 * This function changes a queue full of hw rsc buffers into a completed
1156 * packet. It uses the ->prev pointers to find the first packet and then
1157 * turns it into the frag list owner.
1158 **/
aa80175a 1159static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1160{
1161 unsigned int frag_list_size = 0;
aa80175a 1162 unsigned int skb_cnt = 1;
f8212f97
AD		 1163
1164 while (skb->prev) {
1165 struct sk_buff *prev = skb->prev;
1166 frag_list_size += skb->len;
1167 skb->prev = NULL;
1168 skb = prev;
aa80175a 1169 skb_cnt++;
f8212f97
AD		 1170 }
1171
1172 skb_shinfo(skb)->frag_list = skb->next;
1173 skb->next = NULL;
1174 skb->len += frag_list_size;
1175 skb->data_len += frag_list_size;
1176 skb->truesize += frag_list_size;
aa80175a
AD		 1177 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1178
f8212f97
AD		 1179 return skb;
1180}
1181
aa80175a
AD		 1182static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1183{
1184 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1185 IXGBE_RXDADV_RSCCNT_MASK);
1186}
43634e82 1187
c267fc16 1188static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1189 struct ixgbe_ring *rx_ring,
1190 int *work_done, int work_to_do)
9a799d71 1191{
78b6f4ce 1192 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1193 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1194 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1195 struct sk_buff *skb;
d2f4fbe2 1196 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1197 const int current_node = numa_node_id();
3d8fd385
YZ		 1198#ifdef IXGBE_FCOE
1199 int ddp_bytes = 0;
1200#endif /* IXGBE_FCOE */
c267fc16
AD		 1201 u32 staterr;
1202 u16 i;
1203 u16 cleaned_count = 0;
aa80175a 1204 bool pkt_is_rsc = false;
9a799d71
AK		 1205
1206 i = rx_ring->next_to_clean;
31f05a2d 1207 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1208 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1209
1210 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1211 u32 upper_len = 0;
9a799d71 1212
3c945e5b 1213 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1214
c267fc16
AD		 1215 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1216
9a799d71 1217 skb = rx_buffer_info->skb;
9a799d71 1218 rx_buffer_info->skb = NULL;
c267fc16 1219 prefetch(skb->data);
9a799d71 1220
c267fc16 1221 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1222 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1223
1224 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1225 if (rx_buffer_info->dma) {
c267fc16 1226 u16 hlen;
aa80175a 1227 if (pkt_is_rsc &&
c267fc16
AD		 1228 !(staterr & IXGBE_RXD_STAT_EOP) &&
1229 !skb->prev) {
43634e82
MC		 1230 /*
1231 * When HWRSC is enabled, delay unmapping
1232 * of the first packet. It carries the
1233 * header information, HW may still
1234 * access the header after the writeback.
1235 * Only unmap it when EOP is reached
1236 */
e8171aaa 1237 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1238 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1239 } else {
b6ec895e 1240 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1241 rx_buffer_info->dma,
1242 rx_ring->rx_buf_len,
1243 DMA_FROM_DEVICE);
e8171aaa 1244 }
4f57ca6e 1245 rx_buffer_info->dma = 0;
c267fc16
AD		 1246
1247 if (ring_is_ps_enabled(rx_ring)) {
1248 hlen = ixgbe_get_hlen(rx_desc);
1249 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1250 } else {
1251 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1252 }
1253
1254 skb_put(skb, hlen);
1255 } else {
1256 /* assume packet split since header is unmapped */
1257 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1258 }
1259
1260 if (upper_len) {
b6ec895e
AD		 1261 dma_unmap_page(rx_ring->dev,
1262 rx_buffer_info->page_dma,
1263 PAGE_SIZE / 2,
1264 DMA_FROM_DEVICE);
9a799d71
AK		 1265 rx_buffer_info->page_dma = 0;
1266 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1267 rx_buffer_info->page,
1268 rx_buffer_info->page_offset,
1269 upper_len);
762f4c57 1270
c267fc16
AD		 1271 if ((page_count(rx_buffer_info->page) == 1) &&
1272 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1273 get_page(rx_buffer_info->page);
c267fc16
AD		 1274 else
1275 rx_buffer_info->page = NULL;
9a799d71
AK		 1276
1277 skb->len += upper_len;
1278 skb->data_len += upper_len;
1279 skb->truesize += upper_len;
1280 }
1281
1282 i++;
1283 if (i == rx_ring->count)
1284 i = 0;
9a799d71 1285
31f05a2d 1286 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1287 prefetch(next_rxd);
9a799d71 1288 cleaned_count++;
f8212f97 1289
aa80175a 1290 if (pkt_is_rsc) {
f8212f97
AD		 1291 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1292 IXGBE_RXDADV_NEXTP_SHIFT;
1293 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1294 } else {
1295 next_buffer = &rx_ring->rx_buffer_info[i];
1296 }
1297
c267fc16 1298 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1299 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1300 rx_buffer_info->skb = next_buffer->skb;
1301 rx_buffer_info->dma = next_buffer->dma;
1302 next_buffer->skb = skb;
1303 next_buffer->dma = 0;
1304 } else {
1305 skb->next = next_buffer->skb;
1306 skb->next->prev = skb;
1307 }
5b7da515 1308 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1309 goto next_desc;
1310 }
1311
aa80175a
AD		 1312 if (skb->prev) {
1313 skb = ixgbe_transform_rsc_queue(skb);
1314 /* if we got here without RSC the packet is invalid */
1315 if (!pkt_is_rsc) {
1316 __pskb_trim(skb, 0);
1317 rx_buffer_info->skb = skb;
1318 goto next_desc;
1319 }
1320 }
c267fc16
AD		 1321
1322 if (ring_is_rsc_enabled(rx_ring)) {
1323 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1324 dma_unmap_single(rx_ring->dev,
1325 IXGBE_RSC_CB(skb)->dma,
1326 rx_ring->rx_buf_len,
1327 DMA_FROM_DEVICE);
1328 IXGBE_RSC_CB(skb)->dma = 0;
1329 IXGBE_RSC_CB(skb)->delay_unmap = false;
1330 }
aa80175a
AD		 1331 }
1332 if (pkt_is_rsc) {
c267fc16
AD		 1333 if (ring_is_ps_enabled(rx_ring))
1334 rx_ring->rx_stats.rsc_count +=
aa80175a 1335 skb_shinfo(skb)->nr_frags;
c267fc16 1336 else
aa80175a
AD		 1337 rx_ring->rx_stats.rsc_count +=
1338 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1339 rx_ring->rx_stats.rsc_flush++;
1340 }
1341
1342 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1343 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1344 /* trim packet back to size 0 and recycle it */
1345 __pskb_trim(skb, 0);
1346 rx_buffer_info->skb = skb;
9a799d71
AK		 1347 goto next_desc;
1348 }
1349
8bae1b2b 1350 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1351
1352 /* probably a little skewed due to removing CRC */
1353 total_rx_bytes += skb->len;
1354 total_rx_packets++;
1355
fc77dc3c 1356 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1357#ifdef IXGBE_FCOE
1358 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1359 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1360 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1361 if (!ddp_bytes)
332d4a7d 1362 goto next_desc;
3d8fd385 1363 }
332d4a7d 1364#endif /* IXGBE_FCOE */
fdaff1ce 1365 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1366
1367next_desc:
1368 rx_desc->wb.upper.status_error = 0;
1369
c267fc16
AD		 1370 (*work_done)++;
1371 if (*work_done >= work_to_do)
1372 break;
1373
9a799d71
AK		 1374 /* return some buffers to hardware, one at a time is too slow */
1375 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1376 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1377 cleaned_count = 0;
1378 }
1379
1380 /* use prefetched values */
1381 rx_desc = next_rxd;
9a799d71 1382 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1383 }
1384
9a799d71
AK		 1385 rx_ring->next_to_clean = i;
1386 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1387
1388 if (cleaned_count)
fc77dc3c 1389 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1390
3d8fd385
YZ		 1391#ifdef IXGBE_FCOE
1392 /* include DDPed FCoE data */
1393 if (ddp_bytes > 0) {
1394 unsigned int mss;
1395
fc77dc3c 1396 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1397 sizeof(struct fc_frame_header) -
1398 sizeof(struct fcoe_crc_eof);
1399 if (mss > 512)
1400 mss &= ~511;
1401 total_rx_bytes += ddp_bytes;
1402 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1403 }
1404#endif /* IXGBE_FCOE */
1405
f494e8fa
AV		 1406 rx_ring->total_packets += total_rx_packets;
1407 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1408 u64_stats_update_begin(&rx_ring->syncp);
1409 rx_ring->stats.packets += total_rx_packets;
1410 rx_ring->stats.bytes += total_rx_bytes;
1411 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1412}
1413
021230d4 1414static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1415/**
1416 * ixgbe_configure_msix - Configure MSI-X hardware
1417 * @adapter: board private structure
1418 *
1419 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1420 * interrupts.
1421 **/
1422static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1423{
021230d4 1424 struct ixgbe_q_vector *q_vector;
bf29ee6c 1425 int i, q_vectors, v_idx, r_idx;
021230d4 1426 u32 mask;
9a799d71 1427
021230d4 1428 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1429
4df10466
JB		 1430 /*
1431 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1432 * corresponding register.
1433 */
1434 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1435 q_vector = adapter->q_vector[v_idx];
984b3f57 1436 /* XXX for_each_set_bit(...) */
021230d4 1437 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1438 adapter->num_rx_queues);
021230d4
AV		 1439
1440 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1441 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1442 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1443 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1444 adapter->num_rx_queues,
1445 r_idx + 1);
021230d4
AV		 1446 }
1447 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1448 adapter->num_tx_queues);
021230d4
AV		 1449
1450 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1451 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1452 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1453 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1454 adapter->num_tx_queues,
1455 r_idx + 1);
021230d4
AV		 1456 }
1457
021230d4 1458 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1459 /* tx only */
1460 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1461 else if (q_vector->rxr_count)
f7554a2b
NS		 1462 /* rx or mixed */
1463 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1464
fe49f04a 1465 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1466 /* If Flow Director is enabled, set interrupt affinity */
1467 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1468 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1469 /*
1470 * Allocate the affinity_hint cpumask, assign the mask
1471 * for this vector, and set our affinity_hint for
1472 * this irq.
1473 */
1474 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1475 GFP_KERNEL))
1476 return;
1477 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1478 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1479 q_vector->affinity_mask);
1480 }
9a799d71
AK		 1481 }
1482
bd508178
AD		 1483 switch (adapter->hw.mac.type) {
1484 case ixgbe_mac_82598EB:
e8e26350 1485 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1486 v_idx);
bd508178
AD		 1487 break;
1488 case ixgbe_mac_82599EB:
e8e26350 1489 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1490 break;
1491
1492 default:
1493 break;
1494 }
021230d4
AV		 1495 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1496
41fb9248 1497 /* set up to autoclear timer, and the vectors */
021230d4 1498 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1499 if (adapter->num_vfs)
1500 mask &= ~(IXGBE_EIMS_OTHER |
1501 IXGBE_EIMS_MAILBOX |
1502 IXGBE_EIMS_LSC);
1503 else
1504 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1506}
1507
f494e8fa
AV		 1508enum latency_range {
1509 lowest_latency = 0,
1510 low_latency = 1,
1511 bulk_latency = 2,
1512 latency_invalid = 255
1513};
1514
1515/**
1516 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1517 * @adapter: pointer to adapter
1518 * @eitr: eitr setting (ints per sec) to give last timeslice
1519 * @itr_setting: current throttle rate in ints/second
1520 * @packets: the number of packets during this measurement interval
1521 * @bytes: the number of bytes during this measurement interval
1522 *
1523 * Stores a new ITR value based on packets and byte
1524 * counts during the last interrupt. The advantage of per interrupt
1525 * computation is faster updates and more accurate ITR for the current
1526 * traffic pattern. Constants in this function were computed
1527 * based on theoretical maximum wire speed and thresholds were set based
1528 * on testing data as well as attempting to minimize response time
1529 * while increasing bulk throughput.
1530 * this functionality is controlled by the InterruptThrottleRate module
1531 * parameter (see ixgbe_param.c)
1532 **/
1533static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1534 u32 eitr, u8 itr_setting,
1535 int packets, int bytes)
f494e8fa
AV		 1536{
1537 unsigned int retval = itr_setting;
1538 u32 timepassed_us;
1539 u64 bytes_perint;
1540
1541 if (packets == 0)
1542 goto update_itr_done;
1543
1544
1545 /* simple throttlerate management
1546 * 0-20MB/s lowest (100000 ints/s)
1547 * 20-100MB/s low (20000 ints/s)
1548 * 100-1249MB/s bulk (8000 ints/s)
1549 */
1550 /* what was last interrupt timeslice? */
1551 timepassed_us = 1000000/eitr;
1552 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1553
1554 switch (itr_setting) {
1555 case lowest_latency:
1556 if (bytes_perint > adapter->eitr_low)
1557 retval = low_latency;
1558 break;
1559 case low_latency:
1560 if (bytes_perint > adapter->eitr_high)
1561 retval = bulk_latency;
1562 else if (bytes_perint <= adapter->eitr_low)
1563 retval = lowest_latency;
1564 break;
1565 case bulk_latency:
1566 if (bytes_perint <= adapter->eitr_high)
1567 retval = low_latency;
1568 break;
1569 }
1570
1571update_itr_done:
1572 return retval;
1573}
1574
509ee935
JB		 1575/**
1576 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1577 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1578 *
1579 * This function is made to be called by ethtool and by the driver
1580 * when it needs to update EITR registers at runtime. Hardware
1581 * specific quirks/differences are taken care of here.
1582 */
fe49f04a 1583void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1584{
fe49f04a 1585 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1586 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1587 int v_idx = q_vector->v_idx;
1588 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1589
bd508178
AD		 1590 switch (adapter->hw.mac.type) {
1591 case ixgbe_mac_82598EB:
509ee935
JB		 1592 /* must write high and low 16 bits to reset counter */
1593 itr_reg |= (itr_reg << 16);
bd508178
AD		 1594 break;
1595 case ixgbe_mac_82599EB:
f8d1dcaf
JB		 1596 /*
1597 * 82599 can support a value of zero, so allow it for
1598 * max interrupt rate, but there is an errata where it can
1599 * not be zero with RSC
1600 */
1601 if (itr_reg == 8 &&
1602 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1603 itr_reg = 0;
1604
509ee935
JB		 1605 /*
1606 * set the WDIS bit to not clear the timer bits and cause an
1607 * immediate assertion of the interrupt
1608 */
1609 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1610 break;
1611 default:
1612 break;
509ee935
JB		 1613 }
1614 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1615}
1616
f494e8fa
AV		 1617static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1618{
1619 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1620 int i, r_idx;
f494e8fa
AV		 1621 u32 new_itr;
1622 u8 current_itr, ret_itr;
f494e8fa
AV		 1623
1624 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1625 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1626 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1627 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1628 q_vector->tx_itr,
1629 tx_ring->total_packets,
1630 tx_ring->total_bytes);
f494e8fa
AV		 1631 /* if the result for this queue would decrease interrupt
1632 * rate for this vector then use that result */
30efa5a3 1633 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1634 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1635 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1636 r_idx + 1);
f494e8fa
AV		 1637 }
1638
1639 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1640 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1641 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1642 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1643 q_vector->rx_itr,
1644 rx_ring->total_packets,
1645 rx_ring->total_bytes);
f494e8fa
AV		 1646 /* if the result for this queue would decrease interrupt
1647 * rate for this vector then use that result */
30efa5a3 1648 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1649 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1650 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1651 r_idx + 1);
f494e8fa
AV		 1652 }
1653
30efa5a3 1654 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1655
1656 switch (current_itr) {
1657 /* counts and packets in update_itr are dependent on these numbers */
1658 case lowest_latency:
1659 new_itr = 100000;
1660 break;
1661 case low_latency:
1662 new_itr = 20000; /* aka hwitr = ~200 */
1663 break;
1664 case bulk_latency:
1665 default:
1666 new_itr = 8000;
1667 break;
1668 }
1669
1670 if (new_itr != q_vector->eitr) {
fe49f04a 1671 /* do an exponential smoothing */
125601bf 1672 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1673
1674 /* save the algorithm value here, not the smoothed one */
1675 q_vector->eitr = new_itr;
fe49f04a
AD		 1676
1677 ixgbe_write_eitr(q_vector);
f494e8fa 1678 }
f494e8fa
AV		 1679}
1680
119fc60a
MC		 1681/**
1682 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1683 * @work: pointer to work_struct containing our data
1684 **/
1685static void ixgbe_check_overtemp_task(struct work_struct *work)
1686{
1687 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1688 struct ixgbe_adapter,
1689 check_overtemp_task);
119fc60a
MC		 1690 struct ixgbe_hw *hw = &adapter->hw;
1691 u32 eicr = adapter->interrupt_event;
1692
7ca647bd
JP		 1693 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1694 return;
1695
1696 switch (hw->device_id) {
1697 case IXGBE_DEV_ID_82599_T3_LOM: {
1698 u32 autoneg;
1699 bool link_up = false;
1700
1701 if (hw->mac.ops.check_link)
1702 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1703
1704 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1705 (eicr & IXGBE_EICR_LSC))
1706 /* Check if this is due to overtemp */
1707 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1708 break;
1709 return;
1710 }
1711 default:
1712 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1713 return;
7ca647bd 1714 break;
119fc60a 1715 }
7ca647bd
JP		 1716 e_crit(drv,
1717 "Network adapter has been stopped because it has over heated. "
1718 "Restart the computer. If the problem persists, "
1719 "power off the system and replace the adapter\n");
1720 /* write to clear the interrupt */
1721 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1722}
1723
0befdb3e
JB		 1724static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1725{
1726 struct ixgbe_hw *hw = &adapter->hw;
1727
1728 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1729 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1730 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1731 /* write to clear the interrupt */
1732 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1733 }
1734}
cf8280ee 1735
e8e26350
PW		 1736static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1737{
1738 struct ixgbe_hw *hw = &adapter->hw;
1739
73c4b7cd
AD		 1740 if (eicr & IXGBE_EICR_GPI_SDP2) {
1741 /* Clear the interrupt */
1742 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1743 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1744 schedule_work(&adapter->sfp_config_module_task);
1745 }
1746
e8e26350
PW		 1747 if (eicr & IXGBE_EICR_GPI_SDP1) {
1748 /* Clear the interrupt */
1749 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
73c4b7cd
AD		 1750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1751 schedule_work(&adapter->multispeed_fiber_task);
e8e26350
PW		 1752 }
1753}
1754
cf8280ee
JB		 1755static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1756{
1757 struct ixgbe_hw *hw = &adapter->hw;
1758
1759 adapter->lsc_int++;
1760 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1761 adapter->link_check_timeout = jiffies;
1762 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1763 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1764 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1765 schedule_work(&adapter->watchdog_task);
1766 }
1767}
1768
9a799d71
AK		 1769static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1770{
1771 struct net_device *netdev = data;
1772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1773 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1774 u32 eicr;
1775
1776 /*
1777 * Workaround for Silicon errata. Use clear-by-write instead
1778 * of clear-by-read. Reading with EICS will return the
1779 * interrupt causes without clearing, which later be done
1780 * with the write to EICR.
1781 */
1782 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1783 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1784
cf8280ee
JB		 1785 if (eicr & IXGBE_EICR_LSC)
1786 ixgbe_check_lsc(adapter);
d4f80882 1787
1cdd1ec8
GR		 1788 if (eicr & IXGBE_EICR_MAILBOX)
1789 ixgbe_msg_task(adapter);
1790
bd508178
AD		 1791 switch (hw->mac.type) {
1792 case ixgbe_mac_82599EB:
c4cf55e5
PWJ		 1793 /* Handle Flow Director Full threshold interrupt */
1794 if (eicr & IXGBE_EICR_FLOW_DIR) {
1795 int i;
1796 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1797 /* Disable transmits before FDIR Re-initialization */
1798 netif_tx_stop_all_queues(netdev);
1799 for (i = 0; i < adapter->num_tx_queues; i++) {
1800 struct ixgbe_ring *tx_ring =
e8e9f696 1801 adapter->tx_ring[i];
7d637bcc
AD		 1802 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1803 &tx_ring->state))
c4cf55e5
PWJ		 1804 schedule_work(&adapter->fdir_reinit_task);
1805 }
1806 }
bd508178
AD		 1807 ixgbe_check_sfp_event(adapter, eicr);
1808 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1809 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1810 adapter->interrupt_event = eicr;
1811 schedule_work(&adapter->check_overtemp_task);
1812 }
1813 break;
1814 default:
1815 break;
c4cf55e5 1816 }
bd508178
AD		 1817
1818 ixgbe_check_fan_failure(adapter, eicr);
1819
d4f80882
AV		 1820 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1821 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1822
1823 return IRQ_HANDLED;
1824}
1825
fe49f04a
AD		 1826static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1827 u64 qmask)
1828{
1829 u32 mask;
bd508178 1830 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1831
bd508178
AD		 1832 switch (hw->mac.type) {
1833 case ixgbe_mac_82598EB:
fe49f04a 1834 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1835 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1836 break;
1837 case ixgbe_mac_82599EB:
fe49f04a 1838 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1839 if (mask)
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1841 mask = (qmask >> 32);
bd508178
AD		 1842 if (mask)
1843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1844 break;
1845 default:
1846 break;
fe49f04a
AD		 1847 }
1848 /* skip the flush */
1849}
1850
1851static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1852 u64 qmask)
fe49f04a
AD		 1853{
1854 u32 mask;
bd508178 1855 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1856
bd508178
AD		 1857 switch (hw->mac.type) {
1858 case ixgbe_mac_82598EB:
fe49f04a 1859 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1861 break;
1862 case ixgbe_mac_82599EB:
fe49f04a 1863 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1864 if (mask)
1865 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1866 mask = (qmask >> 32);
bd508178
AD		 1867 if (mask)
1868 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1869 break;
1870 default:
1871 break;
fe49f04a
AD		 1872 }
1873 /* skip the flush */
1874}
1875
9a799d71
AK		 1876static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1877{
021230d4
AV		 1878 struct ixgbe_q_vector *q_vector = data;
1879 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1880 struct ixgbe_ring *tx_ring;
021230d4
AV		 1881 int i, r_idx;
1882
1883 if (!q_vector->txr_count)
1884 return IRQ_HANDLED;
1885
1886 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1887 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1888 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1889 tx_ring->total_bytes = 0;
1890 tx_ring->total_packets = 0;
021230d4 1891 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1892 r_idx + 1);
021230d4 1893 }
9a799d71 1894
9b471446 1895 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1896 napi_schedule(&q_vector->napi);
1897
9a799d71
AK		 1898 return IRQ_HANDLED;
1899}
1900
021230d4
AV		 1901/**
1902 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1903 * @irq: unused
1904 * @data: pointer to our q_vector struct for this interrupt vector
1905 **/
9a799d71
AK		 1906static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1907{
021230d4
AV		 1908 struct ixgbe_q_vector *q_vector = data;
1909 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1910 struct ixgbe_ring *rx_ring;
021230d4 1911 int r_idx;
30efa5a3 1912 int i;
021230d4 1913
33cf09c9
AD		 1914#ifdef CONFIG_IXGBE_DCA
1915 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1916 ixgbe_update_dca(q_vector);
1917#endif
1918
021230d4 1919 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 1920 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1921 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1922 rx_ring->total_bytes = 0;
1923 rx_ring->total_packets = 0;
1924 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1925 r_idx + 1);
30efa5a3
JB		 1926 }
1927
021230d4
AV		 1928 if (!q_vector->rxr_count)
1929 return IRQ_HANDLED;
1930
9b471446 1931 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1932 napi_schedule(&q_vector->napi);
021230d4
AV		 1933
1934 return IRQ_HANDLED;
1935}
1936
1937static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1938{
91281fd3
AD		 1939 struct ixgbe_q_vector *q_vector = data;
1940 struct ixgbe_adapter *adapter = q_vector->adapter;
1941 struct ixgbe_ring *ring;
1942 int r_idx;
1943 int i;
1944
1945 if (!q_vector->txr_count && !q_vector->rxr_count)
1946 return IRQ_HANDLED;
1947
1948 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1949 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1950 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1951 ring->total_bytes = 0;
1952 ring->total_packets = 0;
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1954 r_idx + 1);
91281fd3
AD		 1955 }
1956
1957 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1958 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1959 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1960 ring->total_bytes = 0;
1961 ring->total_packets = 0;
1962 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1963 r_idx + 1);
91281fd3
AD		 1964 }
1965
9b471446 1966 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1967 napi_schedule(&q_vector->napi);
9a799d71 1968
9a799d71
AK		 1969 return IRQ_HANDLED;
1970}
1971
021230d4
AV		 1972/**
1973 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1974 * @napi: napi struct with our devices info in it
1975 * @budget: amount of work driver is allowed to do this pass, in packets
1976 *
f0848276
JB		 1977 * This function is optimized for cleaning one queue only on a single
1978 * q_vector!!!
021230d4 1979 **/
9a799d71
AK		 1980static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1981{
021230d4 1982 struct ixgbe_q_vector *q_vector =
e8e9f696 1983 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1984 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1985 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1986 int work_done = 0;
021230d4 1987 long r_idx;
9a799d71 1988
5dd2d332 1989#ifdef CONFIG_IXGBE_DCA
bd0362dd 1990 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 1991 ixgbe_update_dca(q_vector);
bd0362dd 1992#endif
9a799d71 1993
33cf09c9
AD		 1994 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1995 rx_ring = adapter->rx_ring[r_idx];
1996
78b6f4ce 1997 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1998
021230d4
AV		 1999 /* If all Rx work done, exit the polling mode */
2000 if (work_done < budget) {
288379f0 2001 napi_complete(napi);
f7554a2b 2002 if (adapter->rx_itr_setting & 1)
f494e8fa 2003 ixgbe_set_itr_msix(q_vector);
9a799d71 2004 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2005 ixgbe_irq_enable_queues(adapter,
e8e9f696 2006 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2007 }
2008
2009 return work_done;
2010}
2011
f0848276 2012/**
91281fd3 2013 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2014 * @napi: napi struct with our devices info in it
2015 * @budget: amount of work driver is allowed to do this pass, in packets
2016 *
2017 * This function will clean more than one rx queue associated with a
2018 * q_vector.
2019 **/
91281fd3 2020static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2021{
2022 struct ixgbe_q_vector *q_vector =
e8e9f696 2023 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2024 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2025 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2026 int work_done = 0, i;
2027 long r_idx;
91281fd3
AD		 2028 bool tx_clean_complete = true;
2029
33cf09c9
AD		 2030#ifdef CONFIG_IXGBE_DCA
2031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2032 ixgbe_update_dca(q_vector);
2033#endif
2034
91281fd3
AD		 2035 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2036 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2037 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2038 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2039 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2040 r_idx + 1);
91281fd3 2041 }
f0848276
JB		 2042
2043 /* attempt to distribute budget to each queue fairly, but don't allow
2044 * the budget to go below 1 because we'll exit polling */
2045 budget /= (q_vector->rxr_count ?: 1);
2046 budget = max(budget, 1);
2047 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2048 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2049 ring = adapter->rx_ring[r_idx];
91281fd3 2050 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2051 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2052 r_idx + 1);
f0848276
JB		 2053 }
2054
2055 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2056 ring = adapter->rx_ring[r_idx];
f0848276 2057 /* If all Rx work done, exit the polling mode */
7f821875 2058 if (work_done < budget) {
288379f0 2059 napi_complete(napi);
f7554a2b 2060 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2061 ixgbe_set_itr_msix(q_vector);
2062 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2063 ixgbe_irq_enable_queues(adapter,
e8e9f696 2064 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2065 return 0;
2066 }
2067
2068 return work_done;
2069}
91281fd3
AD		 2070
2071/**
2072 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2073 * @napi: napi struct with our devices info in it
2074 * @budget: amount of work driver is allowed to do this pass, in packets
2075 *
2076 * This function is optimized for cleaning one queue only on a single
2077 * q_vector!!!
2078 **/
2079static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2080{
2081 struct ixgbe_q_vector *q_vector =
e8e9f696 2082 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2083 struct ixgbe_adapter *adapter = q_vector->adapter;
2084 struct ixgbe_ring *tx_ring = NULL;
2085 int work_done = 0;
2086 long r_idx;
2087
91281fd3
AD		 2088#ifdef CONFIG_IXGBE_DCA
2089 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2090 ixgbe_update_dca(q_vector);
91281fd3
AD		 2091#endif
2092
33cf09c9
AD		 2093 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2094 tx_ring = adapter->tx_ring[r_idx];
2095
91281fd3
AD		 2096 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2097 work_done = budget;
2098
f7554a2b 2099 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2100 if (work_done < budget) {
2101 napi_complete(napi);
f7554a2b 2102 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2103 ixgbe_set_itr_msix(q_vector);
2104 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2105 ixgbe_irq_enable_queues(adapter,
2106 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2107 }
2108
2109 return work_done;
2110}
2111
021230d4 2112static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2113 int r_idx)
021230d4 2114{
7a921c93 2115 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2116 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2117
2118 set_bit(r_idx, q_vector->rxr_idx);
2119 q_vector->rxr_count++;
2274543f 2120 rx_ring->q_vector = q_vector;
021230d4
AV		 2121}
2122
2123static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2124 int t_idx)
021230d4 2125{
7a921c93 2126 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2127 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2128
2129 set_bit(t_idx, q_vector->txr_idx);
2130 q_vector->txr_count++;
2274543f 2131 tx_ring->q_vector = q_vector;
021230d4
AV		 2132}
2133
9a799d71 2134/**
021230d4
AV		 2135 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2136 * @adapter: board private structure to initialize
9a799d71 2137 *
021230d4
AV		 2138 * This function maps descriptor rings to the queue-specific vectors
2139 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2140 * one vector per ring/queue, but on a constrained vector budget, we
2141 * group the rings as "efficiently" as possible. You would add new
2142 * mapping configurations in here.
9a799d71 2143 **/
d0759ebb 2144static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2145{
d0759ebb 2146 int q_vectors;
021230d4
AV		 2147 int v_start = 0;
2148 int rxr_idx = 0, txr_idx = 0;
2149 int rxr_remaining = adapter->num_rx_queues;
2150 int txr_remaining = adapter->num_tx_queues;
2151 int i, j;
2152 int rqpv, tqpv;
2153 int err = 0;
2154
2155 /* No mapping required if MSI-X is disabled. */
2156 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2157 goto out;
9a799d71 2158
d0759ebb
AD		 2159 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2160
021230d4
AV		 2161 /*
2162 * The ideal configuration...
2163 * We have enough vectors to map one per queue.
2164 */
d0759ebb 2165 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2166 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2167 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2168
021230d4
AV		 2169 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2170 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2171
9a799d71 2172 goto out;
021230d4 2173 }
9a799d71 2174
021230d4
AV		 2175 /*
2176 * If we don't have enough vectors for a 1-to-1
2177 * mapping, we'll have to group them so there are
2178 * multiple queues per vector.
2179 */
2180 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2181 for (i = v_start; i < q_vectors; i++) {
2182 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2183 for (j = 0; j < rqpv; j++) {
2184 map_vector_to_rxq(adapter, i, rxr_idx);
2185 rxr_idx++;
2186 rxr_remaining--;
2187 }
d0759ebb 2188 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2189 for (j = 0; j < tqpv; j++) {
2190 map_vector_to_txq(adapter, i, txr_idx);
2191 txr_idx++;
2192 txr_remaining--;
9a799d71 2193 }
9a799d71 2194 }
021230d4
AV		 2195out:
2196 return err;
2197}
2198
2199/**
2200 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2201 * @adapter: board private structure
2202 *
2203 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2204 * interrupts from the kernel.
2205 **/
2206static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2207{
2208 struct net_device *netdev = adapter->netdev;
2209 irqreturn_t (*handler)(int, void *);
2210 int i, vector, q_vectors, err;
e8e9f696 2211 int ri = 0, ti = 0;
021230d4
AV		 2212
2213 /* Decrement for Other and TCP Timer vectors */
2214 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2215
d0759ebb 2216 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2217 if (err)
d0759ebb 2218 return err;
021230d4 2219
d0759ebb
AD		 2220#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2221 ? &ixgbe_msix_clean_many : \
2222 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2223 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2224 NULL)
021230d4 2225 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2226 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2227 handler = SET_HANDLER(q_vector);
cb13fc20 2228
e8e9f696 2229 if (handler == &ixgbe_msix_clean_rx) {
d0759ebb 2230 sprintf(q_vector->name, "%s-%s-%d",
cb13fc20 2231 netdev->name, "rx", ri++);
e8e9f696 2232 } else if (handler == &ixgbe_msix_clean_tx) {
d0759ebb 2233 sprintf(q_vector->name, "%s-%s-%d",
cb13fc20 2234 netdev->name, "tx", ti++);
d0759ebb
AD		 2235 } else if (handler == &ixgbe_msix_clean_many) {
2236 sprintf(q_vector->name, "%s-%s-%d",
32aa77a4
AD		 2237 netdev->name, "TxRx", ri++);
2238 ti++;
d0759ebb
AD		 2239 } else {
2240 /* skip this unused q_vector */
2241 continue;
32aa77a4 2242 }
021230d4 2243 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2244 handler, 0, q_vector->name,
2245 q_vector);
9a799d71 2246 if (err) {
396e799c 2247 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2248 "Error: %d\n", err);
021230d4 2249 goto free_queue_irqs;
9a799d71 2250 }
9a799d71
AK		 2251 }
2252
d0759ebb 2253 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2254 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2255 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2256 if (err) {
396e799c 2257 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2258 goto free_queue_irqs;
9a799d71
AK		 2259 }
2260
9a799d71
AK		 2261 return 0;
2262
021230d4
AV		 2263free_queue_irqs:
2264 for (i = vector - 1; i >= 0; i--)
2265 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2266 adapter->q_vector[i]);
021230d4
AV		 2267 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2268 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2269 kfree(adapter->msix_entries);
2270 adapter->msix_entries = NULL;
9a799d71
AK		 2271 return err;
2272}
2273
f494e8fa
AV		 2274static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2275{
7a921c93 2276 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2277 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2278 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2279 u32 new_itr = q_vector->eitr;
2280 u8 current_itr;
f494e8fa 2281
30efa5a3 2282 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2283 q_vector->tx_itr,
2284 tx_ring->total_packets,
2285 tx_ring->total_bytes);
30efa5a3 2286 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2287 q_vector->rx_itr,
2288 rx_ring->total_packets,
2289 rx_ring->total_bytes);
f494e8fa 2290
30efa5a3 2291 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2292
2293 switch (current_itr) {
2294 /* counts and packets in update_itr are dependent on these numbers */
2295 case lowest_latency:
2296 new_itr = 100000;
2297 break;
2298 case low_latency:
2299 new_itr = 20000; /* aka hwitr = ~200 */
2300 break;
2301 case bulk_latency:
2302 new_itr = 8000;
2303 break;
2304 default:
2305 break;
2306 }
2307
2308 if (new_itr != q_vector->eitr) {
fe49f04a 2309 /* do an exponential smoothing */
125601bf 2310 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2311
125601bf 2312 /* save the algorithm value here */
509ee935 2313 q_vector->eitr = new_itr;
fe49f04a
AD		 2314
2315 ixgbe_write_eitr(q_vector);
f494e8fa 2316 }
f494e8fa
AV		 2317}
2318
79aefa45
AD		 2319/**
2320 * ixgbe_irq_enable - Enable default interrupt generation settings
2321 * @adapter: board private structure
2322 **/
6af3b9eb
ET		 2323static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2324 bool flush)
79aefa45
AD		 2325{
2326 u32 mask;
835462fc
NS		 2327
2328 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2329 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2330 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2331 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2332 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2333 switch (adapter->hw.mac.type) {
2334 case ixgbe_mac_82599EB:
2a41ff81 2335 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2336 mask |= IXGBE_EIMS_GPI_SDP1;
2337 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2338 if (adapter->num_vfs)
2339 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2340 break;
2341 default:
2342 break;
e8e26350 2343 }
c4cf55e5
PWJ		 2344 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2345 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2346 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2347
79aefa45 2348 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2349 if (queues)
2350 ixgbe_irq_enable_queues(adapter, ~0);
2351 if (flush)
2352 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2353
2354 if (adapter->num_vfs > 32) {
2355 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2356 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2357 }
79aefa45 2358}
021230d4 2359
9a799d71 2360/**
021230d4 2361 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2362 * @irq: interrupt number
2363 * @data: pointer to a network interface device structure
9a799d71
AK		 2364 **/
2365static irqreturn_t ixgbe_intr(int irq, void *data)
2366{
2367 struct net_device *netdev = data;
2368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2369 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2370 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2371 u32 eicr;
2372
54037505 2373 /*
6af3b9eb 2374 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2375 * before the read of EICR.
2376 */
2377 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2378
021230d4
AV		 2379 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2380 * therefore no explict interrupt disable is necessary */
2381 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2382 if (!eicr) {
6af3b9eb
ET		 2383 /*
2384 * shared interrupt alert!
f47cf66e 2385 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2386 * have disabled interrupts due to EIAM
2387 * finish the workaround of silicon errata on 82598. Unmask
2388 * the interrupt that we masked before the EICR read.
2389 */
2390 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2391 ixgbe_irq_enable(adapter, true, true);
9a799d71 2392 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2393 }
9a799d71 2394
cf8280ee
JB		 2395 if (eicr & IXGBE_EICR_LSC)
2396 ixgbe_check_lsc(adapter);
021230d4 2397
bd508178
AD		 2398 switch (hw->mac.type) {
2399 case ixgbe_mac_82599EB:
e8e26350 2400 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2401 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2402 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2403 adapter->interrupt_event = eicr;
2404 schedule_work(&adapter->check_overtemp_task);
2405 }
2406 break;
2407 default:
2408 break;
2409 }
e8e26350 2410
0befdb3e
JB		 2411 ixgbe_check_fan_failure(adapter, eicr);
2412
7a921c93 2413 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2414 adapter->tx_ring[0]->total_packets = 0;
2415 adapter->tx_ring[0]->total_bytes = 0;
2416 adapter->rx_ring[0]->total_packets = 0;
2417 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2418 /* would disable interrupts here but EIAM disabled it */
7a921c93 2419 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2420 }
2421
6af3b9eb
ET		 2422 /*
2423 * re-enable link(maybe) and non-queue interrupts, no flush.
2424 * ixgbe_poll will re-enable the queue interrupts
2425 */
2426
2427 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2428 ixgbe_irq_enable(adapter, false, false);
2429
9a799d71
AK		 2430 return IRQ_HANDLED;
2431}
2432
021230d4
AV		 2433static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2434{
2435 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2436
2437 for (i = 0; i < q_vectors; i++) {
7a921c93 2438 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2439 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2440 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2441 q_vector->rxr_count = 0;
2442 q_vector->txr_count = 0;
2443 }
2444}
2445
9a799d71
AK		 2446/**
2447 * ixgbe_request_irq - initialize interrupts
2448 * @adapter: board private structure
2449 *
2450 * Attempts to configure interrupts using the best available
2451 * capabilities of the hardware and kernel.
2452 **/
021230d4 2453static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2454{
2455 struct net_device *netdev = adapter->netdev;
021230d4 2456 int err;
9a799d71 2457
021230d4
AV		 2458 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2459 err = ixgbe_request_msix_irqs(adapter);
2460 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2461 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2462 netdev->name, netdev);
021230d4 2463 } else {
a0607fd3 2464 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2465 netdev->name, netdev);
9a799d71
AK		 2466 }
2467
9a799d71 2468 if (err)
396e799c 2469 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2470
9a799d71
AK		 2471 return err;
2472}
2473
2474static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2475{
2476 struct net_device *netdev = adapter->netdev;
2477
2478 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2479 int i, q_vectors;
9a799d71 2480
021230d4
AV		 2481 q_vectors = adapter->num_msix_vectors;
2482
2483 i = q_vectors - 1;
9a799d71 2484 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2485
021230d4
AV		 2486 i--;
2487 for (; i >= 0; i--) {
2488 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2489 adapter->q_vector[i]);
021230d4
AV		 2490 }
2491
2492 ixgbe_reset_q_vectors(adapter);
2493 } else {
2494 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2495 }
2496}
2497
22d5a71b
JB		 2498/**
2499 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2500 * @adapter: board private structure
2501 **/
2502static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2503{
bd508178
AD		 2504 switch (adapter->hw.mac.type) {
2505 case ixgbe_mac_82598EB:
835462fc 2506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2507 break;
2508 case ixgbe_mac_82599EB:
835462fc
NS		 2509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2511 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2512 if (adapter->num_vfs > 32)
2513 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2514 break;
2515 default:
2516 break;
22d5a71b
JB		 2517 }
2518 IXGBE_WRITE_FLUSH(&adapter->hw);
2519 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2520 int i;
2521 for (i = 0; i < adapter->num_msix_vectors; i++)
2522 synchronize_irq(adapter->msix_entries[i].vector);
2523 } else {
2524 synchronize_irq(adapter->pdev->irq);
2525 }
2526}
2527
9a799d71
AK		 2528/**
2529 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2530 *
2531 **/
2532static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2533{
9a799d71
AK		 2534 struct ixgbe_hw *hw = &adapter->hw;
2535
021230d4 2536 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2537 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2538
e8e26350
PW		 2539 ixgbe_set_ivar(adapter, 0, 0, 0);
2540 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2541
2542 map_vector_to_rxq(adapter, 0, 0);
2543 map_vector_to_txq(adapter, 0, 0);
2544
396e799c 2545 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2546}
2547
43e69bf0
AD		 2548/**
2549 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2550 * @adapter: board private structure
2551 * @ring: structure containing ring specific data
2552 *
2553 * Configure the Tx descriptor ring after a reset.
2554 **/
84418e3b
AD		 2555void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2556 struct ixgbe_ring *ring)
43e69bf0
AD		 2557{
2558 struct ixgbe_hw *hw = &adapter->hw;
2559 u64 tdba = ring->dma;
2f1860b8
AD		 2560 int wait_loop = 10;
2561 u32 txdctl;
bf29ee6c 2562 u8 reg_idx = ring->reg_idx;
43e69bf0 2563
2f1860b8
AD		 2564 /* disable queue to avoid issues while updating state */
2565 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2566 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2567 txdctl & ~IXGBE_TXDCTL_ENABLE);
2568 IXGBE_WRITE_FLUSH(hw);
2569
43e69bf0 2570 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2571 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2572 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2573 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2574 ring->count * sizeof(union ixgbe_adv_tx_desc));
2575 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2576 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2577 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2578
2f1860b8
AD		 2579 /* configure fetching thresholds */
2580 if (adapter->rx_itr_setting == 0) {
2581 /* cannot set wthresh when itr==0 */
2582 txdctl &= ~0x007F0000;
2583 } else {
2584 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2585 txdctl |= (8 << 16);
2586 }
2587 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2588 /* PThresh workaround for Tx hang with DFP enabled. */
2589 txdctl |= 32;
2590 }
2591
2592 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2593 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2594 adapter->atr_sample_rate) {
2595 ring->atr_sample_rate = adapter->atr_sample_rate;
2596 ring->atr_count = 0;
2597 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2598 } else {
2599 ring->atr_sample_rate = 0;
2600 }
2f1860b8
AD		 2601
2602 /* enable queue */
2603 txdctl |= IXGBE_TXDCTL_ENABLE;
2604 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2605
2606 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2607 if (hw->mac.type == ixgbe_mac_82598EB &&
2608 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2609 return;
2610
2611 /* poll to verify queue is enabled */
2612 do {
2613 msleep(1);
2614 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2615 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2616 if (!wait_loop)
2617 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2618}
2619
120ff942
AD		 2620static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2621{
2622 struct ixgbe_hw *hw = &adapter->hw;
2623 u32 rttdcs;
2624 u32 mask;
2625
2626 if (hw->mac.type == ixgbe_mac_82598EB)
2627 return;
2628
2629 /* disable the arbiter while setting MTQC */
2630 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2631 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2632 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2633
2634 /* set transmit pool layout */
2635 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2636 switch (adapter->flags & mask) {
2637
2638 case (IXGBE_FLAG_SRIOV_ENABLED):
2639 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2640 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2641 break;
2642
2643 case (IXGBE_FLAG_DCB_ENABLED):
2644 /* We enable 8 traffic classes, DCB only */
2645 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2646 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2647 break;
2648
2649 default:
2650 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2651 break;
2652 }
2653
2654 /* re-enable the arbiter */
2655 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2656 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2657}
2658
9a799d71 2659/**
3a581073 2660 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2661 * @adapter: board private structure
2662 *
2663 * Configure the Tx unit of the MAC after a reset.
2664 **/
2665static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2666{
2f1860b8
AD		 2667 struct ixgbe_hw *hw = &adapter->hw;
2668 u32 dmatxctl;
43e69bf0 2669 u32 i;
9a799d71 2670
2f1860b8
AD		 2671 ixgbe_setup_mtqc(adapter);
2672
2673 if (hw->mac.type != ixgbe_mac_82598EB) {
2674 /* DMATXCTL.EN must be before Tx queues are enabled */
2675 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2676 dmatxctl |= IXGBE_DMATXCTL_TE;
2677 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2678 }
2679
9a799d71 2680 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2681 for (i = 0; i < adapter->num_tx_queues; i++)
2682 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2683}
2684
e8e26350 2685#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2686
a6616b42 2687static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2688 struct ixgbe_ring *rx_ring)
cc41ac7c 2689{
cc41ac7c 2690 u32 srrctl;
bf29ee6c 2691 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2692
bd508178
AD		 2693 switch (adapter->hw.mac.type) {
2694 case ixgbe_mac_82598EB: {
2695 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2696 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2697 reg_idx = reg_idx & mask;
cc41ac7c 2698 }
bd508178
AD		 2699 break;
2700 case ixgbe_mac_82599EB:
2701 default:
2702 break;
2703 }
2704
bf29ee6c 2705 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2706
2707 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2708 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2709 if (adapter->num_vfs)
2710 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2711
afafd5b0
AD		 2712 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2713 IXGBE_SRRCTL_BSIZEHDR_MASK;
2714
7d637bcc 2715 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2716#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2717 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2718#else
2719 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2720#endif
cc41ac7c 2721 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2722 } else {
afafd5b0
AD		 2723 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2724 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2725 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2726 }
e8e26350 2727
bf29ee6c 2728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2729}
9a799d71 2730
05abb126 2731static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2732{
05abb126
AD		 2733 struct ixgbe_hw *hw = &adapter->hw;
2734 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2735 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2736 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2737 u32 mrqc = 0, reta = 0;
2738 u32 rxcsum;
2739 int i, j;
0cefafad
JB		 2740 int mask;
2741
05abb126
AD		 2742 /* Fill out hash function seeds */
2743 for (i = 0; i < 10; i++)
2744 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2745
2746 /* Fill out redirection table */
2747 for (i = 0, j = 0; i < 128; i++, j++) {
2748 if (j == adapter->ring_feature[RING_F_RSS].indices)
2749 j = 0;
2750 /* reta = 4-byte sliding window of
2751 * 0x00..(indices-1)(indices-1)00..etc. */
2752 reta = (reta << 8) | (j * 0x11);
2753 if ((i & 3) == 3)
2754 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2755 }
0cefafad 2756
05abb126
AD		 2757 /* Disable indicating checksum in descriptor, enables RSS hash */
2758 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2759 rxcsum |= IXGBE_RXCSUM_PCSD;
2760 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2761
2762 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2763 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2764 else
2765 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2766#ifdef CONFIG_IXGBE_DCB
05abb126 2767 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2768#endif
05abb126
AD		 2769 | IXGBE_FLAG_SRIOV_ENABLED
2770 );
0cefafad
JB		 2771
2772 switch (mask) {
2773 case (IXGBE_FLAG_RSS_ENABLED):
2774 mrqc = IXGBE_MRQC_RSSEN;
2775 break;
1cdd1ec8
GR		 2776 case (IXGBE_FLAG_SRIOV_ENABLED):
2777 mrqc = IXGBE_MRQC_VMDQEN;
2778 break;
0cefafad
JB		 2779#ifdef CONFIG_IXGBE_DCB
2780 case (IXGBE_FLAG_DCB_ENABLED):
2781 mrqc = IXGBE_MRQC_RT8TCEN;
2782 break;
2783#endif /* CONFIG_IXGBE_DCB */
2784 default:
2785 break;
2786 }
2787
05abb126
AD		 2788 /* Perform hash on these packet types */
2789 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2790 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2791 | IXGBE_MRQC_RSS_FIELD_IPV6
2792 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2793
2794 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2795}
2796
bb5a9ad2
NS		 2797/**
2798 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2799 * @adapter: address of board private structure
2800 * @index: index of ring to set
bb5a9ad2 2801 **/
7367096a
AD		 2802static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *ring)
bb5a9ad2 2804{
bb5a9ad2 2805 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2806 u32 rscctrl;
edd2ea55 2807 int rx_buf_len;
bf29ee6c 2808 u8 reg_idx = ring->reg_idx;
7367096a 2809
7d637bcc 2810 if (!ring_is_rsc_enabled(ring))
7367096a 2811 return;
bb5a9ad2 2812
7367096a
AD		 2813 rx_buf_len = ring->rx_buf_len;
2814 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2815 rscctrl |= IXGBE_RSCCTL_RSCEN;
2816 /*
2817 * we must limit the number of descriptors so that the
2818 * total size of max desc * buf_len is not greater
2819 * than 65535
2820 */
7d637bcc 2821 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2822#if (MAX_SKB_FRAGS > 16)
2823 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2824#elif (MAX_SKB_FRAGS > 8)
2825 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2826#elif (MAX_SKB_FRAGS > 4)
2827 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2828#else
2829 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2830#endif
2831 } else {
2832 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2833 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2834 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2835 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2836 else
2837 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2838 }
7367096a 2839 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2840}
2841
9e10e045
AD		 2842/**
2843 * ixgbe_set_uta - Set unicast filter table address
2844 * @adapter: board private structure
2845 *
2846 * The unicast table address is a register array of 32-bit registers.
2847 * The table is meant to be used in a way similar to how the MTA is used
2848 * however due to certain limitations in the hardware it is necessary to
2849 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2850 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2851 **/
2852static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2853{
2854 struct ixgbe_hw *hw = &adapter->hw;
2855 int i;
2856
2857 /* The UTA table only exists on 82599 hardware and newer */
2858 if (hw->mac.type < ixgbe_mac_82599EB)
2859 return;
2860
2861 /* we only need to do this if VMDq is enabled */
2862 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2863 return;
2864
2865 for (i = 0; i < 128; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2867}
2868
2869#define IXGBE_MAX_RX_DESC_POLL 10
2870static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2871 struct ixgbe_ring *ring)
2872{
2873 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2874 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2875 u32 rxdctl;
bf29ee6c 2876 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2877
2878 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2879 if (hw->mac.type == ixgbe_mac_82598EB &&
2880 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2881 return;
2882
2883 do {
2884 msleep(1);
2885 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2886 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2887
2888 if (!wait_loop) {
2889 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2890 "the polling period\n", reg_idx);
2891 }
2892}
2893
84418e3b
AD		 2894void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2895 struct ixgbe_ring *ring)
acd37177
AD		 2896{
2897 struct ixgbe_hw *hw = &adapter->hw;
2898 u64 rdba = ring->dma;
9e10e045 2899 u32 rxdctl;
bf29ee6c 2900 u8 reg_idx = ring->reg_idx;
acd37177 2901
9e10e045
AD		 2902 /* disable queue to avoid issues while updating state */
2903 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2904 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2905 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2906 IXGBE_WRITE_FLUSH(hw);
2907
acd37177
AD		 2908 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2909 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2910 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2911 ring->count * sizeof(union ixgbe_adv_rx_desc));
2912 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2913 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2914 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2915
2916 ixgbe_configure_srrctl(adapter, ring);
2917 ixgbe_configure_rscctl(adapter, ring);
2918
2919 if (hw->mac.type == ixgbe_mac_82598EB) {
2920 /*
2921 * enable cache line friendly hardware writes:
2922 * PTHRESH=32 descriptors (half the internal cache),
2923 * this also removes ugly rx_no_buffer_count increment
2924 * HTHRESH=4 descriptors (to minimize latency on fetch)
2925 * WTHRESH=8 burst writeback up to two cache lines
2926 */
2927 rxdctl &= ~0x3FFFFF;
2928 rxdctl |= 0x080420;
2929 }
2930
2931 /* enable receive descriptor ring */
2932 rxdctl |= IXGBE_RXDCTL_ENABLE;
2933 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2934
2935 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 2936 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2937}
2938
48654521
AD		 2939static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2940{
2941 struct ixgbe_hw *hw = &adapter->hw;
2942 int p;
2943
2944 /* PSRTYPE must be initialized in non 82598 adapters */
2945 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2946 IXGBE_PSRTYPE_UDPHDR |
2947 IXGBE_PSRTYPE_IPV4HDR |
48654521 2948 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2949 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2950
2951 if (hw->mac.type == ixgbe_mac_82598EB)
2952 return;
2953
2954 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2955 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2956
2957 for (p = 0; p < adapter->num_rx_pools; p++)
2958 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2959 psrtype);
2960}
2961
f5b4a52e
AD		 2962static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2963{
2964 struct ixgbe_hw *hw = &adapter->hw;
2965 u32 gcr_ext;
2966 u32 vt_reg_bits;
2967 u32 reg_offset, vf_shift;
2968 u32 vmdctl;
2969
2970 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2971 return;
2972
2973 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2974 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2975 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2976 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2977
2978 vf_shift = adapter->num_vfs % 32;
2979 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2980
2981 /* Enable only the PF's pool for Tx/Rx */
2982 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2983 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2984 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2985 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2986 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2987
2988 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2989 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2990
2991 /*
2992 * Set up VF register offsets for selected VT Mode,
2993 * i.e. 32 or 64 VFs for SR-IOV
2994 */
2995 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2996 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2997 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2998 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2999
3000 /* enable Tx loopback for VF/PF communication */
3001 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3002}
3003
477de6ed 3004static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3005{
9a799d71
AK		 3006 struct ixgbe_hw *hw = &adapter->hw;
3007 struct net_device *netdev = adapter->netdev;
3008 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3009 int rx_buf_len;
477de6ed
AD		 3010 struct ixgbe_ring *rx_ring;
3011 int i;
3012 u32 mhadd, hlreg0;
48654521 3013
9a799d71 3014 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 3015 /* Do not use packet split if we're in SR-IOV Mode */
3016 if (!adapter->num_vfs)
3017 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3018
3019 /* Set the RX buffer length according to the mode */
3020 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3021 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3022 } else {
0c19d6af 3023 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3024 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3025 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3026 else
477de6ed 3027 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3028 }
3029
63f39bd1 3030#ifdef IXGBE_FCOE
477de6ed
AD		 3031 /* adjust max frame to be able to do baby jumbo for FCoE */
3032 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3033 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3034 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3035
477de6ed
AD		 3036#endif /* IXGBE_FCOE */
3037 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3038 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3039 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3040 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3041
3042 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3043 }
3044
3045 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3046 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3047 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3048 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3049
0cefafad
JB		 3050 /*
3051 * Setup the HW Rx Head and Tail Descriptor Pointers and
3052 * the Base and Length of the Rx Descriptor Ring
3053 */
9a799d71 3054 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3055 rx_ring = adapter->rx_ring[i];
a6616b42 3056 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3057
6e455b89 3058 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3059 set_ring_ps_enabled(rx_ring);
3060 else
3061 clear_ring_ps_enabled(rx_ring);
3062
3063 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3064 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3065 else
7d637bcc 3066 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3067
63f39bd1 3068#ifdef IXGBE_FCOE
e8e9f696 3069 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3070 struct ixgbe_ring_feature *f;
3071 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3072 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3073 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3074 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3075 rx_ring->rx_buf_len =
e8e9f696 3076 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3077 } else if (!ring_is_rsc_enabled(rx_ring) &&
3078 !ring_is_ps_enabled(rx_ring)) {
3079 rx_ring->rx_buf_len =
3080 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3081 }
63f39bd1 3082 }
63f39bd1 3083#endif /* IXGBE_FCOE */
477de6ed 3084 }
477de6ed
AD		 3085}
3086
7367096a
AD		 3087static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3088{
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3091
3092 switch (hw->mac.type) {
3093 case ixgbe_mac_82598EB:
3094 /*
3095 * For VMDq support of different descriptor types or
3096 * buffer sizes through the use of multiple SRRCTL
3097 * registers, RDRXCTL.MVMEN must be set to 1
3098 *
3099 * also, the manual doesn't mention it clearly but DCA hints
3100 * will only use queue 0's tags unless this bit is set. Side
3101 * effects of setting this bit are only that SRRCTL must be
3102 * fully programmed [0..15]
3103 */
3104 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3105 break;
3106 case ixgbe_mac_82599EB:
3107 /* Disable RSC for ACK packets */
3108 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3109 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3110 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3111 /* hardware requires some bits to be set by default */
3112 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3113 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3114 break;
3115 default:
3116 /* We should do nothing since we don't know this hardware */
3117 return;
3118 }
3119
3120 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3121}
3122
477de6ed
AD		 3123/**
3124 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3125 * @adapter: board private structure
3126 *
3127 * Configure the Rx unit of the MAC after a reset.
3128 **/
3129static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3130{
3131 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3132 int i;
3133 u32 rxctrl;
477de6ed
AD		 3134
3135 /* disable receives while setting up the descriptors */
3136 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3137 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3138
3139 ixgbe_setup_psrtype(adapter);
7367096a 3140 ixgbe_setup_rdrxctl(adapter);
477de6ed 3141
9e10e045 3142 /* Program registers for the distribution of queues */
f5b4a52e 3143 ixgbe_setup_mrqc(adapter);
f5b4a52e 3144
9e10e045
AD		 3145 ixgbe_set_uta(adapter);
3146
477de6ed
AD		 3147 /* set_rx_buffer_len must be called before ring initialization */
3148 ixgbe_set_rx_buffer_len(adapter);
3149
3150 /*
3151 * Setup the HW Rx Head and Tail Descriptor Pointers and
3152 * the Base and Length of the Rx Descriptor Ring
3153 */
9e10e045
AD		 3154 for (i = 0; i < adapter->num_rx_queues; i++)
3155 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3156
9e10e045
AD		 3157 /* disable drop enable for 82598 parts */
3158 if (hw->mac.type == ixgbe_mac_82598EB)
3159 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3160
3161 /* enable all receives */
3162 rxctrl |= IXGBE_RXCTRL_RXEN;
3163 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3164}
3165
068c89b0
DS		 3166static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3167{
3168 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3169 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3170 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3171
3172 /* add VID to filter table */
1ada1b1b 3173 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3174 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3175}
3176
3177static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3178{
3179 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3180 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3181 int pool_ndx = adapter->num_vfs;
068c89b0 3182
068c89b0 3183 /* remove VID from filter table */
1ada1b1b 3184 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3185 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3186}
3187
5f6c0181
JB		 3188/**
3189 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3190 * @adapter: driver data
3191 */
3192static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3193{
3194 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3195 u32 vlnctrl;
3196
3197 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3198 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3199 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3200}
3201
3202/**
3203 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3204 * @adapter: driver data
3205 */
3206static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3207{
3208 struct ixgbe_hw *hw = &adapter->hw;
3209 u32 vlnctrl;
3210
3211 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3212 vlnctrl |= IXGBE_VLNCTRL_VFE;
3213 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3214 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3215}
3216
3217/**
3218 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3219 * @adapter: driver data
3220 */
3221static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3222{
3223 struct ixgbe_hw *hw = &adapter->hw;
3224 u32 vlnctrl;
5f6c0181
JB		 3225 int i, j;
3226
3227 switch (hw->mac.type) {
3228 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3229 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3230 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3231 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3232 break;
3233 case ixgbe_mac_82599EB:
5f6c0181
JB		 3234 for (i = 0; i < adapter->num_rx_queues; i++) {
3235 j = adapter->rx_ring[i]->reg_idx;
3236 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3237 vlnctrl &= ~IXGBE_RXDCTL_VME;
3238 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3239 }
3240 break;
3241 default:
3242 break;
3243 }
3244}
3245
3246/**
f62bbb5e 3247 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3248 * @adapter: driver data
3249 */
f62bbb5e 3250static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3251{
3252 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3253 u32 vlnctrl;
5f6c0181
JB		 3254 int i, j;
3255
3256 switch (hw->mac.type) {
3257 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3258 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3259 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3260 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3261 break;
3262 case ixgbe_mac_82599EB:
5f6c0181
JB		 3263 for (i = 0; i < adapter->num_rx_queues; i++) {
3264 j = adapter->rx_ring[i]->reg_idx;
3265 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3266 vlnctrl |= IXGBE_RXDCTL_VME;
3267 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3268 }
3269 break;
3270 default:
3271 break;
3272 }
3273}
3274
9a799d71
AK		 3275static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3276{
f62bbb5e 3277 u16 vid;
9a799d71 3278
f62bbb5e
JG		 3279 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3280
3281 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3282 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3283}
3284
2850062a
AD		 3285/**
3286 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3287 * @netdev: network interface device structure
3288 *
3289 * Writes unicast address list to the RAR table.
3290 * Returns: -ENOMEM on failure/insufficient address space
3291 * 0 on no addresses written
3292 * X on writing X addresses to the RAR table
3293 **/
3294static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3295{
3296 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3297 struct ixgbe_hw *hw = &adapter->hw;
3298 unsigned int vfn = adapter->num_vfs;
3299 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3300 int count = 0;
3301
3302 /* return ENOMEM indicating insufficient memory for addresses */
3303 if (netdev_uc_count(netdev) > rar_entries)
3304 return -ENOMEM;
3305
3306 if (!netdev_uc_empty(netdev) && rar_entries) {
3307 struct netdev_hw_addr *ha;
3308 /* return error if we do not support writing to RAR table */
3309 if (!hw->mac.ops.set_rar)
3310 return -ENOMEM;
3311
3312 netdev_for_each_uc_addr(ha, netdev) {
3313 if (!rar_entries)
3314 break;
3315 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3316 vfn, IXGBE_RAH_AV);
3317 count++;
3318 }
3319 }
3320 /* write the addresses in reverse order to avoid write combining */
3321 for (; rar_entries > 0 ; rar_entries--)
3322 hw->mac.ops.clear_rar(hw, rar_entries);
3323
3324 return count;
3325}
3326
9a799d71 3327/**
2c5645cf 3328 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3329 * @netdev: network interface device structure
3330 *
2c5645cf
CL		 3331 * The set_rx_method entry point is called whenever the unicast/multicast
3332 * address list or the network interface flags are updated. This routine is
3333 * responsible for configuring the hardware for proper unicast, multicast and
3334 * promiscuous mode.
9a799d71 3335 **/
7f870475 3336void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3337{
3338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3339 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3340 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3341 int count;
9a799d71
AK		 3342
3343 /* Check for Promiscuous and All Multicast modes */
3344
3345 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3346
f5dc442b
AD		 3347 /* set all bits that we expect to always be set */
3348 fctrl |= IXGBE_FCTRL_BAM;
3349 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3350 fctrl |= IXGBE_FCTRL_PMCF;
3351
2850062a
AD		 3352 /* clear the bits we are changing the status of */
3353 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3354
9a799d71 3355 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3356 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3357 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3358 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3359 /* don't hardware filter vlans in promisc mode */
3360 ixgbe_vlan_filter_disable(adapter);
9a799d71 3361 } else {
746b9f02
PM		 3362 if (netdev->flags & IFF_ALLMULTI) {
3363 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3364 vmolr |= IXGBE_VMOLR_MPE;
3365 } else {
3366 /*
3367 * Write addresses to the MTA, if the attempt fails
3368 * then we should just turn on promiscous mode so
3369 * that we can at least receive multicast traffic
3370 */
3371 hw->mac.ops.update_mc_addr_list(hw, netdev);
3372 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3373 }
5f6c0181 3374 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3375 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3376 /*
3377 * Write addresses to available RAR registers, if there is not
3378 * sufficient space to store all the addresses then enable
3379 * unicast promiscous mode
3380 */
3381 count = ixgbe_write_uc_addr_list(netdev);
3382 if (count < 0) {
3383 fctrl |= IXGBE_FCTRL_UPE;
3384 vmolr |= IXGBE_VMOLR_ROPE;
3385 }
9a799d71
AK		 3386 }
3387
2850062a 3388 if (adapter->num_vfs) {
1cdd1ec8 3389 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3390 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3391 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3392 IXGBE_VMOLR_ROPE);
3393 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3394 }
3395
3396 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3397
3398 if (netdev->features & NETIF_F_HW_VLAN_RX)
3399 ixgbe_vlan_strip_enable(adapter);
3400 else
3401 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3402}
3403
021230d4
AV		 3404static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3405{
3406 int q_idx;
3407 struct ixgbe_q_vector *q_vector;
3408 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3409
3410 /* legacy and MSI only use one vector */
3411 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3412 q_vectors = 1;
3413
3414 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3415 struct napi_struct *napi;
7a921c93 3416 q_vector = adapter->q_vector[q_idx];
f0848276 3417 napi = &q_vector->napi;
91281fd3
AD		 3418 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3419 if (!q_vector->rxr_count || !q_vector->txr_count) {
3420 if (q_vector->txr_count == 1)
3421 napi->poll = &ixgbe_clean_txonly;
3422 else if (q_vector->rxr_count == 1)
3423 napi->poll = &ixgbe_clean_rxonly;
3424 }
3425 }
f0848276
JB		 3426
3427 napi_enable(napi);
021230d4
AV		 3428 }
3429}
3430
3431static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3432{
3433 int q_idx;
3434 struct ixgbe_q_vector *q_vector;
3435 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3436
3437 /* legacy and MSI only use one vector */
3438 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3439 q_vectors = 1;
3440
3441 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3442 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3443 napi_disable(&q_vector->napi);
3444 }
3445}
3446
7a6b6f51 3447#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3448/*
3449 * ixgbe_configure_dcb - Configure DCB hardware
3450 * @adapter: ixgbe adapter struct
3451 *
3452 * This is called by the driver on open to configure the DCB hardware.
3453 * This is also called by the gennetlink interface when reconfiguring
3454 * the DCB state.
3455 */
3456static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3457{
3458 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3459 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3460
67ebd791
AD		 3461 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3462 if (hw->mac.type == ixgbe_mac_82598EB)
3463 netif_set_gso_max_size(adapter->netdev, 65536);
3464 return;
3465 }
3466
3467 if (hw->mac.type == ixgbe_mac_82598EB)
3468 netif_set_gso_max_size(adapter->netdev, 32768);
3469
9806307a
JF		 3470#ifdef CONFIG_FCOE
3471 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3472 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3473#endif
3474
80ab193d 3475 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3476 DCB_TX_CONFIG);
80ab193d 3477 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3478 DCB_RX_CONFIG);
2f90b865 3479
2f90b865 3480 /* Enable VLAN tag insert/strip */
f62bbb5e 3481 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3482
2f90b865 3483 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3484
3485 /* reconfigure the hardware */
3486 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
2f90b865
AD		 3487}
3488
3489#endif
9a799d71
AK		 3490static void ixgbe_configure(struct ixgbe_adapter *adapter)
3491{
3492 struct net_device *netdev = adapter->netdev;
c4cf55e5 3493 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3494 int i;
3495
7a6b6f51 3496#ifdef CONFIG_IXGBE_DCB
67ebd791 3497 ixgbe_configure_dcb(adapter);
2f90b865 3498#endif
9a799d71 3499
f62bbb5e
JG		 3500 ixgbe_set_rx_mode(netdev);
3501 ixgbe_restore_vlan(adapter);
3502
eacd73f7
YZ		 3503#ifdef IXGBE_FCOE
3504 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3505 ixgbe_configure_fcoe(adapter);
3506
3507#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3508 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3509 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3510 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3511 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3512 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3513 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3514 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3515 }
933d41f1 3516 ixgbe_configure_virtualization(adapter);
c4cf55e5 3517
9a799d71
AK		 3518 ixgbe_configure_tx(adapter);
3519 ixgbe_configure_rx(adapter);
9a799d71
AK		 3520}
3521
e8e26350
PW		 3522static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3523{
3524 switch (hw->phy.type) {
3525 case ixgbe_phy_sfp_avago:
3526 case ixgbe_phy_sfp_ftl:
3527 case ixgbe_phy_sfp_intel:
3528 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3529 case ixgbe_phy_sfp_passive_tyco:
3530 case ixgbe_phy_sfp_passive_unknown:
3531 case ixgbe_phy_sfp_active_unknown:
3532 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3533 return true;
3534 default:
3535 return false;
3536 }
3537}
3538
0ecc061d 3539/**
e8e26350
PW		 3540 * ixgbe_sfp_link_config - set up SFP+ link
3541 * @adapter: pointer to private adapter struct
3542 **/
3543static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3544{
3545 struct ixgbe_hw *hw = &adapter->hw;
3546
3547 if (hw->phy.multispeed_fiber) {
3548 /*
3549 * In multispeed fiber setups, the device may not have
3550 * had a physical connection when the driver loaded.
3551 * If that's the case, the initial link configuration
3552 * couldn't get the MAC into 10G or 1G mode, so we'll
3553 * never have a link status change interrupt fire.
3554 * We need to try and force an autonegotiation
3555 * session, then bring up link.
3556 */
3557 hw->mac.ops.setup_sfp(hw);
3558 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3559 schedule_work(&adapter->multispeed_fiber_task);
3560 } else {
3561 /*
3562 * Direct Attach Cu and non-multispeed fiber modules
3563 * still need to be configured properly prior to
3564 * attempting link.
3565 */
3566 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3567 schedule_work(&adapter->sfp_config_module_task);
3568 }
3569}
3570
3571/**
3572 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3573 * @hw: pointer to private hardware struct
3574 *
3575 * Returns 0 on success, negative on failure
3576 **/
e8e26350 3577static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3578{
3579 u32 autoneg;
8620a103 3580 bool negotiation, link_up = false;
0ecc061d
PWJ		 3581 u32 ret = IXGBE_ERR_LINK_SETUP;
3582
3583 if (hw->mac.ops.check_link)
3584 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3585
3586 if (ret)
3587 goto link_cfg_out;
3588
3589 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3590 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3591 &negotiation);
0ecc061d
PWJ		 3592 if (ret)
3593 goto link_cfg_out;
3594
8620a103
MC		 3595 if (hw->mac.ops.setup_link)
3596 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3597link_cfg_out:
3598 return ret;
3599}
3600
a34bcfff 3601static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3602{
9a799d71 3603 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3604 u32 gpie = 0;
9a799d71 3605
9b471446 3606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3607 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3608 IXGBE_GPIE_OCD;
3609 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3610 /*
3611 * use EIAM to auto-mask when MSI-X interrupt is asserted
3612 * this saves a register write for every interrupt
3613 */
3614 switch (hw->mac.type) {
3615 case ixgbe_mac_82598EB:
3616 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3617 break;
3618 default:
3619 case ixgbe_mac_82599EB:
3620 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3621 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3622 break;
3623 }
3624 } else {
021230d4
AV		 3625 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3626 * specifically only auto mask tx and rx interrupts */
3627 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3628 }
9a799d71 3629
a34bcfff
AD		 3630 /* XXX: to interrupt immediately for EICS writes, enable this */
3631 /* gpie |= IXGBE_GPIE_EIMEN; */
3632
3633 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3634 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3635 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3636 }
3637
a34bcfff
AD		 3638 /* Enable fan failure interrupt */
3639 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3640 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3641
a34bcfff 3642 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3643 gpie |= IXGBE_SDP1_GPIEN;
3644 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3645
3646 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3647}
3648
3649static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3650{
3651 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3652 int err;
a34bcfff
AD		 3653 u32 ctrl_ext;
3654
3655 ixgbe_get_hw_control(adapter);
3656 ixgbe_setup_gpie(adapter);
e8e26350 3657
9a799d71
AK		 3658 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3659 ixgbe_configure_msix(adapter);
3660 else
3661 ixgbe_configure_msi_and_legacy(adapter);
3662
61fac744 3663 /* enable the optics */
e3de4b7b 3664 if (hw->phy.multispeed_fiber && hw->mac.ops.enable_tx_laser)
61fac744
PW		 3665 hw->mac.ops.enable_tx_laser(hw);
3666
9a799d71 3667 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3668 ixgbe_napi_enable_all(adapter);
3669
73c4b7cd
AD		 3670 if (ixgbe_is_sfp(hw)) {
3671 ixgbe_sfp_link_config(adapter);
3672 } else {
3673 err = ixgbe_non_sfp_link_config(hw);
3674 if (err)
3675 e_err(probe, "link_config FAILED %d\n", err);
3676 }
3677
021230d4
AV		 3678 /* clear any pending interrupts, may auto mask */
3679 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3680 ixgbe_irq_enable(adapter, true, true);
9a799d71 3681
bf069c97
DS		 3682 /*
3683 * If this adapter has a fan, check to see if we had a failure
3684 * before we enabled the interrupt.
3685 */
3686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3687 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3688 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3689 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3690 }
3691
e8e26350
PW		 3692 /*
3693 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3694 * arrived before interrupts were enabled but after probe. Such
3695 * devices wouldn't have their type identified yet. We need to
3696 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3697 * If we're not hot-pluggable SFP+, we just need to configure link
3698 * and bring it up.
3699 */
73c4b7cd
AD		 3700 if (hw->phy.type == ixgbe_phy_unknown)
3701 schedule_work(&adapter->sfp_config_module_task);
0ecc061d 3702
1da100bb 3703 /* enable transmits */
477de6ed 3704 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3705
9a799d71
AK		 3706 /* bring the link up in the watchdog, this could race with our first
3707 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3708 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3709 adapter->link_check_timeout = jiffies;
9a799d71 3710 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3711
3712 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3713 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3714 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3715 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3716
9a799d71
AK		 3717 return 0;
3718}
3719
d4f80882
AV		 3720void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3721{
3722 WARN_ON(in_interrupt());
3723 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3724 msleep(1);
3725 ixgbe_down(adapter);
5809a1ae
GR		 3726 /*
3727 * If SR-IOV enabled then wait a bit before bringing the adapter
3728 * back up to give the VFs time to respond to the reset. The
3729 * two second wait is based upon the watchdog timer cycle in
3730 * the VF driver.
3731 */
3732 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3733 msleep(2000);
d4f80882
AV		 3734 ixgbe_up(adapter);
3735 clear_bit(__IXGBE_RESETTING, &adapter->state);
3736}
3737
9a799d71
AK		 3738int ixgbe_up(struct ixgbe_adapter *adapter)
3739{
3740 /* hardware has been reset, we need to reload some things */
3741 ixgbe_configure(adapter);
3742
3743 return ixgbe_up_complete(adapter);
3744}
3745
3746void ixgbe_reset(struct ixgbe_adapter *adapter)
3747{
c44ade9e 3748 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3749 int err;
3750
3751 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3752 switch (err) {
3753 case 0:
3754 case IXGBE_ERR_SFP_NOT_PRESENT:
3755 break;
3756 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3757 e_dev_err("master disable timed out\n");
da4dd0f7 3758 break;
794caeb2
PWJ		 3759 case IXGBE_ERR_EEPROM_VERSION:
3760 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3761 e_dev_warn("This device is a pre-production adapter/LOM. "
3762 "Please be aware there may be issuesassociated with "
3763 "your hardware. If you are experiencing problems "
3764 "please contact your Intel or hardware "
3765 "representative who provided you with this "
3766 "hardware.\n");
794caeb2 3767 break;
da4dd0f7 3768 default:
849c4542 3769 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3770 }
9a799d71
AK		 3771
3772 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3773 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3774 IXGBE_RAH_AV);
9a799d71
AK		 3775}
3776
9a799d71
AK		 3777/**
3778 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3779 * @rx_ring: ring to free buffers from
3780 **/
b6ec895e 3781static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3782{
b6ec895e 3783 struct device *dev = rx_ring->dev;
9a799d71 3784 unsigned long size;
b6ec895e 3785 u16 i;
9a799d71 3786
84418e3b
AD		 3787 /* ring already cleared, nothing to do */
3788 if (!rx_ring->rx_buffer_info)
3789 return;
9a799d71 3790
84418e3b 3791 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3792 for (i = 0; i < rx_ring->count; i++) {
3793 struct ixgbe_rx_buffer *rx_buffer_info;
3794
3795 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3796 if (rx_buffer_info->dma) {
b6ec895e 3797 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3798 rx_ring->rx_buf_len,
1b507730 3799 DMA_FROM_DEVICE);
9a799d71
AK		 3800 rx_buffer_info->dma = 0;
3801 }
3802 if (rx_buffer_info->skb) {
f8212f97 3803 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3804 rx_buffer_info->skb = NULL;
f8212f97
AD		 3805 do {
3806 struct sk_buff *this = skb;
e8171aaa 3807 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3808 dma_unmap_single(dev,
1b507730 3809 IXGBE_RSC_CB(this)->dma,
e8e9f696 3810 rx_ring->rx_buf_len,
1b507730 3811 DMA_FROM_DEVICE);
fd3686a8 3812 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3813 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3814 }
f8212f97
AD		 3815 skb = skb->prev;
3816 dev_kfree_skb(this);
3817 } while (skb);
9a799d71
AK		 3818 }
3819 if (!rx_buffer_info->page)
3820 continue;
4f57ca6e 3821 if (rx_buffer_info->page_dma) {
b6ec895e 3822 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3823 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3824 rx_buffer_info->page_dma = 0;
3825 }
9a799d71
AK		 3826 put_page(rx_buffer_info->page);
3827 rx_buffer_info->page = NULL;
762f4c57 3828 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3829 }
3830
3831 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3832 memset(rx_ring->rx_buffer_info, 0, size);
3833
3834 /* Zero out the descriptor ring */
3835 memset(rx_ring->desc, 0, rx_ring->size);
3836
3837 rx_ring->next_to_clean = 0;
3838 rx_ring->next_to_use = 0;
9a799d71
AK		 3839}
3840
3841/**
3842 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3843 * @tx_ring: ring to be cleaned
3844 **/
b6ec895e 3845static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3846{
3847 struct ixgbe_tx_buffer *tx_buffer_info;
3848 unsigned long size;
b6ec895e 3849 u16 i;
9a799d71 3850
84418e3b
AD		 3851 /* ring already cleared, nothing to do */
3852 if (!tx_ring->tx_buffer_info)
3853 return;
9a799d71 3854
84418e3b 3855 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3856 for (i = 0; i < tx_ring->count; i++) {
3857 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3858 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3859 }
3860
3861 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3862 memset(tx_ring->tx_buffer_info, 0, size);
3863
3864 /* Zero out the descriptor ring */
3865 memset(tx_ring->desc, 0, tx_ring->size);
3866
3867 tx_ring->next_to_use = 0;
3868 tx_ring->next_to_clean = 0;
9a799d71
AK		 3869}
3870
3871/**
021230d4 3872 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3873 * @adapter: board private structure
3874 **/
021230d4 3875static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3876{
3877 int i;
3878
021230d4 3879 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3880 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3881}
3882
3883/**
021230d4 3884 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3885 * @adapter: board private structure
3886 **/
021230d4 3887static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3888{
3889 int i;
3890
021230d4 3891 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3892 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3893}
3894
3895void ixgbe_down(struct ixgbe_adapter *adapter)
3896{
3897 struct net_device *netdev = adapter->netdev;
7f821875 3898 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3899 u32 rxctrl;
7f821875 3900 u32 txdctl;
bf29ee6c 3901 int i;
b25ebfd2 3902 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3903
3904 /* signal that we are down to the interrupt handler */
3905 set_bit(__IXGBE_DOWN, &adapter->state);
3906
767081ad
GR		 3907 /* disable receive for all VFs and wait one second */
3908 if (adapter->num_vfs) {
767081ad
GR		 3909 /* ping all the active vfs to let them know we are going down */
3910 ixgbe_ping_all_vfs(adapter);
581d1aa7 3911
767081ad
GR		 3912 /* Disable all VFTE/VFRE TX/RX */
3913 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3914
3915 /* Mark all the VFs as inactive */
3916 for (i = 0 ; i < adapter->num_vfs; i++)
3917 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3918 }
3919
9a799d71 3920 /* disable receives */
7f821875
JB		 3921 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3922 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3923
7f821875 3924 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3925 msleep(10);
3926
7f821875
JB		 3927 netif_tx_stop_all_queues(netdev);
3928
0a1f87cb
DS		 3929 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3930 del_timer_sync(&adapter->sfp_timer);
9a799d71 3931 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3932 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3933
c0dfb90e
JF		 3934 netif_carrier_off(netdev);
3935 netif_tx_disable(netdev);
3936
3937 ixgbe_irq_disable(adapter);
3938
3939 ixgbe_napi_disable_all(adapter);
3940
b25ebfd2
PW		 3941 /* Cleanup the affinity_hint CPU mask memory and callback */
3942 for (i = 0; i < num_q_vectors; i++) {
3943 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3944 /* clear the affinity_mask in the IRQ descriptor */
3945 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3946 /* release the CPU mask memory */
3947 free_cpumask_var(q_vector->affinity_mask);
3948 }
3949
c4cf55e5
PWJ		 3950 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3951 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3952 cancel_work_sync(&adapter->fdir_reinit_task);
3953
119fc60a
MC		 3954 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3955 cancel_work_sync(&adapter->check_overtemp_task);
3956
7f821875
JB		 3957 /* disable transmits in the hardware now that interrupts are off */
3958 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 3959 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3960 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3961 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 3962 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3963 }
88512539 3964 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 3965 switch (hw->mac.type) {
3966 case ixgbe_mac_82599EB:
88512539 3967 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3968 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3969 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 3970 break;
3971 default:
3972 break;
3973 }
7f821875 3974
9f756f01 3975 /* power down the optics */
e3de4b7b 3976 if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
9f756f01
JF		 3977 hw->mac.ops.disable_tx_laser(hw);
3978
9a713e7c
PW		 3979 /* clear n-tuple filters that are cached */
3980 ethtool_ntuple_flush(netdev);
3981
6f4a0e45
PL		 3982 if (!pci_channel_offline(adapter->pdev))
3983 ixgbe_reset(adapter);
9a799d71
AK		 3984 ixgbe_clean_all_tx_rings(adapter);
3985 ixgbe_clean_all_rx_rings(adapter);
3986
5dd2d332 3987#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3988 /* since we reset the hardware DCA settings were cleared */
e35ec126 3989 ixgbe_setup_dca(adapter);
96b0e0f6 3990#endif
9a799d71
AK		 3991}
3992
9a799d71 3993/**
021230d4
AV		 3994 * ixgbe_poll - NAPI Rx polling callback
3995 * @napi: structure for representing this polling device
3996 * @budget: how many packets driver is allowed to clean
3997 *
3998 * This function is used for legacy and MSI, NAPI mode
9a799d71 3999 **/
021230d4 4000static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4001{
9a1a69ad 4002 struct ixgbe_q_vector *q_vector =
e8e9f696 4003 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4004 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4005 int tx_clean_complete, work_done = 0;
9a799d71 4006
5dd2d332 4007#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4008 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4009 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4010#endif
4011
4a0b9ca0
PW		 4012 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4013 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4014
9a1a69ad 4015 if (!tx_clean_complete)
d2c7ddd6
DM		 4016 work_done = budget;
4017
53e52c72
DM		 4018 /* If budget not fully consumed, exit the polling mode */
4019 if (work_done < budget) {
288379f0 4020 napi_complete(napi);
f7554a2b 4021 if (adapter->rx_itr_setting & 1)
f494e8fa 4022 ixgbe_set_itr(adapter);
d4f80882 4023 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4024 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4025 }
9a799d71
AK		 4026 return work_done;
4027}
4028
4029/**
4030 * ixgbe_tx_timeout - Respond to a Tx Hang
4031 * @netdev: network interface device structure
4032 **/
4033static void ixgbe_tx_timeout(struct net_device *netdev)
4034{
4035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4036
4037 /* Do the reset outside of interrupt context */
4038 schedule_work(&adapter->reset_task);
4039}
4040
4041static void ixgbe_reset_task(struct work_struct *work)
4042{
4043 struct ixgbe_adapter *adapter;
4044 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4045
2f90b865
AD		 4046 /* If we're already down or resetting, just bail */
4047 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4048 test_bit(__IXGBE_RESETTING, &adapter->state))
4049 return;
4050
9a799d71
AK		 4051 adapter->tx_timeout_count++;
4052
dcd79aeb
TI		 4053 ixgbe_dump(adapter);
4054 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4055 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4056}
4057
bc97114d
PWJ		 4058#ifdef CONFIG_IXGBE_DCB
4059static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 4060{
bc97114d 4061 bool ret = false;
0cefafad 4062 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 4063
0cefafad
JB		 4064 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4065 return ret;
4066
4067 f->mask = 0x7 << 3;
4068 adapter->num_rx_queues = f->indices;
4069 adapter->num_tx_queues = f->indices;
4070 ret = true;
2f90b865 4071
bc97114d
PWJ		 4072 return ret;
4073}
4074#endif
4075
4df10466
JB		 4076/**
4077 * ixgbe_set_rss_queues: Allocate queues for RSS
4078 * @adapter: board private structure to initialize
4079 *
4080 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4081 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4082 *
4083 **/
bc97114d
PWJ		 4084static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4085{
4086 bool ret = false;
0cefafad 4087 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4088
4089 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4090 f->mask = 0xF;
4091 adapter->num_rx_queues = f->indices;
4092 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4093 ret = true;
4094 } else {
bc97114d 4095 ret = false;
b9804972
JB		 4096 }
4097
bc97114d
PWJ		 4098 return ret;
4099}
4100
c4cf55e5
PWJ		 4101/**
4102 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4103 * @adapter: board private structure to initialize
4104 *
4105 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4106 * to the original CPU that initiated the Tx session. This runs in addition
4107 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4108 * Rx load across CPUs using RSS.
4109 *
4110 **/
e8e9f696 4111static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4112{
4113 bool ret = false;
4114 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4115
4116 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4117 f_fdir->mask = 0;
4118
4119 /* Flow Director must have RSS enabled */
4120 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4121 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4122 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4123 adapter->num_tx_queues = f_fdir->indices;
4124 adapter->num_rx_queues = f_fdir->indices;
4125 ret = true;
4126 } else {
4127 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4128 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4129 }
4130 return ret;
4131}
4132
0331a832
YZ		 4133#ifdef IXGBE_FCOE
4134/**
4135 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4136 * @adapter: board private structure to initialize
4137 *
4138 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4139 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4140 * rx queues out of the max number of rx queues, instead, it is used as the
4141 * index of the first rx queue used by FCoE.
4142 *
4143 **/
4144static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4145{
4146 bool ret = false;
4147 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4148
4149 f->indices = min((int)num_online_cpus(), f->indices);
4150 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4151 adapter->num_rx_queues = 1;
4152 adapter->num_tx_queues = 1;
0331a832
YZ		 4153#ifdef CONFIG_IXGBE_DCB
4154 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4155 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4156 ixgbe_set_dcb_queues(adapter);
4157 }
4158#endif
4159 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4160 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4161 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4162 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4163 ixgbe_set_fdir_queues(adapter);
4164 else
4165 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4166 }
4167 /* adding FCoE rx rings to the end */
4168 f->mask = adapter->num_rx_queues;
4169 adapter->num_rx_queues += f->indices;
8de8b2e6 4170 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4171
4172 ret = true;
4173 }
4174
4175 return ret;
4176}
4177
4178#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4179/**
4180 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4181 * @adapter: board private structure to initialize
4182 *
4183 * IOV doesn't actually use anything, so just NAK the
4184 * request for now and let the other queue routines
4185 * figure out what to do.
4186 */
4187static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4188{
4189 return false;
4190}
4191
4df10466
JB		 4192/*
4193 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4194 * @adapter: board private structure to initialize
4195 *
4196 * This is the top level queue allocation routine. The order here is very
4197 * important, starting with the "most" number of features turned on at once,
4198 * and ending with the smallest set of features. This way large combinations
4199 * can be allocated if they're turned on, and smaller combinations are the
4200 * fallthrough conditions.
4201 *
4202 **/
847f53ff 4203static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4204{
1cdd1ec8
GR		 4205 /* Start with base case */
4206 adapter->num_rx_queues = 1;
4207 adapter->num_tx_queues = 1;
4208 adapter->num_rx_pools = adapter->num_rx_queues;
4209 adapter->num_rx_queues_per_pool = 1;
4210
4211 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4212 goto done;
1cdd1ec8 4213
0331a832
YZ		 4214#ifdef IXGBE_FCOE
4215 if (ixgbe_set_fcoe_queues(adapter))
4216 goto done;
4217
4218#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4219#ifdef CONFIG_IXGBE_DCB
4220 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4221 goto done;
bc97114d
PWJ		 4222
4223#endif
c4cf55e5
PWJ		 4224 if (ixgbe_set_fdir_queues(adapter))
4225 goto done;
4226
bc97114d 4227 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4228 goto done;
4229
4230 /* fallback to base case */
4231 adapter->num_rx_queues = 1;
4232 adapter->num_tx_queues = 1;
4233
4234done:
847f53ff 4235 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4236 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4237 return netif_set_real_num_rx_queues(adapter->netdev,
4238 adapter->num_rx_queues);
b9804972
JB		 4239}
4240
021230d4 4241static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4242 int vectors)
021230d4
AV		 4243{
4244 int err, vector_threshold;
4245
4246 /* We'll want at least 3 (vector_threshold):
4247 * 1) TxQ[0] Cleanup
4248 * 2) RxQ[0] Cleanup
4249 * 3) Other (Link Status Change, etc.)
4250 * 4) TCP Timer (optional)
4251 */
4252 vector_threshold = MIN_MSIX_COUNT;
4253
4254 /* The more we get, the more we will assign to Tx/Rx Cleanup
4255 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4256 * Right now, we simply care about how many we'll get; we'll
4257 * set them up later while requesting irq's.
4258 */
4259 while (vectors >= vector_threshold) {
4260 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4261 vectors);
021230d4
AV		 4262 if (!err) /* Success in acquiring all requested vectors. */
4263 break;
4264 else if (err < 0)
4265 vectors = 0; /* Nasty failure, quit now */
4266 else /* err == number of vectors we should try again with */
4267 vectors = err;
4268 }
4269
4270 if (vectors < vector_threshold) {
4271 /* Can't allocate enough MSI-X interrupts? Oh well.
4272 * This just means we'll go with either a single MSI
4273 * vector or fall back to legacy interrupts.
4274 */
849c4542
ET		 4275 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4276 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4277 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4278 kfree(adapter->msix_entries);
4279 adapter->msix_entries = NULL;
021230d4
AV		 4280 } else {
4281 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4282 /*
4283 * Adjust for only the vectors we'll use, which is minimum
4284 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4285 * vectors we were allocated.
4286 */
4287 adapter->num_msix_vectors = min(vectors,
e8e9f696 4288 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4289 }
4290}
4291
021230d4 4292/**
bc97114d 4293 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4294 * @adapter: board private structure to initialize
4295 *
bc97114d
PWJ		 4296 * Cache the descriptor ring offsets for RSS to the assigned rings.
4297 *
021230d4 4298 **/
bc97114d 4299static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4300{
bc97114d 4301 int i;
bc97114d 4302
9d6b758f
AD		 4303 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4304 return false;
bc97114d 4305
9d6b758f
AD		 4306 for (i = 0; i < adapter->num_rx_queues; i++)
4307 adapter->rx_ring[i]->reg_idx = i;
4308 for (i = 0; i < adapter->num_tx_queues; i++)
4309 adapter->tx_ring[i]->reg_idx = i;
4310
4311 return true;
bc97114d
PWJ		 4312}
4313
4314#ifdef CONFIG_IXGBE_DCB
4315/**
4316 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4317 * @adapter: board private structure to initialize
4318 *
4319 * Cache the descriptor ring offsets for DCB to the assigned rings.
4320 *
4321 **/
4322static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4323{
4324 int i;
4325 bool ret = false;
4326 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4327
bd508178
AD		 4328 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4329 return false;
f92ef202 4330
bd508178
AD		 4331 /* the number of queues is assumed to be symmetric */
4332 switch (adapter->hw.mac.type) {
4333 case ixgbe_mac_82598EB:
4334 for (i = 0; i < dcb_i; i++) {
4335 adapter->rx_ring[i]->reg_idx = i << 3;
4336 adapter->tx_ring[i]->reg_idx = i << 2;
4337 }
4338 ret = true;
4339 break;
4340 case ixgbe_mac_82599EB:
4341 if (dcb_i == 8) {
4342 /*
4343 * Tx TC0 starts at: descriptor queue 0
4344 * Tx TC1 starts at: descriptor queue 32
4345 * Tx TC2 starts at: descriptor queue 64
4346 * Tx TC3 starts at: descriptor queue 80
4347 * Tx TC4 starts at: descriptor queue 96
4348 * Tx TC5 starts at: descriptor queue 104
4349 * Tx TC6 starts at: descriptor queue 112
4350 * Tx TC7 starts at: descriptor queue 120
4351 *
4352 * Rx TC0-TC7 are offset by 16 queues each
4353 */
4354 for (i = 0; i < 3; i++) {
4355 adapter->tx_ring[i]->reg_idx = i << 5;
4356 adapter->rx_ring[i]->reg_idx = i << 4;
e8e26350 4357 }
bd508178
AD		 4358 for ( ; i < 5; i++) {
4359 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4360 adapter->rx_ring[i]->reg_idx = i << 4;
4361 }
4362 for ( ; i < dcb_i; i++) {
4363 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4364 adapter->rx_ring[i]->reg_idx = i << 4;
4365 }
4366 ret = true;
4367 } else if (dcb_i == 4) {
4368 /*
4369 * Tx TC0 starts at: descriptor queue 0
4370 * Tx TC1 starts at: descriptor queue 64
4371 * Tx TC2 starts at: descriptor queue 96
4372 * Tx TC3 starts at: descriptor queue 112
4373 *
4374 * Rx TC0-TC3 are offset by 32 queues each
4375 */
4376 adapter->tx_ring[0]->reg_idx = 0;
4377 adapter->tx_ring[1]->reg_idx = 64;
4378 adapter->tx_ring[2]->reg_idx = 96;
4379 adapter->tx_ring[3]->reg_idx = 112;
4380 for (i = 0 ; i < dcb_i; i++)
4381 adapter->rx_ring[i]->reg_idx = i << 5;
4382 ret = true;
021230d4 4383 }
bd508178
AD		 4384 break;
4385 default:
4386 break;
021230d4 4387 }
bc97114d
PWJ		 4388 return ret;
4389}
4390#endif
4391
c4cf55e5
PWJ		 4392/**
4393 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4394 * @adapter: board private structure to initialize
4395 *
4396 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4397 *
4398 **/
e8e9f696 4399static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4400{
4401 int i;
4402 bool ret = false;
4403
4404 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4405 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4406 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4407 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4408 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4409 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4410 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4411 ret = true;
4412 }
4413
4414 return ret;
4415}
4416
0331a832
YZ		 4417#ifdef IXGBE_FCOE
4418/**
4419 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4420 * @adapter: board private structure to initialize
4421 *
4422 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4423 *
4424 */
4425static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4426{
0331a832 4427 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4428 int i;
4429 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4430
4431 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4432 return false;
0331a832 4433
0331a832 4434#ifdef CONFIG_IXGBE_DCB
bf29ee6c
AD		 4435 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4436 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
8de8b2e6 4437
bf29ee6c
AD		 4438 ixgbe_cache_ring_dcb(adapter);
4439 /* find out queues in TC for FCoE */
4440 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4441 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4442 /*
4443 * In 82599, the number of Tx queues for each traffic
4444 * class for both 8-TC and 4-TC modes are:
4445 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4446 * 8 TCs: 32 32 16 16 8 8 8 8
4447 * 4 TCs: 64 64 32 32
4448 * We have max 8 queues for FCoE, where 8 the is
4449 * FCoE redirection table size. If TC for FCoE is
4450 * less than or equal to TC3, we have enough queues
4451 * to add max of 8 queues for FCoE, so we start FCoE
4452 * Tx queue from the next one, i.e., reg_idx + 1.
4453 * If TC for FCoE is above TC3, implying 8 TC mode,
4454 * and we need 8 for FCoE, we have to take all queues
4455 * in that traffic class for FCoE.
4456 */
4457 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4458 fcoe_tx_i--;
4459 }
0331a832 4460#endif /* CONFIG_IXGBE_DCB */
bf29ee6c
AD		 4461 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4462 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4463 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4464 ixgbe_cache_ring_fdir(adapter);
4465 else
4466 ixgbe_cache_ring_rss(adapter);
8faa2a78 4467
bf29ee6c
AD		 4468 fcoe_rx_i = f->mask;
4469 fcoe_tx_i = f->mask;
0331a832 4470 }
bf29ee6c
AD		 4471 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4472 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4473 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4474 }
4475 return true;
0331a832
YZ		 4476}
4477
4478#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4479/**
4480 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4481 * @adapter: board private structure to initialize
4482 *
4483 * SR-IOV doesn't use any descriptor rings but changes the default if
4484 * no other mapping is used.
4485 *
4486 */
4487static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4488{
4a0b9ca0
PW		 4489 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4490 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4491 if (adapter->num_vfs)
4492 return true;
4493 else
4494 return false;
4495}
4496
bc97114d
PWJ		 4497/**
4498 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4499 * @adapter: board private structure to initialize
4500 *
4501 * Once we know the feature-set enabled for the device, we'll cache
4502 * the register offset the descriptor ring is assigned to.
4503 *
4504 * Note, the order the various feature calls is important. It must start with
4505 * the "most" features enabled at the same time, then trickle down to the
4506 * least amount of features turned on at once.
4507 **/
4508static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4509{
4510 /* start with default case */
4a0b9ca0
PW		 4511 adapter->rx_ring[0]->reg_idx = 0;
4512 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4513
1cdd1ec8
GR		 4514 if (ixgbe_cache_ring_sriov(adapter))
4515 return;
4516
0331a832
YZ		 4517#ifdef IXGBE_FCOE
4518 if (ixgbe_cache_ring_fcoe(adapter))
4519 return;
4520
4521#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4522#ifdef CONFIG_IXGBE_DCB
4523 if (ixgbe_cache_ring_dcb(adapter))
4524 return;
4525
4526#endif
c4cf55e5
PWJ		 4527 if (ixgbe_cache_ring_fdir(adapter))
4528 return;
4529
bc97114d
PWJ		 4530 if (ixgbe_cache_ring_rss(adapter))
4531 return;
021230d4
AV		 4532}
4533
9a799d71
AK		 4534/**
4535 * ixgbe_alloc_queues - Allocate memory for all rings
4536 * @adapter: board private structure to initialize
4537 *
4538 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4539 * number of queues at compile-time. The polling_netdev array is
4540 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4541 **/
2f90b865 4542static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4543{
4544 int i;
b6ec895e 4545 int rx_count;
4a0b9ca0 4546 int orig_node = adapter->node;
9a799d71 4547
021230d4 4548 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4549 struct ixgbe_ring *ring = adapter->tx_ring[i];
4550 if (orig_node == -1) {
4551 int cur_node = next_online_node(adapter->node);
4552 if (cur_node == MAX_NUMNODES)
4553 cur_node = first_online_node;
4554 adapter->node = cur_node;
4555 }
4556 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4557 adapter->node);
4a0b9ca0
PW		 4558 if (!ring)
4559 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4560 if (!ring)
4561 goto err_tx_ring_allocation;
4562 ring->count = adapter->tx_ring_count;
4563 ring->queue_index = i;
b6ec895e 4564 ring->dev = &adapter->pdev->dev;
fc77dc3c 4565 ring->netdev = adapter->netdev;
4a0b9ca0
PW		 4566 ring->numa_node = adapter->node;
4567
4568 adapter->tx_ring[i] = ring;
021230d4 4569 }
b9804972 4570
4a0b9ca0
PW		 4571 /* Restore the adapter's original node */
4572 adapter->node = orig_node;
4573
b6ec895e 4574 rx_count = adapter->rx_ring_count;
9a799d71 4575 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4576 struct ixgbe_ring *ring = adapter->rx_ring[i];
4577 if (orig_node == -1) {
4578 int cur_node = next_online_node(adapter->node);
4579 if (cur_node == MAX_NUMNODES)
4580 cur_node = first_online_node;
4581 adapter->node = cur_node;
4582 }
4583 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4584 adapter->node);
4a0b9ca0
PW		 4585 if (!ring)
4586 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4587 if (!ring)
4588 goto err_rx_ring_allocation;
b6ec895e 4589 ring->count = rx_count;
4a0b9ca0 4590 ring->queue_index = i;
b6ec895e 4591 ring->dev = &adapter->pdev->dev;
fc77dc3c 4592 ring->netdev = adapter->netdev;
4a0b9ca0
PW		 4593 ring->numa_node = adapter->node;
4594
4595 adapter->rx_ring[i] = ring;
021230d4
AV		 4596 }
4597
4a0b9ca0
PW		 4598 /* Restore the adapter's original node */
4599 adapter->node = orig_node;
4600
021230d4
AV		 4601 ixgbe_cache_ring_register(adapter);
4602
4603 return 0;
4604
4605err_rx_ring_allocation:
4a0b9ca0
PW		 4606 for (i = 0; i < adapter->num_tx_queues; i++)
4607 kfree(adapter->tx_ring[i]);
021230d4
AV		 4608err_tx_ring_allocation:
4609 return -ENOMEM;
4610}
4611
4612/**
4613 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4614 * @adapter: board private structure to initialize
4615 *
4616 * Attempt to configure the interrupts using the best available
4617 * capabilities of the hardware and the kernel.
4618 **/
feea6a57 4619static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4620{
8be0e467 4621 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4622 int err = 0;
4623 int vector, v_budget;
4624
4625 /*
4626 * It's easy to be greedy for MSI-X vectors, but it really
4627 * doesn't do us much good if we have a lot more vectors
4628 * than CPU's. So let's be conservative and only ask for
342bde1b 4629 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4630 */
4631 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4632 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4633
4634 /*
4635 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4636 * hw.mac->max_msix_vectors vectors. With features
4637 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4638 * descriptor queues supported by our device. Thus, we cap it off in
4639 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4640 */
8be0e467 4641 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4642
4643 /* A failure in MSI-X entry allocation isn't fatal, but it does
4644 * mean we disable MSI-X capabilities of the adapter. */
4645 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4646 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4647 if (adapter->msix_entries) {
4648 for (vector = 0; vector < v_budget; vector++)
4649 adapter->msix_entries[vector].entry = vector;
021230d4 4650
7a921c93 4651 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4652
7a921c93
AD		 4653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4654 goto out;
4655 }
26d27844 4656
7a921c93
AD		 4657 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4658 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4659 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4660 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4661 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4662 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4663 ixgbe_disable_sriov(adapter);
4664
847f53ff
BH		 4665 err = ixgbe_set_num_queues(adapter);
4666 if (err)
4667 return err;
021230d4 4668
021230d4
AV		 4669 err = pci_enable_msi(adapter->pdev);
4670 if (!err) {
4671 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4672 } else {
849c4542
ET		 4673 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4674 "Unable to allocate MSI interrupt, "
4675 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4676 /* reset err */
4677 err = 0;
4678 }
4679
4680out:
021230d4
AV		 4681 return err;
4682}
4683
7a921c93
AD		 4684/**
4685 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4686 * @adapter: board private structure to initialize
4687 *
4688 * We allocate one q_vector per queue interrupt. If allocation fails we
4689 * return -ENOMEM.
4690 **/
4691static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4692{
4693 int q_idx, num_q_vectors;
4694 struct ixgbe_q_vector *q_vector;
4695 int napi_vectors;
4696 int (*poll)(struct napi_struct *, int);
4697
4698 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4699 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4700 napi_vectors = adapter->num_rx_queues;
91281fd3 4701 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4702 } else {
4703 num_q_vectors = 1;
4704 napi_vectors = 1;
4705 poll = &ixgbe_poll;
4706 }
4707
4708 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4709 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4710 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4711 if (!q_vector)
4712 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4713 GFP_KERNEL);
7a921c93
AD		 4714 if (!q_vector)
4715 goto err_out;
4716 q_vector->adapter = adapter;
f7554a2b
NS		 4717 if (q_vector->txr_count && !q_vector->rxr_count)
4718 q_vector->eitr = adapter->tx_eitr_param;
4719 else
4720 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4721 q_vector->v_idx = q_idx;
91281fd3 4722 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4723 adapter->q_vector[q_idx] = q_vector;
4724 }
4725
4726 return 0;
4727
4728err_out:
4729 while (q_idx) {
4730 q_idx--;
4731 q_vector = adapter->q_vector[q_idx];
4732 netif_napi_del(&q_vector->napi);
4733 kfree(q_vector);
4734 adapter->q_vector[q_idx] = NULL;
4735 }
4736 return -ENOMEM;
4737}
4738
4739/**
4740 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4741 * @adapter: board private structure to initialize
4742 *
4743 * This function frees the memory allocated to the q_vectors. In addition if
4744 * NAPI is enabled it will delete any references to the NAPI struct prior
4745 * to freeing the q_vector.
4746 **/
4747static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4748{
4749 int q_idx, num_q_vectors;
7a921c93 4750
91281fd3 4751 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4752 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4753 else
7a921c93 4754 num_q_vectors = 1;
7a921c93
AD		 4755
4756 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4757 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4758 adapter->q_vector[q_idx] = NULL;
91281fd3 4759 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4760 kfree(q_vector);
4761 }
4762}
4763
7b25cdba 4764static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4765{
4766 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4767 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4768 pci_disable_msix(adapter->pdev);
4769 kfree(adapter->msix_entries);
4770 adapter->msix_entries = NULL;
4771 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4772 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4773 pci_disable_msi(adapter->pdev);
4774 }
021230d4
AV		 4775}
4776
4777/**
4778 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4779 * @adapter: board private structure to initialize
4780 *
4781 * We determine which interrupt scheme to use based on...
4782 * - Kernel support (MSI, MSI-X)
4783 * - which can be user-defined (via MODULE_PARAM)
4784 * - Hardware queue count (num_*_queues)
4785 * - defined by miscellaneous hardware support/features (RSS, etc.)
4786 **/
2f90b865 4787int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4788{
4789 int err;
4790
4791 /* Number of supported queues */
847f53ff
BH		 4792 err = ixgbe_set_num_queues(adapter);
4793 if (err)
4794 return err;
021230d4 4795
021230d4
AV		 4796 err = ixgbe_set_interrupt_capability(adapter);
4797 if (err) {
849c4542 4798 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4799 goto err_set_interrupt;
9a799d71
AK		 4800 }
4801
7a921c93
AD		 4802 err = ixgbe_alloc_q_vectors(adapter);
4803 if (err) {
849c4542 4804 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4805 goto err_alloc_q_vectors;
4806 }
4807
4808 err = ixgbe_alloc_queues(adapter);
4809 if (err) {
849c4542 4810 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4811 goto err_alloc_queues;
4812 }
4813
849c4542 4814 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4815 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4816 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4817
4818 set_bit(__IXGBE_DOWN, &adapter->state);
4819
9a799d71 4820 return 0;
021230d4 4821
7a921c93
AD		 4822err_alloc_queues:
4823 ixgbe_free_q_vectors(adapter);
4824err_alloc_q_vectors:
4825 ixgbe_reset_interrupt_capability(adapter);
021230d4 4826err_set_interrupt:
7a921c93
AD		 4827 return err;
4828}
4829
1a51502b
ED		 4830static void ring_free_rcu(struct rcu_head *head)
4831{
4832 kfree(container_of(head, struct ixgbe_ring, rcu));
4833}
4834
7a921c93
AD		 4835/**
4836 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4837 * @adapter: board private structure to clear interrupt scheme on
4838 *
4839 * We go through and clear interrupt specific resources and reset the structure
4840 * to pre-load conditions
4841 **/
4842void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4843{
4a0b9ca0
PW		 4844 int i;
4845
4846 for (i = 0; i < adapter->num_tx_queues; i++) {
4847 kfree(adapter->tx_ring[i]);
4848 adapter->tx_ring[i] = NULL;
4849 }
4850 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4851 struct ixgbe_ring *ring = adapter->rx_ring[i];
4852
4853 /* ixgbe_get_stats64() might access this ring, we must wait
4854 * a grace period before freeing it.
4855 */
4856 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 4857 adapter->rx_ring[i] = NULL;
4858 }
7a921c93
AD		 4859
4860 ixgbe_free_q_vectors(adapter);
4861 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4862}
4863
c4900be0
DS		 4864/**
4865 * ixgbe_sfp_timer - worker thread to find a missing module
4866 * @data: pointer to our adapter struct
4867 **/
4868static void ixgbe_sfp_timer(unsigned long data)
4869{
4870 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4871
4df10466
JB		 4872 /*
4873 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4874 * delays that sfp+ detection requires
4875 */
4876 schedule_work(&adapter->sfp_task);
4877}
4878
4879/**
4880 * ixgbe_sfp_task - worker thread to find a missing module
4881 * @work: pointer to work_struct containing our data
4882 **/
4883static void ixgbe_sfp_task(struct work_struct *work)
4884{
4885 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4886 struct ixgbe_adapter,
4887 sfp_task);
c4900be0
DS		 4888 struct ixgbe_hw *hw = &adapter->hw;
4889
4890 if ((hw->phy.type == ixgbe_phy_nl) &&
4891 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4892 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4893 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4894 goto reschedule;
4895 ret = hw->phy.ops.reset(hw);
4896 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4897 e_dev_err("failed to initialize because an unsupported "
4898 "SFP+ module type was detected.\n");
4899 e_dev_err("Reload the driver after installing a "
4900 "supported module.\n");
c4900be0
DS		 4901 unregister_netdev(adapter->netdev);
4902 } else {
396e799c 4903 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4904 }
4905 /* don't need this routine any more */
4906 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4907 }
4908 return;
4909reschedule:
4910 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4911 mod_timer(&adapter->sfp_timer,
e8e9f696 4912 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4913}
4914
9a799d71
AK		 4915/**
4916 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4917 * @adapter: board private structure to initialize
4918 *
4919 * ixgbe_sw_init initializes the Adapter private data structure.
4920 * Fields are initialized based on PCI device information and
4921 * OS network device settings (MTU size).
4922 **/
4923static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4924{
4925 struct ixgbe_hw *hw = &adapter->hw;
4926 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4927 struct net_device *dev = adapter->netdev;
021230d4 4928 unsigned int rss;
7a6b6f51 4929#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4930 int j;
4931 struct tc_configuration *tc;
4932#endif
16b61beb 4933 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4934
c44ade9e
JB		 4935 /* PCI config space info */
4936
4937 hw->vendor_id = pdev->vendor;
4938 hw->device_id = pdev->device;
4939 hw->revision_id = pdev->revision;
4940 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4941 hw->subsystem_device_id = pdev->subsystem_device;
4942
021230d4
AV		 4943 /* Set capability flags */
4944 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4945 adapter->ring_feature[RING_F_RSS].indices = rss;
4946 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4947 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 4948 switch (hw->mac.type) {
4949 case ixgbe_mac_82598EB:
bf069c97
DS		 4950 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4951 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4952 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 4953 break;
4954 case ixgbe_mac_82599EB:
e8e26350 4955 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4956 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4957 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4958 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4959 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4960 if (dev->features & NETIF_F_NTUPLE) {
4961 /* Flow Director perfect filter enabled */
4962 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4963 adapter->atr_sample_rate = 0;
4964 spin_lock_init(&adapter->fdir_perfect_lock);
4965 } else {
4966 /* Flow Director hash filters enabled */
4967 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4968 adapter->atr_sample_rate = 20;
4969 }
c4cf55e5 4970 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4971 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4972 adapter->fdir_pballoc = 0;
eacd73f7 4973#ifdef IXGBE_FCOE
0d551589
YZ		 4974 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4975 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4976 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4977#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4978 /* Default traffic class to use for FCoE */
4979 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4980 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4981#endif
eacd73f7 4982#endif /* IXGBE_FCOE */
bd508178
AD		 4983 break;
4984 default:
4985 break;
f8212f97 4986 }
2f90b865 4987
7a6b6f51 4988#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4989 /* Configure DCB traffic classes */
4990 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4991 tc = &adapter->dcb_cfg.tc_config[j];
4992 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4993 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4994 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4995 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4996 tc->dcb_pfc = pfc_disabled;
4997 }
4998 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4999 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5000 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5001 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 5002 adapter->dcb_cfg.round_robin_enable = false;
5003 adapter->dcb_set_bitmap = 0x00;
5004 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 5005 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 5006
5007#endif
9a799d71
AK		 5008
5009 /* default flow control settings */
cd7664f6 5010 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5011 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5012#ifdef CONFIG_DCB
5013 adapter->last_lfc_mode = hw->fc.current_mode;
5014#endif
16b61beb
JF		 5015 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5016 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5017 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5018 hw->fc.send_xon = true;
71fd570b 5019 hw->fc.disable_fc_autoneg = false;
9a799d71 5020
30efa5a3 5021 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5022 adapter->rx_itr_setting = 1;
5023 adapter->rx_eitr_param = 20000;
5024 adapter->tx_itr_setting = 1;
5025 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5026
5027 /* set defaults for eitr in MegaBytes */
5028 adapter->eitr_low = 10;
5029 adapter->eitr_high = 20;
5030
5031 /* set default ring sizes */
5032 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5033 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5034
9a799d71 5035 /* initialize eeprom parameters */
c44ade9e 5036 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5037 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5038 return -EIO;
5039 }
5040
021230d4 5041 /* enable rx csum by default */
9a799d71
AK		 5042 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5043
1a6c14a2
JB		 5044 /* get assigned NUMA node */
5045 adapter->node = dev_to_node(&pdev->dev);
5046
9a799d71
AK		 5047 set_bit(__IXGBE_DOWN, &adapter->state);
5048
5049 return 0;
5050}
5051
5052/**
5053 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5054 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5055 *
5056 * Return 0 on success, negative on failure
5057 **/
b6ec895e 5058int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5059{
b6ec895e 5060 struct device *dev = tx_ring->dev;
9a799d71
AK		 5061 int size;
5062
3a581073 5063 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 5064 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 5065 if (!tx_ring->tx_buffer_info)
5066 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 5067 if (!tx_ring->tx_buffer_info)
5068 goto err;
3a581073 5069 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 5070
5071 /* round up to nearest 4K */
12207e49 5072 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5073 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5074
b6ec895e 5075 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5076 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5077 if (!tx_ring->desc)
5078 goto err;
9a799d71 5079
3a581073
JB		 5080 tx_ring->next_to_use = 0;
5081 tx_ring->next_to_clean = 0;
5082 tx_ring->work_limit = tx_ring->count;
9a799d71 5083 return 0;
e01c31a5
JB		 5084
5085err:
5086 vfree(tx_ring->tx_buffer_info);
5087 tx_ring->tx_buffer_info = NULL;
b6ec895e 5088 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5089 return -ENOMEM;
9a799d71
AK		 5090}
5091
69888674
AD		 5092/**
5093 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5094 * @adapter: board private structure
5095 *
5096 * If this function returns with an error, then it's possible one or
5097 * more of the rings is populated (while the rest are not). It is the
5098 * callers duty to clean those orphaned rings.
5099 *
5100 * Return 0 on success, negative on failure
5101 **/
5102static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5103{
5104 int i, err = 0;
5105
5106 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5107 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5108 if (!err)
5109 continue;
396e799c 5110 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5111 break;
5112 }
5113
5114 return err;
5115}
5116
9a799d71
AK		 5117/**
5118 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5119 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5120 *
5121 * Returns 0 on success, negative on failure
5122 **/
b6ec895e 5123int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5124{
b6ec895e 5125 struct device *dev = rx_ring->dev;
021230d4 5126 int size;
9a799d71 5127
3a581073 5128 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
b6ec895e 5129 rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
1a6c14a2
JB		 5130 if (!rx_ring->rx_buffer_info)
5131 rx_ring->rx_buffer_info = vmalloc(size);
b6ec895e
AD		 5132 if (!rx_ring->rx_buffer_info)
5133 goto err;
3a581073 5134 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5135
9a799d71 5136 /* Round up to nearest 4K */
3a581073
JB		 5137 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5138 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5139
b6ec895e 5140 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5141 &rx_ring->dma, GFP_KERNEL);
9a799d71 5142
b6ec895e
AD		 5143 if (!rx_ring->desc)
5144 goto err;
9a799d71 5145
3a581073
JB		 5146 rx_ring->next_to_clean = 0;
5147 rx_ring->next_to_use = 0;
9a799d71
AK		 5148
5149 return 0;
b6ec895e
AD		 5150err:
5151 vfree(rx_ring->rx_buffer_info);
5152 rx_ring->rx_buffer_info = NULL;
5153 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5154 return -ENOMEM;
9a799d71
AK		 5155}
5156
69888674
AD		 5157/**
5158 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5159 * @adapter: board private structure
5160 *
5161 * If this function returns with an error, then it's possible one or
5162 * more of the rings is populated (while the rest are not). It is the
5163 * callers duty to clean those orphaned rings.
5164 *
5165 * Return 0 on success, negative on failure
5166 **/
69888674
AD		 5167static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5168{
5169 int i, err = 0;
5170
5171 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5172 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5173 if (!err)
5174 continue;
396e799c 5175 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5176 break;
5177 }
5178
5179 return err;
5180}
5181
9a799d71
AK		 5182/**
5183 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5184 * @tx_ring: Tx descriptor ring for a specific queue
5185 *
5186 * Free all transmit software resources
5187 **/
b6ec895e 5188void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5189{
b6ec895e 5190 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5191
5192 vfree(tx_ring->tx_buffer_info);
5193 tx_ring->tx_buffer_info = NULL;
5194
b6ec895e
AD		 5195 /* if not set, then don't free */
5196 if (!tx_ring->desc)
5197 return;
5198
5199 dma_free_coherent(tx_ring->dev, tx_ring->size,
5200 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5201
5202 tx_ring->desc = NULL;
5203}
5204
5205/**
5206 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5207 * @adapter: board private structure
5208 *
5209 * Free all transmit software resources
5210 **/
5211static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5212{
5213 int i;
5214
5215 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5216 if (adapter->tx_ring[i]->desc)
b6ec895e 5217 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5218}
5219
5220/**
b4617240 5221 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5222 * @rx_ring: ring to clean the resources from
5223 *
5224 * Free all receive software resources
5225 **/
b6ec895e 5226void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5227{
b6ec895e 5228 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5229
5230 vfree(rx_ring->rx_buffer_info);
5231 rx_ring->rx_buffer_info = NULL;
5232
b6ec895e
AD		 5233 /* if not set, then don't free */
5234 if (!rx_ring->desc)
5235 return;
5236
5237 dma_free_coherent(rx_ring->dev, rx_ring->size,
5238 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5239
5240 rx_ring->desc = NULL;
5241}
5242
5243/**
5244 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5245 * @adapter: board private structure
5246 *
5247 * Free all receive software resources
5248 **/
5249static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5250{
5251 int i;
5252
5253 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5254 if (adapter->rx_ring[i]->desc)
b6ec895e 5255 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5256}
5257
9a799d71
AK		 5258/**
5259 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5260 * @netdev: network interface device structure
5261 * @new_mtu: new value for maximum frame size
5262 *
5263 * Returns 0 on success, negative on failure
5264 **/
5265static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5266{
5267 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5268 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5269 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5270
42c783c5
JB		 5271 /* MTU < 68 is an error and causes problems on some kernels */
5272 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5273 return -EINVAL;
5274
396e799c 5275 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5276 /* must set new MTU before calling down or up */
9a799d71
AK		 5277 netdev->mtu = new_mtu;
5278
16b61beb
JF		 5279 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5280 hw->fc.low_water = FC_LOW_WATER(max_frame);
5281
d4f80882
AV		 5282 if (netif_running(netdev))
5283 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5284
5285 return 0;
5286}
5287
5288/**
5289 * ixgbe_open - Called when a network interface is made active
5290 * @netdev: network interface device structure
5291 *
5292 * Returns 0 on success, negative value on failure
5293 *
5294 * The open entry point is called when a network interface is made
5295 * active by the system (IFF_UP). At this point all resources needed
5296 * for transmit and receive operations are allocated, the interrupt
5297 * handler is registered with the OS, the watchdog timer is started,
5298 * and the stack is notified that the interface is ready.
5299 **/
5300static int ixgbe_open(struct net_device *netdev)
5301{
5302 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5303 int err;
4bebfaa5
AK		 5304
5305 /* disallow open during test */
5306 if (test_bit(__IXGBE_TESTING, &adapter->state))
5307 return -EBUSY;
9a799d71 5308
54386467
JB		 5309 netif_carrier_off(netdev);
5310
9a799d71
AK		 5311 /* allocate transmit descriptors */
5312 err = ixgbe_setup_all_tx_resources(adapter);
5313 if (err)
5314 goto err_setup_tx;
5315
9a799d71
AK		 5316 /* allocate receive descriptors */
5317 err = ixgbe_setup_all_rx_resources(adapter);
5318 if (err)
5319 goto err_setup_rx;
5320
5321 ixgbe_configure(adapter);
5322
021230d4 5323 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5324 if (err)
5325 goto err_req_irq;
5326
9a799d71
AK		 5327 err = ixgbe_up_complete(adapter);
5328 if (err)
5329 goto err_up;
5330
d55b53ff
JK		 5331 netif_tx_start_all_queues(netdev);
5332
9a799d71
AK		 5333 return 0;
5334
5335err_up:
5eba3699 5336 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5337 ixgbe_free_irq(adapter);
5338err_req_irq:
9a799d71 5339err_setup_rx:
a20a1199 5340 ixgbe_free_all_rx_resources(adapter);
9a799d71 5341err_setup_tx:
a20a1199 5342 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5343 ixgbe_reset(adapter);
5344
5345 return err;
5346}
5347
5348/**
5349 * ixgbe_close - Disables a network interface
5350 * @netdev: network interface device structure
5351 *
5352 * Returns 0, this is not allowed to fail
5353 *
5354 * The close entry point is called when an interface is de-activated
5355 * by the OS. The hardware is still under the drivers control, but
5356 * needs to be disabled. A global MAC reset is issued to stop the
5357 * hardware, and all transmit and receive resources are freed.
5358 **/
5359static int ixgbe_close(struct net_device *netdev)
5360{
5361 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5362
5363 ixgbe_down(adapter);
5364 ixgbe_free_irq(adapter);
5365
5366 ixgbe_free_all_tx_resources(adapter);
5367 ixgbe_free_all_rx_resources(adapter);
5368
5eba3699 5369 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5370
5371 return 0;
5372}
5373
b3c8b4ba
AD		 5374#ifdef CONFIG_PM
5375static int ixgbe_resume(struct pci_dev *pdev)
5376{
c60fbb00
AD		 5377 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5378 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5379 u32 err;
5380
5381 pci_set_power_state(pdev, PCI_D0);
5382 pci_restore_state(pdev);
656ab817
DS		 5383 /*
5384 * pci_restore_state clears dev->state_saved so call
5385 * pci_save_state to restore it.
5386 */
5387 pci_save_state(pdev);
9ce77666 5388
5389 err = pci_enable_device_mem(pdev);
b3c8b4ba 5390 if (err) {
849c4542 5391 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5392 return err;
5393 }
5394 pci_set_master(pdev);
5395
dd4d8ca6 5396 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5397
5398 err = ixgbe_init_interrupt_scheme(adapter);
5399 if (err) {
849c4542 5400 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5401 return err;
5402 }
5403
b3c8b4ba
AD		 5404 ixgbe_reset(adapter);
5405
495dce12
WJP		 5406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5407
b3c8b4ba 5408 if (netif_running(netdev)) {
c60fbb00 5409 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5410 if (err)
5411 return err;
5412 }
5413
5414 netif_device_attach(netdev);
5415
5416 return 0;
5417}
b3c8b4ba 5418#endif /* CONFIG_PM */
9d8d05ae
RW		 5419
5420static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5421{
c60fbb00
AD		 5422 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5423 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5424 struct ixgbe_hw *hw = &adapter->hw;
5425 u32 ctrl, fctrl;
5426 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5427#ifdef CONFIG_PM
5428 int retval = 0;
5429#endif
5430
5431 netif_device_detach(netdev);
5432
5433 if (netif_running(netdev)) {
5434 ixgbe_down(adapter);
5435 ixgbe_free_irq(adapter);
5436 ixgbe_free_all_tx_resources(adapter);
5437 ixgbe_free_all_rx_resources(adapter);
5438 }
b3c8b4ba 5439
5f5ae6fc
AD		 5440 ixgbe_clear_interrupt_scheme(adapter);
5441
b3c8b4ba
AD		 5442#ifdef CONFIG_PM
5443 retval = pci_save_state(pdev);
5444 if (retval)
5445 return retval;
4df10466 5446
b3c8b4ba 5447#endif
e8e26350
PW		 5448 if (wufc) {
5449 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5450
e8e26350
PW		 5451 /* turn on all-multi mode if wake on multicast is enabled */
5452 if (wufc & IXGBE_WUFC_MC) {
5453 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5454 fctrl |= IXGBE_FCTRL_MPE;
5455 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5456 }
5457
5458 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5459 ctrl |= IXGBE_CTRL_GIO_DIS;
5460 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5461
5462 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5463 } else {
5464 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5465 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5466 }
5467
bd508178
AD		 5468 switch (hw->mac.type) {
5469 case ixgbe_mac_82598EB:
dd4d8ca6 5470 pci_wake_from_d3(pdev, false);
bd508178
AD		 5471 break;
5472 case ixgbe_mac_82599EB:
5473 pci_wake_from_d3(pdev, !!wufc);
5474 break;
5475 default:
5476 break;
5477 }
b3c8b4ba 5478
9d8d05ae
RW		 5479 *enable_wake = !!wufc;
5480
b3c8b4ba
AD		 5481 ixgbe_release_hw_control(adapter);
5482
5483 pci_disable_device(pdev);
5484
9d8d05ae
RW		 5485 return 0;
5486}
5487
5488#ifdef CONFIG_PM
5489static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5490{
5491 int retval;
5492 bool wake;
5493
5494 retval = __ixgbe_shutdown(pdev, &wake);
5495 if (retval)
5496 return retval;
5497
5498 if (wake) {
5499 pci_prepare_to_sleep(pdev);
5500 } else {
5501 pci_wake_from_d3(pdev, false);
5502 pci_set_power_state(pdev, PCI_D3hot);
5503 }
b3c8b4ba
AD		 5504
5505 return 0;
5506}
9d8d05ae 5507#endif /* CONFIG_PM */
b3c8b4ba
AD		 5508
5509static void ixgbe_shutdown(struct pci_dev *pdev)
5510{
9d8d05ae
RW		 5511 bool wake;
5512
5513 __ixgbe_shutdown(pdev, &wake);
5514
5515 if (system_state == SYSTEM_POWER_OFF) {
5516 pci_wake_from_d3(pdev, wake);
5517 pci_set_power_state(pdev, PCI_D3hot);
5518 }
b3c8b4ba
AD		 5519}
5520
9a799d71
AK		 5521/**
5522 * ixgbe_update_stats - Update the board statistics counters.
5523 * @adapter: board private structure
5524 **/
5525void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5526{
2d86f139 5527 struct net_device *netdev = adapter->netdev;
9a799d71 5528 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5529 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5530 u64 total_mpc = 0;
5531 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5532 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5533 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5534 u64 bytes = 0, packets = 0;
9a799d71 5535
d08935c2
DS		 5536 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5537 test_bit(__IXGBE_RESETTING, &adapter->state))
5538 return;
5539
94b982b2 5540 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5541 u64 rsc_count = 0;
94b982b2 5542 u64 rsc_flush = 0;
d51019a4
PW		 5543 for (i = 0; i < 16; i++)
5544 adapter->hw_rx_no_dma_resources +=
7ca647bd 5545 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5546 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5547 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5548 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5549 }
5550 adapter->rsc_total_count = rsc_count;
5551 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5552 }
5553
5b7da515
AD		 5554 for (i = 0; i < adapter->num_rx_queues; i++) {
5555 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5556 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5557 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5558 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5559 bytes += rx_ring->stats.bytes;
5560 packets += rx_ring->stats.packets;
5561 }
5562 adapter->non_eop_descs = non_eop_descs;
5563 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5564 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5565 netdev->stats.rx_bytes = bytes;
5566 netdev->stats.rx_packets = packets;
5567
5568 bytes = 0;
5569 packets = 0;
7ca3bc58 5570 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5571 for (i = 0; i < adapter->num_tx_queues; i++) {
5572 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5573 restart_queue += tx_ring->tx_stats.restart_queue;
5574 tx_busy += tx_ring->tx_stats.tx_busy;
5575 bytes += tx_ring->stats.bytes;
5576 packets += tx_ring->stats.packets;
5577 }
eb985f09 5578 adapter->restart_queue = restart_queue;
5b7da515
AD		 5579 adapter->tx_busy = tx_busy;
5580 netdev->stats.tx_bytes = bytes;
5581 netdev->stats.tx_packets = packets;
7ca3bc58 5582
7ca647bd 5583 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5584 for (i = 0; i < 8; i++) {
5585 /* for packet buffers not used, the register should read 0 */
5586 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5587 missed_rx += mpc;
7ca647bd
JP		 5588 hwstats->mpc[i] += mpc;
5589 total_mpc += hwstats->mpc[i];
e8e26350 5590 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5591 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5592 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5593 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5594 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5595 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5596 switch (hw->mac.type) {
5597 case ixgbe_mac_82598EB:
7ca647bd
JP		 5598 hwstats->pxonrxc[i] +=
5599 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5600 hwstats->pxoffrxc[i] +=
5601 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178
AD		 5602 break;
5603 case ixgbe_mac_82599EB:
5604 hwstats->pxonrxc[i] +=
5605 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5606 hwstats->pxoffrxc[i] +=
5607 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5608 break;
5609 default:
5610 break;
e8e26350 5611 }
7ca647bd
JP		 5612 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5613 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5614 }
7ca647bd 5615 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5616 /* work around hardware counting issue */
7ca647bd 5617 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5618
5619 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5620 switch (hw->mac.type) {
5621 case ixgbe_mac_82598EB:
5622 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5623 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5624 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5625 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5626 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5627 break;
5628 case ixgbe_mac_82599EB:
7ca647bd 5629 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5630 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5631 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5632 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5633 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5634 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5635 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5636 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5637 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5638 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5639#ifdef IXGBE_FCOE
7ca647bd
JP		 5640 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5641 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5642 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5643 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5644 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5645 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5646#endif /* IXGBE_FCOE */
bd508178
AD		 5647 break;
5648 default:
5649 break;
e8e26350 5650 }
9a799d71 5651 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5652 hwstats->bprc += bprc;
5653 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5654 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5655 hwstats->mprc -= bprc;
5656 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5657 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5658 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5659 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5660 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5661 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5662 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5663 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5664 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5665 hwstats->lxontxc += lxon;
6f11eef7 5666 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5667 hwstats->lxofftxc += lxoff;
5668 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5669 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5670 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5671 /*
5672 * 82598 errata - tx of flow control packets is included in tx counters
5673 */
5674 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5675 hwstats->gptc -= xon_off_tot;
5676 hwstats->mptc -= xon_off_tot;
5677 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5678 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5679 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5680 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5681 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5682 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5683 hwstats->ptc64 -= xon_off_tot;
5684 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5685 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5686 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5687 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5688 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5689 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5690
5691 /* Fill out the OS statistics structure */
7ca647bd 5692 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5693
5694 /* Rx Errors */
7ca647bd 5695 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5696 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5697 netdev->stats.rx_length_errors = hwstats->rlec;
5698 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5699 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5700}
5701
5702/**
5703 * ixgbe_watchdog - Timer Call-back
5704 * @data: pointer to adapter cast into an unsigned long
5705 **/
5706static void ixgbe_watchdog(unsigned long data)
5707{
5708 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5709 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5710 u64 eics = 0;
5711 int i;
cf8280ee 5712
fe49f04a
AD		 5713 /*
5714 * Do the watchdog outside of interrupt context due to the lovely
5715 * delays that some of the newer hardware requires
5716 */
22d5a71b 5717
fe49f04a
AD		 5718 if (test_bit(__IXGBE_DOWN, &adapter->state))
5719 goto watchdog_short_circuit;
22d5a71b 5720
fe49f04a
AD		 5721 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5722 /*
5723 * for legacy and MSI interrupts don't set any bits
5724 * that are enabled for EIAM, because this operation
5725 * would set *both* EIMS and EICS for any bit in EIAM
5726 */
5727 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5728 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5729 goto watchdog_reschedule;
5730 }
5731
5732 /* get one bit for every active tx/rx interrupt vector */
5733 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5734 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5735 if (qv->rxr_count || qv->txr_count)
5736 eics |= ((u64)1 << i);
cf8280ee 5737 }
9a799d71 5738
fe49f04a
AD		 5739 /* Cause software interrupt to ensure rx rings are cleaned */
5740 ixgbe_irq_rearm_queues(adapter, eics);
5741
5742watchdog_reschedule:
5743 /* Reset the timer */
5744 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5745
5746watchdog_short_circuit:
cf8280ee
JB		 5747 schedule_work(&adapter->watchdog_task);
5748}
5749
e8e26350
PW		 5750/**
5751 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5752 * @work: pointer to work_struct containing our data
5753 **/
5754static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5755{
5756 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5757 struct ixgbe_adapter,
5758 multispeed_fiber_task);
e8e26350
PW		 5759 struct ixgbe_hw *hw = &adapter->hw;
5760 u32 autoneg;
8620a103 5761 bool negotiation;
e8e26350
PW		 5762
5763 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5764 autoneg = hw->phy.autoneg_advertised;
5765 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5766 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5767 hw->mac.autotry_restart = false;
8620a103
MC		 5768 if (hw->mac.ops.setup_link)
5769 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5770 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5771 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5772}
5773
5774/**
5775 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5776 * @work: pointer to work_struct containing our data
5777 **/
5778static void ixgbe_sfp_config_module_task(struct work_struct *work)
5779{
5780 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5781 struct ixgbe_adapter,
5782 sfp_config_module_task);
e8e26350
PW		 5783 struct ixgbe_hw *hw = &adapter->hw;
5784 u32 err;
5785
5786 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5787
5788 /* Time for electrical oscillations to settle down */
5789 msleep(100);
e8e26350 5790 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5791
e8e26350 5792 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5793 e_dev_err("failed to initialize because an unsupported SFP+ "
5794 "module type was detected.\n");
5795 e_dev_err("Reload the driver after installing a supported "
5796 "module.\n");
63d6e1d8 5797 unregister_netdev(adapter->netdev);
e8e26350
PW		 5798 return;
5799 }
5800 hw->mac.ops.setup_sfp(hw);
5801
8d1c3c07 5802 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5803 /* This will also work for DA Twinax connections */
5804 schedule_work(&adapter->multispeed_fiber_task);
5805 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5806}
5807
c4cf55e5
PWJ		 5808/**
5809 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5810 * @work: pointer to work_struct containing our data
5811 **/
5812static void ixgbe_fdir_reinit_task(struct work_struct *work)
5813{
5814 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5815 struct ixgbe_adapter,
5816 fdir_reinit_task);
c4cf55e5
PWJ		 5817 struct ixgbe_hw *hw = &adapter->hw;
5818 int i;
5819
5820 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5821 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 5822 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5823 &(adapter->tx_ring[i]->state));
c4cf55e5 5824 } else {
396e799c 5825 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5826 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5827 }
5828 /* Done FDIR Re-initialization, enable transmits */
5829 netif_tx_start_all_queues(adapter->netdev);
5830}
5831
10eec955
JF		 5832static DEFINE_MUTEX(ixgbe_watchdog_lock);
5833
cf8280ee 5834/**
69888674
AD		 5835 * ixgbe_watchdog_task - worker thread to bring link up
5836 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5837 **/
5838static void ixgbe_watchdog_task(struct work_struct *work)
5839{
5840 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5841 struct ixgbe_adapter,
5842 watchdog_task);
cf8280ee
JB		 5843 struct net_device *netdev = adapter->netdev;
5844 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5845 u32 link_speed;
5846 bool link_up;
bc59fcda
NS		 5847 int i;
5848 struct ixgbe_ring *tx_ring;
5849 int some_tx_pending = 0;
cf8280ee 5850
10eec955
JF		 5851 mutex_lock(&ixgbe_watchdog_lock);
5852
5853 link_up = adapter->link_up;
5854 link_speed = adapter->link_speed;
cf8280ee
JB		 5855
5856 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5857 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5858 if (link_up) {
5859#ifdef CONFIG_DCB
5860 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5861 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5862 hw->mac.ops.fc_enable(hw, i);
264857b8 5863 } else {
620fa036 5864 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5865 }
5866#else
620fa036 5867 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5868#endif
5869 }
5870
cf8280ee
JB		 5871 if (link_up ||
5872 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5873 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5874 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5875 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5876 }
5877 adapter->link_up = link_up;
5878 adapter->link_speed = link_speed;
5879 }
9a799d71
AK		 5880
5881 if (link_up) {
5882 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5883 bool flow_rx, flow_tx;
5884
bd508178
AD		 5885 switch (hw->mac.type) {
5886 case ixgbe_mac_82598EB: {
e8e26350
PW		 5887 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5888 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5889 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5890 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350 5891 }
bd508178
AD		 5892 break;
5893 case ixgbe_mac_82599EB: {
5894 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5895 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5896 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5897 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5898 }
5899 break;
5900 default:
5901 flow_tx = false;
5902 flow_rx = false;
5903 break;
5904 }
e8e26350 5905
396e799c 5906 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5907 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5908 "10 Gbps" :
5909 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5910 "1 Gbps" : "unknown speed")),
e8e26350 5911 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5912 (flow_rx ? "RX" :
5913 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5914
5915 netif_carrier_on(netdev);
9a799d71
AK		 5916 } else {
5917 /* Force detection of hung controller */
7d637bcc
AD		 5918 for (i = 0; i < adapter->num_tx_queues; i++) {
5919 tx_ring = adapter->tx_ring[i];
5920 set_check_for_tx_hang(tx_ring);
5921 }
9a799d71
AK		 5922 }
5923 } else {
cf8280ee
JB		 5924 adapter->link_up = false;
5925 adapter->link_speed = 0;
9a799d71 5926 if (netif_carrier_ok(netdev)) {
396e799c 5927 e_info(drv, "NIC Link is Down\n");
9a799d71 5928 netif_carrier_off(netdev);
9a799d71
AK		 5929 }
5930 }
5931
bc59fcda
NS		 5932 if (!netif_carrier_ok(netdev)) {
5933 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5934 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5935 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5936 some_tx_pending = 1;
5937 break;
5938 }
5939 }
5940
5941 if (some_tx_pending) {
5942 /* We've lost link, so the controller stops DMA,
5943 * but we've got queued Tx work that's never going
5944 * to get done, so reset controller to flush Tx.
5945 * (Do the reset outside of interrupt context).
5946 */
5947 schedule_work(&adapter->reset_task);
5948 }
5949 }
5950
9a799d71 5951 ixgbe_update_stats(adapter);
10eec955 5952 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5953}
5954
9a799d71 5955static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 5956 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 5957 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 5958{
5959 struct ixgbe_adv_tx_context_desc *context_desc;
5960 unsigned int i;
5961 int err;
5962 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5963 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5964 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5965
5966 if (skb_is_gso(skb)) {
5967 if (skb_header_cloned(skb)) {
5968 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5969 if (err)
5970 return err;
5971 }
5972 l4len = tcp_hdrlen(skb);
5973 *hdr_len += l4len;
5974
5e09a105 5975 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5976 struct iphdr *iph = ip_hdr(skb);
5977 iph->tot_len = 0;
5978 iph->check = 0;
5979 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5980 iph->daddr, 0,
5981 IPPROTO_TCP,
5982 0);
8e1e8a47 5983 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5984 ipv6_hdr(skb)->payload_len = 0;
5985 tcp_hdr(skb)->check =
5986 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5987 &ipv6_hdr(skb)->daddr,
5988 0, IPPROTO_TCP, 0);
9a799d71
AK		 5989 }
5990
5991 i = tx_ring->next_to_use;
5992
5993 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5994 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5995
5996 /* VLAN MACLEN IPLEN */
5997 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5998 vlan_macip_lens |=
5999 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6000 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6001 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6002 *hdr_len += skb_network_offset(skb);
6003 vlan_macip_lens |=
6004 (skb_transport_header(skb) - skb_network_header(skb));
6005 *hdr_len +=
6006 (skb_transport_header(skb) - skb_network_header(skb));
6007 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6008 context_desc->seqnum_seed = 0;
6009
6010 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6011 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6012 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6013
5e09a105 6014 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6015 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6016 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6017 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6018
6019 /* MSS L4LEN IDX */
9f8cdf4f 6020 mss_l4len_idx =
9a799d71
AK		 6021 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6022 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6023 /* use index 1 for TSO */
6024 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6025 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6026
6027 tx_buffer_info->time_stamp = jiffies;
6028 tx_buffer_info->next_to_watch = i;
6029
6030 i++;
6031 if (i == tx_ring->count)
6032 i = 0;
6033 tx_ring->next_to_use = i;
6034
6035 return true;
6036 }
6037 return false;
6038}
6039
5e09a105
HZ		 6040static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6041 __be16 protocol)
7ca647bd
JP		 6042{
6043 u32 rtn = 0;
7ca647bd
JP		 6044
6045 switch (protocol) {
6046 case cpu_to_be16(ETH_P_IP):
6047 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6048 switch (ip_hdr(skb)->protocol) {
6049 case IPPROTO_TCP:
6050 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6051 break;
6052 case IPPROTO_SCTP:
6053 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6054 break;
6055 }
6056 break;
6057 case cpu_to_be16(ETH_P_IPV6):
6058 /* XXX what about other V6 headers?? */
6059 switch (ipv6_hdr(skb)->nexthdr) {
6060 case IPPROTO_TCP:
6061 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6062 break;
6063 case IPPROTO_SCTP:
6064 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6065 break;
6066 }
6067 break;
6068 default:
6069 if (unlikely(net_ratelimit()))
6070 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6071 protocol);
7ca647bd
JP		 6072 break;
6073 }
6074
6075 return rtn;
6076}
6077
9a799d71 6078static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6079 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6080 struct sk_buff *skb, u32 tx_flags,
6081 __be16 protocol)
9a799d71
AK		 6082{
6083 struct ixgbe_adv_tx_context_desc *context_desc;
6084 unsigned int i;
6085 struct ixgbe_tx_buffer *tx_buffer_info;
6086 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6087
6088 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6089 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6090 i = tx_ring->next_to_use;
6091 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6092 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6093
6094 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6095 vlan_macip_lens |=
6096 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6097 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6098 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6099 if (skb->ip_summed == CHECKSUM_PARTIAL)
6100 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6101 skb_network_header(skb));
9a799d71
AK		 6102
6103 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6104 context_desc->seqnum_seed = 0;
6105
6106 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6107 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6108
7ca647bd 6109 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6110 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6111
6112 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6113 /* use index zero for tx checksum offload */
9a799d71
AK		 6114 context_desc->mss_l4len_idx = 0;
6115
6116 tx_buffer_info->time_stamp = jiffies;
6117 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6118
9a799d71
AK		 6119 i++;
6120 if (i == tx_ring->count)
6121 i = 0;
6122 tx_ring->next_to_use = i;
6123
6124 return true;
6125 }
9f8cdf4f 6126
9a799d71
AK		 6127 return false;
6128}
6129
6130static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6131 struct ixgbe_ring *tx_ring,
6132 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6133 unsigned int first, const u8 hdr_len)
9a799d71 6134{
b6ec895e 6135 struct device *dev = tx_ring->dev;
9a799d71 6136 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6137 unsigned int len;
6138 unsigned int total = skb->len;
9a799d71
AK		 6139 unsigned int offset = 0, size, count = 0, i;
6140 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6141 unsigned int f;
8ad494b0
AD		 6142 unsigned int bytecount = skb->len;
6143 u16 gso_segs = 1;
9a799d71
AK		 6144
6145 i = tx_ring->next_to_use;
6146
eacd73f7
YZ		 6147 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6148 /* excluding fcoe_crc_eof for FCoE */
6149 total -= sizeof(struct fcoe_crc_eof);
6150
6151 len = min(skb_headlen(skb), total);
9a799d71
AK		 6152 while (len) {
6153 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6154 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6155
6156 tx_buffer_info->length = size;
e5a43549 6157 tx_buffer_info->mapped_as_page = false;
b6ec895e 6158 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6159 skb->data + offset,
1b507730 6160 size, DMA_TO_DEVICE);
b6ec895e 6161 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6162 goto dma_error;
9a799d71
AK		 6163 tx_buffer_info->time_stamp = jiffies;
6164 tx_buffer_info->next_to_watch = i;
6165
6166 len -= size;
eacd73f7 6167 total -= size;
9a799d71
AK		 6168 offset += size;
6169 count++;
44df32c5
AD		 6170
6171 if (len) {
6172 i++;
6173 if (i == tx_ring->count)
6174 i = 0;
6175 }
9a799d71
AK		 6176 }
6177
6178 for (f = 0; f < nr_frags; f++) {
6179 struct skb_frag_struct *frag;
6180
6181 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6182 len = min((unsigned int)frag->size, total);
e5a43549 6183 offset = frag->page_offset;
9a799d71
AK		 6184
6185 while (len) {
44df32c5
AD		 6186 i++;
6187 if (i == tx_ring->count)
6188 i = 0;
6189
9a799d71
AK		 6190 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6191 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6192
6193 tx_buffer_info->length = size;
b6ec895e 6194 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6195 frag->page,
6196 offset, size,
1b507730 6197 DMA_TO_DEVICE);
e5a43549 6198 tx_buffer_info->mapped_as_page = true;
b6ec895e 6199 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6200 goto dma_error;
9a799d71
AK		 6201 tx_buffer_info->time_stamp = jiffies;
6202 tx_buffer_info->next_to_watch = i;
6203
6204 len -= size;
eacd73f7 6205 total -= size;
9a799d71
AK		 6206 offset += size;
6207 count++;
9a799d71 6208 }
eacd73f7
YZ		 6209 if (total == 0)
6210 break;
9a799d71 6211 }
44df32c5 6212
8ad494b0
AD		 6213 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6214 gso_segs = skb_shinfo(skb)->gso_segs;
6215#ifdef IXGBE_FCOE
6216 /* adjust for FCoE Sequence Offload */
6217 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6218 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6219 skb_shinfo(skb)->gso_size);
6220#endif /* IXGBE_FCOE */
6221 bytecount += (gso_segs - 1) * hdr_len;
6222
6223 /* multiply data chunks by size of headers */
6224 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6225 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6226 tx_ring->tx_buffer_info[i].skb = skb;
6227 tx_ring->tx_buffer_info[first].next_to_watch = i;
6228
e5a43549
AD		 6229 return count;
6230
6231dma_error:
849c4542 6232 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6233
6234 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6235 tx_buffer_info->dma = 0;
6236 tx_buffer_info->time_stamp = 0;
6237 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6238 if (count)
6239 count--;
e5a43549
AD		 6240
6241 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6242 while (count--) {
e8e9f696 6243 if (i == 0)
e5a43549 6244 i += tx_ring->count;
c1fa347f 6245 i--;
e5a43549 6246 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6247 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6248 }
6249
e44d38e1 6250 return 0;
9a799d71
AK		 6251}
6252
84ea2591 6253static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6254 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6255{
6256 union ixgbe_adv_tx_desc *tx_desc = NULL;
6257 struct ixgbe_tx_buffer *tx_buffer_info;
6258 u32 olinfo_status = 0, cmd_type_len = 0;
6259 unsigned int i;
6260 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6261
6262 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6263
6264 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6265
6266 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6267 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6268
6269 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6270 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6271
6272 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6273 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6274
4eeae6fd
PW		 6275 /* use index 1 context for tso */
6276 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6277 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6278 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6279 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6280
6281 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6282 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6283 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6284
eacd73f7
YZ		 6285 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6286 olinfo_status |= IXGBE_ADVTXD_CC;
6287 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6288 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6289 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6290 }
6291
9a799d71
AK		 6292 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6293
6294 i = tx_ring->next_to_use;
6295 while (count--) {
6296 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6297 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6298 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6299 tx_desc->read.cmd_type_len =
e8e9f696 6300 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6301 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6302 i++;
6303 if (i == tx_ring->count)
6304 i = 0;
6305 }
6306
6307 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6308
6309 /*
6310 * Force memory writes to complete before letting h/w
6311 * know there are new descriptors to fetch. (Only
6312 * applicable for weak-ordered memory model archs,
6313 * such as IA-64).
6314 */
6315 wmb();
6316
6317 tx_ring->next_to_use = i;
84ea2591 6318 writel(i, tx_ring->tail);
9a799d71
AK		 6319}
6320
c4cf55e5 6321static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
ee9e0f0b 6322 u8 queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6323{
c4cf55e5 6324 struct ixgbe_atr_input atr_input;
c4cf55e5
PWJ		 6325 struct iphdr *iph = ip_hdr(skb);
6326 struct ethhdr *eth = (struct ethhdr *)skb->data;
ee9e0f0b
AD		 6327 struct tcphdr *th;
6328 u16 vlan_id;
c4cf55e5 6329
ee9e0f0b
AD		 6330 /* Right now, we support IPv4 w/ TCP only */
6331 if (protocol != htons(ETH_P_IP) ||
6332 iph->protocol != IPPROTO_TCP)
d3ead241 6333 return;
c4cf55e5
PWJ		 6334
6335 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6336
6337 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6338 IXGBE_TX_FLAGS_VLAN_SHIFT;
ee9e0f0b
AD		 6339
6340 th = tcp_hdr(skb);
c4cf55e5
PWJ		 6341
6342 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
ee9e0f0b
AD		 6343 ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6344 ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6345 ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6346 ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
c4cf55e5 6347 /* src and dst are inverted, think how the receiver sees them */
ee9e0f0b
AD		 6348 ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6349 ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
c4cf55e5
PWJ		 6350
6351 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6352 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6353}
6354
fc77dc3c 6355static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6356{
fc77dc3c 6357 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6358 /* Herbert's original patch had:
6359 * smp_mb__after_netif_stop_queue();
6360 * but since that doesn't exist yet, just open code it. */
6361 smp_mb();
6362
6363 /* We need to check again in a case another CPU has just
6364 * made room available. */
6365 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6366 return -EBUSY;
6367
6368 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6369 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6370 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6371 return 0;
6372}
6373
fc77dc3c 6374static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6375{
6376 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6377 return 0;
fc77dc3c 6378 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6379}
6380
09a3b1f8
SH		 6381static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6382{
6383 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6384 int txq = smp_processor_id();
56075a98 6385#ifdef IXGBE_FCOE
5e09a105
HZ		 6386 __be16 protocol;
6387
6388 protocol = vlan_get_protocol(skb);
6389
6390 if ((protocol == htons(ETH_P_FCOE)) ||
6391 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6392 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6393 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6394 txq += adapter->ring_feature[RING_F_FCOE].mask;
6395 return txq;
4bc091d8 6396#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6397 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6398 txq = adapter->fcoe.up;
6399 return txq;
4bc091d8 6400#endif
56075a98
JF		 6401 }
6402 }
6403#endif
6404
fdd3d631
KK		 6405 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6406 while (unlikely(txq >= dev->real_num_tx_queues))
6407 txq -= dev->real_num_tx_queues;
5f715823 6408 return txq;
fdd3d631 6409 }
c4cf55e5 6410
2ea186ae
JF		 6411 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6412 if (skb->priority == TC_PRIO_CONTROL)
6413 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6414 else
6415 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6416 >> 13;
6417 return txq;
6418 }
09a3b1f8
SH		 6419
6420 return skb_tx_hash(dev, skb);
6421}
6422
fc77dc3c 6423netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6424 struct ixgbe_adapter *adapter,
6425 struct ixgbe_ring *tx_ring)
9a799d71 6426{
fc77dc3c 6427 struct net_device *netdev = tx_ring->netdev;
60d51134 6428 struct netdev_queue *txq;
9a799d71
AK		 6429 unsigned int first;
6430 unsigned int tx_flags = 0;
30eba97a 6431 u8 hdr_len = 0;
5f715823 6432 int tso;
9a799d71
AK		 6433 int count = 0;
6434 unsigned int f;
5e09a105
HZ		 6435 __be16 protocol;
6436
6437 protocol = vlan_get_protocol(skb);
9f8cdf4f 6438
eab6d18d 6439 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6440 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6441 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6442 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6443 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6444 }
6445 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6446 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6447 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6448 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6449 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6450 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6451 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6452 }
eacd73f7 6453
09ad1cc0 6454#ifdef IXGBE_FCOE
56075a98
JF		 6455 /* for FCoE with DCB, we force the priority to what
6456 * was specified by the switch */
6457 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6458 (protocol == htons(ETH_P_FCOE) ||
6459 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6460#ifdef CONFIG_IXGBE_DCB
6461 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6462 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6463 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6464 tx_flags |= ((adapter->fcoe.up << 13)
6465 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6466 }
6467#endif
ca77cd59 6468 /* flag for FCoE offloads */
5e09a105 6469 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6470 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6471 }
ca77cd59
RL		 6472#endif
6473
eacd73f7 6474 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6475 if (skb_is_gso(skb) ||
6476 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6477 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6478 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6479 count++;
6480
9f8cdf4f
JB		 6481 count += TXD_USE_COUNT(skb_headlen(skb));
6482 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6483 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6484
fc77dc3c 6485 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6486 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6487 return NETDEV_TX_BUSY;
6488 }
9a799d71 6489
9a799d71 6490 first = tx_ring->next_to_use;
eacd73f7
YZ		 6491 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6492#ifdef IXGBE_FCOE
6493 /* setup tx offload for FCoE */
6494 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6495 if (tso < 0) {
6496 dev_kfree_skb_any(skb);
6497 return NETDEV_TX_OK;
6498 }
6499 if (tso)
6500 tx_flags |= IXGBE_TX_FLAGS_FSO;
6501#endif /* IXGBE_FCOE */
6502 } else {
5e09a105 6503 if (protocol == htons(ETH_P_IP))
eacd73f7 6504 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6505 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6506 protocol);
eacd73f7
YZ		 6507 if (tso < 0) {
6508 dev_kfree_skb_any(skb);
6509 return NETDEV_TX_OK;
6510 }
9a799d71 6511
eacd73f7
YZ		 6512 if (tso)
6513 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6514 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6515 protocol) &&
eacd73f7
YZ		 6516 (skb->ip_summed == CHECKSUM_PARTIAL))
6517 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6518 }
9a799d71 6519
8ad494b0 6520 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6521 if (count) {
c4cf55e5
PWJ		 6522 /* add the ATR filter if ATR is on */
6523 if (tx_ring->atr_sample_rate) {
6524 ++tx_ring->atr_count;
6525 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
7d637bcc
AD		 6526 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6527 &tx_ring->state)) {
c4cf55e5 6528 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6529 tx_flags, protocol);
c4cf55e5
PWJ		 6530 tx_ring->atr_count = 0;
6531 }
6532 }
60d51134
ED		 6533 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6534 txq->tx_bytes += skb->len;
6535 txq->tx_packets++;
84ea2591 6536 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6537 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6538
44df32c5
AD		 6539 } else {
6540 dev_kfree_skb_any(skb);
6541 tx_ring->tx_buffer_info[first].time_stamp = 0;
6542 tx_ring->next_to_use = first;
6543 }
9a799d71
AK		 6544
6545 return NETDEV_TX_OK;
6546}
6547
84418e3b
AD		 6548static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6549{
6550 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6551 struct ixgbe_ring *tx_ring;
6552
6553 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6554 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6555}
6556
9a799d71
AK		 6557/**
6558 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6559 * @netdev: network interface device structure
6560 * @p: pointer to an address structure
6561 *
6562 * Returns 0 on success, negative on failure
6563 **/
6564static int ixgbe_set_mac(struct net_device *netdev, void *p)
6565{
6566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6567 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6568 struct sockaddr *addr = p;
6569
6570 if (!is_valid_ether_addr(addr->sa_data))
6571 return -EADDRNOTAVAIL;
6572
6573 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6574 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6575
1cdd1ec8
GR		 6576 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6577 IXGBE_RAH_AV);
9a799d71
AK		 6578
6579 return 0;
6580}
6581
6b73e10d
BH		 6582static int
6583ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6584{
6585 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6586 struct ixgbe_hw *hw = &adapter->hw;
6587 u16 value;
6588 int rc;
6589
6590 if (prtad != hw->phy.mdio.prtad)
6591 return -EINVAL;
6592 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6593 if (!rc)
6594 rc = value;
6595 return rc;
6596}
6597
6598static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6599 u16 addr, u16 value)
6600{
6601 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6602 struct ixgbe_hw *hw = &adapter->hw;
6603
6604 if (prtad != hw->phy.mdio.prtad)
6605 return -EINVAL;
6606 return hw->phy.ops.write_reg(hw, addr, devad, value);
6607}
6608
6609static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6610{
6611 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6612
6613 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6614}
6615
0365e6e4
PW		 6616/**
6617 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6618 * netdev->dev_addrs
0365e6e4
PW		 6619 * @netdev: network interface device structure
6620 *
6621 * Returns non-zero on failure
6622 **/
6623static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6624{
6625 int err = 0;
6626 struct ixgbe_adapter *adapter = netdev_priv(dev);
6627 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6628
6629 if (is_valid_ether_addr(mac->san_addr)) {
6630 rtnl_lock();
6631 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6632 rtnl_unlock();
6633 }
6634 return err;
6635}
6636
6637/**
6638 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6639 * netdev->dev_addrs
0365e6e4
PW		 6640 * @netdev: network interface device structure
6641 *
6642 * Returns non-zero on failure
6643 **/
6644static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6645{
6646 int err = 0;
6647 struct ixgbe_adapter *adapter = netdev_priv(dev);
6648 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6649
6650 if (is_valid_ether_addr(mac->san_addr)) {
6651 rtnl_lock();
6652 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6653 rtnl_unlock();
6654 }
6655 return err;
6656}
6657
9a799d71
AK		 6658#ifdef CONFIG_NET_POLL_CONTROLLER
6659/*
6660 * Polling 'interrupt' - used by things like netconsole to send skbs
6661 * without having to re-enable interrupts. It's not called while
6662 * the interrupt routine is executing.
6663 */
6664static void ixgbe_netpoll(struct net_device *netdev)
6665{
6666 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6667 int i;
9a799d71 6668
1a647bd2
AD		 6669 /* if interface is down do nothing */
6670 if (test_bit(__IXGBE_DOWN, &adapter->state))
6671 return;
6672
9a799d71 6673 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6675 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6676 for (i = 0; i < num_q_vectors; i++) {
6677 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6678 ixgbe_msix_clean_many(0, q_vector);
6679 }
6680 } else {
6681 ixgbe_intr(adapter->pdev->irq, netdev);
6682 }
9a799d71 6683 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6684}
6685#endif
6686
de1036b1
ED		 6687static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6688 struct rtnl_link_stats64 *stats)
6689{
6690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6691 int i;
6692
6693 /* accurate rx/tx bytes/packets stats */
6694 dev_txq_stats_fold(netdev, stats);
1a51502b 6695 rcu_read_lock();
de1036b1 6696 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6697 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6698 u64 bytes, packets;
6699 unsigned int start;
6700
1a51502b
ED		 6701 if (ring) {
6702 do {
6703 start = u64_stats_fetch_begin_bh(&ring->syncp);
6704 packets = ring->stats.packets;
6705 bytes = ring->stats.bytes;
6706 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6707 stats->rx_packets += packets;
6708 stats->rx_bytes += bytes;
6709 }
de1036b1 6710 }
1a51502b 6711 rcu_read_unlock();
de1036b1
ED		 6712 /* following stats updated by ixgbe_watchdog_task() */
6713 stats->multicast = netdev->stats.multicast;
6714 stats->rx_errors = netdev->stats.rx_errors;
6715 stats->rx_length_errors = netdev->stats.rx_length_errors;
6716 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6717 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6718 return stats;
6719}
6720
6721
0edc3527 6722static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6723 .ndo_open = ixgbe_open,
0edc3527 6724 .ndo_stop = ixgbe_close,
00829823 6725 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6726 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6727 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6728 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6729 .ndo_validate_addr = eth_validate_addr,
6730 .ndo_set_mac_address = ixgbe_set_mac,
6731 .ndo_change_mtu = ixgbe_change_mtu,
6732 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6733 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6734 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6735 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6736 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6737 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6738 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6739 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6740 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6741#ifdef CONFIG_NET_POLL_CONTROLLER
6742 .ndo_poll_controller = ixgbe_netpoll,
6743#endif
332d4a7d
YZ		 6744#ifdef IXGBE_FCOE
6745 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6746 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6747 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6748 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6749 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6750#endif /* IXGBE_FCOE */
0edc3527
SH		 6751};
6752
1cdd1ec8
GR		 6753static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6754 const struct ixgbe_info *ii)
6755{
6756#ifdef CONFIG_PCI_IOV
6757 struct ixgbe_hw *hw = &adapter->hw;
6758 int err;
6759
6760 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6761 return;
6762
6763 /* The 82599 supports up to 64 VFs per physical function
6764 * but this implementation limits allocation to 63 so that
6765 * basic networking resources are still available to the
6766 * physical function
6767 */
6768 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6769 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6770 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6771 if (err) {
396e799c 6772 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6773 goto err_novfs;
6774 }
6775 /* If call to enable VFs succeeded then allocate memory
6776 * for per VF control structures.
6777 */
6778 adapter->vfinfo =
6779 kcalloc(adapter->num_vfs,
6780 sizeof(struct vf_data_storage), GFP_KERNEL);
6781 if (adapter->vfinfo) {
6782 /* Now that we're sure SR-IOV is enabled
6783 * and memory allocated set up the mailbox parameters
6784 */
6785 ixgbe_init_mbx_params_pf(hw);
6786 memcpy(&hw->mbx.ops, ii->mbx_ops,
6787 sizeof(hw->mbx.ops));
6788
6789 /* Disable RSC when in SR-IOV mode */
6790 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6791 IXGBE_FLAG2_RSC_ENABLED);
6792 return;
6793 }
6794
6795 /* Oh oh */
396e799c
ET		 6796 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6797 "SRIOV disabled\n");
1cdd1ec8
GR		 6798 pci_disable_sriov(adapter->pdev);
6799
6800err_novfs:
6801 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6802 adapter->num_vfs = 0;
6803#endif /* CONFIG_PCI_IOV */
6804}
6805
9a799d71
AK		 6806/**
6807 * ixgbe_probe - Device Initialization Routine
6808 * @pdev: PCI device information struct
6809 * @ent: entry in ixgbe_pci_tbl
6810 *
6811 * Returns 0 on success, negative on failure
6812 *
6813 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6814 * The OS initialization, configuring of the adapter private structure,
6815 * and a hardware reset occur.
6816 **/
6817static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6818 const struct pci_device_id *ent)
9a799d71
AK		 6819{
6820 struct net_device *netdev;
6821 struct ixgbe_adapter *adapter = NULL;
6822 struct ixgbe_hw *hw;
6823 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6824 static int cards_found;
6825 int i, err, pci_using_dac;
c85a2618 6826 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6827#ifdef IXGBE_FCOE
6828 u16 device_caps;
6829#endif
c44ade9e 6830 u32 part_num, eec;
9a799d71 6831
bded64a7
AG		 6832 /* Catch broken hardware that put the wrong VF device ID in
6833 * the PCIe SR-IOV capability.
6834 */
6835 if (pdev->is_virtfn) {
6836 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6837 pci_name(pdev), pdev->vendor, pdev->device);
6838 return -EINVAL;
6839 }
6840
9ce77666 6841 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6842 if (err)
6843 return err;
6844
1b507730
NN		 6845 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6846 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6847 pci_using_dac = 1;
6848 } else {
1b507730 6849 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6850 if (err) {
1b507730
NN		 6851 err = dma_set_coherent_mask(&pdev->dev,
6852 DMA_BIT_MASK(32));
9a799d71 6853 if (err) {
b8bc0421
DC		 6854 dev_err(&pdev->dev,
6855 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6856 goto err_dma;
6857 }
6858 }
6859 pci_using_dac = 0;
6860 }
6861
9ce77666 6862 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6863 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6864 if (err) {
b8bc0421
DC		 6865 dev_err(&pdev->dev,
6866 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6867 goto err_pci_reg;
6868 }
6869
19d5afd4 6870 pci_enable_pcie_error_reporting(pdev);
6fabd715 6871
9a799d71 6872 pci_set_master(pdev);
fb3b27bc 6873 pci_save_state(pdev);
9a799d71 6874
c85a2618
JF		 6875 if (ii->mac == ixgbe_mac_82598EB)
6876 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6877 else
6878 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6879
6880 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6881#ifdef IXGBE_FCOE
6882 indices += min_t(unsigned int, num_possible_cpus(),
6883 IXGBE_MAX_FCOE_INDICES);
6884#endif
c85a2618 6885 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6886 if (!netdev) {
6887 err = -ENOMEM;
6888 goto err_alloc_etherdev;
6889 }
6890
9a799d71
AK		 6891 SET_NETDEV_DEV(netdev, &pdev->dev);
6892
9a799d71 6893 adapter = netdev_priv(netdev);
c60fbb00 6894 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 6895
6896 adapter->netdev = netdev;
6897 adapter->pdev = pdev;
6898 hw = &adapter->hw;
6899 hw->back = adapter;
6900 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6901
05857980 6902 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6903 pci_resource_len(pdev, 0));
9a799d71
AK		 6904 if (!hw->hw_addr) {
6905 err = -EIO;
6906 goto err_ioremap;
6907 }
6908
6909 for (i = 1; i <= 5; i++) {
6910 if (pci_resource_len(pdev, i) == 0)
6911 continue;
6912 }
6913
0edc3527 6914 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6915 ixgbe_set_ethtool_ops(netdev);
9a799d71 6916 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6917 strcpy(netdev->name, pci_name(pdev));
6918
9a799d71
AK		 6919 adapter->bd_number = cards_found;
6920
9a799d71
AK		 6921 /* Setup hw api */
6922 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6923 hw->mac.type = ii->mac;
9a799d71 6924
c44ade9e
JB		 6925 /* EEPROM */
6926 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6927 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6928 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6929 if (!(eec & (1 << 8)))
6930 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6931
6932 /* PHY */
6933 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6934 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6935 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6936 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6937 hw->phy.mdio.mmds = 0;
6938 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6939 hw->phy.mdio.dev = netdev;
6940 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6941 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6942
6943 /* set up this timer and work struct before calling get_invariants
6944 * which might start the timer
6945 */
6946 init_timer(&adapter->sfp_timer);
c061b18d 6947 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6948 adapter->sfp_timer.data = (unsigned long) adapter;
6949
6950 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6951
e8e26350
PW		 6952 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6953 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6954
6955 /* a new SFP+ module arrival, called from GPI SDP2 context */
6956 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6957 ixgbe_sfp_config_module_task);
e8e26350 6958
8ca783ab 6959 ii->get_invariants(hw);
9a799d71
AK		 6960
6961 /* setup the private structure */
6962 err = ixgbe_sw_init(adapter);
6963 if (err)
6964 goto err_sw_init;
6965
e86bff0e
DS		 6966 /* Make it possible the adapter to be woken up via WOL */
6967 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6969
bf069c97
DS		 6970 /*
6971 * If there is a fan on this device and it has failed log the
6972 * failure.
6973 */
6974 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6975 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6976 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6977 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6978 }
6979
c44ade9e 6980 /* reset_hw fills in the perm_addr as well */
119fc60a 6981 hw->phy.reset_if_overtemp = true;
c44ade9e 6982 err = hw->mac.ops.reset_hw(hw);
119fc60a 6983 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6984 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6985 hw->mac.type == ixgbe_mac_82598EB) {
6986 /*
6987 * Start a kernel thread to watch for a module to arrive.
6988 * Only do this for 82598, since 82599 will generate
6989 * interrupts on module arrival.
6990 */
6991 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6992 mod_timer(&adapter->sfp_timer,
6993 round_jiffies(jiffies + (2 * HZ)));
6994 err = 0;
6995 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6996 e_dev_err("failed to initialize because an unsupported SFP+ "
6997 "module type was detected.\n");
6998 e_dev_err("Reload the driver after installing a supported "
6999 "module.\n");
04f165ef
PW		 7000 goto err_sw_init;
7001 } else if (err) {
849c4542 7002 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7003 goto err_sw_init;
7004 }
7005
1cdd1ec8
GR		 7006 ixgbe_probe_vf(adapter, ii);
7007
396e799c 7008 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7009 NETIF_F_IP_CSUM |
7010 NETIF_F_HW_VLAN_TX |
7011 NETIF_F_HW_VLAN_RX |
7012 NETIF_F_HW_VLAN_FILTER;
9a799d71 7013
e9990a9c 7014 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7015 netdev->features |= NETIF_F_TSO;
9a799d71 7016 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7017 netdev->features |= NETIF_F_GRO;
ad31c402 7018
45a5ead0
JB		 7019 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7020 netdev->features |= NETIF_F_SCTP_CSUM;
7021
ad31c402
JK		 7022 netdev->vlan_features |= NETIF_F_TSO;
7023 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7024 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7025 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7026 netdev->vlan_features |= NETIF_F_SG;
7027
1cdd1ec8
GR		 7028 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7029 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7030 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 7031 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7032 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7033
7a6b6f51 7034#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7035 netdev->dcbnl_ops = &dcbnl_ops;
7036#endif
7037
eacd73f7 7038#ifdef IXGBE_FCOE
0d551589 7039 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7040 if (hw->mac.ops.get_device_caps) {
7041 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7042 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7043 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7044 }
7045 }
5e09d7f6
YZ		 7046 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7047 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7048 netdev->vlan_features |= NETIF_F_FSO;
7049 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7050 }
eacd73f7 7051#endif /* IXGBE_FCOE */
7b872a55 7052 if (pci_using_dac) {
9a799d71 7053 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7054 netdev->vlan_features |= NETIF_F_HIGHDMA;
7055 }
9a799d71 7056
0c19d6af 7057 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7058 netdev->features |= NETIF_F_LRO;
7059
9a799d71 7060 /* make sure the EEPROM is good */
c44ade9e 7061 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7062 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7063 err = -EIO;
7064 goto err_eeprom;
7065 }
7066
7067 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7068 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7069
c44ade9e 7070 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7071 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7072 err = -EIO;
7073 goto err_eeprom;
7074 }
7075
61fac744 7076 /* power down the optics */
e3de4b7b 7077 if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
61fac744
PW		 7078 hw->mac.ops.disable_tx_laser(hw);
7079
9a799d71 7080 init_timer(&adapter->watchdog_timer);
c061b18d 7081 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7082 adapter->watchdog_timer.data = (unsigned long)adapter;
7083
7084 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7085 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7086
021230d4
AV		 7087 err = ixgbe_init_interrupt_scheme(adapter);
7088 if (err)
7089 goto err_sw_init;
9a799d71 7090
e8e26350 7091 switch (pdev->device) {
50d6c681
AD		 7092 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7093 /* All except this subdevice support WOL */
7094 if (pdev->subsystem_device ==
7095 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
7096 adapter->wol = 0;
7097 break;
7098 }
e8e26350 7099 case IXGBE_DEV_ID_82599_KX4:
495dce12 7100 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7101 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7102 break;
7103 default:
7104 adapter->wol = 0;
7105 break;
7106 }
e8e26350
PW		 7107 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7108
04f165ef
PW		 7109 /* pick up the PCI bus settings for reporting later */
7110 hw->mac.ops.get_bus_info(hw);
7111
9a799d71 7112 /* print bus type/speed/width info */
849c4542 7113 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 7114 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7115 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7116 "Unknown"),
7117 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7118 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7119 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7120 "Unknown"),
7121 netdev->dev_addr);
c44ade9e 7122 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 7123 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 7124 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7125 "PBA No: %06x-%03x\n",
7126 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7127 (part_num >> 8), (part_num & 0xff));
e8e26350 7128 else
849c4542
ET		 7129 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7130 hw->mac.type, hw->phy.type,
7131 (part_num >> 8), (part_num & 0xff));
9a799d71 7132
e8e26350 7133 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7134 e_dev_warn("PCI-Express bandwidth available for this card is "
7135 "not sufficient for optimal performance.\n");
7136 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7137 "is required.\n");
0c254d86
AK		 7138 }
7139
34b0368c
PWJ		 7140 /* save off EEPROM version number */
7141 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7142
9a799d71 7143 /* reset the hardware with the new settings */
794caeb2 7144 err = hw->mac.ops.start_hw(hw);
c44ade9e 7145
794caeb2
PWJ		 7146 if (err == IXGBE_ERR_EEPROM_VERSION) {
7147 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7148 e_dev_warn("This device is a pre-production adapter/LOM. "
7149 "Please be aware there may be issues associated "
7150 "with your hardware. If you are experiencing "
7151 "problems please contact your Intel or hardware "
7152 "representative who provided you with this "
7153 "hardware.\n");
794caeb2 7154 }
9a799d71
AK		 7155 strcpy(netdev->name, "eth%d");
7156 err = register_netdev(netdev);
7157 if (err)
7158 goto err_register;
7159
54386467
JB		 7160 /* carrier off reporting is important to ethtool even BEFORE open */
7161 netif_carrier_off(netdev);
7162
c4cf55e5
PWJ		 7163 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7164 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7165 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7166
119fc60a 7167 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7168 INIT_WORK(&adapter->check_overtemp_task,
7169 ixgbe_check_overtemp_task);
5dd2d332 7170#ifdef CONFIG_IXGBE_DCA
652f093f 7171 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7172 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7173 ixgbe_setup_dca(adapter);
7174 }
7175#endif
1cdd1ec8 7176 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7177 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7178 for (i = 0; i < adapter->num_vfs; i++)
7179 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7180 }
7181
0365e6e4
PW		 7182 /* add san mac addr to netdev */
7183 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7184
849c4542 7185 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7186 cards_found++;
7187 return 0;
7188
7189err_register:
5eba3699 7190 ixgbe_release_hw_control(adapter);
7a921c93 7191 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7192err_sw_init:
7193err_eeprom:
1cdd1ec8
GR		 7194 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7195 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7196 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7197 del_timer_sync(&adapter->sfp_timer);
7198 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7199 cancel_work_sync(&adapter->multispeed_fiber_task);
7200 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7201 iounmap(hw->hw_addr);
7202err_ioremap:
7203 free_netdev(netdev);
7204err_alloc_etherdev:
e8e9f696
JP		 7205 pci_release_selected_regions(pdev,
7206 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7207err_pci_reg:
7208err_dma:
7209 pci_disable_device(pdev);
7210 return err;
7211}
7212
7213/**
7214 * ixgbe_remove - Device Removal Routine
7215 * @pdev: PCI device information struct
7216 *
7217 * ixgbe_remove is called by the PCI subsystem to alert the driver
7218 * that it should release a PCI device. The could be caused by a
7219 * Hot-Plug event, or because the driver is going to be removed from
7220 * memory.
7221 **/
7222static void __devexit ixgbe_remove(struct pci_dev *pdev)
7223{
c60fbb00
AD		 7224 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7225 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7226
7227 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7228 /* clear the module not found bit to make sure the worker won't
7229 * reschedule
7230 */
7231 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7232 del_timer_sync(&adapter->watchdog_timer);
7233
c4900be0
DS		 7234 del_timer_sync(&adapter->sfp_timer);
7235 cancel_work_sync(&adapter->watchdog_task);
7236 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7237 cancel_work_sync(&adapter->multispeed_fiber_task);
7238 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7239 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7240 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7241 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7242 flush_scheduled_work();
7243
5dd2d332 7244#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7245 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7246 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7247 dca_remove_requester(&pdev->dev);
7248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7249 }
7250
7251#endif
332d4a7d
YZ		 7252#ifdef IXGBE_FCOE
7253 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7254 ixgbe_cleanup_fcoe(adapter);
7255
7256#endif /* IXGBE_FCOE */
0365e6e4
PW		 7257
7258 /* remove the added san mac */
7259 ixgbe_del_sanmac_netdev(netdev);
7260
c4900be0
DS		 7261 if (netdev->reg_state == NETREG_REGISTERED)
7262 unregister_netdev(netdev);
9a799d71 7263
1cdd1ec8
GR		 7264 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7265 ixgbe_disable_sriov(adapter);
7266
7a921c93 7267 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7268
021230d4 7269 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7270
7271 iounmap(adapter->hw.hw_addr);
9ce77666 7272 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7273 IORESOURCE_MEM));
9a799d71 7274
849c4542 7275 e_dev_info("complete\n");
021230d4 7276
9a799d71
AK		 7277 free_netdev(netdev);
7278
19d5afd4 7279 pci_disable_pcie_error_reporting(pdev);
6fabd715 7280
9a799d71
AK		 7281 pci_disable_device(pdev);
7282}
7283
7284/**
7285 * ixgbe_io_error_detected - called when PCI error is detected
7286 * @pdev: Pointer to PCI device
7287 * @state: The current pci connection state
7288 *
7289 * This function is called after a PCI bus error affecting
7290 * this device has been detected.
7291 */
7292static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7293 pci_channel_state_t state)
9a799d71 7294{
c60fbb00
AD		 7295 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7296 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7297
7298 netif_device_detach(netdev);
7299
3044b8d1
BL		 7300 if (state == pci_channel_io_perm_failure)
7301 return PCI_ERS_RESULT_DISCONNECT;
7302
9a799d71
AK		 7303 if (netif_running(netdev))
7304 ixgbe_down(adapter);
7305 pci_disable_device(pdev);
7306
b4617240 7307 /* Request a slot reset. */
9a799d71
AK		 7308 return PCI_ERS_RESULT_NEED_RESET;
7309}
7310
7311/**
7312 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7313 * @pdev: Pointer to PCI device
7314 *
7315 * Restart the card from scratch, as if from a cold-boot.
7316 */
7317static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7318{
c60fbb00 7319 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7320 pci_ers_result_t result;
7321 int err;
9a799d71 7322
9ce77666 7323 if (pci_enable_device_mem(pdev)) {
396e799c 7324 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7325 result = PCI_ERS_RESULT_DISCONNECT;
7326 } else {
7327 pci_set_master(pdev);
7328 pci_restore_state(pdev);
c0e1f68b 7329 pci_save_state(pdev);
9a799d71 7330
dd4d8ca6 7331 pci_wake_from_d3(pdev, false);
9a799d71 7332
6fabd715 7333 ixgbe_reset(adapter);
88512539 7334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7335 result = PCI_ERS_RESULT_RECOVERED;
7336 }
7337
7338 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7339 if (err) {
849c4542
ET		 7340 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7341 "failed 0x%0x\n", err);
6fabd715
PWJ		 7342 /* non-fatal, continue */
7343 }
9a799d71 7344
6fabd715 7345 return result;
9a799d71
AK		 7346}
7347
7348/**
7349 * ixgbe_io_resume - called when traffic can start flowing again.
7350 * @pdev: Pointer to PCI device
7351 *
7352 * This callback is called when the error recovery driver tells us that
7353 * its OK to resume normal operation.
7354 */
7355static void ixgbe_io_resume(struct pci_dev *pdev)
7356{
c60fbb00
AD		 7357 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7358 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7359
7360 if (netif_running(netdev)) {
7361 if (ixgbe_up(adapter)) {
396e799c 7362 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7363 return;
7364 }
7365 }
7366
7367 netif_device_attach(netdev);
9a799d71
AK		 7368}
7369
7370static struct pci_error_handlers ixgbe_err_handler = {
7371 .error_detected = ixgbe_io_error_detected,
7372 .slot_reset = ixgbe_io_slot_reset,
7373 .resume = ixgbe_io_resume,
7374};
7375
7376static struct pci_driver ixgbe_driver = {
7377 .name = ixgbe_driver_name,
7378 .id_table = ixgbe_pci_tbl,
7379 .probe = ixgbe_probe,
7380 .remove = __devexit_p(ixgbe_remove),
7381#ifdef CONFIG_PM
7382 .suspend = ixgbe_suspend,
7383 .resume = ixgbe_resume,
7384#endif
7385 .shutdown = ixgbe_shutdown,
7386 .err_handler = &ixgbe_err_handler
7387};
7388
7389/**
7390 * ixgbe_init_module - Driver Registration Routine
7391 *
7392 * ixgbe_init_module is the first routine called when the driver is
7393 * loaded. All it does is register with the PCI subsystem.
7394 **/
7395static int __init ixgbe_init_module(void)
7396{
7397 int ret;
c7689578 7398 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7399 pr_info("%s\n", ixgbe_copyright);
9a799d71 7400
5dd2d332 7401#ifdef CONFIG_IXGBE_DCA
bd0362dd 7402 dca_register_notify(&dca_notifier);
bd0362dd 7403#endif
5dd2d332 7404
9a799d71
AK		 7405 ret = pci_register_driver(&ixgbe_driver);
7406 return ret;
7407}
b4617240 7408
9a799d71
AK		 7409module_init(ixgbe_init_module);
7410
7411/**
7412 * ixgbe_exit_module - Driver Exit Cleanup Routine
7413 *
7414 * ixgbe_exit_module is called just before the driver is removed
7415 * from memory.
7416 **/
7417static void __exit ixgbe_exit_module(void)
7418{
5dd2d332 7419#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7420 dca_unregister_notify(&dca_notifier);
7421#endif
9a799d71 7422 pci_unregister_driver(&ixgbe_driver);
1a51502b 7423 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7424}
bd0362dd 7425
5dd2d332 7426#ifdef CONFIG_IXGBE_DCA
bd0362dd 7427static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7428 void *p)
bd0362dd
JC		 7429{
7430 int ret_val;
7431
7432 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7433 __ixgbe_notify_dca);
bd0362dd
JC		 7434
7435 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7436}
b453368d 7437
5dd2d332 7438#endif /* CONFIG_IXGBE_DCA */
849c4542 7439
b453368d 7440/**
849c4542 7441 * ixgbe_get_hw_dev return device
b453368d
AD		 7442 * used by hardware layer to print debugging information
7443 **/
849c4542 7444struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7445{
7446 struct ixgbe_adapter *adapter = hw->back;
849c4542 7447 return adapter->netdev;
b453368d 7448}
bd0362dd 7449
9a799d71
AK		 7450module_exit(ixgbe_exit_module);
7451
7452/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree