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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
1da177e4
LT		 80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
ff5688ae 91#include <linux/jiffies.h>
5a0e3ad6 92#include <linux/gfp.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
86de79b6
SH		 105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
a3aa1884 378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
1da177e4
LT		 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
1da177e4
LT		 438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
cc2d6596
AV		 544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
cc2d6596
AV		 564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 566#if DO_ZEROCOPY
567 struct {
cc2d6596
AV		 568 __le32 addr;
569 __le32 length;
1da177e4
LT		 570 } frag[1+MAX_SKB_FRAGS];
571#else
cc2d6596
AV		 572 __le32 addr;
573 __le32 length;
1da177e4
LT		 574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
8d1d0340
SK		 588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
1da177e4
LT		 593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
62afe595
JL		 612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 625 full_duplex:1, autoselect:1,
1da177e4
LT		 626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1; /* accept large frames */
637 int drv_flags;
638 u16 status_enable;
639 u16 intr_enable;
640 u16 available_media; /* From Wn3_Options. */
641 u16 capabilities, info1, info2; /* Various, from EEPROM. */
642 u16 advertising; /* NWay media advertisement */
643 unsigned char phys[2]; /* MII device addresses. */
644 u16 deferred; /* Resend these interrupts when we
645 * bale from the ISR */
646 u16 io_size; /* Size of PCI region (for release_region) */
de847272
BH		 647
648 /* Serialises access to hardware other than MII and variables below.
649 * The lock hierarchy is rtnl_lock > lock > mii_lock > window_lock. */
650 spinlock_t lock;
651
652 spinlock_t mii_lock; /* Serialises access to MII */
653 struct mii_if_info mii; /* MII lib hooks/info */
654 spinlock_t window_lock; /* Serialises access to windowed regs */
655 int window; /* Register window */
1da177e4
LT		 656};
657
a095cfc4
BH		 658static void window_set(struct vortex_private *vp, int window)
659{
660 if (window != vp->window) {
661 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
662 vp->window = window;
663 }
664}
665
666#define DEFINE_WINDOW_IO(size) \
667static u ## size \
668window_read ## size(struct vortex_private *vp, int window, int addr) \
669{ \
de847272
BH		 670 unsigned long flags; \
671 u ## size ret; \
672 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4 673 window_set(vp, window); \
de847272
BH		 674 ret = ioread ## size(vp->ioaddr + addr); \
675 spin_unlock_irqrestore(&vp->window_lock, flags); \
676 return ret; \
a095cfc4
BH		 677} \
678static void \
679window_write ## size(struct vortex_private *vp, u ## size value, \
680 int window, int addr) \
681{ \
de847272
BH		 682 unsigned long flags; \
683 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4
BH		 684 window_set(vp, window); \
685 iowrite ## size(value, vp->ioaddr + addr); \
de847272 686 spin_unlock_irqrestore(&vp->window_lock, flags); \
a095cfc4
BH		 687}
688DEFINE_WINDOW_IO(8)
689DEFINE_WINDOW_IO(16)
690DEFINE_WINDOW_IO(32)
691
1da177e4
LT		 692#ifdef CONFIG_PCI
693#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
694#else
695#define DEVICE_PCI(dev) NULL
696#endif
697
698#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
699
700#ifdef CONFIG_EISA
701#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
702#else
703#define DEVICE_EISA(dev) NULL
704#endif
705
706#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
707
708/* The action to take with a media selection timer tick.
709 Note that we deviate from the 3Com order by checking 10base2 before AUI.
710 */
711enum xcvr_types {
712 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
713 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
714};
715
f71e1309 716static const struct media_table {
1da177e4
LT		 717 char *name;
718 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
719 mask:8, /* The transceiver-present bit in Wn3_Config.*/
720 next:8; /* The media type to try next. */
721 int wait; /* Time before we check media status. */
722} media_tbl[] = {
723 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
724 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
725 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
726 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
727 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
728 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
729 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
730 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
731 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
732 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
733 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
734};
735
736static struct {
737 const char str[ETH_GSTRING_LEN];
738} ethtool_stats_keys[] = {
739 { "tx_deferred" },
8d1d0340 740 { "tx_max_collisions" },
1da177e4 741 { "tx_multiple_collisions" },
8d1d0340 742 { "tx_single_collisions" },
1da177e4
LT		 743 { "rx_bad_ssd" },
744};
745
746/* number of ETHTOOL_GSTATS u64's */
8d1d0340 747#define VORTEX_NUM_STATS 5
1da177e4 748
62afe595 749static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 750 int chip_idx, int card_idx);
c8303d10 751static int vortex_up(struct net_device *dev);
1da177e4
LT		 752static void vortex_down(struct net_device *dev, int final);
753static int vortex_open(struct net_device *dev);
a095cfc4 754static void mdio_sync(struct vortex_private *vp, int bits);
1da177e4
LT		 755static int mdio_read(struct net_device *dev, int phy_id, int location);
756static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
757static void vortex_timer(unsigned long arg);
758static void rx_oom_timer(unsigned long arg);
27a1de95
SH		 759static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
760 struct net_device *dev);
761static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
762 struct net_device *dev);
1da177e4
LT		 763static int vortex_rx(struct net_device *dev);
764static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 765static irqreturn_t vortex_interrupt(int irq, void *dev_id);
766static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 767static int vortex_close(struct net_device *dev);
768static void dump_tx_ring(struct net_device *dev);
62afe595 769static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 770static struct net_device_stats *vortex_get_stats(struct net_device *dev);
771static void set_rx_mode(struct net_device *dev);
772#ifdef CONFIG_PCI
773static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
774#endif
775static void vortex_tx_timeout(struct net_device *dev);
776static void acpi_set_WOL(struct net_device *dev);
7282d491 777static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 778static void set_8021q_mode(struct net_device *dev, int enable);
779
1da177e4
LT		 780/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
781/* Option count limit only -- unlimited interfaces are supported. */
782#define MAX_UNITS 8
9954ab7f
JL		 783static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
784static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
785static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
786static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
787static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 788static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 789static int global_options = -1;
790static int global_full_duplex = -1;
791static int global_enable_wol = -1;
900fd17d 792static int global_use_mmio = -1;
1da177e4 793
1da177e4
LT		 794/* Variables to work-around the Compaq PCI BIOS32 problem. */
795static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
796static struct net_device *compaq_net_device;
797
798static int vortex_cards_found;
799
800module_param(debug, int, 0);
801module_param(global_options, int, 0);
802module_param_array(options, int, NULL, 0);
803module_param(global_full_duplex, int, 0);
804module_param_array(full_duplex, int, NULL, 0);
805module_param_array(hw_checksums, int, NULL, 0);
806module_param_array(flow_ctrl, int, NULL, 0);
807module_param(global_enable_wol, int, 0);
808module_param_array(enable_wol, int, NULL, 0);
809module_param(rx_copybreak, int, 0);
810module_param(max_interrupt_work, int, 0);
811module_param(compaq_ioaddr, int, 0);
812module_param(compaq_irq, int, 0);
813module_param(compaq_device_id, int, 0);
814module_param(watchdog, int, 0);
900fd17d
JL		 815module_param(global_use_mmio, int, 0);
816module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 817MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
818MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
819MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
820MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 821MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 822MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
823MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
824MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 825MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 826MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
827MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
828MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
829MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
830MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
831MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 832MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
833MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 834
835#ifdef CONFIG_NET_POLL_CONTROLLER
836static void poll_vortex(struct net_device *dev)
837{
838 struct vortex_private *vp = netdev_priv(dev);
839 unsigned long flags;
0d38ff1d 840 local_irq_save(flags);
7d12e780 841 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 842 local_irq_restore(flags);
6aa20a22 843}
1da177e4
LT		 844#endif
845
846#ifdef CONFIG_PM
847
7bfc4ab5 848static int vortex_suspend(struct device *dev)
1da177e4 849{
7bfc4ab5
AV		 850 struct pci_dev *pdev = to_pci_dev(dev);
851 struct net_device *ndev = pci_get_drvdata(pdev);
852
853 if (!ndev || !netif_running(ndev))
854 return 0;
855
856 netif_device_detach(ndev);
857 vortex_down(ndev, 1);
1da177e4 858
1da177e4
LT		 859 return 0;
860}
861
7bfc4ab5 862static int vortex_resume(struct device *dev)
1da177e4 863{
7bfc4ab5
AV		 864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct net_device *ndev = pci_get_drvdata(pdev);
e1265153 866 int err;
1da177e4 867
7bfc4ab5
AV		 868 if (!ndev || !netif_running(ndev))
869 return 0;
870
871 err = vortex_up(ndev);
872 if (err)
873 return err;
874
875 netif_device_attach(ndev);
876
1da177e4
LT		 877 return 0;
878}
879
47145210 880static const struct dev_pm_ops vortex_pm_ops = {
7bfc4ab5
AV		 881 .suspend = vortex_suspend,
882 .resume = vortex_resume,
883 .freeze = vortex_suspend,
884 .thaw = vortex_resume,
885 .poweroff = vortex_suspend,
886 .restore = vortex_resume,
887};
888
889#define VORTEX_PM_OPS (&vortex_pm_ops)
890
891#else /* !CONFIG_PM */
892
893#define VORTEX_PM_OPS NULL
894
895#endif /* !CONFIG_PM */
1da177e4
LT		 896
897#ifdef CONFIG_EISA
898static struct eisa_device_id vortex_eisa_ids[] = {
899 { "TCM5920", CH_3C592 },
900 { "TCM5970", CH_3C597 },
901 { "" }
902};
07563c71 903MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 904
95c408a9 905static int __init vortex_eisa_probe(struct device *device)
1da177e4 906{
62afe595 907 void __iomem *ioaddr;
1da177e4
LT		 908 struct eisa_device *edev;
909
a880c4cd 910 edev = to_eisa_device(device);
1da177e4 911
62afe595 912 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 913 return -EBUSY;
914
62afe595
JL		 915 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
916
917 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 918 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 919 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 920 return -ENODEV;
921 }
922
923 vortex_cards_found++;
924
925 return 0;
926}
927
95c408a9 928static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 929{
930 struct eisa_device *edev;
931 struct net_device *dev;
932 struct vortex_private *vp;
62afe595 933 void __iomem *ioaddr;
1da177e4 934
a880c4cd
SK		 935 edev = to_eisa_device(device);
936 dev = eisa_get_drvdata(edev);
1da177e4
LT		 937
938 if (!dev) {
39738e16 939 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 940 BUG();
941 }
942
943 vp = netdev_priv(dev);
62afe595 944 ioaddr = vp->ioaddr;
6aa20a22 945
a880c4cd
SK		 946 unregister_netdev(dev);
947 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
948 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 949
a880c4cd 950 free_netdev(dev);
1da177e4
LT		 951 return 0;
952}
95c408a9
RB		 953
954static struct eisa_driver vortex_eisa_driver = {
955 .id_table = vortex_eisa_ids,
956 .driver = {
957 .name = "3c59x",
958 .probe = vortex_eisa_probe,
959 .remove = __devexit_p(vortex_eisa_remove)
960 }
961};
962
963#endif /* CONFIG_EISA */
1da177e4
LT		 964
965/* returns count found (>= 0), or negative on error */
a880c4cd 966static int __init vortex_eisa_init(void)
1da177e4
LT		 967{
968 int eisa_found = 0;
969 int orig_cards_found = vortex_cards_found;
970
971#ifdef CONFIG_EISA
c2f6fabb
BH		 972 int err;
973
974 err = eisa_driver_register (&vortex_eisa_driver);
975 if (!err) {
976 /*
977 * Because of the way EISA bus is probed, we cannot assume
978 * any device have been found when we exit from
979 * eisa_driver_register (the bus root driver may not be
980 * initialized yet). So we blindly assume something was
981 * found, and let the sysfs magic happend...
982 */
983 eisa_found = 1;
1da177e4
LT		 984 }
985#endif
6aa20a22 986
1da177e4
LT		 987 /* Special code to work-around the Compaq PCI BIOS32 problem. */
988 if (compaq_ioaddr) {
62afe595
JL		 989 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
990 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 991 }
992
993 return vortex_cards_found - orig_cards_found + eisa_found;
994}
995
996/* returns count (>= 0), or negative on error */
a880c4cd 997static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 998 const struct pci_device_id *ent)
999{
900fd17d
JL		 1000 int rc, unit, pci_bar;
1001 struct vortex_chip_info *vci;
1002 void __iomem *ioaddr;
1da177e4 1003
6aa20a22 1004 /* wake up and enable device */
a880c4cd 1005 rc = pci_enable_device(pdev);
1da177e4
LT		 1006 if (rc < 0)
1007 goto out;
1008
900fd17d
JL		 1009 unit = vortex_cards_found;
1010
1011 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1012 /* Determine the default if the user didn't override us */
1013 vci = &vortex_info_tbl[ent->driver_data];
1014 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1015 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1016 pci_bar = use_mmio[unit] ? 1 : 0;
1017 else
1018 pci_bar = global_use_mmio ? 1 : 0;
1019
1020 ioaddr = pci_iomap(pdev, pci_bar, 0);
1021 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1022 ioaddr = pci_iomap(pdev, 0, 0);
8cd47ea1
KV		 1023 if (!ioaddr) {
1024 pci_disable_device(pdev);
1025 rc = -ENOMEM;
1026 goto out;
1027 }
900fd17d
JL		 1028
1029 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1030 ent->driver_data, unit);
1da177e4 1031 if (rc < 0) {
f89f5d0e 1032 pci_iounmap(pdev, ioaddr);
a880c4cd 1033 pci_disable_device(pdev);
1da177e4
LT		 1034 goto out;
1035 }
1036
1037 vortex_cards_found++;
1038
1039out:
1040 return rc;
1041}
1042
48b47a5e
SH		 1043static const struct net_device_ops boomrang_netdev_ops = {
1044 .ndo_open = vortex_open,
1045 .ndo_stop = vortex_close,
1046 .ndo_start_xmit = boomerang_start_xmit,
1047 .ndo_tx_timeout = vortex_tx_timeout,
1048 .ndo_get_stats = vortex_get_stats,
1049#ifdef CONFIG_PCI
1050 .ndo_do_ioctl = vortex_ioctl,
1051#endif
1052 .ndo_set_multicast_list = set_rx_mode,
1053 .ndo_change_mtu = eth_change_mtu,
1054 .ndo_set_mac_address = eth_mac_addr,
1055 .ndo_validate_addr = eth_validate_addr,
1056#ifdef CONFIG_NET_POLL_CONTROLLER
1057 .ndo_poll_controller = poll_vortex,
1058#endif
1059};
1060
1061static const struct net_device_ops vortex_netdev_ops = {
1062 .ndo_open = vortex_open,
1063 .ndo_stop = vortex_close,
1064 .ndo_start_xmit = vortex_start_xmit,
1065 .ndo_tx_timeout = vortex_tx_timeout,
1066 .ndo_get_stats = vortex_get_stats,
1067#ifdef CONFIG_PCI
1068 .ndo_do_ioctl = vortex_ioctl,
1069#endif
1070 .ndo_set_multicast_list = set_rx_mode,
1071 .ndo_change_mtu = eth_change_mtu,
1072 .ndo_set_mac_address = eth_mac_addr,
1073 .ndo_validate_addr = eth_validate_addr,
1074#ifdef CONFIG_NET_POLL_CONTROLLER
1075 .ndo_poll_controller = poll_vortex,
1076#endif
1077};
1078
1da177e4
LT		 1079/*
1080 * Start up the PCI/EISA device which is described by *gendev.
1081 * Return 0 on success.
1082 *
1083 * NOTE: pdev can be NULL, for the case of a Compaq device
1084 */
1085static int __devinit vortex_probe1(struct device *gendev,
62afe595 1086 void __iomem *ioaddr, int irq,
1da177e4
LT		 1087 int chip_idx, int card_idx)
1088{
1089 struct vortex_private *vp;
1090 int option;
1091 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1092 int i, step;
1093 struct net_device *dev;
1094 static int printed_version;
1095 int retval, print_info;
1096 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1097 const char *print_name = "3c59x";
1da177e4
LT		 1098 struct pci_dev *pdev = NULL;
1099 struct eisa_device *edev = NULL;
1100
1101 if (!printed_version) {
39738e16 1102 pr_info("%s", version);
1da177e4
LT		 1103 printed_version = 1;
1104 }
1105
1106 if (gendev) {
1107 if ((pdev = DEVICE_PCI(gendev))) {
1108 print_name = pci_name(pdev);
1109 }
1110
1111 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1112 print_name = dev_name(&edev->dev);
1da177e4
LT		 1113 }
1114 }
1115
1116 dev = alloc_etherdev(sizeof(*vp));
1117 retval = -ENOMEM;
1118 if (!dev) {
39738e16 1119 pr_err(PFX "unable to allocate etherdev, aborting\n");
1da177e4
LT		 1120 goto out;
1121 }
1da177e4
LT		 1122 SET_NETDEV_DEV(dev, gendev);
1123 vp = netdev_priv(dev);
1124
1125 option = global_options;
1126
1127 /* The lower four bits are the media type. */
1128 if (dev->mem_start) {
1129 /*
1130 * The 'options' param is passed in as the third arg to the
1131 * LILO 'ether=' argument for non-modular use
1132 */
1133 option = dev->mem_start;
1134 }
1135 else if (card_idx < MAX_UNITS) {
1136 if (options[card_idx] >= 0)
1137 option = options[card_idx];
1138 }
1139
1140 if (option > 0) {
1141 if (option & 0x8000)
1142 vortex_debug = 7;
1143 if (option & 0x4000)
1144 vortex_debug = 2;
1145 if (option & 0x0400)
1146 vp->enable_wol = 1;
1147 }
1148
1149 print_info = (vortex_debug > 1);
1150 if (print_info)
39738e16 1151 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1152
39738e16 1153 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1154 print_name,
1155 pdev ? "PCI" : "EISA",
1156 vci->name,
1157 ioaddr);
1158
62afe595 1159 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1160 dev->irq = irq;
1161 dev->mtu = mtu;
62afe595 1162 vp->ioaddr = ioaddr;
1da177e4
LT		 1163 vp->large_frames = mtu > 1500;
1164 vp->drv_flags = vci->drv_flags;
1165 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1166 vp->io_size = vci->io_size;
1167 vp->card_idx = card_idx;
a095cfc4 1168 vp->window = -1;
1da177e4
LT		 1169
1170 /* module list only for Compaq device */
1171 if (gendev == NULL) {
1172 compaq_net_device = dev;
1173 }
1174
1175 /* PCI-only startup logic */
1176 if (pdev) {
1177 /* EISA resources already marked, so only PCI needs to do this here */
1178 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1179 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1180 vp->must_free_region = 1;
1181
6aa20a22 1182 /* enable bus-mastering if necessary */
1da177e4 1183 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1184 pci_set_master(pdev);
1da177e4
LT		 1185
1186 if (vci->drv_flags & IS_VORTEX) {
1187 u8 pci_latency;
1188 u8 new_latency = 248;
1189
1190 /* Check the PCI latency value. On the 3c590 series the latency timer
1191 must be set to the maximum value to avoid data corruption that occurs
1192 when the timer expires during a transfer. This bug exists the Vortex
1193 chip only. */
1194 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1195 if (pci_latency < new_latency) {
39738e16 1196 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1197 print_name, pci_latency, new_latency);
39738e16 1198 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1199 }
1200 }
1201 }
1202
1203 spin_lock_init(&vp->lock);
de847272
BH		 1204 spin_lock_init(&vp->mii_lock);
1205 spin_lock_init(&vp->window_lock);
1da177e4
LT		 1206 vp->gendev = gendev;
1207 vp->mii.dev = dev;
1208 vp->mii.mdio_read = mdio_read;
1209 vp->mii.mdio_write = mdio_write;
1210 vp->mii.phy_id_mask = 0x1f;
1211 vp->mii.reg_num_mask = 0x1f;
1212
1213 /* Makes sure rings are at least 16 byte aligned. */
1214 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1215 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1216 &vp->rx_ring_dma);
1217 retval = -ENOMEM;
cc2d6596 1218 if (!vp->rx_ring)
1da177e4
LT		 1219 goto free_region;
1220
1221 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1222 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1223
1224 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1225 * instead of a module list */
1da177e4
LT		 1226 if (pdev)
1227 pci_set_drvdata(pdev, dev);
1228 if (edev)
a880c4cd 1229 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1230
1231 vp->media_override = 7;
1232 if (option >= 0) {
1233 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1234 if (vp->media_override != 7)
1235 vp->medialock = 1;
1236 vp->full_duplex = (option & 0x200) ? 1 : 0;
1237 vp->bus_master = (option & 16) ? 1 : 0;
1238 }
1239
1240 if (global_full_duplex > 0)
1241 vp->full_duplex = 1;
1242 if (global_enable_wol > 0)
1243 vp->enable_wol = 1;
1244
1245 if (card_idx < MAX_UNITS) {
1246 if (full_duplex[card_idx] > 0)
1247 vp->full_duplex = 1;
1248 if (flow_ctrl[card_idx] > 0)
1249 vp->flow_ctrl = 1;
1250 if (enable_wol[card_idx] > 0)
1251 vp->enable_wol = 1;
1252 }
1253
125d5ce8 1254 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1255 vp->options = option;
1256 /* Read the station address from the EEPROM. */
1da177e4
LT		 1257 {
1258 int base;
1259
1260 if (vci->drv_flags & EEPROM_8BIT)
1261 base = 0x230;
1262 else if (vci->drv_flags & EEPROM_OFFSET)
1263 base = EEPROM_Read + 0x30;
1264 else
1265 base = EEPROM_Read;
1266
1267 for (i = 0; i < 0x40; i++) {
1268 int timer;
a095cfc4 1269 window_write16(vp, base + i, 0, Wn0EepromCmd);
1da177e4
LT		 1270 /* Pause for at least 162 us. for the read to take place. */
1271 for (timer = 10; timer >= 0; timer--) {
1272 udelay(162);
a095cfc4
BH		 1273 if ((window_read16(vp, 0, Wn0EepromCmd) &
1274 0x8000) == 0)
1da177e4
LT		 1275 break;
1276 }
a095cfc4 1277 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1da177e4
LT		 1278 }
1279 }
1280 for (i = 0; i < 0x18; i++)
1281 checksum ^= eeprom[i];
1282 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1283 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1284 while (i < 0x21)
1285 checksum ^= eeprom[i++];
1286 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1287 }
1288 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1289 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1290 for (i = 0; i < 3; i++)
cc2d6596 1291 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1292 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1293 if (print_info)
39738e16 1294 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1295 /* Unfortunately an all zero eeprom passes the checksum and this
1296 gets found in the wild in failure cases. Crypto is hard 8) */
1297 if (!is_valid_ether_addr(dev->dev_addr)) {
1298 retval = -EINVAL;
39738e16 1299 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1300 goto free_ring; /* With every pack */
1301 }
1da177e4 1302 for (i = 0; i < 6; i++)
a095cfc4 1303 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1304
1da177e4 1305 if (print_info)
39738e16 1306 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1307 /* Tell them about an invalid IRQ. */
60e4ad7a 1308 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1309 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1310 dev->irq);
1da177e4 1311
a095cfc4 1312 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1313 if (print_info) {
39738e16
AB		 1314 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1315 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1316 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1317 }
1318
1319
1320 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1321 unsigned short n;
1322
62afe595
JL		 1323 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1324 if (!vp->cb_fn_base) {
1da177e4 1325 retval = -ENOMEM;
62afe595 1326 goto free_ring;
1da177e4 1327 }
62afe595 1328
1da177e4 1329 if (print_info) {
39738e16 1330 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1331 print_name,
1332 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1333 vp->cb_fn_base);
1da177e4 1334 }
1da177e4 1335
a095cfc4 1336 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1337 if (vp->drv_flags & INVERT_LED_PWR)
1338 n |= 0x10;
1339 if (vp->drv_flags & INVERT_MII_PWR)
1340 n |= 0x4000;
a095cfc4 1341 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4 1342 if (vp->drv_flags & WNO_XCVR_PWR) {
a095cfc4 1343 window_write16(vp, 0x0800, 0, 0);
1da177e4
LT		 1344 }
1345 }
1346
1347 /* Extract our information from the EEPROM data. */
1348 vp->info1 = eeprom[13];
1349 vp->info2 = eeprom[15];
1350 vp->capabilities = eeprom[16];
1351
1352 if (vp->info1 & 0x8000) {
1353 vp->full_duplex = 1;
1354 if (print_info)
39738e16 1355 pr_info("Full duplex capable\n");
1da177e4
LT		 1356 }
1357
1358 {
f71e1309 1359 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4 1360 unsigned int config;
a095cfc4 1361 vp->available_media = window_read16(vp, 3, Wn3_Options);
1da177e4
LT		 1362 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1363 vp->available_media = 0x40;
a095cfc4 1364 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1365 if (print_info) {
39738e16 1366 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
a095cfc4 1367 config, window_read16(vp, 3, Wn3_Options));
39738e16 1368 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1369 8 << RAM_SIZE(config),
1370 RAM_WIDTH(config) ? "word" : "byte",
1371 ram_split[RAM_SPLIT(config)],
1372 AUTOSELECT(config) ? "autoselect/" : "",
1373 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1374 media_tbl[XCVR(config)].name);
1375 }
1376 vp->default_media = XCVR(config);
1377 if (vp->default_media == XCVR_NWAY)
1378 vp->has_nway = 1;
1379 vp->autoselect = AUTOSELECT(config);
1380 }
1381
1382 if (vp->media_override != 7) {
39738e16 1383 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1384 print_name, vp->media_override,
1385 media_tbl[vp->media_override].name);
1386 dev->if_port = vp->media_override;
1387 } else
1388 dev->if_port = vp->default_media;
1389
1390 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1391 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1392 int phy, phy_idx = 0;
1da177e4
LT		 1393 mii_preamble_required++;
1394 if (vp->drv_flags & EXTRA_PREAMBLE)
1395 mii_preamble_required++;
344e0f62 1396 mdio_sync(vp, 32);
106427e6 1397 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1398 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1399 int mii_status, phyx;
1400
1401 /*
1402 * For the 3c905CX we look at index 24 first, because it bogusly
1403 * reports an external PHY at all indices
1404 */
1405 if (phy == 0)
1406 phyx = 24;
1407 else if (phy <= 24)
1408 phyx = phy - 1;
1409 else
1410 phyx = phy;
106427e6 1411 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1412 if (mii_status && mii_status != 0xffff) {
1413 vp->phys[phy_idx++] = phyx;
1414 if (print_info) {
39738e16
AB		 1415 pr_info(" MII transceiver found at address %d, status %4x.\n",
1416 phyx, mii_status);
1da177e4
LT		 1417 }
1418 if ((mii_status & 0x0040) == 0)
1419 mii_preamble_required++;
1420 }
1421 }
1422 mii_preamble_required--;
1423 if (phy_idx == 0) {
39738e16 1424 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1425 vp->phys[0] = 24;
1426 } else {
106427e6 1427 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1428 if (vp->full_duplex) {
1429 /* Only advertise the FD media types. */
1430 vp->advertising &= ~0x02A0;
1431 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1432 }
1433 }
1434 vp->mii.phy_id = vp->phys[0];
1435 }
1436
1437 if (vp->capabilities & CapBusMaster) {
1438 vp->full_bus_master_tx = 1;
1439 if (print_info) {
39738e16 1440 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1441 (vp->info2 & 1) ? "early" : "whole-frame" );
1442 }
1443 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1444 vp->bus_master = 0; /* AKPM: vortex only */
1445 }
1446
1447 /* The 3c59x-specific entries in the device structure. */
1da177e4 1448 if (vp->full_bus_master_tx) {
48b47a5e 1449 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1450 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1451 if (card_idx < MAX_UNITS &&
1452 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1453 hw_checksums[card_idx] == 1)) {
d311b0d3 1454 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1455 }
48b47a5e
SH		 1456 } else
1457 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1458
1459 if (print_info) {
39738e16 1460 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1461 print_name,
1462 (dev->features & NETIF_F_SG) ? "en":"dis",
1463 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1464 }
1465
1da177e4 1466 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1467 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1468
1da177e4
LT		 1469 if (pdev) {
1470 vp->pm_state_valid = 1;
1471 pci_save_state(VORTEX_PCI(vp));
1472 acpi_set_WOL(dev);
1473 }
1474 retval = register_netdev(dev);
1475 if (retval == 0)
1476 return 0;
1477
1478free_ring:
1479 pci_free_consistent(pdev,
1480 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1481 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1482 vp->rx_ring,
1483 vp->rx_ring_dma);
1484free_region:
1485 if (vp->must_free_region)
62afe595 1486 release_region(dev->base_addr, vci->io_size);
1da177e4 1487 free_netdev(dev);
39738e16 1488 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1489out:
1490 return retval;
1491}
1492
1493static void
1494issue_and_wait(struct net_device *dev, int cmd)
1495{
62afe595
JL		 1496 struct vortex_private *vp = netdev_priv(dev);
1497 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1498 int i;
1499
62afe595 1500 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1501 for (i = 0; i < 2000; i++) {
62afe595 1502 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1503 return;
1504 }
1505
1506 /* OK, that didn't work. Do it the slow way. One second */
1507 for (i = 0; i < 100000; i++) {
62afe595 1508 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1509 if (vortex_debug > 1)
39738e16 1510 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1511 dev->name, cmd, i * 10);
1512 return;
1513 }
1514 udelay(10);
1515 }
39738e16 1516 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1517 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1518}
1519
125d5ce8
SK		 1520static void
1521vortex_set_duplex(struct net_device *dev)
1522{
1523 struct vortex_private *vp = netdev_priv(dev);
125d5ce8 1524
39738e16 1525 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1526 dev->name, (vp->full_duplex) ? "full" : "half");
1527
125d5ce8 1528 /* Set the full-duplex bit. */
a095cfc4
BH		 1529 window_write16(vp,
1530 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1531 (vp->large_frames ? 0x40 : 0) |
1532 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1533 0x100 : 0),
1534 3, Wn3_MAC_Ctrl);
125d5ce8
SK		 1535}
1536
1537static void vortex_check_media(struct net_device *dev, unsigned int init)
1538{
1539 struct vortex_private *vp = netdev_priv(dev);
1540 unsigned int ok_to_print = 0;
1541
1542 if (vortex_debug > 3)
1543 ok_to_print = 1;
1544
1545 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1546 vp->full_duplex = vp->mii.full_duplex;
1547 vortex_set_duplex(dev);
1548 } else if (init) {
1549 vortex_set_duplex(dev);
1550 }
1551}
1552
c8303d10 1553static int
1da177e4
LT		 1554vortex_up(struct net_device *dev)
1555{
1da177e4 1556 struct vortex_private *vp = netdev_priv(dev);
62afe595 1557 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1558 unsigned int config;
0280f9f9 1559 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1560
1561 if (VORTEX_PCI(vp)) {
1562 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1563 if (vp->pm_state_valid)
1564 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1565 err = pci_enable_device(VORTEX_PCI(vp));
1566 if (err) {
39738e16 1567 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1568 dev->name);
1569 goto err_out;
1570 }
1da177e4
LT		 1571 }
1572
1573 /* Before initializing select the active media port. */
a095cfc4 1574 config = window_read32(vp, 3, Wn3_Config);
1da177e4
LT		 1575
1576 if (vp->media_override != 7) {
39738e16 1577 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1578 dev->name, vp->media_override,
1579 media_tbl[vp->media_override].name);
1580 dev->if_port = vp->media_override;
1581 } else if (vp->autoselect) {
1582 if (vp->has_nway) {
1583 if (vortex_debug > 1)
39738e16 1584 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1585 dev->name, dev->if_port);
1586 dev->if_port = XCVR_NWAY;
1587 } else {
1588 /* Find first available media type, starting with 100baseTx. */
1589 dev->if_port = XCVR_100baseTx;
1590 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1591 dev->if_port = media_tbl[dev->if_port].next;
1592 if (vortex_debug > 1)
39738e16 1593 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1594 dev->name, media_tbl[dev->if_port].name);
1595 }
1596 } else {
1597 dev->if_port = vp->default_media;
1598 if (vortex_debug > 1)
39738e16 1599 pr_info("%s: using default media %s\n",
1da177e4
LT		 1600 dev->name, media_tbl[dev->if_port].name);
1601 }
1602
1603 init_timer(&vp->timer);
1604 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1605 vp->timer.data = (unsigned long)dev;
1606 vp->timer.function = vortex_timer; /* timer handler */
1607 add_timer(&vp->timer);
1608
1609 init_timer(&vp->rx_oom_timer);
1610 vp->rx_oom_timer.data = (unsigned long)dev;
1611 vp->rx_oom_timer.function = rx_oom_timer;
1612
1613 if (vortex_debug > 1)
39738e16 1614 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1615 dev->name, media_tbl[dev->if_port].name);
1616
125d5ce8 1617 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1618 config = BFINS(config, dev->if_port, 20, 4);
1619 if (vortex_debug > 6)
39738e16 1620 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
a095cfc4 1621 window_write32(vp, config, 3, Wn3_Config);
1da177e4
LT		 1622
1623 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
09ce3512
SK		 1624 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1625 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1626 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1627 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1628
125d5ce8 1629 vortex_check_media(dev, 1);
1da177e4 1630 }
125d5ce8
SK		 1631 else
1632 vortex_set_duplex(dev);
1da177e4 1633
09ce3512
SK		 1634 issue_and_wait(dev, TxReset);
1635 /*
1636 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1637 */
1638 issue_and_wait(dev, RxReset|0x04);
1639
1da177e4 1640
62afe595 1641 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1642
1643 if (vortex_debug > 1) {
39738e16 1644 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
a095cfc4 1645 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1da177e4
LT		 1646 }
1647
1648 /* Set the station address and mask in window 2 each time opened. */
1da177e4 1649 for (i = 0; i < 6; i++)
a095cfc4 1650 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1651 for (; i < 12; i+=2)
a095cfc4 1652 window_write16(vp, 0, 2, i);
1da177e4
LT		 1653
1654 if (vp->cb_fn_base) {
a095cfc4 1655 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1656 if (vp->drv_flags & INVERT_LED_PWR)
1657 n |= 0x10;
1658 if (vp->drv_flags & INVERT_MII_PWR)
1659 n |= 0x4000;
a095cfc4 1660 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4
LT		 1661 }
1662
1663 if (dev->if_port == XCVR_10base2)
1664 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1665 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4 1666 if (dev->if_port != XCVR_NWAY) {
a095cfc4
BH		 1667 window_write16(vp,
1668 (window_read16(vp, 4, Wn4_Media) &
1669 ~(Media_10TP|Media_SQE)) |
1670 media_tbl[dev->if_port].media_bits,
1671 4, Wn4_Media);
1da177e4
LT		 1672 }
1673
1674 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1675 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4 1676 for (i = 0; i < 10; i++)
a095cfc4
BH		 1677 window_read8(vp, 6, i);
1678 window_read16(vp, 6, 10);
1679 window_read16(vp, 6, 12);
1da177e4 1680 /* New: On the Vortex we must also clear the BadSSD counter. */
a095cfc4 1681 window_read8(vp, 4, 12);
1da177e4 1682 /* ..and on the Boomerang we enable the extra statistics bits. */
a095cfc4 1683 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1da177e4
LT		 1684
1685 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1686 vp->cur_rx = vp->dirty_rx = 0;
1687 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1688 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1689 iowrite32(0x0020, ioaddr + PktStatus);
1690 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1691 }
1692 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1693 vp->cur_tx = vp->dirty_tx = 0;
1694 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1695 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1696 /* Clear the Rx, Tx rings. */
1697 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1698 vp->rx_ring[i].status = 0;
1699 for (i = 0; i < TX_RING_SIZE; i++)
1700 vp->tx_skbuff[i] = NULL;
62afe595 1701 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1702 }
1703 /* Set receiver mode: presumably accept b-case and phys addr only. */
1704 set_rx_mode(dev);
1705 /* enable 802.1q tagged frames */
1706 set_8021q_mode(dev, 1);
62afe595 1707 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1708
62afe595
JL		 1709 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1710 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1711 /* Allow status bits to be seen. */
1712 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1713 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1714 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1715 (vp->bus_master ? DMADone : 0);
1716 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1717 (vp->full_bus_master_rx ? 0 : RxComplete) |
1718 StatsFull | HostError | TxComplete | IntReq
1719 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1720 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1721 /* Ack all pending events, and set active indicator mask. */
62afe595 1722 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1723 ioaddr + EL3_CMD);
62afe595 1724 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1725 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1726 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1727 netif_start_queue (dev);
c8303d10
MH		 1728err_out:
1729 return err;
1da177e4
LT		 1730}
1731
1732static int
1733vortex_open(struct net_device *dev)
1734{
1735 struct vortex_private *vp = netdev_priv(dev);
1736 int i;
1737 int retval;
1738
1739 /* Use the now-standard shared IRQ implementation. */
1740 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1741 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1742 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1743 goto err;
1da177e4
LT		 1744 }
1745
1746 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1747 if (vortex_debug > 2)
39738e16 1748 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1749 for (i = 0; i < RX_RING_SIZE; i++) {
1750 struct sk_buff *skb;
1751 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1752 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1753 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1754
1755 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1756 GFP_KERNEL);
1da177e4
LT		 1757 vp->rx_skbuff[i] = skb;
1758 if (skb == NULL)
1759 break; /* Bad news! */
9a5d3414
SH		 1760
1761 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1762 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1763 }
1764 if (i != RX_RING_SIZE) {
1765 int j;
39738e16 1766 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1767 for (j = 0; j < i; j++) {
1768 if (vp->rx_skbuff[j]) {
1769 dev_kfree_skb(vp->rx_skbuff[j]);
1770 vp->rx_skbuff[j] = NULL;
1771 }
1772 }
1773 retval = -ENOMEM;
c8303d10 1774 goto err_free_irq;
1da177e4
LT		 1775 }
1776 /* Wrap the ring. */
1777 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1778 }
1779
c8303d10
MH		 1780 retval = vortex_up(dev);
1781 if (!retval)
1782 goto out;
1da177e4 1783
c8303d10 1784err_free_irq:
1da177e4 1785 free_irq(dev->irq, dev);
c8303d10 1786err:
1da177e4 1787 if (vortex_debug > 1)
39738e16 1788 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1789out:
1da177e4
LT		 1790 return retval;
1791}
1792
1793static void
1794vortex_timer(unsigned long data)
1795{
1796 struct net_device *dev = (struct net_device *)data;
1797 struct vortex_private *vp = netdev_priv(dev);
62afe595 1798 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1799 int next_tick = 60*HZ;
1800 int ok = 0;
a095cfc4 1801 int media_status;
1da177e4
LT		 1802
1803 if (vortex_debug > 2) {
39738e16 1804 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1805 dev->name, media_tbl[dev->if_port].name);
39738e16 1806 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1807 }
1808
a095cfc4 1809 media_status = window_read16(vp, 4, Wn4_Media);
1da177e4
LT		 1810 switch (dev->if_port) {
1811 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1812 if (media_status & Media_LnkBeat) {
1813 netif_carrier_on(dev);
1814 ok = 1;
1815 if (vortex_debug > 1)
39738e16 1816 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1817 dev->name, media_tbl[dev->if_port].name, media_status);
1818 } else {
1819 netif_carrier_off(dev);
1820 if (vortex_debug > 1) {
39738e16 1821 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1822 dev->name, media_tbl[dev->if_port].name, media_status);
1823 }
1824 }
1825 break;
1826 case XCVR_MII: case XCVR_NWAY:
1827 {
1da177e4 1828 ok = 1;
125d5ce8 1829 vortex_check_media(dev, 0);
1da177e4
LT		 1830 }
1831 break;
1832 default: /* Other media types handled by Tx timeouts. */
1833 if (vortex_debug > 1)
39738e16 1834 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1835 dev->name, media_tbl[dev->if_port].name, media_status);
1836 ok = 1;
1837 }
b4ff6450
SK		 1838
1839 if (!netif_carrier_ok(dev))
1840 next_tick = 5*HZ;
1841
e94d10eb
SK		 1842 if (vp->medialock)
1843 goto leave_media_alone;
1844
a880c4cd 1845 if (!ok) {
1da177e4
LT		 1846 unsigned int config;
1847
de847272
BH		 1848 spin_lock_irq(&vp->lock);
1849
1da177e4
LT		 1850 do {
1851 dev->if_port = media_tbl[dev->if_port].next;
1852 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1853 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1854 dev->if_port = vp->default_media;
1855 if (vortex_debug > 1)
39738e16 1856 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1857 dev->name, media_tbl[dev->if_port].name);
1858 } else {
1859 if (vortex_debug > 1)
39738e16 1860 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1861 dev->name, media_tbl[dev->if_port].name);
1862 next_tick = media_tbl[dev->if_port].wait;
1863 }
a095cfc4
BH		 1864 window_write16(vp,
1865 (media_status & ~(Media_10TP|Media_SQE)) |
1866 media_tbl[dev->if_port].media_bits,
1867 4, Wn4_Media);
1da177e4 1868
a095cfc4 1869 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1870 config = BFINS(config, dev->if_port, 20, 4);
a095cfc4 1871 window_write32(vp, config, 3, Wn3_Config);
1da177e4 1872
62afe595 1873 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1874 ioaddr + EL3_CMD);
1875 if (vortex_debug > 1)
39738e16 1876 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4 1877 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
de847272
BH		 1878
1879 spin_unlock_irq(&vp->lock);
1da177e4 1880 }
1da177e4
LT		 1881
1882leave_media_alone:
1883 if (vortex_debug > 2)
39738e16 1884 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1885 dev->name, media_tbl[dev->if_port].name);
1886
1887 mod_timer(&vp->timer, RUN_AT(next_tick));
1888 if (vp->deferred)
62afe595 1889 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1890}
1891
1892static void vortex_tx_timeout(struct net_device *dev)
1893{
1894 struct vortex_private *vp = netdev_priv(dev);
62afe595 1895 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1896
39738e16 1897 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1898 dev->name, ioread8(ioaddr + TxStatus),
1899 ioread16(ioaddr + EL3_STATUS));
39738e16 1900 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
a095cfc4
BH		 1901 window_read16(vp, 4, Wn4_NetDiag),
1902 window_read16(vp, 4, Wn4_Media),
62afe595 1903 ioread32(ioaddr + PktStatus),
a095cfc4 1904 window_read16(vp, 4, Wn4_FIFODiag));
1da177e4 1905 /* Slight code bloat to be user friendly. */
62afe595 1906 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1907 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1908 " network cable problem?\n", dev->name);
62afe595 1909 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1910 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1911 " IRQ blocked by another device?\n", dev->name);
1912 /* Bad idea here.. but we might as well handle a few events. */
1913 {
1914 /*
1915 * Block interrupts because vortex_interrupt does a bare spin_lock()
1916 */
1917 unsigned long flags;
1918 local_irq_save(flags);
1919 if (vp->full_bus_master_tx)
7d12e780 1920 boomerang_interrupt(dev->irq, dev);
1da177e4 1921 else
7d12e780 1922 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1923 local_irq_restore(flags);
1924 }
1925 }
1926
1927 if (vortex_debug > 0)
1928 dump_tx_ring(dev);
1929
1930 issue_and_wait(dev, TxReset);
1931
1daad055 1932 dev->stats.tx_errors++;
1da177e4 1933 if (vp->full_bus_master_tx) {
39738e16 1934 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1935 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1936 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1937 ioaddr + DownListPtr);
1938 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1939 netif_wake_queue (dev);
1940 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1941 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1942 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1943 } else {
1daad055 1944 dev->stats.tx_dropped++;
1da177e4
LT		 1945 netif_wake_queue(dev);
1946 }
6aa20a22 1947
1da177e4 1948 /* Issue Tx Enable */
62afe595 1949 iowrite16(TxEnable, ioaddr + EL3_CMD);
1ae5dc34 1950 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1951}
1952
1953/*
1954 * Handle uncommon interrupt sources. This is a separate routine to minimize
1955 * the cache impact.
1956 */
1957static void
1958vortex_error(struct net_device *dev, int status)
1959{
1960 struct vortex_private *vp = netdev_priv(dev);
62afe595 1961 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1962 int do_tx_reset = 0, reset_mask = 0;
1963 unsigned char tx_status = 0;
1964
1965 if (vortex_debug > 2) {
39738e16 1966 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1967 }
1968
1969 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1970 tx_status = ioread8(ioaddr + TxStatus);
1da177e4 1971 /* Presumably a tx-timeout. We must merely re-enable. */
8e95a202
JP		 1972 if (vortex_debug > 2 ||
1973 (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1974 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1975 dev->name, tx_status);
1976 if (tx_status == 0x82) {
39738e16 1977 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1978 "Documentation/networking/vortex.txt\n");
1979 }
1980 dump_tx_ring(dev);
1981 }
1daad055
PZ		 1982 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1983 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1984 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1985 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1986 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1987 do_tx_reset = 1;
0000754c
AM		 1988 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1989 do_tx_reset = 1;
1990 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1991 } else { /* Merely re-enable the transmitter. */
62afe595 1992 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1993 }
1994 }
1995
1996 if (status & RxEarly) { /* Rx early is unused. */
1997 vortex_rx(dev);
62afe595 1998 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1999 }
2000 if (status & StatsFull) { /* Empty statistics. */
2001 static int DoneDidThat;
2002 if (vortex_debug > 4)
39738e16 2003 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 2004 update_stats(ioaddr, dev);
2005 /* HACK: Disable statistics as an interrupt source. */
2006 /* This occurs when we have the wrong media type! */
2007 if (DoneDidThat == 0 &&
62afe595 2008 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 2009 pr_warning("%s: Updating statistics failed, disabling "
1da177e4 2010 "stats as an interrupt source.\n", dev->name);
a095cfc4
BH		 2011 iowrite16(SetIntrEnb |
2012 (window_read16(vp, 5, 10) & ~StatsFull),
2013 ioaddr + EL3_CMD);
1da177e4 2014 vp->intr_enable &= ~StatsFull;
1da177e4
LT		 2015 DoneDidThat++;
2016 }
2017 }
2018 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2019 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2020 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2021 }
2022 if (status & HostError) {
2023 u16 fifo_diag;
a095cfc4 2024 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
39738e16 2025 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2026 dev->name, fifo_diag);
2027 /* Adapter failure requires Tx/Rx reset and reinit. */
2028 if (vp->full_bus_master_tx) {
62afe595 2029 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2030 /* 0x80000000 PCI master abort. */
2031 /* 0x40000000 PCI target abort. */
2032 if (vortex_debug)
39738e16 2033 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2034
2035 /* In this case, blow the card away */
2036 /* Must not enter D3 or we can't legally issue the reset! */
2037 vortex_down(dev, 0);
2038 issue_and_wait(dev, TotalReset | 0xff);
2039 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2040 } else if (fifo_diag & 0x0400)
2041 do_tx_reset = 1;
2042 if (fifo_diag & 0x3000) {
2043 /* Reset Rx fifo and upload logic */
2044 issue_and_wait(dev, RxReset|0x07);
2045 /* Set the Rx filter to the current state. */
2046 set_rx_mode(dev);
2047 /* enable 802.1q VLAN tagged frames */
2048 set_8021q_mode(dev, 1);
62afe595
JL		 2049 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2050 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2051 }
2052 }
2053
2054 if (do_tx_reset) {
2055 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2056 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2057 if (!vp->full_bus_master_tx)
2058 netif_wake_queue(dev);
2059 }
2060}
2061
27a1de95 2062static netdev_tx_t
1da177e4
LT		 2063vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2064{
2065 struct vortex_private *vp = netdev_priv(dev);
62afe595 2066 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2067
2068 /* Put out the doubleword header... */
62afe595 2069 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2070 if (vp->bus_master) {
2071 /* Set the bus-master controller to transfer the packet. */
2072 int len = (skb->len + 3) & ~3;
a095cfc4
BH		 2073 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2074 PCI_DMA_TODEVICE);
de847272 2075 spin_lock_irq(&vp->window_lock);
a095cfc4
BH		 2076 window_set(vp, 7);
2077 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
62afe595 2078 iowrite16(len, ioaddr + Wn7_MasterLen);
de847272 2079 spin_unlock_irq(&vp->window_lock);
1da177e4 2080 vp->tx_skb = skb;
62afe595 2081 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2082 /* netif_wake_queue() will be called at the DMADone interrupt. */
2083 } else {
2084 /* ... and the packet rounded to a doubleword. */
62afe595 2085 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2086 dev_kfree_skb (skb);
62afe595 2087 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2088 netif_start_queue (dev); /* AKPM: redundant? */
2089 } else {
2090 /* Interrupt us when the FIFO has room for max-sized packet. */
2091 netif_stop_queue(dev);
62afe595 2092 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2093 }
2094 }
2095
1da177e4
LT		 2096
2097 /* Clear the Tx status stack. */
2098 {
2099 int tx_status;
2100 int i = 32;
2101
62afe595 2102 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2103 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2104 if (vortex_debug > 2)
39738e16 2105 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2106 dev->name, tx_status);
1daad055
PZ		 2107 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2108 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2109 if (tx_status & 0x30) {
2110 issue_and_wait(dev, TxReset);
2111 }
62afe595 2112 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2113 }
62afe595 2114 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2115 }
2116 }
6ed10654 2117 return NETDEV_TX_OK;
1da177e4
LT		 2118}
2119
27a1de95 2120static netdev_tx_t
1da177e4
LT		 2121boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2122{
2123 struct vortex_private *vp = netdev_priv(dev);
62afe595 2124 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2125 /* Calculate the next Tx descriptor entry. */
2126 int entry = vp->cur_tx % TX_RING_SIZE;
2127 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2128 unsigned long flags;
2129
2130 if (vortex_debug > 6) {
39738e16
AB		 2131 pr_debug("boomerang_start_xmit()\n");
2132 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2133 dev->name, vp->cur_tx);
1da177e4
LT		 2134 }
2135
2136 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2137 if (vortex_debug > 0)
39738e16 2138 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2139 dev->name);
2140 netif_stop_queue(dev);
5b548140 2141 return NETDEV_TX_BUSY;
1da177e4
LT		 2142 }
2143
2144 vp->tx_skbuff[entry] = skb;
2145
2146 vp->tx_ring[entry].next = 0;
2147#if DO_ZEROCOPY
84fa7933 2148 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2149 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2150 else
2151 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2152
2153 if (!skb_shinfo(skb)->nr_frags) {
2154 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2155 skb->len, PCI_DMA_TODEVICE));
2156 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2157 } else {
2158 int i;
2159
2160 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
e743d313
ED		 2161 skb_headlen(skb), PCI_DMA_TODEVICE));
2162 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
1da177e4
LT		 2163
2164 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2165 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2166
2167 vp->tx_ring[entry].frag[i+1].addr =
2168 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2169 (void*)page_address(frag->page) + frag->page_offset,
2170 frag->size, PCI_DMA_TODEVICE));
2171
2172 if (i == skb_shinfo(skb)->nr_frags-1)
2173 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2174 else
2175 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2176 }
2177 }
2178#else
2179 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2180 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2181 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2182#endif
2183
2184 spin_lock_irqsave(&vp->lock, flags);
2185 /* Wait for the stall to complete. */
2186 issue_and_wait(dev, DownStall);
2187 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2188 if (ioread32(ioaddr + DownListPtr) == 0) {
2189 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2190 vp->queued_packet++;
2191 }
2192
2193 vp->cur_tx++;
2194 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2195 netif_stop_queue (dev);
2196 } else { /* Clear previous interrupt enable. */
2197#if defined(tx_interrupt_mitigation)
2198 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2199 * were selected, this would corrupt DN_COMPLETE. No?
2200 */
2201 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2202#endif
2203 }
62afe595 2204 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 2205 spin_unlock_irqrestore(&vp->lock, flags);
6ed10654 2206 return NETDEV_TX_OK;
1da177e4
LT		 2207}
2208
2209/* The interrupt handler does all of the Rx thread work and cleans up
2210 after the Tx thread. */
2211
2212/*
2213 * This is the ISR for the vortex series chips.
2214 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2215 */
2216
2217static irqreturn_t
7d12e780 2218vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2219{
2220 struct net_device *dev = dev_id;
2221 struct vortex_private *vp = netdev_priv(dev);
62afe595 2222 void __iomem *ioaddr;
1da177e4
LT		 2223 int status;
2224 int work_done = max_interrupt_work;
2225 int handled = 0;
2226
62afe595 2227 ioaddr = vp->ioaddr;
1da177e4
LT		 2228 spin_lock(&vp->lock);
2229
62afe595 2230 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2231
2232 if (vortex_debug > 6)
39738e16 2233 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2234
2235 if ((status & IntLatch) == 0)
2236 goto handler_exit; /* No interrupt: shared IRQs cause this */
2237 handled = 1;
2238
2239 if (status & IntReq) {
2240 status |= vp->deferred;
2241 vp->deferred = 0;
2242 }
2243
2244 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2245 goto handler_exit;
2246
2247 if (vortex_debug > 4)
39738e16 2248 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2249 dev->name, status, ioread8(ioaddr + Timer));
1da177e4 2250
de847272 2251 spin_lock(&vp->window_lock);
a095cfc4
BH		 2252 window_set(vp, 7);
2253
1da177e4
LT		 2254 do {
2255 if (vortex_debug > 5)
39738e16 2256 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2257 dev->name, status);
2258 if (status & RxComplete)
2259 vortex_rx(dev);
2260
2261 if (status & TxAvailable) {
2262 if (vortex_debug > 5)
39738e16 2263 pr_debug(" TX room bit was handled.\n");
1da177e4 2264 /* There's room in the FIFO for a full-sized packet. */
62afe595 2265 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2266 netif_wake_queue (dev);
2267 }
2268
2269 if (status & DMADone) {
62afe595
JL		 2270 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2271 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2272 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2273 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2274 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2275 /*
2276 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2277 * insufficient FIFO room, the TxAvailable test will succeed and call
2278 * netif_wake_queue()
2279 */
2280 netif_wake_queue(dev);
2281 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2282 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2283 netif_stop_queue(dev);
2284 }
2285 }
2286 }
2287 /* Check for all uncommon interrupts at once. */
2288 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2289 if (status == 0xffff)
2290 break;
2291 vortex_error(dev, status);
2292 }
2293
2294 if (--work_done < 0) {
39738e16
AB		 2295 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2296 dev->name, status);
1da177e4
LT		 2297 /* Disable all pending interrupts. */
2298 do {
2299 vp->deferred |= status;
62afe595 2300 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2301 ioaddr + EL3_CMD);
62afe595
JL		 2302 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2303 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2304 /* The timer will reenable interrupts. */
2305 mod_timer(&vp->timer, jiffies + 1*HZ);
2306 break;
2307 }
2308 /* Acknowledge the IRQ. */
62afe595
JL		 2309 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2310 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4 2311
de847272
BH		 2312 spin_unlock(&vp->window_lock);
2313
1da177e4 2314 if (vortex_debug > 4)
39738e16 2315 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2316 dev->name, status);
2317handler_exit:
2318 spin_unlock(&vp->lock);
2319 return IRQ_RETVAL(handled);
2320}
2321
2322/*
2323 * This is the ISR for the boomerang series chips.
2324 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2325 */
2326
2327static irqreturn_t
7d12e780 2328boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2329{
2330 struct net_device *dev = dev_id;
2331 struct vortex_private *vp = netdev_priv(dev);
62afe595 2332 void __iomem *ioaddr;
1da177e4
LT		 2333 int status;
2334 int work_done = max_interrupt_work;
2335
62afe595 2336 ioaddr = vp->ioaddr;
1da177e4
LT		 2337
2338 /*
2339 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2340 * and boomerang_start_xmit
2341 */
2342 spin_lock(&vp->lock);
2343
62afe595 2344 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2345
2346 if (vortex_debug > 6)
39738e16 2347 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2348
2349 if ((status & IntLatch) == 0)
2350 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2351
2352 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2353 if (vortex_debug > 1)
39738e16 2354 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2355 goto handler_exit;
2356 }
2357
2358 if (status & IntReq) {
2359 status |= vp->deferred;
2360 vp->deferred = 0;
2361 }
2362
2363 if (vortex_debug > 4)
39738e16 2364 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2365 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2366 do {
2367 if (vortex_debug > 5)
39738e16 2368 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2369 dev->name, status);
2370 if (status & UpComplete) {
62afe595 2371 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2372 if (vortex_debug > 5)
39738e16 2373 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2374 boomerang_rx(dev);
2375 }
2376
2377 if (status & DownComplete) {
2378 unsigned int dirty_tx = vp->dirty_tx;
2379
62afe595 2380 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2381 while (vp->cur_tx - dirty_tx > 0) {
2382 int entry = dirty_tx % TX_RING_SIZE;
2383#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2384 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2385 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2386 break; /* It still hasn't been processed. */
2387#else
2388 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2389 break; /* It still hasn't been processed. */
2390#endif
6aa20a22 2391
1da177e4
LT		 2392 if (vp->tx_skbuff[entry]) {
2393 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2394#if DO_ZEROCOPY
1da177e4
LT		 2395 int i;
2396 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2397 pci_unmap_single(VORTEX_PCI(vp),
2398 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2399 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2400 PCI_DMA_TODEVICE);
2401#else
2402 pci_unmap_single(VORTEX_PCI(vp),
2403 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2404#endif
2405 dev_kfree_skb_irq(skb);
2406 vp->tx_skbuff[entry] = NULL;
2407 } else {
39738e16 2408 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2409 }
1daad055 2410 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2411 dirty_tx++;
2412 }
2413 vp->dirty_tx = dirty_tx;
2414 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2415 if (vortex_debug > 6)
39738e16 2416 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2417 netif_wake_queue (dev);
2418 }
2419 }
2420
2421 /* Check for all uncommon interrupts at once. */
2422 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2423 vortex_error(dev, status);
2424
2425 if (--work_done < 0) {
39738e16
AB		 2426 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2427 dev->name, status);
1da177e4
LT		 2428 /* Disable all pending interrupts. */
2429 do {
2430 vp->deferred |= status;
62afe595 2431 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2432 ioaddr + EL3_CMD);
62afe595
JL		 2433 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2434 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2435 /* The timer will reenable interrupts. */
2436 mod_timer(&vp->timer, jiffies + 1*HZ);
2437 break;
2438 }
2439 /* Acknowledge the IRQ. */
62afe595 2440 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2441 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2442 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2443
62afe595 2444 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2445
2446 if (vortex_debug > 4)
39738e16 2447 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2448 dev->name, status);
2449handler_exit:
2450 spin_unlock(&vp->lock);
2451 return IRQ_HANDLED;
2452}
2453
2454static int vortex_rx(struct net_device *dev)
2455{
2456 struct vortex_private *vp = netdev_priv(dev);
62afe595 2457 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2458 int i;
2459 short rx_status;
2460
2461 if (vortex_debug > 5)
39738e16 2462 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2463 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2464 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2465 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2466 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2467 if (vortex_debug > 2)
39738e16 2468 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2469 dev->stats.rx_errors++;
2470 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2471 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2472 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2473 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2474 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2475 } else {
2476 /* The packet length: up to 4.5K!. */
2477 int pkt_len = rx_status & 0x1fff;
2478 struct sk_buff *skb;
2479
2480 skb = dev_alloc_skb(pkt_len + 5);
2481 if (vortex_debug > 4)
39738e16 2482 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2483 pkt_len, rx_status);
2484 if (skb != NULL) {
1da177e4
LT		 2485 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2486 /* 'skb_put()' points to the start of sk_buff data area. */
2487 if (vp->bus_master &&
62afe595 2488 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2489 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2490 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2491 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2492 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2493 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2494 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2495 ;
2496 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2497 } else {
62afe595
JL		 2498 ioread32_rep(ioaddr + RX_FIFO,
2499 skb_put(skb, pkt_len),
2500 (pkt_len + 3) >> 2);
1da177e4 2501 }
62afe595 2502 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2503 skb->protocol = eth_type_trans(skb, dev);
2504 netif_rx(skb);
1daad055 2505 dev->stats.rx_packets++;
1da177e4
LT		 2506 /* Wait a limited time to go to next packet. */
2507 for (i = 200; i >= 0; i--)
62afe595 2508 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2509 break;
2510 continue;
2511 } else if (vortex_debug > 0)
39738e16
AB		 2512 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2513 dev->name, pkt_len);
1daad055 2514 dev->stats.rx_dropped++;
1da177e4 2515 }
1da177e4
LT		 2516 issue_and_wait(dev, RxDiscard);
2517 }
2518
2519 return 0;
2520}
2521
2522static int
2523boomerang_rx(struct net_device *dev)
2524{
2525 struct vortex_private *vp = netdev_priv(dev);
2526 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2527 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2528 int rx_status;
2529 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2530
2531 if (vortex_debug > 5)
39738e16 2532 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2533
2534 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2535 if (--rx_work_limit < 0)
2536 break;
2537 if (rx_status & RxDError) { /* Error, update stats. */
2538 unsigned char rx_error = rx_status >> 16;
2539 if (vortex_debug > 2)
39738e16 2540 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2541 dev->stats.rx_errors++;
2542 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2543 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2544 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2545 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2546 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2547 } else {
2548 /* The packet length: up to 4.5K!. */
2549 int pkt_len = rx_status & 0x1fff;
2550 struct sk_buff *skb;
2551 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2552
2553 if (vortex_debug > 4)
39738e16 2554 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2555 pkt_len, rx_status);
2556
2557 /* Check if the packet is long enough to just accept without
2558 copying to a properly sized skbuff. */
cc2d6596 2559 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2560 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2561 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2562 /* 'skb_put()' points to the start of sk_buff data area. */
2563 memcpy(skb_put(skb, pkt_len),
689be439 2564 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2565 pkt_len);
2566 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2567 vp->rx_copy++;
2568 } else {
2569 /* Pass up the skbuff already on the Rx ring. */
2570 skb = vp->rx_skbuff[entry];
2571 vp->rx_skbuff[entry] = NULL;
2572 skb_put(skb, pkt_len);
2573 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2574 vp->rx_nocopy++;
2575 }
2576 skb->protocol = eth_type_trans(skb, dev);
2577 { /* Use hardware checksum info. */
2578 int csum_bits = rx_status & 0xee000000;
2579 if (csum_bits &&
2580 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2581 csum_bits == (IPChksumValid | UDPChksumValid))) {
2582 skb->ip_summed = CHECKSUM_UNNECESSARY;
2583 vp->rx_csumhits++;
2584 }
2585 }
2586 netif_rx(skb);
1daad055 2587 dev->stats.rx_packets++;
1da177e4
LT		 2588 }
2589 entry = (++vp->cur_rx) % RX_RING_SIZE;
2590 }
2591 /* Refill the Rx ring buffers. */
2592 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2593 struct sk_buff *skb;
2594 entry = vp->dirty_rx % RX_RING_SIZE;
2595 if (vp->rx_skbuff[entry] == NULL) {
89d71a66 2596 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
1da177e4
LT		 2597 if (skb == NULL) {
2598 static unsigned long last_jif;
ff5688ae 2599 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2600 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2601 last_jif = jiffies;
2602 }
2603 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2604 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2605 break; /* Bad news! */
2606 }
9a5d3414 2607
689be439 2608 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2609 vp->rx_skbuff[entry] = skb;
2610 }
2611 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2612 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2613 }
2614 return 0;
2615}
2616
2617/*
2618 * If we've hit a total OOM refilling the Rx ring we poll once a second
2619 * for some memory. Otherwise there is no way to restart the rx process.
2620 */
2621static void
2622rx_oom_timer(unsigned long arg)
2623{
2624 struct net_device *dev = (struct net_device *)arg;
2625 struct vortex_private *vp = netdev_priv(dev);
2626
2627 spin_lock_irq(&vp->lock);
2628 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2629 boomerang_rx(dev);
2630 if (vortex_debug > 1) {
39738e16 2631 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2632 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2633 }
2634 spin_unlock_irq(&vp->lock);
2635}
2636
2637static void
2638vortex_down(struct net_device *dev, int final_down)
2639{
2640 struct vortex_private *vp = netdev_priv(dev);
62afe595 2641 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2642
2643 netif_stop_queue (dev);
2644
2645 del_timer_sync(&vp->rx_oom_timer);
2646 del_timer_sync(&vp->timer);
2647
1daad055 2648 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2649 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2650
2651 /* Disable the receiver and transmitter. */
62afe595
JL		 2652 iowrite16(RxDisable, ioaddr + EL3_CMD);
2653 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2654
2655 /* Disable receiving 802.1q tagged frames */
2656 set_8021q_mode(dev, 0);
2657
2658 if (dev->if_port == XCVR_10base2)
2659 /* Turn off thinnet power. Green! */
62afe595 2660 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2661
62afe595 2662 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2663
2664 update_stats(ioaddr, dev);
2665 if (vp->full_bus_master_rx)
62afe595 2666 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2667 if (vp->full_bus_master_tx)
62afe595 2668 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2669
2670 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2671 vp->pm_state_valid = 1;
1da177e4
LT		 2672 pci_save_state(VORTEX_PCI(vp));
2673 acpi_set_WOL(dev);
2674 }
2675}
2676
2677static int
2678vortex_close(struct net_device *dev)
2679{
2680 struct vortex_private *vp = netdev_priv(dev);
62afe595 2681 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2682 int i;
2683
2684 if (netif_device_present(dev))
2685 vortex_down(dev, 1);
2686
2687 if (vortex_debug > 1) {
39738e16 2688 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2689 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2690 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2691 " tx_queued %d Rx pre-checksummed %d.\n",
2692 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2693 }
2694
2695#if DO_ZEROCOPY
32fb5f06
JL		 2696 if (vp->rx_csumhits &&
2697 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2698 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2699 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2700 }
2701#endif
6aa20a22 2702
1da177e4
LT		 2703 free_irq(dev->irq, dev);
2704
2705 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2706 for (i = 0; i < RX_RING_SIZE; i++)
2707 if (vp->rx_skbuff[i]) {
2708 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2709 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2710 dev_kfree_skb(vp->rx_skbuff[i]);
2711 vp->rx_skbuff[i] = NULL;
2712 }
2713 }
2714 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2715 for (i = 0; i < TX_RING_SIZE; i++) {
2716 if (vp->tx_skbuff[i]) {
2717 struct sk_buff *skb = vp->tx_skbuff[i];
2718#if DO_ZEROCOPY
2719 int k;
2720
2721 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2722 pci_unmap_single(VORTEX_PCI(vp),
2723 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2724 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2725 PCI_DMA_TODEVICE);
2726#else
2727 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2728#endif
2729 dev_kfree_skb(skb);
2730 vp->tx_skbuff[i] = NULL;
2731 }
2732 }
2733 }
2734
2735 return 0;
2736}
2737
2738static void
2739dump_tx_ring(struct net_device *dev)
2740{
2741 if (vortex_debug > 0) {
2742 struct vortex_private *vp = netdev_priv(dev);
62afe595 2743 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2744
1da177e4
LT		 2745 if (vp->full_bus_master_tx) {
2746 int i;
62afe595 2747 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2748
39738e16 2749 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2750 vp->full_bus_master_tx,
2751 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2752 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2753 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2754 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2755 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2756 issue_and_wait(dev, DownStall);
2757 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2758 unsigned int length;
2759
1da177e4 2760#if DO_ZEROCOPY
0cb13536 2761 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2762#else
0cb13536 2763 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2764#endif
0cb13536
JD		 2765 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2766 i, &vp->tx_ring[i], length,
1da177e4
LT		 2767 le32_to_cpu(vp->tx_ring[i].status));
2768 }
2769 if (!stalled)
62afe595 2770 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2771 }
2772 }
2773}
2774
2775static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2776{
2777 struct vortex_private *vp = netdev_priv(dev);
62afe595 2778 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2779 unsigned long flags;
2780
2781 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2782 spin_lock_irqsave (&vp->lock, flags);
62afe595 2783 update_stats(ioaddr, dev);
1da177e4
LT		 2784 spin_unlock_irqrestore (&vp->lock, flags);
2785 }
1daad055 2786 return &dev->stats;
1da177e4
LT		 2787}
2788
2789/* Update statistics.
2790 Unlike with the EL3 we need not worry about interrupts changing
2791 the window setting from underneath us, but we must still guard
2792 against a race condition with a StatsUpdate interrupt updating the
2793 table. This is done by checking that the ASM (!) code generated uses
2794 atomic updates with '+='.
2795 */
62afe595 2796static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2797{
2798 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2799
1da177e4
LT		 2800 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2801 /* Switch to the stats window, and read everything. */
a095cfc4
BH		 2802 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2803 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2804 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2805 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2806 dev->stats.tx_packets += window_read8(vp, 6, 6);
2807 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2808 0x30) << 4;
2809 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
1da177e4
LT		 2810 /* Don't bother with register 9, an extension of registers 6&7.
2811 If we do use the 6&7 values the atomic update assumption above
2812 is invalid. */
a095cfc4
BH		 2813 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2814 dev->stats.tx_bytes += window_read16(vp, 6, 12);
1da177e4 2815 /* Extra stats for get_ethtool_stats() */
a095cfc4
BH		 2816 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2817 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2818 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2819 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
1da177e4 2820
1daad055 2821 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2822 + vp->xstats.tx_single_collisions
2823 + vp->xstats.tx_max_collisions;
2824
1da177e4 2825 {
a095cfc4 2826 u8 up = window_read8(vp, 4, 13);
1daad055
PZ		 2827 dev->stats.rx_bytes += (up & 0x0f) << 16;
2828 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4 2829 }
1da177e4
LT		 2830}
2831
2832static int vortex_nway_reset(struct net_device *dev)
2833{
2834 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2835
de847272 2836 return mii_nway_restart(&vp->mii);
1da177e4
LT		 2837}
2838
1da177e4
LT		 2839static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2840{
2841 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2842
de847272 2843 return mii_ethtool_gset(&vp->mii, cmd);
1da177e4
LT		 2844}
2845
2846static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2847{
2848 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2849
de847272 2850 return mii_ethtool_sset(&vp->mii, cmd);
1da177e4
LT		 2851}
2852
2853static u32 vortex_get_msglevel(struct net_device *dev)
2854{
2855 return vortex_debug;
2856}
2857
2858static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2859{
2860 vortex_debug = dbg;
2861}
2862
b9f2c044 2863static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2864{
b9f2c044
JG		 2865 switch (sset) {
2866 case ETH_SS_STATS:
2867 return VORTEX_NUM_STATS;
2868 default:
2869 return -EOPNOTSUPP;
2870 }
1da177e4
LT		 2871}
2872
2873static void vortex_get_ethtool_stats(struct net_device *dev,
2874 struct ethtool_stats *stats, u64 *data)
2875{
2876 struct vortex_private *vp = netdev_priv(dev);
62afe595 2877 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2878 unsigned long flags;
2879
2880 spin_lock_irqsave(&vp->lock, flags);
62afe595 2881 update_stats(ioaddr, dev);
1da177e4
LT		 2882 spin_unlock_irqrestore(&vp->lock, flags);
2883
2884 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2885 data[1] = vp->xstats.tx_max_collisions;
2886 data[2] = vp->xstats.tx_multiple_collisions;
2887 data[3] = vp->xstats.tx_single_collisions;
2888 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2889}
2890
2891
2892static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2893{
2894 switch (stringset) {
2895 case ETH_SS_STATS:
2896 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2897 break;
2898 default:
2899 WARN_ON(1);
2900 break;
2901 }
2902}
2903
2904static void vortex_get_drvinfo(struct net_device *dev,
2905 struct ethtool_drvinfo *info)
2906{
2907 struct vortex_private *vp = netdev_priv(dev);
2908
2909 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2910 if (VORTEX_PCI(vp)) {
2911 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2912 } else {
2913 if (VORTEX_EISA(vp))
86de79b6 2914 strcpy(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2915 else
2916 sprintf(info->bus_info, "EISA 0x%lx %d",
2917 dev->base_addr, dev->irq);
2918 }
2919}
2920
690a1f20
AS		 2921static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2922{
2923 struct vortex_private *vp = netdev_priv(dev);
2924
2925 spin_lock_irq(&vp->lock);
2926 wol->supported = WAKE_MAGIC;
2927
2928 wol->wolopts = 0;
2929 if (vp->enable_wol)
2930 wol->wolopts |= WAKE_MAGIC;
2931 spin_unlock_irq(&vp->lock);
2932}
2933
2934static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2935{
2936 struct vortex_private *vp = netdev_priv(dev);
2937 if (wol->wolopts & ~WAKE_MAGIC)
2938 return -EINVAL;
2939
2940 spin_lock_irq(&vp->lock);
2941 if (wol->wolopts & WAKE_MAGIC)
2942 vp->enable_wol = 1;
2943 else
2944 vp->enable_wol = 0;
2945 acpi_set_WOL(dev);
2946 spin_unlock_irq(&vp->lock);
2947
2948 return 0;
2949}
2950
7282d491 2951static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2952 .get_drvinfo = vortex_get_drvinfo,
2953 .get_strings = vortex_get_strings,
2954 .get_msglevel = vortex_get_msglevel,
2955 .set_msglevel = vortex_set_msglevel,
2956 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2957 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2958 .get_settings = vortex_get_settings,
2959 .set_settings = vortex_set_settings,
373a6887 2960 .get_link = ethtool_op_get_link,
1da177e4 2961 .nway_reset = vortex_nway_reset,
690a1f20
AS		 2962 .get_wol = vortex_get_wol,
2963 .set_wol = vortex_set_wol,
1da177e4
LT		 2964};
2965
2966#ifdef CONFIG_PCI
2967/*
2968 * Must power the device up to do MDIO operations
2969 */
2970static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2971{
2972 int err;
2973 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2974 unsigned long flags;
cc2d6596 2975 pci_power_t state = 0;
1da177e4
LT		 2976
2977 if(VORTEX_PCI(vp))
2978 state = VORTEX_PCI(vp)->current_state;
2979
2980 /* The kernel core really should have pci_get_power_state() */
2981
2982 if(state != 0)
2983 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2984 spin_lock_irqsave(&vp->lock, flags);
1da177e4
LT		 2985 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2986 spin_unlock_irqrestore(&vp->lock, flags);
2987 if(state != 0)
2988 pci_set_power_state(VORTEX_PCI(vp), state);
2989
2990 return err;
2991}
2992#endif
2993
2994
2995/* Pre-Cyclone chips have no documented multicast filter, so the only
2996 multicast setting is to receive all multicast frames. At least
2997 the chip has a very clean way to set the mode, unlike many others. */
2998static void set_rx_mode(struct net_device *dev)
2999{
62afe595
JL		 3000 struct vortex_private *vp = netdev_priv(dev);
3001 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3002 int new_mode;
3003
3004 if (dev->flags & IFF_PROMISC) {
d5b20697 3005 if (vortex_debug > 3)
39738e16 3006 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4 3007 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
59ce25d9 3008 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1da177e4
LT		 3009 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3010 } else
3011 new_mode = SetRxFilter | RxStation | RxBroadcast;
3012
62afe595 3013 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3014}
3015
3016#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3017/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3018 Note that this must be done after each RxReset due to some backwards
3019 compatibility logic in the Cyclone and Tornado ASICs */
3020
3021/* The Ethernet Type used for 802.1q tagged frames */
3022#define VLAN_ETHER_TYPE 0x8100
3023
3024static void set_8021q_mode(struct net_device *dev, int enable)
3025{
3026 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3027 int mac_ctrl;
3028
3029 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3030 /* cyclone and tornado chipsets can recognize 802.1q
3031 * tagged frames and treat them correctly */
3032
3033 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3034 if (enable)
3035 max_pkt_size += 4; /* 802.1Q VLAN tag */
3036
a095cfc4 3037 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
1da177e4
LT		 3038
3039 /* set VlanEtherType to let the hardware checksumming
3040 treat tagged frames correctly */
a095cfc4 3041 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
1da177e4
LT		 3042 } else {
3043 /* on older cards we have to enable large frames */
3044
3045 vp->large_frames = dev->mtu > 1500 || enable;
3046
a095cfc4 3047 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
1da177e4
LT		 3048 if (vp->large_frames)
3049 mac_ctrl |= 0x40;
3050 else
3051 mac_ctrl &= ~0x40;
a095cfc4 3052 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
1da177e4 3053 }
1da177e4
LT		 3054}
3055#else
3056
3057static void set_8021q_mode(struct net_device *dev, int enable)
3058{
3059}
3060
3061
3062#endif
3063
3064/* MII transceiver control section.
3065 Read and write the MII registers using software-generated serial
3066 MDIO protocol. See the MII specifications or DP83840A data sheet
3067 for details. */
3068
3069/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3070 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3071 "overclocking" issues. */
a095cfc4
BH		 3072static void mdio_delay(struct vortex_private *vp)
3073{
3074 window_read32(vp, 4, Wn4_PhysicalMgmt);
3075}
1da177e4
LT		 3076
3077#define MDIO_SHIFT_CLK 0x01
3078#define MDIO_DIR_WRITE 0x04
3079#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3080#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3081#define MDIO_DATA_READ 0x02
3082#define MDIO_ENB_IN 0x00
3083
3084/* Generate the preamble required for initial synchronization and
3085 a few older transceivers. */
a095cfc4 3086static void mdio_sync(struct vortex_private *vp, int bits)
1da177e4 3087{
1da177e4
LT		 3088 /* Establish sync by sending at least 32 logic ones. */
3089 while (-- bits >= 0) {
a095cfc4
BH		 3090 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3091 mdio_delay(vp);
3092 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3093 4, Wn4_PhysicalMgmt);
3094 mdio_delay(vp);
1da177e4
LT		 3095 }
3096}
3097
3098static int mdio_read(struct net_device *dev, int phy_id, int location)
3099{
3100 int i;
62afe595 3101 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3102 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3103 unsigned int retval = 0;
1da177e4 3104
de847272
BH		 3105 spin_lock_bh(&vp->mii_lock);
3106
1da177e4 3107 if (mii_preamble_required)
a095cfc4 3108 mdio_sync(vp, 32);
1da177e4
LT		 3109
3110 /* Shift the read command bits out. */
3111 for (i = 14; i >= 0; i--) {
3112 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3113 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3114 mdio_delay(vp);
3115 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3116 4, Wn4_PhysicalMgmt);
3117 mdio_delay(vp);
1da177e4
LT		 3118 }
3119 /* Read the two transition, 16 data, and wire-idle bits. */
3120 for (i = 19; i > 0; i--) {
a095cfc4
BH		 3121 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3122 mdio_delay(vp);
3123 retval = (retval << 1) |
3124 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3125 MDIO_DATA_READ) ? 1 : 0);
3126 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3127 4, Wn4_PhysicalMgmt);
3128 mdio_delay(vp);
1da177e4 3129 }
de847272
BH		 3130
3131 spin_unlock_bh(&vp->mii_lock);
3132
1da177e4
LT		 3133 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3134}
3135
3136static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3137{
62afe595 3138 struct vortex_private *vp = netdev_priv(dev);
1da177e4 3139 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
1da177e4
LT		 3140 int i;
3141
de847272
BH		 3142 spin_lock_bh(&vp->mii_lock);
3143
1da177e4 3144 if (mii_preamble_required)
a095cfc4 3145 mdio_sync(vp, 32);
1da177e4
LT		 3146
3147 /* Shift the command bits out. */
3148 for (i = 31; i >= 0; i--) {
3149 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3150 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3151 mdio_delay(vp);
3152 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3153 4, Wn4_PhysicalMgmt);
3154 mdio_delay(vp);
1da177e4
LT		 3155 }
3156 /* Leave the interface idle. */
3157 for (i = 1; i >= 0; i--) {
a095cfc4
BH		 3158 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3159 mdio_delay(vp);
3160 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3161 4, Wn4_PhysicalMgmt);
3162 mdio_delay(vp);
1da177e4 3163 }
de847272
BH		 3164
3165 spin_unlock_bh(&vp->mii_lock);
1da177e4 3166}
a880c4cd 3167
1da177e4
LT		 3168/* ACPI: Advanced Configuration and Power Interface. */
3169/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3170static void acpi_set_WOL(struct net_device *dev)
3171{
3172 struct vortex_private *vp = netdev_priv(dev);
62afe595 3173 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3174
c17931c5
SK		 3175 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3176
1da177e4
LT		 3177 if (vp->enable_wol) {
3178 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
a095cfc4 3179 window_write16(vp, 2, 7, 0x0c);
1da177e4 3180 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3181 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3182 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3183
1a1769f3 3184 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3185 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3186
3187 vp->enable_wol = 0;
3188 return;
3189 }
3c8fad18
DR		 3190
3191 /* Change the power state to D3; RxEnable doesn't take effect. */
3192 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3193 }
1da177e4
LT		 3194}
3195
3196
a880c4cd 3197static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3198{
3199 struct net_device *dev = pci_get_drvdata(pdev);
3200 struct vortex_private *vp;
3201
3202 if (!dev) {
39738e16 3203 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3204 BUG();
3205 }
3206
3207 vp = netdev_priv(dev);
3208
62afe595
JL		 3209 if (vp->cb_fn_base)
3210 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3211
1da177e4
LT		 3212 unregister_netdev(dev);
3213
3214 if (VORTEX_PCI(vp)) {
3215 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3216 if (vp->pm_state_valid)
3217 pci_restore_state(VORTEX_PCI(vp));
3218 pci_disable_device(VORTEX_PCI(vp));
3219 }
3220 /* Should really use issue_and_wait() here */
62afe595
JL		 3221 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3222 vp->ioaddr + EL3_CMD);
3223
3224 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3225
3226 pci_free_consistent(pdev,
3227 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3228 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3229 vp->rx_ring,
3230 vp->rx_ring_dma);
3231 if (vp->must_free_region)
3232 release_region(dev->base_addr, vp->io_size);
3233 free_netdev(dev);
3234}
3235
3236
3237static struct pci_driver vortex_driver = {
3238 .name = "3c59x",
3239 .probe = vortex_init_one,
3240 .remove = __devexit_p(vortex_remove_one),
3241 .id_table = vortex_pci_tbl,
7bfc4ab5 3242 .driver.pm = VORTEX_PM_OPS,
1da177e4
LT		 3243};
3244
3245
3246static int vortex_have_pci;
3247static int vortex_have_eisa;
3248
3249
a880c4cd 3250static int __init vortex_init(void)
1da177e4
LT		 3251{
3252 int pci_rc, eisa_rc;
3253
29917620 3254 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3255 eisa_rc = vortex_eisa_init();
3256
3257 if (pci_rc == 0)
3258 vortex_have_pci = 1;
3259 if (eisa_rc > 0)
3260 vortex_have_eisa = 1;
3261
3262 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3263}
3264
3265
a880c4cd 3266static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3267{
3268 struct vortex_private *vp;
62afe595 3269 void __iomem *ioaddr;
1da177e4
LT		 3270
3271#ifdef CONFIG_EISA
3272 /* Take care of the EISA devices */
a880c4cd 3273 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3274#endif
6aa20a22 3275
1da177e4 3276 if (compaq_net_device) {
454d7c9b 3277 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3278 ioaddr = ioport_map(compaq_net_device->base_addr,
3279 VORTEX_TOTAL_SIZE);
1da177e4 3280
a880c4cd
SK		 3281 unregister_netdev(compaq_net_device);
3282 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3283 release_region(compaq_net_device->base_addr,
3284 VORTEX_TOTAL_SIZE);
1da177e4 3285
a880c4cd 3286 free_netdev(compaq_net_device);
1da177e4
LT		 3287 }
3288}
3289
3290
a880c4cd 3291static void __exit vortex_cleanup(void)
1da177e4
LT		 3292{
3293 if (vortex_have_pci)
a880c4cd 3294 pci_unregister_driver(&vortex_driver);
1da177e4 3295 if (vortex_have_eisa)
a880c4cd 3296 vortex_eisa_cleanup();
1da177e4
LT		 3297}
3298
3299
3300module_init(vortex_init);
3301module_exit(vortex_cleanup);
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