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[net-next-2.6.git] / drivers / net / 3c59x.c
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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
2c2a8c53 106DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
aa807f79 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
b8a1fcee 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
cc2d6596
AV		 541 __le32 next; /* Last entry points to 0. */
542 __le32 status;
543 __le32 addr; /* Up to 63 addr/len pairs possible. */
544 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
cc2d6596
AV		 561 __le32 next; /* Last entry points to 0. */
562 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 563#if DO_ZEROCOPY
564 struct {
cc2d6596
AV		 565 __le32 addr;
566 __le32 length;
1da177e4
LT		 567 } frag[1+MAX_SKB_FRAGS];
568#else
cc2d6596
AV		 569 __le32 addr;
570 __le32 length;
1da177e4
LT		 571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 603 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
604 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
605 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
606
607 /* PCI configuration space information. */
608 struct device *gendev;
62afe595
JL		 609 void __iomem *ioaddr; /* IO address space */
610 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 611
612 /* Some values here only for performance evaluation and path-coverage */
613 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
614 int card_idx;
615
616 /* The remainder are related to chip state, mostly media selection. */
617 struct timer_list timer; /* Media selection timer. */
618 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
619 int options; /* User-settable misc. driver options. */
620 unsigned int media_override:4, /* Passed-in media type. */
621 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 622 full_duplex:1, autoselect:1,
1da177e4
LT		 623 bus_master:1, /* Vortex can only do a fragment bus-m. */
624 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
625 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
626 partner_flow_ctrl:1, /* Partner supports flow control */
627 has_nway:1,
628 enable_wol:1, /* Wake-on-LAN is enabled */
629 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
630 open:1,
631 medialock:1,
632 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
633 large_frames:1; /* accept large frames */
634 int drv_flags;
635 u16 status_enable;
636 u16 intr_enable;
637 u16 available_media; /* From Wn3_Options. */
638 u16 capabilities, info1, info2; /* Various, from EEPROM. */
639 u16 advertising; /* NWay media advertisement */
640 unsigned char phys[2]; /* MII device addresses. */
641 u16 deferred; /* Resend these interrupts when we
642 * bale from the ISR */
643 u16 io_size; /* Size of PCI region (for release_region) */
644 spinlock_t lock; /* Serialise access to device & its vortex_private */
645 struct mii_if_info mii; /* MII lib hooks/info */
646};
647
648#ifdef CONFIG_PCI
649#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
650#else
651#define DEVICE_PCI(dev) NULL
652#endif
653
654#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
655
656#ifdef CONFIG_EISA
657#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
658#else
659#define DEVICE_EISA(dev) NULL
660#endif
661
662#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
663
664/* The action to take with a media selection timer tick.
665 Note that we deviate from the 3Com order by checking 10base2 before AUI.
666 */
667enum xcvr_types {
668 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
669 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
670};
671
f71e1309 672static const struct media_table {
1da177e4
LT		 673 char *name;
674 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
675 mask:8, /* The transceiver-present bit in Wn3_Config.*/
676 next:8; /* The media type to try next. */
677 int wait; /* Time before we check media status. */
678} media_tbl[] = {
679 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
680 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
681 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
682 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
683 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
684 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
685 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
686 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
687 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
688 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
689 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
690};
691
692static struct {
693 const char str[ETH_GSTRING_LEN];
694} ethtool_stats_keys[] = {
695 { "tx_deferred" },
8d1d0340 696 { "tx_max_collisions" },
1da177e4 697 { "tx_multiple_collisions" },
8d1d0340 698 { "tx_single_collisions" },
1da177e4
LT		 699 { "rx_bad_ssd" },
700};
701
702/* number of ETHTOOL_GSTATS u64's */
8d1d0340 703#define VORTEX_NUM_STATS 5
1da177e4 704
62afe595 705static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 706 int chip_idx, int card_idx);
c8303d10 707static int vortex_up(struct net_device *dev);
1da177e4
LT		 708static void vortex_down(struct net_device *dev, int final);
709static int vortex_open(struct net_device *dev);
62afe595 710static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 711static int mdio_read(struct net_device *dev, int phy_id, int location);
712static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
713static void vortex_timer(unsigned long arg);
714static void rx_oom_timer(unsigned long arg);
715static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
716static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int vortex_rx(struct net_device *dev);
718static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 719static irqreturn_t vortex_interrupt(int irq, void *dev_id);
720static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 721static int vortex_close(struct net_device *dev);
722static void dump_tx_ring(struct net_device *dev);
62afe595 723static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 724static struct net_device_stats *vortex_get_stats(struct net_device *dev);
725static void set_rx_mode(struct net_device *dev);
726#ifdef CONFIG_PCI
727static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
728#endif
729static void vortex_tx_timeout(struct net_device *dev);
730static void acpi_set_WOL(struct net_device *dev);
7282d491 731static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 732static void set_8021q_mode(struct net_device *dev, int enable);
733
1da177e4
LT		 734/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
735/* Option count limit only -- unlimited interfaces are supported. */
736#define MAX_UNITS 8
9954ab7f
JL		 737static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
738static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
739static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 742static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 743static int global_options = -1;
744static int global_full_duplex = -1;
745static int global_enable_wol = -1;
900fd17d 746static int global_use_mmio = -1;
1da177e4 747
1da177e4
LT		 748/* Variables to work-around the Compaq PCI BIOS32 problem. */
749static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
750static struct net_device *compaq_net_device;
751
752static int vortex_cards_found;
753
754module_param(debug, int, 0);
755module_param(global_options, int, 0);
756module_param_array(options, int, NULL, 0);
757module_param(global_full_duplex, int, 0);
758module_param_array(full_duplex, int, NULL, 0);
759module_param_array(hw_checksums, int, NULL, 0);
760module_param_array(flow_ctrl, int, NULL, 0);
761module_param(global_enable_wol, int, 0);
762module_param_array(enable_wol, int, NULL, 0);
763module_param(rx_copybreak, int, 0);
764module_param(max_interrupt_work, int, 0);
765module_param(compaq_ioaddr, int, 0);
766module_param(compaq_irq, int, 0);
767module_param(compaq_device_id, int, 0);
768module_param(watchdog, int, 0);
900fd17d
JL		 769module_param(global_use_mmio, int, 0);
770module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 771MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
772MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
773MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
774MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 775MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 776MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
777MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
778MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 779MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 780MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
781MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
782MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
783MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 786MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
787MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 788
789#ifdef CONFIG_NET_POLL_CONTROLLER
790static void poll_vortex(struct net_device *dev)
791{
792 struct vortex_private *vp = netdev_priv(dev);
793 unsigned long flags;
0d38ff1d 794 local_irq_save(flags);
7d12e780 795 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 796 local_irq_restore(flags);
6aa20a22 797}
1da177e4
LT		 798#endif
799
800#ifdef CONFIG_PM
801
a880c4cd 802static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 803{
804 struct net_device *dev = pci_get_drvdata(pdev);
805
454d7c9b 806 if (dev && netdev_priv(dev)) {
1da177e4
LT		 807 if (netif_running(dev)) {
808 netif_device_detach(dev);
809 vortex_down(dev, 1);
810 }
5b039e68
RW		 811 pci_save_state(pdev);
812 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
813 free_irq(dev->irq, dev);
814 pci_disable_device(pdev);
815 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 816 }
817 return 0;
818}
819
a880c4cd 820static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 821{
822 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 823 struct vortex_private *vp = netdev_priv(dev);
e1265153 824 int err;
1da177e4 825
5b039e68
RW		 826 if (dev && vp) {
827 pci_set_power_state(pdev, PCI_D0);
828 pci_restore_state(pdev);
e1265153
DM		 829 err = pci_enable_device(pdev);
830 if (err) {
831 printk(KERN_WARNING "%s: Could not enable device \n",
832 dev->name);
833 return err;
834 }
5b039e68
RW		 835 pci_set_master(pdev);
836 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 837 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 838 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
839 pci_disable_device(pdev);
840 return -EBUSY;
841 }
1da177e4 842 if (netif_running(dev)) {
c8303d10
MH		 843 err = vortex_up(dev);
844 if (err)
845 return err;
846 else
847 netif_device_attach(dev);
1da177e4
LT		 848 }
849 }
850 return 0;
851}
852
853#endif /* CONFIG_PM */
854
855#ifdef CONFIG_EISA
856static struct eisa_device_id vortex_eisa_ids[] = {
857 { "TCM5920", CH_3C592 },
858 { "TCM5970", CH_3C597 },
859 { "" }
860};
07563c71 861MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 862
95c408a9 863static int __init vortex_eisa_probe(struct device *device)
1da177e4 864{
62afe595 865 void __iomem *ioaddr;
1da177e4
LT		 866 struct eisa_device *edev;
867
a880c4cd 868 edev = to_eisa_device(device);
1da177e4 869
62afe595 870 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 871 return -EBUSY;
872
62afe595
JL		 873 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
874
875 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 876 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 877 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 878 return -ENODEV;
879 }
880
881 vortex_cards_found++;
882
883 return 0;
884}
885
95c408a9 886static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 887{
888 struct eisa_device *edev;
889 struct net_device *dev;
890 struct vortex_private *vp;
62afe595 891 void __iomem *ioaddr;
1da177e4 892
a880c4cd
SK		 893 edev = to_eisa_device(device);
894 dev = eisa_get_drvdata(edev);
1da177e4
LT		 895
896 if (!dev) {
897 printk("vortex_eisa_remove called for Compaq device!\n");
898 BUG();
899 }
900
901 vp = netdev_priv(dev);
62afe595 902 ioaddr = vp->ioaddr;
6aa20a22 903
a880c4cd
SK		 904 unregister_netdev(dev);
905 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
906 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 907
a880c4cd 908 free_netdev(dev);
1da177e4
LT		 909 return 0;
910}
95c408a9
RB		 911
912static struct eisa_driver vortex_eisa_driver = {
913 .id_table = vortex_eisa_ids,
914 .driver = {
915 .name = "3c59x",
916 .probe = vortex_eisa_probe,
917 .remove = __devexit_p(vortex_eisa_remove)
918 }
919};
920
921#endif /* CONFIG_EISA */
1da177e4
LT		 922
923/* returns count found (>= 0), or negative on error */
a880c4cd 924static int __init vortex_eisa_init(void)
1da177e4
LT		 925{
926 int eisa_found = 0;
927 int orig_cards_found = vortex_cards_found;
928
929#ifdef CONFIG_EISA
c2f6fabb
BH		 930 int err;
931
932 err = eisa_driver_register (&vortex_eisa_driver);
933 if (!err) {
934 /*
935 * Because of the way EISA bus is probed, we cannot assume
936 * any device have been found when we exit from
937 * eisa_driver_register (the bus root driver may not be
938 * initialized yet). So we blindly assume something was
939 * found, and let the sysfs magic happend...
940 */
941 eisa_found = 1;
1da177e4
LT		 942 }
943#endif
6aa20a22 944
1da177e4
LT		 945 /* Special code to work-around the Compaq PCI BIOS32 problem. */
946 if (compaq_ioaddr) {
62afe595
JL		 947 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
948 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 949 }
950
951 return vortex_cards_found - orig_cards_found + eisa_found;
952}
953
954/* returns count (>= 0), or negative on error */
a880c4cd 955static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 956 const struct pci_device_id *ent)
957{
900fd17d
JL		 958 int rc, unit, pci_bar;
959 struct vortex_chip_info *vci;
960 void __iomem *ioaddr;
1da177e4 961
6aa20a22 962 /* wake up and enable device */
a880c4cd 963 rc = pci_enable_device(pdev);
1da177e4
LT		 964 if (rc < 0)
965 goto out;
966
900fd17d
JL		 967 unit = vortex_cards_found;
968
969 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
970 /* Determine the default if the user didn't override us */
971 vci = &vortex_info_tbl[ent->driver_data];
972 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
973 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
974 pci_bar = use_mmio[unit] ? 1 : 0;
975 else
976 pci_bar = global_use_mmio ? 1 : 0;
977
978 ioaddr = pci_iomap(pdev, pci_bar, 0);
979 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
980 ioaddr = pci_iomap(pdev, 0, 0);
981
982 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
983 ent->driver_data, unit);
1da177e4 984 if (rc < 0) {
a880c4cd 985 pci_disable_device(pdev);
1da177e4
LT		 986 goto out;
987 }
988
989 vortex_cards_found++;
990
991out:
992 return rc;
993}
994
48b47a5e
SH		 995static const struct net_device_ops boomrang_netdev_ops = {
996 .ndo_open = vortex_open,
997 .ndo_stop = vortex_close,
998 .ndo_start_xmit = boomerang_start_xmit,
999 .ndo_tx_timeout = vortex_tx_timeout,
1000 .ndo_get_stats = vortex_get_stats,
1001#ifdef CONFIG_PCI
1002 .ndo_do_ioctl = vortex_ioctl,
1003#endif
1004 .ndo_set_multicast_list = set_rx_mode,
1005 .ndo_change_mtu = eth_change_mtu,
1006 .ndo_set_mac_address = eth_mac_addr,
1007 .ndo_validate_addr = eth_validate_addr,
1008#ifdef CONFIG_NET_POLL_CONTROLLER
1009 .ndo_poll_controller = poll_vortex,
1010#endif
1011};
1012
1013static const struct net_device_ops vortex_netdev_ops = {
1014 .ndo_open = vortex_open,
1015 .ndo_stop = vortex_close,
1016 .ndo_start_xmit = vortex_start_xmit,
1017 .ndo_tx_timeout = vortex_tx_timeout,
1018 .ndo_get_stats = vortex_get_stats,
1019#ifdef CONFIG_PCI
1020 .ndo_do_ioctl = vortex_ioctl,
1021#endif
1022 .ndo_set_multicast_list = set_rx_mode,
1023 .ndo_change_mtu = eth_change_mtu,
1024 .ndo_set_mac_address = eth_mac_addr,
1025 .ndo_validate_addr = eth_validate_addr,
1026#ifdef CONFIG_NET_POLL_CONTROLLER
1027 .ndo_poll_controller = poll_vortex,
1028#endif
1029};
1030
1da177e4
LT		 1031/*
1032 * Start up the PCI/EISA device which is described by *gendev.
1033 * Return 0 on success.
1034 *
1035 * NOTE: pdev can be NULL, for the case of a Compaq device
1036 */
1037static int __devinit vortex_probe1(struct device *gendev,
62afe595 1038 void __iomem *ioaddr, int irq,
1da177e4
LT		 1039 int chip_idx, int card_idx)
1040{
1041 struct vortex_private *vp;
1042 int option;
1043 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1044 int i, step;
1045 struct net_device *dev;
1046 static int printed_version;
1047 int retval, print_info;
1048 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1049 const char *print_name = "3c59x";
1da177e4
LT		 1050 struct pci_dev *pdev = NULL;
1051 struct eisa_device *edev = NULL;
1052
1053 if (!printed_version) {
1054 printk (version);
1055 printed_version = 1;
1056 }
1057
1058 if (gendev) {
1059 if ((pdev = DEVICE_PCI(gendev))) {
1060 print_name = pci_name(pdev);
1061 }
1062
1063 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1064 print_name = dev_name(&edev->dev);
1da177e4
LT		 1065 }
1066 }
1067
1068 dev = alloc_etherdev(sizeof(*vp));
1069 retval = -ENOMEM;
1070 if (!dev) {
1071 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1072 goto out;
1073 }
1da177e4
LT		 1074 SET_NETDEV_DEV(dev, gendev);
1075 vp = netdev_priv(dev);
1076
1077 option = global_options;
1078
1079 /* The lower four bits are the media type. */
1080 if (dev->mem_start) {
1081 /*
1082 * The 'options' param is passed in as the third arg to the
1083 * LILO 'ether=' argument for non-modular use
1084 */
1085 option = dev->mem_start;
1086 }
1087 else if (card_idx < MAX_UNITS) {
1088 if (options[card_idx] >= 0)
1089 option = options[card_idx];
1090 }
1091
1092 if (option > 0) {
1093 if (option & 0x8000)
1094 vortex_debug = 7;
1095 if (option & 0x4000)
1096 vortex_debug = 2;
1097 if (option & 0x0400)
1098 vp->enable_wol = 1;
1099 }
1100
1101 print_info = (vortex_debug > 1);
1102 if (print_info)
1103 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1104
61238602 1105 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1106 print_name,
1107 pdev ? "PCI" : "EISA",
1108 vci->name,
1109 ioaddr);
1110
62afe595 1111 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1112 dev->irq = irq;
1113 dev->mtu = mtu;
62afe595 1114 vp->ioaddr = ioaddr;
1da177e4
LT		 1115 vp->large_frames = mtu > 1500;
1116 vp->drv_flags = vci->drv_flags;
1117 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1118 vp->io_size = vci->io_size;
1119 vp->card_idx = card_idx;
1120
1121 /* module list only for Compaq device */
1122 if (gendev == NULL) {
1123 compaq_net_device = dev;
1124 }
1125
1126 /* PCI-only startup logic */
1127 if (pdev) {
1128 /* EISA resources already marked, so only PCI needs to do this here */
1129 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1130 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1131 vp->must_free_region = 1;
1132
6aa20a22 1133 /* enable bus-mastering if necessary */
1da177e4 1134 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1135 pci_set_master(pdev);
1da177e4
LT		 1136
1137 if (vci->drv_flags & IS_VORTEX) {
1138 u8 pci_latency;
1139 u8 new_latency = 248;
1140
1141 /* Check the PCI latency value. On the 3c590 series the latency timer
1142 must be set to the maximum value to avoid data corruption that occurs
1143 when the timer expires during a transfer. This bug exists the Vortex
1144 chip only. */
1145 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1146 if (pci_latency < new_latency) {
1147 printk(KERN_INFO "%s: Overriding PCI latency"
1148 " timer (CFLT) setting of %d, new value is %d.\n",
1149 print_name, pci_latency, new_latency);
1150 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1151 }
1152 }
1153 }
1154
1155 spin_lock_init(&vp->lock);
1156 vp->gendev = gendev;
1157 vp->mii.dev = dev;
1158 vp->mii.mdio_read = mdio_read;
1159 vp->mii.mdio_write = mdio_write;
1160 vp->mii.phy_id_mask = 0x1f;
1161 vp->mii.reg_num_mask = 0x1f;
1162
1163 /* Makes sure rings are at least 16 byte aligned. */
1164 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1165 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1166 &vp->rx_ring_dma);
1167 retval = -ENOMEM;
cc2d6596 1168 if (!vp->rx_ring)
1da177e4
LT		 1169 goto free_region;
1170
1171 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1172 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1173
1174 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1175 * instead of a module list */
1da177e4
LT		 1176 if (pdev)
1177 pci_set_drvdata(pdev, dev);
1178 if (edev)
a880c4cd 1179 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1180
1181 vp->media_override = 7;
1182 if (option >= 0) {
1183 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1184 if (vp->media_override != 7)
1185 vp->medialock = 1;
1186 vp->full_duplex = (option & 0x200) ? 1 : 0;
1187 vp->bus_master = (option & 16) ? 1 : 0;
1188 }
1189
1190 if (global_full_duplex > 0)
1191 vp->full_duplex = 1;
1192 if (global_enable_wol > 0)
1193 vp->enable_wol = 1;
1194
1195 if (card_idx < MAX_UNITS) {
1196 if (full_duplex[card_idx] > 0)
1197 vp->full_duplex = 1;
1198 if (flow_ctrl[card_idx] > 0)
1199 vp->flow_ctrl = 1;
1200 if (enable_wol[card_idx] > 0)
1201 vp->enable_wol = 1;
1202 }
1203
125d5ce8 1204 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1205 vp->options = option;
1206 /* Read the station address from the EEPROM. */
1207 EL3WINDOW(0);
1208 {
1209 int base;
1210
1211 if (vci->drv_flags & EEPROM_8BIT)
1212 base = 0x230;
1213 else if (vci->drv_flags & EEPROM_OFFSET)
1214 base = EEPROM_Read + 0x30;
1215 else
1216 base = EEPROM_Read;
1217
1218 for (i = 0; i < 0x40; i++) {
1219 int timer;
62afe595 1220 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1221 /* Pause for at least 162 us. for the read to take place. */
1222 for (timer = 10; timer >= 0; timer--) {
1223 udelay(162);
62afe595 1224 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1225 break;
1226 }
62afe595 1227 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1228 }
1229 }
1230 for (i = 0; i < 0x18; i++)
1231 checksum ^= eeprom[i];
1232 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1233 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1234 while (i < 0x21)
1235 checksum ^= eeprom[i++];
1236 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1237 }
1238 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1239 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1240 for (i = 0; i < 3; i++)
cc2d6596 1241 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1242 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1243 if (print_info)
e174961c 1244 printk(" %pM", dev->dev_addr);
1da177e4
LT		 1245 /* Unfortunately an all zero eeprom passes the checksum and this
1246 gets found in the wild in failure cases. Crypto is hard 8) */
1247 if (!is_valid_ether_addr(dev->dev_addr)) {
1248 retval = -EINVAL;
1249 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1250 goto free_ring; /* With every pack */
1251 }
1252 EL3WINDOW(2);
1253 for (i = 0; i < 6; i++)
62afe595 1254 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1255
1da177e4
LT		 1256 if (print_info)
1257 printk(", IRQ %d\n", dev->irq);
1258 /* Tell them about an invalid IRQ. */
60e4ad7a 1259 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1da177e4
LT		 1260 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1261 dev->irq);
1da177e4
LT		 1262
1263 EL3WINDOW(4);
62afe595 1264 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1265 if (print_info) {
1266 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1267 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1268 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1269 }
1270
1271
1272 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1273 unsigned short n;
1274
62afe595
JL		 1275 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1276 if (!vp->cb_fn_base) {
1da177e4 1277 retval = -ENOMEM;
62afe595 1278 goto free_ring;
1da177e4 1279 }
62afe595 1280
1da177e4 1281 if (print_info) {
7c7459d1
GKH		 1282 printk(KERN_INFO "%s: CardBus functions mapped "
1283 "%16.16llx->%p\n",
1284 print_name,
1285 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1286 vp->cb_fn_base);
1da177e4
LT		 1287 }
1288 EL3WINDOW(2);
1289
62afe595 1290 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1291 if (vp->drv_flags & INVERT_LED_PWR)
1292 n |= 0x10;
1293 if (vp->drv_flags & INVERT_MII_PWR)
1294 n |= 0x4000;
62afe595 1295 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1296 if (vp->drv_flags & WNO_XCVR_PWR) {
1297 EL3WINDOW(0);
62afe595 1298 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1299 }
1300 }
1301
1302 /* Extract our information from the EEPROM data. */
1303 vp->info1 = eeprom[13];
1304 vp->info2 = eeprom[15];
1305 vp->capabilities = eeprom[16];
1306
1307 if (vp->info1 & 0x8000) {
1308 vp->full_duplex = 1;
1309 if (print_info)
1310 printk(KERN_INFO "Full duplex capable\n");
1311 }
1312
1313 {
f71e1309 1314 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1315 unsigned int config;
1316 EL3WINDOW(3);
62afe595 1317 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1318 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1319 vp->available_media = 0x40;
62afe595 1320 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1321 if (print_info) {
1322 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1323 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1324 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1325 8 << RAM_SIZE(config),
1326 RAM_WIDTH(config) ? "word" : "byte",
1327 ram_split[RAM_SPLIT(config)],
1328 AUTOSELECT(config) ? "autoselect/" : "",
1329 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1330 media_tbl[XCVR(config)].name);
1331 }
1332 vp->default_media = XCVR(config);
1333 if (vp->default_media == XCVR_NWAY)
1334 vp->has_nway = 1;
1335 vp->autoselect = AUTOSELECT(config);
1336 }
1337
1338 if (vp->media_override != 7) {
1339 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1340 print_name, vp->media_override,
1341 media_tbl[vp->media_override].name);
1342 dev->if_port = vp->media_override;
1343 } else
1344 dev->if_port = vp->default_media;
1345
1346 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1347 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1348 int phy, phy_idx = 0;
1349 EL3WINDOW(4);
1350 mii_preamble_required++;
1351 if (vp->drv_flags & EXTRA_PREAMBLE)
1352 mii_preamble_required++;
1353 mdio_sync(ioaddr, 32);
106427e6 1354 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1355 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1356 int mii_status, phyx;
1357
1358 /*
1359 * For the 3c905CX we look at index 24 first, because it bogusly
1360 * reports an external PHY at all indices
1361 */
1362 if (phy == 0)
1363 phyx = 24;
1364 else if (phy <= 24)
1365 phyx = phy - 1;
1366 else
1367 phyx = phy;
106427e6 1368 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1369 if (mii_status && mii_status != 0xffff) {
1370 vp->phys[phy_idx++] = phyx;
1371 if (print_info) {
1372 printk(KERN_INFO " MII transceiver found at address %d,"
1373 " status %4x.\n", phyx, mii_status);
1374 }
1375 if ((mii_status & 0x0040) == 0)
1376 mii_preamble_required++;
1377 }
1378 }
1379 mii_preamble_required--;
1380 if (phy_idx == 0) {
1381 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1382 vp->phys[0] = 24;
1383 } else {
106427e6 1384 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1385 if (vp->full_duplex) {
1386 /* Only advertise the FD media types. */
1387 vp->advertising &= ~0x02A0;
1388 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1389 }
1390 }
1391 vp->mii.phy_id = vp->phys[0];
1392 }
1393
1394 if (vp->capabilities & CapBusMaster) {
1395 vp->full_bus_master_tx = 1;
1396 if (print_info) {
1397 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1398 (vp->info2 & 1) ? "early" : "whole-frame" );
1399 }
1400 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1401 vp->bus_master = 0; /* AKPM: vortex only */
1402 }
1403
1404 /* The 3c59x-specific entries in the device structure. */
1da177e4 1405 if (vp->full_bus_master_tx) {
48b47a5e 1406 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1407 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1408 if (card_idx < MAX_UNITS &&
1409 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1410 hw_checksums[card_idx] == 1)) {
d311b0d3 1411 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1412 }
48b47a5e
SH		 1413 } else
1414 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1415
1416 if (print_info) {
1417 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1418 print_name,
1419 (dev->features & NETIF_F_SG) ? "en":"dis",
1420 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1421 }
1422
1da177e4 1423 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1424 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1425
1da177e4
LT		 1426 if (pdev) {
1427 vp->pm_state_valid = 1;
1428 pci_save_state(VORTEX_PCI(vp));
1429 acpi_set_WOL(dev);
1430 }
1431 retval = register_netdev(dev);
1432 if (retval == 0)
1433 return 0;
1434
1435free_ring:
1436 pci_free_consistent(pdev,
1437 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1438 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1439 vp->rx_ring,
1440 vp->rx_ring_dma);
1441free_region:
1442 if (vp->must_free_region)
62afe595 1443 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1444 free_netdev(dev);
1445 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1446out:
1447 return retval;
1448}
1449
1450static void
1451issue_and_wait(struct net_device *dev, int cmd)
1452{
62afe595
JL		 1453 struct vortex_private *vp = netdev_priv(dev);
1454 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1455 int i;
1456
62afe595 1457 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1458 for (i = 0; i < 2000; i++) {
62afe595 1459 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1460 return;
1461 }
1462
1463 /* OK, that didn't work. Do it the slow way. One second */
1464 for (i = 0; i < 100000; i++) {
62afe595 1465 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1466 if (vortex_debug > 1)
1467 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1468 dev->name, cmd, i * 10);
1469 return;
1470 }
1471 udelay(10);
1472 }
1473 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1474 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1475}
1476
125d5ce8
SK		 1477static void
1478vortex_set_duplex(struct net_device *dev)
1479{
1480 struct vortex_private *vp = netdev_priv(dev);
1481 void __iomem *ioaddr = vp->ioaddr;
1482
1483 printk(KERN_INFO "%s: setting %s-duplex.\n",
1484 dev->name, (vp->full_duplex) ? "full" : "half");
1485
1486 EL3WINDOW(3);
1487 /* Set the full-duplex bit. */
1488 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1489 (vp->large_frames ? 0x40 : 0) |
1490 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1491 0x100 : 0),
1492 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1493}
1494
1495static void vortex_check_media(struct net_device *dev, unsigned int init)
1496{
1497 struct vortex_private *vp = netdev_priv(dev);
1498 unsigned int ok_to_print = 0;
1499
1500 if (vortex_debug > 3)
1501 ok_to_print = 1;
1502
1503 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1504 vp->full_duplex = vp->mii.full_duplex;
1505 vortex_set_duplex(dev);
1506 } else if (init) {
1507 vortex_set_duplex(dev);
1508 }
1509}
1510
c8303d10 1511static int
1da177e4
LT		 1512vortex_up(struct net_device *dev)
1513{
1da177e4 1514 struct vortex_private *vp = netdev_priv(dev);
62afe595 1515 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1516 unsigned int config;
0280f9f9 1517 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1518
1519 if (VORTEX_PCI(vp)) {
1520 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1521 if (vp->pm_state_valid)
1522 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1523 err = pci_enable_device(VORTEX_PCI(vp));
1524 if (err) {
1525 printk(KERN_WARNING "%s: Could not enable device \n",
1526 dev->name);
1527 goto err_out;
1528 }
1da177e4
LT		 1529 }
1530
1531 /* Before initializing select the active media port. */
1532 EL3WINDOW(3);
62afe595 1533 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1534
1535 if (vp->media_override != 7) {
1536 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1537 dev->name, vp->media_override,
1538 media_tbl[vp->media_override].name);
1539 dev->if_port = vp->media_override;
1540 } else if (vp->autoselect) {
1541 if (vp->has_nway) {
1542 if (vortex_debug > 1)
1543 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1544 dev->name, dev->if_port);
1545 dev->if_port = XCVR_NWAY;
1546 } else {
1547 /* Find first available media type, starting with 100baseTx. */
1548 dev->if_port = XCVR_100baseTx;
1549 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1550 dev->if_port = media_tbl[dev->if_port].next;
1551 if (vortex_debug > 1)
1552 printk(KERN_INFO "%s: first available media type: %s\n",
1553 dev->name, media_tbl[dev->if_port].name);
1554 }
1555 } else {
1556 dev->if_port = vp->default_media;
1557 if (vortex_debug > 1)
1558 printk(KERN_INFO "%s: using default media %s\n",
1559 dev->name, media_tbl[dev->if_port].name);
1560 }
1561
1562 init_timer(&vp->timer);
1563 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1564 vp->timer.data = (unsigned long)dev;
1565 vp->timer.function = vortex_timer; /* timer handler */
1566 add_timer(&vp->timer);
1567
1568 init_timer(&vp->rx_oom_timer);
1569 vp->rx_oom_timer.data = (unsigned long)dev;
1570 vp->rx_oom_timer.function = rx_oom_timer;
1571
1572 if (vortex_debug > 1)
1573 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1574 dev->name, media_tbl[dev->if_port].name);
1575
125d5ce8 1576 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1577 config = BFINS(config, dev->if_port, 20, 4);
1578 if (vortex_debug > 6)
1579 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1580 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1581
1582 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1583 EL3WINDOW(4);
09ce3512
SK		 1584 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1585 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1586 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1587 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1588
125d5ce8 1589 vortex_check_media(dev, 1);
1da177e4 1590 }
125d5ce8
SK		 1591 else
1592 vortex_set_duplex(dev);
1da177e4 1593
09ce3512
SK		 1594 issue_and_wait(dev, TxReset);
1595 /*
1596 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1597 */
1598 issue_and_wait(dev, RxReset|0x04);
1599
1da177e4 1600
62afe595 1601 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1602
1603 if (vortex_debug > 1) {
1604 EL3WINDOW(4);
1605 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1606 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1607 }
1608
1609 /* Set the station address and mask in window 2 each time opened. */
1610 EL3WINDOW(2);
1611 for (i = 0; i < 6; i++)
62afe595 1612 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1613 for (; i < 12; i+=2)
62afe595 1614 iowrite16(0, ioaddr + i);
1da177e4
LT		 1615
1616 if (vp->cb_fn_base) {
62afe595 1617 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1618 if (vp->drv_flags & INVERT_LED_PWR)
1619 n |= 0x10;
1620 if (vp->drv_flags & INVERT_MII_PWR)
1621 n |= 0x4000;
62afe595 1622 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1623 }
1624
1625 if (dev->if_port == XCVR_10base2)
1626 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1627 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1628 if (dev->if_port != XCVR_NWAY) {
1629 EL3WINDOW(4);
62afe595 1630 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1631 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1632 }
1633
1634 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1635 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1636 EL3WINDOW(6);
1637 for (i = 0; i < 10; i++)
62afe595
JL		 1638 ioread8(ioaddr + i);
1639 ioread16(ioaddr + 10);
1640 ioread16(ioaddr + 12);
1da177e4
LT		 1641 /* New: On the Vortex we must also clear the BadSSD counter. */
1642 EL3WINDOW(4);
62afe595 1643 ioread8(ioaddr + 12);
1da177e4 1644 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1645 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1646
1647 /* Switch to register set 7 for normal use. */
1648 EL3WINDOW(7);
1649
1650 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1651 vp->cur_rx = vp->dirty_rx = 0;
1652 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1653 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1654 iowrite32(0x0020, ioaddr + PktStatus);
1655 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1656 }
1657 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1658 vp->cur_tx = vp->dirty_tx = 0;
1659 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1660 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1661 /* Clear the Rx, Tx rings. */
1662 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1663 vp->rx_ring[i].status = 0;
1664 for (i = 0; i < TX_RING_SIZE; i++)
1665 vp->tx_skbuff[i] = NULL;
62afe595 1666 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1667 }
1668 /* Set receiver mode: presumably accept b-case and phys addr only. */
1669 set_rx_mode(dev);
1670 /* enable 802.1q tagged frames */
1671 set_8021q_mode(dev, 1);
62afe595 1672 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1673
62afe595
JL		 1674 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1675 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1676 /* Allow status bits to be seen. */
1677 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1678 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1679 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1680 (vp->bus_master ? DMADone : 0);
1681 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1682 (vp->full_bus_master_rx ? 0 : RxComplete) |
1683 StatsFull | HostError | TxComplete | IntReq
1684 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1685 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1686 /* Ack all pending events, and set active indicator mask. */
62afe595 1687 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1688 ioaddr + EL3_CMD);
62afe595 1689 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1690 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1691 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1692 netif_start_queue (dev);
c8303d10
MH		 1693err_out:
1694 return err;
1da177e4
LT		 1695}
1696
1697static int
1698vortex_open(struct net_device *dev)
1699{
1700 struct vortex_private *vp = netdev_priv(dev);
1701 int i;
1702 int retval;
1703
1704 /* Use the now-standard shared IRQ implementation. */
1705 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1706 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4 1707 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1708 goto err;
1da177e4
LT		 1709 }
1710
1711 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1712 if (vortex_debug > 2)
1713 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1714 for (i = 0; i < RX_RING_SIZE; i++) {
1715 struct sk_buff *skb;
1716 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1717 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1718 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1719
1720 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1721 GFP_KERNEL);
1da177e4
LT		 1722 vp->rx_skbuff[i] = skb;
1723 if (skb == NULL)
1724 break; /* Bad news! */
9a5d3414
SH		 1725
1726 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1727 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1728 }
1729 if (i != RX_RING_SIZE) {
1730 int j;
1731 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1732 for (j = 0; j < i; j++) {
1733 if (vp->rx_skbuff[j]) {
1734 dev_kfree_skb(vp->rx_skbuff[j]);
1735 vp->rx_skbuff[j] = NULL;
1736 }
1737 }
1738 retval = -ENOMEM;
c8303d10 1739 goto err_free_irq;
1da177e4
LT		 1740 }
1741 /* Wrap the ring. */
1742 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1743 }
1744
c8303d10
MH		 1745 retval = vortex_up(dev);
1746 if (!retval)
1747 goto out;
1da177e4 1748
c8303d10 1749err_free_irq:
1da177e4 1750 free_irq(dev->irq, dev);
c8303d10 1751err:
1da177e4
LT		 1752 if (vortex_debug > 1)
1753 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1754out:
1da177e4
LT		 1755 return retval;
1756}
1757
1758static void
1759vortex_timer(unsigned long data)
1760{
1761 struct net_device *dev = (struct net_device *)data;
1762 struct vortex_private *vp = netdev_priv(dev);
62afe595 1763 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1764 int next_tick = 60*HZ;
1765 int ok = 0;
125d5ce8 1766 int media_status, old_window;
1da177e4
LT		 1767
1768 if (vortex_debug > 2) {
1769 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1770 dev->name, media_tbl[dev->if_port].name);
1771 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1772 }
1773
0a9da4bd 1774 disable_irq_lockdep(dev->irq);
62afe595 1775 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1776 EL3WINDOW(4);
62afe595 1777 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1778 switch (dev->if_port) {
1779 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1780 if (media_status & Media_LnkBeat) {
1781 netif_carrier_on(dev);
1782 ok = 1;
1783 if (vortex_debug > 1)
1784 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1785 dev->name, media_tbl[dev->if_port].name, media_status);
1786 } else {
1787 netif_carrier_off(dev);
1788 if (vortex_debug > 1) {
1789 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1790 dev->name, media_tbl[dev->if_port].name, media_status);
1791 }
1792 }
1793 break;
1794 case XCVR_MII: case XCVR_NWAY:
1795 {
1da177e4 1796 ok = 1;
c5643cab
IM		 1797 /* Interrupts are already disabled */
1798 spin_lock(&vp->lock);
125d5ce8 1799 vortex_check_media(dev, 0);
c5643cab 1800 spin_unlock(&vp->lock);
1da177e4
LT		 1801 }
1802 break;
1803 default: /* Other media types handled by Tx timeouts. */
1804 if (vortex_debug > 1)
1805 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1806 dev->name, media_tbl[dev->if_port].name, media_status);
1807 ok = 1;
1808 }
b4ff6450
SK		 1809
1810 if (!netif_carrier_ok(dev))
1811 next_tick = 5*HZ;
1812
e94d10eb
SK		 1813 if (vp->medialock)
1814 goto leave_media_alone;
1815
a880c4cd 1816 if (!ok) {
1da177e4
LT		 1817 unsigned int config;
1818
1819 do {
1820 dev->if_port = media_tbl[dev->if_port].next;
1821 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1822 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1823 dev->if_port = vp->default_media;
1824 if (vortex_debug > 1)
1825 printk(KERN_DEBUG "%s: Media selection failing, using default "
1826 "%s port.\n",
1827 dev->name, media_tbl[dev->if_port].name);
1828 } else {
1829 if (vortex_debug > 1)
1830 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1831 "%s port.\n",
1832 dev->name, media_tbl[dev->if_port].name);
1833 next_tick = media_tbl[dev->if_port].wait;
1834 }
62afe595 1835 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1836 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1837
1838 EL3WINDOW(3);
62afe595 1839 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1840 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1841 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1842
62afe595 1843 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1844 ioaddr + EL3_CMD);
1845 if (vortex_debug > 1)
1846 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1847 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1848 }
1da177e4
LT		 1849
1850leave_media_alone:
1851 if (vortex_debug > 2)
1852 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1853 dev->name, media_tbl[dev->if_port].name);
1854
e94d10eb 1855 EL3WINDOW(old_window);
0a9da4bd 1856 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1857 mod_timer(&vp->timer, RUN_AT(next_tick));
1858 if (vp->deferred)
62afe595 1859 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1860 return;
1861}
1862
1863static void vortex_tx_timeout(struct net_device *dev)
1864{
1865 struct vortex_private *vp = netdev_priv(dev);
62afe595 1866 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1867
1868 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1869 dev->name, ioread8(ioaddr + TxStatus),
1870 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1871 EL3WINDOW(4);
1872 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1873 ioread16(ioaddr + Wn4_NetDiag),
1874 ioread16(ioaddr + Wn4_Media),
1875 ioread32(ioaddr + PktStatus),
1876 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1877 /* Slight code bloat to be user friendly. */
62afe595 1878 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1879 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1880 " network cable problem?\n", dev->name);
62afe595 1881 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1882 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1883 " IRQ blocked by another device?\n", dev->name);
1884 /* Bad idea here.. but we might as well handle a few events. */
1885 {
1886 /*
1887 * Block interrupts because vortex_interrupt does a bare spin_lock()
1888 */
1889 unsigned long flags;
1890 local_irq_save(flags);
1891 if (vp->full_bus_master_tx)
7d12e780 1892 boomerang_interrupt(dev->irq, dev);
1da177e4 1893 else
7d12e780 1894 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1895 local_irq_restore(flags);
1896 }
1897 }
1898
1899 if (vortex_debug > 0)
1900 dump_tx_ring(dev);
1901
1902 issue_and_wait(dev, TxReset);
1903
1daad055 1904 dev->stats.tx_errors++;
1da177e4
LT		 1905 if (vp->full_bus_master_tx) {
1906 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1907 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1908 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1909 ioaddr + DownListPtr);
1910 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1911 netif_wake_queue (dev);
1912 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1913 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1914 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1915 } else {
1daad055 1916 dev->stats.tx_dropped++;
1da177e4
LT		 1917 netif_wake_queue(dev);
1918 }
6aa20a22 1919
1da177e4 1920 /* Issue Tx Enable */
62afe595 1921 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1922 dev->trans_start = jiffies;
6aa20a22 1923
1da177e4
LT		 1924 /* Switch to register set 7 for normal use. */
1925 EL3WINDOW(7);
1926}
1927
1928/*
1929 * Handle uncommon interrupt sources. This is a separate routine to minimize
1930 * the cache impact.
1931 */
1932static void
1933vortex_error(struct net_device *dev, int status)
1934{
1935 struct vortex_private *vp = netdev_priv(dev);
62afe595 1936 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1937 int do_tx_reset = 0, reset_mask = 0;
1938 unsigned char tx_status = 0;
1939
1940 if (vortex_debug > 2) {
1941 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1942 }
1943
1944 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1945 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1946 /* Presumably a tx-timeout. We must merely re-enable. */
1947 if (vortex_debug > 2
1948 || (tx_status != 0x88 && vortex_debug > 0)) {
1949 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1950 dev->name, tx_status);
1951 if (tx_status == 0x82) {
1952 printk(KERN_ERR "Probably a duplex mismatch. See "
1953 "Documentation/networking/vortex.txt\n");
1954 }
1955 dump_tx_ring(dev);
1956 }
1daad055
PZ		 1957 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1958 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1959 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1960 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1961 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1962 do_tx_reset = 1;
0000754c
AM		 1963 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1964 do_tx_reset = 1;
1965 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1966 } else { /* Merely re-enable the transmitter. */
62afe595 1967 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1968 }
1969 }
1970
1971 if (status & RxEarly) { /* Rx early is unused. */
1972 vortex_rx(dev);
62afe595 1973 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1974 }
1975 if (status & StatsFull) { /* Empty statistics. */
1976 static int DoneDidThat;
1977 if (vortex_debug > 4)
1978 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1979 update_stats(ioaddr, dev);
1980 /* HACK: Disable statistics as an interrupt source. */
1981 /* This occurs when we have the wrong media type! */
1982 if (DoneDidThat == 0 &&
62afe595 1983 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1984 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1985 "stats as an interrupt source.\n", dev->name);
1986 EL3WINDOW(5);
62afe595 1987 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1988 vp->intr_enable &= ~StatsFull;
1989 EL3WINDOW(7);
1990 DoneDidThat++;
1991 }
1992 }
1993 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1994 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1995 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1996 }
1997 if (status & HostError) {
1998 u16 fifo_diag;
1999 EL3WINDOW(4);
62afe595 2000 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 2001 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2002 dev->name, fifo_diag);
2003 /* Adapter failure requires Tx/Rx reset and reinit. */
2004 if (vp->full_bus_master_tx) {
62afe595 2005 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2006 /* 0x80000000 PCI master abort. */
2007 /* 0x40000000 PCI target abort. */
2008 if (vortex_debug)
2009 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2010
2011 /* In this case, blow the card away */
2012 /* Must not enter D3 or we can't legally issue the reset! */
2013 vortex_down(dev, 0);
2014 issue_and_wait(dev, TotalReset | 0xff);
2015 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2016 } else if (fifo_diag & 0x0400)
2017 do_tx_reset = 1;
2018 if (fifo_diag & 0x3000) {
2019 /* Reset Rx fifo and upload logic */
2020 issue_and_wait(dev, RxReset|0x07);
2021 /* Set the Rx filter to the current state. */
2022 set_rx_mode(dev);
2023 /* enable 802.1q VLAN tagged frames */
2024 set_8021q_mode(dev, 1);
62afe595
JL		 2025 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2026 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2027 }
2028 }
2029
2030 if (do_tx_reset) {
2031 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2032 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2033 if (!vp->full_bus_master_tx)
2034 netif_wake_queue(dev);
2035 }
2036}
2037
2038static int
2039vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2040{
2041 struct vortex_private *vp = netdev_priv(dev);
62afe595 2042 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2043
2044 /* Put out the doubleword header... */
62afe595 2045 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2046 if (vp->bus_master) {
2047 /* Set the bus-master controller to transfer the packet. */
2048 int len = (skb->len + 3) & ~3;
a880c4cd 2049 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2050 ioaddr + Wn7_MasterAddr);
62afe595 2051 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2052 vp->tx_skb = skb;
62afe595 2053 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2054 /* netif_wake_queue() will be called at the DMADone interrupt. */
2055 } else {
2056 /* ... and the packet rounded to a doubleword. */
62afe595 2057 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2058 dev_kfree_skb (skb);
62afe595 2059 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2060 netif_start_queue (dev); /* AKPM: redundant? */
2061 } else {
2062 /* Interrupt us when the FIFO has room for max-sized packet. */
2063 netif_stop_queue(dev);
62afe595 2064 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2065 }
2066 }
2067
2068 dev->trans_start = jiffies;
2069
2070 /* Clear the Tx status stack. */
2071 {
2072 int tx_status;
2073 int i = 32;
2074
62afe595 2075 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2076 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2077 if (vortex_debug > 2)
2078 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2079 dev->name, tx_status);
1daad055
PZ		 2080 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2081 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2082 if (tx_status & 0x30) {
2083 issue_and_wait(dev, TxReset);
2084 }
62afe595 2085 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2086 }
62afe595 2087 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2088 }
2089 }
2090 return 0;
2091}
2092
2093static int
2094boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2095{
2096 struct vortex_private *vp = netdev_priv(dev);
62afe595 2097 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2098 /* Calculate the next Tx descriptor entry. */
2099 int entry = vp->cur_tx % TX_RING_SIZE;
2100 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2101 unsigned long flags;
2102
2103 if (vortex_debug > 6) {
2104 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2105 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2106 dev->name, vp->cur_tx);
1da177e4
LT		 2107 }
2108
2109 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2110 if (vortex_debug > 0)
2111 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2112 dev->name);
2113 netif_stop_queue(dev);
2114 return 1;
2115 }
2116
2117 vp->tx_skbuff[entry] = skb;
2118
2119 vp->tx_ring[entry].next = 0;
2120#if DO_ZEROCOPY
84fa7933 2121 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2122 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2123 else
2124 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2125
2126 if (!skb_shinfo(skb)->nr_frags) {
2127 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2128 skb->len, PCI_DMA_TODEVICE));
2129 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2130 } else {
2131 int i;
2132
2133 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2134 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2135 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2136
2137 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2138 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2139
2140 vp->tx_ring[entry].frag[i+1].addr =
2141 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2142 (void*)page_address(frag->page) + frag->page_offset,
2143 frag->size, PCI_DMA_TODEVICE));
2144
2145 if (i == skb_shinfo(skb)->nr_frags-1)
2146 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2147 else
2148 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2149 }
2150 }
2151#else
2152 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2153 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2154 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2155#endif
2156
2157 spin_lock_irqsave(&vp->lock, flags);
2158 /* Wait for the stall to complete. */
2159 issue_and_wait(dev, DownStall);
2160 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2161 if (ioread32(ioaddr + DownListPtr) == 0) {
2162 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2163 vp->queued_packet++;
2164 }
2165
2166 vp->cur_tx++;
2167 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2168 netif_stop_queue (dev);
2169 } else { /* Clear previous interrupt enable. */
2170#if defined(tx_interrupt_mitigation)
2171 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2172 * were selected, this would corrupt DN_COMPLETE. No?
2173 */
2174 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2175#endif
2176 }
62afe595 2177 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2178 spin_unlock_irqrestore(&vp->lock, flags);
2179 dev->trans_start = jiffies;
2180 return 0;
2181}
2182
2183/* The interrupt handler does all of the Rx thread work and cleans up
2184 after the Tx thread. */
2185
2186/*
2187 * This is the ISR for the vortex series chips.
2188 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2189 */
2190
2191static irqreturn_t
7d12e780 2192vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2193{
2194 struct net_device *dev = dev_id;
2195 struct vortex_private *vp = netdev_priv(dev);
62afe595 2196 void __iomem *ioaddr;
1da177e4
LT		 2197 int status;
2198 int work_done = max_interrupt_work;
2199 int handled = 0;
2200
62afe595 2201 ioaddr = vp->ioaddr;
1da177e4
LT		 2202 spin_lock(&vp->lock);
2203
62afe595 2204 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2205
2206 if (vortex_debug > 6)
2207 printk("vortex_interrupt(). status=0x%4x\n", status);
2208
2209 if ((status & IntLatch) == 0)
2210 goto handler_exit; /* No interrupt: shared IRQs cause this */
2211 handled = 1;
2212
2213 if (status & IntReq) {
2214 status |= vp->deferred;
2215 vp->deferred = 0;
2216 }
2217
2218 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2219 goto handler_exit;
2220
2221 if (vortex_debug > 4)
2222 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2223 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2224
2225 do {
2226 if (vortex_debug > 5)
2227 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2228 dev->name, status);
2229 if (status & RxComplete)
2230 vortex_rx(dev);
2231
2232 if (status & TxAvailable) {
2233 if (vortex_debug > 5)
2234 printk(KERN_DEBUG " TX room bit was handled.\n");
2235 /* There's room in the FIFO for a full-sized packet. */
62afe595 2236 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2237 netif_wake_queue (dev);
2238 }
2239
2240 if (status & DMADone) {
62afe595
JL		 2241 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2242 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2243 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2244 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2245 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2246 /*
2247 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2248 * insufficient FIFO room, the TxAvailable test will succeed and call
2249 * netif_wake_queue()
2250 */
2251 netif_wake_queue(dev);
2252 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2253 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2254 netif_stop_queue(dev);
2255 }
2256 }
2257 }
2258 /* Check for all uncommon interrupts at once. */
2259 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2260 if (status == 0xffff)
2261 break;
2262 vortex_error(dev, status);
2263 }
2264
2265 if (--work_done < 0) {
2266 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2267 "%4.4x.\n", dev->name, status);
2268 /* Disable all pending interrupts. */
2269 do {
2270 vp->deferred |= status;
62afe595 2271 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2272 ioaddr + EL3_CMD);
62afe595
JL		 2273 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2274 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2275 /* The timer will reenable interrupts. */
2276 mod_timer(&vp->timer, jiffies + 1*HZ);
2277 break;
2278 }
2279 /* Acknowledge the IRQ. */
62afe595
JL		 2280 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2281 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2282
2283 if (vortex_debug > 4)
2284 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2285 dev->name, status);
2286handler_exit:
2287 spin_unlock(&vp->lock);
2288 return IRQ_RETVAL(handled);
2289}
2290
2291/*
2292 * This is the ISR for the boomerang series chips.
2293 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2294 */
2295
2296static irqreturn_t
7d12e780 2297boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2298{
2299 struct net_device *dev = dev_id;
2300 struct vortex_private *vp = netdev_priv(dev);
62afe595 2301 void __iomem *ioaddr;
1da177e4
LT		 2302 int status;
2303 int work_done = max_interrupt_work;
2304
62afe595 2305 ioaddr = vp->ioaddr;
1da177e4
LT		 2306
2307 /*
2308 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2309 * and boomerang_start_xmit
2310 */
2311 spin_lock(&vp->lock);
2312
62afe595 2313 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2314
2315 if (vortex_debug > 6)
2316 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2317
2318 if ((status & IntLatch) == 0)
2319 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2320
2321 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2322 if (vortex_debug > 1)
2323 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2324 goto handler_exit;
2325 }
2326
2327 if (status & IntReq) {
2328 status |= vp->deferred;
2329 vp->deferred = 0;
2330 }
2331
2332 if (vortex_debug > 4)
2333 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2334 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2335 do {
2336 if (vortex_debug > 5)
2337 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2338 dev->name, status);
2339 if (status & UpComplete) {
62afe595 2340 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2341 if (vortex_debug > 5)
2342 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2343 boomerang_rx(dev);
2344 }
2345
2346 if (status & DownComplete) {
2347 unsigned int dirty_tx = vp->dirty_tx;
2348
62afe595 2349 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2350 while (vp->cur_tx - dirty_tx > 0) {
2351 int entry = dirty_tx % TX_RING_SIZE;
2352#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2353 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2354 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2355 break; /* It still hasn't been processed. */
2356#else
2357 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2358 break; /* It still hasn't been processed. */
2359#endif
6aa20a22 2360
1da177e4
LT		 2361 if (vp->tx_skbuff[entry]) {
2362 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2363#if DO_ZEROCOPY
1da177e4
LT		 2364 int i;
2365 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2366 pci_unmap_single(VORTEX_PCI(vp),
2367 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2368 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2369 PCI_DMA_TODEVICE);
2370#else
2371 pci_unmap_single(VORTEX_PCI(vp),
2372 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2373#endif
2374 dev_kfree_skb_irq(skb);
2375 vp->tx_skbuff[entry] = NULL;
2376 } else {
2377 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2378 }
1daad055 2379 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2380 dirty_tx++;
2381 }
2382 vp->dirty_tx = dirty_tx;
2383 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2384 if (vortex_debug > 6)
2385 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2386 netif_wake_queue (dev);
2387 }
2388 }
2389
2390 /* Check for all uncommon interrupts at once. */
2391 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2392 vortex_error(dev, status);
2393
2394 if (--work_done < 0) {
2395 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2396 "%4.4x.\n", dev->name, status);
2397 /* Disable all pending interrupts. */
2398 do {
2399 vp->deferred |= status;
62afe595 2400 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2401 ioaddr + EL3_CMD);
62afe595
JL		 2402 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2403 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2404 /* The timer will reenable interrupts. */
2405 mod_timer(&vp->timer, jiffies + 1*HZ);
2406 break;
2407 }
2408 /* Acknowledge the IRQ. */
62afe595 2409 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2410 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2411 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2412
62afe595 2413 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2414
2415 if (vortex_debug > 4)
2416 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2417 dev->name, status);
2418handler_exit:
2419 spin_unlock(&vp->lock);
2420 return IRQ_HANDLED;
2421}
2422
2423static int vortex_rx(struct net_device *dev)
2424{
2425 struct vortex_private *vp = netdev_priv(dev);
62afe595 2426 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2427 int i;
2428 short rx_status;
2429
2430 if (vortex_debug > 5)
2431 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2432 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2433 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2434 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2435 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2436 if (vortex_debug > 2)
2437 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2438 dev->stats.rx_errors++;
2439 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2440 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2441 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2442 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2443 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2444 } else {
2445 /* The packet length: up to 4.5K!. */
2446 int pkt_len = rx_status & 0x1fff;
2447 struct sk_buff *skb;
2448
2449 skb = dev_alloc_skb(pkt_len + 5);
2450 if (vortex_debug > 4)
2451 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2452 pkt_len, rx_status);
2453 if (skb != NULL) {
1da177e4
LT		 2454 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2455 /* 'skb_put()' points to the start of sk_buff data area. */
2456 if (vp->bus_master &&
62afe595 2457 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2458 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2459 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2460 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2461 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2462 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2463 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2464 ;
2465 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2466 } else {
62afe595
JL		 2467 ioread32_rep(ioaddr + RX_FIFO,
2468 skb_put(skb, pkt_len),
2469 (pkt_len + 3) >> 2);
1da177e4 2470 }
62afe595 2471 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2472 skb->protocol = eth_type_trans(skb, dev);
2473 netif_rx(skb);
1daad055 2474 dev->stats.rx_packets++;
1da177e4
LT		 2475 /* Wait a limited time to go to next packet. */
2476 for (i = 200; i >= 0; i--)
62afe595 2477 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2478 break;
2479 continue;
2480 } else if (vortex_debug > 0)
2481 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2482 "size %d.\n", dev->name, pkt_len);
1daad055 2483 dev->stats.rx_dropped++;
1da177e4 2484 }
1da177e4
LT		 2485 issue_and_wait(dev, RxDiscard);
2486 }
2487
2488 return 0;
2489}
2490
2491static int
2492boomerang_rx(struct net_device *dev)
2493{
2494 struct vortex_private *vp = netdev_priv(dev);
2495 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2496 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2497 int rx_status;
2498 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2499
2500 if (vortex_debug > 5)
62afe595 2501 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2502
2503 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2504 if (--rx_work_limit < 0)
2505 break;
2506 if (rx_status & RxDError) { /* Error, update stats. */
2507 unsigned char rx_error = rx_status >> 16;
2508 if (vortex_debug > 2)
2509 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2510 dev->stats.rx_errors++;
2511 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2512 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2513 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2514 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2515 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2516 } else {
2517 /* The packet length: up to 4.5K!. */
2518 int pkt_len = rx_status & 0x1fff;
2519 struct sk_buff *skb;
2520 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2521
2522 if (vortex_debug > 4)
2523 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2524 pkt_len, rx_status);
2525
2526 /* Check if the packet is long enough to just accept without
2527 copying to a properly sized skbuff. */
cc2d6596 2528 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2529 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2530 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2531 /* 'skb_put()' points to the start of sk_buff data area. */
2532 memcpy(skb_put(skb, pkt_len),
689be439 2533 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2534 pkt_len);
2535 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2536 vp->rx_copy++;
2537 } else {
2538 /* Pass up the skbuff already on the Rx ring. */
2539 skb = vp->rx_skbuff[entry];
2540 vp->rx_skbuff[entry] = NULL;
2541 skb_put(skb, pkt_len);
2542 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2543 vp->rx_nocopy++;
2544 }
2545 skb->protocol = eth_type_trans(skb, dev);
2546 { /* Use hardware checksum info. */
2547 int csum_bits = rx_status & 0xee000000;
2548 if (csum_bits &&
2549 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2550 csum_bits == (IPChksumValid | UDPChksumValid))) {
2551 skb->ip_summed = CHECKSUM_UNNECESSARY;
2552 vp->rx_csumhits++;
2553 }
2554 }
2555 netif_rx(skb);
1daad055 2556 dev->stats.rx_packets++;
1da177e4
LT		 2557 }
2558 entry = (++vp->cur_rx) % RX_RING_SIZE;
2559 }
2560 /* Refill the Rx ring buffers. */
2561 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2562 struct sk_buff *skb;
2563 entry = vp->dirty_rx % RX_RING_SIZE;
2564 if (vp->rx_skbuff[entry] == NULL) {
9a5d3414 2565 skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1da177e4
LT		 2566 if (skb == NULL) {
2567 static unsigned long last_jif;
ff5688ae 2568 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2569 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2570 last_jif = jiffies;
2571 }
2572 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2573 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2574 break; /* Bad news! */
2575 }
9a5d3414
SH		 2576
2577 skb_reserve(skb, NET_IP_ALIGN);
689be439 2578 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2579 vp->rx_skbuff[entry] = skb;
2580 }
2581 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2582 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2583 }
2584 return 0;
2585}
2586
2587/*
2588 * If we've hit a total OOM refilling the Rx ring we poll once a second
2589 * for some memory. Otherwise there is no way to restart the rx process.
2590 */
2591static void
2592rx_oom_timer(unsigned long arg)
2593{
2594 struct net_device *dev = (struct net_device *)arg;
2595 struct vortex_private *vp = netdev_priv(dev);
2596
2597 spin_lock_irq(&vp->lock);
2598 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2599 boomerang_rx(dev);
2600 if (vortex_debug > 1) {
2601 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2602 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2603 }
2604 spin_unlock_irq(&vp->lock);
2605}
2606
2607static void
2608vortex_down(struct net_device *dev, int final_down)
2609{
2610 struct vortex_private *vp = netdev_priv(dev);
62afe595 2611 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2612
2613 netif_stop_queue (dev);
2614
2615 del_timer_sync(&vp->rx_oom_timer);
2616 del_timer_sync(&vp->timer);
2617
1daad055 2618 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2619 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2620
2621 /* Disable the receiver and transmitter. */
62afe595
JL		 2622 iowrite16(RxDisable, ioaddr + EL3_CMD);
2623 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2624
2625 /* Disable receiving 802.1q tagged frames */
2626 set_8021q_mode(dev, 0);
2627
2628 if (dev->if_port == XCVR_10base2)
2629 /* Turn off thinnet power. Green! */
62afe595 2630 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2631
62afe595 2632 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2633
2634 update_stats(ioaddr, dev);
2635 if (vp->full_bus_master_rx)
62afe595 2636 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2637 if (vp->full_bus_master_tx)
62afe595 2638 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2639
2640 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2641 vp->pm_state_valid = 1;
1da177e4
LT		 2642 pci_save_state(VORTEX_PCI(vp));
2643 acpi_set_WOL(dev);
2644 }
2645}
2646
2647static int
2648vortex_close(struct net_device *dev)
2649{
2650 struct vortex_private *vp = netdev_priv(dev);
62afe595 2651 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2652 int i;
2653
2654 if (netif_device_present(dev))
2655 vortex_down(dev, 1);
2656
2657 if (vortex_debug > 1) {
2658 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2659 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2660 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2661 " tx_queued %d Rx pre-checksummed %d.\n",
2662 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2663 }
2664
2665#if DO_ZEROCOPY
32fb5f06
JL		 2666 if (vp->rx_csumhits &&
2667 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2668 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2669 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2670 "not using them!\n", dev->name);
1da177e4
LT		 2671 }
2672#endif
6aa20a22 2673
1da177e4
LT		 2674 free_irq(dev->irq, dev);
2675
2676 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2677 for (i = 0; i < RX_RING_SIZE; i++)
2678 if (vp->rx_skbuff[i]) {
2679 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2680 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2681 dev_kfree_skb(vp->rx_skbuff[i]);
2682 vp->rx_skbuff[i] = NULL;
2683 }
2684 }
2685 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2686 for (i = 0; i < TX_RING_SIZE; i++) {
2687 if (vp->tx_skbuff[i]) {
2688 struct sk_buff *skb = vp->tx_skbuff[i];
2689#if DO_ZEROCOPY
2690 int k;
2691
2692 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2693 pci_unmap_single(VORTEX_PCI(vp),
2694 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2695 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2696 PCI_DMA_TODEVICE);
2697#else
2698 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2699#endif
2700 dev_kfree_skb(skb);
2701 vp->tx_skbuff[i] = NULL;
2702 }
2703 }
2704 }
2705
2706 return 0;
2707}
2708
2709static void
2710dump_tx_ring(struct net_device *dev)
2711{
2712 if (vortex_debug > 0) {
2713 struct vortex_private *vp = netdev_priv(dev);
62afe595 2714 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2715
1da177e4
LT		 2716 if (vp->full_bus_master_tx) {
2717 int i;
62afe595 2718 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2719
2720 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2721 vp->full_bus_master_tx,
2722 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2723 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2724 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2725 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2726 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2727 issue_and_wait(dev, DownStall);
2728 for (i = 0; i < TX_RING_SIZE; i++) {
2729 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2730 &vp->tx_ring[i],
2731#if DO_ZEROCOPY
2732 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2733#else
2734 le32_to_cpu(vp->tx_ring[i].length),
2735#endif
2736 le32_to_cpu(vp->tx_ring[i].status));
2737 }
2738 if (!stalled)
62afe595 2739 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2740 }
2741 }
2742}
2743
2744static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2745{
2746 struct vortex_private *vp = netdev_priv(dev);
62afe595 2747 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2748 unsigned long flags;
2749
2750 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2751 spin_lock_irqsave (&vp->lock, flags);
62afe595 2752 update_stats(ioaddr, dev);
1da177e4
LT		 2753 spin_unlock_irqrestore (&vp->lock, flags);
2754 }
1daad055 2755 return &dev->stats;
1da177e4
LT		 2756}
2757
2758/* Update statistics.
2759 Unlike with the EL3 we need not worry about interrupts changing
2760 the window setting from underneath us, but we must still guard
2761 against a race condition with a StatsUpdate interrupt updating the
2762 table. This is done by checking that the ASM (!) code generated uses
2763 atomic updates with '+='.
2764 */
62afe595 2765static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2766{
2767 struct vortex_private *vp = netdev_priv(dev);
62afe595 2768 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2769
2770 if (old_window == 0xffff) /* Chip suspended or ejected. */
2771 return;
2772 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2773 /* Switch to the stats window, and read everything. */
2774 EL3WINDOW(6);
1daad055
PZ		 2775 dev->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2776 dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2777 dev->stats.tx_window_errors += ioread8(ioaddr + 4);
2778 dev->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2779 dev->stats.tx_packets += ioread8(ioaddr + 6);
2780 dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
62afe595 2781 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2782 /* Don't bother with register 9, an extension of registers 6&7.
2783 If we do use the 6&7 values the atomic update assumption above
2784 is invalid. */
1daad055
PZ		 2785 dev->stats.rx_bytes += ioread16(ioaddr + 10);
2786 dev->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2787 /* Extra stats for get_ethtool_stats() */
62afe595 2788 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2789 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2790 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2791 EL3WINDOW(4);
62afe595 2792 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2793
1daad055 2794 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2795 + vp->xstats.tx_single_collisions
2796 + vp->xstats.tx_max_collisions;
2797
1da177e4 2798 {
62afe595 2799 u8 up = ioread8(ioaddr + 13);
1daad055
PZ		 2800 dev->stats.rx_bytes += (up & 0x0f) << 16;
2801 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4
LT		 2802 }
2803
2804 EL3WINDOW(old_window >> 13);
2805 return;
2806}
2807
2808static int vortex_nway_reset(struct net_device *dev)
2809{
2810 struct vortex_private *vp = netdev_priv(dev);
62afe595 2811 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2812 unsigned long flags;
2813 int rc;
2814
2815 spin_lock_irqsave(&vp->lock, flags);
2816 EL3WINDOW(4);
2817 rc = mii_nway_restart(&vp->mii);
2818 spin_unlock_irqrestore(&vp->lock, flags);
2819 return rc;
2820}
2821
1da177e4
LT		 2822static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2823{
2824 struct vortex_private *vp = netdev_priv(dev);
62afe595 2825 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2826 unsigned long flags;
2827 int rc;
2828
2829 spin_lock_irqsave(&vp->lock, flags);
2830 EL3WINDOW(4);
2831 rc = mii_ethtool_gset(&vp->mii, cmd);
2832 spin_unlock_irqrestore(&vp->lock, flags);
2833 return rc;
2834}
2835
2836static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2837{
2838 struct vortex_private *vp = netdev_priv(dev);
62afe595 2839 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2840 unsigned long flags;
2841 int rc;
2842
2843 spin_lock_irqsave(&vp->lock, flags);
2844 EL3WINDOW(4);
2845 rc = mii_ethtool_sset(&vp->mii, cmd);
2846 spin_unlock_irqrestore(&vp->lock, flags);
2847 return rc;
2848}
2849
2850static u32 vortex_get_msglevel(struct net_device *dev)
2851{
2852 return vortex_debug;
2853}
2854
2855static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2856{
2857 vortex_debug = dbg;
2858}
2859
b9f2c044 2860static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2861{
b9f2c044
JG		 2862 switch (sset) {
2863 case ETH_SS_STATS:
2864 return VORTEX_NUM_STATS;
2865 default:
2866 return -EOPNOTSUPP;
2867 }
1da177e4
LT		 2868}
2869
2870static void vortex_get_ethtool_stats(struct net_device *dev,
2871 struct ethtool_stats *stats, u64 *data)
2872{
2873 struct vortex_private *vp = netdev_priv(dev);
62afe595 2874 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2875 unsigned long flags;
2876
2877 spin_lock_irqsave(&vp->lock, flags);
62afe595 2878 update_stats(ioaddr, dev);
1da177e4
LT		 2879 spin_unlock_irqrestore(&vp->lock, flags);
2880
2881 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2882 data[1] = vp->xstats.tx_max_collisions;
2883 data[2] = vp->xstats.tx_multiple_collisions;
2884 data[3] = vp->xstats.tx_single_collisions;
2885 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2886}
2887
2888
2889static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2890{
2891 switch (stringset) {
2892 case ETH_SS_STATS:
2893 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2894 break;
2895 default:
2896 WARN_ON(1);
2897 break;
2898 }
2899}
2900
2901static void vortex_get_drvinfo(struct net_device *dev,
2902 struct ethtool_drvinfo *info)
2903{
2904 struct vortex_private *vp = netdev_priv(dev);
2905
2906 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2907 if (VORTEX_PCI(vp)) {
2908 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2909 } else {
2910 if (VORTEX_EISA(vp))
fb28ad35 2911 sprintf(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2912 else
2913 sprintf(info->bus_info, "EISA 0x%lx %d",
2914 dev->base_addr, dev->irq);
2915 }
2916}
2917
7282d491 2918static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2919 .get_drvinfo = vortex_get_drvinfo,
2920 .get_strings = vortex_get_strings,
2921 .get_msglevel = vortex_get_msglevel,
2922 .set_msglevel = vortex_set_msglevel,
2923 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2924 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2925 .get_settings = vortex_get_settings,
2926 .set_settings = vortex_set_settings,
373a6887 2927 .get_link = ethtool_op_get_link,
1da177e4
LT		 2928 .nway_reset = vortex_nway_reset,
2929};
2930
2931#ifdef CONFIG_PCI
2932/*
2933 * Must power the device up to do MDIO operations
2934 */
2935static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2936{
2937 int err;
2938 struct vortex_private *vp = netdev_priv(dev);
62afe595 2939 void __iomem *ioaddr = vp->ioaddr;
1da177e4 2940 unsigned long flags;
cc2d6596 2941 pci_power_t state = 0;
1da177e4
LT		 2942
2943 if(VORTEX_PCI(vp))
2944 state = VORTEX_PCI(vp)->current_state;
2945
2946 /* The kernel core really should have pci_get_power_state() */
2947
2948 if(state != 0)
2949 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2950 spin_lock_irqsave(&vp->lock, flags);
2951 EL3WINDOW(4);
2952 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2953 spin_unlock_irqrestore(&vp->lock, flags);
2954 if(state != 0)
2955 pci_set_power_state(VORTEX_PCI(vp), state);
2956
2957 return err;
2958}
2959#endif
2960
2961
2962/* Pre-Cyclone chips have no documented multicast filter, so the only
2963 multicast setting is to receive all multicast frames. At least
2964 the chip has a very clean way to set the mode, unlike many others. */
2965static void set_rx_mode(struct net_device *dev)
2966{
62afe595
JL		 2967 struct vortex_private *vp = netdev_priv(dev);
2968 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2969 int new_mode;
2970
2971 if (dev->flags & IFF_PROMISC) {
d5b20697 2972 if (vortex_debug > 3)
1da177e4
LT		 2973 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2974 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2975 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2976 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2977 } else
2978 new_mode = SetRxFilter | RxStation | RxBroadcast;
2979
62afe595 2980 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2981}
2982
2983#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2984/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2985 Note that this must be done after each RxReset due to some backwards
2986 compatibility logic in the Cyclone and Tornado ASICs */
2987
2988/* The Ethernet Type used for 802.1q tagged frames */
2989#define VLAN_ETHER_TYPE 0x8100
2990
2991static void set_8021q_mode(struct net_device *dev, int enable)
2992{
2993 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2994 void __iomem *ioaddr = vp->ioaddr;
2995 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2996 int mac_ctrl;
2997
2998 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2999 /* cyclone and tornado chipsets can recognize 802.1q
3000 * tagged frames and treat them correctly */
3001
3002 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3003 if (enable)
3004 max_pkt_size += 4; /* 802.1Q VLAN tag */
3005
3006 EL3WINDOW(3);
62afe595 3007 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3008
3009 /* set VlanEtherType to let the hardware checksumming
3010 treat tagged frames correctly */
3011 EL3WINDOW(7);
62afe595 3012 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3013 } else {
3014 /* on older cards we have to enable large frames */
3015
3016 vp->large_frames = dev->mtu > 1500 || enable;
3017
3018 EL3WINDOW(3);
62afe595 3019 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3020 if (vp->large_frames)
3021 mac_ctrl |= 0x40;
3022 else
3023 mac_ctrl &= ~0x40;
62afe595 3024 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3025 }
3026
3027 EL3WINDOW(old_window);
3028}
3029#else
3030
3031static void set_8021q_mode(struct net_device *dev, int enable)
3032{
3033}
3034
3035
3036#endif
3037
3038/* MII transceiver control section.
3039 Read and write the MII registers using software-generated serial
3040 MDIO protocol. See the MII specifications or DP83840A data sheet
3041 for details. */
3042
3043/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3044 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3045 "overclocking" issues. */
62afe595 3046#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3047
3048#define MDIO_SHIFT_CLK 0x01
3049#define MDIO_DIR_WRITE 0x04
3050#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3051#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3052#define MDIO_DATA_READ 0x02
3053#define MDIO_ENB_IN 0x00
3054
3055/* Generate the preamble required for initial synchronization and
3056 a few older transceivers. */
62afe595 3057static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3058{
62afe595 3059 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3060
3061 /* Establish sync by sending at least 32 logic ones. */
3062 while (-- bits >= 0) {
62afe595 3063 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3064 mdio_delay();
62afe595 3065 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3066 mdio_delay();
3067 }
3068}
3069
3070static int mdio_read(struct net_device *dev, int phy_id, int location)
3071{
3072 int i;
62afe595
JL		 3073 struct vortex_private *vp = netdev_priv(dev);
3074 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3075 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3076 unsigned int retval = 0;
62afe595 3077 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3078
3079 if (mii_preamble_required)
3080 mdio_sync(ioaddr, 32);
3081
3082 /* Shift the read command bits out. */
3083 for (i = 14; i >= 0; i--) {
3084 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3085 iowrite16(dataval, mdio_addr);
1da177e4 3086 mdio_delay();
62afe595 3087 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3088 mdio_delay();
3089 }
3090 /* Read the two transition, 16 data, and wire-idle bits. */
3091 for (i = 19; i > 0; i--) {
62afe595 3092 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3093 mdio_delay();
62afe595
JL		 3094 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3095 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3096 mdio_delay();
3097 }
3098 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3099}
3100
3101static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3102{
62afe595
JL		 3103 struct vortex_private *vp = netdev_priv(dev);
3104 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3105 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3106 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3107 int i;
3108
3109 if (mii_preamble_required)
3110 mdio_sync(ioaddr, 32);
3111
3112 /* Shift the command bits out. */
3113 for (i = 31; i >= 0; i--) {
3114 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3115 iowrite16(dataval, mdio_addr);
1da177e4 3116 mdio_delay();
62afe595 3117 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3118 mdio_delay();
3119 }
3120 /* Leave the interface idle. */
3121 for (i = 1; i >= 0; i--) {
62afe595 3122 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3123 mdio_delay();
62afe595 3124 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3125 mdio_delay();
3126 }
3127 return;
3128}
a880c4cd 3129
1da177e4
LT		 3130/* ACPI: Advanced Configuration and Power Interface. */
3131/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3132static void acpi_set_WOL(struct net_device *dev)
3133{
3134 struct vortex_private *vp = netdev_priv(dev);
62afe595 3135 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3136
c17931c5
SK		 3137 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3138
1da177e4
LT		 3139 if (vp->enable_wol) {
3140 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3141 EL3WINDOW(7);
62afe595 3142 iowrite16(2, ioaddr + 0x0c);
1da177e4 3143 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3144 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3145 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3146
1a1769f3
SK		 3147 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3148 printk(KERN_INFO "%s: WOL not supported.\n",
3149 pci_name(VORTEX_PCI(vp)));
3150
3151 vp->enable_wol = 0;
3152 return;
3153 }
3c8fad18
DR		 3154
3155 /* Change the power state to D3; RxEnable doesn't take effect. */
3156 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3157 }
1da177e4
LT		 3158}
3159
3160
a880c4cd 3161static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3162{
3163 struct net_device *dev = pci_get_drvdata(pdev);
3164 struct vortex_private *vp;
3165
3166 if (!dev) {
3167 printk("vortex_remove_one called for Compaq device!\n");
3168 BUG();
3169 }
3170
3171 vp = netdev_priv(dev);
3172
62afe595
JL		 3173 if (vp->cb_fn_base)
3174 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3175
1da177e4
LT		 3176 unregister_netdev(dev);
3177
3178 if (VORTEX_PCI(vp)) {
3179 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3180 if (vp->pm_state_valid)
3181 pci_restore_state(VORTEX_PCI(vp));
3182 pci_disable_device(VORTEX_PCI(vp));
3183 }
3184 /* Should really use issue_and_wait() here */
62afe595
JL		 3185 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3186 vp->ioaddr + EL3_CMD);
3187
3188 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3189
3190 pci_free_consistent(pdev,
3191 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3192 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3193 vp->rx_ring,
3194 vp->rx_ring_dma);
3195 if (vp->must_free_region)
3196 release_region(dev->base_addr, vp->io_size);
3197 free_netdev(dev);
3198}
3199
3200
3201static struct pci_driver vortex_driver = {
3202 .name = "3c59x",
3203 .probe = vortex_init_one,
3204 .remove = __devexit_p(vortex_remove_one),
3205 .id_table = vortex_pci_tbl,
3206#ifdef CONFIG_PM
3207 .suspend = vortex_suspend,
3208 .resume = vortex_resume,
3209#endif
3210};
3211
3212
3213static int vortex_have_pci;
3214static int vortex_have_eisa;
3215
3216
a880c4cd 3217static int __init vortex_init(void)
1da177e4
LT		 3218{
3219 int pci_rc, eisa_rc;
3220
29917620 3221 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3222 eisa_rc = vortex_eisa_init();
3223
3224 if (pci_rc == 0)
3225 vortex_have_pci = 1;
3226 if (eisa_rc > 0)
3227 vortex_have_eisa = 1;
3228
3229 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3230}
3231
3232
a880c4cd 3233static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3234{
3235 struct vortex_private *vp;
62afe595 3236 void __iomem *ioaddr;
1da177e4
LT		 3237
3238#ifdef CONFIG_EISA
3239 /* Take care of the EISA devices */
a880c4cd 3240 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3241#endif
6aa20a22 3242
1da177e4 3243 if (compaq_net_device) {
454d7c9b 3244 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3245 ioaddr = ioport_map(compaq_net_device->base_addr,
3246 VORTEX_TOTAL_SIZE);
1da177e4 3247
a880c4cd
SK		 3248 unregister_netdev(compaq_net_device);
3249 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3250 release_region(compaq_net_device->base_addr,
3251 VORTEX_TOTAL_SIZE);
1da177e4 3252
a880c4cd 3253 free_netdev(compaq_net_device);
1da177e4
LT		 3254 }
3255}
3256
3257
a880c4cd 3258static void __exit vortex_cleanup(void)
1da177e4
LT		 3259{
3260 if (vortex_have_pci)
a880c4cd 3261 pci_unregister_driver(&vortex_driver);
1da177e4 3262 if (vortex_have_eisa)
a880c4cd 3263 vortex_eisa_cleanup();
1da177e4
LT		 3264}
3265
3266
3267module_init(vortex_init);
3268module_exit(vortex_cleanup);
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