]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/3c59x.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IRQ: Typedef the IRQ handler function type
[net-next-2.6.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
1da177e4
LT		 93#include <asm/irq.h> /* For NR_IRQS only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
106DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
1f1bd5fc 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
1f1bd5fc 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
541 u32 next; /* Last entry points to 0. */
542 s32 status;
543 u32 addr; /* Up to 63 addr/len pairs possible. */
544 s32 length; /* Set LAST_FRAG to indicate last pair. */
545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
561 u32 next; /* Last entry points to 0. */
562 s32 status; /* bits 0:12 length, others see below. */
563#if DO_ZEROCOPY
564 struct {
565 u32 addr;
566 s32 length;
567 } frag[1+MAX_SKB_FRAGS];
568#else
569 u32 addr;
570 s32 length;
571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
62afe595
JL		 610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 623 full_duplex:1, autoselect:1,
1da177e4
LT		 624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647};
648
649#ifdef CONFIG_PCI
650#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651#else
652#define DEVICE_PCI(dev) NULL
653#endif
654
655#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657#ifdef CONFIG_EISA
658#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659#else
660#define DEVICE_EISA(dev) NULL
661#endif
662
663#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665/* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671};
672
f71e1309 673static const struct media_table {
1da177e4
LT		 674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679} media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691};
692
693static struct {
694 const char str[ETH_GSTRING_LEN];
695} ethtool_stats_keys[] = {
696 { "tx_deferred" },
8d1d0340 697 { "tx_max_collisions" },
1da177e4 698 { "tx_multiple_collisions" },
8d1d0340 699 { "tx_single_collisions" },
1da177e4
LT		 700 { "rx_bad_ssd" },
701};
702
703/* number of ETHTOOL_GSTATS u64's */
8d1d0340 704#define VORTEX_NUM_STATS 5
1da177e4 705
62afe595 706static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 707 int chip_idx, int card_idx);
708static void vortex_up(struct net_device *dev);
709static void vortex_down(struct net_device *dev, int final);
710static int vortex_open(struct net_device *dev);
62afe595 711static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 712static int mdio_read(struct net_device *dev, int phy_id, int location);
713static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714static void vortex_timer(unsigned long arg);
715static void rx_oom_timer(unsigned long arg);
716static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718static int vortex_rx(struct net_device *dev);
719static int boomerang_rx(struct net_device *dev);
720static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
721static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
722static int vortex_close(struct net_device *dev);
723static void dump_tx_ring(struct net_device *dev);
62afe595 724static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 725static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726static void set_rx_mode(struct net_device *dev);
727#ifdef CONFIG_PCI
728static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729#endif
730static void vortex_tx_timeout(struct net_device *dev);
731static void acpi_set_WOL(struct net_device *dev);
7282d491 732static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 733static void set_8021q_mode(struct net_device *dev, int enable);
734
1da177e4
LT		 735/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736/* Option count limit only -- unlimited interfaces are supported. */
737#define MAX_UNITS 8
9954ab7f
JL		 738static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 743static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 744static int global_options = -1;
745static int global_full_duplex = -1;
746static int global_enable_wol = -1;
900fd17d 747static int global_use_mmio = -1;
1da177e4 748
1da177e4
LT		 749/* Variables to work-around the Compaq PCI BIOS32 problem. */
750static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751static struct net_device *compaq_net_device;
752
753static int vortex_cards_found;
754
755module_param(debug, int, 0);
756module_param(global_options, int, 0);
757module_param_array(options, int, NULL, 0);
758module_param(global_full_duplex, int, 0);
759module_param_array(full_duplex, int, NULL, 0);
760module_param_array(hw_checksums, int, NULL, 0);
761module_param_array(flow_ctrl, int, NULL, 0);
762module_param(global_enable_wol, int, 0);
763module_param_array(enable_wol, int, NULL, 0);
764module_param(rx_copybreak, int, 0);
765module_param(max_interrupt_work, int, 0);
766module_param(compaq_ioaddr, int, 0);
767module_param(compaq_irq, int, 0);
768module_param(compaq_device_id, int, 0);
769module_param(watchdog, int, 0);
900fd17d
JL		 770module_param(global_use_mmio, int, 0);
771module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 772MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 776MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 777MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 780MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 781MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 787MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 789
790#ifdef CONFIG_NET_POLL_CONTROLLER
791static void poll_vortex(struct net_device *dev)
792{
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
795 local_save_flags(flags);
796 local_irq_disable();
797 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
798 local_irq_restore(flags);
6aa20a22 799}
1da177e4
LT		 800#endif
801
802#ifdef CONFIG_PM
803
a880c4cd 804static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 805{
806 struct net_device *dev = pci_get_drvdata(pdev);
807
808 if (dev && dev->priv) {
809 if (netif_running(dev)) {
810 netif_device_detach(dev);
811 vortex_down(dev, 1);
812 }
5b039e68
RW		 813 pci_save_state(pdev);
814 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
815 free_irq(dev->irq, dev);
816 pci_disable_device(pdev);
817 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 818 }
819 return 0;
820}
821
a880c4cd 822static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 823{
824 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 825 struct vortex_private *vp = netdev_priv(dev);
1da177e4 826
5b039e68
RW		 827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
830 pci_enable_device(pdev);
831 pci_set_master(pdev);
832 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 833 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 834 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
835 pci_disable_device(pdev);
836 return -EBUSY;
837 }
1da177e4
LT		 838 if (netif_running(dev)) {
839 vortex_up(dev);
840 netif_device_attach(dev);
841 }
842 }
843 return 0;
844}
845
846#endif /* CONFIG_PM */
847
848#ifdef CONFIG_EISA
849static struct eisa_device_id vortex_eisa_ids[] = {
850 { "TCM5920", CH_3C592 },
851 { "TCM5970", CH_3C597 },
852 { "" }
853};
07563c71 854MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 855
a880c4cd
SK		 856static int vortex_eisa_probe(struct device *device);
857static int vortex_eisa_remove(struct device *device);
1da177e4
LT		 858
859static struct eisa_driver vortex_eisa_driver = {
860 .id_table = vortex_eisa_ids,
861 .driver = {
862 .name = "3c59x",
863 .probe = vortex_eisa_probe,
864 .remove = vortex_eisa_remove
865 }
866};
867
a880c4cd 868static int vortex_eisa_probe(struct device *device)
1da177e4 869{
62afe595 870 void __iomem *ioaddr;
1da177e4
LT		 871 struct eisa_device *edev;
872
a880c4cd 873 edev = to_eisa_device(device);
1da177e4 874
62afe595 875 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 876 return -EBUSY;
877
62afe595
JL		 878 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
879
880 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 881 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 882 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 883 return -ENODEV;
884 }
885
886 vortex_cards_found++;
887
888 return 0;
889}
890
a880c4cd 891static int vortex_eisa_remove(struct device *device)
1da177e4
LT		 892{
893 struct eisa_device *edev;
894 struct net_device *dev;
895 struct vortex_private *vp;
62afe595 896 void __iomem *ioaddr;
1da177e4 897
a880c4cd
SK		 898 edev = to_eisa_device(device);
899 dev = eisa_get_drvdata(edev);
1da177e4
LT		 900
901 if (!dev) {
902 printk("vortex_eisa_remove called for Compaq device!\n");
903 BUG();
904 }
905
906 vp = netdev_priv(dev);
62afe595 907 ioaddr = vp->ioaddr;
6aa20a22 908
a880c4cd
SK		 909 unregister_netdev(dev);
910 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
911 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 912
a880c4cd 913 free_netdev(dev);
1da177e4
LT		 914 return 0;
915}
916#endif
917
918/* returns count found (>= 0), or negative on error */
a880c4cd 919static int __init vortex_eisa_init(void)
1da177e4
LT		 920{
921 int eisa_found = 0;
922 int orig_cards_found = vortex_cards_found;
923
924#ifdef CONFIG_EISA
c2f6fabb
BH		 925 int err;
926
927 err = eisa_driver_register (&vortex_eisa_driver);
928 if (!err) {
929 /*
930 * Because of the way EISA bus is probed, we cannot assume
931 * any device have been found when we exit from
932 * eisa_driver_register (the bus root driver may not be
933 * initialized yet). So we blindly assume something was
934 * found, and let the sysfs magic happend...
935 */
936 eisa_found = 1;
1da177e4
LT		 937 }
938#endif
6aa20a22 939
1da177e4
LT		 940 /* Special code to work-around the Compaq PCI BIOS32 problem. */
941 if (compaq_ioaddr) {
62afe595
JL		 942 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
943 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 944 }
945
946 return vortex_cards_found - orig_cards_found + eisa_found;
947}
948
949/* returns count (>= 0), or negative on error */
a880c4cd 950static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 951 const struct pci_device_id *ent)
952{
900fd17d
JL		 953 int rc, unit, pci_bar;
954 struct vortex_chip_info *vci;
955 void __iomem *ioaddr;
1da177e4 956
6aa20a22 957 /* wake up and enable device */
a880c4cd 958 rc = pci_enable_device(pdev);
1da177e4
LT		 959 if (rc < 0)
960 goto out;
961
900fd17d
JL		 962 unit = vortex_cards_found;
963
964 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
965 /* Determine the default if the user didn't override us */
966 vci = &vortex_info_tbl[ent->driver_data];
967 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
968 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
969 pci_bar = use_mmio[unit] ? 1 : 0;
970 else
971 pci_bar = global_use_mmio ? 1 : 0;
972
973 ioaddr = pci_iomap(pdev, pci_bar, 0);
974 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
975 ioaddr = pci_iomap(pdev, 0, 0);
976
977 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
978 ent->driver_data, unit);
1da177e4 979 if (rc < 0) {
a880c4cd 980 pci_disable_device(pdev);
1da177e4
LT		 981 goto out;
982 }
983
984 vortex_cards_found++;
985
986out:
987 return rc;
988}
989
990/*
991 * Start up the PCI/EISA device which is described by *gendev.
992 * Return 0 on success.
993 *
994 * NOTE: pdev can be NULL, for the case of a Compaq device
995 */
996static int __devinit vortex_probe1(struct device *gendev,
62afe595 997 void __iomem *ioaddr, int irq,
1da177e4
LT		 998 int chip_idx, int card_idx)
999{
1000 struct vortex_private *vp;
1001 int option;
1002 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1003 int i, step;
1004 struct net_device *dev;
1005 static int printed_version;
1006 int retval, print_info;
1007 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1008 char *print_name = "3c59x";
1009 struct pci_dev *pdev = NULL;
1010 struct eisa_device *edev = NULL;
1011
1012 if (!printed_version) {
1013 printk (version);
1014 printed_version = 1;
1015 }
1016
1017 if (gendev) {
1018 if ((pdev = DEVICE_PCI(gendev))) {
1019 print_name = pci_name(pdev);
1020 }
1021
1022 if ((edev = DEVICE_EISA(gendev))) {
1023 print_name = edev->dev.bus_id;
1024 }
1025 }
1026
1027 dev = alloc_etherdev(sizeof(*vp));
1028 retval = -ENOMEM;
1029 if (!dev) {
1030 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1031 goto out;
1032 }
1033 SET_MODULE_OWNER(dev);
1034 SET_NETDEV_DEV(dev, gendev);
1035 vp = netdev_priv(dev);
1036
1037 option = global_options;
1038
1039 /* The lower four bits are the media type. */
1040 if (dev->mem_start) {
1041 /*
1042 * The 'options' param is passed in as the third arg to the
1043 * LILO 'ether=' argument for non-modular use
1044 */
1045 option = dev->mem_start;
1046 }
1047 else if (card_idx < MAX_UNITS) {
1048 if (options[card_idx] >= 0)
1049 option = options[card_idx];
1050 }
1051
1052 if (option > 0) {
1053 if (option & 0x8000)
1054 vortex_debug = 7;
1055 if (option & 0x4000)
1056 vortex_debug = 2;
1057 if (option & 0x0400)
1058 vp->enable_wol = 1;
1059 }
1060
1061 print_info = (vortex_debug > 1);
1062 if (print_info)
1063 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1064
61238602 1065 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1066 print_name,
1067 pdev ? "PCI" : "EISA",
1068 vci->name,
1069 ioaddr);
1070
62afe595 1071 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1072 dev->irq = irq;
1073 dev->mtu = mtu;
62afe595 1074 vp->ioaddr = ioaddr;
1da177e4
LT		 1075 vp->large_frames = mtu > 1500;
1076 vp->drv_flags = vci->drv_flags;
1077 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1078 vp->io_size = vci->io_size;
1079 vp->card_idx = card_idx;
1080
1081 /* module list only for Compaq device */
1082 if (gendev == NULL) {
1083 compaq_net_device = dev;
1084 }
1085
1086 /* PCI-only startup logic */
1087 if (pdev) {
1088 /* EISA resources already marked, so only PCI needs to do this here */
1089 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1090 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1091 vp->must_free_region = 1;
1092
6aa20a22 1093 /* enable bus-mastering if necessary */
1da177e4 1094 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1095 pci_set_master(pdev);
1da177e4
LT		 1096
1097 if (vci->drv_flags & IS_VORTEX) {
1098 u8 pci_latency;
1099 u8 new_latency = 248;
1100
1101 /* Check the PCI latency value. On the 3c590 series the latency timer
1102 must be set to the maximum value to avoid data corruption that occurs
1103 when the timer expires during a transfer. This bug exists the Vortex
1104 chip only. */
1105 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1106 if (pci_latency < new_latency) {
1107 printk(KERN_INFO "%s: Overriding PCI latency"
1108 " timer (CFLT) setting of %d, new value is %d.\n",
1109 print_name, pci_latency, new_latency);
1110 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1111 }
1112 }
1113 }
1114
1115 spin_lock_init(&vp->lock);
1116 vp->gendev = gendev;
1117 vp->mii.dev = dev;
1118 vp->mii.mdio_read = mdio_read;
1119 vp->mii.mdio_write = mdio_write;
1120 vp->mii.phy_id_mask = 0x1f;
1121 vp->mii.reg_num_mask = 0x1f;
1122
1123 /* Makes sure rings are at least 16 byte aligned. */
1124 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1125 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1126 &vp->rx_ring_dma);
1127 retval = -ENOMEM;
1128 if (vp->rx_ring == 0)
1129 goto free_region;
1130
1131 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1132 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1133
1134 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1135 * instead of a module list */
1da177e4
LT		 1136 if (pdev)
1137 pci_set_drvdata(pdev, dev);
1138 if (edev)
a880c4cd 1139 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1140
1141 vp->media_override = 7;
1142 if (option >= 0) {
1143 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1144 if (vp->media_override != 7)
1145 vp->medialock = 1;
1146 vp->full_duplex = (option & 0x200) ? 1 : 0;
1147 vp->bus_master = (option & 16) ? 1 : 0;
1148 }
1149
1150 if (global_full_duplex > 0)
1151 vp->full_duplex = 1;
1152 if (global_enable_wol > 0)
1153 vp->enable_wol = 1;
1154
1155 if (card_idx < MAX_UNITS) {
1156 if (full_duplex[card_idx] > 0)
1157 vp->full_duplex = 1;
1158 if (flow_ctrl[card_idx] > 0)
1159 vp->flow_ctrl = 1;
1160 if (enable_wol[card_idx] > 0)
1161 vp->enable_wol = 1;
1162 }
1163
125d5ce8 1164 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1165 vp->options = option;
1166 /* Read the station address from the EEPROM. */
1167 EL3WINDOW(0);
1168 {
1169 int base;
1170
1171 if (vci->drv_flags & EEPROM_8BIT)
1172 base = 0x230;
1173 else if (vci->drv_flags & EEPROM_OFFSET)
1174 base = EEPROM_Read + 0x30;
1175 else
1176 base = EEPROM_Read;
1177
1178 for (i = 0; i < 0x40; i++) {
1179 int timer;
62afe595 1180 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1181 /* Pause for at least 162 us. for the read to take place. */
1182 for (timer = 10; timer >= 0; timer--) {
1183 udelay(162);
62afe595 1184 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1185 break;
1186 }
62afe595 1187 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1188 }
1189 }
1190 for (i = 0; i < 0x18; i++)
1191 checksum ^= eeprom[i];
1192 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1193 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1194 while (i < 0x21)
1195 checksum ^= eeprom[i++];
1196 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1197 }
1198 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1199 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1200 for (i = 0; i < 3; i++)
1201 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1202 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1203 if (print_info) {
1204 for (i = 0; i < 6; i++)
1205 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1206 }
1207 /* Unfortunately an all zero eeprom passes the checksum and this
1208 gets found in the wild in failure cases. Crypto is hard 8) */
1209 if (!is_valid_ether_addr(dev->dev_addr)) {
1210 retval = -EINVAL;
1211 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1212 goto free_ring; /* With every pack */
1213 }
1214 EL3WINDOW(2);
1215 for (i = 0; i < 6; i++)
62afe595 1216 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1217
1da177e4
LT		 1218 if (print_info)
1219 printk(", IRQ %d\n", dev->irq);
1220 /* Tell them about an invalid IRQ. */
1221 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1222 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1223 dev->irq);
1da177e4
LT		 1224
1225 EL3WINDOW(4);
62afe595 1226 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1227 if (print_info) {
1228 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1229 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1230 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1231 }
1232
1233
1234 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1235 unsigned short n;
1236
62afe595
JL		 1237 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1238 if (!vp->cb_fn_base) {
1da177e4 1239 retval = -ENOMEM;
62afe595 1240 goto free_ring;
1da177e4 1241 }
62afe595 1242
1da177e4 1243 if (print_info) {
7c7459d1
GKH		 1244 printk(KERN_INFO "%s: CardBus functions mapped "
1245 "%16.16llx->%p\n",
1246 print_name,
1247 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1248 vp->cb_fn_base);
1da177e4
LT		 1249 }
1250 EL3WINDOW(2);
1251
62afe595 1252 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1253 if (vp->drv_flags & INVERT_LED_PWR)
1254 n |= 0x10;
1255 if (vp->drv_flags & INVERT_MII_PWR)
1256 n |= 0x4000;
62afe595 1257 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1258 if (vp->drv_flags & WNO_XCVR_PWR) {
1259 EL3WINDOW(0);
62afe595 1260 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1261 }
1262 }
1263
1264 /* Extract our information from the EEPROM data. */
1265 vp->info1 = eeprom[13];
1266 vp->info2 = eeprom[15];
1267 vp->capabilities = eeprom[16];
1268
1269 if (vp->info1 & 0x8000) {
1270 vp->full_duplex = 1;
1271 if (print_info)
1272 printk(KERN_INFO "Full duplex capable\n");
1273 }
1274
1275 {
f71e1309 1276 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1277 unsigned int config;
1278 EL3WINDOW(3);
62afe595 1279 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1280 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1281 vp->available_media = 0x40;
62afe595 1282 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1283 if (print_info) {
1284 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1285 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1286 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1287 8 << RAM_SIZE(config),
1288 RAM_WIDTH(config) ? "word" : "byte",
1289 ram_split[RAM_SPLIT(config)],
1290 AUTOSELECT(config) ? "autoselect/" : "",
1291 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1292 media_tbl[XCVR(config)].name);
1293 }
1294 vp->default_media = XCVR(config);
1295 if (vp->default_media == XCVR_NWAY)
1296 vp->has_nway = 1;
1297 vp->autoselect = AUTOSELECT(config);
1298 }
1299
1300 if (vp->media_override != 7) {
1301 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1302 print_name, vp->media_override,
1303 media_tbl[vp->media_override].name);
1304 dev->if_port = vp->media_override;
1305 } else
1306 dev->if_port = vp->default_media;
1307
1308 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1309 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1310 int phy, phy_idx = 0;
1311 EL3WINDOW(4);
1312 mii_preamble_required++;
1313 if (vp->drv_flags & EXTRA_PREAMBLE)
1314 mii_preamble_required++;
1315 mdio_sync(ioaddr, 32);
106427e6 1316 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1317 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1318 int mii_status, phyx;
1319
1320 /*
1321 * For the 3c905CX we look at index 24 first, because it bogusly
1322 * reports an external PHY at all indices
1323 */
1324 if (phy == 0)
1325 phyx = 24;
1326 else if (phy <= 24)
1327 phyx = phy - 1;
1328 else
1329 phyx = phy;
106427e6 1330 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1331 if (mii_status && mii_status != 0xffff) {
1332 vp->phys[phy_idx++] = phyx;
1333 if (print_info) {
1334 printk(KERN_INFO " MII transceiver found at address %d,"
1335 " status %4x.\n", phyx, mii_status);
1336 }
1337 if ((mii_status & 0x0040) == 0)
1338 mii_preamble_required++;
1339 }
1340 }
1341 mii_preamble_required--;
1342 if (phy_idx == 0) {
1343 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1344 vp->phys[0] = 24;
1345 } else {
106427e6 1346 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1347 if (vp->full_duplex) {
1348 /* Only advertise the FD media types. */
1349 vp->advertising &= ~0x02A0;
1350 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1351 }
1352 }
1353 vp->mii.phy_id = vp->phys[0];
1354 }
1355
1356 if (vp->capabilities & CapBusMaster) {
1357 vp->full_bus_master_tx = 1;
1358 if (print_info) {
1359 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1360 (vp->info2 & 1) ? "early" : "whole-frame" );
1361 }
1362 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1363 vp->bus_master = 0; /* AKPM: vortex only */
1364 }
1365
1366 /* The 3c59x-specific entries in the device structure. */
1367 dev->open = vortex_open;
1368 if (vp->full_bus_master_tx) {
1369 dev->hard_start_xmit = boomerang_start_xmit;
1370 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1371 if (card_idx < MAX_UNITS &&
1372 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1373 hw_checksums[card_idx] == 1)) {
d311b0d3 1374 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1375 }
1376 } else {
1377 dev->hard_start_xmit = vortex_start_xmit;
1378 }
1379
1380 if (print_info) {
1381 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1382 print_name,
1383 (dev->features & NETIF_F_SG) ? "en":"dis",
1384 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1385 }
1386
1387 dev->stop = vortex_close;
1388 dev->get_stats = vortex_get_stats;
1389#ifdef CONFIG_PCI
1390 dev->do_ioctl = vortex_ioctl;
1391#endif
1392 dev->ethtool_ops = &vortex_ethtool_ops;
1393 dev->set_multicast_list = set_rx_mode;
1394 dev->tx_timeout = vortex_tx_timeout;
1395 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1396#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 1397 dev->poll_controller = poll_vortex;
1da177e4
LT		 1398#endif
1399 if (pdev) {
1400 vp->pm_state_valid = 1;
1401 pci_save_state(VORTEX_PCI(vp));
1402 acpi_set_WOL(dev);
1403 }
1404 retval = register_netdev(dev);
1405 if (retval == 0)
1406 return 0;
1407
1408free_ring:
1409 pci_free_consistent(pdev,
1410 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1411 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1412 vp->rx_ring,
1413 vp->rx_ring_dma);
1414free_region:
1415 if (vp->must_free_region)
62afe595 1416 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1417 free_netdev(dev);
1418 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1419out:
1420 return retval;
1421}
1422
1423static void
1424issue_and_wait(struct net_device *dev, int cmd)
1425{
62afe595
JL		 1426 struct vortex_private *vp = netdev_priv(dev);
1427 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1428 int i;
1429
62afe595 1430 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1431 for (i = 0; i < 2000; i++) {
62afe595 1432 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1433 return;
1434 }
1435
1436 /* OK, that didn't work. Do it the slow way. One second */
1437 for (i = 0; i < 100000; i++) {
62afe595 1438 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1439 if (vortex_debug > 1)
1440 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1441 dev->name, cmd, i * 10);
1442 return;
1443 }
1444 udelay(10);
1445 }
1446 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1447 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1448}
1449
125d5ce8
SK		 1450static void
1451vortex_set_duplex(struct net_device *dev)
1452{
1453 struct vortex_private *vp = netdev_priv(dev);
1454 void __iomem *ioaddr = vp->ioaddr;
1455
1456 printk(KERN_INFO "%s: setting %s-duplex.\n",
1457 dev->name, (vp->full_duplex) ? "full" : "half");
1458
1459 EL3WINDOW(3);
1460 /* Set the full-duplex bit. */
1461 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1462 (vp->large_frames ? 0x40 : 0) |
1463 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1464 0x100 : 0),
1465 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1466}
1467
1468static void vortex_check_media(struct net_device *dev, unsigned int init)
1469{
1470 struct vortex_private *vp = netdev_priv(dev);
1471 unsigned int ok_to_print = 0;
1472
1473 if (vortex_debug > 3)
1474 ok_to_print = 1;
1475
1476 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1477 vp->full_duplex = vp->mii.full_duplex;
1478 vortex_set_duplex(dev);
1479 } else if (init) {
1480 vortex_set_duplex(dev);
1481 }
1482}
1483
1da177e4
LT		 1484static void
1485vortex_up(struct net_device *dev)
1486{
1da177e4 1487 struct vortex_private *vp = netdev_priv(dev);
62afe595 1488 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1489 unsigned int config;
09ce3512 1490 int i, mii_reg1, mii_reg5;
1da177e4
LT		 1491
1492 if (VORTEX_PCI(vp)) {
1493 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1494 if (vp->pm_state_valid)
1495 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1496 pci_enable_device(VORTEX_PCI(vp));
1497 }
1498
1499 /* Before initializing select the active media port. */
1500 EL3WINDOW(3);
62afe595 1501 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1502
1503 if (vp->media_override != 7) {
1504 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1505 dev->name, vp->media_override,
1506 media_tbl[vp->media_override].name);
1507 dev->if_port = vp->media_override;
1508 } else if (vp->autoselect) {
1509 if (vp->has_nway) {
1510 if (vortex_debug > 1)
1511 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1512 dev->name, dev->if_port);
1513 dev->if_port = XCVR_NWAY;
1514 } else {
1515 /* Find first available media type, starting with 100baseTx. */
1516 dev->if_port = XCVR_100baseTx;
1517 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1518 dev->if_port = media_tbl[dev->if_port].next;
1519 if (vortex_debug > 1)
1520 printk(KERN_INFO "%s: first available media type: %s\n",
1521 dev->name, media_tbl[dev->if_port].name);
1522 }
1523 } else {
1524 dev->if_port = vp->default_media;
1525 if (vortex_debug > 1)
1526 printk(KERN_INFO "%s: using default media %s\n",
1527 dev->name, media_tbl[dev->if_port].name);
1528 }
1529
1530 init_timer(&vp->timer);
1531 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1532 vp->timer.data = (unsigned long)dev;
1533 vp->timer.function = vortex_timer; /* timer handler */
1534 add_timer(&vp->timer);
1535
1536 init_timer(&vp->rx_oom_timer);
1537 vp->rx_oom_timer.data = (unsigned long)dev;
1538 vp->rx_oom_timer.function = rx_oom_timer;
1539
1540 if (vortex_debug > 1)
1541 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1542 dev->name, media_tbl[dev->if_port].name);
1543
125d5ce8 1544 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1545 config = BFINS(config, dev->if_port, 20, 4);
1546 if (vortex_debug > 6)
1547 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1548 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1549
1550 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1551 EL3WINDOW(4);
09ce3512
SK		 1552 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1553 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1554 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1555
125d5ce8 1556 vortex_check_media(dev, 1);
1da177e4 1557 }
125d5ce8
SK		 1558 else
1559 vortex_set_duplex(dev);
1da177e4 1560
09ce3512
SK		 1561 issue_and_wait(dev, TxReset);
1562 /*
1563 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1564 */
1565 issue_and_wait(dev, RxReset|0x04);
1566
1da177e4 1567
62afe595 1568 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1569
1570 if (vortex_debug > 1) {
1571 EL3WINDOW(4);
1572 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1573 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1574 }
1575
1576 /* Set the station address and mask in window 2 each time opened. */
1577 EL3WINDOW(2);
1578 for (i = 0; i < 6; i++)
62afe595 1579 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1580 for (; i < 12; i+=2)
62afe595 1581 iowrite16(0, ioaddr + i);
1da177e4
LT		 1582
1583 if (vp->cb_fn_base) {
62afe595 1584 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1585 if (vp->drv_flags & INVERT_LED_PWR)
1586 n |= 0x10;
1587 if (vp->drv_flags & INVERT_MII_PWR)
1588 n |= 0x4000;
62afe595 1589 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1590 }
1591
1592 if (dev->if_port == XCVR_10base2)
1593 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1594 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1595 if (dev->if_port != XCVR_NWAY) {
1596 EL3WINDOW(4);
62afe595 1597 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1598 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1599 }
1600
1601 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1602 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1603 EL3WINDOW(6);
1604 for (i = 0; i < 10; i++)
62afe595
JL		 1605 ioread8(ioaddr + i);
1606 ioread16(ioaddr + 10);
1607 ioread16(ioaddr + 12);
1da177e4
LT		 1608 /* New: On the Vortex we must also clear the BadSSD counter. */
1609 EL3WINDOW(4);
62afe595 1610 ioread8(ioaddr + 12);
1da177e4 1611 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1612 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1613
1614 /* Switch to register set 7 for normal use. */
1615 EL3WINDOW(7);
1616
1617 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1618 vp->cur_rx = vp->dirty_rx = 0;
1619 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1620 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1621 iowrite32(0x0020, ioaddr + PktStatus);
1622 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1623 }
1624 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1625 vp->cur_tx = vp->dirty_tx = 0;
1626 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1627 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1628 /* Clear the Rx, Tx rings. */
1629 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1630 vp->rx_ring[i].status = 0;
1631 for (i = 0; i < TX_RING_SIZE; i++)
1632 vp->tx_skbuff[i] = NULL;
62afe595 1633 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1634 }
1635 /* Set receiver mode: presumably accept b-case and phys addr only. */
1636 set_rx_mode(dev);
1637 /* enable 802.1q tagged frames */
1638 set_8021q_mode(dev, 1);
62afe595 1639 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1640
62afe595
JL		 1641 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1642 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1643 /* Allow status bits to be seen. */
1644 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1645 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1646 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1647 (vp->bus_master ? DMADone : 0);
1648 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1649 (vp->full_bus_master_rx ? 0 : RxComplete) |
1650 StatsFull | HostError | TxComplete | IntReq
1651 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1652 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1653 /* Ack all pending events, and set active indicator mask. */
62afe595 1654 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1655 ioaddr + EL3_CMD);
62afe595 1656 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1657 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1658 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1659 netif_start_queue (dev);
1660}
1661
1662static int
1663vortex_open(struct net_device *dev)
1664{
1665 struct vortex_private *vp = netdev_priv(dev);
1666 int i;
1667 int retval;
1668
1669 /* Use the now-standard shared IRQ implementation. */
1670 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1671 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4
LT		 1672 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1673 goto out;
1674 }
1675
1676 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1677 if (vortex_debug > 2)
1678 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1679 for (i = 0; i < RX_RING_SIZE; i++) {
1680 struct sk_buff *skb;
1681 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1682 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1683 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1684 skb = dev_alloc_skb(PKT_BUF_SZ);
1685 vp->rx_skbuff[i] = skb;
1686 if (skb == NULL)
1687 break; /* Bad news! */
1688 skb->dev = dev; /* Mark as being used by this device. */
1689 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1690 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1691 }
1692 if (i != RX_RING_SIZE) {
1693 int j;
1694 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1695 for (j = 0; j < i; j++) {
1696 if (vp->rx_skbuff[j]) {
1697 dev_kfree_skb(vp->rx_skbuff[j]);
1698 vp->rx_skbuff[j] = NULL;
1699 }
1700 }
1701 retval = -ENOMEM;
1702 goto out_free_irq;
1703 }
1704 /* Wrap the ring. */
1705 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1706 }
1707
1708 vortex_up(dev);
1709 return 0;
1710
1711out_free_irq:
1712 free_irq(dev->irq, dev);
1713out:
1714 if (vortex_debug > 1)
1715 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1716 return retval;
1717}
1718
1719static void
1720vortex_timer(unsigned long data)
1721{
1722 struct net_device *dev = (struct net_device *)data;
1723 struct vortex_private *vp = netdev_priv(dev);
62afe595 1724 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1725 int next_tick = 60*HZ;
1726 int ok = 0;
125d5ce8 1727 int media_status, old_window;
1da177e4
LT		 1728
1729 if (vortex_debug > 2) {
1730 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1731 dev->name, media_tbl[dev->if_port].name);
1732 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1733 }
1734
0a9da4bd 1735 disable_irq_lockdep(dev->irq);
62afe595 1736 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1737 EL3WINDOW(4);
62afe595 1738 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1739 switch (dev->if_port) {
1740 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1741 if (media_status & Media_LnkBeat) {
1742 netif_carrier_on(dev);
1743 ok = 1;
1744 if (vortex_debug > 1)
1745 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1746 dev->name, media_tbl[dev->if_port].name, media_status);
1747 } else {
1748 netif_carrier_off(dev);
1749 if (vortex_debug > 1) {
1750 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1751 dev->name, media_tbl[dev->if_port].name, media_status);
1752 }
1753 }
1754 break;
1755 case XCVR_MII: case XCVR_NWAY:
1756 {
1da177e4 1757 ok = 1;
125d5ce8
SK		 1758 spin_lock_bh(&vp->lock);
1759 vortex_check_media(dev, 0);
1da177e4
LT		 1760 spin_unlock_bh(&vp->lock);
1761 }
1762 break;
1763 default: /* Other media types handled by Tx timeouts. */
1764 if (vortex_debug > 1)
1765 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1766 dev->name, media_tbl[dev->if_port].name, media_status);
1767 ok = 1;
1768 }
b4ff6450
SK		 1769
1770 if (!netif_carrier_ok(dev))
1771 next_tick = 5*HZ;
1772
e94d10eb
SK		 1773 if (vp->medialock)
1774 goto leave_media_alone;
1775
a880c4cd 1776 if (!ok) {
1da177e4
LT		 1777 unsigned int config;
1778
1779 do {
1780 dev->if_port = media_tbl[dev->if_port].next;
1781 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1782 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1783 dev->if_port = vp->default_media;
1784 if (vortex_debug > 1)
1785 printk(KERN_DEBUG "%s: Media selection failing, using default "
1786 "%s port.\n",
1787 dev->name, media_tbl[dev->if_port].name);
1788 } else {
1789 if (vortex_debug > 1)
1790 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1791 "%s port.\n",
1792 dev->name, media_tbl[dev->if_port].name);
1793 next_tick = media_tbl[dev->if_port].wait;
1794 }
62afe595 1795 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1796 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1797
1798 EL3WINDOW(3);
62afe595 1799 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1800 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1801 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1802
62afe595 1803 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1804 ioaddr + EL3_CMD);
1805 if (vortex_debug > 1)
1806 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1807 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1808 }
1da177e4
LT		 1809
1810leave_media_alone:
1811 if (vortex_debug > 2)
1812 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1813 dev->name, media_tbl[dev->if_port].name);
1814
e94d10eb 1815 EL3WINDOW(old_window);
0a9da4bd 1816 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1817 mod_timer(&vp->timer, RUN_AT(next_tick));
1818 if (vp->deferred)
62afe595 1819 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1820 return;
1821}
1822
1823static void vortex_tx_timeout(struct net_device *dev)
1824{
1825 struct vortex_private *vp = netdev_priv(dev);
62afe595 1826 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1827
1828 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1829 dev->name, ioread8(ioaddr + TxStatus),
1830 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1831 EL3WINDOW(4);
1832 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1833 ioread16(ioaddr + Wn4_NetDiag),
1834 ioread16(ioaddr + Wn4_Media),
1835 ioread32(ioaddr + PktStatus),
1836 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1837 /* Slight code bloat to be user friendly. */
62afe595 1838 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1839 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1840 " network cable problem?\n", dev->name);
62afe595 1841 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1842 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1843 " IRQ blocked by another device?\n", dev->name);
1844 /* Bad idea here.. but we might as well handle a few events. */
1845 {
1846 /*
1847 * Block interrupts because vortex_interrupt does a bare spin_lock()
1848 */
1849 unsigned long flags;
1850 local_irq_save(flags);
1851 if (vp->full_bus_master_tx)
1852 boomerang_interrupt(dev->irq, dev, NULL);
1853 else
1854 vortex_interrupt(dev->irq, dev, NULL);
1855 local_irq_restore(flags);
1856 }
1857 }
1858
1859 if (vortex_debug > 0)
1860 dump_tx_ring(dev);
1861
1862 issue_and_wait(dev, TxReset);
1863
1864 vp->stats.tx_errors++;
1865 if (vp->full_bus_master_tx) {
1866 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1867 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1868 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1869 ioaddr + DownListPtr);
1870 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1871 netif_wake_queue (dev);
1872 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1873 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1874 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 1875 } else {
1876 vp->stats.tx_dropped++;
1877 netif_wake_queue(dev);
1878 }
6aa20a22 1879
1da177e4 1880 /* Issue Tx Enable */
62afe595 1881 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1882 dev->trans_start = jiffies;
6aa20a22 1883
1da177e4
LT		 1884 /* Switch to register set 7 for normal use. */
1885 EL3WINDOW(7);
1886}
1887
1888/*
1889 * Handle uncommon interrupt sources. This is a separate routine to minimize
1890 * the cache impact.
1891 */
1892static void
1893vortex_error(struct net_device *dev, int status)
1894{
1895 struct vortex_private *vp = netdev_priv(dev);
62afe595 1896 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1897 int do_tx_reset = 0, reset_mask = 0;
1898 unsigned char tx_status = 0;
1899
1900 if (vortex_debug > 2) {
1901 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1902 }
1903
1904 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1905 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1906 /* Presumably a tx-timeout. We must merely re-enable. */
1907 if (vortex_debug > 2
1908 || (tx_status != 0x88 && vortex_debug > 0)) {
1909 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1910 dev->name, tx_status);
1911 if (tx_status == 0x82) {
1912 printk(KERN_ERR "Probably a duplex mismatch. See "
1913 "Documentation/networking/vortex.txt\n");
1914 }
1915 dump_tx_ring(dev);
1916 }
1917 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1918 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
0000754c 1919 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1920 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1921 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1922 do_tx_reset = 1;
0000754c
AM		 1923 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1924 do_tx_reset = 1;
1925 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1926 } else { /* Merely re-enable the transmitter. */
62afe595 1927 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1928 }
1929 }
1930
1931 if (status & RxEarly) { /* Rx early is unused. */
1932 vortex_rx(dev);
62afe595 1933 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1934 }
1935 if (status & StatsFull) { /* Empty statistics. */
1936 static int DoneDidThat;
1937 if (vortex_debug > 4)
1938 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1939 update_stats(ioaddr, dev);
1940 /* HACK: Disable statistics as an interrupt source. */
1941 /* This occurs when we have the wrong media type! */
1942 if (DoneDidThat == 0 &&
62afe595 1943 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1944 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1945 "stats as an interrupt source.\n", dev->name);
1946 EL3WINDOW(5);
62afe595 1947 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1948 vp->intr_enable &= ~StatsFull;
1949 EL3WINDOW(7);
1950 DoneDidThat++;
1951 }
1952 }
1953 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1954 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1955 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1956 }
1957 if (status & HostError) {
1958 u16 fifo_diag;
1959 EL3WINDOW(4);
62afe595 1960 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 1961 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1962 dev->name, fifo_diag);
1963 /* Adapter failure requires Tx/Rx reset and reinit. */
1964 if (vp->full_bus_master_tx) {
62afe595 1965 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 1966 /* 0x80000000 PCI master abort. */
1967 /* 0x40000000 PCI target abort. */
1968 if (vortex_debug)
1969 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1970
1971 /* In this case, blow the card away */
1972 /* Must not enter D3 or we can't legally issue the reset! */
1973 vortex_down(dev, 0);
1974 issue_and_wait(dev, TotalReset | 0xff);
1975 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1976 } else if (fifo_diag & 0x0400)
1977 do_tx_reset = 1;
1978 if (fifo_diag & 0x3000) {
1979 /* Reset Rx fifo and upload logic */
1980 issue_and_wait(dev, RxReset|0x07);
1981 /* Set the Rx filter to the current state. */
1982 set_rx_mode(dev);
1983 /* enable 802.1q VLAN tagged frames */
1984 set_8021q_mode(dev, 1);
62afe595
JL		 1985 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1986 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 1987 }
1988 }
1989
1990 if (do_tx_reset) {
1991 issue_and_wait(dev, TxReset|reset_mask);
62afe595 1992 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1993 if (!vp->full_bus_master_tx)
1994 netif_wake_queue(dev);
1995 }
1996}
1997
1998static int
1999vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2000{
2001 struct vortex_private *vp = netdev_priv(dev);
62afe595 2002 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2003
2004 /* Put out the doubleword header... */
62afe595 2005 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2006 if (vp->bus_master) {
2007 /* Set the bus-master controller to transfer the packet. */
2008 int len = (skb->len + 3) & ~3;
a880c4cd 2009 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2010 ioaddr + Wn7_MasterAddr);
62afe595 2011 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2012 vp->tx_skb = skb;
62afe595 2013 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2014 /* netif_wake_queue() will be called at the DMADone interrupt. */
2015 } else {
2016 /* ... and the packet rounded to a doubleword. */
62afe595 2017 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2018 dev_kfree_skb (skb);
62afe595 2019 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2020 netif_start_queue (dev); /* AKPM: redundant? */
2021 } else {
2022 /* Interrupt us when the FIFO has room for max-sized packet. */
2023 netif_stop_queue(dev);
62afe595 2024 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2025 }
2026 }
2027
2028 dev->trans_start = jiffies;
2029
2030 /* Clear the Tx status stack. */
2031 {
2032 int tx_status;
2033 int i = 32;
2034
62afe595 2035 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2036 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2037 if (vortex_debug > 2)
2038 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2039 dev->name, tx_status);
2040 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2041 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2042 if (tx_status & 0x30) {
2043 issue_and_wait(dev, TxReset);
2044 }
62afe595 2045 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2046 }
62afe595 2047 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2048 }
2049 }
2050 return 0;
2051}
2052
2053static int
2054boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2055{
2056 struct vortex_private *vp = netdev_priv(dev);
62afe595 2057 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2058 /* Calculate the next Tx descriptor entry. */
2059 int entry = vp->cur_tx % TX_RING_SIZE;
2060 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2061 unsigned long flags;
2062
2063 if (vortex_debug > 6) {
2064 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2065 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2066 dev->name, vp->cur_tx);
1da177e4
LT		 2067 }
2068
2069 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2070 if (vortex_debug > 0)
2071 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2072 dev->name);
2073 netif_stop_queue(dev);
2074 return 1;
2075 }
2076
2077 vp->tx_skbuff[entry] = skb;
2078
2079 vp->tx_ring[entry].next = 0;
2080#if DO_ZEROCOPY
84fa7933 2081 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2082 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2083 else
2084 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2085
2086 if (!skb_shinfo(skb)->nr_frags) {
2087 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2088 skb->len, PCI_DMA_TODEVICE));
2089 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2090 } else {
2091 int i;
2092
2093 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2094 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2095 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2096
2097 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2098 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2099
2100 vp->tx_ring[entry].frag[i+1].addr =
2101 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2102 (void*)page_address(frag->page) + frag->page_offset,
2103 frag->size, PCI_DMA_TODEVICE));
2104
2105 if (i == skb_shinfo(skb)->nr_frags-1)
2106 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2107 else
2108 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2109 }
2110 }
2111#else
2112 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2113 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2114 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2115#endif
2116
2117 spin_lock_irqsave(&vp->lock, flags);
2118 /* Wait for the stall to complete. */
2119 issue_and_wait(dev, DownStall);
2120 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2121 if (ioread32(ioaddr + DownListPtr) == 0) {
2122 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2123 vp->queued_packet++;
2124 }
2125
2126 vp->cur_tx++;
2127 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2128 netif_stop_queue (dev);
2129 } else { /* Clear previous interrupt enable. */
2130#if defined(tx_interrupt_mitigation)
2131 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2132 * were selected, this would corrupt DN_COMPLETE. No?
2133 */
2134 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2135#endif
2136 }
62afe595 2137 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2138 spin_unlock_irqrestore(&vp->lock, flags);
2139 dev->trans_start = jiffies;
2140 return 0;
2141}
2142
2143/* The interrupt handler does all of the Rx thread work and cleans up
2144 after the Tx thread. */
2145
2146/*
2147 * This is the ISR for the vortex series chips.
2148 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2149 */
2150
2151static irqreturn_t
2152vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2153{
2154 struct net_device *dev = dev_id;
2155 struct vortex_private *vp = netdev_priv(dev);
62afe595 2156 void __iomem *ioaddr;
1da177e4
LT		 2157 int status;
2158 int work_done = max_interrupt_work;
2159 int handled = 0;
2160
62afe595 2161 ioaddr = vp->ioaddr;
1da177e4
LT		 2162 spin_lock(&vp->lock);
2163
62afe595 2164 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2165
2166 if (vortex_debug > 6)
2167 printk("vortex_interrupt(). status=0x%4x\n", status);
2168
2169 if ((status & IntLatch) == 0)
2170 goto handler_exit; /* No interrupt: shared IRQs cause this */
2171 handled = 1;
2172
2173 if (status & IntReq) {
2174 status |= vp->deferred;
2175 vp->deferred = 0;
2176 }
2177
2178 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2179 goto handler_exit;
2180
2181 if (vortex_debug > 4)
2182 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2183 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2184
2185 do {
2186 if (vortex_debug > 5)
2187 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2188 dev->name, status);
2189 if (status & RxComplete)
2190 vortex_rx(dev);
2191
2192 if (status & TxAvailable) {
2193 if (vortex_debug > 5)
2194 printk(KERN_DEBUG " TX room bit was handled.\n");
2195 /* There's room in the FIFO for a full-sized packet. */
62afe595 2196 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2197 netif_wake_queue (dev);
2198 }
2199
2200 if (status & DMADone) {
62afe595
JL		 2201 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2202 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2203 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2204 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2205 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2206 /*
2207 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2208 * insufficient FIFO room, the TxAvailable test will succeed and call
2209 * netif_wake_queue()
2210 */
2211 netif_wake_queue(dev);
2212 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2213 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2214 netif_stop_queue(dev);
2215 }
2216 }
2217 }
2218 /* Check for all uncommon interrupts at once. */
2219 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2220 if (status == 0xffff)
2221 break;
2222 vortex_error(dev, status);
2223 }
2224
2225 if (--work_done < 0) {
2226 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2227 "%4.4x.\n", dev->name, status);
2228 /* Disable all pending interrupts. */
2229 do {
2230 vp->deferred |= status;
62afe595 2231 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2232 ioaddr + EL3_CMD);
62afe595
JL		 2233 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2234 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2235 /* The timer will reenable interrupts. */
2236 mod_timer(&vp->timer, jiffies + 1*HZ);
2237 break;
2238 }
2239 /* Acknowledge the IRQ. */
62afe595
JL		 2240 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2241 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2242
2243 if (vortex_debug > 4)
2244 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2245 dev->name, status);
2246handler_exit:
2247 spin_unlock(&vp->lock);
2248 return IRQ_RETVAL(handled);
2249}
2250
2251/*
2252 * This is the ISR for the boomerang series chips.
2253 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2254 */
2255
2256static irqreturn_t
2257boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2258{
2259 struct net_device *dev = dev_id;
2260 struct vortex_private *vp = netdev_priv(dev);
62afe595 2261 void __iomem *ioaddr;
1da177e4
LT		 2262 int status;
2263 int work_done = max_interrupt_work;
2264
62afe595 2265 ioaddr = vp->ioaddr;
1da177e4
LT		 2266
2267 /*
2268 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2269 * and boomerang_start_xmit
2270 */
2271 spin_lock(&vp->lock);
2272
62afe595 2273 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2274
2275 if (vortex_debug > 6)
2276 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2277
2278 if ((status & IntLatch) == 0)
2279 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2280
2281 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2282 if (vortex_debug > 1)
2283 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2284 goto handler_exit;
2285 }
2286
2287 if (status & IntReq) {
2288 status |= vp->deferred;
2289 vp->deferred = 0;
2290 }
2291
2292 if (vortex_debug > 4)
2293 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2294 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2295 do {
2296 if (vortex_debug > 5)
2297 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2298 dev->name, status);
2299 if (status & UpComplete) {
62afe595 2300 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2301 if (vortex_debug > 5)
2302 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2303 boomerang_rx(dev);
2304 }
2305
2306 if (status & DownComplete) {
2307 unsigned int dirty_tx = vp->dirty_tx;
2308
62afe595 2309 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2310 while (vp->cur_tx - dirty_tx > 0) {
2311 int entry = dirty_tx % TX_RING_SIZE;
2312#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2313 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2314 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2315 break; /* It still hasn't been processed. */
2316#else
2317 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2318 break; /* It still hasn't been processed. */
2319#endif
6aa20a22 2320
1da177e4
LT		 2321 if (vp->tx_skbuff[entry]) {
2322 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2323#if DO_ZEROCOPY
1da177e4
LT		 2324 int i;
2325 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2326 pci_unmap_single(VORTEX_PCI(vp),
2327 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2328 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2329 PCI_DMA_TODEVICE);
2330#else
2331 pci_unmap_single(VORTEX_PCI(vp),
2332 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2333#endif
2334 dev_kfree_skb_irq(skb);
2335 vp->tx_skbuff[entry] = NULL;
2336 } else {
2337 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2338 }
2339 /* vp->stats.tx_packets++; Counted below. */
2340 dirty_tx++;
2341 }
2342 vp->dirty_tx = dirty_tx;
2343 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2344 if (vortex_debug > 6)
2345 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2346 netif_wake_queue (dev);
2347 }
2348 }
2349
2350 /* Check for all uncommon interrupts at once. */
2351 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2352 vortex_error(dev, status);
2353
2354 if (--work_done < 0) {
2355 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2356 "%4.4x.\n", dev->name, status);
2357 /* Disable all pending interrupts. */
2358 do {
2359 vp->deferred |= status;
62afe595 2360 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2361 ioaddr + EL3_CMD);
62afe595
JL		 2362 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2363 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2364 /* The timer will reenable interrupts. */
2365 mod_timer(&vp->timer, jiffies + 1*HZ);
2366 break;
2367 }
2368 /* Acknowledge the IRQ. */
62afe595 2369 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2370 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2371 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2372
62afe595 2373 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2374
2375 if (vortex_debug > 4)
2376 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2377 dev->name, status);
2378handler_exit:
2379 spin_unlock(&vp->lock);
2380 return IRQ_HANDLED;
2381}
2382
2383static int vortex_rx(struct net_device *dev)
2384{
2385 struct vortex_private *vp = netdev_priv(dev);
62afe595 2386 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2387 int i;
2388 short rx_status;
2389
2390 if (vortex_debug > 5)
2391 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2392 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2393 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2394 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2395 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2396 if (vortex_debug > 2)
2397 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2398 vp->stats.rx_errors++;
2399 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2400 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2401 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2402 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2403 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2404 } else {
2405 /* The packet length: up to 4.5K!. */
2406 int pkt_len = rx_status & 0x1fff;
2407 struct sk_buff *skb;
2408
2409 skb = dev_alloc_skb(pkt_len + 5);
2410 if (vortex_debug > 4)
2411 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2412 pkt_len, rx_status);
2413 if (skb != NULL) {
2414 skb->dev = dev;
2415 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2416 /* 'skb_put()' points to the start of sk_buff data area. */
2417 if (vp->bus_master &&
62afe595 2418 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2419 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2420 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2421 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2422 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2423 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2424 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2425 ;
2426 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2427 } else {
62afe595
JL		 2428 ioread32_rep(ioaddr + RX_FIFO,
2429 skb_put(skb, pkt_len),
2430 (pkt_len + 3) >> 2);
1da177e4 2431 }
62afe595 2432 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2433 skb->protocol = eth_type_trans(skb, dev);
2434 netif_rx(skb);
2435 dev->last_rx = jiffies;
2436 vp->stats.rx_packets++;
2437 /* Wait a limited time to go to next packet. */
2438 for (i = 200; i >= 0; i--)
62afe595 2439 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2440 break;
2441 continue;
2442 } else if (vortex_debug > 0)
2443 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2444 "size %d.\n", dev->name, pkt_len);
35b30674 2445 vp->stats.rx_dropped++;
1da177e4 2446 }
1da177e4
LT		 2447 issue_and_wait(dev, RxDiscard);
2448 }
2449
2450 return 0;
2451}
2452
2453static int
2454boomerang_rx(struct net_device *dev)
2455{
2456 struct vortex_private *vp = netdev_priv(dev);
2457 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2458 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2459 int rx_status;
2460 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2461
2462 if (vortex_debug > 5)
62afe595 2463 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2464
2465 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2466 if (--rx_work_limit < 0)
2467 break;
2468 if (rx_status & RxDError) { /* Error, update stats. */
2469 unsigned char rx_error = rx_status >> 16;
2470 if (vortex_debug > 2)
2471 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2472 vp->stats.rx_errors++;
2473 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2474 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2475 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2476 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2477 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2478 } else {
2479 /* The packet length: up to 4.5K!. */
2480 int pkt_len = rx_status & 0x1fff;
2481 struct sk_buff *skb;
2482 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2483
2484 if (vortex_debug > 4)
2485 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2486 pkt_len, rx_status);
2487
2488 /* Check if the packet is long enough to just accept without
2489 copying to a properly sized skbuff. */
2490 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2491 skb->dev = dev;
2492 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2493 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2494 /* 'skb_put()' points to the start of sk_buff data area. */
2495 memcpy(skb_put(skb, pkt_len),
689be439 2496 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2497 pkt_len);
2498 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2499 vp->rx_copy++;
2500 } else {
2501 /* Pass up the skbuff already on the Rx ring. */
2502 skb = vp->rx_skbuff[entry];
2503 vp->rx_skbuff[entry] = NULL;
2504 skb_put(skb, pkt_len);
2505 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2506 vp->rx_nocopy++;
2507 }
2508 skb->protocol = eth_type_trans(skb, dev);
2509 { /* Use hardware checksum info. */
2510 int csum_bits = rx_status & 0xee000000;
2511 if (csum_bits &&
2512 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2513 csum_bits == (IPChksumValid | UDPChksumValid))) {
2514 skb->ip_summed = CHECKSUM_UNNECESSARY;
2515 vp->rx_csumhits++;
2516 }
2517 }
2518 netif_rx(skb);
2519 dev->last_rx = jiffies;
2520 vp->stats.rx_packets++;
2521 }
2522 entry = (++vp->cur_rx) % RX_RING_SIZE;
2523 }
2524 /* Refill the Rx ring buffers. */
2525 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2526 struct sk_buff *skb;
2527 entry = vp->dirty_rx % RX_RING_SIZE;
2528 if (vp->rx_skbuff[entry] == NULL) {
2529 skb = dev_alloc_skb(PKT_BUF_SZ);
2530 if (skb == NULL) {
2531 static unsigned long last_jif;
ff5688ae 2532 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2533 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2534 last_jif = jiffies;
2535 }
2536 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2537 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2538 break; /* Bad news! */
2539 }
2540 skb->dev = dev; /* Mark as being used by this device. */
2541 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2542 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2543 vp->rx_skbuff[entry] = skb;
2544 }
2545 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2546 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2547 }
2548 return 0;
2549}
2550
2551/*
2552 * If we've hit a total OOM refilling the Rx ring we poll once a second
2553 * for some memory. Otherwise there is no way to restart the rx process.
2554 */
2555static void
2556rx_oom_timer(unsigned long arg)
2557{
2558 struct net_device *dev = (struct net_device *)arg;
2559 struct vortex_private *vp = netdev_priv(dev);
2560
2561 spin_lock_irq(&vp->lock);
2562 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2563 boomerang_rx(dev);
2564 if (vortex_debug > 1) {
2565 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2566 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2567 }
2568 spin_unlock_irq(&vp->lock);
2569}
2570
2571static void
2572vortex_down(struct net_device *dev, int final_down)
2573{
2574 struct vortex_private *vp = netdev_priv(dev);
62afe595 2575 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2576
2577 netif_stop_queue (dev);
2578
2579 del_timer_sync(&vp->rx_oom_timer);
2580 del_timer_sync(&vp->timer);
2581
2582 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2583 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2584
2585 /* Disable the receiver and transmitter. */
62afe595
JL		 2586 iowrite16(RxDisable, ioaddr + EL3_CMD);
2587 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2588
2589 /* Disable receiving 802.1q tagged frames */
2590 set_8021q_mode(dev, 0);
2591
2592 if (dev->if_port == XCVR_10base2)
2593 /* Turn off thinnet power. Green! */
62afe595 2594 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2595
62afe595 2596 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2597
2598 update_stats(ioaddr, dev);
2599 if (vp->full_bus_master_rx)
62afe595 2600 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2601 if (vp->full_bus_master_tx)
62afe595 2602 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2603
2604 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2605 vp->pm_state_valid = 1;
1da177e4
LT		 2606 pci_save_state(VORTEX_PCI(vp));
2607 acpi_set_WOL(dev);
2608 }
2609}
2610
2611static int
2612vortex_close(struct net_device *dev)
2613{
2614 struct vortex_private *vp = netdev_priv(dev);
62afe595 2615 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2616 int i;
2617
2618 if (netif_device_present(dev))
2619 vortex_down(dev, 1);
2620
2621 if (vortex_debug > 1) {
2622 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2623 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2624 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2625 " tx_queued %d Rx pre-checksummed %d.\n",
2626 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2627 }
2628
2629#if DO_ZEROCOPY
32fb5f06
JL		 2630 if (vp->rx_csumhits &&
2631 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2632 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2633 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2634 "not using them!\n", dev->name);
1da177e4
LT		 2635 }
2636#endif
6aa20a22 2637
1da177e4
LT		 2638 free_irq(dev->irq, dev);
2639
2640 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2641 for (i = 0; i < RX_RING_SIZE; i++)
2642 if (vp->rx_skbuff[i]) {
2643 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2644 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2645 dev_kfree_skb(vp->rx_skbuff[i]);
2646 vp->rx_skbuff[i] = NULL;
2647 }
2648 }
2649 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2650 for (i = 0; i < TX_RING_SIZE; i++) {
2651 if (vp->tx_skbuff[i]) {
2652 struct sk_buff *skb = vp->tx_skbuff[i];
2653#if DO_ZEROCOPY
2654 int k;
2655
2656 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2657 pci_unmap_single(VORTEX_PCI(vp),
2658 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2659 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2660 PCI_DMA_TODEVICE);
2661#else
2662 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2663#endif
2664 dev_kfree_skb(skb);
2665 vp->tx_skbuff[i] = NULL;
2666 }
2667 }
2668 }
2669
2670 return 0;
2671}
2672
2673static void
2674dump_tx_ring(struct net_device *dev)
2675{
2676 if (vortex_debug > 0) {
2677 struct vortex_private *vp = netdev_priv(dev);
62afe595 2678 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2679
1da177e4
LT		 2680 if (vp->full_bus_master_tx) {
2681 int i;
62afe595 2682 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2683
2684 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2685 vp->full_bus_master_tx,
2686 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2687 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2688 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2689 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2690 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2691 issue_and_wait(dev, DownStall);
2692 for (i = 0; i < TX_RING_SIZE; i++) {
2693 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2694 &vp->tx_ring[i],
2695#if DO_ZEROCOPY
2696 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2697#else
2698 le32_to_cpu(vp->tx_ring[i].length),
2699#endif
2700 le32_to_cpu(vp->tx_ring[i].status));
2701 }
2702 if (!stalled)
62afe595 2703 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2704 }
2705 }
2706}
2707
2708static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2709{
2710 struct vortex_private *vp = netdev_priv(dev);
62afe595 2711 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2712 unsigned long flags;
2713
2714 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2715 spin_lock_irqsave (&vp->lock, flags);
62afe595 2716 update_stats(ioaddr, dev);
1da177e4
LT		 2717 spin_unlock_irqrestore (&vp->lock, flags);
2718 }
2719 return &vp->stats;
2720}
2721
2722/* Update statistics.
2723 Unlike with the EL3 we need not worry about interrupts changing
2724 the window setting from underneath us, but we must still guard
2725 against a race condition with a StatsUpdate interrupt updating the
2726 table. This is done by checking that the ASM (!) code generated uses
2727 atomic updates with '+='.
2728 */
62afe595 2729static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2730{
2731 struct vortex_private *vp = netdev_priv(dev);
62afe595 2732 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2733
2734 if (old_window == 0xffff) /* Chip suspended or ejected. */
2735 return;
2736 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2737 /* Switch to the stats window, and read everything. */
2738 EL3WINDOW(6);
62afe595
JL		 2739 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2740 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2741 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2742 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2743 vp->stats.tx_packets += ioread8(ioaddr + 6);
2744 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2745 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2746 /* Don't bother with register 9, an extension of registers 6&7.
2747 If we do use the 6&7 values the atomic update assumption above
2748 is invalid. */
62afe595
JL		 2749 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2750 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2751 /* Extra stats for get_ethtool_stats() */
62afe595 2752 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2753 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2754 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2755 EL3WINDOW(4);
62afe595 2756 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2757
8d1d0340
SK		 2758 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2759 + vp->xstats.tx_single_collisions
2760 + vp->xstats.tx_max_collisions;
2761
1da177e4 2762 {
62afe595 2763 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2764 vp->stats.rx_bytes += (up & 0x0f) << 16;
2765 vp->stats.tx_bytes += (up & 0xf0) << 12;
2766 }
2767
2768 EL3WINDOW(old_window >> 13);
2769 return;
2770}
2771
2772static int vortex_nway_reset(struct net_device *dev)
2773{
2774 struct vortex_private *vp = netdev_priv(dev);
62afe595 2775 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2776 unsigned long flags;
2777 int rc;
2778
2779 spin_lock_irqsave(&vp->lock, flags);
2780 EL3WINDOW(4);
2781 rc = mii_nway_restart(&vp->mii);
2782 spin_unlock_irqrestore(&vp->lock, flags);
2783 return rc;
2784}
2785
1da177e4
LT		 2786static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2787{
2788 struct vortex_private *vp = netdev_priv(dev);
62afe595 2789 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2790 unsigned long flags;
2791 int rc;
2792
2793 spin_lock_irqsave(&vp->lock, flags);
2794 EL3WINDOW(4);
2795 rc = mii_ethtool_gset(&vp->mii, cmd);
2796 spin_unlock_irqrestore(&vp->lock, flags);
2797 return rc;
2798}
2799
2800static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2801{
2802 struct vortex_private *vp = netdev_priv(dev);
62afe595 2803 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2804 unsigned long flags;
2805 int rc;
2806
2807 spin_lock_irqsave(&vp->lock, flags);
2808 EL3WINDOW(4);
2809 rc = mii_ethtool_sset(&vp->mii, cmd);
2810 spin_unlock_irqrestore(&vp->lock, flags);
2811 return rc;
2812}
2813
2814static u32 vortex_get_msglevel(struct net_device *dev)
2815{
2816 return vortex_debug;
2817}
2818
2819static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2820{
2821 vortex_debug = dbg;
2822}
2823
2824static int vortex_get_stats_count(struct net_device *dev)
2825{
2826 return VORTEX_NUM_STATS;
2827}
2828
2829static void vortex_get_ethtool_stats(struct net_device *dev,
2830 struct ethtool_stats *stats, u64 *data)
2831{
2832 struct vortex_private *vp = netdev_priv(dev);
62afe595 2833 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2834 unsigned long flags;
2835
2836 spin_lock_irqsave(&vp->lock, flags);
62afe595 2837 update_stats(ioaddr, dev);
1da177e4
LT		 2838 spin_unlock_irqrestore(&vp->lock, flags);
2839
2840 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2841 data[1] = vp->xstats.tx_max_collisions;
2842 data[2] = vp->xstats.tx_multiple_collisions;
2843 data[3] = vp->xstats.tx_single_collisions;
2844 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2845}
2846
2847
2848static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2849{
2850 switch (stringset) {
2851 case ETH_SS_STATS:
2852 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2853 break;
2854 default:
2855 WARN_ON(1);
2856 break;
2857 }
2858}
2859
2860static void vortex_get_drvinfo(struct net_device *dev,
2861 struct ethtool_drvinfo *info)
2862{
2863 struct vortex_private *vp = netdev_priv(dev);
2864
2865 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2866 if (VORTEX_PCI(vp)) {
2867 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2868 } else {
2869 if (VORTEX_EISA(vp))
2870 sprintf(info->bus_info, vp->gendev->bus_id);
2871 else
2872 sprintf(info->bus_info, "EISA 0x%lx %d",
2873 dev->base_addr, dev->irq);
2874 }
2875}
2876
7282d491 2877static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2878 .get_drvinfo = vortex_get_drvinfo,
2879 .get_strings = vortex_get_strings,
2880 .get_msglevel = vortex_get_msglevel,
2881 .set_msglevel = vortex_set_msglevel,
2882 .get_ethtool_stats = vortex_get_ethtool_stats,
2883 .get_stats_count = vortex_get_stats_count,
2884 .get_settings = vortex_get_settings,
2885 .set_settings = vortex_set_settings,
373a6887 2886 .get_link = ethtool_op_get_link,
1da177e4 2887 .nway_reset = vortex_nway_reset,
a880c4cd 2888 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 2889};
2890
2891#ifdef CONFIG_PCI
2892/*
2893 * Must power the device up to do MDIO operations
2894 */
2895static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2896{
2897 int err;
2898 struct vortex_private *vp = netdev_priv(dev);
62afe595 2899 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2900 unsigned long flags;
2901 int state = 0;
2902
2903 if(VORTEX_PCI(vp))
2904 state = VORTEX_PCI(vp)->current_state;
2905
2906 /* The kernel core really should have pci_get_power_state() */
2907
2908 if(state != 0)
2909 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2910 spin_lock_irqsave(&vp->lock, flags);
2911 EL3WINDOW(4);
2912 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2913 spin_unlock_irqrestore(&vp->lock, flags);
2914 if(state != 0)
2915 pci_set_power_state(VORTEX_PCI(vp), state);
2916
2917 return err;
2918}
2919#endif
2920
2921
2922/* Pre-Cyclone chips have no documented multicast filter, so the only
2923 multicast setting is to receive all multicast frames. At least
2924 the chip has a very clean way to set the mode, unlike many others. */
2925static void set_rx_mode(struct net_device *dev)
2926{
62afe595
JL		 2927 struct vortex_private *vp = netdev_priv(dev);
2928 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2929 int new_mode;
2930
2931 if (dev->flags & IFF_PROMISC) {
d5b20697 2932 if (vortex_debug > 3)
1da177e4
LT		 2933 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2934 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2935 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2936 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2937 } else
2938 new_mode = SetRxFilter | RxStation | RxBroadcast;
2939
62afe595 2940 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2941}
2942
2943#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2944/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2945 Note that this must be done after each RxReset due to some backwards
2946 compatibility logic in the Cyclone and Tornado ASICs */
2947
2948/* The Ethernet Type used for 802.1q tagged frames */
2949#define VLAN_ETHER_TYPE 0x8100
2950
2951static void set_8021q_mode(struct net_device *dev, int enable)
2952{
2953 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2954 void __iomem *ioaddr = vp->ioaddr;
2955 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2956 int mac_ctrl;
2957
2958 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2959 /* cyclone and tornado chipsets can recognize 802.1q
2960 * tagged frames and treat them correctly */
2961
2962 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2963 if (enable)
2964 max_pkt_size += 4; /* 802.1Q VLAN tag */
2965
2966 EL3WINDOW(3);
62afe595 2967 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 2968
2969 /* set VlanEtherType to let the hardware checksumming
2970 treat tagged frames correctly */
2971 EL3WINDOW(7);
62afe595 2972 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 2973 } else {
2974 /* on older cards we have to enable large frames */
2975
2976 vp->large_frames = dev->mtu > 1500 || enable;
2977
2978 EL3WINDOW(3);
62afe595 2979 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2980 if (vp->large_frames)
2981 mac_ctrl |= 0x40;
2982 else
2983 mac_ctrl &= ~0x40;
62afe595 2984 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2985 }
2986
2987 EL3WINDOW(old_window);
2988}
2989#else
2990
2991static void set_8021q_mode(struct net_device *dev, int enable)
2992{
2993}
2994
2995
2996#endif
2997
2998/* MII transceiver control section.
2999 Read and write the MII registers using software-generated serial
3000 MDIO protocol. See the MII specifications or DP83840A data sheet
3001 for details. */
3002
3003/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3004 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3005 "overclocking" issues. */
62afe595 3006#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3007
3008#define MDIO_SHIFT_CLK 0x01
3009#define MDIO_DIR_WRITE 0x04
3010#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3011#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3012#define MDIO_DATA_READ 0x02
3013#define MDIO_ENB_IN 0x00
3014
3015/* Generate the preamble required for initial synchronization and
3016 a few older transceivers. */
62afe595 3017static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3018{
62afe595 3019 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3020
3021 /* Establish sync by sending at least 32 logic ones. */
3022 while (-- bits >= 0) {
62afe595 3023 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3024 mdio_delay();
62afe595 3025 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3026 mdio_delay();
3027 }
3028}
3029
3030static int mdio_read(struct net_device *dev, int phy_id, int location)
3031{
3032 int i;
62afe595
JL		 3033 struct vortex_private *vp = netdev_priv(dev);
3034 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3035 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3036 unsigned int retval = 0;
62afe595 3037 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3038
3039 if (mii_preamble_required)
3040 mdio_sync(ioaddr, 32);
3041
3042 /* Shift the read command bits out. */
3043 for (i = 14; i >= 0; i--) {
3044 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3045 iowrite16(dataval, mdio_addr);
1da177e4 3046 mdio_delay();
62afe595 3047 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3048 mdio_delay();
3049 }
3050 /* Read the two transition, 16 data, and wire-idle bits. */
3051 for (i = 19; i > 0; i--) {
62afe595 3052 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3053 mdio_delay();
62afe595
JL		 3054 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3055 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3056 mdio_delay();
3057 }
3058 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3059}
3060
3061static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3062{
62afe595
JL		 3063 struct vortex_private *vp = netdev_priv(dev);
3064 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3065 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3066 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3067 int i;
3068
3069 if (mii_preamble_required)
3070 mdio_sync(ioaddr, 32);
3071
3072 /* Shift the command bits out. */
3073 for (i = 31; i >= 0; i--) {
3074 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3075 iowrite16(dataval, mdio_addr);
1da177e4 3076 mdio_delay();
62afe595 3077 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3078 mdio_delay();
3079 }
3080 /* Leave the interface idle. */
3081 for (i = 1; i >= 0; i--) {
62afe595 3082 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3083 mdio_delay();
62afe595 3084 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3085 mdio_delay();
3086 }
3087 return;
3088}
a880c4cd 3089
1da177e4
LT		 3090/* ACPI: Advanced Configuration and Power Interface. */
3091/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3092static void acpi_set_WOL(struct net_device *dev)
3093{
3094 struct vortex_private *vp = netdev_priv(dev);
62afe595 3095 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3096
3097 if (vp->enable_wol) {
3098 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3099 EL3WINDOW(7);
62afe595 3100 iowrite16(2, ioaddr + 0x0c);
1da177e4 3101 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3102 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3103 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3104
3105 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3106
3107 /* Change the power state to D3; RxEnable doesn't take effect. */
3108 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3109 }
1da177e4
LT		 3110}
3111
3112
a880c4cd 3113static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3114{
3115 struct net_device *dev = pci_get_drvdata(pdev);
3116 struct vortex_private *vp;
3117
3118 if (!dev) {
3119 printk("vortex_remove_one called for Compaq device!\n");
3120 BUG();
3121 }
3122
3123 vp = netdev_priv(dev);
3124
62afe595
JL		 3125 if (vp->cb_fn_base)
3126 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3127
1da177e4
LT		 3128 unregister_netdev(dev);
3129
3130 if (VORTEX_PCI(vp)) {
3131 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3132 if (vp->pm_state_valid)
3133 pci_restore_state(VORTEX_PCI(vp));
3134 pci_disable_device(VORTEX_PCI(vp));
3135 }
3136 /* Should really use issue_and_wait() here */
62afe595
JL		 3137 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3138 vp->ioaddr + EL3_CMD);
3139
3140 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3141
3142 pci_free_consistent(pdev,
3143 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3144 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3145 vp->rx_ring,
3146 vp->rx_ring_dma);
3147 if (vp->must_free_region)
3148 release_region(dev->base_addr, vp->io_size);
3149 free_netdev(dev);
3150}
3151
3152
3153static struct pci_driver vortex_driver = {
3154 .name = "3c59x",
3155 .probe = vortex_init_one,
3156 .remove = __devexit_p(vortex_remove_one),
3157 .id_table = vortex_pci_tbl,
3158#ifdef CONFIG_PM
3159 .suspend = vortex_suspend,
3160 .resume = vortex_resume,
3161#endif
3162};
3163
3164
3165static int vortex_have_pci;
3166static int vortex_have_eisa;
3167
3168
a880c4cd 3169static int __init vortex_init(void)
1da177e4
LT		 3170{
3171 int pci_rc, eisa_rc;
3172
29917620 3173 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3174 eisa_rc = vortex_eisa_init();
3175
3176 if (pci_rc == 0)
3177 vortex_have_pci = 1;
3178 if (eisa_rc > 0)
3179 vortex_have_eisa = 1;
3180
3181 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3182}
3183
3184
a880c4cd 3185static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3186{
3187 struct vortex_private *vp;
62afe595 3188 void __iomem *ioaddr;
1da177e4
LT		 3189
3190#ifdef CONFIG_EISA
3191 /* Take care of the EISA devices */
a880c4cd 3192 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3193#endif
6aa20a22 3194
1da177e4
LT		 3195 if (compaq_net_device) {
3196 vp = compaq_net_device->priv;
62afe595
JL		 3197 ioaddr = ioport_map(compaq_net_device->base_addr,
3198 VORTEX_TOTAL_SIZE);
1da177e4 3199
a880c4cd
SK		 3200 unregister_netdev(compaq_net_device);
3201 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3202 release_region(compaq_net_device->base_addr,
3203 VORTEX_TOTAL_SIZE);
1da177e4 3204
a880c4cd 3205 free_netdev(compaq_net_device);
1da177e4
LT		 3206 }
3207}
3208
3209
a880c4cd 3210static void __exit vortex_cleanup(void)
1da177e4
LT		 3211{
3212 if (vortex_have_pci)
a880c4cd 3213 pci_unregister_driver(&vortex_driver);
1da177e4 3214 if (vortex_have_eisa)
a880c4cd 3215 vortex_eisa_cleanup();
1da177e4
LT		 3216}
3217
3218
3219module_init(vortex_init);
3220module_exit(vortex_cleanup);
Clone of davem's net-next-2.6 tree