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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186*/
187
188/*
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
191 *
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
195 */
196
197
198#define DRV_NAME "3c59x"
199#define DRV_VERSION "LK1.1.19"
200#define DRV_RELDATE "10 Nov 2002"
201
202
203
204/* A few values that may be tweaked. */
205/* Keep the ring sizes a power of two for efficiency. */
206#define TX_RING_SIZE 16
207#define RX_RING_SIZE 32
208#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
209
210/* "Knobs" that adjust features and parameters. */
211/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
212 Setting to > 1512 effectively disables this feature. */
213#ifndef __arm__
214static int rx_copybreak = 200;
215#else
216/* ARM systems perform better by disregarding the bus-master
217 transfer capability of these cards. -- rmk */
218static int rx_copybreak = 1513;
219#endif
220/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
221static const int mtu = 1500;
222/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
223static int max_interrupt_work = 32;
224/* Tx timeout interval (millisecs) */
225static int watchdog = 5000;
226
227/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
228 * of possible Tx stalls if the system is blocking interrupts
229 * somewhere else. Undefine this to disable.
230 */
231#define tx_interrupt_mitigation 1
232
233/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
234#define vortex_debug debug
235#ifdef VORTEX_DEBUG
236static int vortex_debug = VORTEX_DEBUG;
237#else
238static int vortex_debug = 1;
239#endif
240
241#include <linux/config.h>
242#include <linux/module.h>
243#include <linux/kernel.h>
244#include <linux/string.h>
245#include <linux/timer.h>
246#include <linux/errno.h>
247#include <linux/in.h>
248#include <linux/ioport.h>
249#include <linux/slab.h>
250#include <linux/interrupt.h>
251#include <linux/pci.h>
252#include <linux/mii.h>
253#include <linux/init.h>
254#include <linux/netdevice.h>
255#include <linux/etherdevice.h>
256#include <linux/skbuff.h>
257#include <linux/ethtool.h>
258#include <linux/highmem.h>
259#include <linux/eisa.h>
260#include <linux/bitops.h>
261#include <asm/irq.h> /* For NR_IRQS only. */
262#include <asm/io.h>
263#include <asm/uaccess.h>
264
265/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
266 This is only in the support-all-kernels source code. */
267
268#define RUN_AT(x) (jiffies + (x))
269
270#include <linux/delay.h>
271
272
273static char version[] __devinitdata =
274DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
275
276MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
277MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "
278 DRV_VERSION " " DRV_RELDATE);
279MODULE_LICENSE("GPL");
280MODULE_VERSION(DRV_VERSION);
281
282
283/* Operational parameter that usually are not changed. */
284
285/* The Vortex size is twice that of the original EtherLinkIII series: the
286 runtime register window, window 1, is now always mapped in.
287 The Boomerang size is twice as large as the Vortex -- it has additional
288 bus master control registers. */
289#define VORTEX_TOTAL_SIZE 0x20
290#define BOOMERANG_TOTAL_SIZE 0x40
291
292/* Set iff a MII transceiver on any interface requires mdio preamble.
293 This only set with the original DP83840 on older 3c905 boards, so the extra
294 code size of a per-interface flag is not worthwhile. */
295static char mii_preamble_required;
296
297#define PFX DRV_NAME ": "
298
299
300
301/*
302 Theory of Operation
303
304I. Board Compatibility
305
306This device driver is designed for the 3Com FastEtherLink and FastEtherLink
307XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
308versions of the FastEtherLink cards. The supported product IDs are
309 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
310
311The related ISA 3c515 is supported with a separate driver, 3c515.c, included
312with the kernel source or available from
313 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
314
315II. Board-specific settings
316
317PCI bus devices are configured by the system at boot time, so no jumpers
318need to be set on the board. The system BIOS should be set to assign the
319PCI INTA signal to an otherwise unused system IRQ line.
320
321The EEPROM settings for media type and forced-full-duplex are observed.
322The EEPROM media type should be left at the default "autoselect" unless using
32310base2 or AUI connections which cannot be reliably detected.
324
325III. Driver operation
326
327The 3c59x series use an interface that's very similar to the previous 3c5x9
328series. The primary interface is two programmed-I/O FIFOs, with an
329alternate single-contiguous-region bus-master transfer (see next).
330
331The 3c900 "Boomerang" series uses a full-bus-master interface with separate
332lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
333DEC Tulip and Intel Speedo3. The first chip version retains a compatible
334programmed-I/O interface that has been removed in 'B' and subsequent board
335revisions.
336
337One extension that is advertised in a very large font is that the adapters
338are capable of being bus masters. On the Vortex chip this capability was
339only for a single contiguous region making it far less useful than the full
340bus master capability. There is a significant performance impact of taking
341an extra interrupt or polling for the completion of each transfer, as well
342as difficulty sharing the single transfer engine between the transmit and
343receive threads. Using DMA transfers is a win only with large blocks or
344with the flawed versions of the Intel Orion motherboard PCI controller.
345
346The Boomerang chip's full-bus-master interface is useful, and has the
347currently-unused advantages over other similar chips that queued transmit
348packets may be reordered and receive buffer groups are associated with a
349single frame.
350
351With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
352Rather than a fixed intermediate receive buffer, this scheme allocates
353full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
354the copying breakpoint: it is chosen to trade-off the memory wasted by
355passing the full-sized skbuff to the queue layer for all frames vs. the
356copying cost of copying a frame to a correctly-sized skbuff.
357
358IIIC. Synchronization
359The driver runs as two independent, single-threaded flows of control. One
360is the send-packet routine, which enforces single-threaded use by the
361dev->tbusy flag. The other thread is the interrupt handler, which is single
362threaded by the hardware and other software.
363
364IV. Notes
365
366Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
3673c590, 3c595, and 3c900 boards.
368The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
369the EISA version is called "Demon". According to Terry these names come
370from rides at the local amusement park.
371
372The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
373This driver only supports ethernet packets because of the skbuff allocation
374limit of 4K.
375*/
376
377/* This table drives the PCI probe routines. It's mostly boilerplate in all
378 of the drivers, and will likely be provided by some future kernel.
379*/
380enum pci_flags_bit {
381 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
382 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
383};
384
385enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
386 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
387 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
388 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
389 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
390 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
391
392enum vortex_chips {
393 CH_3C590 = 0,
394 CH_3C592,
395 CH_3C597,
396 CH_3C595_1,
397 CH_3C595_2,
398
399 CH_3C595_3,
400 CH_3C900_1,
401 CH_3C900_2,
402 CH_3C900_3,
403 CH_3C900_4,
404
405 CH_3C900_5,
406 CH_3C900B_FL,
407 CH_3C905_1,
408 CH_3C905_2,
409 CH_3C905B_1,
410
411 CH_3C905B_2,
412 CH_3C905B_FX,
413 CH_3C905C,
414 CH_3C9202,
415 CH_3C980,
416 CH_3C9805,
417
418 CH_3CSOHO100_TX,
419 CH_3C555,
420 CH_3C556,
421 CH_3C556B,
422 CH_3C575,
423
424 CH_3C575_1,
425 CH_3CCFE575,
426 CH_3CCFE575CT,
427 CH_3CCFE656,
428 CH_3CCFEM656,
429
430 CH_3CCFEM656_1,
431 CH_3C450,
432 CH_3C920,
433 CH_3C982A,
434 CH_3C982B,
435
436 CH_905BT4,
437 CH_920B_EMB_WNM,
438};
439
440
441/* note: this array directly indexed by above enums, and MUST
442 * be kept in sync with both the enums above, and the PCI device
443 * table below
444 */
445static struct vortex_chip_info {
446 const char *name;
447 int flags;
448 int drv_flags;
449 int io_size;
450} vortex_info_tbl[] __devinitdata = {
451 {"3c590 Vortex 10Mbps",
452 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
453 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
454 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
455 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
456 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
457 {"3c595 Vortex 100baseTx",
458 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
459 {"3c595 Vortex 100baseT4",
460 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
461
462 {"3c595 Vortex 100base-MII",
463 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
464 {"3c900 Boomerang 10baseT",
465 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
466 {"3c900 Boomerang 10Mbps Combo",
467 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
468 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
469 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
470 {"3c900 Cyclone 10Mbps Combo",
471 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
472
473 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
474 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
475 {"3c900B-FL Cyclone 10base-FL",
476 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
477 {"3c905 Boomerang 100baseTx",
478 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
479 {"3c905 Boomerang 100baseT4",
480 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
481 {"3c905B Cyclone 100baseTx",
482 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
483
484 {"3c905B Cyclone 10/100/BNC",
485 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
486 {"3c905B-FX Cyclone 100baseFx",
487 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
488 {"3c905C Tornado",
489 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
490 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
491 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
492 {"3c980 Cyclone",
493 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
494
495 {"3c980C Python-T",
496 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
497 {"3cSOHO100-TX Hurricane",
498 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
499 {"3c555 Laptop Hurricane",
500 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
501 {"3c556 Laptop Tornado",
502 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
503 HAS_HWCKSM, 128, },
504 {"3c556B Laptop Hurricane",
505 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
506 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
507
508 {"3c575 [Megahertz] 10/100 LAN CardBus",
509 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
510 {"3c575 Boomerang CardBus",
511 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
512 {"3CCFE575BT Cyclone CardBus",
513 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
514 INVERT_LED_PWR|HAS_HWCKSM, 128, },
515 {"3CCFE575CT Tornado CardBus",
516 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
517 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
518 {"3CCFE656 Cyclone CardBus",
519 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
520 INVERT_LED_PWR|HAS_HWCKSM, 128, },
521
522 {"3CCFEM656B Cyclone+Winmodem CardBus",
523 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
524 INVERT_LED_PWR|HAS_HWCKSM, 128, },
525 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
526 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
527 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
528 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
529 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
530 {"3c920 Tornado",
531 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
532 {"3c982 Hydra Dual Port A",
533 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
534
535 {"3c982 Hydra Dual Port B",
536 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
537 {"3c905B-T4",
538 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
539 {"3c920B-EMB-WNM Tornado",
540 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
541
542 {NULL,}, /* NULL terminated list. */
543};
544
545
546static struct pci_device_id vortex_pci_tbl[] = {
547 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
548 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
549 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
550 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
551 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
552
553 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
554 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
555 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
556 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
557 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
558
559 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
560 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
561 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
562 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
563 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
564
565 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
566 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
567 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
568 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
569 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
570 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
571
572 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
573 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
574 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
575 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
576 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
577
578 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
579 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
580 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
581 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
582 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
583
584 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
585 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
586 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
587 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
588 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
589
590 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
591 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
592
593 {0,} /* 0 terminated list. */
594};
595MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
596
597
598/* Operational definitions.
599 These are not used by other compilation units and thus are not
600 exported in a ".h" file.
601
602 First the windows. There are eight register windows, with the command
603 and status registers available in each.
604 */
605#define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
606#define EL3_CMD 0x0e
607#define EL3_STATUS 0x0e
608
609/* The top five bits written to EL3_CMD are a command, the lower
610 11 bits are the parameter, if applicable.
611 Note that 11 parameters bits was fine for ethernet, but the new chip
612 can handle FDDI length frames (~4500 octets) and now parameters count
613 32-bit 'Dwords' rather than octets. */
614
615enum vortex_cmd {
616 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
617 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
618 UpStall = 6<<11, UpUnstall = (6<<11)+1,
619 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
620 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
621 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
622 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
623 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
624 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
625 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
626
627/* The SetRxFilter command accepts the following classes: */
628enum RxFilter {
629 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
630
631/* Bits in the general status register. */
632enum vortex_status {
633 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
634 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
635 IntReq = 0x0040, StatsFull = 0x0080,
636 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
637 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
638 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
639};
640
641/* Register window 1 offsets, the window used in normal operation.
642 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
643enum Window1 {
644 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
645 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
646 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
647};
648enum Window0 {
649 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
650 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
651 IntrStatus=0x0E, /* Valid in all windows. */
652};
653enum Win0_EEPROM_bits {
654 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
655 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
656 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
657};
658/* EEPROM locations. */
659enum eeprom_offset {
660 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
661 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
662 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
663 DriverTune=13, Checksum=15};
664
665enum Window2 { /* Window 2. */
666 Wn2_ResetOptions=12,
667};
668enum Window3 { /* Window 3: MAC/config bits. */
669 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
670};
671
672#define BFEXT(value, offset, bitcount) \
673 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
674
675#define BFINS(lhs, rhs, offset, bitcount) \
676 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
677 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
678
679#define RAM_SIZE(v) BFEXT(v, 0, 3)
680#define RAM_WIDTH(v) BFEXT(v, 3, 1)
681#define RAM_SPEED(v) BFEXT(v, 4, 2)
682#define ROM_SIZE(v) BFEXT(v, 6, 2)
683#define RAM_SPLIT(v) BFEXT(v, 16, 2)
684#define XCVR(v) BFEXT(v, 20, 4)
685#define AUTOSELECT(v) BFEXT(v, 24, 1)
686
687enum Window4 { /* Window 4: Xcvr/media bits. */
688 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
689};
690enum Win4_Media_bits {
691 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
692 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
693 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
694 Media_LnkBeat = 0x0800,
695};
696enum Window7 { /* Window 7: Bus Master control. */
697 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
698 Wn7_MasterStatus = 12,
699};
700/* Boomerang bus master control registers. */
701enum MasterCtrl {
702 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
703 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
704};
705
706/* The Rx and Tx descriptor lists.
707 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
708 alignment contraint on tx_ring[] and rx_ring[]. */
709#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
710#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
711struct boom_rx_desc {
712 u32 next; /* Last entry points to 0. */
713 s32 status;
714 u32 addr; /* Up to 63 addr/len pairs possible. */
715 s32 length; /* Set LAST_FRAG to indicate last pair. */
716};
717/* Values for the Rx status entry. */
718enum rx_desc_status {
719 RxDComplete=0x00008000, RxDError=0x4000,
720 /* See boomerang_rx() for actual error bits */
721 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
722 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
723};
724
725#ifdef MAX_SKB_FRAGS
726#define DO_ZEROCOPY 1
727#else
728#define DO_ZEROCOPY 0
729#endif
730
731struct boom_tx_desc {
732 u32 next; /* Last entry points to 0. */
733 s32 status; /* bits 0:12 length, others see below. */
734#if DO_ZEROCOPY
735 struct {
736 u32 addr;
737 s32 length;
738 } frag[1+MAX_SKB_FRAGS];
739#else
740 u32 addr;
741 s32 length;
742#endif
743};
744
745/* Values for the Tx status entry. */
746enum tx_desc_status {
747 CRCDisable=0x2000, TxDComplete=0x8000,
748 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
749 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
750};
751
752/* Chip features we care about in vp->capabilities, read from the EEPROM. */
753enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
754
755struct vortex_extra_stats {
756 unsigned long tx_deferred;
757 unsigned long tx_multiple_collisions;
758 unsigned long rx_bad_ssd;
759};
760
761struct vortex_private {
762 /* The Rx and Tx rings should be quad-word-aligned. */
763 struct boom_rx_desc* rx_ring;
764 struct boom_tx_desc* tx_ring;
765 dma_addr_t rx_ring_dma;
766 dma_addr_t tx_ring_dma;
767 /* The addresses of transmit- and receive-in-place skbuffs. */
768 struct sk_buff* rx_skbuff[RX_RING_SIZE];
769 struct sk_buff* tx_skbuff[TX_RING_SIZE];
770 unsigned int cur_rx, cur_tx; /* The next free ring entry */
771 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
772 struct net_device_stats stats; /* Generic stats */
773 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
774 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
775 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
776
777 /* PCI configuration space information. */
778 struct device *gendev;
779 char __iomem *cb_fn_base; /* CardBus function status addr space. */
780
781 /* Some values here only for performance evaluation and path-coverage */
782 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
783 int card_idx;
784
785 /* The remainder are related to chip state, mostly media selection. */
786 struct timer_list timer; /* Media selection timer. */
787 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
788 int options; /* User-settable misc. driver options. */
789 unsigned int media_override:4, /* Passed-in media type. */
790 default_media:4, /* Read from the EEPROM/Wn3_Config. */
791 full_duplex:1, force_fd:1, autoselect:1,
792 bus_master:1, /* Vortex can only do a fragment bus-m. */
793 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
794 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
795 partner_flow_ctrl:1, /* Partner supports flow control */
796 has_nway:1,
797 enable_wol:1, /* Wake-on-LAN is enabled */
798 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
799 open:1,
800 medialock:1,
801 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
802 large_frames:1; /* accept large frames */
803 int drv_flags;
804 u16 status_enable;
805 u16 intr_enable;
806 u16 available_media; /* From Wn3_Options. */
807 u16 capabilities, info1, info2; /* Various, from EEPROM. */
808 u16 advertising; /* NWay media advertisement */
809 unsigned char phys[2]; /* MII device addresses. */
810 u16 deferred; /* Resend these interrupts when we
811 * bale from the ISR */
812 u16 io_size; /* Size of PCI region (for release_region) */
813 spinlock_t lock; /* Serialise access to device & its vortex_private */
814 struct mii_if_info mii; /* MII lib hooks/info */
815};
816
817#ifdef CONFIG_PCI
818#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
819#else
820#define DEVICE_PCI(dev) NULL
821#endif
822
823#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
824
825#ifdef CONFIG_EISA
826#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
827#else
828#define DEVICE_EISA(dev) NULL
829#endif
830
831#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
832
833/* The action to take with a media selection timer tick.
834 Note that we deviate from the 3Com order by checking 10base2 before AUI.
835 */
836enum xcvr_types {
837 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
838 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
839};
840
841static struct media_table {
842 char *name;
843 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
844 mask:8, /* The transceiver-present bit in Wn3_Config.*/
845 next:8; /* The media type to try next. */
846 int wait; /* Time before we check media status. */
847} media_tbl[] = {
848 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
849 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
850 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
851 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
852 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
853 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
854 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
855 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
856 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
857 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
858 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
859};
860
861static struct {
862 const char str[ETH_GSTRING_LEN];
863} ethtool_stats_keys[] = {
864 { "tx_deferred" },
865 { "tx_multiple_collisions" },
866 { "rx_bad_ssd" },
867};
868
869/* number of ETHTOOL_GSTATS u64's */
870#define VORTEX_NUM_STATS 3
871
872static int vortex_probe1(struct device *gendev, long ioaddr, int irq,
873 int chip_idx, int card_idx);
874static void vortex_up(struct net_device *dev);
875static void vortex_down(struct net_device *dev, int final);
876static int vortex_open(struct net_device *dev);
877static void mdio_sync(long ioaddr, int bits);
878static int mdio_read(struct net_device *dev, int phy_id, int location);
879static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
880static void vortex_timer(unsigned long arg);
881static void rx_oom_timer(unsigned long arg);
882static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
883static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
884static int vortex_rx(struct net_device *dev);
885static int boomerang_rx(struct net_device *dev);
886static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
887static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
888static int vortex_close(struct net_device *dev);
889static void dump_tx_ring(struct net_device *dev);
890static void update_stats(long ioaddr, struct net_device *dev);
891static struct net_device_stats *vortex_get_stats(struct net_device *dev);
892static void set_rx_mode(struct net_device *dev);
893#ifdef CONFIG_PCI
894static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
895#endif
896static void vortex_tx_timeout(struct net_device *dev);
897static void acpi_set_WOL(struct net_device *dev);
898static struct ethtool_ops vortex_ethtool_ops;
899static void set_8021q_mode(struct net_device *dev, int enable);
900
901\f
902/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
903/* Option count limit only -- unlimited interfaces are supported. */
904#define MAX_UNITS 8
905static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,};
906static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
907static int hw_checksums[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
908static int flow_ctrl[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
909static int enable_wol[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
910static int global_options = -1;
911static int global_full_duplex = -1;
912static int global_enable_wol = -1;
913
914/* #define dev_alloc_skb dev_alloc_skb_debug */
915
916/* Variables to work-around the Compaq PCI BIOS32 problem. */
917static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
918static struct net_device *compaq_net_device;
919
920static int vortex_cards_found;
921
922module_param(debug, int, 0);
923module_param(global_options, int, 0);
924module_param_array(options, int, NULL, 0);
925module_param(global_full_duplex, int, 0);
926module_param_array(full_duplex, int, NULL, 0);
927module_param_array(hw_checksums, int, NULL, 0);
928module_param_array(flow_ctrl, int, NULL, 0);
929module_param(global_enable_wol, int, 0);
930module_param_array(enable_wol, int, NULL, 0);
931module_param(rx_copybreak, int, 0);
932module_param(max_interrupt_work, int, 0);
933module_param(compaq_ioaddr, int, 0);
934module_param(compaq_irq, int, 0);
935module_param(compaq_device_id, int, 0);
936module_param(watchdog, int, 0);
937MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
938MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
939MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
940MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
941MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if options is unset");
942MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
943MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
944MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
945MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if options is unset");
946MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
947MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
948MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
949MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
950MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
951MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
952
953#ifdef CONFIG_NET_POLL_CONTROLLER
954static void poll_vortex(struct net_device *dev)
955{
956 struct vortex_private *vp = netdev_priv(dev);
957 unsigned long flags;
958 local_save_flags(flags);
959 local_irq_disable();
960 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
961 local_irq_restore(flags);
962}
963#endif
964
965#ifdef CONFIG_PM
966
967static int vortex_suspend (struct pci_dev *pdev, pm_message_t state)
968{
969 struct net_device *dev = pci_get_drvdata(pdev);
970
971 if (dev && dev->priv) {
972 if (netif_running(dev)) {
973 netif_device_detach(dev);
974 vortex_down(dev, 1);
975 }
5b039e68
RW		 976 pci_save_state(pdev);
977 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
978 free_irq(dev->irq, dev);
979 pci_disable_device(pdev);
980 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 981 }
982 return 0;
983}
984
985static int vortex_resume (struct pci_dev *pdev)
986{
987 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 988 struct vortex_private *vp = netdev_priv(dev);
1da177e4 989
5b039e68
RW		 990 if (dev && vp) {
991 pci_set_power_state(pdev, PCI_D0);
992 pci_restore_state(pdev);
993 pci_enable_device(pdev);
994 pci_set_master(pdev);
995 if (request_irq(dev->irq, vp->full_bus_master_rx ?
996 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
997 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
998 pci_disable_device(pdev);
999 return -EBUSY;
1000 }
1da177e4
LT		 1001 if (netif_running(dev)) {
1002 vortex_up(dev);
1003 netif_device_attach(dev);
1004 }
1005 }
1006 return 0;
1007}
1008
1009#endif /* CONFIG_PM */
1010
1011#ifdef CONFIG_EISA
1012static struct eisa_device_id vortex_eisa_ids[] = {
1013 { "TCM5920", CH_3C592 },
1014 { "TCM5970", CH_3C597 },
1015 { "" }
1016};
1017
1018static int vortex_eisa_probe (struct device *device);
1019static int vortex_eisa_remove (struct device *device);
1020
1021static struct eisa_driver vortex_eisa_driver = {
1022 .id_table = vortex_eisa_ids,
1023 .driver = {
1024 .name = "3c59x",
1025 .probe = vortex_eisa_probe,
1026 .remove = vortex_eisa_remove
1027 }
1028};
1029
1030static int vortex_eisa_probe (struct device *device)
1031{
1032 long ioaddr;
1033 struct eisa_device *edev;
1034
1035 edev = to_eisa_device (device);
1036 ioaddr = edev->base_addr;
1037
1038 if (!request_region(ioaddr, VORTEX_TOTAL_SIZE, DRV_NAME))
1039 return -EBUSY;
1040
1041 if (vortex_probe1(device, ioaddr, inw(ioaddr + 0xC88) >> 12,
1042 edev->id.driver_data, vortex_cards_found)) {
1043 release_region (ioaddr, VORTEX_TOTAL_SIZE);
1044 return -ENODEV;
1045 }
1046
1047 vortex_cards_found++;
1048
1049 return 0;
1050}
1051
1052static int vortex_eisa_remove (struct device *device)
1053{
1054 struct eisa_device *edev;
1055 struct net_device *dev;
1056 struct vortex_private *vp;
1057 long ioaddr;
1058
1059 edev = to_eisa_device (device);
1060 dev = eisa_get_drvdata (edev);
1061
1062 if (!dev) {
1063 printk("vortex_eisa_remove called for Compaq device!\n");
1064 BUG();
1065 }
1066
1067 vp = netdev_priv(dev);
1068 ioaddr = dev->base_addr;
1069
1070 unregister_netdev (dev);
1071 outw (TotalReset|0x14, ioaddr + EL3_CMD);
1072 release_region (ioaddr, VORTEX_TOTAL_SIZE);
1073
1074 free_netdev (dev);
1075 return 0;
1076}
1077#endif
1078
1079/* returns count found (>= 0), or negative on error */
1080static int __init vortex_eisa_init (void)
1081{
1082 int eisa_found = 0;
1083 int orig_cards_found = vortex_cards_found;
1084
1085#ifdef CONFIG_EISA
1086 if (eisa_driver_register (&vortex_eisa_driver) >= 0) {
1087 /* Because of the way EISA bus is probed, we cannot assume
1088 * any device have been found when we exit from
1089 * eisa_driver_register (the bus root driver may not be
1090 * initialized yet). So we blindly assume something was
1091 * found, and let the sysfs magic happend... */
1092
1093 eisa_found = 1;
1094 }
1095#endif
1096
1097 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1098 if (compaq_ioaddr) {
1099 vortex_probe1(NULL, compaq_ioaddr, compaq_irq,
1100 compaq_device_id, vortex_cards_found++);
1101 }
1102
1103 return vortex_cards_found - orig_cards_found + eisa_found;
1104}
1105
1106/* returns count (>= 0), or negative on error */
1107static int __devinit vortex_init_one (struct pci_dev *pdev,
1108 const struct pci_device_id *ent)
1109{
1110 int rc;
1111
1112 /* wake up and enable device */
1113 rc = pci_enable_device (pdev);
1114 if (rc < 0)
1115 goto out;
1116
1117 rc = vortex_probe1 (&pdev->dev, pci_resource_start (pdev, 0),
1118 pdev->irq, ent->driver_data, vortex_cards_found);
1119 if (rc < 0) {
1120 pci_disable_device (pdev);
1121 goto out;
1122 }
1123
1124 vortex_cards_found++;
1125
1126out:
1127 return rc;
1128}
1129
1130/*
1131 * Start up the PCI/EISA device which is described by *gendev.
1132 * Return 0 on success.
1133 *
1134 * NOTE: pdev can be NULL, for the case of a Compaq device
1135 */
1136static int __devinit vortex_probe1(struct device *gendev,
1137 long ioaddr, int irq,
1138 int chip_idx, int card_idx)
1139{
1140 struct vortex_private *vp;
1141 int option;
1142 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1143 int i, step;
1144 struct net_device *dev;
1145 static int printed_version;
1146 int retval, print_info;
1147 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1148 char *print_name = "3c59x";
1149 struct pci_dev *pdev = NULL;
1150 struct eisa_device *edev = NULL;
1151
1152 if (!printed_version) {
1153 printk (version);
1154 printed_version = 1;
1155 }
1156
1157 if (gendev) {
1158 if ((pdev = DEVICE_PCI(gendev))) {
1159 print_name = pci_name(pdev);
1160 }
1161
1162 if ((edev = DEVICE_EISA(gendev))) {
1163 print_name = edev->dev.bus_id;
1164 }
1165 }
1166
1167 dev = alloc_etherdev(sizeof(*vp));
1168 retval = -ENOMEM;
1169 if (!dev) {
1170 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1171 goto out;
1172 }
1173 SET_MODULE_OWNER(dev);
1174 SET_NETDEV_DEV(dev, gendev);
1175 vp = netdev_priv(dev);
1176
1177 option = global_options;
1178
1179 /* The lower four bits are the media type. */
1180 if (dev->mem_start) {
1181 /*
1182 * The 'options' param is passed in as the third arg to the
1183 * LILO 'ether=' argument for non-modular use
1184 */
1185 option = dev->mem_start;
1186 }
1187 else if (card_idx < MAX_UNITS) {
1188 if (options[card_idx] >= 0)
1189 option = options[card_idx];
1190 }
1191
1192 if (option > 0) {
1193 if (option & 0x8000)
1194 vortex_debug = 7;
1195 if (option & 0x4000)
1196 vortex_debug = 2;
1197 if (option & 0x0400)
1198 vp->enable_wol = 1;
1199 }
1200
1201 print_info = (vortex_debug > 1);
1202 if (print_info)
1203 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1204
1205 printk(KERN_INFO "%s: 3Com %s %s at 0x%lx. Vers " DRV_VERSION "\n",
1206 print_name,
1207 pdev ? "PCI" : "EISA",
1208 vci->name,
1209 ioaddr);
1210
1211 dev->base_addr = ioaddr;
1212 dev->irq = irq;
1213 dev->mtu = mtu;
1214 vp->large_frames = mtu > 1500;
1215 vp->drv_flags = vci->drv_flags;
1216 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1217 vp->io_size = vci->io_size;
1218 vp->card_idx = card_idx;
1219
1220 /* module list only for Compaq device */
1221 if (gendev == NULL) {
1222 compaq_net_device = dev;
1223 }
1224
1225 /* PCI-only startup logic */
1226 if (pdev) {
1227 /* EISA resources already marked, so only PCI needs to do this here */
1228 /* Ignore return value, because Cardbus drivers already allocate for us */
1229 if (request_region(ioaddr, vci->io_size, print_name) != NULL)
1230 vp->must_free_region = 1;
1231
1232 /* enable bus-mastering if necessary */
1233 if (vci->flags & PCI_USES_MASTER)
1234 pci_set_master (pdev);
1235
1236 if (vci->drv_flags & IS_VORTEX) {
1237 u8 pci_latency;
1238 u8 new_latency = 248;
1239
1240 /* Check the PCI latency value. On the 3c590 series the latency timer
1241 must be set to the maximum value to avoid data corruption that occurs
1242 when the timer expires during a transfer. This bug exists the Vortex
1243 chip only. */
1244 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1245 if (pci_latency < new_latency) {
1246 printk(KERN_INFO "%s: Overriding PCI latency"
1247 " timer (CFLT) setting of %d, new value is %d.\n",
1248 print_name, pci_latency, new_latency);
1249 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1250 }
1251 }
1252 }
1253
1254 spin_lock_init(&vp->lock);
1255 vp->gendev = gendev;
1256 vp->mii.dev = dev;
1257 vp->mii.mdio_read = mdio_read;
1258 vp->mii.mdio_write = mdio_write;
1259 vp->mii.phy_id_mask = 0x1f;
1260 vp->mii.reg_num_mask = 0x1f;
1261
1262 /* Makes sure rings are at least 16 byte aligned. */
1263 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1264 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1265 &vp->rx_ring_dma);
1266 retval = -ENOMEM;
1267 if (vp->rx_ring == 0)
1268 goto free_region;
1269
1270 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1271 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1272
1273 /* if we are a PCI driver, we store info in pdev->driver_data
1274 * instead of a module list */
1275 if (pdev)
1276 pci_set_drvdata(pdev, dev);
1277 if (edev)
1278 eisa_set_drvdata (edev, dev);
1279
1280 vp->media_override = 7;
1281 if (option >= 0) {
1282 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1283 if (vp->media_override != 7)
1284 vp->medialock = 1;
1285 vp->full_duplex = (option & 0x200) ? 1 : 0;
1286 vp->bus_master = (option & 16) ? 1 : 0;
1287 }
1288
1289 if (global_full_duplex > 0)
1290 vp->full_duplex = 1;
1291 if (global_enable_wol > 0)
1292 vp->enable_wol = 1;
1293
1294 if (card_idx < MAX_UNITS) {
1295 if (full_duplex[card_idx] > 0)
1296 vp->full_duplex = 1;
1297 if (flow_ctrl[card_idx] > 0)
1298 vp->flow_ctrl = 1;
1299 if (enable_wol[card_idx] > 0)
1300 vp->enable_wol = 1;
1301 }
1302
1303 vp->force_fd = vp->full_duplex;
1304 vp->options = option;
1305 /* Read the station address from the EEPROM. */
1306 EL3WINDOW(0);
1307 {
1308 int base;
1309
1310 if (vci->drv_flags & EEPROM_8BIT)
1311 base = 0x230;
1312 else if (vci->drv_flags & EEPROM_OFFSET)
1313 base = EEPROM_Read + 0x30;
1314 else
1315 base = EEPROM_Read;
1316
1317 for (i = 0; i < 0x40; i++) {
1318 int timer;
1319 outw(base + i, ioaddr + Wn0EepromCmd);
1320 /* Pause for at least 162 us. for the read to take place. */
1321 for (timer = 10; timer >= 0; timer--) {
1322 udelay(162);
1323 if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1324 break;
1325 }
1326 eeprom[i] = inw(ioaddr + Wn0EepromData);
1327 }
1328 }
1329 for (i = 0; i < 0x18; i++)
1330 checksum ^= eeprom[i];
1331 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1332 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1333 while (i < 0x21)
1334 checksum ^= eeprom[i++];
1335 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1336 }
1337 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1338 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1339 for (i = 0; i < 3; i++)
1340 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1341 if (print_info) {
1342 for (i = 0; i < 6; i++)
1343 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1344 }
1345 /* Unfortunately an all zero eeprom passes the checksum and this
1346 gets found in the wild in failure cases. Crypto is hard 8) */
1347 if (!is_valid_ether_addr(dev->dev_addr)) {
1348 retval = -EINVAL;
1349 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1350 goto free_ring; /* With every pack */
1351 }
1352 EL3WINDOW(2);
1353 for (i = 0; i < 6; i++)
1354 outb(dev->dev_addr[i], ioaddr + i);
1355
1356#ifdef __sparc__
1357 if (print_info)
1358 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1359#else
1360 if (print_info)
1361 printk(", IRQ %d\n", dev->irq);
1362 /* Tell them about an invalid IRQ. */
1363 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1364 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1365 dev->irq);
1366#endif
1367
1368 EL3WINDOW(4);
1369 step = (inb(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1370 if (print_info) {
1371 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1372 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1373 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1374 }
1375
1376
1377 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1378 unsigned long fn_st_addr; /* Cardbus function status space */
1379 unsigned short n;
1380
1381 fn_st_addr = pci_resource_start (pdev, 2);
1382 if (fn_st_addr) {
1383 vp->cb_fn_base = ioremap(fn_st_addr, 128);
1384 retval = -ENOMEM;
1385 if (!vp->cb_fn_base)
1386 goto free_ring;
1387 }
1388 if (print_info) {
1389 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
1390 print_name, fn_st_addr, vp->cb_fn_base);
1391 }
1392 EL3WINDOW(2);
1393
1394 n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1395 if (vp->drv_flags & INVERT_LED_PWR)
1396 n |= 0x10;
1397 if (vp->drv_flags & INVERT_MII_PWR)
1398 n |= 0x4000;
1399 outw(n, ioaddr + Wn2_ResetOptions);
1400 if (vp->drv_flags & WNO_XCVR_PWR) {
1401 EL3WINDOW(0);
1402 outw(0x0800, ioaddr);
1403 }
1404 }
1405
1406 /* Extract our information from the EEPROM data. */
1407 vp->info1 = eeprom[13];
1408 vp->info2 = eeprom[15];
1409 vp->capabilities = eeprom[16];
1410
1411 if (vp->info1 & 0x8000) {
1412 vp->full_duplex = 1;
1413 if (print_info)
1414 printk(KERN_INFO "Full duplex capable\n");
1415 }
1416
1417 {
1418 static const char * ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1419 unsigned int config;
1420 EL3WINDOW(3);
1421 vp->available_media = inw(ioaddr + Wn3_Options);
1422 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1423 vp->available_media = 0x40;
1424 config = inl(ioaddr + Wn3_Config);
1425 if (print_info) {
1426 printk(KERN_DEBUG " Internal config register is %4.4x, "
1427 "transceivers %#x.\n", config, inw(ioaddr + Wn3_Options));
1428 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1429 8 << RAM_SIZE(config),
1430 RAM_WIDTH(config) ? "word" : "byte",
1431 ram_split[RAM_SPLIT(config)],
1432 AUTOSELECT(config) ? "autoselect/" : "",
1433 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1434 media_tbl[XCVR(config)].name);
1435 }
1436 vp->default_media = XCVR(config);
1437 if (vp->default_media == XCVR_NWAY)
1438 vp->has_nway = 1;
1439 vp->autoselect = AUTOSELECT(config);
1440 }
1441
1442 if (vp->media_override != 7) {
1443 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1444 print_name, vp->media_override,
1445 media_tbl[vp->media_override].name);
1446 dev->if_port = vp->media_override;
1447 } else
1448 dev->if_port = vp->default_media;
1449
1450 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1451 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1452 int phy, phy_idx = 0;
1453 EL3WINDOW(4);
1454 mii_preamble_required++;
1455 if (vp->drv_flags & EXTRA_PREAMBLE)
1456 mii_preamble_required++;
1457 mdio_sync(ioaddr, 32);
1458 mdio_read(dev, 24, 1);
1459 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1460 int mii_status, phyx;
1461
1462 /*
1463 * For the 3c905CX we look at index 24 first, because it bogusly
1464 * reports an external PHY at all indices
1465 */
1466 if (phy == 0)
1467 phyx = 24;
1468 else if (phy <= 24)
1469 phyx = phy - 1;
1470 else
1471 phyx = phy;
1472 mii_status = mdio_read(dev, phyx, 1);
1473 if (mii_status && mii_status != 0xffff) {
1474 vp->phys[phy_idx++] = phyx;
1475 if (print_info) {
1476 printk(KERN_INFO " MII transceiver found at address %d,"
1477 " status %4x.\n", phyx, mii_status);
1478 }
1479 if ((mii_status & 0x0040) == 0)
1480 mii_preamble_required++;
1481 }
1482 }
1483 mii_preamble_required--;
1484 if (phy_idx == 0) {
1485 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1486 vp->phys[0] = 24;
1487 } else {
1488 vp->advertising = mdio_read(dev, vp->phys[0], 4);
1489 if (vp->full_duplex) {
1490 /* Only advertise the FD media types. */
1491 vp->advertising &= ~0x02A0;
1492 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1493 }
1494 }
1495 vp->mii.phy_id = vp->phys[0];
1496 }
1497
1498 if (vp->capabilities & CapBusMaster) {
1499 vp->full_bus_master_tx = 1;
1500 if (print_info) {
1501 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1502 (vp->info2 & 1) ? "early" : "whole-frame" );
1503 }
1504 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1505 vp->bus_master = 0; /* AKPM: vortex only */
1506 }
1507
1508 /* The 3c59x-specific entries in the device structure. */
1509 dev->open = vortex_open;
1510 if (vp->full_bus_master_tx) {
1511 dev->hard_start_xmit = boomerang_start_xmit;
1512 /* Actually, it still should work with iommu. */
1513 dev->features |= NETIF_F_SG;
1514 if (((hw_checksums[card_idx] == -1) && (vp->drv_flags & HAS_HWCKSM)) ||
1515 (hw_checksums[card_idx] == 1)) {
1516 dev->features |= NETIF_F_IP_CSUM;
1517 }
1518 } else {
1519 dev->hard_start_xmit = vortex_start_xmit;
1520 }
1521
1522 if (print_info) {
1523 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1524 print_name,
1525 (dev->features & NETIF_F_SG) ? "en":"dis",
1526 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1527 }
1528
1529 dev->stop = vortex_close;
1530 dev->get_stats = vortex_get_stats;
1531#ifdef CONFIG_PCI
1532 dev->do_ioctl = vortex_ioctl;
1533#endif
1534 dev->ethtool_ops = &vortex_ethtool_ops;
1535 dev->set_multicast_list = set_rx_mode;
1536 dev->tx_timeout = vortex_tx_timeout;
1537 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1538#ifdef CONFIG_NET_POLL_CONTROLLER
1539 dev->poll_controller = poll_vortex;
1540#endif
1541 if (pdev) {
1542 vp->pm_state_valid = 1;
1543 pci_save_state(VORTEX_PCI(vp));
1544 acpi_set_WOL(dev);
1545 }
1546 retval = register_netdev(dev);
1547 if (retval == 0)
1548 return 0;
1549
1550free_ring:
1551 pci_free_consistent(pdev,
1552 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1553 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1554 vp->rx_ring,
1555 vp->rx_ring_dma);
1556free_region:
1557 if (vp->must_free_region)
1558 release_region(ioaddr, vci->io_size);
1559 free_netdev(dev);
1560 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1561out:
1562 return retval;
1563}
1564
1565static void
1566issue_and_wait(struct net_device *dev, int cmd)
1567{
1568 int i;
1569
1570 outw(cmd, dev->base_addr + EL3_CMD);
1571 for (i = 0; i < 2000; i++) {
1572 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress))
1573 return;
1574 }
1575
1576 /* OK, that didn't work. Do it the slow way. One second */
1577 for (i = 0; i < 100000; i++) {
1578 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress)) {
1579 if (vortex_debug > 1)
1580 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1581 dev->name, cmd, i * 10);
1582 return;
1583 }
1584 udelay(10);
1585 }
1586 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1587 dev->name, cmd, inw(dev->base_addr + EL3_STATUS));
1588}
1589
1590static void
1591vortex_up(struct net_device *dev)
1592{
1593 long ioaddr = dev->base_addr;
1594 struct vortex_private *vp = netdev_priv(dev);
1595 unsigned int config;
1596 int i;
1597
1598 if (VORTEX_PCI(vp)) {
1599 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1600 if (vp->pm_state_valid)
1601 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1602 pci_enable_device(VORTEX_PCI(vp));
1603 }
1604
1605 /* Before initializing select the active media port. */
1606 EL3WINDOW(3);
1607 config = inl(ioaddr + Wn3_Config);
1608
1609 if (vp->media_override != 7) {
1610 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1611 dev->name, vp->media_override,
1612 media_tbl[vp->media_override].name);
1613 dev->if_port = vp->media_override;
1614 } else if (vp->autoselect) {
1615 if (vp->has_nway) {
1616 if (vortex_debug > 1)
1617 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1618 dev->name, dev->if_port);
1619 dev->if_port = XCVR_NWAY;
1620 } else {
1621 /* Find first available media type, starting with 100baseTx. */
1622 dev->if_port = XCVR_100baseTx;
1623 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1624 dev->if_port = media_tbl[dev->if_port].next;
1625 if (vortex_debug > 1)
1626 printk(KERN_INFO "%s: first available media type: %s\n",
1627 dev->name, media_tbl[dev->if_port].name);
1628 }
1629 } else {
1630 dev->if_port = vp->default_media;
1631 if (vortex_debug > 1)
1632 printk(KERN_INFO "%s: using default media %s\n",
1633 dev->name, media_tbl[dev->if_port].name);
1634 }
1635
1636 init_timer(&vp->timer);
1637 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1638 vp->timer.data = (unsigned long)dev;
1639 vp->timer.function = vortex_timer; /* timer handler */
1640 add_timer(&vp->timer);
1641
1642 init_timer(&vp->rx_oom_timer);
1643 vp->rx_oom_timer.data = (unsigned long)dev;
1644 vp->rx_oom_timer.function = rx_oom_timer;
1645
1646 if (vortex_debug > 1)
1647 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1648 dev->name, media_tbl[dev->if_port].name);
1649
1650 vp->full_duplex = vp->force_fd;
1651 config = BFINS(config, dev->if_port, 20, 4);
1652 if (vortex_debug > 6)
1653 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1654 outl(config, ioaddr + Wn3_Config);
1655
1656 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1657 int mii_reg1, mii_reg5;
1658 EL3WINDOW(4);
1659 /* Read BMSR (reg1) only to clear old status. */
1660 mii_reg1 = mdio_read(dev, vp->phys[0], 1);
1661 mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1662 if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) {
1663 netif_carrier_off(dev); /* No MII device or no link partner report */
1664 } else {
1665 mii_reg5 &= vp->advertising;
1666 if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1667 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1668 vp->full_duplex = 1;
1669 netif_carrier_on(dev);
1670 }
1671 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1672 if (vortex_debug > 1)
1673 printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1674 " info1 %04x, setting %s-duplex.\n",
1675 dev->name, vp->phys[0],
1676 mii_reg1, mii_reg5,
1677 vp->info1, ((vp->info1 & 0x8000) || vp->full_duplex) ? "full" : "half");
1678 EL3WINDOW(3);
1679 }
1680
1681 /* Set the full-duplex bit. */
1682 outw( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1683 (vp->large_frames ? 0x40 : 0) |
1684 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1685 ioaddr + Wn3_MAC_Ctrl);
1686
1687 if (vortex_debug > 1) {
1688 printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",
1689 dev->name, config);
1690 }
1691
1692 issue_and_wait(dev, TxReset);
1693 /*
1694 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1695 */
1696 issue_and_wait(dev, RxReset|0x04);
1697
1698 outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1699
1700 if (vortex_debug > 1) {
1701 EL3WINDOW(4);
1702 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1703 dev->name, dev->irq, inw(ioaddr + Wn4_Media));
1704 }
1705
1706 /* Set the station address and mask in window 2 each time opened. */
1707 EL3WINDOW(2);
1708 for (i = 0; i < 6; i++)
1709 outb(dev->dev_addr[i], ioaddr + i);
1710 for (; i < 12; i+=2)
1711 outw(0, ioaddr + i);
1712
1713 if (vp->cb_fn_base) {
1714 unsigned short n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1715 if (vp->drv_flags & INVERT_LED_PWR)
1716 n |= 0x10;
1717 if (vp->drv_flags & INVERT_MII_PWR)
1718 n |= 0x4000;
1719 outw(n, ioaddr + Wn2_ResetOptions);
1720 }
1721
1722 if (dev->if_port == XCVR_10base2)
1723 /* Start the thinnet transceiver. We should really wait 50ms...*/
1724 outw(StartCoax, ioaddr + EL3_CMD);
1725 if (dev->if_port != XCVR_NWAY) {
1726 EL3WINDOW(4);
1727 outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1728 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1729 }
1730
1731 /* Switch to the stats window, and clear all stats by reading. */
1732 outw(StatsDisable, ioaddr + EL3_CMD);
1733 EL3WINDOW(6);
1734 for (i = 0; i < 10; i++)
1735 inb(ioaddr + i);
1736 inw(ioaddr + 10);
1737 inw(ioaddr + 12);
1738 /* New: On the Vortex we must also clear the BadSSD counter. */
1739 EL3WINDOW(4);
1740 inb(ioaddr + 12);
1741 /* ..and on the Boomerang we enable the extra statistics bits. */
1742 outw(0x0040, ioaddr + Wn4_NetDiag);
1743
1744 /* Switch to register set 7 for normal use. */
1745 EL3WINDOW(7);
1746
1747 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1748 vp->cur_rx = vp->dirty_rx = 0;
1749 /* Initialize the RxEarly register as recommended. */
1750 outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1751 outl(0x0020, ioaddr + PktStatus);
1752 outl(vp->rx_ring_dma, ioaddr + UpListPtr);
1753 }
1754 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1755 vp->cur_tx = vp->dirty_tx = 0;
1756 if (vp->drv_flags & IS_BOOMERANG)
1757 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1758 /* Clear the Rx, Tx rings. */
1759 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1760 vp->rx_ring[i].status = 0;
1761 for (i = 0; i < TX_RING_SIZE; i++)
1762 vp->tx_skbuff[i] = NULL;
1763 outl(0, ioaddr + DownListPtr);
1764 }
1765 /* Set receiver mode: presumably accept b-case and phys addr only. */
1766 set_rx_mode(dev);
1767 /* enable 802.1q tagged frames */
1768 set_8021q_mode(dev, 1);
1769 outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1770
1771// issue_and_wait(dev, SetTxStart|0x07ff);
1772 outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1773 outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1774 /* Allow status bits to be seen. */
1775 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1776 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1777 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1778 (vp->bus_master ? DMADone : 0);
1779 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1780 (vp->full_bus_master_rx ? 0 : RxComplete) |
1781 StatsFull | HostError | TxComplete | IntReq
1782 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1783 outw(vp->status_enable, ioaddr + EL3_CMD);
1784 /* Ack all pending events, and set active indicator mask. */
1785 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1786 ioaddr + EL3_CMD);
1787 outw(vp->intr_enable, ioaddr + EL3_CMD);
1788 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1789 writel(0x8000, vp->cb_fn_base + 4);
1790 netif_start_queue (dev);
1791}
1792
1793static int
1794vortex_open(struct net_device *dev)
1795{
1796 struct vortex_private *vp = netdev_priv(dev);
1797 int i;
1798 int retval;
1799
1800 /* Use the now-standard shared IRQ implementation. */
1801 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1802 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1803 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1804 goto out;
1805 }
1806
1807 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1808 if (vortex_debug > 2)
1809 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1810 for (i = 0; i < RX_RING_SIZE; i++) {
1811 struct sk_buff *skb;
1812 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1813 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1814 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1815 skb = dev_alloc_skb(PKT_BUF_SZ);
1816 vp->rx_skbuff[i] = skb;
1817 if (skb == NULL)
1818 break; /* Bad news! */
1819 skb->dev = dev; /* Mark as being used by this device. */
1820 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1821 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1822 }
1823 if (i != RX_RING_SIZE) {
1824 int j;
1825 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1826 for (j = 0; j < i; j++) {
1827 if (vp->rx_skbuff[j]) {
1828 dev_kfree_skb(vp->rx_skbuff[j]);
1829 vp->rx_skbuff[j] = NULL;
1830 }
1831 }
1832 retval = -ENOMEM;
1833 goto out_free_irq;
1834 }
1835 /* Wrap the ring. */
1836 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1837 }
1838
1839 vortex_up(dev);
1840 return 0;
1841
1842out_free_irq:
1843 free_irq(dev->irq, dev);
1844out:
1845 if (vortex_debug > 1)
1846 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1847 return retval;
1848}
1849
1850static void
1851vortex_timer(unsigned long data)
1852{
1853 struct net_device *dev = (struct net_device *)data;
1854 struct vortex_private *vp = netdev_priv(dev);
1855 long ioaddr = dev->base_addr;
1856 int next_tick = 60*HZ;
1857 int ok = 0;
1858 int media_status, mii_status, old_window;
1859
1860 if (vortex_debug > 2) {
1861 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1862 dev->name, media_tbl[dev->if_port].name);
1863 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1864 }
1865
1866 if (vp->medialock)
1867 goto leave_media_alone;
1868 disable_irq(dev->irq);
1869 old_window = inw(ioaddr + EL3_CMD) >> 13;
1870 EL3WINDOW(4);
1871 media_status = inw(ioaddr + Wn4_Media);
1872 switch (dev->if_port) {
1873 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1874 if (media_status & Media_LnkBeat) {
1875 netif_carrier_on(dev);
1876 ok = 1;
1877 if (vortex_debug > 1)
1878 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1879 dev->name, media_tbl[dev->if_port].name, media_status);
1880 } else {
1881 netif_carrier_off(dev);
1882 if (vortex_debug > 1) {
1883 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1884 dev->name, media_tbl[dev->if_port].name, media_status);
1885 }
1886 }
1887 break;
1888 case XCVR_MII: case XCVR_NWAY:
1889 {
1890 spin_lock_bh(&vp->lock);
1891 mii_status = mdio_read(dev, vp->phys[0], 1);
2de93fbf 1892 mii_status = mdio_read(dev, vp->phys[0], 1);
1da177e4
LT		 1893 ok = 1;
1894 if (vortex_debug > 2)
1895 printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1896 dev->name, mii_status);
1897 if (mii_status & BMSR_LSTATUS) {
1898 int mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1899 if (! vp->force_fd && mii_reg5 != 0xffff) {
1900 int duplex;
1901
1902 mii_reg5 &= vp->advertising;
1903 duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
1904 if (vp->full_duplex != duplex) {
1905 vp->full_duplex = duplex;
1906 printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1907 "#%d link partner capability of %4.4x.\n",
1908 dev->name, vp->full_duplex ? "full" : "half",
1909 vp->phys[0], mii_reg5);
1910 /* Set the full-duplex bit. */
1911 EL3WINDOW(3);
1912 outw( (vp->full_duplex ? 0x20 : 0) |
1913 (vp->large_frames ? 0x40 : 0) |
1914 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1915 ioaddr + Wn3_MAC_Ctrl);
1916 if (vortex_debug > 1)
1917 printk(KERN_DEBUG "Setting duplex in Wn3_MAC_Ctrl\n");
1918 /* AKPM: bug: should reset Tx and Rx after setting Duplex. Page 180 */
1919 }
1920 }
1921 netif_carrier_on(dev);
1922 } else {
1923 netif_carrier_off(dev);
1924 }
1925 spin_unlock_bh(&vp->lock);
1926 }
1927 break;
1928 default: /* Other media types handled by Tx timeouts. */
1929 if (vortex_debug > 1)
1930 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1931 dev->name, media_tbl[dev->if_port].name, media_status);
1932 ok = 1;
1933 }
1934 if ( ! ok) {
1935 unsigned int config;
1936
1937 do {
1938 dev->if_port = media_tbl[dev->if_port].next;
1939 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1940 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1941 dev->if_port = vp->default_media;
1942 if (vortex_debug > 1)
1943 printk(KERN_DEBUG "%s: Media selection failing, using default "
1944 "%s port.\n",
1945 dev->name, media_tbl[dev->if_port].name);
1946 } else {
1947 if (vortex_debug > 1)
1948 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1949 "%s port.\n",
1950 dev->name, media_tbl[dev->if_port].name);
1951 next_tick = media_tbl[dev->if_port].wait;
1952 }
1953 outw((media_status & ~(Media_10TP|Media_SQE)) |
1954 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1955
1956 EL3WINDOW(3);
1957 config = inl(ioaddr + Wn3_Config);
1958 config = BFINS(config, dev->if_port, 20, 4);
1959 outl(config, ioaddr + Wn3_Config);
1960
1961 outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1962 ioaddr + EL3_CMD);
1963 if (vortex_debug > 1)
1964 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1965 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1966 }
1967 EL3WINDOW(old_window);
1968 enable_irq(dev->irq);
1969
1970leave_media_alone:
1971 if (vortex_debug > 2)
1972 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1973 dev->name, media_tbl[dev->if_port].name);
1974
1975 mod_timer(&vp->timer, RUN_AT(next_tick));
1976 if (vp->deferred)
1977 outw(FakeIntr, ioaddr + EL3_CMD);
1978 return;
1979}
1980
1981static void vortex_tx_timeout(struct net_device *dev)
1982{
1983 struct vortex_private *vp = netdev_priv(dev);
1984 long ioaddr = dev->base_addr;
1985
1986 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1987 dev->name, inb(ioaddr + TxStatus),
1988 inw(ioaddr + EL3_STATUS));
1989 EL3WINDOW(4);
1990 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1991 inw(ioaddr + Wn4_NetDiag),
1992 inw(ioaddr + Wn4_Media),
1993 inl(ioaddr + PktStatus),
1994 inw(ioaddr + Wn4_FIFODiag));
1995 /* Slight code bloat to be user friendly. */
1996 if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
1997 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1998 " network cable problem?\n", dev->name);
1999 if (inw(ioaddr + EL3_STATUS) & IntLatch) {
2000 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2001 " IRQ blocked by another device?\n", dev->name);
2002 /* Bad idea here.. but we might as well handle a few events. */
2003 {
2004 /*
2005 * Block interrupts because vortex_interrupt does a bare spin_lock()
2006 */
2007 unsigned long flags;
2008 local_irq_save(flags);
2009 if (vp->full_bus_master_tx)
2010 boomerang_interrupt(dev->irq, dev, NULL);
2011 else
2012 vortex_interrupt(dev->irq, dev, NULL);
2013 local_irq_restore(flags);
2014 }
2015 }
2016
2017 if (vortex_debug > 0)
2018 dump_tx_ring(dev);
2019
2020 issue_and_wait(dev, TxReset);
2021
2022 vp->stats.tx_errors++;
2023 if (vp->full_bus_master_tx) {
2024 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
2025 if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0)
2026 outl(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
2027 ioaddr + DownListPtr);
2028 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2029 netif_wake_queue (dev);
2030 if (vp->drv_flags & IS_BOOMERANG)
2031 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2032 outw(DownUnstall, ioaddr + EL3_CMD);
2033 } else {
2034 vp->stats.tx_dropped++;
2035 netif_wake_queue(dev);
2036 }
2037
2038 /* Issue Tx Enable */
2039 outw(TxEnable, ioaddr + EL3_CMD);
2040 dev->trans_start = jiffies;
2041
2042 /* Switch to register set 7 for normal use. */
2043 EL3WINDOW(7);
2044}
2045
2046/*
2047 * Handle uncommon interrupt sources. This is a separate routine to minimize
2048 * the cache impact.
2049 */
2050static void
2051vortex_error(struct net_device *dev, int status)
2052{
2053 struct vortex_private *vp = netdev_priv(dev);
2054 long ioaddr = dev->base_addr;
2055 int do_tx_reset = 0, reset_mask = 0;
2056 unsigned char tx_status = 0;
2057
2058 if (vortex_debug > 2) {
2059 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2060 }
2061
2062 if (status & TxComplete) { /* Really "TxError" for us. */
2063 tx_status = inb(ioaddr + TxStatus);
2064 /* Presumably a tx-timeout. We must merely re-enable. */
2065 if (vortex_debug > 2
2066 || (tx_status != 0x88 && vortex_debug > 0)) {
2067 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2068 dev->name, tx_status);
2069 if (tx_status == 0x82) {
2070 printk(KERN_ERR "Probably a duplex mismatch. See "
2071 "Documentation/networking/vortex.txt\n");
2072 }
2073 dump_tx_ring(dev);
2074 }
2075 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2076 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2077 outb(0, ioaddr + TxStatus);
2078 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2079 do_tx_reset = 1;
2080 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
2081 do_tx_reset = 1;
2082 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2083 } else { /* Merely re-enable the transmitter. */
2084 outw(TxEnable, ioaddr + EL3_CMD);
2085 }
2086 }
2087
2088 if (status & RxEarly) { /* Rx early is unused. */
2089 vortex_rx(dev);
2090 outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
2091 }
2092 if (status & StatsFull) { /* Empty statistics. */
2093 static int DoneDidThat;
2094 if (vortex_debug > 4)
2095 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2096 update_stats(ioaddr, dev);
2097 /* HACK: Disable statistics as an interrupt source. */
2098 /* This occurs when we have the wrong media type! */
2099 if (DoneDidThat == 0 &&
2100 inw(ioaddr + EL3_STATUS) & StatsFull) {
2101 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2102 "stats as an interrupt source.\n", dev->name);
2103 EL3WINDOW(5);
2104 outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
2105 vp->intr_enable &= ~StatsFull;
2106 EL3WINDOW(7);
2107 DoneDidThat++;
2108 }
2109 }
2110 if (status & IntReq) { /* Restore all interrupt sources. */
2111 outw(vp->status_enable, ioaddr + EL3_CMD);
2112 outw(vp->intr_enable, ioaddr + EL3_CMD);
2113 }
2114 if (status & HostError) {
2115 u16 fifo_diag;
2116 EL3WINDOW(4);
2117 fifo_diag = inw(ioaddr + Wn4_FIFODiag);
2118 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2119 dev->name, fifo_diag);
2120 /* Adapter failure requires Tx/Rx reset and reinit. */
2121 if (vp->full_bus_master_tx) {
2122 int bus_status = inl(ioaddr + PktStatus);
2123 /* 0x80000000 PCI master abort. */
2124 /* 0x40000000 PCI target abort. */
2125 if (vortex_debug)
2126 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2127
2128 /* In this case, blow the card away */
2129 /* Must not enter D3 or we can't legally issue the reset! */
2130 vortex_down(dev, 0);
2131 issue_and_wait(dev, TotalReset | 0xff);
2132 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2133 } else if (fifo_diag & 0x0400)
2134 do_tx_reset = 1;
2135 if (fifo_diag & 0x3000) {
2136 /* Reset Rx fifo and upload logic */
2137 issue_and_wait(dev, RxReset|0x07);
2138 /* Set the Rx filter to the current state. */
2139 set_rx_mode(dev);
2140 /* enable 802.1q VLAN tagged frames */
2141 set_8021q_mode(dev, 1);
2142 outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2143 outw(AckIntr | HostError, ioaddr + EL3_CMD);
2144 }
2145 }
2146
2147 if (do_tx_reset) {
2148 issue_and_wait(dev, TxReset|reset_mask);
2149 outw(TxEnable, ioaddr + EL3_CMD);
2150 if (!vp->full_bus_master_tx)
2151 netif_wake_queue(dev);
2152 }
2153}
2154
2155static int
2156vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2157{
2158 struct vortex_private *vp = netdev_priv(dev);
2159 long ioaddr = dev->base_addr;
2160
2161 /* Put out the doubleword header... */
2162 outl(skb->len, ioaddr + TX_FIFO);
2163 if (vp->bus_master) {
2164 /* Set the bus-master controller to transfer the packet. */
2165 int len = (skb->len + 3) & ~3;
2166 outl( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2167 ioaddr + Wn7_MasterAddr);
2168 outw(len, ioaddr + Wn7_MasterLen);
2169 vp->tx_skb = skb;
2170 outw(StartDMADown, ioaddr + EL3_CMD);
2171 /* netif_wake_queue() will be called at the DMADone interrupt. */
2172 } else {
2173 /* ... and the packet rounded to a doubleword. */
2174 outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2175 dev_kfree_skb (skb);
2176 if (inw(ioaddr + TxFree) > 1536) {
2177 netif_start_queue (dev); /* AKPM: redundant? */
2178 } else {
2179 /* Interrupt us when the FIFO has room for max-sized packet. */
2180 netif_stop_queue(dev);
2181 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2182 }
2183 }
2184
2185 dev->trans_start = jiffies;
2186
2187 /* Clear the Tx status stack. */
2188 {
2189 int tx_status;
2190 int i = 32;
2191
2192 while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
2193 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2194 if (vortex_debug > 2)
2195 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2196 dev->name, tx_status);
2197 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2198 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2199 if (tx_status & 0x30) {
2200 issue_and_wait(dev, TxReset);
2201 }
2202 outw(TxEnable, ioaddr + EL3_CMD);
2203 }
2204 outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2205 }
2206 }
2207 return 0;
2208}
2209
2210static int
2211boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2212{
2213 struct vortex_private *vp = netdev_priv(dev);
2214 long ioaddr = dev->base_addr;
2215 /* Calculate the next Tx descriptor entry. */
2216 int entry = vp->cur_tx % TX_RING_SIZE;
2217 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2218 unsigned long flags;
2219
2220 if (vortex_debug > 6) {
2221 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2222 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2223 dev->name, vp->cur_tx);
1da177e4
LT		 2224 }
2225
2226 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2227 if (vortex_debug > 0)
2228 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2229 dev->name);
2230 netif_stop_queue(dev);
2231 return 1;
2232 }
2233
2234 vp->tx_skbuff[entry] = skb;
2235
2236 vp->tx_ring[entry].next = 0;
2237#if DO_ZEROCOPY
2238 if (skb->ip_summed != CHECKSUM_HW)
2239 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2240 else
2241 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2242
2243 if (!skb_shinfo(skb)->nr_frags) {
2244 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2245 skb->len, PCI_DMA_TODEVICE));
2246 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2247 } else {
2248 int i;
2249
2250 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2251 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2252 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2253
2254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2255 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2256
2257 vp->tx_ring[entry].frag[i+1].addr =
2258 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2259 (void*)page_address(frag->page) + frag->page_offset,
2260 frag->size, PCI_DMA_TODEVICE));
2261
2262 if (i == skb_shinfo(skb)->nr_frags-1)
2263 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2264 else
2265 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2266 }
2267 }
2268#else
2269 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2270 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2271 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2272#endif
2273
2274 spin_lock_irqsave(&vp->lock, flags);
2275 /* Wait for the stall to complete. */
2276 issue_and_wait(dev, DownStall);
2277 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2278 if (inl(ioaddr + DownListPtr) == 0) {
2279 outl(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2280 vp->queued_packet++;
2281 }
2282
2283 vp->cur_tx++;
2284 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2285 netif_stop_queue (dev);
2286 } else { /* Clear previous interrupt enable. */
2287#if defined(tx_interrupt_mitigation)
2288 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2289 * were selected, this would corrupt DN_COMPLETE. No?
2290 */
2291 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2292#endif
2293 }
2294 outw(DownUnstall, ioaddr + EL3_CMD);
2295 spin_unlock_irqrestore(&vp->lock, flags);
2296 dev->trans_start = jiffies;
2297 return 0;
2298}
2299
2300/* The interrupt handler does all of the Rx thread work and cleans up
2301 after the Tx thread. */
2302
2303/*
2304 * This is the ISR for the vortex series chips.
2305 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2306 */
2307
2308static irqreturn_t
2309vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2310{
2311 struct net_device *dev = dev_id;
2312 struct vortex_private *vp = netdev_priv(dev);
2313 long ioaddr;
2314 int status;
2315 int work_done = max_interrupt_work;
2316 int handled = 0;
2317
2318 ioaddr = dev->base_addr;
2319 spin_lock(&vp->lock);
2320
2321 status = inw(ioaddr + EL3_STATUS);
2322
2323 if (vortex_debug > 6)
2324 printk("vortex_interrupt(). status=0x%4x\n", status);
2325
2326 if ((status & IntLatch) == 0)
2327 goto handler_exit; /* No interrupt: shared IRQs cause this */
2328 handled = 1;
2329
2330 if (status & IntReq) {
2331 status |= vp->deferred;
2332 vp->deferred = 0;
2333 }
2334
2335 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2336 goto handler_exit;
2337
2338 if (vortex_debug > 4)
2339 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2340 dev->name, status, inb(ioaddr + Timer));
2341
2342 do {
2343 if (vortex_debug > 5)
2344 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2345 dev->name, status);
2346 if (status & RxComplete)
2347 vortex_rx(dev);
2348
2349 if (status & TxAvailable) {
2350 if (vortex_debug > 5)
2351 printk(KERN_DEBUG " TX room bit was handled.\n");
2352 /* There's room in the FIFO for a full-sized packet. */
2353 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2354 netif_wake_queue (dev);
2355 }
2356
2357 if (status & DMADone) {
2358 if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) {
2359 outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2360 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2361 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2362 if (inw(ioaddr + TxFree) > 1536) {
2363 /*
2364 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2365 * insufficient FIFO room, the TxAvailable test will succeed and call
2366 * netif_wake_queue()
2367 */
2368 netif_wake_queue(dev);
2369 } else { /* Interrupt when FIFO has room for max-sized packet. */
2370 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2371 netif_stop_queue(dev);
2372 }
2373 }
2374 }
2375 /* Check for all uncommon interrupts at once. */
2376 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2377 if (status == 0xffff)
2378 break;
2379 vortex_error(dev, status);
2380 }
2381
2382 if (--work_done < 0) {
2383 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2384 "%4.4x.\n", dev->name, status);
2385 /* Disable all pending interrupts. */
2386 do {
2387 vp->deferred |= status;
2388 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2389 ioaddr + EL3_CMD);
2390 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2391 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2392 /* The timer will reenable interrupts. */
2393 mod_timer(&vp->timer, jiffies + 1*HZ);
2394 break;
2395 }
2396 /* Acknowledge the IRQ. */
2397 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2398 } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2399
2400 if (vortex_debug > 4)
2401 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2402 dev->name, status);
2403handler_exit:
2404 spin_unlock(&vp->lock);
2405 return IRQ_RETVAL(handled);
2406}
2407
2408/*
2409 * This is the ISR for the boomerang series chips.
2410 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2411 */
2412
2413static irqreturn_t
2414boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2415{
2416 struct net_device *dev = dev_id;
2417 struct vortex_private *vp = netdev_priv(dev);
2418 long ioaddr;
2419 int status;
2420 int work_done = max_interrupt_work;
2421
2422 ioaddr = dev->base_addr;
2423
2424 /*
2425 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2426 * and boomerang_start_xmit
2427 */
2428 spin_lock(&vp->lock);
2429
2430 status = inw(ioaddr + EL3_STATUS);
2431
2432 if (vortex_debug > 6)
2433 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2434
2435 if ((status & IntLatch) == 0)
2436 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2437
2438 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2439 if (vortex_debug > 1)
2440 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2441 goto handler_exit;
2442 }
2443
2444 if (status & IntReq) {
2445 status |= vp->deferred;
2446 vp->deferred = 0;
2447 }
2448
2449 if (vortex_debug > 4)
2450 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2451 dev->name, status, inb(ioaddr + Timer));
2452 do {
2453 if (vortex_debug > 5)
2454 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2455 dev->name, status);
2456 if (status & UpComplete) {
2457 outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
2458 if (vortex_debug > 5)
2459 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2460 boomerang_rx(dev);
2461 }
2462
2463 if (status & DownComplete) {
2464 unsigned int dirty_tx = vp->dirty_tx;
2465
2466 outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
2467 while (vp->cur_tx - dirty_tx > 0) {
2468 int entry = dirty_tx % TX_RING_SIZE;
2469#if 1 /* AKPM: the latter is faster, but cyclone-only */
2470 if (inl(ioaddr + DownListPtr) ==
2471 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2472 break; /* It still hasn't been processed. */
2473#else
2474 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2475 break; /* It still hasn't been processed. */
2476#endif
2477
2478 if (vp->tx_skbuff[entry]) {
2479 struct sk_buff *skb = vp->tx_skbuff[entry];
2480#if DO_ZEROCOPY
2481 int i;
2482 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2483 pci_unmap_single(VORTEX_PCI(vp),
2484 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2485 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2486 PCI_DMA_TODEVICE);
2487#else
2488 pci_unmap_single(VORTEX_PCI(vp),
2489 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2490#endif
2491 dev_kfree_skb_irq(skb);
2492 vp->tx_skbuff[entry] = NULL;
2493 } else {
2494 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2495 }
2496 /* vp->stats.tx_packets++; Counted below. */
2497 dirty_tx++;
2498 }
2499 vp->dirty_tx = dirty_tx;
2500 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2501 if (vortex_debug > 6)
2502 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2503 netif_wake_queue (dev);
2504 }
2505 }
2506
2507 /* Check for all uncommon interrupts at once. */
2508 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2509 vortex_error(dev, status);
2510
2511 if (--work_done < 0) {
2512 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2513 "%4.4x.\n", dev->name, status);
2514 /* Disable all pending interrupts. */
2515 do {
2516 vp->deferred |= status;
2517 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2518 ioaddr + EL3_CMD);
2519 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2520 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2521 /* The timer will reenable interrupts. */
2522 mod_timer(&vp->timer, jiffies + 1*HZ);
2523 break;
2524 }
2525 /* Acknowledge the IRQ. */
2526 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2527 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2528 writel(0x8000, vp->cb_fn_base + 4);
2529
2530 } while ((status = inw(ioaddr + EL3_STATUS)) & IntLatch);
2531
2532 if (vortex_debug > 4)
2533 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2534 dev->name, status);
2535handler_exit:
2536 spin_unlock(&vp->lock);
2537 return IRQ_HANDLED;
2538}
2539
2540static int vortex_rx(struct net_device *dev)
2541{
2542 struct vortex_private *vp = netdev_priv(dev);
2543 long ioaddr = dev->base_addr;
2544 int i;
2545 short rx_status;
2546
2547 if (vortex_debug > 5)
2548 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2549 inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
2550 while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
2551 if (rx_status & 0x4000) { /* Error, update stats. */
2552 unsigned char rx_error = inb(ioaddr + RxErrors);
2553 if (vortex_debug > 2)
2554 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2555 vp->stats.rx_errors++;
2556 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2557 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2558 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2559 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2560 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2561 } else {
2562 /* The packet length: up to 4.5K!. */
2563 int pkt_len = rx_status & 0x1fff;
2564 struct sk_buff *skb;
2565
2566 skb = dev_alloc_skb(pkt_len + 5);
2567 if (vortex_debug > 4)
2568 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2569 pkt_len, rx_status);
2570 if (skb != NULL) {
2571 skb->dev = dev;
2572 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2573 /* 'skb_put()' points to the start of sk_buff data area. */
2574 if (vp->bus_master &&
2575 ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2576 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2577 pkt_len, PCI_DMA_FROMDEVICE);
2578 outl(dma, ioaddr + Wn7_MasterAddr);
2579 outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2580 outw(StartDMAUp, ioaddr + EL3_CMD);
2581 while (inw(ioaddr + Wn7_MasterStatus) & 0x8000)
2582 ;
2583 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2584 } else {
2585 insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
2586 (pkt_len + 3) >> 2);
2587 }
2588 outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2589 skb->protocol = eth_type_trans(skb, dev);
2590 netif_rx(skb);
2591 dev->last_rx = jiffies;
2592 vp->stats.rx_packets++;
2593 /* Wait a limited time to go to next packet. */
2594 for (i = 200; i >= 0; i--)
2595 if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
2596 break;
2597 continue;
2598 } else if (vortex_debug > 0)
2599 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2600 "size %d.\n", dev->name, pkt_len);
2601 }
2602 vp->stats.rx_dropped++;
2603 issue_and_wait(dev, RxDiscard);
2604 }
2605
2606 return 0;
2607}
2608
2609static int
2610boomerang_rx(struct net_device *dev)
2611{
2612 struct vortex_private *vp = netdev_priv(dev);
2613 int entry = vp->cur_rx % RX_RING_SIZE;
2614 long ioaddr = dev->base_addr;
2615 int rx_status;
2616 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2617
2618 if (vortex_debug > 5)
2619 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", inw(ioaddr+EL3_STATUS));
2620
2621 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2622 if (--rx_work_limit < 0)
2623 break;
2624 if (rx_status & RxDError) { /* Error, update stats. */
2625 unsigned char rx_error = rx_status >> 16;
2626 if (vortex_debug > 2)
2627 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2628 vp->stats.rx_errors++;
2629 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2630 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2631 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2632 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2633 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2634 } else {
2635 /* The packet length: up to 4.5K!. */
2636 int pkt_len = rx_status & 0x1fff;
2637 struct sk_buff *skb;
2638 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2639
2640 if (vortex_debug > 4)
2641 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2642 pkt_len, rx_status);
2643
2644 /* Check if the packet is long enough to just accept without
2645 copying to a properly sized skbuff. */
2646 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2647 skb->dev = dev;
2648 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2649 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2650 /* 'skb_put()' points to the start of sk_buff data area. */
2651 memcpy(skb_put(skb, pkt_len),
689be439 2652 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2653 pkt_len);
2654 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2655 vp->rx_copy++;
2656 } else {
2657 /* Pass up the skbuff already on the Rx ring. */
2658 skb = vp->rx_skbuff[entry];
2659 vp->rx_skbuff[entry] = NULL;
2660 skb_put(skb, pkt_len);
2661 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2662 vp->rx_nocopy++;
2663 }
2664 skb->protocol = eth_type_trans(skb, dev);
2665 { /* Use hardware checksum info. */
2666 int csum_bits = rx_status & 0xee000000;
2667 if (csum_bits &&
2668 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2669 csum_bits == (IPChksumValid | UDPChksumValid))) {
2670 skb->ip_summed = CHECKSUM_UNNECESSARY;
2671 vp->rx_csumhits++;
2672 }
2673 }
2674 netif_rx(skb);
2675 dev->last_rx = jiffies;
2676 vp->stats.rx_packets++;
2677 }
2678 entry = (++vp->cur_rx) % RX_RING_SIZE;
2679 }
2680 /* Refill the Rx ring buffers. */
2681 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2682 struct sk_buff *skb;
2683 entry = vp->dirty_rx % RX_RING_SIZE;
2684 if (vp->rx_skbuff[entry] == NULL) {
2685 skb = dev_alloc_skb(PKT_BUF_SZ);
2686 if (skb == NULL) {
2687 static unsigned long last_jif;
2688 if ((jiffies - last_jif) > 10 * HZ) {
2689 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2690 last_jif = jiffies;
2691 }
2692 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2693 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2694 break; /* Bad news! */
2695 }
2696 skb->dev = dev; /* Mark as being used by this device. */
2697 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2698 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2699 vp->rx_skbuff[entry] = skb;
2700 }
2701 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2702 outw(UpUnstall, ioaddr + EL3_CMD);
2703 }
2704 return 0;
2705}
2706
2707/*
2708 * If we've hit a total OOM refilling the Rx ring we poll once a second
2709 * for some memory. Otherwise there is no way to restart the rx process.
2710 */
2711static void
2712rx_oom_timer(unsigned long arg)
2713{
2714 struct net_device *dev = (struct net_device *)arg;
2715 struct vortex_private *vp = netdev_priv(dev);
2716
2717 spin_lock_irq(&vp->lock);
2718 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2719 boomerang_rx(dev);
2720 if (vortex_debug > 1) {
2721 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2722 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2723 }
2724 spin_unlock_irq(&vp->lock);
2725}
2726
2727static void
2728vortex_down(struct net_device *dev, int final_down)
2729{
2730 struct vortex_private *vp = netdev_priv(dev);
2731 long ioaddr = dev->base_addr;
2732
2733 netif_stop_queue (dev);
2734
2735 del_timer_sync(&vp->rx_oom_timer);
2736 del_timer_sync(&vp->timer);
2737
2738 /* Turn off statistics ASAP. We update vp->stats below. */
2739 outw(StatsDisable, ioaddr + EL3_CMD);
2740
2741 /* Disable the receiver and transmitter. */
2742 outw(RxDisable, ioaddr + EL3_CMD);
2743 outw(TxDisable, ioaddr + EL3_CMD);
2744
2745 /* Disable receiving 802.1q tagged frames */
2746 set_8021q_mode(dev, 0);
2747
2748 if (dev->if_port == XCVR_10base2)
2749 /* Turn off thinnet power. Green! */
2750 outw(StopCoax, ioaddr + EL3_CMD);
2751
2752 outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2753
2754 update_stats(ioaddr, dev);
2755 if (vp->full_bus_master_rx)
2756 outl(0, ioaddr + UpListPtr);
2757 if (vp->full_bus_master_tx)
2758 outl(0, ioaddr + DownListPtr);
2759
2760 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2761 vp->pm_state_valid = 1;
1da177e4
LT		 2762 pci_save_state(VORTEX_PCI(vp));
2763 acpi_set_WOL(dev);
2764 }
2765}
2766
2767static int
2768vortex_close(struct net_device *dev)
2769{
2770 struct vortex_private *vp = netdev_priv(dev);
2771 long ioaddr = dev->base_addr;
2772 int i;
2773
2774 if (netif_device_present(dev))
2775 vortex_down(dev, 1);
2776
2777 if (vortex_debug > 1) {
2778 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2779 dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus));
2780 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2781 " tx_queued %d Rx pre-checksummed %d.\n",
2782 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2783 }
2784
2785#if DO_ZEROCOPY
2786 if ( vp->rx_csumhits &&
2787 ((vp->drv_flags & HAS_HWCKSM) == 0) &&
2788 (hw_checksums[vp->card_idx] == -1)) {
2789 printk(KERN_WARNING "%s supports hardware checksums, and we're not using them!\n", dev->name);
2790 }
2791#endif
2792
2793 free_irq(dev->irq, dev);
2794
2795 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2796 for (i = 0; i < RX_RING_SIZE; i++)
2797 if (vp->rx_skbuff[i]) {
2798 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2799 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2800 dev_kfree_skb(vp->rx_skbuff[i]);
2801 vp->rx_skbuff[i] = NULL;
2802 }
2803 }
2804 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2805 for (i = 0; i < TX_RING_SIZE; i++) {
2806 if (vp->tx_skbuff[i]) {
2807 struct sk_buff *skb = vp->tx_skbuff[i];
2808#if DO_ZEROCOPY
2809 int k;
2810
2811 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2812 pci_unmap_single(VORTEX_PCI(vp),
2813 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2814 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2815 PCI_DMA_TODEVICE);
2816#else
2817 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2818#endif
2819 dev_kfree_skb(skb);
2820 vp->tx_skbuff[i] = NULL;
2821 }
2822 }
2823 }
2824
2825 return 0;
2826}
2827
2828static void
2829dump_tx_ring(struct net_device *dev)
2830{
2831 if (vortex_debug > 0) {
2832 struct vortex_private *vp = netdev_priv(dev);
2833 long ioaddr = dev->base_addr;
2834
2835 if (vp->full_bus_master_tx) {
2836 int i;
2837 int stalled = inl(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2838
2839 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2840 vp->full_bus_master_tx,
2841 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2842 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2843 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2844 inl(ioaddr + DownListPtr),
2845 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2846 issue_and_wait(dev, DownStall);
2847 for (i = 0; i < TX_RING_SIZE; i++) {
2848 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2849 &vp->tx_ring[i],
2850#if DO_ZEROCOPY
2851 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2852#else
2853 le32_to_cpu(vp->tx_ring[i].length),
2854#endif
2855 le32_to_cpu(vp->tx_ring[i].status));
2856 }
2857 if (!stalled)
2858 outw(DownUnstall, ioaddr + EL3_CMD);
2859 }
2860 }
2861}
2862
2863static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2864{
2865 struct vortex_private *vp = netdev_priv(dev);
2866 unsigned long flags;
2867
2868 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2869 spin_lock_irqsave (&vp->lock, flags);
2870 update_stats(dev->base_addr, dev);
2871 spin_unlock_irqrestore (&vp->lock, flags);
2872 }
2873 return &vp->stats;
2874}
2875
2876/* Update statistics.
2877 Unlike with the EL3 we need not worry about interrupts changing
2878 the window setting from underneath us, but we must still guard
2879 against a race condition with a StatsUpdate interrupt updating the
2880 table. This is done by checking that the ASM (!) code generated uses
2881 atomic updates with '+='.
2882 */
2883static void update_stats(long ioaddr, struct net_device *dev)
2884{
2885 struct vortex_private *vp = netdev_priv(dev);
2886 int old_window = inw(ioaddr + EL3_CMD);
2887
2888 if (old_window == 0xffff) /* Chip suspended or ejected. */
2889 return;
2890 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2891 /* Switch to the stats window, and read everything. */
2892 EL3WINDOW(6);
2893 vp->stats.tx_carrier_errors += inb(ioaddr + 0);
2894 vp->stats.tx_heartbeat_errors += inb(ioaddr + 1);
2895 vp->stats.collisions += inb(ioaddr + 3);
2896 vp->stats.tx_window_errors += inb(ioaddr + 4);
2897 vp->stats.rx_fifo_errors += inb(ioaddr + 5);
2898 vp->stats.tx_packets += inb(ioaddr + 6);
2899 vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4;
2900 /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */
2901 /* Don't bother with register 9, an extension of registers 6&7.
2902 If we do use the 6&7 values the atomic update assumption above
2903 is invalid. */
2904 vp->stats.rx_bytes += inw(ioaddr + 10);
2905 vp->stats.tx_bytes += inw(ioaddr + 12);
2906 /* Extra stats for get_ethtool_stats() */
2907 vp->xstats.tx_multiple_collisions += inb(ioaddr + 2);
2908 vp->xstats.tx_deferred += inb(ioaddr + 8);
2909 EL3WINDOW(4);
2910 vp->xstats.rx_bad_ssd += inb(ioaddr + 12);
2911
2912 {
2913 u8 up = inb(ioaddr + 13);
2914 vp->stats.rx_bytes += (up & 0x0f) << 16;
2915 vp->stats.tx_bytes += (up & 0xf0) << 12;
2916 }
2917
2918 EL3WINDOW(old_window >> 13);
2919 return;
2920}
2921
2922static int vortex_nway_reset(struct net_device *dev)
2923{
2924 struct vortex_private *vp = netdev_priv(dev);
2925 long ioaddr = dev->base_addr;
2926 unsigned long flags;
2927 int rc;
2928
2929 spin_lock_irqsave(&vp->lock, flags);
2930 EL3WINDOW(4);
2931 rc = mii_nway_restart(&vp->mii);
2932 spin_unlock_irqrestore(&vp->lock, flags);
2933 return rc;
2934}
2935
2936static u32 vortex_get_link(struct net_device *dev)
2937{
2938 struct vortex_private *vp = netdev_priv(dev);
2939 long ioaddr = dev->base_addr;
2940 unsigned long flags;
2941 int rc;
2942
2943 spin_lock_irqsave(&vp->lock, flags);
2944 EL3WINDOW(4);
2945 rc = mii_link_ok(&vp->mii);
2946 spin_unlock_irqrestore(&vp->lock, flags);
2947 return rc;
2948}
2949
2950static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2951{
2952 struct vortex_private *vp = netdev_priv(dev);
2953 long ioaddr = dev->base_addr;
2954 unsigned long flags;
2955 int rc;
2956
2957 spin_lock_irqsave(&vp->lock, flags);
2958 EL3WINDOW(4);
2959 rc = mii_ethtool_gset(&vp->mii, cmd);
2960 spin_unlock_irqrestore(&vp->lock, flags);
2961 return rc;
2962}
2963
2964static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2965{
2966 struct vortex_private *vp = netdev_priv(dev);
2967 long ioaddr = dev->base_addr;
2968 unsigned long flags;
2969 int rc;
2970
2971 spin_lock_irqsave(&vp->lock, flags);
2972 EL3WINDOW(4);
2973 rc = mii_ethtool_sset(&vp->mii, cmd);
2974 spin_unlock_irqrestore(&vp->lock, flags);
2975 return rc;
2976}
2977
2978static u32 vortex_get_msglevel(struct net_device *dev)
2979{
2980 return vortex_debug;
2981}
2982
2983static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2984{
2985 vortex_debug = dbg;
2986}
2987
2988static int vortex_get_stats_count(struct net_device *dev)
2989{
2990 return VORTEX_NUM_STATS;
2991}
2992
2993static void vortex_get_ethtool_stats(struct net_device *dev,
2994 struct ethtool_stats *stats, u64 *data)
2995{
2996 struct vortex_private *vp = netdev_priv(dev);
2997 unsigned long flags;
2998
2999 spin_lock_irqsave(&vp->lock, flags);
3000 update_stats(dev->base_addr, dev);
3001 spin_unlock_irqrestore(&vp->lock, flags);
3002
3003 data[0] = vp->xstats.tx_deferred;
3004 data[1] = vp->xstats.tx_multiple_collisions;
3005 data[2] = vp->xstats.rx_bad_ssd;
3006}
3007
3008
3009static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3010{
3011 switch (stringset) {
3012 case ETH_SS_STATS:
3013 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
3014 break;
3015 default:
3016 WARN_ON(1);
3017 break;
3018 }
3019}
3020
3021static void vortex_get_drvinfo(struct net_device *dev,
3022 struct ethtool_drvinfo *info)
3023{
3024 struct vortex_private *vp = netdev_priv(dev);
3025
3026 strcpy(info->driver, DRV_NAME);
3027 strcpy(info->version, DRV_VERSION);
3028 if (VORTEX_PCI(vp)) {
3029 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3030 } else {
3031 if (VORTEX_EISA(vp))
3032 sprintf(info->bus_info, vp->gendev->bus_id);
3033 else
3034 sprintf(info->bus_info, "EISA 0x%lx %d",
3035 dev->base_addr, dev->irq);
3036 }
3037}
3038
3039static struct ethtool_ops vortex_ethtool_ops = {
3040 .get_drvinfo = vortex_get_drvinfo,
3041 .get_strings = vortex_get_strings,
3042 .get_msglevel = vortex_get_msglevel,
3043 .set_msglevel = vortex_set_msglevel,
3044 .get_ethtool_stats = vortex_get_ethtool_stats,
3045 .get_stats_count = vortex_get_stats_count,
3046 .get_settings = vortex_get_settings,
3047 .set_settings = vortex_set_settings,
3048 .get_link = vortex_get_link,
3049 .nway_reset = vortex_nway_reset,
3050};
3051
3052#ifdef CONFIG_PCI
3053/*
3054 * Must power the device up to do MDIO operations
3055 */
3056static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3057{
3058 int err;
3059 struct vortex_private *vp = netdev_priv(dev);
3060 long ioaddr = dev->base_addr;
3061 unsigned long flags;
3062 int state = 0;
3063
3064 if(VORTEX_PCI(vp))
3065 state = VORTEX_PCI(vp)->current_state;
3066
3067 /* The kernel core really should have pci_get_power_state() */
3068
3069 if(state != 0)
3070 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3071 spin_lock_irqsave(&vp->lock, flags);
3072 EL3WINDOW(4);
3073 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3074 spin_unlock_irqrestore(&vp->lock, flags);
3075 if(state != 0)
3076 pci_set_power_state(VORTEX_PCI(vp), state);
3077
3078 return err;
3079}
3080#endif
3081
3082
3083/* Pre-Cyclone chips have no documented multicast filter, so the only
3084 multicast setting is to receive all multicast frames. At least
3085 the chip has a very clean way to set the mode, unlike many others. */
3086static void set_rx_mode(struct net_device *dev)
3087{
3088 long ioaddr = dev->base_addr;
3089 int new_mode;
3090
3091 if (dev->flags & IFF_PROMISC) {
3092 if (vortex_debug > 0)
3093 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3094 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3095 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3096 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3097 } else
3098 new_mode = SetRxFilter | RxStation | RxBroadcast;
3099
3100 outw(new_mode, ioaddr + EL3_CMD);
3101}
3102
3103#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3104/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3105 Note that this must be done after each RxReset due to some backwards
3106 compatibility logic in the Cyclone and Tornado ASICs */
3107
3108/* The Ethernet Type used for 802.1q tagged frames */
3109#define VLAN_ETHER_TYPE 0x8100
3110
3111static void set_8021q_mode(struct net_device *dev, int enable)
3112{
3113 struct vortex_private *vp = netdev_priv(dev);
3114 long ioaddr = dev->base_addr;
3115 int old_window = inw(ioaddr + EL3_CMD);
3116 int mac_ctrl;
3117
3118 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3119 /* cyclone and tornado chipsets can recognize 802.1q
3120 * tagged frames and treat them correctly */
3121
3122 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3123 if (enable)
3124 max_pkt_size += 4; /* 802.1Q VLAN tag */
3125
3126 EL3WINDOW(3);
3127 outw(max_pkt_size, ioaddr+Wn3_MaxPktSize);
3128
3129 /* set VlanEtherType to let the hardware checksumming
3130 treat tagged frames correctly */
3131 EL3WINDOW(7);
3132 outw(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
3133 } else {
3134 /* on older cards we have to enable large frames */
3135
3136 vp->large_frames = dev->mtu > 1500 || enable;
3137
3138 EL3WINDOW(3);
3139 mac_ctrl = inw(ioaddr+Wn3_MAC_Ctrl);
3140 if (vp->large_frames)
3141 mac_ctrl |= 0x40;
3142 else
3143 mac_ctrl &= ~0x40;
3144 outw(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3145 }
3146
3147 EL3WINDOW(old_window);
3148}
3149#else
3150
3151static void set_8021q_mode(struct net_device *dev, int enable)
3152{
3153}
3154
3155
3156#endif
3157
3158/* MII transceiver control section.
3159 Read and write the MII registers using software-generated serial
3160 MDIO protocol. See the MII specifications or DP83840A data sheet
3161 for details. */
3162
3163/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3164 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3165 "overclocking" issues. */
3166#define mdio_delay() inl(mdio_addr)
3167
3168#define MDIO_SHIFT_CLK 0x01
3169#define MDIO_DIR_WRITE 0x04
3170#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3171#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3172#define MDIO_DATA_READ 0x02
3173#define MDIO_ENB_IN 0x00
3174
3175/* Generate the preamble required for initial synchronization and
3176 a few older transceivers. */
3177static void mdio_sync(long ioaddr, int bits)
3178{
3179 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3180
3181 /* Establish sync by sending at least 32 logic ones. */
3182 while (-- bits >= 0) {
3183 outw(MDIO_DATA_WRITE1, mdio_addr);
3184 mdio_delay();
3185 outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3186 mdio_delay();
3187 }
3188}
3189
3190static int mdio_read(struct net_device *dev, int phy_id, int location)
3191{
3192 int i;
3193 long ioaddr = dev->base_addr;
3194 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3195 unsigned int retval = 0;
3196 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3197
3198 if (mii_preamble_required)
3199 mdio_sync(ioaddr, 32);
3200
3201 /* Shift the read command bits out. */
3202 for (i = 14; i >= 0; i--) {
3203 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3204 outw(dataval, mdio_addr);
3205 mdio_delay();
3206 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
3207 mdio_delay();
3208 }
3209 /* Read the two transition, 16 data, and wire-idle bits. */
3210 for (i = 19; i > 0; i--) {
3211 outw(MDIO_ENB_IN, mdio_addr);
3212 mdio_delay();
3213 retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3214 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3215 mdio_delay();
3216 }
3217 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3218}
3219
3220static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3221{
3222 long ioaddr = dev->base_addr;
3223 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3224 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3225 int i;
3226
3227 if (mii_preamble_required)
3228 mdio_sync(ioaddr, 32);
3229
3230 /* Shift the command bits out. */
3231 for (i = 31; i >= 0; i--) {
3232 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3233 outw(dataval, mdio_addr);
3234 mdio_delay();
3235 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
3236 mdio_delay();
3237 }
3238 /* Leave the interface idle. */
3239 for (i = 1; i >= 0; i--) {
3240 outw(MDIO_ENB_IN, mdio_addr);
3241 mdio_delay();
3242 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3243 mdio_delay();
3244 }
3245 return;
3246}
3247\f
3248/* ACPI: Advanced Configuration and Power Interface. */
3249/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3250static void acpi_set_WOL(struct net_device *dev)
3251{
3252 struct vortex_private *vp = netdev_priv(dev);
3253 long ioaddr = dev->base_addr;
3254
3255 if (vp->enable_wol) {
3256 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3257 EL3WINDOW(7);
3258 outw(2, ioaddr + 0x0c);
3259 /* The RxFilter must accept the WOL frames. */
3260 outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3261 outw(RxEnable, ioaddr + EL3_CMD);
3262
3263 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3264
3265 /* Change the power state to D3; RxEnable doesn't take effect. */
3266 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3267 }
1da177e4
LT		 3268}
3269
3270
3271static void __devexit vortex_remove_one (struct pci_dev *pdev)
3272{
3273 struct net_device *dev = pci_get_drvdata(pdev);
3274 struct vortex_private *vp;
3275
3276 if (!dev) {
3277 printk("vortex_remove_one called for Compaq device!\n");
3278 BUG();
3279 }
3280
3281 vp = netdev_priv(dev);
3282
3283 /* AKPM: FIXME: we should have
3284 * if (vp->cb_fn_base) iounmap(vp->cb_fn_base);
3285 * here
3286 */
3287 unregister_netdev(dev);
3288
3289 if (VORTEX_PCI(vp)) {
3290 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3291 if (vp->pm_state_valid)
3292 pci_restore_state(VORTEX_PCI(vp));
3293 pci_disable_device(VORTEX_PCI(vp));
3294 }
3295 /* Should really use issue_and_wait() here */
3296 outw(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3297 dev->base_addr + EL3_CMD);
3298
3299 pci_free_consistent(pdev,
3300 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3301 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3302 vp->rx_ring,
3303 vp->rx_ring_dma);
3304 if (vp->must_free_region)
3305 release_region(dev->base_addr, vp->io_size);
3306 free_netdev(dev);
3307}
3308
3309
3310static struct pci_driver vortex_driver = {
3311 .name = "3c59x",
3312 .probe = vortex_init_one,
3313 .remove = __devexit_p(vortex_remove_one),
3314 .id_table = vortex_pci_tbl,
3315#ifdef CONFIG_PM
3316 .suspend = vortex_suspend,
3317 .resume = vortex_resume,
3318#endif
3319};
3320
3321
3322static int vortex_have_pci;
3323static int vortex_have_eisa;
3324
3325
3326static int __init vortex_init (void)
3327{
3328 int pci_rc, eisa_rc;
3329
3330 pci_rc = pci_module_init(&vortex_driver);
3331 eisa_rc = vortex_eisa_init();
3332
3333 if (pci_rc == 0)
3334 vortex_have_pci = 1;
3335 if (eisa_rc > 0)
3336 vortex_have_eisa = 1;
3337
3338 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3339}
3340
3341
3342static void __exit vortex_eisa_cleanup (void)
3343{
3344 struct vortex_private *vp;
3345 long ioaddr;
3346
3347#ifdef CONFIG_EISA
3348 /* Take care of the EISA devices */
3349 eisa_driver_unregister (&vortex_eisa_driver);
3350#endif
3351
3352 if (compaq_net_device) {
3353 vp = compaq_net_device->priv;
3354 ioaddr = compaq_net_device->base_addr;
3355
3356 unregister_netdev (compaq_net_device);
3357 outw (TotalReset, ioaddr + EL3_CMD);
3358 release_region (ioaddr, VORTEX_TOTAL_SIZE);
3359
3360 free_netdev (compaq_net_device);
3361 }
3362}
3363
3364
3365static void __exit vortex_cleanup (void)
3366{
3367 if (vortex_have_pci)
3368 pci_unregister_driver (&vortex_driver);
3369 if (vortex_have_eisa)
3370 vortex_eisa_cleanup ();
3371}
3372
3373
3374module_init(vortex_init);
3375module_exit(vortex_cleanup);
3376
3377\f
3378/*
3379 * Local variables:
3380 * c-indent-level: 4
3381 * c-basic-offset: 4
3382 * tab-width: 4
3383 * End:
3384 */
Clone of davem's net-next-2.6 tree