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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
1da177e4
LT		 93#include <asm/irq.h> /* For NR_IRQS only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
106DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
1f1bd5fc 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
1f1bd5fc 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
541 u32 next; /* Last entry points to 0. */
542 s32 status;
543 u32 addr; /* Up to 63 addr/len pairs possible. */
544 s32 length; /* Set LAST_FRAG to indicate last pair. */
545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
561 u32 next; /* Last entry points to 0. */
562 s32 status; /* bits 0:12 length, others see below. */
563#if DO_ZEROCOPY
564 struct {
565 u32 addr;
566 s32 length;
567 } frag[1+MAX_SKB_FRAGS];
568#else
569 u32 addr;
570 s32 length;
571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
62afe595
JL		 610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 623 full_duplex:1, autoselect:1,
1da177e4
LT		 624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647};
648
649#ifdef CONFIG_PCI
650#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651#else
652#define DEVICE_PCI(dev) NULL
653#endif
654
655#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657#ifdef CONFIG_EISA
658#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659#else
660#define DEVICE_EISA(dev) NULL
661#endif
662
663#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665/* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671};
672
f71e1309 673static const struct media_table {
1da177e4
LT		 674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679} media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691};
692
693static struct {
694 const char str[ETH_GSTRING_LEN];
695} ethtool_stats_keys[] = {
696 { "tx_deferred" },
8d1d0340 697 { "tx_max_collisions" },
1da177e4 698 { "tx_multiple_collisions" },
8d1d0340 699 { "tx_single_collisions" },
1da177e4
LT		 700 { "rx_bad_ssd" },
701};
702
703/* number of ETHTOOL_GSTATS u64's */
8d1d0340 704#define VORTEX_NUM_STATS 5
1da177e4 705
62afe595 706static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 707 int chip_idx, int card_idx);
708static void vortex_up(struct net_device *dev);
709static void vortex_down(struct net_device *dev, int final);
710static int vortex_open(struct net_device *dev);
62afe595 711static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 712static int mdio_read(struct net_device *dev, int phy_id, int location);
713static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714static void vortex_timer(unsigned long arg);
715static void rx_oom_timer(unsigned long arg);
716static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718static int vortex_rx(struct net_device *dev);
719static int boomerang_rx(struct net_device *dev);
720static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
721static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
722static int vortex_close(struct net_device *dev);
723static void dump_tx_ring(struct net_device *dev);
62afe595 724static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 725static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726static void set_rx_mode(struct net_device *dev);
727#ifdef CONFIG_PCI
728static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729#endif
730static void vortex_tx_timeout(struct net_device *dev);
731static void acpi_set_WOL(struct net_device *dev);
732static struct ethtool_ops vortex_ethtool_ops;
733static void set_8021q_mode(struct net_device *dev, int enable);
734
1da177e4
LT		 735/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736/* Option count limit only -- unlimited interfaces are supported. */
737#define MAX_UNITS 8
9954ab7f
JL		 738static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 743static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 744static int global_options = -1;
745static int global_full_duplex = -1;
746static int global_enable_wol = -1;
900fd17d 747static int global_use_mmio = -1;
1da177e4 748
1da177e4
LT		 749/* Variables to work-around the Compaq PCI BIOS32 problem. */
750static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751static struct net_device *compaq_net_device;
752
753static int vortex_cards_found;
754
755module_param(debug, int, 0);
756module_param(global_options, int, 0);
757module_param_array(options, int, NULL, 0);
758module_param(global_full_duplex, int, 0);
759module_param_array(full_duplex, int, NULL, 0);
760module_param_array(hw_checksums, int, NULL, 0);
761module_param_array(flow_ctrl, int, NULL, 0);
762module_param(global_enable_wol, int, 0);
763module_param_array(enable_wol, int, NULL, 0);
764module_param(rx_copybreak, int, 0);
765module_param(max_interrupt_work, int, 0);
766module_param(compaq_ioaddr, int, 0);
767module_param(compaq_irq, int, 0);
768module_param(compaq_device_id, int, 0);
769module_param(watchdog, int, 0);
900fd17d
JL		 770module_param(global_use_mmio, int, 0);
771module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 772MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 776MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 777MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 780MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 781MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 787MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 789
790#ifdef CONFIG_NET_POLL_CONTROLLER
791static void poll_vortex(struct net_device *dev)
792{
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
795 local_save_flags(flags);
796 local_irq_disable();
797 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
798 local_irq_restore(flags);
799}
800#endif
801
802#ifdef CONFIG_PM
803
a880c4cd 804static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 805{
806 struct net_device *dev = pci_get_drvdata(pdev);
807
808 if (dev && dev->priv) {
809 if (netif_running(dev)) {
810 netif_device_detach(dev);
811 vortex_down(dev, 1);
812 }
5b039e68
RW		 813 pci_save_state(pdev);
814 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
815 free_irq(dev->irq, dev);
816 pci_disable_device(pdev);
817 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 818 }
819 return 0;
820}
821
a880c4cd 822static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 823{
824 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 825 struct vortex_private *vp = netdev_priv(dev);
1da177e4 826
5b039e68
RW		 827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
830 pci_enable_device(pdev);
831 pci_set_master(pdev);
832 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 833 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 834 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
835 pci_disable_device(pdev);
836 return -EBUSY;
837 }
1da177e4
LT		 838 if (netif_running(dev)) {
839 vortex_up(dev);
840 netif_device_attach(dev);
841 }
842 }
843 return 0;
844}
845
846#endif /* CONFIG_PM */
847
848#ifdef CONFIG_EISA
849static struct eisa_device_id vortex_eisa_ids[] = {
850 { "TCM5920", CH_3C592 },
851 { "TCM5970", CH_3C597 },
852 { "" }
853};
854
a880c4cd
SK		 855static int vortex_eisa_probe(struct device *device);
856static int vortex_eisa_remove(struct device *device);
1da177e4
LT		 857
858static struct eisa_driver vortex_eisa_driver = {
859 .id_table = vortex_eisa_ids,
860 .driver = {
861 .name = "3c59x",
862 .probe = vortex_eisa_probe,
863 .remove = vortex_eisa_remove
864 }
865};
866
a880c4cd 867static int vortex_eisa_probe(struct device *device)
1da177e4 868{
62afe595 869 void __iomem *ioaddr;
1da177e4
LT		 870 struct eisa_device *edev;
871
a880c4cd 872 edev = to_eisa_device(device);
1da177e4 873
62afe595 874 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 875 return -EBUSY;
876
62afe595
JL		 877 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
878
879 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 880 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 881 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 882 return -ENODEV;
883 }
884
885 vortex_cards_found++;
886
887 return 0;
888}
889
a880c4cd 890static int vortex_eisa_remove(struct device *device)
1da177e4
LT		 891{
892 struct eisa_device *edev;
893 struct net_device *dev;
894 struct vortex_private *vp;
62afe595 895 void __iomem *ioaddr;
1da177e4 896
a880c4cd
SK		 897 edev = to_eisa_device(device);
898 dev = eisa_get_drvdata(edev);
1da177e4
LT		 899
900 if (!dev) {
901 printk("vortex_eisa_remove called for Compaq device!\n");
902 BUG();
903 }
904
905 vp = netdev_priv(dev);
62afe595 906 ioaddr = vp->ioaddr;
1da177e4 907
a880c4cd
SK		 908 unregister_netdev(dev);
909 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
910 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 911
a880c4cd 912 free_netdev(dev);
1da177e4
LT		 913 return 0;
914}
915#endif
916
917/* returns count found (>= 0), or negative on error */
a880c4cd 918static int __init vortex_eisa_init(void)
1da177e4
LT		 919{
920 int eisa_found = 0;
921 int orig_cards_found = vortex_cards_found;
922
923#ifdef CONFIG_EISA
c2f6fabb
BH		 924 int err;
925
926 err = eisa_driver_register (&vortex_eisa_driver);
927 if (!err) {
928 /*
929 * Because of the way EISA bus is probed, we cannot assume
930 * any device have been found when we exit from
931 * eisa_driver_register (the bus root driver may not be
932 * initialized yet). So we blindly assume something was
933 * found, and let the sysfs magic happend...
934 */
935 eisa_found = 1;
1da177e4
LT		 936 }
937#endif
938
939 /* Special code to work-around the Compaq PCI BIOS32 problem. */
940 if (compaq_ioaddr) {
62afe595
JL		 941 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
942 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 943 }
944
945 return vortex_cards_found - orig_cards_found + eisa_found;
946}
947
948/* returns count (>= 0), or negative on error */
a880c4cd 949static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 950 const struct pci_device_id *ent)
951{
900fd17d
JL		 952 int rc, unit, pci_bar;
953 struct vortex_chip_info *vci;
954 void __iomem *ioaddr;
1da177e4
LT		 955
956 /* wake up and enable device */
a880c4cd 957 rc = pci_enable_device(pdev);
1da177e4
LT		 958 if (rc < 0)
959 goto out;
960
900fd17d
JL		 961 unit = vortex_cards_found;
962
963 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
964 /* Determine the default if the user didn't override us */
965 vci = &vortex_info_tbl[ent->driver_data];
966 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
967 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
968 pci_bar = use_mmio[unit] ? 1 : 0;
969 else
970 pci_bar = global_use_mmio ? 1 : 0;
971
972 ioaddr = pci_iomap(pdev, pci_bar, 0);
973 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
974 ioaddr = pci_iomap(pdev, 0, 0);
975
976 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
977 ent->driver_data, unit);
1da177e4 978 if (rc < 0) {
a880c4cd 979 pci_disable_device(pdev);
1da177e4
LT		 980 goto out;
981 }
982
983 vortex_cards_found++;
984
985out:
986 return rc;
987}
988
989/*
990 * Start up the PCI/EISA device which is described by *gendev.
991 * Return 0 on success.
992 *
993 * NOTE: pdev can be NULL, for the case of a Compaq device
994 */
995static int __devinit vortex_probe1(struct device *gendev,
62afe595 996 void __iomem *ioaddr, int irq,
1da177e4
LT		 997 int chip_idx, int card_idx)
998{
999 struct vortex_private *vp;
1000 int option;
1001 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1002 int i, step;
1003 struct net_device *dev;
1004 static int printed_version;
1005 int retval, print_info;
1006 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1007 char *print_name = "3c59x";
1008 struct pci_dev *pdev = NULL;
1009 struct eisa_device *edev = NULL;
1010
1011 if (!printed_version) {
1012 printk (version);
1013 printed_version = 1;
1014 }
1015
1016 if (gendev) {
1017 if ((pdev = DEVICE_PCI(gendev))) {
1018 print_name = pci_name(pdev);
1019 }
1020
1021 if ((edev = DEVICE_EISA(gendev))) {
1022 print_name = edev->dev.bus_id;
1023 }
1024 }
1025
1026 dev = alloc_etherdev(sizeof(*vp));
1027 retval = -ENOMEM;
1028 if (!dev) {
1029 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1030 goto out;
1031 }
1032 SET_MODULE_OWNER(dev);
1033 SET_NETDEV_DEV(dev, gendev);
1034 vp = netdev_priv(dev);
1035
1036 option = global_options;
1037
1038 /* The lower four bits are the media type. */
1039 if (dev->mem_start) {
1040 /*
1041 * The 'options' param is passed in as the third arg to the
1042 * LILO 'ether=' argument for non-modular use
1043 */
1044 option = dev->mem_start;
1045 }
1046 else if (card_idx < MAX_UNITS) {
1047 if (options[card_idx] >= 0)
1048 option = options[card_idx];
1049 }
1050
1051 if (option > 0) {
1052 if (option & 0x8000)
1053 vortex_debug = 7;
1054 if (option & 0x4000)
1055 vortex_debug = 2;
1056 if (option & 0x0400)
1057 vp->enable_wol = 1;
1058 }
1059
1060 print_info = (vortex_debug > 1);
1061 if (print_info)
1062 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1063
61238602 1064 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1065 print_name,
1066 pdev ? "PCI" : "EISA",
1067 vci->name,
1068 ioaddr);
1069
62afe595 1070 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1071 dev->irq = irq;
1072 dev->mtu = mtu;
62afe595 1073 vp->ioaddr = ioaddr;
1da177e4
LT		 1074 vp->large_frames = mtu > 1500;
1075 vp->drv_flags = vci->drv_flags;
1076 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1077 vp->io_size = vci->io_size;
1078 vp->card_idx = card_idx;
1079
1080 /* module list only for Compaq device */
1081 if (gendev == NULL) {
1082 compaq_net_device = dev;
1083 }
1084
1085 /* PCI-only startup logic */
1086 if (pdev) {
1087 /* EISA resources already marked, so only PCI needs to do this here */
1088 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1089 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1090 vp->must_free_region = 1;
1091
1092 /* enable bus-mastering if necessary */
1093 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1094 pci_set_master(pdev);
1da177e4
LT		 1095
1096 if (vci->drv_flags & IS_VORTEX) {
1097 u8 pci_latency;
1098 u8 new_latency = 248;
1099
1100 /* Check the PCI latency value. On the 3c590 series the latency timer
1101 must be set to the maximum value to avoid data corruption that occurs
1102 when the timer expires during a transfer. This bug exists the Vortex
1103 chip only. */
1104 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1105 if (pci_latency < new_latency) {
1106 printk(KERN_INFO "%s: Overriding PCI latency"
1107 " timer (CFLT) setting of %d, new value is %d.\n",
1108 print_name, pci_latency, new_latency);
1109 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1110 }
1111 }
1112 }
1113
1114 spin_lock_init(&vp->lock);
1115 vp->gendev = gendev;
1116 vp->mii.dev = dev;
1117 vp->mii.mdio_read = mdio_read;
1118 vp->mii.mdio_write = mdio_write;
1119 vp->mii.phy_id_mask = 0x1f;
1120 vp->mii.reg_num_mask = 0x1f;
1121
1122 /* Makes sure rings are at least 16 byte aligned. */
1123 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1124 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1125 &vp->rx_ring_dma);
1126 retval = -ENOMEM;
1127 if (vp->rx_ring == 0)
1128 goto free_region;
1129
1130 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1131 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1132
1133 /* if we are a PCI driver, we store info in pdev->driver_data
1134 * instead of a module list */
1135 if (pdev)
1136 pci_set_drvdata(pdev, dev);
1137 if (edev)
a880c4cd 1138 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1139
1140 vp->media_override = 7;
1141 if (option >= 0) {
1142 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1143 if (vp->media_override != 7)
1144 vp->medialock = 1;
1145 vp->full_duplex = (option & 0x200) ? 1 : 0;
1146 vp->bus_master = (option & 16) ? 1 : 0;
1147 }
1148
1149 if (global_full_duplex > 0)
1150 vp->full_duplex = 1;
1151 if (global_enable_wol > 0)
1152 vp->enable_wol = 1;
1153
1154 if (card_idx < MAX_UNITS) {
1155 if (full_duplex[card_idx] > 0)
1156 vp->full_duplex = 1;
1157 if (flow_ctrl[card_idx] > 0)
1158 vp->flow_ctrl = 1;
1159 if (enable_wol[card_idx] > 0)
1160 vp->enable_wol = 1;
1161 }
1162
125d5ce8 1163 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1164 vp->options = option;
1165 /* Read the station address from the EEPROM. */
1166 EL3WINDOW(0);
1167 {
1168 int base;
1169
1170 if (vci->drv_flags & EEPROM_8BIT)
1171 base = 0x230;
1172 else if (vci->drv_flags & EEPROM_OFFSET)
1173 base = EEPROM_Read + 0x30;
1174 else
1175 base = EEPROM_Read;
1176
1177 for (i = 0; i < 0x40; i++) {
1178 int timer;
62afe595 1179 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1180 /* Pause for at least 162 us. for the read to take place. */
1181 for (timer = 10; timer >= 0; timer--) {
1182 udelay(162);
62afe595 1183 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1184 break;
1185 }
62afe595 1186 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1187 }
1188 }
1189 for (i = 0; i < 0x18; i++)
1190 checksum ^= eeprom[i];
1191 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1192 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1193 while (i < 0x21)
1194 checksum ^= eeprom[i++];
1195 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1196 }
1197 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1198 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1199 for (i = 0; i < 3; i++)
1200 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1201 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1202 if (print_info) {
1203 for (i = 0; i < 6; i++)
1204 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1205 }
1206 /* Unfortunately an all zero eeprom passes the checksum and this
1207 gets found in the wild in failure cases. Crypto is hard 8) */
1208 if (!is_valid_ether_addr(dev->dev_addr)) {
1209 retval = -EINVAL;
1210 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1211 goto free_ring; /* With every pack */
1212 }
1213 EL3WINDOW(2);
1214 for (i = 0; i < 6; i++)
62afe595 1215 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1216
1da177e4
LT		 1217 if (print_info)
1218 printk(", IRQ %d\n", dev->irq);
1219 /* Tell them about an invalid IRQ. */
1220 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1221 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1222 dev->irq);
1da177e4
LT		 1223
1224 EL3WINDOW(4);
62afe595 1225 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1226 if (print_info) {
1227 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1228 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1229 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1230 }
1231
1232
1233 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1234 unsigned short n;
1235
62afe595
JL		 1236 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1237 if (!vp->cb_fn_base) {
1da177e4 1238 retval = -ENOMEM;
62afe595 1239 goto free_ring;
1da177e4 1240 }
62afe595 1241
1da177e4 1242 if (print_info) {
7c7459d1
GKH		 1243 printk(KERN_INFO "%s: CardBus functions mapped "
1244 "%16.16llx->%p\n",
1245 print_name,
1246 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1247 vp->cb_fn_base);
1da177e4
LT		 1248 }
1249 EL3WINDOW(2);
1250
62afe595 1251 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1252 if (vp->drv_flags & INVERT_LED_PWR)
1253 n |= 0x10;
1254 if (vp->drv_flags & INVERT_MII_PWR)
1255 n |= 0x4000;
62afe595 1256 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1257 if (vp->drv_flags & WNO_XCVR_PWR) {
1258 EL3WINDOW(0);
62afe595 1259 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1260 }
1261 }
1262
1263 /* Extract our information from the EEPROM data. */
1264 vp->info1 = eeprom[13];
1265 vp->info2 = eeprom[15];
1266 vp->capabilities = eeprom[16];
1267
1268 if (vp->info1 & 0x8000) {
1269 vp->full_duplex = 1;
1270 if (print_info)
1271 printk(KERN_INFO "Full duplex capable\n");
1272 }
1273
1274 {
f71e1309 1275 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1276 unsigned int config;
1277 EL3WINDOW(3);
62afe595 1278 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1279 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1280 vp->available_media = 0x40;
62afe595 1281 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1282 if (print_info) {
1283 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1284 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1285 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1286 8 << RAM_SIZE(config),
1287 RAM_WIDTH(config) ? "word" : "byte",
1288 ram_split[RAM_SPLIT(config)],
1289 AUTOSELECT(config) ? "autoselect/" : "",
1290 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1291 media_tbl[XCVR(config)].name);
1292 }
1293 vp->default_media = XCVR(config);
1294 if (vp->default_media == XCVR_NWAY)
1295 vp->has_nway = 1;
1296 vp->autoselect = AUTOSELECT(config);
1297 }
1298
1299 if (vp->media_override != 7) {
1300 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1301 print_name, vp->media_override,
1302 media_tbl[vp->media_override].name);
1303 dev->if_port = vp->media_override;
1304 } else
1305 dev->if_port = vp->default_media;
1306
1307 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1308 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1309 int phy, phy_idx = 0;
1310 EL3WINDOW(4);
1311 mii_preamble_required++;
1312 if (vp->drv_flags & EXTRA_PREAMBLE)
1313 mii_preamble_required++;
1314 mdio_sync(ioaddr, 32);
106427e6 1315 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1316 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1317 int mii_status, phyx;
1318
1319 /*
1320 * For the 3c905CX we look at index 24 first, because it bogusly
1321 * reports an external PHY at all indices
1322 */
1323 if (phy == 0)
1324 phyx = 24;
1325 else if (phy <= 24)
1326 phyx = phy - 1;
1327 else
1328 phyx = phy;
106427e6 1329 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1330 if (mii_status && mii_status != 0xffff) {
1331 vp->phys[phy_idx++] = phyx;
1332 if (print_info) {
1333 printk(KERN_INFO " MII transceiver found at address %d,"
1334 " status %4x.\n", phyx, mii_status);
1335 }
1336 if ((mii_status & 0x0040) == 0)
1337 mii_preamble_required++;
1338 }
1339 }
1340 mii_preamble_required--;
1341 if (phy_idx == 0) {
1342 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1343 vp->phys[0] = 24;
1344 } else {
106427e6 1345 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1346 if (vp->full_duplex) {
1347 /* Only advertise the FD media types. */
1348 vp->advertising &= ~0x02A0;
1349 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1350 }
1351 }
1352 vp->mii.phy_id = vp->phys[0];
1353 }
1354
1355 if (vp->capabilities & CapBusMaster) {
1356 vp->full_bus_master_tx = 1;
1357 if (print_info) {
1358 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1359 (vp->info2 & 1) ? "early" : "whole-frame" );
1360 }
1361 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1362 vp->bus_master = 0; /* AKPM: vortex only */
1363 }
1364
1365 /* The 3c59x-specific entries in the device structure. */
1366 dev->open = vortex_open;
1367 if (vp->full_bus_master_tx) {
1368 dev->hard_start_xmit = boomerang_start_xmit;
1369 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1370 if (card_idx < MAX_UNITS &&
1371 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1372 hw_checksums[card_idx] == 1)) {
d311b0d3 1373 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1374 }
1375 } else {
1376 dev->hard_start_xmit = vortex_start_xmit;
1377 }
1378
1379 if (print_info) {
1380 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1381 print_name,
1382 (dev->features & NETIF_F_SG) ? "en":"dis",
1383 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1384 }
1385
1386 dev->stop = vortex_close;
1387 dev->get_stats = vortex_get_stats;
1388#ifdef CONFIG_PCI
1389 dev->do_ioctl = vortex_ioctl;
1390#endif
1391 dev->ethtool_ops = &vortex_ethtool_ops;
1392 dev->set_multicast_list = set_rx_mode;
1393 dev->tx_timeout = vortex_tx_timeout;
1394 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1395#ifdef CONFIG_NET_POLL_CONTROLLER
1396 dev->poll_controller = poll_vortex;
1397#endif
1398 if (pdev) {
1399 vp->pm_state_valid = 1;
1400 pci_save_state(VORTEX_PCI(vp));
1401 acpi_set_WOL(dev);
1402 }
1403 retval = register_netdev(dev);
1404 if (retval == 0)
1405 return 0;
1406
1407free_ring:
1408 pci_free_consistent(pdev,
1409 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1410 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1411 vp->rx_ring,
1412 vp->rx_ring_dma);
1413free_region:
1414 if (vp->must_free_region)
62afe595 1415 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1416 free_netdev(dev);
1417 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1418out:
1419 return retval;
1420}
1421
1422static void
1423issue_and_wait(struct net_device *dev, int cmd)
1424{
62afe595
JL		 1425 struct vortex_private *vp = netdev_priv(dev);
1426 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1427 int i;
1428
62afe595 1429 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1430 for (i = 0; i < 2000; i++) {
62afe595 1431 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1432 return;
1433 }
1434
1435 /* OK, that didn't work. Do it the slow way. One second */
1436 for (i = 0; i < 100000; i++) {
62afe595 1437 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1438 if (vortex_debug > 1)
1439 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1440 dev->name, cmd, i * 10);
1441 return;
1442 }
1443 udelay(10);
1444 }
1445 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1446 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1447}
1448
125d5ce8
SK		 1449static void
1450vortex_set_duplex(struct net_device *dev)
1451{
1452 struct vortex_private *vp = netdev_priv(dev);
1453 void __iomem *ioaddr = vp->ioaddr;
1454
1455 printk(KERN_INFO "%s: setting %s-duplex.\n",
1456 dev->name, (vp->full_duplex) ? "full" : "half");
1457
1458 EL3WINDOW(3);
1459 /* Set the full-duplex bit. */
1460 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1461 (vp->large_frames ? 0x40 : 0) |
1462 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1463 0x100 : 0),
1464 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1465}
1466
1467static void vortex_check_media(struct net_device *dev, unsigned int init)
1468{
1469 struct vortex_private *vp = netdev_priv(dev);
1470 unsigned int ok_to_print = 0;
1471
1472 if (vortex_debug > 3)
1473 ok_to_print = 1;
1474
1475 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1476 vp->full_duplex = vp->mii.full_duplex;
1477 vortex_set_duplex(dev);
1478 } else if (init) {
1479 vortex_set_duplex(dev);
1480 }
1481}
1482
1da177e4
LT		 1483static void
1484vortex_up(struct net_device *dev)
1485{
1da177e4 1486 struct vortex_private *vp = netdev_priv(dev);
62afe595 1487 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1488 unsigned int config;
09ce3512 1489 int i, mii_reg1, mii_reg5;
1da177e4
LT		 1490
1491 if (VORTEX_PCI(vp)) {
1492 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1493 if (vp->pm_state_valid)
1494 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1495 pci_enable_device(VORTEX_PCI(vp));
1496 }
1497
1498 /* Before initializing select the active media port. */
1499 EL3WINDOW(3);
62afe595 1500 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1501
1502 if (vp->media_override != 7) {
1503 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1504 dev->name, vp->media_override,
1505 media_tbl[vp->media_override].name);
1506 dev->if_port = vp->media_override;
1507 } else if (vp->autoselect) {
1508 if (vp->has_nway) {
1509 if (vortex_debug > 1)
1510 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1511 dev->name, dev->if_port);
1512 dev->if_port = XCVR_NWAY;
1513 } else {
1514 /* Find first available media type, starting with 100baseTx. */
1515 dev->if_port = XCVR_100baseTx;
1516 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1517 dev->if_port = media_tbl[dev->if_port].next;
1518 if (vortex_debug > 1)
1519 printk(KERN_INFO "%s: first available media type: %s\n",
1520 dev->name, media_tbl[dev->if_port].name);
1521 }
1522 } else {
1523 dev->if_port = vp->default_media;
1524 if (vortex_debug > 1)
1525 printk(KERN_INFO "%s: using default media %s\n",
1526 dev->name, media_tbl[dev->if_port].name);
1527 }
1528
1529 init_timer(&vp->timer);
1530 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1531 vp->timer.data = (unsigned long)dev;
1532 vp->timer.function = vortex_timer; /* timer handler */
1533 add_timer(&vp->timer);
1534
1535 init_timer(&vp->rx_oom_timer);
1536 vp->rx_oom_timer.data = (unsigned long)dev;
1537 vp->rx_oom_timer.function = rx_oom_timer;
1538
1539 if (vortex_debug > 1)
1540 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1541 dev->name, media_tbl[dev->if_port].name);
1542
125d5ce8 1543 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1544 config = BFINS(config, dev->if_port, 20, 4);
1545 if (vortex_debug > 6)
1546 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1547 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1548
1549 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1550 EL3WINDOW(4);
09ce3512
SK		 1551 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1552 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1553 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1554
125d5ce8 1555 vortex_check_media(dev, 1);
1da177e4 1556 }
125d5ce8
SK		 1557 else
1558 vortex_set_duplex(dev);
1da177e4 1559
09ce3512
SK		 1560 issue_and_wait(dev, TxReset);
1561 /*
1562 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1563 */
1564 issue_and_wait(dev, RxReset|0x04);
1565
1da177e4 1566
62afe595 1567 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1568
1569 if (vortex_debug > 1) {
1570 EL3WINDOW(4);
1571 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1572 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1573 }
1574
1575 /* Set the station address and mask in window 2 each time opened. */
1576 EL3WINDOW(2);
1577 for (i = 0; i < 6; i++)
62afe595 1578 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1579 for (; i < 12; i+=2)
62afe595 1580 iowrite16(0, ioaddr + i);
1da177e4
LT		 1581
1582 if (vp->cb_fn_base) {
62afe595 1583 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1584 if (vp->drv_flags & INVERT_LED_PWR)
1585 n |= 0x10;
1586 if (vp->drv_flags & INVERT_MII_PWR)
1587 n |= 0x4000;
62afe595 1588 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1589 }
1590
1591 if (dev->if_port == XCVR_10base2)
1592 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1593 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1594 if (dev->if_port != XCVR_NWAY) {
1595 EL3WINDOW(4);
62afe595 1596 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1597 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1598 }
1599
1600 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1601 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1602 EL3WINDOW(6);
1603 for (i = 0; i < 10; i++)
62afe595
JL		 1604 ioread8(ioaddr + i);
1605 ioread16(ioaddr + 10);
1606 ioread16(ioaddr + 12);
1da177e4
LT		 1607 /* New: On the Vortex we must also clear the BadSSD counter. */
1608 EL3WINDOW(4);
62afe595 1609 ioread8(ioaddr + 12);
1da177e4 1610 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1611 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1612
1613 /* Switch to register set 7 for normal use. */
1614 EL3WINDOW(7);
1615
1616 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1617 vp->cur_rx = vp->dirty_rx = 0;
1618 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1619 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1620 iowrite32(0x0020, ioaddr + PktStatus);
1621 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1622 }
1623 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1624 vp->cur_tx = vp->dirty_tx = 0;
1625 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1626 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1627 /* Clear the Rx, Tx rings. */
1628 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1629 vp->rx_ring[i].status = 0;
1630 for (i = 0; i < TX_RING_SIZE; i++)
1631 vp->tx_skbuff[i] = NULL;
62afe595 1632 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1633 }
1634 /* Set receiver mode: presumably accept b-case and phys addr only. */
1635 set_rx_mode(dev);
1636 /* enable 802.1q tagged frames */
1637 set_8021q_mode(dev, 1);
62afe595 1638 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1639
62afe595
JL		 1640 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1641 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1642 /* Allow status bits to be seen. */
1643 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1644 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1645 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1646 (vp->bus_master ? DMADone : 0);
1647 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1648 (vp->full_bus_master_rx ? 0 : RxComplete) |
1649 StatsFull | HostError | TxComplete | IntReq
1650 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1651 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1652 /* Ack all pending events, and set active indicator mask. */
62afe595 1653 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1654 ioaddr + EL3_CMD);
62afe595 1655 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1656 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1657 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1658 netif_start_queue (dev);
1659}
1660
1661static int
1662vortex_open(struct net_device *dev)
1663{
1664 struct vortex_private *vp = netdev_priv(dev);
1665 int i;
1666 int retval;
1667
1668 /* Use the now-standard shared IRQ implementation. */
1669 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1670 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4
LT		 1671 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1672 goto out;
1673 }
1674
1675 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1676 if (vortex_debug > 2)
1677 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1678 for (i = 0; i < RX_RING_SIZE; i++) {
1679 struct sk_buff *skb;
1680 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1681 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1682 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1683 skb = dev_alloc_skb(PKT_BUF_SZ);
1684 vp->rx_skbuff[i] = skb;
1685 if (skb == NULL)
1686 break; /* Bad news! */
1687 skb->dev = dev; /* Mark as being used by this device. */
1688 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1689 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1690 }
1691 if (i != RX_RING_SIZE) {
1692 int j;
1693 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1694 for (j = 0; j < i; j++) {
1695 if (vp->rx_skbuff[j]) {
1696 dev_kfree_skb(vp->rx_skbuff[j]);
1697 vp->rx_skbuff[j] = NULL;
1698 }
1699 }
1700 retval = -ENOMEM;
1701 goto out_free_irq;
1702 }
1703 /* Wrap the ring. */
1704 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1705 }
1706
1707 vortex_up(dev);
1708 return 0;
1709
1710out_free_irq:
1711 free_irq(dev->irq, dev);
1712out:
1713 if (vortex_debug > 1)
1714 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1715 return retval;
1716}
1717
1718static void
1719vortex_timer(unsigned long data)
1720{
1721 struct net_device *dev = (struct net_device *)data;
1722 struct vortex_private *vp = netdev_priv(dev);
62afe595 1723 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1724 int next_tick = 60*HZ;
1725 int ok = 0;
125d5ce8 1726 int media_status, old_window;
1da177e4
LT		 1727
1728 if (vortex_debug > 2) {
1729 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1730 dev->name, media_tbl[dev->if_port].name);
1731 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1732 }
1733
0a9da4bd 1734 disable_irq_lockdep(dev->irq);
62afe595 1735 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1736 EL3WINDOW(4);
62afe595 1737 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1738 switch (dev->if_port) {
1739 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1740 if (media_status & Media_LnkBeat) {
1741 netif_carrier_on(dev);
1742 ok = 1;
1743 if (vortex_debug > 1)
1744 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1745 dev->name, media_tbl[dev->if_port].name, media_status);
1746 } else {
1747 netif_carrier_off(dev);
1748 if (vortex_debug > 1) {
1749 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1750 dev->name, media_tbl[dev->if_port].name, media_status);
1751 }
1752 }
1753 break;
1754 case XCVR_MII: case XCVR_NWAY:
1755 {
1da177e4 1756 ok = 1;
125d5ce8
SK		 1757 spin_lock_bh(&vp->lock);
1758 vortex_check_media(dev, 0);
1da177e4
LT		 1759 spin_unlock_bh(&vp->lock);
1760 }
1761 break;
1762 default: /* Other media types handled by Tx timeouts. */
1763 if (vortex_debug > 1)
1764 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1765 dev->name, media_tbl[dev->if_port].name, media_status);
1766 ok = 1;
1767 }
b4ff6450
SK		 1768
1769 if (!netif_carrier_ok(dev))
1770 next_tick = 5*HZ;
1771
e94d10eb
SK		 1772 if (vp->medialock)
1773 goto leave_media_alone;
1774
a880c4cd 1775 if (!ok) {
1da177e4
LT		 1776 unsigned int config;
1777
1778 do {
1779 dev->if_port = media_tbl[dev->if_port].next;
1780 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1781 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1782 dev->if_port = vp->default_media;
1783 if (vortex_debug > 1)
1784 printk(KERN_DEBUG "%s: Media selection failing, using default "
1785 "%s port.\n",
1786 dev->name, media_tbl[dev->if_port].name);
1787 } else {
1788 if (vortex_debug > 1)
1789 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1790 "%s port.\n",
1791 dev->name, media_tbl[dev->if_port].name);
1792 next_tick = media_tbl[dev->if_port].wait;
1793 }
62afe595 1794 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1795 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1796
1797 EL3WINDOW(3);
62afe595 1798 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1799 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1800 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1801
62afe595 1802 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1803 ioaddr + EL3_CMD);
1804 if (vortex_debug > 1)
1805 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1806 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1807 }
1da177e4
LT		 1808
1809leave_media_alone:
1810 if (vortex_debug > 2)
1811 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1812 dev->name, media_tbl[dev->if_port].name);
1813
e94d10eb 1814 EL3WINDOW(old_window);
0a9da4bd 1815 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1816 mod_timer(&vp->timer, RUN_AT(next_tick));
1817 if (vp->deferred)
62afe595 1818 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1819 return;
1820}
1821
1822static void vortex_tx_timeout(struct net_device *dev)
1823{
1824 struct vortex_private *vp = netdev_priv(dev);
62afe595 1825 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1826
1827 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1828 dev->name, ioread8(ioaddr + TxStatus),
1829 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1830 EL3WINDOW(4);
1831 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1832 ioread16(ioaddr + Wn4_NetDiag),
1833 ioread16(ioaddr + Wn4_Media),
1834 ioread32(ioaddr + PktStatus),
1835 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1836 /* Slight code bloat to be user friendly. */
62afe595 1837 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1838 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1839 " network cable problem?\n", dev->name);
62afe595 1840 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1841 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1842 " IRQ blocked by another device?\n", dev->name);
1843 /* Bad idea here.. but we might as well handle a few events. */
1844 {
1845 /*
1846 * Block interrupts because vortex_interrupt does a bare spin_lock()
1847 */
1848 unsigned long flags;
1849 local_irq_save(flags);
1850 if (vp->full_bus_master_tx)
1851 boomerang_interrupt(dev->irq, dev, NULL);
1852 else
1853 vortex_interrupt(dev->irq, dev, NULL);
1854 local_irq_restore(flags);
1855 }
1856 }
1857
1858 if (vortex_debug > 0)
1859 dump_tx_ring(dev);
1860
1861 issue_and_wait(dev, TxReset);
1862
1863 vp->stats.tx_errors++;
1864 if (vp->full_bus_master_tx) {
1865 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1866 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1867 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1868 ioaddr + DownListPtr);
1869 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1870 netif_wake_queue (dev);
1871 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1872 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1873 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 1874 } else {
1875 vp->stats.tx_dropped++;
1876 netif_wake_queue(dev);
1877 }
1878
1879 /* Issue Tx Enable */
62afe595 1880 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1881 dev->trans_start = jiffies;
1882
1883 /* Switch to register set 7 for normal use. */
1884 EL3WINDOW(7);
1885}
1886
1887/*
1888 * Handle uncommon interrupt sources. This is a separate routine to minimize
1889 * the cache impact.
1890 */
1891static void
1892vortex_error(struct net_device *dev, int status)
1893{
1894 struct vortex_private *vp = netdev_priv(dev);
62afe595 1895 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1896 int do_tx_reset = 0, reset_mask = 0;
1897 unsigned char tx_status = 0;
1898
1899 if (vortex_debug > 2) {
1900 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1901 }
1902
1903 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1904 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1905 /* Presumably a tx-timeout. We must merely re-enable. */
1906 if (vortex_debug > 2
1907 || (tx_status != 0x88 && vortex_debug > 0)) {
1908 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1909 dev->name, tx_status);
1910 if (tx_status == 0x82) {
1911 printk(KERN_ERR "Probably a duplex mismatch. See "
1912 "Documentation/networking/vortex.txt\n");
1913 }
1914 dump_tx_ring(dev);
1915 }
1916 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1917 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
0000754c 1918 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1919 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1920 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1921 do_tx_reset = 1;
0000754c
AM		 1922 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1923 do_tx_reset = 1;
1924 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1925 } else { /* Merely re-enable the transmitter. */
62afe595 1926 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1927 }
1928 }
1929
1930 if (status & RxEarly) { /* Rx early is unused. */
1931 vortex_rx(dev);
62afe595 1932 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1933 }
1934 if (status & StatsFull) { /* Empty statistics. */
1935 static int DoneDidThat;
1936 if (vortex_debug > 4)
1937 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1938 update_stats(ioaddr, dev);
1939 /* HACK: Disable statistics as an interrupt source. */
1940 /* This occurs when we have the wrong media type! */
1941 if (DoneDidThat == 0 &&
62afe595 1942 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1943 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1944 "stats as an interrupt source.\n", dev->name);
1945 EL3WINDOW(5);
62afe595 1946 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1947 vp->intr_enable &= ~StatsFull;
1948 EL3WINDOW(7);
1949 DoneDidThat++;
1950 }
1951 }
1952 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1953 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1954 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1955 }
1956 if (status & HostError) {
1957 u16 fifo_diag;
1958 EL3WINDOW(4);
62afe595 1959 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 1960 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1961 dev->name, fifo_diag);
1962 /* Adapter failure requires Tx/Rx reset and reinit. */
1963 if (vp->full_bus_master_tx) {
62afe595 1964 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 1965 /* 0x80000000 PCI master abort. */
1966 /* 0x40000000 PCI target abort. */
1967 if (vortex_debug)
1968 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1969
1970 /* In this case, blow the card away */
1971 /* Must not enter D3 or we can't legally issue the reset! */
1972 vortex_down(dev, 0);
1973 issue_and_wait(dev, TotalReset | 0xff);
1974 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1975 } else if (fifo_diag & 0x0400)
1976 do_tx_reset = 1;
1977 if (fifo_diag & 0x3000) {
1978 /* Reset Rx fifo and upload logic */
1979 issue_and_wait(dev, RxReset|0x07);
1980 /* Set the Rx filter to the current state. */
1981 set_rx_mode(dev);
1982 /* enable 802.1q VLAN tagged frames */
1983 set_8021q_mode(dev, 1);
62afe595
JL		 1984 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1985 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 1986 }
1987 }
1988
1989 if (do_tx_reset) {
1990 issue_and_wait(dev, TxReset|reset_mask);
62afe595 1991 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1992 if (!vp->full_bus_master_tx)
1993 netif_wake_queue(dev);
1994 }
1995}
1996
1997static int
1998vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
1999{
2000 struct vortex_private *vp = netdev_priv(dev);
62afe595 2001 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2002
2003 /* Put out the doubleword header... */
62afe595 2004 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2005 if (vp->bus_master) {
2006 /* Set the bus-master controller to transfer the packet. */
2007 int len = (skb->len + 3) & ~3;
a880c4cd 2008 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2009 ioaddr + Wn7_MasterAddr);
62afe595 2010 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2011 vp->tx_skb = skb;
62afe595 2012 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2013 /* netif_wake_queue() will be called at the DMADone interrupt. */
2014 } else {
2015 /* ... and the packet rounded to a doubleword. */
62afe595 2016 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2017 dev_kfree_skb (skb);
62afe595 2018 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2019 netif_start_queue (dev); /* AKPM: redundant? */
2020 } else {
2021 /* Interrupt us when the FIFO has room for max-sized packet. */
2022 netif_stop_queue(dev);
62afe595 2023 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2024 }
2025 }
2026
2027 dev->trans_start = jiffies;
2028
2029 /* Clear the Tx status stack. */
2030 {
2031 int tx_status;
2032 int i = 32;
2033
62afe595 2034 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2035 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2036 if (vortex_debug > 2)
2037 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2038 dev->name, tx_status);
2039 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2040 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2041 if (tx_status & 0x30) {
2042 issue_and_wait(dev, TxReset);
2043 }
62afe595 2044 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2045 }
62afe595 2046 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2047 }
2048 }
2049 return 0;
2050}
2051
2052static int
2053boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2054{
2055 struct vortex_private *vp = netdev_priv(dev);
62afe595 2056 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2057 /* Calculate the next Tx descriptor entry. */
2058 int entry = vp->cur_tx % TX_RING_SIZE;
2059 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2060 unsigned long flags;
2061
2062 if (vortex_debug > 6) {
2063 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2064 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2065 dev->name, vp->cur_tx);
1da177e4
LT		 2066 }
2067
2068 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2069 if (vortex_debug > 0)
2070 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2071 dev->name);
2072 netif_stop_queue(dev);
2073 return 1;
2074 }
2075
2076 vp->tx_skbuff[entry] = skb;
2077
2078 vp->tx_ring[entry].next = 0;
2079#if DO_ZEROCOPY
2080 if (skb->ip_summed != CHECKSUM_HW)
2081 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2082 else
2083 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2084
2085 if (!skb_shinfo(skb)->nr_frags) {
2086 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2087 skb->len, PCI_DMA_TODEVICE));
2088 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2089 } else {
2090 int i;
2091
2092 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2093 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2094 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2095
2096 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2098
2099 vp->tx_ring[entry].frag[i+1].addr =
2100 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2101 (void*)page_address(frag->page) + frag->page_offset,
2102 frag->size, PCI_DMA_TODEVICE));
2103
2104 if (i == skb_shinfo(skb)->nr_frags-1)
2105 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2106 else
2107 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2108 }
2109 }
2110#else
2111 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2112 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2113 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2114#endif
2115
2116 spin_lock_irqsave(&vp->lock, flags);
2117 /* Wait for the stall to complete. */
2118 issue_and_wait(dev, DownStall);
2119 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2120 if (ioread32(ioaddr + DownListPtr) == 0) {
2121 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2122 vp->queued_packet++;
2123 }
2124
2125 vp->cur_tx++;
2126 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2127 netif_stop_queue (dev);
2128 } else { /* Clear previous interrupt enable. */
2129#if defined(tx_interrupt_mitigation)
2130 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2131 * were selected, this would corrupt DN_COMPLETE. No?
2132 */
2133 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2134#endif
2135 }
62afe595 2136 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2137 spin_unlock_irqrestore(&vp->lock, flags);
2138 dev->trans_start = jiffies;
2139 return 0;
2140}
2141
2142/* The interrupt handler does all of the Rx thread work and cleans up
2143 after the Tx thread. */
2144
2145/*
2146 * This is the ISR for the vortex series chips.
2147 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2148 */
2149
2150static irqreturn_t
2151vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2152{
2153 struct net_device *dev = dev_id;
2154 struct vortex_private *vp = netdev_priv(dev);
62afe595 2155 void __iomem *ioaddr;
1da177e4
LT		 2156 int status;
2157 int work_done = max_interrupt_work;
2158 int handled = 0;
2159
62afe595 2160 ioaddr = vp->ioaddr;
1da177e4
LT		 2161 spin_lock(&vp->lock);
2162
62afe595 2163 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2164
2165 if (vortex_debug > 6)
2166 printk("vortex_interrupt(). status=0x%4x\n", status);
2167
2168 if ((status & IntLatch) == 0)
2169 goto handler_exit; /* No interrupt: shared IRQs cause this */
2170 handled = 1;
2171
2172 if (status & IntReq) {
2173 status |= vp->deferred;
2174 vp->deferred = 0;
2175 }
2176
2177 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2178 goto handler_exit;
2179
2180 if (vortex_debug > 4)
2181 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2182 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2183
2184 do {
2185 if (vortex_debug > 5)
2186 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2187 dev->name, status);
2188 if (status & RxComplete)
2189 vortex_rx(dev);
2190
2191 if (status & TxAvailable) {
2192 if (vortex_debug > 5)
2193 printk(KERN_DEBUG " TX room bit was handled.\n");
2194 /* There's room in the FIFO for a full-sized packet. */
62afe595 2195 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2196 netif_wake_queue (dev);
2197 }
2198
2199 if (status & DMADone) {
62afe595
JL		 2200 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2201 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2202 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2203 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2204 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2205 /*
2206 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2207 * insufficient FIFO room, the TxAvailable test will succeed and call
2208 * netif_wake_queue()
2209 */
2210 netif_wake_queue(dev);
2211 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2212 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2213 netif_stop_queue(dev);
2214 }
2215 }
2216 }
2217 /* Check for all uncommon interrupts at once. */
2218 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2219 if (status == 0xffff)
2220 break;
2221 vortex_error(dev, status);
2222 }
2223
2224 if (--work_done < 0) {
2225 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2226 "%4.4x.\n", dev->name, status);
2227 /* Disable all pending interrupts. */
2228 do {
2229 vp->deferred |= status;
62afe595 2230 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2231 ioaddr + EL3_CMD);
62afe595
JL		 2232 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2233 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2234 /* The timer will reenable interrupts. */
2235 mod_timer(&vp->timer, jiffies + 1*HZ);
2236 break;
2237 }
2238 /* Acknowledge the IRQ. */
62afe595
JL		 2239 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2240 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2241
2242 if (vortex_debug > 4)
2243 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2244 dev->name, status);
2245handler_exit:
2246 spin_unlock(&vp->lock);
2247 return IRQ_RETVAL(handled);
2248}
2249
2250/*
2251 * This is the ISR for the boomerang series chips.
2252 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2253 */
2254
2255static irqreturn_t
2256boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2257{
2258 struct net_device *dev = dev_id;
2259 struct vortex_private *vp = netdev_priv(dev);
62afe595 2260 void __iomem *ioaddr;
1da177e4
LT		 2261 int status;
2262 int work_done = max_interrupt_work;
2263
62afe595 2264 ioaddr = vp->ioaddr;
1da177e4
LT		 2265
2266 /*
2267 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2268 * and boomerang_start_xmit
2269 */
2270 spin_lock(&vp->lock);
2271
62afe595 2272 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2273
2274 if (vortex_debug > 6)
2275 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2276
2277 if ((status & IntLatch) == 0)
2278 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2279
2280 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2281 if (vortex_debug > 1)
2282 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2283 goto handler_exit;
2284 }
2285
2286 if (status & IntReq) {
2287 status |= vp->deferred;
2288 vp->deferred = 0;
2289 }
2290
2291 if (vortex_debug > 4)
2292 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2293 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2294 do {
2295 if (vortex_debug > 5)
2296 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2297 dev->name, status);
2298 if (status & UpComplete) {
62afe595 2299 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2300 if (vortex_debug > 5)
2301 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2302 boomerang_rx(dev);
2303 }
2304
2305 if (status & DownComplete) {
2306 unsigned int dirty_tx = vp->dirty_tx;
2307
62afe595 2308 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2309 while (vp->cur_tx - dirty_tx > 0) {
2310 int entry = dirty_tx % TX_RING_SIZE;
2311#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2312 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2313 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2314 break; /* It still hasn't been processed. */
2315#else
2316 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2317 break; /* It still hasn't been processed. */
2318#endif
2319
2320 if (vp->tx_skbuff[entry]) {
2321 struct sk_buff *skb = vp->tx_skbuff[entry];
2322#if DO_ZEROCOPY
2323 int i;
2324 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2325 pci_unmap_single(VORTEX_PCI(vp),
2326 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2327 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2328 PCI_DMA_TODEVICE);
2329#else
2330 pci_unmap_single(VORTEX_PCI(vp),
2331 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2332#endif
2333 dev_kfree_skb_irq(skb);
2334 vp->tx_skbuff[entry] = NULL;
2335 } else {
2336 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2337 }
2338 /* vp->stats.tx_packets++; Counted below. */
2339 dirty_tx++;
2340 }
2341 vp->dirty_tx = dirty_tx;
2342 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2343 if (vortex_debug > 6)
2344 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2345 netif_wake_queue (dev);
2346 }
2347 }
2348
2349 /* Check for all uncommon interrupts at once. */
2350 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2351 vortex_error(dev, status);
2352
2353 if (--work_done < 0) {
2354 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2355 "%4.4x.\n", dev->name, status);
2356 /* Disable all pending interrupts. */
2357 do {
2358 vp->deferred |= status;
62afe595 2359 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2360 ioaddr + EL3_CMD);
62afe595
JL		 2361 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2362 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2363 /* The timer will reenable interrupts. */
2364 mod_timer(&vp->timer, jiffies + 1*HZ);
2365 break;
2366 }
2367 /* Acknowledge the IRQ. */
62afe595 2368 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2369 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2370 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2371
62afe595 2372 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2373
2374 if (vortex_debug > 4)
2375 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2376 dev->name, status);
2377handler_exit:
2378 spin_unlock(&vp->lock);
2379 return IRQ_HANDLED;
2380}
2381
2382static int vortex_rx(struct net_device *dev)
2383{
2384 struct vortex_private *vp = netdev_priv(dev);
62afe595 2385 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2386 int i;
2387 short rx_status;
2388
2389 if (vortex_debug > 5)
2390 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2391 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2392 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2393 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2394 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2395 if (vortex_debug > 2)
2396 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2397 vp->stats.rx_errors++;
2398 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2399 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2400 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2401 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2402 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2403 } else {
2404 /* The packet length: up to 4.5K!. */
2405 int pkt_len = rx_status & 0x1fff;
2406 struct sk_buff *skb;
2407
2408 skb = dev_alloc_skb(pkt_len + 5);
2409 if (vortex_debug > 4)
2410 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2411 pkt_len, rx_status);
2412 if (skb != NULL) {
2413 skb->dev = dev;
2414 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2415 /* 'skb_put()' points to the start of sk_buff data area. */
2416 if (vp->bus_master &&
62afe595 2417 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2418 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2419 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2420 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2421 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2422 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2423 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2424 ;
2425 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2426 } else {
62afe595
JL		 2427 ioread32_rep(ioaddr + RX_FIFO,
2428 skb_put(skb, pkt_len),
2429 (pkt_len + 3) >> 2);
1da177e4 2430 }
62afe595 2431 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2432 skb->protocol = eth_type_trans(skb, dev);
2433 netif_rx(skb);
2434 dev->last_rx = jiffies;
2435 vp->stats.rx_packets++;
2436 /* Wait a limited time to go to next packet. */
2437 for (i = 200; i >= 0; i--)
62afe595 2438 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2439 break;
2440 continue;
2441 } else if (vortex_debug > 0)
2442 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2443 "size %d.\n", dev->name, pkt_len);
35b30674 2444 vp->stats.rx_dropped++;
1da177e4 2445 }
1da177e4
LT		 2446 issue_and_wait(dev, RxDiscard);
2447 }
2448
2449 return 0;
2450}
2451
2452static int
2453boomerang_rx(struct net_device *dev)
2454{
2455 struct vortex_private *vp = netdev_priv(dev);
2456 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2457 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2458 int rx_status;
2459 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2460
2461 if (vortex_debug > 5)
62afe595 2462 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2463
2464 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2465 if (--rx_work_limit < 0)
2466 break;
2467 if (rx_status & RxDError) { /* Error, update stats. */
2468 unsigned char rx_error = rx_status >> 16;
2469 if (vortex_debug > 2)
2470 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2471 vp->stats.rx_errors++;
2472 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2473 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2474 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2475 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2476 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2477 } else {
2478 /* The packet length: up to 4.5K!. */
2479 int pkt_len = rx_status & 0x1fff;
2480 struct sk_buff *skb;
2481 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2482
2483 if (vortex_debug > 4)
2484 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2485 pkt_len, rx_status);
2486
2487 /* Check if the packet is long enough to just accept without
2488 copying to a properly sized skbuff. */
2489 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2490 skb->dev = dev;
2491 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2492 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2493 /* 'skb_put()' points to the start of sk_buff data area. */
2494 memcpy(skb_put(skb, pkt_len),
689be439 2495 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2496 pkt_len);
2497 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2498 vp->rx_copy++;
2499 } else {
2500 /* Pass up the skbuff already on the Rx ring. */
2501 skb = vp->rx_skbuff[entry];
2502 vp->rx_skbuff[entry] = NULL;
2503 skb_put(skb, pkt_len);
2504 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2505 vp->rx_nocopy++;
2506 }
2507 skb->protocol = eth_type_trans(skb, dev);
2508 { /* Use hardware checksum info. */
2509 int csum_bits = rx_status & 0xee000000;
2510 if (csum_bits &&
2511 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2512 csum_bits == (IPChksumValid | UDPChksumValid))) {
2513 skb->ip_summed = CHECKSUM_UNNECESSARY;
2514 vp->rx_csumhits++;
2515 }
2516 }
2517 netif_rx(skb);
2518 dev->last_rx = jiffies;
2519 vp->stats.rx_packets++;
2520 }
2521 entry = (++vp->cur_rx) % RX_RING_SIZE;
2522 }
2523 /* Refill the Rx ring buffers. */
2524 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2525 struct sk_buff *skb;
2526 entry = vp->dirty_rx % RX_RING_SIZE;
2527 if (vp->rx_skbuff[entry] == NULL) {
2528 skb = dev_alloc_skb(PKT_BUF_SZ);
2529 if (skb == NULL) {
2530 static unsigned long last_jif;
ff5688ae 2531 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2532 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2533 last_jif = jiffies;
2534 }
2535 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2536 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2537 break; /* Bad news! */
2538 }
2539 skb->dev = dev; /* Mark as being used by this device. */
2540 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2541 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2542 vp->rx_skbuff[entry] = skb;
2543 }
2544 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2545 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2546 }
2547 return 0;
2548}
2549
2550/*
2551 * If we've hit a total OOM refilling the Rx ring we poll once a second
2552 * for some memory. Otherwise there is no way to restart the rx process.
2553 */
2554static void
2555rx_oom_timer(unsigned long arg)
2556{
2557 struct net_device *dev = (struct net_device *)arg;
2558 struct vortex_private *vp = netdev_priv(dev);
2559
2560 spin_lock_irq(&vp->lock);
2561 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2562 boomerang_rx(dev);
2563 if (vortex_debug > 1) {
2564 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2565 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2566 }
2567 spin_unlock_irq(&vp->lock);
2568}
2569
2570static void
2571vortex_down(struct net_device *dev, int final_down)
2572{
2573 struct vortex_private *vp = netdev_priv(dev);
62afe595 2574 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2575
2576 netif_stop_queue (dev);
2577
2578 del_timer_sync(&vp->rx_oom_timer);
2579 del_timer_sync(&vp->timer);
2580
2581 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2582 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2583
2584 /* Disable the receiver and transmitter. */
62afe595
JL		 2585 iowrite16(RxDisable, ioaddr + EL3_CMD);
2586 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2587
2588 /* Disable receiving 802.1q tagged frames */
2589 set_8021q_mode(dev, 0);
2590
2591 if (dev->if_port == XCVR_10base2)
2592 /* Turn off thinnet power. Green! */
62afe595 2593 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2594
62afe595 2595 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2596
2597 update_stats(ioaddr, dev);
2598 if (vp->full_bus_master_rx)
62afe595 2599 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2600 if (vp->full_bus_master_tx)
62afe595 2601 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2602
2603 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2604 vp->pm_state_valid = 1;
1da177e4
LT		 2605 pci_save_state(VORTEX_PCI(vp));
2606 acpi_set_WOL(dev);
2607 }
2608}
2609
2610static int
2611vortex_close(struct net_device *dev)
2612{
2613 struct vortex_private *vp = netdev_priv(dev);
62afe595 2614 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2615 int i;
2616
2617 if (netif_device_present(dev))
2618 vortex_down(dev, 1);
2619
2620 if (vortex_debug > 1) {
2621 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2622 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2623 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2624 " tx_queued %d Rx pre-checksummed %d.\n",
2625 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2626 }
2627
2628#if DO_ZEROCOPY
32fb5f06
JL		 2629 if (vp->rx_csumhits &&
2630 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2631 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2632 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2633 "not using them!\n", dev->name);
1da177e4
LT		 2634 }
2635#endif
2636
2637 free_irq(dev->irq, dev);
2638
2639 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2640 for (i = 0; i < RX_RING_SIZE; i++)
2641 if (vp->rx_skbuff[i]) {
2642 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2643 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2644 dev_kfree_skb(vp->rx_skbuff[i]);
2645 vp->rx_skbuff[i] = NULL;
2646 }
2647 }
2648 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2649 for (i = 0; i < TX_RING_SIZE; i++) {
2650 if (vp->tx_skbuff[i]) {
2651 struct sk_buff *skb = vp->tx_skbuff[i];
2652#if DO_ZEROCOPY
2653 int k;
2654
2655 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2656 pci_unmap_single(VORTEX_PCI(vp),
2657 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2658 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2659 PCI_DMA_TODEVICE);
2660#else
2661 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2662#endif
2663 dev_kfree_skb(skb);
2664 vp->tx_skbuff[i] = NULL;
2665 }
2666 }
2667 }
2668
2669 return 0;
2670}
2671
2672static void
2673dump_tx_ring(struct net_device *dev)
2674{
2675 if (vortex_debug > 0) {
2676 struct vortex_private *vp = netdev_priv(dev);
62afe595 2677 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2678
2679 if (vp->full_bus_master_tx) {
2680 int i;
62afe595 2681 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2682
2683 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2684 vp->full_bus_master_tx,
2685 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2686 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2687 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2688 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2689 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2690 issue_and_wait(dev, DownStall);
2691 for (i = 0; i < TX_RING_SIZE; i++) {
2692 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2693 &vp->tx_ring[i],
2694#if DO_ZEROCOPY
2695 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2696#else
2697 le32_to_cpu(vp->tx_ring[i].length),
2698#endif
2699 le32_to_cpu(vp->tx_ring[i].status));
2700 }
2701 if (!stalled)
62afe595 2702 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2703 }
2704 }
2705}
2706
2707static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2708{
2709 struct vortex_private *vp = netdev_priv(dev);
62afe595 2710 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2711 unsigned long flags;
2712
2713 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2714 spin_lock_irqsave (&vp->lock, flags);
62afe595 2715 update_stats(ioaddr, dev);
1da177e4
LT		 2716 spin_unlock_irqrestore (&vp->lock, flags);
2717 }
2718 return &vp->stats;
2719}
2720
2721/* Update statistics.
2722 Unlike with the EL3 we need not worry about interrupts changing
2723 the window setting from underneath us, but we must still guard
2724 against a race condition with a StatsUpdate interrupt updating the
2725 table. This is done by checking that the ASM (!) code generated uses
2726 atomic updates with '+='.
2727 */
62afe595 2728static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2729{
2730 struct vortex_private *vp = netdev_priv(dev);
62afe595 2731 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2732
2733 if (old_window == 0xffff) /* Chip suspended or ejected. */
2734 return;
2735 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2736 /* Switch to the stats window, and read everything. */
2737 EL3WINDOW(6);
62afe595
JL		 2738 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2739 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2740 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2741 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2742 vp->stats.tx_packets += ioread8(ioaddr + 6);
2743 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2744 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2745 /* Don't bother with register 9, an extension of registers 6&7.
2746 If we do use the 6&7 values the atomic update assumption above
2747 is invalid. */
62afe595
JL		 2748 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2749 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2750 /* Extra stats for get_ethtool_stats() */
62afe595 2751 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2752 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2753 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2754 EL3WINDOW(4);
62afe595 2755 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2756
8d1d0340
SK		 2757 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2758 + vp->xstats.tx_single_collisions
2759 + vp->xstats.tx_max_collisions;
2760
1da177e4 2761 {
62afe595 2762 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2763 vp->stats.rx_bytes += (up & 0x0f) << 16;
2764 vp->stats.tx_bytes += (up & 0xf0) << 12;
2765 }
2766
2767 EL3WINDOW(old_window >> 13);
2768 return;
2769}
2770
2771static int vortex_nway_reset(struct net_device *dev)
2772{
2773 struct vortex_private *vp = netdev_priv(dev);
62afe595 2774 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2775 unsigned long flags;
2776 int rc;
2777
2778 spin_lock_irqsave(&vp->lock, flags);
2779 EL3WINDOW(4);
2780 rc = mii_nway_restart(&vp->mii);
2781 spin_unlock_irqrestore(&vp->lock, flags);
2782 return rc;
2783}
2784
1da177e4
LT		 2785static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2786{
2787 struct vortex_private *vp = netdev_priv(dev);
62afe595 2788 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2789 unsigned long flags;
2790 int rc;
2791
2792 spin_lock_irqsave(&vp->lock, flags);
2793 EL3WINDOW(4);
2794 rc = mii_ethtool_gset(&vp->mii, cmd);
2795 spin_unlock_irqrestore(&vp->lock, flags);
2796 return rc;
2797}
2798
2799static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2800{
2801 struct vortex_private *vp = netdev_priv(dev);
62afe595 2802 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2803 unsigned long flags;
2804 int rc;
2805
2806 spin_lock_irqsave(&vp->lock, flags);
2807 EL3WINDOW(4);
2808 rc = mii_ethtool_sset(&vp->mii, cmd);
2809 spin_unlock_irqrestore(&vp->lock, flags);
2810 return rc;
2811}
2812
2813static u32 vortex_get_msglevel(struct net_device *dev)
2814{
2815 return vortex_debug;
2816}
2817
2818static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2819{
2820 vortex_debug = dbg;
2821}
2822
2823static int vortex_get_stats_count(struct net_device *dev)
2824{
2825 return VORTEX_NUM_STATS;
2826}
2827
2828static void vortex_get_ethtool_stats(struct net_device *dev,
2829 struct ethtool_stats *stats, u64 *data)
2830{
2831 struct vortex_private *vp = netdev_priv(dev);
62afe595 2832 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2833 unsigned long flags;
2834
2835 spin_lock_irqsave(&vp->lock, flags);
62afe595 2836 update_stats(ioaddr, dev);
1da177e4
LT		 2837 spin_unlock_irqrestore(&vp->lock, flags);
2838
2839 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2840 data[1] = vp->xstats.tx_max_collisions;
2841 data[2] = vp->xstats.tx_multiple_collisions;
2842 data[3] = vp->xstats.tx_single_collisions;
2843 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2844}
2845
2846
2847static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2848{
2849 switch (stringset) {
2850 case ETH_SS_STATS:
2851 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2852 break;
2853 default:
2854 WARN_ON(1);
2855 break;
2856 }
2857}
2858
2859static void vortex_get_drvinfo(struct net_device *dev,
2860 struct ethtool_drvinfo *info)
2861{
2862 struct vortex_private *vp = netdev_priv(dev);
2863
2864 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2865 if (VORTEX_PCI(vp)) {
2866 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2867 } else {
2868 if (VORTEX_EISA(vp))
2869 sprintf(info->bus_info, vp->gendev->bus_id);
2870 else
2871 sprintf(info->bus_info, "EISA 0x%lx %d",
2872 dev->base_addr, dev->irq);
2873 }
2874}
2875
2876static struct ethtool_ops vortex_ethtool_ops = {
2877 .get_drvinfo = vortex_get_drvinfo,
2878 .get_strings = vortex_get_strings,
2879 .get_msglevel = vortex_get_msglevel,
2880 .set_msglevel = vortex_set_msglevel,
2881 .get_ethtool_stats = vortex_get_ethtool_stats,
2882 .get_stats_count = vortex_get_stats_count,
2883 .get_settings = vortex_get_settings,
2884 .set_settings = vortex_set_settings,
373a6887 2885 .get_link = ethtool_op_get_link,
1da177e4 2886 .nway_reset = vortex_nway_reset,
a880c4cd 2887 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 2888};
2889
2890#ifdef CONFIG_PCI
2891/*
2892 * Must power the device up to do MDIO operations
2893 */
2894static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2895{
2896 int err;
2897 struct vortex_private *vp = netdev_priv(dev);
62afe595 2898 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2899 unsigned long flags;
2900 int state = 0;
2901
2902 if(VORTEX_PCI(vp))
2903 state = VORTEX_PCI(vp)->current_state;
2904
2905 /* The kernel core really should have pci_get_power_state() */
2906
2907 if(state != 0)
2908 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2909 spin_lock_irqsave(&vp->lock, flags);
2910 EL3WINDOW(4);
2911 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2912 spin_unlock_irqrestore(&vp->lock, flags);
2913 if(state != 0)
2914 pci_set_power_state(VORTEX_PCI(vp), state);
2915
2916 return err;
2917}
2918#endif
2919
2920
2921/* Pre-Cyclone chips have no documented multicast filter, so the only
2922 multicast setting is to receive all multicast frames. At least
2923 the chip has a very clean way to set the mode, unlike many others. */
2924static void set_rx_mode(struct net_device *dev)
2925{
62afe595
JL		 2926 struct vortex_private *vp = netdev_priv(dev);
2927 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2928 int new_mode;
2929
2930 if (dev->flags & IFF_PROMISC) {
2931 if (vortex_debug > 0)
2932 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2933 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2934 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2935 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2936 } else
2937 new_mode = SetRxFilter | RxStation | RxBroadcast;
2938
62afe595 2939 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2940}
2941
2942#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2943/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2944 Note that this must be done after each RxReset due to some backwards
2945 compatibility logic in the Cyclone and Tornado ASICs */
2946
2947/* The Ethernet Type used for 802.1q tagged frames */
2948#define VLAN_ETHER_TYPE 0x8100
2949
2950static void set_8021q_mode(struct net_device *dev, int enable)
2951{
2952 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2953 void __iomem *ioaddr = vp->ioaddr;
2954 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2955 int mac_ctrl;
2956
2957 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2958 /* cyclone and tornado chipsets can recognize 802.1q
2959 * tagged frames and treat them correctly */
2960
2961 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2962 if (enable)
2963 max_pkt_size += 4; /* 802.1Q VLAN tag */
2964
2965 EL3WINDOW(3);
62afe595 2966 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 2967
2968 /* set VlanEtherType to let the hardware checksumming
2969 treat tagged frames correctly */
2970 EL3WINDOW(7);
62afe595 2971 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 2972 } else {
2973 /* on older cards we have to enable large frames */
2974
2975 vp->large_frames = dev->mtu > 1500 || enable;
2976
2977 EL3WINDOW(3);
62afe595 2978 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2979 if (vp->large_frames)
2980 mac_ctrl |= 0x40;
2981 else
2982 mac_ctrl &= ~0x40;
62afe595 2983 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2984 }
2985
2986 EL3WINDOW(old_window);
2987}
2988#else
2989
2990static void set_8021q_mode(struct net_device *dev, int enable)
2991{
2992}
2993
2994
2995#endif
2996
2997/* MII transceiver control section.
2998 Read and write the MII registers using software-generated serial
2999 MDIO protocol. See the MII specifications or DP83840A data sheet
3000 for details. */
3001
3002/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3003 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3004 "overclocking" issues. */
62afe595 3005#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3006
3007#define MDIO_SHIFT_CLK 0x01
3008#define MDIO_DIR_WRITE 0x04
3009#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3010#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3011#define MDIO_DATA_READ 0x02
3012#define MDIO_ENB_IN 0x00
3013
3014/* Generate the preamble required for initial synchronization and
3015 a few older transceivers. */
62afe595 3016static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3017{
62afe595 3018 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3019
3020 /* Establish sync by sending at least 32 logic ones. */
3021 while (-- bits >= 0) {
62afe595 3022 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3023 mdio_delay();
62afe595 3024 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3025 mdio_delay();
3026 }
3027}
3028
3029static int mdio_read(struct net_device *dev, int phy_id, int location)
3030{
3031 int i;
62afe595
JL		 3032 struct vortex_private *vp = netdev_priv(dev);
3033 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3034 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3035 unsigned int retval = 0;
62afe595 3036 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3037
3038 if (mii_preamble_required)
3039 mdio_sync(ioaddr, 32);
3040
3041 /* Shift the read command bits out. */
3042 for (i = 14; i >= 0; i--) {
3043 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3044 iowrite16(dataval, mdio_addr);
1da177e4 3045 mdio_delay();
62afe595 3046 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3047 mdio_delay();
3048 }
3049 /* Read the two transition, 16 data, and wire-idle bits. */
3050 for (i = 19; i > 0; i--) {
62afe595 3051 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3052 mdio_delay();
62afe595
JL		 3053 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3054 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3055 mdio_delay();
3056 }
3057 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3058}
3059
3060static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3061{
62afe595
JL		 3062 struct vortex_private *vp = netdev_priv(dev);
3063 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3064 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3065 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3066 int i;
3067
3068 if (mii_preamble_required)
3069 mdio_sync(ioaddr, 32);
3070
3071 /* Shift the command bits out. */
3072 for (i = 31; i >= 0; i--) {
3073 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3074 iowrite16(dataval, mdio_addr);
1da177e4 3075 mdio_delay();
62afe595 3076 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3077 mdio_delay();
3078 }
3079 /* Leave the interface idle. */
3080 for (i = 1; i >= 0; i--) {
62afe595 3081 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3082 mdio_delay();
62afe595 3083 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3084 mdio_delay();
3085 }
3086 return;
3087}
a880c4cd 3088
1da177e4
LT		 3089/* ACPI: Advanced Configuration and Power Interface. */
3090/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3091static void acpi_set_WOL(struct net_device *dev)
3092{
3093 struct vortex_private *vp = netdev_priv(dev);
62afe595 3094 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3095
3096 if (vp->enable_wol) {
3097 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3098 EL3WINDOW(7);
62afe595 3099 iowrite16(2, ioaddr + 0x0c);
1da177e4 3100 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3101 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3102 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3103
3104 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3105
3106 /* Change the power state to D3; RxEnable doesn't take effect. */
3107 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3108 }
1da177e4
LT		 3109}
3110
3111
a880c4cd 3112static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3113{
3114 struct net_device *dev = pci_get_drvdata(pdev);
3115 struct vortex_private *vp;
3116
3117 if (!dev) {
3118 printk("vortex_remove_one called for Compaq device!\n");
3119 BUG();
3120 }
3121
3122 vp = netdev_priv(dev);
3123
62afe595
JL		 3124 if (vp->cb_fn_base)
3125 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3126
1da177e4
LT		 3127 unregister_netdev(dev);
3128
3129 if (VORTEX_PCI(vp)) {
3130 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3131 if (vp->pm_state_valid)
3132 pci_restore_state(VORTEX_PCI(vp));
3133 pci_disable_device(VORTEX_PCI(vp));
3134 }
3135 /* Should really use issue_and_wait() here */
62afe595
JL		 3136 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3137 vp->ioaddr + EL3_CMD);
3138
3139 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3140
3141 pci_free_consistent(pdev,
3142 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3143 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3144 vp->rx_ring,
3145 vp->rx_ring_dma);
3146 if (vp->must_free_region)
3147 release_region(dev->base_addr, vp->io_size);
3148 free_netdev(dev);
3149}
3150
3151
3152static struct pci_driver vortex_driver = {
3153 .name = "3c59x",
3154 .probe = vortex_init_one,
3155 .remove = __devexit_p(vortex_remove_one),
3156 .id_table = vortex_pci_tbl,
3157#ifdef CONFIG_PM
3158 .suspend = vortex_suspend,
3159 .resume = vortex_resume,
3160#endif
3161};
3162
3163
3164static int vortex_have_pci;
3165static int vortex_have_eisa;
3166
3167
a880c4cd 3168static int __init vortex_init(void)
1da177e4
LT		 3169{
3170 int pci_rc, eisa_rc;
3171
3172 pci_rc = pci_module_init(&vortex_driver);
3173 eisa_rc = vortex_eisa_init();
3174
3175 if (pci_rc == 0)
3176 vortex_have_pci = 1;
3177 if (eisa_rc > 0)
3178 vortex_have_eisa = 1;
3179
3180 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3181}
3182
3183
a880c4cd 3184static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3185{
3186 struct vortex_private *vp;
62afe595 3187 void __iomem *ioaddr;
1da177e4
LT		 3188
3189#ifdef CONFIG_EISA
3190 /* Take care of the EISA devices */
a880c4cd 3191 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4
LT		 3192#endif
3193
3194 if (compaq_net_device) {
3195 vp = compaq_net_device->priv;
62afe595
JL		 3196 ioaddr = ioport_map(compaq_net_device->base_addr,
3197 VORTEX_TOTAL_SIZE);
1da177e4 3198
a880c4cd
SK		 3199 unregister_netdev(compaq_net_device);
3200 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3201 release_region(compaq_net_device->base_addr,
3202 VORTEX_TOTAL_SIZE);
1da177e4 3203
a880c4cd 3204 free_netdev(compaq_net_device);
1da177e4
LT		 3205 }
3206}
3207
3208
a880c4cd 3209static void __exit vortex_cleanup(void)
1da177e4
LT		 3210{
3211 if (vortex_have_pci)
a880c4cd 3212 pci_unregister_driver(&vortex_driver);
1da177e4 3213 if (vortex_have_eisa)
a880c4cd 3214 vortex_eisa_cleanup();
1da177e4
LT		 3215}
3216
3217
3218module_init(vortex_init);
3219module_exit(vortex_cleanup);
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