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[PATCH] 3c59x: convert to use of pci_iomap API
[net-next-2.6.git] / drivers / net / 3c59x.c
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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186*/
187
188/*
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
191 *
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
195 */
196
197
198#define DRV_NAME "3c59x"
199#define DRV_VERSION "LK1.1.19"
200#define DRV_RELDATE "10 Nov 2002"
201
202
203
204/* A few values that may be tweaked. */
205/* Keep the ring sizes a power of two for efficiency. */
206#define TX_RING_SIZE 16
207#define RX_RING_SIZE 32
208#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
209
210/* "Knobs" that adjust features and parameters. */
211/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
212 Setting to > 1512 effectively disables this feature. */
213#ifndef __arm__
214static int rx_copybreak = 200;
215#else
216/* ARM systems perform better by disregarding the bus-master
217 transfer capability of these cards. -- rmk */
218static int rx_copybreak = 1513;
219#endif
220/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
221static const int mtu = 1500;
222/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
223static int max_interrupt_work = 32;
224/* Tx timeout interval (millisecs) */
225static int watchdog = 5000;
226
227/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
228 * of possible Tx stalls if the system is blocking interrupts
229 * somewhere else. Undefine this to disable.
230 */
231#define tx_interrupt_mitigation 1
232
233/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
234#define vortex_debug debug
235#ifdef VORTEX_DEBUG
236static int vortex_debug = VORTEX_DEBUG;
237#else
238static int vortex_debug = 1;
239#endif
240
241#include <linux/config.h>
242#include <linux/module.h>
243#include <linux/kernel.h>
244#include <linux/string.h>
245#include <linux/timer.h>
246#include <linux/errno.h>
247#include <linux/in.h>
248#include <linux/ioport.h>
249#include <linux/slab.h>
250#include <linux/interrupt.h>
251#include <linux/pci.h>
252#include <linux/mii.h>
253#include <linux/init.h>
254#include <linux/netdevice.h>
255#include <linux/etherdevice.h>
256#include <linux/skbuff.h>
257#include <linux/ethtool.h>
258#include <linux/highmem.h>
259#include <linux/eisa.h>
260#include <linux/bitops.h>
261#include <asm/irq.h> /* For NR_IRQS only. */
262#include <asm/io.h>
263#include <asm/uaccess.h>
264
265/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
266 This is only in the support-all-kernels source code. */
267
268#define RUN_AT(x) (jiffies + (x))
269
270#include <linux/delay.h>
271
272
273static char version[] __devinitdata =
274DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
275
276MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
277MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "
278 DRV_VERSION " " DRV_RELDATE);
279MODULE_LICENSE("GPL");
280MODULE_VERSION(DRV_VERSION);
281
282
283/* Operational parameter that usually are not changed. */
284
285/* The Vortex size is twice that of the original EtherLinkIII series: the
286 runtime register window, window 1, is now always mapped in.
287 The Boomerang size is twice as large as the Vortex -- it has additional
288 bus master control registers. */
289#define VORTEX_TOTAL_SIZE 0x20
290#define BOOMERANG_TOTAL_SIZE 0x40
291
292/* Set iff a MII transceiver on any interface requires mdio preamble.
293 This only set with the original DP83840 on older 3c905 boards, so the extra
294 code size of a per-interface flag is not worthwhile. */
295static char mii_preamble_required;
296
297#define PFX DRV_NAME ": "
298
299
300
301/*
302 Theory of Operation
303
304I. Board Compatibility
305
306This device driver is designed for the 3Com FastEtherLink and FastEtherLink
307XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
308versions of the FastEtherLink cards. The supported product IDs are
309 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
310
311The related ISA 3c515 is supported with a separate driver, 3c515.c, included
312with the kernel source or available from
313 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
314
315II. Board-specific settings
316
317PCI bus devices are configured by the system at boot time, so no jumpers
318need to be set on the board. The system BIOS should be set to assign the
319PCI INTA signal to an otherwise unused system IRQ line.
320
321The EEPROM settings for media type and forced-full-duplex are observed.
322The EEPROM media type should be left at the default "autoselect" unless using
32310base2 or AUI connections which cannot be reliably detected.
324
325III. Driver operation
326
327The 3c59x series use an interface that's very similar to the previous 3c5x9
328series. The primary interface is two programmed-I/O FIFOs, with an
329alternate single-contiguous-region bus-master transfer (see next).
330
331The 3c900 "Boomerang" series uses a full-bus-master interface with separate
332lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
333DEC Tulip and Intel Speedo3. The first chip version retains a compatible
334programmed-I/O interface that has been removed in 'B' and subsequent board
335revisions.
336
337One extension that is advertised in a very large font is that the adapters
338are capable of being bus masters. On the Vortex chip this capability was
339only for a single contiguous region making it far less useful than the full
340bus master capability. There is a significant performance impact of taking
341an extra interrupt or polling for the completion of each transfer, as well
342as difficulty sharing the single transfer engine between the transmit and
343receive threads. Using DMA transfers is a win only with large blocks or
344with the flawed versions of the Intel Orion motherboard PCI controller.
345
346The Boomerang chip's full-bus-master interface is useful, and has the
347currently-unused advantages over other similar chips that queued transmit
348packets may be reordered and receive buffer groups are associated with a
349single frame.
350
351With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
352Rather than a fixed intermediate receive buffer, this scheme allocates
353full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
354the copying breakpoint: it is chosen to trade-off the memory wasted by
355passing the full-sized skbuff to the queue layer for all frames vs. the
356copying cost of copying a frame to a correctly-sized skbuff.
357
358IIIC. Synchronization
359The driver runs as two independent, single-threaded flows of control. One
360is the send-packet routine, which enforces single-threaded use by the
361dev->tbusy flag. The other thread is the interrupt handler, which is single
362threaded by the hardware and other software.
363
364IV. Notes
365
366Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
3673c590, 3c595, and 3c900 boards.
368The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
369the EISA version is called "Demon". According to Terry these names come
370from rides at the local amusement park.
371
372The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
373This driver only supports ethernet packets because of the skbuff allocation
374limit of 4K.
375*/
376
377/* This table drives the PCI probe routines. It's mostly boilerplate in all
378 of the drivers, and will likely be provided by some future kernel.
379*/
380enum pci_flags_bit {
381 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
382 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
383};
384
385enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
386 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
387 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
388 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
389 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
390 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
391
392enum vortex_chips {
393 CH_3C590 = 0,
394 CH_3C592,
395 CH_3C597,
396 CH_3C595_1,
397 CH_3C595_2,
398
399 CH_3C595_3,
400 CH_3C900_1,
401 CH_3C900_2,
402 CH_3C900_3,
403 CH_3C900_4,
404
405 CH_3C900_5,
406 CH_3C900B_FL,
407 CH_3C905_1,
408 CH_3C905_2,
409 CH_3C905B_1,
410
411 CH_3C905B_2,
412 CH_3C905B_FX,
413 CH_3C905C,
414 CH_3C9202,
415 CH_3C980,
416 CH_3C9805,
417
418 CH_3CSOHO100_TX,
419 CH_3C555,
420 CH_3C556,
421 CH_3C556B,
422 CH_3C575,
423
424 CH_3C575_1,
425 CH_3CCFE575,
426 CH_3CCFE575CT,
427 CH_3CCFE656,
428 CH_3CCFEM656,
429
430 CH_3CCFEM656_1,
431 CH_3C450,
432 CH_3C920,
433 CH_3C982A,
434 CH_3C982B,
435
436 CH_905BT4,
437 CH_920B_EMB_WNM,
438};
439
440
441/* note: this array directly indexed by above enums, and MUST
442 * be kept in sync with both the enums above, and the PCI device
443 * table below
444 */
445static struct vortex_chip_info {
446 const char *name;
447 int flags;
448 int drv_flags;
449 int io_size;
450} vortex_info_tbl[] __devinitdata = {
451 {"3c590 Vortex 10Mbps",
452 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
453 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
454 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
455 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
456 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
457 {"3c595 Vortex 100baseTx",
458 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
459 {"3c595 Vortex 100baseT4",
460 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
461
462 {"3c595 Vortex 100base-MII",
463 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
464 {"3c900 Boomerang 10baseT",
465 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
466 {"3c900 Boomerang 10Mbps Combo",
467 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
468 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
469 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
470 {"3c900 Cyclone 10Mbps Combo",
471 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
472
473 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
474 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
475 {"3c900B-FL Cyclone 10base-FL",
476 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
477 {"3c905 Boomerang 100baseTx",
478 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
479 {"3c905 Boomerang 100baseT4",
480 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
481 {"3c905B Cyclone 100baseTx",
482 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
483
484 {"3c905B Cyclone 10/100/BNC",
485 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
486 {"3c905B-FX Cyclone 100baseFx",
487 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
488 {"3c905C Tornado",
489 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
490 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
491 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
492 {"3c980 Cyclone",
493 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
494
495 {"3c980C Python-T",
496 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
497 {"3cSOHO100-TX Hurricane",
498 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
499 {"3c555 Laptop Hurricane",
500 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
501 {"3c556 Laptop Tornado",
502 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
503 HAS_HWCKSM, 128, },
504 {"3c556B Laptop Hurricane",
505 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
506 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
507
508 {"3c575 [Megahertz] 10/100 LAN CardBus",
509 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
510 {"3c575 Boomerang CardBus",
511 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
512 {"3CCFE575BT Cyclone CardBus",
513 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
514 INVERT_LED_PWR|HAS_HWCKSM, 128, },
515 {"3CCFE575CT Tornado CardBus",
516 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
517 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
518 {"3CCFE656 Cyclone CardBus",
519 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
520 INVERT_LED_PWR|HAS_HWCKSM, 128, },
521
522 {"3CCFEM656B Cyclone+Winmodem CardBus",
523 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
524 INVERT_LED_PWR|HAS_HWCKSM, 128, },
525 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
526 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
527 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
528 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
529 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
530 {"3c920 Tornado",
531 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
532 {"3c982 Hydra Dual Port A",
533 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
534
535 {"3c982 Hydra Dual Port B",
536 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
537 {"3c905B-T4",
538 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
539 {"3c920B-EMB-WNM Tornado",
540 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
541
542 {NULL,}, /* NULL terminated list. */
543};
544
545
546static struct pci_device_id vortex_pci_tbl[] = {
547 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
548 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
549 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
550 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
551 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
552
553 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
554 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
555 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
556 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
557 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
558
559 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
560 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
561 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
562 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
563 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
564
565 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
566 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
567 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
568 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
569 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
570 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
571
572 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
573 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
574 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
575 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
576 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
577
578 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
579 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
580 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
581 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
582 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
583
584 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
585 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
586 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
587 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
588 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
589
590 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
591 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
592
593 {0,} /* 0 terminated list. */
594};
595MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
596
597
598/* Operational definitions.
599 These are not used by other compilation units and thus are not
600 exported in a ".h" file.
601
602 First the windows. There are eight register windows, with the command
603 and status registers available in each.
604 */
62afe595 605#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 606#define EL3_CMD 0x0e
607#define EL3_STATUS 0x0e
608
609/* The top five bits written to EL3_CMD are a command, the lower
610 11 bits are the parameter, if applicable.
611 Note that 11 parameters bits was fine for ethernet, but the new chip
612 can handle FDDI length frames (~4500 octets) and now parameters count
613 32-bit 'Dwords' rather than octets. */
614
615enum vortex_cmd {
616 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
617 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
618 UpStall = 6<<11, UpUnstall = (6<<11)+1,
619 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
620 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
621 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
622 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
623 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
624 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
625 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
626
627/* The SetRxFilter command accepts the following classes: */
628enum RxFilter {
629 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
630
631/* Bits in the general status register. */
632enum vortex_status {
633 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
634 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
635 IntReq = 0x0040, StatsFull = 0x0080,
636 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
637 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
638 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
639};
640
641/* Register window 1 offsets, the window used in normal operation.
642 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
643enum Window1 {
644 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
645 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
646 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
647};
648enum Window0 {
649 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
650 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
651 IntrStatus=0x0E, /* Valid in all windows. */
652};
653enum Win0_EEPROM_bits {
654 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
655 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
656 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
657};
658/* EEPROM locations. */
659enum eeprom_offset {
660 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
661 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
662 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
663 DriverTune=13, Checksum=15};
664
665enum Window2 { /* Window 2. */
666 Wn2_ResetOptions=12,
667};
668enum Window3 { /* Window 3: MAC/config bits. */
669 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
670};
671
672#define BFEXT(value, offset, bitcount) \
673 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
674
675#define BFINS(lhs, rhs, offset, bitcount) \
676 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
677 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
678
679#define RAM_SIZE(v) BFEXT(v, 0, 3)
680#define RAM_WIDTH(v) BFEXT(v, 3, 1)
681#define RAM_SPEED(v) BFEXT(v, 4, 2)
682#define ROM_SIZE(v) BFEXT(v, 6, 2)
683#define RAM_SPLIT(v) BFEXT(v, 16, 2)
684#define XCVR(v) BFEXT(v, 20, 4)
685#define AUTOSELECT(v) BFEXT(v, 24, 1)
686
687enum Window4 { /* Window 4: Xcvr/media bits. */
688 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
689};
690enum Win4_Media_bits {
691 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
692 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
693 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
694 Media_LnkBeat = 0x0800,
695};
696enum Window7 { /* Window 7: Bus Master control. */
697 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
698 Wn7_MasterStatus = 12,
699};
700/* Boomerang bus master control registers. */
701enum MasterCtrl {
702 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
703 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
704};
705
706/* The Rx and Tx descriptor lists.
707 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
708 alignment contraint on tx_ring[] and rx_ring[]. */
709#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
710#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
711struct boom_rx_desc {
712 u32 next; /* Last entry points to 0. */
713 s32 status;
714 u32 addr; /* Up to 63 addr/len pairs possible. */
715 s32 length; /* Set LAST_FRAG to indicate last pair. */
716};
717/* Values for the Rx status entry. */
718enum rx_desc_status {
719 RxDComplete=0x00008000, RxDError=0x4000,
720 /* See boomerang_rx() for actual error bits */
721 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
722 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
723};
724
725#ifdef MAX_SKB_FRAGS
726#define DO_ZEROCOPY 1
727#else
728#define DO_ZEROCOPY 0
729#endif
730
731struct boom_tx_desc {
732 u32 next; /* Last entry points to 0. */
733 s32 status; /* bits 0:12 length, others see below. */
734#if DO_ZEROCOPY
735 struct {
736 u32 addr;
737 s32 length;
738 } frag[1+MAX_SKB_FRAGS];
739#else
740 u32 addr;
741 s32 length;
742#endif
743};
744
745/* Values for the Tx status entry. */
746enum tx_desc_status {
747 CRCDisable=0x2000, TxDComplete=0x8000,
748 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
749 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
750};
751
752/* Chip features we care about in vp->capabilities, read from the EEPROM. */
753enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
754
755struct vortex_extra_stats {
756 unsigned long tx_deferred;
757 unsigned long tx_multiple_collisions;
758 unsigned long rx_bad_ssd;
759};
760
761struct vortex_private {
762 /* The Rx and Tx rings should be quad-word-aligned. */
763 struct boom_rx_desc* rx_ring;
764 struct boom_tx_desc* tx_ring;
765 dma_addr_t rx_ring_dma;
766 dma_addr_t tx_ring_dma;
767 /* The addresses of transmit- and receive-in-place skbuffs. */
768 struct sk_buff* rx_skbuff[RX_RING_SIZE];
769 struct sk_buff* tx_skbuff[TX_RING_SIZE];
770 unsigned int cur_rx, cur_tx; /* The next free ring entry */
771 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
772 struct net_device_stats stats; /* Generic stats */
773 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
774 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
775 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
776
777 /* PCI configuration space information. */
778 struct device *gendev;
62afe595
JL		 779 void __iomem *ioaddr; /* IO address space */
780 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 781
782 /* Some values here only for performance evaluation and path-coverage */
783 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
784 int card_idx;
785
786 /* The remainder are related to chip state, mostly media selection. */
787 struct timer_list timer; /* Media selection timer. */
788 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
789 int options; /* User-settable misc. driver options. */
790 unsigned int media_override:4, /* Passed-in media type. */
791 default_media:4, /* Read from the EEPROM/Wn3_Config. */
792 full_duplex:1, force_fd:1, autoselect:1,
793 bus_master:1, /* Vortex can only do a fragment bus-m. */
794 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
795 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
796 partner_flow_ctrl:1, /* Partner supports flow control */
797 has_nway:1,
798 enable_wol:1, /* Wake-on-LAN is enabled */
799 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
800 open:1,
801 medialock:1,
802 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
803 large_frames:1; /* accept large frames */
804 int drv_flags;
805 u16 status_enable;
806 u16 intr_enable;
807 u16 available_media; /* From Wn3_Options. */
808 u16 capabilities, info1, info2; /* Various, from EEPROM. */
809 u16 advertising; /* NWay media advertisement */
810 unsigned char phys[2]; /* MII device addresses. */
811 u16 deferred; /* Resend these interrupts when we
812 * bale from the ISR */
813 u16 io_size; /* Size of PCI region (for release_region) */
814 spinlock_t lock; /* Serialise access to device & its vortex_private */
815 struct mii_if_info mii; /* MII lib hooks/info */
816};
817
818#ifdef CONFIG_PCI
819#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
820#else
821#define DEVICE_PCI(dev) NULL
822#endif
823
824#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
825
826#ifdef CONFIG_EISA
827#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
828#else
829#define DEVICE_EISA(dev) NULL
830#endif
831
832#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
833
834/* The action to take with a media selection timer tick.
835 Note that we deviate from the 3Com order by checking 10base2 before AUI.
836 */
837enum xcvr_types {
838 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
839 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
840};
841
842static struct media_table {
843 char *name;
844 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
845 mask:8, /* The transceiver-present bit in Wn3_Config.*/
846 next:8; /* The media type to try next. */
847 int wait; /* Time before we check media status. */
848} media_tbl[] = {
849 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
850 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
851 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
852 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
853 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
854 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
855 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
856 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
857 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
858 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
859 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
860};
861
862static struct {
863 const char str[ETH_GSTRING_LEN];
864} ethtool_stats_keys[] = {
865 { "tx_deferred" },
866 { "tx_multiple_collisions" },
867 { "rx_bad_ssd" },
868};
869
870/* number of ETHTOOL_GSTATS u64's */
871#define VORTEX_NUM_STATS 3
872
62afe595 873static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 874 int chip_idx, int card_idx);
875static void vortex_up(struct net_device *dev);
876static void vortex_down(struct net_device *dev, int final);
877static int vortex_open(struct net_device *dev);
62afe595 878static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 879static int mdio_read(struct net_device *dev, int phy_id, int location);
880static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
881static void vortex_timer(unsigned long arg);
882static void rx_oom_timer(unsigned long arg);
883static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
884static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
885static int vortex_rx(struct net_device *dev);
886static int boomerang_rx(struct net_device *dev);
887static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
888static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
889static int vortex_close(struct net_device *dev);
890static void dump_tx_ring(struct net_device *dev);
62afe595 891static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 892static struct net_device_stats *vortex_get_stats(struct net_device *dev);
893static void set_rx_mode(struct net_device *dev);
894#ifdef CONFIG_PCI
895static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
896#endif
897static void vortex_tx_timeout(struct net_device *dev);
898static void acpi_set_WOL(struct net_device *dev);
899static struct ethtool_ops vortex_ethtool_ops;
900static void set_8021q_mode(struct net_device *dev, int enable);
901
902\f
903/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
904/* Option count limit only -- unlimited interfaces are supported. */
905#define MAX_UNITS 8
906static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,};
907static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
908static int hw_checksums[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
909static int flow_ctrl[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
910static int enable_wol[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
911static int global_options = -1;
912static int global_full_duplex = -1;
913static int global_enable_wol = -1;
914
915/* #define dev_alloc_skb dev_alloc_skb_debug */
916
917/* Variables to work-around the Compaq PCI BIOS32 problem. */
918static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
919static struct net_device *compaq_net_device;
920
921static int vortex_cards_found;
922
923module_param(debug, int, 0);
924module_param(global_options, int, 0);
925module_param_array(options, int, NULL, 0);
926module_param(global_full_duplex, int, 0);
927module_param_array(full_duplex, int, NULL, 0);
928module_param_array(hw_checksums, int, NULL, 0);
929module_param_array(flow_ctrl, int, NULL, 0);
930module_param(global_enable_wol, int, 0);
931module_param_array(enable_wol, int, NULL, 0);
932module_param(rx_copybreak, int, 0);
933module_param(max_interrupt_work, int, 0);
934module_param(compaq_ioaddr, int, 0);
935module_param(compaq_irq, int, 0);
936module_param(compaq_device_id, int, 0);
937module_param(watchdog, int, 0);
938MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
939MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
940MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
941MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
942MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if options is unset");
943MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
944MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
945MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
946MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if options is unset");
947MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
948MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
949MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
950MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
951MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
952MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
953
954#ifdef CONFIG_NET_POLL_CONTROLLER
955static void poll_vortex(struct net_device *dev)
956{
957 struct vortex_private *vp = netdev_priv(dev);
958 unsigned long flags;
959 local_save_flags(flags);
960 local_irq_disable();
961 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
962 local_irq_restore(flags);
963}
964#endif
965
966#ifdef CONFIG_PM
967
968static int vortex_suspend (struct pci_dev *pdev, pm_message_t state)
969{
970 struct net_device *dev = pci_get_drvdata(pdev);
971
972 if (dev && dev->priv) {
973 if (netif_running(dev)) {
974 netif_device_detach(dev);
975 vortex_down(dev, 1);
976 }
5b039e68
RW		 977 pci_save_state(pdev);
978 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
979 free_irq(dev->irq, dev);
980 pci_disable_device(pdev);
981 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 982 }
983 return 0;
984}
985
986static int vortex_resume (struct pci_dev *pdev)
987{
988 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 989 struct vortex_private *vp = netdev_priv(dev);
1da177e4 990
5b039e68
RW		 991 if (dev && vp) {
992 pci_set_power_state(pdev, PCI_D0);
993 pci_restore_state(pdev);
994 pci_enable_device(pdev);
995 pci_set_master(pdev);
996 if (request_irq(dev->irq, vp->full_bus_master_rx ?
997 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
998 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
999 pci_disable_device(pdev);
1000 return -EBUSY;
1001 }
1da177e4
LT		 1002 if (netif_running(dev)) {
1003 vortex_up(dev);
1004 netif_device_attach(dev);
1005 }
1006 }
1007 return 0;
1008}
1009
1010#endif /* CONFIG_PM */
1011
1012#ifdef CONFIG_EISA
1013static struct eisa_device_id vortex_eisa_ids[] = {
1014 { "TCM5920", CH_3C592 },
1015 { "TCM5970", CH_3C597 },
1016 { "" }
1017};
1018
1019static int vortex_eisa_probe (struct device *device);
1020static int vortex_eisa_remove (struct device *device);
1021
1022static struct eisa_driver vortex_eisa_driver = {
1023 .id_table = vortex_eisa_ids,
1024 .driver = {
1025 .name = "3c59x",
1026 .probe = vortex_eisa_probe,
1027 .remove = vortex_eisa_remove
1028 }
1029};
1030
1031static int vortex_eisa_probe (struct device *device)
1032{
62afe595 1033 void __iomem *ioaddr;
1da177e4
LT		 1034 struct eisa_device *edev;
1035
1036 edev = to_eisa_device (device);
1da177e4 1037
62afe595 1038 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 1039 return -EBUSY;
1040
62afe595
JL		 1041 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
1042
1043 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 1044 edev->id.driver_data, vortex_cards_found)) {
62afe595 1045 release_region (edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1046 return -ENODEV;
1047 }
1048
1049 vortex_cards_found++;
1050
1051 return 0;
1052}
1053
1054static int vortex_eisa_remove (struct device *device)
1055{
1056 struct eisa_device *edev;
1057 struct net_device *dev;
1058 struct vortex_private *vp;
62afe595 1059 void __iomem *ioaddr;
1da177e4
LT		 1060
1061 edev = to_eisa_device (device);
1062 dev = eisa_get_drvdata (edev);
1063
1064 if (!dev) {
1065 printk("vortex_eisa_remove called for Compaq device!\n");
1066 BUG();
1067 }
1068
1069 vp = netdev_priv(dev);
62afe595 1070 ioaddr = vp->ioaddr;
1da177e4
LT		 1071
1072 unregister_netdev (dev);
62afe595
JL		 1073 iowrite16 (TotalReset|0x14, ioaddr + EL3_CMD);
1074 release_region (dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1075
1076 free_netdev (dev);
1077 return 0;
1078}
1079#endif
1080
1081/* returns count found (>= 0), or negative on error */
1082static int __init vortex_eisa_init (void)
1083{
1084 int eisa_found = 0;
1085 int orig_cards_found = vortex_cards_found;
1086
1087#ifdef CONFIG_EISA
1088 if (eisa_driver_register (&vortex_eisa_driver) >= 0) {
1089 /* Because of the way EISA bus is probed, we cannot assume
1090 * any device have been found when we exit from
1091 * eisa_driver_register (the bus root driver may not be
1092 * initialized yet). So we blindly assume something was
1093 * found, and let the sysfs magic happend... */
1094
1095 eisa_found = 1;
1096 }
1097#endif
1098
1099 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1100 if (compaq_ioaddr) {
62afe595
JL		 1101 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
1102 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 1103 }
1104
1105 return vortex_cards_found - orig_cards_found + eisa_found;
1106}
1107
1108/* returns count (>= 0), or negative on error */
1109static int __devinit vortex_init_one (struct pci_dev *pdev,
1110 const struct pci_device_id *ent)
1111{
1112 int rc;
1113
1114 /* wake up and enable device */
1115 rc = pci_enable_device (pdev);
1116 if (rc < 0)
1117 goto out;
1118
62afe595
JL		 1119 rc = vortex_probe1 (&pdev->dev, pci_iomap(pdev, 0, 0),
1120 pdev->irq, ent->driver_data, vortex_cards_found);
1da177e4
LT		 1121 if (rc < 0) {
1122 pci_disable_device (pdev);
1123 goto out;
1124 }
1125
1126 vortex_cards_found++;
1127
1128out:
1129 return rc;
1130}
1131
1132/*
1133 * Start up the PCI/EISA device which is described by *gendev.
1134 * Return 0 on success.
1135 *
1136 * NOTE: pdev can be NULL, for the case of a Compaq device
1137 */
1138static int __devinit vortex_probe1(struct device *gendev,
62afe595 1139 void __iomem *ioaddr, int irq,
1da177e4
LT		 1140 int chip_idx, int card_idx)
1141{
1142 struct vortex_private *vp;
1143 int option;
1144 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1145 int i, step;
1146 struct net_device *dev;
1147 static int printed_version;
1148 int retval, print_info;
1149 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1150 char *print_name = "3c59x";
1151 struct pci_dev *pdev = NULL;
1152 struct eisa_device *edev = NULL;
1153
1154 if (!printed_version) {
1155 printk (version);
1156 printed_version = 1;
1157 }
1158
1159 if (gendev) {
1160 if ((pdev = DEVICE_PCI(gendev))) {
1161 print_name = pci_name(pdev);
1162 }
1163
1164 if ((edev = DEVICE_EISA(gendev))) {
1165 print_name = edev->dev.bus_id;
1166 }
1167 }
1168
1169 dev = alloc_etherdev(sizeof(*vp));
1170 retval = -ENOMEM;
1171 if (!dev) {
1172 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1173 goto out;
1174 }
1175 SET_MODULE_OWNER(dev);
1176 SET_NETDEV_DEV(dev, gendev);
1177 vp = netdev_priv(dev);
1178
1179 option = global_options;
1180
1181 /* The lower four bits are the media type. */
1182 if (dev->mem_start) {
1183 /*
1184 * The 'options' param is passed in as the third arg to the
1185 * LILO 'ether=' argument for non-modular use
1186 */
1187 option = dev->mem_start;
1188 }
1189 else if (card_idx < MAX_UNITS) {
1190 if (options[card_idx] >= 0)
1191 option = options[card_idx];
1192 }
1193
1194 if (option > 0) {
1195 if (option & 0x8000)
1196 vortex_debug = 7;
1197 if (option & 0x4000)
1198 vortex_debug = 2;
1199 if (option & 0x0400)
1200 vp->enable_wol = 1;
1201 }
1202
1203 print_info = (vortex_debug > 1);
1204 if (print_info)
1205 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1206
62afe595 1207 printk(KERN_INFO "%s: 3Com %s %s at %p. Vers " DRV_VERSION "\n",
1da177e4
LT		 1208 print_name,
1209 pdev ? "PCI" : "EISA",
1210 vci->name,
1211 ioaddr);
1212
62afe595 1213 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1214 dev->irq = irq;
1215 dev->mtu = mtu;
62afe595 1216 vp->ioaddr = ioaddr;
1da177e4
LT		 1217 vp->large_frames = mtu > 1500;
1218 vp->drv_flags = vci->drv_flags;
1219 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1220 vp->io_size = vci->io_size;
1221 vp->card_idx = card_idx;
1222
1223 /* module list only for Compaq device */
1224 if (gendev == NULL) {
1225 compaq_net_device = dev;
1226 }
1227
1228 /* PCI-only startup logic */
1229 if (pdev) {
1230 /* EISA resources already marked, so only PCI needs to do this here */
1231 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1232 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1233 vp->must_free_region = 1;
1234
1235 /* enable bus-mastering if necessary */
1236 if (vci->flags & PCI_USES_MASTER)
1237 pci_set_master (pdev);
1238
1239 if (vci->drv_flags & IS_VORTEX) {
1240 u8 pci_latency;
1241 u8 new_latency = 248;
1242
1243 /* Check the PCI latency value. On the 3c590 series the latency timer
1244 must be set to the maximum value to avoid data corruption that occurs
1245 when the timer expires during a transfer. This bug exists the Vortex
1246 chip only. */
1247 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1248 if (pci_latency < new_latency) {
1249 printk(KERN_INFO "%s: Overriding PCI latency"
1250 " timer (CFLT) setting of %d, new value is %d.\n",
1251 print_name, pci_latency, new_latency);
1252 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1253 }
1254 }
1255 }
1256
1257 spin_lock_init(&vp->lock);
1258 vp->gendev = gendev;
1259 vp->mii.dev = dev;
1260 vp->mii.mdio_read = mdio_read;
1261 vp->mii.mdio_write = mdio_write;
1262 vp->mii.phy_id_mask = 0x1f;
1263 vp->mii.reg_num_mask = 0x1f;
1264
1265 /* Makes sure rings are at least 16 byte aligned. */
1266 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1267 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1268 &vp->rx_ring_dma);
1269 retval = -ENOMEM;
1270 if (vp->rx_ring == 0)
1271 goto free_region;
1272
1273 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1274 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1275
1276 /* if we are a PCI driver, we store info in pdev->driver_data
1277 * instead of a module list */
1278 if (pdev)
1279 pci_set_drvdata(pdev, dev);
1280 if (edev)
1281 eisa_set_drvdata (edev, dev);
1282
1283 vp->media_override = 7;
1284 if (option >= 0) {
1285 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1286 if (vp->media_override != 7)
1287 vp->medialock = 1;
1288 vp->full_duplex = (option & 0x200) ? 1 : 0;
1289 vp->bus_master = (option & 16) ? 1 : 0;
1290 }
1291
1292 if (global_full_duplex > 0)
1293 vp->full_duplex = 1;
1294 if (global_enable_wol > 0)
1295 vp->enable_wol = 1;
1296
1297 if (card_idx < MAX_UNITS) {
1298 if (full_duplex[card_idx] > 0)
1299 vp->full_duplex = 1;
1300 if (flow_ctrl[card_idx] > 0)
1301 vp->flow_ctrl = 1;
1302 if (enable_wol[card_idx] > 0)
1303 vp->enable_wol = 1;
1304 }
1305
1306 vp->force_fd = vp->full_duplex;
1307 vp->options = option;
1308 /* Read the station address from the EEPROM. */
1309 EL3WINDOW(0);
1310 {
1311 int base;
1312
1313 if (vci->drv_flags & EEPROM_8BIT)
1314 base = 0x230;
1315 else if (vci->drv_flags & EEPROM_OFFSET)
1316 base = EEPROM_Read + 0x30;
1317 else
1318 base = EEPROM_Read;
1319
1320 for (i = 0; i < 0x40; i++) {
1321 int timer;
62afe595 1322 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1323 /* Pause for at least 162 us. for the read to take place. */
1324 for (timer = 10; timer >= 0; timer--) {
1325 udelay(162);
62afe595 1326 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1327 break;
1328 }
62afe595 1329 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1330 }
1331 }
1332 for (i = 0; i < 0x18; i++)
1333 checksum ^= eeprom[i];
1334 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1335 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1336 while (i < 0x21)
1337 checksum ^= eeprom[i++];
1338 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1339 }
1340 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1341 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1342 for (i = 0; i < 3; i++)
1343 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1344 if (print_info) {
1345 for (i = 0; i < 6; i++)
1346 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1347 }
1348 /* Unfortunately an all zero eeprom passes the checksum and this
1349 gets found in the wild in failure cases. Crypto is hard 8) */
1350 if (!is_valid_ether_addr(dev->dev_addr)) {
1351 retval = -EINVAL;
1352 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1353 goto free_ring; /* With every pack */
1354 }
1355 EL3WINDOW(2);
1356 for (i = 0; i < 6; i++)
62afe595 1357 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4
LT		 1358
1359#ifdef __sparc__
1360 if (print_info)
1361 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1362#else
1363 if (print_info)
1364 printk(", IRQ %d\n", dev->irq);
1365 /* Tell them about an invalid IRQ. */
1366 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1367 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1368 dev->irq);
1369#endif
1370
1371 EL3WINDOW(4);
62afe595 1372 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1373 if (print_info) {
1374 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1375 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1376 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1377 }
1378
1379
1380 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1381 unsigned short n;
1382
62afe595
JL		 1383 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1384 if (!vp->cb_fn_base) {
1da177e4 1385 retval = -ENOMEM;
62afe595 1386 goto free_ring;
1da177e4 1387 }
62afe595 1388
1da177e4
LT		 1389 if (print_info) {
1390 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
62afe595
JL		 1391 print_name, pci_resource_start(pdev, 2),
1392 vp->cb_fn_base);
1da177e4
LT		 1393 }
1394 EL3WINDOW(2);
1395
62afe595 1396 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1397 if (vp->drv_flags & INVERT_LED_PWR)
1398 n |= 0x10;
1399 if (vp->drv_flags & INVERT_MII_PWR)
1400 n |= 0x4000;
62afe595 1401 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1402 if (vp->drv_flags & WNO_XCVR_PWR) {
1403 EL3WINDOW(0);
62afe595 1404 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1405 }
1406 }
1407
1408 /* Extract our information from the EEPROM data. */
1409 vp->info1 = eeprom[13];
1410 vp->info2 = eeprom[15];
1411 vp->capabilities = eeprom[16];
1412
1413 if (vp->info1 & 0x8000) {
1414 vp->full_duplex = 1;
1415 if (print_info)
1416 printk(KERN_INFO "Full duplex capable\n");
1417 }
1418
1419 {
1420 static const char * ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1421 unsigned int config;
1422 EL3WINDOW(3);
62afe595 1423 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1424 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1425 vp->available_media = 0x40;
62afe595 1426 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1427 if (print_info) {
1428 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1429 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1430 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1431 8 << RAM_SIZE(config),
1432 RAM_WIDTH(config) ? "word" : "byte",
1433 ram_split[RAM_SPLIT(config)],
1434 AUTOSELECT(config) ? "autoselect/" : "",
1435 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1436 media_tbl[XCVR(config)].name);
1437 }
1438 vp->default_media = XCVR(config);
1439 if (vp->default_media == XCVR_NWAY)
1440 vp->has_nway = 1;
1441 vp->autoselect = AUTOSELECT(config);
1442 }
1443
1444 if (vp->media_override != 7) {
1445 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1446 print_name, vp->media_override,
1447 media_tbl[vp->media_override].name);
1448 dev->if_port = vp->media_override;
1449 } else
1450 dev->if_port = vp->default_media;
1451
1452 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1453 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1454 int phy, phy_idx = 0;
1455 EL3WINDOW(4);
1456 mii_preamble_required++;
1457 if (vp->drv_flags & EXTRA_PREAMBLE)
1458 mii_preamble_required++;
1459 mdio_sync(ioaddr, 32);
1460 mdio_read(dev, 24, 1);
1461 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1462 int mii_status, phyx;
1463
1464 /*
1465 * For the 3c905CX we look at index 24 first, because it bogusly
1466 * reports an external PHY at all indices
1467 */
1468 if (phy == 0)
1469 phyx = 24;
1470 else if (phy <= 24)
1471 phyx = phy - 1;
1472 else
1473 phyx = phy;
1474 mii_status = mdio_read(dev, phyx, 1);
1475 if (mii_status && mii_status != 0xffff) {
1476 vp->phys[phy_idx++] = phyx;
1477 if (print_info) {
1478 printk(KERN_INFO " MII transceiver found at address %d,"
1479 " status %4x.\n", phyx, mii_status);
1480 }
1481 if ((mii_status & 0x0040) == 0)
1482 mii_preamble_required++;
1483 }
1484 }
1485 mii_preamble_required--;
1486 if (phy_idx == 0) {
1487 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1488 vp->phys[0] = 24;
1489 } else {
1490 vp->advertising = mdio_read(dev, vp->phys[0], 4);
1491 if (vp->full_duplex) {
1492 /* Only advertise the FD media types. */
1493 vp->advertising &= ~0x02A0;
1494 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1495 }
1496 }
1497 vp->mii.phy_id = vp->phys[0];
1498 }
1499
1500 if (vp->capabilities & CapBusMaster) {
1501 vp->full_bus_master_tx = 1;
1502 if (print_info) {
1503 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1504 (vp->info2 & 1) ? "early" : "whole-frame" );
1505 }
1506 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1507 vp->bus_master = 0; /* AKPM: vortex only */
1508 }
1509
1510 /* The 3c59x-specific entries in the device structure. */
1511 dev->open = vortex_open;
1512 if (vp->full_bus_master_tx) {
1513 dev->hard_start_xmit = boomerang_start_xmit;
1514 /* Actually, it still should work with iommu. */
1515 dev->features |= NETIF_F_SG;
1516 if (((hw_checksums[card_idx] == -1) && (vp->drv_flags & HAS_HWCKSM)) ||
1517 (hw_checksums[card_idx] == 1)) {
1518 dev->features |= NETIF_F_IP_CSUM;
1519 }
1520 } else {
1521 dev->hard_start_xmit = vortex_start_xmit;
1522 }
1523
1524 if (print_info) {
1525 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1526 print_name,
1527 (dev->features & NETIF_F_SG) ? "en":"dis",
1528 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1529 }
1530
1531 dev->stop = vortex_close;
1532 dev->get_stats = vortex_get_stats;
1533#ifdef CONFIG_PCI
1534 dev->do_ioctl = vortex_ioctl;
1535#endif
1536 dev->ethtool_ops = &vortex_ethtool_ops;
1537 dev->set_multicast_list = set_rx_mode;
1538 dev->tx_timeout = vortex_tx_timeout;
1539 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1540#ifdef CONFIG_NET_POLL_CONTROLLER
1541 dev->poll_controller = poll_vortex;
1542#endif
1543 if (pdev) {
1544 vp->pm_state_valid = 1;
1545 pci_save_state(VORTEX_PCI(vp));
1546 acpi_set_WOL(dev);
1547 }
1548 retval = register_netdev(dev);
1549 if (retval == 0)
1550 return 0;
1551
1552free_ring:
1553 pci_free_consistent(pdev,
1554 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1555 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1556 vp->rx_ring,
1557 vp->rx_ring_dma);
1558free_region:
1559 if (vp->must_free_region)
62afe595 1560 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1561 free_netdev(dev);
1562 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1563out:
1564 return retval;
1565}
1566
1567static void
1568issue_and_wait(struct net_device *dev, int cmd)
1569{
62afe595
JL		 1570 struct vortex_private *vp = netdev_priv(dev);
1571 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1572 int i;
1573
62afe595 1574 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1575 for (i = 0; i < 2000; i++) {
62afe595 1576 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1577 return;
1578 }
1579
1580 /* OK, that didn't work. Do it the slow way. One second */
1581 for (i = 0; i < 100000; i++) {
62afe595 1582 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1583 if (vortex_debug > 1)
1584 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1585 dev->name, cmd, i * 10);
1586 return;
1587 }
1588 udelay(10);
1589 }
1590 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1591 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1592}
1593
1594static void
1595vortex_up(struct net_device *dev)
1596{
1da177e4 1597 struct vortex_private *vp = netdev_priv(dev);
62afe595 1598 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1599 unsigned int config;
1600 int i;
1601
1602 if (VORTEX_PCI(vp)) {
1603 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1604 if (vp->pm_state_valid)
1605 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1606 pci_enable_device(VORTEX_PCI(vp));
1607 }
1608
1609 /* Before initializing select the active media port. */
1610 EL3WINDOW(3);
62afe595 1611 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1612
1613 if (vp->media_override != 7) {
1614 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1615 dev->name, vp->media_override,
1616 media_tbl[vp->media_override].name);
1617 dev->if_port = vp->media_override;
1618 } else if (vp->autoselect) {
1619 if (vp->has_nway) {
1620 if (vortex_debug > 1)
1621 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1622 dev->name, dev->if_port);
1623 dev->if_port = XCVR_NWAY;
1624 } else {
1625 /* Find first available media type, starting with 100baseTx. */
1626 dev->if_port = XCVR_100baseTx;
1627 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1628 dev->if_port = media_tbl[dev->if_port].next;
1629 if (vortex_debug > 1)
1630 printk(KERN_INFO "%s: first available media type: %s\n",
1631 dev->name, media_tbl[dev->if_port].name);
1632 }
1633 } else {
1634 dev->if_port = vp->default_media;
1635 if (vortex_debug > 1)
1636 printk(KERN_INFO "%s: using default media %s\n",
1637 dev->name, media_tbl[dev->if_port].name);
1638 }
1639
1640 init_timer(&vp->timer);
1641 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1642 vp->timer.data = (unsigned long)dev;
1643 vp->timer.function = vortex_timer; /* timer handler */
1644 add_timer(&vp->timer);
1645
1646 init_timer(&vp->rx_oom_timer);
1647 vp->rx_oom_timer.data = (unsigned long)dev;
1648 vp->rx_oom_timer.function = rx_oom_timer;
1649
1650 if (vortex_debug > 1)
1651 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1652 dev->name, media_tbl[dev->if_port].name);
1653
1654 vp->full_duplex = vp->force_fd;
1655 config = BFINS(config, dev->if_port, 20, 4);
1656 if (vortex_debug > 6)
1657 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1658 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1659
1660 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1661 int mii_reg1, mii_reg5;
1662 EL3WINDOW(4);
1663 /* Read BMSR (reg1) only to clear old status. */
1664 mii_reg1 = mdio_read(dev, vp->phys[0], 1);
1665 mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1666 if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) {
1667 netif_carrier_off(dev); /* No MII device or no link partner report */
1668 } else {
1669 mii_reg5 &= vp->advertising;
1670 if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1671 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1672 vp->full_duplex = 1;
1673 netif_carrier_on(dev);
1674 }
1675 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1676 if (vortex_debug > 1)
1677 printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1678 " info1 %04x, setting %s-duplex.\n",
1679 dev->name, vp->phys[0],
1680 mii_reg1, mii_reg5,
1681 vp->info1, ((vp->info1 & 0x8000) || vp->full_duplex) ? "full" : "half");
1682 EL3WINDOW(3);
1683 }
1684
1685 /* Set the full-duplex bit. */
62afe595 1686 iowrite16( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1da177e4
LT		 1687 (vp->large_frames ? 0x40 : 0) |
1688 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1689 ioaddr + Wn3_MAC_Ctrl);
1690
1691 if (vortex_debug > 1) {
1692 printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",
1693 dev->name, config);
1694 }
1695
1696 issue_and_wait(dev, TxReset);
1697 /*
1698 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1699 */
1700 issue_and_wait(dev, RxReset|0x04);
1701
62afe595 1702 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1703
1704 if (vortex_debug > 1) {
1705 EL3WINDOW(4);
1706 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1707 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1708 }
1709
1710 /* Set the station address and mask in window 2 each time opened. */
1711 EL3WINDOW(2);
1712 for (i = 0; i < 6; i++)
62afe595 1713 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1714 for (; i < 12; i+=2)
62afe595 1715 iowrite16(0, ioaddr + i);
1da177e4
LT		 1716
1717 if (vp->cb_fn_base) {
62afe595 1718 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1719 if (vp->drv_flags & INVERT_LED_PWR)
1720 n |= 0x10;
1721 if (vp->drv_flags & INVERT_MII_PWR)
1722 n |= 0x4000;
62afe595 1723 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1724 }
1725
1726 if (dev->if_port == XCVR_10base2)
1727 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1728 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1729 if (dev->if_port != XCVR_NWAY) {
1730 EL3WINDOW(4);
62afe595 1731 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1732 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1733 }
1734
1735 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1736 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1737 EL3WINDOW(6);
1738 for (i = 0; i < 10; i++)
62afe595
JL		 1739 ioread8(ioaddr + i);
1740 ioread16(ioaddr + 10);
1741 ioread16(ioaddr + 12);
1da177e4
LT		 1742 /* New: On the Vortex we must also clear the BadSSD counter. */
1743 EL3WINDOW(4);
62afe595 1744 ioread8(ioaddr + 12);
1da177e4 1745 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1746 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1747
1748 /* Switch to register set 7 for normal use. */
1749 EL3WINDOW(7);
1750
1751 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1752 vp->cur_rx = vp->dirty_rx = 0;
1753 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1754 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1755 iowrite32(0x0020, ioaddr + PktStatus);
1756 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1757 }
1758 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1759 vp->cur_tx = vp->dirty_tx = 0;
1760 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1761 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1762 /* Clear the Rx, Tx rings. */
1763 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1764 vp->rx_ring[i].status = 0;
1765 for (i = 0; i < TX_RING_SIZE; i++)
1766 vp->tx_skbuff[i] = NULL;
62afe595 1767 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1768 }
1769 /* Set receiver mode: presumably accept b-case and phys addr only. */
1770 set_rx_mode(dev);
1771 /* enable 802.1q tagged frames */
1772 set_8021q_mode(dev, 1);
62afe595 1773 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4
LT		 1774
1775// issue_and_wait(dev, SetTxStart|0x07ff);
62afe595
JL		 1776 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1777 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1778 /* Allow status bits to be seen. */
1779 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1780 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1781 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1782 (vp->bus_master ? DMADone : 0);
1783 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1784 (vp->full_bus_master_rx ? 0 : RxComplete) |
1785 StatsFull | HostError | TxComplete | IntReq
1786 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1787 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1788 /* Ack all pending events, and set active indicator mask. */
62afe595 1789 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1790 ioaddr + EL3_CMD);
62afe595 1791 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1792 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1793 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1794 netif_start_queue (dev);
1795}
1796
1797static int
1798vortex_open(struct net_device *dev)
1799{
1800 struct vortex_private *vp = netdev_priv(dev);
1801 int i;
1802 int retval;
1803
1804 /* Use the now-standard shared IRQ implementation. */
1805 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1806 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1807 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1808 goto out;
1809 }
1810
1811 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1812 if (vortex_debug > 2)
1813 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1814 for (i = 0; i < RX_RING_SIZE; i++) {
1815 struct sk_buff *skb;
1816 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1817 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1818 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1819 skb = dev_alloc_skb(PKT_BUF_SZ);
1820 vp->rx_skbuff[i] = skb;
1821 if (skb == NULL)
1822 break; /* Bad news! */
1823 skb->dev = dev; /* Mark as being used by this device. */
1824 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1825 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1826 }
1827 if (i != RX_RING_SIZE) {
1828 int j;
1829 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1830 for (j = 0; j < i; j++) {
1831 if (vp->rx_skbuff[j]) {
1832 dev_kfree_skb(vp->rx_skbuff[j]);
1833 vp->rx_skbuff[j] = NULL;
1834 }
1835 }
1836 retval = -ENOMEM;
1837 goto out_free_irq;
1838 }
1839 /* Wrap the ring. */
1840 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1841 }
1842
1843 vortex_up(dev);
1844 return 0;
1845
1846out_free_irq:
1847 free_irq(dev->irq, dev);
1848out:
1849 if (vortex_debug > 1)
1850 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1851 return retval;
1852}
1853
1854static void
1855vortex_timer(unsigned long data)
1856{
1857 struct net_device *dev = (struct net_device *)data;
1858 struct vortex_private *vp = netdev_priv(dev);
62afe595 1859 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1860 int next_tick = 60*HZ;
1861 int ok = 0;
1862 int media_status, mii_status, old_window;
1863
1864 if (vortex_debug > 2) {
1865 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1866 dev->name, media_tbl[dev->if_port].name);
1867 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1868 }
1869
1870 if (vp->medialock)
1871 goto leave_media_alone;
1872 disable_irq(dev->irq);
62afe595 1873 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1874 EL3WINDOW(4);
62afe595 1875 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1876 switch (dev->if_port) {
1877 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1878 if (media_status & Media_LnkBeat) {
1879 netif_carrier_on(dev);
1880 ok = 1;
1881 if (vortex_debug > 1)
1882 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1883 dev->name, media_tbl[dev->if_port].name, media_status);
1884 } else {
1885 netif_carrier_off(dev);
1886 if (vortex_debug > 1) {
1887 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1888 dev->name, media_tbl[dev->if_port].name, media_status);
1889 }
1890 }
1891 break;
1892 case XCVR_MII: case XCVR_NWAY:
1893 {
1894 spin_lock_bh(&vp->lock);
1895 mii_status = mdio_read(dev, vp->phys[0], 1);
2de93fbf 1896 mii_status = mdio_read(dev, vp->phys[0], 1);
1da177e4
LT		 1897 ok = 1;
1898 if (vortex_debug > 2)
1899 printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1900 dev->name, mii_status);
1901 if (mii_status & BMSR_LSTATUS) {
1902 int mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1903 if (! vp->force_fd && mii_reg5 != 0xffff) {
1904 int duplex;
1905
1906 mii_reg5 &= vp->advertising;
1907 duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
1908 if (vp->full_duplex != duplex) {
1909 vp->full_duplex = duplex;
1910 printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1911 "#%d link partner capability of %4.4x.\n",
1912 dev->name, vp->full_duplex ? "full" : "half",
1913 vp->phys[0], mii_reg5);
1914 /* Set the full-duplex bit. */
1915 EL3WINDOW(3);
62afe595 1916 iowrite16( (vp->full_duplex ? 0x20 : 0) |
1da177e4
LT		 1917 (vp->large_frames ? 0x40 : 0) |
1918 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1919 ioaddr + Wn3_MAC_Ctrl);
1920 if (vortex_debug > 1)
1921 printk(KERN_DEBUG "Setting duplex in Wn3_MAC_Ctrl\n");
1922 /* AKPM: bug: should reset Tx and Rx after setting Duplex. Page 180 */
1923 }
1924 }
1925 netif_carrier_on(dev);
1926 } else {
1927 netif_carrier_off(dev);
1928 }
1929 spin_unlock_bh(&vp->lock);
1930 }
1931 break;
1932 default: /* Other media types handled by Tx timeouts. */
1933 if (vortex_debug > 1)
1934 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1935 dev->name, media_tbl[dev->if_port].name, media_status);
1936 ok = 1;
1937 }
1938 if ( ! ok) {
1939 unsigned int config;
1940
1941 do {
1942 dev->if_port = media_tbl[dev->if_port].next;
1943 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1944 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1945 dev->if_port = vp->default_media;
1946 if (vortex_debug > 1)
1947 printk(KERN_DEBUG "%s: Media selection failing, using default "
1948 "%s port.\n",
1949 dev->name, media_tbl[dev->if_port].name);
1950 } else {
1951 if (vortex_debug > 1)
1952 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1953 "%s port.\n",
1954 dev->name, media_tbl[dev->if_port].name);
1955 next_tick = media_tbl[dev->if_port].wait;
1956 }
62afe595 1957 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1958 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1959
1960 EL3WINDOW(3);
62afe595 1961 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1962 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1963 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1964
62afe595 1965 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1966 ioaddr + EL3_CMD);
1967 if (vortex_debug > 1)
1968 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1969 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1970 }
1971 EL3WINDOW(old_window);
1972 enable_irq(dev->irq);
1973
1974leave_media_alone:
1975 if (vortex_debug > 2)
1976 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1977 dev->name, media_tbl[dev->if_port].name);
1978
1979 mod_timer(&vp->timer, RUN_AT(next_tick));
1980 if (vp->deferred)
62afe595 1981 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1982 return;
1983}
1984
1985static void vortex_tx_timeout(struct net_device *dev)
1986{
1987 struct vortex_private *vp = netdev_priv(dev);
62afe595 1988 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1989
1990 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1991 dev->name, ioread8(ioaddr + TxStatus),
1992 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1993 EL3WINDOW(4);
1994 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1995 ioread16(ioaddr + Wn4_NetDiag),
1996 ioread16(ioaddr + Wn4_Media),
1997 ioread32(ioaddr + PktStatus),
1998 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1999 /* Slight code bloat to be user friendly. */
62afe595 2000 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 2001 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
2002 " network cable problem?\n", dev->name);
62afe595 2003 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 2004 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2005 " IRQ blocked by another device?\n", dev->name);
2006 /* Bad idea here.. but we might as well handle a few events. */
2007 {
2008 /*
2009 * Block interrupts because vortex_interrupt does a bare spin_lock()
2010 */
2011 unsigned long flags;
2012 local_irq_save(flags);
2013 if (vp->full_bus_master_tx)
2014 boomerang_interrupt(dev->irq, dev, NULL);
2015 else
2016 vortex_interrupt(dev->irq, dev, NULL);
2017 local_irq_restore(flags);
2018 }
2019 }
2020
2021 if (vortex_debug > 0)
2022 dump_tx_ring(dev);
2023
2024 issue_and_wait(dev, TxReset);
2025
2026 vp->stats.tx_errors++;
2027 if (vp->full_bus_master_tx) {
2028 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 2029 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
2030 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 2031 ioaddr + DownListPtr);
2032 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2033 netif_wake_queue (dev);
2034 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 2035 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2036 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2037 } else {
2038 vp->stats.tx_dropped++;
2039 netif_wake_queue(dev);
2040 }
2041
2042 /* Issue Tx Enable */
62afe595 2043 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2044 dev->trans_start = jiffies;
2045
2046 /* Switch to register set 7 for normal use. */
2047 EL3WINDOW(7);
2048}
2049
2050/*
2051 * Handle uncommon interrupt sources. This is a separate routine to minimize
2052 * the cache impact.
2053 */
2054static void
2055vortex_error(struct net_device *dev, int status)
2056{
2057 struct vortex_private *vp = netdev_priv(dev);
62afe595 2058 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2059 int do_tx_reset = 0, reset_mask = 0;
2060 unsigned char tx_status = 0;
2061
2062 if (vortex_debug > 2) {
2063 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2064 }
2065
2066 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 2067 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 2068 /* Presumably a tx-timeout. We must merely re-enable. */
2069 if (vortex_debug > 2
2070 || (tx_status != 0x88 && vortex_debug > 0)) {
2071 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2072 dev->name, tx_status);
2073 if (tx_status == 0x82) {
2074 printk(KERN_ERR "Probably a duplex mismatch. See "
2075 "Documentation/networking/vortex.txt\n");
2076 }
2077 dump_tx_ring(dev);
2078 }
2079 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2080 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
62afe595 2081 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 2082 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2083 do_tx_reset = 1;
2084 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
2085 do_tx_reset = 1;
2086 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2087 } else { /* Merely re-enable the transmitter. */
62afe595 2088 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2089 }
2090 }
2091
2092 if (status & RxEarly) { /* Rx early is unused. */
2093 vortex_rx(dev);
62afe595 2094 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 2095 }
2096 if (status & StatsFull) { /* Empty statistics. */
2097 static int DoneDidThat;
2098 if (vortex_debug > 4)
2099 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2100 update_stats(ioaddr, dev);
2101 /* HACK: Disable statistics as an interrupt source. */
2102 /* This occurs when we have the wrong media type! */
2103 if (DoneDidThat == 0 &&
62afe595 2104 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 2105 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2106 "stats as an interrupt source.\n", dev->name);
2107 EL3WINDOW(5);
62afe595 2108 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 2109 vp->intr_enable &= ~StatsFull;
2110 EL3WINDOW(7);
2111 DoneDidThat++;
2112 }
2113 }
2114 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2115 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2116 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2117 }
2118 if (status & HostError) {
2119 u16 fifo_diag;
2120 EL3WINDOW(4);
62afe595 2121 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 2122 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2123 dev->name, fifo_diag);
2124 /* Adapter failure requires Tx/Rx reset and reinit. */
2125 if (vp->full_bus_master_tx) {
62afe595 2126 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2127 /* 0x80000000 PCI master abort. */
2128 /* 0x40000000 PCI target abort. */
2129 if (vortex_debug)
2130 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2131
2132 /* In this case, blow the card away */
2133 /* Must not enter D3 or we can't legally issue the reset! */
2134 vortex_down(dev, 0);
2135 issue_and_wait(dev, TotalReset | 0xff);
2136 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2137 } else if (fifo_diag & 0x0400)
2138 do_tx_reset = 1;
2139 if (fifo_diag & 0x3000) {
2140 /* Reset Rx fifo and upload logic */
2141 issue_and_wait(dev, RxReset|0x07);
2142 /* Set the Rx filter to the current state. */
2143 set_rx_mode(dev);
2144 /* enable 802.1q VLAN tagged frames */
2145 set_8021q_mode(dev, 1);
62afe595
JL		 2146 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2147 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2148 }
2149 }
2150
2151 if (do_tx_reset) {
2152 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2153 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2154 if (!vp->full_bus_master_tx)
2155 netif_wake_queue(dev);
2156 }
2157}
2158
2159static int
2160vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2161{
2162 struct vortex_private *vp = netdev_priv(dev);
62afe595 2163 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2164
2165 /* Put out the doubleword header... */
62afe595 2166 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2167 if (vp->bus_master) {
2168 /* Set the bus-master controller to transfer the packet. */
2169 int len = (skb->len + 3) & ~3;
62afe595 2170 iowrite32( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2171 ioaddr + Wn7_MasterAddr);
62afe595 2172 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2173 vp->tx_skb = skb;
62afe595 2174 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2175 /* netif_wake_queue() will be called at the DMADone interrupt. */
2176 } else {
2177 /* ... and the packet rounded to a doubleword. */
62afe595 2178 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2179 dev_kfree_skb (skb);
62afe595 2180 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2181 netif_start_queue (dev); /* AKPM: redundant? */
2182 } else {
2183 /* Interrupt us when the FIFO has room for max-sized packet. */
2184 netif_stop_queue(dev);
62afe595 2185 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2186 }
2187 }
2188
2189 dev->trans_start = jiffies;
2190
2191 /* Clear the Tx status stack. */
2192 {
2193 int tx_status;
2194 int i = 32;
2195
62afe595 2196 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2197 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2198 if (vortex_debug > 2)
2199 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2200 dev->name, tx_status);
2201 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2202 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2203 if (tx_status & 0x30) {
2204 issue_and_wait(dev, TxReset);
2205 }
62afe595 2206 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2207 }
62afe595 2208 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2209 }
2210 }
2211 return 0;
2212}
2213
2214static int
2215boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2216{
2217 struct vortex_private *vp = netdev_priv(dev);
62afe595 2218 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2219 /* Calculate the next Tx descriptor entry. */
2220 int entry = vp->cur_tx % TX_RING_SIZE;
2221 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2222 unsigned long flags;
2223
2224 if (vortex_debug > 6) {
2225 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2226 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2227 dev->name, vp->cur_tx);
1da177e4
LT		 2228 }
2229
2230 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2231 if (vortex_debug > 0)
2232 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2233 dev->name);
2234 netif_stop_queue(dev);
2235 return 1;
2236 }
2237
2238 vp->tx_skbuff[entry] = skb;
2239
2240 vp->tx_ring[entry].next = 0;
2241#if DO_ZEROCOPY
2242 if (skb->ip_summed != CHECKSUM_HW)
2243 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2244 else
2245 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2246
2247 if (!skb_shinfo(skb)->nr_frags) {
2248 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2249 skb->len, PCI_DMA_TODEVICE));
2250 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2251 } else {
2252 int i;
2253
2254 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2255 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2256 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2257
2258 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2259 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2260
2261 vp->tx_ring[entry].frag[i+1].addr =
2262 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2263 (void*)page_address(frag->page) + frag->page_offset,
2264 frag->size, PCI_DMA_TODEVICE));
2265
2266 if (i == skb_shinfo(skb)->nr_frags-1)
2267 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2268 else
2269 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2270 }
2271 }
2272#else
2273 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2274 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2275 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2276#endif
2277
2278 spin_lock_irqsave(&vp->lock, flags);
2279 /* Wait for the stall to complete. */
2280 issue_and_wait(dev, DownStall);
2281 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2282 if (ioread32(ioaddr + DownListPtr) == 0) {
2283 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2284 vp->queued_packet++;
2285 }
2286
2287 vp->cur_tx++;
2288 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2289 netif_stop_queue (dev);
2290 } else { /* Clear previous interrupt enable. */
2291#if defined(tx_interrupt_mitigation)
2292 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2293 * were selected, this would corrupt DN_COMPLETE. No?
2294 */
2295 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2296#endif
2297 }
62afe595 2298 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2299 spin_unlock_irqrestore(&vp->lock, flags);
2300 dev->trans_start = jiffies;
2301 return 0;
2302}
2303
2304/* The interrupt handler does all of the Rx thread work and cleans up
2305 after the Tx thread. */
2306
2307/*
2308 * This is the ISR for the vortex series chips.
2309 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2310 */
2311
2312static irqreturn_t
2313vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2314{
2315 struct net_device *dev = dev_id;
2316 struct vortex_private *vp = netdev_priv(dev);
62afe595 2317 void __iomem *ioaddr;
1da177e4
LT		 2318 int status;
2319 int work_done = max_interrupt_work;
2320 int handled = 0;
2321
62afe595 2322 ioaddr = vp->ioaddr;
1da177e4
LT		 2323 spin_lock(&vp->lock);
2324
62afe595 2325 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2326
2327 if (vortex_debug > 6)
2328 printk("vortex_interrupt(). status=0x%4x\n", status);
2329
2330 if ((status & IntLatch) == 0)
2331 goto handler_exit; /* No interrupt: shared IRQs cause this */
2332 handled = 1;
2333
2334 if (status & IntReq) {
2335 status |= vp->deferred;
2336 vp->deferred = 0;
2337 }
2338
2339 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2340 goto handler_exit;
2341
2342 if (vortex_debug > 4)
2343 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2344 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2345
2346 do {
2347 if (vortex_debug > 5)
2348 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2349 dev->name, status);
2350 if (status & RxComplete)
2351 vortex_rx(dev);
2352
2353 if (status & TxAvailable) {
2354 if (vortex_debug > 5)
2355 printk(KERN_DEBUG " TX room bit was handled.\n");
2356 /* There's room in the FIFO for a full-sized packet. */
62afe595 2357 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2358 netif_wake_queue (dev);
2359 }
2360
2361 if (status & DMADone) {
62afe595
JL		 2362 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2363 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2364 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2365 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2366 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2367 /*
2368 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2369 * insufficient FIFO room, the TxAvailable test will succeed and call
2370 * netif_wake_queue()
2371 */
2372 netif_wake_queue(dev);
2373 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2374 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2375 netif_stop_queue(dev);
2376 }
2377 }
2378 }
2379 /* Check for all uncommon interrupts at once. */
2380 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2381 if (status == 0xffff)
2382 break;
2383 vortex_error(dev, status);
2384 }
2385
2386 if (--work_done < 0) {
2387 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2388 "%4.4x.\n", dev->name, status);
2389 /* Disable all pending interrupts. */
2390 do {
2391 vp->deferred |= status;
62afe595 2392 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2393 ioaddr + EL3_CMD);
62afe595
JL		 2394 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2395 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2396 /* The timer will reenable interrupts. */
2397 mod_timer(&vp->timer, jiffies + 1*HZ);
2398 break;
2399 }
2400 /* Acknowledge the IRQ. */
62afe595
JL		 2401 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2402 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2403
2404 if (vortex_debug > 4)
2405 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2406 dev->name, status);
2407handler_exit:
2408 spin_unlock(&vp->lock);
2409 return IRQ_RETVAL(handled);
2410}
2411
2412/*
2413 * This is the ISR for the boomerang series chips.
2414 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2415 */
2416
2417static irqreturn_t
2418boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2419{
2420 struct net_device *dev = dev_id;
2421 struct vortex_private *vp = netdev_priv(dev);
62afe595 2422 void __iomem *ioaddr;
1da177e4
LT		 2423 int status;
2424 int work_done = max_interrupt_work;
2425
62afe595 2426 ioaddr = vp->ioaddr;
1da177e4
LT		 2427
2428 /*
2429 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2430 * and boomerang_start_xmit
2431 */
2432 spin_lock(&vp->lock);
2433
62afe595 2434 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2435
2436 if (vortex_debug > 6)
2437 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2438
2439 if ((status & IntLatch) == 0)
2440 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2441
2442 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2443 if (vortex_debug > 1)
2444 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2445 goto handler_exit;
2446 }
2447
2448 if (status & IntReq) {
2449 status |= vp->deferred;
2450 vp->deferred = 0;
2451 }
2452
2453 if (vortex_debug > 4)
2454 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2455 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2456 do {
2457 if (vortex_debug > 5)
2458 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2459 dev->name, status);
2460 if (status & UpComplete) {
62afe595 2461 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2462 if (vortex_debug > 5)
2463 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2464 boomerang_rx(dev);
2465 }
2466
2467 if (status & DownComplete) {
2468 unsigned int dirty_tx = vp->dirty_tx;
2469
62afe595 2470 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2471 while (vp->cur_tx - dirty_tx > 0) {
2472 int entry = dirty_tx % TX_RING_SIZE;
2473#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2474 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2475 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2476 break; /* It still hasn't been processed. */
2477#else
2478 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2479 break; /* It still hasn't been processed. */
2480#endif
2481
2482 if (vp->tx_skbuff[entry]) {
2483 struct sk_buff *skb = vp->tx_skbuff[entry];
2484#if DO_ZEROCOPY
2485 int i;
2486 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2487 pci_unmap_single(VORTEX_PCI(vp),
2488 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2489 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2490 PCI_DMA_TODEVICE);
2491#else
2492 pci_unmap_single(VORTEX_PCI(vp),
2493 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2494#endif
2495 dev_kfree_skb_irq(skb);
2496 vp->tx_skbuff[entry] = NULL;
2497 } else {
2498 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2499 }
2500 /* vp->stats.tx_packets++; Counted below. */
2501 dirty_tx++;
2502 }
2503 vp->dirty_tx = dirty_tx;
2504 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2505 if (vortex_debug > 6)
2506 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2507 netif_wake_queue (dev);
2508 }
2509 }
2510
2511 /* Check for all uncommon interrupts at once. */
2512 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2513 vortex_error(dev, status);
2514
2515 if (--work_done < 0) {
2516 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2517 "%4.4x.\n", dev->name, status);
2518 /* Disable all pending interrupts. */
2519 do {
2520 vp->deferred |= status;
62afe595 2521 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2522 ioaddr + EL3_CMD);
62afe595
JL		 2523 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2524 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2525 /* The timer will reenable interrupts. */
2526 mod_timer(&vp->timer, jiffies + 1*HZ);
2527 break;
2528 }
2529 /* Acknowledge the IRQ. */
62afe595 2530 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2531 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2532 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2533
62afe595 2534 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2535
2536 if (vortex_debug > 4)
2537 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2538 dev->name, status);
2539handler_exit:
2540 spin_unlock(&vp->lock);
2541 return IRQ_HANDLED;
2542}
2543
2544static int vortex_rx(struct net_device *dev)
2545{
2546 struct vortex_private *vp = netdev_priv(dev);
62afe595 2547 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2548 int i;
2549 short rx_status;
2550
2551 if (vortex_debug > 5)
2552 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2553 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2554 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2555 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2556 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2557 if (vortex_debug > 2)
2558 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2559 vp->stats.rx_errors++;
2560 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2561 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2562 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2563 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2564 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2565 } else {
2566 /* The packet length: up to 4.5K!. */
2567 int pkt_len = rx_status & 0x1fff;
2568 struct sk_buff *skb;
2569
2570 skb = dev_alloc_skb(pkt_len + 5);
2571 if (vortex_debug > 4)
2572 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2573 pkt_len, rx_status);
2574 if (skb != NULL) {
2575 skb->dev = dev;
2576 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2577 /* 'skb_put()' points to the start of sk_buff data area. */
2578 if (vp->bus_master &&
62afe595 2579 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2580 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2581 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2582 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2583 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2584 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2585 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2586 ;
2587 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2588 } else {
62afe595
JL		 2589 ioread32_rep(ioaddr + RX_FIFO,
2590 skb_put(skb, pkt_len),
2591 (pkt_len + 3) >> 2);
1da177e4 2592 }
62afe595 2593 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2594 skb->protocol = eth_type_trans(skb, dev);
2595 netif_rx(skb);
2596 dev->last_rx = jiffies;
2597 vp->stats.rx_packets++;
2598 /* Wait a limited time to go to next packet. */
2599 for (i = 200; i >= 0; i--)
62afe595 2600 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2601 break;
2602 continue;
2603 } else if (vortex_debug > 0)
2604 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2605 "size %d.\n", dev->name, pkt_len);
2606 }
2607 vp->stats.rx_dropped++;
2608 issue_and_wait(dev, RxDiscard);
2609 }
2610
2611 return 0;
2612}
2613
2614static int
2615boomerang_rx(struct net_device *dev)
2616{
2617 struct vortex_private *vp = netdev_priv(dev);
2618 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2619 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2620 int rx_status;
2621 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2622
2623 if (vortex_debug > 5)
62afe595 2624 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2625
2626 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2627 if (--rx_work_limit < 0)
2628 break;
2629 if (rx_status & RxDError) { /* Error, update stats. */
2630 unsigned char rx_error = rx_status >> 16;
2631 if (vortex_debug > 2)
2632 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2633 vp->stats.rx_errors++;
2634 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2635 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2636 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2637 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2638 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2639 } else {
2640 /* The packet length: up to 4.5K!. */
2641 int pkt_len = rx_status & 0x1fff;
2642 struct sk_buff *skb;
2643 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2644
2645 if (vortex_debug > 4)
2646 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2647 pkt_len, rx_status);
2648
2649 /* Check if the packet is long enough to just accept without
2650 copying to a properly sized skbuff. */
2651 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2652 skb->dev = dev;
2653 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2654 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2655 /* 'skb_put()' points to the start of sk_buff data area. */
2656 memcpy(skb_put(skb, pkt_len),
689be439 2657 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2658 pkt_len);
2659 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2660 vp->rx_copy++;
2661 } else {
2662 /* Pass up the skbuff already on the Rx ring. */
2663 skb = vp->rx_skbuff[entry];
2664 vp->rx_skbuff[entry] = NULL;
2665 skb_put(skb, pkt_len);
2666 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2667 vp->rx_nocopy++;
2668 }
2669 skb->protocol = eth_type_trans(skb, dev);
2670 { /* Use hardware checksum info. */
2671 int csum_bits = rx_status & 0xee000000;
2672 if (csum_bits &&
2673 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2674 csum_bits == (IPChksumValid | UDPChksumValid))) {
2675 skb->ip_summed = CHECKSUM_UNNECESSARY;
2676 vp->rx_csumhits++;
2677 }
2678 }
2679 netif_rx(skb);
2680 dev->last_rx = jiffies;
2681 vp->stats.rx_packets++;
2682 }
2683 entry = (++vp->cur_rx) % RX_RING_SIZE;
2684 }
2685 /* Refill the Rx ring buffers. */
2686 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2687 struct sk_buff *skb;
2688 entry = vp->dirty_rx % RX_RING_SIZE;
2689 if (vp->rx_skbuff[entry] == NULL) {
2690 skb = dev_alloc_skb(PKT_BUF_SZ);
2691 if (skb == NULL) {
2692 static unsigned long last_jif;
2693 if ((jiffies - last_jif) > 10 * HZ) {
2694 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2695 last_jif = jiffies;
2696 }
2697 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2698 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2699 break; /* Bad news! */
2700 }
2701 skb->dev = dev; /* Mark as being used by this device. */
2702 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2703 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2704 vp->rx_skbuff[entry] = skb;
2705 }
2706 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2707 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2708 }
2709 return 0;
2710}
2711
2712/*
2713 * If we've hit a total OOM refilling the Rx ring we poll once a second
2714 * for some memory. Otherwise there is no way to restart the rx process.
2715 */
2716static void
2717rx_oom_timer(unsigned long arg)
2718{
2719 struct net_device *dev = (struct net_device *)arg;
2720 struct vortex_private *vp = netdev_priv(dev);
2721
2722 spin_lock_irq(&vp->lock);
2723 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2724 boomerang_rx(dev);
2725 if (vortex_debug > 1) {
2726 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2727 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2728 }
2729 spin_unlock_irq(&vp->lock);
2730}
2731
2732static void
2733vortex_down(struct net_device *dev, int final_down)
2734{
2735 struct vortex_private *vp = netdev_priv(dev);
62afe595 2736 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2737
2738 netif_stop_queue (dev);
2739
2740 del_timer_sync(&vp->rx_oom_timer);
2741 del_timer_sync(&vp->timer);
2742
2743 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2744 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2745
2746 /* Disable the receiver and transmitter. */
62afe595
JL		 2747 iowrite16(RxDisable, ioaddr + EL3_CMD);
2748 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2749
2750 /* Disable receiving 802.1q tagged frames */
2751 set_8021q_mode(dev, 0);
2752
2753 if (dev->if_port == XCVR_10base2)
2754 /* Turn off thinnet power. Green! */
62afe595 2755 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2756
62afe595 2757 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2758
2759 update_stats(ioaddr, dev);
2760 if (vp->full_bus_master_rx)
62afe595 2761 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2762 if (vp->full_bus_master_tx)
62afe595 2763 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2764
2765 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2766 vp->pm_state_valid = 1;
1da177e4
LT		 2767 pci_save_state(VORTEX_PCI(vp));
2768 acpi_set_WOL(dev);
2769 }
2770}
2771
2772static int
2773vortex_close(struct net_device *dev)
2774{
2775 struct vortex_private *vp = netdev_priv(dev);
62afe595 2776 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2777 int i;
2778
2779 if (netif_device_present(dev))
2780 vortex_down(dev, 1);
2781
2782 if (vortex_debug > 1) {
2783 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2784 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2785 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2786 " tx_queued %d Rx pre-checksummed %d.\n",
2787 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2788 }
2789
2790#if DO_ZEROCOPY
2791 if ( vp->rx_csumhits &&
2792 ((vp->drv_flags & HAS_HWCKSM) == 0) &&
2793 (hw_checksums[vp->card_idx] == -1)) {
2794 printk(KERN_WARNING "%s supports hardware checksums, and we're not using them!\n", dev->name);
2795 }
2796#endif
2797
2798 free_irq(dev->irq, dev);
2799
2800 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2801 for (i = 0; i < RX_RING_SIZE; i++)
2802 if (vp->rx_skbuff[i]) {
2803 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2804 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2805 dev_kfree_skb(vp->rx_skbuff[i]);
2806 vp->rx_skbuff[i] = NULL;
2807 }
2808 }
2809 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2810 for (i = 0; i < TX_RING_SIZE; i++) {
2811 if (vp->tx_skbuff[i]) {
2812 struct sk_buff *skb = vp->tx_skbuff[i];
2813#if DO_ZEROCOPY
2814 int k;
2815
2816 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2817 pci_unmap_single(VORTEX_PCI(vp),
2818 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2819 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2820 PCI_DMA_TODEVICE);
2821#else
2822 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2823#endif
2824 dev_kfree_skb(skb);
2825 vp->tx_skbuff[i] = NULL;
2826 }
2827 }
2828 }
2829
2830 return 0;
2831}
2832
2833static void
2834dump_tx_ring(struct net_device *dev)
2835{
2836 if (vortex_debug > 0) {
2837 struct vortex_private *vp = netdev_priv(dev);
62afe595 2838 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2839
2840 if (vp->full_bus_master_tx) {
2841 int i;
62afe595 2842 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2843
2844 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2845 vp->full_bus_master_tx,
2846 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2847 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2848 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2849 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2850 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2851 issue_and_wait(dev, DownStall);
2852 for (i = 0; i < TX_RING_SIZE; i++) {
2853 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2854 &vp->tx_ring[i],
2855#if DO_ZEROCOPY
2856 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2857#else
2858 le32_to_cpu(vp->tx_ring[i].length),
2859#endif
2860 le32_to_cpu(vp->tx_ring[i].status));
2861 }
2862 if (!stalled)
62afe595 2863 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2864 }
2865 }
2866}
2867
2868static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2869{
2870 struct vortex_private *vp = netdev_priv(dev);
62afe595 2871 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2872 unsigned long flags;
2873
2874 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2875 spin_lock_irqsave (&vp->lock, flags);
62afe595 2876 update_stats(ioaddr, dev);
1da177e4
LT		 2877 spin_unlock_irqrestore (&vp->lock, flags);
2878 }
2879 return &vp->stats;
2880}
2881
2882/* Update statistics.
2883 Unlike with the EL3 we need not worry about interrupts changing
2884 the window setting from underneath us, but we must still guard
2885 against a race condition with a StatsUpdate interrupt updating the
2886 table. This is done by checking that the ASM (!) code generated uses
2887 atomic updates with '+='.
2888 */
62afe595 2889static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2890{
2891 struct vortex_private *vp = netdev_priv(dev);
62afe595 2892 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2893
2894 if (old_window == 0xffff) /* Chip suspended or ejected. */
2895 return;
2896 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2897 /* Switch to the stats window, and read everything. */
2898 EL3WINDOW(6);
62afe595
JL		 2899 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2900 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2901 vp->stats.collisions += ioread8(ioaddr + 3);
2902 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2903 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2904 vp->stats.tx_packets += ioread8(ioaddr + 6);
2905 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2906 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2907 /* Don't bother with register 9, an extension of registers 6&7.
2908 If we do use the 6&7 values the atomic update assumption above
2909 is invalid. */
62afe595
JL		 2910 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2911 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2912 /* Extra stats for get_ethtool_stats() */
62afe595
JL		 2913 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2914 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2915 EL3WINDOW(4);
62afe595 2916 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4
LT		 2917
2918 {
62afe595 2919 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2920 vp->stats.rx_bytes += (up & 0x0f) << 16;
2921 vp->stats.tx_bytes += (up & 0xf0) << 12;
2922 }
2923
2924 EL3WINDOW(old_window >> 13);
2925 return;
2926}
2927
2928static int vortex_nway_reset(struct net_device *dev)
2929{
2930 struct vortex_private *vp = netdev_priv(dev);
62afe595 2931 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2932 unsigned long flags;
2933 int rc;
2934
2935 spin_lock_irqsave(&vp->lock, flags);
2936 EL3WINDOW(4);
2937 rc = mii_nway_restart(&vp->mii);
2938 spin_unlock_irqrestore(&vp->lock, flags);
2939 return rc;
2940}
2941
2942static u32 vortex_get_link(struct net_device *dev)
2943{
2944 struct vortex_private *vp = netdev_priv(dev);
62afe595 2945 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2946 unsigned long flags;
2947 int rc;
2948
2949 spin_lock_irqsave(&vp->lock, flags);
2950 EL3WINDOW(4);
2951 rc = mii_link_ok(&vp->mii);
2952 spin_unlock_irqrestore(&vp->lock, flags);
2953 return rc;
2954}
2955
2956static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2957{
2958 struct vortex_private *vp = netdev_priv(dev);
62afe595 2959 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2960 unsigned long flags;
2961 int rc;
2962
2963 spin_lock_irqsave(&vp->lock, flags);
2964 EL3WINDOW(4);
2965 rc = mii_ethtool_gset(&vp->mii, cmd);
2966 spin_unlock_irqrestore(&vp->lock, flags);
2967 return rc;
2968}
2969
2970static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2971{
2972 struct vortex_private *vp = netdev_priv(dev);
62afe595 2973 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2974 unsigned long flags;
2975 int rc;
2976
2977 spin_lock_irqsave(&vp->lock, flags);
2978 EL3WINDOW(4);
2979 rc = mii_ethtool_sset(&vp->mii, cmd);
2980 spin_unlock_irqrestore(&vp->lock, flags);
2981 return rc;
2982}
2983
2984static u32 vortex_get_msglevel(struct net_device *dev)
2985{
2986 return vortex_debug;
2987}
2988
2989static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2990{
2991 vortex_debug = dbg;
2992}
2993
2994static int vortex_get_stats_count(struct net_device *dev)
2995{
2996 return VORTEX_NUM_STATS;
2997}
2998
2999static void vortex_get_ethtool_stats(struct net_device *dev,
3000 struct ethtool_stats *stats, u64 *data)
3001{
3002 struct vortex_private *vp = netdev_priv(dev);
62afe595 3003 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3004 unsigned long flags;
3005
3006 spin_lock_irqsave(&vp->lock, flags);
62afe595 3007 update_stats(ioaddr, dev);
1da177e4
LT		 3008 spin_unlock_irqrestore(&vp->lock, flags);
3009
3010 data[0] = vp->xstats.tx_deferred;
3011 data[1] = vp->xstats.tx_multiple_collisions;
3012 data[2] = vp->xstats.rx_bad_ssd;
3013}
3014
3015
3016static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3017{
3018 switch (stringset) {
3019 case ETH_SS_STATS:
3020 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
3021 break;
3022 default:
3023 WARN_ON(1);
3024 break;
3025 }
3026}
3027
3028static void vortex_get_drvinfo(struct net_device *dev,
3029 struct ethtool_drvinfo *info)
3030{
3031 struct vortex_private *vp = netdev_priv(dev);
3032
3033 strcpy(info->driver, DRV_NAME);
3034 strcpy(info->version, DRV_VERSION);
3035 if (VORTEX_PCI(vp)) {
3036 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3037 } else {
3038 if (VORTEX_EISA(vp))
3039 sprintf(info->bus_info, vp->gendev->bus_id);
3040 else
3041 sprintf(info->bus_info, "EISA 0x%lx %d",
3042 dev->base_addr, dev->irq);
3043 }
3044}
3045
3046static struct ethtool_ops vortex_ethtool_ops = {
3047 .get_drvinfo = vortex_get_drvinfo,
3048 .get_strings = vortex_get_strings,
3049 .get_msglevel = vortex_get_msglevel,
3050 .set_msglevel = vortex_set_msglevel,
3051 .get_ethtool_stats = vortex_get_ethtool_stats,
3052 .get_stats_count = vortex_get_stats_count,
3053 .get_settings = vortex_get_settings,
3054 .set_settings = vortex_set_settings,
3055 .get_link = vortex_get_link,
3056 .nway_reset = vortex_nway_reset,
3057};
3058
3059#ifdef CONFIG_PCI
3060/*
3061 * Must power the device up to do MDIO operations
3062 */
3063static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3064{
3065 int err;
3066 struct vortex_private *vp = netdev_priv(dev);
62afe595 3067 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3068 unsigned long flags;
3069 int state = 0;
3070
3071 if(VORTEX_PCI(vp))
3072 state = VORTEX_PCI(vp)->current_state;
3073
3074 /* The kernel core really should have pci_get_power_state() */
3075
3076 if(state != 0)
3077 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3078 spin_lock_irqsave(&vp->lock, flags);
3079 EL3WINDOW(4);
3080 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3081 spin_unlock_irqrestore(&vp->lock, flags);
3082 if(state != 0)
3083 pci_set_power_state(VORTEX_PCI(vp), state);
3084
3085 return err;
3086}
3087#endif
3088
3089
3090/* Pre-Cyclone chips have no documented multicast filter, so the only
3091 multicast setting is to receive all multicast frames. At least
3092 the chip has a very clean way to set the mode, unlike many others. */
3093static void set_rx_mode(struct net_device *dev)
3094{
62afe595
JL		 3095 struct vortex_private *vp = netdev_priv(dev);
3096 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3097 int new_mode;
3098
3099 if (dev->flags & IFF_PROMISC) {
3100 if (vortex_debug > 0)
3101 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3102 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3103 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3104 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3105 } else
3106 new_mode = SetRxFilter | RxStation | RxBroadcast;
3107
62afe595 3108 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3109}
3110
3111#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3112/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3113 Note that this must be done after each RxReset due to some backwards
3114 compatibility logic in the Cyclone and Tornado ASICs */
3115
3116/* The Ethernet Type used for 802.1q tagged frames */
3117#define VLAN_ETHER_TYPE 0x8100
3118
3119static void set_8021q_mode(struct net_device *dev, int enable)
3120{
3121 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 3122 void __iomem *ioaddr = vp->ioaddr;
3123 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 3124 int mac_ctrl;
3125
3126 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3127 /* cyclone and tornado chipsets can recognize 802.1q
3128 * tagged frames and treat them correctly */
3129
3130 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3131 if (enable)
3132 max_pkt_size += 4; /* 802.1Q VLAN tag */
3133
3134 EL3WINDOW(3);
62afe595 3135 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3136
3137 /* set VlanEtherType to let the hardware checksumming
3138 treat tagged frames correctly */
3139 EL3WINDOW(7);
62afe595 3140 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3141 } else {
3142 /* on older cards we have to enable large frames */
3143
3144 vp->large_frames = dev->mtu > 1500 || enable;
3145
3146 EL3WINDOW(3);
62afe595 3147 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3148 if (vp->large_frames)
3149 mac_ctrl |= 0x40;
3150 else
3151 mac_ctrl &= ~0x40;
62afe595 3152 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3153 }
3154
3155 EL3WINDOW(old_window);
3156}
3157#else
3158
3159static void set_8021q_mode(struct net_device *dev, int enable)
3160{
3161}
3162
3163
3164#endif
3165
3166/* MII transceiver control section.
3167 Read and write the MII registers using software-generated serial
3168 MDIO protocol. See the MII specifications or DP83840A data sheet
3169 for details. */
3170
3171/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3172 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3173 "overclocking" issues. */
62afe595 3174#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3175
3176#define MDIO_SHIFT_CLK 0x01
3177#define MDIO_DIR_WRITE 0x04
3178#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3179#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3180#define MDIO_DATA_READ 0x02
3181#define MDIO_ENB_IN 0x00
3182
3183/* Generate the preamble required for initial synchronization and
3184 a few older transceivers. */
62afe595 3185static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3186{
62afe595 3187 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3188
3189 /* Establish sync by sending at least 32 logic ones. */
3190 while (-- bits >= 0) {
62afe595 3191 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3192 mdio_delay();
62afe595 3193 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3194 mdio_delay();
3195 }
3196}
3197
3198static int mdio_read(struct net_device *dev, int phy_id, int location)
3199{
3200 int i;
62afe595
JL		 3201 struct vortex_private *vp = netdev_priv(dev);
3202 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3203 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3204 unsigned int retval = 0;
62afe595 3205 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3206
3207 if (mii_preamble_required)
3208 mdio_sync(ioaddr, 32);
3209
3210 /* Shift the read command bits out. */
3211 for (i = 14; i >= 0; i--) {
3212 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3213 iowrite16(dataval, mdio_addr);
1da177e4 3214 mdio_delay();
62afe595 3215 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3216 mdio_delay();
3217 }
3218 /* Read the two transition, 16 data, and wire-idle bits. */
3219 for (i = 19; i > 0; i--) {
62afe595 3220 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3221 mdio_delay();
62afe595
JL		 3222 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3223 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3224 mdio_delay();
3225 }
3226 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3227}
3228
3229static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3230{
62afe595
JL		 3231 struct vortex_private *vp = netdev_priv(dev);
3232 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3233 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3234 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3235 int i;
3236
3237 if (mii_preamble_required)
3238 mdio_sync(ioaddr, 32);
3239
3240 /* Shift the command bits out. */
3241 for (i = 31; i >= 0; i--) {
3242 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3243 iowrite16(dataval, mdio_addr);
1da177e4 3244 mdio_delay();
62afe595 3245 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3246 mdio_delay();
3247 }
3248 /* Leave the interface idle. */
3249 for (i = 1; i >= 0; i--) {
62afe595 3250 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3251 mdio_delay();
62afe595 3252 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3253 mdio_delay();
3254 }
3255 return;
3256}
3257\f
3258/* ACPI: Advanced Configuration and Power Interface. */
3259/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3260static void acpi_set_WOL(struct net_device *dev)
3261{
3262 struct vortex_private *vp = netdev_priv(dev);
62afe595 3263 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3264
3265 if (vp->enable_wol) {
3266 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3267 EL3WINDOW(7);
62afe595 3268 iowrite16(2, ioaddr + 0x0c);
1da177e4 3269 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3270 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3271 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3272
3273 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3274
3275 /* Change the power state to D3; RxEnable doesn't take effect. */
3276 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3277 }
1da177e4
LT		 3278}
3279
3280
3281static void __devexit vortex_remove_one (struct pci_dev *pdev)
3282{
3283 struct net_device *dev = pci_get_drvdata(pdev);
3284 struct vortex_private *vp;
3285
3286 if (!dev) {
3287 printk("vortex_remove_one called for Compaq device!\n");
3288 BUG();
3289 }
3290
3291 vp = netdev_priv(dev);
3292
62afe595
JL		 3293 if (vp->cb_fn_base)
3294 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3295
1da177e4
LT		 3296 unregister_netdev(dev);
3297
3298 if (VORTEX_PCI(vp)) {
3299 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3300 if (vp->pm_state_valid)
3301 pci_restore_state(VORTEX_PCI(vp));
3302 pci_disable_device(VORTEX_PCI(vp));
3303 }
3304 /* Should really use issue_and_wait() here */
62afe595
JL		 3305 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3306 vp->ioaddr + EL3_CMD);
3307
3308 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3309
3310 pci_free_consistent(pdev,
3311 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3312 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3313 vp->rx_ring,
3314 vp->rx_ring_dma);
3315 if (vp->must_free_region)
3316 release_region(dev->base_addr, vp->io_size);
3317 free_netdev(dev);
3318}
3319
3320
3321static struct pci_driver vortex_driver = {
3322 .name = "3c59x",
3323 .probe = vortex_init_one,
3324 .remove = __devexit_p(vortex_remove_one),
3325 .id_table = vortex_pci_tbl,
3326#ifdef CONFIG_PM
3327 .suspend = vortex_suspend,
3328 .resume = vortex_resume,
3329#endif
3330};
3331
3332
3333static int vortex_have_pci;
3334static int vortex_have_eisa;
3335
3336
3337static int __init vortex_init (void)
3338{
3339 int pci_rc, eisa_rc;
3340
3341 pci_rc = pci_module_init(&vortex_driver);
3342 eisa_rc = vortex_eisa_init();
3343
3344 if (pci_rc == 0)
3345 vortex_have_pci = 1;
3346 if (eisa_rc > 0)
3347 vortex_have_eisa = 1;
3348
3349 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3350}
3351
3352
3353static void __exit vortex_eisa_cleanup (void)
3354{
3355 struct vortex_private *vp;
62afe595 3356 void __iomem *ioaddr;
1da177e4
LT		 3357
3358#ifdef CONFIG_EISA
3359 /* Take care of the EISA devices */
3360 eisa_driver_unregister (&vortex_eisa_driver);
3361#endif
3362
3363 if (compaq_net_device) {
3364 vp = compaq_net_device->priv;
62afe595
JL		 3365 ioaddr = ioport_map(compaq_net_device->base_addr,
3366 VORTEX_TOTAL_SIZE);
1da177e4
LT		 3367
3368 unregister_netdev (compaq_net_device);
62afe595
JL		 3369 iowrite16 (TotalReset, ioaddr + EL3_CMD);
3370 release_region(compaq_net_device->base_addr,
3371 VORTEX_TOTAL_SIZE);
1da177e4
LT		 3372
3373 free_netdev (compaq_net_device);
3374 }
3375}
3376
3377
3378static void __exit vortex_cleanup (void)
3379{
3380 if (vortex_have_pci)
3381 pci_unregister_driver (&vortex_driver);
3382 if (vortex_have_eisa)
3383 vortex_eisa_cleanup ();
3384}
3385
3386
3387module_init(vortex_init);
3388module_exit(vortex_cleanup);
3389
3390\f
3391/*
3392 * Local variables:
3393 * c-indent-level: 4
3394 * c-basic-offset: 4
3395 * tab-width: 4
3396 * End:
3397 */
Clone of davem's net-next-2.6 tree