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[RT2x00]: add driver for Ralink wireless hardware
[net-next-2.6.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
1da177e4
LT		 93#include <asm/irq.h> /* For NR_IRQS only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
2c2a8c53 106DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
1f1bd5fc 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
b8a1fcee 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
541 u32 next; /* Last entry points to 0. */
542 s32 status;
543 u32 addr; /* Up to 63 addr/len pairs possible. */
544 s32 length; /* Set LAST_FRAG to indicate last pair. */
545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
561 u32 next; /* Last entry points to 0. */
562 s32 status; /* bits 0:12 length, others see below. */
563#if DO_ZEROCOPY
564 struct {
565 u32 addr;
566 s32 length;
567 } frag[1+MAX_SKB_FRAGS];
568#else
569 u32 addr;
570 s32 length;
571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
62afe595
JL		 610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 623 full_duplex:1, autoselect:1,
1da177e4
LT		 624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647};
648
649#ifdef CONFIG_PCI
650#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651#else
652#define DEVICE_PCI(dev) NULL
653#endif
654
655#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657#ifdef CONFIG_EISA
658#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659#else
660#define DEVICE_EISA(dev) NULL
661#endif
662
663#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665/* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671};
672
f71e1309 673static const struct media_table {
1da177e4
LT		 674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679} media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691};
692
693static struct {
694 const char str[ETH_GSTRING_LEN];
695} ethtool_stats_keys[] = {
696 { "tx_deferred" },
8d1d0340 697 { "tx_max_collisions" },
1da177e4 698 { "tx_multiple_collisions" },
8d1d0340 699 { "tx_single_collisions" },
1da177e4
LT		 700 { "rx_bad_ssd" },
701};
702
703/* number of ETHTOOL_GSTATS u64's */
8d1d0340 704#define VORTEX_NUM_STATS 5
1da177e4 705
62afe595 706static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 707 int chip_idx, int card_idx);
c8303d10 708static int vortex_up(struct net_device *dev);
1da177e4
LT		 709static void vortex_down(struct net_device *dev, int final);
710static int vortex_open(struct net_device *dev);
62afe595 711static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 712static int mdio_read(struct net_device *dev, int phy_id, int location);
713static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714static void vortex_timer(unsigned long arg);
715static void rx_oom_timer(unsigned long arg);
716static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718static int vortex_rx(struct net_device *dev);
719static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 720static irqreturn_t vortex_interrupt(int irq, void *dev_id);
721static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 722static int vortex_close(struct net_device *dev);
723static void dump_tx_ring(struct net_device *dev);
62afe595 724static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 725static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726static void set_rx_mode(struct net_device *dev);
727#ifdef CONFIG_PCI
728static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729#endif
730static void vortex_tx_timeout(struct net_device *dev);
731static void acpi_set_WOL(struct net_device *dev);
7282d491 732static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 733static void set_8021q_mode(struct net_device *dev, int enable);
734
1da177e4
LT		 735/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736/* Option count limit only -- unlimited interfaces are supported. */
737#define MAX_UNITS 8
9954ab7f
JL		 738static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 743static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 744static int global_options = -1;
745static int global_full_duplex = -1;
746static int global_enable_wol = -1;
900fd17d 747static int global_use_mmio = -1;
1da177e4 748
1da177e4
LT		 749/* Variables to work-around the Compaq PCI BIOS32 problem. */
750static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751static struct net_device *compaq_net_device;
752
753static int vortex_cards_found;
754
755module_param(debug, int, 0);
756module_param(global_options, int, 0);
757module_param_array(options, int, NULL, 0);
758module_param(global_full_duplex, int, 0);
759module_param_array(full_duplex, int, NULL, 0);
760module_param_array(hw_checksums, int, NULL, 0);
761module_param_array(flow_ctrl, int, NULL, 0);
762module_param(global_enable_wol, int, 0);
763module_param_array(enable_wol, int, NULL, 0);
764module_param(rx_copybreak, int, 0);
765module_param(max_interrupt_work, int, 0);
766module_param(compaq_ioaddr, int, 0);
767module_param(compaq_irq, int, 0);
768module_param(compaq_device_id, int, 0);
769module_param(watchdog, int, 0);
900fd17d
JL		 770module_param(global_use_mmio, int, 0);
771module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 772MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 776MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 777MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 780MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 781MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 787MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 789
790#ifdef CONFIG_NET_POLL_CONTROLLER
791static void poll_vortex(struct net_device *dev)
792{
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
0d38ff1d 795 local_irq_save(flags);
7d12e780 796 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 797 local_irq_restore(flags);
6aa20a22 798}
1da177e4
LT		 799#endif
800
801#ifdef CONFIG_PM
802
a880c4cd 803static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 804{
805 struct net_device *dev = pci_get_drvdata(pdev);
806
807 if (dev && dev->priv) {
808 if (netif_running(dev)) {
809 netif_device_detach(dev);
810 vortex_down(dev, 1);
811 }
5b039e68
RW		 812 pci_save_state(pdev);
813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
814 free_irq(dev->irq, dev);
815 pci_disable_device(pdev);
816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 817 }
818 return 0;
819}
820
a880c4cd 821static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 822{
823 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 824 struct vortex_private *vp = netdev_priv(dev);
e1265153 825 int err;
1da177e4 826
5b039e68
RW		 827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
e1265153
DM		 830 err = pci_enable_device(pdev);
831 if (err) {
832 printk(KERN_WARNING "%s: Could not enable device \n",
833 dev->name);
834 return err;
835 }
5b039e68
RW		 836 pci_set_master(pdev);
837 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 838 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 839 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
840 pci_disable_device(pdev);
841 return -EBUSY;
842 }
1da177e4 843 if (netif_running(dev)) {
c8303d10
MH		 844 err = vortex_up(dev);
845 if (err)
846 return err;
847 else
848 netif_device_attach(dev);
1da177e4
LT		 849 }
850 }
851 return 0;
852}
853
854#endif /* CONFIG_PM */
855
856#ifdef CONFIG_EISA
857static struct eisa_device_id vortex_eisa_ids[] = {
858 { "TCM5920", CH_3C592 },
859 { "TCM5970", CH_3C597 },
860 { "" }
861};
07563c71 862MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 863
95c408a9 864static int __init vortex_eisa_probe(struct device *device)
1da177e4 865{
62afe595 866 void __iomem *ioaddr;
1da177e4
LT		 867 struct eisa_device *edev;
868
a880c4cd 869 edev = to_eisa_device(device);
1da177e4 870
62afe595 871 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 872 return -EBUSY;
873
62afe595
JL		 874 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
875
876 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 877 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 878 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 879 return -ENODEV;
880 }
881
882 vortex_cards_found++;
883
884 return 0;
885}
886
95c408a9 887static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 888{
889 struct eisa_device *edev;
890 struct net_device *dev;
891 struct vortex_private *vp;
62afe595 892 void __iomem *ioaddr;
1da177e4 893
a880c4cd
SK		 894 edev = to_eisa_device(device);
895 dev = eisa_get_drvdata(edev);
1da177e4
LT		 896
897 if (!dev) {
898 printk("vortex_eisa_remove called for Compaq device!\n");
899 BUG();
900 }
901
902 vp = netdev_priv(dev);
62afe595 903 ioaddr = vp->ioaddr;
6aa20a22 904
a880c4cd
SK		 905 unregister_netdev(dev);
906 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
907 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 908
a880c4cd 909 free_netdev(dev);
1da177e4
LT		 910 return 0;
911}
95c408a9
RB		 912
913static struct eisa_driver vortex_eisa_driver = {
914 .id_table = vortex_eisa_ids,
915 .driver = {
916 .name = "3c59x",
917 .probe = vortex_eisa_probe,
918 .remove = __devexit_p(vortex_eisa_remove)
919 }
920};
921
922#endif /* CONFIG_EISA */
1da177e4
LT		 923
924/* returns count found (>= 0), or negative on error */
a880c4cd 925static int __init vortex_eisa_init(void)
1da177e4
LT		 926{
927 int eisa_found = 0;
928 int orig_cards_found = vortex_cards_found;
929
930#ifdef CONFIG_EISA
c2f6fabb
BH		 931 int err;
932
933 err = eisa_driver_register (&vortex_eisa_driver);
934 if (!err) {
935 /*
936 * Because of the way EISA bus is probed, we cannot assume
937 * any device have been found when we exit from
938 * eisa_driver_register (the bus root driver may not be
939 * initialized yet). So we blindly assume something was
940 * found, and let the sysfs magic happend...
941 */
942 eisa_found = 1;
1da177e4
LT		 943 }
944#endif
6aa20a22 945
1da177e4
LT		 946 /* Special code to work-around the Compaq PCI BIOS32 problem. */
947 if (compaq_ioaddr) {
62afe595
JL		 948 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
949 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 950 }
951
952 return vortex_cards_found - orig_cards_found + eisa_found;
953}
954
955/* returns count (>= 0), or negative on error */
a880c4cd 956static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 957 const struct pci_device_id *ent)
958{
900fd17d
JL		 959 int rc, unit, pci_bar;
960 struct vortex_chip_info *vci;
961 void __iomem *ioaddr;
1da177e4 962
6aa20a22 963 /* wake up and enable device */
a880c4cd 964 rc = pci_enable_device(pdev);
1da177e4
LT		 965 if (rc < 0)
966 goto out;
967
900fd17d
JL		 968 unit = vortex_cards_found;
969
970 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
971 /* Determine the default if the user didn't override us */
972 vci = &vortex_info_tbl[ent->driver_data];
973 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
974 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
975 pci_bar = use_mmio[unit] ? 1 : 0;
976 else
977 pci_bar = global_use_mmio ? 1 : 0;
978
979 ioaddr = pci_iomap(pdev, pci_bar, 0);
980 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
981 ioaddr = pci_iomap(pdev, 0, 0);
982
983 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
984 ent->driver_data, unit);
1da177e4 985 if (rc < 0) {
a880c4cd 986 pci_disable_device(pdev);
1da177e4
LT		 987 goto out;
988 }
989
990 vortex_cards_found++;
991
992out:
993 return rc;
994}
995
996/*
997 * Start up the PCI/EISA device which is described by *gendev.
998 * Return 0 on success.
999 *
1000 * NOTE: pdev can be NULL, for the case of a Compaq device
1001 */
1002static int __devinit vortex_probe1(struct device *gendev,
62afe595 1003 void __iomem *ioaddr, int irq,
1da177e4
LT		 1004 int chip_idx, int card_idx)
1005{
1006 struct vortex_private *vp;
1007 int option;
1008 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1009 int i, step;
1010 struct net_device *dev;
1011 static int printed_version;
1012 int retval, print_info;
1013 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1014 char *print_name = "3c59x";
1015 struct pci_dev *pdev = NULL;
1016 struct eisa_device *edev = NULL;
1017
1018 if (!printed_version) {
1019 printk (version);
1020 printed_version = 1;
1021 }
1022
1023 if (gendev) {
1024 if ((pdev = DEVICE_PCI(gendev))) {
1025 print_name = pci_name(pdev);
1026 }
1027
1028 if ((edev = DEVICE_EISA(gendev))) {
1029 print_name = edev->dev.bus_id;
1030 }
1031 }
1032
1033 dev = alloc_etherdev(sizeof(*vp));
1034 retval = -ENOMEM;
1035 if (!dev) {
1036 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1037 goto out;
1038 }
1da177e4
LT		 1039 SET_NETDEV_DEV(dev, gendev);
1040 vp = netdev_priv(dev);
1041
1042 option = global_options;
1043
1044 /* The lower four bits are the media type. */
1045 if (dev->mem_start) {
1046 /*
1047 * The 'options' param is passed in as the third arg to the
1048 * LILO 'ether=' argument for non-modular use
1049 */
1050 option = dev->mem_start;
1051 }
1052 else if (card_idx < MAX_UNITS) {
1053 if (options[card_idx] >= 0)
1054 option = options[card_idx];
1055 }
1056
1057 if (option > 0) {
1058 if (option & 0x8000)
1059 vortex_debug = 7;
1060 if (option & 0x4000)
1061 vortex_debug = 2;
1062 if (option & 0x0400)
1063 vp->enable_wol = 1;
1064 }
1065
1066 print_info = (vortex_debug > 1);
1067 if (print_info)
1068 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1069
61238602 1070 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1071 print_name,
1072 pdev ? "PCI" : "EISA",
1073 vci->name,
1074 ioaddr);
1075
62afe595 1076 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1077 dev->irq = irq;
1078 dev->mtu = mtu;
62afe595 1079 vp->ioaddr = ioaddr;
1da177e4
LT		 1080 vp->large_frames = mtu > 1500;
1081 vp->drv_flags = vci->drv_flags;
1082 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1083 vp->io_size = vci->io_size;
1084 vp->card_idx = card_idx;
1085
1086 /* module list only for Compaq device */
1087 if (gendev == NULL) {
1088 compaq_net_device = dev;
1089 }
1090
1091 /* PCI-only startup logic */
1092 if (pdev) {
1093 /* EISA resources already marked, so only PCI needs to do this here */
1094 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1095 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1096 vp->must_free_region = 1;
1097
6aa20a22 1098 /* enable bus-mastering if necessary */
1da177e4 1099 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1100 pci_set_master(pdev);
1da177e4
LT		 1101
1102 if (vci->drv_flags & IS_VORTEX) {
1103 u8 pci_latency;
1104 u8 new_latency = 248;
1105
1106 /* Check the PCI latency value. On the 3c590 series the latency timer
1107 must be set to the maximum value to avoid data corruption that occurs
1108 when the timer expires during a transfer. This bug exists the Vortex
1109 chip only. */
1110 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1111 if (pci_latency < new_latency) {
1112 printk(KERN_INFO "%s: Overriding PCI latency"
1113 " timer (CFLT) setting of %d, new value is %d.\n",
1114 print_name, pci_latency, new_latency);
1115 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1116 }
1117 }
1118 }
1119
1120 spin_lock_init(&vp->lock);
1121 vp->gendev = gendev;
1122 vp->mii.dev = dev;
1123 vp->mii.mdio_read = mdio_read;
1124 vp->mii.mdio_write = mdio_write;
1125 vp->mii.phy_id_mask = 0x1f;
1126 vp->mii.reg_num_mask = 0x1f;
1127
1128 /* Makes sure rings are at least 16 byte aligned. */
1129 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1130 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1131 &vp->rx_ring_dma);
1132 retval = -ENOMEM;
1133 if (vp->rx_ring == 0)
1134 goto free_region;
1135
1136 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1137 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1138
1139 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1140 * instead of a module list */
1da177e4
LT		 1141 if (pdev)
1142 pci_set_drvdata(pdev, dev);
1143 if (edev)
a880c4cd 1144 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1145
1146 vp->media_override = 7;
1147 if (option >= 0) {
1148 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1149 if (vp->media_override != 7)
1150 vp->medialock = 1;
1151 vp->full_duplex = (option & 0x200) ? 1 : 0;
1152 vp->bus_master = (option & 16) ? 1 : 0;
1153 }
1154
1155 if (global_full_duplex > 0)
1156 vp->full_duplex = 1;
1157 if (global_enable_wol > 0)
1158 vp->enable_wol = 1;
1159
1160 if (card_idx < MAX_UNITS) {
1161 if (full_duplex[card_idx] > 0)
1162 vp->full_duplex = 1;
1163 if (flow_ctrl[card_idx] > 0)
1164 vp->flow_ctrl = 1;
1165 if (enable_wol[card_idx] > 0)
1166 vp->enable_wol = 1;
1167 }
1168
125d5ce8 1169 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1170 vp->options = option;
1171 /* Read the station address from the EEPROM. */
1172 EL3WINDOW(0);
1173 {
1174 int base;
1175
1176 if (vci->drv_flags & EEPROM_8BIT)
1177 base = 0x230;
1178 else if (vci->drv_flags & EEPROM_OFFSET)
1179 base = EEPROM_Read + 0x30;
1180 else
1181 base = EEPROM_Read;
1182
1183 for (i = 0; i < 0x40; i++) {
1184 int timer;
62afe595 1185 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1186 /* Pause for at least 162 us. for the read to take place. */
1187 for (timer = 10; timer >= 0; timer--) {
1188 udelay(162);
62afe595 1189 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1190 break;
1191 }
62afe595 1192 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1193 }
1194 }
1195 for (i = 0; i < 0x18; i++)
1196 checksum ^= eeprom[i];
1197 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1198 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1199 while (i < 0x21)
1200 checksum ^= eeprom[i++];
1201 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1202 }
1203 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1204 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1205 for (i = 0; i < 3; i++)
1206 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1207 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1208 if (print_info) {
1209 for (i = 0; i < 6; i++)
1210 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1211 }
1212 /* Unfortunately an all zero eeprom passes the checksum and this
1213 gets found in the wild in failure cases. Crypto is hard 8) */
1214 if (!is_valid_ether_addr(dev->dev_addr)) {
1215 retval = -EINVAL;
1216 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1217 goto free_ring; /* With every pack */
1218 }
1219 EL3WINDOW(2);
1220 for (i = 0; i < 6; i++)
62afe595 1221 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1222
1da177e4
LT		 1223 if (print_info)
1224 printk(", IRQ %d\n", dev->irq);
1225 /* Tell them about an invalid IRQ. */
1226 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1227 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1228 dev->irq);
1da177e4
LT		 1229
1230 EL3WINDOW(4);
62afe595 1231 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1232 if (print_info) {
1233 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1234 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1235 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1236 }
1237
1238
1239 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1240 unsigned short n;
1241
62afe595
JL		 1242 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1243 if (!vp->cb_fn_base) {
1da177e4 1244 retval = -ENOMEM;
62afe595 1245 goto free_ring;
1da177e4 1246 }
62afe595 1247
1da177e4 1248 if (print_info) {
7c7459d1
GKH		 1249 printk(KERN_INFO "%s: CardBus functions mapped "
1250 "%16.16llx->%p\n",
1251 print_name,
1252 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1253 vp->cb_fn_base);
1da177e4
LT		 1254 }
1255 EL3WINDOW(2);
1256
62afe595 1257 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1258 if (vp->drv_flags & INVERT_LED_PWR)
1259 n |= 0x10;
1260 if (vp->drv_flags & INVERT_MII_PWR)
1261 n |= 0x4000;
62afe595 1262 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1263 if (vp->drv_flags & WNO_XCVR_PWR) {
1264 EL3WINDOW(0);
62afe595 1265 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1266 }
1267 }
1268
1269 /* Extract our information from the EEPROM data. */
1270 vp->info1 = eeprom[13];
1271 vp->info2 = eeprom[15];
1272 vp->capabilities = eeprom[16];
1273
1274 if (vp->info1 & 0x8000) {
1275 vp->full_duplex = 1;
1276 if (print_info)
1277 printk(KERN_INFO "Full duplex capable\n");
1278 }
1279
1280 {
f71e1309 1281 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1282 unsigned int config;
1283 EL3WINDOW(3);
62afe595 1284 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1285 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1286 vp->available_media = 0x40;
62afe595 1287 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1288 if (print_info) {
1289 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1290 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1291 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1292 8 << RAM_SIZE(config),
1293 RAM_WIDTH(config) ? "word" : "byte",
1294 ram_split[RAM_SPLIT(config)],
1295 AUTOSELECT(config) ? "autoselect/" : "",
1296 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1297 media_tbl[XCVR(config)].name);
1298 }
1299 vp->default_media = XCVR(config);
1300 if (vp->default_media == XCVR_NWAY)
1301 vp->has_nway = 1;
1302 vp->autoselect = AUTOSELECT(config);
1303 }
1304
1305 if (vp->media_override != 7) {
1306 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1307 print_name, vp->media_override,
1308 media_tbl[vp->media_override].name);
1309 dev->if_port = vp->media_override;
1310 } else
1311 dev->if_port = vp->default_media;
1312
1313 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1314 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1315 int phy, phy_idx = 0;
1316 EL3WINDOW(4);
1317 mii_preamble_required++;
1318 if (vp->drv_flags & EXTRA_PREAMBLE)
1319 mii_preamble_required++;
1320 mdio_sync(ioaddr, 32);
106427e6 1321 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1322 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1323 int mii_status, phyx;
1324
1325 /*
1326 * For the 3c905CX we look at index 24 first, because it bogusly
1327 * reports an external PHY at all indices
1328 */
1329 if (phy == 0)
1330 phyx = 24;
1331 else if (phy <= 24)
1332 phyx = phy - 1;
1333 else
1334 phyx = phy;
106427e6 1335 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1336 if (mii_status && mii_status != 0xffff) {
1337 vp->phys[phy_idx++] = phyx;
1338 if (print_info) {
1339 printk(KERN_INFO " MII transceiver found at address %d,"
1340 " status %4x.\n", phyx, mii_status);
1341 }
1342 if ((mii_status & 0x0040) == 0)
1343 mii_preamble_required++;
1344 }
1345 }
1346 mii_preamble_required--;
1347 if (phy_idx == 0) {
1348 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1349 vp->phys[0] = 24;
1350 } else {
106427e6 1351 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1352 if (vp->full_duplex) {
1353 /* Only advertise the FD media types. */
1354 vp->advertising &= ~0x02A0;
1355 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1356 }
1357 }
1358 vp->mii.phy_id = vp->phys[0];
1359 }
1360
1361 if (vp->capabilities & CapBusMaster) {
1362 vp->full_bus_master_tx = 1;
1363 if (print_info) {
1364 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1365 (vp->info2 & 1) ? "early" : "whole-frame" );
1366 }
1367 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1368 vp->bus_master = 0; /* AKPM: vortex only */
1369 }
1370
1371 /* The 3c59x-specific entries in the device structure. */
1372 dev->open = vortex_open;
1373 if (vp->full_bus_master_tx) {
1374 dev->hard_start_xmit = boomerang_start_xmit;
1375 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1376 if (card_idx < MAX_UNITS &&
1377 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1378 hw_checksums[card_idx] == 1)) {
d311b0d3 1379 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1380 }
1381 } else {
1382 dev->hard_start_xmit = vortex_start_xmit;
1383 }
1384
1385 if (print_info) {
1386 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1387 print_name,
1388 (dev->features & NETIF_F_SG) ? "en":"dis",
1389 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1390 }
1391
1392 dev->stop = vortex_close;
1393 dev->get_stats = vortex_get_stats;
1394#ifdef CONFIG_PCI
1395 dev->do_ioctl = vortex_ioctl;
1396#endif
1397 dev->ethtool_ops = &vortex_ethtool_ops;
1398 dev->set_multicast_list = set_rx_mode;
1399 dev->tx_timeout = vortex_tx_timeout;
1400 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1401#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 1402 dev->poll_controller = poll_vortex;
1da177e4
LT		 1403#endif
1404 if (pdev) {
1405 vp->pm_state_valid = 1;
1406 pci_save_state(VORTEX_PCI(vp));
1407 acpi_set_WOL(dev);
1408 }
1409 retval = register_netdev(dev);
1410 if (retval == 0)
1411 return 0;
1412
1413free_ring:
1414 pci_free_consistent(pdev,
1415 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1416 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1417 vp->rx_ring,
1418 vp->rx_ring_dma);
1419free_region:
1420 if (vp->must_free_region)
62afe595 1421 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1422 free_netdev(dev);
1423 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1424out:
1425 return retval;
1426}
1427
1428static void
1429issue_and_wait(struct net_device *dev, int cmd)
1430{
62afe595
JL		 1431 struct vortex_private *vp = netdev_priv(dev);
1432 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1433 int i;
1434
62afe595 1435 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1436 for (i = 0; i < 2000; i++) {
62afe595 1437 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1438 return;
1439 }
1440
1441 /* OK, that didn't work. Do it the slow way. One second */
1442 for (i = 0; i < 100000; i++) {
62afe595 1443 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1444 if (vortex_debug > 1)
1445 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1446 dev->name, cmd, i * 10);
1447 return;
1448 }
1449 udelay(10);
1450 }
1451 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1452 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1453}
1454
125d5ce8
SK		 1455static void
1456vortex_set_duplex(struct net_device *dev)
1457{
1458 struct vortex_private *vp = netdev_priv(dev);
1459 void __iomem *ioaddr = vp->ioaddr;
1460
1461 printk(KERN_INFO "%s: setting %s-duplex.\n",
1462 dev->name, (vp->full_duplex) ? "full" : "half");
1463
1464 EL3WINDOW(3);
1465 /* Set the full-duplex bit. */
1466 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1467 (vp->large_frames ? 0x40 : 0) |
1468 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1469 0x100 : 0),
1470 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1471}
1472
1473static void vortex_check_media(struct net_device *dev, unsigned int init)
1474{
1475 struct vortex_private *vp = netdev_priv(dev);
1476 unsigned int ok_to_print = 0;
1477
1478 if (vortex_debug > 3)
1479 ok_to_print = 1;
1480
1481 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1482 vp->full_duplex = vp->mii.full_duplex;
1483 vortex_set_duplex(dev);
1484 } else if (init) {
1485 vortex_set_duplex(dev);
1486 }
1487}
1488
c8303d10 1489static int
1da177e4
LT		 1490vortex_up(struct net_device *dev)
1491{
1da177e4 1492 struct vortex_private *vp = netdev_priv(dev);
62afe595 1493 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1494 unsigned int config;
c8303d10 1495 int i, mii_reg1, mii_reg5, err;
1da177e4
LT		 1496
1497 if (VORTEX_PCI(vp)) {
1498 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1499 if (vp->pm_state_valid)
1500 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1501 err = pci_enable_device(VORTEX_PCI(vp));
1502 if (err) {
1503 printk(KERN_WARNING "%s: Could not enable device \n",
1504 dev->name);
1505 goto err_out;
1506 }
1da177e4
LT		 1507 }
1508
1509 /* Before initializing select the active media port. */
1510 EL3WINDOW(3);
62afe595 1511 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1512
1513 if (vp->media_override != 7) {
1514 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1515 dev->name, vp->media_override,
1516 media_tbl[vp->media_override].name);
1517 dev->if_port = vp->media_override;
1518 } else if (vp->autoselect) {
1519 if (vp->has_nway) {
1520 if (vortex_debug > 1)
1521 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1522 dev->name, dev->if_port);
1523 dev->if_port = XCVR_NWAY;
1524 } else {
1525 /* Find first available media type, starting with 100baseTx. */
1526 dev->if_port = XCVR_100baseTx;
1527 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1528 dev->if_port = media_tbl[dev->if_port].next;
1529 if (vortex_debug > 1)
1530 printk(KERN_INFO "%s: first available media type: %s\n",
1531 dev->name, media_tbl[dev->if_port].name);
1532 }
1533 } else {
1534 dev->if_port = vp->default_media;
1535 if (vortex_debug > 1)
1536 printk(KERN_INFO "%s: using default media %s\n",
1537 dev->name, media_tbl[dev->if_port].name);
1538 }
1539
1540 init_timer(&vp->timer);
1541 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1542 vp->timer.data = (unsigned long)dev;
1543 vp->timer.function = vortex_timer; /* timer handler */
1544 add_timer(&vp->timer);
1545
1546 init_timer(&vp->rx_oom_timer);
1547 vp->rx_oom_timer.data = (unsigned long)dev;
1548 vp->rx_oom_timer.function = rx_oom_timer;
1549
1550 if (vortex_debug > 1)
1551 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1552 dev->name, media_tbl[dev->if_port].name);
1553
125d5ce8 1554 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1555 config = BFINS(config, dev->if_port, 20, 4);
1556 if (vortex_debug > 6)
1557 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1558 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1559
1560 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1561 EL3WINDOW(4);
09ce3512
SK		 1562 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1563 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1564 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1565 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1566
125d5ce8 1567 vortex_check_media(dev, 1);
1da177e4 1568 }
125d5ce8
SK		 1569 else
1570 vortex_set_duplex(dev);
1da177e4 1571
09ce3512
SK		 1572 issue_and_wait(dev, TxReset);
1573 /*
1574 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1575 */
1576 issue_and_wait(dev, RxReset|0x04);
1577
1da177e4 1578
62afe595 1579 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1580
1581 if (vortex_debug > 1) {
1582 EL3WINDOW(4);
1583 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1584 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1585 }
1586
1587 /* Set the station address and mask in window 2 each time opened. */
1588 EL3WINDOW(2);
1589 for (i = 0; i < 6; i++)
62afe595 1590 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1591 for (; i < 12; i+=2)
62afe595 1592 iowrite16(0, ioaddr + i);
1da177e4
LT		 1593
1594 if (vp->cb_fn_base) {
62afe595 1595 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1596 if (vp->drv_flags & INVERT_LED_PWR)
1597 n |= 0x10;
1598 if (vp->drv_flags & INVERT_MII_PWR)
1599 n |= 0x4000;
62afe595 1600 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1601 }
1602
1603 if (dev->if_port == XCVR_10base2)
1604 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1605 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1606 if (dev->if_port != XCVR_NWAY) {
1607 EL3WINDOW(4);
62afe595 1608 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1609 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1610 }
1611
1612 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1613 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1614 EL3WINDOW(6);
1615 for (i = 0; i < 10; i++)
62afe595
JL		 1616 ioread8(ioaddr + i);
1617 ioread16(ioaddr + 10);
1618 ioread16(ioaddr + 12);
1da177e4
LT		 1619 /* New: On the Vortex we must also clear the BadSSD counter. */
1620 EL3WINDOW(4);
62afe595 1621 ioread8(ioaddr + 12);
1da177e4 1622 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1623 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1624
1625 /* Switch to register set 7 for normal use. */
1626 EL3WINDOW(7);
1627
1628 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1629 vp->cur_rx = vp->dirty_rx = 0;
1630 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1631 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1632 iowrite32(0x0020, ioaddr + PktStatus);
1633 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1634 }
1635 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1636 vp->cur_tx = vp->dirty_tx = 0;
1637 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1638 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1639 /* Clear the Rx, Tx rings. */
1640 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1641 vp->rx_ring[i].status = 0;
1642 for (i = 0; i < TX_RING_SIZE; i++)
1643 vp->tx_skbuff[i] = NULL;
62afe595 1644 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1645 }
1646 /* Set receiver mode: presumably accept b-case and phys addr only. */
1647 set_rx_mode(dev);
1648 /* enable 802.1q tagged frames */
1649 set_8021q_mode(dev, 1);
62afe595 1650 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1651
62afe595
JL		 1652 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1653 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1654 /* Allow status bits to be seen. */
1655 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1656 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1657 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1658 (vp->bus_master ? DMADone : 0);
1659 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1660 (vp->full_bus_master_rx ? 0 : RxComplete) |
1661 StatsFull | HostError | TxComplete | IntReq
1662 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1663 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1664 /* Ack all pending events, and set active indicator mask. */
62afe595 1665 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1666 ioaddr + EL3_CMD);
62afe595 1667 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1668 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1669 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1670 netif_start_queue (dev);
c8303d10
MH		 1671err_out:
1672 return err;
1da177e4
LT		 1673}
1674
1675static int
1676vortex_open(struct net_device *dev)
1677{
1678 struct vortex_private *vp = netdev_priv(dev);
1679 int i;
1680 int retval;
1681
1682 /* Use the now-standard shared IRQ implementation. */
1683 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1684 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4 1685 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1686 goto err;
1da177e4
LT		 1687 }
1688
1689 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1690 if (vortex_debug > 2)
1691 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1692 for (i = 0; i < RX_RING_SIZE; i++) {
1693 struct sk_buff *skb;
1694 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1695 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1696 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1697 skb = dev_alloc_skb(PKT_BUF_SZ);
1698 vp->rx_skbuff[i] = skb;
1699 if (skb == NULL)
1700 break; /* Bad news! */
1701 skb->dev = dev; /* Mark as being used by this device. */
1702 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1703 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1704 }
1705 if (i != RX_RING_SIZE) {
1706 int j;
1707 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1708 for (j = 0; j < i; j++) {
1709 if (vp->rx_skbuff[j]) {
1710 dev_kfree_skb(vp->rx_skbuff[j]);
1711 vp->rx_skbuff[j] = NULL;
1712 }
1713 }
1714 retval = -ENOMEM;
c8303d10 1715 goto err_free_irq;
1da177e4
LT		 1716 }
1717 /* Wrap the ring. */
1718 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1719 }
1720
c8303d10
MH		 1721 retval = vortex_up(dev);
1722 if (!retval)
1723 goto out;
1da177e4 1724
c8303d10 1725err_free_irq:
1da177e4 1726 free_irq(dev->irq, dev);
c8303d10 1727err:
1da177e4
LT		 1728 if (vortex_debug > 1)
1729 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1730out:
1da177e4
LT		 1731 return retval;
1732}
1733
1734static void
1735vortex_timer(unsigned long data)
1736{
1737 struct net_device *dev = (struct net_device *)data;
1738 struct vortex_private *vp = netdev_priv(dev);
62afe595 1739 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1740 int next_tick = 60*HZ;
1741 int ok = 0;
125d5ce8 1742 int media_status, old_window;
1da177e4
LT		 1743
1744 if (vortex_debug > 2) {
1745 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1746 dev->name, media_tbl[dev->if_port].name);
1747 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1748 }
1749
0a9da4bd 1750 disable_irq_lockdep(dev->irq);
62afe595 1751 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1752 EL3WINDOW(4);
62afe595 1753 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1754 switch (dev->if_port) {
1755 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1756 if (media_status & Media_LnkBeat) {
1757 netif_carrier_on(dev);
1758 ok = 1;
1759 if (vortex_debug > 1)
1760 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1761 dev->name, media_tbl[dev->if_port].name, media_status);
1762 } else {
1763 netif_carrier_off(dev);
1764 if (vortex_debug > 1) {
1765 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1766 dev->name, media_tbl[dev->if_port].name, media_status);
1767 }
1768 }
1769 break;
1770 case XCVR_MII: case XCVR_NWAY:
1771 {
1da177e4 1772 ok = 1;
125d5ce8
SK		 1773 spin_lock_bh(&vp->lock);
1774 vortex_check_media(dev, 0);
1da177e4
LT		 1775 spin_unlock_bh(&vp->lock);
1776 }
1777 break;
1778 default: /* Other media types handled by Tx timeouts. */
1779 if (vortex_debug > 1)
1780 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1781 dev->name, media_tbl[dev->if_port].name, media_status);
1782 ok = 1;
1783 }
b4ff6450
SK		 1784
1785 if (!netif_carrier_ok(dev))
1786 next_tick = 5*HZ;
1787
e94d10eb
SK		 1788 if (vp->medialock)
1789 goto leave_media_alone;
1790
a880c4cd 1791 if (!ok) {
1da177e4
LT		 1792 unsigned int config;
1793
1794 do {
1795 dev->if_port = media_tbl[dev->if_port].next;
1796 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1797 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1798 dev->if_port = vp->default_media;
1799 if (vortex_debug > 1)
1800 printk(KERN_DEBUG "%s: Media selection failing, using default "
1801 "%s port.\n",
1802 dev->name, media_tbl[dev->if_port].name);
1803 } else {
1804 if (vortex_debug > 1)
1805 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1806 "%s port.\n",
1807 dev->name, media_tbl[dev->if_port].name);
1808 next_tick = media_tbl[dev->if_port].wait;
1809 }
62afe595 1810 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1811 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1812
1813 EL3WINDOW(3);
62afe595 1814 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1815 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1816 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1817
62afe595 1818 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1819 ioaddr + EL3_CMD);
1820 if (vortex_debug > 1)
1821 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1822 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1823 }
1da177e4
LT		 1824
1825leave_media_alone:
1826 if (vortex_debug > 2)
1827 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1828 dev->name, media_tbl[dev->if_port].name);
1829
e94d10eb 1830 EL3WINDOW(old_window);
0a9da4bd 1831 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1832 mod_timer(&vp->timer, RUN_AT(next_tick));
1833 if (vp->deferred)
62afe595 1834 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1835 return;
1836}
1837
1838static void vortex_tx_timeout(struct net_device *dev)
1839{
1840 struct vortex_private *vp = netdev_priv(dev);
62afe595 1841 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1842
1843 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1844 dev->name, ioread8(ioaddr + TxStatus),
1845 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1846 EL3WINDOW(4);
1847 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1848 ioread16(ioaddr + Wn4_NetDiag),
1849 ioread16(ioaddr + Wn4_Media),
1850 ioread32(ioaddr + PktStatus),
1851 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1852 /* Slight code bloat to be user friendly. */
62afe595 1853 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1854 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1855 " network cable problem?\n", dev->name);
62afe595 1856 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1857 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1858 " IRQ blocked by another device?\n", dev->name);
1859 /* Bad idea here.. but we might as well handle a few events. */
1860 {
1861 /*
1862 * Block interrupts because vortex_interrupt does a bare spin_lock()
1863 */
1864 unsigned long flags;
1865 local_irq_save(flags);
1866 if (vp->full_bus_master_tx)
7d12e780 1867 boomerang_interrupt(dev->irq, dev);
1da177e4 1868 else
7d12e780 1869 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1870 local_irq_restore(flags);
1871 }
1872 }
1873
1874 if (vortex_debug > 0)
1875 dump_tx_ring(dev);
1876
1877 issue_and_wait(dev, TxReset);
1878
1879 vp->stats.tx_errors++;
1880 if (vp->full_bus_master_tx) {
1881 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1882 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1883 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1884 ioaddr + DownListPtr);
1885 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1886 netif_wake_queue (dev);
1887 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1888 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1889 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 1890 } else {
1891 vp->stats.tx_dropped++;
1892 netif_wake_queue(dev);
1893 }
6aa20a22 1894
1da177e4 1895 /* Issue Tx Enable */
62afe595 1896 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1897 dev->trans_start = jiffies;
6aa20a22 1898
1da177e4
LT		 1899 /* Switch to register set 7 for normal use. */
1900 EL3WINDOW(7);
1901}
1902
1903/*
1904 * Handle uncommon interrupt sources. This is a separate routine to minimize
1905 * the cache impact.
1906 */
1907static void
1908vortex_error(struct net_device *dev, int status)
1909{
1910 struct vortex_private *vp = netdev_priv(dev);
62afe595 1911 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1912 int do_tx_reset = 0, reset_mask = 0;
1913 unsigned char tx_status = 0;
1914
1915 if (vortex_debug > 2) {
1916 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1917 }
1918
1919 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1920 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1921 /* Presumably a tx-timeout. We must merely re-enable. */
1922 if (vortex_debug > 2
1923 || (tx_status != 0x88 && vortex_debug > 0)) {
1924 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1925 dev->name, tx_status);
1926 if (tx_status == 0x82) {
1927 printk(KERN_ERR "Probably a duplex mismatch. See "
1928 "Documentation/networking/vortex.txt\n");
1929 }
1930 dump_tx_ring(dev);
1931 }
1932 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1933 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
0000754c 1934 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1935 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1936 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1937 do_tx_reset = 1;
0000754c
AM		 1938 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1939 do_tx_reset = 1;
1940 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1941 } else { /* Merely re-enable the transmitter. */
62afe595 1942 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1943 }
1944 }
1945
1946 if (status & RxEarly) { /* Rx early is unused. */
1947 vortex_rx(dev);
62afe595 1948 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1949 }
1950 if (status & StatsFull) { /* Empty statistics. */
1951 static int DoneDidThat;
1952 if (vortex_debug > 4)
1953 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1954 update_stats(ioaddr, dev);
1955 /* HACK: Disable statistics as an interrupt source. */
1956 /* This occurs when we have the wrong media type! */
1957 if (DoneDidThat == 0 &&
62afe595 1958 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1959 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1960 "stats as an interrupt source.\n", dev->name);
1961 EL3WINDOW(5);
62afe595 1962 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1963 vp->intr_enable &= ~StatsFull;
1964 EL3WINDOW(7);
1965 DoneDidThat++;
1966 }
1967 }
1968 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1969 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1970 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1971 }
1972 if (status & HostError) {
1973 u16 fifo_diag;
1974 EL3WINDOW(4);
62afe595 1975 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 1976 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1977 dev->name, fifo_diag);
1978 /* Adapter failure requires Tx/Rx reset and reinit. */
1979 if (vp->full_bus_master_tx) {
62afe595 1980 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 1981 /* 0x80000000 PCI master abort. */
1982 /* 0x40000000 PCI target abort. */
1983 if (vortex_debug)
1984 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1985
1986 /* In this case, blow the card away */
1987 /* Must not enter D3 or we can't legally issue the reset! */
1988 vortex_down(dev, 0);
1989 issue_and_wait(dev, TotalReset | 0xff);
1990 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1991 } else if (fifo_diag & 0x0400)
1992 do_tx_reset = 1;
1993 if (fifo_diag & 0x3000) {
1994 /* Reset Rx fifo and upload logic */
1995 issue_and_wait(dev, RxReset|0x07);
1996 /* Set the Rx filter to the current state. */
1997 set_rx_mode(dev);
1998 /* enable 802.1q VLAN tagged frames */
1999 set_8021q_mode(dev, 1);
62afe595
JL		 2000 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2001 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2002 }
2003 }
2004
2005 if (do_tx_reset) {
2006 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2007 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2008 if (!vp->full_bus_master_tx)
2009 netif_wake_queue(dev);
2010 }
2011}
2012
2013static int
2014vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2015{
2016 struct vortex_private *vp = netdev_priv(dev);
62afe595 2017 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2018
2019 /* Put out the doubleword header... */
62afe595 2020 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2021 if (vp->bus_master) {
2022 /* Set the bus-master controller to transfer the packet. */
2023 int len = (skb->len + 3) & ~3;
a880c4cd 2024 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2025 ioaddr + Wn7_MasterAddr);
62afe595 2026 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2027 vp->tx_skb = skb;
62afe595 2028 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2029 /* netif_wake_queue() will be called at the DMADone interrupt. */
2030 } else {
2031 /* ... and the packet rounded to a doubleword. */
62afe595 2032 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2033 dev_kfree_skb (skb);
62afe595 2034 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2035 netif_start_queue (dev); /* AKPM: redundant? */
2036 } else {
2037 /* Interrupt us when the FIFO has room for max-sized packet. */
2038 netif_stop_queue(dev);
62afe595 2039 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2040 }
2041 }
2042
2043 dev->trans_start = jiffies;
2044
2045 /* Clear the Tx status stack. */
2046 {
2047 int tx_status;
2048 int i = 32;
2049
62afe595 2050 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2051 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2052 if (vortex_debug > 2)
2053 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2054 dev->name, tx_status);
2055 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2056 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2057 if (tx_status & 0x30) {
2058 issue_and_wait(dev, TxReset);
2059 }
62afe595 2060 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2061 }
62afe595 2062 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2063 }
2064 }
2065 return 0;
2066}
2067
2068static int
2069boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2070{
2071 struct vortex_private *vp = netdev_priv(dev);
62afe595 2072 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2073 /* Calculate the next Tx descriptor entry. */
2074 int entry = vp->cur_tx % TX_RING_SIZE;
2075 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2076 unsigned long flags;
2077
2078 if (vortex_debug > 6) {
2079 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2080 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2081 dev->name, vp->cur_tx);
1da177e4
LT		 2082 }
2083
2084 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2085 if (vortex_debug > 0)
2086 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2087 dev->name);
2088 netif_stop_queue(dev);
2089 return 1;
2090 }
2091
2092 vp->tx_skbuff[entry] = skb;
2093
2094 vp->tx_ring[entry].next = 0;
2095#if DO_ZEROCOPY
84fa7933 2096 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2097 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2098 else
2099 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2100
2101 if (!skb_shinfo(skb)->nr_frags) {
2102 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2103 skb->len, PCI_DMA_TODEVICE));
2104 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2105 } else {
2106 int i;
2107
2108 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2109 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2110 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2111
2112 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2113 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2114
2115 vp->tx_ring[entry].frag[i+1].addr =
2116 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2117 (void*)page_address(frag->page) + frag->page_offset,
2118 frag->size, PCI_DMA_TODEVICE));
2119
2120 if (i == skb_shinfo(skb)->nr_frags-1)
2121 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2122 else
2123 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2124 }
2125 }
2126#else
2127 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2128 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2129 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2130#endif
2131
2132 spin_lock_irqsave(&vp->lock, flags);
2133 /* Wait for the stall to complete. */
2134 issue_and_wait(dev, DownStall);
2135 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2136 if (ioread32(ioaddr + DownListPtr) == 0) {
2137 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2138 vp->queued_packet++;
2139 }
2140
2141 vp->cur_tx++;
2142 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2143 netif_stop_queue (dev);
2144 } else { /* Clear previous interrupt enable. */
2145#if defined(tx_interrupt_mitigation)
2146 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2147 * were selected, this would corrupt DN_COMPLETE. No?
2148 */
2149 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2150#endif
2151 }
62afe595 2152 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2153 spin_unlock_irqrestore(&vp->lock, flags);
2154 dev->trans_start = jiffies;
2155 return 0;
2156}
2157
2158/* The interrupt handler does all of the Rx thread work and cleans up
2159 after the Tx thread. */
2160
2161/*
2162 * This is the ISR for the vortex series chips.
2163 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2164 */
2165
2166static irqreturn_t
7d12e780 2167vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2168{
2169 struct net_device *dev = dev_id;
2170 struct vortex_private *vp = netdev_priv(dev);
62afe595 2171 void __iomem *ioaddr;
1da177e4
LT		 2172 int status;
2173 int work_done = max_interrupt_work;
2174 int handled = 0;
2175
62afe595 2176 ioaddr = vp->ioaddr;
1da177e4
LT		 2177 spin_lock(&vp->lock);
2178
62afe595 2179 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2180
2181 if (vortex_debug > 6)
2182 printk("vortex_interrupt(). status=0x%4x\n", status);
2183
2184 if ((status & IntLatch) == 0)
2185 goto handler_exit; /* No interrupt: shared IRQs cause this */
2186 handled = 1;
2187
2188 if (status & IntReq) {
2189 status |= vp->deferred;
2190 vp->deferred = 0;
2191 }
2192
2193 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2194 goto handler_exit;
2195
2196 if (vortex_debug > 4)
2197 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2198 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2199
2200 do {
2201 if (vortex_debug > 5)
2202 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2203 dev->name, status);
2204 if (status & RxComplete)
2205 vortex_rx(dev);
2206
2207 if (status & TxAvailable) {
2208 if (vortex_debug > 5)
2209 printk(KERN_DEBUG " TX room bit was handled.\n");
2210 /* There's room in the FIFO for a full-sized packet. */
62afe595 2211 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2212 netif_wake_queue (dev);
2213 }
2214
2215 if (status & DMADone) {
62afe595
JL		 2216 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2217 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2218 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2219 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2220 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2221 /*
2222 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2223 * insufficient FIFO room, the TxAvailable test will succeed and call
2224 * netif_wake_queue()
2225 */
2226 netif_wake_queue(dev);
2227 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2228 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2229 netif_stop_queue(dev);
2230 }
2231 }
2232 }
2233 /* Check for all uncommon interrupts at once. */
2234 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2235 if (status == 0xffff)
2236 break;
2237 vortex_error(dev, status);
2238 }
2239
2240 if (--work_done < 0) {
2241 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2242 "%4.4x.\n", dev->name, status);
2243 /* Disable all pending interrupts. */
2244 do {
2245 vp->deferred |= status;
62afe595 2246 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2247 ioaddr + EL3_CMD);
62afe595
JL		 2248 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2249 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2250 /* The timer will reenable interrupts. */
2251 mod_timer(&vp->timer, jiffies + 1*HZ);
2252 break;
2253 }
2254 /* Acknowledge the IRQ. */
62afe595
JL		 2255 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2256 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2257
2258 if (vortex_debug > 4)
2259 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2260 dev->name, status);
2261handler_exit:
2262 spin_unlock(&vp->lock);
2263 return IRQ_RETVAL(handled);
2264}
2265
2266/*
2267 * This is the ISR for the boomerang series chips.
2268 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2269 */
2270
2271static irqreturn_t
7d12e780 2272boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2273{
2274 struct net_device *dev = dev_id;
2275 struct vortex_private *vp = netdev_priv(dev);
62afe595 2276 void __iomem *ioaddr;
1da177e4
LT		 2277 int status;
2278 int work_done = max_interrupt_work;
2279
62afe595 2280 ioaddr = vp->ioaddr;
1da177e4
LT		 2281
2282 /*
2283 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2284 * and boomerang_start_xmit
2285 */
2286 spin_lock(&vp->lock);
2287
62afe595 2288 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2289
2290 if (vortex_debug > 6)
2291 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2292
2293 if ((status & IntLatch) == 0)
2294 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2295
2296 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2297 if (vortex_debug > 1)
2298 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2299 goto handler_exit;
2300 }
2301
2302 if (status & IntReq) {
2303 status |= vp->deferred;
2304 vp->deferred = 0;
2305 }
2306
2307 if (vortex_debug > 4)
2308 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2309 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2310 do {
2311 if (vortex_debug > 5)
2312 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2313 dev->name, status);
2314 if (status & UpComplete) {
62afe595 2315 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2316 if (vortex_debug > 5)
2317 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2318 boomerang_rx(dev);
2319 }
2320
2321 if (status & DownComplete) {
2322 unsigned int dirty_tx = vp->dirty_tx;
2323
62afe595 2324 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2325 while (vp->cur_tx - dirty_tx > 0) {
2326 int entry = dirty_tx % TX_RING_SIZE;
2327#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2328 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2329 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2330 break; /* It still hasn't been processed. */
2331#else
2332 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2333 break; /* It still hasn't been processed. */
2334#endif
6aa20a22 2335
1da177e4
LT		 2336 if (vp->tx_skbuff[entry]) {
2337 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2338#if DO_ZEROCOPY
1da177e4
LT		 2339 int i;
2340 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2341 pci_unmap_single(VORTEX_PCI(vp),
2342 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2343 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2344 PCI_DMA_TODEVICE);
2345#else
2346 pci_unmap_single(VORTEX_PCI(vp),
2347 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2348#endif
2349 dev_kfree_skb_irq(skb);
2350 vp->tx_skbuff[entry] = NULL;
2351 } else {
2352 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2353 }
2354 /* vp->stats.tx_packets++; Counted below. */
2355 dirty_tx++;
2356 }
2357 vp->dirty_tx = dirty_tx;
2358 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2359 if (vortex_debug > 6)
2360 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2361 netif_wake_queue (dev);
2362 }
2363 }
2364
2365 /* Check for all uncommon interrupts at once. */
2366 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2367 vortex_error(dev, status);
2368
2369 if (--work_done < 0) {
2370 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2371 "%4.4x.\n", dev->name, status);
2372 /* Disable all pending interrupts. */
2373 do {
2374 vp->deferred |= status;
62afe595 2375 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2376 ioaddr + EL3_CMD);
62afe595
JL		 2377 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2378 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2379 /* The timer will reenable interrupts. */
2380 mod_timer(&vp->timer, jiffies + 1*HZ);
2381 break;
2382 }
2383 /* Acknowledge the IRQ. */
62afe595 2384 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2385 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2386 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2387
62afe595 2388 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2389
2390 if (vortex_debug > 4)
2391 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2392 dev->name, status);
2393handler_exit:
2394 spin_unlock(&vp->lock);
2395 return IRQ_HANDLED;
2396}
2397
2398static int vortex_rx(struct net_device *dev)
2399{
2400 struct vortex_private *vp = netdev_priv(dev);
62afe595 2401 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2402 int i;
2403 short rx_status;
2404
2405 if (vortex_debug > 5)
2406 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2407 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2408 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2409 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2410 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2411 if (vortex_debug > 2)
2412 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2413 vp->stats.rx_errors++;
2414 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2415 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2416 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2417 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2418 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2419 } else {
2420 /* The packet length: up to 4.5K!. */
2421 int pkt_len = rx_status & 0x1fff;
2422 struct sk_buff *skb;
2423
2424 skb = dev_alloc_skb(pkt_len + 5);
2425 if (vortex_debug > 4)
2426 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2427 pkt_len, rx_status);
2428 if (skb != NULL) {
1da177e4
LT		 2429 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2430 /* 'skb_put()' points to the start of sk_buff data area. */
2431 if (vp->bus_master &&
62afe595 2432 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2433 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2434 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2435 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2436 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2437 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2438 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2439 ;
2440 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2441 } else {
62afe595
JL		 2442 ioread32_rep(ioaddr + RX_FIFO,
2443 skb_put(skb, pkt_len),
2444 (pkt_len + 3) >> 2);
1da177e4 2445 }
62afe595 2446 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2447 skb->protocol = eth_type_trans(skb, dev);
2448 netif_rx(skb);
2449 dev->last_rx = jiffies;
2450 vp->stats.rx_packets++;
2451 /* Wait a limited time to go to next packet. */
2452 for (i = 200; i >= 0; i--)
62afe595 2453 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2454 break;
2455 continue;
2456 } else if (vortex_debug > 0)
2457 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2458 "size %d.\n", dev->name, pkt_len);
35b30674 2459 vp->stats.rx_dropped++;
1da177e4 2460 }
1da177e4
LT		 2461 issue_and_wait(dev, RxDiscard);
2462 }
2463
2464 return 0;
2465}
2466
2467static int
2468boomerang_rx(struct net_device *dev)
2469{
2470 struct vortex_private *vp = netdev_priv(dev);
2471 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2472 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2473 int rx_status;
2474 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2475
2476 if (vortex_debug > 5)
62afe595 2477 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2478
2479 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2480 if (--rx_work_limit < 0)
2481 break;
2482 if (rx_status & RxDError) { /* Error, update stats. */
2483 unsigned char rx_error = rx_status >> 16;
2484 if (vortex_debug > 2)
2485 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2486 vp->stats.rx_errors++;
2487 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2488 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2489 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2490 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2491 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2492 } else {
2493 /* The packet length: up to 4.5K!. */
2494 int pkt_len = rx_status & 0x1fff;
2495 struct sk_buff *skb;
2496 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2497
2498 if (vortex_debug > 4)
2499 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2500 pkt_len, rx_status);
2501
2502 /* Check if the packet is long enough to just accept without
2503 copying to a properly sized skbuff. */
2504 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
1da177e4
LT		 2505 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2506 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2507 /* 'skb_put()' points to the start of sk_buff data area. */
2508 memcpy(skb_put(skb, pkt_len),
689be439 2509 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2510 pkt_len);
2511 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2512 vp->rx_copy++;
2513 } else {
2514 /* Pass up the skbuff already on the Rx ring. */
2515 skb = vp->rx_skbuff[entry];
2516 vp->rx_skbuff[entry] = NULL;
2517 skb_put(skb, pkt_len);
2518 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2519 vp->rx_nocopy++;
2520 }
2521 skb->protocol = eth_type_trans(skb, dev);
2522 { /* Use hardware checksum info. */
2523 int csum_bits = rx_status & 0xee000000;
2524 if (csum_bits &&
2525 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2526 csum_bits == (IPChksumValid | UDPChksumValid))) {
2527 skb->ip_summed = CHECKSUM_UNNECESSARY;
2528 vp->rx_csumhits++;
2529 }
2530 }
2531 netif_rx(skb);
2532 dev->last_rx = jiffies;
2533 vp->stats.rx_packets++;
2534 }
2535 entry = (++vp->cur_rx) % RX_RING_SIZE;
2536 }
2537 /* Refill the Rx ring buffers. */
2538 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2539 struct sk_buff *skb;
2540 entry = vp->dirty_rx % RX_RING_SIZE;
2541 if (vp->rx_skbuff[entry] == NULL) {
2542 skb = dev_alloc_skb(PKT_BUF_SZ);
2543 if (skb == NULL) {
2544 static unsigned long last_jif;
ff5688ae 2545 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2546 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2547 last_jif = jiffies;
2548 }
2549 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2550 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2551 break; /* Bad news! */
2552 }
2553 skb->dev = dev; /* Mark as being used by this device. */
2554 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2555 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2556 vp->rx_skbuff[entry] = skb;
2557 }
2558 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2559 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2560 }
2561 return 0;
2562}
2563
2564/*
2565 * If we've hit a total OOM refilling the Rx ring we poll once a second
2566 * for some memory. Otherwise there is no way to restart the rx process.
2567 */
2568static void
2569rx_oom_timer(unsigned long arg)
2570{
2571 struct net_device *dev = (struct net_device *)arg;
2572 struct vortex_private *vp = netdev_priv(dev);
2573
2574 spin_lock_irq(&vp->lock);
2575 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2576 boomerang_rx(dev);
2577 if (vortex_debug > 1) {
2578 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2579 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2580 }
2581 spin_unlock_irq(&vp->lock);
2582}
2583
2584static void
2585vortex_down(struct net_device *dev, int final_down)
2586{
2587 struct vortex_private *vp = netdev_priv(dev);
62afe595 2588 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2589
2590 netif_stop_queue (dev);
2591
2592 del_timer_sync(&vp->rx_oom_timer);
2593 del_timer_sync(&vp->timer);
2594
2595 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2596 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2597
2598 /* Disable the receiver and transmitter. */
62afe595
JL		 2599 iowrite16(RxDisable, ioaddr + EL3_CMD);
2600 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2601
2602 /* Disable receiving 802.1q tagged frames */
2603 set_8021q_mode(dev, 0);
2604
2605 if (dev->if_port == XCVR_10base2)
2606 /* Turn off thinnet power. Green! */
62afe595 2607 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2608
62afe595 2609 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2610
2611 update_stats(ioaddr, dev);
2612 if (vp->full_bus_master_rx)
62afe595 2613 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2614 if (vp->full_bus_master_tx)
62afe595 2615 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2616
2617 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2618 vp->pm_state_valid = 1;
1da177e4
LT		 2619 pci_save_state(VORTEX_PCI(vp));
2620 acpi_set_WOL(dev);
2621 }
2622}
2623
2624static int
2625vortex_close(struct net_device *dev)
2626{
2627 struct vortex_private *vp = netdev_priv(dev);
62afe595 2628 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2629 int i;
2630
2631 if (netif_device_present(dev))
2632 vortex_down(dev, 1);
2633
2634 if (vortex_debug > 1) {
2635 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2636 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2637 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2638 " tx_queued %d Rx pre-checksummed %d.\n",
2639 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2640 }
2641
2642#if DO_ZEROCOPY
32fb5f06
JL		 2643 if (vp->rx_csumhits &&
2644 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2645 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2646 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2647 "not using them!\n", dev->name);
1da177e4
LT		 2648 }
2649#endif
6aa20a22 2650
1da177e4
LT		 2651 free_irq(dev->irq, dev);
2652
2653 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2654 for (i = 0; i < RX_RING_SIZE; i++)
2655 if (vp->rx_skbuff[i]) {
2656 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2657 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2658 dev_kfree_skb(vp->rx_skbuff[i]);
2659 vp->rx_skbuff[i] = NULL;
2660 }
2661 }
2662 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2663 for (i = 0; i < TX_RING_SIZE; i++) {
2664 if (vp->tx_skbuff[i]) {
2665 struct sk_buff *skb = vp->tx_skbuff[i];
2666#if DO_ZEROCOPY
2667 int k;
2668
2669 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2670 pci_unmap_single(VORTEX_PCI(vp),
2671 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2672 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2673 PCI_DMA_TODEVICE);
2674#else
2675 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2676#endif
2677 dev_kfree_skb(skb);
2678 vp->tx_skbuff[i] = NULL;
2679 }
2680 }
2681 }
2682
2683 return 0;
2684}
2685
2686static void
2687dump_tx_ring(struct net_device *dev)
2688{
2689 if (vortex_debug > 0) {
2690 struct vortex_private *vp = netdev_priv(dev);
62afe595 2691 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2692
1da177e4
LT		 2693 if (vp->full_bus_master_tx) {
2694 int i;
62afe595 2695 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2696
2697 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2698 vp->full_bus_master_tx,
2699 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2700 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2701 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2702 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2703 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2704 issue_and_wait(dev, DownStall);
2705 for (i = 0; i < TX_RING_SIZE; i++) {
2706 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2707 &vp->tx_ring[i],
2708#if DO_ZEROCOPY
2709 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2710#else
2711 le32_to_cpu(vp->tx_ring[i].length),
2712#endif
2713 le32_to_cpu(vp->tx_ring[i].status));
2714 }
2715 if (!stalled)
62afe595 2716 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2717 }
2718 }
2719}
2720
2721static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2722{
2723 struct vortex_private *vp = netdev_priv(dev);
62afe595 2724 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2725 unsigned long flags;
2726
2727 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2728 spin_lock_irqsave (&vp->lock, flags);
62afe595 2729 update_stats(ioaddr, dev);
1da177e4
LT		 2730 spin_unlock_irqrestore (&vp->lock, flags);
2731 }
2732 return &vp->stats;
2733}
2734
2735/* Update statistics.
2736 Unlike with the EL3 we need not worry about interrupts changing
2737 the window setting from underneath us, but we must still guard
2738 against a race condition with a StatsUpdate interrupt updating the
2739 table. This is done by checking that the ASM (!) code generated uses
2740 atomic updates with '+='.
2741 */
62afe595 2742static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2743{
2744 struct vortex_private *vp = netdev_priv(dev);
62afe595 2745 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2746
2747 if (old_window == 0xffff) /* Chip suspended or ejected. */
2748 return;
2749 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2750 /* Switch to the stats window, and read everything. */
2751 EL3WINDOW(6);
62afe595
JL		 2752 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2753 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2754 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2755 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2756 vp->stats.tx_packets += ioread8(ioaddr + 6);
2757 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2758 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2759 /* Don't bother with register 9, an extension of registers 6&7.
2760 If we do use the 6&7 values the atomic update assumption above
2761 is invalid. */
62afe595
JL		 2762 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2763 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2764 /* Extra stats for get_ethtool_stats() */
62afe595 2765 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2766 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2767 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2768 EL3WINDOW(4);
62afe595 2769 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2770
8d1d0340
SK		 2771 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2772 + vp->xstats.tx_single_collisions
2773 + vp->xstats.tx_max_collisions;
2774
1da177e4 2775 {
62afe595 2776 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2777 vp->stats.rx_bytes += (up & 0x0f) << 16;
2778 vp->stats.tx_bytes += (up & 0xf0) << 12;
2779 }
2780
2781 EL3WINDOW(old_window >> 13);
2782 return;
2783}
2784
2785static int vortex_nway_reset(struct net_device *dev)
2786{
2787 struct vortex_private *vp = netdev_priv(dev);
62afe595 2788 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2789 unsigned long flags;
2790 int rc;
2791
2792 spin_lock_irqsave(&vp->lock, flags);
2793 EL3WINDOW(4);
2794 rc = mii_nway_restart(&vp->mii);
2795 spin_unlock_irqrestore(&vp->lock, flags);
2796 return rc;
2797}
2798
1da177e4
LT		 2799static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2800{
2801 struct vortex_private *vp = netdev_priv(dev);
62afe595 2802 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2803 unsigned long flags;
2804 int rc;
2805
2806 spin_lock_irqsave(&vp->lock, flags);
2807 EL3WINDOW(4);
2808 rc = mii_ethtool_gset(&vp->mii, cmd);
2809 spin_unlock_irqrestore(&vp->lock, flags);
2810 return rc;
2811}
2812
2813static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2814{
2815 struct vortex_private *vp = netdev_priv(dev);
62afe595 2816 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2817 unsigned long flags;
2818 int rc;
2819
2820 spin_lock_irqsave(&vp->lock, flags);
2821 EL3WINDOW(4);
2822 rc = mii_ethtool_sset(&vp->mii, cmd);
2823 spin_unlock_irqrestore(&vp->lock, flags);
2824 return rc;
2825}
2826
2827static u32 vortex_get_msglevel(struct net_device *dev)
2828{
2829 return vortex_debug;
2830}
2831
2832static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2833{
2834 vortex_debug = dbg;
2835}
2836
2837static int vortex_get_stats_count(struct net_device *dev)
2838{
2839 return VORTEX_NUM_STATS;
2840}
2841
2842static void vortex_get_ethtool_stats(struct net_device *dev,
2843 struct ethtool_stats *stats, u64 *data)
2844{
2845 struct vortex_private *vp = netdev_priv(dev);
62afe595 2846 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2847 unsigned long flags;
2848
2849 spin_lock_irqsave(&vp->lock, flags);
62afe595 2850 update_stats(ioaddr, dev);
1da177e4
LT		 2851 spin_unlock_irqrestore(&vp->lock, flags);
2852
2853 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2854 data[1] = vp->xstats.tx_max_collisions;
2855 data[2] = vp->xstats.tx_multiple_collisions;
2856 data[3] = vp->xstats.tx_single_collisions;
2857 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2858}
2859
2860
2861static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2862{
2863 switch (stringset) {
2864 case ETH_SS_STATS:
2865 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2866 break;
2867 default:
2868 WARN_ON(1);
2869 break;
2870 }
2871}
2872
2873static void vortex_get_drvinfo(struct net_device *dev,
2874 struct ethtool_drvinfo *info)
2875{
2876 struct vortex_private *vp = netdev_priv(dev);
2877
2878 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2879 if (VORTEX_PCI(vp)) {
2880 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2881 } else {
2882 if (VORTEX_EISA(vp))
2883 sprintf(info->bus_info, vp->gendev->bus_id);
2884 else
2885 sprintf(info->bus_info, "EISA 0x%lx %d",
2886 dev->base_addr, dev->irq);
2887 }
2888}
2889
7282d491 2890static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2891 .get_drvinfo = vortex_get_drvinfo,
2892 .get_strings = vortex_get_strings,
2893 .get_msglevel = vortex_get_msglevel,
2894 .set_msglevel = vortex_set_msglevel,
2895 .get_ethtool_stats = vortex_get_ethtool_stats,
2896 .get_stats_count = vortex_get_stats_count,
2897 .get_settings = vortex_get_settings,
2898 .set_settings = vortex_set_settings,
373a6887 2899 .get_link = ethtool_op_get_link,
1da177e4
LT		 2900 .nway_reset = vortex_nway_reset,
2901};
2902
2903#ifdef CONFIG_PCI
2904/*
2905 * Must power the device up to do MDIO operations
2906 */
2907static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2908{
2909 int err;
2910 struct vortex_private *vp = netdev_priv(dev);
62afe595 2911 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2912 unsigned long flags;
2913 int state = 0;
2914
2915 if(VORTEX_PCI(vp))
2916 state = VORTEX_PCI(vp)->current_state;
2917
2918 /* The kernel core really should have pci_get_power_state() */
2919
2920 if(state != 0)
2921 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2922 spin_lock_irqsave(&vp->lock, flags);
2923 EL3WINDOW(4);
2924 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2925 spin_unlock_irqrestore(&vp->lock, flags);
2926 if(state != 0)
2927 pci_set_power_state(VORTEX_PCI(vp), state);
2928
2929 return err;
2930}
2931#endif
2932
2933
2934/* Pre-Cyclone chips have no documented multicast filter, so the only
2935 multicast setting is to receive all multicast frames. At least
2936 the chip has a very clean way to set the mode, unlike many others. */
2937static void set_rx_mode(struct net_device *dev)
2938{
62afe595
JL		 2939 struct vortex_private *vp = netdev_priv(dev);
2940 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2941 int new_mode;
2942
2943 if (dev->flags & IFF_PROMISC) {
d5b20697 2944 if (vortex_debug > 3)
1da177e4
LT		 2945 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2946 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2947 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2948 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2949 } else
2950 new_mode = SetRxFilter | RxStation | RxBroadcast;
2951
62afe595 2952 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2953}
2954
2955#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2956/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2957 Note that this must be done after each RxReset due to some backwards
2958 compatibility logic in the Cyclone and Tornado ASICs */
2959
2960/* The Ethernet Type used for 802.1q tagged frames */
2961#define VLAN_ETHER_TYPE 0x8100
2962
2963static void set_8021q_mode(struct net_device *dev, int enable)
2964{
2965 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2966 void __iomem *ioaddr = vp->ioaddr;
2967 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2968 int mac_ctrl;
2969
2970 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2971 /* cyclone and tornado chipsets can recognize 802.1q
2972 * tagged frames and treat them correctly */
2973
2974 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2975 if (enable)
2976 max_pkt_size += 4; /* 802.1Q VLAN tag */
2977
2978 EL3WINDOW(3);
62afe595 2979 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 2980
2981 /* set VlanEtherType to let the hardware checksumming
2982 treat tagged frames correctly */
2983 EL3WINDOW(7);
62afe595 2984 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 2985 } else {
2986 /* on older cards we have to enable large frames */
2987
2988 vp->large_frames = dev->mtu > 1500 || enable;
2989
2990 EL3WINDOW(3);
62afe595 2991 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2992 if (vp->large_frames)
2993 mac_ctrl |= 0x40;
2994 else
2995 mac_ctrl &= ~0x40;
62afe595 2996 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2997 }
2998
2999 EL3WINDOW(old_window);
3000}
3001#else
3002
3003static void set_8021q_mode(struct net_device *dev, int enable)
3004{
3005}
3006
3007
3008#endif
3009
3010/* MII transceiver control section.
3011 Read and write the MII registers using software-generated serial
3012 MDIO protocol. See the MII specifications or DP83840A data sheet
3013 for details. */
3014
3015/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3016 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3017 "overclocking" issues. */
62afe595 3018#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3019
3020#define MDIO_SHIFT_CLK 0x01
3021#define MDIO_DIR_WRITE 0x04
3022#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3023#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3024#define MDIO_DATA_READ 0x02
3025#define MDIO_ENB_IN 0x00
3026
3027/* Generate the preamble required for initial synchronization and
3028 a few older transceivers. */
62afe595 3029static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3030{
62afe595 3031 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3032
3033 /* Establish sync by sending at least 32 logic ones. */
3034 while (-- bits >= 0) {
62afe595 3035 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3036 mdio_delay();
62afe595 3037 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3038 mdio_delay();
3039 }
3040}
3041
3042static int mdio_read(struct net_device *dev, int phy_id, int location)
3043{
3044 int i;
62afe595
JL		 3045 struct vortex_private *vp = netdev_priv(dev);
3046 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3047 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3048 unsigned int retval = 0;
62afe595 3049 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3050
3051 if (mii_preamble_required)
3052 mdio_sync(ioaddr, 32);
3053
3054 /* Shift the read command bits out. */
3055 for (i = 14; i >= 0; i--) {
3056 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3057 iowrite16(dataval, mdio_addr);
1da177e4 3058 mdio_delay();
62afe595 3059 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3060 mdio_delay();
3061 }
3062 /* Read the two transition, 16 data, and wire-idle bits. */
3063 for (i = 19; i > 0; i--) {
62afe595 3064 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3065 mdio_delay();
62afe595
JL		 3066 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3067 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3068 mdio_delay();
3069 }
3070 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3071}
3072
3073static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3074{
62afe595
JL		 3075 struct vortex_private *vp = netdev_priv(dev);
3076 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3077 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3078 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3079 int i;
3080
3081 if (mii_preamble_required)
3082 mdio_sync(ioaddr, 32);
3083
3084 /* Shift the command bits out. */
3085 for (i = 31; i >= 0; i--) {
3086 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3087 iowrite16(dataval, mdio_addr);
1da177e4 3088 mdio_delay();
62afe595 3089 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3090 mdio_delay();
3091 }
3092 /* Leave the interface idle. */
3093 for (i = 1; i >= 0; i--) {
62afe595 3094 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3095 mdio_delay();
62afe595 3096 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3097 mdio_delay();
3098 }
3099 return;
3100}
a880c4cd 3101
1da177e4
LT		 3102/* ACPI: Advanced Configuration and Power Interface. */
3103/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3104static void acpi_set_WOL(struct net_device *dev)
3105{
3106 struct vortex_private *vp = netdev_priv(dev);
62afe595 3107 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3108
3109 if (vp->enable_wol) {
3110 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3111 EL3WINDOW(7);
62afe595 3112 iowrite16(2, ioaddr + 0x0c);
1da177e4 3113 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3114 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3115 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3116
3117 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3118
3119 /* Change the power state to D3; RxEnable doesn't take effect. */
3120 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3121 }
1da177e4
LT		 3122}
3123
3124
a880c4cd 3125static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3126{
3127 struct net_device *dev = pci_get_drvdata(pdev);
3128 struct vortex_private *vp;
3129
3130 if (!dev) {
3131 printk("vortex_remove_one called for Compaq device!\n");
3132 BUG();
3133 }
3134
3135 vp = netdev_priv(dev);
3136
62afe595
JL		 3137 if (vp->cb_fn_base)
3138 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3139
1da177e4
LT		 3140 unregister_netdev(dev);
3141
3142 if (VORTEX_PCI(vp)) {
3143 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3144 if (vp->pm_state_valid)
3145 pci_restore_state(VORTEX_PCI(vp));
3146 pci_disable_device(VORTEX_PCI(vp));
3147 }
3148 /* Should really use issue_and_wait() here */
62afe595
JL		 3149 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3150 vp->ioaddr + EL3_CMD);
3151
3152 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3153
3154 pci_free_consistent(pdev,
3155 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3156 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3157 vp->rx_ring,
3158 vp->rx_ring_dma);
3159 if (vp->must_free_region)
3160 release_region(dev->base_addr, vp->io_size);
3161 free_netdev(dev);
3162}
3163
3164
3165static struct pci_driver vortex_driver = {
3166 .name = "3c59x",
3167 .probe = vortex_init_one,
3168 .remove = __devexit_p(vortex_remove_one),
3169 .id_table = vortex_pci_tbl,
3170#ifdef CONFIG_PM
3171 .suspend = vortex_suspend,
3172 .resume = vortex_resume,
3173#endif
3174};
3175
3176
3177static int vortex_have_pci;
3178static int vortex_have_eisa;
3179
3180
a880c4cd 3181static int __init vortex_init(void)
1da177e4
LT		 3182{
3183 int pci_rc, eisa_rc;
3184
29917620 3185 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3186 eisa_rc = vortex_eisa_init();
3187
3188 if (pci_rc == 0)
3189 vortex_have_pci = 1;
3190 if (eisa_rc > 0)
3191 vortex_have_eisa = 1;
3192
3193 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3194}
3195
3196
a880c4cd 3197static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3198{
3199 struct vortex_private *vp;
62afe595 3200 void __iomem *ioaddr;
1da177e4
LT		 3201
3202#ifdef CONFIG_EISA
3203 /* Take care of the EISA devices */
a880c4cd 3204 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3205#endif
6aa20a22 3206
1da177e4
LT		 3207 if (compaq_net_device) {
3208 vp = compaq_net_device->priv;
62afe595
JL		 3209 ioaddr = ioport_map(compaq_net_device->base_addr,
3210 VORTEX_TOTAL_SIZE);
1da177e4 3211
a880c4cd
SK		 3212 unregister_netdev(compaq_net_device);
3213 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3214 release_region(compaq_net_device->base_addr,
3215 VORTEX_TOTAL_SIZE);
1da177e4 3216
a880c4cd 3217 free_netdev(compaq_net_device);
1da177e4
LT		 3218 }
3219}
3220
3221
a880c4cd 3222static void __exit vortex_cleanup(void)
1da177e4
LT		 3223{
3224 if (vortex_have_pci)
a880c4cd 3225 pci_unregister_driver(&vortex_driver);
1da177e4 3226 if (vortex_have_eisa)
a880c4cd 3227 vortex_eisa_cleanup();
1da177e4
LT		 3228}
3229
3230
3231module_init(vortex_init);
3232module_exit(vortex_cleanup);
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