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Merge branch 'for-2.6.26' of git://git.farnsworth.org/dale/linux-2.6-mv643xx_eth...
[net-next-2.6.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
1da177e4
LT		 93#include <asm/irq.h> /* For NR_IRQS only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
2c2a8c53 106DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
1f1bd5fc 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
b8a1fcee 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
cc2d6596
AV		 541 __le32 next; /* Last entry points to 0. */
542 __le32 status;
543 __le32 addr; /* Up to 63 addr/len pairs possible. */
544 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
cc2d6596
AV		 561 __le32 next; /* Last entry points to 0. */
562 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 563#if DO_ZEROCOPY
564 struct {
cc2d6596
AV		 565 __le32 addr;
566 __le32 length;
1da177e4
LT		 567 } frag[1+MAX_SKB_FRAGS];
568#else
cc2d6596
AV		 569 __le32 addr;
570 __le32 length;
1da177e4
LT		 571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
62afe595
JL		 610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 623 full_duplex:1, autoselect:1,
1da177e4
LT		 624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647};
648
649#ifdef CONFIG_PCI
650#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651#else
652#define DEVICE_PCI(dev) NULL
653#endif
654
655#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657#ifdef CONFIG_EISA
658#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659#else
660#define DEVICE_EISA(dev) NULL
661#endif
662
663#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665/* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671};
672
f71e1309 673static const struct media_table {
1da177e4
LT		 674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679} media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691};
692
693static struct {
694 const char str[ETH_GSTRING_LEN];
695} ethtool_stats_keys[] = {
696 { "tx_deferred" },
8d1d0340 697 { "tx_max_collisions" },
1da177e4 698 { "tx_multiple_collisions" },
8d1d0340 699 { "tx_single_collisions" },
1da177e4
LT		 700 { "rx_bad_ssd" },
701};
702
703/* number of ETHTOOL_GSTATS u64's */
8d1d0340 704#define VORTEX_NUM_STATS 5
1da177e4 705
62afe595 706static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 707 int chip_idx, int card_idx);
c8303d10 708static int vortex_up(struct net_device *dev);
1da177e4
LT		 709static void vortex_down(struct net_device *dev, int final);
710static int vortex_open(struct net_device *dev);
62afe595 711static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 712static int mdio_read(struct net_device *dev, int phy_id, int location);
713static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714static void vortex_timer(unsigned long arg);
715static void rx_oom_timer(unsigned long arg);
716static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718static int vortex_rx(struct net_device *dev);
719static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 720static irqreturn_t vortex_interrupt(int irq, void *dev_id);
721static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 722static int vortex_close(struct net_device *dev);
723static void dump_tx_ring(struct net_device *dev);
62afe595 724static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 725static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726static void set_rx_mode(struct net_device *dev);
727#ifdef CONFIG_PCI
728static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729#endif
730static void vortex_tx_timeout(struct net_device *dev);
731static void acpi_set_WOL(struct net_device *dev);
7282d491 732static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 733static void set_8021q_mode(struct net_device *dev, int enable);
734
1da177e4
LT		 735/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736/* Option count limit only -- unlimited interfaces are supported. */
737#define MAX_UNITS 8
9954ab7f
JL		 738static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 743static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 744static int global_options = -1;
745static int global_full_duplex = -1;
746static int global_enable_wol = -1;
900fd17d 747static int global_use_mmio = -1;
1da177e4 748
1da177e4
LT		 749/* Variables to work-around the Compaq PCI BIOS32 problem. */
750static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751static struct net_device *compaq_net_device;
752
753static int vortex_cards_found;
754
755module_param(debug, int, 0);
756module_param(global_options, int, 0);
757module_param_array(options, int, NULL, 0);
758module_param(global_full_duplex, int, 0);
759module_param_array(full_duplex, int, NULL, 0);
760module_param_array(hw_checksums, int, NULL, 0);
761module_param_array(flow_ctrl, int, NULL, 0);
762module_param(global_enable_wol, int, 0);
763module_param_array(enable_wol, int, NULL, 0);
764module_param(rx_copybreak, int, 0);
765module_param(max_interrupt_work, int, 0);
766module_param(compaq_ioaddr, int, 0);
767module_param(compaq_irq, int, 0);
768module_param(compaq_device_id, int, 0);
769module_param(watchdog, int, 0);
900fd17d
JL		 770module_param(global_use_mmio, int, 0);
771module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 772MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 776MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 777MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 780MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 781MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 787MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 789
790#ifdef CONFIG_NET_POLL_CONTROLLER
791static void poll_vortex(struct net_device *dev)
792{
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
0d38ff1d 795 local_irq_save(flags);
7d12e780 796 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 797 local_irq_restore(flags);
6aa20a22 798}
1da177e4
LT		 799#endif
800
801#ifdef CONFIG_PM
802
a880c4cd 803static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 804{
805 struct net_device *dev = pci_get_drvdata(pdev);
806
807 if (dev && dev->priv) {
808 if (netif_running(dev)) {
809 netif_device_detach(dev);
810 vortex_down(dev, 1);
811 }
5b039e68
RW		 812 pci_save_state(pdev);
813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
814 free_irq(dev->irq, dev);
815 pci_disable_device(pdev);
816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 817 }
818 return 0;
819}
820
a880c4cd 821static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 822{
823 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 824 struct vortex_private *vp = netdev_priv(dev);
e1265153 825 int err;
1da177e4 826
5b039e68
RW		 827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
e1265153
DM		 830 err = pci_enable_device(pdev);
831 if (err) {
832 printk(KERN_WARNING "%s: Could not enable device \n",
833 dev->name);
834 return err;
835 }
5b039e68
RW		 836 pci_set_master(pdev);
837 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 838 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 839 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
840 pci_disable_device(pdev);
841 return -EBUSY;
842 }
1da177e4 843 if (netif_running(dev)) {
c8303d10
MH		 844 err = vortex_up(dev);
845 if (err)
846 return err;
847 else
848 netif_device_attach(dev);
1da177e4
LT		 849 }
850 }
851 return 0;
852}
853
854#endif /* CONFIG_PM */
855
856#ifdef CONFIG_EISA
857static struct eisa_device_id vortex_eisa_ids[] = {
858 { "TCM5920", CH_3C592 },
859 { "TCM5970", CH_3C597 },
860 { "" }
861};
07563c71 862MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 863
95c408a9 864static int __init vortex_eisa_probe(struct device *device)
1da177e4 865{
62afe595 866 void __iomem *ioaddr;
1da177e4
LT		 867 struct eisa_device *edev;
868
a880c4cd 869 edev = to_eisa_device(device);
1da177e4 870
62afe595 871 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 872 return -EBUSY;
873
62afe595
JL		 874 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
875
876 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 877 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 878 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 879 return -ENODEV;
880 }
881
882 vortex_cards_found++;
883
884 return 0;
885}
886
95c408a9 887static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 888{
889 struct eisa_device *edev;
890 struct net_device *dev;
891 struct vortex_private *vp;
62afe595 892 void __iomem *ioaddr;
1da177e4 893
a880c4cd
SK		 894 edev = to_eisa_device(device);
895 dev = eisa_get_drvdata(edev);
1da177e4
LT		 896
897 if (!dev) {
898 printk("vortex_eisa_remove called for Compaq device!\n");
899 BUG();
900 }
901
902 vp = netdev_priv(dev);
62afe595 903 ioaddr = vp->ioaddr;
6aa20a22 904
a880c4cd
SK		 905 unregister_netdev(dev);
906 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
907 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 908
a880c4cd 909 free_netdev(dev);
1da177e4
LT		 910 return 0;
911}
95c408a9
RB		 912
913static struct eisa_driver vortex_eisa_driver = {
914 .id_table = vortex_eisa_ids,
915 .driver = {
916 .name = "3c59x",
917 .probe = vortex_eisa_probe,
918 .remove = __devexit_p(vortex_eisa_remove)
919 }
920};
921
922#endif /* CONFIG_EISA */
1da177e4
LT		 923
924/* returns count found (>= 0), or negative on error */
a880c4cd 925static int __init vortex_eisa_init(void)
1da177e4
LT		 926{
927 int eisa_found = 0;
928 int orig_cards_found = vortex_cards_found;
929
930#ifdef CONFIG_EISA
c2f6fabb
BH		 931 int err;
932
933 err = eisa_driver_register (&vortex_eisa_driver);
934 if (!err) {
935 /*
936 * Because of the way EISA bus is probed, we cannot assume
937 * any device have been found when we exit from
938 * eisa_driver_register (the bus root driver may not be
939 * initialized yet). So we blindly assume something was
940 * found, and let the sysfs magic happend...
941 */
942 eisa_found = 1;
1da177e4
LT		 943 }
944#endif
6aa20a22 945
1da177e4
LT		 946 /* Special code to work-around the Compaq PCI BIOS32 problem. */
947 if (compaq_ioaddr) {
62afe595
JL		 948 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
949 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 950 }
951
952 return vortex_cards_found - orig_cards_found + eisa_found;
953}
954
955/* returns count (>= 0), or negative on error */
a880c4cd 956static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 957 const struct pci_device_id *ent)
958{
900fd17d
JL		 959 int rc, unit, pci_bar;
960 struct vortex_chip_info *vci;
961 void __iomem *ioaddr;
1da177e4 962
6aa20a22 963 /* wake up and enable device */
a880c4cd 964 rc = pci_enable_device(pdev);
1da177e4
LT		 965 if (rc < 0)
966 goto out;
967
900fd17d
JL		 968 unit = vortex_cards_found;
969
970 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
971 /* Determine the default if the user didn't override us */
972 vci = &vortex_info_tbl[ent->driver_data];
973 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
974 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
975 pci_bar = use_mmio[unit] ? 1 : 0;
976 else
977 pci_bar = global_use_mmio ? 1 : 0;
978
979 ioaddr = pci_iomap(pdev, pci_bar, 0);
980 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
981 ioaddr = pci_iomap(pdev, 0, 0);
982
983 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
984 ent->driver_data, unit);
1da177e4 985 if (rc < 0) {
a880c4cd 986 pci_disable_device(pdev);
1da177e4
LT		 987 goto out;
988 }
989
990 vortex_cards_found++;
991
992out:
993 return rc;
994}
995
996/*
997 * Start up the PCI/EISA device which is described by *gendev.
998 * Return 0 on success.
999 *
1000 * NOTE: pdev can be NULL, for the case of a Compaq device
1001 */
1002static int __devinit vortex_probe1(struct device *gendev,
62afe595 1003 void __iomem *ioaddr, int irq,
1da177e4
LT		 1004 int chip_idx, int card_idx)
1005{
1006 struct vortex_private *vp;
1007 int option;
1008 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1009 int i, step;
1010 struct net_device *dev;
1011 static int printed_version;
1012 int retval, print_info;
1013 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1014 char *print_name = "3c59x";
1015 struct pci_dev *pdev = NULL;
1016 struct eisa_device *edev = NULL;
0795af57 1017 DECLARE_MAC_BUF(mac);
1da177e4
LT		 1018
1019 if (!printed_version) {
1020 printk (version);
1021 printed_version = 1;
1022 }
1023
1024 if (gendev) {
1025 if ((pdev = DEVICE_PCI(gendev))) {
1026 print_name = pci_name(pdev);
1027 }
1028
1029 if ((edev = DEVICE_EISA(gendev))) {
1030 print_name = edev->dev.bus_id;
1031 }
1032 }
1033
1034 dev = alloc_etherdev(sizeof(*vp));
1035 retval = -ENOMEM;
1036 if (!dev) {
1037 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1038 goto out;
1039 }
1da177e4
LT		 1040 SET_NETDEV_DEV(dev, gendev);
1041 vp = netdev_priv(dev);
1042
1043 option = global_options;
1044
1045 /* The lower four bits are the media type. */
1046 if (dev->mem_start) {
1047 /*
1048 * The 'options' param is passed in as the third arg to the
1049 * LILO 'ether=' argument for non-modular use
1050 */
1051 option = dev->mem_start;
1052 }
1053 else if (card_idx < MAX_UNITS) {
1054 if (options[card_idx] >= 0)
1055 option = options[card_idx];
1056 }
1057
1058 if (option > 0) {
1059 if (option & 0x8000)
1060 vortex_debug = 7;
1061 if (option & 0x4000)
1062 vortex_debug = 2;
1063 if (option & 0x0400)
1064 vp->enable_wol = 1;
1065 }
1066
1067 print_info = (vortex_debug > 1);
1068 if (print_info)
1069 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1070
61238602 1071 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1072 print_name,
1073 pdev ? "PCI" : "EISA",
1074 vci->name,
1075 ioaddr);
1076
62afe595 1077 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1078 dev->irq = irq;
1079 dev->mtu = mtu;
62afe595 1080 vp->ioaddr = ioaddr;
1da177e4
LT		 1081 vp->large_frames = mtu > 1500;
1082 vp->drv_flags = vci->drv_flags;
1083 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1084 vp->io_size = vci->io_size;
1085 vp->card_idx = card_idx;
1086
1087 /* module list only for Compaq device */
1088 if (gendev == NULL) {
1089 compaq_net_device = dev;
1090 }
1091
1092 /* PCI-only startup logic */
1093 if (pdev) {
1094 /* EISA resources already marked, so only PCI needs to do this here */
1095 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1096 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1097 vp->must_free_region = 1;
1098
6aa20a22 1099 /* enable bus-mastering if necessary */
1da177e4 1100 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1101 pci_set_master(pdev);
1da177e4
LT		 1102
1103 if (vci->drv_flags & IS_VORTEX) {
1104 u8 pci_latency;
1105 u8 new_latency = 248;
1106
1107 /* Check the PCI latency value. On the 3c590 series the latency timer
1108 must be set to the maximum value to avoid data corruption that occurs
1109 when the timer expires during a transfer. This bug exists the Vortex
1110 chip only. */
1111 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1112 if (pci_latency < new_latency) {
1113 printk(KERN_INFO "%s: Overriding PCI latency"
1114 " timer (CFLT) setting of %d, new value is %d.\n",
1115 print_name, pci_latency, new_latency);
1116 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1117 }
1118 }
1119 }
1120
1121 spin_lock_init(&vp->lock);
1122 vp->gendev = gendev;
1123 vp->mii.dev = dev;
1124 vp->mii.mdio_read = mdio_read;
1125 vp->mii.mdio_write = mdio_write;
1126 vp->mii.phy_id_mask = 0x1f;
1127 vp->mii.reg_num_mask = 0x1f;
1128
1129 /* Makes sure rings are at least 16 byte aligned. */
1130 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1131 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1132 &vp->rx_ring_dma);
1133 retval = -ENOMEM;
cc2d6596 1134 if (!vp->rx_ring)
1da177e4
LT		 1135 goto free_region;
1136
1137 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1138 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1139
1140 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1141 * instead of a module list */
1da177e4
LT		 1142 if (pdev)
1143 pci_set_drvdata(pdev, dev);
1144 if (edev)
a880c4cd 1145 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1146
1147 vp->media_override = 7;
1148 if (option >= 0) {
1149 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1150 if (vp->media_override != 7)
1151 vp->medialock = 1;
1152 vp->full_duplex = (option & 0x200) ? 1 : 0;
1153 vp->bus_master = (option & 16) ? 1 : 0;
1154 }
1155
1156 if (global_full_duplex > 0)
1157 vp->full_duplex = 1;
1158 if (global_enable_wol > 0)
1159 vp->enable_wol = 1;
1160
1161 if (card_idx < MAX_UNITS) {
1162 if (full_duplex[card_idx] > 0)
1163 vp->full_duplex = 1;
1164 if (flow_ctrl[card_idx] > 0)
1165 vp->flow_ctrl = 1;
1166 if (enable_wol[card_idx] > 0)
1167 vp->enable_wol = 1;
1168 }
1169
125d5ce8 1170 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1171 vp->options = option;
1172 /* Read the station address from the EEPROM. */
1173 EL3WINDOW(0);
1174 {
1175 int base;
1176
1177 if (vci->drv_flags & EEPROM_8BIT)
1178 base = 0x230;
1179 else if (vci->drv_flags & EEPROM_OFFSET)
1180 base = EEPROM_Read + 0x30;
1181 else
1182 base = EEPROM_Read;
1183
1184 for (i = 0; i < 0x40; i++) {
1185 int timer;
62afe595 1186 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1187 /* Pause for at least 162 us. for the read to take place. */
1188 for (timer = 10; timer >= 0; timer--) {
1189 udelay(162);
62afe595 1190 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1191 break;
1192 }
62afe595 1193 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1194 }
1195 }
1196 for (i = 0; i < 0x18; i++)
1197 checksum ^= eeprom[i];
1198 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1199 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1200 while (i < 0x21)
1201 checksum ^= eeprom[i++];
1202 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1203 }
1204 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1205 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1206 for (i = 0; i < 3; i++)
cc2d6596 1207 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1208 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57
JP		 1209 if (print_info)
1210 printk(" %s", print_mac(mac, dev->dev_addr));
1da177e4
LT		 1211 /* Unfortunately an all zero eeprom passes the checksum and this
1212 gets found in the wild in failure cases. Crypto is hard 8) */
1213 if (!is_valid_ether_addr(dev->dev_addr)) {
1214 retval = -EINVAL;
1215 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1216 goto free_ring; /* With every pack */
1217 }
1218 EL3WINDOW(2);
1219 for (i = 0; i < 6; i++)
62afe595 1220 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1221
1da177e4
LT		 1222 if (print_info)
1223 printk(", IRQ %d\n", dev->irq);
1224 /* Tell them about an invalid IRQ. */
1225 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1226 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1227 dev->irq);
1da177e4
LT		 1228
1229 EL3WINDOW(4);
62afe595 1230 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1231 if (print_info) {
1232 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1233 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1234 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1235 }
1236
1237
1238 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1239 unsigned short n;
1240
62afe595
JL		 1241 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1242 if (!vp->cb_fn_base) {
1da177e4 1243 retval = -ENOMEM;
62afe595 1244 goto free_ring;
1da177e4 1245 }
62afe595 1246
1da177e4 1247 if (print_info) {
7c7459d1
GKH		 1248 printk(KERN_INFO "%s: CardBus functions mapped "
1249 "%16.16llx->%p\n",
1250 print_name,
1251 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1252 vp->cb_fn_base);
1da177e4
LT		 1253 }
1254 EL3WINDOW(2);
1255
62afe595 1256 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1257 if (vp->drv_flags & INVERT_LED_PWR)
1258 n |= 0x10;
1259 if (vp->drv_flags & INVERT_MII_PWR)
1260 n |= 0x4000;
62afe595 1261 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1262 if (vp->drv_flags & WNO_XCVR_PWR) {
1263 EL3WINDOW(0);
62afe595 1264 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1265 }
1266 }
1267
1268 /* Extract our information from the EEPROM data. */
1269 vp->info1 = eeprom[13];
1270 vp->info2 = eeprom[15];
1271 vp->capabilities = eeprom[16];
1272
1273 if (vp->info1 & 0x8000) {
1274 vp->full_duplex = 1;
1275 if (print_info)
1276 printk(KERN_INFO "Full duplex capable\n");
1277 }
1278
1279 {
f71e1309 1280 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1281 unsigned int config;
1282 EL3WINDOW(3);
62afe595 1283 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1284 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1285 vp->available_media = 0x40;
62afe595 1286 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1287 if (print_info) {
1288 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1289 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1290 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1291 8 << RAM_SIZE(config),
1292 RAM_WIDTH(config) ? "word" : "byte",
1293 ram_split[RAM_SPLIT(config)],
1294 AUTOSELECT(config) ? "autoselect/" : "",
1295 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1296 media_tbl[XCVR(config)].name);
1297 }
1298 vp->default_media = XCVR(config);
1299 if (vp->default_media == XCVR_NWAY)
1300 vp->has_nway = 1;
1301 vp->autoselect = AUTOSELECT(config);
1302 }
1303
1304 if (vp->media_override != 7) {
1305 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1306 print_name, vp->media_override,
1307 media_tbl[vp->media_override].name);
1308 dev->if_port = vp->media_override;
1309 } else
1310 dev->if_port = vp->default_media;
1311
1312 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1313 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1314 int phy, phy_idx = 0;
1315 EL3WINDOW(4);
1316 mii_preamble_required++;
1317 if (vp->drv_flags & EXTRA_PREAMBLE)
1318 mii_preamble_required++;
1319 mdio_sync(ioaddr, 32);
106427e6 1320 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1321 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1322 int mii_status, phyx;
1323
1324 /*
1325 * For the 3c905CX we look at index 24 first, because it bogusly
1326 * reports an external PHY at all indices
1327 */
1328 if (phy == 0)
1329 phyx = 24;
1330 else if (phy <= 24)
1331 phyx = phy - 1;
1332 else
1333 phyx = phy;
106427e6 1334 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1335 if (mii_status && mii_status != 0xffff) {
1336 vp->phys[phy_idx++] = phyx;
1337 if (print_info) {
1338 printk(KERN_INFO " MII transceiver found at address %d,"
1339 " status %4x.\n", phyx, mii_status);
1340 }
1341 if ((mii_status & 0x0040) == 0)
1342 mii_preamble_required++;
1343 }
1344 }
1345 mii_preamble_required--;
1346 if (phy_idx == 0) {
1347 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1348 vp->phys[0] = 24;
1349 } else {
106427e6 1350 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1351 if (vp->full_duplex) {
1352 /* Only advertise the FD media types. */
1353 vp->advertising &= ~0x02A0;
1354 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1355 }
1356 }
1357 vp->mii.phy_id = vp->phys[0];
1358 }
1359
1360 if (vp->capabilities & CapBusMaster) {
1361 vp->full_bus_master_tx = 1;
1362 if (print_info) {
1363 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1364 (vp->info2 & 1) ? "early" : "whole-frame" );
1365 }
1366 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1367 vp->bus_master = 0; /* AKPM: vortex only */
1368 }
1369
1370 /* The 3c59x-specific entries in the device structure. */
1371 dev->open = vortex_open;
1372 if (vp->full_bus_master_tx) {
1373 dev->hard_start_xmit = boomerang_start_xmit;
1374 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1375 if (card_idx < MAX_UNITS &&
1376 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1377 hw_checksums[card_idx] == 1)) {
d311b0d3 1378 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1379 }
1380 } else {
1381 dev->hard_start_xmit = vortex_start_xmit;
1382 }
1383
1384 if (print_info) {
1385 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1386 print_name,
1387 (dev->features & NETIF_F_SG) ? "en":"dis",
1388 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1389 }
1390
1391 dev->stop = vortex_close;
1392 dev->get_stats = vortex_get_stats;
1393#ifdef CONFIG_PCI
1394 dev->do_ioctl = vortex_ioctl;
1395#endif
1396 dev->ethtool_ops = &vortex_ethtool_ops;
1397 dev->set_multicast_list = set_rx_mode;
1398 dev->tx_timeout = vortex_tx_timeout;
1399 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1400#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 1401 dev->poll_controller = poll_vortex;
1da177e4
LT		 1402#endif
1403 if (pdev) {
1404 vp->pm_state_valid = 1;
1405 pci_save_state(VORTEX_PCI(vp));
1406 acpi_set_WOL(dev);
1407 }
1408 retval = register_netdev(dev);
1409 if (retval == 0)
1410 return 0;
1411
1412free_ring:
1413 pci_free_consistent(pdev,
1414 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1415 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1416 vp->rx_ring,
1417 vp->rx_ring_dma);
1418free_region:
1419 if (vp->must_free_region)
62afe595 1420 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1421 free_netdev(dev);
1422 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1423out:
1424 return retval;
1425}
1426
1427static void
1428issue_and_wait(struct net_device *dev, int cmd)
1429{
62afe595
JL		 1430 struct vortex_private *vp = netdev_priv(dev);
1431 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1432 int i;
1433
62afe595 1434 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1435 for (i = 0; i < 2000; i++) {
62afe595 1436 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1437 return;
1438 }
1439
1440 /* OK, that didn't work. Do it the slow way. One second */
1441 for (i = 0; i < 100000; i++) {
62afe595 1442 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1443 if (vortex_debug > 1)
1444 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1445 dev->name, cmd, i * 10);
1446 return;
1447 }
1448 udelay(10);
1449 }
1450 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1451 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1452}
1453
125d5ce8
SK		 1454static void
1455vortex_set_duplex(struct net_device *dev)
1456{
1457 struct vortex_private *vp = netdev_priv(dev);
1458 void __iomem *ioaddr = vp->ioaddr;
1459
1460 printk(KERN_INFO "%s: setting %s-duplex.\n",
1461 dev->name, (vp->full_duplex) ? "full" : "half");
1462
1463 EL3WINDOW(3);
1464 /* Set the full-duplex bit. */
1465 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1466 (vp->large_frames ? 0x40 : 0) |
1467 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1468 0x100 : 0),
1469 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1470}
1471
1472static void vortex_check_media(struct net_device *dev, unsigned int init)
1473{
1474 struct vortex_private *vp = netdev_priv(dev);
1475 unsigned int ok_to_print = 0;
1476
1477 if (vortex_debug > 3)
1478 ok_to_print = 1;
1479
1480 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1481 vp->full_duplex = vp->mii.full_duplex;
1482 vortex_set_duplex(dev);
1483 } else if (init) {
1484 vortex_set_duplex(dev);
1485 }
1486}
1487
c8303d10 1488static int
1da177e4
LT		 1489vortex_up(struct net_device *dev)
1490{
1da177e4 1491 struct vortex_private *vp = netdev_priv(dev);
62afe595 1492 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1493 unsigned int config;
0280f9f9 1494 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1495
1496 if (VORTEX_PCI(vp)) {
1497 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1498 if (vp->pm_state_valid)
1499 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1500 err = pci_enable_device(VORTEX_PCI(vp));
1501 if (err) {
1502 printk(KERN_WARNING "%s: Could not enable device \n",
1503 dev->name);
1504 goto err_out;
1505 }
1da177e4
LT		 1506 }
1507
1508 /* Before initializing select the active media port. */
1509 EL3WINDOW(3);
62afe595 1510 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1511
1512 if (vp->media_override != 7) {
1513 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1514 dev->name, vp->media_override,
1515 media_tbl[vp->media_override].name);
1516 dev->if_port = vp->media_override;
1517 } else if (vp->autoselect) {
1518 if (vp->has_nway) {
1519 if (vortex_debug > 1)
1520 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1521 dev->name, dev->if_port);
1522 dev->if_port = XCVR_NWAY;
1523 } else {
1524 /* Find first available media type, starting with 100baseTx. */
1525 dev->if_port = XCVR_100baseTx;
1526 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1527 dev->if_port = media_tbl[dev->if_port].next;
1528 if (vortex_debug > 1)
1529 printk(KERN_INFO "%s: first available media type: %s\n",
1530 dev->name, media_tbl[dev->if_port].name);
1531 }
1532 } else {
1533 dev->if_port = vp->default_media;
1534 if (vortex_debug > 1)
1535 printk(KERN_INFO "%s: using default media %s\n",
1536 dev->name, media_tbl[dev->if_port].name);
1537 }
1538
1539 init_timer(&vp->timer);
1540 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1541 vp->timer.data = (unsigned long)dev;
1542 vp->timer.function = vortex_timer; /* timer handler */
1543 add_timer(&vp->timer);
1544
1545 init_timer(&vp->rx_oom_timer);
1546 vp->rx_oom_timer.data = (unsigned long)dev;
1547 vp->rx_oom_timer.function = rx_oom_timer;
1548
1549 if (vortex_debug > 1)
1550 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1551 dev->name, media_tbl[dev->if_port].name);
1552
125d5ce8 1553 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1554 config = BFINS(config, dev->if_port, 20, 4);
1555 if (vortex_debug > 6)
1556 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1557 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1558
1559 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1560 EL3WINDOW(4);
09ce3512
SK		 1561 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1562 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1563 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1564 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1565
125d5ce8 1566 vortex_check_media(dev, 1);
1da177e4 1567 }
125d5ce8
SK		 1568 else
1569 vortex_set_duplex(dev);
1da177e4 1570
09ce3512
SK		 1571 issue_and_wait(dev, TxReset);
1572 /*
1573 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1574 */
1575 issue_and_wait(dev, RxReset|0x04);
1576
1da177e4 1577
62afe595 1578 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1579
1580 if (vortex_debug > 1) {
1581 EL3WINDOW(4);
1582 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1583 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1584 }
1585
1586 /* Set the station address and mask in window 2 each time opened. */
1587 EL3WINDOW(2);
1588 for (i = 0; i < 6; i++)
62afe595 1589 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1590 for (; i < 12; i+=2)
62afe595 1591 iowrite16(0, ioaddr + i);
1da177e4
LT		 1592
1593 if (vp->cb_fn_base) {
62afe595 1594 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1595 if (vp->drv_flags & INVERT_LED_PWR)
1596 n |= 0x10;
1597 if (vp->drv_flags & INVERT_MII_PWR)
1598 n |= 0x4000;
62afe595 1599 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1600 }
1601
1602 if (dev->if_port == XCVR_10base2)
1603 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1604 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1605 if (dev->if_port != XCVR_NWAY) {
1606 EL3WINDOW(4);
62afe595 1607 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1608 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1609 }
1610
1611 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1612 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1613 EL3WINDOW(6);
1614 for (i = 0; i < 10; i++)
62afe595
JL		 1615 ioread8(ioaddr + i);
1616 ioread16(ioaddr + 10);
1617 ioread16(ioaddr + 12);
1da177e4
LT		 1618 /* New: On the Vortex we must also clear the BadSSD counter. */
1619 EL3WINDOW(4);
62afe595 1620 ioread8(ioaddr + 12);
1da177e4 1621 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1622 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1623
1624 /* Switch to register set 7 for normal use. */
1625 EL3WINDOW(7);
1626
1627 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1628 vp->cur_rx = vp->dirty_rx = 0;
1629 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1630 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1631 iowrite32(0x0020, ioaddr + PktStatus);
1632 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1633 }
1634 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1635 vp->cur_tx = vp->dirty_tx = 0;
1636 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1637 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1638 /* Clear the Rx, Tx rings. */
1639 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1640 vp->rx_ring[i].status = 0;
1641 for (i = 0; i < TX_RING_SIZE; i++)
1642 vp->tx_skbuff[i] = NULL;
62afe595 1643 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1644 }
1645 /* Set receiver mode: presumably accept b-case and phys addr only. */
1646 set_rx_mode(dev);
1647 /* enable 802.1q tagged frames */
1648 set_8021q_mode(dev, 1);
62afe595 1649 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1650
62afe595
JL		 1651 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1652 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1653 /* Allow status bits to be seen. */
1654 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1655 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1656 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1657 (vp->bus_master ? DMADone : 0);
1658 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1659 (vp->full_bus_master_rx ? 0 : RxComplete) |
1660 StatsFull | HostError | TxComplete | IntReq
1661 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1662 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1663 /* Ack all pending events, and set active indicator mask. */
62afe595 1664 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1665 ioaddr + EL3_CMD);
62afe595 1666 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1667 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1668 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1669 netif_start_queue (dev);
c8303d10
MH		 1670err_out:
1671 return err;
1da177e4
LT		 1672}
1673
1674static int
1675vortex_open(struct net_device *dev)
1676{
1677 struct vortex_private *vp = netdev_priv(dev);
1678 int i;
1679 int retval;
1680
1681 /* Use the now-standard shared IRQ implementation. */
1682 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1683 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4 1684 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1685 goto err;
1da177e4
LT		 1686 }
1687
1688 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1689 if (vortex_debug > 2)
1690 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1691 for (i = 0; i < RX_RING_SIZE; i++) {
1692 struct sk_buff *skb;
1693 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1694 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1695 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1696 skb = dev_alloc_skb(PKT_BUF_SZ);
1697 vp->rx_skbuff[i] = skb;
1698 if (skb == NULL)
1699 break; /* Bad news! */
1700 skb->dev = dev; /* Mark as being used by this device. */
1701 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1702 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1703 }
1704 if (i != RX_RING_SIZE) {
1705 int j;
1706 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1707 for (j = 0; j < i; j++) {
1708 if (vp->rx_skbuff[j]) {
1709 dev_kfree_skb(vp->rx_skbuff[j]);
1710 vp->rx_skbuff[j] = NULL;
1711 }
1712 }
1713 retval = -ENOMEM;
c8303d10 1714 goto err_free_irq;
1da177e4
LT		 1715 }
1716 /* Wrap the ring. */
1717 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1718 }
1719
c8303d10
MH		 1720 retval = vortex_up(dev);
1721 if (!retval)
1722 goto out;
1da177e4 1723
c8303d10 1724err_free_irq:
1da177e4 1725 free_irq(dev->irq, dev);
c8303d10 1726err:
1da177e4
LT		 1727 if (vortex_debug > 1)
1728 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1729out:
1da177e4
LT		 1730 return retval;
1731}
1732
1733static void
1734vortex_timer(unsigned long data)
1735{
1736 struct net_device *dev = (struct net_device *)data;
1737 struct vortex_private *vp = netdev_priv(dev);
62afe595 1738 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1739 int next_tick = 60*HZ;
1740 int ok = 0;
125d5ce8 1741 int media_status, old_window;
1da177e4
LT		 1742
1743 if (vortex_debug > 2) {
1744 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1745 dev->name, media_tbl[dev->if_port].name);
1746 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1747 }
1748
0a9da4bd 1749 disable_irq_lockdep(dev->irq);
62afe595 1750 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1751 EL3WINDOW(4);
62afe595 1752 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1753 switch (dev->if_port) {
1754 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1755 if (media_status & Media_LnkBeat) {
1756 netif_carrier_on(dev);
1757 ok = 1;
1758 if (vortex_debug > 1)
1759 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1760 dev->name, media_tbl[dev->if_port].name, media_status);
1761 } else {
1762 netif_carrier_off(dev);
1763 if (vortex_debug > 1) {
1764 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1765 dev->name, media_tbl[dev->if_port].name, media_status);
1766 }
1767 }
1768 break;
1769 case XCVR_MII: case XCVR_NWAY:
1770 {
1da177e4 1771 ok = 1;
125d5ce8
SK		 1772 spin_lock_bh(&vp->lock);
1773 vortex_check_media(dev, 0);
1da177e4
LT		 1774 spin_unlock_bh(&vp->lock);
1775 }
1776 break;
1777 default: /* Other media types handled by Tx timeouts. */
1778 if (vortex_debug > 1)
1779 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1780 dev->name, media_tbl[dev->if_port].name, media_status);
1781 ok = 1;
1782 }
b4ff6450
SK		 1783
1784 if (!netif_carrier_ok(dev))
1785 next_tick = 5*HZ;
1786
e94d10eb
SK		 1787 if (vp->medialock)
1788 goto leave_media_alone;
1789
a880c4cd 1790 if (!ok) {
1da177e4
LT		 1791 unsigned int config;
1792
1793 do {
1794 dev->if_port = media_tbl[dev->if_port].next;
1795 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1796 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1797 dev->if_port = vp->default_media;
1798 if (vortex_debug > 1)
1799 printk(KERN_DEBUG "%s: Media selection failing, using default "
1800 "%s port.\n",
1801 dev->name, media_tbl[dev->if_port].name);
1802 } else {
1803 if (vortex_debug > 1)
1804 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1805 "%s port.\n",
1806 dev->name, media_tbl[dev->if_port].name);
1807 next_tick = media_tbl[dev->if_port].wait;
1808 }
62afe595 1809 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1810 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1811
1812 EL3WINDOW(3);
62afe595 1813 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1814 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1815 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1816
62afe595 1817 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1818 ioaddr + EL3_CMD);
1819 if (vortex_debug > 1)
1820 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1821 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1822 }
1da177e4
LT		 1823
1824leave_media_alone:
1825 if (vortex_debug > 2)
1826 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1827 dev->name, media_tbl[dev->if_port].name);
1828
e94d10eb 1829 EL3WINDOW(old_window);
0a9da4bd 1830 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1831 mod_timer(&vp->timer, RUN_AT(next_tick));
1832 if (vp->deferred)
62afe595 1833 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1834 return;
1835}
1836
1837static void vortex_tx_timeout(struct net_device *dev)
1838{
1839 struct vortex_private *vp = netdev_priv(dev);
62afe595 1840 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1841
1842 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1843 dev->name, ioread8(ioaddr + TxStatus),
1844 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1845 EL3WINDOW(4);
1846 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1847 ioread16(ioaddr + Wn4_NetDiag),
1848 ioread16(ioaddr + Wn4_Media),
1849 ioread32(ioaddr + PktStatus),
1850 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1851 /* Slight code bloat to be user friendly. */
62afe595 1852 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1853 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1854 " network cable problem?\n", dev->name);
62afe595 1855 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1856 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1857 " IRQ blocked by another device?\n", dev->name);
1858 /* Bad idea here.. but we might as well handle a few events. */
1859 {
1860 /*
1861 * Block interrupts because vortex_interrupt does a bare spin_lock()
1862 */
1863 unsigned long flags;
1864 local_irq_save(flags);
1865 if (vp->full_bus_master_tx)
7d12e780 1866 boomerang_interrupt(dev->irq, dev);
1da177e4 1867 else
7d12e780 1868 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1869 local_irq_restore(flags);
1870 }
1871 }
1872
1873 if (vortex_debug > 0)
1874 dump_tx_ring(dev);
1875
1876 issue_and_wait(dev, TxReset);
1877
1878 vp->stats.tx_errors++;
1879 if (vp->full_bus_master_tx) {
1880 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1881 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1882 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1883 ioaddr + DownListPtr);
1884 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1885 netif_wake_queue (dev);
1886 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1887 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1888 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 1889 } else {
1890 vp->stats.tx_dropped++;
1891 netif_wake_queue(dev);
1892 }
6aa20a22 1893
1da177e4 1894 /* Issue Tx Enable */
62afe595 1895 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1896 dev->trans_start = jiffies;
6aa20a22 1897
1da177e4
LT		 1898 /* Switch to register set 7 for normal use. */
1899 EL3WINDOW(7);
1900}
1901
1902/*
1903 * Handle uncommon interrupt sources. This is a separate routine to minimize
1904 * the cache impact.
1905 */
1906static void
1907vortex_error(struct net_device *dev, int status)
1908{
1909 struct vortex_private *vp = netdev_priv(dev);
62afe595 1910 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1911 int do_tx_reset = 0, reset_mask = 0;
1912 unsigned char tx_status = 0;
1913
1914 if (vortex_debug > 2) {
1915 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1916 }
1917
1918 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1919 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1920 /* Presumably a tx-timeout. We must merely re-enable. */
1921 if (vortex_debug > 2
1922 || (tx_status != 0x88 && vortex_debug > 0)) {
1923 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1924 dev->name, tx_status);
1925 if (tx_status == 0x82) {
1926 printk(KERN_ERR "Probably a duplex mismatch. See "
1927 "Documentation/networking/vortex.txt\n");
1928 }
1929 dump_tx_ring(dev);
1930 }
1931 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1932 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
0000754c 1933 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1934 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1935 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1936 do_tx_reset = 1;
0000754c
AM		 1937 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1938 do_tx_reset = 1;
1939 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1940 } else { /* Merely re-enable the transmitter. */
62afe595 1941 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1942 }
1943 }
1944
1945 if (status & RxEarly) { /* Rx early is unused. */
1946 vortex_rx(dev);
62afe595 1947 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1948 }
1949 if (status & StatsFull) { /* Empty statistics. */
1950 static int DoneDidThat;
1951 if (vortex_debug > 4)
1952 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1953 update_stats(ioaddr, dev);
1954 /* HACK: Disable statistics as an interrupt source. */
1955 /* This occurs when we have the wrong media type! */
1956 if (DoneDidThat == 0 &&
62afe595 1957 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1958 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1959 "stats as an interrupt source.\n", dev->name);
1960 EL3WINDOW(5);
62afe595 1961 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1962 vp->intr_enable &= ~StatsFull;
1963 EL3WINDOW(7);
1964 DoneDidThat++;
1965 }
1966 }
1967 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1968 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1969 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1970 }
1971 if (status & HostError) {
1972 u16 fifo_diag;
1973 EL3WINDOW(4);
62afe595 1974 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 1975 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1976 dev->name, fifo_diag);
1977 /* Adapter failure requires Tx/Rx reset and reinit. */
1978 if (vp->full_bus_master_tx) {
62afe595 1979 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 1980 /* 0x80000000 PCI master abort. */
1981 /* 0x40000000 PCI target abort. */
1982 if (vortex_debug)
1983 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1984
1985 /* In this case, blow the card away */
1986 /* Must not enter D3 or we can't legally issue the reset! */
1987 vortex_down(dev, 0);
1988 issue_and_wait(dev, TotalReset | 0xff);
1989 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1990 } else if (fifo_diag & 0x0400)
1991 do_tx_reset = 1;
1992 if (fifo_diag & 0x3000) {
1993 /* Reset Rx fifo and upload logic */
1994 issue_and_wait(dev, RxReset|0x07);
1995 /* Set the Rx filter to the current state. */
1996 set_rx_mode(dev);
1997 /* enable 802.1q VLAN tagged frames */
1998 set_8021q_mode(dev, 1);
62afe595
JL		 1999 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2000 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2001 }
2002 }
2003
2004 if (do_tx_reset) {
2005 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2006 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2007 if (!vp->full_bus_master_tx)
2008 netif_wake_queue(dev);
2009 }
2010}
2011
2012static int
2013vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2014{
2015 struct vortex_private *vp = netdev_priv(dev);
62afe595 2016 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2017
2018 /* Put out the doubleword header... */
62afe595 2019 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2020 if (vp->bus_master) {
2021 /* Set the bus-master controller to transfer the packet. */
2022 int len = (skb->len + 3) & ~3;
a880c4cd 2023 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2024 ioaddr + Wn7_MasterAddr);
62afe595 2025 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2026 vp->tx_skb = skb;
62afe595 2027 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2028 /* netif_wake_queue() will be called at the DMADone interrupt. */
2029 } else {
2030 /* ... and the packet rounded to a doubleword. */
62afe595 2031 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2032 dev_kfree_skb (skb);
62afe595 2033 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2034 netif_start_queue (dev); /* AKPM: redundant? */
2035 } else {
2036 /* Interrupt us when the FIFO has room for max-sized packet. */
2037 netif_stop_queue(dev);
62afe595 2038 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2039 }
2040 }
2041
2042 dev->trans_start = jiffies;
2043
2044 /* Clear the Tx status stack. */
2045 {
2046 int tx_status;
2047 int i = 32;
2048
62afe595 2049 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2050 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2051 if (vortex_debug > 2)
2052 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2053 dev->name, tx_status);
2054 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2055 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2056 if (tx_status & 0x30) {
2057 issue_and_wait(dev, TxReset);
2058 }
62afe595 2059 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2060 }
62afe595 2061 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2062 }
2063 }
2064 return 0;
2065}
2066
2067static int
2068boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2069{
2070 struct vortex_private *vp = netdev_priv(dev);
62afe595 2071 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2072 /* Calculate the next Tx descriptor entry. */
2073 int entry = vp->cur_tx % TX_RING_SIZE;
2074 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2075 unsigned long flags;
2076
2077 if (vortex_debug > 6) {
2078 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2079 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2080 dev->name, vp->cur_tx);
1da177e4
LT		 2081 }
2082
2083 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2084 if (vortex_debug > 0)
2085 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2086 dev->name);
2087 netif_stop_queue(dev);
2088 return 1;
2089 }
2090
2091 vp->tx_skbuff[entry] = skb;
2092
2093 vp->tx_ring[entry].next = 0;
2094#if DO_ZEROCOPY
84fa7933 2095 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2096 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2097 else
2098 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2099
2100 if (!skb_shinfo(skb)->nr_frags) {
2101 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2102 skb->len, PCI_DMA_TODEVICE));
2103 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2104 } else {
2105 int i;
2106
2107 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2108 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2109 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2110
2111 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2112 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2113
2114 vp->tx_ring[entry].frag[i+1].addr =
2115 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2116 (void*)page_address(frag->page) + frag->page_offset,
2117 frag->size, PCI_DMA_TODEVICE));
2118
2119 if (i == skb_shinfo(skb)->nr_frags-1)
2120 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2121 else
2122 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2123 }
2124 }
2125#else
2126 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2127 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2128 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2129#endif
2130
2131 spin_lock_irqsave(&vp->lock, flags);
2132 /* Wait for the stall to complete. */
2133 issue_and_wait(dev, DownStall);
2134 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2135 if (ioread32(ioaddr + DownListPtr) == 0) {
2136 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2137 vp->queued_packet++;
2138 }
2139
2140 vp->cur_tx++;
2141 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2142 netif_stop_queue (dev);
2143 } else { /* Clear previous interrupt enable. */
2144#if defined(tx_interrupt_mitigation)
2145 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2146 * were selected, this would corrupt DN_COMPLETE. No?
2147 */
2148 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2149#endif
2150 }
62afe595 2151 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2152 spin_unlock_irqrestore(&vp->lock, flags);
2153 dev->trans_start = jiffies;
2154 return 0;
2155}
2156
2157/* The interrupt handler does all of the Rx thread work and cleans up
2158 after the Tx thread. */
2159
2160/*
2161 * This is the ISR for the vortex series chips.
2162 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2163 */
2164
2165static irqreturn_t
7d12e780 2166vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2167{
2168 struct net_device *dev = dev_id;
2169 struct vortex_private *vp = netdev_priv(dev);
62afe595 2170 void __iomem *ioaddr;
1da177e4
LT		 2171 int status;
2172 int work_done = max_interrupt_work;
2173 int handled = 0;
2174
62afe595 2175 ioaddr = vp->ioaddr;
1da177e4
LT		 2176 spin_lock(&vp->lock);
2177
62afe595 2178 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2179
2180 if (vortex_debug > 6)
2181 printk("vortex_interrupt(). status=0x%4x\n", status);
2182
2183 if ((status & IntLatch) == 0)
2184 goto handler_exit; /* No interrupt: shared IRQs cause this */
2185 handled = 1;
2186
2187 if (status & IntReq) {
2188 status |= vp->deferred;
2189 vp->deferred = 0;
2190 }
2191
2192 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2193 goto handler_exit;
2194
2195 if (vortex_debug > 4)
2196 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2197 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2198
2199 do {
2200 if (vortex_debug > 5)
2201 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2202 dev->name, status);
2203 if (status & RxComplete)
2204 vortex_rx(dev);
2205
2206 if (status & TxAvailable) {
2207 if (vortex_debug > 5)
2208 printk(KERN_DEBUG " TX room bit was handled.\n");
2209 /* There's room in the FIFO for a full-sized packet. */
62afe595 2210 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2211 netif_wake_queue (dev);
2212 }
2213
2214 if (status & DMADone) {
62afe595
JL		 2215 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2216 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2217 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2218 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2219 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2220 /*
2221 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2222 * insufficient FIFO room, the TxAvailable test will succeed and call
2223 * netif_wake_queue()
2224 */
2225 netif_wake_queue(dev);
2226 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2227 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2228 netif_stop_queue(dev);
2229 }
2230 }
2231 }
2232 /* Check for all uncommon interrupts at once. */
2233 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2234 if (status == 0xffff)
2235 break;
2236 vortex_error(dev, status);
2237 }
2238
2239 if (--work_done < 0) {
2240 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2241 "%4.4x.\n", dev->name, status);
2242 /* Disable all pending interrupts. */
2243 do {
2244 vp->deferred |= status;
62afe595 2245 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2246 ioaddr + EL3_CMD);
62afe595
JL		 2247 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2248 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2249 /* The timer will reenable interrupts. */
2250 mod_timer(&vp->timer, jiffies + 1*HZ);
2251 break;
2252 }
2253 /* Acknowledge the IRQ. */
62afe595
JL		 2254 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2255 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2256
2257 if (vortex_debug > 4)
2258 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2259 dev->name, status);
2260handler_exit:
2261 spin_unlock(&vp->lock);
2262 return IRQ_RETVAL(handled);
2263}
2264
2265/*
2266 * This is the ISR for the boomerang series chips.
2267 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2268 */
2269
2270static irqreturn_t
7d12e780 2271boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2272{
2273 struct net_device *dev = dev_id;
2274 struct vortex_private *vp = netdev_priv(dev);
62afe595 2275 void __iomem *ioaddr;
1da177e4
LT		 2276 int status;
2277 int work_done = max_interrupt_work;
2278
62afe595 2279 ioaddr = vp->ioaddr;
1da177e4
LT		 2280
2281 /*
2282 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2283 * and boomerang_start_xmit
2284 */
2285 spin_lock(&vp->lock);
2286
62afe595 2287 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2288
2289 if (vortex_debug > 6)
2290 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2291
2292 if ((status & IntLatch) == 0)
2293 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2294
2295 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2296 if (vortex_debug > 1)
2297 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2298 goto handler_exit;
2299 }
2300
2301 if (status & IntReq) {
2302 status |= vp->deferred;
2303 vp->deferred = 0;
2304 }
2305
2306 if (vortex_debug > 4)
2307 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2308 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2309 do {
2310 if (vortex_debug > 5)
2311 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2312 dev->name, status);
2313 if (status & UpComplete) {
62afe595 2314 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2315 if (vortex_debug > 5)
2316 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2317 boomerang_rx(dev);
2318 }
2319
2320 if (status & DownComplete) {
2321 unsigned int dirty_tx = vp->dirty_tx;
2322
62afe595 2323 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2324 while (vp->cur_tx - dirty_tx > 0) {
2325 int entry = dirty_tx % TX_RING_SIZE;
2326#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2327 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2328 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2329 break; /* It still hasn't been processed. */
2330#else
2331 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2332 break; /* It still hasn't been processed. */
2333#endif
6aa20a22 2334
1da177e4
LT		 2335 if (vp->tx_skbuff[entry]) {
2336 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2337#if DO_ZEROCOPY
1da177e4
LT		 2338 int i;
2339 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2340 pci_unmap_single(VORTEX_PCI(vp),
2341 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2342 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2343 PCI_DMA_TODEVICE);
2344#else
2345 pci_unmap_single(VORTEX_PCI(vp),
2346 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2347#endif
2348 dev_kfree_skb_irq(skb);
2349 vp->tx_skbuff[entry] = NULL;
2350 } else {
2351 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2352 }
2353 /* vp->stats.tx_packets++; Counted below. */
2354 dirty_tx++;
2355 }
2356 vp->dirty_tx = dirty_tx;
2357 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2358 if (vortex_debug > 6)
2359 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2360 netif_wake_queue (dev);
2361 }
2362 }
2363
2364 /* Check for all uncommon interrupts at once. */
2365 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2366 vortex_error(dev, status);
2367
2368 if (--work_done < 0) {
2369 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2370 "%4.4x.\n", dev->name, status);
2371 /* Disable all pending interrupts. */
2372 do {
2373 vp->deferred |= status;
62afe595 2374 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2375 ioaddr + EL3_CMD);
62afe595
JL		 2376 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2377 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2378 /* The timer will reenable interrupts. */
2379 mod_timer(&vp->timer, jiffies + 1*HZ);
2380 break;
2381 }
2382 /* Acknowledge the IRQ. */
62afe595 2383 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2384 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2385 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2386
62afe595 2387 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2388
2389 if (vortex_debug > 4)
2390 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2391 dev->name, status);
2392handler_exit:
2393 spin_unlock(&vp->lock);
2394 return IRQ_HANDLED;
2395}
2396
2397static int vortex_rx(struct net_device *dev)
2398{
2399 struct vortex_private *vp = netdev_priv(dev);
62afe595 2400 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2401 int i;
2402 short rx_status;
2403
2404 if (vortex_debug > 5)
2405 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2406 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2407 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2408 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2409 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2410 if (vortex_debug > 2)
2411 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2412 vp->stats.rx_errors++;
2413 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2414 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2415 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2416 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2417 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2418 } else {
2419 /* The packet length: up to 4.5K!. */
2420 int pkt_len = rx_status & 0x1fff;
2421 struct sk_buff *skb;
2422
2423 skb = dev_alloc_skb(pkt_len + 5);
2424 if (vortex_debug > 4)
2425 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2426 pkt_len, rx_status);
2427 if (skb != NULL) {
1da177e4
LT		 2428 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2429 /* 'skb_put()' points to the start of sk_buff data area. */
2430 if (vp->bus_master &&
62afe595 2431 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2432 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2433 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2434 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2435 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2436 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2437 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2438 ;
2439 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2440 } else {
62afe595
JL		 2441 ioread32_rep(ioaddr + RX_FIFO,
2442 skb_put(skb, pkt_len),
2443 (pkt_len + 3) >> 2);
1da177e4 2444 }
62afe595 2445 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2446 skb->protocol = eth_type_trans(skb, dev);
2447 netif_rx(skb);
2448 dev->last_rx = jiffies;
2449 vp->stats.rx_packets++;
2450 /* Wait a limited time to go to next packet. */
2451 for (i = 200; i >= 0; i--)
62afe595 2452 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2453 break;
2454 continue;
2455 } else if (vortex_debug > 0)
2456 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2457 "size %d.\n", dev->name, pkt_len);
35b30674 2458 vp->stats.rx_dropped++;
1da177e4 2459 }
1da177e4
LT		 2460 issue_and_wait(dev, RxDiscard);
2461 }
2462
2463 return 0;
2464}
2465
2466static int
2467boomerang_rx(struct net_device *dev)
2468{
2469 struct vortex_private *vp = netdev_priv(dev);
2470 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2471 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2472 int rx_status;
2473 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2474
2475 if (vortex_debug > 5)
62afe595 2476 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2477
2478 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2479 if (--rx_work_limit < 0)
2480 break;
2481 if (rx_status & RxDError) { /* Error, update stats. */
2482 unsigned char rx_error = rx_status >> 16;
2483 if (vortex_debug > 2)
2484 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2485 vp->stats.rx_errors++;
2486 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2487 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2488 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2489 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2490 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2491 } else {
2492 /* The packet length: up to 4.5K!. */
2493 int pkt_len = rx_status & 0x1fff;
2494 struct sk_buff *skb;
2495 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2496
2497 if (vortex_debug > 4)
2498 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2499 pkt_len, rx_status);
2500
2501 /* Check if the packet is long enough to just accept without
2502 copying to a properly sized skbuff. */
cc2d6596 2503 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2504 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2505 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2506 /* 'skb_put()' points to the start of sk_buff data area. */
2507 memcpy(skb_put(skb, pkt_len),
689be439 2508 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2509 pkt_len);
2510 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2511 vp->rx_copy++;
2512 } else {
2513 /* Pass up the skbuff already on the Rx ring. */
2514 skb = vp->rx_skbuff[entry];
2515 vp->rx_skbuff[entry] = NULL;
2516 skb_put(skb, pkt_len);
2517 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2518 vp->rx_nocopy++;
2519 }
2520 skb->protocol = eth_type_trans(skb, dev);
2521 { /* Use hardware checksum info. */
2522 int csum_bits = rx_status & 0xee000000;
2523 if (csum_bits &&
2524 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2525 csum_bits == (IPChksumValid | UDPChksumValid))) {
2526 skb->ip_summed = CHECKSUM_UNNECESSARY;
2527 vp->rx_csumhits++;
2528 }
2529 }
2530 netif_rx(skb);
2531 dev->last_rx = jiffies;
2532 vp->stats.rx_packets++;
2533 }
2534 entry = (++vp->cur_rx) % RX_RING_SIZE;
2535 }
2536 /* Refill the Rx ring buffers. */
2537 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2538 struct sk_buff *skb;
2539 entry = vp->dirty_rx % RX_RING_SIZE;
2540 if (vp->rx_skbuff[entry] == NULL) {
2541 skb = dev_alloc_skb(PKT_BUF_SZ);
2542 if (skb == NULL) {
2543 static unsigned long last_jif;
ff5688ae 2544 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2545 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2546 last_jif = jiffies;
2547 }
2548 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2549 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2550 break; /* Bad news! */
2551 }
2552 skb->dev = dev; /* Mark as being used by this device. */
2553 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2554 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2555 vp->rx_skbuff[entry] = skb;
2556 }
2557 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2558 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2559 }
2560 return 0;
2561}
2562
2563/*
2564 * If we've hit a total OOM refilling the Rx ring we poll once a second
2565 * for some memory. Otherwise there is no way to restart the rx process.
2566 */
2567static void
2568rx_oom_timer(unsigned long arg)
2569{
2570 struct net_device *dev = (struct net_device *)arg;
2571 struct vortex_private *vp = netdev_priv(dev);
2572
2573 spin_lock_irq(&vp->lock);
2574 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2575 boomerang_rx(dev);
2576 if (vortex_debug > 1) {
2577 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2578 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2579 }
2580 spin_unlock_irq(&vp->lock);
2581}
2582
2583static void
2584vortex_down(struct net_device *dev, int final_down)
2585{
2586 struct vortex_private *vp = netdev_priv(dev);
62afe595 2587 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2588
2589 netif_stop_queue (dev);
2590
2591 del_timer_sync(&vp->rx_oom_timer);
2592 del_timer_sync(&vp->timer);
2593
2594 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2595 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2596
2597 /* Disable the receiver and transmitter. */
62afe595
JL		 2598 iowrite16(RxDisable, ioaddr + EL3_CMD);
2599 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2600
2601 /* Disable receiving 802.1q tagged frames */
2602 set_8021q_mode(dev, 0);
2603
2604 if (dev->if_port == XCVR_10base2)
2605 /* Turn off thinnet power. Green! */
62afe595 2606 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2607
62afe595 2608 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2609
2610 update_stats(ioaddr, dev);
2611 if (vp->full_bus_master_rx)
62afe595 2612 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2613 if (vp->full_bus_master_tx)
62afe595 2614 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2615
2616 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2617 vp->pm_state_valid = 1;
1da177e4
LT		 2618 pci_save_state(VORTEX_PCI(vp));
2619 acpi_set_WOL(dev);
2620 }
2621}
2622
2623static int
2624vortex_close(struct net_device *dev)
2625{
2626 struct vortex_private *vp = netdev_priv(dev);
62afe595 2627 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2628 int i;
2629
2630 if (netif_device_present(dev))
2631 vortex_down(dev, 1);
2632
2633 if (vortex_debug > 1) {
2634 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2635 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2636 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2637 " tx_queued %d Rx pre-checksummed %d.\n",
2638 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2639 }
2640
2641#if DO_ZEROCOPY
32fb5f06
JL		 2642 if (vp->rx_csumhits &&
2643 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2644 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2645 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2646 "not using them!\n", dev->name);
1da177e4
LT		 2647 }
2648#endif
6aa20a22 2649
1da177e4
LT		 2650 free_irq(dev->irq, dev);
2651
2652 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2653 for (i = 0; i < RX_RING_SIZE; i++)
2654 if (vp->rx_skbuff[i]) {
2655 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2656 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2657 dev_kfree_skb(vp->rx_skbuff[i]);
2658 vp->rx_skbuff[i] = NULL;
2659 }
2660 }
2661 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2662 for (i = 0; i < TX_RING_SIZE; i++) {
2663 if (vp->tx_skbuff[i]) {
2664 struct sk_buff *skb = vp->tx_skbuff[i];
2665#if DO_ZEROCOPY
2666 int k;
2667
2668 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2669 pci_unmap_single(VORTEX_PCI(vp),
2670 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2671 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2672 PCI_DMA_TODEVICE);
2673#else
2674 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2675#endif
2676 dev_kfree_skb(skb);
2677 vp->tx_skbuff[i] = NULL;
2678 }
2679 }
2680 }
2681
2682 return 0;
2683}
2684
2685static void
2686dump_tx_ring(struct net_device *dev)
2687{
2688 if (vortex_debug > 0) {
2689 struct vortex_private *vp = netdev_priv(dev);
62afe595 2690 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2691
1da177e4
LT		 2692 if (vp->full_bus_master_tx) {
2693 int i;
62afe595 2694 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2695
2696 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2697 vp->full_bus_master_tx,
2698 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2699 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2700 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2701 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2702 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2703 issue_and_wait(dev, DownStall);
2704 for (i = 0; i < TX_RING_SIZE; i++) {
2705 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2706 &vp->tx_ring[i],
2707#if DO_ZEROCOPY
2708 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2709#else
2710 le32_to_cpu(vp->tx_ring[i].length),
2711#endif
2712 le32_to_cpu(vp->tx_ring[i].status));
2713 }
2714 if (!stalled)
62afe595 2715 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2716 }
2717 }
2718}
2719
2720static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2721{
2722 struct vortex_private *vp = netdev_priv(dev);
62afe595 2723 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2724 unsigned long flags;
2725
2726 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2727 spin_lock_irqsave (&vp->lock, flags);
62afe595 2728 update_stats(ioaddr, dev);
1da177e4
LT		 2729 spin_unlock_irqrestore (&vp->lock, flags);
2730 }
2731 return &vp->stats;
2732}
2733
2734/* Update statistics.
2735 Unlike with the EL3 we need not worry about interrupts changing
2736 the window setting from underneath us, but we must still guard
2737 against a race condition with a StatsUpdate interrupt updating the
2738 table. This is done by checking that the ASM (!) code generated uses
2739 atomic updates with '+='.
2740 */
62afe595 2741static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2742{
2743 struct vortex_private *vp = netdev_priv(dev);
62afe595 2744 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2745
2746 if (old_window == 0xffff) /* Chip suspended or ejected. */
2747 return;
2748 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2749 /* Switch to the stats window, and read everything. */
2750 EL3WINDOW(6);
62afe595
JL		 2751 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2752 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2753 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2754 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2755 vp->stats.tx_packets += ioread8(ioaddr + 6);
2756 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2757 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2758 /* Don't bother with register 9, an extension of registers 6&7.
2759 If we do use the 6&7 values the atomic update assumption above
2760 is invalid. */
62afe595
JL		 2761 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2762 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2763 /* Extra stats for get_ethtool_stats() */
62afe595 2764 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2765 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2766 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2767 EL3WINDOW(4);
62afe595 2768 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2769
8d1d0340
SK		 2770 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2771 + vp->xstats.tx_single_collisions
2772 + vp->xstats.tx_max_collisions;
2773
1da177e4 2774 {
62afe595 2775 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2776 vp->stats.rx_bytes += (up & 0x0f) << 16;
2777 vp->stats.tx_bytes += (up & 0xf0) << 12;
2778 }
2779
2780 EL3WINDOW(old_window >> 13);
2781 return;
2782}
2783
2784static int vortex_nway_reset(struct net_device *dev)
2785{
2786 struct vortex_private *vp = netdev_priv(dev);
62afe595 2787 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2788 unsigned long flags;
2789 int rc;
2790
2791 spin_lock_irqsave(&vp->lock, flags);
2792 EL3WINDOW(4);
2793 rc = mii_nway_restart(&vp->mii);
2794 spin_unlock_irqrestore(&vp->lock, flags);
2795 return rc;
2796}
2797
1da177e4
LT		 2798static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2799{
2800 struct vortex_private *vp = netdev_priv(dev);
62afe595 2801 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2802 unsigned long flags;
2803 int rc;
2804
2805 spin_lock_irqsave(&vp->lock, flags);
2806 EL3WINDOW(4);
2807 rc = mii_ethtool_gset(&vp->mii, cmd);
2808 spin_unlock_irqrestore(&vp->lock, flags);
2809 return rc;
2810}
2811
2812static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2813{
2814 struct vortex_private *vp = netdev_priv(dev);
62afe595 2815 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2816 unsigned long flags;
2817 int rc;
2818
2819 spin_lock_irqsave(&vp->lock, flags);
2820 EL3WINDOW(4);
2821 rc = mii_ethtool_sset(&vp->mii, cmd);
2822 spin_unlock_irqrestore(&vp->lock, flags);
2823 return rc;
2824}
2825
2826static u32 vortex_get_msglevel(struct net_device *dev)
2827{
2828 return vortex_debug;
2829}
2830
2831static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2832{
2833 vortex_debug = dbg;
2834}
2835
b9f2c044 2836static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2837{
b9f2c044
JG		 2838 switch (sset) {
2839 case ETH_SS_STATS:
2840 return VORTEX_NUM_STATS;
2841 default:
2842 return -EOPNOTSUPP;
2843 }
1da177e4
LT		 2844}
2845
2846static void vortex_get_ethtool_stats(struct net_device *dev,
2847 struct ethtool_stats *stats, u64 *data)
2848{
2849 struct vortex_private *vp = netdev_priv(dev);
62afe595 2850 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2851 unsigned long flags;
2852
2853 spin_lock_irqsave(&vp->lock, flags);
62afe595 2854 update_stats(ioaddr, dev);
1da177e4
LT		 2855 spin_unlock_irqrestore(&vp->lock, flags);
2856
2857 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2858 data[1] = vp->xstats.tx_max_collisions;
2859 data[2] = vp->xstats.tx_multiple_collisions;
2860 data[3] = vp->xstats.tx_single_collisions;
2861 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2862}
2863
2864
2865static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2866{
2867 switch (stringset) {
2868 case ETH_SS_STATS:
2869 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2870 break;
2871 default:
2872 WARN_ON(1);
2873 break;
2874 }
2875}
2876
2877static void vortex_get_drvinfo(struct net_device *dev,
2878 struct ethtool_drvinfo *info)
2879{
2880 struct vortex_private *vp = netdev_priv(dev);
2881
2882 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2883 if (VORTEX_PCI(vp)) {
2884 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2885 } else {
2886 if (VORTEX_EISA(vp))
2887 sprintf(info->bus_info, vp->gendev->bus_id);
2888 else
2889 sprintf(info->bus_info, "EISA 0x%lx %d",
2890 dev->base_addr, dev->irq);
2891 }
2892}
2893
7282d491 2894static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2895 .get_drvinfo = vortex_get_drvinfo,
2896 .get_strings = vortex_get_strings,
2897 .get_msglevel = vortex_get_msglevel,
2898 .set_msglevel = vortex_set_msglevel,
2899 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2900 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2901 .get_settings = vortex_get_settings,
2902 .set_settings = vortex_set_settings,
373a6887 2903 .get_link = ethtool_op_get_link,
1da177e4
LT		 2904 .nway_reset = vortex_nway_reset,
2905};
2906
2907#ifdef CONFIG_PCI
2908/*
2909 * Must power the device up to do MDIO operations
2910 */
2911static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2912{
2913 int err;
2914 struct vortex_private *vp = netdev_priv(dev);
62afe595 2915 void __iomem *ioaddr = vp->ioaddr;
1da177e4 2916 unsigned long flags;
cc2d6596 2917 pci_power_t state = 0;
1da177e4
LT		 2918
2919 if(VORTEX_PCI(vp))
2920 state = VORTEX_PCI(vp)->current_state;
2921
2922 /* The kernel core really should have pci_get_power_state() */
2923
2924 if(state != 0)
2925 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2926 spin_lock_irqsave(&vp->lock, flags);
2927 EL3WINDOW(4);
2928 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2929 spin_unlock_irqrestore(&vp->lock, flags);
2930 if(state != 0)
2931 pci_set_power_state(VORTEX_PCI(vp), state);
2932
2933 return err;
2934}
2935#endif
2936
2937
2938/* Pre-Cyclone chips have no documented multicast filter, so the only
2939 multicast setting is to receive all multicast frames. At least
2940 the chip has a very clean way to set the mode, unlike many others. */
2941static void set_rx_mode(struct net_device *dev)
2942{
62afe595
JL		 2943 struct vortex_private *vp = netdev_priv(dev);
2944 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2945 int new_mode;
2946
2947 if (dev->flags & IFF_PROMISC) {
d5b20697 2948 if (vortex_debug > 3)
1da177e4
LT		 2949 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2950 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2951 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2952 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2953 } else
2954 new_mode = SetRxFilter | RxStation | RxBroadcast;
2955
62afe595 2956 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2957}
2958
2959#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2960/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2961 Note that this must be done after each RxReset due to some backwards
2962 compatibility logic in the Cyclone and Tornado ASICs */
2963
2964/* The Ethernet Type used for 802.1q tagged frames */
2965#define VLAN_ETHER_TYPE 0x8100
2966
2967static void set_8021q_mode(struct net_device *dev, int enable)
2968{
2969 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2970 void __iomem *ioaddr = vp->ioaddr;
2971 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2972 int mac_ctrl;
2973
2974 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2975 /* cyclone and tornado chipsets can recognize 802.1q
2976 * tagged frames and treat them correctly */
2977
2978 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2979 if (enable)
2980 max_pkt_size += 4; /* 802.1Q VLAN tag */
2981
2982 EL3WINDOW(3);
62afe595 2983 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 2984
2985 /* set VlanEtherType to let the hardware checksumming
2986 treat tagged frames correctly */
2987 EL3WINDOW(7);
62afe595 2988 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 2989 } else {
2990 /* on older cards we have to enable large frames */
2991
2992 vp->large_frames = dev->mtu > 1500 || enable;
2993
2994 EL3WINDOW(3);
62afe595 2995 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2996 if (vp->large_frames)
2997 mac_ctrl |= 0x40;
2998 else
2999 mac_ctrl &= ~0x40;
62afe595 3000 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3001 }
3002
3003 EL3WINDOW(old_window);
3004}
3005#else
3006
3007static void set_8021q_mode(struct net_device *dev, int enable)
3008{
3009}
3010
3011
3012#endif
3013
3014/* MII transceiver control section.
3015 Read and write the MII registers using software-generated serial
3016 MDIO protocol. See the MII specifications or DP83840A data sheet
3017 for details. */
3018
3019/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3020 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3021 "overclocking" issues. */
62afe595 3022#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3023
3024#define MDIO_SHIFT_CLK 0x01
3025#define MDIO_DIR_WRITE 0x04
3026#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3027#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3028#define MDIO_DATA_READ 0x02
3029#define MDIO_ENB_IN 0x00
3030
3031/* Generate the preamble required for initial synchronization and
3032 a few older transceivers. */
62afe595 3033static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3034{
62afe595 3035 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3036
3037 /* Establish sync by sending at least 32 logic ones. */
3038 while (-- bits >= 0) {
62afe595 3039 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3040 mdio_delay();
62afe595 3041 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3042 mdio_delay();
3043 }
3044}
3045
3046static int mdio_read(struct net_device *dev, int phy_id, int location)
3047{
3048 int i;
62afe595
JL		 3049 struct vortex_private *vp = netdev_priv(dev);
3050 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3051 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3052 unsigned int retval = 0;
62afe595 3053 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3054
3055 if (mii_preamble_required)
3056 mdio_sync(ioaddr, 32);
3057
3058 /* Shift the read command bits out. */
3059 for (i = 14; i >= 0; i--) {
3060 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3061 iowrite16(dataval, mdio_addr);
1da177e4 3062 mdio_delay();
62afe595 3063 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3064 mdio_delay();
3065 }
3066 /* Read the two transition, 16 data, and wire-idle bits. */
3067 for (i = 19; i > 0; i--) {
62afe595 3068 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3069 mdio_delay();
62afe595
JL		 3070 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3071 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3072 mdio_delay();
3073 }
3074 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3075}
3076
3077static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3078{
62afe595
JL		 3079 struct vortex_private *vp = netdev_priv(dev);
3080 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3081 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3082 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3083 int i;
3084
3085 if (mii_preamble_required)
3086 mdio_sync(ioaddr, 32);
3087
3088 /* Shift the command bits out. */
3089 for (i = 31; i >= 0; i--) {
3090 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3091 iowrite16(dataval, mdio_addr);
1da177e4 3092 mdio_delay();
62afe595 3093 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3094 mdio_delay();
3095 }
3096 /* Leave the interface idle. */
3097 for (i = 1; i >= 0; i--) {
62afe595 3098 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3099 mdio_delay();
62afe595 3100 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3101 mdio_delay();
3102 }
3103 return;
3104}
a880c4cd 3105
1da177e4
LT		 3106/* ACPI: Advanced Configuration and Power Interface. */
3107/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3108static void acpi_set_WOL(struct net_device *dev)
3109{
3110 struct vortex_private *vp = netdev_priv(dev);
62afe595 3111 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3112
3113 if (vp->enable_wol) {
3114 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3115 EL3WINDOW(7);
62afe595 3116 iowrite16(2, ioaddr + 0x0c);
1da177e4 3117 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3118 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3119 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3120
1a1769f3
SK		 3121 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3122 printk(KERN_INFO "%s: WOL not supported.\n",
3123 pci_name(VORTEX_PCI(vp)));
3124
3125 vp->enable_wol = 0;
3126 return;
3127 }
3c8fad18
DR		 3128
3129 /* Change the power state to D3; RxEnable doesn't take effect. */
3130 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3131 }
1da177e4
LT		 3132}
3133
3134
a880c4cd 3135static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3136{
3137 struct net_device *dev = pci_get_drvdata(pdev);
3138 struct vortex_private *vp;
3139
3140 if (!dev) {
3141 printk("vortex_remove_one called for Compaq device!\n");
3142 BUG();
3143 }
3144
3145 vp = netdev_priv(dev);
3146
62afe595
JL		 3147 if (vp->cb_fn_base)
3148 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3149
1da177e4
LT		 3150 unregister_netdev(dev);
3151
3152 if (VORTEX_PCI(vp)) {
3153 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3154 if (vp->pm_state_valid)
3155 pci_restore_state(VORTEX_PCI(vp));
3156 pci_disable_device(VORTEX_PCI(vp));
3157 }
3158 /* Should really use issue_and_wait() here */
62afe595
JL		 3159 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3160 vp->ioaddr + EL3_CMD);
3161
3162 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3163
3164 pci_free_consistent(pdev,
3165 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3166 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3167 vp->rx_ring,
3168 vp->rx_ring_dma);
3169 if (vp->must_free_region)
3170 release_region(dev->base_addr, vp->io_size);
3171 free_netdev(dev);
3172}
3173
3174
3175static struct pci_driver vortex_driver = {
3176 .name = "3c59x",
3177 .probe = vortex_init_one,
3178 .remove = __devexit_p(vortex_remove_one),
3179 .id_table = vortex_pci_tbl,
3180#ifdef CONFIG_PM
3181 .suspend = vortex_suspend,
3182 .resume = vortex_resume,
3183#endif
3184};
3185
3186
3187static int vortex_have_pci;
3188static int vortex_have_eisa;
3189
3190
a880c4cd 3191static int __init vortex_init(void)
1da177e4
LT		 3192{
3193 int pci_rc, eisa_rc;
3194
29917620 3195 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3196 eisa_rc = vortex_eisa_init();
3197
3198 if (pci_rc == 0)
3199 vortex_have_pci = 1;
3200 if (eisa_rc > 0)
3201 vortex_have_eisa = 1;
3202
3203 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3204}
3205
3206
a880c4cd 3207static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3208{
3209 struct vortex_private *vp;
62afe595 3210 void __iomem *ioaddr;
1da177e4
LT		 3211
3212#ifdef CONFIG_EISA
3213 /* Take care of the EISA devices */
a880c4cd 3214 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3215#endif
6aa20a22 3216
1da177e4
LT		 3217 if (compaq_net_device) {
3218 vp = compaq_net_device->priv;
62afe595
JL		 3219 ioaddr = ioport_map(compaq_net_device->base_addr,
3220 VORTEX_TOTAL_SIZE);
1da177e4 3221
a880c4cd
SK		 3222 unregister_netdev(compaq_net_device);
3223 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3224 release_region(compaq_net_device->base_addr,
3225 VORTEX_TOTAL_SIZE);
1da177e4 3226
a880c4cd 3227 free_netdev(compaq_net_device);
1da177e4
LT		 3228 }
3229}
3230
3231
a880c4cd 3232static void __exit vortex_cleanup(void)
1da177e4
LT		 3233{
3234 if (vortex_have_pci)
a880c4cd 3235 pci_unregister_driver(&vortex_driver);
1da177e4 3236 if (vortex_have_eisa)
a880c4cd 3237 vortex_eisa_cleanup();
1da177e4
LT		 3238}
3239
3240
3241module_init(vortex_init);
3242module_exit(vortex_cleanup);
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