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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
1da177e4
LT		 80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
ff5688ae 91#include <linux/jiffies.h>
5a0e3ad6 92#include <linux/gfp.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
86de79b6
SH		 105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
a3aa1884 378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
1da177e4
LT		 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
1da177e4
LT		 438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
cc2d6596
AV		 544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
cc2d6596
AV		 564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 566#if DO_ZEROCOPY
567 struct {
cc2d6596
AV		 568 __le32 addr;
569 __le32 length;
1da177e4
LT		 570 } frag[1+MAX_SKB_FRAGS];
571#else
cc2d6596
AV		 572 __le32 addr;
573 __le32 length;
1da177e4
LT		 574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
8d1d0340
SK		 588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
1da177e4
LT		 593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
62afe595
JL		 612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 625 full_duplex:1, autoselect:1,
1da177e4
LT		 626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1; /* accept large frames */
637 int drv_flags;
638 u16 status_enable;
639 u16 intr_enable;
640 u16 available_media; /* From Wn3_Options. */
641 u16 capabilities, info1, info2; /* Various, from EEPROM. */
642 u16 advertising; /* NWay media advertisement */
643 unsigned char phys[2]; /* MII device addresses. */
644 u16 deferred; /* Resend these interrupts when we
645 * bale from the ISR */
646 u16 io_size; /* Size of PCI region (for release_region) */
de847272
BH		 647
648 /* Serialises access to hardware other than MII and variables below.
649 * The lock hierarchy is rtnl_lock > lock > mii_lock > window_lock. */
650 spinlock_t lock;
651
652 spinlock_t mii_lock; /* Serialises access to MII */
653 struct mii_if_info mii; /* MII lib hooks/info */
654 spinlock_t window_lock; /* Serialises access to windowed regs */
655 int window; /* Register window */
1da177e4
LT		 656};
657
a095cfc4
BH		 658static void window_set(struct vortex_private *vp, int window)
659{
660 if (window != vp->window) {
661 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
662 vp->window = window;
663 }
664}
665
666#define DEFINE_WINDOW_IO(size) \
667static u ## size \
668window_read ## size(struct vortex_private *vp, int window, int addr) \
669{ \
de847272
BH		 670 unsigned long flags; \
671 u ## size ret; \
672 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4 673 window_set(vp, window); \
de847272
BH		 674 ret = ioread ## size(vp->ioaddr + addr); \
675 spin_unlock_irqrestore(&vp->window_lock, flags); \
676 return ret; \
a095cfc4
BH		 677} \
678static void \
679window_write ## size(struct vortex_private *vp, u ## size value, \
680 int window, int addr) \
681{ \
de847272
BH		 682 unsigned long flags; \
683 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4
BH		 684 window_set(vp, window); \
685 iowrite ## size(value, vp->ioaddr + addr); \
de847272 686 spin_unlock_irqrestore(&vp->window_lock, flags); \
a095cfc4
BH		 687}
688DEFINE_WINDOW_IO(8)
689DEFINE_WINDOW_IO(16)
690DEFINE_WINDOW_IO(32)
691
1da177e4
LT		 692#ifdef CONFIG_PCI
693#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
694#else
695#define DEVICE_PCI(dev) NULL
696#endif
697
698#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
699
700#ifdef CONFIG_EISA
701#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
702#else
703#define DEVICE_EISA(dev) NULL
704#endif
705
706#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
707
708/* The action to take with a media selection timer tick.
709 Note that we deviate from the 3Com order by checking 10base2 before AUI.
710 */
711enum xcvr_types {
712 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
713 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
714};
715
f71e1309 716static const struct media_table {
1da177e4
LT		 717 char *name;
718 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
719 mask:8, /* The transceiver-present bit in Wn3_Config.*/
720 next:8; /* The media type to try next. */
721 int wait; /* Time before we check media status. */
722} media_tbl[] = {
723 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
724 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
725 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
726 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
727 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
728 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
729 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
730 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
731 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
732 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
733 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
734};
735
736static struct {
737 const char str[ETH_GSTRING_LEN];
738} ethtool_stats_keys[] = {
739 { "tx_deferred" },
8d1d0340 740 { "tx_max_collisions" },
1da177e4 741 { "tx_multiple_collisions" },
8d1d0340 742 { "tx_single_collisions" },
1da177e4
LT		 743 { "rx_bad_ssd" },
744};
745
746/* number of ETHTOOL_GSTATS u64's */
8d1d0340 747#define VORTEX_NUM_STATS 5
1da177e4 748
62afe595 749static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 750 int chip_idx, int card_idx);
c8303d10 751static int vortex_up(struct net_device *dev);
1da177e4
LT		 752static void vortex_down(struct net_device *dev, int final);
753static int vortex_open(struct net_device *dev);
a095cfc4 754static void mdio_sync(struct vortex_private *vp, int bits);
1da177e4
LT		 755static int mdio_read(struct net_device *dev, int phy_id, int location);
756static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
757static void vortex_timer(unsigned long arg);
758static void rx_oom_timer(unsigned long arg);
27a1de95
SH		 759static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
760 struct net_device *dev);
761static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
762 struct net_device *dev);
1da177e4
LT		 763static int vortex_rx(struct net_device *dev);
764static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 765static irqreturn_t vortex_interrupt(int irq, void *dev_id);
766static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 767static int vortex_close(struct net_device *dev);
768static void dump_tx_ring(struct net_device *dev);
62afe595 769static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 770static struct net_device_stats *vortex_get_stats(struct net_device *dev);
771static void set_rx_mode(struct net_device *dev);
772#ifdef CONFIG_PCI
773static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
774#endif
775static void vortex_tx_timeout(struct net_device *dev);
776static void acpi_set_WOL(struct net_device *dev);
7282d491 777static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 778static void set_8021q_mode(struct net_device *dev, int enable);
779
1da177e4
LT		 780/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
781/* Option count limit only -- unlimited interfaces are supported. */
782#define MAX_UNITS 8
9954ab7f
JL		 783static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
784static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
785static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
786static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
787static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 788static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 789static int global_options = -1;
790static int global_full_duplex = -1;
791static int global_enable_wol = -1;
900fd17d 792static int global_use_mmio = -1;
1da177e4 793
1da177e4
LT		 794/* Variables to work-around the Compaq PCI BIOS32 problem. */
795static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
796static struct net_device *compaq_net_device;
797
798static int vortex_cards_found;
799
800module_param(debug, int, 0);
801module_param(global_options, int, 0);
802module_param_array(options, int, NULL, 0);
803module_param(global_full_duplex, int, 0);
804module_param_array(full_duplex, int, NULL, 0);
805module_param_array(hw_checksums, int, NULL, 0);
806module_param_array(flow_ctrl, int, NULL, 0);
807module_param(global_enable_wol, int, 0);
808module_param_array(enable_wol, int, NULL, 0);
809module_param(rx_copybreak, int, 0);
810module_param(max_interrupt_work, int, 0);
811module_param(compaq_ioaddr, int, 0);
812module_param(compaq_irq, int, 0);
813module_param(compaq_device_id, int, 0);
814module_param(watchdog, int, 0);
900fd17d
JL		 815module_param(global_use_mmio, int, 0);
816module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 817MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
818MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
819MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
820MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 821MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 822MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
823MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
824MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 825MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 826MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
827MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
828MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
829MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
830MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
831MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 832MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
833MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 834
835#ifdef CONFIG_NET_POLL_CONTROLLER
836static void poll_vortex(struct net_device *dev)
837{
838 struct vortex_private *vp = netdev_priv(dev);
839 unsigned long flags;
0d38ff1d 840 local_irq_save(flags);
7d12e780 841 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 842 local_irq_restore(flags);
6aa20a22 843}
1da177e4
LT		 844#endif
845
846#ifdef CONFIG_PM
847
7bfc4ab5 848static int vortex_suspend(struct device *dev)
1da177e4 849{
7bfc4ab5
AV		 850 struct pci_dev *pdev = to_pci_dev(dev);
851 struct net_device *ndev = pci_get_drvdata(pdev);
852
853 if (!ndev || !netif_running(ndev))
854 return 0;
855
856 netif_device_detach(ndev);
857 vortex_down(ndev, 1);
1da177e4 858
1da177e4
LT		 859 return 0;
860}
861
7bfc4ab5 862static int vortex_resume(struct device *dev)
1da177e4 863{
7bfc4ab5
AV		 864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct net_device *ndev = pci_get_drvdata(pdev);
e1265153 866 int err;
1da177e4 867
7bfc4ab5
AV		 868 if (!ndev || !netif_running(ndev))
869 return 0;
870
871 err = vortex_up(ndev);
872 if (err)
873 return err;
874
875 netif_device_attach(ndev);
876
1da177e4
LT		 877 return 0;
878}
879
47145210 880static const struct dev_pm_ops vortex_pm_ops = {
7bfc4ab5
AV		 881 .suspend = vortex_suspend,
882 .resume = vortex_resume,
883 .freeze = vortex_suspend,
884 .thaw = vortex_resume,
885 .poweroff = vortex_suspend,
886 .restore = vortex_resume,
887};
888
889#define VORTEX_PM_OPS (&vortex_pm_ops)
890
891#else /* !CONFIG_PM */
892
893#define VORTEX_PM_OPS NULL
894
895#endif /* !CONFIG_PM */
1da177e4
LT		 896
897#ifdef CONFIG_EISA
898static struct eisa_device_id vortex_eisa_ids[] = {
899 { "TCM5920", CH_3C592 },
900 { "TCM5970", CH_3C597 },
901 { "" }
902};
07563c71 903MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 904
95c408a9 905static int __init vortex_eisa_probe(struct device *device)
1da177e4 906{
62afe595 907 void __iomem *ioaddr;
1da177e4
LT		 908 struct eisa_device *edev;
909
a880c4cd 910 edev = to_eisa_device(device);
1da177e4 911
62afe595 912 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 913 return -EBUSY;
914
62afe595
JL		 915 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
916
917 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 918 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 919 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 920 return -ENODEV;
921 }
922
923 vortex_cards_found++;
924
925 return 0;
926}
927
95c408a9 928static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 929{
930 struct eisa_device *edev;
931 struct net_device *dev;
932 struct vortex_private *vp;
62afe595 933 void __iomem *ioaddr;
1da177e4 934
a880c4cd
SK		 935 edev = to_eisa_device(device);
936 dev = eisa_get_drvdata(edev);
1da177e4
LT		 937
938 if (!dev) {
39738e16 939 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 940 BUG();
941 }
942
943 vp = netdev_priv(dev);
62afe595 944 ioaddr = vp->ioaddr;
6aa20a22 945
a880c4cd
SK		 946 unregister_netdev(dev);
947 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
948 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 949
a880c4cd 950 free_netdev(dev);
1da177e4
LT		 951 return 0;
952}
95c408a9
RB		 953
954static struct eisa_driver vortex_eisa_driver = {
955 .id_table = vortex_eisa_ids,
956 .driver = {
957 .name = "3c59x",
958 .probe = vortex_eisa_probe,
959 .remove = __devexit_p(vortex_eisa_remove)
960 }
961};
962
963#endif /* CONFIG_EISA */
1da177e4
LT		 964
965/* returns count found (>= 0), or negative on error */
a880c4cd 966static int __init vortex_eisa_init(void)
1da177e4
LT		 967{
968 int eisa_found = 0;
969 int orig_cards_found = vortex_cards_found;
970
971#ifdef CONFIG_EISA
c2f6fabb
BH		 972 int err;
973
974 err = eisa_driver_register (&vortex_eisa_driver);
975 if (!err) {
976 /*
977 * Because of the way EISA bus is probed, we cannot assume
978 * any device have been found when we exit from
979 * eisa_driver_register (the bus root driver may not be
980 * initialized yet). So we blindly assume something was
981 * found, and let the sysfs magic happend...
982 */
983 eisa_found = 1;
1da177e4
LT		 984 }
985#endif
6aa20a22 986
1da177e4
LT		 987 /* Special code to work-around the Compaq PCI BIOS32 problem. */
988 if (compaq_ioaddr) {
62afe595
JL		 989 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
990 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 991 }
992
993 return vortex_cards_found - orig_cards_found + eisa_found;
994}
995
996/* returns count (>= 0), or negative on error */
a880c4cd 997static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 998 const struct pci_device_id *ent)
999{
900fd17d
JL		 1000 int rc, unit, pci_bar;
1001 struct vortex_chip_info *vci;
1002 void __iomem *ioaddr;
1da177e4 1003
6aa20a22 1004 /* wake up and enable device */
a880c4cd 1005 rc = pci_enable_device(pdev);
1da177e4
LT		 1006 if (rc < 0)
1007 goto out;
1008
900fd17d
JL		 1009 unit = vortex_cards_found;
1010
1011 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1012 /* Determine the default if the user didn't override us */
1013 vci = &vortex_info_tbl[ent->driver_data];
1014 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1015 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1016 pci_bar = use_mmio[unit] ? 1 : 0;
1017 else
1018 pci_bar = global_use_mmio ? 1 : 0;
1019
1020 ioaddr = pci_iomap(pdev, pci_bar, 0);
1021 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1022 ioaddr = pci_iomap(pdev, 0, 0);
8cd47ea1
KV		 1023 if (!ioaddr) {
1024 pci_disable_device(pdev);
1025 rc = -ENOMEM;
1026 goto out;
1027 }
900fd17d
JL		 1028
1029 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1030 ent->driver_data, unit);
1da177e4 1031 if (rc < 0) {
a880c4cd 1032 pci_disable_device(pdev);
1da177e4
LT		 1033 goto out;
1034 }
1035
1036 vortex_cards_found++;
1037
1038out:
1039 return rc;
1040}
1041
48b47a5e
SH		 1042static const struct net_device_ops boomrang_netdev_ops = {
1043 .ndo_open = vortex_open,
1044 .ndo_stop = vortex_close,
1045 .ndo_start_xmit = boomerang_start_xmit,
1046 .ndo_tx_timeout = vortex_tx_timeout,
1047 .ndo_get_stats = vortex_get_stats,
1048#ifdef CONFIG_PCI
1049 .ndo_do_ioctl = vortex_ioctl,
1050#endif
1051 .ndo_set_multicast_list = set_rx_mode,
1052 .ndo_change_mtu = eth_change_mtu,
1053 .ndo_set_mac_address = eth_mac_addr,
1054 .ndo_validate_addr = eth_validate_addr,
1055#ifdef CONFIG_NET_POLL_CONTROLLER
1056 .ndo_poll_controller = poll_vortex,
1057#endif
1058};
1059
1060static const struct net_device_ops vortex_netdev_ops = {
1061 .ndo_open = vortex_open,
1062 .ndo_stop = vortex_close,
1063 .ndo_start_xmit = vortex_start_xmit,
1064 .ndo_tx_timeout = vortex_tx_timeout,
1065 .ndo_get_stats = vortex_get_stats,
1066#ifdef CONFIG_PCI
1067 .ndo_do_ioctl = vortex_ioctl,
1068#endif
1069 .ndo_set_multicast_list = set_rx_mode,
1070 .ndo_change_mtu = eth_change_mtu,
1071 .ndo_set_mac_address = eth_mac_addr,
1072 .ndo_validate_addr = eth_validate_addr,
1073#ifdef CONFIG_NET_POLL_CONTROLLER
1074 .ndo_poll_controller = poll_vortex,
1075#endif
1076};
1077
1da177e4
LT		 1078/*
1079 * Start up the PCI/EISA device which is described by *gendev.
1080 * Return 0 on success.
1081 *
1082 * NOTE: pdev can be NULL, for the case of a Compaq device
1083 */
1084static int __devinit vortex_probe1(struct device *gendev,
62afe595 1085 void __iomem *ioaddr, int irq,
1da177e4
LT		 1086 int chip_idx, int card_idx)
1087{
1088 struct vortex_private *vp;
1089 int option;
1090 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1091 int i, step;
1092 struct net_device *dev;
1093 static int printed_version;
1094 int retval, print_info;
1095 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1096 const char *print_name = "3c59x";
1da177e4
LT		 1097 struct pci_dev *pdev = NULL;
1098 struct eisa_device *edev = NULL;
1099
1100 if (!printed_version) {
39738e16 1101 pr_info("%s", version);
1da177e4
LT		 1102 printed_version = 1;
1103 }
1104
1105 if (gendev) {
1106 if ((pdev = DEVICE_PCI(gendev))) {
1107 print_name = pci_name(pdev);
1108 }
1109
1110 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1111 print_name = dev_name(&edev->dev);
1da177e4
LT		 1112 }
1113 }
1114
1115 dev = alloc_etherdev(sizeof(*vp));
1116 retval = -ENOMEM;
1117 if (!dev) {
39738e16 1118 pr_err(PFX "unable to allocate etherdev, aborting\n");
1da177e4
LT		 1119 goto out;
1120 }
1da177e4
LT		 1121 SET_NETDEV_DEV(dev, gendev);
1122 vp = netdev_priv(dev);
1123
1124 option = global_options;
1125
1126 /* The lower four bits are the media type. */
1127 if (dev->mem_start) {
1128 /*
1129 * The 'options' param is passed in as the third arg to the
1130 * LILO 'ether=' argument for non-modular use
1131 */
1132 option = dev->mem_start;
1133 }
1134 else if (card_idx < MAX_UNITS) {
1135 if (options[card_idx] >= 0)
1136 option = options[card_idx];
1137 }
1138
1139 if (option > 0) {
1140 if (option & 0x8000)
1141 vortex_debug = 7;
1142 if (option & 0x4000)
1143 vortex_debug = 2;
1144 if (option & 0x0400)
1145 vp->enable_wol = 1;
1146 }
1147
1148 print_info = (vortex_debug > 1);
1149 if (print_info)
39738e16 1150 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1151
39738e16 1152 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1153 print_name,
1154 pdev ? "PCI" : "EISA",
1155 vci->name,
1156 ioaddr);
1157
62afe595 1158 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1159 dev->irq = irq;
1160 dev->mtu = mtu;
62afe595 1161 vp->ioaddr = ioaddr;
1da177e4
LT		 1162 vp->large_frames = mtu > 1500;
1163 vp->drv_flags = vci->drv_flags;
1164 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1165 vp->io_size = vci->io_size;
1166 vp->card_idx = card_idx;
a095cfc4 1167 vp->window = -1;
1da177e4
LT		 1168
1169 /* module list only for Compaq device */
1170 if (gendev == NULL) {
1171 compaq_net_device = dev;
1172 }
1173
1174 /* PCI-only startup logic */
1175 if (pdev) {
1176 /* EISA resources already marked, so only PCI needs to do this here */
1177 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1178 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1179 vp->must_free_region = 1;
1180
6aa20a22 1181 /* enable bus-mastering if necessary */
1da177e4 1182 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1183 pci_set_master(pdev);
1da177e4
LT		 1184
1185 if (vci->drv_flags & IS_VORTEX) {
1186 u8 pci_latency;
1187 u8 new_latency = 248;
1188
1189 /* Check the PCI latency value. On the 3c590 series the latency timer
1190 must be set to the maximum value to avoid data corruption that occurs
1191 when the timer expires during a transfer. This bug exists the Vortex
1192 chip only. */
1193 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1194 if (pci_latency < new_latency) {
39738e16 1195 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1196 print_name, pci_latency, new_latency);
39738e16 1197 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1198 }
1199 }
1200 }
1201
1202 spin_lock_init(&vp->lock);
de847272
BH		 1203 spin_lock_init(&vp->mii_lock);
1204 spin_lock_init(&vp->window_lock);
1da177e4
LT		 1205 vp->gendev = gendev;
1206 vp->mii.dev = dev;
1207 vp->mii.mdio_read = mdio_read;
1208 vp->mii.mdio_write = mdio_write;
1209 vp->mii.phy_id_mask = 0x1f;
1210 vp->mii.reg_num_mask = 0x1f;
1211
1212 /* Makes sure rings are at least 16 byte aligned. */
1213 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1214 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1215 &vp->rx_ring_dma);
1216 retval = -ENOMEM;
cc2d6596 1217 if (!vp->rx_ring)
1da177e4
LT		 1218 goto free_region;
1219
1220 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1221 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1222
1223 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1224 * instead of a module list */
1da177e4
LT		 1225 if (pdev)
1226 pci_set_drvdata(pdev, dev);
1227 if (edev)
a880c4cd 1228 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1229
1230 vp->media_override = 7;
1231 if (option >= 0) {
1232 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1233 if (vp->media_override != 7)
1234 vp->medialock = 1;
1235 vp->full_duplex = (option & 0x200) ? 1 : 0;
1236 vp->bus_master = (option & 16) ? 1 : 0;
1237 }
1238
1239 if (global_full_duplex > 0)
1240 vp->full_duplex = 1;
1241 if (global_enable_wol > 0)
1242 vp->enable_wol = 1;
1243
1244 if (card_idx < MAX_UNITS) {
1245 if (full_duplex[card_idx] > 0)
1246 vp->full_duplex = 1;
1247 if (flow_ctrl[card_idx] > 0)
1248 vp->flow_ctrl = 1;
1249 if (enable_wol[card_idx] > 0)
1250 vp->enable_wol = 1;
1251 }
1252
125d5ce8 1253 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1254 vp->options = option;
1255 /* Read the station address from the EEPROM. */
1da177e4
LT		 1256 {
1257 int base;
1258
1259 if (vci->drv_flags & EEPROM_8BIT)
1260 base = 0x230;
1261 else if (vci->drv_flags & EEPROM_OFFSET)
1262 base = EEPROM_Read + 0x30;
1263 else
1264 base = EEPROM_Read;
1265
1266 for (i = 0; i < 0x40; i++) {
1267 int timer;
a095cfc4 1268 window_write16(vp, base + i, 0, Wn0EepromCmd);
1da177e4
LT		 1269 /* Pause for at least 162 us. for the read to take place. */
1270 for (timer = 10; timer >= 0; timer--) {
1271 udelay(162);
a095cfc4
BH		 1272 if ((window_read16(vp, 0, Wn0EepromCmd) &
1273 0x8000) == 0)
1da177e4
LT		 1274 break;
1275 }
a095cfc4 1276 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1da177e4
LT		 1277 }
1278 }
1279 for (i = 0; i < 0x18; i++)
1280 checksum ^= eeprom[i];
1281 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1282 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1283 while (i < 0x21)
1284 checksum ^= eeprom[i++];
1285 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1286 }
1287 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1288 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1289 for (i = 0; i < 3; i++)
cc2d6596 1290 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1291 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1292 if (print_info)
39738e16 1293 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1294 /* Unfortunately an all zero eeprom passes the checksum and this
1295 gets found in the wild in failure cases. Crypto is hard 8) */
1296 if (!is_valid_ether_addr(dev->dev_addr)) {
1297 retval = -EINVAL;
39738e16 1298 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1299 goto free_ring; /* With every pack */
1300 }
1da177e4 1301 for (i = 0; i < 6; i++)
a095cfc4 1302 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1303
1da177e4 1304 if (print_info)
39738e16 1305 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1306 /* Tell them about an invalid IRQ. */
60e4ad7a 1307 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1308 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1309 dev->irq);
1da177e4 1310
a095cfc4 1311 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1312 if (print_info) {
39738e16
AB		 1313 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1314 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1315 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1316 }
1317
1318
1319 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1320 unsigned short n;
1321
62afe595
JL		 1322 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1323 if (!vp->cb_fn_base) {
1da177e4 1324 retval = -ENOMEM;
62afe595 1325 goto free_ring;
1da177e4 1326 }
62afe595 1327
1da177e4 1328 if (print_info) {
39738e16 1329 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1330 print_name,
1331 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1332 vp->cb_fn_base);
1da177e4 1333 }
1da177e4 1334
a095cfc4 1335 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1336 if (vp->drv_flags & INVERT_LED_PWR)
1337 n |= 0x10;
1338 if (vp->drv_flags & INVERT_MII_PWR)
1339 n |= 0x4000;
a095cfc4 1340 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4 1341 if (vp->drv_flags & WNO_XCVR_PWR) {
a095cfc4 1342 window_write16(vp, 0x0800, 0, 0);
1da177e4
LT		 1343 }
1344 }
1345
1346 /* Extract our information from the EEPROM data. */
1347 vp->info1 = eeprom[13];
1348 vp->info2 = eeprom[15];
1349 vp->capabilities = eeprom[16];
1350
1351 if (vp->info1 & 0x8000) {
1352 vp->full_duplex = 1;
1353 if (print_info)
39738e16 1354 pr_info("Full duplex capable\n");
1da177e4
LT		 1355 }
1356
1357 {
f71e1309 1358 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4 1359 unsigned int config;
a095cfc4 1360 vp->available_media = window_read16(vp, 3, Wn3_Options);
1da177e4
LT		 1361 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1362 vp->available_media = 0x40;
a095cfc4 1363 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1364 if (print_info) {
39738e16 1365 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
a095cfc4 1366 config, window_read16(vp, 3, Wn3_Options));
39738e16 1367 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1368 8 << RAM_SIZE(config),
1369 RAM_WIDTH(config) ? "word" : "byte",
1370 ram_split[RAM_SPLIT(config)],
1371 AUTOSELECT(config) ? "autoselect/" : "",
1372 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1373 media_tbl[XCVR(config)].name);
1374 }
1375 vp->default_media = XCVR(config);
1376 if (vp->default_media == XCVR_NWAY)
1377 vp->has_nway = 1;
1378 vp->autoselect = AUTOSELECT(config);
1379 }
1380
1381 if (vp->media_override != 7) {
39738e16 1382 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1383 print_name, vp->media_override,
1384 media_tbl[vp->media_override].name);
1385 dev->if_port = vp->media_override;
1386 } else
1387 dev->if_port = vp->default_media;
1388
1389 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1390 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1391 int phy, phy_idx = 0;
1da177e4
LT		 1392 mii_preamble_required++;
1393 if (vp->drv_flags & EXTRA_PREAMBLE)
1394 mii_preamble_required++;
1395 mdio_sync(ioaddr, 32);
106427e6 1396 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1397 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1398 int mii_status, phyx;
1399
1400 /*
1401 * For the 3c905CX we look at index 24 first, because it bogusly
1402 * reports an external PHY at all indices
1403 */
1404 if (phy == 0)
1405 phyx = 24;
1406 else if (phy <= 24)
1407 phyx = phy - 1;
1408 else
1409 phyx = phy;
106427e6 1410 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1411 if (mii_status && mii_status != 0xffff) {
1412 vp->phys[phy_idx++] = phyx;
1413 if (print_info) {
39738e16
AB		 1414 pr_info(" MII transceiver found at address %d, status %4x.\n",
1415 phyx, mii_status);
1da177e4
LT		 1416 }
1417 if ((mii_status & 0x0040) == 0)
1418 mii_preamble_required++;
1419 }
1420 }
1421 mii_preamble_required--;
1422 if (phy_idx == 0) {
39738e16 1423 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1424 vp->phys[0] = 24;
1425 } else {
106427e6 1426 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1427 if (vp->full_duplex) {
1428 /* Only advertise the FD media types. */
1429 vp->advertising &= ~0x02A0;
1430 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1431 }
1432 }
1433 vp->mii.phy_id = vp->phys[0];
1434 }
1435
1436 if (vp->capabilities & CapBusMaster) {
1437 vp->full_bus_master_tx = 1;
1438 if (print_info) {
39738e16 1439 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1440 (vp->info2 & 1) ? "early" : "whole-frame" );
1441 }
1442 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1443 vp->bus_master = 0; /* AKPM: vortex only */
1444 }
1445
1446 /* The 3c59x-specific entries in the device structure. */
1da177e4 1447 if (vp->full_bus_master_tx) {
48b47a5e 1448 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1449 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1450 if (card_idx < MAX_UNITS &&
1451 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1452 hw_checksums[card_idx] == 1)) {
d311b0d3 1453 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1454 }
48b47a5e
SH		 1455 } else
1456 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1457
1458 if (print_info) {
39738e16 1459 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1460 print_name,
1461 (dev->features & NETIF_F_SG) ? "en":"dis",
1462 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1463 }
1464
1da177e4 1465 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1466 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1467
1da177e4
LT		 1468 if (pdev) {
1469 vp->pm_state_valid = 1;
1470 pci_save_state(VORTEX_PCI(vp));
1471 acpi_set_WOL(dev);
1472 }
1473 retval = register_netdev(dev);
1474 if (retval == 0)
1475 return 0;
1476
1477free_ring:
1478 pci_free_consistent(pdev,
1479 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1480 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1481 vp->rx_ring,
1482 vp->rx_ring_dma);
1483free_region:
1484 if (vp->must_free_region)
62afe595 1485 release_region(dev->base_addr, vci->io_size);
1da177e4 1486 free_netdev(dev);
39738e16 1487 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1488out:
1489 return retval;
1490}
1491
1492static void
1493issue_and_wait(struct net_device *dev, int cmd)
1494{
62afe595
JL		 1495 struct vortex_private *vp = netdev_priv(dev);
1496 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1497 int i;
1498
62afe595 1499 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1500 for (i = 0; i < 2000; i++) {
62afe595 1501 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1502 return;
1503 }
1504
1505 /* OK, that didn't work. Do it the slow way. One second */
1506 for (i = 0; i < 100000; i++) {
62afe595 1507 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1508 if (vortex_debug > 1)
39738e16 1509 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1510 dev->name, cmd, i * 10);
1511 return;
1512 }
1513 udelay(10);
1514 }
39738e16 1515 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1516 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1517}
1518
125d5ce8
SK		 1519static void
1520vortex_set_duplex(struct net_device *dev)
1521{
1522 struct vortex_private *vp = netdev_priv(dev);
125d5ce8 1523
39738e16 1524 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1525 dev->name, (vp->full_duplex) ? "full" : "half");
1526
125d5ce8 1527 /* Set the full-duplex bit. */
a095cfc4
BH		 1528 window_write16(vp,
1529 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1530 (vp->large_frames ? 0x40 : 0) |
1531 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1532 0x100 : 0),
1533 3, Wn3_MAC_Ctrl);
125d5ce8
SK		 1534}
1535
1536static void vortex_check_media(struct net_device *dev, unsigned int init)
1537{
1538 struct vortex_private *vp = netdev_priv(dev);
1539 unsigned int ok_to_print = 0;
1540
1541 if (vortex_debug > 3)
1542 ok_to_print = 1;
1543
1544 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1545 vp->full_duplex = vp->mii.full_duplex;
1546 vortex_set_duplex(dev);
1547 } else if (init) {
1548 vortex_set_duplex(dev);
1549 }
1550}
1551
c8303d10 1552static int
1da177e4
LT		 1553vortex_up(struct net_device *dev)
1554{
1da177e4 1555 struct vortex_private *vp = netdev_priv(dev);
62afe595 1556 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1557 unsigned int config;
0280f9f9 1558 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1559
1560 if (VORTEX_PCI(vp)) {
1561 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1562 if (vp->pm_state_valid)
1563 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1564 err = pci_enable_device(VORTEX_PCI(vp));
1565 if (err) {
39738e16 1566 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1567 dev->name);
1568 goto err_out;
1569 }
1da177e4
LT		 1570 }
1571
1572 /* Before initializing select the active media port. */
a095cfc4 1573 config = window_read32(vp, 3, Wn3_Config);
1da177e4
LT		 1574
1575 if (vp->media_override != 7) {
39738e16 1576 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1577 dev->name, vp->media_override,
1578 media_tbl[vp->media_override].name);
1579 dev->if_port = vp->media_override;
1580 } else if (vp->autoselect) {
1581 if (vp->has_nway) {
1582 if (vortex_debug > 1)
39738e16 1583 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1584 dev->name, dev->if_port);
1585 dev->if_port = XCVR_NWAY;
1586 } else {
1587 /* Find first available media type, starting with 100baseTx. */
1588 dev->if_port = XCVR_100baseTx;
1589 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1590 dev->if_port = media_tbl[dev->if_port].next;
1591 if (vortex_debug > 1)
39738e16 1592 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1593 dev->name, media_tbl[dev->if_port].name);
1594 }
1595 } else {
1596 dev->if_port = vp->default_media;
1597 if (vortex_debug > 1)
39738e16 1598 pr_info("%s: using default media %s\n",
1da177e4
LT		 1599 dev->name, media_tbl[dev->if_port].name);
1600 }
1601
1602 init_timer(&vp->timer);
1603 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1604 vp->timer.data = (unsigned long)dev;
1605 vp->timer.function = vortex_timer; /* timer handler */
1606 add_timer(&vp->timer);
1607
1608 init_timer(&vp->rx_oom_timer);
1609 vp->rx_oom_timer.data = (unsigned long)dev;
1610 vp->rx_oom_timer.function = rx_oom_timer;
1611
1612 if (vortex_debug > 1)
39738e16 1613 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1614 dev->name, media_tbl[dev->if_port].name);
1615
125d5ce8 1616 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1617 config = BFINS(config, dev->if_port, 20, 4);
1618 if (vortex_debug > 6)
39738e16 1619 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
a095cfc4 1620 window_write32(vp, config, 3, Wn3_Config);
1da177e4
LT		 1621
1622 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
09ce3512
SK		 1623 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1624 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1625 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1626 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1627
125d5ce8 1628 vortex_check_media(dev, 1);
1da177e4 1629 }
125d5ce8
SK		 1630 else
1631 vortex_set_duplex(dev);
1da177e4 1632
09ce3512
SK		 1633 issue_and_wait(dev, TxReset);
1634 /*
1635 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1636 */
1637 issue_and_wait(dev, RxReset|0x04);
1638
1da177e4 1639
62afe595 1640 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1641
1642 if (vortex_debug > 1) {
39738e16 1643 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
a095cfc4 1644 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1da177e4
LT		 1645 }
1646
1647 /* Set the station address and mask in window 2 each time opened. */
1da177e4 1648 for (i = 0; i < 6; i++)
a095cfc4 1649 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1650 for (; i < 12; i+=2)
a095cfc4 1651 window_write16(vp, 0, 2, i);
1da177e4
LT		 1652
1653 if (vp->cb_fn_base) {
a095cfc4 1654 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1655 if (vp->drv_flags & INVERT_LED_PWR)
1656 n |= 0x10;
1657 if (vp->drv_flags & INVERT_MII_PWR)
1658 n |= 0x4000;
a095cfc4 1659 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4
LT		 1660 }
1661
1662 if (dev->if_port == XCVR_10base2)
1663 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1664 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4 1665 if (dev->if_port != XCVR_NWAY) {
a095cfc4
BH		 1666 window_write16(vp,
1667 (window_read16(vp, 4, Wn4_Media) &
1668 ~(Media_10TP|Media_SQE)) |
1669 media_tbl[dev->if_port].media_bits,
1670 4, Wn4_Media);
1da177e4
LT		 1671 }
1672
1673 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1674 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4 1675 for (i = 0; i < 10; i++)
a095cfc4
BH		 1676 window_read8(vp, 6, i);
1677 window_read16(vp, 6, 10);
1678 window_read16(vp, 6, 12);
1da177e4 1679 /* New: On the Vortex we must also clear the BadSSD counter. */
a095cfc4 1680 window_read8(vp, 4, 12);
1da177e4 1681 /* ..and on the Boomerang we enable the extra statistics bits. */
a095cfc4 1682 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1da177e4
LT		 1683
1684 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1685 vp->cur_rx = vp->dirty_rx = 0;
1686 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1687 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1688 iowrite32(0x0020, ioaddr + PktStatus);
1689 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1690 }
1691 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1692 vp->cur_tx = vp->dirty_tx = 0;
1693 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1694 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1695 /* Clear the Rx, Tx rings. */
1696 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1697 vp->rx_ring[i].status = 0;
1698 for (i = 0; i < TX_RING_SIZE; i++)
1699 vp->tx_skbuff[i] = NULL;
62afe595 1700 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1701 }
1702 /* Set receiver mode: presumably accept b-case and phys addr only. */
1703 set_rx_mode(dev);
1704 /* enable 802.1q tagged frames */
1705 set_8021q_mode(dev, 1);
62afe595 1706 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1707
62afe595
JL		 1708 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1709 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1710 /* Allow status bits to be seen. */
1711 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1712 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1713 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1714 (vp->bus_master ? DMADone : 0);
1715 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1716 (vp->full_bus_master_rx ? 0 : RxComplete) |
1717 StatsFull | HostError | TxComplete | IntReq
1718 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1719 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1720 /* Ack all pending events, and set active indicator mask. */
62afe595 1721 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1722 ioaddr + EL3_CMD);
62afe595 1723 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1724 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1725 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1726 netif_start_queue (dev);
c8303d10
MH		 1727err_out:
1728 return err;
1da177e4
LT		 1729}
1730
1731static int
1732vortex_open(struct net_device *dev)
1733{
1734 struct vortex_private *vp = netdev_priv(dev);
1735 int i;
1736 int retval;
1737
1738 /* Use the now-standard shared IRQ implementation. */
1739 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1740 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1741 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1742 goto err;
1da177e4
LT		 1743 }
1744
1745 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1746 if (vortex_debug > 2)
39738e16 1747 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1748 for (i = 0; i < RX_RING_SIZE; i++) {
1749 struct sk_buff *skb;
1750 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1751 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1752 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1753
1754 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1755 GFP_KERNEL);
1da177e4
LT		 1756 vp->rx_skbuff[i] = skb;
1757 if (skb == NULL)
1758 break; /* Bad news! */
9a5d3414
SH		 1759
1760 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1761 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1762 }
1763 if (i != RX_RING_SIZE) {
1764 int j;
39738e16 1765 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1766 for (j = 0; j < i; j++) {
1767 if (vp->rx_skbuff[j]) {
1768 dev_kfree_skb(vp->rx_skbuff[j]);
1769 vp->rx_skbuff[j] = NULL;
1770 }
1771 }
1772 retval = -ENOMEM;
c8303d10 1773 goto err_free_irq;
1da177e4
LT		 1774 }
1775 /* Wrap the ring. */
1776 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1777 }
1778
c8303d10
MH		 1779 retval = vortex_up(dev);
1780 if (!retval)
1781 goto out;
1da177e4 1782
c8303d10 1783err_free_irq:
1da177e4 1784 free_irq(dev->irq, dev);
c8303d10 1785err:
1da177e4 1786 if (vortex_debug > 1)
39738e16 1787 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1788out:
1da177e4
LT		 1789 return retval;
1790}
1791
1792static void
1793vortex_timer(unsigned long data)
1794{
1795 struct net_device *dev = (struct net_device *)data;
1796 struct vortex_private *vp = netdev_priv(dev);
62afe595 1797 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1798 int next_tick = 60*HZ;
1799 int ok = 0;
a095cfc4 1800 int media_status;
1da177e4
LT		 1801
1802 if (vortex_debug > 2) {
39738e16 1803 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1804 dev->name, media_tbl[dev->if_port].name);
39738e16 1805 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1806 }
1807
a095cfc4 1808 media_status = window_read16(vp, 4, Wn4_Media);
1da177e4
LT		 1809 switch (dev->if_port) {
1810 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1811 if (media_status & Media_LnkBeat) {
1812 netif_carrier_on(dev);
1813 ok = 1;
1814 if (vortex_debug > 1)
39738e16 1815 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1816 dev->name, media_tbl[dev->if_port].name, media_status);
1817 } else {
1818 netif_carrier_off(dev);
1819 if (vortex_debug > 1) {
39738e16 1820 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1821 dev->name, media_tbl[dev->if_port].name, media_status);
1822 }
1823 }
1824 break;
1825 case XCVR_MII: case XCVR_NWAY:
1826 {
1da177e4 1827 ok = 1;
125d5ce8 1828 vortex_check_media(dev, 0);
1da177e4
LT		 1829 }
1830 break;
1831 default: /* Other media types handled by Tx timeouts. */
1832 if (vortex_debug > 1)
39738e16 1833 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1834 dev->name, media_tbl[dev->if_port].name, media_status);
1835 ok = 1;
1836 }
b4ff6450
SK		 1837
1838 if (!netif_carrier_ok(dev))
1839 next_tick = 5*HZ;
1840
e94d10eb
SK		 1841 if (vp->medialock)
1842 goto leave_media_alone;
1843
a880c4cd 1844 if (!ok) {
1da177e4
LT		 1845 unsigned int config;
1846
de847272
BH		 1847 spin_lock_irq(&vp->lock);
1848
1da177e4
LT		 1849 do {
1850 dev->if_port = media_tbl[dev->if_port].next;
1851 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1852 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1853 dev->if_port = vp->default_media;
1854 if (vortex_debug > 1)
39738e16 1855 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1856 dev->name, media_tbl[dev->if_port].name);
1857 } else {
1858 if (vortex_debug > 1)
39738e16 1859 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1860 dev->name, media_tbl[dev->if_port].name);
1861 next_tick = media_tbl[dev->if_port].wait;
1862 }
a095cfc4
BH		 1863 window_write16(vp,
1864 (media_status & ~(Media_10TP|Media_SQE)) |
1865 media_tbl[dev->if_port].media_bits,
1866 4, Wn4_Media);
1da177e4 1867
a095cfc4 1868 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1869 config = BFINS(config, dev->if_port, 20, 4);
a095cfc4 1870 window_write32(vp, config, 3, Wn3_Config);
1da177e4 1871
62afe595 1872 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1873 ioaddr + EL3_CMD);
1874 if (vortex_debug > 1)
39738e16 1875 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4 1876 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
de847272
BH		 1877
1878 spin_unlock_irq(&vp->lock);
1da177e4 1879 }
1da177e4
LT		 1880
1881leave_media_alone:
1882 if (vortex_debug > 2)
39738e16 1883 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1884 dev->name, media_tbl[dev->if_port].name);
1885
1886 mod_timer(&vp->timer, RUN_AT(next_tick));
1887 if (vp->deferred)
62afe595 1888 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1889}
1890
1891static void vortex_tx_timeout(struct net_device *dev)
1892{
1893 struct vortex_private *vp = netdev_priv(dev);
62afe595 1894 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1895
39738e16 1896 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1897 dev->name, ioread8(ioaddr + TxStatus),
1898 ioread16(ioaddr + EL3_STATUS));
39738e16 1899 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
a095cfc4
BH		 1900 window_read16(vp, 4, Wn4_NetDiag),
1901 window_read16(vp, 4, Wn4_Media),
62afe595 1902 ioread32(ioaddr + PktStatus),
a095cfc4 1903 window_read16(vp, 4, Wn4_FIFODiag));
1da177e4 1904 /* Slight code bloat to be user friendly. */
62afe595 1905 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1906 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1907 " network cable problem?\n", dev->name);
62afe595 1908 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1909 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1910 " IRQ blocked by another device?\n", dev->name);
1911 /* Bad idea here.. but we might as well handle a few events. */
1912 {
1913 /*
1914 * Block interrupts because vortex_interrupt does a bare spin_lock()
1915 */
1916 unsigned long flags;
1917 local_irq_save(flags);
1918 if (vp->full_bus_master_tx)
7d12e780 1919 boomerang_interrupt(dev->irq, dev);
1da177e4 1920 else
7d12e780 1921 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1922 local_irq_restore(flags);
1923 }
1924 }
1925
1926 if (vortex_debug > 0)
1927 dump_tx_ring(dev);
1928
1929 issue_and_wait(dev, TxReset);
1930
1daad055 1931 dev->stats.tx_errors++;
1da177e4 1932 if (vp->full_bus_master_tx) {
39738e16 1933 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1934 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1935 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1936 ioaddr + DownListPtr);
1937 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1938 netif_wake_queue (dev);
1939 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1940 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1941 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1942 } else {
1daad055 1943 dev->stats.tx_dropped++;
1da177e4
LT		 1944 netif_wake_queue(dev);
1945 }
6aa20a22 1946
1da177e4 1947 /* Issue Tx Enable */
62afe595 1948 iowrite16(TxEnable, ioaddr + EL3_CMD);
1ae5dc34 1949 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1950}
1951
1952/*
1953 * Handle uncommon interrupt sources. This is a separate routine to minimize
1954 * the cache impact.
1955 */
1956static void
1957vortex_error(struct net_device *dev, int status)
1958{
1959 struct vortex_private *vp = netdev_priv(dev);
62afe595 1960 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1961 int do_tx_reset = 0, reset_mask = 0;
1962 unsigned char tx_status = 0;
1963
1964 if (vortex_debug > 2) {
39738e16 1965 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1966 }
1967
1968 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1969 tx_status = ioread8(ioaddr + TxStatus);
1da177e4 1970 /* Presumably a tx-timeout. We must merely re-enable. */
8e95a202
JP		 1971 if (vortex_debug > 2 ||
1972 (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1973 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1974 dev->name, tx_status);
1975 if (tx_status == 0x82) {
39738e16 1976 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1977 "Documentation/networking/vortex.txt\n");
1978 }
1979 dump_tx_ring(dev);
1980 }
1daad055
PZ		 1981 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1982 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1983 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1984 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1985 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1986 do_tx_reset = 1;
0000754c
AM		 1987 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1988 do_tx_reset = 1;
1989 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1990 } else { /* Merely re-enable the transmitter. */
62afe595 1991 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1992 }
1993 }
1994
1995 if (status & RxEarly) { /* Rx early is unused. */
1996 vortex_rx(dev);
62afe595 1997 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1998 }
1999 if (status & StatsFull) { /* Empty statistics. */
2000 static int DoneDidThat;
2001 if (vortex_debug > 4)
39738e16 2002 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 2003 update_stats(ioaddr, dev);
2004 /* HACK: Disable statistics as an interrupt source. */
2005 /* This occurs when we have the wrong media type! */
2006 if (DoneDidThat == 0 &&
62afe595 2007 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 2008 pr_warning("%s: Updating statistics failed, disabling "
1da177e4 2009 "stats as an interrupt source.\n", dev->name);
a095cfc4
BH		 2010 iowrite16(SetIntrEnb |
2011 (window_read16(vp, 5, 10) & ~StatsFull),
2012 ioaddr + EL3_CMD);
1da177e4 2013 vp->intr_enable &= ~StatsFull;
1da177e4
LT		 2014 DoneDidThat++;
2015 }
2016 }
2017 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2018 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2019 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2020 }
2021 if (status & HostError) {
2022 u16 fifo_diag;
a095cfc4 2023 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
39738e16 2024 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2025 dev->name, fifo_diag);
2026 /* Adapter failure requires Tx/Rx reset and reinit. */
2027 if (vp->full_bus_master_tx) {
62afe595 2028 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2029 /* 0x80000000 PCI master abort. */
2030 /* 0x40000000 PCI target abort. */
2031 if (vortex_debug)
39738e16 2032 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2033
2034 /* In this case, blow the card away */
2035 /* Must not enter D3 or we can't legally issue the reset! */
2036 vortex_down(dev, 0);
2037 issue_and_wait(dev, TotalReset | 0xff);
2038 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2039 } else if (fifo_diag & 0x0400)
2040 do_tx_reset = 1;
2041 if (fifo_diag & 0x3000) {
2042 /* Reset Rx fifo and upload logic */
2043 issue_and_wait(dev, RxReset|0x07);
2044 /* Set the Rx filter to the current state. */
2045 set_rx_mode(dev);
2046 /* enable 802.1q VLAN tagged frames */
2047 set_8021q_mode(dev, 1);
62afe595
JL		 2048 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2049 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2050 }
2051 }
2052
2053 if (do_tx_reset) {
2054 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2055 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2056 if (!vp->full_bus_master_tx)
2057 netif_wake_queue(dev);
2058 }
2059}
2060
27a1de95 2061static netdev_tx_t
1da177e4
LT		 2062vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2063{
2064 struct vortex_private *vp = netdev_priv(dev);
62afe595 2065 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2066
2067 /* Put out the doubleword header... */
62afe595 2068 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2069 if (vp->bus_master) {
2070 /* Set the bus-master controller to transfer the packet. */
2071 int len = (skb->len + 3) & ~3;
a095cfc4
BH		 2072 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2073 PCI_DMA_TODEVICE);
de847272 2074 spin_lock_irq(&vp->window_lock);
a095cfc4
BH		 2075 window_set(vp, 7);
2076 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
62afe595 2077 iowrite16(len, ioaddr + Wn7_MasterLen);
de847272 2078 spin_unlock_irq(&vp->window_lock);
1da177e4 2079 vp->tx_skb = skb;
62afe595 2080 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2081 /* netif_wake_queue() will be called at the DMADone interrupt. */
2082 } else {
2083 /* ... and the packet rounded to a doubleword. */
62afe595 2084 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2085 dev_kfree_skb (skb);
62afe595 2086 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2087 netif_start_queue (dev); /* AKPM: redundant? */
2088 } else {
2089 /* Interrupt us when the FIFO has room for max-sized packet. */
2090 netif_stop_queue(dev);
62afe595 2091 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2092 }
2093 }
2094
1da177e4
LT		 2095
2096 /* Clear the Tx status stack. */
2097 {
2098 int tx_status;
2099 int i = 32;
2100
62afe595 2101 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2102 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2103 if (vortex_debug > 2)
39738e16 2104 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2105 dev->name, tx_status);
1daad055
PZ		 2106 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2107 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2108 if (tx_status & 0x30) {
2109 issue_and_wait(dev, TxReset);
2110 }
62afe595 2111 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2112 }
62afe595 2113 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2114 }
2115 }
6ed10654 2116 return NETDEV_TX_OK;
1da177e4
LT		 2117}
2118
27a1de95 2119static netdev_tx_t
1da177e4
LT		 2120boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2121{
2122 struct vortex_private *vp = netdev_priv(dev);
62afe595 2123 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2124 /* Calculate the next Tx descriptor entry. */
2125 int entry = vp->cur_tx % TX_RING_SIZE;
2126 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2127 unsigned long flags;
2128
2129 if (vortex_debug > 6) {
39738e16
AB		 2130 pr_debug("boomerang_start_xmit()\n");
2131 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2132 dev->name, vp->cur_tx);
1da177e4
LT		 2133 }
2134
2135 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2136 if (vortex_debug > 0)
39738e16 2137 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2138 dev->name);
2139 netif_stop_queue(dev);
5b548140 2140 return NETDEV_TX_BUSY;
1da177e4
LT		 2141 }
2142
2143 vp->tx_skbuff[entry] = skb;
2144
2145 vp->tx_ring[entry].next = 0;
2146#if DO_ZEROCOPY
84fa7933 2147 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2148 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2149 else
2150 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2151
2152 if (!skb_shinfo(skb)->nr_frags) {
2153 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2154 skb->len, PCI_DMA_TODEVICE));
2155 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2156 } else {
2157 int i;
2158
2159 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
e743d313
ED		 2160 skb_headlen(skb), PCI_DMA_TODEVICE));
2161 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
1da177e4
LT		 2162
2163 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2164 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2165
2166 vp->tx_ring[entry].frag[i+1].addr =
2167 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2168 (void*)page_address(frag->page) + frag->page_offset,
2169 frag->size, PCI_DMA_TODEVICE));
2170
2171 if (i == skb_shinfo(skb)->nr_frags-1)
2172 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2173 else
2174 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2175 }
2176 }
2177#else
2178 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2179 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2180 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2181#endif
2182
2183 spin_lock_irqsave(&vp->lock, flags);
2184 /* Wait for the stall to complete. */
2185 issue_and_wait(dev, DownStall);
2186 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2187 if (ioread32(ioaddr + DownListPtr) == 0) {
2188 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2189 vp->queued_packet++;
2190 }
2191
2192 vp->cur_tx++;
2193 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2194 netif_stop_queue (dev);
2195 } else { /* Clear previous interrupt enable. */
2196#if defined(tx_interrupt_mitigation)
2197 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2198 * were selected, this would corrupt DN_COMPLETE. No?
2199 */
2200 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2201#endif
2202 }
62afe595 2203 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 2204 spin_unlock_irqrestore(&vp->lock, flags);
6ed10654 2205 return NETDEV_TX_OK;
1da177e4
LT		 2206}
2207
2208/* The interrupt handler does all of the Rx thread work and cleans up
2209 after the Tx thread. */
2210
2211/*
2212 * This is the ISR for the vortex series chips.
2213 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2214 */
2215
2216static irqreturn_t
7d12e780 2217vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2218{
2219 struct net_device *dev = dev_id;
2220 struct vortex_private *vp = netdev_priv(dev);
62afe595 2221 void __iomem *ioaddr;
1da177e4
LT		 2222 int status;
2223 int work_done = max_interrupt_work;
2224 int handled = 0;
2225
62afe595 2226 ioaddr = vp->ioaddr;
1da177e4
LT		 2227 spin_lock(&vp->lock);
2228
62afe595 2229 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2230
2231 if (vortex_debug > 6)
39738e16 2232 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2233
2234 if ((status & IntLatch) == 0)
2235 goto handler_exit; /* No interrupt: shared IRQs cause this */
2236 handled = 1;
2237
2238 if (status & IntReq) {
2239 status |= vp->deferred;
2240 vp->deferred = 0;
2241 }
2242
2243 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2244 goto handler_exit;
2245
2246 if (vortex_debug > 4)
39738e16 2247 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2248 dev->name, status, ioread8(ioaddr + Timer));
1da177e4 2249
de847272 2250 spin_lock(&vp->window_lock);
a095cfc4
BH		 2251 window_set(vp, 7);
2252
1da177e4
LT		 2253 do {
2254 if (vortex_debug > 5)
39738e16 2255 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2256 dev->name, status);
2257 if (status & RxComplete)
2258 vortex_rx(dev);
2259
2260 if (status & TxAvailable) {
2261 if (vortex_debug > 5)
39738e16 2262 pr_debug(" TX room bit was handled.\n");
1da177e4 2263 /* There's room in the FIFO for a full-sized packet. */
62afe595 2264 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2265 netif_wake_queue (dev);
2266 }
2267
2268 if (status & DMADone) {
62afe595
JL		 2269 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2270 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2271 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2272 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2273 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2274 /*
2275 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2276 * insufficient FIFO room, the TxAvailable test will succeed and call
2277 * netif_wake_queue()
2278 */
2279 netif_wake_queue(dev);
2280 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2281 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2282 netif_stop_queue(dev);
2283 }
2284 }
2285 }
2286 /* Check for all uncommon interrupts at once. */
2287 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2288 if (status == 0xffff)
2289 break;
2290 vortex_error(dev, status);
2291 }
2292
2293 if (--work_done < 0) {
39738e16
AB		 2294 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2295 dev->name, status);
1da177e4
LT		 2296 /* Disable all pending interrupts. */
2297 do {
2298 vp->deferred |= status;
62afe595 2299 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2300 ioaddr + EL3_CMD);
62afe595
JL		 2301 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2302 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2303 /* The timer will reenable interrupts. */
2304 mod_timer(&vp->timer, jiffies + 1*HZ);
2305 break;
2306 }
2307 /* Acknowledge the IRQ. */
62afe595
JL		 2308 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2309 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4 2310
de847272
BH		 2311 spin_unlock(&vp->window_lock);
2312
1da177e4 2313 if (vortex_debug > 4)
39738e16 2314 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2315 dev->name, status);
2316handler_exit:
2317 spin_unlock(&vp->lock);
2318 return IRQ_RETVAL(handled);
2319}
2320
2321/*
2322 * This is the ISR for the boomerang series chips.
2323 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2324 */
2325
2326static irqreturn_t
7d12e780 2327boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2328{
2329 struct net_device *dev = dev_id;
2330 struct vortex_private *vp = netdev_priv(dev);
62afe595 2331 void __iomem *ioaddr;
1da177e4
LT		 2332 int status;
2333 int work_done = max_interrupt_work;
2334
62afe595 2335 ioaddr = vp->ioaddr;
1da177e4
LT		 2336
2337 /*
2338 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2339 * and boomerang_start_xmit
2340 */
2341 spin_lock(&vp->lock);
2342
62afe595 2343 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2344
2345 if (vortex_debug > 6)
39738e16 2346 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2347
2348 if ((status & IntLatch) == 0)
2349 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2350
2351 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2352 if (vortex_debug > 1)
39738e16 2353 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2354 goto handler_exit;
2355 }
2356
2357 if (status & IntReq) {
2358 status |= vp->deferred;
2359 vp->deferred = 0;
2360 }
2361
2362 if (vortex_debug > 4)
39738e16 2363 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2364 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2365 do {
2366 if (vortex_debug > 5)
39738e16 2367 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2368 dev->name, status);
2369 if (status & UpComplete) {
62afe595 2370 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2371 if (vortex_debug > 5)
39738e16 2372 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2373 boomerang_rx(dev);
2374 }
2375
2376 if (status & DownComplete) {
2377 unsigned int dirty_tx = vp->dirty_tx;
2378
62afe595 2379 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2380 while (vp->cur_tx - dirty_tx > 0) {
2381 int entry = dirty_tx % TX_RING_SIZE;
2382#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2383 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2384 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2385 break; /* It still hasn't been processed. */
2386#else
2387 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2388 break; /* It still hasn't been processed. */
2389#endif
6aa20a22 2390
1da177e4
LT		 2391 if (vp->tx_skbuff[entry]) {
2392 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2393#if DO_ZEROCOPY
1da177e4
LT		 2394 int i;
2395 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2396 pci_unmap_single(VORTEX_PCI(vp),
2397 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2398 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2399 PCI_DMA_TODEVICE);
2400#else
2401 pci_unmap_single(VORTEX_PCI(vp),
2402 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2403#endif
2404 dev_kfree_skb_irq(skb);
2405 vp->tx_skbuff[entry] = NULL;
2406 } else {
39738e16 2407 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2408 }
1daad055 2409 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2410 dirty_tx++;
2411 }
2412 vp->dirty_tx = dirty_tx;
2413 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2414 if (vortex_debug > 6)
39738e16 2415 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2416 netif_wake_queue (dev);
2417 }
2418 }
2419
2420 /* Check for all uncommon interrupts at once. */
2421 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2422 vortex_error(dev, status);
2423
2424 if (--work_done < 0) {
39738e16
AB		 2425 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2426 dev->name, status);
1da177e4
LT		 2427 /* Disable all pending interrupts. */
2428 do {
2429 vp->deferred |= status;
62afe595 2430 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2431 ioaddr + EL3_CMD);
62afe595
JL		 2432 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2433 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2434 /* The timer will reenable interrupts. */
2435 mod_timer(&vp->timer, jiffies + 1*HZ);
2436 break;
2437 }
2438 /* Acknowledge the IRQ. */
62afe595 2439 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2440 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2441 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2442
62afe595 2443 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2444
2445 if (vortex_debug > 4)
39738e16 2446 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2447 dev->name, status);
2448handler_exit:
2449 spin_unlock(&vp->lock);
2450 return IRQ_HANDLED;
2451}
2452
2453static int vortex_rx(struct net_device *dev)
2454{
2455 struct vortex_private *vp = netdev_priv(dev);
62afe595 2456 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2457 int i;
2458 short rx_status;
2459
2460 if (vortex_debug > 5)
39738e16 2461 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2462 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2463 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2464 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2465 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2466 if (vortex_debug > 2)
39738e16 2467 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2468 dev->stats.rx_errors++;
2469 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2470 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2471 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2472 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2473 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2474 } else {
2475 /* The packet length: up to 4.5K!. */
2476 int pkt_len = rx_status & 0x1fff;
2477 struct sk_buff *skb;
2478
2479 skb = dev_alloc_skb(pkt_len + 5);
2480 if (vortex_debug > 4)
39738e16 2481 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2482 pkt_len, rx_status);
2483 if (skb != NULL) {
1da177e4
LT		 2484 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2485 /* 'skb_put()' points to the start of sk_buff data area. */
2486 if (vp->bus_master &&
62afe595 2487 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2488 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2489 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2490 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2491 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2492 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2493 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2494 ;
2495 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2496 } else {
62afe595
JL		 2497 ioread32_rep(ioaddr + RX_FIFO,
2498 skb_put(skb, pkt_len),
2499 (pkt_len + 3) >> 2);
1da177e4 2500 }
62afe595 2501 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2502 skb->protocol = eth_type_trans(skb, dev);
2503 netif_rx(skb);
1daad055 2504 dev->stats.rx_packets++;
1da177e4
LT		 2505 /* Wait a limited time to go to next packet. */
2506 for (i = 200; i >= 0; i--)
62afe595 2507 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2508 break;
2509 continue;
2510 } else if (vortex_debug > 0)
39738e16
AB		 2511 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2512 dev->name, pkt_len);
1daad055 2513 dev->stats.rx_dropped++;
1da177e4 2514 }
1da177e4
LT		 2515 issue_and_wait(dev, RxDiscard);
2516 }
2517
2518 return 0;
2519}
2520
2521static int
2522boomerang_rx(struct net_device *dev)
2523{
2524 struct vortex_private *vp = netdev_priv(dev);
2525 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2526 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2527 int rx_status;
2528 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2529
2530 if (vortex_debug > 5)
39738e16 2531 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2532
2533 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2534 if (--rx_work_limit < 0)
2535 break;
2536 if (rx_status & RxDError) { /* Error, update stats. */
2537 unsigned char rx_error = rx_status >> 16;
2538 if (vortex_debug > 2)
39738e16 2539 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2540 dev->stats.rx_errors++;
2541 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2542 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2543 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2544 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2545 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2546 } else {
2547 /* The packet length: up to 4.5K!. */
2548 int pkt_len = rx_status & 0x1fff;
2549 struct sk_buff *skb;
2550 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2551
2552 if (vortex_debug > 4)
39738e16 2553 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2554 pkt_len, rx_status);
2555
2556 /* Check if the packet is long enough to just accept without
2557 copying to a properly sized skbuff. */
cc2d6596 2558 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2559 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2560 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2561 /* 'skb_put()' points to the start of sk_buff data area. */
2562 memcpy(skb_put(skb, pkt_len),
689be439 2563 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2564 pkt_len);
2565 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2566 vp->rx_copy++;
2567 } else {
2568 /* Pass up the skbuff already on the Rx ring. */
2569 skb = vp->rx_skbuff[entry];
2570 vp->rx_skbuff[entry] = NULL;
2571 skb_put(skb, pkt_len);
2572 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2573 vp->rx_nocopy++;
2574 }
2575 skb->protocol = eth_type_trans(skb, dev);
2576 { /* Use hardware checksum info. */
2577 int csum_bits = rx_status & 0xee000000;
2578 if (csum_bits &&
2579 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2580 csum_bits == (IPChksumValid | UDPChksumValid))) {
2581 skb->ip_summed = CHECKSUM_UNNECESSARY;
2582 vp->rx_csumhits++;
2583 }
2584 }
2585 netif_rx(skb);
1daad055 2586 dev->stats.rx_packets++;
1da177e4
LT		 2587 }
2588 entry = (++vp->cur_rx) % RX_RING_SIZE;
2589 }
2590 /* Refill the Rx ring buffers. */
2591 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2592 struct sk_buff *skb;
2593 entry = vp->dirty_rx % RX_RING_SIZE;
2594 if (vp->rx_skbuff[entry] == NULL) {
89d71a66 2595 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
1da177e4
LT		 2596 if (skb == NULL) {
2597 static unsigned long last_jif;
ff5688ae 2598 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2599 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2600 last_jif = jiffies;
2601 }
2602 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2603 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2604 break; /* Bad news! */
2605 }
9a5d3414 2606
689be439 2607 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2608 vp->rx_skbuff[entry] = skb;
2609 }
2610 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2611 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2612 }
2613 return 0;
2614}
2615
2616/*
2617 * If we've hit a total OOM refilling the Rx ring we poll once a second
2618 * for some memory. Otherwise there is no way to restart the rx process.
2619 */
2620static void
2621rx_oom_timer(unsigned long arg)
2622{
2623 struct net_device *dev = (struct net_device *)arg;
2624 struct vortex_private *vp = netdev_priv(dev);
2625
2626 spin_lock_irq(&vp->lock);
2627 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2628 boomerang_rx(dev);
2629 if (vortex_debug > 1) {
39738e16 2630 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2631 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2632 }
2633 spin_unlock_irq(&vp->lock);
2634}
2635
2636static void
2637vortex_down(struct net_device *dev, int final_down)
2638{
2639 struct vortex_private *vp = netdev_priv(dev);
62afe595 2640 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2641
2642 netif_stop_queue (dev);
2643
2644 del_timer_sync(&vp->rx_oom_timer);
2645 del_timer_sync(&vp->timer);
2646
1daad055 2647 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2648 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2649
2650 /* Disable the receiver and transmitter. */
62afe595
JL		 2651 iowrite16(RxDisable, ioaddr + EL3_CMD);
2652 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2653
2654 /* Disable receiving 802.1q tagged frames */
2655 set_8021q_mode(dev, 0);
2656
2657 if (dev->if_port == XCVR_10base2)
2658 /* Turn off thinnet power. Green! */
62afe595 2659 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2660
62afe595 2661 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2662
2663 update_stats(ioaddr, dev);
2664 if (vp->full_bus_master_rx)
62afe595 2665 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2666 if (vp->full_bus_master_tx)
62afe595 2667 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2668
2669 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2670 vp->pm_state_valid = 1;
1da177e4
LT		 2671 pci_save_state(VORTEX_PCI(vp));
2672 acpi_set_WOL(dev);
2673 }
2674}
2675
2676static int
2677vortex_close(struct net_device *dev)
2678{
2679 struct vortex_private *vp = netdev_priv(dev);
62afe595 2680 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2681 int i;
2682
2683 if (netif_device_present(dev))
2684 vortex_down(dev, 1);
2685
2686 if (vortex_debug > 1) {
39738e16 2687 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2688 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2689 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2690 " tx_queued %d Rx pre-checksummed %d.\n",
2691 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2692 }
2693
2694#if DO_ZEROCOPY
32fb5f06
JL		 2695 if (vp->rx_csumhits &&
2696 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2697 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2698 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2699 }
2700#endif
6aa20a22 2701
1da177e4
LT		 2702 free_irq(dev->irq, dev);
2703
2704 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2705 for (i = 0; i < RX_RING_SIZE; i++)
2706 if (vp->rx_skbuff[i]) {
2707 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2708 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2709 dev_kfree_skb(vp->rx_skbuff[i]);
2710 vp->rx_skbuff[i] = NULL;
2711 }
2712 }
2713 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2714 for (i = 0; i < TX_RING_SIZE; i++) {
2715 if (vp->tx_skbuff[i]) {
2716 struct sk_buff *skb = vp->tx_skbuff[i];
2717#if DO_ZEROCOPY
2718 int k;
2719
2720 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2721 pci_unmap_single(VORTEX_PCI(vp),
2722 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2723 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2724 PCI_DMA_TODEVICE);
2725#else
2726 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2727#endif
2728 dev_kfree_skb(skb);
2729 vp->tx_skbuff[i] = NULL;
2730 }
2731 }
2732 }
2733
2734 return 0;
2735}
2736
2737static void
2738dump_tx_ring(struct net_device *dev)
2739{
2740 if (vortex_debug > 0) {
2741 struct vortex_private *vp = netdev_priv(dev);
62afe595 2742 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2743
1da177e4
LT		 2744 if (vp->full_bus_master_tx) {
2745 int i;
62afe595 2746 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2747
39738e16 2748 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2749 vp->full_bus_master_tx,
2750 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2751 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2752 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2753 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2754 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2755 issue_and_wait(dev, DownStall);
2756 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2757 unsigned int length;
2758
1da177e4 2759#if DO_ZEROCOPY
0cb13536 2760 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2761#else
0cb13536 2762 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2763#endif
0cb13536
JD		 2764 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2765 i, &vp->tx_ring[i], length,
1da177e4
LT		 2766 le32_to_cpu(vp->tx_ring[i].status));
2767 }
2768 if (!stalled)
62afe595 2769 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2770 }
2771 }
2772}
2773
2774static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2775{
2776 struct vortex_private *vp = netdev_priv(dev);
62afe595 2777 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2778 unsigned long flags;
2779
2780 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2781 spin_lock_irqsave (&vp->lock, flags);
62afe595 2782 update_stats(ioaddr, dev);
1da177e4
LT		 2783 spin_unlock_irqrestore (&vp->lock, flags);
2784 }
1daad055 2785 return &dev->stats;
1da177e4
LT		 2786}
2787
2788/* Update statistics.
2789 Unlike with the EL3 we need not worry about interrupts changing
2790 the window setting from underneath us, but we must still guard
2791 against a race condition with a StatsUpdate interrupt updating the
2792 table. This is done by checking that the ASM (!) code generated uses
2793 atomic updates with '+='.
2794 */
62afe595 2795static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2796{
2797 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2798
1da177e4
LT		 2799 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2800 /* Switch to the stats window, and read everything. */
a095cfc4
BH		 2801 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2802 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2803 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2804 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2805 dev->stats.tx_packets += window_read8(vp, 6, 6);
2806 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2807 0x30) << 4;
2808 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
1da177e4
LT		 2809 /* Don't bother with register 9, an extension of registers 6&7.
2810 If we do use the 6&7 values the atomic update assumption above
2811 is invalid. */
a095cfc4
BH		 2812 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2813 dev->stats.tx_bytes += window_read16(vp, 6, 12);
1da177e4 2814 /* Extra stats for get_ethtool_stats() */
a095cfc4
BH		 2815 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2816 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2817 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2818 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
1da177e4 2819
1daad055 2820 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2821 + vp->xstats.tx_single_collisions
2822 + vp->xstats.tx_max_collisions;
2823
1da177e4 2824 {
a095cfc4 2825 u8 up = window_read8(vp, 4, 13);
1daad055
PZ		 2826 dev->stats.rx_bytes += (up & 0x0f) << 16;
2827 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4 2828 }
1da177e4
LT		 2829}
2830
2831static int vortex_nway_reset(struct net_device *dev)
2832{
2833 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2834
de847272 2835 return mii_nway_restart(&vp->mii);
1da177e4
LT		 2836}
2837
1da177e4
LT		 2838static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2839{
2840 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2841
de847272 2842 return mii_ethtool_gset(&vp->mii, cmd);
1da177e4
LT		 2843}
2844
2845static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2846{
2847 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2848
de847272 2849 return mii_ethtool_sset(&vp->mii, cmd);
1da177e4
LT		 2850}
2851
2852static u32 vortex_get_msglevel(struct net_device *dev)
2853{
2854 return vortex_debug;
2855}
2856
2857static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2858{
2859 vortex_debug = dbg;
2860}
2861
b9f2c044 2862static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2863{
b9f2c044
JG		 2864 switch (sset) {
2865 case ETH_SS_STATS:
2866 return VORTEX_NUM_STATS;
2867 default:
2868 return -EOPNOTSUPP;
2869 }
1da177e4
LT		 2870}
2871
2872static void vortex_get_ethtool_stats(struct net_device *dev,
2873 struct ethtool_stats *stats, u64 *data)
2874{
2875 struct vortex_private *vp = netdev_priv(dev);
62afe595 2876 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2877 unsigned long flags;
2878
2879 spin_lock_irqsave(&vp->lock, flags);
62afe595 2880 update_stats(ioaddr, dev);
1da177e4
LT		 2881 spin_unlock_irqrestore(&vp->lock, flags);
2882
2883 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2884 data[1] = vp->xstats.tx_max_collisions;
2885 data[2] = vp->xstats.tx_multiple_collisions;
2886 data[3] = vp->xstats.tx_single_collisions;
2887 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2888}
2889
2890
2891static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2892{
2893 switch (stringset) {
2894 case ETH_SS_STATS:
2895 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2896 break;
2897 default:
2898 WARN_ON(1);
2899 break;
2900 }
2901}
2902
2903static void vortex_get_drvinfo(struct net_device *dev,
2904 struct ethtool_drvinfo *info)
2905{
2906 struct vortex_private *vp = netdev_priv(dev);
2907
2908 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2909 if (VORTEX_PCI(vp)) {
2910 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2911 } else {
2912 if (VORTEX_EISA(vp))
86de79b6 2913 strcpy(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2914 else
2915 sprintf(info->bus_info, "EISA 0x%lx %d",
2916 dev->base_addr, dev->irq);
2917 }
2918}
2919
7282d491 2920static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2921 .get_drvinfo = vortex_get_drvinfo,
2922 .get_strings = vortex_get_strings,
2923 .get_msglevel = vortex_get_msglevel,
2924 .set_msglevel = vortex_set_msglevel,
2925 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2926 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2927 .get_settings = vortex_get_settings,
2928 .set_settings = vortex_set_settings,
373a6887 2929 .get_link = ethtool_op_get_link,
1da177e4
LT		 2930 .nway_reset = vortex_nway_reset,
2931};
2932
2933#ifdef CONFIG_PCI
2934/*
2935 * Must power the device up to do MDIO operations
2936 */
2937static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2938{
2939 int err;
2940 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2941 unsigned long flags;
cc2d6596 2942 pci_power_t state = 0;
1da177e4
LT		 2943
2944 if(VORTEX_PCI(vp))
2945 state = VORTEX_PCI(vp)->current_state;
2946
2947 /* The kernel core really should have pci_get_power_state() */
2948
2949 if(state != 0)
2950 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2951 spin_lock_irqsave(&vp->lock, flags);
1da177e4
LT		 2952 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2953 spin_unlock_irqrestore(&vp->lock, flags);
2954 if(state != 0)
2955 pci_set_power_state(VORTEX_PCI(vp), state);
2956
2957 return err;
2958}
2959#endif
2960
2961
2962/* Pre-Cyclone chips have no documented multicast filter, so the only
2963 multicast setting is to receive all multicast frames. At least
2964 the chip has a very clean way to set the mode, unlike many others. */
2965static void set_rx_mode(struct net_device *dev)
2966{
62afe595
JL		 2967 struct vortex_private *vp = netdev_priv(dev);
2968 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2969 int new_mode;
2970
2971 if (dev->flags & IFF_PROMISC) {
d5b20697 2972 if (vortex_debug > 3)
39738e16 2973 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4 2974 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
59ce25d9 2975 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2976 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2977 } else
2978 new_mode = SetRxFilter | RxStation | RxBroadcast;
2979
62afe595 2980 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2981}
2982
2983#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2984/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2985 Note that this must be done after each RxReset due to some backwards
2986 compatibility logic in the Cyclone and Tornado ASICs */
2987
2988/* The Ethernet Type used for 802.1q tagged frames */
2989#define VLAN_ETHER_TYPE 0x8100
2990
2991static void set_8021q_mode(struct net_device *dev, int enable)
2992{
2993 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 2994 int mac_ctrl;
2995
2996 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2997 /* cyclone and tornado chipsets can recognize 802.1q
2998 * tagged frames and treat them correctly */
2999
3000 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3001 if (enable)
3002 max_pkt_size += 4; /* 802.1Q VLAN tag */
3003
a095cfc4 3004 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
1da177e4
LT		 3005
3006 /* set VlanEtherType to let the hardware checksumming
3007 treat tagged frames correctly */
a095cfc4 3008 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
1da177e4
LT		 3009 } else {
3010 /* on older cards we have to enable large frames */
3011
3012 vp->large_frames = dev->mtu > 1500 || enable;
3013
a095cfc4 3014 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
1da177e4
LT		 3015 if (vp->large_frames)
3016 mac_ctrl |= 0x40;
3017 else
3018 mac_ctrl &= ~0x40;
a095cfc4 3019 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
1da177e4 3020 }
1da177e4
LT		 3021}
3022#else
3023
3024static void set_8021q_mode(struct net_device *dev, int enable)
3025{
3026}
3027
3028
3029#endif
3030
3031/* MII transceiver control section.
3032 Read and write the MII registers using software-generated serial
3033 MDIO protocol. See the MII specifications or DP83840A data sheet
3034 for details. */
3035
3036/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3037 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3038 "overclocking" issues. */
a095cfc4
BH		 3039static void mdio_delay(struct vortex_private *vp)
3040{
3041 window_read32(vp, 4, Wn4_PhysicalMgmt);
3042}
1da177e4
LT		 3043
3044#define MDIO_SHIFT_CLK 0x01
3045#define MDIO_DIR_WRITE 0x04
3046#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3047#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3048#define MDIO_DATA_READ 0x02
3049#define MDIO_ENB_IN 0x00
3050
3051/* Generate the preamble required for initial synchronization and
3052 a few older transceivers. */
a095cfc4 3053static void mdio_sync(struct vortex_private *vp, int bits)
1da177e4 3054{
1da177e4
LT		 3055 /* Establish sync by sending at least 32 logic ones. */
3056 while (-- bits >= 0) {
a095cfc4
BH		 3057 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3058 mdio_delay(vp);
3059 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3060 4, Wn4_PhysicalMgmt);
3061 mdio_delay(vp);
1da177e4
LT		 3062 }
3063}
3064
3065static int mdio_read(struct net_device *dev, int phy_id, int location)
3066{
3067 int i;
62afe595 3068 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3069 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3070 unsigned int retval = 0;
1da177e4 3071
de847272
BH		 3072 spin_lock_bh(&vp->mii_lock);
3073
1da177e4 3074 if (mii_preamble_required)
a095cfc4 3075 mdio_sync(vp, 32);
1da177e4
LT		 3076
3077 /* Shift the read command bits out. */
3078 for (i = 14; i >= 0; i--) {
3079 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3080 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3081 mdio_delay(vp);
3082 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3083 4, Wn4_PhysicalMgmt);
3084 mdio_delay(vp);
1da177e4
LT		 3085 }
3086 /* Read the two transition, 16 data, and wire-idle bits. */
3087 for (i = 19; i > 0; i--) {
a095cfc4
BH		 3088 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3089 mdio_delay(vp);
3090 retval = (retval << 1) |
3091 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3092 MDIO_DATA_READ) ? 1 : 0);
3093 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3094 4, Wn4_PhysicalMgmt);
3095 mdio_delay(vp);
1da177e4 3096 }
de847272
BH		 3097
3098 spin_unlock_bh(&vp->mii_lock);
3099
1da177e4
LT		 3100 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3101}
3102
3103static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3104{
62afe595 3105 struct vortex_private *vp = netdev_priv(dev);
1da177e4 3106 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
1da177e4
LT		 3107 int i;
3108
de847272
BH		 3109 spin_lock_bh(&vp->mii_lock);
3110
1da177e4 3111 if (mii_preamble_required)
a095cfc4 3112 mdio_sync(vp, 32);
1da177e4
LT		 3113
3114 /* Shift the command bits out. */
3115 for (i = 31; i >= 0; i--) {
3116 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3117 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3118 mdio_delay(vp);
3119 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3120 4, Wn4_PhysicalMgmt);
3121 mdio_delay(vp);
1da177e4
LT		 3122 }
3123 /* Leave the interface idle. */
3124 for (i = 1; i >= 0; i--) {
a095cfc4
BH		 3125 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3126 mdio_delay(vp);
3127 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3128 4, Wn4_PhysicalMgmt);
3129 mdio_delay(vp);
1da177e4 3130 }
de847272
BH		 3131
3132 spin_unlock_bh(&vp->mii_lock);
1da177e4 3133}
a880c4cd 3134
1da177e4
LT		 3135/* ACPI: Advanced Configuration and Power Interface. */
3136/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3137static void acpi_set_WOL(struct net_device *dev)
3138{
3139 struct vortex_private *vp = netdev_priv(dev);
62afe595 3140 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3141
c17931c5
SK		 3142 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3143
1da177e4
LT		 3144 if (vp->enable_wol) {
3145 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
a095cfc4 3146 window_write16(vp, 2, 7, 0x0c);
1da177e4 3147 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3148 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3149 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3150
1a1769f3 3151 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3152 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3153
3154 vp->enable_wol = 0;
3155 return;
3156 }
3c8fad18
DR		 3157
3158 /* Change the power state to D3; RxEnable doesn't take effect. */
3159 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3160 }
1da177e4
LT		 3161}
3162
3163
a880c4cd 3164static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3165{
3166 struct net_device *dev = pci_get_drvdata(pdev);
3167 struct vortex_private *vp;
3168
3169 if (!dev) {
39738e16 3170 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3171 BUG();
3172 }
3173
3174 vp = netdev_priv(dev);
3175
62afe595
JL		 3176 if (vp->cb_fn_base)
3177 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3178
1da177e4
LT		 3179 unregister_netdev(dev);
3180
3181 if (VORTEX_PCI(vp)) {
3182 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3183 if (vp->pm_state_valid)
3184 pci_restore_state(VORTEX_PCI(vp));
3185 pci_disable_device(VORTEX_PCI(vp));
3186 }
3187 /* Should really use issue_and_wait() here */
62afe595
JL		 3188 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3189 vp->ioaddr + EL3_CMD);
3190
3191 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3192
3193 pci_free_consistent(pdev,
3194 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3195 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3196 vp->rx_ring,
3197 vp->rx_ring_dma);
3198 if (vp->must_free_region)
3199 release_region(dev->base_addr, vp->io_size);
3200 free_netdev(dev);
3201}
3202
3203
3204static struct pci_driver vortex_driver = {
3205 .name = "3c59x",
3206 .probe = vortex_init_one,
3207 .remove = __devexit_p(vortex_remove_one),
3208 .id_table = vortex_pci_tbl,
7bfc4ab5 3209 .driver.pm = VORTEX_PM_OPS,
1da177e4
LT		 3210};
3211
3212
3213static int vortex_have_pci;
3214static int vortex_have_eisa;
3215
3216
a880c4cd 3217static int __init vortex_init(void)
1da177e4
LT		 3218{
3219 int pci_rc, eisa_rc;
3220
29917620 3221 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3222 eisa_rc = vortex_eisa_init();
3223
3224 if (pci_rc == 0)
3225 vortex_have_pci = 1;
3226 if (eisa_rc > 0)
3227 vortex_have_eisa = 1;
3228
3229 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3230}
3231
3232
a880c4cd 3233static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3234{
3235 struct vortex_private *vp;
62afe595 3236 void __iomem *ioaddr;
1da177e4
LT		 3237
3238#ifdef CONFIG_EISA
3239 /* Take care of the EISA devices */
a880c4cd 3240 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3241#endif
6aa20a22 3242
1da177e4 3243 if (compaq_net_device) {
454d7c9b 3244 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3245 ioaddr = ioport_map(compaq_net_device->base_addr,
3246 VORTEX_TOTAL_SIZE);
1da177e4 3247
a880c4cd
SK		 3248 unregister_netdev(compaq_net_device);
3249 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3250 release_region(compaq_net_device->base_addr,
3251 VORTEX_TOTAL_SIZE);
1da177e4 3252
a880c4cd 3253 free_netdev(compaq_net_device);
1da177e4
LT		 3254 }
3255}
3256
3257
a880c4cd 3258static void __exit vortex_cleanup(void)
1da177e4
LT		 3259{
3260 if (vortex_have_pci)
a880c4cd 3261 pci_unregister_driver(&vortex_driver);
1da177e4 3262 if (vortex_have_eisa)
a880c4cd 3263 vortex_eisa_cleanup();
1da177e4
LT		 3264}
3265
3266
3267module_init(vortex_init);
3268module_exit(vortex_cleanup);
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