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stmmac: add CSR Clock range selection
[net-next-2.6.git] / drivers / net / stmmac / stmmac_main.c
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47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
5a0e3ad6 47#include <linux/slab.h>
47dd7a54
GC		 48#include "stmmac.h"
49
50#define STMMAC_RESOURCE_NAME "stmmaceth"
51#define PHY_RESOURCE_NAME "stmmacphy"
52
53#undef STMMAC_DEBUG
54/*#define STMMAC_DEBUG*/
55#ifdef STMMAC_DEBUG
56#define DBG(nlevel, klevel, fmt, args...) \
57 ((void)(netif_msg_##nlevel(priv) && \
58 printk(KERN_##klevel fmt, ## args)))
59#else
60#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61#endif
62
63#undef STMMAC_RX_DEBUG
64/*#define STMMAC_RX_DEBUG*/
65#ifdef STMMAC_RX_DEBUG
66#define RX_DBG(fmt, args...) printk(fmt, ## args)
67#else
68#define RX_DBG(fmt, args...) do { } while (0)
69#endif
70
71#undef STMMAC_XMIT_DEBUG
72/*#define STMMAC_XMIT_DEBUG*/
73#ifdef STMMAC_TX_DEBUG
74#define TX_DBG(fmt, args...) printk(fmt, ## args)
75#else
76#define TX_DBG(fmt, args...) do { } while (0)
77#endif
78
79#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
80#define JUMBO_LEN 9000
81
82/* Module parameters */
83#define TX_TIMEO 5000 /* default 5 seconds */
84static int watchdog = TX_TIMEO;
85module_param(watchdog, int, S_IRUGO | S_IWUSR);
86MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
87
88static int debug = -1; /* -1: default, 0: no output, 16: all */
89module_param(debug, int, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
91
92static int phyaddr = -1;
93module_param(phyaddr, int, S_IRUGO);
94MODULE_PARM_DESC(phyaddr, "Physical device address");
95
96#define DMA_TX_SIZE 256
97static int dma_txsize = DMA_TX_SIZE;
98module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
99MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
100
101#define DMA_RX_SIZE 256
102static int dma_rxsize = DMA_RX_SIZE;
103module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
104MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
105
106static int flow_ctrl = FLOW_OFF;
107module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
108MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
109
110static int pause = PAUSE_TIME;
111module_param(pause, int, S_IRUGO | S_IWUSR);
112MODULE_PARM_DESC(pause, "Flow Control Pause Time");
113
114#define TC_DEFAULT 64
115static int tc = TC_DEFAULT;
116module_param(tc, int, S_IRUGO | S_IWUSR);
117MODULE_PARM_DESC(tc, "DMA threshold control value");
118
119#define RX_NO_COALESCE 1 /* Always interrupt on completion */
120#define TX_NO_COALESCE -1 /* No moderation by default */
121
122/* Pay attention to tune this parameter; take care of both
123 * hardware capability and network stabitily/performance impact.
124 * Many tests showed that ~4ms latency seems to be good enough. */
125#ifdef CONFIG_STMMAC_TIMER
126#define DEFAULT_PERIODIC_RATE 256
127static int tmrate = DEFAULT_PERIODIC_RATE;
128module_param(tmrate, int, S_IRUGO | S_IWUSR);
129MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
130#endif
131
132#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
133static int buf_sz = DMA_BUFFER_SIZE;
134module_param(buf_sz, int, S_IRUGO | S_IWUSR);
135MODULE_PARM_DESC(buf_sz, "DMA buffer size");
136
137/* In case of Giga ETH, we can enable/disable the COE for the
138 * transmit HW checksum computation.
139 * Note that, if tx csum is off in HW, SG will be still supported. */
140static int tx_coe = HW_CSUM;
141module_param(tx_coe, int, S_IRUGO | S_IWUSR);
142MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
143
144static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
145 NETIF_MSG_LINK | NETIF_MSG_IFUP |
146 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
147
148static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
149static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
150
151/**
152 * stmmac_verify_args - verify the driver parameters.
153 * Description: it verifies if some wrong parameter is passed to the driver.
154 * Note that wrong parameters are replaced with the default values.
155 */
156static void stmmac_verify_args(void)
157{
158 if (unlikely(watchdog < 0))
159 watchdog = TX_TIMEO;
160 if (unlikely(dma_rxsize < 0))
161 dma_rxsize = DMA_RX_SIZE;
162 if (unlikely(dma_txsize < 0))
163 dma_txsize = DMA_TX_SIZE;
164 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
165 buf_sz = DMA_BUFFER_SIZE;
166 if (unlikely(flow_ctrl > 1))
167 flow_ctrl = FLOW_AUTO;
168 else if (likely(flow_ctrl < 0))
169 flow_ctrl = FLOW_OFF;
170 if (unlikely((pause < 0) || (pause > 0xffff)))
171 pause = PAUSE_TIME;
47dd7a54
GC		 172}
173
174#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
175static void print_pkt(unsigned char *buf, int len)
176{
177 int j;
178 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
179 for (j = 0; j < len; j++) {
180 if ((j % 16) == 0)
181 pr_info("\n %03x:", j);
182 pr_info(" %02x", buf[j]);
183 }
184 pr_info("\n");
47dd7a54
GC		 185}
186#endif
187
188/* minimum number of free TX descriptors required to wake up TX process */
189#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
190
191static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
192{
193 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
194}
195
196/**
197 * stmmac_adjust_link
198 * @dev: net device structure
199 * Description: it adjusts the link parameters.
200 */
201static void stmmac_adjust_link(struct net_device *dev)
202{
203 struct stmmac_priv *priv = netdev_priv(dev);
204 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 205 unsigned long flags;
206 int new_state = 0;
207 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
208
209 if (phydev == NULL)
210 return;
211
212 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
213 phydev->addr, phydev->link);
214
215 spin_lock_irqsave(&priv->lock, flags);
216 if (phydev->link) {
ad01b7d4 217 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 218
219 /* Now we make sure that we can be in full duplex mode.
220 * If not, we operate in half-duplex mode. */
221 if (phydev->duplex != priv->oldduplex) {
222 new_state = 1;
223 if (!(phydev->duplex))
db98a0b0 224 ctrl &= ~priv->hw->link.duplex;
47dd7a54 225 else
db98a0b0 226 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 227 priv->oldduplex = phydev->duplex;
228 }
229 /* Flow Control operation */
230 if (phydev->pause)
ad01b7d4 231 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 232 fc, pause_time);
47dd7a54
GC		 233
234 if (phydev->speed != priv->speed) {
235 new_state = 1;
236 switch (phydev->speed) {
237 case 1000:
238 if (likely(priv->is_gmac))
db98a0b0 239 ctrl &= ~priv->hw->link.port;
219dd113
PM		 240 if (likely(priv->fix_mac_speed))
241 priv->fix_mac_speed(priv->bsp_priv,
242 phydev->speed);
47dd7a54
GC		 243 break;
244 case 100:
245 case 10:
246 if (priv->is_gmac) {
db98a0b0 247 ctrl |= priv->hw->link.port;
47dd7a54 248 if (phydev->speed == SPEED_100) {
db98a0b0 249 ctrl |= priv->hw->link.speed;
47dd7a54 250 } else {
db98a0b0 251 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 252 }
253 } else {
db98a0b0 254 ctrl &= ~priv->hw->link.port;
47dd7a54 255 }
65818fa7
GC		 256 if (likely(priv->fix_mac_speed))
257 priv->fix_mac_speed(priv->bsp_priv,
258 phydev->speed);
47dd7a54
GC		 259 break;
260 default:
261 if (netif_msg_link(priv))
262 pr_warning("%s: Speed (%d) is not 10"
263 " or 100!\n", dev->name, phydev->speed);
264 break;
265 }
266
267 priv->speed = phydev->speed;
268 }
269
ad01b7d4 270 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 271
272 if (!priv->oldlink) {
273 new_state = 1;
274 priv->oldlink = 1;
275 }
276 } else if (priv->oldlink) {
277 new_state = 1;
278 priv->oldlink = 0;
279 priv->speed = 0;
280 priv->oldduplex = -1;
281 }
282
283 if (new_state && netif_msg_link(priv))
284 phy_print_status(phydev);
285
286 spin_unlock_irqrestore(&priv->lock, flags);
287
288 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
289}
290
291/**
292 * stmmac_init_phy - PHY initialization
293 * @dev: net device structure
294 * Description: it initializes the driver's PHY state, and attaches the PHY
295 * to the mac driver.
296 * Return value:
297 * 0 on success
298 */
299static int stmmac_init_phy(struct net_device *dev)
300{
301 struct stmmac_priv *priv = netdev_priv(dev);
302 struct phy_device *phydev;
109cdd66
GC		 303 char phy_id[MII_BUS_ID_SIZE + 3];
304 char bus_id[MII_BUS_ID_SIZE];
47dd7a54
GC		 305
306 priv->oldlink = 0;
307 priv->speed = 0;
308 priv->oldduplex = -1;
309
310 if (priv->phy_addr == -1) {
311 /* We don't have a PHY, so do nothing */
312 return 0;
313 }
314
315 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
109cdd66
GC		 316 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
317 priv->phy_addr);
47dd7a54
GC		 318 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
319
320 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
321 priv->phy_interface);
322
323 if (IS_ERR(phydev)) {
324 pr_err("%s: Could not attach to PHY\n", dev->name);
325 return PTR_ERR(phydev);
326 }
327
328 /*
329 * Broken HW is sometimes missing the pull-up resistor on the
330 * MDIO line, which results in reads to non-existent devices returning
331 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
332 * device as well.
333 * Note: phydev->phy_id is the result of reading the UID PHY registers.
334 */
335 if (phydev->phy_id == 0) {
336 phy_disconnect(phydev);
337 return -ENODEV;
338 }
339 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
340 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
341
342 priv->phydev = phydev;
343
344 return 0;
345}
346
ad01b7d4 347static inline void stmmac_mac_enable_rx(void __iomem *ioaddr)
47dd7a54
GC		 348{
349 u32 value = readl(ioaddr + MAC_CTRL_REG);
350 value |= MAC_RNABLE_RX;
351 /* Set the RE (receive enable bit into the MAC CTRL register). */
352 writel(value, ioaddr + MAC_CTRL_REG);
353}
354
ad01b7d4 355static inline void stmmac_mac_enable_tx(void __iomem *ioaddr)
47dd7a54
GC		 356{
357 u32 value = readl(ioaddr + MAC_CTRL_REG);
358 value |= MAC_ENABLE_TX;
359 /* Set the TE (transmit enable bit into the MAC CTRL register). */
360 writel(value, ioaddr + MAC_CTRL_REG);
361}
362
ad01b7d4 363static inline void stmmac_mac_disable_rx(void __iomem *ioaddr)
47dd7a54
GC		 364{
365 u32 value = readl(ioaddr + MAC_CTRL_REG);
366 value &= ~MAC_RNABLE_RX;
367 writel(value, ioaddr + MAC_CTRL_REG);
368}
369
ad01b7d4 370static inline void stmmac_mac_disable_tx(void __iomem *ioaddr)
47dd7a54
GC		 371{
372 u32 value = readl(ioaddr + MAC_CTRL_REG);
373 value &= ~MAC_ENABLE_TX;
374 writel(value, ioaddr + MAC_CTRL_REG);
375}
376
377/**
378 * display_ring
379 * @p: pointer to the ring.
380 * @size: size of the ring.
381 * Description: display all the descriptors within the ring.
382 */
383static void display_ring(struct dma_desc *p, int size)
384{
385 struct tmp_s {
386 u64 a;
387 unsigned int b;
388 unsigned int c;
389 };
390 int i;
391 for (i = 0; i < size; i++) {
392 struct tmp_s *x = (struct tmp_s *)(p + i);
393 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
394 i, (unsigned int)virt_to_phys(&p[i]),
395 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
396 x->b, x->c);
397 pr_info("\n");
398 }
399}
400
401/**
402 * init_dma_desc_rings - init the RX/TX descriptor rings
403 * @dev: net device structure
404 * Description: this function initializes the DMA RX/TX descriptors
405 * and allocates the socket buffers.
406 */
407static void init_dma_desc_rings(struct net_device *dev)
408{
409 int i;
410 struct stmmac_priv *priv = netdev_priv(dev);
411 struct sk_buff *skb;
412 unsigned int txsize = priv->dma_tx_size;
413 unsigned int rxsize = priv->dma_rx_size;
414 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 415 int buff2_needed = 0, dis_ic = 0;
47dd7a54 416
47dd7a54
GC		 417 /* Set the Buffer size according to the MTU;
418 * indeed, in case of jumbo we need to bump-up the buffer sizes.
419 */
420 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
421 bfsize = BUF_SIZE_16KiB;
422 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
423 bfsize = BUF_SIZE_8KiB;
424 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
425 bfsize = BUF_SIZE_4KiB;
426 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
427 bfsize = BUF_SIZE_2KiB;
428 else
429 bfsize = DMA_BUFFER_SIZE;
430
73cfe264
GC		 431#ifdef CONFIG_STMMAC_TIMER
432 /* Disable interrupts on completion for the reception if timer is on */
433 if (likely(priv->tm->enable))
434 dis_ic = 1;
435#endif
47dd7a54
GC		 436 /* If the MTU exceeds 8k so use the second buffer in the chain */
437 if (bfsize >= BUF_SIZE_8KiB)
438 buff2_needed = 1;
439
440 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
441 txsize, rxsize, bfsize);
442
443 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
444 priv->rx_skbuff =
445 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
446 priv->dma_rx =
447 (struct dma_desc *)dma_alloc_coherent(priv->device,
448 rxsize *
449 sizeof(struct dma_desc),
450 &priv->dma_rx_phy,
451 GFP_KERNEL);
452 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
453 GFP_KERNEL);
454 priv->dma_tx =
455 (struct dma_desc *)dma_alloc_coherent(priv->device,
456 txsize *
457 sizeof(struct dma_desc),
458 &priv->dma_tx_phy,
459 GFP_KERNEL);
460
461 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
462 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
463 return;
464 }
465
466 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
467 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
468 dev->name, priv->dma_rx, priv->dma_tx,
469 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
470
471 /* RX INITIALIZATION */
472 DBG(probe, INFO, "stmmac: SKB addresses:\n"
473 "skb\t\tskb data\tdma data\n");
474
475 for (i = 0; i < rxsize; i++) {
476 struct dma_desc *p = priv->dma_rx + i;
477
478 skb = netdev_alloc_skb_ip_align(dev, bfsize);
479 if (unlikely(skb == NULL)) {
480 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
481 break;
482 }
483 priv->rx_skbuff[i] = skb;
484 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
485 bfsize, DMA_FROM_DEVICE);
486
487 p->des2 = priv->rx_skbuff_dma[i];
488 if (unlikely(buff2_needed))
489 p->des3 = p->des2 + BUF_SIZE_8KiB;
490 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
491 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
492 }
493 priv->cur_rx = 0;
494 priv->dirty_rx = (unsigned int)(i - rxsize);
495 priv->dma_buf_sz = bfsize;
496 buf_sz = bfsize;
497
498 /* TX INITIALIZATION */
499 for (i = 0; i < txsize; i++) {
500 priv->tx_skbuff[i] = NULL;
501 priv->dma_tx[i].des2 = 0;
502 }
503 priv->dirty_tx = 0;
504 priv->cur_tx = 0;
505
506 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 507 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
508 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 509
510 if (netif_msg_hw(priv)) {
511 pr_info("RX descriptor ring:\n");
512 display_ring(priv->dma_rx, rxsize);
513 pr_info("TX descriptor ring:\n");
514 display_ring(priv->dma_tx, txsize);
515 }
47dd7a54
GC		 516}
517
518static void dma_free_rx_skbufs(struct stmmac_priv *priv)
519{
520 int i;
521
522 for (i = 0; i < priv->dma_rx_size; i++) {
523 if (priv->rx_skbuff[i]) {
524 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
525 priv->dma_buf_sz, DMA_FROM_DEVICE);
526 dev_kfree_skb_any(priv->rx_skbuff[i]);
527 }
528 priv->rx_skbuff[i] = NULL;
529 }
47dd7a54
GC		 530}
531
532static void dma_free_tx_skbufs(struct stmmac_priv *priv)
533{
534 int i;
535
536 for (i = 0; i < priv->dma_tx_size; i++) {
537 if (priv->tx_skbuff[i] != NULL) {
538 struct dma_desc *p = priv->dma_tx + i;
539 if (p->des2)
540 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 541 priv->hw->desc->get_tx_len(p),
542 DMA_TO_DEVICE);
47dd7a54
GC		 543 dev_kfree_skb_any(priv->tx_skbuff[i]);
544 priv->tx_skbuff[i] = NULL;
545 }
546 }
47dd7a54
GC		 547}
548
549static void free_dma_desc_resources(struct stmmac_priv *priv)
550{
551 /* Release the DMA TX/RX socket buffers */
552 dma_free_rx_skbufs(priv);
553 dma_free_tx_skbufs(priv);
554
555 /* Free the region of consistent memory previously allocated for
556 * the DMA */
557 dma_free_coherent(priv->device,
558 priv->dma_tx_size * sizeof(struct dma_desc),
559 priv->dma_tx, priv->dma_tx_phy);
560 dma_free_coherent(priv->device,
561 priv->dma_rx_size * sizeof(struct dma_desc),
562 priv->dma_rx, priv->dma_rx_phy);
563 kfree(priv->rx_skbuff_dma);
564 kfree(priv->rx_skbuff);
565 kfree(priv->tx_skbuff);
47dd7a54
GC		 566}
567
47dd7a54
GC		 568/**
569 * stmmac_dma_operation_mode - HW DMA operation mode
570 * @priv : pointer to the private device structure.
571 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
572 * or Store-And-Forward capability. It also verifies the COE for the
573 * transmission in case of Giga ETH.
574 */
575static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
576{
577 if (!priv->is_gmac) {
578 /* MAC 10/100 */
ad01b7d4 579 priv->hw->dma->dma_mode(priv->ioaddr, tc, 0);
47dd7a54
GC		 580 priv->tx_coe = NO_HW_CSUM;
581 } else {
582 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
ad01b7d4 583 priv->hw->dma->dma_mode(priv->ioaddr,
db98a0b0 584 SF_DMA_MODE, SF_DMA_MODE);
47dd7a54
GC		 585 tc = SF_DMA_MODE;
586 priv->tx_coe = HW_CSUM;
587 } else {
588 /* Checksum computation is performed in software. */
ad01b7d4 589 priv->hw->dma->dma_mode(priv->ioaddr, tc,
db98a0b0 590 SF_DMA_MODE);
47dd7a54
GC		 591 priv->tx_coe = NO_HW_CSUM;
592 }
593 }
594 tx_coe = priv->tx_coe;
47dd7a54
GC		 595}
596
47dd7a54
GC		 597/**
598 * stmmac_tx:
599 * @priv: private driver structure
600 * Description: it reclaims resources after transmission completes.
601 */
602static void stmmac_tx(struct stmmac_priv *priv)
603{
604 unsigned int txsize = priv->dma_tx_size;
47dd7a54
GC		 605
606 while (priv->dirty_tx != priv->cur_tx) {
607 int last;
608 unsigned int entry = priv->dirty_tx % txsize;
609 struct sk_buff *skb = priv->tx_skbuff[entry];
610 struct dma_desc *p = priv->dma_tx + entry;
611
612 /* Check if the descriptor is owned by the DMA. */
db98a0b0 613 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 614 break;
615
616 /* Verify tx error by looking at the last segment */
db98a0b0 617 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 618 if (likely(last)) {
619 int tx_error =
db98a0b0
GC		 620 priv->hw->desc->tx_status(&priv->dev->stats,
621 &priv->xstats, p,
ad01b7d4 622 priv->ioaddr);
47dd7a54
GC		 623 if (likely(tx_error == 0)) {
624 priv->dev->stats.tx_packets++;
625 priv->xstats.tx_pkt_n++;
626 } else
627 priv->dev->stats.tx_errors++;
628 }
629 TX_DBG("%s: curr %d, dirty %d\n", __func__,
630 priv->cur_tx, priv->dirty_tx);
631
632 if (likely(p->des2))
633 dma_unmap_single(priv->device, p->des2,
db98a0b0 634 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 635 DMA_TO_DEVICE);
636 if (unlikely(p->des3))
637 p->des3 = 0;
638
639 if (likely(skb != NULL)) {
640 /*
641 * If there's room in the queue (limit it to size)
642 * we add this skb back into the pool,
643 * if it's the right size.
644 */
645 if ((skb_queue_len(&priv->rx_recycle) <
646 priv->dma_rx_size) &&
647 skb_recycle_check(skb, priv->dma_buf_sz))
648 __skb_queue_head(&priv->rx_recycle, skb);
649 else
650 dev_kfree_skb(skb);
651
652 priv->tx_skbuff[entry] = NULL;
653 }
654
db98a0b0 655 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 656
657 entry = (++priv->dirty_tx) % txsize;
658 }
659 if (unlikely(netif_queue_stopped(priv->dev) &&
660 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
661 netif_tx_lock(priv->dev);
662 if (netif_queue_stopped(priv->dev) &&
663 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
664 TX_DBG("%s: restart transmit\n", __func__);
665 netif_wake_queue(priv->dev);
666 }
667 netif_tx_unlock(priv->dev);
668 }
47dd7a54
GC		 669}
670
671static inline void stmmac_enable_irq(struct stmmac_priv *priv)
672{
73cfe264
GC		 673#ifdef CONFIG_STMMAC_TIMER
674 if (likely(priv->tm->enable))
675 priv->tm->timer_start(tmrate);
676 else
47dd7a54 677#endif
ad01b7d4 678 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 679}
680
681static inline void stmmac_disable_irq(struct stmmac_priv *priv)
682{
73cfe264
GC		 683#ifdef CONFIG_STMMAC_TIMER
684 if (likely(priv->tm->enable))
685 priv->tm->timer_stop();
686 else
47dd7a54 687#endif
ad01b7d4 688 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 689}
690
691static int stmmac_has_work(struct stmmac_priv *priv)
692{
693 unsigned int has_work = 0;
694 int rxret, tx_work = 0;
695
db98a0b0 696 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 697 (priv->cur_rx % priv->dma_rx_size));
698
699 if (priv->dirty_tx != priv->cur_tx)
700 tx_work = 1;
701
702 if (likely(!rxret || tx_work))
703 has_work = 1;
704
705 return has_work;
706}
707
708static inline void _stmmac_schedule(struct stmmac_priv *priv)
709{
710 if (likely(stmmac_has_work(priv))) {
711 stmmac_disable_irq(priv);
712 napi_schedule(&priv->napi);
713 }
714}
715
716#ifdef CONFIG_STMMAC_TIMER
717void stmmac_schedule(struct net_device *dev)
718{
719 struct stmmac_priv *priv = netdev_priv(dev);
720
721 priv->xstats.sched_timer_n++;
722
723 _stmmac_schedule(priv);
47dd7a54
GC		 724}
725
726static void stmmac_no_timer_started(unsigned int x)
727{;
728};
729
730static void stmmac_no_timer_stopped(void)
731{;
732};
733#endif
734
735/**
736 * stmmac_tx_err:
737 * @priv: pointer to the private device structure
738 * Description: it cleans the descriptors and restarts the transmission
739 * in case of errors.
740 */
741static void stmmac_tx_err(struct stmmac_priv *priv)
742{
ad01b7d4 743
47dd7a54
GC		 744 netif_stop_queue(priv->dev);
745
ad01b7d4 746 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 747 dma_free_tx_skbufs(priv);
db98a0b0 748 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 749 priv->dirty_tx = 0;
750 priv->cur_tx = 0;
ad01b7d4 751 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 752
753 priv->dev->stats.tx_errors++;
754 netif_wake_queue(priv->dev);
47dd7a54
GC		 755}
756
47dd7a54 757
aec7ff27
GC		 758static void stmmac_dma_interrupt(struct stmmac_priv *priv)
759{
aec7ff27
GC		 760 int status;
761
ad01b7d4 762 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 763 if (likely(status == handle_tx_rx))
764 _stmmac_schedule(priv);
765
766 else if (unlikely(status == tx_hard_error_bump_tc)) {
767 /* Try to bump up the dma threshold on this failure */
768 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
769 tc += 64;
ad01b7d4 770 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 771 priv->xstats.threshold = tc;
47dd7a54 772 }
aec7ff27
GC		 773 stmmac_tx_err(priv);
774 } else if (unlikely(status == tx_hard_error))
775 stmmac_tx_err(priv);
47dd7a54
GC		 776}
777
778/**
779 * stmmac_open - open entry point of the driver
780 * @dev : pointer to the device structure.
781 * Description:
782 * This function is the open entry point of the driver.
783 * Return value:
784 * 0 on success and an appropriate (-)ve integer as defined in errno.h
785 * file on failure.
786 */
787static int stmmac_open(struct net_device *dev)
788{
789 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 790 int ret;
791
792 /* Check that the MAC address is valid. If its not, refuse
793 * to bring the device up. The user must specify an
794 * address using the following linux command:
795 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
796 if (!is_valid_ether_addr(dev->dev_addr)) {
797 random_ether_addr(dev->dev_addr);
798 pr_warning("%s: generated random MAC address %pM\n", dev->name,
799 dev->dev_addr);
800 }
801
802 stmmac_verify_args();
803
804 ret = stmmac_init_phy(dev);
805 if (unlikely(ret)) {
806 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
807 return ret;
808 }
809
810 /* Request the IRQ lines */
a0607fd3 811 ret = request_irq(dev->irq, stmmac_interrupt,
47dd7a54
GC		 812 IRQF_SHARED, dev->name, dev);
813 if (unlikely(ret < 0)) {
814 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
815 __func__, dev->irq, ret);
816 return ret;
817 }
818
819#ifdef CONFIG_STMMAC_TIMER
73cfe264 820 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 821 if (unlikely(priv->tm == NULL)) {
2381a55c 822 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 823 return -ENOMEM;
824 }
825 priv->tm->freq = tmrate;
826
73cfe264
GC		 827 /* Test if the external timer can be actually used.
828 * In case of failure continue without timer. */
47dd7a54 829 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 830 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 831 priv->tm->freq = 0;
832 priv->tm->timer_start = stmmac_no_timer_started;
833 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 834 } else
835 priv->tm->enable = 1;
47dd7a54
GC		 836#endif
837
838 /* Create and initialize the TX/RX descriptors chains. */
839 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
840 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
841 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
842 init_dma_desc_rings(dev);
843
844 /* DMA initialization and SW reset */
ad01b7d4
GC		 845 if (unlikely(priv->hw->dma->init(priv->ioaddr, priv->pbl,
846 priv->dma_tx_phy,
db98a0b0 847 priv->dma_rx_phy) < 0)) {
47dd7a54
GC		 848
849 pr_err("%s: DMA initialization failed\n", __func__);
850 return -1;
851 }
852
853 /* Copy the MAC addr into the HW */
ad01b7d4 854 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1
GC		 855 /* If required, perform hw setup of the bus. */
856 if (priv->bus_setup)
ad01b7d4 857 priv->bus_setup(priv->ioaddr);
47dd7a54 858 /* Initialize the MAC Core */
ad01b7d4 859 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54
GC		 860
861 priv->shutdown = 0;
862
863 /* Initialise the MMC (if present) to disable all interrupts. */
ad01b7d4
GC		 864 writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK);
865 writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
47dd7a54
GC		 866
867 /* Enable the MAC Rx/Tx */
ad01b7d4
GC		 868 stmmac_mac_enable_rx(priv->ioaddr);
869 stmmac_mac_enable_tx(priv->ioaddr);
47dd7a54
GC		 870
871 /* Set the HW DMA mode and the COE */
872 stmmac_dma_operation_mode(priv);
873
874 /* Extra statistics */
875 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
876 priv->xstats.threshold = tc;
877
878 /* Start the ball rolling... */
879 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 880 priv->hw->dma->start_tx(priv->ioaddr);
881 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 882
883#ifdef CONFIG_STMMAC_TIMER
884 priv->tm->timer_start(tmrate);
885#endif
886 /* Dump DMA/MAC registers */
887 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 888 priv->hw->mac->dump_regs(priv->ioaddr);
889 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 890 }
891
892 if (priv->phydev)
893 phy_start(priv->phydev);
894
895 napi_enable(&priv->napi);
896 skb_queue_head_init(&priv->rx_recycle);
897 netif_start_queue(dev);
898 return 0;
899}
900
901/**
902 * stmmac_release - close entry point of the driver
903 * @dev : device pointer.
904 * Description:
905 * This is the stop entry point of the driver.
906 */
907static int stmmac_release(struct net_device *dev)
908{
909 struct stmmac_priv *priv = netdev_priv(dev);
910
911 /* Stop and disconnect the PHY */
912 if (priv->phydev) {
913 phy_stop(priv->phydev);
914 phy_disconnect(priv->phydev);
915 priv->phydev = NULL;
916 }
917
918 netif_stop_queue(dev);
919
920#ifdef CONFIG_STMMAC_TIMER
921 /* Stop and release the timer */
922 stmmac_close_ext_timer();
923 if (priv->tm != NULL)
924 kfree(priv->tm);
925#endif
926 napi_disable(&priv->napi);
927 skb_queue_purge(&priv->rx_recycle);
928
929 /* Free the IRQ lines */
930 free_irq(dev->irq, dev);
931
932 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 933 priv->hw->dma->stop_tx(priv->ioaddr);
934 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 935
936 /* Release and free the Rx/Tx resources */
937 free_dma_desc_resources(priv);
938
939 /* Disable the MAC core */
ad01b7d4
GC		 940 stmmac_mac_disable_tx(priv->ioaddr);
941 stmmac_mac_disable_rx(priv->ioaddr);
47dd7a54
GC		 942
943 netif_carrier_off(dev);
944
945 return 0;
946}
947
948/*
949 * To perform emulated hardware segmentation on skb.
950 */
951static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
952{
953 struct sk_buff *segs, *curr_skb;
954 int gso_segs = skb_shinfo(skb)->gso_segs;
955
956 /* Estimate the number of fragments in the worst case */
957 if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
958 netif_stop_queue(priv->dev);
959 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
960 __func__);
961 if (stmmac_tx_avail(priv) < gso_segs)
962 return NETDEV_TX_BUSY;
963
964 netif_wake_queue(priv->dev);
965 }
966 TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
967 skb, skb->len);
968
969 segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
970 if (unlikely(IS_ERR(segs)))
971 goto sw_tso_end;
972
973 do {
974 curr_skb = segs;
975 segs = segs->next;
976 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
977 "*next %p\n", curr_skb->len, curr_skb, segs);
978 curr_skb->next = NULL;
979 stmmac_xmit(curr_skb, priv->dev);
980 } while (segs);
981
982sw_tso_end:
983 dev_kfree_skb(skb);
984
985 return NETDEV_TX_OK;
986}
987
988static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
989 struct net_device *dev,
990 int csum_insertion)
991{
992 struct stmmac_priv *priv = netdev_priv(dev);
993 unsigned int nopaged_len = skb_headlen(skb);
994 unsigned int txsize = priv->dma_tx_size;
995 unsigned int entry = priv->cur_tx % txsize;
996 struct dma_desc *desc = priv->dma_tx + entry;
997
998 if (nopaged_len > BUF_SIZE_8KiB) {
999
1000 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1001
1002 desc->des2 = dma_map_single(priv->device, skb->data,
1003 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1004 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1005 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1006 csum_insertion);
47dd7a54
GC		 1007
1008 entry = (++priv->cur_tx) % txsize;
1009 desc = priv->dma_tx + entry;
1010
1011 desc->des2 = dma_map_single(priv->device,
1012 skb->data + BUF_SIZE_8KiB,
1013 buf2_size, DMA_TO_DEVICE);
1014 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1015 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1016 csum_insertion);
1017 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1018 priv->tx_skbuff[entry] = NULL;
1019 } else {
1020 desc->des2 = dma_map_single(priv->device, skb->data,
1021 nopaged_len, DMA_TO_DEVICE);
1022 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1023 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1024 csum_insertion);
47dd7a54
GC		 1025 }
1026 return entry;
1027}
1028
1029/**
1030 * stmmac_xmit:
1031 * @skb : the socket buffer
1032 * @dev : device pointer
1033 * Description : Tx entry point of the driver.
1034 */
1035static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1036{
1037 struct stmmac_priv *priv = netdev_priv(dev);
1038 unsigned int txsize = priv->dma_tx_size;
1039 unsigned int entry;
1040 int i, csum_insertion = 0;
1041 int nfrags = skb_shinfo(skb)->nr_frags;
1042 struct dma_desc *desc, *first;
1043
1044 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1045 if (!netif_queue_stopped(dev)) {
1046 netif_stop_queue(dev);
1047 /* This is a hard error, log it. */
1048 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1049 __func__);
1050 }
1051 return NETDEV_TX_BUSY;
1052 }
1053
1054 entry = priv->cur_tx % txsize;
1055
1056#ifdef STMMAC_XMIT_DEBUG
1057 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1058 pr_info("stmmac xmit:\n"
1059 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1060 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1061 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1062 !skb_is_gso(skb) ? "isn't" : "is");
1063#endif
1064
1065 if (unlikely(skb_is_gso(skb)))
1066 return stmmac_sw_tso(priv, skb);
1067
1068 if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1069 if (likely(priv->tx_coe == NO_HW_CSUM))
1070 skb_checksum_help(skb);
1071 else
1072 csum_insertion = 1;
1073 }
1074
1075 desc = priv->dma_tx + entry;
1076 first = desc;
1077
1078#ifdef STMMAC_XMIT_DEBUG
1079 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1080 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1081 "\t\tn_frags: %d, ip_summed: %d\n",
1082 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1083#endif
1084 priv->tx_skbuff[entry] = skb;
1085 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1086 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1087 desc = priv->dma_tx + entry;
1088 } else {
1089 unsigned int nopaged_len = skb_headlen(skb);
1090 desc->des2 = dma_map_single(priv->device, skb->data,
1091 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1092 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1093 csum_insertion);
47dd7a54
GC		 1094 }
1095
1096 for (i = 0; i < nfrags; i++) {
1097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1098 int len = frag->size;
1099
1100 entry = (++priv->cur_tx) % txsize;
1101 desc = priv->dma_tx + entry;
1102
1103 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1104 desc->des2 = dma_map_page(priv->device, frag->page,
1105 frag->page_offset,
1106 len, DMA_TO_DEVICE);
1107 priv->tx_skbuff[entry] = NULL;
db98a0b0
GC		 1108 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1109 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1110 }
1111
1112 /* Interrupt on completition only for the latest segment */
db98a0b0 1113 priv->hw->desc->close_tx_desc(desc);
73cfe264 1114
47dd7a54 1115#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1116 /* Clean IC while using timer */
1117 if (likely(priv->tm->enable))
db98a0b0 1118 priv->hw->desc->clear_tx_ic(desc);
47dd7a54
GC		 1119#endif
1120 /* To avoid raise condition */
db98a0b0 1121 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1122
1123 priv->cur_tx++;
1124
1125#ifdef STMMAC_XMIT_DEBUG
1126 if (netif_msg_pktdata(priv)) {
1127 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1128 "first=%p, nfrags=%d\n",
1129 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1130 entry, first, nfrags);
1131 display_ring(priv->dma_tx, txsize);
1132 pr_info(">>> frame to be transmitted: ");
1133 print_pkt(skb->data, skb->len);
1134 }
1135#endif
1136 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1137 TX_DBG("%s: stop transmitted packets\n", __func__);
1138 netif_stop_queue(dev);
1139 }
1140
1141 dev->stats.tx_bytes += skb->len;
1142
ad01b7d4 1143 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
47dd7a54
GC		 1144
1145 return NETDEV_TX_OK;
1146}
1147
1148static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1149{
1150 unsigned int rxsize = priv->dma_rx_size;
1151 int bfsize = priv->dma_buf_sz;
1152 struct dma_desc *p = priv->dma_rx;
1153
1154 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1155 unsigned int entry = priv->dirty_rx % rxsize;
1156 if (likely(priv->rx_skbuff[entry] == NULL)) {
1157 struct sk_buff *skb;
1158
1159 skb = __skb_dequeue(&priv->rx_recycle);
1160 if (skb == NULL)
1161 skb = netdev_alloc_skb_ip_align(priv->dev,
1162 bfsize);
1163
1164 if (unlikely(skb == NULL))
1165 break;
1166
1167 priv->rx_skbuff[entry] = skb;
1168 priv->rx_skbuff_dma[entry] =
1169 dma_map_single(priv->device, skb->data, bfsize,
1170 DMA_FROM_DEVICE);
1171
1172 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1173 if (unlikely(priv->is_gmac)) {
1174 if (bfsize >= BUF_SIZE_8KiB)
1175 (p + entry)->des3 =
1176 (p + entry)->des2 + BUF_SIZE_8KiB;
1177 }
1178 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1179 }
db98a0b0 1180 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1181 }
47dd7a54
GC		 1182}
1183
1184static int stmmac_rx(struct stmmac_priv *priv, int limit)
1185{
1186 unsigned int rxsize = priv->dma_rx_size;
1187 unsigned int entry = priv->cur_rx % rxsize;
1188 unsigned int next_entry;
1189 unsigned int count = 0;
1190 struct dma_desc *p = priv->dma_rx + entry;
1191 struct dma_desc *p_next;
1192
1193#ifdef STMMAC_RX_DEBUG
1194 if (netif_msg_hw(priv)) {
1195 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1196 display_ring(priv->dma_rx, rxsize);
1197 }
1198#endif
1199 count = 0;
db98a0b0 1200 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1201 int status;
1202
1203 if (count >= limit)
1204 break;
1205
1206 count++;
1207
1208 next_entry = (++priv->cur_rx) % rxsize;
1209 p_next = priv->dma_rx + next_entry;
1210 prefetch(p_next);
1211
1212 /* read the status of the incoming frame */
db98a0b0
GC		 1213 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1214 &priv->xstats, p));
47dd7a54
GC		 1215 if (unlikely(status == discard_frame))
1216 priv->dev->stats.rx_errors++;
1217 else {
1218 struct sk_buff *skb;
3eeb2997 1219 int frame_len;
47dd7a54 1220
3eeb2997
GC		 1221 frame_len = priv->hw->desc->get_rx_frame_len(p);
1222 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1223 * Type frames (LLC/LLC-SNAP) */
1224 if (unlikely(status != llc_snap))
1225 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1226#ifdef STMMAC_RX_DEBUG
1227 if (frame_len > ETH_FRAME_LEN)
1228 pr_debug("\tRX frame size %d, COE status: %d\n",
1229 frame_len, status);
1230
1231 if (netif_msg_hw(priv))
1232 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1233 p, entry, p->des2);
1234#endif
1235 skb = priv->rx_skbuff[entry];
1236 if (unlikely(!skb)) {
1237 pr_err("%s: Inconsistent Rx descriptor chain\n",
1238 priv->dev->name);
1239 priv->dev->stats.rx_dropped++;
1240 break;
1241 }
1242 prefetch(skb->data - NET_IP_ALIGN);
1243 priv->rx_skbuff[entry] = NULL;
1244
1245 skb_put(skb, frame_len);
1246 dma_unmap_single(priv->device,
1247 priv->rx_skbuff_dma[entry],
1248 priv->dma_buf_sz, DMA_FROM_DEVICE);
1249#ifdef STMMAC_RX_DEBUG
1250 if (netif_msg_pktdata(priv)) {
1251 pr_info(" frame received (%dbytes)", frame_len);
1252 print_pkt(skb->data, frame_len);
1253 }
1254#endif
1255 skb->protocol = eth_type_trans(skb, priv->dev);
1256
1257 if (unlikely(status == csum_none)) {
1258 /* always for the old mac 10/100 */
bc8acf2c 1259 skb_checksum_none_assert(skb);
47dd7a54
GC		 1260 netif_receive_skb(skb);
1261 } else {
1262 skb->ip_summed = CHECKSUM_UNNECESSARY;
1263 napi_gro_receive(&priv->napi, skb);
1264 }
1265
1266 priv->dev->stats.rx_packets++;
1267 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1268 }
1269 entry = next_entry;
1270 p = p_next; /* use prefetched values */
1271 }
1272
1273 stmmac_rx_refill(priv);
1274
1275 priv->xstats.rx_pkt_n += count;
1276
1277 return count;
1278}
1279
1280/**
1281 * stmmac_poll - stmmac poll method (NAPI)
1282 * @napi : pointer to the napi structure.
1283 * @budget : maximum number of packets that the current CPU can receive from
1284 * all interfaces.
1285 * Description :
1286 * This function implements the the reception process.
1287 * Also it runs the TX completion thread
1288 */
1289static int stmmac_poll(struct napi_struct *napi, int budget)
1290{
1291 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1292 int work_done = 0;
1293
1294 priv->xstats.poll_n++;
1295 stmmac_tx(priv);
1296 work_done = stmmac_rx(priv, budget);
1297
1298 if (work_done < budget) {
1299 napi_complete(napi);
1300 stmmac_enable_irq(priv);
1301 }
1302 return work_done;
1303}
1304
1305/**
1306 * stmmac_tx_timeout
1307 * @dev : Pointer to net device structure
1308 * Description: this function is called when a packet transmission fails to
1309 * complete within a reasonable tmrate. The driver will mark the error in the
1310 * netdev structure and arrange for the device to be reset to a sane state
1311 * in order to transmit a new packet.
1312 */
1313static void stmmac_tx_timeout(struct net_device *dev)
1314{
1315 struct stmmac_priv *priv = netdev_priv(dev);
1316
1317 /* Clear Tx resources and restart transmitting again */
1318 stmmac_tx_err(priv);
47dd7a54
GC		 1319}
1320
1321/* Configuration changes (passed on by ifconfig) */
1322static int stmmac_config(struct net_device *dev, struct ifmap *map)
1323{
1324 if (dev->flags & IFF_UP) /* can't act on a running interface */
1325 return -EBUSY;
1326
1327 /* Don't allow changing the I/O address */
1328 if (map->base_addr != dev->base_addr) {
1329 pr_warning("%s: can't change I/O address\n", dev->name);
1330 return -EOPNOTSUPP;
1331 }
1332
1333 /* Don't allow changing the IRQ */
1334 if (map->irq != dev->irq) {
1335 pr_warning("%s: can't change IRQ number %d\n",
1336 dev->name, dev->irq);
1337 return -EOPNOTSUPP;
1338 }
1339
1340 /* ignore other fields */
1341 return 0;
1342}
1343
1344/**
1345 * stmmac_multicast_list - entry point for multicast addressing
1346 * @dev : pointer to the device structure
1347 * Description:
1348 * This function is a driver entry point which gets called by the kernel
1349 * whenever multicast addresses must be enabled/disabled.
1350 * Return value:
1351 * void.
1352 */
1353static void stmmac_multicast_list(struct net_device *dev)
1354{
1355 struct stmmac_priv *priv = netdev_priv(dev);
1356
1357 spin_lock(&priv->lock);
db98a0b0 1358 priv->hw->mac->set_filter(dev);
47dd7a54 1359 spin_unlock(&priv->lock);
47dd7a54
GC		 1360}
1361
1362/**
1363 * stmmac_change_mtu - entry point to change MTU size for the device.
1364 * @dev : device pointer.
1365 * @new_mtu : the new MTU size for the device.
1366 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1367 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1368 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1369 * Return value:
1370 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1371 * file on failure.
1372 */
1373static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1374{
1375 struct stmmac_priv *priv = netdev_priv(dev);
1376 int max_mtu;
1377
1378 if (netif_running(dev)) {
1379 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1380 return -EBUSY;
1381 }
1382
1383 if (priv->is_gmac)
1384 max_mtu = JUMBO_LEN;
1385 else
1386 max_mtu = ETH_DATA_LEN;
1387
1388 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1389 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1390 return -EINVAL;
1391 }
1392
1393 dev->mtu = new_mtu;
1394
1395 return 0;
1396}
1397
1398static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1399{
1400 struct net_device *dev = (struct net_device *)dev_id;
1401 struct stmmac_priv *priv = netdev_priv(dev);
1402
1403 if (unlikely(!dev)) {
1404 pr_err("%s: invalid dev pointer\n", __func__);
1405 return IRQ_NONE;
1406 }
1407
ad01b7d4 1408 if (priv->is_gmac)
47dd7a54 1409 /* To handle GMAC own interrupts */
ad01b7d4 1410 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1411
1412 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1413
1414 return IRQ_HANDLED;
1415}
1416
1417#ifdef CONFIG_NET_POLL_CONTROLLER
1418/* Polling receive - used by NETCONSOLE and other diagnostic tools
1419 * to allow network I/O with interrupts disabled. */
1420static void stmmac_poll_controller(struct net_device *dev)
1421{
1422 disable_irq(dev->irq);
1423 stmmac_interrupt(dev->irq, dev);
1424 enable_irq(dev->irq);
1425}
1426#endif
1427
1428/**
1429 * stmmac_ioctl - Entry point for the Ioctl
1430 * @dev: Device pointer.
1431 * @rq: An IOCTL specefic structure, that can contain a pointer to
1432 * a proprietary structure used to pass information to the driver.
1433 * @cmd: IOCTL command
1434 * Description:
1435 * Currently there are no special functionality supported in IOCTL, just the
1436 * phy_mii_ioctl(...) can be invoked.
1437 */
1438static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1439{
1440 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1441 int ret;
47dd7a54
GC		 1442
1443 if (!netif_running(dev))
1444 return -EINVAL;
1445
28b04113
RC		 1446 if (!priv->phydev)
1447 return -EINVAL;
1448
1449 spin_lock(&priv->lock);
1450 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1451 spin_unlock(&priv->lock);
1452
47dd7a54
GC		 1453 return ret;
1454}
1455
1456#ifdef STMMAC_VLAN_TAG_USED
1457static void stmmac_vlan_rx_register(struct net_device *dev,
1458 struct vlan_group *grp)
1459{
1460 struct stmmac_priv *priv = netdev_priv(dev);
1461
1462 DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1463
1464 spin_lock(&priv->lock);
1465 priv->vlgrp = grp;
1466 spin_unlock(&priv->lock);
47dd7a54
GC		 1467}
1468#endif
1469
1470static const struct net_device_ops stmmac_netdev_ops = {
1471 .ndo_open = stmmac_open,
1472 .ndo_start_xmit = stmmac_xmit,
1473 .ndo_stop = stmmac_release,
1474 .ndo_change_mtu = stmmac_change_mtu,
1475 .ndo_set_multicast_list = stmmac_multicast_list,
1476 .ndo_tx_timeout = stmmac_tx_timeout,
1477 .ndo_do_ioctl = stmmac_ioctl,
1478 .ndo_set_config = stmmac_config,
1479#ifdef STMMAC_VLAN_TAG_USED
1480 .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1481#endif
1482#ifdef CONFIG_NET_POLL_CONTROLLER
1483 .ndo_poll_controller = stmmac_poll_controller,
1484#endif
1485 .ndo_set_mac_address = eth_mac_addr,
1486};
1487
1488/**
1489 * stmmac_probe - Initialization of the adapter .
1490 * @dev : device pointer
1491 * Description: The function initializes the network device structure for
1492 * the STMMAC driver. It also calls the low level routines
1493 * in order to init the HW (i.e. the DMA engine)
1494 */
1495static int stmmac_probe(struct net_device *dev)
1496{
1497 int ret = 0;
1498 struct stmmac_priv *priv = netdev_priv(dev);
1499
1500 ether_setup(dev);
1501
1502 dev->netdev_ops = &stmmac_netdev_ops;
1503 stmmac_set_ethtool_ops(dev);
1504
1505 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1506 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1507#ifdef STMMAC_VLAN_TAG_USED
1508 /* Both mac100 and gmac support receive VLAN tag detection */
1509 dev->features |= NETIF_F_HW_VLAN_RX;
1510#endif
1511 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1512
1513 if (priv->is_gmac)
1514 priv->rx_csum = 1;
1515
1516 if (flow_ctrl)
1517 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1518
1519 priv->pause = pause;
1520 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1521
1522 /* Get the MAC address */
ad01b7d4
GC		 1523 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1524 dev->dev_addr, 0);
47dd7a54
GC		 1525
1526 if (!is_valid_ether_addr(dev->dev_addr))
1527 pr_warning("\tno valid MAC address;"
1528 "please, use ifconfig or nwhwconfig!\n");
1529
1530 ret = register_netdev(dev);
1531 if (ret) {
1532 pr_err("%s: ERROR %i registering the device\n",
1533 __func__, ret);
1534 return -ENODEV;
1535 }
1536
1537 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1538 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1539 (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1540
1541 spin_lock_init(&priv->lock);
1542
1543 return ret;
1544}
1545
1546/**
1547 * stmmac_mac_device_setup
1548 * @dev : device pointer
1549 * Description: select and initialise the mac device (mac100 or Gmac).
1550 */
1551static int stmmac_mac_device_setup(struct net_device *dev)
1552{
1553 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1554
1555 struct mac_device_info *device;
1556
3d90c508 1557 if (priv->is_gmac)
ad01b7d4 1558 device = dwmac1000_setup(priv->ioaddr);
3d90c508 1559 else
ad01b7d4 1560 device = dwmac100_setup(priv->ioaddr);
3d90c508 1561
1ff21906
DC		 1562 if (!device)
1563 return -ENOMEM;
1564
3d90c508
GC		 1565 if (priv->enh_desc) {
1566 device->desc = &enh_desc_ops;
1567 pr_info("\tEnhanced descriptor structure\n");
1568 } else
56b106ae 1569 device->desc = &ndesc_ops;
47dd7a54 1570
db98a0b0 1571 priv->hw = device;
47dd7a54 1572
db98a0b0 1573 priv->wolenabled = priv->hw->pmt; /* PMT supported */
47dd7a54
GC		 1574 if (priv->wolenabled == PMT_SUPPORTED)
1575 priv->wolopts = WAKE_MAGIC; /* Magic Frame */
1576
1577 return 0;
1578}
1579
1580static int stmmacphy_dvr_probe(struct platform_device *pdev)
1581{
ee7946a7 1582 struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1583
1584 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1585 plat_dat->bus_id);
1586
1587 return 0;
1588}
1589
1590static int stmmacphy_dvr_remove(struct platform_device *pdev)
1591{
1592 return 0;
1593}
1594
1595static struct platform_driver stmmacphy_driver = {
1596 .driver = {
1597 .name = PHY_RESOURCE_NAME,
1598 },
1599 .probe = stmmacphy_dvr_probe,
1600 .remove = stmmacphy_dvr_remove,
1601};
1602
1603/**
1604 * stmmac_associate_phy
1605 * @dev: pointer to device structure
1606 * @data: points to the private structure.
1607 * Description: Scans through all the PHYs we have registered and checks if
1608 * any are associated with our MAC. If so, then just fill in
1609 * the blanks in our local context structure
1610 */
1611static int stmmac_associate_phy(struct device *dev, void *data)
1612{
1613 struct stmmac_priv *priv = (struct stmmac_priv *)data;
ee7946a7 1614 struct plat_stmmacphy_data *plat_dat = dev->platform_data;
47dd7a54
GC		 1615
1616 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1617 plat_dat->bus_id);
1618
1619 /* Check that this phy is for the MAC being initialised */
1620 if (priv->bus_id != plat_dat->bus_id)
1621 return 0;
1622
1623 /* OK, this PHY is connected to the MAC.
1624 Go ahead and get the parameters */
1625 DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1626 priv->phy_irq =
1627 platform_get_irq_byname(to_platform_device(dev), "phyirq");
1628 DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1629 plat_dat->bus_id, priv->phy_irq);
1630
1631 /* Override with kernel parameters if supplied XXX CRS XXX
1632 * this needs to have multiple instances */
1633 if ((phyaddr >= 0) && (phyaddr <= 31))
1634 plat_dat->phy_addr = phyaddr;
1635
1636 priv->phy_addr = plat_dat->phy_addr;
1637 priv->phy_mask = plat_dat->phy_mask;
1638 priv->phy_interface = plat_dat->interface;
1639 priv->phy_reset = plat_dat->phy_reset;
1640
1641 DBG(probe, DEBUG, "%s: exiting\n", __func__);
1642 return 1; /* forces exit of driver_for_each_device() */
1643}
1644
1645/**
1646 * stmmac_dvr_probe
1647 * @pdev: platform device pointer
1648 * Description: the driver is initialized through platform_device.
1649 */
1650static int stmmac_dvr_probe(struct platform_device *pdev)
1651{
1652 int ret = 0;
1653 struct resource *res;
ad01b7d4 1654 void __iomem *addr = NULL;
47dd7a54
GC		 1655 struct net_device *ndev = NULL;
1656 struct stmmac_priv *priv;
1657 struct plat_stmmacenet_data *plat_dat;
1658
1659 pr_info("STMMAC driver:\n\tplatform registration... ");
1660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1661 if (!res) {
1662 ret = -ENODEV;
1663 goto out;
1664 }
1665 pr_info("done!\n");
1666
b6222682 1667 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1668 pdev->name)) {
1669 pr_err("%s: ERROR: memory allocation failed"
1670 "cannot get the I/O addr 0x%x\n",
1671 __func__, (unsigned int)res->start);
1672 ret = -EBUSY;
1673 goto out;
1674 }
1675
7c5365bc 1676 addr = ioremap(res->start, resource_size(res));
47dd7a54 1677 if (!addr) {
7c5365bc 1678 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54
GC		 1679 ret = -ENOMEM;
1680 goto out;
1681 }
1682
1683 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1684 if (!ndev) {
1685 pr_err("%s: ERROR: allocating the device\n", __func__);
1686 ret = -ENOMEM;
1687 goto out;
1688 }
1689
1690 SET_NETDEV_DEV(ndev, &pdev->dev);
1691
1692 /* Get the MAC information */
1693 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1694 if (ndev->irq == -ENXIO) {
1695 pr_err("%s: ERROR: MAC IRQ configuration "
1696 "information not found\n", __func__);
1697 ret = -ENODEV;
1698 goto out;
1699 }
1700
1701 priv = netdev_priv(ndev);
1702 priv->device = &(pdev->dev);
1703 priv->dev = ndev;
ee7946a7 1704 plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1705 priv->bus_id = plat_dat->bus_id;
1706 priv->pbl = plat_dat->pbl; /* TLI */
dfb8fb96 1707 priv->mii_clk_csr = plat_dat->clk_csr;
47dd7a54 1708 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
3d90c508 1709 priv->enh_desc = plat_dat->enh_desc;
ad01b7d4 1710 priv->ioaddr = addr;
47dd7a54
GC		 1711
1712 platform_set_drvdata(pdev, ndev);
1713
1714 /* Set the I/O base addr */
1715 ndev->base_addr = (unsigned long)addr;
1716
ee7946a7
GC		 1717 /* Verify embedded resource for the platform */
1718 ret = stmmac_claim_resource(pdev);
1719 if (ret < 0)
1720 goto out;
1721
47dd7a54
GC		 1722 /* MAC HW revice detection */
1723 ret = stmmac_mac_device_setup(ndev);
1724 if (ret < 0)
1725 goto out;
1726
1727 /* Network Device Registration */
1728 ret = stmmac_probe(ndev);
1729 if (ret < 0)
1730 goto out;
1731
1732 /* associate a PHY - it is provided by another platform bus */
1733 if (!driver_for_each_device
1734 (&(stmmacphy_driver.driver), NULL, (void *)priv,
1735 stmmac_associate_phy)) {
1736 pr_err("No PHY device is associated with this MAC!\n");
1737 ret = -ENODEV;
1738 goto out;
1739 }
1740
1741 priv->fix_mac_speed = plat_dat->fix_mac_speed;
ee7946a7 1742 priv->bus_setup = plat_dat->bus_setup;
47dd7a54
GC		 1743 priv->bsp_priv = plat_dat->bsp_priv;
1744
1745 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1746 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1747 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1748
1749 /* MDIO bus Registration */
1750 pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1751 ret = stmmac_mdio_register(ndev);
1752 if (ret < 0)
1753 goto out;
1754 pr_debug("registered!\n");
1755
1756out:
1757 if (ret < 0) {
1758 platform_set_drvdata(pdev, NULL);
7c5365bc 1759 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1760 if (addr != NULL)
1761 iounmap(addr);
1762 }
1763
1764 return ret;
1765}
1766
1767/**
1768 * stmmac_dvr_remove
1769 * @pdev: platform device pointer
1770 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1771 * changes the link status, releases the DMA descriptor rings,
1772 * unregisters the MDIO bus and unmaps the allocated memory.
1773 */
1774static int stmmac_dvr_remove(struct platform_device *pdev)
1775{
1776 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1777 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1778 struct resource *res;
1779
1780 pr_info("%s:\n\tremoving driver", __func__);
1781
ad01b7d4
GC		 1782 priv->hw->dma->stop_rx(priv->ioaddr);
1783 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1784
ad01b7d4
GC		 1785 stmmac_mac_disable_rx(priv->ioaddr);
1786 stmmac_mac_disable_tx(priv->ioaddr);
47dd7a54
GC		 1787
1788 netif_carrier_off(ndev);
1789
1790 stmmac_mdio_unregister(ndev);
1791
1792 platform_set_drvdata(pdev, NULL);
1793 unregister_netdev(ndev);
1794
ad01b7d4 1795 iounmap((void *)priv->ioaddr);
47dd7a54 1796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1797 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1798
1799 free_netdev(ndev);
1800
1801 return 0;
1802}
1803
1804#ifdef CONFIG_PM
1805static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
1806{
1807 struct net_device *dev = platform_get_drvdata(pdev);
1808 struct stmmac_priv *priv = netdev_priv(dev);
1809 int dis_ic = 0;
1810
1811 if (!dev || !netif_running(dev))
1812 return 0;
1813
1814 spin_lock(&priv->lock);
1815
1816 if (state.event == PM_EVENT_SUSPEND) {
1817 netif_device_detach(dev);
1818 netif_stop_queue(dev);
1819 if (priv->phydev)
1820 phy_stop(priv->phydev);
1821
1822#ifdef CONFIG_STMMAC_TIMER
1823 priv->tm->timer_stop();
73cfe264
GC		 1824 if (likely(priv->tm->enable))
1825 dis_ic = 1;
47dd7a54
GC		 1826#endif
1827 napi_disable(&priv->napi);
1828
1829 /* Stop TX/RX DMA */
ad01b7d4
GC		 1830 priv->hw->dma->stop_tx(priv->ioaddr);
1831 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54 1832 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 1833 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1834 dis_ic);
1835 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54 1836
ad01b7d4 1837 stmmac_mac_disable_tx(priv->ioaddr);
47dd7a54
GC		 1838
1839 if (device_may_wakeup(&(pdev->dev))) {
1840 /* Enable Power down mode by programming the PMT regs */
1841 if (priv->wolenabled == PMT_SUPPORTED)
ad01b7d4 1842 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
47dd7a54 1843 } else {
ad01b7d4 1844 stmmac_mac_disable_rx(priv->ioaddr);
47dd7a54
GC		 1845 }
1846 } else {
1847 priv->shutdown = 1;
1848 /* Although this can appear slightly redundant it actually
1849 * makes fast the standby operation and guarantees the driver
1850 * working if hibernation is on media. */
1851 stmmac_release(dev);
1852 }
1853
1854 spin_unlock(&priv->lock);
1855 return 0;
1856}
1857
1858static int stmmac_resume(struct platform_device *pdev)
1859{
1860 struct net_device *dev = platform_get_drvdata(pdev);
1861 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1862
1863 if (!netif_running(dev))
1864 return 0;
1865
47dd7a54
GC		 1866 if (priv->shutdown) {
1867 /* Re-open the interface and re-init the MAC/DMA
c4433be6 1868 and the rings (i.e. on hibernation stage) */
47dd7a54 1869 stmmac_open(dev);
c4433be6 1870 return 0;
47dd7a54
GC		 1871 }
1872
c4433be6
GC		 1873 spin_lock(&priv->lock);
1874
47dd7a54
GC		 1875 /* Power Down bit, into the PM register, is cleared
1876 * automatically as soon as a magic packet or a Wake-up frame
1877 * is received. Anyway, it's better to manually clear
1878 * this bit because it can generate problems while resuming
1879 * from another devices (e.g. serial console). */
1880 if (device_may_wakeup(&(pdev->dev)))
1881 if (priv->wolenabled == PMT_SUPPORTED)
ad01b7d4 1882 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54
GC		 1883
1884 netif_device_attach(dev);
1885
1886 /* Enable the MAC and DMA */
ad01b7d4
GC		 1887 stmmac_mac_enable_rx(priv->ioaddr);
1888 stmmac_mac_enable_tx(priv->ioaddr);
1889 priv->hw->dma->start_tx(priv->ioaddr);
1890 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 1891
1892#ifdef CONFIG_STMMAC_TIMER
1893 priv->tm->timer_start(tmrate);
1894#endif
1895 napi_enable(&priv->napi);
1896
1897 if (priv->phydev)
1898 phy_start(priv->phydev);
1899
1900 netif_start_queue(dev);
1901
47dd7a54
GC		 1902 spin_unlock(&priv->lock);
1903 return 0;
1904}
1905#endif
1906
1907static struct platform_driver stmmac_driver = {
1908 .driver = {
1909 .name = STMMAC_RESOURCE_NAME,
1910 },
1911 .probe = stmmac_dvr_probe,
1912 .remove = stmmac_dvr_remove,
1913#ifdef CONFIG_PM
1914 .suspend = stmmac_suspend,
1915 .resume = stmmac_resume,
1916#endif
1917
1918};
1919
1920/**
1921 * stmmac_init_module - Entry point for the driver
1922 * Description: This function is the entry point for the driver.
1923 */
1924static int __init stmmac_init_module(void)
1925{
1926 int ret;
1927
1928 if (platform_driver_register(&stmmacphy_driver)) {
1929 pr_err("No PHY devices registered!\n");
1930 return -ENODEV;
1931 }
1932
1933 ret = platform_driver_register(&stmmac_driver);
1934 return ret;
1935}
1936
1937/**
1938 * stmmac_cleanup_module - Cleanup routine for the driver
1939 * Description: This function is the cleanup routine for the driver.
1940 */
1941static void __exit stmmac_cleanup_module(void)
1942{
1943 platform_driver_unregister(&stmmacphy_driver);
1944 platform_driver_unregister(&stmmac_driver);
1945}
1946
1947#ifndef MODULE
1948static int __init stmmac_cmdline_opt(char *str)
1949{
1950 char *opt;
1951
1952 if (!str || !*str)
1953 return -EINVAL;
1954 while ((opt = strsep(&str, ",")) != NULL) {
1955 if (!strncmp(opt, "debug:", 6))
1956 strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
1957 else if (!strncmp(opt, "phyaddr:", 8))
1958 strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
1959 else if (!strncmp(opt, "dma_txsize:", 11))
1960 strict_strtoul(opt + 11, 0,
1961 (unsigned long *)&dma_txsize);
1962 else if (!strncmp(opt, "dma_rxsize:", 11))
1963 strict_strtoul(opt + 11, 0,
1964 (unsigned long *)&dma_rxsize);
1965 else if (!strncmp(opt, "buf_sz:", 7))
1966 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
1967 else if (!strncmp(opt, "tc:", 3))
1968 strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
1969 else if (!strncmp(opt, "tx_coe:", 7))
1970 strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
1971 else if (!strncmp(opt, "watchdog:", 9))
1972 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
1973 else if (!strncmp(opt, "flow_ctrl:", 10))
1974 strict_strtoul(opt + 10, 0,
1975 (unsigned long *)&flow_ctrl);
1976 else if (!strncmp(opt, "pause:", 6))
1977 strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
1978#ifdef CONFIG_STMMAC_TIMER
1979 else if (!strncmp(opt, "tmrate:", 7))
1980 strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
1981#endif
1982 }
1983 return 0;
1984}
1985
1986__setup("stmmaceth=", stmmac_cmdline_opt);
1987#endif
1988
1989module_init(stmmac_init_module);
1990module_exit(stmmac_cleanup_module);
1991
1992MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
1993MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
1994MODULE_LICENSE("GPL");
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