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[net-next-2.6.git] / drivers / net / stmmac / stmmac_main.c
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47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
5a0e3ad6 47#include <linux/slab.h>
47dd7a54
GC		 48#include "stmmac.h"
49
50#define STMMAC_RESOURCE_NAME "stmmaceth"
51#define PHY_RESOURCE_NAME "stmmacphy"
52
53#undef STMMAC_DEBUG
54/*#define STMMAC_DEBUG*/
55#ifdef STMMAC_DEBUG
56#define DBG(nlevel, klevel, fmt, args...) \
57 ((void)(netif_msg_##nlevel(priv) && \
58 printk(KERN_##klevel fmt, ## args)))
59#else
60#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61#endif
62
63#undef STMMAC_RX_DEBUG
64/*#define STMMAC_RX_DEBUG*/
65#ifdef STMMAC_RX_DEBUG
66#define RX_DBG(fmt, args...) printk(fmt, ## args)
67#else
68#define RX_DBG(fmt, args...) do { } while (0)
69#endif
70
71#undef STMMAC_XMIT_DEBUG
72/*#define STMMAC_XMIT_DEBUG*/
73#ifdef STMMAC_TX_DEBUG
74#define TX_DBG(fmt, args...) printk(fmt, ## args)
75#else
76#define TX_DBG(fmt, args...) do { } while (0)
77#endif
78
79#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
80#define JUMBO_LEN 9000
81
82/* Module parameters */
83#define TX_TIMEO 5000 /* default 5 seconds */
84static int watchdog = TX_TIMEO;
85module_param(watchdog, int, S_IRUGO | S_IWUSR);
86MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
87
88static int debug = -1; /* -1: default, 0: no output, 16: all */
89module_param(debug, int, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
91
92static int phyaddr = -1;
93module_param(phyaddr, int, S_IRUGO);
94MODULE_PARM_DESC(phyaddr, "Physical device address");
95
96#define DMA_TX_SIZE 256
97static int dma_txsize = DMA_TX_SIZE;
98module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
99MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
100
101#define DMA_RX_SIZE 256
102static int dma_rxsize = DMA_RX_SIZE;
103module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
104MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
105
106static int flow_ctrl = FLOW_OFF;
107module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
108MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
109
110static int pause = PAUSE_TIME;
111module_param(pause, int, S_IRUGO | S_IWUSR);
112MODULE_PARM_DESC(pause, "Flow Control Pause Time");
113
114#define TC_DEFAULT 64
115static int tc = TC_DEFAULT;
116module_param(tc, int, S_IRUGO | S_IWUSR);
117MODULE_PARM_DESC(tc, "DMA threshold control value");
118
119#define RX_NO_COALESCE 1 /* Always interrupt on completion */
120#define TX_NO_COALESCE -1 /* No moderation by default */
121
122/* Pay attention to tune this parameter; take care of both
123 * hardware capability and network stabitily/performance impact.
124 * Many tests showed that ~4ms latency seems to be good enough. */
125#ifdef CONFIG_STMMAC_TIMER
126#define DEFAULT_PERIODIC_RATE 256
127static int tmrate = DEFAULT_PERIODIC_RATE;
128module_param(tmrate, int, S_IRUGO | S_IWUSR);
129MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
130#endif
131
132#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
133static int buf_sz = DMA_BUFFER_SIZE;
134module_param(buf_sz, int, S_IRUGO | S_IWUSR);
135MODULE_PARM_DESC(buf_sz, "DMA buffer size");
136
137/* In case of Giga ETH, we can enable/disable the COE for the
138 * transmit HW checksum computation.
139 * Note that, if tx csum is off in HW, SG will be still supported. */
140static int tx_coe = HW_CSUM;
141module_param(tx_coe, int, S_IRUGO | S_IWUSR);
142MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
143
144static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
145 NETIF_MSG_LINK | NETIF_MSG_IFUP |
146 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
147
148static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
149static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
150
151/**
152 * stmmac_verify_args - verify the driver parameters.
153 * Description: it verifies if some wrong parameter is passed to the driver.
154 * Note that wrong parameters are replaced with the default values.
155 */
156static void stmmac_verify_args(void)
157{
158 if (unlikely(watchdog < 0))
159 watchdog = TX_TIMEO;
160 if (unlikely(dma_rxsize < 0))
161 dma_rxsize = DMA_RX_SIZE;
162 if (unlikely(dma_txsize < 0))
163 dma_txsize = DMA_TX_SIZE;
164 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
165 buf_sz = DMA_BUFFER_SIZE;
166 if (unlikely(flow_ctrl > 1))
167 flow_ctrl = FLOW_AUTO;
168 else if (likely(flow_ctrl < 0))
169 flow_ctrl = FLOW_OFF;
170 if (unlikely((pause < 0) || (pause > 0xffff)))
171 pause = PAUSE_TIME;
47dd7a54
GC		 172}
173
174#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
175static void print_pkt(unsigned char *buf, int len)
176{
177 int j;
178 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
179 for (j = 0; j < len; j++) {
180 if ((j % 16) == 0)
181 pr_info("\n %03x:", j);
182 pr_info(" %02x", buf[j]);
183 }
184 pr_info("\n");
47dd7a54
GC		 185}
186#endif
187
188/* minimum number of free TX descriptors required to wake up TX process */
189#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
190
191static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
192{
193 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
194}
195
196/**
197 * stmmac_adjust_link
198 * @dev: net device structure
199 * Description: it adjusts the link parameters.
200 */
201static void stmmac_adjust_link(struct net_device *dev)
202{
203 struct stmmac_priv *priv = netdev_priv(dev);
204 struct phy_device *phydev = priv->phydev;
205 unsigned long ioaddr = dev->base_addr;
206 unsigned long flags;
207 int new_state = 0;
208 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
209
210 if (phydev == NULL)
211 return;
212
213 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
214 phydev->addr, phydev->link);
215
216 spin_lock_irqsave(&priv->lock, flags);
217 if (phydev->link) {
218 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
219
220 /* Now we make sure that we can be in full duplex mode.
221 * If not, we operate in half-duplex mode. */
222 if (phydev->duplex != priv->oldduplex) {
223 new_state = 1;
224 if (!(phydev->duplex))
db98a0b0 225 ctrl &= ~priv->hw->link.duplex;
47dd7a54 226 else
db98a0b0 227 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 228 priv->oldduplex = phydev->duplex;
229 }
230 /* Flow Control operation */
231 if (phydev->pause)
db98a0b0
GC		 232 priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex,
233 fc, pause_time);
47dd7a54
GC		 234
235 if (phydev->speed != priv->speed) {
236 new_state = 1;
237 switch (phydev->speed) {
238 case 1000:
239 if (likely(priv->is_gmac))
db98a0b0 240 ctrl &= ~priv->hw->link.port;
47dd7a54
GC		 241 break;
242 case 100:
243 case 10:
244 if (priv->is_gmac) {
db98a0b0 245 ctrl |= priv->hw->link.port;
47dd7a54 246 if (phydev->speed == SPEED_100) {
db98a0b0 247 ctrl |= priv->hw->link.speed;
47dd7a54 248 } else {
db98a0b0 249 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 250 }
251 } else {
db98a0b0 252 ctrl &= ~priv->hw->link.port;
47dd7a54 253 }
65818fa7
GC		 254 if (likely(priv->fix_mac_speed))
255 priv->fix_mac_speed(priv->bsp_priv,
256 phydev->speed);
47dd7a54
GC		 257 break;
258 default:
259 if (netif_msg_link(priv))
260 pr_warning("%s: Speed (%d) is not 10"
261 " or 100!\n", dev->name, phydev->speed);
262 break;
263 }
264
265 priv->speed = phydev->speed;
266 }
267
268 writel(ctrl, ioaddr + MAC_CTRL_REG);
269
270 if (!priv->oldlink) {
271 new_state = 1;
272 priv->oldlink = 1;
273 }
274 } else if (priv->oldlink) {
275 new_state = 1;
276 priv->oldlink = 0;
277 priv->speed = 0;
278 priv->oldduplex = -1;
279 }
280
281 if (new_state && netif_msg_link(priv))
282 phy_print_status(phydev);
283
284 spin_unlock_irqrestore(&priv->lock, flags);
285
286 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
287}
288
289/**
290 * stmmac_init_phy - PHY initialization
291 * @dev: net device structure
292 * Description: it initializes the driver's PHY state, and attaches the PHY
293 * to the mac driver.
294 * Return value:
295 * 0 on success
296 */
297static int stmmac_init_phy(struct net_device *dev)
298{
299 struct stmmac_priv *priv = netdev_priv(dev);
300 struct phy_device *phydev;
109cdd66
GC		 301 char phy_id[MII_BUS_ID_SIZE + 3];
302 char bus_id[MII_BUS_ID_SIZE];
47dd7a54
GC		 303
304 priv->oldlink = 0;
305 priv->speed = 0;
306 priv->oldduplex = -1;
307
308 if (priv->phy_addr == -1) {
309 /* We don't have a PHY, so do nothing */
310 return 0;
311 }
312
313 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
109cdd66
GC		 314 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
315 priv->phy_addr);
47dd7a54
GC		 316 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
317
318 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
319 priv->phy_interface);
320
321 if (IS_ERR(phydev)) {
322 pr_err("%s: Could not attach to PHY\n", dev->name);
323 return PTR_ERR(phydev);
324 }
325
326 /*
327 * Broken HW is sometimes missing the pull-up resistor on the
328 * MDIO line, which results in reads to non-existent devices returning
329 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
330 * device as well.
331 * Note: phydev->phy_id is the result of reading the UID PHY registers.
332 */
333 if (phydev->phy_id == 0) {
334 phy_disconnect(phydev);
335 return -ENODEV;
336 }
337 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
338 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
339
340 priv->phydev = phydev;
341
342 return 0;
343}
344
345static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
346{
347 u32 value = readl(ioaddr + MAC_CTRL_REG);
348 value |= MAC_RNABLE_RX;
349 /* Set the RE (receive enable bit into the MAC CTRL register). */
350 writel(value, ioaddr + MAC_CTRL_REG);
351}
352
353static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
354{
355 u32 value = readl(ioaddr + MAC_CTRL_REG);
356 value |= MAC_ENABLE_TX;
357 /* Set the TE (transmit enable bit into the MAC CTRL register). */
358 writel(value, ioaddr + MAC_CTRL_REG);
359}
360
361static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
362{
363 u32 value = readl(ioaddr + MAC_CTRL_REG);
364 value &= ~MAC_RNABLE_RX;
365 writel(value, ioaddr + MAC_CTRL_REG);
366}
367
368static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
369{
370 u32 value = readl(ioaddr + MAC_CTRL_REG);
371 value &= ~MAC_ENABLE_TX;
372 writel(value, ioaddr + MAC_CTRL_REG);
373}
374
375/**
376 * display_ring
377 * @p: pointer to the ring.
378 * @size: size of the ring.
379 * Description: display all the descriptors within the ring.
380 */
381static void display_ring(struct dma_desc *p, int size)
382{
383 struct tmp_s {
384 u64 a;
385 unsigned int b;
386 unsigned int c;
387 };
388 int i;
389 for (i = 0; i < size; i++) {
390 struct tmp_s *x = (struct tmp_s *)(p + i);
391 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
392 i, (unsigned int)virt_to_phys(&p[i]),
393 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
394 x->b, x->c);
395 pr_info("\n");
396 }
397}
398
399/**
400 * init_dma_desc_rings - init the RX/TX descriptor rings
401 * @dev: net device structure
402 * Description: this function initializes the DMA RX/TX descriptors
403 * and allocates the socket buffers.
404 */
405static void init_dma_desc_rings(struct net_device *dev)
406{
407 int i;
408 struct stmmac_priv *priv = netdev_priv(dev);
409 struct sk_buff *skb;
410 unsigned int txsize = priv->dma_tx_size;
411 unsigned int rxsize = priv->dma_rx_size;
412 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 413 int buff2_needed = 0, dis_ic = 0;
47dd7a54 414
47dd7a54
GC		 415 /* Set the Buffer size according to the MTU;
416 * indeed, in case of jumbo we need to bump-up the buffer sizes.
417 */
418 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
419 bfsize = BUF_SIZE_16KiB;
420 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
421 bfsize = BUF_SIZE_8KiB;
422 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
423 bfsize = BUF_SIZE_4KiB;
424 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
425 bfsize = BUF_SIZE_2KiB;
426 else
427 bfsize = DMA_BUFFER_SIZE;
428
73cfe264
GC		 429#ifdef CONFIG_STMMAC_TIMER
430 /* Disable interrupts on completion for the reception if timer is on */
431 if (likely(priv->tm->enable))
432 dis_ic = 1;
433#endif
47dd7a54
GC		 434 /* If the MTU exceeds 8k so use the second buffer in the chain */
435 if (bfsize >= BUF_SIZE_8KiB)
436 buff2_needed = 1;
437
438 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
439 txsize, rxsize, bfsize);
440
441 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
442 priv->rx_skbuff =
443 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
444 priv->dma_rx =
445 (struct dma_desc *)dma_alloc_coherent(priv->device,
446 rxsize *
447 sizeof(struct dma_desc),
448 &priv->dma_rx_phy,
449 GFP_KERNEL);
450 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
451 GFP_KERNEL);
452 priv->dma_tx =
453 (struct dma_desc *)dma_alloc_coherent(priv->device,
454 txsize *
455 sizeof(struct dma_desc),
456 &priv->dma_tx_phy,
457 GFP_KERNEL);
458
459 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
460 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
461 return;
462 }
463
464 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
465 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
466 dev->name, priv->dma_rx, priv->dma_tx,
467 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
468
469 /* RX INITIALIZATION */
470 DBG(probe, INFO, "stmmac: SKB addresses:\n"
471 "skb\t\tskb data\tdma data\n");
472
473 for (i = 0; i < rxsize; i++) {
474 struct dma_desc *p = priv->dma_rx + i;
475
476 skb = netdev_alloc_skb_ip_align(dev, bfsize);
477 if (unlikely(skb == NULL)) {
478 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
479 break;
480 }
481 priv->rx_skbuff[i] = skb;
482 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
483 bfsize, DMA_FROM_DEVICE);
484
485 p->des2 = priv->rx_skbuff_dma[i];
486 if (unlikely(buff2_needed))
487 p->des3 = p->des2 + BUF_SIZE_8KiB;
488 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
489 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
490 }
491 priv->cur_rx = 0;
492 priv->dirty_rx = (unsigned int)(i - rxsize);
493 priv->dma_buf_sz = bfsize;
494 buf_sz = bfsize;
495
496 /* TX INITIALIZATION */
497 for (i = 0; i < txsize; i++) {
498 priv->tx_skbuff[i] = NULL;
499 priv->dma_tx[i].des2 = 0;
500 }
501 priv->dirty_tx = 0;
502 priv->cur_tx = 0;
503
504 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 505 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
506 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 507
508 if (netif_msg_hw(priv)) {
509 pr_info("RX descriptor ring:\n");
510 display_ring(priv->dma_rx, rxsize);
511 pr_info("TX descriptor ring:\n");
512 display_ring(priv->dma_tx, txsize);
513 }
47dd7a54
GC		 514}
515
516static void dma_free_rx_skbufs(struct stmmac_priv *priv)
517{
518 int i;
519
520 for (i = 0; i < priv->dma_rx_size; i++) {
521 if (priv->rx_skbuff[i]) {
522 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
523 priv->dma_buf_sz, DMA_FROM_DEVICE);
524 dev_kfree_skb_any(priv->rx_skbuff[i]);
525 }
526 priv->rx_skbuff[i] = NULL;
527 }
47dd7a54
GC		 528}
529
530static void dma_free_tx_skbufs(struct stmmac_priv *priv)
531{
532 int i;
533
534 for (i = 0; i < priv->dma_tx_size; i++) {
535 if (priv->tx_skbuff[i] != NULL) {
536 struct dma_desc *p = priv->dma_tx + i;
537 if (p->des2)
538 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 539 priv->hw->desc->get_tx_len(p),
540 DMA_TO_DEVICE);
47dd7a54
GC		 541 dev_kfree_skb_any(priv->tx_skbuff[i]);
542 priv->tx_skbuff[i] = NULL;
543 }
544 }
47dd7a54
GC		 545}
546
547static void free_dma_desc_resources(struct stmmac_priv *priv)
548{
549 /* Release the DMA TX/RX socket buffers */
550 dma_free_rx_skbufs(priv);
551 dma_free_tx_skbufs(priv);
552
553 /* Free the region of consistent memory previously allocated for
554 * the DMA */
555 dma_free_coherent(priv->device,
556 priv->dma_tx_size * sizeof(struct dma_desc),
557 priv->dma_tx, priv->dma_tx_phy);
558 dma_free_coherent(priv->device,
559 priv->dma_rx_size * sizeof(struct dma_desc),
560 priv->dma_rx, priv->dma_rx_phy);
561 kfree(priv->rx_skbuff_dma);
562 kfree(priv->rx_skbuff);
563 kfree(priv->tx_skbuff);
47dd7a54
GC		 564}
565
47dd7a54
GC		 566/**
567 * stmmac_dma_operation_mode - HW DMA operation mode
568 * @priv : pointer to the private device structure.
569 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
570 * or Store-And-Forward capability. It also verifies the COE for the
571 * transmission in case of Giga ETH.
572 */
573static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
574{
575 if (!priv->is_gmac) {
576 /* MAC 10/100 */
db98a0b0 577 priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0);
47dd7a54
GC		 578 priv->tx_coe = NO_HW_CSUM;
579 } else {
580 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
db98a0b0
GC		 581 priv->hw->dma->dma_mode(priv->dev->base_addr,
582 SF_DMA_MODE, SF_DMA_MODE);
47dd7a54
GC		 583 tc = SF_DMA_MODE;
584 priv->tx_coe = HW_CSUM;
585 } else {
586 /* Checksum computation is performed in software. */
db98a0b0
GC		 587 priv->hw->dma->dma_mode(priv->dev->base_addr, tc,
588 SF_DMA_MODE);
47dd7a54
GC		 589 priv->tx_coe = NO_HW_CSUM;
590 }
591 }
592 tx_coe = priv->tx_coe;
47dd7a54
GC		 593}
594
47dd7a54
GC		 595/**
596 * stmmac_tx:
597 * @priv: private driver structure
598 * Description: it reclaims resources after transmission completes.
599 */
600static void stmmac_tx(struct stmmac_priv *priv)
601{
602 unsigned int txsize = priv->dma_tx_size;
603 unsigned long ioaddr = priv->dev->base_addr;
604
605 while (priv->dirty_tx != priv->cur_tx) {
606 int last;
607 unsigned int entry = priv->dirty_tx % txsize;
608 struct sk_buff *skb = priv->tx_skbuff[entry];
609 struct dma_desc *p = priv->dma_tx + entry;
610
611 /* Check if the descriptor is owned by the DMA. */
db98a0b0 612 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 613 break;
614
615 /* Verify tx error by looking at the last segment */
db98a0b0 616 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 617 if (likely(last)) {
618 int tx_error =
db98a0b0
GC		 619 priv->hw->desc->tx_status(&priv->dev->stats,
620 &priv->xstats, p,
621 ioaddr);
47dd7a54
GC		 622 if (likely(tx_error == 0)) {
623 priv->dev->stats.tx_packets++;
624 priv->xstats.tx_pkt_n++;
625 } else
626 priv->dev->stats.tx_errors++;
627 }
628 TX_DBG("%s: curr %d, dirty %d\n", __func__,
629 priv->cur_tx, priv->dirty_tx);
630
631 if (likely(p->des2))
632 dma_unmap_single(priv->device, p->des2,
db98a0b0 633 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 634 DMA_TO_DEVICE);
635 if (unlikely(p->des3))
636 p->des3 = 0;
637
638 if (likely(skb != NULL)) {
639 /*
640 * If there's room in the queue (limit it to size)
641 * we add this skb back into the pool,
642 * if it's the right size.
643 */
644 if ((skb_queue_len(&priv->rx_recycle) <
645 priv->dma_rx_size) &&
646 skb_recycle_check(skb, priv->dma_buf_sz))
647 __skb_queue_head(&priv->rx_recycle, skb);
648 else
649 dev_kfree_skb(skb);
650
651 priv->tx_skbuff[entry] = NULL;
652 }
653
db98a0b0 654 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 655
656 entry = (++priv->dirty_tx) % txsize;
657 }
658 if (unlikely(netif_queue_stopped(priv->dev) &&
659 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
660 netif_tx_lock(priv->dev);
661 if (netif_queue_stopped(priv->dev) &&
662 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
663 TX_DBG("%s: restart transmit\n", __func__);
664 netif_wake_queue(priv->dev);
665 }
666 netif_tx_unlock(priv->dev);
667 }
47dd7a54
GC		 668}
669
670static inline void stmmac_enable_irq(struct stmmac_priv *priv)
671{
73cfe264
GC		 672#ifdef CONFIG_STMMAC_TIMER
673 if (likely(priv->tm->enable))
674 priv->tm->timer_start(tmrate);
675 else
47dd7a54 676#endif
aec7ff27 677 priv->hw->dma->enable_dma_irq(priv->dev->base_addr);
47dd7a54
GC		 678}
679
680static inline void stmmac_disable_irq(struct stmmac_priv *priv)
681{
73cfe264
GC		 682#ifdef CONFIG_STMMAC_TIMER
683 if (likely(priv->tm->enable))
684 priv->tm->timer_stop();
685 else
47dd7a54 686#endif
aec7ff27 687 priv->hw->dma->disable_dma_irq(priv->dev->base_addr);
47dd7a54
GC		 688}
689
690static int stmmac_has_work(struct stmmac_priv *priv)
691{
692 unsigned int has_work = 0;
693 int rxret, tx_work = 0;
694
db98a0b0 695 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 696 (priv->cur_rx % priv->dma_rx_size));
697
698 if (priv->dirty_tx != priv->cur_tx)
699 tx_work = 1;
700
701 if (likely(!rxret || tx_work))
702 has_work = 1;
703
704 return has_work;
705}
706
707static inline void _stmmac_schedule(struct stmmac_priv *priv)
708{
709 if (likely(stmmac_has_work(priv))) {
710 stmmac_disable_irq(priv);
711 napi_schedule(&priv->napi);
712 }
713}
714
715#ifdef CONFIG_STMMAC_TIMER
716void stmmac_schedule(struct net_device *dev)
717{
718 struct stmmac_priv *priv = netdev_priv(dev);
719
720 priv->xstats.sched_timer_n++;
721
722 _stmmac_schedule(priv);
47dd7a54
GC		 723}
724
725static void stmmac_no_timer_started(unsigned int x)
726{;
727};
728
729static void stmmac_no_timer_stopped(void)
730{;
731};
732#endif
733
734/**
735 * stmmac_tx_err:
736 * @priv: pointer to the private device structure
737 * Description: it cleans the descriptors and restarts the transmission
738 * in case of errors.
739 */
740static void stmmac_tx_err(struct stmmac_priv *priv)
741{
742 netif_stop_queue(priv->dev);
743
aec7ff27 744 priv->hw->dma->stop_tx(priv->dev->base_addr);
47dd7a54 745 dma_free_tx_skbufs(priv);
db98a0b0 746 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 747 priv->dirty_tx = 0;
748 priv->cur_tx = 0;
aec7ff27 749 priv->hw->dma->start_tx(priv->dev->base_addr);
47dd7a54
GC		 750
751 priv->dev->stats.tx_errors++;
752 netif_wake_queue(priv->dev);
47dd7a54
GC		 753}
754
47dd7a54 755
aec7ff27
GC		 756static void stmmac_dma_interrupt(struct stmmac_priv *priv)
757{
758 unsigned long ioaddr = priv->dev->base_addr;
759 int status;
760
761 status = priv->hw->dma->dma_interrupt(priv->dev->base_addr,
762 &priv->xstats);
763 if (likely(status == handle_tx_rx))
764 _stmmac_schedule(priv);
765
766 else if (unlikely(status == tx_hard_error_bump_tc)) {
767 /* Try to bump up the dma threshold on this failure */
768 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
769 tc += 64;
770 priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE);
771 priv->xstats.threshold = tc;
47dd7a54 772 }
aec7ff27
GC		 773 stmmac_tx_err(priv);
774 } else if (unlikely(status == tx_hard_error))
775 stmmac_tx_err(priv);
47dd7a54
GC		 776}
777
778/**
779 * stmmac_open - open entry point of the driver
780 * @dev : pointer to the device structure.
781 * Description:
782 * This function is the open entry point of the driver.
783 * Return value:
784 * 0 on success and an appropriate (-)ve integer as defined in errno.h
785 * file on failure.
786 */
787static int stmmac_open(struct net_device *dev)
788{
789 struct stmmac_priv *priv = netdev_priv(dev);
790 unsigned long ioaddr = dev->base_addr;
791 int ret;
792
793 /* Check that the MAC address is valid. If its not, refuse
794 * to bring the device up. The user must specify an
795 * address using the following linux command:
796 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
797 if (!is_valid_ether_addr(dev->dev_addr)) {
798 random_ether_addr(dev->dev_addr);
799 pr_warning("%s: generated random MAC address %pM\n", dev->name,
800 dev->dev_addr);
801 }
802
803 stmmac_verify_args();
804
805 ret = stmmac_init_phy(dev);
806 if (unlikely(ret)) {
807 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
808 return ret;
809 }
810
811 /* Request the IRQ lines */
a0607fd3 812 ret = request_irq(dev->irq, stmmac_interrupt,
47dd7a54
GC		 813 IRQF_SHARED, dev->name, dev);
814 if (unlikely(ret < 0)) {
815 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
816 __func__, dev->irq, ret);
817 return ret;
818 }
819
820#ifdef CONFIG_STMMAC_TIMER
73cfe264 821 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 822 if (unlikely(priv->tm == NULL)) {
2381a55c 823 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 824 return -ENOMEM;
825 }
826 priv->tm->freq = tmrate;
827
73cfe264
GC		 828 /* Test if the external timer can be actually used.
829 * In case of failure continue without timer. */
47dd7a54 830 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 831 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 832 priv->tm->freq = 0;
833 priv->tm->timer_start = stmmac_no_timer_started;
834 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 835 } else
836 priv->tm->enable = 1;
47dd7a54
GC		 837#endif
838
839 /* Create and initialize the TX/RX descriptors chains. */
840 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
841 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
842 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
843 init_dma_desc_rings(dev);
844
845 /* DMA initialization and SW reset */
db98a0b0
GC		 846 if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy,
847 priv->dma_rx_phy) < 0)) {
47dd7a54
GC		 848
849 pr_err("%s: DMA initialization failed\n", __func__);
850 return -1;
851 }
852
853 /* Copy the MAC addr into the HW */
db98a0b0 854 priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0);
ca5f12c1
GC		 855 /* If required, perform hw setup of the bus. */
856 if (priv->bus_setup)
857 priv->bus_setup(ioaddr);
47dd7a54 858 /* Initialize the MAC Core */
db98a0b0 859 priv->hw->mac->core_init(ioaddr);
47dd7a54
GC		 860
861 priv->shutdown = 0;
862
863 /* Initialise the MMC (if present) to disable all interrupts. */
864 writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
865 writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
866
867 /* Enable the MAC Rx/Tx */
868 stmmac_mac_enable_rx(ioaddr);
869 stmmac_mac_enable_tx(ioaddr);
870
871 /* Set the HW DMA mode and the COE */
872 stmmac_dma_operation_mode(priv);
873
874 /* Extra statistics */
875 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
876 priv->xstats.threshold = tc;
877
878 /* Start the ball rolling... */
879 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
aec7ff27
GC		 880 priv->hw->dma->start_tx(ioaddr);
881 priv->hw->dma->start_rx(ioaddr);
47dd7a54
GC		 882
883#ifdef CONFIG_STMMAC_TIMER
884 priv->tm->timer_start(tmrate);
885#endif
886 /* Dump DMA/MAC registers */
887 if (netif_msg_hw(priv)) {
db98a0b0
GC		 888 priv->hw->mac->dump_regs(ioaddr);
889 priv->hw->dma->dump_regs(ioaddr);
47dd7a54
GC		 890 }
891
892 if (priv->phydev)
893 phy_start(priv->phydev);
894
895 napi_enable(&priv->napi);
896 skb_queue_head_init(&priv->rx_recycle);
897 netif_start_queue(dev);
898 return 0;
899}
900
901/**
902 * stmmac_release - close entry point of the driver
903 * @dev : device pointer.
904 * Description:
905 * This is the stop entry point of the driver.
906 */
907static int stmmac_release(struct net_device *dev)
908{
909 struct stmmac_priv *priv = netdev_priv(dev);
910
911 /* Stop and disconnect the PHY */
912 if (priv->phydev) {
913 phy_stop(priv->phydev);
914 phy_disconnect(priv->phydev);
915 priv->phydev = NULL;
916 }
917
918 netif_stop_queue(dev);
919
920#ifdef CONFIG_STMMAC_TIMER
921 /* Stop and release the timer */
922 stmmac_close_ext_timer();
923 if (priv->tm != NULL)
924 kfree(priv->tm);
925#endif
926 napi_disable(&priv->napi);
927 skb_queue_purge(&priv->rx_recycle);
928
929 /* Free the IRQ lines */
930 free_irq(dev->irq, dev);
931
932 /* Stop TX/RX DMA and clear the descriptors */
aec7ff27
GC		 933 priv->hw->dma->stop_tx(dev->base_addr);
934 priv->hw->dma->stop_rx(dev->base_addr);
47dd7a54
GC		 935
936 /* Release and free the Rx/Tx resources */
937 free_dma_desc_resources(priv);
938
939 /* Disable the MAC core */
940 stmmac_mac_disable_tx(dev->base_addr);
941 stmmac_mac_disable_rx(dev->base_addr);
942
943 netif_carrier_off(dev);
944
945 return 0;
946}
947
948/*
949 * To perform emulated hardware segmentation on skb.
950 */
951static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
952{
953 struct sk_buff *segs, *curr_skb;
954 int gso_segs = skb_shinfo(skb)->gso_segs;
955
956 /* Estimate the number of fragments in the worst case */
957 if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
958 netif_stop_queue(priv->dev);
959 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
960 __func__);
961 if (stmmac_tx_avail(priv) < gso_segs)
962 return NETDEV_TX_BUSY;
963
964 netif_wake_queue(priv->dev);
965 }
966 TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
967 skb, skb->len);
968
969 segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
970 if (unlikely(IS_ERR(segs)))
971 goto sw_tso_end;
972
973 do {
974 curr_skb = segs;
975 segs = segs->next;
976 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
977 "*next %p\n", curr_skb->len, curr_skb, segs);
978 curr_skb->next = NULL;
979 stmmac_xmit(curr_skb, priv->dev);
980 } while (segs);
981
982sw_tso_end:
983 dev_kfree_skb(skb);
984
985 return NETDEV_TX_OK;
986}
987
988static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
989 struct net_device *dev,
990 int csum_insertion)
991{
992 struct stmmac_priv *priv = netdev_priv(dev);
993 unsigned int nopaged_len = skb_headlen(skb);
994 unsigned int txsize = priv->dma_tx_size;
995 unsigned int entry = priv->cur_tx % txsize;
996 struct dma_desc *desc = priv->dma_tx + entry;
997
998 if (nopaged_len > BUF_SIZE_8KiB) {
999
1000 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1001
1002 desc->des2 = dma_map_single(priv->device, skb->data,
1003 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1004 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1005 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1006 csum_insertion);
47dd7a54
GC		 1007
1008 entry = (++priv->cur_tx) % txsize;
1009 desc = priv->dma_tx + entry;
1010
1011 desc->des2 = dma_map_single(priv->device,
1012 skb->data + BUF_SIZE_8KiB,
1013 buf2_size, DMA_TO_DEVICE);
1014 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1015 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1016 csum_insertion);
1017 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1018 priv->tx_skbuff[entry] = NULL;
1019 } else {
1020 desc->des2 = dma_map_single(priv->device, skb->data,
1021 nopaged_len, DMA_TO_DEVICE);
1022 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1023 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1024 csum_insertion);
47dd7a54
GC		 1025 }
1026 return entry;
1027}
1028
1029/**
1030 * stmmac_xmit:
1031 * @skb : the socket buffer
1032 * @dev : device pointer
1033 * Description : Tx entry point of the driver.
1034 */
1035static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1036{
1037 struct stmmac_priv *priv = netdev_priv(dev);
1038 unsigned int txsize = priv->dma_tx_size;
1039 unsigned int entry;
1040 int i, csum_insertion = 0;
1041 int nfrags = skb_shinfo(skb)->nr_frags;
1042 struct dma_desc *desc, *first;
1043
1044 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1045 if (!netif_queue_stopped(dev)) {
1046 netif_stop_queue(dev);
1047 /* This is a hard error, log it. */
1048 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1049 __func__);
1050 }
1051 return NETDEV_TX_BUSY;
1052 }
1053
1054 entry = priv->cur_tx % txsize;
1055
1056#ifdef STMMAC_XMIT_DEBUG
1057 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1058 pr_info("stmmac xmit:\n"
1059 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1060 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1061 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1062 !skb_is_gso(skb) ? "isn't" : "is");
1063#endif
1064
1065 if (unlikely(skb_is_gso(skb)))
1066 return stmmac_sw_tso(priv, skb);
1067
1068 if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1069 if (likely(priv->tx_coe == NO_HW_CSUM))
1070 skb_checksum_help(skb);
1071 else
1072 csum_insertion = 1;
1073 }
1074
1075 desc = priv->dma_tx + entry;
1076 first = desc;
1077
1078#ifdef STMMAC_XMIT_DEBUG
1079 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1080 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1081 "\t\tn_frags: %d, ip_summed: %d\n",
1082 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1083#endif
1084 priv->tx_skbuff[entry] = skb;
1085 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1086 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1087 desc = priv->dma_tx + entry;
1088 } else {
1089 unsigned int nopaged_len = skb_headlen(skb);
1090 desc->des2 = dma_map_single(priv->device, skb->data,
1091 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1092 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1093 csum_insertion);
47dd7a54
GC		 1094 }
1095
1096 for (i = 0; i < nfrags; i++) {
1097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1098 int len = frag->size;
1099
1100 entry = (++priv->cur_tx) % txsize;
1101 desc = priv->dma_tx + entry;
1102
1103 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1104 desc->des2 = dma_map_page(priv->device, frag->page,
1105 frag->page_offset,
1106 len, DMA_TO_DEVICE);
1107 priv->tx_skbuff[entry] = NULL;
db98a0b0
GC		 1108 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1109 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1110 }
1111
1112 /* Interrupt on completition only for the latest segment */
db98a0b0 1113 priv->hw->desc->close_tx_desc(desc);
73cfe264 1114
47dd7a54 1115#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1116 /* Clean IC while using timer */
1117 if (likely(priv->tm->enable))
db98a0b0 1118 priv->hw->desc->clear_tx_ic(desc);
47dd7a54
GC		 1119#endif
1120 /* To avoid raise condition */
db98a0b0 1121 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1122
1123 priv->cur_tx++;
1124
1125#ifdef STMMAC_XMIT_DEBUG
1126 if (netif_msg_pktdata(priv)) {
1127 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1128 "first=%p, nfrags=%d\n",
1129 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1130 entry, first, nfrags);
1131 display_ring(priv->dma_tx, txsize);
1132 pr_info(">>> frame to be transmitted: ");
1133 print_pkt(skb->data, skb->len);
1134 }
1135#endif
1136 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1137 TX_DBG("%s: stop transmitted packets\n", __func__);
1138 netif_stop_queue(dev);
1139 }
1140
1141 dev->stats.tx_bytes += skb->len;
1142
aec7ff27 1143 priv->hw->dma->enable_dma_transmission(dev->base_addr);
47dd7a54
GC		 1144
1145 return NETDEV_TX_OK;
1146}
1147
1148static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1149{
1150 unsigned int rxsize = priv->dma_rx_size;
1151 int bfsize = priv->dma_buf_sz;
1152 struct dma_desc *p = priv->dma_rx;
1153
1154 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1155 unsigned int entry = priv->dirty_rx % rxsize;
1156 if (likely(priv->rx_skbuff[entry] == NULL)) {
1157 struct sk_buff *skb;
1158
1159 skb = __skb_dequeue(&priv->rx_recycle);
1160 if (skb == NULL)
1161 skb = netdev_alloc_skb_ip_align(priv->dev,
1162 bfsize);
1163
1164 if (unlikely(skb == NULL))
1165 break;
1166
1167 priv->rx_skbuff[entry] = skb;
1168 priv->rx_skbuff_dma[entry] =
1169 dma_map_single(priv->device, skb->data, bfsize,
1170 DMA_FROM_DEVICE);
1171
1172 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1173 if (unlikely(priv->is_gmac)) {
1174 if (bfsize >= BUF_SIZE_8KiB)
1175 (p + entry)->des3 =
1176 (p + entry)->des2 + BUF_SIZE_8KiB;
1177 }
1178 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1179 }
db98a0b0 1180 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1181 }
47dd7a54
GC		 1182}
1183
1184static int stmmac_rx(struct stmmac_priv *priv, int limit)
1185{
1186 unsigned int rxsize = priv->dma_rx_size;
1187 unsigned int entry = priv->cur_rx % rxsize;
1188 unsigned int next_entry;
1189 unsigned int count = 0;
1190 struct dma_desc *p = priv->dma_rx + entry;
1191 struct dma_desc *p_next;
1192
1193#ifdef STMMAC_RX_DEBUG
1194 if (netif_msg_hw(priv)) {
1195 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1196 display_ring(priv->dma_rx, rxsize);
1197 }
1198#endif
1199 count = 0;
db98a0b0 1200 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1201 int status;
1202
1203 if (count >= limit)
1204 break;
1205
1206 count++;
1207
1208 next_entry = (++priv->cur_rx) % rxsize;
1209 p_next = priv->dma_rx + next_entry;
1210 prefetch(p_next);
1211
1212 /* read the status of the incoming frame */
db98a0b0
GC		 1213 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1214 &priv->xstats, p));
47dd7a54
GC		 1215 if (unlikely(status == discard_frame))
1216 priv->dev->stats.rx_errors++;
1217 else {
1218 struct sk_buff *skb;
3eeb2997 1219 int frame_len;
47dd7a54 1220
3eeb2997
GC		 1221 frame_len = priv->hw->desc->get_rx_frame_len(p);
1222 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1223 * Type frames (LLC/LLC-SNAP) */
1224 if (unlikely(status != llc_snap))
1225 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1226#ifdef STMMAC_RX_DEBUG
1227 if (frame_len > ETH_FRAME_LEN)
1228 pr_debug("\tRX frame size %d, COE status: %d\n",
1229 frame_len, status);
1230
1231 if (netif_msg_hw(priv))
1232 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1233 p, entry, p->des2);
1234#endif
1235 skb = priv->rx_skbuff[entry];
1236 if (unlikely(!skb)) {
1237 pr_err("%s: Inconsistent Rx descriptor chain\n",
1238 priv->dev->name);
1239 priv->dev->stats.rx_dropped++;
1240 break;
1241 }
1242 prefetch(skb->data - NET_IP_ALIGN);
1243 priv->rx_skbuff[entry] = NULL;
1244
1245 skb_put(skb, frame_len);
1246 dma_unmap_single(priv->device,
1247 priv->rx_skbuff_dma[entry],
1248 priv->dma_buf_sz, DMA_FROM_DEVICE);
1249#ifdef STMMAC_RX_DEBUG
1250 if (netif_msg_pktdata(priv)) {
1251 pr_info(" frame received (%dbytes)", frame_len);
1252 print_pkt(skb->data, frame_len);
1253 }
1254#endif
1255 skb->protocol = eth_type_trans(skb, priv->dev);
1256
1257 if (unlikely(status == csum_none)) {
1258 /* always for the old mac 10/100 */
1259 skb->ip_summed = CHECKSUM_NONE;
1260 netif_receive_skb(skb);
1261 } else {
1262 skb->ip_summed = CHECKSUM_UNNECESSARY;
1263 napi_gro_receive(&priv->napi, skb);
1264 }
1265
1266 priv->dev->stats.rx_packets++;
1267 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1268 }
1269 entry = next_entry;
1270 p = p_next; /* use prefetched values */
1271 }
1272
1273 stmmac_rx_refill(priv);
1274
1275 priv->xstats.rx_pkt_n += count;
1276
1277 return count;
1278}
1279
1280/**
1281 * stmmac_poll - stmmac poll method (NAPI)
1282 * @napi : pointer to the napi structure.
1283 * @budget : maximum number of packets that the current CPU can receive from
1284 * all interfaces.
1285 * Description :
1286 * This function implements the the reception process.
1287 * Also it runs the TX completion thread
1288 */
1289static int stmmac_poll(struct napi_struct *napi, int budget)
1290{
1291 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1292 int work_done = 0;
1293
1294 priv->xstats.poll_n++;
1295 stmmac_tx(priv);
1296 work_done = stmmac_rx(priv, budget);
1297
1298 if (work_done < budget) {
1299 napi_complete(napi);
1300 stmmac_enable_irq(priv);
1301 }
1302 return work_done;
1303}
1304
1305/**
1306 * stmmac_tx_timeout
1307 * @dev : Pointer to net device structure
1308 * Description: this function is called when a packet transmission fails to
1309 * complete within a reasonable tmrate. The driver will mark the error in the
1310 * netdev structure and arrange for the device to be reset to a sane state
1311 * in order to transmit a new packet.
1312 */
1313static void stmmac_tx_timeout(struct net_device *dev)
1314{
1315 struct stmmac_priv *priv = netdev_priv(dev);
1316
1317 /* Clear Tx resources and restart transmitting again */
1318 stmmac_tx_err(priv);
47dd7a54
GC		 1319}
1320
1321/* Configuration changes (passed on by ifconfig) */
1322static int stmmac_config(struct net_device *dev, struct ifmap *map)
1323{
1324 if (dev->flags & IFF_UP) /* can't act on a running interface */
1325 return -EBUSY;
1326
1327 /* Don't allow changing the I/O address */
1328 if (map->base_addr != dev->base_addr) {
1329 pr_warning("%s: can't change I/O address\n", dev->name);
1330 return -EOPNOTSUPP;
1331 }
1332
1333 /* Don't allow changing the IRQ */
1334 if (map->irq != dev->irq) {
1335 pr_warning("%s: can't change IRQ number %d\n",
1336 dev->name, dev->irq);
1337 return -EOPNOTSUPP;
1338 }
1339
1340 /* ignore other fields */
1341 return 0;
1342}
1343
1344/**
1345 * stmmac_multicast_list - entry point for multicast addressing
1346 * @dev : pointer to the device structure
1347 * Description:
1348 * This function is a driver entry point which gets called by the kernel
1349 * whenever multicast addresses must be enabled/disabled.
1350 * Return value:
1351 * void.
1352 */
1353static void stmmac_multicast_list(struct net_device *dev)
1354{
1355 struct stmmac_priv *priv = netdev_priv(dev);
1356
1357 spin_lock(&priv->lock);
db98a0b0 1358 priv->hw->mac->set_filter(dev);
47dd7a54 1359 spin_unlock(&priv->lock);
47dd7a54
GC		 1360}
1361
1362/**
1363 * stmmac_change_mtu - entry point to change MTU size for the device.
1364 * @dev : device pointer.
1365 * @new_mtu : the new MTU size for the device.
1366 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1367 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1368 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1369 * Return value:
1370 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1371 * file on failure.
1372 */
1373static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1374{
1375 struct stmmac_priv *priv = netdev_priv(dev);
1376 int max_mtu;
1377
1378 if (netif_running(dev)) {
1379 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1380 return -EBUSY;
1381 }
1382
1383 if (priv->is_gmac)
1384 max_mtu = JUMBO_LEN;
1385 else
1386 max_mtu = ETH_DATA_LEN;
1387
1388 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1389 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1390 return -EINVAL;
1391 }
1392
1393 dev->mtu = new_mtu;
1394
1395 return 0;
1396}
1397
1398static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1399{
1400 struct net_device *dev = (struct net_device *)dev_id;
1401 struct stmmac_priv *priv = netdev_priv(dev);
1402
1403 if (unlikely(!dev)) {
1404 pr_err("%s: invalid dev pointer\n", __func__);
1405 return IRQ_NONE;
1406 }
1407
1408 if (priv->is_gmac) {
1409 unsigned long ioaddr = dev->base_addr;
1410 /* To handle GMAC own interrupts */
db98a0b0 1411 priv->hw->mac->host_irq_status(ioaddr);
47dd7a54 1412 }
aec7ff27
GC		 1413
1414 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1415
1416 return IRQ_HANDLED;
1417}
1418
1419#ifdef CONFIG_NET_POLL_CONTROLLER
1420/* Polling receive - used by NETCONSOLE and other diagnostic tools
1421 * to allow network I/O with interrupts disabled. */
1422static void stmmac_poll_controller(struct net_device *dev)
1423{
1424 disable_irq(dev->irq);
1425 stmmac_interrupt(dev->irq, dev);
1426 enable_irq(dev->irq);
1427}
1428#endif
1429
1430/**
1431 * stmmac_ioctl - Entry point for the Ioctl
1432 * @dev: Device pointer.
1433 * @rq: An IOCTL specefic structure, that can contain a pointer to
1434 * a proprietary structure used to pass information to the driver.
1435 * @cmd: IOCTL command
1436 * Description:
1437 * Currently there are no special functionality supported in IOCTL, just the
1438 * phy_mii_ioctl(...) can be invoked.
1439 */
1440static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1441{
1442 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1443 int ret;
47dd7a54
GC		 1444
1445 if (!netif_running(dev))
1446 return -EINVAL;
1447
28b04113
RC		 1448 if (!priv->phydev)
1449 return -EINVAL;
1450
1451 spin_lock(&priv->lock);
1452 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1453 spin_unlock(&priv->lock);
1454
47dd7a54
GC		 1455 return ret;
1456}
1457
1458#ifdef STMMAC_VLAN_TAG_USED
1459static void stmmac_vlan_rx_register(struct net_device *dev,
1460 struct vlan_group *grp)
1461{
1462 struct stmmac_priv *priv = netdev_priv(dev);
1463
1464 DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1465
1466 spin_lock(&priv->lock);
1467 priv->vlgrp = grp;
1468 spin_unlock(&priv->lock);
47dd7a54
GC		 1469}
1470#endif
1471
1472static const struct net_device_ops stmmac_netdev_ops = {
1473 .ndo_open = stmmac_open,
1474 .ndo_start_xmit = stmmac_xmit,
1475 .ndo_stop = stmmac_release,
1476 .ndo_change_mtu = stmmac_change_mtu,
1477 .ndo_set_multicast_list = stmmac_multicast_list,
1478 .ndo_tx_timeout = stmmac_tx_timeout,
1479 .ndo_do_ioctl = stmmac_ioctl,
1480 .ndo_set_config = stmmac_config,
1481#ifdef STMMAC_VLAN_TAG_USED
1482 .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1483#endif
1484#ifdef CONFIG_NET_POLL_CONTROLLER
1485 .ndo_poll_controller = stmmac_poll_controller,
1486#endif
1487 .ndo_set_mac_address = eth_mac_addr,
1488};
1489
1490/**
1491 * stmmac_probe - Initialization of the adapter .
1492 * @dev : device pointer
1493 * Description: The function initializes the network device structure for
1494 * the STMMAC driver. It also calls the low level routines
1495 * in order to init the HW (i.e. the DMA engine)
1496 */
1497static int stmmac_probe(struct net_device *dev)
1498{
1499 int ret = 0;
1500 struct stmmac_priv *priv = netdev_priv(dev);
1501
1502 ether_setup(dev);
1503
1504 dev->netdev_ops = &stmmac_netdev_ops;
1505 stmmac_set_ethtool_ops(dev);
1506
1507 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1508 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1509#ifdef STMMAC_VLAN_TAG_USED
1510 /* Both mac100 and gmac support receive VLAN tag detection */
1511 dev->features |= NETIF_F_HW_VLAN_RX;
1512#endif
1513 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1514
1515 if (priv->is_gmac)
1516 priv->rx_csum = 1;
1517
1518 if (flow_ctrl)
1519 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1520
1521 priv->pause = pause;
1522 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1523
1524 /* Get the MAC address */
db98a0b0 1525 priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
47dd7a54
GC		 1526
1527 if (!is_valid_ether_addr(dev->dev_addr))
1528 pr_warning("\tno valid MAC address;"
1529 "please, use ifconfig or nwhwconfig!\n");
1530
1531 ret = register_netdev(dev);
1532 if (ret) {
1533 pr_err("%s: ERROR %i registering the device\n",
1534 __func__, ret);
1535 return -ENODEV;
1536 }
1537
1538 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1539 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1540 (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1541
1542 spin_lock_init(&priv->lock);
1543
1544 return ret;
1545}
1546
1547/**
1548 * stmmac_mac_device_setup
1549 * @dev : device pointer
1550 * Description: select and initialise the mac device (mac100 or Gmac).
1551 */
1552static int stmmac_mac_device_setup(struct net_device *dev)
1553{
1554 struct stmmac_priv *priv = netdev_priv(dev);
1555 unsigned long ioaddr = dev->base_addr;
1556
1557 struct mac_device_info *device;
1558
3d90c508 1559 if (priv->is_gmac)
21d437cc 1560 device = dwmac1000_setup(ioaddr);
3d90c508 1561 else
7e848ae1 1562 device = dwmac100_setup(ioaddr);
3d90c508 1563
1ff21906
DC		 1564 if (!device)
1565 return -ENOMEM;
1566
3d90c508
GC		 1567 if (priv->enh_desc) {
1568 device->desc = &enh_desc_ops;
1569 pr_info("\tEnhanced descriptor structure\n");
1570 } else
56b106ae 1571 device->desc = &ndesc_ops;
47dd7a54 1572
db98a0b0 1573 priv->hw = device;
47dd7a54 1574
db98a0b0 1575 priv->wolenabled = priv->hw->pmt; /* PMT supported */
47dd7a54
GC		 1576 if (priv->wolenabled == PMT_SUPPORTED)
1577 priv->wolopts = WAKE_MAGIC; /* Magic Frame */
1578
1579 return 0;
1580}
1581
1582static int stmmacphy_dvr_probe(struct platform_device *pdev)
1583{
ee7946a7 1584 struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1585
1586 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1587 plat_dat->bus_id);
1588
1589 return 0;
1590}
1591
1592static int stmmacphy_dvr_remove(struct platform_device *pdev)
1593{
1594 return 0;
1595}
1596
1597static struct platform_driver stmmacphy_driver = {
1598 .driver = {
1599 .name = PHY_RESOURCE_NAME,
1600 },
1601 .probe = stmmacphy_dvr_probe,
1602 .remove = stmmacphy_dvr_remove,
1603};
1604
1605/**
1606 * stmmac_associate_phy
1607 * @dev: pointer to device structure
1608 * @data: points to the private structure.
1609 * Description: Scans through all the PHYs we have registered and checks if
1610 * any are associated with our MAC. If so, then just fill in
1611 * the blanks in our local context structure
1612 */
1613static int stmmac_associate_phy(struct device *dev, void *data)
1614{
1615 struct stmmac_priv *priv = (struct stmmac_priv *)data;
ee7946a7 1616 struct plat_stmmacphy_data *plat_dat = dev->platform_data;
47dd7a54
GC		 1617
1618 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1619 plat_dat->bus_id);
1620
1621 /* Check that this phy is for the MAC being initialised */
1622 if (priv->bus_id != plat_dat->bus_id)
1623 return 0;
1624
1625 /* OK, this PHY is connected to the MAC.
1626 Go ahead and get the parameters */
1627 DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1628 priv->phy_irq =
1629 platform_get_irq_byname(to_platform_device(dev), "phyirq");
1630 DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1631 plat_dat->bus_id, priv->phy_irq);
1632
1633 /* Override with kernel parameters if supplied XXX CRS XXX
1634 * this needs to have multiple instances */
1635 if ((phyaddr >= 0) && (phyaddr <= 31))
1636 plat_dat->phy_addr = phyaddr;
1637
1638 priv->phy_addr = plat_dat->phy_addr;
1639 priv->phy_mask = plat_dat->phy_mask;
1640 priv->phy_interface = plat_dat->interface;
1641 priv->phy_reset = plat_dat->phy_reset;
1642
1643 DBG(probe, DEBUG, "%s: exiting\n", __func__);
1644 return 1; /* forces exit of driver_for_each_device() */
1645}
1646
1647/**
1648 * stmmac_dvr_probe
1649 * @pdev: platform device pointer
1650 * Description: the driver is initialized through platform_device.
1651 */
1652static int stmmac_dvr_probe(struct platform_device *pdev)
1653{
1654 int ret = 0;
1655 struct resource *res;
1656 unsigned int *addr = NULL;
1657 struct net_device *ndev = NULL;
1658 struct stmmac_priv *priv;
1659 struct plat_stmmacenet_data *plat_dat;
1660
1661 pr_info("STMMAC driver:\n\tplatform registration... ");
1662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1663 if (!res) {
1664 ret = -ENODEV;
1665 goto out;
1666 }
1667 pr_info("done!\n");
1668
b6222682 1669 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1670 pdev->name)) {
1671 pr_err("%s: ERROR: memory allocation failed"
1672 "cannot get the I/O addr 0x%x\n",
1673 __func__, (unsigned int)res->start);
1674 ret = -EBUSY;
1675 goto out;
1676 }
1677
7c5365bc 1678 addr = ioremap(res->start, resource_size(res));
47dd7a54 1679 if (!addr) {
7c5365bc 1680 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54
GC		 1681 ret = -ENOMEM;
1682 goto out;
1683 }
1684
1685 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1686 if (!ndev) {
1687 pr_err("%s: ERROR: allocating the device\n", __func__);
1688 ret = -ENOMEM;
1689 goto out;
1690 }
1691
1692 SET_NETDEV_DEV(ndev, &pdev->dev);
1693
1694 /* Get the MAC information */
1695 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1696 if (ndev->irq == -ENXIO) {
1697 pr_err("%s: ERROR: MAC IRQ configuration "
1698 "information not found\n", __func__);
1699 ret = -ENODEV;
1700 goto out;
1701 }
1702
1703 priv = netdev_priv(ndev);
1704 priv->device = &(pdev->dev);
1705 priv->dev = ndev;
ee7946a7 1706 plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1707 priv->bus_id = plat_dat->bus_id;
1708 priv->pbl = plat_dat->pbl; /* TLI */
1709 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
3d90c508 1710 priv->enh_desc = plat_dat->enh_desc;
47dd7a54
GC		 1711
1712 platform_set_drvdata(pdev, ndev);
1713
1714 /* Set the I/O base addr */
1715 ndev->base_addr = (unsigned long)addr;
1716
ee7946a7
GC		 1717 /* Verify embedded resource for the platform */
1718 ret = stmmac_claim_resource(pdev);
1719 if (ret < 0)
1720 goto out;
1721
47dd7a54
GC		 1722 /* MAC HW revice detection */
1723 ret = stmmac_mac_device_setup(ndev);
1724 if (ret < 0)
1725 goto out;
1726
1727 /* Network Device Registration */
1728 ret = stmmac_probe(ndev);
1729 if (ret < 0)
1730 goto out;
1731
1732 /* associate a PHY - it is provided by another platform bus */
1733 if (!driver_for_each_device
1734 (&(stmmacphy_driver.driver), NULL, (void *)priv,
1735 stmmac_associate_phy)) {
1736 pr_err("No PHY device is associated with this MAC!\n");
1737 ret = -ENODEV;
1738 goto out;
1739 }
1740
1741 priv->fix_mac_speed = plat_dat->fix_mac_speed;
ee7946a7 1742 priv->bus_setup = plat_dat->bus_setup;
47dd7a54
GC		 1743 priv->bsp_priv = plat_dat->bsp_priv;
1744
1745 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1746 "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1747 pdev->id, ndev->irq, (unsigned int)addr);
1748
1749 /* MDIO bus Registration */
1750 pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1751 ret = stmmac_mdio_register(ndev);
1752 if (ret < 0)
1753 goto out;
1754 pr_debug("registered!\n");
1755
1756out:
1757 if (ret < 0) {
1758 platform_set_drvdata(pdev, NULL);
7c5365bc 1759 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1760 if (addr != NULL)
1761 iounmap(addr);
1762 }
1763
1764 return ret;
1765}
1766
1767/**
1768 * stmmac_dvr_remove
1769 * @pdev: platform device pointer
1770 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1771 * changes the link status, releases the DMA descriptor rings,
1772 * unregisters the MDIO bus and unmaps the allocated memory.
1773 */
1774static int stmmac_dvr_remove(struct platform_device *pdev)
1775{
1776 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1777 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1778 struct resource *res;
1779
1780 pr_info("%s:\n\tremoving driver", __func__);
1781
aec7ff27
GC		 1782 priv->hw->dma->stop_rx(ndev->base_addr);
1783 priv->hw->dma->stop_tx(ndev->base_addr);
47dd7a54
GC		 1784
1785 stmmac_mac_disable_rx(ndev->base_addr);
1786 stmmac_mac_disable_tx(ndev->base_addr);
1787
1788 netif_carrier_off(ndev);
1789
1790 stmmac_mdio_unregister(ndev);
1791
1792 platform_set_drvdata(pdev, NULL);
1793 unregister_netdev(ndev);
1794
1795 iounmap((void *)ndev->base_addr);
1796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1797 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1798
1799 free_netdev(ndev);
1800
1801 return 0;
1802}
1803
1804#ifdef CONFIG_PM
1805static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
1806{
1807 struct net_device *dev = platform_get_drvdata(pdev);
1808 struct stmmac_priv *priv = netdev_priv(dev);
1809 int dis_ic = 0;
1810
1811 if (!dev || !netif_running(dev))
1812 return 0;
1813
1814 spin_lock(&priv->lock);
1815
1816 if (state.event == PM_EVENT_SUSPEND) {
1817 netif_device_detach(dev);
1818 netif_stop_queue(dev);
1819 if (priv->phydev)
1820 phy_stop(priv->phydev);
1821
1822#ifdef CONFIG_STMMAC_TIMER
1823 priv->tm->timer_stop();
73cfe264
GC		 1824 if (likely(priv->tm->enable))
1825 dis_ic = 1;
47dd7a54
GC		 1826#endif
1827 napi_disable(&priv->napi);
1828
1829 /* Stop TX/RX DMA */
aec7ff27
GC		 1830 priv->hw->dma->stop_tx(dev->base_addr);
1831 priv->hw->dma->stop_rx(dev->base_addr);
47dd7a54 1832 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 1833 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1834 dis_ic);
1835 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 1836
1837 stmmac_mac_disable_tx(dev->base_addr);
1838
1839 if (device_may_wakeup(&(pdev->dev))) {
1840 /* Enable Power down mode by programming the PMT regs */
1841 if (priv->wolenabled == PMT_SUPPORTED)
db98a0b0
GC		 1842 priv->hw->mac->pmt(dev->base_addr,
1843 priv->wolopts);
47dd7a54
GC		 1844 } else {
1845 stmmac_mac_disable_rx(dev->base_addr);
1846 }
1847 } else {
1848 priv->shutdown = 1;
1849 /* Although this can appear slightly redundant it actually
1850 * makes fast the standby operation and guarantees the driver
1851 * working if hibernation is on media. */
1852 stmmac_release(dev);
1853 }
1854
1855 spin_unlock(&priv->lock);
1856 return 0;
1857}
1858
1859static int stmmac_resume(struct platform_device *pdev)
1860{
1861 struct net_device *dev = platform_get_drvdata(pdev);
1862 struct stmmac_priv *priv = netdev_priv(dev);
1863 unsigned long ioaddr = dev->base_addr;
1864
1865 if (!netif_running(dev))
1866 return 0;
1867
1868 spin_lock(&priv->lock);
1869
1870 if (priv->shutdown) {
1871 /* Re-open the interface and re-init the MAC/DMA
1872 and the rings. */
1873 stmmac_open(dev);
1874 goto out_resume;
1875 }
1876
1877 /* Power Down bit, into the PM register, is cleared
1878 * automatically as soon as a magic packet or a Wake-up frame
1879 * is received. Anyway, it's better to manually clear
1880 * this bit because it can generate problems while resuming
1881 * from another devices (e.g. serial console). */
1882 if (device_may_wakeup(&(pdev->dev)))
1883 if (priv->wolenabled == PMT_SUPPORTED)
db98a0b0 1884 priv->hw->mac->pmt(dev->base_addr, 0);
47dd7a54
GC		 1885
1886 netif_device_attach(dev);
1887
1888 /* Enable the MAC and DMA */
1889 stmmac_mac_enable_rx(ioaddr);
1890 stmmac_mac_enable_tx(ioaddr);
aec7ff27
GC		 1891 priv->hw->dma->start_tx(ioaddr);
1892 priv->hw->dma->start_rx(ioaddr);
47dd7a54
GC		 1893
1894#ifdef CONFIG_STMMAC_TIMER
1895 priv->tm->timer_start(tmrate);
1896#endif
1897 napi_enable(&priv->napi);
1898
1899 if (priv->phydev)
1900 phy_start(priv->phydev);
1901
1902 netif_start_queue(dev);
1903
1904out_resume:
1905 spin_unlock(&priv->lock);
1906 return 0;
1907}
1908#endif
1909
1910static struct platform_driver stmmac_driver = {
1911 .driver = {
1912 .name = STMMAC_RESOURCE_NAME,
1913 },
1914 .probe = stmmac_dvr_probe,
1915 .remove = stmmac_dvr_remove,
1916#ifdef CONFIG_PM
1917 .suspend = stmmac_suspend,
1918 .resume = stmmac_resume,
1919#endif
1920
1921};
1922
1923/**
1924 * stmmac_init_module - Entry point for the driver
1925 * Description: This function is the entry point for the driver.
1926 */
1927static int __init stmmac_init_module(void)
1928{
1929 int ret;
1930
1931 if (platform_driver_register(&stmmacphy_driver)) {
1932 pr_err("No PHY devices registered!\n");
1933 return -ENODEV;
1934 }
1935
1936 ret = platform_driver_register(&stmmac_driver);
1937 return ret;
1938}
1939
1940/**
1941 * stmmac_cleanup_module - Cleanup routine for the driver
1942 * Description: This function is the cleanup routine for the driver.
1943 */
1944static void __exit stmmac_cleanup_module(void)
1945{
1946 platform_driver_unregister(&stmmacphy_driver);
1947 platform_driver_unregister(&stmmac_driver);
1948}
1949
1950#ifndef MODULE
1951static int __init stmmac_cmdline_opt(char *str)
1952{
1953 char *opt;
1954
1955 if (!str || !*str)
1956 return -EINVAL;
1957 while ((opt = strsep(&str, ",")) != NULL) {
1958 if (!strncmp(opt, "debug:", 6))
1959 strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
1960 else if (!strncmp(opt, "phyaddr:", 8))
1961 strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
1962 else if (!strncmp(opt, "dma_txsize:", 11))
1963 strict_strtoul(opt + 11, 0,
1964 (unsigned long *)&dma_txsize);
1965 else if (!strncmp(opt, "dma_rxsize:", 11))
1966 strict_strtoul(opt + 11, 0,
1967 (unsigned long *)&dma_rxsize);
1968 else if (!strncmp(opt, "buf_sz:", 7))
1969 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
1970 else if (!strncmp(opt, "tc:", 3))
1971 strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
1972 else if (!strncmp(opt, "tx_coe:", 7))
1973 strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
1974 else if (!strncmp(opt, "watchdog:", 9))
1975 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
1976 else if (!strncmp(opt, "flow_ctrl:", 10))
1977 strict_strtoul(opt + 10, 0,
1978 (unsigned long *)&flow_ctrl);
1979 else if (!strncmp(opt, "pause:", 6))
1980 strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
1981#ifdef CONFIG_STMMAC_TIMER
1982 else if (!strncmp(opt, "tmrate:", 7))
1983 strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
1984#endif
1985 }
1986 return 0;
1987}
1988
1989__setup("stmmaceth=", stmmac_cmdline_opt);
1990#endif
1991
1992module_init(stmmac_init_module);
1993module_exit(stmmac_cleanup_module);
1994
1995MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
1996MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
1997MODULE_LICENSE("GPL");
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