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stmmac: add the new Header file for stmmac platform data
[net-next-2.6.git] / drivers / net / stmmac / stmmac_main.c
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47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/platform_device.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/skbuff.h>
41#include <linux/ethtool.h>
42#include <linux/if_ether.h>
43#include <linux/crc32.h>
44#include <linux/mii.h>
45#include <linux/phy.h>
46#include <linux/if_vlan.h>
47#include <linux/dma-mapping.h>
48#include <linux/stm/soc.h>
49#include "stmmac.h"
50
51#define STMMAC_RESOURCE_NAME "stmmaceth"
52#define PHY_RESOURCE_NAME "stmmacphy"
53
54#undef STMMAC_DEBUG
55/*#define STMMAC_DEBUG*/
56#ifdef STMMAC_DEBUG
57#define DBG(nlevel, klevel, fmt, args...) \
58 ((void)(netif_msg_##nlevel(priv) && \
59 printk(KERN_##klevel fmt, ## args)))
60#else
61#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
62#endif
63
64#undef STMMAC_RX_DEBUG
65/*#define STMMAC_RX_DEBUG*/
66#ifdef STMMAC_RX_DEBUG
67#define RX_DBG(fmt, args...) printk(fmt, ## args)
68#else
69#define RX_DBG(fmt, args...) do { } while (0)
70#endif
71
72#undef STMMAC_XMIT_DEBUG
73/*#define STMMAC_XMIT_DEBUG*/
74#ifdef STMMAC_TX_DEBUG
75#define TX_DBG(fmt, args...) printk(fmt, ## args)
76#else
77#define TX_DBG(fmt, args...) do { } while (0)
78#endif
79
80#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
81#define JUMBO_LEN 9000
82
83/* Module parameters */
84#define TX_TIMEO 5000 /* default 5 seconds */
85static int watchdog = TX_TIMEO;
86module_param(watchdog, int, S_IRUGO | S_IWUSR);
87MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
88
89static int debug = -1; /* -1: default, 0: no output, 16: all */
90module_param(debug, int, S_IRUGO | S_IWUSR);
91MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
92
93static int phyaddr = -1;
94module_param(phyaddr, int, S_IRUGO);
95MODULE_PARM_DESC(phyaddr, "Physical device address");
96
97#define DMA_TX_SIZE 256
98static int dma_txsize = DMA_TX_SIZE;
99module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
100MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
101
102#define DMA_RX_SIZE 256
103static int dma_rxsize = DMA_RX_SIZE;
104module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
105MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
106
107static int flow_ctrl = FLOW_OFF;
108module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
110
111static int pause = PAUSE_TIME;
112module_param(pause, int, S_IRUGO | S_IWUSR);
113MODULE_PARM_DESC(pause, "Flow Control Pause Time");
114
115#define TC_DEFAULT 64
116static int tc = TC_DEFAULT;
117module_param(tc, int, S_IRUGO | S_IWUSR);
118MODULE_PARM_DESC(tc, "DMA threshold control value");
119
120#define RX_NO_COALESCE 1 /* Always interrupt on completion */
121#define TX_NO_COALESCE -1 /* No moderation by default */
122
123/* Pay attention to tune this parameter; take care of both
124 * hardware capability and network stabitily/performance impact.
125 * Many tests showed that ~4ms latency seems to be good enough. */
126#ifdef CONFIG_STMMAC_TIMER
127#define DEFAULT_PERIODIC_RATE 256
128static int tmrate = DEFAULT_PERIODIC_RATE;
129module_param(tmrate, int, S_IRUGO | S_IWUSR);
130MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
131#endif
132
133#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
134static int buf_sz = DMA_BUFFER_SIZE;
135module_param(buf_sz, int, S_IRUGO | S_IWUSR);
136MODULE_PARM_DESC(buf_sz, "DMA buffer size");
137
138/* In case of Giga ETH, we can enable/disable the COE for the
139 * transmit HW checksum computation.
140 * Note that, if tx csum is off in HW, SG will be still supported. */
141static int tx_coe = HW_CSUM;
142module_param(tx_coe, int, S_IRUGO | S_IWUSR);
143MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
144
145static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
146 NETIF_MSG_LINK | NETIF_MSG_IFUP |
147 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
148
149static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
150static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
151
152/**
153 * stmmac_verify_args - verify the driver parameters.
154 * Description: it verifies if some wrong parameter is passed to the driver.
155 * Note that wrong parameters are replaced with the default values.
156 */
157static void stmmac_verify_args(void)
158{
159 if (unlikely(watchdog < 0))
160 watchdog = TX_TIMEO;
161 if (unlikely(dma_rxsize < 0))
162 dma_rxsize = DMA_RX_SIZE;
163 if (unlikely(dma_txsize < 0))
164 dma_txsize = DMA_TX_SIZE;
165 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
166 buf_sz = DMA_BUFFER_SIZE;
167 if (unlikely(flow_ctrl > 1))
168 flow_ctrl = FLOW_AUTO;
169 else if (likely(flow_ctrl < 0))
170 flow_ctrl = FLOW_OFF;
171 if (unlikely((pause < 0) || (pause > 0xffff)))
172 pause = PAUSE_TIME;
173
174 return;
175}
176
177#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
178static void print_pkt(unsigned char *buf, int len)
179{
180 int j;
181 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
182 for (j = 0; j < len; j++) {
183 if ((j % 16) == 0)
184 pr_info("\n %03x:", j);
185 pr_info(" %02x", buf[j]);
186 }
187 pr_info("\n");
188 return;
189}
190#endif
191
192/* minimum number of free TX descriptors required to wake up TX process */
193#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
194
195static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
196{
197 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
198}
199
200/**
201 * stmmac_adjust_link
202 * @dev: net device structure
203 * Description: it adjusts the link parameters.
204 */
205static void stmmac_adjust_link(struct net_device *dev)
206{
207 struct stmmac_priv *priv = netdev_priv(dev);
208 struct phy_device *phydev = priv->phydev;
209 unsigned long ioaddr = dev->base_addr;
210 unsigned long flags;
211 int new_state = 0;
212 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
213
214 if (phydev == NULL)
215 return;
216
217 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
218 phydev->addr, phydev->link);
219
220 spin_lock_irqsave(&priv->lock, flags);
221 if (phydev->link) {
222 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
223
224 /* Now we make sure that we can be in full duplex mode.
225 * If not, we operate in half-duplex mode. */
226 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1;
228 if (!(phydev->duplex))
229 ctrl &= ~priv->mac_type->hw.link.duplex;
230 else
231 ctrl |= priv->mac_type->hw.link.duplex;
232 priv->oldduplex = phydev->duplex;
233 }
234 /* Flow Control operation */
235 if (phydev->pause)
236 priv->mac_type->ops->flow_ctrl(ioaddr, phydev->duplex,
237 fc, pause_time);
238
239 if (phydev->speed != priv->speed) {
240 new_state = 1;
241 switch (phydev->speed) {
242 case 1000:
243 if (likely(priv->is_gmac))
244 ctrl &= ~priv->mac_type->hw.link.port;
245 break;
246 case 100:
247 case 10:
248 if (priv->is_gmac) {
249 ctrl |= priv->mac_type->hw.link.port;
250 if (phydev->speed == SPEED_100) {
251 ctrl |=
252 priv->mac_type->hw.link.
253 speed;
254 } else {
255 ctrl &=
256 ~(priv->mac_type->hw.
257 link.speed);
258 }
259 } else {
260 ctrl &= ~priv->mac_type->hw.link.port;
261 }
262 priv->fix_mac_speed(priv->bsp_priv,
263 phydev->speed);
264 break;
265 default:
266 if (netif_msg_link(priv))
267 pr_warning("%s: Speed (%d) is not 10"
268 " or 100!\n", dev->name, phydev->speed);
269 break;
270 }
271
272 priv->speed = phydev->speed;
273 }
274
275 writel(ctrl, ioaddr + MAC_CTRL_REG);
276
277 if (!priv->oldlink) {
278 new_state = 1;
279 priv->oldlink = 1;
280 }
281 } else if (priv->oldlink) {
282 new_state = 1;
283 priv->oldlink = 0;
284 priv->speed = 0;
285 priv->oldduplex = -1;
286 }
287
288 if (new_state && netif_msg_link(priv))
289 phy_print_status(phydev);
290
291 spin_unlock_irqrestore(&priv->lock, flags);
292
293 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
294}
295
296/**
297 * stmmac_init_phy - PHY initialization
298 * @dev: net device structure
299 * Description: it initializes the driver's PHY state, and attaches the PHY
300 * to the mac driver.
301 * Return value:
302 * 0 on success
303 */
304static int stmmac_init_phy(struct net_device *dev)
305{
306 struct stmmac_priv *priv = netdev_priv(dev);
307 struct phy_device *phydev;
109cdd66
GC		 308 char phy_id[MII_BUS_ID_SIZE + 3];
309 char bus_id[MII_BUS_ID_SIZE];
47dd7a54
GC		 310
311 priv->oldlink = 0;
312 priv->speed = 0;
313 priv->oldduplex = -1;
314
315 if (priv->phy_addr == -1) {
316 /* We don't have a PHY, so do nothing */
317 return 0;
318 }
319
320 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
109cdd66
GC		 321 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
322 priv->phy_addr);
47dd7a54
GC		 323 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
324
325 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
326 priv->phy_interface);
327
328 if (IS_ERR(phydev)) {
329 pr_err("%s: Could not attach to PHY\n", dev->name);
330 return PTR_ERR(phydev);
331 }
332
333 /*
334 * Broken HW is sometimes missing the pull-up resistor on the
335 * MDIO line, which results in reads to non-existent devices returning
336 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
337 * device as well.
338 * Note: phydev->phy_id is the result of reading the UID PHY registers.
339 */
340 if (phydev->phy_id == 0) {
341 phy_disconnect(phydev);
342 return -ENODEV;
343 }
344 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
345 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
346
347 priv->phydev = phydev;
348
349 return 0;
350}
351
352static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
353{
354 u32 value = readl(ioaddr + MAC_CTRL_REG);
355 value |= MAC_RNABLE_RX;
356 /* Set the RE (receive enable bit into the MAC CTRL register). */
357 writel(value, ioaddr + MAC_CTRL_REG);
358}
359
360static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
361{
362 u32 value = readl(ioaddr + MAC_CTRL_REG);
363 value |= MAC_ENABLE_TX;
364 /* Set the TE (transmit enable bit into the MAC CTRL register). */
365 writel(value, ioaddr + MAC_CTRL_REG);
366}
367
368static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
369{
370 u32 value = readl(ioaddr + MAC_CTRL_REG);
371 value &= ~MAC_RNABLE_RX;
372 writel(value, ioaddr + MAC_CTRL_REG);
373}
374
375static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
376{
377 u32 value = readl(ioaddr + MAC_CTRL_REG);
378 value &= ~MAC_ENABLE_TX;
379 writel(value, ioaddr + MAC_CTRL_REG);
380}
381
382/**
383 * display_ring
384 * @p: pointer to the ring.
385 * @size: size of the ring.
386 * Description: display all the descriptors within the ring.
387 */
388static void display_ring(struct dma_desc *p, int size)
389{
390 struct tmp_s {
391 u64 a;
392 unsigned int b;
393 unsigned int c;
394 };
395 int i;
396 for (i = 0; i < size; i++) {
397 struct tmp_s *x = (struct tmp_s *)(p + i);
398 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
399 i, (unsigned int)virt_to_phys(&p[i]),
400 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
401 x->b, x->c);
402 pr_info("\n");
403 }
404}
405
406/**
407 * init_dma_desc_rings - init the RX/TX descriptor rings
408 * @dev: net device structure
409 * Description: this function initializes the DMA RX/TX descriptors
410 * and allocates the socket buffers.
411 */
412static void init_dma_desc_rings(struct net_device *dev)
413{
414 int i;
415 struct stmmac_priv *priv = netdev_priv(dev);
416 struct sk_buff *skb;
417 unsigned int txsize = priv->dma_tx_size;
418 unsigned int rxsize = priv->dma_rx_size;
419 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 420 int buff2_needed = 0, dis_ic = 0;
47dd7a54 421
47dd7a54
GC		 422 /* Set the Buffer size according to the MTU;
423 * indeed, in case of jumbo we need to bump-up the buffer sizes.
424 */
425 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
426 bfsize = BUF_SIZE_16KiB;
427 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
428 bfsize = BUF_SIZE_8KiB;
429 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
430 bfsize = BUF_SIZE_4KiB;
431 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
432 bfsize = BUF_SIZE_2KiB;
433 else
434 bfsize = DMA_BUFFER_SIZE;
435
73cfe264
GC		 436#ifdef CONFIG_STMMAC_TIMER
437 /* Disable interrupts on completion for the reception if timer is on */
438 if (likely(priv->tm->enable))
439 dis_ic = 1;
440#endif
47dd7a54
GC		 441 /* If the MTU exceeds 8k so use the second buffer in the chain */
442 if (bfsize >= BUF_SIZE_8KiB)
443 buff2_needed = 1;
444
445 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
446 txsize, rxsize, bfsize);
447
448 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
449 priv->rx_skbuff =
450 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
451 priv->dma_rx =
452 (struct dma_desc *)dma_alloc_coherent(priv->device,
453 rxsize *
454 sizeof(struct dma_desc),
455 &priv->dma_rx_phy,
456 GFP_KERNEL);
457 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
458 GFP_KERNEL);
459 priv->dma_tx =
460 (struct dma_desc *)dma_alloc_coherent(priv->device,
461 txsize *
462 sizeof(struct dma_desc),
463 &priv->dma_tx_phy,
464 GFP_KERNEL);
465
466 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
467 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
468 return;
469 }
470
471 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
472 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
473 dev->name, priv->dma_rx, priv->dma_tx,
474 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
475
476 /* RX INITIALIZATION */
477 DBG(probe, INFO, "stmmac: SKB addresses:\n"
478 "skb\t\tskb data\tdma data\n");
479
480 for (i = 0; i < rxsize; i++) {
481 struct dma_desc *p = priv->dma_rx + i;
482
483 skb = netdev_alloc_skb_ip_align(dev, bfsize);
484 if (unlikely(skb == NULL)) {
485 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
486 break;
487 }
488 priv->rx_skbuff[i] = skb;
489 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
490 bfsize, DMA_FROM_DEVICE);
491
492 p->des2 = priv->rx_skbuff_dma[i];
493 if (unlikely(buff2_needed))
494 p->des3 = p->des2 + BUF_SIZE_8KiB;
495 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
496 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
497 }
498 priv->cur_rx = 0;
499 priv->dirty_rx = (unsigned int)(i - rxsize);
500 priv->dma_buf_sz = bfsize;
501 buf_sz = bfsize;
502
503 /* TX INITIALIZATION */
504 for (i = 0; i < txsize; i++) {
505 priv->tx_skbuff[i] = NULL;
506 priv->dma_tx[i].des2 = 0;
507 }
508 priv->dirty_tx = 0;
509 priv->cur_tx = 0;
510
511 /* Clear the Rx/Tx descriptors */
512 priv->mac_type->ops->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
513 priv->mac_type->ops->init_tx_desc(priv->dma_tx, txsize);
514
515 if (netif_msg_hw(priv)) {
516 pr_info("RX descriptor ring:\n");
517 display_ring(priv->dma_rx, rxsize);
518 pr_info("TX descriptor ring:\n");
519 display_ring(priv->dma_tx, txsize);
520 }
521 return;
522}
523
524static void dma_free_rx_skbufs(struct stmmac_priv *priv)
525{
526 int i;
527
528 for (i = 0; i < priv->dma_rx_size; i++) {
529 if (priv->rx_skbuff[i]) {
530 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
531 priv->dma_buf_sz, DMA_FROM_DEVICE);
532 dev_kfree_skb_any(priv->rx_skbuff[i]);
533 }
534 priv->rx_skbuff[i] = NULL;
535 }
536 return;
537}
538
539static void dma_free_tx_skbufs(struct stmmac_priv *priv)
540{
541 int i;
542
543 for (i = 0; i < priv->dma_tx_size; i++) {
544 if (priv->tx_skbuff[i] != NULL) {
545 struct dma_desc *p = priv->dma_tx + i;
546 if (p->des2)
547 dma_unmap_single(priv->device, p->des2,
548 priv->mac_type->ops->get_tx_len(p),
549 DMA_TO_DEVICE);
550 dev_kfree_skb_any(priv->tx_skbuff[i]);
551 priv->tx_skbuff[i] = NULL;
552 }
553 }
554 return;
555}
556
557static void free_dma_desc_resources(struct stmmac_priv *priv)
558{
559 /* Release the DMA TX/RX socket buffers */
560 dma_free_rx_skbufs(priv);
561 dma_free_tx_skbufs(priv);
562
563 /* Free the region of consistent memory previously allocated for
564 * the DMA */
565 dma_free_coherent(priv->device,
566 priv->dma_tx_size * sizeof(struct dma_desc),
567 priv->dma_tx, priv->dma_tx_phy);
568 dma_free_coherent(priv->device,
569 priv->dma_rx_size * sizeof(struct dma_desc),
570 priv->dma_rx, priv->dma_rx_phy);
571 kfree(priv->rx_skbuff_dma);
572 kfree(priv->rx_skbuff);
573 kfree(priv->tx_skbuff);
574
575 return;
576}
577
578/**
579 * stmmac_dma_start_tx
580 * @ioaddr: device I/O address
581 * Description: this function starts the DMA tx process.
582 */
583static void stmmac_dma_start_tx(unsigned long ioaddr)
584{
585 u32 value = readl(ioaddr + DMA_CONTROL);
586 value |= DMA_CONTROL_ST;
587 writel(value, ioaddr + DMA_CONTROL);
588 return;
589}
590
591static void stmmac_dma_stop_tx(unsigned long ioaddr)
592{
593 u32 value = readl(ioaddr + DMA_CONTROL);
594 value &= ~DMA_CONTROL_ST;
595 writel(value, ioaddr + DMA_CONTROL);
596 return;
597}
598
599/**
600 * stmmac_dma_start_rx
601 * @ioaddr: device I/O address
602 * Description: this function starts the DMA rx process.
603 */
604static void stmmac_dma_start_rx(unsigned long ioaddr)
605{
606 u32 value = readl(ioaddr + DMA_CONTROL);
607 value |= DMA_CONTROL_SR;
608 writel(value, ioaddr + DMA_CONTROL);
609
610 return;
611}
612
613static void stmmac_dma_stop_rx(unsigned long ioaddr)
614{
615 u32 value = readl(ioaddr + DMA_CONTROL);
616 value &= ~DMA_CONTROL_SR;
617 writel(value, ioaddr + DMA_CONTROL);
618
619 return;
620}
621
622/**
623 * stmmac_dma_operation_mode - HW DMA operation mode
624 * @priv : pointer to the private device structure.
625 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
626 * or Store-And-Forward capability. It also verifies the COE for the
627 * transmission in case of Giga ETH.
628 */
629static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
630{
631 if (!priv->is_gmac) {
632 /* MAC 10/100 */
633 priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc, 0);
634 priv->tx_coe = NO_HW_CSUM;
635 } else {
636 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
637 priv->mac_type->ops->dma_mode(priv->dev->base_addr,
638 SF_DMA_MODE, SF_DMA_MODE);
639 tc = SF_DMA_MODE;
640 priv->tx_coe = HW_CSUM;
641 } else {
642 /* Checksum computation is performed in software. */
643 priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc,
644 SF_DMA_MODE);
645 priv->tx_coe = NO_HW_CSUM;
646 }
647 }
648 tx_coe = priv->tx_coe;
649
650 return;
651}
652
653#ifdef STMMAC_DEBUG
654/**
655 * show_tx_process_state
656 * @status: tx descriptor status field
657 * Description: it shows the Transmit Process State for CSR5[22:20]
658 */
659static void show_tx_process_state(unsigned int status)
660{
661 unsigned int state;
662 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
663
664 switch (state) {
665 case 0:
666 pr_info("- TX (Stopped): Reset or Stop command\n");
667 break;
668 case 1:
669 pr_info("- TX (Running):Fetching the Tx desc\n");
670 break;
671 case 2:
672 pr_info("- TX (Running): Waiting for end of tx\n");
673 break;
674 case 3:
675 pr_info("- TX (Running): Reading the data "
676 "and queuing the data into the Tx buf\n");
677 break;
678 case 6:
679 pr_info("- TX (Suspended): Tx Buff Underflow "
680 "or an unavailable Transmit descriptor\n");
681 break;
682 case 7:
683 pr_info("- TX (Running): Closing Tx descriptor\n");
684 break;
685 default:
686 break;
687 }
688 return;
689}
690
691/**
692 * show_rx_process_state
693 * @status: rx descriptor status field
694 * Description: it shows the Receive Process State for CSR5[19:17]
695 */
696static void show_rx_process_state(unsigned int status)
697{
698 unsigned int state;
699 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
700
701 switch (state) {
702 case 0:
703 pr_info("- RX (Stopped): Reset or Stop command\n");
704 break;
705 case 1:
706 pr_info("- RX (Running): Fetching the Rx desc\n");
707 break;
708 case 2:
709 pr_info("- RX (Running):Checking for end of pkt\n");
710 break;
711 case 3:
712 pr_info("- RX (Running): Waiting for Rx pkt\n");
713 break;
714 case 4:
715 pr_info("- RX (Suspended): Unavailable Rx buf\n");
716 break;
717 case 5:
718 pr_info("- RX (Running): Closing Rx descriptor\n");
719 break;
720 case 6:
721 pr_info("- RX(Running): Flushing the current frame"
722 " from the Rx buf\n");
723 break;
724 case 7:
725 pr_info("- RX (Running): Queuing the Rx frame"
726 " from the Rx buf into memory\n");
727 break;
728 default:
729 break;
730 }
731 return;
732}
733#endif
734
735/**
736 * stmmac_tx:
737 * @priv: private driver structure
738 * Description: it reclaims resources after transmission completes.
739 */
740static void stmmac_tx(struct stmmac_priv *priv)
741{
742 unsigned int txsize = priv->dma_tx_size;
743 unsigned long ioaddr = priv->dev->base_addr;
744
745 while (priv->dirty_tx != priv->cur_tx) {
746 int last;
747 unsigned int entry = priv->dirty_tx % txsize;
748 struct sk_buff *skb = priv->tx_skbuff[entry];
749 struct dma_desc *p = priv->dma_tx + entry;
750
751 /* Check if the descriptor is owned by the DMA. */
752 if (priv->mac_type->ops->get_tx_owner(p))
753 break;
754
755 /* Verify tx error by looking at the last segment */
756 last = priv->mac_type->ops->get_tx_ls(p);
757 if (likely(last)) {
758 int tx_error =
759 priv->mac_type->ops->tx_status(&priv->dev->stats,
760 &priv->xstats,
761 p, ioaddr);
762 if (likely(tx_error == 0)) {
763 priv->dev->stats.tx_packets++;
764 priv->xstats.tx_pkt_n++;
765 } else
766 priv->dev->stats.tx_errors++;
767 }
768 TX_DBG("%s: curr %d, dirty %d\n", __func__,
769 priv->cur_tx, priv->dirty_tx);
770
771 if (likely(p->des2))
772 dma_unmap_single(priv->device, p->des2,
773 priv->mac_type->ops->get_tx_len(p),
774 DMA_TO_DEVICE);
775 if (unlikely(p->des3))
776 p->des3 = 0;
777
778 if (likely(skb != NULL)) {
779 /*
780 * If there's room in the queue (limit it to size)
781 * we add this skb back into the pool,
782 * if it's the right size.
783 */
784 if ((skb_queue_len(&priv->rx_recycle) <
785 priv->dma_rx_size) &&
786 skb_recycle_check(skb, priv->dma_buf_sz))
787 __skb_queue_head(&priv->rx_recycle, skb);
788 else
789 dev_kfree_skb(skb);
790
791 priv->tx_skbuff[entry] = NULL;
792 }
793
794 priv->mac_type->ops->release_tx_desc(p);
795
796 entry = (++priv->dirty_tx) % txsize;
797 }
798 if (unlikely(netif_queue_stopped(priv->dev) &&
799 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
800 netif_tx_lock(priv->dev);
801 if (netif_queue_stopped(priv->dev) &&
802 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
803 TX_DBG("%s: restart transmit\n", __func__);
804 netif_wake_queue(priv->dev);
805 }
806 netif_tx_unlock(priv->dev);
807 }
808 return;
809}
810
811static inline void stmmac_enable_irq(struct stmmac_priv *priv)
812{
73cfe264
GC		 813#ifdef CONFIG_STMMAC_TIMER
814 if (likely(priv->tm->enable))
815 priv->tm->timer_start(tmrate);
816 else
47dd7a54 817#endif
73cfe264 818 writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA);
47dd7a54
GC		 819}
820
821static inline void stmmac_disable_irq(struct stmmac_priv *priv)
822{
73cfe264
GC		 823#ifdef CONFIG_STMMAC_TIMER
824 if (likely(priv->tm->enable))
825 priv->tm->timer_stop();
826 else
47dd7a54 827#endif
73cfe264 828 writel(0, priv->dev->base_addr + DMA_INTR_ENA);
47dd7a54
GC		 829}
830
831static int stmmac_has_work(struct stmmac_priv *priv)
832{
833 unsigned int has_work = 0;
834 int rxret, tx_work = 0;
835
836 rxret = priv->mac_type->ops->get_rx_owner(priv->dma_rx +
837 (priv->cur_rx % priv->dma_rx_size));
838
839 if (priv->dirty_tx != priv->cur_tx)
840 tx_work = 1;
841
842 if (likely(!rxret || tx_work))
843 has_work = 1;
844
845 return has_work;
846}
847
848static inline void _stmmac_schedule(struct stmmac_priv *priv)
849{
850 if (likely(stmmac_has_work(priv))) {
851 stmmac_disable_irq(priv);
852 napi_schedule(&priv->napi);
853 }
854}
855
856#ifdef CONFIG_STMMAC_TIMER
857void stmmac_schedule(struct net_device *dev)
858{
859 struct stmmac_priv *priv = netdev_priv(dev);
860
861 priv->xstats.sched_timer_n++;
862
863 _stmmac_schedule(priv);
864
865 return;
866}
867
868static void stmmac_no_timer_started(unsigned int x)
869{;
870};
871
872static void stmmac_no_timer_stopped(void)
873{;
874};
875#endif
876
877/**
878 * stmmac_tx_err:
879 * @priv: pointer to the private device structure
880 * Description: it cleans the descriptors and restarts the transmission
881 * in case of errors.
882 */
883static void stmmac_tx_err(struct stmmac_priv *priv)
884{
885 netif_stop_queue(priv->dev);
886
887 stmmac_dma_stop_tx(priv->dev->base_addr);
888 dma_free_tx_skbufs(priv);
889 priv->mac_type->ops->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
890 priv->dirty_tx = 0;
891 priv->cur_tx = 0;
892 stmmac_dma_start_tx(priv->dev->base_addr);
893
894 priv->dev->stats.tx_errors++;
895 netif_wake_queue(priv->dev);
896
897 return;
898}
899
900/**
901 * stmmac_dma_interrupt - Interrupt handler for the driver
902 * @dev: net device structure
903 * Description: Interrupt handler for the driver (DMA).
904 */
905static void stmmac_dma_interrupt(struct net_device *dev)
906{
907 unsigned long ioaddr = dev->base_addr;
908 struct stmmac_priv *priv = netdev_priv(dev);
909 /* read the status register (CSR5) */
910 u32 intr_status = readl(ioaddr + DMA_STATUS);
911
912 DBG(intr, INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
913
914#ifdef STMMAC_DEBUG
915 /* It displays the DMA transmit process state (CSR5 register) */
916 if (netif_msg_tx_done(priv))
917 show_tx_process_state(intr_status);
918 if (netif_msg_rx_status(priv))
919 show_rx_process_state(intr_status);
920#endif
921 /* ABNORMAL interrupts */
922 if (unlikely(intr_status & DMA_STATUS_AIS)) {
923 DBG(intr, INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
924 if (unlikely(intr_status & DMA_STATUS_UNF)) {
925 DBG(intr, INFO, "transmit underflow\n");
8e95a202 926 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
47dd7a54
GC		 927 /* Try to bump up the threshold */
928 tc += 64;
929 priv->mac_type->ops->dma_mode(ioaddr, tc,
930 SF_DMA_MODE);
931 priv->xstats.threshold = tc;
932 }
933 stmmac_tx_err(priv);
934 priv->xstats.tx_undeflow_irq++;
935 }
936 if (unlikely(intr_status & DMA_STATUS_TJT)) {
937 DBG(intr, INFO, "transmit jabber\n");
938 priv->xstats.tx_jabber_irq++;
939 }
940 if (unlikely(intr_status & DMA_STATUS_OVF)) {
941 DBG(intr, INFO, "recv overflow\n");
942 priv->xstats.rx_overflow_irq++;
943 }
944 if (unlikely(intr_status & DMA_STATUS_RU)) {
945 DBG(intr, INFO, "receive buffer unavailable\n");
946 priv->xstats.rx_buf_unav_irq++;
947 }
948 if (unlikely(intr_status & DMA_STATUS_RPS)) {
949 DBG(intr, INFO, "receive process stopped\n");
950 priv->xstats.rx_process_stopped_irq++;
951 }
952 if (unlikely(intr_status & DMA_STATUS_RWT)) {
953 DBG(intr, INFO, "receive watchdog\n");
954 priv->xstats.rx_watchdog_irq++;
955 }
956 if (unlikely(intr_status & DMA_STATUS_ETI)) {
957 DBG(intr, INFO, "transmit early interrupt\n");
958 priv->xstats.tx_early_irq++;
959 }
960 if (unlikely(intr_status & DMA_STATUS_TPS)) {
961 DBG(intr, INFO, "transmit process stopped\n");
962 priv->xstats.tx_process_stopped_irq++;
963 stmmac_tx_err(priv);
964 }
965 if (unlikely(intr_status & DMA_STATUS_FBI)) {
966 DBG(intr, INFO, "fatal bus error\n");
967 priv->xstats.fatal_bus_error_irq++;
968 stmmac_tx_err(priv);
969 }
970 }
971
972 /* TX/RX NORMAL interrupts */
973 if (intr_status & DMA_STATUS_NIS) {
974 priv->xstats.normal_irq_n++;
975 if (likely((intr_status & DMA_STATUS_RI) ||
976 (intr_status & (DMA_STATUS_TI))))
977 _stmmac_schedule(priv);
978 }
979
980 /* Optional hardware blocks, interrupts should be disabled */
981 if (unlikely(intr_status &
982 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
983 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
984
985 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
986 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
987
988 DBG(intr, INFO, "\n\n");
989
990 return;
991}
992
993/**
994 * stmmac_open - open entry point of the driver
995 * @dev : pointer to the device structure.
996 * Description:
997 * This function is the open entry point of the driver.
998 * Return value:
999 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1000 * file on failure.
1001 */
1002static int stmmac_open(struct net_device *dev)
1003{
1004 struct stmmac_priv *priv = netdev_priv(dev);
1005 unsigned long ioaddr = dev->base_addr;
1006 int ret;
1007
1008 /* Check that the MAC address is valid. If its not, refuse
1009 * to bring the device up. The user must specify an
1010 * address using the following linux command:
1011 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
1012 if (!is_valid_ether_addr(dev->dev_addr)) {
1013 random_ether_addr(dev->dev_addr);
1014 pr_warning("%s: generated random MAC address %pM\n", dev->name,
1015 dev->dev_addr);
1016 }
1017
1018 stmmac_verify_args();
1019
1020 ret = stmmac_init_phy(dev);
1021 if (unlikely(ret)) {
1022 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1023 return ret;
1024 }
1025
1026 /* Request the IRQ lines */
a0607fd3 1027 ret = request_irq(dev->irq, stmmac_interrupt,
47dd7a54
GC		 1028 IRQF_SHARED, dev->name, dev);
1029 if (unlikely(ret < 0)) {
1030 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1031 __func__, dev->irq, ret);
1032 return ret;
1033 }
1034
1035#ifdef CONFIG_STMMAC_TIMER
73cfe264 1036 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54
GC		 1037 if (unlikely(priv->tm == NULL)) {
1038 pr_err("%s: ERROR: timer memory alloc failed \n", __func__);
1039 return -ENOMEM;
1040 }
1041 priv->tm->freq = tmrate;
1042
73cfe264
GC		 1043 /* Test if the external timer can be actually used.
1044 * In case of failure continue without timer. */
47dd7a54 1045 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 1046 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 1047 tmrate = 0;
1048 priv->tm->freq = 0;
1049 priv->tm->timer_start = stmmac_no_timer_started;
1050 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 1051 } else
1052 priv->tm->enable = 1;
47dd7a54
GC		 1053#endif
1054
1055 /* Create and initialize the TX/RX descriptors chains. */
1056 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1057 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1058 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1059 init_dma_desc_rings(dev);
1060
1061 /* DMA initialization and SW reset */
1062 if (unlikely(priv->mac_type->ops->dma_init(ioaddr,
1063 priv->pbl, priv->dma_tx_phy, priv->dma_rx_phy) < 0)) {
1064
1065 pr_err("%s: DMA initialization failed\n", __func__);
1066 return -1;
1067 }
1068
1069 /* Copy the MAC addr into the HW */
1070 priv->mac_type->ops->set_umac_addr(ioaddr, dev->dev_addr, 0);
1071 /* Initialize the MAC Core */
1072 priv->mac_type->ops->core_init(ioaddr);
1073
1074 priv->shutdown = 0;
1075
1076 /* Initialise the MMC (if present) to disable all interrupts. */
1077 writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
1078 writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
1079
1080 /* Enable the MAC Rx/Tx */
1081 stmmac_mac_enable_rx(ioaddr);
1082 stmmac_mac_enable_tx(ioaddr);
1083
1084 /* Set the HW DMA mode and the COE */
1085 stmmac_dma_operation_mode(priv);
1086
1087 /* Extra statistics */
1088 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1089 priv->xstats.threshold = tc;
1090
1091 /* Start the ball rolling... */
1092 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1093 stmmac_dma_start_tx(ioaddr);
1094 stmmac_dma_start_rx(ioaddr);
1095
1096#ifdef CONFIG_STMMAC_TIMER
1097 priv->tm->timer_start(tmrate);
1098#endif
1099 /* Dump DMA/MAC registers */
1100 if (netif_msg_hw(priv)) {
1101 priv->mac_type->ops->dump_mac_regs(ioaddr);
1102 priv->mac_type->ops->dump_dma_regs(ioaddr);
1103 }
1104
1105 if (priv->phydev)
1106 phy_start(priv->phydev);
1107
1108 napi_enable(&priv->napi);
1109 skb_queue_head_init(&priv->rx_recycle);
1110 netif_start_queue(dev);
1111 return 0;
1112}
1113
1114/**
1115 * stmmac_release - close entry point of the driver
1116 * @dev : device pointer.
1117 * Description:
1118 * This is the stop entry point of the driver.
1119 */
1120static int stmmac_release(struct net_device *dev)
1121{
1122 struct stmmac_priv *priv = netdev_priv(dev);
1123
1124 /* Stop and disconnect the PHY */
1125 if (priv->phydev) {
1126 phy_stop(priv->phydev);
1127 phy_disconnect(priv->phydev);
1128 priv->phydev = NULL;
1129 }
1130
1131 netif_stop_queue(dev);
1132
1133#ifdef CONFIG_STMMAC_TIMER
1134 /* Stop and release the timer */
1135 stmmac_close_ext_timer();
1136 if (priv->tm != NULL)
1137 kfree(priv->tm);
1138#endif
1139 napi_disable(&priv->napi);
1140 skb_queue_purge(&priv->rx_recycle);
1141
1142 /* Free the IRQ lines */
1143 free_irq(dev->irq, dev);
1144
1145 /* Stop TX/RX DMA and clear the descriptors */
1146 stmmac_dma_stop_tx(dev->base_addr);
1147 stmmac_dma_stop_rx(dev->base_addr);
1148
1149 /* Release and free the Rx/Tx resources */
1150 free_dma_desc_resources(priv);
1151
1152 /* Disable the MAC core */
1153 stmmac_mac_disable_tx(dev->base_addr);
1154 stmmac_mac_disable_rx(dev->base_addr);
1155
1156 netif_carrier_off(dev);
1157
1158 return 0;
1159}
1160
1161/*
1162 * To perform emulated hardware segmentation on skb.
1163 */
1164static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
1165{
1166 struct sk_buff *segs, *curr_skb;
1167 int gso_segs = skb_shinfo(skb)->gso_segs;
1168
1169 /* Estimate the number of fragments in the worst case */
1170 if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
1171 netif_stop_queue(priv->dev);
1172 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
1173 __func__);
1174 if (stmmac_tx_avail(priv) < gso_segs)
1175 return NETDEV_TX_BUSY;
1176
1177 netif_wake_queue(priv->dev);
1178 }
1179 TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
1180 skb, skb->len);
1181
1182 segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
1183 if (unlikely(IS_ERR(segs)))
1184 goto sw_tso_end;
1185
1186 do {
1187 curr_skb = segs;
1188 segs = segs->next;
1189 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
1190 "*next %p\n", curr_skb->len, curr_skb, segs);
1191 curr_skb->next = NULL;
1192 stmmac_xmit(curr_skb, priv->dev);
1193 } while (segs);
1194
1195sw_tso_end:
1196 dev_kfree_skb(skb);
1197
1198 return NETDEV_TX_OK;
1199}
1200
1201static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1202 struct net_device *dev,
1203 int csum_insertion)
1204{
1205 struct stmmac_priv *priv = netdev_priv(dev);
1206 unsigned int nopaged_len = skb_headlen(skb);
1207 unsigned int txsize = priv->dma_tx_size;
1208 unsigned int entry = priv->cur_tx % txsize;
1209 struct dma_desc *desc = priv->dma_tx + entry;
1210
1211 if (nopaged_len > BUF_SIZE_8KiB) {
1212
1213 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1214
1215 desc->des2 = dma_map_single(priv->device, skb->data,
1216 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1217 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1218 priv->mac_type->ops->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1219 csum_insertion);
1220
1221 entry = (++priv->cur_tx) % txsize;
1222 desc = priv->dma_tx + entry;
1223
1224 desc->des2 = dma_map_single(priv->device,
1225 skb->data + BUF_SIZE_8KiB,
1226 buf2_size, DMA_TO_DEVICE);
1227 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1228 priv->mac_type->ops->prepare_tx_desc(desc, 0,
1229 buf2_size, csum_insertion);
1230 priv->mac_type->ops->set_tx_owner(desc);
1231 priv->tx_skbuff[entry] = NULL;
1232 } else {
1233 desc->des2 = dma_map_single(priv->device, skb->data,
1234 nopaged_len, DMA_TO_DEVICE);
1235 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1236 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len,
1237 csum_insertion);
1238 }
1239 return entry;
1240}
1241
1242/**
1243 * stmmac_xmit:
1244 * @skb : the socket buffer
1245 * @dev : device pointer
1246 * Description : Tx entry point of the driver.
1247 */
1248static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1249{
1250 struct stmmac_priv *priv = netdev_priv(dev);
1251 unsigned int txsize = priv->dma_tx_size;
1252 unsigned int entry;
1253 int i, csum_insertion = 0;
1254 int nfrags = skb_shinfo(skb)->nr_frags;
1255 struct dma_desc *desc, *first;
1256
1257 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1258 if (!netif_queue_stopped(dev)) {
1259 netif_stop_queue(dev);
1260 /* This is a hard error, log it. */
1261 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1262 __func__);
1263 }
1264 return NETDEV_TX_BUSY;
1265 }
1266
1267 entry = priv->cur_tx % txsize;
1268
1269#ifdef STMMAC_XMIT_DEBUG
1270 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1271 pr_info("stmmac xmit:\n"
1272 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1273 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1274 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1275 !skb_is_gso(skb) ? "isn't" : "is");
1276#endif
1277
1278 if (unlikely(skb_is_gso(skb)))
1279 return stmmac_sw_tso(priv, skb);
1280
1281 if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1282 if (likely(priv->tx_coe == NO_HW_CSUM))
1283 skb_checksum_help(skb);
1284 else
1285 csum_insertion = 1;
1286 }
1287
1288 desc = priv->dma_tx + entry;
1289 first = desc;
1290
1291#ifdef STMMAC_XMIT_DEBUG
1292 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1293 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1294 "\t\tn_frags: %d, ip_summed: %d\n",
1295 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1296#endif
1297 priv->tx_skbuff[entry] = skb;
1298 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1299 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1300 desc = priv->dma_tx + entry;
1301 } else {
1302 unsigned int nopaged_len = skb_headlen(skb);
1303 desc->des2 = dma_map_single(priv->device, skb->data,
1304 nopaged_len, DMA_TO_DEVICE);
1305 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len,
1306 csum_insertion);
1307 }
1308
1309 for (i = 0; i < nfrags; i++) {
1310 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1311 int len = frag->size;
1312
1313 entry = (++priv->cur_tx) % txsize;
1314 desc = priv->dma_tx + entry;
1315
1316 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1317 desc->des2 = dma_map_page(priv->device, frag->page,
1318 frag->page_offset,
1319 len, DMA_TO_DEVICE);
1320 priv->tx_skbuff[entry] = NULL;
1321 priv->mac_type->ops->prepare_tx_desc(desc, 0, len,
1322 csum_insertion);
1323 priv->mac_type->ops->set_tx_owner(desc);
1324 }
1325
1326 /* Interrupt on completition only for the latest segment */
1327 priv->mac_type->ops->close_tx_desc(desc);
73cfe264 1328
47dd7a54 1329#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1330 /* Clean IC while using timer */
1331 if (likely(priv->tm->enable))
1332 priv->mac_type->ops->clear_tx_ic(desc);
47dd7a54
GC		 1333#endif
1334 /* To avoid raise condition */
1335 priv->mac_type->ops->set_tx_owner(first);
1336
1337 priv->cur_tx++;
1338
1339#ifdef STMMAC_XMIT_DEBUG
1340 if (netif_msg_pktdata(priv)) {
1341 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1342 "first=%p, nfrags=%d\n",
1343 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1344 entry, first, nfrags);
1345 display_ring(priv->dma_tx, txsize);
1346 pr_info(">>> frame to be transmitted: ");
1347 print_pkt(skb->data, skb->len);
1348 }
1349#endif
1350 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1351 TX_DBG("%s: stop transmitted packets\n", __func__);
1352 netif_stop_queue(dev);
1353 }
1354
1355 dev->stats.tx_bytes += skb->len;
1356
1357 /* CSR1 enables the transmit DMA to check for new descriptor */
1358 writel(1, dev->base_addr + DMA_XMT_POLL_DEMAND);
1359
1360 return NETDEV_TX_OK;
1361}
1362
1363static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1364{
1365 unsigned int rxsize = priv->dma_rx_size;
1366 int bfsize = priv->dma_buf_sz;
1367 struct dma_desc *p = priv->dma_rx;
1368
1369 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1370 unsigned int entry = priv->dirty_rx % rxsize;
1371 if (likely(priv->rx_skbuff[entry] == NULL)) {
1372 struct sk_buff *skb;
1373
1374 skb = __skb_dequeue(&priv->rx_recycle);
1375 if (skb == NULL)
1376 skb = netdev_alloc_skb_ip_align(priv->dev,
1377 bfsize);
1378
1379 if (unlikely(skb == NULL))
1380 break;
1381
1382 priv->rx_skbuff[entry] = skb;
1383 priv->rx_skbuff_dma[entry] =
1384 dma_map_single(priv->device, skb->data, bfsize,
1385 DMA_FROM_DEVICE);
1386
1387 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1388 if (unlikely(priv->is_gmac)) {
1389 if (bfsize >= BUF_SIZE_8KiB)
1390 (p + entry)->des3 =
1391 (p + entry)->des2 + BUF_SIZE_8KiB;
1392 }
1393 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1394 }
1395 priv->mac_type->ops->set_rx_owner(p + entry);
1396 }
1397 return;
1398}
1399
1400static int stmmac_rx(struct stmmac_priv *priv, int limit)
1401{
1402 unsigned int rxsize = priv->dma_rx_size;
1403 unsigned int entry = priv->cur_rx % rxsize;
1404 unsigned int next_entry;
1405 unsigned int count = 0;
1406 struct dma_desc *p = priv->dma_rx + entry;
1407 struct dma_desc *p_next;
1408
1409#ifdef STMMAC_RX_DEBUG
1410 if (netif_msg_hw(priv)) {
1411 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1412 display_ring(priv->dma_rx, rxsize);
1413 }
1414#endif
1415 count = 0;
1416 while (!priv->mac_type->ops->get_rx_owner(p)) {
1417 int status;
1418
1419 if (count >= limit)
1420 break;
1421
1422 count++;
1423
1424 next_entry = (++priv->cur_rx) % rxsize;
1425 p_next = priv->dma_rx + next_entry;
1426 prefetch(p_next);
1427
1428 /* read the status of the incoming frame */
1429 status = (priv->mac_type->ops->rx_status(&priv->dev->stats,
1430 &priv->xstats, p));
1431 if (unlikely(status == discard_frame))
1432 priv->dev->stats.rx_errors++;
1433 else {
1434 struct sk_buff *skb;
1435 /* Length should omit the CRC */
1436 int frame_len =
1437 priv->mac_type->ops->get_rx_frame_len(p) - 4;
1438
1439#ifdef STMMAC_RX_DEBUG
1440 if (frame_len > ETH_FRAME_LEN)
1441 pr_debug("\tRX frame size %d, COE status: %d\n",
1442 frame_len, status);
1443
1444 if (netif_msg_hw(priv))
1445 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1446 p, entry, p->des2);
1447#endif
1448 skb = priv->rx_skbuff[entry];
1449 if (unlikely(!skb)) {
1450 pr_err("%s: Inconsistent Rx descriptor chain\n",
1451 priv->dev->name);
1452 priv->dev->stats.rx_dropped++;
1453 break;
1454 }
1455 prefetch(skb->data - NET_IP_ALIGN);
1456 priv->rx_skbuff[entry] = NULL;
1457
1458 skb_put(skb, frame_len);
1459 dma_unmap_single(priv->device,
1460 priv->rx_skbuff_dma[entry],
1461 priv->dma_buf_sz, DMA_FROM_DEVICE);
1462#ifdef STMMAC_RX_DEBUG
1463 if (netif_msg_pktdata(priv)) {
1464 pr_info(" frame received (%dbytes)", frame_len);
1465 print_pkt(skb->data, frame_len);
1466 }
1467#endif
1468 skb->protocol = eth_type_trans(skb, priv->dev);
1469
1470 if (unlikely(status == csum_none)) {
1471 /* always for the old mac 10/100 */
1472 skb->ip_summed = CHECKSUM_NONE;
1473 netif_receive_skb(skb);
1474 } else {
1475 skb->ip_summed = CHECKSUM_UNNECESSARY;
1476 napi_gro_receive(&priv->napi, skb);
1477 }
1478
1479 priv->dev->stats.rx_packets++;
1480 priv->dev->stats.rx_bytes += frame_len;
1481 priv->dev->last_rx = jiffies;
1482 }
1483 entry = next_entry;
1484 p = p_next; /* use prefetched values */
1485 }
1486
1487 stmmac_rx_refill(priv);
1488
1489 priv->xstats.rx_pkt_n += count;
1490
1491 return count;
1492}
1493
1494/**
1495 * stmmac_poll - stmmac poll method (NAPI)
1496 * @napi : pointer to the napi structure.
1497 * @budget : maximum number of packets that the current CPU can receive from
1498 * all interfaces.
1499 * Description :
1500 * This function implements the the reception process.
1501 * Also it runs the TX completion thread
1502 */
1503static int stmmac_poll(struct napi_struct *napi, int budget)
1504{
1505 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1506 int work_done = 0;
1507
1508 priv->xstats.poll_n++;
1509 stmmac_tx(priv);
1510 work_done = stmmac_rx(priv, budget);
1511
1512 if (work_done < budget) {
1513 napi_complete(napi);
1514 stmmac_enable_irq(priv);
1515 }
1516 return work_done;
1517}
1518
1519/**
1520 * stmmac_tx_timeout
1521 * @dev : Pointer to net device structure
1522 * Description: this function is called when a packet transmission fails to
1523 * complete within a reasonable tmrate. The driver will mark the error in the
1524 * netdev structure and arrange for the device to be reset to a sane state
1525 * in order to transmit a new packet.
1526 */
1527static void stmmac_tx_timeout(struct net_device *dev)
1528{
1529 struct stmmac_priv *priv = netdev_priv(dev);
1530
1531 /* Clear Tx resources and restart transmitting again */
1532 stmmac_tx_err(priv);
1533 return;
1534}
1535
1536/* Configuration changes (passed on by ifconfig) */
1537static int stmmac_config(struct net_device *dev, struct ifmap *map)
1538{
1539 if (dev->flags & IFF_UP) /* can't act on a running interface */
1540 return -EBUSY;
1541
1542 /* Don't allow changing the I/O address */
1543 if (map->base_addr != dev->base_addr) {
1544 pr_warning("%s: can't change I/O address\n", dev->name);
1545 return -EOPNOTSUPP;
1546 }
1547
1548 /* Don't allow changing the IRQ */
1549 if (map->irq != dev->irq) {
1550 pr_warning("%s: can't change IRQ number %d\n",
1551 dev->name, dev->irq);
1552 return -EOPNOTSUPP;
1553 }
1554
1555 /* ignore other fields */
1556 return 0;
1557}
1558
1559/**
1560 * stmmac_multicast_list - entry point for multicast addressing
1561 * @dev : pointer to the device structure
1562 * Description:
1563 * This function is a driver entry point which gets called by the kernel
1564 * whenever multicast addresses must be enabled/disabled.
1565 * Return value:
1566 * void.
1567 */
1568static void stmmac_multicast_list(struct net_device *dev)
1569{
1570 struct stmmac_priv *priv = netdev_priv(dev);
1571
1572 spin_lock(&priv->lock);
1573 priv->mac_type->ops->set_filter(dev);
1574 spin_unlock(&priv->lock);
1575 return;
1576}
1577
1578/**
1579 * stmmac_change_mtu - entry point to change MTU size for the device.
1580 * @dev : device pointer.
1581 * @new_mtu : the new MTU size for the device.
1582 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1583 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1584 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1585 * Return value:
1586 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1587 * file on failure.
1588 */
1589static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1590{
1591 struct stmmac_priv *priv = netdev_priv(dev);
1592 int max_mtu;
1593
1594 if (netif_running(dev)) {
1595 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1596 return -EBUSY;
1597 }
1598
1599 if (priv->is_gmac)
1600 max_mtu = JUMBO_LEN;
1601 else
1602 max_mtu = ETH_DATA_LEN;
1603
1604 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1605 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1606 return -EINVAL;
1607 }
1608
1609 dev->mtu = new_mtu;
1610
1611 return 0;
1612}
1613
1614static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1615{
1616 struct net_device *dev = (struct net_device *)dev_id;
1617 struct stmmac_priv *priv = netdev_priv(dev);
1618
1619 if (unlikely(!dev)) {
1620 pr_err("%s: invalid dev pointer\n", __func__);
1621 return IRQ_NONE;
1622 }
1623
1624 if (priv->is_gmac) {
1625 unsigned long ioaddr = dev->base_addr;
1626 /* To handle GMAC own interrupts */
1627 priv->mac_type->ops->host_irq_status(ioaddr);
1628 }
1629 stmmac_dma_interrupt(dev);
1630
1631 return IRQ_HANDLED;
1632}
1633
1634#ifdef CONFIG_NET_POLL_CONTROLLER
1635/* Polling receive - used by NETCONSOLE and other diagnostic tools
1636 * to allow network I/O with interrupts disabled. */
1637static void stmmac_poll_controller(struct net_device *dev)
1638{
1639 disable_irq(dev->irq);
1640 stmmac_interrupt(dev->irq, dev);
1641 enable_irq(dev->irq);
1642}
1643#endif
1644
1645/**
1646 * stmmac_ioctl - Entry point for the Ioctl
1647 * @dev: Device pointer.
1648 * @rq: An IOCTL specefic structure, that can contain a pointer to
1649 * a proprietary structure used to pass information to the driver.
1650 * @cmd: IOCTL command
1651 * Description:
1652 * Currently there are no special functionality supported in IOCTL, just the
1653 * phy_mii_ioctl(...) can be invoked.
1654 */
1655static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1656{
1657 struct stmmac_priv *priv = netdev_priv(dev);
1658 int ret = -EOPNOTSUPP;
1659
1660 if (!netif_running(dev))
1661 return -EINVAL;
1662
1663 switch (cmd) {
1664 case SIOCGMIIPHY:
1665 case SIOCGMIIREG:
1666 case SIOCSMIIREG:
1667 if (!priv->phydev)
1668 return -EINVAL;
1669
1670 spin_lock(&priv->lock);
1671 ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1672 spin_unlock(&priv->lock);
1673 default:
1674 break;
1675 }
1676 return ret;
1677}
1678
1679#ifdef STMMAC_VLAN_TAG_USED
1680static void stmmac_vlan_rx_register(struct net_device *dev,
1681 struct vlan_group *grp)
1682{
1683 struct stmmac_priv *priv = netdev_priv(dev);
1684
1685 DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1686
1687 spin_lock(&priv->lock);
1688 priv->vlgrp = grp;
1689 spin_unlock(&priv->lock);
1690
1691 return;
1692}
1693#endif
1694
1695static const struct net_device_ops stmmac_netdev_ops = {
1696 .ndo_open = stmmac_open,
1697 .ndo_start_xmit = stmmac_xmit,
1698 .ndo_stop = stmmac_release,
1699 .ndo_change_mtu = stmmac_change_mtu,
1700 .ndo_set_multicast_list = stmmac_multicast_list,
1701 .ndo_tx_timeout = stmmac_tx_timeout,
1702 .ndo_do_ioctl = stmmac_ioctl,
1703 .ndo_set_config = stmmac_config,
1704#ifdef STMMAC_VLAN_TAG_USED
1705 .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1706#endif
1707#ifdef CONFIG_NET_POLL_CONTROLLER
1708 .ndo_poll_controller = stmmac_poll_controller,
1709#endif
1710 .ndo_set_mac_address = eth_mac_addr,
1711};
1712
1713/**
1714 * stmmac_probe - Initialization of the adapter .
1715 * @dev : device pointer
1716 * Description: The function initializes the network device structure for
1717 * the STMMAC driver. It also calls the low level routines
1718 * in order to init the HW (i.e. the DMA engine)
1719 */
1720static int stmmac_probe(struct net_device *dev)
1721{
1722 int ret = 0;
1723 struct stmmac_priv *priv = netdev_priv(dev);
1724
1725 ether_setup(dev);
1726
1727 dev->netdev_ops = &stmmac_netdev_ops;
1728 stmmac_set_ethtool_ops(dev);
1729
1730 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1731 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1732#ifdef STMMAC_VLAN_TAG_USED
1733 /* Both mac100 and gmac support receive VLAN tag detection */
1734 dev->features |= NETIF_F_HW_VLAN_RX;
1735#endif
1736 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1737
1738 if (priv->is_gmac)
1739 priv->rx_csum = 1;
1740
1741 if (flow_ctrl)
1742 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1743
1744 priv->pause = pause;
1745 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1746
1747 /* Get the MAC address */
1748 priv->mac_type->ops->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
1749
1750 if (!is_valid_ether_addr(dev->dev_addr))
1751 pr_warning("\tno valid MAC address;"
1752 "please, use ifconfig or nwhwconfig!\n");
1753
1754 ret = register_netdev(dev);
1755 if (ret) {
1756 pr_err("%s: ERROR %i registering the device\n",
1757 __func__, ret);
1758 return -ENODEV;
1759 }
1760
1761 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1762 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1763 (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1764
1765 spin_lock_init(&priv->lock);
1766
1767 return ret;
1768}
1769
1770/**
1771 * stmmac_mac_device_setup
1772 * @dev : device pointer
1773 * Description: select and initialise the mac device (mac100 or Gmac).
1774 */
1775static int stmmac_mac_device_setup(struct net_device *dev)
1776{
1777 struct stmmac_priv *priv = netdev_priv(dev);
1778 unsigned long ioaddr = dev->base_addr;
1779
1780 struct mac_device_info *device;
1781
1782 if (priv->is_gmac)
1783 device = gmac_setup(ioaddr);
1784 else
1785 device = mac100_setup(ioaddr);
1786
1787 if (!device)
1788 return -ENOMEM;
1789
1790 priv->mac_type = device;
1791
1792 priv->wolenabled = priv->mac_type->hw.pmt; /* PMT supported */
1793 if (priv->wolenabled == PMT_SUPPORTED)
1794 priv->wolopts = WAKE_MAGIC; /* Magic Frame */
1795
1796 return 0;
1797}
1798
1799static int stmmacphy_dvr_probe(struct platform_device *pdev)
1800{
1801 struct plat_stmmacphy_data *plat_dat;
1802 plat_dat = (struct plat_stmmacphy_data *)((pdev->dev).platform_data);
1803
1804 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1805 plat_dat->bus_id);
1806
1807 return 0;
1808}
1809
1810static int stmmacphy_dvr_remove(struct platform_device *pdev)
1811{
1812 return 0;
1813}
1814
1815static struct platform_driver stmmacphy_driver = {
1816 .driver = {
1817 .name = PHY_RESOURCE_NAME,
1818 },
1819 .probe = stmmacphy_dvr_probe,
1820 .remove = stmmacphy_dvr_remove,
1821};
1822
1823/**
1824 * stmmac_associate_phy
1825 * @dev: pointer to device structure
1826 * @data: points to the private structure.
1827 * Description: Scans through all the PHYs we have registered and checks if
1828 * any are associated with our MAC. If so, then just fill in
1829 * the blanks in our local context structure
1830 */
1831static int stmmac_associate_phy(struct device *dev, void *data)
1832{
1833 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1834 struct plat_stmmacphy_data *plat_dat;
1835
1836 plat_dat = (struct plat_stmmacphy_data *)(dev->platform_data);
1837
1838 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1839 plat_dat->bus_id);
1840
1841 /* Check that this phy is for the MAC being initialised */
1842 if (priv->bus_id != plat_dat->bus_id)
1843 return 0;
1844
1845 /* OK, this PHY is connected to the MAC.
1846 Go ahead and get the parameters */
1847 DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1848 priv->phy_irq =
1849 platform_get_irq_byname(to_platform_device(dev), "phyirq");
1850 DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1851 plat_dat->bus_id, priv->phy_irq);
1852
1853 /* Override with kernel parameters if supplied XXX CRS XXX
1854 * this needs to have multiple instances */
1855 if ((phyaddr >= 0) && (phyaddr <= 31))
1856 plat_dat->phy_addr = phyaddr;
1857
1858 priv->phy_addr = plat_dat->phy_addr;
1859 priv->phy_mask = plat_dat->phy_mask;
1860 priv->phy_interface = plat_dat->interface;
1861 priv->phy_reset = plat_dat->phy_reset;
1862
1863 DBG(probe, DEBUG, "%s: exiting\n", __func__);
1864 return 1; /* forces exit of driver_for_each_device() */
1865}
1866
1867/**
1868 * stmmac_dvr_probe
1869 * @pdev: platform device pointer
1870 * Description: the driver is initialized through platform_device.
1871 */
1872static int stmmac_dvr_probe(struct platform_device *pdev)
1873{
1874 int ret = 0;
1875 struct resource *res;
1876 unsigned int *addr = NULL;
1877 struct net_device *ndev = NULL;
1878 struct stmmac_priv *priv;
1879 struct plat_stmmacenet_data *plat_dat;
1880
1881 pr_info("STMMAC driver:\n\tplatform registration... ");
1882 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1883 if (!res) {
1884 ret = -ENODEV;
1885 goto out;
1886 }
1887 pr_info("done!\n");
1888
1889 if (!request_mem_region(res->start, (res->end - res->start),
1890 pdev->name)) {
1891 pr_err("%s: ERROR: memory allocation failed"
1892 "cannot get the I/O addr 0x%x\n",
1893 __func__, (unsigned int)res->start);
1894 ret = -EBUSY;
1895 goto out;
1896 }
1897
1898 addr = ioremap(res->start, (res->end - res->start));
1899 if (!addr) {
1900 pr_err("%s: ERROR: memory mapping failed \n", __func__);
1901 ret = -ENOMEM;
1902 goto out;
1903 }
1904
1905 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1906 if (!ndev) {
1907 pr_err("%s: ERROR: allocating the device\n", __func__);
1908 ret = -ENOMEM;
1909 goto out;
1910 }
1911
1912 SET_NETDEV_DEV(ndev, &pdev->dev);
1913
1914 /* Get the MAC information */
1915 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1916 if (ndev->irq == -ENXIO) {
1917 pr_err("%s: ERROR: MAC IRQ configuration "
1918 "information not found\n", __func__);
1919 ret = -ENODEV;
1920 goto out;
1921 }
1922
1923 priv = netdev_priv(ndev);
1924 priv->device = &(pdev->dev);
1925 priv->dev = ndev;
1926 plat_dat = (struct plat_stmmacenet_data *)((pdev->dev).platform_data);
1927 priv->bus_id = plat_dat->bus_id;
1928 priv->pbl = plat_dat->pbl; /* TLI */
1929 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
1930
1931 platform_set_drvdata(pdev, ndev);
1932
1933 /* Set the I/O base addr */
1934 ndev->base_addr = (unsigned long)addr;
1935
1936 /* MAC HW revice detection */
1937 ret = stmmac_mac_device_setup(ndev);
1938 if (ret < 0)
1939 goto out;
1940
1941 /* Network Device Registration */
1942 ret = stmmac_probe(ndev);
1943 if (ret < 0)
1944 goto out;
1945
1946 /* associate a PHY - it is provided by another platform bus */
1947 if (!driver_for_each_device
1948 (&(stmmacphy_driver.driver), NULL, (void *)priv,
1949 stmmac_associate_phy)) {
1950 pr_err("No PHY device is associated with this MAC!\n");
1951 ret = -ENODEV;
1952 goto out;
1953 }
1954
1955 priv->fix_mac_speed = plat_dat->fix_mac_speed;
1956 priv->bsp_priv = plat_dat->bsp_priv;
1957
1958 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1959 "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1960 pdev->id, ndev->irq, (unsigned int)addr);
1961
1962 /* MDIO bus Registration */
1963 pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1964 ret = stmmac_mdio_register(ndev);
1965 if (ret < 0)
1966 goto out;
1967 pr_debug("registered!\n");
1968
1969out:
1970 if (ret < 0) {
1971 platform_set_drvdata(pdev, NULL);
1972 release_mem_region(res->start, (res->end - res->start));
1973 if (addr != NULL)
1974 iounmap(addr);
1975 }
1976
1977 return ret;
1978}
1979
1980/**
1981 * stmmac_dvr_remove
1982 * @pdev: platform device pointer
1983 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1984 * changes the link status, releases the DMA descriptor rings,
1985 * unregisters the MDIO bus and unmaps the allocated memory.
1986 */
1987static int stmmac_dvr_remove(struct platform_device *pdev)
1988{
1989 struct net_device *ndev = platform_get_drvdata(pdev);
1990 struct resource *res;
1991
1992 pr_info("%s:\n\tremoving driver", __func__);
1993
1994 stmmac_dma_stop_rx(ndev->base_addr);
1995 stmmac_dma_stop_tx(ndev->base_addr);
1996
1997 stmmac_mac_disable_rx(ndev->base_addr);
1998 stmmac_mac_disable_tx(ndev->base_addr);
1999
2000 netif_carrier_off(ndev);
2001
2002 stmmac_mdio_unregister(ndev);
2003
2004 platform_set_drvdata(pdev, NULL);
2005 unregister_netdev(ndev);
2006
2007 iounmap((void *)ndev->base_addr);
2008 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2009 release_mem_region(res->start, (res->end - res->start));
2010
2011 free_netdev(ndev);
2012
2013 return 0;
2014}
2015
2016#ifdef CONFIG_PM
2017static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
2018{
2019 struct net_device *dev = platform_get_drvdata(pdev);
2020 struct stmmac_priv *priv = netdev_priv(dev);
2021 int dis_ic = 0;
2022
2023 if (!dev || !netif_running(dev))
2024 return 0;
2025
2026 spin_lock(&priv->lock);
2027
2028 if (state.event == PM_EVENT_SUSPEND) {
2029 netif_device_detach(dev);
2030 netif_stop_queue(dev);
2031 if (priv->phydev)
2032 phy_stop(priv->phydev);
2033
2034#ifdef CONFIG_STMMAC_TIMER
2035 priv->tm->timer_stop();
73cfe264
GC		 2036 if (likely(priv->tm->enable))
2037 dis_ic = 1;
47dd7a54
GC		 2038#endif
2039 napi_disable(&priv->napi);
2040
2041 /* Stop TX/RX DMA */
2042 stmmac_dma_stop_tx(dev->base_addr);
2043 stmmac_dma_stop_rx(dev->base_addr);
2044 /* Clear the Rx/Tx descriptors */
2045 priv->mac_type->ops->init_rx_desc(priv->dma_rx,
2046 priv->dma_rx_size, dis_ic);
2047 priv->mac_type->ops->init_tx_desc(priv->dma_tx,
2048 priv->dma_tx_size);
2049
2050 stmmac_mac_disable_tx(dev->base_addr);
2051
2052 if (device_may_wakeup(&(pdev->dev))) {
2053 /* Enable Power down mode by programming the PMT regs */
2054 if (priv->wolenabled == PMT_SUPPORTED)
2055 priv->mac_type->ops->pmt(dev->base_addr,
2056 priv->wolopts);
2057 } else {
2058 stmmac_mac_disable_rx(dev->base_addr);
2059 }
2060 } else {
2061 priv->shutdown = 1;
2062 /* Although this can appear slightly redundant it actually
2063 * makes fast the standby operation and guarantees the driver
2064 * working if hibernation is on media. */
2065 stmmac_release(dev);
2066 }
2067
2068 spin_unlock(&priv->lock);
2069 return 0;
2070}
2071
2072static int stmmac_resume(struct platform_device *pdev)
2073{
2074 struct net_device *dev = platform_get_drvdata(pdev);
2075 struct stmmac_priv *priv = netdev_priv(dev);
2076 unsigned long ioaddr = dev->base_addr;
2077
2078 if (!netif_running(dev))
2079 return 0;
2080
2081 spin_lock(&priv->lock);
2082
2083 if (priv->shutdown) {
2084 /* Re-open the interface and re-init the MAC/DMA
2085 and the rings. */
2086 stmmac_open(dev);
2087 goto out_resume;
2088 }
2089
2090 /* Power Down bit, into the PM register, is cleared
2091 * automatically as soon as a magic packet or a Wake-up frame
2092 * is received. Anyway, it's better to manually clear
2093 * this bit because it can generate problems while resuming
2094 * from another devices (e.g. serial console). */
2095 if (device_may_wakeup(&(pdev->dev)))
2096 if (priv->wolenabled == PMT_SUPPORTED)
2097 priv->mac_type->ops->pmt(dev->base_addr, 0);
2098
2099 netif_device_attach(dev);
2100
2101 /* Enable the MAC and DMA */
2102 stmmac_mac_enable_rx(ioaddr);
2103 stmmac_mac_enable_tx(ioaddr);
2104 stmmac_dma_start_tx(ioaddr);
2105 stmmac_dma_start_rx(ioaddr);
2106
2107#ifdef CONFIG_STMMAC_TIMER
2108 priv->tm->timer_start(tmrate);
2109#endif
2110 napi_enable(&priv->napi);
2111
2112 if (priv->phydev)
2113 phy_start(priv->phydev);
2114
2115 netif_start_queue(dev);
2116
2117out_resume:
2118 spin_unlock(&priv->lock);
2119 return 0;
2120}
2121#endif
2122
2123static struct platform_driver stmmac_driver = {
2124 .driver = {
2125 .name = STMMAC_RESOURCE_NAME,
2126 },
2127 .probe = stmmac_dvr_probe,
2128 .remove = stmmac_dvr_remove,
2129#ifdef CONFIG_PM
2130 .suspend = stmmac_suspend,
2131 .resume = stmmac_resume,
2132#endif
2133
2134};
2135
2136/**
2137 * stmmac_init_module - Entry point for the driver
2138 * Description: This function is the entry point for the driver.
2139 */
2140static int __init stmmac_init_module(void)
2141{
2142 int ret;
2143
2144 if (platform_driver_register(&stmmacphy_driver)) {
2145 pr_err("No PHY devices registered!\n");
2146 return -ENODEV;
2147 }
2148
2149 ret = platform_driver_register(&stmmac_driver);
2150 return ret;
2151}
2152
2153/**
2154 * stmmac_cleanup_module - Cleanup routine for the driver
2155 * Description: This function is the cleanup routine for the driver.
2156 */
2157static void __exit stmmac_cleanup_module(void)
2158{
2159 platform_driver_unregister(&stmmacphy_driver);
2160 platform_driver_unregister(&stmmac_driver);
2161}
2162
2163#ifndef MODULE
2164static int __init stmmac_cmdline_opt(char *str)
2165{
2166 char *opt;
2167
2168 if (!str || !*str)
2169 return -EINVAL;
2170 while ((opt = strsep(&str, ",")) != NULL) {
2171 if (!strncmp(opt, "debug:", 6))
2172 strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
2173 else if (!strncmp(opt, "phyaddr:", 8))
2174 strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
2175 else if (!strncmp(opt, "dma_txsize:", 11))
2176 strict_strtoul(opt + 11, 0,
2177 (unsigned long *)&dma_txsize);
2178 else if (!strncmp(opt, "dma_rxsize:", 11))
2179 strict_strtoul(opt + 11, 0,
2180 (unsigned long *)&dma_rxsize);
2181 else if (!strncmp(opt, "buf_sz:", 7))
2182 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
2183 else if (!strncmp(opt, "tc:", 3))
2184 strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
2185 else if (!strncmp(opt, "tx_coe:", 7))
2186 strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
2187 else if (!strncmp(opt, "watchdog:", 9))
2188 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
2189 else if (!strncmp(opt, "flow_ctrl:", 10))
2190 strict_strtoul(opt + 10, 0,
2191 (unsigned long *)&flow_ctrl);
2192 else if (!strncmp(opt, "pause:", 6))
2193 strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
2194#ifdef CONFIG_STMMAC_TIMER
2195 else if (!strncmp(opt, "tmrate:", 7))
2196 strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
2197#endif
2198 }
2199 return 0;
2200}
2201
2202__setup("stmmaceth=", stmmac_cmdline_opt);
2203#endif
2204
2205module_init(stmmac_init_module);
2206module_exit(stmmac_cleanup_module);
2207
2208MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2209MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2210MODULE_LICENSE("GPL");
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