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[net-next-2.6.git] / drivers / net / stmmac / stmmac_main.c
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47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
47dd7a54
GC		 47#include "stmmac.h"
48
49#define STMMAC_RESOURCE_NAME "stmmaceth"
50#define PHY_RESOURCE_NAME "stmmacphy"
51
52#undef STMMAC_DEBUG
53/*#define STMMAC_DEBUG*/
54#ifdef STMMAC_DEBUG
55#define DBG(nlevel, klevel, fmt, args...) \
56 ((void)(netif_msg_##nlevel(priv) && \
57 printk(KERN_##klevel fmt, ## args)))
58#else
59#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
60#endif
61
62#undef STMMAC_RX_DEBUG
63/*#define STMMAC_RX_DEBUG*/
64#ifdef STMMAC_RX_DEBUG
65#define RX_DBG(fmt, args...) printk(fmt, ## args)
66#else
67#define RX_DBG(fmt, args...) do { } while (0)
68#endif
69
70#undef STMMAC_XMIT_DEBUG
71/*#define STMMAC_XMIT_DEBUG*/
72#ifdef STMMAC_TX_DEBUG
73#define TX_DBG(fmt, args...) printk(fmt, ## args)
74#else
75#define TX_DBG(fmt, args...) do { } while (0)
76#endif
77
78#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
79#define JUMBO_LEN 9000
80
81/* Module parameters */
82#define TX_TIMEO 5000 /* default 5 seconds */
83static int watchdog = TX_TIMEO;
84module_param(watchdog, int, S_IRUGO | S_IWUSR);
85MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
86
87static int debug = -1; /* -1: default, 0: no output, 16: all */
88module_param(debug, int, S_IRUGO | S_IWUSR);
89MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
90
91static int phyaddr = -1;
92module_param(phyaddr, int, S_IRUGO);
93MODULE_PARM_DESC(phyaddr, "Physical device address");
94
95#define DMA_TX_SIZE 256
96static int dma_txsize = DMA_TX_SIZE;
97module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
98MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
99
100#define DMA_RX_SIZE 256
101static int dma_rxsize = DMA_RX_SIZE;
102module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
103MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
104
105static int flow_ctrl = FLOW_OFF;
106module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
107MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
108
109static int pause = PAUSE_TIME;
110module_param(pause, int, S_IRUGO | S_IWUSR);
111MODULE_PARM_DESC(pause, "Flow Control Pause Time");
112
113#define TC_DEFAULT 64
114static int tc = TC_DEFAULT;
115module_param(tc, int, S_IRUGO | S_IWUSR);
116MODULE_PARM_DESC(tc, "DMA threshold control value");
117
118#define RX_NO_COALESCE 1 /* Always interrupt on completion */
119#define TX_NO_COALESCE -1 /* No moderation by default */
120
121/* Pay attention to tune this parameter; take care of both
122 * hardware capability and network stabitily/performance impact.
123 * Many tests showed that ~4ms latency seems to be good enough. */
124#ifdef CONFIG_STMMAC_TIMER
125#define DEFAULT_PERIODIC_RATE 256
126static int tmrate = DEFAULT_PERIODIC_RATE;
127module_param(tmrate, int, S_IRUGO | S_IWUSR);
128MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
129#endif
130
131#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
132static int buf_sz = DMA_BUFFER_SIZE;
133module_param(buf_sz, int, S_IRUGO | S_IWUSR);
134MODULE_PARM_DESC(buf_sz, "DMA buffer size");
135
136/* In case of Giga ETH, we can enable/disable the COE for the
137 * transmit HW checksum computation.
138 * Note that, if tx csum is off in HW, SG will be still supported. */
139static int tx_coe = HW_CSUM;
140module_param(tx_coe, int, S_IRUGO | S_IWUSR);
141MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
142
143static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
144 NETIF_MSG_LINK | NETIF_MSG_IFUP |
145 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
146
147static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
148static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
149
150/**
151 * stmmac_verify_args - verify the driver parameters.
152 * Description: it verifies if some wrong parameter is passed to the driver.
153 * Note that wrong parameters are replaced with the default values.
154 */
155static void stmmac_verify_args(void)
156{
157 if (unlikely(watchdog < 0))
158 watchdog = TX_TIMEO;
159 if (unlikely(dma_rxsize < 0))
160 dma_rxsize = DMA_RX_SIZE;
161 if (unlikely(dma_txsize < 0))
162 dma_txsize = DMA_TX_SIZE;
163 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
164 buf_sz = DMA_BUFFER_SIZE;
165 if (unlikely(flow_ctrl > 1))
166 flow_ctrl = FLOW_AUTO;
167 else if (likely(flow_ctrl < 0))
168 flow_ctrl = FLOW_OFF;
169 if (unlikely((pause < 0) || (pause > 0xffff)))
170 pause = PAUSE_TIME;
171
172 return;
173}
174
175#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
176static void print_pkt(unsigned char *buf, int len)
177{
178 int j;
179 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
180 for (j = 0; j < len; j++) {
181 if ((j % 16) == 0)
182 pr_info("\n %03x:", j);
183 pr_info(" %02x", buf[j]);
184 }
185 pr_info("\n");
186 return;
187}
188#endif
189
190/* minimum number of free TX descriptors required to wake up TX process */
191#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
192
193static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
194{
195 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
196}
197
198/**
199 * stmmac_adjust_link
200 * @dev: net device structure
201 * Description: it adjusts the link parameters.
202 */
203static void stmmac_adjust_link(struct net_device *dev)
204{
205 struct stmmac_priv *priv = netdev_priv(dev);
206 struct phy_device *phydev = priv->phydev;
207 unsigned long ioaddr = dev->base_addr;
208 unsigned long flags;
209 int new_state = 0;
210 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
211
212 if (phydev == NULL)
213 return;
214
215 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
216 phydev->addr, phydev->link);
217
218 spin_lock_irqsave(&priv->lock, flags);
219 if (phydev->link) {
220 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
221
222 /* Now we make sure that we can be in full duplex mode.
223 * If not, we operate in half-duplex mode. */
224 if (phydev->duplex != priv->oldduplex) {
225 new_state = 1;
226 if (!(phydev->duplex))
db98a0b0 227 ctrl &= ~priv->hw->link.duplex;
47dd7a54 228 else
db98a0b0 229 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 230 priv->oldduplex = phydev->duplex;
231 }
232 /* Flow Control operation */
233 if (phydev->pause)
db98a0b0
GC		 234 priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex,
235 fc, pause_time);
47dd7a54
GC		 236
237 if (phydev->speed != priv->speed) {
238 new_state = 1;
239 switch (phydev->speed) {
240 case 1000:
241 if (likely(priv->is_gmac))
db98a0b0 242 ctrl &= ~priv->hw->link.port;
47dd7a54
GC		 243 break;
244 case 100:
245 case 10:
246 if (priv->is_gmac) {
db98a0b0 247 ctrl |= priv->hw->link.port;
47dd7a54 248 if (phydev->speed == SPEED_100) {
db98a0b0 249 ctrl |= priv->hw->link.speed;
47dd7a54 250 } else {
db98a0b0 251 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 252 }
253 } else {
db98a0b0 254 ctrl &= ~priv->hw->link.port;
47dd7a54 255 }
65818fa7
GC		 256 if (likely(priv->fix_mac_speed))
257 priv->fix_mac_speed(priv->bsp_priv,
258 phydev->speed);
47dd7a54
GC		 259 break;
260 default:
261 if (netif_msg_link(priv))
262 pr_warning("%s: Speed (%d) is not 10"
263 " or 100!\n", dev->name, phydev->speed);
264 break;
265 }
266
267 priv->speed = phydev->speed;
268 }
269
270 writel(ctrl, ioaddr + MAC_CTRL_REG);
271
272 if (!priv->oldlink) {
273 new_state = 1;
274 priv->oldlink = 1;
275 }
276 } else if (priv->oldlink) {
277 new_state = 1;
278 priv->oldlink = 0;
279 priv->speed = 0;
280 priv->oldduplex = -1;
281 }
282
283 if (new_state && netif_msg_link(priv))
284 phy_print_status(phydev);
285
286 spin_unlock_irqrestore(&priv->lock, flags);
287
288 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
289}
290
291/**
292 * stmmac_init_phy - PHY initialization
293 * @dev: net device structure
294 * Description: it initializes the driver's PHY state, and attaches the PHY
295 * to the mac driver.
296 * Return value:
297 * 0 on success
298 */
299static int stmmac_init_phy(struct net_device *dev)
300{
301 struct stmmac_priv *priv = netdev_priv(dev);
302 struct phy_device *phydev;
109cdd66
GC		 303 char phy_id[MII_BUS_ID_SIZE + 3];
304 char bus_id[MII_BUS_ID_SIZE];
47dd7a54
GC		 305
306 priv->oldlink = 0;
307 priv->speed = 0;
308 priv->oldduplex = -1;
309
310 if (priv->phy_addr == -1) {
311 /* We don't have a PHY, so do nothing */
312 return 0;
313 }
314
315 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
109cdd66
GC		 316 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
317 priv->phy_addr);
47dd7a54
GC		 318 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
319
320 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
321 priv->phy_interface);
322
323 if (IS_ERR(phydev)) {
324 pr_err("%s: Could not attach to PHY\n", dev->name);
325 return PTR_ERR(phydev);
326 }
327
328 /*
329 * Broken HW is sometimes missing the pull-up resistor on the
330 * MDIO line, which results in reads to non-existent devices returning
331 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
332 * device as well.
333 * Note: phydev->phy_id is the result of reading the UID PHY registers.
334 */
335 if (phydev->phy_id == 0) {
336 phy_disconnect(phydev);
337 return -ENODEV;
338 }
339 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
340 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
341
342 priv->phydev = phydev;
343
344 return 0;
345}
346
347static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
348{
349 u32 value = readl(ioaddr + MAC_CTRL_REG);
350 value |= MAC_RNABLE_RX;
351 /* Set the RE (receive enable bit into the MAC CTRL register). */
352 writel(value, ioaddr + MAC_CTRL_REG);
353}
354
355static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
356{
357 u32 value = readl(ioaddr + MAC_CTRL_REG);
358 value |= MAC_ENABLE_TX;
359 /* Set the TE (transmit enable bit into the MAC CTRL register). */
360 writel(value, ioaddr + MAC_CTRL_REG);
361}
362
363static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
364{
365 u32 value = readl(ioaddr + MAC_CTRL_REG);
366 value &= ~MAC_RNABLE_RX;
367 writel(value, ioaddr + MAC_CTRL_REG);
368}
369
370static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
371{
372 u32 value = readl(ioaddr + MAC_CTRL_REG);
373 value &= ~MAC_ENABLE_TX;
374 writel(value, ioaddr + MAC_CTRL_REG);
375}
376
377/**
378 * display_ring
379 * @p: pointer to the ring.
380 * @size: size of the ring.
381 * Description: display all the descriptors within the ring.
382 */
383static void display_ring(struct dma_desc *p, int size)
384{
385 struct tmp_s {
386 u64 a;
387 unsigned int b;
388 unsigned int c;
389 };
390 int i;
391 for (i = 0; i < size; i++) {
392 struct tmp_s *x = (struct tmp_s *)(p + i);
393 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
394 i, (unsigned int)virt_to_phys(&p[i]),
395 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
396 x->b, x->c);
397 pr_info("\n");
398 }
399}
400
401/**
402 * init_dma_desc_rings - init the RX/TX descriptor rings
403 * @dev: net device structure
404 * Description: this function initializes the DMA RX/TX descriptors
405 * and allocates the socket buffers.
406 */
407static void init_dma_desc_rings(struct net_device *dev)
408{
409 int i;
410 struct stmmac_priv *priv = netdev_priv(dev);
411 struct sk_buff *skb;
412 unsigned int txsize = priv->dma_tx_size;
413 unsigned int rxsize = priv->dma_rx_size;
414 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 415 int buff2_needed = 0, dis_ic = 0;
47dd7a54 416
47dd7a54
GC		 417 /* Set the Buffer size according to the MTU;
418 * indeed, in case of jumbo we need to bump-up the buffer sizes.
419 */
420 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
421 bfsize = BUF_SIZE_16KiB;
422 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
423 bfsize = BUF_SIZE_8KiB;
424 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
425 bfsize = BUF_SIZE_4KiB;
426 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
427 bfsize = BUF_SIZE_2KiB;
428 else
429 bfsize = DMA_BUFFER_SIZE;
430
73cfe264
GC		 431#ifdef CONFIG_STMMAC_TIMER
432 /* Disable interrupts on completion for the reception if timer is on */
433 if (likely(priv->tm->enable))
434 dis_ic = 1;
435#endif
47dd7a54
GC		 436 /* If the MTU exceeds 8k so use the second buffer in the chain */
437 if (bfsize >= BUF_SIZE_8KiB)
438 buff2_needed = 1;
439
440 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
441 txsize, rxsize, bfsize);
442
443 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
444 priv->rx_skbuff =
445 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
446 priv->dma_rx =
447 (struct dma_desc *)dma_alloc_coherent(priv->device,
448 rxsize *
449 sizeof(struct dma_desc),
450 &priv->dma_rx_phy,
451 GFP_KERNEL);
452 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
453 GFP_KERNEL);
454 priv->dma_tx =
455 (struct dma_desc *)dma_alloc_coherent(priv->device,
456 txsize *
457 sizeof(struct dma_desc),
458 &priv->dma_tx_phy,
459 GFP_KERNEL);
460
461 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
462 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
463 return;
464 }
465
466 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
467 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
468 dev->name, priv->dma_rx, priv->dma_tx,
469 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
470
471 /* RX INITIALIZATION */
472 DBG(probe, INFO, "stmmac: SKB addresses:\n"
473 "skb\t\tskb data\tdma data\n");
474
475 for (i = 0; i < rxsize; i++) {
476 struct dma_desc *p = priv->dma_rx + i;
477
478 skb = netdev_alloc_skb_ip_align(dev, bfsize);
479 if (unlikely(skb == NULL)) {
480 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
481 break;
482 }
483 priv->rx_skbuff[i] = skb;
484 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
485 bfsize, DMA_FROM_DEVICE);
486
487 p->des2 = priv->rx_skbuff_dma[i];
488 if (unlikely(buff2_needed))
489 p->des3 = p->des2 + BUF_SIZE_8KiB;
490 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
491 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
492 }
493 priv->cur_rx = 0;
494 priv->dirty_rx = (unsigned int)(i - rxsize);
495 priv->dma_buf_sz = bfsize;
496 buf_sz = bfsize;
497
498 /* TX INITIALIZATION */
499 for (i = 0; i < txsize; i++) {
500 priv->tx_skbuff[i] = NULL;
501 priv->dma_tx[i].des2 = 0;
502 }
503 priv->dirty_tx = 0;
504 priv->cur_tx = 0;
505
506 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 507 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
508 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 509
510 if (netif_msg_hw(priv)) {
511 pr_info("RX descriptor ring:\n");
512 display_ring(priv->dma_rx, rxsize);
513 pr_info("TX descriptor ring:\n");
514 display_ring(priv->dma_tx, txsize);
515 }
516 return;
517}
518
519static void dma_free_rx_skbufs(struct stmmac_priv *priv)
520{
521 int i;
522
523 for (i = 0; i < priv->dma_rx_size; i++) {
524 if (priv->rx_skbuff[i]) {
525 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
526 priv->dma_buf_sz, DMA_FROM_DEVICE);
527 dev_kfree_skb_any(priv->rx_skbuff[i]);
528 }
529 priv->rx_skbuff[i] = NULL;
530 }
531 return;
532}
533
534static void dma_free_tx_skbufs(struct stmmac_priv *priv)
535{
536 int i;
537
538 for (i = 0; i < priv->dma_tx_size; i++) {
539 if (priv->tx_skbuff[i] != NULL) {
540 struct dma_desc *p = priv->dma_tx + i;
541 if (p->des2)
542 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 543 priv->hw->desc->get_tx_len(p),
544 DMA_TO_DEVICE);
47dd7a54
GC		 545 dev_kfree_skb_any(priv->tx_skbuff[i]);
546 priv->tx_skbuff[i] = NULL;
547 }
548 }
549 return;
550}
551
552static void free_dma_desc_resources(struct stmmac_priv *priv)
553{
554 /* Release the DMA TX/RX socket buffers */
555 dma_free_rx_skbufs(priv);
556 dma_free_tx_skbufs(priv);
557
558 /* Free the region of consistent memory previously allocated for
559 * the DMA */
560 dma_free_coherent(priv->device,
561 priv->dma_tx_size * sizeof(struct dma_desc),
562 priv->dma_tx, priv->dma_tx_phy);
563 dma_free_coherent(priv->device,
564 priv->dma_rx_size * sizeof(struct dma_desc),
565 priv->dma_rx, priv->dma_rx_phy);
566 kfree(priv->rx_skbuff_dma);
567 kfree(priv->rx_skbuff);
568 kfree(priv->tx_skbuff);
569
570 return;
571}
572
47dd7a54
GC		 573/**
574 * stmmac_dma_operation_mode - HW DMA operation mode
575 * @priv : pointer to the private device structure.
576 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
577 * or Store-And-Forward capability. It also verifies the COE for the
578 * transmission in case of Giga ETH.
579 */
580static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
581{
582 if (!priv->is_gmac) {
583 /* MAC 10/100 */
db98a0b0 584 priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0);
47dd7a54
GC		 585 priv->tx_coe = NO_HW_CSUM;
586 } else {
587 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
db98a0b0
GC		 588 priv->hw->dma->dma_mode(priv->dev->base_addr,
589 SF_DMA_MODE, SF_DMA_MODE);
47dd7a54
GC		 590 tc = SF_DMA_MODE;
591 priv->tx_coe = HW_CSUM;
592 } else {
593 /* Checksum computation is performed in software. */
db98a0b0
GC		 594 priv->hw->dma->dma_mode(priv->dev->base_addr, tc,
595 SF_DMA_MODE);
47dd7a54
GC		 596 priv->tx_coe = NO_HW_CSUM;
597 }
598 }
599 tx_coe = priv->tx_coe;
600
601 return;
602}
603
47dd7a54
GC		 604/**
605 * stmmac_tx:
606 * @priv: private driver structure
607 * Description: it reclaims resources after transmission completes.
608 */
609static void stmmac_tx(struct stmmac_priv *priv)
610{
611 unsigned int txsize = priv->dma_tx_size;
612 unsigned long ioaddr = priv->dev->base_addr;
613
614 while (priv->dirty_tx != priv->cur_tx) {
615 int last;
616 unsigned int entry = priv->dirty_tx % txsize;
617 struct sk_buff *skb = priv->tx_skbuff[entry];
618 struct dma_desc *p = priv->dma_tx + entry;
619
620 /* Check if the descriptor is owned by the DMA. */
db98a0b0 621 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 622 break;
623
624 /* Verify tx error by looking at the last segment */
db98a0b0 625 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 626 if (likely(last)) {
627 int tx_error =
db98a0b0
GC		 628 priv->hw->desc->tx_status(&priv->dev->stats,
629 &priv->xstats, p,
630 ioaddr);
47dd7a54
GC		 631 if (likely(tx_error == 0)) {
632 priv->dev->stats.tx_packets++;
633 priv->xstats.tx_pkt_n++;
634 } else
635 priv->dev->stats.tx_errors++;
636 }
637 TX_DBG("%s: curr %d, dirty %d\n", __func__,
638 priv->cur_tx, priv->dirty_tx);
639
640 if (likely(p->des2))
641 dma_unmap_single(priv->device, p->des2,
db98a0b0 642 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 643 DMA_TO_DEVICE);
644 if (unlikely(p->des3))
645 p->des3 = 0;
646
647 if (likely(skb != NULL)) {
648 /*
649 * If there's room in the queue (limit it to size)
650 * we add this skb back into the pool,
651 * if it's the right size.
652 */
653 if ((skb_queue_len(&priv->rx_recycle) <
654 priv->dma_rx_size) &&
655 skb_recycle_check(skb, priv->dma_buf_sz))
656 __skb_queue_head(&priv->rx_recycle, skb);
657 else
658 dev_kfree_skb(skb);
659
660 priv->tx_skbuff[entry] = NULL;
661 }
662
db98a0b0 663 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 664
665 entry = (++priv->dirty_tx) % txsize;
666 }
667 if (unlikely(netif_queue_stopped(priv->dev) &&
668 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
669 netif_tx_lock(priv->dev);
670 if (netif_queue_stopped(priv->dev) &&
671 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
672 TX_DBG("%s: restart transmit\n", __func__);
673 netif_wake_queue(priv->dev);
674 }
675 netif_tx_unlock(priv->dev);
676 }
677 return;
678}
679
680static inline void stmmac_enable_irq(struct stmmac_priv *priv)
681{
73cfe264
GC		 682#ifdef CONFIG_STMMAC_TIMER
683 if (likely(priv->tm->enable))
684 priv->tm->timer_start(tmrate);
685 else
47dd7a54 686#endif
aec7ff27 687 priv->hw->dma->enable_dma_irq(priv->dev->base_addr);
47dd7a54
GC		 688}
689
690static inline void stmmac_disable_irq(struct stmmac_priv *priv)
691{
73cfe264
GC		 692#ifdef CONFIG_STMMAC_TIMER
693 if (likely(priv->tm->enable))
694 priv->tm->timer_stop();
695 else
47dd7a54 696#endif
aec7ff27 697 priv->hw->dma->disable_dma_irq(priv->dev->base_addr);
47dd7a54
GC		 698}
699
700static int stmmac_has_work(struct stmmac_priv *priv)
701{
702 unsigned int has_work = 0;
703 int rxret, tx_work = 0;
704
db98a0b0 705 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 706 (priv->cur_rx % priv->dma_rx_size));
707
708 if (priv->dirty_tx != priv->cur_tx)
709 tx_work = 1;
710
711 if (likely(!rxret || tx_work))
712 has_work = 1;
713
714 return has_work;
715}
716
717static inline void _stmmac_schedule(struct stmmac_priv *priv)
718{
719 if (likely(stmmac_has_work(priv))) {
720 stmmac_disable_irq(priv);
721 napi_schedule(&priv->napi);
722 }
723}
724
725#ifdef CONFIG_STMMAC_TIMER
726void stmmac_schedule(struct net_device *dev)
727{
728 struct stmmac_priv *priv = netdev_priv(dev);
729
730 priv->xstats.sched_timer_n++;
731
732 _stmmac_schedule(priv);
733
734 return;
735}
736
737static void stmmac_no_timer_started(unsigned int x)
738{;
739};
740
741static void stmmac_no_timer_stopped(void)
742{;
743};
744#endif
745
746/**
747 * stmmac_tx_err:
748 * @priv: pointer to the private device structure
749 * Description: it cleans the descriptors and restarts the transmission
750 * in case of errors.
751 */
752static void stmmac_tx_err(struct stmmac_priv *priv)
753{
754 netif_stop_queue(priv->dev);
755
aec7ff27 756 priv->hw->dma->stop_tx(priv->dev->base_addr);
47dd7a54 757 dma_free_tx_skbufs(priv);
db98a0b0 758 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 759 priv->dirty_tx = 0;
760 priv->cur_tx = 0;
aec7ff27 761 priv->hw->dma->start_tx(priv->dev->base_addr);
47dd7a54
GC		 762
763 priv->dev->stats.tx_errors++;
764 netif_wake_queue(priv->dev);
765
766 return;
767}
768
47dd7a54 769
aec7ff27
GC		 770static void stmmac_dma_interrupt(struct stmmac_priv *priv)
771{
772 unsigned long ioaddr = priv->dev->base_addr;
773 int status;
774
775 status = priv->hw->dma->dma_interrupt(priv->dev->base_addr,
776 &priv->xstats);
777 if (likely(status == handle_tx_rx))
778 _stmmac_schedule(priv);
779
780 else if (unlikely(status == tx_hard_error_bump_tc)) {
781 /* Try to bump up the dma threshold on this failure */
782 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
783 tc += 64;
784 priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE);
785 priv->xstats.threshold = tc;
47dd7a54 786 }
aec7ff27
GC		 787 stmmac_tx_err(priv);
788 } else if (unlikely(status == tx_hard_error))
789 stmmac_tx_err(priv);
47dd7a54
GC		 790
791 return;
792}
793
794/**
795 * stmmac_open - open entry point of the driver
796 * @dev : pointer to the device structure.
797 * Description:
798 * This function is the open entry point of the driver.
799 * Return value:
800 * 0 on success and an appropriate (-)ve integer as defined in errno.h
801 * file on failure.
802 */
803static int stmmac_open(struct net_device *dev)
804{
805 struct stmmac_priv *priv = netdev_priv(dev);
806 unsigned long ioaddr = dev->base_addr;
807 int ret;
808
809 /* Check that the MAC address is valid. If its not, refuse
810 * to bring the device up. The user must specify an
811 * address using the following linux command:
812 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
813 if (!is_valid_ether_addr(dev->dev_addr)) {
814 random_ether_addr(dev->dev_addr);
815 pr_warning("%s: generated random MAC address %pM\n", dev->name,
816 dev->dev_addr);
817 }
818
819 stmmac_verify_args();
820
821 ret = stmmac_init_phy(dev);
822 if (unlikely(ret)) {
823 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
824 return ret;
825 }
826
827 /* Request the IRQ lines */
a0607fd3 828 ret = request_irq(dev->irq, stmmac_interrupt,
47dd7a54
GC		 829 IRQF_SHARED, dev->name, dev);
830 if (unlikely(ret < 0)) {
831 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
832 __func__, dev->irq, ret);
833 return ret;
834 }
835
836#ifdef CONFIG_STMMAC_TIMER
73cfe264 837 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54
GC		 838 if (unlikely(priv->tm == NULL)) {
839 pr_err("%s: ERROR: timer memory alloc failed \n", __func__);
840 return -ENOMEM;
841 }
842 priv->tm->freq = tmrate;
843
73cfe264
GC		 844 /* Test if the external timer can be actually used.
845 * In case of failure continue without timer. */
47dd7a54 846 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 847 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 848 tmrate = 0;
849 priv->tm->freq = 0;
850 priv->tm->timer_start = stmmac_no_timer_started;
851 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 852 } else
853 priv->tm->enable = 1;
47dd7a54
GC		 854#endif
855
856 /* Create and initialize the TX/RX descriptors chains. */
857 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
858 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
859 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
860 init_dma_desc_rings(dev);
861
862 /* DMA initialization and SW reset */
db98a0b0
GC		 863 if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy,
864 priv->dma_rx_phy) < 0)) {
47dd7a54
GC		 865
866 pr_err("%s: DMA initialization failed\n", __func__);
867 return -1;
868 }
869
870 /* Copy the MAC addr into the HW */
db98a0b0 871 priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0);
ca5f12c1
GC		 872 /* If required, perform hw setup of the bus. */
873 if (priv->bus_setup)
874 priv->bus_setup(ioaddr);
47dd7a54 875 /* Initialize the MAC Core */
db98a0b0 876 priv->hw->mac->core_init(ioaddr);
47dd7a54
GC		 877
878 priv->shutdown = 0;
879
880 /* Initialise the MMC (if present) to disable all interrupts. */
881 writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
882 writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
883
884 /* Enable the MAC Rx/Tx */
885 stmmac_mac_enable_rx(ioaddr);
886 stmmac_mac_enable_tx(ioaddr);
887
888 /* Set the HW DMA mode and the COE */
889 stmmac_dma_operation_mode(priv);
890
891 /* Extra statistics */
892 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
893 priv->xstats.threshold = tc;
894
895 /* Start the ball rolling... */
896 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
aec7ff27
GC		 897 priv->hw->dma->start_tx(ioaddr);
898 priv->hw->dma->start_rx(ioaddr);
47dd7a54
GC		 899
900#ifdef CONFIG_STMMAC_TIMER
901 priv->tm->timer_start(tmrate);
902#endif
903 /* Dump DMA/MAC registers */
904 if (netif_msg_hw(priv)) {
db98a0b0
GC		 905 priv->hw->mac->dump_regs(ioaddr);
906 priv->hw->dma->dump_regs(ioaddr);
47dd7a54
GC		 907 }
908
909 if (priv->phydev)
910 phy_start(priv->phydev);
911
912 napi_enable(&priv->napi);
913 skb_queue_head_init(&priv->rx_recycle);
914 netif_start_queue(dev);
915 return 0;
916}
917
918/**
919 * stmmac_release - close entry point of the driver
920 * @dev : device pointer.
921 * Description:
922 * This is the stop entry point of the driver.
923 */
924static int stmmac_release(struct net_device *dev)
925{
926 struct stmmac_priv *priv = netdev_priv(dev);
927
928 /* Stop and disconnect the PHY */
929 if (priv->phydev) {
930 phy_stop(priv->phydev);
931 phy_disconnect(priv->phydev);
932 priv->phydev = NULL;
933 }
934
935 netif_stop_queue(dev);
936
937#ifdef CONFIG_STMMAC_TIMER
938 /* Stop and release the timer */
939 stmmac_close_ext_timer();
940 if (priv->tm != NULL)
941 kfree(priv->tm);
942#endif
943 napi_disable(&priv->napi);
944 skb_queue_purge(&priv->rx_recycle);
945
946 /* Free the IRQ lines */
947 free_irq(dev->irq, dev);
948
949 /* Stop TX/RX DMA and clear the descriptors */
aec7ff27
GC		 950 priv->hw->dma->stop_tx(dev->base_addr);
951 priv->hw->dma->stop_rx(dev->base_addr);
47dd7a54
GC		 952
953 /* Release and free the Rx/Tx resources */
954 free_dma_desc_resources(priv);
955
956 /* Disable the MAC core */
957 stmmac_mac_disable_tx(dev->base_addr);
958 stmmac_mac_disable_rx(dev->base_addr);
959
960 netif_carrier_off(dev);
961
962 return 0;
963}
964
965/*
966 * To perform emulated hardware segmentation on skb.
967 */
968static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
969{
970 struct sk_buff *segs, *curr_skb;
971 int gso_segs = skb_shinfo(skb)->gso_segs;
972
973 /* Estimate the number of fragments in the worst case */
974 if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
975 netif_stop_queue(priv->dev);
976 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
977 __func__);
978 if (stmmac_tx_avail(priv) < gso_segs)
979 return NETDEV_TX_BUSY;
980
981 netif_wake_queue(priv->dev);
982 }
983 TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
984 skb, skb->len);
985
986 segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
987 if (unlikely(IS_ERR(segs)))
988 goto sw_tso_end;
989
990 do {
991 curr_skb = segs;
992 segs = segs->next;
993 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
994 "*next %p\n", curr_skb->len, curr_skb, segs);
995 curr_skb->next = NULL;
996 stmmac_xmit(curr_skb, priv->dev);
997 } while (segs);
998
999sw_tso_end:
1000 dev_kfree_skb(skb);
1001
1002 return NETDEV_TX_OK;
1003}
1004
1005static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1006 struct net_device *dev,
1007 int csum_insertion)
1008{
1009 struct stmmac_priv *priv = netdev_priv(dev);
1010 unsigned int nopaged_len = skb_headlen(skb);
1011 unsigned int txsize = priv->dma_tx_size;
1012 unsigned int entry = priv->cur_tx % txsize;
1013 struct dma_desc *desc = priv->dma_tx + entry;
1014
1015 if (nopaged_len > BUF_SIZE_8KiB) {
1016
1017 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1018
1019 desc->des2 = dma_map_single(priv->device, skb->data,
1020 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1021 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1022 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1023 csum_insertion);
47dd7a54
GC		 1024
1025 entry = (++priv->cur_tx) % txsize;
1026 desc = priv->dma_tx + entry;
1027
1028 desc->des2 = dma_map_single(priv->device,
1029 skb->data + BUF_SIZE_8KiB,
1030 buf2_size, DMA_TO_DEVICE);
1031 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1032 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1033 csum_insertion);
1034 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1035 priv->tx_skbuff[entry] = NULL;
1036 } else {
1037 desc->des2 = dma_map_single(priv->device, skb->data,
1038 nopaged_len, DMA_TO_DEVICE);
1039 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1040 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1041 csum_insertion);
47dd7a54
GC		 1042 }
1043 return entry;
1044}
1045
1046/**
1047 * stmmac_xmit:
1048 * @skb : the socket buffer
1049 * @dev : device pointer
1050 * Description : Tx entry point of the driver.
1051 */
1052static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1053{
1054 struct stmmac_priv *priv = netdev_priv(dev);
1055 unsigned int txsize = priv->dma_tx_size;
1056 unsigned int entry;
1057 int i, csum_insertion = 0;
1058 int nfrags = skb_shinfo(skb)->nr_frags;
1059 struct dma_desc *desc, *first;
1060
1061 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1062 if (!netif_queue_stopped(dev)) {
1063 netif_stop_queue(dev);
1064 /* This is a hard error, log it. */
1065 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1066 __func__);
1067 }
1068 return NETDEV_TX_BUSY;
1069 }
1070
1071 entry = priv->cur_tx % txsize;
1072
1073#ifdef STMMAC_XMIT_DEBUG
1074 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1075 pr_info("stmmac xmit:\n"
1076 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1077 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1078 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1079 !skb_is_gso(skb) ? "isn't" : "is");
1080#endif
1081
1082 if (unlikely(skb_is_gso(skb)))
1083 return stmmac_sw_tso(priv, skb);
1084
1085 if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1086 if (likely(priv->tx_coe == NO_HW_CSUM))
1087 skb_checksum_help(skb);
1088 else
1089 csum_insertion = 1;
1090 }
1091
1092 desc = priv->dma_tx + entry;
1093 first = desc;
1094
1095#ifdef STMMAC_XMIT_DEBUG
1096 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1097 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1098 "\t\tn_frags: %d, ip_summed: %d\n",
1099 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1100#endif
1101 priv->tx_skbuff[entry] = skb;
1102 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1103 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1104 desc = priv->dma_tx + entry;
1105 } else {
1106 unsigned int nopaged_len = skb_headlen(skb);
1107 desc->des2 = dma_map_single(priv->device, skb->data,
1108 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1109 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1110 csum_insertion);
47dd7a54
GC		 1111 }
1112
1113 for (i = 0; i < nfrags; i++) {
1114 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1115 int len = frag->size;
1116
1117 entry = (++priv->cur_tx) % txsize;
1118 desc = priv->dma_tx + entry;
1119
1120 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1121 desc->des2 = dma_map_page(priv->device, frag->page,
1122 frag->page_offset,
1123 len, DMA_TO_DEVICE);
1124 priv->tx_skbuff[entry] = NULL;
db98a0b0
GC		 1125 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1126 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1127 }
1128
1129 /* Interrupt on completition only for the latest segment */
db98a0b0 1130 priv->hw->desc->close_tx_desc(desc);
73cfe264 1131
47dd7a54 1132#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1133 /* Clean IC while using timer */
1134 if (likely(priv->tm->enable))
db98a0b0 1135 priv->hw->desc->clear_tx_ic(desc);
47dd7a54
GC		 1136#endif
1137 /* To avoid raise condition */
db98a0b0 1138 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1139
1140 priv->cur_tx++;
1141
1142#ifdef STMMAC_XMIT_DEBUG
1143 if (netif_msg_pktdata(priv)) {
1144 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1145 "first=%p, nfrags=%d\n",
1146 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1147 entry, first, nfrags);
1148 display_ring(priv->dma_tx, txsize);
1149 pr_info(">>> frame to be transmitted: ");
1150 print_pkt(skb->data, skb->len);
1151 }
1152#endif
1153 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1154 TX_DBG("%s: stop transmitted packets\n", __func__);
1155 netif_stop_queue(dev);
1156 }
1157
1158 dev->stats.tx_bytes += skb->len;
1159
aec7ff27 1160 priv->hw->dma->enable_dma_transmission(dev->base_addr);
47dd7a54
GC		 1161
1162 return NETDEV_TX_OK;
1163}
1164
1165static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1166{
1167 unsigned int rxsize = priv->dma_rx_size;
1168 int bfsize = priv->dma_buf_sz;
1169 struct dma_desc *p = priv->dma_rx;
1170
1171 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1172 unsigned int entry = priv->dirty_rx % rxsize;
1173 if (likely(priv->rx_skbuff[entry] == NULL)) {
1174 struct sk_buff *skb;
1175
1176 skb = __skb_dequeue(&priv->rx_recycle);
1177 if (skb == NULL)
1178 skb = netdev_alloc_skb_ip_align(priv->dev,
1179 bfsize);
1180
1181 if (unlikely(skb == NULL))
1182 break;
1183
1184 priv->rx_skbuff[entry] = skb;
1185 priv->rx_skbuff_dma[entry] =
1186 dma_map_single(priv->device, skb->data, bfsize,
1187 DMA_FROM_DEVICE);
1188
1189 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1190 if (unlikely(priv->is_gmac)) {
1191 if (bfsize >= BUF_SIZE_8KiB)
1192 (p + entry)->des3 =
1193 (p + entry)->des2 + BUF_SIZE_8KiB;
1194 }
1195 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1196 }
db98a0b0 1197 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54
GC		 1198 }
1199 return;
1200}
1201
1202static int stmmac_rx(struct stmmac_priv *priv, int limit)
1203{
1204 unsigned int rxsize = priv->dma_rx_size;
1205 unsigned int entry = priv->cur_rx % rxsize;
1206 unsigned int next_entry;
1207 unsigned int count = 0;
1208 struct dma_desc *p = priv->dma_rx + entry;
1209 struct dma_desc *p_next;
1210
1211#ifdef STMMAC_RX_DEBUG
1212 if (netif_msg_hw(priv)) {
1213 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1214 display_ring(priv->dma_rx, rxsize);
1215 }
1216#endif
1217 count = 0;
db98a0b0 1218 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1219 int status;
1220
1221 if (count >= limit)
1222 break;
1223
1224 count++;
1225
1226 next_entry = (++priv->cur_rx) % rxsize;
1227 p_next = priv->dma_rx + next_entry;
1228 prefetch(p_next);
1229
1230 /* read the status of the incoming frame */
db98a0b0
GC		 1231 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1232 &priv->xstats, p));
47dd7a54
GC		 1233 if (unlikely(status == discard_frame))
1234 priv->dev->stats.rx_errors++;
1235 else {
1236 struct sk_buff *skb;
1237 /* Length should omit the CRC */
db98a0b0 1238 int frame_len = priv->hw->desc->get_rx_frame_len(p) - 4;
47dd7a54
GC		 1239
1240#ifdef STMMAC_RX_DEBUG
1241 if (frame_len > ETH_FRAME_LEN)
1242 pr_debug("\tRX frame size %d, COE status: %d\n",
1243 frame_len, status);
1244
1245 if (netif_msg_hw(priv))
1246 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1247 p, entry, p->des2);
1248#endif
1249 skb = priv->rx_skbuff[entry];
1250 if (unlikely(!skb)) {
1251 pr_err("%s: Inconsistent Rx descriptor chain\n",
1252 priv->dev->name);
1253 priv->dev->stats.rx_dropped++;
1254 break;
1255 }
1256 prefetch(skb->data - NET_IP_ALIGN);
1257 priv->rx_skbuff[entry] = NULL;
1258
1259 skb_put(skb, frame_len);
1260 dma_unmap_single(priv->device,
1261 priv->rx_skbuff_dma[entry],
1262 priv->dma_buf_sz, DMA_FROM_DEVICE);
1263#ifdef STMMAC_RX_DEBUG
1264 if (netif_msg_pktdata(priv)) {
1265 pr_info(" frame received (%dbytes)", frame_len);
1266 print_pkt(skb->data, frame_len);
1267 }
1268#endif
1269 skb->protocol = eth_type_trans(skb, priv->dev);
1270
1271 if (unlikely(status == csum_none)) {
1272 /* always for the old mac 10/100 */
1273 skb->ip_summed = CHECKSUM_NONE;
1274 netif_receive_skb(skb);
1275 } else {
1276 skb->ip_summed = CHECKSUM_UNNECESSARY;
1277 napi_gro_receive(&priv->napi, skb);
1278 }
1279
1280 priv->dev->stats.rx_packets++;
1281 priv->dev->stats.rx_bytes += frame_len;
1282 priv->dev->last_rx = jiffies;
1283 }
1284 entry = next_entry;
1285 p = p_next; /* use prefetched values */
1286 }
1287
1288 stmmac_rx_refill(priv);
1289
1290 priv->xstats.rx_pkt_n += count;
1291
1292 return count;
1293}
1294
1295/**
1296 * stmmac_poll - stmmac poll method (NAPI)
1297 * @napi : pointer to the napi structure.
1298 * @budget : maximum number of packets that the current CPU can receive from
1299 * all interfaces.
1300 * Description :
1301 * This function implements the the reception process.
1302 * Also it runs the TX completion thread
1303 */
1304static int stmmac_poll(struct napi_struct *napi, int budget)
1305{
1306 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1307 int work_done = 0;
1308
1309 priv->xstats.poll_n++;
1310 stmmac_tx(priv);
1311 work_done = stmmac_rx(priv, budget);
1312
1313 if (work_done < budget) {
1314 napi_complete(napi);
1315 stmmac_enable_irq(priv);
1316 }
1317 return work_done;
1318}
1319
1320/**
1321 * stmmac_tx_timeout
1322 * @dev : Pointer to net device structure
1323 * Description: this function is called when a packet transmission fails to
1324 * complete within a reasonable tmrate. The driver will mark the error in the
1325 * netdev structure and arrange for the device to be reset to a sane state
1326 * in order to transmit a new packet.
1327 */
1328static void stmmac_tx_timeout(struct net_device *dev)
1329{
1330 struct stmmac_priv *priv = netdev_priv(dev);
1331
1332 /* Clear Tx resources and restart transmitting again */
1333 stmmac_tx_err(priv);
1334 return;
1335}
1336
1337/* Configuration changes (passed on by ifconfig) */
1338static int stmmac_config(struct net_device *dev, struct ifmap *map)
1339{
1340 if (dev->flags & IFF_UP) /* can't act on a running interface */
1341 return -EBUSY;
1342
1343 /* Don't allow changing the I/O address */
1344 if (map->base_addr != dev->base_addr) {
1345 pr_warning("%s: can't change I/O address\n", dev->name);
1346 return -EOPNOTSUPP;
1347 }
1348
1349 /* Don't allow changing the IRQ */
1350 if (map->irq != dev->irq) {
1351 pr_warning("%s: can't change IRQ number %d\n",
1352 dev->name, dev->irq);
1353 return -EOPNOTSUPP;
1354 }
1355
1356 /* ignore other fields */
1357 return 0;
1358}
1359
1360/**
1361 * stmmac_multicast_list - entry point for multicast addressing
1362 * @dev : pointer to the device structure
1363 * Description:
1364 * This function is a driver entry point which gets called by the kernel
1365 * whenever multicast addresses must be enabled/disabled.
1366 * Return value:
1367 * void.
1368 */
1369static void stmmac_multicast_list(struct net_device *dev)
1370{
1371 struct stmmac_priv *priv = netdev_priv(dev);
1372
1373 spin_lock(&priv->lock);
db98a0b0 1374 priv->hw->mac->set_filter(dev);
47dd7a54
GC		 1375 spin_unlock(&priv->lock);
1376 return;
1377}
1378
1379/**
1380 * stmmac_change_mtu - entry point to change MTU size for the device.
1381 * @dev : device pointer.
1382 * @new_mtu : the new MTU size for the device.
1383 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1384 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1385 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1386 * Return value:
1387 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1388 * file on failure.
1389 */
1390static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1391{
1392 struct stmmac_priv *priv = netdev_priv(dev);
1393 int max_mtu;
1394
1395 if (netif_running(dev)) {
1396 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1397 return -EBUSY;
1398 }
1399
1400 if (priv->is_gmac)
1401 max_mtu = JUMBO_LEN;
1402 else
1403 max_mtu = ETH_DATA_LEN;
1404
1405 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1406 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1407 return -EINVAL;
1408 }
1409
1410 dev->mtu = new_mtu;
1411
1412 return 0;
1413}
1414
1415static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1416{
1417 struct net_device *dev = (struct net_device *)dev_id;
1418 struct stmmac_priv *priv = netdev_priv(dev);
1419
1420 if (unlikely(!dev)) {
1421 pr_err("%s: invalid dev pointer\n", __func__);
1422 return IRQ_NONE;
1423 }
1424
1425 if (priv->is_gmac) {
1426 unsigned long ioaddr = dev->base_addr;
1427 /* To handle GMAC own interrupts */
db98a0b0 1428 priv->hw->mac->host_irq_status(ioaddr);
47dd7a54 1429 }
aec7ff27
GC		 1430
1431 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1432
1433 return IRQ_HANDLED;
1434}
1435
1436#ifdef CONFIG_NET_POLL_CONTROLLER
1437/* Polling receive - used by NETCONSOLE and other diagnostic tools
1438 * to allow network I/O with interrupts disabled. */
1439static void stmmac_poll_controller(struct net_device *dev)
1440{
1441 disable_irq(dev->irq);
1442 stmmac_interrupt(dev->irq, dev);
1443 enable_irq(dev->irq);
1444}
1445#endif
1446
1447/**
1448 * stmmac_ioctl - Entry point for the Ioctl
1449 * @dev: Device pointer.
1450 * @rq: An IOCTL specefic structure, that can contain a pointer to
1451 * a proprietary structure used to pass information to the driver.
1452 * @cmd: IOCTL command
1453 * Description:
1454 * Currently there are no special functionality supported in IOCTL, just the
1455 * phy_mii_ioctl(...) can be invoked.
1456 */
1457static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1458{
1459 struct stmmac_priv *priv = netdev_priv(dev);
1460 int ret = -EOPNOTSUPP;
1461
1462 if (!netif_running(dev))
1463 return -EINVAL;
1464
1465 switch (cmd) {
1466 case SIOCGMIIPHY:
1467 case SIOCGMIIREG:
1468 case SIOCSMIIREG:
1469 if (!priv->phydev)
1470 return -EINVAL;
1471
1472 spin_lock(&priv->lock);
1473 ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1474 spin_unlock(&priv->lock);
1475 default:
1476 break;
1477 }
1478 return ret;
1479}
1480
1481#ifdef STMMAC_VLAN_TAG_USED
1482static void stmmac_vlan_rx_register(struct net_device *dev,
1483 struct vlan_group *grp)
1484{
1485 struct stmmac_priv *priv = netdev_priv(dev);
1486
1487 DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1488
1489 spin_lock(&priv->lock);
1490 priv->vlgrp = grp;
1491 spin_unlock(&priv->lock);
1492
1493 return;
1494}
1495#endif
1496
1497static const struct net_device_ops stmmac_netdev_ops = {
1498 .ndo_open = stmmac_open,
1499 .ndo_start_xmit = stmmac_xmit,
1500 .ndo_stop = stmmac_release,
1501 .ndo_change_mtu = stmmac_change_mtu,
1502 .ndo_set_multicast_list = stmmac_multicast_list,
1503 .ndo_tx_timeout = stmmac_tx_timeout,
1504 .ndo_do_ioctl = stmmac_ioctl,
1505 .ndo_set_config = stmmac_config,
1506#ifdef STMMAC_VLAN_TAG_USED
1507 .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1508#endif
1509#ifdef CONFIG_NET_POLL_CONTROLLER
1510 .ndo_poll_controller = stmmac_poll_controller,
1511#endif
1512 .ndo_set_mac_address = eth_mac_addr,
1513};
1514
1515/**
1516 * stmmac_probe - Initialization of the adapter .
1517 * @dev : device pointer
1518 * Description: The function initializes the network device structure for
1519 * the STMMAC driver. It also calls the low level routines
1520 * in order to init the HW (i.e. the DMA engine)
1521 */
1522static int stmmac_probe(struct net_device *dev)
1523{
1524 int ret = 0;
1525 struct stmmac_priv *priv = netdev_priv(dev);
1526
1527 ether_setup(dev);
1528
1529 dev->netdev_ops = &stmmac_netdev_ops;
1530 stmmac_set_ethtool_ops(dev);
1531
1532 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1533 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1534#ifdef STMMAC_VLAN_TAG_USED
1535 /* Both mac100 and gmac support receive VLAN tag detection */
1536 dev->features |= NETIF_F_HW_VLAN_RX;
1537#endif
1538 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1539
1540 if (priv->is_gmac)
1541 priv->rx_csum = 1;
1542
1543 if (flow_ctrl)
1544 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1545
1546 priv->pause = pause;
1547 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1548
1549 /* Get the MAC address */
db98a0b0 1550 priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
47dd7a54
GC		 1551
1552 if (!is_valid_ether_addr(dev->dev_addr))
1553 pr_warning("\tno valid MAC address;"
1554 "please, use ifconfig or nwhwconfig!\n");
1555
1556 ret = register_netdev(dev);
1557 if (ret) {
1558 pr_err("%s: ERROR %i registering the device\n",
1559 __func__, ret);
1560 return -ENODEV;
1561 }
1562
1563 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1564 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1565 (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1566
1567 spin_lock_init(&priv->lock);
1568
1569 return ret;
1570}
1571
1572/**
1573 * stmmac_mac_device_setup
1574 * @dev : device pointer
1575 * Description: select and initialise the mac device (mac100 or Gmac).
1576 */
1577static int stmmac_mac_device_setup(struct net_device *dev)
1578{
1579 struct stmmac_priv *priv = netdev_priv(dev);
1580 unsigned long ioaddr = dev->base_addr;
1581
1582 struct mac_device_info *device;
1583
1584 if (priv->is_gmac)
21d437cc 1585 device = dwmac1000_setup(ioaddr);
47dd7a54 1586 else
7e848ae1 1587 device = dwmac100_setup(ioaddr);
47dd7a54
GC		 1588
1589 if (!device)
1590 return -ENOMEM;
1591
db98a0b0 1592 priv->hw = device;
47dd7a54 1593
db98a0b0 1594 priv->wolenabled = priv->hw->pmt; /* PMT supported */
47dd7a54
GC		 1595 if (priv->wolenabled == PMT_SUPPORTED)
1596 priv->wolopts = WAKE_MAGIC; /* Magic Frame */
1597
1598 return 0;
1599}
1600
1601static int stmmacphy_dvr_probe(struct platform_device *pdev)
1602{
ee7946a7 1603 struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1604
1605 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1606 plat_dat->bus_id);
1607
1608 return 0;
1609}
1610
1611static int stmmacphy_dvr_remove(struct platform_device *pdev)
1612{
1613 return 0;
1614}
1615
1616static struct platform_driver stmmacphy_driver = {
1617 .driver = {
1618 .name = PHY_RESOURCE_NAME,
1619 },
1620 .probe = stmmacphy_dvr_probe,
1621 .remove = stmmacphy_dvr_remove,
1622};
1623
1624/**
1625 * stmmac_associate_phy
1626 * @dev: pointer to device structure
1627 * @data: points to the private structure.
1628 * Description: Scans through all the PHYs we have registered and checks if
1629 * any are associated with our MAC. If so, then just fill in
1630 * the blanks in our local context structure
1631 */
1632static int stmmac_associate_phy(struct device *dev, void *data)
1633{
1634 struct stmmac_priv *priv = (struct stmmac_priv *)data;
ee7946a7 1635 struct plat_stmmacphy_data *plat_dat = dev->platform_data;
47dd7a54
GC		 1636
1637 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1638 plat_dat->bus_id);
1639
1640 /* Check that this phy is for the MAC being initialised */
1641 if (priv->bus_id != plat_dat->bus_id)
1642 return 0;
1643
1644 /* OK, this PHY is connected to the MAC.
1645 Go ahead and get the parameters */
1646 DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1647 priv->phy_irq =
1648 platform_get_irq_byname(to_platform_device(dev), "phyirq");
1649 DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1650 plat_dat->bus_id, priv->phy_irq);
1651
1652 /* Override with kernel parameters if supplied XXX CRS XXX
1653 * this needs to have multiple instances */
1654 if ((phyaddr >= 0) && (phyaddr <= 31))
1655 plat_dat->phy_addr = phyaddr;
1656
1657 priv->phy_addr = plat_dat->phy_addr;
1658 priv->phy_mask = plat_dat->phy_mask;
1659 priv->phy_interface = plat_dat->interface;
1660 priv->phy_reset = plat_dat->phy_reset;
1661
1662 DBG(probe, DEBUG, "%s: exiting\n", __func__);
1663 return 1; /* forces exit of driver_for_each_device() */
1664}
1665
1666/**
1667 * stmmac_dvr_probe
1668 * @pdev: platform device pointer
1669 * Description: the driver is initialized through platform_device.
1670 */
1671static int stmmac_dvr_probe(struct platform_device *pdev)
1672{
1673 int ret = 0;
1674 struct resource *res;
1675 unsigned int *addr = NULL;
1676 struct net_device *ndev = NULL;
1677 struct stmmac_priv *priv;
1678 struct plat_stmmacenet_data *plat_dat;
1679
1680 pr_info("STMMAC driver:\n\tplatform registration... ");
1681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1682 if (!res) {
1683 ret = -ENODEV;
1684 goto out;
1685 }
1686 pr_info("done!\n");
1687
1688 if (!request_mem_region(res->start, (res->end - res->start),
1689 pdev->name)) {
1690 pr_err("%s: ERROR: memory allocation failed"
1691 "cannot get the I/O addr 0x%x\n",
1692 __func__, (unsigned int)res->start);
1693 ret = -EBUSY;
1694 goto out;
1695 }
1696
1697 addr = ioremap(res->start, (res->end - res->start));
1698 if (!addr) {
1699 pr_err("%s: ERROR: memory mapping failed \n", __func__);
1700 ret = -ENOMEM;
1701 goto out;
1702 }
1703
1704 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1705 if (!ndev) {
1706 pr_err("%s: ERROR: allocating the device\n", __func__);
1707 ret = -ENOMEM;
1708 goto out;
1709 }
1710
1711 SET_NETDEV_DEV(ndev, &pdev->dev);
1712
1713 /* Get the MAC information */
1714 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1715 if (ndev->irq == -ENXIO) {
1716 pr_err("%s: ERROR: MAC IRQ configuration "
1717 "information not found\n", __func__);
1718 ret = -ENODEV;
1719 goto out;
1720 }
1721
1722 priv = netdev_priv(ndev);
1723 priv->device = &(pdev->dev);
1724 priv->dev = ndev;
ee7946a7 1725 plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1726 priv->bus_id = plat_dat->bus_id;
1727 priv->pbl = plat_dat->pbl; /* TLI */
1728 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
1729
1730 platform_set_drvdata(pdev, ndev);
1731
1732 /* Set the I/O base addr */
1733 ndev->base_addr = (unsigned long)addr;
1734
ee7946a7
GC		 1735 /* Verify embedded resource for the platform */
1736 ret = stmmac_claim_resource(pdev);
1737 if (ret < 0)
1738 goto out;
1739
47dd7a54
GC		 1740 /* MAC HW revice detection */
1741 ret = stmmac_mac_device_setup(ndev);
1742 if (ret < 0)
1743 goto out;
1744
1745 /* Network Device Registration */
1746 ret = stmmac_probe(ndev);
1747 if (ret < 0)
1748 goto out;
1749
1750 /* associate a PHY - it is provided by another platform bus */
1751 if (!driver_for_each_device
1752 (&(stmmacphy_driver.driver), NULL, (void *)priv,
1753 stmmac_associate_phy)) {
1754 pr_err("No PHY device is associated with this MAC!\n");
1755 ret = -ENODEV;
1756 goto out;
1757 }
1758
1759 priv->fix_mac_speed = plat_dat->fix_mac_speed;
ee7946a7 1760 priv->bus_setup = plat_dat->bus_setup;
47dd7a54
GC		 1761 priv->bsp_priv = plat_dat->bsp_priv;
1762
1763 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1764 "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1765 pdev->id, ndev->irq, (unsigned int)addr);
1766
1767 /* MDIO bus Registration */
1768 pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1769 ret = stmmac_mdio_register(ndev);
1770 if (ret < 0)
1771 goto out;
1772 pr_debug("registered!\n");
1773
1774out:
1775 if (ret < 0) {
1776 platform_set_drvdata(pdev, NULL);
1777 release_mem_region(res->start, (res->end - res->start));
1778 if (addr != NULL)
1779 iounmap(addr);
1780 }
1781
1782 return ret;
1783}
1784
1785/**
1786 * stmmac_dvr_remove
1787 * @pdev: platform device pointer
1788 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1789 * changes the link status, releases the DMA descriptor rings,
1790 * unregisters the MDIO bus and unmaps the allocated memory.
1791 */
1792static int stmmac_dvr_remove(struct platform_device *pdev)
1793{
1794 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1795 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1796 struct resource *res;
1797
1798 pr_info("%s:\n\tremoving driver", __func__);
1799
aec7ff27
GC		 1800 priv->hw->dma->stop_rx(ndev->base_addr);
1801 priv->hw->dma->stop_tx(ndev->base_addr);
47dd7a54
GC		 1802
1803 stmmac_mac_disable_rx(ndev->base_addr);
1804 stmmac_mac_disable_tx(ndev->base_addr);
1805
1806 netif_carrier_off(ndev);
1807
1808 stmmac_mdio_unregister(ndev);
1809
1810 platform_set_drvdata(pdev, NULL);
1811 unregister_netdev(ndev);
1812
1813 iounmap((void *)ndev->base_addr);
1814 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1815 release_mem_region(res->start, (res->end - res->start));
1816
1817 free_netdev(ndev);
1818
1819 return 0;
1820}
1821
1822#ifdef CONFIG_PM
1823static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
1824{
1825 struct net_device *dev = platform_get_drvdata(pdev);
1826 struct stmmac_priv *priv = netdev_priv(dev);
1827 int dis_ic = 0;
1828
1829 if (!dev || !netif_running(dev))
1830 return 0;
1831
1832 spin_lock(&priv->lock);
1833
1834 if (state.event == PM_EVENT_SUSPEND) {
1835 netif_device_detach(dev);
1836 netif_stop_queue(dev);
1837 if (priv->phydev)
1838 phy_stop(priv->phydev);
1839
1840#ifdef CONFIG_STMMAC_TIMER
1841 priv->tm->timer_stop();
73cfe264
GC		 1842 if (likely(priv->tm->enable))
1843 dis_ic = 1;
47dd7a54
GC		 1844#endif
1845 napi_disable(&priv->napi);
1846
1847 /* Stop TX/RX DMA */
aec7ff27
GC		 1848 priv->hw->dma->stop_tx(dev->base_addr);
1849 priv->hw->dma->stop_rx(dev->base_addr);
47dd7a54 1850 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 1851 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1852 dis_ic);
1853 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 1854
1855 stmmac_mac_disable_tx(dev->base_addr);
1856
1857 if (device_may_wakeup(&(pdev->dev))) {
1858 /* Enable Power down mode by programming the PMT regs */
1859 if (priv->wolenabled == PMT_SUPPORTED)
db98a0b0
GC		 1860 priv->hw->mac->pmt(dev->base_addr,
1861 priv->wolopts);
47dd7a54
GC		 1862 } else {
1863 stmmac_mac_disable_rx(dev->base_addr);
1864 }
1865 } else {
1866 priv->shutdown = 1;
1867 /* Although this can appear slightly redundant it actually
1868 * makes fast the standby operation and guarantees the driver
1869 * working if hibernation is on media. */
1870 stmmac_release(dev);
1871 }
1872
1873 spin_unlock(&priv->lock);
1874 return 0;
1875}
1876
1877static int stmmac_resume(struct platform_device *pdev)
1878{
1879 struct net_device *dev = platform_get_drvdata(pdev);
1880 struct stmmac_priv *priv = netdev_priv(dev);
1881 unsigned long ioaddr = dev->base_addr;
1882
1883 if (!netif_running(dev))
1884 return 0;
1885
1886 spin_lock(&priv->lock);
1887
1888 if (priv->shutdown) {
1889 /* Re-open the interface and re-init the MAC/DMA
1890 and the rings. */
1891 stmmac_open(dev);
1892 goto out_resume;
1893 }
1894
1895 /* Power Down bit, into the PM register, is cleared
1896 * automatically as soon as a magic packet or a Wake-up frame
1897 * is received. Anyway, it's better to manually clear
1898 * this bit because it can generate problems while resuming
1899 * from another devices (e.g. serial console). */
1900 if (device_may_wakeup(&(pdev->dev)))
1901 if (priv->wolenabled == PMT_SUPPORTED)
db98a0b0 1902 priv->hw->mac->pmt(dev->base_addr, 0);
47dd7a54
GC		 1903
1904 netif_device_attach(dev);
1905
1906 /* Enable the MAC and DMA */
1907 stmmac_mac_enable_rx(ioaddr);
1908 stmmac_mac_enable_tx(ioaddr);
aec7ff27
GC		 1909 priv->hw->dma->start_tx(ioaddr);
1910 priv->hw->dma->start_rx(ioaddr);
47dd7a54
GC		 1911
1912#ifdef CONFIG_STMMAC_TIMER
1913 priv->tm->timer_start(tmrate);
1914#endif
1915 napi_enable(&priv->napi);
1916
1917 if (priv->phydev)
1918 phy_start(priv->phydev);
1919
1920 netif_start_queue(dev);
1921
1922out_resume:
1923 spin_unlock(&priv->lock);
1924 return 0;
1925}
1926#endif
1927
1928static struct platform_driver stmmac_driver = {
1929 .driver = {
1930 .name = STMMAC_RESOURCE_NAME,
1931 },
1932 .probe = stmmac_dvr_probe,
1933 .remove = stmmac_dvr_remove,
1934#ifdef CONFIG_PM
1935 .suspend = stmmac_suspend,
1936 .resume = stmmac_resume,
1937#endif
1938
1939};
1940
1941/**
1942 * stmmac_init_module - Entry point for the driver
1943 * Description: This function is the entry point for the driver.
1944 */
1945static int __init stmmac_init_module(void)
1946{
1947 int ret;
1948
1949 if (platform_driver_register(&stmmacphy_driver)) {
1950 pr_err("No PHY devices registered!\n");
1951 return -ENODEV;
1952 }
1953
1954 ret = platform_driver_register(&stmmac_driver);
1955 return ret;
1956}
1957
1958/**
1959 * stmmac_cleanup_module - Cleanup routine for the driver
1960 * Description: This function is the cleanup routine for the driver.
1961 */
1962static void __exit stmmac_cleanup_module(void)
1963{
1964 platform_driver_unregister(&stmmacphy_driver);
1965 platform_driver_unregister(&stmmac_driver);
1966}
1967
1968#ifndef MODULE
1969static int __init stmmac_cmdline_opt(char *str)
1970{
1971 char *opt;
1972
1973 if (!str || !*str)
1974 return -EINVAL;
1975 while ((opt = strsep(&str, ",")) != NULL) {
1976 if (!strncmp(opt, "debug:", 6))
1977 strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
1978 else if (!strncmp(opt, "phyaddr:", 8))
1979 strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
1980 else if (!strncmp(opt, "dma_txsize:", 11))
1981 strict_strtoul(opt + 11, 0,
1982 (unsigned long *)&dma_txsize);
1983 else if (!strncmp(opt, "dma_rxsize:", 11))
1984 strict_strtoul(opt + 11, 0,
1985 (unsigned long *)&dma_rxsize);
1986 else if (!strncmp(opt, "buf_sz:", 7))
1987 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
1988 else if (!strncmp(opt, "tc:", 3))
1989 strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
1990 else if (!strncmp(opt, "tx_coe:", 7))
1991 strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
1992 else if (!strncmp(opt, "watchdog:", 9))
1993 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
1994 else if (!strncmp(opt, "flow_ctrl:", 10))
1995 strict_strtoul(opt + 10, 0,
1996 (unsigned long *)&flow_ctrl);
1997 else if (!strncmp(opt, "pause:", 6))
1998 strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
1999#ifdef CONFIG_STMMAC_TIMER
2000 else if (!strncmp(opt, "tmrate:", 7))
2001 strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
2002#endif
2003 }
2004 return 0;
2005}
2006
2007__setup("stmmaceth=", stmmac_cmdline_opt);
2008#endif
2009
2010module_init(stmmac_init_module);
2011module_exit(stmmac_cleanup_module);
2012
2013MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2014MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2015MODULE_LICENSE("GPL");
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