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[net-next-2.6.git] / drivers / net / stmmac / stmmac_main.c
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47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
5a0e3ad6 47#include <linux/slab.h>
47dd7a54
GC		 48#include "stmmac.h"
49
50#define STMMAC_RESOURCE_NAME "stmmaceth"
51#define PHY_RESOURCE_NAME "stmmacphy"
52
53#undef STMMAC_DEBUG
54/*#define STMMAC_DEBUG*/
55#ifdef STMMAC_DEBUG
56#define DBG(nlevel, klevel, fmt, args...) \
57 ((void)(netif_msg_##nlevel(priv) && \
58 printk(KERN_##klevel fmt, ## args)))
59#else
60#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61#endif
62
63#undef STMMAC_RX_DEBUG
64/*#define STMMAC_RX_DEBUG*/
65#ifdef STMMAC_RX_DEBUG
66#define RX_DBG(fmt, args...) printk(fmt, ## args)
67#else
68#define RX_DBG(fmt, args...) do { } while (0)
69#endif
70
71#undef STMMAC_XMIT_DEBUG
72/*#define STMMAC_XMIT_DEBUG*/
73#ifdef STMMAC_TX_DEBUG
74#define TX_DBG(fmt, args...) printk(fmt, ## args)
75#else
76#define TX_DBG(fmt, args...) do { } while (0)
77#endif
78
79#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
80#define JUMBO_LEN 9000
81
82/* Module parameters */
83#define TX_TIMEO 5000 /* default 5 seconds */
84static int watchdog = TX_TIMEO;
85module_param(watchdog, int, S_IRUGO | S_IWUSR);
86MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
87
88static int debug = -1; /* -1: default, 0: no output, 16: all */
89module_param(debug, int, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
91
92static int phyaddr = -1;
93module_param(phyaddr, int, S_IRUGO);
94MODULE_PARM_DESC(phyaddr, "Physical device address");
95
96#define DMA_TX_SIZE 256
97static int dma_txsize = DMA_TX_SIZE;
98module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
99MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
100
101#define DMA_RX_SIZE 256
102static int dma_rxsize = DMA_RX_SIZE;
103module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
104MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
105
106static int flow_ctrl = FLOW_OFF;
107module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
108MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
109
110static int pause = PAUSE_TIME;
111module_param(pause, int, S_IRUGO | S_IWUSR);
112MODULE_PARM_DESC(pause, "Flow Control Pause Time");
113
114#define TC_DEFAULT 64
115static int tc = TC_DEFAULT;
116module_param(tc, int, S_IRUGO | S_IWUSR);
117MODULE_PARM_DESC(tc, "DMA threshold control value");
118
119#define RX_NO_COALESCE 1 /* Always interrupt on completion */
120#define TX_NO_COALESCE -1 /* No moderation by default */
121
122/* Pay attention to tune this parameter; take care of both
123 * hardware capability and network stabitily/performance impact.
124 * Many tests showed that ~4ms latency seems to be good enough. */
125#ifdef CONFIG_STMMAC_TIMER
126#define DEFAULT_PERIODIC_RATE 256
127static int tmrate = DEFAULT_PERIODIC_RATE;
128module_param(tmrate, int, S_IRUGO | S_IWUSR);
129MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
130#endif
131
132#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
133static int buf_sz = DMA_BUFFER_SIZE;
134module_param(buf_sz, int, S_IRUGO | S_IWUSR);
135MODULE_PARM_DESC(buf_sz, "DMA buffer size");
136
137/* In case of Giga ETH, we can enable/disable the COE for the
138 * transmit HW checksum computation.
139 * Note that, if tx csum is off in HW, SG will be still supported. */
140static int tx_coe = HW_CSUM;
141module_param(tx_coe, int, S_IRUGO | S_IWUSR);
142MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
143
144static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
145 NETIF_MSG_LINK | NETIF_MSG_IFUP |
146 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
147
148static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
149static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
150
151/**
152 * stmmac_verify_args - verify the driver parameters.
153 * Description: it verifies if some wrong parameter is passed to the driver.
154 * Note that wrong parameters are replaced with the default values.
155 */
156static void stmmac_verify_args(void)
157{
158 if (unlikely(watchdog < 0))
159 watchdog = TX_TIMEO;
160 if (unlikely(dma_rxsize < 0))
161 dma_rxsize = DMA_RX_SIZE;
162 if (unlikely(dma_txsize < 0))
163 dma_txsize = DMA_TX_SIZE;
164 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
165 buf_sz = DMA_BUFFER_SIZE;
166 if (unlikely(flow_ctrl > 1))
167 flow_ctrl = FLOW_AUTO;
168 else if (likely(flow_ctrl < 0))
169 flow_ctrl = FLOW_OFF;
170 if (unlikely((pause < 0) || (pause > 0xffff)))
171 pause = PAUSE_TIME;
47dd7a54
GC		 172}
173
174#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
175static void print_pkt(unsigned char *buf, int len)
176{
177 int j;
178 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
179 for (j = 0; j < len; j++) {
180 if ((j % 16) == 0)
181 pr_info("\n %03x:", j);
182 pr_info(" %02x", buf[j]);
183 }
184 pr_info("\n");
47dd7a54
GC		 185}
186#endif
187
188/* minimum number of free TX descriptors required to wake up TX process */
189#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
190
191static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
192{
193 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
194}
195
196/**
197 * stmmac_adjust_link
198 * @dev: net device structure
199 * Description: it adjusts the link parameters.
200 */
201static void stmmac_adjust_link(struct net_device *dev)
202{
203 struct stmmac_priv *priv = netdev_priv(dev);
204 struct phy_device *phydev = priv->phydev;
205 unsigned long ioaddr = dev->base_addr;
206 unsigned long flags;
207 int new_state = 0;
208 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
209
210 if (phydev == NULL)
211 return;
212
213 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
214 phydev->addr, phydev->link);
215
216 spin_lock_irqsave(&priv->lock, flags);
217 if (phydev->link) {
218 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
219
220 /* Now we make sure that we can be in full duplex mode.
221 * If not, we operate in half-duplex mode. */
222 if (phydev->duplex != priv->oldduplex) {
223 new_state = 1;
224 if (!(phydev->duplex))
db98a0b0 225 ctrl &= ~priv->hw->link.duplex;
47dd7a54 226 else
db98a0b0 227 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 228 priv->oldduplex = phydev->duplex;
229 }
230 /* Flow Control operation */
231 if (phydev->pause)
db98a0b0
GC		 232 priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex,
233 fc, pause_time);
47dd7a54
GC		 234
235 if (phydev->speed != priv->speed) {
236 new_state = 1;
237 switch (phydev->speed) {
238 case 1000:
239 if (likely(priv->is_gmac))
db98a0b0 240 ctrl &= ~priv->hw->link.port;
47dd7a54
GC		 241 break;
242 case 100:
243 case 10:
244 if (priv->is_gmac) {
db98a0b0 245 ctrl |= priv->hw->link.port;
47dd7a54 246 if (phydev->speed == SPEED_100) {
db98a0b0 247 ctrl |= priv->hw->link.speed;
47dd7a54 248 } else {
db98a0b0 249 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 250 }
251 } else {
db98a0b0 252 ctrl &= ~priv->hw->link.port;
47dd7a54 253 }
65818fa7
GC		 254 if (likely(priv->fix_mac_speed))
255 priv->fix_mac_speed(priv->bsp_priv,
256 phydev->speed);
47dd7a54
GC		 257 break;
258 default:
259 if (netif_msg_link(priv))
260 pr_warning("%s: Speed (%d) is not 10"
261 " or 100!\n", dev->name, phydev->speed);
262 break;
263 }
264
265 priv->speed = phydev->speed;
266 }
267
268 writel(ctrl, ioaddr + MAC_CTRL_REG);
269
270 if (!priv->oldlink) {
271 new_state = 1;
272 priv->oldlink = 1;
273 }
274 } else if (priv->oldlink) {
275 new_state = 1;
276 priv->oldlink = 0;
277 priv->speed = 0;
278 priv->oldduplex = -1;
279 }
280
281 if (new_state && netif_msg_link(priv))
282 phy_print_status(phydev);
283
284 spin_unlock_irqrestore(&priv->lock, flags);
285
286 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
287}
288
289/**
290 * stmmac_init_phy - PHY initialization
291 * @dev: net device structure
292 * Description: it initializes the driver's PHY state, and attaches the PHY
293 * to the mac driver.
294 * Return value:
295 * 0 on success
296 */
297static int stmmac_init_phy(struct net_device *dev)
298{
299 struct stmmac_priv *priv = netdev_priv(dev);
300 struct phy_device *phydev;
109cdd66
GC		 301 char phy_id[MII_BUS_ID_SIZE + 3];
302 char bus_id[MII_BUS_ID_SIZE];
47dd7a54
GC		 303
304 priv->oldlink = 0;
305 priv->speed = 0;
306 priv->oldduplex = -1;
307
308 if (priv->phy_addr == -1) {
309 /* We don't have a PHY, so do nothing */
310 return 0;
311 }
312
313 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
109cdd66
GC		 314 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
315 priv->phy_addr);
47dd7a54
GC		 316 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
317
318 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
319 priv->phy_interface);
320
321 if (IS_ERR(phydev)) {
322 pr_err("%s: Could not attach to PHY\n", dev->name);
323 return PTR_ERR(phydev);
324 }
325
326 /*
327 * Broken HW is sometimes missing the pull-up resistor on the
328 * MDIO line, which results in reads to non-existent devices returning
329 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
330 * device as well.
331 * Note: phydev->phy_id is the result of reading the UID PHY registers.
332 */
333 if (phydev->phy_id == 0) {
334 phy_disconnect(phydev);
335 return -ENODEV;
336 }
337 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
338 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
339
340 priv->phydev = phydev;
341
342 return 0;
343}
344
345static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
346{
347 u32 value = readl(ioaddr + MAC_CTRL_REG);
348 value |= MAC_RNABLE_RX;
349 /* Set the RE (receive enable bit into the MAC CTRL register). */
350 writel(value, ioaddr + MAC_CTRL_REG);
351}
352
353static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
354{
355 u32 value = readl(ioaddr + MAC_CTRL_REG);
356 value |= MAC_ENABLE_TX;
357 /* Set the TE (transmit enable bit into the MAC CTRL register). */
358 writel(value, ioaddr + MAC_CTRL_REG);
359}
360
361static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
362{
363 u32 value = readl(ioaddr + MAC_CTRL_REG);
364 value &= ~MAC_RNABLE_RX;
365 writel(value, ioaddr + MAC_CTRL_REG);
366}
367
368static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
369{
370 u32 value = readl(ioaddr + MAC_CTRL_REG);
371 value &= ~MAC_ENABLE_TX;
372 writel(value, ioaddr + MAC_CTRL_REG);
373}
374
375/**
376 * display_ring
377 * @p: pointer to the ring.
378 * @size: size of the ring.
379 * Description: display all the descriptors within the ring.
380 */
381static void display_ring(struct dma_desc *p, int size)
382{
383 struct tmp_s {
384 u64 a;
385 unsigned int b;
386 unsigned int c;
387 };
388 int i;
389 for (i = 0; i < size; i++) {
390 struct tmp_s *x = (struct tmp_s *)(p + i);
391 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
392 i, (unsigned int)virt_to_phys(&p[i]),
393 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
394 x->b, x->c);
395 pr_info("\n");
396 }
397}
398
399/**
400 * init_dma_desc_rings - init the RX/TX descriptor rings
401 * @dev: net device structure
402 * Description: this function initializes the DMA RX/TX descriptors
403 * and allocates the socket buffers.
404 */
405static void init_dma_desc_rings(struct net_device *dev)
406{
407 int i;
408 struct stmmac_priv *priv = netdev_priv(dev);
409 struct sk_buff *skb;
410 unsigned int txsize = priv->dma_tx_size;
411 unsigned int rxsize = priv->dma_rx_size;
412 unsigned int bfsize = priv->dma_buf_sz;
73cfe264 413 int buff2_needed = 0, dis_ic = 0;
47dd7a54 414
47dd7a54
GC		 415 /* Set the Buffer size according to the MTU;
416 * indeed, in case of jumbo we need to bump-up the buffer sizes.
417 */
418 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
419 bfsize = BUF_SIZE_16KiB;
420 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
421 bfsize = BUF_SIZE_8KiB;
422 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
423 bfsize = BUF_SIZE_4KiB;
424 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
425 bfsize = BUF_SIZE_2KiB;
426 else
427 bfsize = DMA_BUFFER_SIZE;
428
73cfe264
GC		 429#ifdef CONFIG_STMMAC_TIMER
430 /* Disable interrupts on completion for the reception if timer is on */
431 if (likely(priv->tm->enable))
432 dis_ic = 1;
433#endif
47dd7a54
GC		 434 /* If the MTU exceeds 8k so use the second buffer in the chain */
435 if (bfsize >= BUF_SIZE_8KiB)
436 buff2_needed = 1;
437
438 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
439 txsize, rxsize, bfsize);
440
441 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
442 priv->rx_skbuff =
443 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
444 priv->dma_rx =
445 (struct dma_desc *)dma_alloc_coherent(priv->device,
446 rxsize *
447 sizeof(struct dma_desc),
448 &priv->dma_rx_phy,
449 GFP_KERNEL);
450 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
451 GFP_KERNEL);
452 priv->dma_tx =
453 (struct dma_desc *)dma_alloc_coherent(priv->device,
454 txsize *
455 sizeof(struct dma_desc),
456 &priv->dma_tx_phy,
457 GFP_KERNEL);
458
459 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
460 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
461 return;
462 }
463
464 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
465 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
466 dev->name, priv->dma_rx, priv->dma_tx,
467 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
468
469 /* RX INITIALIZATION */
470 DBG(probe, INFO, "stmmac: SKB addresses:\n"
471 "skb\t\tskb data\tdma data\n");
472
473 for (i = 0; i < rxsize; i++) {
474 struct dma_desc *p = priv->dma_rx + i;
475
476 skb = netdev_alloc_skb_ip_align(dev, bfsize);
477 if (unlikely(skb == NULL)) {
478 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
479 break;
480 }
481 priv->rx_skbuff[i] = skb;
482 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
483 bfsize, DMA_FROM_DEVICE);
484
485 p->des2 = priv->rx_skbuff_dma[i];
486 if (unlikely(buff2_needed))
487 p->des3 = p->des2 + BUF_SIZE_8KiB;
488 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
489 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
490 }
491 priv->cur_rx = 0;
492 priv->dirty_rx = (unsigned int)(i - rxsize);
493 priv->dma_buf_sz = bfsize;
494 buf_sz = bfsize;
495
496 /* TX INITIALIZATION */
497 for (i = 0; i < txsize; i++) {
498 priv->tx_skbuff[i] = NULL;
499 priv->dma_tx[i].des2 = 0;
500 }
501 priv->dirty_tx = 0;
502 priv->cur_tx = 0;
503
504 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 505 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
506 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 507
508 if (netif_msg_hw(priv)) {
509 pr_info("RX descriptor ring:\n");
510 display_ring(priv->dma_rx, rxsize);
511 pr_info("TX descriptor ring:\n");
512 display_ring(priv->dma_tx, txsize);
513 }
47dd7a54
GC		 514}
515
516static void dma_free_rx_skbufs(struct stmmac_priv *priv)
517{
518 int i;
519
520 for (i = 0; i < priv->dma_rx_size; i++) {
521 if (priv->rx_skbuff[i]) {
522 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
523 priv->dma_buf_sz, DMA_FROM_DEVICE);
524 dev_kfree_skb_any(priv->rx_skbuff[i]);
525 }
526 priv->rx_skbuff[i] = NULL;
527 }
47dd7a54
GC		 528}
529
530static void dma_free_tx_skbufs(struct stmmac_priv *priv)
531{
532 int i;
533
534 for (i = 0; i < priv->dma_tx_size; i++) {
535 if (priv->tx_skbuff[i] != NULL) {
536 struct dma_desc *p = priv->dma_tx + i;
537 if (p->des2)
538 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 539 priv->hw->desc->get_tx_len(p),
540 DMA_TO_DEVICE);
47dd7a54
GC		 541 dev_kfree_skb_any(priv->tx_skbuff[i]);
542 priv->tx_skbuff[i] = NULL;
543 }
544 }
47dd7a54
GC		 545}
546
547static void free_dma_desc_resources(struct stmmac_priv *priv)
548{
549 /* Release the DMA TX/RX socket buffers */
550 dma_free_rx_skbufs(priv);
551 dma_free_tx_skbufs(priv);
552
553 /* Free the region of consistent memory previously allocated for
554 * the DMA */
555 dma_free_coherent(priv->device,
556 priv->dma_tx_size * sizeof(struct dma_desc),
557 priv->dma_tx, priv->dma_tx_phy);
558 dma_free_coherent(priv->device,
559 priv->dma_rx_size * sizeof(struct dma_desc),
560 priv->dma_rx, priv->dma_rx_phy);
561 kfree(priv->rx_skbuff_dma);
562 kfree(priv->rx_skbuff);
563 kfree(priv->tx_skbuff);
47dd7a54
GC		 564}
565
47dd7a54
GC		 566/**
567 * stmmac_dma_operation_mode - HW DMA operation mode
568 * @priv : pointer to the private device structure.
569 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
570 * or Store-And-Forward capability. It also verifies the COE for the
571 * transmission in case of Giga ETH.
572 */
573static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
574{
575 if (!priv->is_gmac) {
576 /* MAC 10/100 */
db98a0b0 577 priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0);
47dd7a54
GC		 578 priv->tx_coe = NO_HW_CSUM;
579 } else {
580 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
db98a0b0
GC		 581 priv->hw->dma->dma_mode(priv->dev->base_addr,
582 SF_DMA_MODE, SF_DMA_MODE);
47dd7a54
GC		 583 tc = SF_DMA_MODE;
584 priv->tx_coe = HW_CSUM;
585 } else {
586 /* Checksum computation is performed in software. */
db98a0b0
GC		 587 priv->hw->dma->dma_mode(priv->dev->base_addr, tc,
588 SF_DMA_MODE);
47dd7a54
GC		 589 priv->tx_coe = NO_HW_CSUM;
590 }
591 }
592 tx_coe = priv->tx_coe;
47dd7a54
GC		 593}
594
47dd7a54
GC		 595/**
596 * stmmac_tx:
597 * @priv: private driver structure
598 * Description: it reclaims resources after transmission completes.
599 */
600static void stmmac_tx(struct stmmac_priv *priv)
601{
602 unsigned int txsize = priv->dma_tx_size;
603 unsigned long ioaddr = priv->dev->base_addr;
604
605 while (priv->dirty_tx != priv->cur_tx) {
606 int last;
607 unsigned int entry = priv->dirty_tx % txsize;
608 struct sk_buff *skb = priv->tx_skbuff[entry];
609 struct dma_desc *p = priv->dma_tx + entry;
610
611 /* Check if the descriptor is owned by the DMA. */
db98a0b0 612 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 613 break;
614
615 /* Verify tx error by looking at the last segment */
db98a0b0 616 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 617 if (likely(last)) {
618 int tx_error =
db98a0b0
GC		 619 priv->hw->desc->tx_status(&priv->dev->stats,
620 &priv->xstats, p,
621 ioaddr);
47dd7a54
GC		 622 if (likely(tx_error == 0)) {
623 priv->dev->stats.tx_packets++;
624 priv->xstats.tx_pkt_n++;
625 } else
626 priv->dev->stats.tx_errors++;
627 }
628 TX_DBG("%s: curr %d, dirty %d\n", __func__,
629 priv->cur_tx, priv->dirty_tx);
630
631 if (likely(p->des2))
632 dma_unmap_single(priv->device, p->des2,
db98a0b0 633 priv->hw->desc->get_tx_len(p),
47dd7a54
GC		 634 DMA_TO_DEVICE);
635 if (unlikely(p->des3))
636 p->des3 = 0;
637
638 if (likely(skb != NULL)) {
639 /*
640 * If there's room in the queue (limit it to size)
641 * we add this skb back into the pool,
642 * if it's the right size.
643 */
644 if ((skb_queue_len(&priv->rx_recycle) <
645 priv->dma_rx_size) &&
646 skb_recycle_check(skb, priv->dma_buf_sz))
647 __skb_queue_head(&priv->rx_recycle, skb);
648 else
649 dev_kfree_skb(skb);
650
651 priv->tx_skbuff[entry] = NULL;
652 }
653
db98a0b0 654 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 655
656 entry = (++priv->dirty_tx) % txsize;
657 }
658 if (unlikely(netif_queue_stopped(priv->dev) &&
659 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
660 netif_tx_lock(priv->dev);
661 if (netif_queue_stopped(priv->dev) &&
662 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
663 TX_DBG("%s: restart transmit\n", __func__);
664 netif_wake_queue(priv->dev);
665 }
666 netif_tx_unlock(priv->dev);
667 }
47dd7a54
GC		 668}
669
670static inline void stmmac_enable_irq(struct stmmac_priv *priv)
671{
73cfe264
GC		 672#ifdef CONFIG_STMMAC_TIMER
673 if (likely(priv->tm->enable))
674 priv->tm->timer_start(tmrate);
675 else
47dd7a54 676#endif
aec7ff27 677 priv->hw->dma->enable_dma_irq(priv->dev->base_addr);
47dd7a54
GC		 678}
679
680static inline void stmmac_disable_irq(struct stmmac_priv *priv)
681{
73cfe264
GC		 682#ifdef CONFIG_STMMAC_TIMER
683 if (likely(priv->tm->enable))
684 priv->tm->timer_stop();
685 else
47dd7a54 686#endif
aec7ff27 687 priv->hw->dma->disable_dma_irq(priv->dev->base_addr);
47dd7a54
GC		 688}
689
690static int stmmac_has_work(struct stmmac_priv *priv)
691{
692 unsigned int has_work = 0;
693 int rxret, tx_work = 0;
694
db98a0b0 695 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 696 (priv->cur_rx % priv->dma_rx_size));
697
698 if (priv->dirty_tx != priv->cur_tx)
699 tx_work = 1;
700
701 if (likely(!rxret || tx_work))
702 has_work = 1;
703
704 return has_work;
705}
706
707static inline void _stmmac_schedule(struct stmmac_priv *priv)
708{
709 if (likely(stmmac_has_work(priv))) {
710 stmmac_disable_irq(priv);
711 napi_schedule(&priv->napi);
712 }
713}
714
715#ifdef CONFIG_STMMAC_TIMER
716void stmmac_schedule(struct net_device *dev)
717{
718 struct stmmac_priv *priv = netdev_priv(dev);
719
720 priv->xstats.sched_timer_n++;
721
722 _stmmac_schedule(priv);
47dd7a54
GC		 723}
724
725static void stmmac_no_timer_started(unsigned int x)
726{;
727};
728
729static void stmmac_no_timer_stopped(void)
730{;
731};
732#endif
733
734/**
735 * stmmac_tx_err:
736 * @priv: pointer to the private device structure
737 * Description: it cleans the descriptors and restarts the transmission
738 * in case of errors.
739 */
740static void stmmac_tx_err(struct stmmac_priv *priv)
741{
742 netif_stop_queue(priv->dev);
743
aec7ff27 744 priv->hw->dma->stop_tx(priv->dev->base_addr);
47dd7a54 745 dma_free_tx_skbufs(priv);
db98a0b0 746 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 747 priv->dirty_tx = 0;
748 priv->cur_tx = 0;
aec7ff27 749 priv->hw->dma->start_tx(priv->dev->base_addr);
47dd7a54
GC		 750
751 priv->dev->stats.tx_errors++;
752 netif_wake_queue(priv->dev);
47dd7a54
GC		 753}
754
47dd7a54 755
aec7ff27
GC		 756static void stmmac_dma_interrupt(struct stmmac_priv *priv)
757{
758 unsigned long ioaddr = priv->dev->base_addr;
759 int status;
760
761 status = priv->hw->dma->dma_interrupt(priv->dev->base_addr,
762 &priv->xstats);
763 if (likely(status == handle_tx_rx))
764 _stmmac_schedule(priv);
765
766 else if (unlikely(status == tx_hard_error_bump_tc)) {
767 /* Try to bump up the dma threshold on this failure */
768 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
769 tc += 64;
770 priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE);
771 priv->xstats.threshold = tc;
47dd7a54 772 }
aec7ff27
GC		 773 stmmac_tx_err(priv);
774 } else if (unlikely(status == tx_hard_error))
775 stmmac_tx_err(priv);
47dd7a54
GC		 776}
777
778/**
779 * stmmac_open - open entry point of the driver
780 * @dev : pointer to the device structure.
781 * Description:
782 * This function is the open entry point of the driver.
783 * Return value:
784 * 0 on success and an appropriate (-)ve integer as defined in errno.h
785 * file on failure.
786 */
787static int stmmac_open(struct net_device *dev)
788{
789 struct stmmac_priv *priv = netdev_priv(dev);
790 unsigned long ioaddr = dev->base_addr;
791 int ret;
792
793 /* Check that the MAC address is valid. If its not, refuse
794 * to bring the device up. The user must specify an
795 * address using the following linux command:
796 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
797 if (!is_valid_ether_addr(dev->dev_addr)) {
798 random_ether_addr(dev->dev_addr);
799 pr_warning("%s: generated random MAC address %pM\n", dev->name,
800 dev->dev_addr);
801 }
802
803 stmmac_verify_args();
804
805 ret = stmmac_init_phy(dev);
806 if (unlikely(ret)) {
807 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
808 return ret;
809 }
810
811 /* Request the IRQ lines */
a0607fd3 812 ret = request_irq(dev->irq, stmmac_interrupt,
47dd7a54
GC		 813 IRQF_SHARED, dev->name, dev);
814 if (unlikely(ret < 0)) {
815 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
816 __func__, dev->irq, ret);
817 return ret;
818 }
819
820#ifdef CONFIG_STMMAC_TIMER
73cfe264 821 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 822 if (unlikely(priv->tm == NULL)) {
2381a55c 823 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 824 return -ENOMEM;
825 }
826 priv->tm->freq = tmrate;
827
73cfe264
GC		 828 /* Test if the external timer can be actually used.
829 * In case of failure continue without timer. */
47dd7a54 830 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 831 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 832 tmrate = 0;
833 priv->tm->freq = 0;
834 priv->tm->timer_start = stmmac_no_timer_started;
835 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 836 } else
837 priv->tm->enable = 1;
47dd7a54
GC		 838#endif
839
840 /* Create and initialize the TX/RX descriptors chains. */
841 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
842 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
843 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
844 init_dma_desc_rings(dev);
845
846 /* DMA initialization and SW reset */
db98a0b0
GC		 847 if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy,
848 priv->dma_rx_phy) < 0)) {
47dd7a54
GC		 849
850 pr_err("%s: DMA initialization failed\n", __func__);
851 return -1;
852 }
853
854 /* Copy the MAC addr into the HW */
db98a0b0 855 priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0);
ca5f12c1
GC		 856 /* If required, perform hw setup of the bus. */
857 if (priv->bus_setup)
858 priv->bus_setup(ioaddr);
47dd7a54 859 /* Initialize the MAC Core */
db98a0b0 860 priv->hw->mac->core_init(ioaddr);
47dd7a54
GC		 861
862 priv->shutdown = 0;
863
864 /* Initialise the MMC (if present) to disable all interrupts. */
865 writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
866 writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
867
868 /* Enable the MAC Rx/Tx */
869 stmmac_mac_enable_rx(ioaddr);
870 stmmac_mac_enable_tx(ioaddr);
871
872 /* Set the HW DMA mode and the COE */
873 stmmac_dma_operation_mode(priv);
874
875 /* Extra statistics */
876 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
877 priv->xstats.threshold = tc;
878
879 /* Start the ball rolling... */
880 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
aec7ff27
GC		 881 priv->hw->dma->start_tx(ioaddr);
882 priv->hw->dma->start_rx(ioaddr);
47dd7a54
GC		 883
884#ifdef CONFIG_STMMAC_TIMER
885 priv->tm->timer_start(tmrate);
886#endif
887 /* Dump DMA/MAC registers */
888 if (netif_msg_hw(priv)) {
db98a0b0
GC		 889 priv->hw->mac->dump_regs(ioaddr);
890 priv->hw->dma->dump_regs(ioaddr);
47dd7a54
GC		 891 }
892
893 if (priv->phydev)
894 phy_start(priv->phydev);
895
896 napi_enable(&priv->napi);
897 skb_queue_head_init(&priv->rx_recycle);
898 netif_start_queue(dev);
899 return 0;
900}
901
902/**
903 * stmmac_release - close entry point of the driver
904 * @dev : device pointer.
905 * Description:
906 * This is the stop entry point of the driver.
907 */
908static int stmmac_release(struct net_device *dev)
909{
910 struct stmmac_priv *priv = netdev_priv(dev);
911
912 /* Stop and disconnect the PHY */
913 if (priv->phydev) {
914 phy_stop(priv->phydev);
915 phy_disconnect(priv->phydev);
916 priv->phydev = NULL;
917 }
918
919 netif_stop_queue(dev);
920
921#ifdef CONFIG_STMMAC_TIMER
922 /* Stop and release the timer */
923 stmmac_close_ext_timer();
924 if (priv->tm != NULL)
925 kfree(priv->tm);
926#endif
927 napi_disable(&priv->napi);
928 skb_queue_purge(&priv->rx_recycle);
929
930 /* Free the IRQ lines */
931 free_irq(dev->irq, dev);
932
933 /* Stop TX/RX DMA and clear the descriptors */
aec7ff27
GC		 934 priv->hw->dma->stop_tx(dev->base_addr);
935 priv->hw->dma->stop_rx(dev->base_addr);
47dd7a54
GC		 936
937 /* Release and free the Rx/Tx resources */
938 free_dma_desc_resources(priv);
939
940 /* Disable the MAC core */
941 stmmac_mac_disable_tx(dev->base_addr);
942 stmmac_mac_disable_rx(dev->base_addr);
943
944 netif_carrier_off(dev);
945
946 return 0;
947}
948
949/*
950 * To perform emulated hardware segmentation on skb.
951 */
952static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
953{
954 struct sk_buff *segs, *curr_skb;
955 int gso_segs = skb_shinfo(skb)->gso_segs;
956
957 /* Estimate the number of fragments in the worst case */
958 if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
959 netif_stop_queue(priv->dev);
960 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
961 __func__);
962 if (stmmac_tx_avail(priv) < gso_segs)
963 return NETDEV_TX_BUSY;
964
965 netif_wake_queue(priv->dev);
966 }
967 TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
968 skb, skb->len);
969
970 segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
971 if (unlikely(IS_ERR(segs)))
972 goto sw_tso_end;
973
974 do {
975 curr_skb = segs;
976 segs = segs->next;
977 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
978 "*next %p\n", curr_skb->len, curr_skb, segs);
979 curr_skb->next = NULL;
980 stmmac_xmit(curr_skb, priv->dev);
981 } while (segs);
982
983sw_tso_end:
984 dev_kfree_skb(skb);
985
986 return NETDEV_TX_OK;
987}
988
989static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
990 struct net_device *dev,
991 int csum_insertion)
992{
993 struct stmmac_priv *priv = netdev_priv(dev);
994 unsigned int nopaged_len = skb_headlen(skb);
995 unsigned int txsize = priv->dma_tx_size;
996 unsigned int entry = priv->cur_tx % txsize;
997 struct dma_desc *desc = priv->dma_tx + entry;
998
999 if (nopaged_len > BUF_SIZE_8KiB) {
1000
1001 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1002
1003 desc->des2 = dma_map_single(priv->device, skb->data,
1004 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1005 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1006 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1007 csum_insertion);
47dd7a54
GC		 1008
1009 entry = (++priv->cur_tx) % txsize;
1010 desc = priv->dma_tx + entry;
1011
1012 desc->des2 = dma_map_single(priv->device,
1013 skb->data + BUF_SIZE_8KiB,
1014 buf2_size, DMA_TO_DEVICE);
1015 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1016 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1017 csum_insertion);
1018 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1019 priv->tx_skbuff[entry] = NULL;
1020 } else {
1021 desc->des2 = dma_map_single(priv->device, skb->data,
1022 nopaged_len, DMA_TO_DEVICE);
1023 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
db98a0b0
GC		 1024 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1025 csum_insertion);
47dd7a54
GC		 1026 }
1027 return entry;
1028}
1029
1030/**
1031 * stmmac_xmit:
1032 * @skb : the socket buffer
1033 * @dev : device pointer
1034 * Description : Tx entry point of the driver.
1035 */
1036static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1037{
1038 struct stmmac_priv *priv = netdev_priv(dev);
1039 unsigned int txsize = priv->dma_tx_size;
1040 unsigned int entry;
1041 int i, csum_insertion = 0;
1042 int nfrags = skb_shinfo(skb)->nr_frags;
1043 struct dma_desc *desc, *first;
1044
1045 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1046 if (!netif_queue_stopped(dev)) {
1047 netif_stop_queue(dev);
1048 /* This is a hard error, log it. */
1049 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1050 __func__);
1051 }
1052 return NETDEV_TX_BUSY;
1053 }
1054
1055 entry = priv->cur_tx % txsize;
1056
1057#ifdef STMMAC_XMIT_DEBUG
1058 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1059 pr_info("stmmac xmit:\n"
1060 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1061 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1062 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1063 !skb_is_gso(skb) ? "isn't" : "is");
1064#endif
1065
1066 if (unlikely(skb_is_gso(skb)))
1067 return stmmac_sw_tso(priv, skb);
1068
1069 if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1070 if (likely(priv->tx_coe == NO_HW_CSUM))
1071 skb_checksum_help(skb);
1072 else
1073 csum_insertion = 1;
1074 }
1075
1076 desc = priv->dma_tx + entry;
1077 first = desc;
1078
1079#ifdef STMMAC_XMIT_DEBUG
1080 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1081 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1082 "\t\tn_frags: %d, ip_summed: %d\n",
1083 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1084#endif
1085 priv->tx_skbuff[entry] = skb;
1086 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1087 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1088 desc = priv->dma_tx + entry;
1089 } else {
1090 unsigned int nopaged_len = skb_headlen(skb);
1091 desc->des2 = dma_map_single(priv->device, skb->data,
1092 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1093 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1094 csum_insertion);
47dd7a54
GC		 1095 }
1096
1097 for (i = 0; i < nfrags; i++) {
1098 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1099 int len = frag->size;
1100
1101 entry = (++priv->cur_tx) % txsize;
1102 desc = priv->dma_tx + entry;
1103
1104 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1105 desc->des2 = dma_map_page(priv->device, frag->page,
1106 frag->page_offset,
1107 len, DMA_TO_DEVICE);
1108 priv->tx_skbuff[entry] = NULL;
db98a0b0
GC		 1109 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1110 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1111 }
1112
1113 /* Interrupt on completition only for the latest segment */
db98a0b0 1114 priv->hw->desc->close_tx_desc(desc);
73cfe264 1115
47dd7a54 1116#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1117 /* Clean IC while using timer */
1118 if (likely(priv->tm->enable))
db98a0b0 1119 priv->hw->desc->clear_tx_ic(desc);
47dd7a54
GC		 1120#endif
1121 /* To avoid raise condition */
db98a0b0 1122 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1123
1124 priv->cur_tx++;
1125
1126#ifdef STMMAC_XMIT_DEBUG
1127 if (netif_msg_pktdata(priv)) {
1128 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1129 "first=%p, nfrags=%d\n",
1130 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1131 entry, first, nfrags);
1132 display_ring(priv->dma_tx, txsize);
1133 pr_info(">>> frame to be transmitted: ");
1134 print_pkt(skb->data, skb->len);
1135 }
1136#endif
1137 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1138 TX_DBG("%s: stop transmitted packets\n", __func__);
1139 netif_stop_queue(dev);
1140 }
1141
1142 dev->stats.tx_bytes += skb->len;
1143
aec7ff27 1144 priv->hw->dma->enable_dma_transmission(dev->base_addr);
47dd7a54
GC		 1145
1146 return NETDEV_TX_OK;
1147}
1148
1149static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1150{
1151 unsigned int rxsize = priv->dma_rx_size;
1152 int bfsize = priv->dma_buf_sz;
1153 struct dma_desc *p = priv->dma_rx;
1154
1155 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1156 unsigned int entry = priv->dirty_rx % rxsize;
1157 if (likely(priv->rx_skbuff[entry] == NULL)) {
1158 struct sk_buff *skb;
1159
1160 skb = __skb_dequeue(&priv->rx_recycle);
1161 if (skb == NULL)
1162 skb = netdev_alloc_skb_ip_align(priv->dev,
1163 bfsize);
1164
1165 if (unlikely(skb == NULL))
1166 break;
1167
1168 priv->rx_skbuff[entry] = skb;
1169 priv->rx_skbuff_dma[entry] =
1170 dma_map_single(priv->device, skb->data, bfsize,
1171 DMA_FROM_DEVICE);
1172
1173 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1174 if (unlikely(priv->is_gmac)) {
1175 if (bfsize >= BUF_SIZE_8KiB)
1176 (p + entry)->des3 =
1177 (p + entry)->des2 + BUF_SIZE_8KiB;
1178 }
1179 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1180 }
db98a0b0 1181 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1182 }
47dd7a54
GC		 1183}
1184
1185static int stmmac_rx(struct stmmac_priv *priv, int limit)
1186{
1187 unsigned int rxsize = priv->dma_rx_size;
1188 unsigned int entry = priv->cur_rx % rxsize;
1189 unsigned int next_entry;
1190 unsigned int count = 0;
1191 struct dma_desc *p = priv->dma_rx + entry;
1192 struct dma_desc *p_next;
1193
1194#ifdef STMMAC_RX_DEBUG
1195 if (netif_msg_hw(priv)) {
1196 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1197 display_ring(priv->dma_rx, rxsize);
1198 }
1199#endif
1200 count = 0;
db98a0b0 1201 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1202 int status;
1203
1204 if (count >= limit)
1205 break;
1206
1207 count++;
1208
1209 next_entry = (++priv->cur_rx) % rxsize;
1210 p_next = priv->dma_rx + next_entry;
1211 prefetch(p_next);
1212
1213 /* read the status of the incoming frame */
db98a0b0
GC		 1214 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1215 &priv->xstats, p));
47dd7a54
GC		 1216 if (unlikely(status == discard_frame))
1217 priv->dev->stats.rx_errors++;
1218 else {
1219 struct sk_buff *skb;
1220 /* Length should omit the CRC */
db98a0b0 1221 int frame_len = priv->hw->desc->get_rx_frame_len(p) - 4;
47dd7a54
GC		 1222
1223#ifdef STMMAC_RX_DEBUG
1224 if (frame_len > ETH_FRAME_LEN)
1225 pr_debug("\tRX frame size %d, COE status: %d\n",
1226 frame_len, status);
1227
1228 if (netif_msg_hw(priv))
1229 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1230 p, entry, p->des2);
1231#endif
1232 skb = priv->rx_skbuff[entry];
1233 if (unlikely(!skb)) {
1234 pr_err("%s: Inconsistent Rx descriptor chain\n",
1235 priv->dev->name);
1236 priv->dev->stats.rx_dropped++;
1237 break;
1238 }
1239 prefetch(skb->data - NET_IP_ALIGN);
1240 priv->rx_skbuff[entry] = NULL;
1241
1242 skb_put(skb, frame_len);
1243 dma_unmap_single(priv->device,
1244 priv->rx_skbuff_dma[entry],
1245 priv->dma_buf_sz, DMA_FROM_DEVICE);
1246#ifdef STMMAC_RX_DEBUG
1247 if (netif_msg_pktdata(priv)) {
1248 pr_info(" frame received (%dbytes)", frame_len);
1249 print_pkt(skb->data, frame_len);
1250 }
1251#endif
1252 skb->protocol = eth_type_trans(skb, priv->dev);
1253
1254 if (unlikely(status == csum_none)) {
1255 /* always for the old mac 10/100 */
1256 skb->ip_summed = CHECKSUM_NONE;
1257 netif_receive_skb(skb);
1258 } else {
1259 skb->ip_summed = CHECKSUM_UNNECESSARY;
1260 napi_gro_receive(&priv->napi, skb);
1261 }
1262
1263 priv->dev->stats.rx_packets++;
1264 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1265 }
1266 entry = next_entry;
1267 p = p_next; /* use prefetched values */
1268 }
1269
1270 stmmac_rx_refill(priv);
1271
1272 priv->xstats.rx_pkt_n += count;
1273
1274 return count;
1275}
1276
1277/**
1278 * stmmac_poll - stmmac poll method (NAPI)
1279 * @napi : pointer to the napi structure.
1280 * @budget : maximum number of packets that the current CPU can receive from
1281 * all interfaces.
1282 * Description :
1283 * This function implements the the reception process.
1284 * Also it runs the TX completion thread
1285 */
1286static int stmmac_poll(struct napi_struct *napi, int budget)
1287{
1288 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1289 int work_done = 0;
1290
1291 priv->xstats.poll_n++;
1292 stmmac_tx(priv);
1293 work_done = stmmac_rx(priv, budget);
1294
1295 if (work_done < budget) {
1296 napi_complete(napi);
1297 stmmac_enable_irq(priv);
1298 }
1299 return work_done;
1300}
1301
1302/**
1303 * stmmac_tx_timeout
1304 * @dev : Pointer to net device structure
1305 * Description: this function is called when a packet transmission fails to
1306 * complete within a reasonable tmrate. The driver will mark the error in the
1307 * netdev structure and arrange for the device to be reset to a sane state
1308 * in order to transmit a new packet.
1309 */
1310static void stmmac_tx_timeout(struct net_device *dev)
1311{
1312 struct stmmac_priv *priv = netdev_priv(dev);
1313
1314 /* Clear Tx resources and restart transmitting again */
1315 stmmac_tx_err(priv);
47dd7a54
GC		 1316}
1317
1318/* Configuration changes (passed on by ifconfig) */
1319static int stmmac_config(struct net_device *dev, struct ifmap *map)
1320{
1321 if (dev->flags & IFF_UP) /* can't act on a running interface */
1322 return -EBUSY;
1323
1324 /* Don't allow changing the I/O address */
1325 if (map->base_addr != dev->base_addr) {
1326 pr_warning("%s: can't change I/O address\n", dev->name);
1327 return -EOPNOTSUPP;
1328 }
1329
1330 /* Don't allow changing the IRQ */
1331 if (map->irq != dev->irq) {
1332 pr_warning("%s: can't change IRQ number %d\n",
1333 dev->name, dev->irq);
1334 return -EOPNOTSUPP;
1335 }
1336
1337 /* ignore other fields */
1338 return 0;
1339}
1340
1341/**
1342 * stmmac_multicast_list - entry point for multicast addressing
1343 * @dev : pointer to the device structure
1344 * Description:
1345 * This function is a driver entry point which gets called by the kernel
1346 * whenever multicast addresses must be enabled/disabled.
1347 * Return value:
1348 * void.
1349 */
1350static void stmmac_multicast_list(struct net_device *dev)
1351{
1352 struct stmmac_priv *priv = netdev_priv(dev);
1353
1354 spin_lock(&priv->lock);
db98a0b0 1355 priv->hw->mac->set_filter(dev);
47dd7a54 1356 spin_unlock(&priv->lock);
47dd7a54
GC		 1357}
1358
1359/**
1360 * stmmac_change_mtu - entry point to change MTU size for the device.
1361 * @dev : device pointer.
1362 * @new_mtu : the new MTU size for the device.
1363 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1364 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1365 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1366 * Return value:
1367 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1368 * file on failure.
1369 */
1370static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1371{
1372 struct stmmac_priv *priv = netdev_priv(dev);
1373 int max_mtu;
1374
1375 if (netif_running(dev)) {
1376 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1377 return -EBUSY;
1378 }
1379
1380 if (priv->is_gmac)
1381 max_mtu = JUMBO_LEN;
1382 else
1383 max_mtu = ETH_DATA_LEN;
1384
1385 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1386 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1387 return -EINVAL;
1388 }
1389
1390 dev->mtu = new_mtu;
1391
1392 return 0;
1393}
1394
1395static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1396{
1397 struct net_device *dev = (struct net_device *)dev_id;
1398 struct stmmac_priv *priv = netdev_priv(dev);
1399
1400 if (unlikely(!dev)) {
1401 pr_err("%s: invalid dev pointer\n", __func__);
1402 return IRQ_NONE;
1403 }
1404
1405 if (priv->is_gmac) {
1406 unsigned long ioaddr = dev->base_addr;
1407 /* To handle GMAC own interrupts */
db98a0b0 1408 priv->hw->mac->host_irq_status(ioaddr);
47dd7a54 1409 }
aec7ff27
GC		 1410
1411 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1412
1413 return IRQ_HANDLED;
1414}
1415
1416#ifdef CONFIG_NET_POLL_CONTROLLER
1417/* Polling receive - used by NETCONSOLE and other diagnostic tools
1418 * to allow network I/O with interrupts disabled. */
1419static void stmmac_poll_controller(struct net_device *dev)
1420{
1421 disable_irq(dev->irq);
1422 stmmac_interrupt(dev->irq, dev);
1423 enable_irq(dev->irq);
1424}
1425#endif
1426
1427/**
1428 * stmmac_ioctl - Entry point for the Ioctl
1429 * @dev: Device pointer.
1430 * @rq: An IOCTL specefic structure, that can contain a pointer to
1431 * a proprietary structure used to pass information to the driver.
1432 * @cmd: IOCTL command
1433 * Description:
1434 * Currently there are no special functionality supported in IOCTL, just the
1435 * phy_mii_ioctl(...) can be invoked.
1436 */
1437static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1438{
1439 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1440 int ret;
47dd7a54
GC		 1441
1442 if (!netif_running(dev))
1443 return -EINVAL;
1444
28b04113
RC		 1445 if (!priv->phydev)
1446 return -EINVAL;
1447
1448 spin_lock(&priv->lock);
1449 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1450 spin_unlock(&priv->lock);
1451
47dd7a54
GC		 1452 return ret;
1453}
1454
1455#ifdef STMMAC_VLAN_TAG_USED
1456static void stmmac_vlan_rx_register(struct net_device *dev,
1457 struct vlan_group *grp)
1458{
1459 struct stmmac_priv *priv = netdev_priv(dev);
1460
1461 DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1462
1463 spin_lock(&priv->lock);
1464 priv->vlgrp = grp;
1465 spin_unlock(&priv->lock);
47dd7a54
GC		 1466}
1467#endif
1468
1469static const struct net_device_ops stmmac_netdev_ops = {
1470 .ndo_open = stmmac_open,
1471 .ndo_start_xmit = stmmac_xmit,
1472 .ndo_stop = stmmac_release,
1473 .ndo_change_mtu = stmmac_change_mtu,
1474 .ndo_set_multicast_list = stmmac_multicast_list,
1475 .ndo_tx_timeout = stmmac_tx_timeout,
1476 .ndo_do_ioctl = stmmac_ioctl,
1477 .ndo_set_config = stmmac_config,
1478#ifdef STMMAC_VLAN_TAG_USED
1479 .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1480#endif
1481#ifdef CONFIG_NET_POLL_CONTROLLER
1482 .ndo_poll_controller = stmmac_poll_controller,
1483#endif
1484 .ndo_set_mac_address = eth_mac_addr,
1485};
1486
1487/**
1488 * stmmac_probe - Initialization of the adapter .
1489 * @dev : device pointer
1490 * Description: The function initializes the network device structure for
1491 * the STMMAC driver. It also calls the low level routines
1492 * in order to init the HW (i.e. the DMA engine)
1493 */
1494static int stmmac_probe(struct net_device *dev)
1495{
1496 int ret = 0;
1497 struct stmmac_priv *priv = netdev_priv(dev);
1498
1499 ether_setup(dev);
1500
1501 dev->netdev_ops = &stmmac_netdev_ops;
1502 stmmac_set_ethtool_ops(dev);
1503
1504 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1505 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1506#ifdef STMMAC_VLAN_TAG_USED
1507 /* Both mac100 and gmac support receive VLAN tag detection */
1508 dev->features |= NETIF_F_HW_VLAN_RX;
1509#endif
1510 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1511
1512 if (priv->is_gmac)
1513 priv->rx_csum = 1;
1514
1515 if (flow_ctrl)
1516 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1517
1518 priv->pause = pause;
1519 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1520
1521 /* Get the MAC address */
db98a0b0 1522 priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
47dd7a54
GC		 1523
1524 if (!is_valid_ether_addr(dev->dev_addr))
1525 pr_warning("\tno valid MAC address;"
1526 "please, use ifconfig or nwhwconfig!\n");
1527
1528 ret = register_netdev(dev);
1529 if (ret) {
1530 pr_err("%s: ERROR %i registering the device\n",
1531 __func__, ret);
1532 return -ENODEV;
1533 }
1534
1535 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1536 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1537 (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1538
1539 spin_lock_init(&priv->lock);
1540
1541 return ret;
1542}
1543
1544/**
1545 * stmmac_mac_device_setup
1546 * @dev : device pointer
1547 * Description: select and initialise the mac device (mac100 or Gmac).
1548 */
1549static int stmmac_mac_device_setup(struct net_device *dev)
1550{
1551 struct stmmac_priv *priv = netdev_priv(dev);
1552 unsigned long ioaddr = dev->base_addr;
1553
1554 struct mac_device_info *device;
1555
3d90c508 1556 if (priv->is_gmac)
21d437cc 1557 device = dwmac1000_setup(ioaddr);
3d90c508 1558 else
7e848ae1 1559 device = dwmac100_setup(ioaddr);
3d90c508
GC		 1560
1561 if (priv->enh_desc) {
1562 device->desc = &enh_desc_ops;
1563 pr_info("\tEnhanced descriptor structure\n");
1564 } else
56b106ae 1565 device->desc = &ndesc_ops;
47dd7a54
GC		 1566
1567 if (!device)
1568 return -ENOMEM;
1569
db98a0b0 1570 priv->hw = device;
47dd7a54 1571
db98a0b0 1572 priv->wolenabled = priv->hw->pmt; /* PMT supported */
47dd7a54
GC		 1573 if (priv->wolenabled == PMT_SUPPORTED)
1574 priv->wolopts = WAKE_MAGIC; /* Magic Frame */
1575
1576 return 0;
1577}
1578
1579static int stmmacphy_dvr_probe(struct platform_device *pdev)
1580{
ee7946a7 1581 struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1582
1583 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1584 plat_dat->bus_id);
1585
1586 return 0;
1587}
1588
1589static int stmmacphy_dvr_remove(struct platform_device *pdev)
1590{
1591 return 0;
1592}
1593
1594static struct platform_driver stmmacphy_driver = {
1595 .driver = {
1596 .name = PHY_RESOURCE_NAME,
1597 },
1598 .probe = stmmacphy_dvr_probe,
1599 .remove = stmmacphy_dvr_remove,
1600};
1601
1602/**
1603 * stmmac_associate_phy
1604 * @dev: pointer to device structure
1605 * @data: points to the private structure.
1606 * Description: Scans through all the PHYs we have registered and checks if
1607 * any are associated with our MAC. If so, then just fill in
1608 * the blanks in our local context structure
1609 */
1610static int stmmac_associate_phy(struct device *dev, void *data)
1611{
1612 struct stmmac_priv *priv = (struct stmmac_priv *)data;
ee7946a7 1613 struct plat_stmmacphy_data *plat_dat = dev->platform_data;
47dd7a54
GC		 1614
1615 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1616 plat_dat->bus_id);
1617
1618 /* Check that this phy is for the MAC being initialised */
1619 if (priv->bus_id != plat_dat->bus_id)
1620 return 0;
1621
1622 /* OK, this PHY is connected to the MAC.
1623 Go ahead and get the parameters */
1624 DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1625 priv->phy_irq =
1626 platform_get_irq_byname(to_platform_device(dev), "phyirq");
1627 DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1628 plat_dat->bus_id, priv->phy_irq);
1629
1630 /* Override with kernel parameters if supplied XXX CRS XXX
1631 * this needs to have multiple instances */
1632 if ((phyaddr >= 0) && (phyaddr <= 31))
1633 plat_dat->phy_addr = phyaddr;
1634
1635 priv->phy_addr = plat_dat->phy_addr;
1636 priv->phy_mask = plat_dat->phy_mask;
1637 priv->phy_interface = plat_dat->interface;
1638 priv->phy_reset = plat_dat->phy_reset;
1639
1640 DBG(probe, DEBUG, "%s: exiting\n", __func__);
1641 return 1; /* forces exit of driver_for_each_device() */
1642}
1643
1644/**
1645 * stmmac_dvr_probe
1646 * @pdev: platform device pointer
1647 * Description: the driver is initialized through platform_device.
1648 */
1649static int stmmac_dvr_probe(struct platform_device *pdev)
1650{
1651 int ret = 0;
1652 struct resource *res;
1653 unsigned int *addr = NULL;
1654 struct net_device *ndev = NULL;
1655 struct stmmac_priv *priv;
1656 struct plat_stmmacenet_data *plat_dat;
1657
1658 pr_info("STMMAC driver:\n\tplatform registration... ");
1659 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1660 if (!res) {
1661 ret = -ENODEV;
1662 goto out;
1663 }
1664 pr_info("done!\n");
1665
b6222682 1666 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1667 pdev->name)) {
1668 pr_err("%s: ERROR: memory allocation failed"
1669 "cannot get the I/O addr 0x%x\n",
1670 __func__, (unsigned int)res->start);
1671 ret = -EBUSY;
1672 goto out;
1673 }
1674
7c5365bc 1675 addr = ioremap(res->start, resource_size(res));
47dd7a54 1676 if (!addr) {
7c5365bc 1677 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54
GC		 1678 ret = -ENOMEM;
1679 goto out;
1680 }
1681
1682 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1683 if (!ndev) {
1684 pr_err("%s: ERROR: allocating the device\n", __func__);
1685 ret = -ENOMEM;
1686 goto out;
1687 }
1688
1689 SET_NETDEV_DEV(ndev, &pdev->dev);
1690
1691 /* Get the MAC information */
1692 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1693 if (ndev->irq == -ENXIO) {
1694 pr_err("%s: ERROR: MAC IRQ configuration "
1695 "information not found\n", __func__);
1696 ret = -ENODEV;
1697 goto out;
1698 }
1699
1700 priv = netdev_priv(ndev);
1701 priv->device = &(pdev->dev);
1702 priv->dev = ndev;
ee7946a7 1703 plat_dat = pdev->dev.platform_data;
47dd7a54
GC		 1704 priv->bus_id = plat_dat->bus_id;
1705 priv->pbl = plat_dat->pbl; /* TLI */
1706 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
3d90c508 1707 priv->enh_desc = plat_dat->enh_desc;
47dd7a54
GC		 1708
1709 platform_set_drvdata(pdev, ndev);
1710
1711 /* Set the I/O base addr */
1712 ndev->base_addr = (unsigned long)addr;
1713
ee7946a7
GC		 1714 /* Verify embedded resource for the platform */
1715 ret = stmmac_claim_resource(pdev);
1716 if (ret < 0)
1717 goto out;
1718
47dd7a54
GC		 1719 /* MAC HW revice detection */
1720 ret = stmmac_mac_device_setup(ndev);
1721 if (ret < 0)
1722 goto out;
1723
1724 /* Network Device Registration */
1725 ret = stmmac_probe(ndev);
1726 if (ret < 0)
1727 goto out;
1728
1729 /* associate a PHY - it is provided by another platform bus */
1730 if (!driver_for_each_device
1731 (&(stmmacphy_driver.driver), NULL, (void *)priv,
1732 stmmac_associate_phy)) {
1733 pr_err("No PHY device is associated with this MAC!\n");
1734 ret = -ENODEV;
1735 goto out;
1736 }
1737
1738 priv->fix_mac_speed = plat_dat->fix_mac_speed;
ee7946a7 1739 priv->bus_setup = plat_dat->bus_setup;
47dd7a54
GC		 1740 priv->bsp_priv = plat_dat->bsp_priv;
1741
1742 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1743 "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1744 pdev->id, ndev->irq, (unsigned int)addr);
1745
1746 /* MDIO bus Registration */
1747 pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1748 ret = stmmac_mdio_register(ndev);
1749 if (ret < 0)
1750 goto out;
1751 pr_debug("registered!\n");
1752
1753out:
1754 if (ret < 0) {
1755 platform_set_drvdata(pdev, NULL);
7c5365bc 1756 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1757 if (addr != NULL)
1758 iounmap(addr);
1759 }
1760
1761 return ret;
1762}
1763
1764/**
1765 * stmmac_dvr_remove
1766 * @pdev: platform device pointer
1767 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1768 * changes the link status, releases the DMA descriptor rings,
1769 * unregisters the MDIO bus and unmaps the allocated memory.
1770 */
1771static int stmmac_dvr_remove(struct platform_device *pdev)
1772{
1773 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1774 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1775 struct resource *res;
1776
1777 pr_info("%s:\n\tremoving driver", __func__);
1778
aec7ff27
GC		 1779 priv->hw->dma->stop_rx(ndev->base_addr);
1780 priv->hw->dma->stop_tx(ndev->base_addr);
47dd7a54
GC		 1781
1782 stmmac_mac_disable_rx(ndev->base_addr);
1783 stmmac_mac_disable_tx(ndev->base_addr);
1784
1785 netif_carrier_off(ndev);
1786
1787 stmmac_mdio_unregister(ndev);
1788
1789 platform_set_drvdata(pdev, NULL);
1790 unregister_netdev(ndev);
1791
1792 iounmap((void *)ndev->base_addr);
1793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1794 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1795
1796 free_netdev(ndev);
1797
1798 return 0;
1799}
1800
1801#ifdef CONFIG_PM
1802static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
1803{
1804 struct net_device *dev = platform_get_drvdata(pdev);
1805 struct stmmac_priv *priv = netdev_priv(dev);
1806 int dis_ic = 0;
1807
1808 if (!dev || !netif_running(dev))
1809 return 0;
1810
1811 spin_lock(&priv->lock);
1812
1813 if (state.event == PM_EVENT_SUSPEND) {
1814 netif_device_detach(dev);
1815 netif_stop_queue(dev);
1816 if (priv->phydev)
1817 phy_stop(priv->phydev);
1818
1819#ifdef CONFIG_STMMAC_TIMER
1820 priv->tm->timer_stop();
73cfe264
GC		 1821 if (likely(priv->tm->enable))
1822 dis_ic = 1;
47dd7a54
GC		 1823#endif
1824 napi_disable(&priv->napi);
1825
1826 /* Stop TX/RX DMA */
aec7ff27
GC		 1827 priv->hw->dma->stop_tx(dev->base_addr);
1828 priv->hw->dma->stop_rx(dev->base_addr);
47dd7a54 1829 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 1830 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1831 dis_ic);
1832 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 1833
1834 stmmac_mac_disable_tx(dev->base_addr);
1835
1836 if (device_may_wakeup(&(pdev->dev))) {
1837 /* Enable Power down mode by programming the PMT regs */
1838 if (priv->wolenabled == PMT_SUPPORTED)
db98a0b0
GC		 1839 priv->hw->mac->pmt(dev->base_addr,
1840 priv->wolopts);
47dd7a54
GC		 1841 } else {
1842 stmmac_mac_disable_rx(dev->base_addr);
1843 }
1844 } else {
1845 priv->shutdown = 1;
1846 /* Although this can appear slightly redundant it actually
1847 * makes fast the standby operation and guarantees the driver
1848 * working if hibernation is on media. */
1849 stmmac_release(dev);
1850 }
1851
1852 spin_unlock(&priv->lock);
1853 return 0;
1854}
1855
1856static int stmmac_resume(struct platform_device *pdev)
1857{
1858 struct net_device *dev = platform_get_drvdata(pdev);
1859 struct stmmac_priv *priv = netdev_priv(dev);
1860 unsigned long ioaddr = dev->base_addr;
1861
1862 if (!netif_running(dev))
1863 return 0;
1864
1865 spin_lock(&priv->lock);
1866
1867 if (priv->shutdown) {
1868 /* Re-open the interface and re-init the MAC/DMA
1869 and the rings. */
1870 stmmac_open(dev);
1871 goto out_resume;
1872 }
1873
1874 /* Power Down bit, into the PM register, is cleared
1875 * automatically as soon as a magic packet or a Wake-up frame
1876 * is received. Anyway, it's better to manually clear
1877 * this bit because it can generate problems while resuming
1878 * from another devices (e.g. serial console). */
1879 if (device_may_wakeup(&(pdev->dev)))
1880 if (priv->wolenabled == PMT_SUPPORTED)
db98a0b0 1881 priv->hw->mac->pmt(dev->base_addr, 0);
47dd7a54
GC		 1882
1883 netif_device_attach(dev);
1884
1885 /* Enable the MAC and DMA */
1886 stmmac_mac_enable_rx(ioaddr);
1887 stmmac_mac_enable_tx(ioaddr);
aec7ff27
GC		 1888 priv->hw->dma->start_tx(ioaddr);
1889 priv->hw->dma->start_rx(ioaddr);
47dd7a54
GC		 1890
1891#ifdef CONFIG_STMMAC_TIMER
1892 priv->tm->timer_start(tmrate);
1893#endif
1894 napi_enable(&priv->napi);
1895
1896 if (priv->phydev)
1897 phy_start(priv->phydev);
1898
1899 netif_start_queue(dev);
1900
1901out_resume:
1902 spin_unlock(&priv->lock);
1903 return 0;
1904}
1905#endif
1906
1907static struct platform_driver stmmac_driver = {
1908 .driver = {
1909 .name = STMMAC_RESOURCE_NAME,
1910 },
1911 .probe = stmmac_dvr_probe,
1912 .remove = stmmac_dvr_remove,
1913#ifdef CONFIG_PM
1914 .suspend = stmmac_suspend,
1915 .resume = stmmac_resume,
1916#endif
1917
1918};
1919
1920/**
1921 * stmmac_init_module - Entry point for the driver
1922 * Description: This function is the entry point for the driver.
1923 */
1924static int __init stmmac_init_module(void)
1925{
1926 int ret;
1927
1928 if (platform_driver_register(&stmmacphy_driver)) {
1929 pr_err("No PHY devices registered!\n");
1930 return -ENODEV;
1931 }
1932
1933 ret = platform_driver_register(&stmmac_driver);
1934 return ret;
1935}
1936
1937/**
1938 * stmmac_cleanup_module - Cleanup routine for the driver
1939 * Description: This function is the cleanup routine for the driver.
1940 */
1941static void __exit stmmac_cleanup_module(void)
1942{
1943 platform_driver_unregister(&stmmacphy_driver);
1944 platform_driver_unregister(&stmmac_driver);
1945}
1946
1947#ifndef MODULE
1948static int __init stmmac_cmdline_opt(char *str)
1949{
1950 char *opt;
1951
1952 if (!str || !*str)
1953 return -EINVAL;
1954 while ((opt = strsep(&str, ",")) != NULL) {
1955 if (!strncmp(opt, "debug:", 6))
1956 strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
1957 else if (!strncmp(opt, "phyaddr:", 8))
1958 strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
1959 else if (!strncmp(opt, "dma_txsize:", 11))
1960 strict_strtoul(opt + 11, 0,
1961 (unsigned long *)&dma_txsize);
1962 else if (!strncmp(opt, "dma_rxsize:", 11))
1963 strict_strtoul(opt + 11, 0,
1964 (unsigned long *)&dma_rxsize);
1965 else if (!strncmp(opt, "buf_sz:", 7))
1966 strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
1967 else if (!strncmp(opt, "tc:", 3))
1968 strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
1969 else if (!strncmp(opt, "tx_coe:", 7))
1970 strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
1971 else if (!strncmp(opt, "watchdog:", 9))
1972 strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
1973 else if (!strncmp(opt, "flow_ctrl:", 10))
1974 strict_strtoul(opt + 10, 0,
1975 (unsigned long *)&flow_ctrl);
1976 else if (!strncmp(opt, "pause:", 6))
1977 strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
1978#ifdef CONFIG_STMMAC_TIMER
1979 else if (!strncmp(opt, "tmrate:", 7))
1980 strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
1981#endif
1982 }
1983 return 0;
1984}
1985
1986__setup("stmmaceth=", stmmac_cmdline_opt);
1987#endif
1988
1989module_init(stmmac_init_module);
1990module_exit(stmmac_cleanup_module);
1991
1992MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
1993MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
1994MODULE_LICENSE("GPL");
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